[Pkg-clamav-commits] [SCM] Debian repository for ClamAV branch, debian/unstable, updated. debian/0.95+dfsg-1-6156-g094ec9b
Török Edvin
edwin at clamav.net
Sun Apr 4 01:06:33 UTC 2010
The following commit has been merged in the debian/unstable branch:
commit 6c5344d3ea01311db9314ee046144ca743b2baef
Author: Török Edvin <edwin at clamav.net>
Date: Fri Oct 2 11:09:40 2009 +0300
Merge LLVM upstream r83242.
Squashed commit of the following:
commit 6f2bf0bd6f1ff49887d30f3433d05bd906e6b3d3
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Oct 2 06:57:25 2009 +0000
getFunctionAlignment should return log2 alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83242 91177308-0d34-0410-b5e6-96231b3b80d8
commit 69e343b1b893bf2b11cc0320973d329eb9102e79
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Oct 2 06:53:57 2009 +0000
Fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83241 91177308-0d34-0410-b5e6-96231b3b80d8
commit 42b0e2ad0096357ac3f62e5e7066703bdb93ba75
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Oct 2 06:50:50 2009 +0000
Fix test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83240 91177308-0d34-0410-b5e6-96231b3b80d8
commit 62213e4da7f2ac9b615a3bd53baad974c1c36bdd
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Oct 2 06:07:47 2009 +0000
C++ member functions must be 2 byte aligned per ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83239 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4a6e6dd500a86c44803aa7b1414c8603d9e5c753
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Oct 2 05:03:07 2009 +0000
Forgot about ARM::tPUSH. It also has a new writeback operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83237 91177308-0d34-0410-b5e6-96231b3b80d8
commit a2e9ca91163c46e55d5ee9e16efb3a1ab6a01467
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Oct 2 04:57:15 2009 +0000
Move load / store multiple before post-alloc scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83236 91177308-0d34-0410-b5e6-96231b3b80d8
commit 926c44a79e4e6eb86e44028d9f313640c6238ddf
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Oct 2 04:45:37 2009 +0000
Test case for aligned attribute on function declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83234 91177308-0d34-0410-b5e6-96231b3b80d8
commit db397e1ea09a961e2b3f16d7ee85eae5f19f8771
Author: David Goodwin <david_goodwin at apple.com>
Date: Thu Oct 1 23:28:47 2009 +0000
All callee-saved registers are live-out of a return block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83223 91177308-0d34-0410-b5e6-96231b3b80d8
commit 736fed9ff71ae677a7c947ac80ebb42a527de0dc
Author: David Goodwin <david_goodwin at apple.com>
Date: Thu Oct 1 22:19:57 2009 +0000
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5d14abe36967fe67c85915dc6102a3b24fc1cd4a
Author: Mike Stump <mrs at apple.com>
Date: Thu Oct 1 22:08:58 2009 +0000
Expand api out in the usual inserter way, though, I do have a
question, can we get rid of the BasicBlock versions of all inserters
and use Head == 0 to indicate the old case when GetInsertBlock == 0?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83216 91177308-0d34-0410-b5e6-96231b3b80d8
commit 089aa85274d26ebec4989ac1ceeefba7fca5e5ea
Author: David Goodwin <david_goodwin at apple.com>
Date: Thu Oct 1 21:46:35 2009 +0000
Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
commit a9a6b6528197d68ea551f665bc6be722a0009630
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Oct 1 20:54:53 2009 +0000
ARM::tPOP and tPOP_RET each has an extra writeback operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83214 91177308-0d34-0410-b5e6-96231b3b80d8
commit 254350268fc9c24618049ec56bb13484a12bd7ea
Author: Jim Grosbach <grosbach at apple.com>
Date: Thu Oct 1 20:45:06 2009 +0000
remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83213 91177308-0d34-0410-b5e6-96231b3b80d8
commit 6a26010c218cd8979439036cc90d3bea93b3996b
Author: Devang Patel <dpatel at apple.com>
Date: Thu Oct 1 20:31:14 2009 +0000
Add support to extract lexical scope information from DebugLoc attached with an machine instruction.
This is not yet enabled.
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commit cdb56fcef112775875904583d3cc07a262a28af3
Author: David Goodwin <david_goodwin at apple.com>
Date: Thu Oct 1 19:45:32 2009 +0000
Use MachineFrameInfo.getPristineRegs() to determine which callee-saved registers are available for anti-dependency breaking. Some cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83208 91177308-0d34-0410-b5e6-96231b3b80d8
commit 90ecd198e2f605f8a613ce0861aeea7e16a56575
Author: Devang Patel <dpatel at apple.com>
Date: Thu Oct 1 18:25:23 2009 +0000
Record first and last instruction of a scope in DbgScope.
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commit 23e904656c452ab739af152a9f767a5e504be4f5
Author: Dan Gohman <gohman at apple.com>
Date: Thu Oct 1 17:39:52 2009 +0000
Don't use identifiers that start with an underscore followed
by a capital letter, which invokes undefined behavior.
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commit 0f9678ef172077982826809d5111881929175d83
Author: Douglas Gregor <doug.gregor at gmail.com>
Date: Thu Oct 1 17:25:36 2009 +0000
Teach CMake to look for bidirectional_iterator, iterator, forward_iterator, uint64_t, and u_int64_t, from Yonggang Luo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83203 91177308-0d34-0410-b5e6-96231b3b80d8
commit 04be082a4a304483410133a89dbd0f1dfe902c9a
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Oct 1 08:26:23 2009 +0000
Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not change
operands of instructions with these properties while breaking anti-dep.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83198 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7c8d5ea09fb5e7a585533f711b9540e9b3b95a5e
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Oct 1 08:22:27 2009 +0000
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
ld / st pairs, etc.
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commit f6ea3038ef1d98019eb620ad0fbb8f2ca5f49da5
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Oct 1 08:21:18 2009 +0000
Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When
set, these flags indicate the instructions source / def operands have special
register allocation requirement that are not captured in their register classes.
Post-allocation passes (e.g. post-alloc scheduler) should not change their
allocations. e.g. ARM::LDRD require the two definitions to be allocated
even / odd register pair.
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commit 8ae1c40d8152145e9810bc28383af1d3ebf5b52b
Author: Douglas Gregor <doug.gregor at gmail.com>
Date: Thu Oct 1 05:30:05 2009 +0000
Remove GVNPRE.cpp from the CMake makefile
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commit 50ee6c55ed015693e91bcebda0c100f6185a47fe
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Oct 1 02:18:36 2009 +0000
remove the GVNPRE pass. It has been subsumed by the GVN pass.
Ok'd by Owen.
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commit 713ff84d1467c64ad625681baa355b49bcc44ca3
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Oct 1 01:39:21 2009 +0000
Update ARM JIT emitter to account for ld/st multiple changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83192 91177308-0d34-0410-b5e6-96231b3b80d8
commit b43a20e3bce6b4b16151ec25ef3541494fce8425
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Oct 1 01:33:39 2009 +0000
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
commit f736728788cddfb56d44fb826cb5d91dfdbfe294
Author: Devang Patel <dpatel at apple.com>
Date: Thu Oct 1 01:15:28 2009 +0000
Add another MDNode into DebugLocTuple. This will be used to keep track of inlined functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83190 91177308-0d34-0410-b5e6-96231b3b80d8
commit 539f434334ae6cc5becba8b3099eb20ab7fe48dc
Author: Devang Patel <dpatel at apple.com>
Date: Thu Oct 1 01:03:26 2009 +0000
If location info is attached with an instruction then keep track of alloca slots used by a variable. This info will be used by AsmPrinter to emit debug info for variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83189 91177308-0d34-0410-b5e6-96231b3b80d8
commit 86049dcedaba49929bf6e4c1cd84f9d85cadb987
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 30 23:12:50 2009 +0000
Use MachineInstr as an processDebugLoc() argument.
This will allow processDebugLoc() to handle scopes for DWARF debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83183 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4d23d84af58fc21b50dce528a8a26a30a62db355
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 30 22:51:28 2009 +0000
Use MDNode * directly as an RecordSourceLine() argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83182 91177308-0d34-0410-b5e6-96231b3b80d8
commit 16030402039c222229fe0e64cbc8307964480e31
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 30 22:43:52 2009 +0000
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83181 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3733e0ac886bb85bd0735fdee4421683d9be3682
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 30 22:34:41 2009 +0000
Add isFOO() helpers. Fix getDirectory() and getFilename() for DIScope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83180 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1f9b67a27f82ba4d75625c2e260d40cb3b662393
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 30 22:25:37 2009 +0000
Use OutStreamer.SwitchSection instead of writing out textual section directives.
Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to
get access to that section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83178 91177308-0d34-0410-b5e6-96231b3b80d8
commit b5f835ee6e48aedbffb804a6bf5308465867e67b
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 30 22:06:26 2009 +0000
Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this
to emit target-specific things at the beginning of the asm output. This
fixes a problem for PPC, where the text sections are not being kept together
as expected. The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives. The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text. With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83176 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4901f432e56cb1b6823a9b3170a08ff56f1f2c37
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 30 21:44:42 2009 +0000
Fix a comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83174 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5c6b6fc5b3777a3001043ba3a5db54ac41f97a1b
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 30 21:26:51 2009 +0000
Check for null MDNode element while printing comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83172 91177308-0d34-0410-b5e6-96231b3b80d8
commit 6ed4b620633aff7001447bf3ddd86924f8fd7d10
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 30 21:26:13 2009 +0000
Fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83171 91177308-0d34-0410-b5e6-96231b3b80d8
commit cd8cb7f1e4075f66179e15deb0c0aecaf09fe4be
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 30 21:24:45 2009 +0000
The AsmPrinter base class contains a DwarfWriter member, so there's no need
for derived AsmPrinters to add another one. In some cases, fixing this
removes the need to override the doInitialization method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83170 91177308-0d34-0410-b5e6-96231b3b80d8
commit cd36d91b6775ae45eb46eb2a0f4ac47b4a8cb9d8
Author: Jeffrey Yasskin <jyasskin at google.com>
Date: Wed Sep 30 21:08:08 2009 +0000
Assert that ConstantArrays are created with correctly-typed elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83168 91177308-0d34-0410-b5e6-96231b3b80d8
commit a6c9ec0753ed03948b49ae3e0d96b87b484ee247
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 30 20:54:16 2009 +0000
Fix this code so that it doesn't try to iterate through a std::vector
while calling changeImmediateDominator, which removes elements from the
vector. This fixes PR5097.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83166 91177308-0d34-0410-b5e6-96231b3b80d8
commit 64ccb3919aa594caf4c2196eed9e72cc9797fe57
Author: Reid Kleckner <reid at kleckner.net>
Date: Wed Sep 30 20:43:07 2009 +0000
Silence comparison always false warning in -Asserts mode.
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commit af24317c91a2383560a6707d35ae41f770c05a14
Author: Jim Grosbach <grosbach at apple.com>
Date: Wed Sep 30 20:35:36 2009 +0000
Add additional assert() to verify no extraneous use of a scavenged register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83163 91177308-0d34-0410-b5e6-96231b3b80d8
commit 60a7ae26df4ce7d2dac4636e924c29eed0f97df4
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 30 20:16:54 2009 +0000
Print tag name for MDNodes that are used to encode debug info.
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commit e9b95fd1ebb1f046d17afd0123d7c3afcd4ddef0
Author: Reid Kleckner <reid at kleckner.net>
Date: Wed Sep 30 20:15:38 2009 +0000
Fix integer overflow in instruction scheduling. This can happen if we have
basic blocks that are so long that their size overflows a short.
Also assert that overflow does not happen in the future, as requested by Evan.
This fixes PR4401.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83159 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5a8c00d3394922bbc310fdd6ffb829939de37cd1
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 30 17:13:41 2009 +0000
Silence unused variable warning.
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commit 65a2b9aff1084c5c54afd4577555a5bf3b124114
Author: Jim Grosbach <grosbach at apple.com>
Date: Wed Sep 30 15:23:38 2009 +0000
Clarify comment phrasing.
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commit 140523508f5e2af96e8c01218b4c4fc1c73abcdb
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 30 08:53:01 2009 +0000
Add a option which would move ld/st multiple pass before post-alloc scheduling.
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commit caa654136388c6b3b1909149a5d9002159983ee1
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 30 08:49:50 2009 +0000
Add a target hook to add pre- post-regalloc scheduling passes.
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commit 28568c1e49f9781afd921e2fbb52b18fb2ec6321
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 30 08:41:27 2009 +0000
Forgot this test earlier.
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commit 2375debd3ff878723a90be0f69860eae30ace312
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 30 06:27:22 2009 +0000
add macruby, fix a validation problem.
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commit 133cf876fff85ed26381f2964e5c1de43764a051
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Wed Sep 30 04:50:26 2009 +0000
Fix compile error as debug interface changed.
By the way, this code is buggy. You can't keep a map<MDNode *, something>
because the MDNode may be destroyed and reused for something else.
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commit a0e180ac4672e4a304f93a2d0207428c83de155e
Author: Jim Grosbach <grosbach at apple.com>
Date: Wed Sep 30 01:47:59 2009 +0000
replace TRI->isVirtualRegister() with TargetRegisterInfo::isVirtualRegister()
per customary usage
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commit ce096d7654254793f6df9dcfea8e44345afa42bf
Author: Jim Grosbach <grosbach at apple.com>
Date: Wed Sep 30 01:43:29 2009 +0000
When checking whether we need to reserve a register for the scavenger,
the size of the saved frame pointer needs to be taken into account.
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commit c6f0c0268cdad78cdc3b8d4b4ad597d1c3ce7ba2
Author: Jim Grosbach <grosbach at apple.com>
Date: Wed Sep 30 01:35:11 2009 +0000
Add "isBarrier = 1" to return instructions.
Patch by Sylvere Teissier.
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commit 25e34f9b00ed6c3b69f77fbec6173ca9071ac793
Author: Jim Grosbach <grosbach at apple.com>
Date: Wed Sep 30 00:37:40 2009 +0000
fix compiler warning
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commit fcadb50767616efc30787f5e5bcbf67b3fc3d7f0
Author: David Goodwin <david_goodwin at apple.com>
Date: Wed Sep 30 00:23:57 2009 +0000
Remove regression that requires post-RA scheduling from a target that does not use that scheduler.
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commit 5147f1174ae1b6f8af2bc03d8f9915bda2937961
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 30 00:23:42 2009 +0000
For Darwin, emit all the text section directives together before the dwarf
section directives. This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations. Radar 7255355.
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commit 48e8d7af49d3f3e2cd279c13b8897fcade1801a5
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 30 00:14:40 2009 +0000
Simplify.
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commit cf89a609bc2c368e2c5c970131edc40c08175893
Author: David Goodwin <david_goodwin at apple.com>
Date: Wed Sep 30 00:10:16 2009 +0000
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
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commit 3abdd85bbfd3f3f16e7c4551ba86fed9c412ea82
Author: Douglas Gregor <doug.gregor at gmail.com>
Date: Wed Sep 30 00:08:25 2009 +0000
Forward-declare ValueSymbolTable so that SymbolTableListTraits.h can be parsed by itself
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83121 91177308-0d34-0410-b5e6-96231b3b80d8
commit b22cd0ff4c6c3ba4a39b8b11afb21ddf40e79f74
Author: Mike Stump <mrs at apple.com>
Date: Wed Sep 30 00:08:22 2009 +0000
Add a way for a frontend to generate more complex dwarf location
information. This allows arbitrary code involving DW_OP_plus_uconst
and DW_OP_deref. The scheme allows for easy extention to include,
any, or all of the DW_OP_ opcodes. I thought about just exposing all
of them, but, wasn't sure if people wanted the dwarf opcodes exposed
in the api. Is that a layering violation?
With this scheme, the entire existing block scheme used by llvm-gcc
can be switched over to the new scheme. I think that would be
cleaner, as then the compiler specific bits are not present in llvm
proper. Before the old code can be yanked however, similar code in
clang would have to be removed.
Next up, more testing.
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commit 278c839fdb36f39a25935fd83e12144b374d4e75
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 29 23:17:20 2009 +0000
minor cleanup and add clarifying comment
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commit 5c888f47d45c8b462e23cc270731bff109e55e0f
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 29 22:05:52 2009 +0000
Lookup handler name only when assertions are enabled.
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commit 91291d92510d559e84bb36184703684dcd330469
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 29 20:42:25 2009 +0000
Add removeMD().
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commit 3402a11ab9fadebbfd897d532e3dd3ec33bc76d5
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 29 20:30:57 2009 +0000
Only one custom meadata of each kind can be attached with an instruction.
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commit 1f2144540eebd8dfd6161f7f1e350f7f0cf8fc89
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 29 20:11:10 2009 +0000
Additional check for regno==0
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commit 789d5d396510406c9dfbf26b8b5e5ee463f0eb60
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 29 20:01:19 2009 +0000
Use assertion instead of early exit to catch malformed custom metadata store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83102 91177308-0d34-0410-b5e6-96231b3b80d8
commit 50ffdfb9df7dceaba43fd40a1053d22787257fd6
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 29 19:56:13 2009 +0000
Remove unnecessary cast.
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commit aaf012ebb492482ba3626e4129140713cd7836b7
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 29 18:40:58 2009 +0000
Remove std::string uses from DebugInfo interface.
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commit e4002bc8194a36ff425f37829d6fb04a56ef1358
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 29 18:39:56 2009 +0000
Create empty StringRef is incoming cstring is NULL.
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commit 428fa81b068032e70a4df96a9bf95aea8647bae7
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 29 18:23:15 2009 +0000
Simplify the tracking of virtual frame index registers. Ranges cannot overlap,
so a simple "current register" will suffice. Also add some additional
sanity-checking assertions to make sure things are as we expect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83081 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1261bc74142b823bf80824e5f7e20697cb136747
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 29 17:24:37 2009 +0000
Moving register scavenging to a post pass results in virtual registers in
the instruction we're scavenging for. The scavenger needs to know to avoid
them when analyzing register usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83077 91177308-0d34-0410-b5e6-96231b3b80d8
commit d87b736e032e2bb48df5de77b2632197cd89d73f
Author: David Goodwin <david_goodwin at apple.com>
Date: Tue Sep 29 17:10:26 2009 +0000
Post-RA regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83075 91177308-0d34-0410-b5e6-96231b3b80d8
commit 350c913b054b04ffd2c0041e8cf63d6031cb060b
Author: Evan Cheng <evan.cheng at apple.com>
Date: Tue Sep 29 07:07:30 2009 +0000
Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83058 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5c2dc21a880cfd629c485bf65dcc7d8380da234d
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Tue Sep 29 06:18:23 2009 +0000
Regenerate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83052 91177308-0d34-0410-b5e6-96231b3b80d8
commit d5f12fed540b9487fe8a48e7480344ab0c33676d
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Tue Sep 29 06:18:00 2009 +0000
Fix configure bug that only shows up in a clean build. Don't try to invoke gcc
until after the compiler itself has been set up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83051 91177308-0d34-0410-b5e6-96231b3b80d8
commit d2813d0d6d353fb32749e66adc03e5a388c6eee2
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Tue Sep 29 05:48:51 2009 +0000
Roll back r83048.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83050 91177308-0d34-0410-b5e6-96231b3b80d8
commit e4ba4c6918a704922ebaf2dada823423d503fe7a
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Tue Sep 29 05:41:21 2009 +0000
Regenerate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83048 91177308-0d34-0410-b5e6-96231b3b80d8
commit 6c6df93ec728e0c4109690a0712100f2381002ce
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Tue Sep 29 05:40:45 2009 +0000
On Linux, uname -m reports the kernel type. Some Linux systems are 32-bit but
with a 64-bit kernel, which confuses LLVM. Make LLVM double-check this by
checking which defines the system gcc actually sets.
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commit 17c60df1f139b966e696c18683d6fac7afb0d4ac
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 29 00:01:14 2009 +0000
Parse custom metadata attached with an instruction.
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commit 8a60e6ab5c0bdebeeb93bf7837306b526c6174cd
Author: Stuart Hastings <stuart at apple.com>
Date: Mon Sep 28 23:42:38 2009 +0000
B&I's buildit forces a PATH that omits /Developer. Temporarily add
/Developer/usr/bin to the PATH when looking for llvm-gcc.
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commit fe70981db2dc986f570f7aeefc6035477e704653
Author: Stuart Hastings <stuart at apple.com>
Date: Mon Sep 28 22:17:53 2009 +0000
For B&I-style builds, tweak build_llvm script to prefer LLVM-G++ if
available. Override by setting CC and CXX in the environment.
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commit e68f04e420b7b2422586e4927db982f30c654e2f
Author: Jim Grosbach <grosbach at apple.com>
Date: Mon Sep 28 22:08:06 2009 +0000
Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack
slot for the register scavenger when compiling Thumb1 functions.
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commit 79af72b8cc78f43bda065f66a27992f14f44839b
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 21:51:41 2009 +0000
Add C API calls for building FNeg operations. Patch by KS Sreeram!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83021 91177308-0d34-0410-b5e6-96231b3b80d8
commit 6de78e26bd0bb682ac466ae1b46a8a29c9d6ae9c
Author: Devang Patel <dpatel at apple.com>
Date: Mon Sep 28 21:41:20 2009 +0000
s/class Metadata/class MetadataContext/g
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commit b5896160216cae66e3a06cb58c3c38ba09f6969e
Author: Devang Patel <dpatel at apple.com>
Date: Mon Sep 28 21:14:55 2009 +0000
Do not use global typedef for MDKindID.
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commit cb8bbe7d7b17bf387769d86e614034a36adc159e
Author: Jeffrey Yasskin <jyasskin at google.com>
Date: Mon Sep 28 21:14:38 2009 +0000
Forgot to update the documentation in r82906. s/DEBUG_RUNTIME/DEBUG_SYMBOLS/.
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commit bb2172f0d0c6dff8c8df6099930aa8c6d97c4a46
Author: Devang Patel <dpatel at apple.com>
Date: Mon Sep 28 21:06:38 2009 +0000
Remove unnecessary include.
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commit 6218ff80a55e355aed58ecd5626a28bcba5f2309
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 21:03:02 2009 +0000
Add a testcase for r83011.
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commit 5de2a439373415252635c44a5441c699c6a9a982
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 21:01:47 2009 +0000
When extending the operands of an addrec, iterate through all
the operands, rather than trying to partition them into a start
and a step. This handles non-affine add recurrences correctly.
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commit a1b5c1ac519a42ccf25664de3acee4b97f5c87a0
Author: Devang Patel <dpatel at apple.com>
Date: Mon Sep 28 20:56:00 2009 +0000
Do not hardcode metadata names.
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commit 83cefbc8b9b22deae1a74c27b6c3576928ec5e83
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 20:48:39 2009 +0000
Add a CHECK line to check the position of the second divsd.
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commit 56a506296805c4967326a41bd5b0ae3202ace90f
Author: Evan Cheng <evan.cheng at apple.com>
Date: Mon Sep 28 20:47:15 2009 +0000
Fix Thumb2 IT block pass bug. t2MOVi32imm may not be the start of a IT block.
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commit 1b17870ccf5ae6abd45044f2788825fa0db381e5
Author: Jakob Stoklund Olesen <stoklund at 2pi.dk>
Date: Mon Sep 28 20:32:46 2009 +0000
Use KILL instead of IMPLICIT_DEF in LowerSubregs pass.
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commit 8f12c7cd04af1b2eadddf46f00bf9527fa484188
Author: Jakob Stoklund Olesen <stoklund at 2pi.dk>
Date: Mon Sep 28 20:32:26 2009 +0000
Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.
KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.
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commit 0404c87e5e2d880e347a1e97e97e775534031692
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 18:40:27 2009 +0000
Add a testcase to help test analysis preservation.
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commit 24e32c155493661e8a9a5dbda73cda80d97e5203
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 18:38:53 2009 +0000
Create a README.txt for lib/Analysis, and add an entry.
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commit d8fdfc78fa6e85af471e6be708819ba7df013613
Author: Devang Patel <dpatel at apple.com>
Date: Mon Sep 28 18:31:56 2009 +0000
Remove dead code.
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commit c7d0e9d24270f52cdc47b94ebaad316d4fcc2b44
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 16:09:41 2009 +0000
Use VerifySchedule instead of doing the work manually.
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commit 52646b13f315ad45d6999871491c804a5ba706df
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 15:40:01 2009 +0000
Fix this debug output to handle the case where the loop has been deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82994 91177308-0d34-0410-b5e6-96231b3b80d8
commit 05e9fccefe7b54166c82415d0d2ab497a22eecb4
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 15:07:18 2009 +0000
Include the name of the loop header in debug messages.
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commit 2dac97890a66877e9f433d75b0f31f07df2ef84a
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 14:38:19 2009 +0000
Remove a redundant #ifndef and add an assertion string.
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commit b65091d85c1c7a467ecf0622747900e54012b2fb
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 14:37:51 2009 +0000
Convert LoopSimplify and LoopExtractor from FunctionPass to LoopPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82990 91177308-0d34-0410-b5e6-96231b3b80d8
commit f4ecc68efa92c06e2de1937f2a6408f57318ee3f
Author: Bob Wilson <bob.wilson at apple.com>
Date: Mon Sep 28 14:30:20 2009 +0000
Pass the optimization level when constructing the ARM instruction selector.
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel. Radar 7250345.
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commit 16c012d9a28fe4db3ee081192a587ad7f30d4cc2
Author: Evan Cheng <evan.cheng at apple.com>
Date: Mon Sep 28 09:14:39 2009 +0000
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
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commit 4468959a4eab134d4ca50b755aac6452617e8857
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 28 07:32:45 2009 +0000
Don't traverse into .svn directories.
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commit fe89b6a96501aabf8edbd991e9fb81108ecde782
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Mon Sep 28 07:26:46 2009 +0000
Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument.
Disable rematting of it for now.
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commit da3ee9ce1a46cf351e614a6c17627b63cec9b2b4
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 28 06:49:44 2009 +0000
The select instruction is not neccesarily in the same block as the
phi nodes. Make sure to phi translate from the right block.
This fixes a llvm-building-llvm failure on GVN-PRE.cpp
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commit 58cb38c09d1b7e0e8c27d56ac94a524552ef436c
Author: Evan Cheng <evan.cheng at apple.com>
Date: Mon Sep 28 05:28:43 2009 +0000
Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of
physical registers. This is especially critical for the later two since they
start the live interval of a super-register. e.g.
%DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
If this instruction is eliminated, the register scavenger will not be happy as
D0 is not defined previously.
This fixes PR5055.
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commit b4cf975e89642255701b2f279b1647caf430947c
Author: Erick Tryzelaar <idadesub at users.sourceforge.net>
Date: Mon Sep 28 04:42:55 2009 +0000
Document a bug in the ocaml bindings has wrong linkage values.
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commit 61c452d71b139822208536338069d2bc7d464256
Author: Erick Tryzelaar <idadesub at users.sourceforge.net>
Date: Mon Sep 28 04:42:47 2009 +0000
Expose the rest of the attribute settings.
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commit 1dc7c1fc51b4268897da277fffbac812cce94e66
Author: Erick Tryzelaar <idadesub at users.sourceforge.net>
Date: Mon Sep 28 04:42:36 2009 +0000
Fix a bug in ocaml bindings that has incorrect linkage options.
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commit 6625665544615314e66cbf54fe4b529a6dcd9441
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Mon Sep 28 01:28:26 2009 +0000
Regenerate.
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commit d42557f9880111a13da39570d5e47e69e72648df
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Mon Sep 28 01:16:42 2009 +0000
Add a way to query the number of input files.
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commit 3c3e02c66a2ac85384c3d7a84a02a60aa71ea591
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Mon Sep 28 01:16:07 2009 +0000
Document the 'not' combinator.
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commit c93d3814ca1727b694a4ac3b88a7979f61915ff7
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Mon Sep 28 01:15:44 2009 +0000
A bit prettier formatting.
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commit e414c1e0cd9d1c1e0e650c5710c3df04bf707762
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 00:44:15 2009 +0000
Remove temporary debugging hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82953 91177308-0d34-0410-b5e6-96231b3b80d8
commit 07fbbcdcfb6812cd5986ccc0188b293a8d01e961
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 00:27:48 2009 +0000
Move the dominator verification code out of special code embedded within
the PassManager code into a regular verifyAnalysis method.
Also, reorganize loop verification. Make the LoopPass infrastructure
call verifyLoop as needed instead of having LoopInfo::verifyAnalysis
check every loop in the function after each looop pass. Add a new
command-line argument, -verify-loop-info, to enable the expensive
full checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82952 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1f7ba836613f713ff32349e1c08c152d0803100b
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 00:10:28 2009 +0000
Move this assert to check the condition as soon as it is known.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82951 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7265f0826dddbc1d46ad1df769a99fc81c4adfe3
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 28 00:07:05 2009 +0000
Extend the StartPassTimer and StopPassTimer functions so that the
code that stops the timer doesn't have to search to find the timer
object before it stops the timer. This avoids a lock acquisition
and a few other things done with the timer running.
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commit 609289558295a0f4a1f6529c14ffe96db547ec41
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Sun Sep 27 23:52:58 2009 +0000
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
This should be better than single load from constpool.
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commit ee836a04ed5b6c302790bf4db303d04e17d48dfd
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 23:52:07 2009 +0000
Fix an old copy+pasto.
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commit a86280282a7ddd9df2015d13012ad229ccfcd383
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 23:49:43 2009 +0000
Extract the code for inserting a loop into the loop queue into
a separate function.
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commit 72a3f38563c08ff695f37880ca47a0212d5eef8f
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 23:43:07 2009 +0000
When a loop is deleted, immediately release all of the active
LoopPasses for that loop. This avoids trouble with the PassManager
trying to call verifyAnalysis on them, and frees up some memory
sooner rather than later.
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commit a27e7c0803f1ec6bd2b58dce5df419100c761c52
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 23:38:27 2009 +0000
Extract the code for releasing a pass into a separate function, and
tidy it up a little.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82944 91177308-0d34-0410-b5e6-96231b3b80d8
commit eb02188cd3e0b830856c05e6136523731ffa68f2
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 27 23:27:42 2009 +0000
Remove the "metadata*" type and simplify the code it complicated. This was only
used to support GlobalVariables storing MDNodes, back when they were derived
from Constant before the introduction of NamedMDNode, but never removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82943 91177308-0d34-0410-b5e6-96231b3b80d8
commit 49545c765c8fc928bcda29e4f87533aced3c808f
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 23:17:47 2009 +0000
LBRX no longer has an explicit SrcValueSDNode operand, so the type
operand is now at index 2, rather than 3. This fixes the
"Invalid child # of SDNode!" failures on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82942 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1d1bc8e896031decb3ec0a78b58b76dc7607a840
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 21:46:50 2009 +0000
simplify some code.
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commit e8ad9aecbfae9799fb3cef18c8ecc4e9bfc8a735
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 21:42:46 2009 +0000
The bitcast case is not needed here: instcombine turns icmp(bitcast(x), null) -> icmp(x, null) already.
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commit a475d661a350f7956630f0b989c7f6aa838090c4
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 27 21:39:46 2009 +0000
New unit test for the cloning module, which so far only covers cloning of
instructions' optimization flags.
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commit 5d1f8e4df0a7deddf1b2ee380793bd32b7c815d2
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 21:36:19 2009 +0000
calls are already unmovable, malloc doesn't need a special case.
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commit 6ad04a09b7acbcc532f109c8521281124df47cf6
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 21:35:11 2009 +0000
calls to external functions are already marked overdefined, special casing
malloc isn't needed.
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commit 35b69d45dd8e3d9b38f8377ec723d37bd458b5c4
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 21:33:46 2009 +0000
calls are already handled, malloc doesn't need a special case.
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commit 7805c35a30b6b119e2c4b2bfd54aa484752eeef8
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 27 21:33:04 2009 +0000
Round out the API for the new optimization flags.
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commit 0a3e013c33b6cb73b01a63d5568373be55186e04
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 21:31:39 2009 +0000
calls are rejected above, no need to special case malloc here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82929 91177308-0d34-0410-b5e6-96231b3b80d8
commit 47fe1012616c84ce6211a298f822462db8dda2ef
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 21:29:28 2009 +0000
remove special handling of bitcast(malloc), it will be handled
when the loop inspects the bitcast operand.
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commit 4e577c0241756a4d6350c2c310c0cb96a3ecee5e
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 21:23:38 2009 +0000
unlike the malloc instruction, "malloc" calls do not claim to be readonly, just nounwind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82927 91177308-0d34-0410-b5e6-96231b3b80d8
commit eb3c9102ab9db6cfde207964f78e34ceca63c57b
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 21:16:52 2009 +0000
add a new DirectiveMap stringmap, which allows more efficient dispatching
to directive handlers and allows for easier extensibility.
I only switched a few over for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82926 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7a54febb0063e0862aee2a084a627bb029779498
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 27 20:58:01 2009 +0000
Link order: it matters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82925 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9b61abd17da1bff8720e5bfbb02c98fec3212ad2
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 20:46:36 2009 +0000
allow pushing icmps through phis with multiple uses and across critical edges.
These are important to push up to encourage jump threading. This shrinks 176.gcc a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82923 91177308-0d34-0410-b5e6-96231b3b80d8
commit ff5cd9de8438a1fbe450b5d0b31a9ae3a0a5fbc5
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 20:18:49 2009 +0000
Enhance the previous fix for PR4895 to allow more values than just
simple constants for the true/false value of the select. We now
do phi translation etc. This really fixes PR4895 :)
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commit f7843b77d709006cc6e93938f396a2aaf9dcd994
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 19:57:57 2009 +0000
implement PR4895, by making FoldOpIntoPhi handle select conditions
that are phi nodes. Also tighten up FoldOpIntoPhi to treat constantexpr
operands to phis just like other variables, avoiding moving constantexpr
computations around.
Patch by Daniel Dunbar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82913 91177308-0d34-0410-b5e6-96231b3b80d8
commit de228ff38a94da4f7b64b2eed20195730bc565b9
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 19:38:39 2009 +0000
avoid copying MCAsmInfo by value, add an (extremely low prio) fixme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82911 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4c2770bd33b6ce5587a1226d52a77a2ad5a3f345
Author: Tilmann Scheller <tilmann.scheller at googlemail.com>
Date: Sun Sep 27 17:58:47 2009 +0000
Use explicit structs instead of std::pair to map callee saved regs to spill slots.
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commit 2a918d684b96d027630a6b65cc61a7dace0d8fd1
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 17:50:44 2009 +0000
Delete a bogus comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82908 91177308-0d34-0410-b5e6-96231b3b80d8
commit bbd99f3f67dcd426cc675998c95f3a119b13b42a
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 17:48:37 2009 +0000
Remove a redundant assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82907 91177308-0d34-0410-b5e6-96231b3b80d8
commit ed62bf33bce67ff2da6a8181428f48b2e4db03aa
Author: Jeffrey Yasskin <jyasskin at google.com>
Date: Sun Sep 27 17:47:29 2009 +0000
Enable -g with DEBUG_SYMBOLS and --enable-debug-symbols instead of
DEBUG_RUNTIME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82906 91177308-0d34-0410-b5e6-96231b3b80d8
commit d9bf0112734209c3d98a574bdb672f2928d6ee08
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 17:46:40 2009 +0000
Fix SCEVExpander's canonical addrec expansion code to work on loops that
aren't in canonical loop-simplify form, since it doesn't itself depend
on LoopSimplify. This means handling loops without preheaders and loops
with multiple backedges.
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commit 6ba2142e9397002278f4275ffbae6caa28342607
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 17:39:12 2009 +0000
Add dominates and releaseMemory member functions to PostDominatorTree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82904 91177308-0d34-0410-b5e6-96231b3b80d8
commit 791c8251355c2f25f39685a7deab22560793c6fa
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 16:10:30 2009 +0000
Grab an LLVM Context from an instruction that exists rather than one
that is deleted in some situations. This fixes a use-after-free.
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commit fecf86a40e1d27384518d37c51470352b7c5bd91
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 15:41:19 2009 +0000
Clarify a comment.
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commit 7936cb8d152d2881952b0013355cbda15e57b99a
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 15:37:03 2009 +0000
Tell ScalarEvolution to forget everything it knows about a loop before
rotating the loop, since loop rotation is a very significant change.
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commit 397d89ff4449862390e51f261b77f7570a95b563
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 15:32:21 2009 +0000
Micro-optimize DerivedType::dropAllTypeUses.
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commit 12319f23b7e7eae3c45b6a56afede0d6d88c4d6b
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 15:30:00 2009 +0000
Instead of testing whether an instruction dominates the loop preheader,
test whether it properly dominates the loop header. This is equivalent
when the loop has a preheader, and has the advantage of working when
the loop doesn't have a preheader. Since IVUsers doesn't Require
LoopSimplify, the loop isn't guaranteed to have a preheader.
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commit 322a984dddfb491b560d582f03b6fc7f1122bdad
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 15:26:03 2009 +0000
Add a properlyDominates member function to ScalarEvolution.
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commit b69db8035d9b7354a43b912ee10dc9e29006f3be
Author: Dan Gohman <gohman at apple.com>
Date: Sun Sep 27 15:21:52 2009 +0000
Remove a redundant #include.
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commit 127f2c5637e7bcfda31bdb7a313726eeedb8a3ea
Author: Edwin Török <edwintorok at gmail.com>
Date: Sun Sep 27 11:08:03 2009 +0000
Avoid using mutex locks if not in multithreaded mode by using a SmartScopedMutex
in RegisterStatistic.
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commit 340684f156c06a256649f09657a198653fbe8881
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sun Sep 27 09:46:04 2009 +0000
Enable pre-regalloc load / store multiple pass for Thumb2.
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commit b9cb1867e50c19f73e6325a34880f259263e843e
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 08:01:44 2009 +0000
rename REG -> REGISTER to make it explicit in the doc. <tt>ify some stuff.
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commit 8599166fed9834e8ba77289f61214bfd9a050b20
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 27 07:56:52 2009 +0000
implement and document support for filecheck variables. This
allows matching and remembering a string and then matching and
verifying that the string occurs later in the file.
Change X86/xor.ll to use this in some cases where the test was
checking for an arbitrary register allocation decision.
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commit 3b3b54d35e1e9f0089c7efdca231a04c77e7d061
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 27 07:55:32 2009 +0000
Remove dead code from this function and optimize. Update its corresponding
LangRef entry too.
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commit c94270c382320cb3fe9c4dc7bf31d56c94e9643d
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 27 07:38:41 2009 +0000
Instruction::clone does not need to take an LLVMContext&. Remove that and
update all the callers.
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commit ebb9633af0245a3eaf03d2a9f4ceb6375cc8769e
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 27 06:25:05 2009 +0000
Filecheckify this one test.
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commit b7b9a48e7b9695ec1dd8d39297658aa020ff77ca
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 27 04:57:35 2009 +0000
Leave a pointer to the documentation so that people don't end up change one but
not the other in the future.
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commit 985d6d15ded32550f7c29aa7f61efd3621562558
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 27 04:56:27 2009 +0000
Correct the version numbers to match those actually tested for by
autoconf/AutoRegen.sh.
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commit 244cf489295b4fed69591a3c4f6404875d0d38ca
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 27 00:45:11 2009 +0000
Move the integer type out of 'derived' and into 'primitive'. This permits us
to explain that derived types are all composed of other types, which primitive
types aren't. Without moving integer out of derived, this wouldn't be true.
Perform a few trivial cleanups; 'i1' went from a link to #t_primitive to
#t_integer (a holdover from when it was a bool type I suppose).
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commit aa2637b6ad3234e068167af31981d688f54191b0
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 26 21:27:04 2009 +0000
remove support for "NoSub" from regex. It seems like a minor optimization
and makes the API more annoying. Add a Regex::getNumMatches() method.
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commit e29707fa8162a0dd61380c9ca6e92a47dcb87170
Author: Edwin Török <edwintorok at gmail.com>
Date: Sat Sep 26 20:18:58 2009 +0000
Speed up clang-only link, by really linking only clang, and not the unittests
too.
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commit 7714ad64800f0e4c645ed922455ce09a71686538
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sat Sep 26 18:51:37 2009 +0000
Remove this test.
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commit c156b7b4c9323f464900e6316b97661143631a6a
Author: Dan Gohman <gohman at apple.com>
Date: Sat Sep 26 18:10:13 2009 +0000
Fix SimplifyLibCalls to transfer attributes from callees rather than
calls, since direct calls don't always reflect the attributes of their
callees.
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commit 5a1645e66706ac33ae463ef43e6328eb5b4ec309
Author: Dan Gohman <gohman at apple.com>
Date: Sat Sep 26 16:11:57 2009 +0000
Fix a case where ScalarEvolution was expanding pointer arithmetic
to inttoptr/ptrtoint unnecessarily.
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commit 1261dde02801ca06f9e8001747eab7fd244fa3f4
Author: Duncan Sands <baldrick at free.fr>
Date: Sat Sep 26 15:35:35 2009 +0000
For the NSWSub support in the builder to actually be useable,
there need to be corresponding changes to the constant folders,
done in this patch.
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commit 2221f5657297e8c645617e7304d360aceda1b409
Author: Dan Gohman <gohman at apple.com>
Date: Sat Sep 26 15:24:17 2009 +0000
Convert comparisons like (x == infinity) to (x >= infinity) on targets
where FCMP_OEQ is not legal and FCMP_OGE is, such as x86.
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commit b2b6ab5a11661fd22b5020a1175ca3715b02a509
Author: Duncan Sands <baldrick at free.fr>
Date: Sat Sep 26 15:21:48 2009 +0000
Add methods for creating NSW subtraction, as already exists
for addition.
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commit 01d166b12f2eed6b31154b48f3f94c45e0b0977f
Author: Dan Gohman <gohman at apple.com>
Date: Sat Sep 26 15:09:53 2009 +0000
Add a comment describing natural loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82859 91177308-0d34-0410-b5e6-96231b3b80d8
commit a7468751ace00baa201c34277c85ae20a896dd90
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 26 05:29:36 2009 +0000
"Update" tests for -disable-if-conversion removal. I think branch.ll should just
be removed, but I XFAIL'd it for now.
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commit 0e367e3f0866e9f690b307b4feefaec8d4a3bdfb
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sat Sep 26 02:49:49 2009 +0000
Really remove this option.
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commit c2bb61fd9699873daeba366e97019d660c4006ca
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sat Sep 26 02:45:45 2009 +0000
Remove a couple of unused command line options.
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commit 7f4c4564fc1f3955b136a050941b236467fca747
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sat Sep 26 02:43:36 2009 +0000
Add comment.
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commit 4c1d7673235202816e1027e08eb16cf6123fe1a4
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sat Sep 26 02:41:17 2009 +0000
Convert test to filecheck.
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commit 7da0592edfecaac630500ce491f7e339d416be60
Author: Dan Gohman <gohman at apple.com>
Date: Sat Sep 26 02:34:00 2009 +0000
Don't hoist or sink instructions with physreg uses if the physreg is
allocatable. Even if it doesn't appear to have any defs, it may latter
on after register allocation.
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commit 40dcae418d4fb290bedfd5a22eb9a63c40c1dc84
Author: Dan Gohman <gohman at apple.com>
Date: Sat Sep 26 01:11:57 2009 +0000
I put the wrong rdar number in this test.
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commit 13b1ad6276483958045c11cb589586e0fb0959ed
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 23:58:45 2009 +0000
Unbreak MachineLICM for instructions that reference RIP on x86-64 too.
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commit 6408b97d7cfea3250c4ada4d8ad08188d68cb9c0
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 23:40:21 2009 +0000
Rename ConstantFP's getInf to getInfinity.
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commit 232e4448242ec67d6a7b48906002ab7c3f7af96c
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 23:33:20 2009 +0000
Move MachineMemOperand::getAlignment out of line, to avoid needing
MathExtras.h in MachineMemOperand.h.
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commit 75b79e54a4fd0ea94c2bc91ab7ac3c6248d1af5c
Author: Daniel Dunbar <daniel at zuster.org>
Date: Fri Sep 25 23:26:56 2009 +0000
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82821 91177308-0d34-0410-b5e6-96231b3b80d8
commit b99d6f9e77125bd9ebf9ebe6df0050b974b8aa5e
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 23:10:17 2009 +0000
Transform pow(x, 0.5) to (x == -inf ? inf : fabs(sqrt(x))), which is
typically faster then doing a general pow.
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commit 43dcfc7462c5602f9f840c6905f905b63a1d8937
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 23:00:48 2009 +0000
Add a ConstantFP::getInf utility function for creating infinity ConstantFPs.
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commit 5dedd5c716f4c2741afd8ac264d5e4e09adbcf1b
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 22:53:29 2009 +0000
Fix MachineSink to be able to sink instructions that use physical registers
which have no defs anywhere in the function. In particular, this fixes sinking
of instructions that reference RIP on x86-64, which is currently being modeled
as a register.
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commit e222c72bba42281674d39d3d33dd75fb8f926ce5
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Fri Sep 25 22:53:17 2009 +0000
Regenerate
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commit bd623a83da8cc21ab3fd2ec6175041ee68f5171d
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Fri Sep 25 22:52:29 2009 +0000
Provide proper masks for neon perfect shuffle table.
I definitely need to read documentation better :(
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commit 04abe740fc7391473a417d498535eed8fd834a4b
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 22:26:13 2009 +0000
Simplify a few more uses of reg_iterator.
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commit 282a4ab6f595a493b5fe6cdd36ff9673454e1f16
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 22:24:52 2009 +0000
Simplify this code by using use_iterator instead of reg_iterator
and skipping the defs.
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commit 65561df4eb4eb52ebf75755e9f9eafa36929fa0e
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Sep 25 21:44:53 2009 +0000
Code clean up and prepare for Thumb2 support. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82805 91177308-0d34-0410-b5e6-96231b3b80d8
commit c9122db8146cea80861ecaac6566ae8f75ed2497
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Sep 25 21:38:11 2009 +0000
Flip -disable-post-RA-scheduler to -post-RA-scheduler.
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commit 41a338b1690f69bf6f35349e064e6c2543b15a6a
Author: Jeffrey Yasskin <jyasskin at google.com>
Date: Fri Sep 25 21:07:20 2009 +0000
Fix a compile failure introduced by r82675 on MinGW which doesn't have
setenv(). This patch just disables the test rather than getting putenv() to
work. Thanks to Sandeep Patel for reporting the problem.
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commit c78858514eb50d76bd73ca360f58971ff9bc4ac4
Author: Dale Johannesen <dalej at apple.com>
Date: Fri Sep 25 20:54:50 2009 +0000
Handle sqrt in CannotBeNegativeZero. absf and absl
appear to be misspellings, removed in favor of fabs*.
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commit 4e3bb1bc735783b73f2dcca82c86b7faca1a87e8
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 20:36:54 2009 +0000
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
commit 61fda0d889b3578fe435455679182c231a649aac
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 18:54:59 2009 +0000
Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
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commit 36bff0c1f84aa517c66320c6864e4443e818e574
Author: David Goodwin <david_goodwin at apple.com>
Date: Fri Sep 25 18:38:29 2009 +0000
Finish scheduling itineraries for NEON.
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commit ba159cf257a14d31d2dbbe8b52e934c9f8af85fb
Author: Dale Johannesen <dalej at apple.com>
Date: Fri Sep 25 18:15:29 2009 +0000
Add readonly to some sin and cos calls; transformations
being checked aren't valid without it.
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commit 131e0fcf808340c24aa7f519b7108121142a9b4b
Author: Victor Hernandez <vhernandez at apple.com>
Date: Fri Sep 25 18:11:52 2009 +0000
Revert 82694 "Auto-upgrade malloc instructions to malloc calls." because it causes regressions in the nightly tests.
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commit bccd219ac7eb590d369f9bda03ade6467aa49e24
Author: Dale Johannesen <dalej at apple.com>
Date: Fri Sep 25 18:00:35 2009 +0000
Make sure sin, cos, sqrt calls are marked readonly
before producing FSIN, FCOS, FSQRT. If they aren't
so marked we have to assume they might set errno.
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commit e2bc7c2439c37d883c22dd27c87301a4e2c935b3
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 25 17:29:36 2009 +0000
reject attempts to use ()'s in patterns, these are reserved for filecheck.
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commit ce89de231525a80c137a1de88fb8d0467c6ce973
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 25 17:23:43 2009 +0000
reimplement the regex matching strategy by building a single
regex and matching it instead of trying to match chunks at a time.
Matching chunks at a time broke with check lines like
CHECK: foo {{.*}}bar
because the .* would eat the entire rest of the line and bar would
never match.
Now we just escape the fixed strings for the user, so that something
like:
CHECK: a() {{.*}}???
is matched as:
CHECK: {{a\(\) .*\?\?\?}}
transparently "under the covers".
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commit 8891e4478909879ca4f4e745312b542cc8aca7e6
Author: Dale Johannesen <dalej at apple.com>
Date: Fri Sep 25 17:23:22 2009 +0000
Generate FSQRT from calls to the sqrt function, which
allows appropriate backends to generate a sqrt instruction.
On x86, this isn't done at -O0 because we go through
FastISel instead. This is a behavior change from before
this series of sqrt patches started. I think this is OK
considering that compile speed is most important at -O0, but
could be convinced otherwise.
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commit f6f6363c80e0e1fd4ff8e20a8f259d1e66310a1f
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 25 17:09:12 2009 +0000
special case Patterns that are a single fixed string. This is a microscopic
perf win and is needed for future changes.
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commit 4730cd3d31451fb62c8c8401cceee4439b7c1626
Author: Dale Johannesen <dalej at apple.com>
Date: Fri Sep 25 17:04:42 2009 +0000
Revise C library functions description to be vaguer, per Chris.
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commit e2de471c77ff3baeac8e535fffc28de1e57799a9
Author: Jeffrey Yasskin <jyasskin at google.com>
Date: Fri Sep 25 16:46:09 2009 +0000
This patch causes the --enable-debug-runtime configure flag and the
DEBUG_RUNTIME Makefile variable to pass -g to gcc when building LLVM's objects.
Without this, it's very hard to debug crashes that happen in Release-Asserts
mode but not Debug mode.
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commit e55e52532c4a76b7ec83e530e3fe3b0bc0b8c00c
Author: Bob Wilson <bob.wilson at apple.com>
Date: Fri Sep 25 16:34:46 2009 +0000
Add some comments to clarify things that I discovered this week.
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commit bd4cb23f6a5954a3fff1afe6f807c02eab8910e9
Author: Daniel Dunbar <daniel at zuster.org>
Date: Fri Sep 25 16:04:21 2009 +0000
Make llvm-bcanalyzer percentages more readable.
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commit 14a16fee44fce77ae10d7144e547b7b8bed872b6
Author: Daniel Dunbar <daniel at zuster.org>
Date: Fri Sep 25 16:03:57 2009 +0000
Strip trailing whitespace.
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commit c1c8b5e19b33c8b5e52c4b516669181f18feb98e
Author: Bob Wilson <bob.wilson at apple.com>
Date: Fri Sep 25 14:41:49 2009 +0000
pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack
alignment is just always 4 bytes. For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.
After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo. This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4. (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.
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commit 8c417db6fa3361d12502438264a66352a8fd6531
Author: Duncan Sands <baldrick at free.fr>
Date: Fri Sep 25 12:28:37 2009 +0000
Print INST_INBOUNDS_GEP rather than UnknownCode30.
Likewise for constant inbounds GEP.
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commit d777d83398260186ab5744a6eb01e55e3d8757fd
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 25 06:49:41 2009 +0000
convert testcases to filecheck.
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commit d33999c4a5ccdb8cd555477e51987ce6c3ed1f04
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 25 06:47:09 2009 +0000
filecheck should not match a \n with a .
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commit 57f2699a01d2bf5a7544da99676c612955bbd05f
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 25 06:37:22 2009 +0000
remove a large unreduced testcase
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commit 8527c712c7db0d0f0a31c225024bbef3f2dde62d
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 25 06:32:47 2009 +0000
turn a std::pair into a real class.
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commit aec69ee8287d0ac26b45fb20240af79e5497ef01
Author: Nate Begeman <natebegeman at mac.com>
Date: Fri Sep 25 06:05:26 2009 +0000
Fix combiner-aa issue with bases which are different, but can alias.
Previously, it treated GV+28 GV+0 as different bases, and assumed they could
not alias.
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commit cbaa5bdd135396a097a648574a6706eec224e5ec
Author: Bob Wilson <bob.wilson at apple.com>
Date: Fri Sep 25 05:30:55 2009 +0000
Update the description of MachineFrameInfo's OffsetAdjustment. The value of
this adjustment does not change the direction or the signs of the object
offsets, and the details of the offset calculations can be target-specific.
Also mention that for most targets this value is only used to generate debug
info.
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commit 06d175346442b0b31427d8806d5022c3248bf674
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 00:57:30 2009 +0000
Don't try to use pre-indexed addressing with sthbrx/stwbrx
instructions. This fixes a PowerPC bug exposed by some unrelated
changes I'm working on.
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commit 594bb86a065af025a8fd90ef486d9f54fb869f95
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 25 00:34:34 2009 +0000
Add a version of dumpr() that has a SelectionDAG* argument.
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commit abd0e3ddaf34e1589bae68eecb9fcfb7f14ac297
Author: Jim Grosbach <grosbach at apple.com>
Date: Thu Sep 24 23:52:18 2009 +0000
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
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commit f47ed3b170f267cc8eb18d841e16fc60e900e9bf
Author: Dale Johannesen <dalej at apple.com>
Date: Thu Sep 24 23:37:40 2009 +0000
Reenable sqrt IR generation test.
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commit 2fd84e281e90d309c22639a7ba9585871050e777
Author: Mike Stump <mrs at apple.com>
Date: Thu Sep 24 23:21:26 2009 +0000
Delete space after function name, before (, reflow a comment and
delete a few blank lines.
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commit cf991836d66fafd16a28b20a04bbff143c99e700
Author: Mike Stump <mrs at apple.com>
Date: Thu Sep 24 23:11:08 2009 +0000
Fix spacing.
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commit f55e81bef95886581ceb0597e7e6c4838e5cf002
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 24 21:47:32 2009 +0000
add and document regex support for FileCheck. You can now do stuff like:
; CHECK: movl {{%e[a-z][xi]}}, %eax
or whatever.
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commit 2255c43ab2731fee0d00702175336d4b42ba9e0e
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 24 21:45:57 2009 +0000
unconditionally request MMI
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commit c77786ebfb8a4dcf223031c7140e454fad3aa702
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 24 21:44:20 2009 +0000
wrap long lines.
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commit edc81f3d96a63163abf9f4b17eb9fdc8068cd9cf
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 24 20:45:07 2009 +0000
Use CanonicalizeInputFile to canonicalize the entire buffer containing the
CHECK strings, instead of canonicalizing the patterns directly. This allows
Pattern to just contain a StringRef instead of std::string.
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commit bbb96e5913e916ab74cd4cec3ec40e8fa9942dda
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 24 20:39:13 2009 +0000
change 'not' matching to use Pattern, move pattern parsing logic into
the Pattern class.
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commit 5ee02f11e57a367a7dbdc855d65a66ab3442e177
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 24 20:25:55 2009 +0000
refactor out the match string into its own Pattern class.
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commit 16905eda1a5f9e55bc061df7018afc1264258b85
Author: Bob Wilson <bob.wilson at apple.com>
Date: Thu Sep 24 20:23:02 2009 +0000
Convert to FileCheck.
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commit ed17499ee7446c5da5638f6c4c34eea660808a3d
Author: David Goodwin <david_goodwin at apple.com>
Date: Thu Sep 24 20:22:50 2009 +0000
Make the end-of-itinerary mark explicit. Some cleanup.
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commit 7f3103731c7d2ee3608f401031d0b9f785293e35
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 24 20:20:08 2009 +0000
Add nounwind to this test.
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commit 81f61b9291284bd0dc93d9dc333c1962a4399719
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 24 20:15:51 2009 +0000
tidy up, fix a memory leak in Regex::isValid
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commit 9fcf4a9c8f35d53460b62db4a13fa14c7e1d1676
Author: Dale Johannesen <dalej at apple.com>
Date: Thu Sep 24 18:38:21 2009 +0000
Clarify that llvm attaches C language semantics to
functions with names that match the C library.
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commit 129b2d16553e46db3b5675b63e777931e2ea4cec
Author: Edwin Török <edwintorok at gmail.com>
Date: Thu Sep 24 18:33:42 2009 +0000
Constant propagating byval pointer is safe if function is readonly.
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commit b493c9735a034856258c992d967b523d0effa7ce
Author: Victor Hernandez <vhernandez at apple.com>
Date: Thu Sep 24 17:47:49 2009 +0000
Auto-upgrade malloc instructions to malloc calls.
Reviewed by Devang Patel.
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commit 92244901c3c0101b8114ffa52c1dcf0e9cda72a1
Author: Bob Wilson <bob.wilson at apple.com>
Date: Thu Sep 24 16:42:27 2009 +0000
Fix a hypothetical problem for targets with StackGrowsUp and a non-zero
LocalAreaOffset. (We don't have any of those right now.)
PEI::calculateFrameObjectOffsets includes the absolute value of the
LocalAreaOffset in the cumulative offset value used to calculate the
stack frame size. It then adds the raw value of the LocalAreaOffset
to the stack size. For a StackGrowsDown target, that raw value is negative
and has the effect of cancelling out the absolute value that was added
earlier, but that obviously won't work for a StackGrowsUp target. Change
to subtract the absolute value of the LocalAreaOffset.
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commit ef534da2d0f3316b5ad378a00899e8d127362b5d
Author: Devang Patel <dpatel at apple.com>
Date: Thu Sep 24 16:19:11 2009 +0000
Move parent assertion check before metadata deletion.
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commit d54353779c9a33c745178f01785113300c7acb0e
Author: Edwin Török <edwintorok at gmail.com>
Date: Thu Sep 24 09:47:18 2009 +0000
Don't constant propagate byval pointers, since they are not really pointers, but
rather structs passed by value.
This fixes PR5038.
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commit a8b807194946fe34f364a39721205c00c1906482
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 24 06:23:57 2009 +0000
Add count/not tools as executables.
- Apparently, I'm willing to do incredibly stupid things in the name of portability.
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commit c73e8ebf88f2c21b857296951b4babc6bd404426
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 24 05:44:53 2009 +0000
unconditionally compute MMI even if the target doesn't support EH or Debug info, because the target may use it for other things, this fixes PR5036
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commit c8b70669b5480ad74079a8b8424d58c51b0cfa84
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 24 05:38:36 2009 +0000
reapply r82348 with a fix, thanks Jeffrey.
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commit f33cdc3f423b26e209fd058d50acea55966adb00
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Sep 24 02:27:09 2009 +0000
Fix PR5024 with a big hammer: disable the double-def assertion in the scavenger.
LiveVariables add implicit kills to correctly track partial register kills. This works well enough and is fairly accurate. But coalescer can make it impossible to maintain these markers. e.g.
BL <ga:sss1>, %R0<kill,undef>, %S0<kill>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def>, ...
...
%reg1031<def> = FLDS <cp#1>, 0, 14, %reg0, Mem:LD4[ConstantPool]
...
%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>
When reg1031 and S0 are coalesced, the copy (FCPYS) will be eliminated the the implicit-kill of D0 is lost. In this case it's possible to move the marker to the FLDS. But in many cases, this is not possible. Suppose
%reg1031<def> = FOO <cp#1>, %D0<imp-def>
...
%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>
When FCPYS goes away, the definition of S0 is the "FOO" instruction. However, transferring the D0 implicit-kill to FOO doesn't work since it is the def of D0 itself. We need to fix this in another time by introducing a "kill" pseudo instruction to track liveness.
Disabling the assertion is not ideal, but machine verifier is doing that job now. It's important to know double-def is not a miscomputation since it means a register should be free but it's not tracked as free. It's a performance issue instead.
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commit 04f3d1de138c7ebffc1d37a273e5a8675b6a933d
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Sep 24 02:15:22 2009 +0000
Clean up LiveVariables and change how it deals with partial updates and kills. This also eliminate the horrible check which scan forward to the end of the basic block. It should be faster and more accurate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82676 91177308-0d34-0410-b5e6-96231b3b80d8
commit 07c5e3ce817f75c90d00d48b0acd765e4e9ec6b5
Author: Jeffrey Yasskin <jyasskin at google.com>
Date: Thu Sep 24 01:14:07 2009 +0000
Roll back r82348, which introduced an infinite loop in ParseCStringVector() that
a trivial unittest would have caught. This revision also adds the trivial
unittest.
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commit f1b016061ea1eb7a321b1b4d20976a651b3c24b6
Author: Dale Johannesen <dalej at apple.com>
Date: Wed Sep 23 22:05:24 2009 +0000
A minor improvment in accuracy to inline cost
computation, and some cosmetics.
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commit 7b4f81c688a6b32d799f7e0b95f6fe131d7ffb24
Author: Dale Johannesen <dalej at apple.com>
Date: Wed Sep 23 21:46:36 2009 +0000
Disable test; what it's testing for is wrong.
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commit 78caa12a415bbd16db04088be6378398d4909b6f
Author: David Goodwin <david_goodwin at apple.com>
Date: Wed Sep 23 21:38:08 2009 +0000
Checkpoint NEON scheduling itineraries.
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commit ad4880332c61c808014c202255dce5f8fafe581e
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 23 21:07:02 2009 +0000
Use getStoreSize() instead of getStoreSizeInBits()/8.
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commit 63521d0ab0566f418464b29e5ac6cca7710ae094
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 23 21:06:36 2009 +0000
Spruce up some comments.
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commit 3bab1f776cf32aadd62d490f54cec968ef38eec7
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 23 21:02:20 2009 +0000
Rename several variables from EVT to more descriptive names, now that EVT
is also the name of their type, as declarations like "EVT EVT" look
really odd.
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commit a387c633b81a60a676445c8d89513a7518b8f7fc
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 23 20:59:10 2009 +0000
Add an EVT::getStoreSize function, like getStoreSizeInBits but in bytes.
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commit ef0853ae5ef4ef4dac82362ecb914ad2b3df1ae0
Author: Jakob Stoklund Olesen <stoklund at 2pi.dk>
Date: Wed Sep 23 20:57:55 2009 +0000
Fix verification of explicit operands.
The machine code verifier did not check for explicit operands correctly. It
used MachineInstr::getNumExplicitOperands, but that method may cheat and use
the declared count in the TargetInstrDesc.
Now we check the explicit operands one at a time in visitMachineOperand.
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commit 95e76c5aee19e6e44bda135a7f7a32c2602c493f
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 23 20:57:02 2009 +0000
Remove BlackfinRegisterInfo::getFrameIndexOffset since it is the same as the
default implementation. Update comment on the default version, which made it
sound like most targets override it. Currently only X86 and SystemZ override
this method.
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commit 1f939a29fdfdfc31e521209c44fc1ca3b1ecfc6f
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 23 20:40:16 2009 +0000
Correct a comment.
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commit 579edbf7bf65497e3afa498baaf1cb6642ef3de0
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 23 20:33:51 2009 +0000
Delete attached metadata when an instruction is deleted.
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commit 3fad552803d264b6bf83981de305e7080cb8ef4f
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Wed Sep 23 19:04:09 2009 +0000
ARM does not support offset folding (yet). Disable it for now.
This fixes PR5031. Unfortunately, there is no small testcase :(
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commit a9b57edff7a7dbf11ba9fe787349d21f7e3e80f6
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 23 18:53:19 2009 +0000
Edit a comment.
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commit 6b7c1e84c407ef2ba17ed953f0368eb54a5ef106
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 23 18:32:25 2009 +0000
Do not leave behind metadata while cloning an instruction.
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commit 724190977bf4a7289c24e923f33ad6b7e172cfbf
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 23 18:20:27 2009 +0000
Add nounwind.
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commit 7fdd6fe71635b720cb3c47fe9bbe4c7587cb027d
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 23 17:20:43 2009 +0000
s/*Location/*DebugLocation/g
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commit 35659ae0fc161cf474f5ca81c497d58a90b7c4e0
Author: Jeffrey Yasskin <jyasskin at google.com>
Date: Wed Sep 23 17:05:42 2009 +0000
PR4047: Permit configure --enable-targets=host,cpp for example. "host" has the
same effect that "host-only" used to have, but can be combined with other
targets. host-only is still available as a synonym but no longer documented.
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commit 83b6ace01ffb5d8d495a4b70c7406d06f0dd2067
Author: David Goodwin <david_goodwin at apple.com>
Date: Wed Sep 23 16:35:25 2009 +0000
Fix bug in kill flag updating for post-register-allocation scheduling. When the kill flag of a superreg needs to be cleared because there are one or more subregs live, we instead add implicit-defs of those subregs and leave the kill flag on the superreg. This allows us to end the live-range of the superreg without ending the live-ranges of the subregs.
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commit 5faba0e3a308107b7a40b53ea72b6bfbdd19e28b
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Wed Sep 23 11:48:57 2009 +0000
Fix a struct/class mismatch.
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commit e9cbef31ba8c374d41249635197e58c102fe41fb
Author: John McCall <rjmccall at apple.com>
Date: Wed Sep 23 06:53:51 2009 +0000
Make the type traits for a const pointer defer to those for a unqualified
pointer, instead of providing independent values modelled on the default
implementation.
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commit d062bf740651c35ed3ee80b66b02d8363fd14a3a
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 23 06:28:31 2009 +0000
Fix PR5024. LiveVariables physical register defs should *commit* only after all
of the defs are processed.
Also fix a implicit_def propagation bug: a implicit_def of a physical register
should be applied to uses of the sub-registers.
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commit 29a1c10040effaa8c0968a3899b053b6b591a73a
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 23 05:23:19 2009 +0000
Fix a obvious logic error.
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commit d3593be80c4db01a12d00222ccd196fb10ddc766
Author: Gabor Greif <ggreif at gmail.com>
Date: Wed Sep 23 02:46:12 2009 +0000
pretty mechanical changes to match coding guidelines (blessed by sabre on IRC)
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commit 03344a20c2a1d291282ead342f0bfb858909c7dc
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 23 02:03:49 2009 +0000
errorstr can be null, don't unconditionally set it. Only report that
"the jit has not been linked in" if the interpreter failed.
This fixes a unit test failure.
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commit cd0d937f2811e62d66743e588b0a2e0154af2411
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 23 01:46:04 2009 +0000
Make EngineBuilder return more error codes, by KS Sreeram.
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commit 915d872b7a05774ea93ba7fbb25f0944d62e10fb
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 23 01:33:16 2009 +0000
Give MachineMemOperand an operator<<, factoring out code from
two different places for printing MachineMemOperands.
Drop the virtual from Value::dump and instead give Value a
protected virtual hook that can be overridden by subclasses
to implement custom printing. This lets printing be more
consistent, and simplifies printing of PseudoSourceValue
values.
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commit 17f460a7f0b06133486bf897cc67373e07687bf2
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 23 01:29:41 2009 +0000
Fix X86's unfoldMemoryOperand to properly handle MachineMemOperands.
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commit 069f1c9642c471d827cfaaca98f31aef707464ee
Author: Mike Stump <mrs at apple.com>
Date: Wed Sep 23 00:13:30 2009 +0000
This is overly constraining with respect to clang.
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commit efb268acfd0ecf9b39a555267393058e685030fb
Author: Erick Tryzelaar <idadesub at users.sourceforge.net>
Date: Tue Sep 22 21:15:19 2009 +0000
Add examples for Kaleidoscope chapters 2 through 6.
Conflicts:
examples/Makefile
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commit 2a20265022d36c31bdf7c4f041b10695bcb09c45
Author: Erick Tryzelaar <idadesub at users.sourceforge.net>
Date: Tue Sep 22 21:15:00 2009 +0000
Rename Kaleidoscope to show that it's for Chapter 7 of the tutorial.
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commit fb577b0367500de745082228b0a1569365ecc68c
Author: Erick Tryzelaar <idadesub at users.sourceforge.net>
Date: Tue Sep 22 21:14:49 2009 +0000
Sync c++ kaleidoscope tutorial with test.
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commit 191278d73343733b56e030ace8f6a9dcdf08818a
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 22 20:56:31 2009 +0000
Add SetLocation() to allow IRBuilder user to set location info for an instruction already created.
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commit 5ffdd0e9c3eb03b473ddf666c885cecbc15f8df7
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 22 20:54:13 2009 +0000
Check exisiting dbg MDKind first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82568 91177308-0d34-0410-b5e6-96231b3b80d8
commit d80fa7f67d06ef47913578a8212be349722a9df5
Author: Victor Hernandez <vhernandez at apple.com>
Date: Tue Sep 22 18:50:03 2009 +0000
No need to verify that malloc's return type is i8*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82561 91177308-0d34-0410-b5e6-96231b3b80d8
commit cc74792c99e085a14bdd6db9edea362b465406da
Author: David Goodwin <david_goodwin at apple.com>
Date: Tue Sep 22 16:47:52 2009 +0000
Use early returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82554 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9f854de1b687e0906e7521393f1fa176e4b15b52
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 16:33:42 2009 +0000
Revert "Don't allow formatted_ostream to be unbuffered, even if its underlying
buffer", while we work out a solution.
Dan convinced me that making debugging annoying for him is worse than 10x being
slower for me. :)
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commit f54515d6770a86c4268b41a60a9536b4993e6400
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 16:10:35 2009 +0000
... missed hiding a variable for MSVC only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82552 91177308-0d34-0410-b5e6-96231b3b80d8
commit 441722f4b863b8b9ac8410c2c36217596252dbd6
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 15:58:35 2009 +0000
Hide MSVC specific CRT interaction behind _MSC_VER.
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commit ed6353b87ccbbf7ddaa63a25bfad14afc3079da0
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Tue Sep 22 15:40:32 2009 +0000
Remove the GetProcessId() call from Win32/Program.inc, take 2.
GetProcessId() was introduced only in Windows XP, and we want to support earlier
versions.
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commit c2d3000deec82fd0c808af98c089e5eb628ef47b
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 10:30:34 2009 +0000
Fix commento.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82544 91177308-0d34-0410-b5e6-96231b3b80d8
commit 6463aedb7b4da91f81362b039b697ee0fed50312
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 09:50:38 2009 +0000
lit: When executing shell scripts internally, don't allow piped stderr on any
commands except the last one, instead redirect the stderr to a temporary
file. This sidesteps a potential deadlocking issue.
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commit 1e57bc8dcf0be1c58fdb06bb83c34b140b9074fa
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 09:50:28 2009 +0000
Add a magic LLVM_DISABLE_CRT_DEBUG environment variable which we check in RegisterHandler and use to disable the Win32 crash dialogs. These are a major blocker to any kind of automated testing.
Also, tweak the 'lit' test runner to set this variable unconditionally.
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commit ff8e568bb5c578639e690ba4e2f0499f3dd78b46
Author: Evan Cheng <evan.cheng at apple.com>
Date: Tue Sep 22 08:47:59 2009 +0000
Forgot this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82536 91177308-0d34-0410-b5e6-96231b3b80d8
commit cd216d523e696749d681faca9f3bda92b13cd695
Author: Evan Cheng <evan.cheng at apple.com>
Date: Tue Sep 22 08:34:46 2009 +0000
Fix PR5024. LiveVariables::FindLastPartialDef should return a set of sub-registers that were defined by the last partial def, not just a single sub-register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82535 91177308-0d34-0410-b5e6-96231b3b80d8
commit a4acff7bb0d00b82a152fe067335260a42b5cab1
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 07:38:44 2009 +0000
Initial support for running LLVM tests from cmake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82534 91177308-0d34-0410-b5e6-96231b3b80d8
commit a018c74c2f4f93f08050ac2dc1c616f8b106dc39
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 07:38:33 2009 +0000
Generate lit.site.cfg from a .in file, as clang does.
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commit cd2674d181e3edb1700721bed54e790cd9c5f4a7
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 07:38:23 2009 +0000
Use Compiler.h macro instead of __attribute__.
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commit b7784533131d4921046a46a406b1e198863e6d11
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 06:09:37 2009 +0000
CMake: Fix definition of LTDL_SHLIB_EXT for Darwin.
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commit c4e0f91cc54f6399b3e9be19a12aaa4dcbfffaff
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 06:09:31 2009 +0000
Fix llvm-config --src-root and --obj-root for CMake builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82529 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2be1b773bb528a793ed59869ad275ac74aad2b77
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 06:09:22 2009 +0000
llvm-config: Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82528 91177308-0d34-0410-b5e6-96231b3b80d8
commit 346a7bb311e53d4af9e8dd3063b10e7323e31c95
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 06:09:13 2009 +0000
Actually use the arguments with the resolved executable path.
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commit 0dfef16716fc2c26777f8404c8fa073cd42bc57e
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 04:44:56 2009 +0000
Revert "Get rid of GetProcessId in Win32/Program.inc.", this breaks
ExecuteAndWait.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82522 91177308-0d34-0410-b5e6-96231b3b80d8
commit dce584a533e962394daa5fa66065ddb344467c47
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 04:44:37 2009 +0000
lit: Don't use close_fds=True on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82521 91177308-0d34-0410-b5e6-96231b3b80d8
commit a5e3ec7946254a90b806176d1868ca919da6c35f
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 04:44:26 2009 +0000
lit: When executing commands internally, perform PATH resolution ourselves.
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commit 4cf9e690c5df0d90fdada4eabd3b203e4e906325
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 03:34:53 2009 +0000
Switch FoldingSet::AddString to StringRef based API.
- This also fixes a dereference of std::string::end, which makes MSVC unhappy and was causing all the static analyzer clang tests to fail.
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commit fa985152c3d160701fa55af97f598a478c3a456e
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 03:34:40 2009 +0000
Workaround what I believe is an MSVC bug where it emits a definition for a
static const class member into each translation unit, with external linkage???
- If someone understands this issue better, please clue me in, I haven't
consulted the standard yet.
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commit c27a50855925ba7455c4049398c80db45fcef36a
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 02:03:18 2009 +0000
Switch DIDescriptor to use a TrackingVH. - This makes it much safer to work with debug info, since it was extraordinarily easy to have dangling pointers thanks to MDNode uniquing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82507 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4f912e5070e7e43b4bd9def2d9f1038254c5806c
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 22 02:02:33 2009 +0000
Add a TrackingVH value handle.
This is designed for tracking a value even when it might move (like WeakVH), but it is an error to delete the referenced value (unlike WeakVH0. TrackingVH is templated like AssertingVH on the tracked Value subclass, it is an error to RAUW a tracked value to an incompatible type.
For implementation reasons the latter error is only diagnosed on accesses to a mis-RAUWed TrackingVH, because we don't want a virtual interface in a templated class.
The former error is also only diagnosed on access, so that clients are allowed to delete a tracked value, as long as they don't use it. This makes it easier for the client to reason about destruction.
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commit b6d716f620ad28e540c2a262504ebaeff6461b3f
Author: Evan Cheng <evan.cheng at apple.com>
Date: Tue Sep 22 01:48:19 2009 +0000
Fix a pasto. Also simplify for Bill's benefit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82505 91177308-0d34-0410-b5e6-96231b3b80d8
commit eb21e377d210da64284a7e52ca694e0f42b5062d
Author: Evan Cheng <evan.cheng at apple.com>
Date: Tue Sep 22 00:29:40 2009 +0000
Minor bug fix. LowerSubregs should translate
%S0<def> = EXTRACT_SUBREG %Q0<kill>, 1
to
%S0<def> = IMPLICIT_DEF %Q0<imp-use,kill>
Implicit_def does not *read* any register so the operand should be marked "implicit". The missing "implicit" marker on the operand is wrong, but it doesn't actually break anything.
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commit 321b572fd6b43198d21fe25f1a5ae5d5e8af50bf
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 22:39:35 2009 +0000
Fix PR5023: The instruction form of DominatorTree::dominates did not
take into consideration that the result of an invoke is only valid in
the normal dest, not the unwind dest. This caused 'PHINode::hasConstantValue'
to return true in an invalid situation, causing mem2reg to delete a phi that
was actually needed. This caused a crash building 483.xalancbmk.
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commit b171ff4d2cc5feb820dee24b5e6ad004493b8576
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 22:30:50 2009 +0000
move DominatorTree::dominates for instructions out of line,
no functionality change.
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commit a5456988b7e38012abf0b14767f0752f87520a44
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 22:27:34 2009 +0000
tidy up
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commit 1e683894a5d61beccb7a58ffa70be000eee12a73
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 22:26:02 2009 +0000
tidy up
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commit b9bbb5795a133c6cca6a5ac4e5ab110016d4e7c1
Author: Evan Cheng <evan.cheng at apple.com>
Date: Mon Sep 21 21:12:25 2009 +0000
Clean up spill weight computation. Also some changes to give loop induction
variable increment / decrement slighter high priority.
This has major impact on some micro-benchmarks. On MultiSource/Applications
and spec tests, it's a minor win. It also reduce 256.bzip instruction count
by 8%, 55 on 164.gzip on i386 / Darwin.
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commit 35d4912e3b08a8a2d0e01c0ef8b23407f8efa8db
Author: David Goodwin <david_goodwin at apple.com>
Date: Mon Sep 21 20:52:17 2009 +0000
Add Cortex-A8 VFP model.
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commit 169948d4180417313f5332b85d2572520592de3c
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 21 19:47:04 2009 +0000
Change MachineMemOperand's alignment value to be the alignment of
the base pointer, without the offset. This matches MemSDNode's
new alignment behavior, and holds more interesting information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82473 91177308-0d34-0410-b5e6-96231b3b80d8
commit 47b5330a18b00883f10807c53120a57127cc0703
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 21 18:32:20 2009 +0000
Add a comment mentioning the rdar number associated with this test.
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commit 51dbce6a853d1b2bc8084b18e741a666e7c83548
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 21 18:30:38 2009 +0000
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool
loads in order to reduce register pressure.
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commit 1948855617427c57a974e270f9fb21fb20b46420
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 21 18:03:22 2009 +0000
Recognize SSE min and max opportunities in even more cases.
And fix a bug with the behavior of min/max instructions formed from
fcmp uge comparisons.
Also, use FiniteOnlyFPMath() for this code instead of UnsafeFPMath,
as it is more specific.
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commit e57ba8991a2b71698d70928e66b8baff012b163c
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 21 17:58:09 2009 +0000
Fix the offset values for these memoperands. For frame objects, the
PseudoSourceValue already effectively represents the offset from the
frame base, so the actual offset should not be added to it.
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commit 1846fa00f3590637b7d8dbfc0f5c2254bd42436f
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 17:55:47 2009 +0000
big endian systems shift by bits too, hopefully this will fix the ppc
bootstrap problems.
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commit 55a622f7da7cdbc88190bb100cafd60127abf0ec
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 21 17:54:42 2009 +0000
Nick pointed out that DominanceFrontier and DominanceTree are preserved
by setPreservesCFG().
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commit b350b3d81e6b7df211447f0bc54b4493af9aa444
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 21 17:53:35 2009 +0000
Remove the special-case for constants in PHI nodes; it's not really
helpful, and it didn't correctly handle the case of constants input
to PHIs for backedges.
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commit 012b360d60c62c975af276d9a04fcfd79cf3ac9c
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 17:24:04 2009 +0000
fix PR5016, a crash I introduced in GVN handing first class
arrays and structs, which cannot be bitcast to integers.
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commit 8435ab1c698f403ef565764e458c7dceb70b0495
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Mon Sep 21 15:53:44 2009 +0000
Use raw_ostream::indent instead of passing strings.
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commit 30a8d480ddd031f85b3386db7ccfe11e027b525c
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 21 15:18:33 2009 +0000
Fix this assertion string to mention subreg_to_reg.
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commit 56b9fc1caef68a302d561472c1691ded886efd56
Author: Nuno Lopes <nunoplopes at sapo.pt>
Date: Mon Sep 21 14:11:56 2009 +0000
initialize SymbolsCanStartWithDigit to false by default
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commit ce08ae8748979ca3ca4a0048ebc610602a76bedc
Author: Xerxes Ranby <xerxes at zafena.se>
Date: Mon Sep 21 08:08:29 2009 +0000
Update cmake.
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commit 8314a42c92bd21ecfa700da8cbe60b6818caba33
Author: Jakob Stoklund Olesen <stoklund at 2pi.dk>
Date: Mon Sep 21 07:19:08 2009 +0000
Verify that phi instructions refer to MBBs in the CFG.
The machine code verifier no longer tolerates phi instructions with noop
operands. All MBBs on a phi instruction must be in the CFG.
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commit aae7fcb7114258c6d289601bf0d68a25aeabf5d5
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 06:48:08 2009 +0000
enable non-local analysis and PRE of large store -> little load.
This doesn't kick in too much because of phi translation issues,
but this can be resolved in the future.
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commit 19b84b380a7341297af6636f8e58373046be7d4b
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 06:30:24 2009 +0000
convert an std::pair to an explicit struct.
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commit 8f91208a30c55c3619cc1ffd1abc1ca41a2ac556
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 06:24:16 2009 +0000
move some functions, add a comment.
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commit 41eb59cc4d3718b4c640a3746b31f5253dcca243
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 06:22:46 2009 +0000
split HandleLoadFromClobberingStore in two pieces: one that does the
analysis, one that does the xform.
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commit c62f2aa0f8d92120fa45a27b97301b173b092ac4
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 06:04:07 2009 +0000
add a note
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commit 98cb5536ab1aa5667bb5b602bf691631f3bbaffc
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 21 05:58:35 2009 +0000
Register the MachineModuleInfo for the ARM JIT, and update JITDwarfEmitter to
assert if the setModuleInfo hasn't been called.
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commit 7932c5775e79a332b5cb036e71995d4738eb7fe9
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 05:57:47 2009 +0000
add pr#
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commit 0907b520a0b293e15a6296de4c37d0a44b40306d
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 05:57:11 2009 +0000
Improve GVN to be able to forward substitute a small load
from a piece of a large store when both are in the same block.
This allows clang to compile the testcase in PR4216 to this code:
_test_bitfield:
movl 4(%esp), %eax
movl %eax, %ecx
andl $-65536, %ecx
orl $32962, %eax
andl $40186, %eax
orl %ecx, %eax
ret
This is not ideal, but is a whole lot better than the code produced
by llvm-gcc:
_test_bitfield:
movw $-32574, %ax
orw 4(%esp), %ax
andw $-25350, %ax
movw %ax, 4(%esp)
movw 7(%esp), %cx
shlw $8, %cx
movzbl 6(%esp), %edx
orw %cx, %dx
movzwl %dx, %ecx
shll $16, %ecx
movzwl %ax, %eax
orl %ecx, %eax
ret
and dramatically better than that produced by gcc 4.2:
_test_bitfield:
pushl %ebx
call L3
"L00000000001$pb":
L3:
popl %ebx
movl 8(%esp), %eax
leal 0(,%eax,4), %edx
sarb $7, %dl
movl %eax, %ecx
andl $7168, %ecx
andl $-7201, %ebx
movzbl %dl, %edx
andl $1, %edx
sall $5, %edx
orl %ecx, %ebx
orl %edx, %ebx
andl $24, %eax
andl $-58336, %ebx
orl %eax, %ebx
orl $32962, %ebx
movl %ebx, %eax
popl %ebx
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82439 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5c3fd1da0082f74a5e7cb3b6b5501a67bf0097bf
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 05:52:45 2009 +0000
add a helper method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82438 91177308-0d34-0410-b5e6-96231b3b80d8
commit a32393f6bbe778ea5f6960bc67c34176ce769198
Author: Evan Cheng <evan.cheng at apple.com>
Date: Mon Sep 21 04:32:32 2009 +0000
Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82436 91177308-0d34-0410-b5e6-96231b3b80d8
commit bd66f1607e2c9e866c66fdb4b1feb9a15718075b
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 21 03:56:00 2009 +0000
Don't allow formatted_ostream to be unbuffered, even if its underlying buffer
is.
- The problem is that formatted_ostream forces its underlying buffer to be
unbuffered, so if some client happens to wrap a formatted_ostream around
something, but still use the underlying stream, then we can end up writing on
a fully unbuffered output (which was never intended to be unbuffered).
- This makes clang (and presumably llvm-gcc) -emit-llvm -S a mere 10x faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82434 91177308-0d34-0410-b5e6-96231b3b80d8
commit 51481994a6a57871da58724cd6b9aa249833c4f8
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 02:53:57 2009 +0000
one case handled, expanded another testcase inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82427 91177308-0d34-0410-b5e6-96231b3b80d8
commit ff36c95843e4cc7402357d937d848e729d022ff6
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 02:42:51 2009 +0000
formatting cleanups, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82426 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3453185664bae401dc32f9c8744c0fa9590f9716
Author: Reid Kleckner <reid at kleckner.net>
Date: Mon Sep 21 02:34:59 2009 +0000
Add documentation on how to use enable debug information in the JIT and use it with GDB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82425 91177308-0d34-0410-b5e6-96231b3b80d8
commit ec3c4b93ee43cac3749ade851f57a1863de06eb5
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 21 02:30:42 2009 +0000
fix a FileCheck bug where:
; CHECK: foo
; CHECK-NOT: foo
; CHECK: bar
would always fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82424 91177308-0d34-0410-b5e6-96231b3b80d8
commit 096f10a51b037861069e280020dd2967fdce6b6e
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 21 00:05:30 2009 +0000
Move ARM and X86 specific AsmParser tests into separate subdirectories, and only
run if appropriate target is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82419 91177308-0d34-0410-b5e6-96231b3b80d8
commit 738b4f2a7d37600af45fc6a5515d5a5be175d19e
Author: Reid Kleckner <reid at kleckner.net>
Date: Sun Sep 20 23:52:43 2009 +0000
Implement the JIT side of the GDB JIT debugging interface. To enable this
feature, either build the JIT in debug mode to enable it by default or pass
-jit-emit-debug to lli.
Right now, the only debug information that this communicates to GDB is call
frame information, since it's already being generated to support exceptions in
the JIT. Eventually, when DWARF generation isn't tied so tightly to AsmPrinter,
it will be easy to push that information to GDB through this interface.
Here's a step-by-step breakdown of how the feature works:
- The JIT generates the machine code and DWARF call frame info
(.eh_frame/.debug_frame) for a function into memory.
- The JIT copies that info into an in-memory ELF file with a symbol for the
function.
- The JIT creates a code entry pointing to the ELF buffer and adds it to a
linked list hanging off of a global descriptor at a special symbol that GDB
knows about.
- The JIT calls a function marked noinline that GDB knows about and has put an
internal breakpoint in.
- GDB catches the breakpoint and reads the global descriptor to look for new
code.
- When sees there is new code, it reads the ELF from the inferior's memory and
adds it to itself as an object file.
- The JIT continues, and the next time we stop the program, we are able to
produce a proper backtrace.
Consider running the following program through the JIT:
#include <stdio.h>
void baz(short z) {
long w = z + 1;
printf("%d, %x\n", w, *((int*)NULL)); // SEGFAULT here
}
void bar(short y) {
int z = y + 1;
baz(z);
}
void foo(char x) {
short y = x + 1;
bar(y);
}
int main(int argc, char** argv) {
char x = 1;
foo(x);
}
Here is a backtrace before this patch:
Program received signal SIGSEGV, Segmentation fault.
[Switching to Thread 0x2aaaabdfbd10 (LWP 25476)]
0x00002aaaabe7d1a8 in ?? ()
(gdb) bt
#0 0x00002aaaabe7d1a8 in ?? ()
#1 0x0000000000000003 in ?? ()
#2 0x0000000000000004 in ?? ()
#3 0x00032aaaabe7cfd0 in ?? ()
#4 0x00002aaaabe7d12c in ?? ()
#5 0x00022aaa00000003 in ?? ()
#6 0x00002aaaabe7d0aa in ?? ()
#7 0x01000002abe7cff0 in ?? ()
#8 0x00002aaaabe7d02c in ?? ()
#9 0x0100000000000001 in ?? ()
#10 0x00000000014388e0 in ?? ()
#11 0x00007fff00000001 in ?? ()
#12 0x0000000000b870a2 in llvm::JIT::runFunction (this=0x1405b70,
F=0x14024e0, ArgValues=@0x7fffffffe050)
at /home/rnk/llvm-gdb/lib/ExecutionEngine/JIT/JIT.cpp:395
#13 0x0000000000baa4c5 in llvm::ExecutionEngine::runFunctionAsMain
(this=0x1405b70, Fn=0x14024e0, argv=@0x13f06f8, envp=0x7fffffffe3b0)
at /home/rnk/llvm-gdb/lib/ExecutionEngine/ExecutionEngine.cpp:377
#14 0x00000000007ebd52 in main (argc=2, argv=0x7fffffffe398,
envp=0x7fffffffe3b0) at /home/rnk/llvm-gdb/tools/lli/lli.cpp:208
And a backtrace after this patch:
Program received signal SIGSEGV, Segmentation fault.
0x00002aaaabe7d1a8 in baz ()
(gdb) bt
#0 0x00002aaaabe7d1a8 in baz ()
#1 0x00002aaaabe7d12c in bar ()
#2 0x00002aaaabe7d0aa in foo ()
#3 0x00002aaaabe7d02c in main ()
#4 0x0000000000b870a2 in llvm::JIT::runFunction (this=0x1405b70,
F=0x14024e0, ArgValues=...)
at /home/rnk/llvm-gdb/lib/ExecutionEngine/JIT/JIT.cpp:395
#5 0x0000000000baa4c5 in llvm::ExecutionEngine::runFunctionAsMain
(this=0x1405b70, Fn=0x14024e0, argv=..., envp=0x7fffffffe3c0)
at /home/rnk/llvm-gdb/lib/ExecutionEngine/ExecutionEngine.cpp:377
#6 0x00000000007ebd52 in main (argc=2, argv=0x7fffffffe3a8,
envp=0x7fffffffe3c0) at /home/rnk/llvm-gdb/tools/lli/lli.cpp:208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82418 91177308-0d34-0410-b5e6-96231b3b80d8
commit 11c06f4536a6ced3db546b5c7b07ff75047a302c
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 20 23:30:31 2009 +0000
Work around a FileCheck bug, for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82416 91177308-0d34-0410-b5e6-96231b3b80d8
commit bc1c1435324c8b816a1174dd8b6b177f420d6ba8
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 22:56:43 2009 +0000
simplify as daniel suggests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82415 91177308-0d34-0410-b5e6-96231b3b80d8
commit a094468e10fe4f091e7d907293becbdcfbd6427e
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 22:54:26 2009 +0000
write rfind in terms of npos as daniel requested
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82414 91177308-0d34-0410-b5e6-96231b3b80d8
commit 637012fa510c7edf6b964a351eb3f265ed799674
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 22:46:42 2009 +0000
remove a dead method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82413 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3472feab21a77560d266b6ff1a24c5e56a99fb42
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 22:45:18 2009 +0000
grammaro
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82412 91177308-0d34-0410-b5e6-96231b3b80d8
commit c911446f73dd4b9d08d33002826f4abb660c8f0a
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 22:44:26 2009 +0000
Revert r82404, it is causing a bootstrap miscompile. This is very very
scary, as it indicates a lurking bug. yay.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82411 91177308-0d34-0410-b5e6-96231b3b80d8
commit 01467f6f77e9ac0cf6529a6859557def9b7a8c89
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 22:42:44 2009 +0000
rewrite CountNumNewlinesBetween to be in terms of StringRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82410 91177308-0d34-0410-b5e6-96231b3b80d8
commit 873602b157d1fbdf0c325f03ec7d1845536286e9
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 22:36:11 2009 +0000
this was not supposed to be committed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82409 91177308-0d34-0410-b5e6-96231b3b80d8
commit 0d82c7077aaeb545a95fc782af1d742ea4a76016
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 22:35:26 2009 +0000
implement and document support for CHECK-NOT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82408 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7f850d129178bcf88a47450425f40adac1ed1dbb
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 22:11:44 2009 +0000
rewrite FileCheck in terms of StringRef instead of manual pointer pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82407 91177308-0d34-0410-b5e6-96231b3b80d8
commit f1e45469b47ce54ae561ac4e1ab5369e5c5d73ec
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 21:00:18 2009 +0000
improve memdep to eliminate bitcasts (and aliases, and noop geps)
early for the stated reasons: this allows it to find more
equivalences and depend less on code layout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82404 91177308-0d34-0410-b5e6-96231b3b80d8
commit d6b1d05df6e52b543bc7a580ae50876b1c75e1ba
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 20:09:34 2009 +0000
Move CoerceAvailableValueToLoadType earlier in GVN.cpp. Hook it up
so that nonlocal and partially redundant loads can use it as well.
The testcase shows examples of craziness this can handle. This triggers
*many* times in 176.gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82403 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3de5c8cdc9d2dbeb463861ec0754ba9d22f3e821
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 19:31:14 2009 +0000
change the interface to CoerceAvailableValueToLoadType to be
more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82402 91177308-0d34-0410-b5e6-96231b3b80d8
commit a266ec3f6128ce246bc5616f23810d74d7189676
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 20 19:04:28 2009 +0000
Teach 'make check-all' to build the site configuration for clang, if it is in tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82400 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7741aa5bd6c283df1435bc6c140ebc5dac40327c
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 19:03:47 2009 +0000
enhance GVN to forward substitute a stored value to a load
(and load -> load) when the base pointers must alias but when
they are different types. This occurs very very frequently in
176.gcc and other code that uses bitfields a lot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82399 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7acce9445f10d7ddea1480a477473ce0ca92a1b0
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 17:37:38 2009 +0000
update an entry, delete an entry which has been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82398 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9c220f60be3a50de7fd2a5c491ccfa63c5d3a342
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 17:32:21 2009 +0000
tidy up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82397 91177308-0d34-0410-b5e6-96231b3b80d8
commit dac97dab11fffaae623be1d4bd2a0c2e249a5c54
Author: Bill Wendling <isanbard at gmail.com>
Date: Sun Sep 20 09:13:15 2009 +0000
--- Reverse-merging r82282 into '.':
U lib/CodeGen/AsmPrinter/DwarfException.cpp
U lib/CodeGen/AsmPrinter/DwarfException.h
--- Reverse-merging r82274 into '.':
U lib/Target/TargetLoweringObjectFile.cpp
G lib/CodeGen/AsmPrinter/DwarfException.cpp
These revisions were breaking everything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82396 91177308-0d34-0410-b5e6-96231b3b80d8
commit f0544b677b4974c107db08d19d419ce3a5703478
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 07:47:59 2009 +0000
remove a temporary hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82395 91177308-0d34-0410-b5e6-96231b3b80d8
commit bf4b6a8e534c6934d3f702cb8d15e727096aabfb
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 07:41:30 2009 +0000
rename X86ATTAsmPrinter.cpp -> X86AsmPrinter.cpp likewise the .h file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82394 91177308-0d34-0410-b5e6-96231b3b80d8
commit c8ef9fecee83d80f51ef84e4ccfb1aff73d965c4
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 07:39:06 2009 +0000
move target registry stuff to X86ATTAsmPrinter.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82393 91177308-0d34-0410-b5e6-96231b3b80d8
commit 937948b3621332a2bbd8b1ca414fbb04b89e65a8
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 07:37:51 2009 +0000
simplify this now that createX86CodePrinterPass is trivial
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82392 91177308-0d34-0410-b5e6-96231b3b80d8
commit 477b9ac19d813b317e3b90ebfdffa1953d4e1261
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 07:35:34 2009 +0000
rename X86ATTAsmPrinter class -> X86AsmPrinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82391 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2aa10dafe6b2eeccc73dda8817d0eebce9481c63
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 07:32:00 2009 +0000
remove the asmstring, it is now dead. Improve comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82390 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5086a10b582cf8d9f0f1ac4d7569c24d260092c8
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 07:31:25 2009 +0000
Peer through zext and sext to eliminate them when it is safe to do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82389 91177308-0d34-0410-b5e6-96231b3b80d8
commit a7e959d869e698bf1b8d22044d96655632f6072e
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 07:28:26 2009 +0000
kill off printPICLabel now, it's specialness is handled by
the MachineInstr ->MCInst lowering process, not in the
asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82388 91177308-0d34-0410-b5e6-96231b3b80d8
commit 548587879c1ca975c31cfa7a2e93d2778270d8ce
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 07:25:17 2009 +0000
delete X86IntelAsmPrinter! Now -x86-asm-syntax just switches
the instruction syntax, not the entire asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82387 91177308-0d34-0410-b5e6-96231b3b80d8
commit cfef6a6a359626560bb9ce090df8895dbc898b00
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 07:21:39 2009 +0000
Fold 'icmp eq (icmp), true' into an xor(icmp).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82386 91177308-0d34-0410-b5e6-96231b3b80d8
commit d6153b455d4f5ef8514356fbfbbeae0f2281ad77
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 07:17:49 2009 +0000
Add an intel syntax MCInstPrinter implementation. You can now
transcode from AT&T to intel syntax with "llvm-mc foo.s -output-asm-variant=1"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82385 91177308-0d34-0410-b5e6-96231b3b80d8
commit a77caae2f50e84a6e1b6e084709806b65680b005
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 07:16:54 2009 +0000
tidy up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82384 91177308-0d34-0410-b5e6-96231b3b80d8
commit 241fa24501d56a9fc02373cb38d1ef53cc155bef
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 07:00:24 2009 +0000
Rewrite this check so that it checks what it's supposed to and doesn't use
CHECK-NOT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82383 91177308-0d34-0410-b5e6-96231b3b80d8
commit fc71ac06870a72ae5c040e28f30c8064db85af48
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 06:58:54 2009 +0000
eliminate a use of strtoul.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82382 91177308-0d34-0410-b5e6-96231b3b80d8
commit 14267fcd04c922b6c52d7b9bb474479e5bf57889
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 06:45:52 2009 +0000
split random COFF asmprinter state out to X86COFFMachineModuleInfo.h.
Make dllexport directives come out in determinstic order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82381 91177308-0d34-0410-b5e6-96231b3b80d8
commit 81f952d11efbfddff01ceacd0a1a98d11b6aaeb5
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 06:27:35 2009 +0000
Correct the comment; this applies to fcmp too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82380 91177308-0d34-0410-b5e6-96231b3b80d8
commit dbcffe8712043251db8648cfa350b2f1e09084e9
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 06:26:34 2009 +0000
Remove tab, again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82379 91177308-0d34-0410-b5e6-96231b3b80d8
commit c9c524ea42f9ed437369879c709b95f24bd3a4e8
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 06:24:51 2009 +0000
Teach the constant folder how to not a cmpinst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82378 91177308-0d34-0410-b5e6-96231b3b80d8
commit e4a6ac9ba8cd5339cb954d9830b1d2a06223355b
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 06:21:43 2009 +0000
smallvectorize getExtraOptionNames
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commit 53f949e7a0b5841e5a497c3015709551729d7874
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 06:21:20 2009 +0000
add a helper method.
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commit 3d211b2bfbab124d05ce785a55bc3af0d067faf2
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 06:18:38 2009 +0000
minor cleanups.
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commit 5b6816d9f3b0fc2e47a458e07d63586aaaf8718f
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 20 06:17:21 2009 +0000
Add 'make check-all', which runs the LLVM tests along with the clang tests if
its in the standard location.
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commit 681869cb3d72675bb06147c36d9fb31fe8f1ad2e
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 20 06:17:12 2009 +0000
Follow googletest logic for suppressing warnings in unittests/UnitTestMain.
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commit 8748d237cb2b4ae277921ccc08e54ad742745a6a
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 05:53:47 2009 +0000
strength reduce further StringRef-> const char*, saving another 620 bytes.
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commit b4f150b44b10efd07b2a88484830602476bd8d7a
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 05:48:50 2009 +0000
Try turning icmp(bitcast(x), bitcast(y)) into icmp(bitcast(bitcast(x)), y) in
the hopes that the two bitcasts will merge.
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commit a81653676cd5fc5e695af54399394225e8d89b79
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 05:48:01 2009 +0000
switch an std::string to StringRef, shaving 400 bytes off CommandLine.o
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commit bd2115c7b222e57eda27fa44dc982fee783c338d
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 05:47:45 2009 +0000
Remove tabs I added.
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commit 0d9aff4829c7463923e2bb17aa34207cca892513
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 05:37:24 2009 +0000
the switch from std::map -> StringMap caused --help output to be in
non-sorted order, restore the sort.
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commit c8240964bf2a87365923de9c21a98f84a29320bd
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 05:22:52 2009 +0000
eliminate the duplicate detection loop, moving it into the loop that populates the Opts vector in the first place.
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commit 34bbc24fd05e08cb98ee66991995363c89fc9bd1
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 05:18:28 2009 +0000
Eliminate a masochistic "algorithm" loop, shrinking CommandLine.o from 71524->70700 bytes.
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commit ab754915527a90d5eb8a702cf656048f3e70d28d
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 05:15:12 2009 +0000
don't use count + insert, just do insert + failure. Also, instead of deleting from
the middle of a vector, swap the last element in and pop_back. Also saves 330 bytes :)
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commit 97be18f541d7a7ddfc824f9318091edca672798f
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 05:12:14 2009 +0000
switch to SmallPtrSet instead of std::set, saving 1K from the
release-asserts .o file (72900->71856).
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commit 78f024be77b8f3ded896be562c20f60aaea019e2
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 05:06:23 2009 +0000
change an std::sort to an array_pod_sort call, shrinking CommandLine.o by 9%.
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commit d516d025a30f0e54aaf4a36bd56cbc992d6888a6
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 05:03:30 2009 +0000
Several changes together in a murky mess:
1. Change some "\n" -> '\n'.
2. eliminte some std::string's by using raw_ostream::indent.
3. move a bunch of code out of the main arg parser routine into
a new static HandlePrefixedOrGroupedOption function.
4. Greatly simplify the implementation of getOptionPred, and make
it avoid splitting prefix options at = when that doesn't match
a non-prefix option.
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commit 4de9f27fca2cc69c8313f1d2dfb06a92623c78b1
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 04:27:06 2009 +0000
Clean up the usage of evaluateICmpRelation's return value.
Add another line to the ConstantExprFold test to demonstrate the GEPs may not
wrap around in either the signed or unsigned senses.
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commit a0a39c32b9db28f69a32be709fdfba69d7d00603
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 20 04:03:41 2009 +0000
Fix refacto, this code was expecting to stride past the argument prefix.
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commit 43e136586bbd27519d726aec7d6b8234117ea3c7
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 20 04:03:34 2009 +0000
Strip trailing whitespace.
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commit 90cc3b72cd886acc682e2a287b5b43638f723e28
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 20 04:03:25 2009 +0000
A few more tabs -> spaces.
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commit 7f7a3db50c589b634e884b5d1b2f426bc49afcd3
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 03:48:46 2009 +0000
Remove dead store by taking a guess at what Chris meant. I wasn't able to
design a testcase that would tickle this behaviour.
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commit 9286265a3ee87750212828f753e362bc4b5ffa56
Author: Bill Wendling <isanbard at gmail.com>
Date: Sun Sep 20 02:27:06 2009 +0000
Still one more thing wrong here...
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commit 3be44e69724c80460d2ef5abab22d802f78615cc
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 20 02:20:51 2009 +0000
Tabs -> spaces, and remove trailing whitespace.
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commit ab2f66670c4c8ecc8e62d989f9d9d9c6f62dc07b
Author: Bill Wendling <isanbard at gmail.com>
Date: Sun Sep 20 02:19:49 2009 +0000
Here's fun! It turns out that these filter functions can be internal. If they're
internal, they shouldn't use the indirect pointer stuff. In the case of
throw_rethrow_test, it was marked as 'internal' and calculated its own offset to
its contents.
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commit 216b5548a9287b2e8e3fd20594c20049ff9248ec
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 02:11:47 2009 +0000
Delete dead code. sext and zext can not turn integers into pointers. Further,
the optimization described in the comment is only valid with target data.
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commit 0a5bcfcc0e41b0ef8933b974d1ec46665c19fcc4
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 02:02:24 2009 +0000
convert argname to StringRef, simplifying LookupOption.
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commit d8168dd1312860814da3181fecb491b4c5500ba1
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 01:53:12 2009 +0000
convert 'Value' to StringRef which makes it easier to
maintain the "null is unspecified, empty is empty" semantics.
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commit 4627c688f7ab3c7951640cc658208826b32c63bd
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 01:49:31 2009 +0000
Change CommaSeparated processing to do it with StringRef instead of temporary std::strings.
This requires StringRef'izing ProvideOption which I also did.
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commit 3c7fc6353a4de5b87d9c22c5714818dfb8f8bf45
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 01:35:59 2009 +0000
Value* were never meant to be const. Removing constness from the constant
folder removes a lot of const_casting and requires no changes to clang or
llvm-gcc.
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commit 17e5709887260f988fe94076ef18d967e0c6ade7
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 01:33:46 2009 +0000
rewrite ParseCStringVector in terms of stringref.
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commit fadd584b7df635545dcd4bb33a3c64adbdad46e0
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 01:22:16 2009 +0000
move a couple non-trivial methods out of line, add new
find_first_of/find_first_of methods.
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commit 2ee921e886c157a1e6206867240c4314b5db5af7
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 01:11:23 2009 +0000
coding style cleanup
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commit 157229d5138579232650753d0514025858b01f8e
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 00:40:49 2009 +0000
convert a bunch more stuff to use StringRef. The ArgName arguments are now
stringref because they may not be nul terminated. For options like -Lfoo
this now avoids a O(n) temporary std::strings where N is the length of
the string after -L.
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commit 2f3b90b1b3b99b963b60b9ed53a67e09c202260f
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 00:38:28 2009 +0000
add size_t and a version of rfind that allows specification of where
to scan from.
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commit 13c4b63b5151f9f9c434341c2ea43f4f34c2243b
Author: Dale Johannesen <dalej at apple.com>
Date: Sun Sep 20 00:36:41 2009 +0000
When computing live intervals for earlyclobber operands,
we pushed the beginning of the interval back 1, so the
interval would overlap with inputs that die. We were
also pushing the end of the interval back 1, though,
which means the earlyclobber didn't overlap with other
output operands. Don't do this. PR 4964.
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commit 747e01e815ec69962736f851866adbe28a27d8c8
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 20 00:07:40 2009 +0000
avoid a bunch of malloc thrashing for PositinoalVals by eliminating
a std::vector and a bunch of std::string temporaries.
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commit 1f40f38b05cb2662351d1a917ecb5f830a0dba83
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 20 00:04:02 2009 +0000
Teach the constant folder how to handle a few simple i1 cases.
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commit 717f77390b5d4bcbddecc414ce46a23abf684c01
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 19 23:59:02 2009 +0000
Avoid some temporary strings.
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commit 60b7363a854bd53c30e474836e3a1e04ac2dc163
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 19 23:58:48 2009 +0000
add some more overloads of StringRef::getAsInteger for
common and useful integer types.
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commit d867fb4396c8affcdb680108b43cb110b7d12db8
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 19 23:57:31 2009 +0000
add a simple c_str() method to SmallString.
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commit a741cb48d356de1e0b27a212385e85fd521755b4
Author: Bill Wendling <isanbard at gmail.com>
Date: Sat Sep 19 22:02:37 2009 +0000
Revert r82274. It's causing failures in the CINT2006 benchmarks.
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commit 5d62cb53f5055c4d43709228c30a2febc6495f48
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 19 20:40:28 2009 +0000
Prefer super class constructor to explicit initialization.
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commit d36c7729ae080ee3721891794d3617080ddaf550
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 19 20:40:21 2009 +0000
Tabs -> spaces (really?)
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commit 19f1d447f73de5807acb64281df5d7acaa23ceeb
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 19 20:40:14 2009 +0000
Fix indentation.
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commit 41716328c597656692f2189f47c7cc56120d2aa5
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 19 20:40:05 2009 +0000
Strip trailing whitespace.
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commit 80b13b31a80b54768abc2da9f00a725209702816
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 19 20:39:50 2009 +0000
RHS of assignment should be const reference.
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commit 9229fdb0d591d22ad962dfb97d98d12ef56b5833
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sat Sep 19 20:30:26 2009 +0000
Remove the default value for ConstantStruct::get's isPacked parameter and
update the code which was broken by this.
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commit b2f35c54ff2c2ef8e03583a0bed0e15bd38426c1
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 19 19:47:14 2009 +0000
provide a "strtoull" operation that works on StringRef's.
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commit 4a5c6fab5776ded60bc45c264f5f22053062678b
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sat Sep 19 19:00:06 2009 +0000
Add a comment explaining why you would ever want to do this.
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commit 47d05cbb759287986bb6223325b987caeda53a6e
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 19 18:55:05 2009 +0000
convert a bunch of std::strings to use StringRef. This should eliminate
a massive number of temporary strings created when parsing a command line.
More still left to eliminate.
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commit 4980177e93ff0c3d02a6fa98a5c91e4b168d6c0c
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sat Sep 19 18:33:36 2009 +0000
Lett users of sparse propagation do their own thing with phi nodes if they want
to. This can be combined with LCSSA or SSI form to store more information on a
PHINode than can be computed by looking at its incoming values.
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commit d899f5970f3e1437cff128a7cf3331a8bcf599b9
Author: Duncan Sands <baldrick at free.fr>
Date: Sat Sep 19 11:25:44 2009 +0000
The flag "--dot-cfg-only" is at the moment equivalent to the flag "--dot-cfg".
It prints the content of all bbs, instead of printing empty bbs to make the
CFG more readable. Fix this. Patch by Tobias Grosser.
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commit bb57eefc4bd33cf3e83b2fb56a6b4fd7f4825bfa
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sat Sep 19 10:09:15 2009 +0000
Fix funky comments.
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commit 4ae44e1230cc009186e73112ff34c4092dd5dafd
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sat Sep 19 10:08:51 2009 +0000
Update comments.
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commit 48086603b0774317c5e35a38627e1c811c09f669
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Sat Sep 19 10:01:45 2009 +0000
Try to speed up the slowest parts of the CommandLine library
- Replace std::map<std::string with StringMap
- Eliminate unnecessary std::string copies
- ~10% speed-up for clang's testsuite on my machine (debug build)
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commit 5f3a54090af5d61d35de2158542ff76fc9ef053f
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sat Sep 19 09:51:03 2009 +0000
Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
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commit 48c3c54ceb1fbdcddac9f11a11163a44efe21f55
Author: Victor Hernandez <vhernandez at apple.com>
Date: Fri Sep 18 22:35:49 2009 +0000
Enhance transform passes so that they apply the same tranforms to malloc calls as to MallocInst.
Reviewed by Dan Gohman.
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commit 627f280adfd69bbf8e859de69b6807ae0c9effce
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 18 22:03:29 2009 +0000
remove an extraneous mem2reg pass early in the pipe. Since
this is run after the 'standard function passes', SRoA was
recently run. This saves a domfrontier construction. Thanks
to Eli for noticing this.
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commit b215f0dab024efb9d46497a28404bcde2638e1a3
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 18 22:01:30 2009 +0000
reduce indentation by using an early exit, and add a comment,
no functionality change.
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commit 1d8662c4dfa69ff87d42037794cf6e6774c2c512
Author: Bob Wilson <bob.wilson at apple.com>
Date: Fri Sep 18 21:43:11 2009 +0000
Fix a comment typo and some whitespace.
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commit 764ce99aff6b5db12d99c31467c9e9b7c5612cf2
Author: Bob Wilson <bob.wilson at apple.com>
Date: Fri Sep 18 21:42:44 2009 +0000
Fix a typo in an assertion message.
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commit 98c415caf6f8e0eac9b9247fb782d6718430e288
Author: Bill Wendling <isanbard at gmail.com>
Date: Fri Sep 18 21:37:56 2009 +0000
Factor out label difference creation.
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commit 82f0ab64c43dcae28ed4f0cb4b8bb69df0b4561d
Author: Victor Hernandez <vhernandez at apple.com>
Date: Fri Sep 18 21:34:51 2009 +0000
Enhance analysis passes so that they apply the same analysis to malloc calls as to MallocInst.
Reviewed by Eli Friedman.
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commit 3c5ec3c11bd3283bfd8bbf7ce12bb81b8d3e3ed0
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 18 21:23:12 2009 +0000
Delete the label names from this test to make it less fragile.
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commit 8c065b334c41ba54d98ad45a6c5b4fdd60c06d2c
Author: Bill Wendling <isanbard at gmail.com>
Date: Fri Sep 18 21:14:36 2009 +0000
It's inefficient to have place the exception tables (which contain the LSDA)
into the __DATA section. At launch time, dyld has to update most of the section
to fix up the type info pointers. It's better to place it into the __TEXT
section and use pc-rel indirect pointer encodings. Similar to the personality
routine.
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commit d7dc983029cf293dd67637c27b92c04c0baf968b
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Sep 18 21:02:19 2009 +0000
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
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commit 8cd2ec566b2bbfa3e07458bc0050af859676fcd4
Author: Shantonu Sen <ssen at apple.com>
Date: Fri Sep 18 20:35:59 2009 +0000
Fix cmake build, which has a different -I that
causes the "../foo" to not find the file
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commit f283fb255f535d56d8cd5f86058ccf2359800e86
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 18 20:22:52 2009 +0000
Make a new X8632_MachoTargetObjectFile TLOF implementation whose
getSymbolForDwarfGlobalReference is smart enough to know that it
needs to register the stub it references with MachineModuleInfoMachO,
so that it gets emitted at the end of the file.
Move stub emission from X86ATTAsmPrinter::doFinalization to the
new X86ATTAsmPrinter::EmitEndOfAsmFile asmprinter hook. The important
thing here is that EmitEndOfAsmFile is called *after* the ehframes are
emitted, so we get all the stubs.
This allows us to remove a gross hack from the asmprinter where it would
"just know" that it needed to output stubs for personality functions.
Now this is all driven from a consistent interface.
The testcase change is just reordering the expected output now that the
stubs come out after the ehframe instead of before.
This also unblocks other changes that Bill wants to make.
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commit b611307c9730ae90448fcacfd8ee9d0d208cc3ee
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 18 20:17:03 2009 +0000
add a new hook to allow targets to splat stuff at the end of the file.
Overriding doFinalization is pretty lame.
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commit 899369d4ad9633b3fcf4aba63dc411ce1988ad75
Author: Dale Johannesen <dalej at apple.com>
Date: Fri Sep 18 20:15:22 2009 +0000
Model the carry bit on ppc32. Without this we could
move a SUBFC (etc.) below the SUBFE (etc.) that consumed
the carry bit. Add missing ADDIC8, noticed along the way.
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commit 12e03298135939c9d40f25f5f762d9522ca352c2
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 18 19:59:53 2009 +0000
Add support for using the FLAGS result of or, xor, and and instructions
on x86, to avoid explicit test instructions. A few existing tests changed
due to arbitrary register allocation differences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82263 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3c8eecdb5aaa4e078ffa0a058219a54dbee98274
Author: Sean Callanan <scallanan at apple.com>
Date: Fri Sep 18 19:35:23 2009 +0000
Added RCL and RCR (rotate left and right with a
carry bit) instructions to the Intel instruction
tables.
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commit adc37616a0ed90c8d25360168e395653b8ad9bd5
Author: Devang Patel <dpatel at apple.com>
Date: Fri Sep 18 19:26:43 2009 +0000
Write and read metadata attachments.
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commit 811ebe0ef3c476c5cbf04d6c2bf362f56a650eec
Author: Victor Hernandez <vhernandez at apple.com>
Date: Fri Sep 18 19:20:02 2009 +0000
Update malloc call creation code (AllocType is now the element type of the malloc, not the resulting type).
In getMallocArraySize(), fix bug in the case that array size is the product of 2 constants.
Extend isArrayMalloc() and getMallocArraySize() to handle case where malloc is used as char array.
Ensure that ArraySize in LowerAllocations::runOnBasicBlock() is correct type.
Extend Instruction::isSafeToSpeculativelyExecute() to handle malloc calls.
Add verification for malloc calls.
Reviewed by Dan Gohman.
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commit 600abb363005c6b5abc9385b35c37720cb2eacbf
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 18 18:34:29 2009 +0000
duncan points out the EH selector values are signed.
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commit 02897795c891a7e250d03153f391851189fb8f5b
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 18 18:31:37 2009 +0000
convert some stuff to StringRef to avoid temporary std::strings.
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commit e5c11a87071a6afaac5df49fb5e552de1d2e5a9a
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 18 18:10:19 2009 +0000
add a comment.
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commit 7e54f154ec3d950827ff8e29f01ca55ae958db0f
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 18 18:08:55 2009 +0000
This file can need access to the X86 instruction enums when the table exceeds 32-bits.
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commit 4dc36eb1b47ec2157748668fb71943f59711c909
Author: Daniel Dunbar <daniel at zuster.org>
Date: Fri Sep 18 17:48:05 2009 +0000
Fix a few more conversion warnings on 4.0
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commit d852f4d69c40e8ad68c4eb43c38e82da068414bf
Author: Mike Stump <mrs at apple.com>
Date: Fri Sep 18 17:10:27 2009 +0000
Update to latest versions of config.guess and config.sub from
http://savannah.gnu.org/projects/config
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commit 3789f872b0ac8f9d22d99696164e04b664af90f6
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Fri Sep 18 16:57:42 2009 +0000
Allow symbols to start from the digit if target requests it. This allows, e.g. pinning
variables to specified absolute address. Make use of this feature for MSP430.
This unbreaks PR4776.
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commit 052e60d59a4f423089f1f088d0e1e7ac61bd5be7
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Fri Sep 18 16:46:16 2009 +0000
Stop using alloca.
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commit 50514c7bab532bd061d9b97bcaf98b5e960653db
Author: Xerxes Ranby <xerxes at zafena.se>
Date: Fri Sep 18 09:50:00 2009 +0000
Revert r82214 completely to fix build.
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commit f3233f2b427e9abfbe1633a91e8e84e7bbb19b43
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Sep 18 08:26:06 2009 +0000
Revert r82214. It broke 403.gcc on x86_64 / Darwin.
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commit ac00d566d4070167ca5aa1cb48f83fa55b1535b9
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Sep 18 08:16:04 2009 +0000
Fix a bug in sdisel switch lowering code. When it updates the phi nodes in switch successor blocks, it can introduce multiple phi operands of the same value from different blocks (and may not be on the predecessor list).
This can be seen on CodeGen/Generic/2006-09-06-SwitchLowering.ll. But it's not known to cause any real regression (but I have added an assertion for it now).
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commit 28c17afa6abed7695d7c148253631920458ee226
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Fri Sep 18 07:36:47 2009 +0000
Add newlines.
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commit ed2ccedb5acf8e5b7f7932aa87f0b188856b894d
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 17 23:56:41 2009 +0000
make this testcase check darwin32 also
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commit f494e5b979e9a6d7f7f6db0d93dc10b4d1caa877
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 17 23:55:12 2009 +0000
rename test
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commit b51aa3322dc54cc149250513132c30574b2e003c
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 17 23:54:54 2009 +0000
tolerate llvm.eh.selector.i64 on 32-bit systems and llvm.eh.selector.i32 on
64-bit systems.
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commit 6c5eea69ce28fd4909f68486bb97ad470e989575
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 17 23:54:26 2009 +0000
convert to filecheck
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commit ec1d9adb02b80de2a1e4219c271ca2cad2362000
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 17 23:42:06 2009 +0000
rename file
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commit 7fbb035781529abc1df7b4e4f6471dd977708e3b
Author: Julien Lerouge <jlerouge at apple.com>
Date: Thu Sep 17 23:27:10 2009 +0000
Use __attribute__((__used__)) if GCC >= 3.1 (seems to be the oldest GCC
supporting this attribute).
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commit 941264e406202121ddb019dffa5e1084819790c3
Author: Devang Patel <dpatel at apple.com>
Date: Thu Sep 17 23:05:07 2009 +0000
A testcase!
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commit 91c792366e0bc38cb14028cd2068b92104f7db51
Author: Devang Patel <dpatel at apple.com>
Date: Thu Sep 17 23:04:48 2009 +0000
Fix parsing of optional metadata for 'load', 'store' and 'alloc' instructions.
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commit c953c1da67f69a4698a7f5379775000e12599134
Author: John McCall <rjmccall at apple.com>
Date: Thu Sep 17 20:35:18 2009 +0000
Fix a few places where PointerIntPair was using PointerLikeTypeTraits<PointerTy>
instead of the PtrTraits provided. Allows PointerIntPair to contain a
PointerUnion safely, as long as the bits add up.
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commit 0ca4b2cefc8cb9260b1467917e630ed7d7d1f6a2
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 17 20:12:05 2009 +0000
Add an svn:ignore.
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commit ee62b0424d8c75617484b2d4a9383565044eb5aa
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 17 18:49:52 2009 +0000
pass machinemoduleinfo down into getSymbolForDwarfGlobalReference,
currently unused.
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commit c20e8bfb90176ee9cd27b027c11a3c8c9c117dd6
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 17 18:05:20 2009 +0000
Teach ScalarEvolution how to reason about no-wrap flags on loops
where the induction variable has a non-unit stride, such as {0,+,2}, and
there are expressions such as {1,+,2} inside the loop formed with
or or add nsw operators.
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commit 47472be0fc842626bbc7103ca8c2d724c213d67e
Author: Jim Grosbach <grosbach at apple.com>
Date: Thu Sep 17 17:57:26 2009 +0000
grammar
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commit 961e43f21b9c3565598054313e7b928b7d0bf656
Author: Jim Grosbach <grosbach at apple.com>
Date: Thu Sep 17 17:55:55 2009 +0000
grammar
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commit dca235bfe8e20482ce3ad2a42dcf5897756314f2
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 17 17:46:53 2009 +0000
Another try at fixing compile warnings on 4.0
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commit a7af40ce842fb14e42581f038d12e76a969121e8
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Thu Sep 17 14:51:57 2009 +0000
Initialize HasMetadata to zero.
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commit 0add5c53c467b953fb803c8c50e450eeb3a42bc9
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 17 06:37:07 2009 +0000
Remove test cases using -regalloc=simple.
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commit b21f415e57b24dbb1a962ddab5fd21ebaebc7d0d
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Sep 17 05:48:07 2009 +0000
Remove simple regalloc. It has bit rotted.
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commit 1581dc7e9c17c8c7e315d70e0b09e8b56b18f520
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 17 01:08:43 2009 +0000
add a version of the APFloat constructor that initializes to 0.0
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commit f7f012381f5d47bb4f8a5a4663311daee8692cbf
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Sep 17 00:57:15 2009 +0000
Fix PR4910: Broken logic in coalescer means when a physical register liveness is being shortened, the sub-registers were not. The symptom is the register allocator could not find a free register for this particular test.
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commit 119fdf6a2815d88d5fdfc5ada6897c96c9f83a0d
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 17 00:14:44 2009 +0000
Some platforms may need malloc.h for alloca.
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commit f955d34bbdbb3377d2e3dc4aa54219b01ba463bc
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 17 00:06:48 2009 +0000
Update CMake.
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commit 23f33d74e817e171decf3915781634cbe9b19a2a
Author: Sean Callanan <scallanan at apple.com>
Date: Wed Sep 16 22:59:28 2009 +0000
Added the LODS (load byte into register, usually
as part string parsing) instructions to the Intel
instruction tables.
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commit d86d635d2831ee15f0e5bafb597d29f0318aaeb4
Author: Daniel Dunbar <daniel at zuster.org>
Date: Wed Sep 16 22:38:48 2009 +0000
Add StringRef::{rfind, rsplit}
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commit 2eddf5d5241b54e02b035b40f16ffa1e5effbe19
Author: Sean Callanan <scallanan at apple.com>
Date: Wed Sep 16 21:55:34 2009 +0000
Added the LAR (load segment access rights)
instructions to the Intel instruction tables.
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commit 503784b9ecdc71df54e3f2b58917b5970c6fcdf5
Author: Sean Callanan <scallanan at apple.com>
Date: Wed Sep 16 21:50:07 2009 +0000
Added the LOOP family of instructions to the Intel
instruction tables.
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commit 11490dcdcd8a798d9d009bfb12a32ab069a0b530
Author: Sean Callanan <scallanan at apple.com>
Date: Wed Sep 16 21:11:23 2009 +0000
Added an alternate form of register-register CMP
to the Intel instruction tables.
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commit 3f7aeddf89537d10eebd50196576e3ec91d066e9
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 16 21:09:07 2009 +0000
Fix typo.
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commit a0fbb00ae6d27128232f1c11550b70bddb6fa76d
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 16 20:39:11 2009 +0000
At iSel time, update DebugLoc based on debug info attached with an instruction.
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commit a653f3541148079687b4c8b95e2dff2e1c91ad77
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 16 20:25:11 2009 +0000
Add a new pass for doing late hoisting of floating-point and vector
constants out of loops. These aren't covered by the regular LICM
pass, because in LLVM IR constants don't require separate
instructions. They're not always covered by the MachineLICM pass
either, because it doesn't know how to unfold folded constant-pool
loads. This is somewhat experimental at this point, and off by
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82076 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1ba76818a6b3281b86c8391cc07aafe821ad45cb
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 16 20:21:17 2009 +0000
Print debug info attached with an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82075 91177308-0d34-0410-b5e6-96231b3b80d8
commit 94ef1628bb9b33484a3887a742fb4cc662b41fd8
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 16 20:20:44 2009 +0000
Expand vector floating-point conversions not supported by NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82074 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1a2d32471a3fdc8f274411142bc8bc22294fa470
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 16 19:18:41 2009 +0000
Now that llc can read .ll files directly, teach it to recognize .ll as
an extension, so that the default output filename for foo.ll is foo.s,
not foo.ll.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82071 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5223bf761d1d6ee0641bf2644e25265e84801926
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 16 18:20:05 2009 +0000
Provide a way to extract location info from DILocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82064 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7464a698dfc9a4b4a42a303e71eb327768288463
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 16 18:18:06 2009 +0000
Parse debug info attached with an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82063 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9514eca3ca9a35a0f5fc01763f6556bec579cc0e
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 16 18:16:11 2009 +0000
Add an interface to attach debugging information with an instruction.
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commit 4b1fad3ca2acec2db8d4c4545b8d5f74a2500b0f
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 16 18:09:00 2009 +0000
Add llvm::Metadata to manage metadata used in a context.
This interface will be used to attach metadata with an instruction.
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commit 86776f75bfef82e33cbd7b9a63c1963b1dd1e7b8
Author: Kevin Enderby <enderby at apple.com>
Date: Wed Sep 16 18:08:00 2009 +0000
Fixed some problems with the logic of parsing line comments by adding
isAtStartOfComment and using that instead in two places where a loop
to check if the char was in MAI.getCommentString().
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commit 01b83cfcffb62aea094d46d17348d592b0259825
Author: Kevin Enderby <enderby at apple.com>
Date: Wed Sep 16 17:18:29 2009 +0000
Fix incorrect assert that should be a user error for code like 'mov $0, %%eax'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82054 91177308-0d34-0410-b5e6-96231b3b80d8
commit 09cf2b6d63c865ade854b6ec1cf62aecf9e9dcb2
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 16 16:50:24 2009 +0000
Change FoldPHIArgBinOpIntoPHI to decline folding if it would introduce two
phis, similar to the FoldPHIArgGEPIntoPHI change.
Also, delete some comments that don't reflect the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82053 91177308-0d34-0410-b5e6-96231b3b80d8
commit 77b713700c3d57b01ec3463dd873f546905a9f3c
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 16 16:33:59 2009 +0000
Fix the comment in this test.
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commit e680e23e781542c39ba1501bee713dd3bf64ad09
Author: Xerxes Ranby <xerxes at zafena.se>
Date: Wed Sep 16 14:36:35 2009 +0000
Make cmake generated llvm-config output correct JIT backend for non X86 targets.
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commit 9ccaf3f7c56c9f3e7e3359165f387895a1cd5ffa
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Wed Sep 16 11:43:12 2009 +0000
Don't sort the vector when it is empty. This should fix some expensive checking
failures.
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commit ec139a0819923967e3c2b8a8e5fafa8859056b8b
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 16 11:35:50 2009 +0000
Reapplied r81355 with the problems fixed.
(See http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090907/086737.html and
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090907/086746.html)
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commit 9f16e4059d7e325248642d3a8051d83bec4c7404
Author: Xerxes Ranby <xerxes at zafena.se>
Date: Wed Sep 16 10:18:36 2009 +0000
updated lib/CodeGen/CMakeLists.txt to unbreak cmake build after r82018
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82038 91177308-0d34-0410-b5e6-96231b3b80d8
commit b072028405dca8e4fab7f655c7622c2578e9353a
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 16 09:26:52 2009 +0000
Preserve ProfileInfo during CodeGenPrepare.
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commit 4117b16b1ef23390d1f1bde4a3f0a1d29250f667
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 06:25:03 2009 +0000
move FnStubs/GVSTubs/HiddenGVStub handling out of the X86 asmprinter
and use MachineModuleInfoMachO instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82022 91177308-0d34-0410-b5e6-96231b3b80d8
commit c3e800a55a04aae2d825fbcf5aed2102a68eaec5
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 06:04:53 2009 +0000
revert a hunk of r82018 that wasn't supposed to go in yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82020 91177308-0d34-0410-b5e6-96231b3b80d8
commit f8a575424917e1f0e6921529c7be86d8825f7778
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 06:03:48 2009 +0000
add a new MachineModuleInfoMachO class, which is the per-module
stuff common across all macho targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82018 91177308-0d34-0410-b5e6-96231b3b80d8
commit 956017391974f44b14d1cb75e824e986841aeea6
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 05:42:12 2009 +0000
apparently russians are really hard to sort or something!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82016 91177308-0d34-0410-b5e6-96231b3b80d8
commit 47d77721c88c70fa8cadbff68df8f2ac1e250e13
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 05:37:13 2009 +0000
I can sort, no really.
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commit 5ee2b3f29d829ac1b99d97d943ffea955d5ee210
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 05:36:54 2009 +0000
make more clear since it is sorted by last name now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82014 91177308-0d34-0410-b5e6-96231b3b80d8
commit 520339201d5c16d1c03d3e129b4cc00cb1f4c1dd
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 05:36:07 2009 +0000
Doug is now the code owner for most of the Clang frontend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82013 91177308-0d34-0410-b5e6-96231b3b80d8
commit 16fcdf9d05d09acde6146d531067fab0bf24f822
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 05:26:00 2009 +0000
the pointer MMI keeps will start out with object-file format specific stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82012 91177308-0d34-0410-b5e6-96231b3b80d8
commit 242f740dcbfc14d95a6eaf5305ca794d28df9a13
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 05:25:43 2009 +0000
tidy up
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commit 4b658b8de70a1feabe23c000212d913d2816c7c0
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 05:20:33 2009 +0000
rearrange X86ATTAsmPrinter::doFinalization, making a scan of
the global variable list only happen for COFF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82010 91177308-0d34-0410-b5e6-96231b3b80d8
commit 0f22f97df2231f18b11b6fe1847dc51a4da98747
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 04:59:30 2009 +0000
Ted is christened as the owner of the clang static analyzer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82008 91177308-0d34-0410-b5e6-96231b3b80d8
commit 500fba8363dccdd3dd29495831e5d689ddc50c49
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 04:57:15 2009 +0000
remove the AsmPrinter::printMCInst hook hack now that
we have MCInstPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82006 91177308-0d34-0410-b5e6-96231b3b80d8
commit d0390a18ad30aa3ed70d39b98ded744755434fde
Author: Shantonu Sen <ssen at apple.com>
Date: Wed Sep 16 04:44:00 2009 +0000
fix cmake build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81999 91177308-0d34-0410-b5e6-96231b3b80d8
commit 253e466f7a96658151b4c89c871386ec401311a0
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 04:12:47 2009 +0000
use an accessor to simplify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81997 91177308-0d34-0410-b5e6-96231b3b80d8
commit 63715c73c20ed0358d5774bb481c9437fd234f54
Author: Nate Begeman <natebegeman at mac.com>
Date: Wed Sep 16 03:20:46 2009 +0000
Do not try and sink a load whose chain result has more than one use, when
trying to create RMW opportunities in the x86 backend. This can cause a
cycle to appear in the graph, since the other uses may eventually feed into
the TokenFactor we are sinking the load below.
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commit 51b7a9968562cad4c543634dcf5b3e3ec1340611
Author: Sean Callanan <scallanan at apple.com>
Date: Wed Sep 16 02:57:13 2009 +0000
Added the ENTER instruction, which sets up a stack
frame, to the Intel instruction tables.
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commit ca503e043f3871c7dd5254613b505f0f0e36c361
Author: Sean Callanan <scallanan at apple.com>
Date: Wed Sep 16 02:28:43 2009 +0000
Added the definitions for one-bit left shifts to
the Intel instruction tables.
The patterns will stay blank because ADD reg, reg
is faster, but having the encoding available is
useful for the disassembler.
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commit 37a534b8dca3f6890042845b8ebb50d47ffc2c08
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 16 02:01:52 2009 +0000
Don't sink gep operators through phi nodes if the result would require
more than one phi, since that leads to higher register pressure on
entry to the phi. This is especially problematic when the phi is in
a loop header, as it increases register pressure throughout the loop.
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commit 1d64b2874ad916274fb18db31b1d898d58cb8076
Author: Sean Callanan <scallanan at apple.com>
Date: Wed Sep 16 01:54:38 2009 +0000
Removed a few instructions that were already
covered by other definitions.
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commit 8886dc29cd311a78fd1f672904fd9a3af51c883c
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 01:46:41 2009 +0000
Big change #1 for personality function references:
Eliminate the PersonalityPrefix/Suffix & NeedsIndirectEncoding
fields from MAI: they aren't part of the asm syntax, they are
related to the structure of the object file.
To replace their functionality, add a new
TLOF::getSymbolForDwarfGlobalReference method which asks targets
to decide how to reference a global from EH in a pc-relative way.
The default implementation just returns the symbol. The default
darwin implementation references the symbol through an indirect
$non_lazy_ptr stub. The bizarro x86-64 darwin specialization
handles the weird "foo at GOTPCREL+4" hack.
DwarfException.cpp now uses this to emit the reference to the
symbol in the right way, and this also eliminates another
horrible hack from DwarfException.cpp:
- if (strcmp(MAI->getPersonalitySuffix(), "+4 at GOTPCREL"))
- O << "-" << MAI->getPCSymbol();
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81991 91177308-0d34-0410-b5e6-96231b3b80d8
commit 73944d4e73d42ea7fcc2a3408c814a13c20c9b29
Author: Daniel Dunbar <daniel at zuster.org>
Date: Wed Sep 16 01:34:52 2009 +0000
lit: Add a custom test format for use in clang.
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commit d0da556cc3eeeac05071458f1544ef7ee05b5b65
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 01:29:11 2009 +0000
remove a dead variable.
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commit af90e3e1f69396d48d549d968e969d1d181ee4b9
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 01:26:31 2009 +0000
add a helper method for creating MCSymbol and MCSymbolRefExpr at
the same time.
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commit 3d5824cc4efb252b69c86e871e4835ece6e16975
Author: Sean Callanan <scallanan at apple.com>
Date: Wed Sep 16 01:13:52 2009 +0000
Added a variety of floating-point and SSE instructions.
All of these do not have patterns (they're for the
disassembler).
Many of the floating-point instructions will probably
be rolled into definitions that have patterns, and may
eventually be superseded by mdefs. So I put them
together and left a comment.
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commit 57c76b5eea6a1b4202941a0c3e7d06f0a00c8485
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 00:35:39 2009 +0000
inline AsmPrinter::getCurrentFunctionEHName into its only caller.
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commit 71dd44de32bd74e60887991c9f06ab3917229a52
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 16 00:32:15 2009 +0000
Expand some more vector operations not supported by Neon.
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commit e25bbf679b89aa172316ec349b4a541db246fde1
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 00:24:31 2009 +0000
remove a dead bool.
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commit c54a0890ddc80c1d7efa21695fb3159ef1b57cf8
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 00:17:39 2009 +0000
Eliminate AsmPrinter::EmitExternalGlobal, inlining its (now)
one implementation into its one caller. This eliminates a totally
awesome and gratuitous hack where we casted a Function* to
GlobalVariable*.
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commit 098abb4f0f560ae8e2c2e649f7e16046740f3cda
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 16 00:17:28 2009 +0000
Neon does not support vector divide or remainder. Expand them.
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commit 8c7099069742b1fda9b8c3c7d513e67e566c6dbb
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 00:14:19 2009 +0000
eliminate the PPC backend's implementation of EmitExternalGlobal
and use PersonalityPrefix/Suffix to achieve the same effect (like
the x86 backend).
This changes the code generated for ppc static mode, but guess what,
we were generating this before:
.byte 0x9B ; Personality (indirect pcrel sdata4)
.long ___gxx_personality_v0-. ; Personality
which is not correct! (it is not an 'indirect' reference).
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commit 5632fabd0a6e1f30e9cbbd6c2b6d3dce6dcc656a
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 00:08:41 2009 +0000
eliminate the horrid AsmPrinter::getGlobalLinkName method, inlining
it into all of its call sites and simplifying them.
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commit fe0e2534a5b2b89019a3d0ed2b55b0acb5ae4498
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 16 00:08:07 2009 +0000
simplify some code
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commit e8fefa0a3f88ebd6f5e24617ca5d5fe7c4734ef9
Author: Bob Wilson <bob.wilson at apple.com>
Date: Tue Sep 15 23:55:57 2009 +0000
Expand all v2f64 arithmetic operations for Neon.
Radar 7200803. (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)
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commit dbaf51315fa3a150fca8aeed3e2b146d48749c9f
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 15 23:40:07 2009 +0000
Put back non-obsolete -f sections for 'opt'.
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commit 7a01257a044b62d94b6a049eb0d682ad35015ba3
Author: Sean Callanan <scallanan at apple.com>
Date: Tue Sep 15 23:37:51 2009 +0000
Added far return instructions (that is, returns to
code in other segments) to the Intel instruction
tables.
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commit 36d0329a368bc31e7129c92b2e1c38559793a48d
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 23:11:32 2009 +0000
remove some horrible MAI hooks which fortunately turn out to be always empty.
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commit 451e8e6330161627a231f22d167d49dd0c374db8
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 22:58:35 2009 +0000
strength reduce a call to PrintRelDirective(true).
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commit 72ba67246b322935e03e118480c6b8c235669b35
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 22:44:26 2009 +0000
add hooks to hang target-specific goop off MachineModuleInfo,
move MachineFunctionInfo virtual method out of line to give it
a home.
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commit 4c9a0d70e34e1cc679f71bc5ca8e9554255b18d6
Author: Nate Begeman <natebegeman at mac.com>
Date: Tue Sep 15 22:30:11 2009 +0000
Do not add the SVOffset to the Node CSE ID. The same pointer argument cannot have different
SVOffsets.
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commit 1482ed20fd413149c26101b5e3741e6ffe7ecf4e
Author: Eric Christopher <echristo at apple.com>
Date: Tue Sep 15 21:56:46 2009 +0000
Expand on comment.
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commit 84df931976ddcf564c582d7385ec8ba305478ed7
Author: Sean Callanan <scallanan at apple.com>
Date: Tue Sep 15 21:43:27 2009 +0000
Updated comments per Eli's suggestion.
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commit 3941cf7d66ec881570c0025013a9d70bcbfd1110
Author: Bob Wilson <bob.wilson at apple.com>
Date: Tue Sep 15 20:58:02 2009 +0000
Convert more tests to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81915 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7e7df0ef9db04445ae99dd1257213132b00d7010
Author: Sean Callanan <scallanan at apple.com>
Date: Tue Sep 15 20:53:57 2009 +0000
Added register-to-register ADD instructions to the
Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.
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commit 48f5114de937c031d43c91691806b04f55d35e2b
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 15 20:31:46 2009 +0000
Drop the raw_ostream required buffer size to 1.
- As best I can tell, we have eliminated all the code which used to require a
larger buffer size.
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commit 6dee039bc647d7ac37a135272648af92dec812e1
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 15 20:31:35 2009 +0000
Remove references to obsolete -f option.
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commit 0a2e0dfe5ec8c5fd8f15bb1f085d635708a7203c
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 15 20:31:28 2009 +0000
Update llc/opt PODs to clarify they support .ll input.
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commit ef65e0c69530a1832ba84028c8a25096b41e5f04
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 15 20:31:12 2009 +0000
Fix -Asserts warning.
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commit 91304e2755539fa6e746731028f25083ab09722f
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 15 20:09:17 2009 +0000
lit: When finding nested test suites, check first in the execpath in case there
is a site configuration.
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commit 2494777a2cb2e6e78713b12c0658523856b44ecb
Author: Nate Begeman <natebegeman at mac.com>
Date: Tue Sep 15 19:05:41 2009 +0000
Better solution for tracking both the original alignment of the access, and the current alignment based
on the source value offset. This avoids increasing the size of mem nodes.
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commit fb75cc9708004e58a40d63b3061b22b44a1c84b2
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 15 18:56:13 2009 +0000
Correct comment pasto
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commit ad87a3af74f9e84f1092e2a97ce28a98deb77437
Author: Sean Callanan <scallanan at apple.com>
Date: Tue Sep 15 18:47:29 2009 +0000
Added a new register class for segment registers
to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.
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commit 5bf764bd78d33c4a1e1e0fc2dfdc72044ee70030
Author: Dale Johannesen <dalej at apple.com>
Date: Tue Sep 15 18:32:14 2009 +0000
Change the marker byte for stubs from 0xcd to 0xce (another form of
interrupt instruction, which shouldn't arise any other way). 0xcd is
also used by JITMemoryManager to initialize the buffer to garbage,
which means it could appear following a noreturn call even when
that is not a stub, confusing X86CompilationCallback2. PR 4929.
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commit d32037b8c08567c1b4e544cec0b3962f9172ae54
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 18:27:02 2009 +0000
fix PR4984 by ensuring that fastisel adds properly sign extended GEP displacement
values to machineinstrs.
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commit fae4dc746dee18665ac310518148c503373eadd4
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 18:23:37 2009 +0000
rename test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81884 91177308-0d34-0410-b5e6-96231b3b80d8
commit e22ad00d2c41cf95d58c05978b106cadd08d0fcc
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 18:23:23 2009 +0000
convert to filecheck
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commit 29af822131334c1b2507844c4807ba7852390fb0
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 18:03:13 2009 +0000
add missing file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81881 91177308-0d34-0410-b5e6-96231b3b80d8
commit 19f0725ebd200ab818b0431a64943eebf61c794d
Author: Bob Wilson <bob.wilson at apple.com>
Date: Tue Sep 15 17:56:18 2009 +0000
Handle AddrMode4 for Thumb2 in rewriteT2FrameIndex. This occurs for
VLDM/VSTM instructions, and without this check, the code assumes that an
offset is allowed, as it would be with VLDR/VSTR. The asm printer,
however, silently drops the offset, producing incorrect code. Since the
address register in this case is either the stack or frame pointer, the
spill location ends up conflicting with some other stack slot or with
outgoing arguments on the stack.
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commit fe9c3803a79895c50881154a3a381f61692e13ae
Author: Sandeep Patel <deeppatel1987 at gmail.com>
Date: Tue Sep 15 17:53:11 2009 +0000
Fix superreg use in ARMAsmPrinter. Approved by Anton Korobeynikov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81878 91177308-0d34-0410-b5e6-96231b3b80d8
commit 49102def1108f7c206537893c0ad47d359d00883
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 17:46:24 2009 +0000
several major improvements to the sparc backend: support for weak linkage
and PIC codegen. Patch by Venkatraman Govindaraju!
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commit 03dd9bb9a759b3cc6c658910a3923f8fb869e2fd
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 15 16:14:44 2009 +0000
Teach ValueTracking how to look through GlobalAliases. GlobalAliases are
not folded in the constant folder because the constant folder doesn't
simplify ConstantExpr operands.
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commit 2b1760f8c98ea4893ee8a9a97c351adf9a377219
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 15 16:00:30 2009 +0000
Fix an accidental inversion of the inbounds flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81862 91177308-0d34-0410-b5e6-96231b3b80d8
commit 72444efbd46645993821a5167411656371e995b1
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 15 15:58:07 2009 +0000
When a constant's type is refined, update the constant in place
instead of cloning and RAUWing it.
- Make AbstractTypeUser a friend of Value so that it can offer
its subclasses a way to update a Value's type in place. This
is better than a universally visible setType method on Value,
and it's sufficient for the immediate need.
- Eliminate the constant "convert" functions. This eliminates a
lot of logic duplication, and fixes a complicated bug where a
constant can't actually be cloned during the type refinement
process because some of the types that its folder needs are
half-destroyed, being in the middle of refinement themselves.
- Move the getValType functions from being static overloaded
functions in Constants.cpp to be members of class template
specializations in ConstantsContext.h. This means that the
code ends up getting instantiated twice, however it also
makes it possible to eliminate all "convert" functions, so
it's not a big net code size increase. And if desired, the
duplicate instantiations could be eliminated with some
reorganization.
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commit 0682a468f8ced6a32d618480ce6ee3367cfaecc4
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 15 15:38:31 2009 +0000
Use llvm-link -S instead of using llvm-dis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81860 91177308-0d34-0410-b5e6-96231b3b80d8
commit d5939a47767d82e5d4d108c258b7f2320e30bc81
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 15 15:35:07 2009 +0000
Give llvm-link a -S option.
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commit 97b59da0a82c96d077a36f4e4a4417529d0e060c
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 15 15:33:42 2009 +0000
Don't bother using a PassManager just to print a Module.
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commit 43dcc4032dde26fad0276e724095b3f37853c6da
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 15 15:09:54 2009 +0000
Restore a comment that was lost in the merge.
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commit 95bb35e9ba16fcbff3d32a0e32d43f876203d172
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 15 15:08:33 2009 +0000
Fix apostrophos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81856 91177308-0d34-0410-b5e6-96231b3b80d8
commit 93a8e411672c28483ba69f42ad33746adedb7195
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Tue Sep 15 07:08:25 2009 +0000
Add more newlines to make up for the ones removed from the end of instructions.
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commit 527a06706f7a5582eb5ef4dbe1bd2cb2b893f5a0
Author: Evan Cheng <evan.cheng at apple.com>
Date: Tue Sep 15 07:05:12 2009 +0000
Forgot this.
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commit 6a48b00dc985aaf83b11bf1c6b31ccd4ba49ede6
Author: Evan Cheng <evan.cheng at apple.com>
Date: Tue Sep 15 06:45:16 2009 +0000
Another try at early partial coalescing. Identity phi source copies (their sources are defined by phi join def) are coalesced. And the phi join copy is backward copy propagated into the other copies.
Still miscompiling some tests. :-(
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commit 9983d964324ffc3bba0d3dd128453d7e49af3c3d
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 06:34:29 2009 +0000
convert to filecheck
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commit b1208609ee4d18b2c0adaf860b72d0b2d5fd43d4
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Tue Sep 15 06:28:26 2009 +0000
Forbid arrays of function-type and structures with function-typed fields.
While I'm there, change code that does:
SomeTy == Type::getFooType(Context)
into:
SomeTy->getTypeID() == FooTyID
to decrease the amount of useless type creation which may involve locking, etc.
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commit f0ecef80afbd600d9004952bce40b55da78b4a78
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 06:28:12 2009 +0000
fix PR4963: folding insertvalue would sometimes turn a packed struct into
an unpacked one.
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commit 69177fbaef43d051fcc9a84184b2884f41765c6b
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 05:40:35 2009 +0000
add a new CallGraphNode::replaceCallEdge method and use it from
argpromote to avoid invalidating an iterator. This fixes PR4977.
All clang tests now pass with expensive checking (on my system
at least).
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commit 5957ef5d5226035be8d48b37260bcef1b171a288
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 05:14:57 2009 +0000
add newline to debug dump
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commit a6001e21c43647daff2d81359cb3e9e8c0f0843e
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 05:03:04 2009 +0000
make -debug-pass=Executions show information about what call graph nodes
are in the SCC for each execution of a CGSCC pass.
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commit 8e3ba7439fb15df005a3125b0b9b6f51ea2697c9
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 04:45:26 2009 +0000
add some missing quotes in debug output
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commit d2d16acc4549ed7c075425a1337cc2a3b953f52c
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 04:37:49 2009 +0000
switch scciterator to use DenseMap instead of std::map
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commit 47fbf883bdac3403a5584be5ec476f11f083fa7f
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 04:27:29 2009 +0000
this is failing on linux hosts, force a triple.
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commit a045a696be25f2dec8969a68283582b33d660aae
Author: Ted Kremenek <kremenek at apple.com>
Date: Tue Sep 15 04:06:36 2009 +0000
Remove invalid add_dependencies line to unbreak the CMake build.
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commit 5083953c49cfb42b74a512d6b876340cdb958733
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Tue Sep 15 03:39:45 2009 +0000
Get rid of GetProcessId in Win32/Program.inc.
GetProcessId was introduced only in XP. As a bonus, this change makes Program
objects copyable, since Program is now basically a PID.
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commit 4f21ba08e546e678bd6cc4c6efd66040507d8050
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 02:27:23 2009 +0000
merge one more in.
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commit dd42dc82ecfb2d3ec5a138e3dbf7c5249dac3b7d
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 02:25:21 2009 +0000
merge some more cmov tests into cmov.ll
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commit e8e2cc606cea71cfc40728aae2906ac85b4d2c7d
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 15 02:22:47 2009 +0000
merge two cmov tests into one.
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commit cbe5a493d522295f64e80d1dafd99360ebec7a99
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 15 01:22:01 2009 +0000
Don't pull a load through a callseq_start if the load's chain
has multiple uses, as one of the other uses may be on a path
to a different node above the callseq_start, because that
leads to a cyclic graph. This problem is exposed when
-combiner-global-alias-analysis is used. This fixes PR4880.
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commit 6647b934fcb19a24d6eb7a07750ce292d79205c3
Author: Nate Begeman <natebegeman at mac.com>
Date: Tue Sep 15 00:38:09 2009 +0000
Remove incorrect CSE code from r81813.
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commit b7e7339c1e4bac5679c7a2e3b46f15d1460882c4
Author: Sean Callanan <scallanan at apple.com>
Date: Tue Sep 15 00:35:17 2009 +0000
Modified the Intel instruction tables to include
versions of CALL and JMP with segmented addresses
provided in-line, as pairs of immediates.
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commit 3d711a3d76b29a8b13ec316c81d0161df47818ce
Author: Kevin Enderby <enderby at apple.com>
Date: Tue Sep 15 00:27:25 2009 +0000
Added the first bits of the ARM target assembler to llvm-mc. For now it only
parses the .word directive as 4 bytes and ARMAsmParser::ParseInstruction will
give an error is called. Broke out the test of the .word directive into two
different test cases, one for x86 and one for arm.
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commit 722f41892d746e32e0456a8e90640be7b93b4175
Author: Nate Begeman <natebegeman at mac.com>
Date: Tue Sep 15 00:18:30 2009 +0000
Substantially speed up combiner-aa in the following ways:
1. Switch from an std::set to a SmallPtrSet for visited chain nodes.
2. Do not force the recursive flattening of token factor nodes, regardless of
use count.
3. Immediately process newly created TokenFactor nodes.
Also, improve combiner-aa by teaching it that loads to non-overlapping offsets
of relatively aligned objects cannot alias.
These changes result in a >5x speedup for combiner-aa on most testcases.
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commit 9e1b9b6fc8c9553b28a676fda614db3d057aa368
Author: Nate Begeman <natebegeman at mac.com>
Date: Tue Sep 15 00:14:28 2009 +0000
Teach the legalizer to propagate the original alignment of loads and store when
it splits them.
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commit 5d38ee448663aae93e51b96d0fab617e191e6a80
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 15 00:14:11 2009 +0000
On x86-64, the 32-bit cmov doesn't actually clear the high 32-bit of
its result if the condition is false.
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commit e22356dcb8d97062576619c5419a1140c76059dd
Author: Nate Begeman <natebegeman at mac.com>
Date: Tue Sep 15 00:13:12 2009 +0000
Add an "original alignment" field to load and store nodes. This enables the
DAG Combiner to disambiguate chains for loads and stores of types which are
broken up by the Legalizer into smaller pieces.
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commit a5e04816bd3e055c1ac97cc22a2035883ec763c6
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 14 23:39:10 2009 +0000
When extending a memset range past the front, set the alignment of the
memset region to the alignment of the new start address.
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commit 713985a2dff2024cc0544f497714e239a01a6251
Author: Erick Tryzelaar <idadesub at users.sourceforge.net>
Date: Mon Sep 14 21:54:32 2009 +0000
Expose initializing the native target for the execution engine.
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commit f161b718f66f519f5fd348ec4619a1d928f25809
Author: Erick Tryzelaar <idadesub at users.sourceforge.net>
Date: Mon Sep 14 21:54:15 2009 +0000
Make sure to initialize the fpm in the ocaml tutorial.
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commit 95320818705e1a8a2ec6e0eaf009695c7b36630e
Author: Evan Cheng <evan.cheng at apple.com>
Date: Mon Sep 14 21:33:42 2009 +0000
Add early coalescing to liveintervals. This is work in progress and is known to miscompute some tests. Read it at your own rish, I have aged 10 year while writing this.
The gist of this is if source of some of the copies that feed into a phi join is defined by the phi join, we'd like to eliminate them. However, if any of the non-identity source overlaps the live interval of the phi join then the coalescer won't be able to coalesce them. The early coalescer's job is to eliminate the identity copies by partially-coalescing the two live intervals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81796 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3380dd66fb6f3cedf9fe83f56c8680802bfaf4cb
Author: Bill Wendling <isanbard at gmail.com>
Date: Mon Sep 14 20:52:37 2009 +0000
Pull the creation of the "RewindFunction" function out of the loop. It's only
created once, so shouldn't be stuck in the middle of the loop. Also early exit
if there are no uses of UnwindInst in the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81785 91177308-0d34-0410-b5e6-96231b3b80d8
commit 35d089b52ad103aedfe249070244d6bdf0ed7039
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 14 20:40:10 2009 +0000
Update a comment to match the source. PseudoSourceValues are now
obtained via accessor functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81782 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3107c9ecfee9c403e89e3d5eccbc00d1099fc151
Author: Jim Grosbach <grosbach at apple.com>
Date: Mon Sep 14 17:27:35 2009 +0000
trivial whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81773 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9105aa9a9dc9f159335af3ff23b9f1f13f208069
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 14 16:49:26 2009 +0000
add PR#
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81770 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9ab1d2e843fe3ce1ed9f135335e9ba92f72912b6
Author: Eric Christopher <echristo at apple.com>
Date: Mon Sep 14 16:38:49 2009 +0000
Enable the jit for llvm-config.
Patch by Xerxes Rånby!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81768 91177308-0d34-0410-b5e6-96231b3b80d8
commit c662a414b78029f6716f128ae926333a77aaecd3
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 14 16:10:32 2009 +0000
Add a valgrind suppressions file for x86_64/linux/4.3.3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81766 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9dbc0054b4e16f3d94c8009b5d510c3753ed7ca2
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 14 15:27:43 2009 +0000
Add a VALGRIND_EXTRA_ARGS makefile variable, with the obvious semantics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81764 91177308-0d34-0410-b5e6-96231b3b80d8
commit 6c3b4e242e24ed183d4561ce5a8222b441893698
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 14 05:22:54 2009 +0000
Update CMake dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81758 91177308-0d34-0410-b5e6-96231b3b80d8
commit a303520a98b34359e350878fa54c91d314fc0dac
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 14 05:22:47 2009 +0000
Update CMake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81757 91177308-0d34-0410-b5e6-96231b3b80d8
commit da5fb6d704adbe833dcf16d12398a87a5af8d01e
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 14 03:15:54 2009 +0000
PIC16 does allow colon after MBB labels, simplify EmitBasicBlockStart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81755 91177308-0d34-0410-b5e6-96231b3b80d8
commit a835afd084f0e1c9ce65902b24eac79921547c79
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 14 03:02:37 2009 +0000
Change MCAsmStreamer to take an MCInstPrinter instead of a
full AsmPrinter, and change TargetRegistry to keep track
of registered MCInstPrinters.
llvm-mc is still linking in the entire
target foo to get the code emitter stuff, but this is an
important step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81754 91177308-0d34-0410-b5e6-96231b3b80d8
commit c2eadb171aaa638fa18a7f8ddcb4e9bc22a0fad8
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 14 02:39:01 2009 +0000
Teach 'make check-lit' to run unittests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81753 91177308-0d34-0410-b5e6-96231b3b80d8
commit e4fe594178a8ee98db0588bfb06d50916cdebc21
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 14 02:38:53 2009 +0000
Attempt to fix some 4.0.0 build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81752 91177308-0d34-0410-b5e6-96231b3b80d8
commit 160f351b7f90ebedb6ef137ea020989769963b98
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 14 02:38:46 2009 +0000
lit: Give test formats control over test discovery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81751 91177308-0d34-0410-b5e6-96231b3b80d8
commit ffe6f6bed8d8b1a5e56088fd13b1f05f68c28051
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Mon Sep 14 02:25:34 2009 +0000
Fix a pair of comment typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81750 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5aab63425cb839d86e7ab908d5fc68f27c3b3b3d
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Mon Sep 14 02:25:19 2009 +0000
Fifth time's a charm! Remove ourselves as abstract type listeners once we've
been told that the type is no longer abstract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81749 91177308-0d34-0410-b5e6-96231b3b80d8
commit e6eb694f39d6edf0cfa3be954776f13d2e959a13
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 14 01:49:26 2009 +0000
Give MCInstPrinter a MCAsmInfo member, make X86ATTInstPrinter
be a MCInstPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81746 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3698084edee8995c957027958dd61a0d27e79849
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 14 01:43:38 2009 +0000
add a new MCInstPrinter class, move the (trivial) MCDisassmbler ctor inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81745 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5ec814dc4fd6e24fdbec8d092d4e9ba0c21d6dac
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 14 01:34:40 2009 +0000
tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81744 91177308-0d34-0410-b5e6-96231b3b80d8
commit c3f01e21df1740df29a8fbf30f16dca9bae44711
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 14 01:27:50 2009 +0000
slightly increase prettiness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81742 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9ccbf08d37a60fb1d5f288ce4043f3f66d0822ed
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 14 01:26:18 2009 +0000
emit the register table as a massive string to avoid relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81741 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7437911091faa98a519d2fbb16fd13e207708be1
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 14 01:19:16 2009 +0000
move StringToOffsetTable out to its own header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81740 91177308-0d34-0410-b5e6-96231b3b80d8
commit 07cb8119f076f45883139ccc1d4a9c283e69966e
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 14 01:16:36 2009 +0000
factor string table generation out to its own class. This changes
the encoding of the AsmStrs table saving a byte or two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81739 91177308-0d34-0410-b5e6-96231b3b80d8
commit b6db52a9bdf56bb5b0ae38cbf3b37a35102144ff
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Mon Sep 14 00:36:52 2009 +0000
Don't leak! Always remove oneself as a listener after adding oneself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81736 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3f0d71da30b9523150a0287745e609d3b481be01
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 13 23:45:39 2009 +0000
Actually remove old types from the set.
Also break the type verification stuff into its own TypeSet to keep the
Verifier pass from becoming an AbstractTypeUser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81729 91177308-0d34-0410-b5e6-96231b3b80d8
commit 826ed7a271c9a966d58a379acdf492fa40c5ffb0
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 22:45:04 2009 +0000
eliminate the TargetRegisterDesc::AsmName field, the asmprinters now have this table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81728 91177308-0d34-0410-b5e6-96231b3b80d8
commit 00512f63d4d10e60ae18c8b46392ce49e663f0bd
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 22:42:03 2009 +0000
kill off the last use of TRI::AsmName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81727 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1063d2402ec84d31cf67eaae00cda4822ba35b56
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 22:41:48 2009 +0000
add some special case handling for strangely named x86 registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81726 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4f1c655d38daf554042502391aac0b873d6d4d75
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 22:39:27 2009 +0000
Build (not test) the unittests as part of a normal build.
- 'make unittests' still builds and tests.
- 'make unitcheck' inside a unittest directory runs the tests in that directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81725 91177308-0d34-0410-b5e6-96231b3b80d8
commit 84c0c9a5d338d233548b6f4bc8a81dcd47744be5
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 22:28:17 2009 +0000
unbreak this test by working around an asmparser bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81724 91177308-0d34-0410-b5e6-96231b3b80d8
commit 98544f744488e29f215a07888500ec59e9fb490a
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 22:24:34 2009 +0000
'printMCInst' doesn't print newlines after instructions anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81723 91177308-0d34-0410-b5e6-96231b3b80d8
commit 453222b9fee0a048540a832ecab293dff2751c9c
Author: Oscar Fuentes <ofv at wanadoo.es>
Date: Sun Sep 13 22:18:38 2009 +0000
CMake: New user-settable variable LLVM_TARGET_ARCH useful when
cross-compiling.
Patch by Xerxes Rånby!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81722 91177308-0d34-0410-b5e6-96231b3b80d8
commit 6d2eab68c04d4b93330a22469a650f7fdaadfbb2
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 13 21:38:54 2009 +0000
Update the tutorial to match changes to examples/Kaleidoscope.
One change I'm not folding in is the removal of two unused variables that
caused warnings, because those were there for expository purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81721 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7909eefe08511c595d7dc8b586abec9c65f2e1f8
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 21:31:21 2009 +0000
Move unittest driver to utils/unittest/UnitTestMain.
- This eliminates a race between building the unittests and linking the
UnitTestMain library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81719 91177308-0d34-0410-b5e6-96231b3b80d8
commit 435de3991f951fdaf77395572f740b7483662a91
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 21:31:07 2009 +0000
Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81718 91177308-0d34-0410-b5e6-96231b3b80d8
commit c904d5b8a23fc2ac8181b0e261f0f3292f379721
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sun Sep 13 21:07:59 2009 +0000
Storing a set of PATypeHolders is a bad idea because their sort order will
change as types are refined. Remove abstract types from CheckedTypes when they
we're informed that they have been refined. The only way types get refined in
the verifier is when later function passes start optimizing. Fixes PR4970.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81716 91177308-0d34-0410-b5e6-96231b3b80d8
commit f0a25de172e71282bba275a51ce75849e5407f8b
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 20:31:40 2009 +0000
remove all but one reference to TargetRegisterDesc::AsmName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81714 91177308-0d34-0410-b5e6-96231b3b80d8
commit 213703ced9eeaa585c06387ae3c643ea4701462e
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 20:19:22 2009 +0000
the tblgen produced 'getRegisterName' method does not access
the object, make it static instead of const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81711 91177308-0d34-0410-b5e6-96231b3b80d8
commit ec219616d65bf4057d0c4509708b31f7979f7ad6
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 20:15:16 2009 +0000
switch the x86 asmprinters to use getRegisterName instead
of getting it from TRI, inst printing now is codegen context
free!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81710 91177308-0d34-0410-b5e6-96231b3b80d8
commit 0288aeed1baf069135de8bc028e1c82efae7316e
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Sun Sep 13 20:14:57 2009 +0000
Fix a small issue with recent changes to this code.
The 'false.c' file wasn't being used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81709 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9222169c3ad7e619d1a8ab155b7a1118182c3c34
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 20:08:00 2009 +0000
make tblgen produce a function that returns the name for a physreg.
Nothing is using this info yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81707 91177308-0d34-0410-b5e6-96231b3b80d8
commit 28f7e3506ee1779753939d87c2ce4e1a2f19e9c0
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 19:48:37 2009 +0000
eliminate an extraneous use of TRI::getAsmName in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81705 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4957efed4f96e7af2efbcba4f5a6b3a6f255c795
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 19:44:38 2009 +0000
make intel asmprinter use TRI::getAsmName instead of TRI::getName like
all the other targets. Add support for weak/linkonce linkage so it doesn't
crash on basically all nontrivial testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81704 91177308-0d34-0410-b5e6-96231b3b80d8
commit 59a6e61b92fa4a02cd9a68b5b6e4e63dee2ff524
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 19:30:11 2009 +0000
split MCInst printing out of the X86ATTInstPrinter
class into its own X86ATTInstPrinter class. The inst
printer now has just one dependence on the code generator
(TRI).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81703 91177308-0d34-0410-b5e6-96231b3b80d8
commit b1c1268be8e349ed9ed5e8012fced58b60da23e2
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 19:10:08 2009 +0000
reduce indentation with early exit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81699 91177308-0d34-0410-b5e6-96231b3b80d8
commit 6f9b24922a442ab59668c859697e2f1b501eb46f
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 19:03:08 2009 +0000
second part to r81695, I missed a directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81696 91177308-0d34-0410-b5e6-96231b3b80d8
commit 149495f84e67c353295dd54c4ca92ccd0fd3c1ef
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 19:02:16 2009 +0000
remove MAI::JumpTableSpecialLabelPrefix now that MAI
has real information about linker private linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81695 91177308-0d34-0410-b5e6-96231b3b80d8
commit 893e8843309b5ca688046b1d11bc7f71eb5fc2a8
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 18:58:14 2009 +0000
Revert unittests build changes temporarily, the unit test build isn't -j safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81692 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7e659812c8d34377bc4d9516f1a116ccec4f073f
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 18:50:22 2009 +0000
delete the fixme too! :)
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commit e82fd5e49c2bcf148abe7b8e066076020944505c
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 18:46:37 2009 +0000
merge the linux cpool/jtbl pic tests into pic.ll and convert to filecheck.
Change the picbase symbol on non-darwin systems from ".Lllvm$4.$piclabel" to
".L4$pb". The actual name doesn't matter and the darwin name is shorter.
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commit 9b41b2da218ae60316e2bbb39bda56bcca893e21
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 18:43:46 2009 +0000
Build (not test) the unittests as part of a normal build.
- 'make unittests' still builds and tests.
- 'make unitcheck' inside a unittest directory runs the tests in that directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81687 91177308-0d34-0410-b5e6-96231b3b80d8
commit b47f641f55f98d8ffecf935616fbe8f407a6c47b
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 18:33:59 2009 +0000
make X86ATTAsmPrinter::PrintPICBaseSymbol forward to X86MCInstLower.
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commit 2faa4ef57551d45e7b58b1827ae8156cea221637
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 18:25:37 2009 +0000
replace printBasicBlockLabel with EmitBasicBlockStart,
now that printBasicBlockLabel is only used for starting
a MBB. This allows elimination of a bunch of arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81684 91177308-0d34-0410-b5e6-96231b3b80d8
commit adfec708f335a7ea93d685ae753f74a53ca05b83
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 18:11:09 2009 +0000
fix MCSymbol printing on darwin to exactly match the mangler (handling of \n and " in a symbol name).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81683 91177308-0d34-0410-b5e6-96231b3b80d8
commit e66b5a5946e9737b7a230ba903779f4c9d15c542
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 18:04:46 2009 +0000
Make the MC symbol printer and llvm::Mangler exactly agree on mangling
for systems that don't support quoting (PR4966).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81682 91177308-0d34-0410-b5e6-96231b3b80d8
commit 126c8fe046bc70bf4289cf3d7889abc0bf0176a2
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 17:25:49 2009 +0000
remove two docs about the old Sparc backend which used Value*'s for vregs.
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commit 5027fd9cf5243d58fdacd2c37ac2dc498bdea6fd
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 17:24:16 2009 +0000
move old clang readme here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81679 91177308-0d34-0410-b5e6-96231b3b80d8
commit c6f802dd7f346ac5a44bbdc57d264ed928fe1e7c
Author: Chris Lattner <sabre at nondot.org>
Date: Sun Sep 13 17:14:04 2009 +0000
convert some uses of printBasicBlockLabel to use GetMBBSymbol
instead.
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commit 7f5f33b5ea2e756e9dd3df83c8924304ac317e4b
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 02:45:57 2009 +0000
Add LLVMGCCBINDIR to path, since LLVMC expects to find llvm-gcc in the path.
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commit 72a7ef551f36b66d339c6c0d91a99d6301ec872c
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 01:41:47 2009 +0000
Switch Ocaml to use llvm_supports_binding.
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commit 3324882bda68403c4723a6856f937320c3428849
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 01:41:18 2009 +0000
tests: Add llvm_supports_binding predicate.
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commit 282ae0b0efbe5ce5ce81c00cb4d89e813b78efc6
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 01:40:48 2009 +0000
tests: Use %abs_tmp instead of ./%t to make these tests portable to 'lit'.
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commit c46101cd59d21edd7614d3c2ad57119baebf0db4
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 01:39:50 2009 +0000
tests: Add a %abs_tmp substitution which is guaranteed to be a full path.
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commit 61e88aec10e345617c054125c4fdfdc7a692be47
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 01:39:08 2009 +0000
Sink llvm-gcc dependent tests into distinct subdirs.
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commit 8b6d1e38583dc7932d23c4803c223f54d79248dd
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 01:37:07 2009 +0000
Rewrite tests to not use Tcl substitution.
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commit 458d03ea01aa32891785347005f83ccf3944728a
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 13 01:36:19 2009 +0000
Simplify LLVMC tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81659 91177308-0d34-0410-b5e6-96231b3b80d8
commit 02791b0d5c7fe12bf1ada874da30dd5d0440bc98
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Sun Sep 13 01:12:15 2009 +0000
Fix merge problem
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commit daf700156a4b1aec6f85be6f611f2f949b154f75
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Sun Sep 13 00:59:43 2009 +0000
Define proper subreg sets for arm - this should fix bunch of subtle problems
with subreg - superreg mapping and also fix PR4965.
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commit b10a5950be94fe5cabce5d6d269bc37dc55bdd41
Author: Dan Gohman <gohman at apple.com>
Date: Sat Sep 12 23:45:47 2009 +0000
Add -mattr=+sse2 to the -march=x86 version of this test. Without
sse, this code falls back to SelectionDAG isel which uses an x87
instruction, which is fine, but not what this test is testing for.
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commit 1b03709c07c801d218f32e90bb5a77dcaf999474
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 12 23:29:02 2009 +0000
Experimental fix for PR4960.
- Could we just always implement this as __clear_cache for __GNUC__?
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commit 08c9708a8aed7028c5e3126d2d680ee1ffb4af9f
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 12 23:02:08 2009 +0000
devirtualize AsmPrinter::printBasicBlockLabel since it is never overridden.
Move GetMBBSymbol up to AsmPrinter and make printBasicBlockLabel use it so that
we only have one place that decides what to name bb labels. Hopefully various
clients of printBasicBlockLabel can start using GetMBBSymbol instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81652 91177308-0d34-0410-b5e6-96231b3b80d8
commit 69f872cbd1278b340ac8ebb23edd441cd2a0c4da
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 12 22:57:37 2009 +0000
we don't want people to override printBasicBlockLabel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81651 91177308-0d34-0410-b5e6-96231b3b80d8
commit f1df5fea30bfd9fc1b9691dab547277aba769dcd
Author: Dan Gohman <gohman at apple.com>
Date: Sat Sep 12 22:24:25 2009 +0000
Remove unnecessary #include.
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commit 3600d16e551d4b49d3d8df86d5c90061804d5c7f
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Sat Sep 12 22:21:08 2009 +0000
Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to
constraint the register usage.
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commit f2e096380d8ea7bd7cb5a47b66a9fa17ef34e365
Author: Dan Gohman <gohman at apple.com>
Date: Sat Sep 12 22:02:17 2009 +0000
Preserve the inbounds flag, so that the constant folder doesn't
recompute it.
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commit 07f468d98bf62faf754bc2c72cca515e8b6c9079
Author: Dan Gohman <gohman at apple.com>
Date: Sat Sep 12 21:56:48 2009 +0000
Fix the build when DEBUG_SYMBOL_TABLE is set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81633 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4f7a156181caf332944bcd5283cf25e074bdc51e
Author: Dan Gohman <gohman at apple.com>
Date: Sat Sep 12 21:55:12 2009 +0000
Convert llvm-link to IRReader.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81632 91177308-0d34-0410-b5e6-96231b3b80d8
commit da044747519b98d6579c6fd0638c863ee3506cb3
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 12 21:06:08 2009 +0000
factor MBB label lowering better
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commit 6874849b9aa710a542b2263e335bd9fe8e073d0b
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 12 21:01:20 2009 +0000
X86MCInstLower::Lower should only not emit anything to OutStreamer,
this means that it can only lower one MachineInstr to one MCInst. To
make this fly, we need to pull out handling of MO_GOT_ABSOLUTE_ADDRESS
(which generates an implicit label) out of X86MCInstLower.
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commit 34461fde24e25c4c789b719f16483367ef125e5c
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 12 20:45:03 2009 +0000
eliminate the "MBBLabel" MCOperand type, and just use a MCSymbol for
MBB labels like everything else.
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commit 1efc2adff3c3193bf402c9167cc3b06ec582a875
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 12 20:34:57 2009 +0000
split MachineInstr -> MCInst lowering into its own class (not
being embedded into X86ATTAsmPrinter). This still depends heavily
on X86ATTAsmPrinter, but this is a step in the right direction.
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commit a16d146018dbdd8e840db89dae3a4c6fcf8aa947
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 12 20:01:36 2009 +0000
remove the "old" at&t style asmprinter. Unfortunately, most of the
operand printing crapola cannot be removed yet because it is used by
the inline asm print stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81626 91177308-0d34-0410-b5e6-96231b3b80d8
commit 58831094f223f49d8fee7413d8ac5933599e4a40
Author: Lang Hames <lhames at gmail.com>
Date: Sat Sep 12 04:54:18 2009 +0000
Whoops. Committed the headers for r81605 - 'Moved some more index operations over to LiveIntervals.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81609 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2a7b3b261e96625d4fff876dbb859dec67e4c04e
Author: Lang Hames <lhames at gmail.com>
Date: Sat Sep 12 03:34:03 2009 +0000
Moved some more index operations over to LiveIntervals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81605 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2c2313a5e064b39cdbad9b0de471c722d800318a
Author: Sean Callanan <scallanan at apple.com>
Date: Sat Sep 12 02:52:41 2009 +0000
Added the WAIT instruction to the Intel tables,
for the purposes of the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81603 91177308-0d34-0410-b5e6-96231b3b80d8
commit 25220d648e0af4f977a0ff96fd6fabcf4e45ddb2
Author: Sean Callanan <scallanan at apple.com>
Date: Sat Sep 12 02:25:20 2009 +0000
Added CMPS (string comparison) instructions for all
operand widths to the Intel instruction tables, for
the purposes of the disassembler.
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commit d0d3ee158facc0f354906b1e5559b73ce0fd20e7
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sat Sep 12 02:14:41 2009 +0000
Remove -new-coalescer-heuristic. It's not useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81600 91177308-0d34-0410-b5e6-96231b3b80d8
commit 16c2f62b7c53316702d1ad99d7c33a08f5f5ced7
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sat Sep 12 02:01:07 2009 +0000
80 col violations.
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commit 3f74d67bcb2ebcb53e4ad66c05bdc668a0859542
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 12 01:11:50 2009 +0000
fix another GCC bootstrap problem, which manifested as things
like:
foo.s:2412:non-relocatable subtraction expression, "_gomp_tls_key" minus "L1$pb"
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commit 34184c9a753003dd6161e5f4f8770e906996621d
Author: Chris Lattner <sabre at nondot.org>
Date: Sat Sep 12 00:49:00 2009 +0000
fix an embarassing typo that resulted in llvm-gcc bootstrap miscompare
because the sorting wasn't sorting.
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commit 481f06df77485baab41d3facb6eb9903ee1b1b13
Author: Sean Callanan <scallanan at apple.com>
Date: Sat Sep 12 00:37:19 2009 +0000
Added SCAS instructions in their 8, 16, 32, and
64-bit variants for the disassembler.
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commit 8d13e71bb592c47f214eefc3cfdc016b12ff6396
Author: Daniel Dunbar <daniel at zuster.org>
Date: Fri Sep 11 22:07:31 2009 +0000
Fix -Asserts warning.
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commit 0cc7539863622c30066b5110a48827dfd55675e8
Author: Ted Kremenek <kremenek at apple.com>
Date: Fri Sep 11 21:49:45 2009 +0000
Update CMake files.
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commit 3996be16362bda84e8975ac6aef9f36358cad869
Author: Douglas Gregor <doug.gregor at gmail.com>
Date: Fri Sep 11 21:26:24 2009 +0000
De-bork CMake build. llvm-extract depends on asmparser
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commit 31b20c7d4a2789da21fe865cc5e7cfa3f6fdd581
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 11 20:46:33 2009 +0000
Fix llvm-extract's "writing bitcode to a terminal" warning, which wasn't
working. To support this, add an is_displayed() function to raw_ostream,
and generalize Process::StandardOutIsDisplayed and friends in order to
support it.
Also, call RemoveFileOnSignal before creating a file instead of after, so
that the file isn't left behind if the program is interrupted between when
the file is created and RemoveFileOnSignal is called.
While here, add a -S to llvm-extract and port it to IRReader so that it
supports assembly input.
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commit 5b01f934c23227abf954e317b5b65cc77f38c21d
Author: Jim Grosbach <grosbach at apple.com>
Date: Fri Sep 11 20:13:17 2009 +0000
Revert array initialization regclass change so that the initialization stays static, not runtime.
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commit 21f15abfa99b786925bb1b36717b454ac800251b
Author: Jim Grosbach <grosbach at apple.com>
Date: Fri Sep 11 19:49:06 2009 +0000
Update register class references to use the global constant ARM::*RegisterClass names.
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commit 8562bef1079463f9d3027bd6cfb688e99298bede
Author: Sean Callanan <scallanan at apple.com>
Date: Fri Sep 11 19:01:56 2009 +0000
Added ADC, SUB, SBB, and OR instructions that operate
on rAX and an immediate.
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commit 53fac396f5ba849f8837234584303c72fd229747
Author: Bob Wilson <bob.wilson at apple.com>
Date: Fri Sep 11 18:42:18 2009 +0000
Fix pr4820: Don't run llvm-config during "make clean" since it may have
already been removed.
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commit 8d8e16bb62905b1b14aea9481c4d085bf1c02796
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 11 18:41:06 2009 +0000
Remove an unnecessary -f.
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commit 0cb2f6731090cfc8b56679c7802983d16a21fd92
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 11 18:36:27 2009 +0000
Convert more tests to avoid llvm-as.
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commit bb9fe84e889c35f2010090c5d0d13198b57c3327
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 18:33:44 2009 +0000
fix pasto
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commit 9da96d8044dc814a45010e9f78af212c189cc447
Author: Caroline Tice <ctice at apple.com>
Date: Fri Sep 11 18:25:54 2009 +0000
Don't generate Dwarf line table entries for source line 0.
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commit 1ee2ec58cab5d4aa340aa50f67af4cd99ef184b6
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 18:20:26 2009 +0000
fix some fixmes: emit stubs in sorted order.
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commit 66c8021be5351d77c0d1cd8dd52f694ad837b741
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 11 18:17:12 2009 +0000
Eliminate more redundant llvm-as calls.
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commit 869beecde3919f7332925a43c336778be770d3b5
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 11 18:16:43 2009 +0000
Fix this test to test what it was originally intended to test.
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commit 3054c0f431010e796b0328150f93aa000f06e863
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 18:15:46 2009 +0000
give densemap iterators real iterator traits.
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commit 3c7d3083e7c99a22ee4803048dfb86c7a57b1006
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 11 18:01:28 2009 +0000
Change tests from "opt %s" to "opt < %s" so that opt doesn't see the
input filename so that opt doesn't print the input filename in the
output so that grep lines in the tests don't unintentionally match
strings in the input filename.
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commit a24946acb21bffc40e9054f7ac25eb9319b406d8
Author: Duncan Sands <baldrick at free.fr>
Date: Fri Sep 11 17:24:29 2009 +0000
Fix PR4948 (and a leak): by not destroying the DwarfException
object, the timer it creates was not being deleted. Since the
timer belonged to a static timer group, the timer group would
be destroyed on shutdown, and would notice and complain that
not all timers it contained were destroyed.
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commit 6cd70ca0ab41c5eab214b92689b072f3fe53bb37
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 17:07:27 2009 +0000
turn on -experimental-asm-printer for x86 / AT&T by default.
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commit fe7ed54bd19fceebdf98f3420567afacf9674904
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 17:07:01 2009 +0000
another random update
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commit c9f609938abc0aa496f65cec8baaccca78b4af81
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 17:05:29 2009 +0000
reject attempts to take the address of an intrinsic, PR4949.
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commit 9a8e2f2f2b6fc5e9c6122ab1539d56ef2198577d
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 17:02:12 2009 +0000
fix a bunch of spurious failures for people whose home directory
is sabre.
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commit 3c4ea8fe60cd502437e00f7e5a402329aaef79f7
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 16:49:18 2009 +0000
this test is using invalid "intrinsics".
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commit c3ad76ad92f6abf6d251e1dfa240c64c19e5bf90
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 16:47:41 2009 +0000
fix test to not get a moduleid that matches 'br'
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commit 099640405eda144320bed8acb8db97153779100a
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 16:33:58 2009 +0000
default construct MCInst's ctor to 0, which is "PHI" which is invalid for MCInsts.
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commit d11bf276c72fb90393a1c8e04ca6ba25553d5739
Author: Daniel Dunbar <daniel at zuster.org>
Date: Fri Sep 11 15:47:24 2009 +0000
... and fix the REQUIRES_RTTI condition.
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commit 7985717063d5538f40b90c688f7da9ba8f8c2bf8
Author: Daniel Dunbar <daniel at zuster.org>
Date: Fri Sep 11 15:45:13 2009 +0000
Fix REQUIRES_RTTI while awake.
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commit 1e12b8277f6064a999129a526587d8e7378cb2f3
Author: Daniel Dunbar <daniel at zuster.org>
Date: Fri Sep 11 15:39:39 2009 +0000
Make REQUIRES_RTTI work.
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commit f207074410fd77ba40ef110b17a6442b42aed6f1
Author: Owen Anderson <resistor at mac.com>
Date: Fri Sep 11 09:01:57 2009 +0000
Eliminate some unnecessary implicit constructors in generated DAG ISel code.
Partial fix for PR4946.
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commit c88e8254682141c4155c39a021038ea7c0c40cdd
Author: Andreas Neustifter <astifter at gmx.at>
Date: Fri Sep 11 08:43:15 2009 +0000
Bugfix. Sorry.
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commit 2634e55f8a73b58ee7399bf55e1cbc21457d3c50
Author: Andreas Neustifter <astifter at gmx.at>
Date: Fri Sep 11 08:39:33 2009 +0000
Make ProfileEstimator even more robust on general CFGs.
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commit 67e71746b1a96204a9f43688df0115f6fc731bfe
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 07:03:20 2009 +0000
switch HiddenGVStubs to be a DenseMap instead of a string map, mirroring FnStubs and GVStubs.
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commit d17abcab0f6c1ccf446a4447a269d1b2709700f8
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 06:59:18 2009 +0000
Fix a bug I introduced in FnStubs generation, switch GVStubs to be a
densemap instead of StringMap to match FnStubs.
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commit 25c61740e62d7ea5191b0d81da96102a266ef6c7
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 06:36:33 2009 +0000
change FnStubs from being a StringMap<std::string> to being a much
more efficient SmallPtrSet<MCSymbol*>. This eliminates string
craziness and fixes CodeGen/X86/darwin-quote.ll with the new asmprinter.
Codegen is producing stubs in a nondeterminstic order, but it was doing
this before anyway.
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commit 2fdf82ddf5816c13fe660d6309e1e09c1550e6df
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 05:59:55 2009 +0000
printInstruction() no longer prints a \n after itself, do it
for the two instruction MOVPC32r sequence.
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commit 2eaccff47f159c4a90dc8c53f9d81898f6081bd9
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 05:58:44 2009 +0000
reimplement X86ATTAsmPrinter::GetGlobalAddressSymbol in terms of
Mangler::getNameWithPrefix. In addition to avoiding some over
quoting, this also is more efficient because it uses smallvector
instead of std::string thrashing.
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commit a84c2917d3f8412b093af06801a595dcf8e00ee0
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 05:51:29 2009 +0000
fix prefix ordering, it's L_foo not _Lfoo
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commit bd7e1108fe9851970a8f9cf190defddde49ab16b
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 05:40:42 2009 +0000
add a new Mangler::getNameWithPrefix API which returns the
(uniqued if unnamed) global variable name with the prefix that
it is supposed to get. It doesn't do "mangling" in the sense of
adding quotes and hacking on bad characters.
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commit 2fe752edba6d2b52a4171262ad9281a3cf21b003
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 04:36:43 2009 +0000
convert X86ATTAsmPrinter::GetExternalSymbolSymbol to use SmallString
instead of std::string and Mangler.
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commit e6fe945acbcf6c92f3b8e9b193f588e1404a9576
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 04:28:13 2009 +0000
rearrange some code, export a SmallString version of DecorateCygMingName.
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commit 9d1e4fa6fdfac2bd80e049ef298365d764553302
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 01:49:31 2009 +0000
more typos
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commit 5b7dbbf6ff503a3bd10b87ebeeed3e48e36e0d55
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Sep 11 01:01:31 2009 +0000
Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index.
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commit 58f44f226573975dce94b0bd23b95c2b2df80d56
Author: Chris Lattner <sabre at nondot.org>
Date: Fri Sep 11 00:41:15 2009 +0000
PHI nodes can never reach the asmprinter, assert and die instead of printing
out an illegal "PHINODE" instruction.
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commit 8f0797fd72559a3066290f87c4f79a257bf64fc6
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Sep 11 00:39:26 2009 +0000
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not
safe. This can happen we a subreg_to_reg 0 has been coalesced. One
exception is when the instruction that folds the load is a move, then we
can simply turn it into a 32-bit load from the stack slot.
rdar://7170444
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commit 8c5f55f3e68092a732e6d3fa0dac6de724461a44
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 11 00:36:43 2009 +0000
Make fast-isel try ISD::FNEG before resorting to bitcasts and xors.
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commit b144a5210c2df1b248b0c92fbf18f0cb1f9f9f91
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 11 00:34:46 2009 +0000
Reapply r81171 with a fix: don't try to use i64 when it
isn't legal.
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commit 78894ba572c0da894a177328a0b37d4e8b0cff39
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 11 00:05:10 2009 +0000
Fix indentation.
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commit 6200a6ec5cb2d2474317cf7c801d242ec25595f4
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 11 00:04:14 2009 +0000
Teach lib/VMCore/ConstantFold.cpp how to set the inbounds keyword and
how to fold notionally-out-of-bounds array getelementptr indices instead
of just doing these in lib/Analysis/ConstantFolding.cpp, because it can
be done in a fairly general way without TargetData, and because not all
constants are visited by lib/Analysis/ConstantFolding.cpp. This enables
more constant folding.
Also, set the "inbounds" flag when the getelementptr indices are
one-past-the-end.
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commit db050e9d9673fda33b4acbf67b1137a6a91e74b7
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 10 23:37:55 2009 +0000
Factor out the code for checking that all indices in a getelementptr are
within the notional bounds of the static type of the getelementptr (which
is not the same as "inbounds") from GlobalOpt into a utility routine,
and use it in ConstantFold.cpp to check whether there are any mis-behaved
indices.
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commit ce128857e923728587cf38bac23d9f6ba231ca01
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 10 23:07:18 2009 +0000
Give these files top-level comments that describe the current code.
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commit ffc801c29e1d6fa3f6ff2d4236b671b4183b67a1
Author: Devang Patel <dpatel at apple.com>
Date: Thu Sep 10 22:36:12 2009 +0000
Fix whitespaces.
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commit 13d28af8449cfa2269589ffb95b3c1d66e9e888c
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 10 22:14:16 2009 +0000
Fix validation errors.
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commit ca831f14d40e32df191244092c71e47a3b3498b0
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 10 22:12:50 2009 +0000
Fix validation errors.
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commit bdebfa961d5a71ebab1e0e622dd2abb463fff8aa
Author: Bob Wilson <bob.wilson at apple.com>
Date: Thu Sep 10 22:09:31 2009 +0000
Don't swap the operands of a subtraction when trying to create a
post-decrement load/store.
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commit 22457ddb96b05ae203164134cc748b43a120ad26
Author: Dale Johannesen <dalej at apple.com>
Date: Thu Sep 10 22:01:32 2009 +0000
Fix uppercaseo.
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commit ae90d09ea43ca4b0dfa02d2c6d679f81380231ed
Author: Kevin Enderby <enderby at apple.com>
Date: Thu Sep 10 20:51:44 2009 +0000
Added the ParseInstruction() hook for target specific assembler directives so
that things like .word can be parsed as target specific. Moved parsing .word
out of AsmParser.cpp into X86AsmParser.cpp as it is 2 bytes on X86 and 4 bytes
for other targets that support the .word directive.
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commit 546b28bd90852f0bea34a6dc10cf22de5a773252
Author: Victor Hernandez <vhernandez at apple.com>
Date: Thu Sep 10 20:18:57 2009 +0000
Fit code within 80 columns
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commit 794457a9a6c91baf493f12fe081f70924b1b7c33
Author: Sean Callanan <scallanan at apple.com>
Date: Thu Sep 10 19:52:26 2009 +0000
Added XOR instructions for rAX and immediates of
various widths.
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commit 70953a5bee9da7718fab97c9db999041dd38666d
Author: Sean Callanan <scallanan at apple.com>
Date: Thu Sep 10 18:33:42 2009 +0000
Added MOV instructions between rAX and memory offsets,
including segment offsets and (for 8-bit operands)
absolute offsets.
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commit 9f3c3f5e4ad869045baed502d9b041f55847f42f
Author: Sean Callanan <scallanan at apple.com>
Date: Thu Sep 10 18:29:13 2009 +0000
Added a variety of PUSH and POP instructions, including
ones capable of accessing R/M operands instead of just
registers.
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commit f2c39f52d692834fd39bfb37e942840188554463
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 10 18:28:06 2009 +0000
Exit early if exception handling isn't supported.
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commit 7360cdd2ba9923efb70579ec60480c5408edac21
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Thu Sep 10 17:04:32 2009 +0000
Allow llvmc to take .bc files as input.
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commit 9fc3b22df49c0bce6268f337a17e196cbedee72c
Author: Andreas Neustifter <astifter at gmx.at>
Date: Thu Sep 10 16:30:38 2009 +0000
Make ProfileEstimator more robust on general CFGs.
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commit 5d83433e2b5a37237f7cce22addd8fb1bbb92306
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 10 16:25:02 2009 +0000
add another broken version of gcc, thanks to Niels Moller for pointing this out.
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commit fcccb9fa64db28ccbb9bdb06341160465dc64a79
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Thu Sep 10 16:22:02 2009 +0000
Distinguish between 'empty' and empty DAG marker.
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commit a125693f1475029900a6764451778cecfbbc69bf
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Thu Sep 10 16:21:38 2009 +0000
Add a logical 'not' operator to llvmc's TableGen dialect.
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commit 6df6696a9d9f9691db9498c865b3abe013cbbe37
Author: Nuno Lopes <nunoplopes at sapo.pt>
Date: Thu Sep 10 14:56:31 2009 +0000
fix leakage of Module
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commit 90deca07b0cfa2fdceb9cba6e2abd470659444b9
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Thu Sep 10 11:31:39 2009 +0000
Add some braces to make newer GCCs happy and update CMakeLists.
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commit 61a788cef4f56ff000806c0c267a7ace68e4f1e2
Author: Andreas Neustifter <astifter at gmx.at>
Date: Thu Sep 10 07:12:35 2009 +0000
Cleaned up code by factoring out common portions of edge loading into function.
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commit 70ae96f3e7d2070972d280cecc2ccf13bdea3974
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Thu Sep 10 07:02:09 2009 +0000
Correctly handle the case where a comparison is created in one BasicBlock and
used by a terminator in another.
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commit 7bb50b4935836725b83eefeb1e90d0a659ef15a5
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 10 06:50:01 2009 +0000
Comment and whitespace cleanups. No intentional functionality change.
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commit 74446ffeba3226ae63f9a437230fe0f407a308d4
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 10 06:27:16 2009 +0000
Revert part of my r81424 patch. I removed what looked like superfluous padding
from the exception tables. However, Duncan explained why it's a can of worms to
do it the GCC way. I went back to doing it the LLVM way and added Duncan's
explanation so that I don't do this again in the future.
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commit a511570cf8e6859deef445efe8a0db3707e10f95
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Sep 10 05:08:51 2009 +0000
Add a test case for r81431.
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commit 67d34bd5b31add07ba8413b05d019e22f35d9a0e
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 10 04:56:59 2009 +0000
Remove prcontext.
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commit e5406467385df42184feed2f03fbdab5ac38c9f5
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Sep 10 04:36:43 2009 +0000
Add malloc call utility functions. Patch by Victor Hernandez.
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commit 5c6e5ae3c8ec8cc5df9f82b4c51d67105e941e5f
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 10 02:07:37 2009 +0000
Don't hardcode the TType format size. In fact, rework the code so that it's more
like what GCC outputs. The mysterious code to insert padding wasn't in GCC at
all. I modified the TType base offset code to calculate the offset like GCC
does, though.
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commit 50e503fc4a90ecd8e98266c4a68c566e5f3e315f
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Sep 10 01:23:53 2009 +0000
Proper support of non-lazy indirect symbols.
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commit 630d3b5c3e116554239d4c50032d2c1b9a01738d
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 10 01:12:47 2009 +0000
Remove the "#if 0" that Noone loved. It wasn't really necessary, because the
code within it was the same inside and out. There's still a problem of the
TypeInfoSize should be the size of the TType format encoding (at least that's
what GCC thinks it should be).
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commit 9ba888a01e1f53c88d8a491b35cee78b170d2ff5
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 10 00:59:15 2009 +0000
MC: Give target specific parsers access to the MCStreamer.
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commit 9aadf0b01025e9a91a285fe87cf58353cc8aa61e
Author: Bob Wilson <bob.wilson at apple.com>
Date: Thu Sep 10 00:49:22 2009 +0000
Revert r81171 which was causing pr4927.
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commit d832f2cd021588a797c00175a894f63d652b3755
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 10 00:17:04 2009 +0000
Pull check for SJLJ EH into a boolean and use that.
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commit 1961846a4701a5cd43a8d7f2624138da0f745e1f
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 10 00:13:16 2009 +0000
Use the SizeOfEncodedValue function instead of magic variables for the
sizeof(DW_EH_PE_udata4).
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commit f551420260bd4eb5e4ca6307eb9ae4d411154061
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 10 00:04:48 2009 +0000
Add helpful comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81406 91177308-0d34-0410-b5e6-96231b3b80d8
commit e99c6d49ea0f6f3b562af85580bdf18bd278b933
Author: Bill Wendling <isanbard at gmail.com>
Date: Wed Sep 9 23:56:55 2009 +0000
Believe it or not, this is a simplification. :-)
Basically, this patch is working towards removing the hard-coded values that are
output for the CIE. In particular, the CIE augmentation and the CIE augmentation
size. Both of these should be calculated. In the process, I was able to make a
bunch of code simpler.
The encodings for the personality, LSDA, and FDE in the CIE are still not
correct. They should be generated either from target-specific callbacks (blech!)
or grokked from first-principles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81404 91177308-0d34-0410-b5e6-96231b3b80d8
commit 71429f87316fc88ebe54b904c4b1326a71fbc3ec
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 9 23:55:03 2009 +0000
Fix double load / store multiple encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81403 91177308-0d34-0410-b5e6-96231b3b80d8
commit 431b4df9155bfbe94d3b50a1f1bdebfa9055cb44
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 23:46:42 2009 +0000
canonicalize namespace gymnastics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81402 91177308-0d34-0410-b5e6-96231b3b80d8
commit b53d938b38393b624f7f12269c9784cd5116c3bf
Author: Dale Johannesen <dalej at apple.com>
Date: Wed Sep 9 23:37:46 2009 +0000
Testcase for (llvm-gcc) 81399. Adjust an older
test case to allow for different, functionally
identical output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81400 91177308-0d34-0410-b5e6-96231b3b80d8
commit 10371a5fdd1b829b3ce0cbd6d0721c700bde1e55
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 9 23:14:54 2009 +0000
Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.
See the bug report for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81397 91177308-0d34-0410-b5e6-96231b3b80d8
commit 32d4cc74e1075b6d9f77c75ff6099784ad4f15b2
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 23:14:36 2009 +0000
remove DebugLoc from MCInst and eliminate "Comment printing" from
the MCInst path of the asmprinter. Instead, pull comment printing
out of the autogenerated asmprinter into each target that uses the
autogenerated asmprinter. This causes code duplication into each
target, but in a way that will be easier to clean up later when more
asmprinter stuff is commonized into the base AsmPrinter class.
This also fixes an xcore strangeness where it inserted two tabs
before every instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81396 91177308-0d34-0410-b5e6-96231b3b80d8
commit c53c4e5693d079829a7a78d662e691217aaf190f
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 23:09:29 2009 +0000
Fix a subtle bug in "return;" generation which caused us to miss
a return in one case. Instead of sprinking return handling code
throughout the asmprinter generator, just treat it like any other
normal statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81395 91177308-0d34-0410-b5e6-96231b3b80d8
commit fa50179c30d291443d10d93a7ec6eb4958ee1ac5
Author: Daniel Dunbar <daniel at zuster.org>
Date: Wed Sep 9 23:01:25 2009 +0000
Add comment re: clang dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81393 91177308-0d34-0410-b5e6-96231b3b80d8
commit ffdf10df7ba8b1cef378d86ab11912a95b04e8d4
Author: Sean Callanan <scallanan at apple.com>
Date: Wed Sep 9 22:49:13 2009 +0000
Added an abstract superclass, MCDisassembler, for
all disassemblers.
Modified the MemoryObject to support 64-bit address
spaces, regardless of the LLVM process's address
width.
Modified the Target class to allow extraction of a
MCDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81392 91177308-0d34-0410-b5e6-96231b3b80d8
commit be23fd415c91d6b17149b67497316d9593305e05
Author: Bill Wendling <isanbard at gmail.com>
Date: Wed Sep 9 21:26:19 2009 +0000
Use the EOL that takes the encoding and translates it into DWARF-English.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81382 91177308-0d34-0410-b5e6-96231b3b80d8
commit c38ebcb176943ab2d8c5e0aa458f3f18990f15b8
Author: Bill Wendling <isanbard at gmail.com>
Date: Wed Sep 9 21:08:12 2009 +0000
Early exit from function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81381 91177308-0d34-0410-b5e6-96231b3b80d8
commit cb3105b639197e0e15486fa17beeee74682a608c
Author: Bill Wendling <isanbard at gmail.com>
Date: Wed Sep 9 21:06:24 2009 +0000
Small amount of code clean-up: Don't use ".size()" when not necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81380 91177308-0d34-0410-b5e6-96231b3b80d8
commit a0741b254540f2c14be367e5de6f893e6b817f35
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 20:45:42 2009 +0000
add a gross hack to get "SrcLine" comments to show up with the
new asmprinter. Differently gross hack coming next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81379 91177308-0d34-0410-b5e6-96231b3b80d8
commit e34788cb7ed482bf3b51075f1b06ccc03021fbac
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 20:34:59 2009 +0000
hoist the call to processDebugLoc out of the generated
asm printer into the "printInstruction" routine. This
fixes a problem where the experimental asmprinter would
drop debug labels in some cases, and fixes issues on ppc/xcore
where pseudo instructions like "mr" didn't get debug locs properly.
It is annoying that this moves the call from one place into each
target, but a future set of more invasive refactorings will fix
that problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81377 91177308-0d34-0410-b5e6-96231b3b80d8
commit a46d337b041e98c716269c600e3097cc5cca64ae
Author: Lang Hames <lhames at gmail.com>
Date: Wed Sep 9 20:14:17 2009 +0000
Removed static qualifier from a few index related methods. These methods may require a LiveIntervals instance in future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81374 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5af655e4025b57503a223cbfba2e540f5bab113f
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 9 18:19:35 2009 +0000
Reverted r81358.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81364 91177308-0d34-0410-b5e6-96231b3b80d8
commit f06a9bac9d29e83d24d667ed42f1028e493de42d
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 9 18:18:18 2009 +0000
Fix SplitCriticalEdge to properly update LCSSA form when splitting a
loop exit edge -- new PHIs may be needed not only for the additional
splits that are made to preserve LoopSimplify form, but also for the
original split. Factor out the code that inserts new PHIs so that it
can be used for both. Remove LoopRotation.cpp's code for manually
updating LCSSA form, as it is now redundant. This fixes PR4934.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81363 91177308-0d34-0410-b5e6-96231b3b80d8
commit 8aa5c72ebecdde5b86c4564ef6059faf34eb1ed7
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Wed Sep 9 18:03:46 2009 +0000
Fix build, add missing simicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81362 91177308-0d34-0410-b5e6-96231b3b80d8
commit a89b291eb4dee0605e7618653dac2634fea14e92
Author: Mike Stump <mrs at apple.com>
Date: Wed Sep 9 17:57:16 2009 +0000
Reflow comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81361 91177308-0d34-0410-b5e6-96231b3b80d8
commit f193e18b174a8fe51242aabb07f3c0a4f39415af
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 9 17:53:39 2009 +0000
Preserve ProfileInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81360 91177308-0d34-0410-b5e6-96231b3b80d8
commit a1eaf2a024b2338fcdf2ffab01b7169319969830
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 9 17:52:57 2009 +0000
Add the first functions for updating ProfileInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81359 91177308-0d34-0410-b5e6-96231b3b80d8
commit ba865fcfc00592809b38bad4e65aa5eebd9103bd
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 9 17:51:39 2009 +0000
Cleaned up code by factoring out common portions of edge loading into funcion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81358 91177308-0d34-0410-b5e6-96231b3b80d8
commit 26f6d849e4659e4bb4944359b302fd2aa0e0155b
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 9 17:44:26 2009 +0000
Take lock before removing a node from MDNodeSet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81356 91177308-0d34-0410-b5e6-96231b3b80d8
commit 44c965aed1380578a557b9367f94dee4261dd28d
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 9 17:30:04 2009 +0000
Enable MDNode uniquing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81355 91177308-0d34-0410-b5e6-96231b3b80d8
commit ae4f2739f3a56d33a4049ca94b06021b2bd9bc7e
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 9 17:17:19 2009 +0000
Fix an 80-column violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81354 91177308-0d34-0410-b5e6-96231b3b80d8
commit 94e5001925e25df698a8372024f06bd8581e6edf
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 9 17:07:07 2009 +0000
Gracefully destroy MDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81353 91177308-0d34-0410-b5e6-96231b3b80d8
commit 0d0ae7a4285264213962e906068c98dcf97f2b8e
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 9 16:47:12 2009 +0000
Hide all cscope files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81350 91177308-0d34-0410-b5e6-96231b3b80d8
commit 99a2c97352dfd94a4b94fc6f23f8f0dd6f1ff7be
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 9 16:45:41 2009 +0000
Updated svn:ignore to hide *.cmx files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81349 91177308-0d34-0410-b5e6-96231b3b80d8
commit 920911d1e9f01bca349c9cf90fe78712491a4766
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 16:00:57 2009 +0000
revert r81335, which breaks the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81347 91177308-0d34-0410-b5e6-96231b3b80d8
commit da58ebcc2659fad293f11e4cd48f9d92b7fc594b
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 9 14:22:57 2009 +0000
When widening a vector load, use the correct chain. This fixes PR4891.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81343 91177308-0d34-0410-b5e6-96231b3b80d8
commit ca1fa68f6f989937a2233797e0f7e6942c4d3b6a
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 9 13:01:03 2009 +0000
Fixed wrong storage option for ProfileVerifierDisableAssertions.
Fixed non working -profile-verifier-noassert option.
Fixed missing newline in debugEntry().
Cleaned up assert messages. (assert(0 && Message) is still shown, but the message is printed before.)
When verifiying loaded profiles the ProfileVerifier got confused when block was a setjmp target, this is checked now.
When verifiying loaded profiles the ProfileVerifier got confused when block eventually reaching an exit(), this is checked now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81338 91177308-0d34-0410-b5e6-96231b3b80d8
commit 20bfe16d937eb797d4248dec6c2a57b691779e35
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 9 12:48:26 2009 +0000
Updated ProfileInfo to have clean seperation between different sentinels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81335 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7662985fce9b2ca4b60bc57321142a7149fe63d2
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Wed Sep 9 12:09:08 2009 +0000
Add a shortcut for OS X to Path::GetMainExecutable. This gives a nice speedup on
clang's testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81333 91177308-0d34-0410-b5e6-96231b3b80d8
commit c755dc57023bd41f52fa464c2fd5008b2171a0c0
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Wed Sep 9 10:14:55 2009 +0000
Copy-pasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81331 91177308-0d34-0410-b5e6-96231b3b80d8
commit 00456a75b37a9e1edda5a37657037001eb2deee9
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Wed Sep 9 09:52:04 2009 +0000
Revert 81248 for now.
Program objects have ownership semantics on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81329 91177308-0d34-0410-b5e6-96231b3b80d8
commit fd1f9fef9648975b0a201da42797d12415eeb83a
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Wed Sep 9 09:51:47 2009 +0000
Check that the 'kill' call succeeded.
Thanks to Duncan Sands for spotting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81328 91177308-0d34-0410-b5e6-96231b3b80d8
commit ebd2da13f15d830ecbac3ffb953fc00bfde9bab2
Author: Edwin Török <edwintorok at gmail.com>
Date: Wed Sep 9 09:34:43 2009 +0000
Add testcase for r81322 (PR4933).
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commit 58b79487c4ff0f1a4d6c39ce02ab323a73c20b03
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Wed Sep 9 08:48:53 2009 +0000
Provide proper section flags for various BSS flavours
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81322 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5e258a3086667213fb50e920d661bd91a7c0c134
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Wed Sep 9 08:41:20 2009 +0000
Whitespace cleanup
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commit 4de5778fc6ee03ef9b6f2c79a3c92f1886b90e73
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 06:19:34 2009 +0000
add a testacse for the objc problem that required required r81305
to be temporarily disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81320 91177308-0d34-0410-b5e6-96231b3b80d8
commit 965cb2f51ad0e6a8e6e22d1d348057c82a7994b6
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 06:11:14 2009 +0000
disable the new asmprinter by default. Both the Mangler and MCSymbol
printing stuff are quoting symbols now, breaking objc testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81319 91177308-0d34-0410-b5e6-96231b3b80d8
commit 52f6f63fbd1339c08b982355b62b85dc344add50
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 9 06:05:16 2009 +0000
Cast MO.getImm() to unsigned before comparing with an unsigned limit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81318 91177308-0d34-0410-b5e6-96231b3b80d8
commit 509ea0c591607793cc3fdf076b80c5743b72ef17
Author: Jeffrey Yasskin <jyasskin at google.com>
Date: Wed Sep 9 05:04:01 2009 +0000
Make TypeBuilder's result depend on the LLVMContext it's passed.
TypeBuilder was using a local static variable to cache its result. This made it
ignore changes in its LLVMContext argument and always return a type constructed
from the argument to the first call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81316 91177308-0d34-0410-b5e6-96231b3b80d8
commit 00b667ca7c080da239365c2b129fa85854005ecb
Author: Daniel Dunbar <daniel at zuster.org>
Date: Wed Sep 9 02:41:50 2009 +0000
Update test.
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commit 8acf90f7d6f9850e5192cb6530261aa5d829663b
Author: Daniel Dunbar <daniel at zuster.org>
Date: Wed Sep 9 02:41:42 2009 +0000
Count test correctly with -q.
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commit 00a068c0defbc610732b89f79904cd04e0a70dc0
Author: Daniel Dunbar <daniel at zuster.org>
Date: Wed Sep 9 02:41:32 2009 +0000
Fix another refactoro.
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commit c84d4d3a2e752a4ba621587c066c1177cb8d5f40
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 9 01:56:29 2009 +0000
Make sure to make stub region writable before emission, executable after emission.
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commit a989293ca8e2c88ac10cf6fb577a9ece58b7b845
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 9 01:47:07 2009 +0000
Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81310 91177308-0d34-0410-b5e6-96231b3b80d8
commit fa04aba9a45c6870836e614150182cd487aa7af3
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 9 01:45:24 2009 +0000
Make sure the memory range is writable before memset'ing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81308 91177308-0d34-0410-b5e6-96231b3b80d8
commit 204d7688f36dfed6dd487371db80ad9140b36986
Author: Eric Christopher <echristo at apple.com>
Date: Wed Sep 9 01:44:53 2009 +0000
Correct __cxa_end_catch documentation to reflect that it doesn't take any arguments.
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commit 7b3c2ad4b0e7825170e90aadb07fe99408d4046b
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 9 01:38:23 2009 +0000
Remove comments which don't add much to .s readibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81306 91177308-0d34-0410-b5e6-96231b3b80d8
commit 89e53b29fc360d43953ac7df1fbded8e33ed9956
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 00:41:36 2009 +0000
turn the mcinst asmprinter on by default for x86, tweaking two tests to
expect the slight syntax differences in the generated code.
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commit 78c95d8c68ea762991d677773b07eb4d082bfcbc
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 00:40:31 2009 +0000
tidy up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81304 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9cecef9d4ce35724024f8df6dac209897a76d6f1
Author: Bill Wendling <isanbard at gmail.com>
Date: Wed Sep 9 00:30:25 2009 +0000
Remove failing test...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81303 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4c8121fc171afe801eab440d89443985b136b53f
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 9 00:23:52 2009 +0000
Add an svn:ignore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81302 91177308-0d34-0410-b5e6-96231b3b80d8
commit d456b2e7d9e9d219e1d429104a35cb6ea5db91ab
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 00:23:32 2009 +0000
make sure to send external symbols through the mangler,
this fixes mingw-alloca.ll with the new asmprinter.
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commit abe57efd23c3d7f05b01aa30be895f5ae3a41ff4
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 9 00:22:49 2009 +0000
Use "opt < %s" instead of "opt %s" to keep the testname away from the grep.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81299 91177308-0d34-0410-b5e6-96231b3b80d8
commit 44130371343172fe453917c41f74dd795e2fe85e
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 00:22:31 2009 +0000
this got merged into lea.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81298 91177308-0d34-0410-b5e6-96231b3b80d8
commit b39ffdf617c65df69bddce5d456bbfb63426060b
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 00:19:46 2009 +0000
filecheckize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81297 91177308-0d34-0410-b5e6-96231b3b80d8
commit 98d648dc6c48b4a9cc0d8126ec22d10ccf51813e
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 00:14:09 2009 +0000
allow @ in symbol names without quoting the identifier. This
allows things like @PLT without quotes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81296 91177308-0d34-0410-b5e6-96231b3b80d8
commit 6b3593ac463ad21559e0097a268888c79e4e403e
Author: Bill Wendling <isanbard at gmail.com>
Date: Wed Sep 9 00:11:02 2009 +0000
Fix PR4865. This syncs up the JIT's DWARF emitter with what's in the
'DwarfException.cpp' file, which changed how CIEs were emitted, the sizes of
some fields, etc.
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commit 50470b55a378c023286f09325ae098496becc002
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 9 00:10:14 2009 +0000
add support for @PLT and friends on external symbols, fixes
x86-64-pic-11.ll with the new asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81294 91177308-0d34-0410-b5e6-96231b3b80d8
commit da594cf0865888a79fe498de539e2285430674cb
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 9 00:09:15 2009 +0000
Eliminate more uses of llvm-as and llvm-dis.
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commit 0a063105e432e649d64d354a3ea4b295172ed6cf
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 8 23:54:48 2009 +0000
Eliminate more uses of llvm-as and llvm-dis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8
commit 801631d7291d79bf1e9381dcd07e1f2af2b9eeb7
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 23:51:06 2009 +0000
update various tests for signedness changes in .s file.
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commit 793df4a99f1c9c201d1d660c469eb396fd30c926
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 23:44:53 2009 +0000
adjust for signedness change. I'd appreciate it if an ARM flavored person
could look at this: the top undefined bits of an immediate shouldn't affect
isel (cmp vs cmp.w)
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commit f104fefd323bde3c0259a290322b01883457ed5a
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 8 23:44:24 2009 +0000
Merge Archive/extract* tests into one; this avoids a race when tests are run in
parallel (the test should really use temps for the output, though).
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commit 84be013efdfb9340a10c2f2821211423d0a962ab
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 23:41:06 2009 +0000
merge thumb2-bic2.ll into thumb2-bic.ll and update for signedness changes.
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commit 221813a2d67821161ca4604121d3d4b9a5e3c406
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 8 23:32:51 2009 +0000
Add Triple::getArchTypeForDarwinArchName, which converts a "Darwin" architecture
name (e.g. "ppc") to the appropriate constant.
Also, StringRefize additional Triple constructor.
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commit ee69fee764b11c7e480bb29ef351f93062bbdcca
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 23:32:40 2009 +0000
tweak this to pass on linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81273 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4b349f2003f776ef5bca4e009bf0af96a884ca52
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 8 23:32:35 2009 +0000
Improve JIT error message for users crazy enough to use -march with JIT, and
mention -version in messages about missing targets.
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commit 75410d8bc45d8536e7a7c7acdce7b7a064256291
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 23:20:50 2009 +0000
parenthesize symbol names that start with $, fixing X86/dollar-name.ll with
the new asmprinter.
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commit cd30f56da8ae5252a5028754cbf035d4081c6cb7
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 23:16:26 2009 +0000
convert to filecheck syntax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81267 91177308-0d34-0410-b5e6-96231b3b80d8
commit 0ac501ab8363823363bb62cba3f3bde409d8c5b5
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 23:05:44 2009 +0000
change selectiondag to add the sign extended versions of immediate operands
to instructions instead of zero extended ones. This makes the asmprinter
print signed values more consistently. This apparently only really affects
the X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81265 91177308-0d34-0410-b5e6-96231b3b80d8
commit fa540692bfbce485b154f35b13f10748819d19e1
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 8 22:57:49 2009 +0000
Use "opt < %s" instead of "opt %s" so that opt doesn't print the test
filename in the output, which interferes with the tests' grep lines.
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commit 14636a5b8822276713045b4322b1f9f9c0c7c600
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Tue Sep 8 22:51:43 2009 +0000
Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81262 91177308-0d34-0410-b5e6-96231b3b80d8
commit f15d065c6f04c706e8262c116d3d4d4040f5eb64
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 8 22:41:33 2009 +0000
Convert a few more opt | llvm-dis to opt -S.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81261 91177308-0d34-0410-b5e6-96231b3b80d8
commit d9352009ee611a1443f5dca5202ffc76430fd385
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 22:38:46 2009 +0000
filecheckize some tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81259 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5bb7c7c3b0d45867a9770d5468624cbefe37adad
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 8 22:34:10 2009 +0000
Use opt -S instead of piping bitcode output through llvm-dis.
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commit 1e4519c64ba34818ace9858444a66399be7eecfd
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 8 22:20:35 2009 +0000
Use MemoryBuffer::getBufferIdentifier() in the AsmPrinter instead
of requiring a name be passed in. This makes it use "<stdin>"
instead of "-" and makes it more consistent with the Bitcode reader.
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commit 61cf99d511f74bef0739cdbfbbcf7094d3db2303
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Tue Sep 8 20:31:27 2009 +0000
This should unbreak the build on 64-bit Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81252 91177308-0d34-0410-b5e6-96231b3b80d8
commit 66b57f3a2a4891f05392bdffb6717326f99b9bc6
Author: Owen Anderson <resistor at mac.com>
Date: Tue Sep 8 19:53:15 2009 +0000
Fix PR4909, patch by Jakub Staszak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81250 91177308-0d34-0410-b5e6-96231b3b80d8
commit c5e639c1b8eb54e0af46b3a529d0a1cac39f8ded
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Tue Sep 8 19:51:39 2009 +0000
Const-correctness.
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commit 7490029b28358b8251bf525e199b2618a7da4afa
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Tue Sep 8 19:51:12 2009 +0000
Since Program is basically a PID, it should be copyable.
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commit 460b0175ff36930e7ab2a0c1e0ac1c861b704765
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Tue Sep 8 19:50:55 2009 +0000
Get rid of the Pid_ member in the Program class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81247 91177308-0d34-0410-b5e6-96231b3b80d8
commit a28016831340436a42b077c2711e040c46cb106f
Author: Mikhail Glushenkov <foldr at codedgers.com>
Date: Tue Sep 8 19:50:27 2009 +0000
Add a Kill() function to the Program class.
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commit 83d45d7286b38453c8182486393dabde6f28c574
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 19:45:34 2009 +0000
another typo
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commit e951acadc8f81264295608f02ea3f7dcbb0e3846
Author: Evan Cheng <evan.cheng at apple.com>
Date: Tue Sep 8 18:52:20 2009 +0000
Do not specify -mmacosx-version-min if building for arm-apple-darwin.
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commit a97bc6042d8356416520f6daf9c9269c3afde89b
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 18:48:01 2009 +0000
remove an extremely dubious instcombine transformation of
extractelement(load).
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commit 1c440a116254922bcaeae433788bfb170a8546e1
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 8 18:14:36 2009 +0000
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81235 91177308-0d34-0410-b5e6-96231b3b80d8
commit d873a95ab04653b72825b360c48420e6763f3da3
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 8 17:03:05 2009 +0000
Trim unnecessary declarations.
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commit 1b4c27779eba0ad4edeb73d1c2855345ad56f6ff
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 8 16:50:01 2009 +0000
Change these tests to feed the assembly files to opt directly, instead
of using llvm-as, now that opt supports this.
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commit 06db349124125c3fc5c310afeb56be0d2d81aacb
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 8 16:14:54 2009 +0000
Fix may-be-used-uninitialized warning.
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commit 25de0deb077ad1db2da9b0ed3ba6c0efc07a936d
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 8 15:52:56 2009 +0000
llvm-as is no longer needed here, now that opt can read assembly
files directly.
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commit 9cec4125f92b12880692c3e4a378b792a85ea67a
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 8 15:45:00 2009 +0000
Re-apply r80926, with fixes: keep the domtree informed of new blocks
that get created during loop unswitching, and fix SplitBlockPredecessors'
LCSSA updating code to create new PHIs instead of trying to just move
existing ones.
Also, optimize Loop::verifyLoop, since it gets called a lot. Use
searches on a sorted list of blocks instead of calling the "contains"
function, as is done in other places in the Loop class, since "contains"
does a linear search. Also, don't call verifyLoop from LoopSimplify or
LCSSA, as the PassManager is already calling verifyLoop as part of
LoopInfo's verifyAnalysis.
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commit dd528195c766db4211a29e0955e5f888f322dc37
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Tue Sep 8 15:22:32 2009 +0000
Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
makes the code faster.
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commit c802e48f18be86250b5249a8f545fc61ae858aa6
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 15:13:16 2009 +0000
fix a couple typos pointed out by edwin and duncan
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commit ce4265b24fa707a83b564c814a66d6f4ca7e76fe
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 8 14:14:24 2009 +0000
Unbreak these tests. Chris, please verify that these changes are intended.
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commit b246f53c4457fe7787ba675807eb78e8c4cdd540
Author: Richard Pennington <rich at pennware.com>
Date: Tue Sep 8 12:47:30 2009 +0000
Add source debug information to the Sparc code generator.
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commit 99c816857be050d35719a3425f46a4ac1b1057e7
Author: Nicolas Geoffray <nicolas.geoffray at lip6.fr>
Date: Tue Sep 8 07:39:27 2009 +0000
When emitting a label for a PostCall safe point, the machine
instruction to insert before can be end(). getDebugLoc on
end() returns an invalid value, therefore use the debug
loc of the call instruction, and give it to InsertLabel.
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commit d326c7aff924917ceb6cb9b9a788865941d8b531
Author: Nicolas Geoffray <nicolas.geoffray at lip6.fr>
Date: Tue Sep 8 07:36:18 2009 +0000
Also emit a label for TargetInstrInfo::GC_LABEL.
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commit a04450b1cad35ec96eb4b15d5646661232475a51
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Tue Sep 8 07:30:03 2009 +0000
Unbreak
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commit 4f6c7da13e517fa7aacc7514bbff034365823970
Author: Evan Cheng <evan.cheng at apple.com>
Date: Tue Sep 8 06:39:07 2009 +0000
When remat'ing and destination virtual register has a sub-register index. Make sure the sub-register class matches the register class of the remat'ed instruction definition register class.
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commit b051a8456f5c4ef77a845b6359f32cd26b6938a8
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 06:37:35 2009 +0000
Print "X-42" instead of "X+-42".
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commit 914d43ea8fcbcc97cf319ce1ea86af4489797ca2
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 06:34:07 2009 +0000
make formatting of expressions more closely match the existing asmprinter.
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commit 44ef733215a9c96583d0d74f32b79fd2017718e5
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 06:27:48 2009 +0000
tidy whitespace.
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commit a2724d2a6913f8ec77ccd2291249cbe11d4405d2
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 06:26:40 2009 +0000
disable some irrelevant eh emission
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commit 420109d27c41cf7306706d14ca814636294f2b55
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 06:25:12 2009 +0000
add support for some missing modifiers on jumptable/constant pool entries.
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commit c638baf0df2f24ebf41eca5f8521a69ad1a5a076
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 06:19:15 2009 +0000
add a bunch more evil lowering code to work around various :subreg32 modifiers
in the .td files. This gets us down to 18 failures in codegen/x86 with the
new asmprinter.
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commit bad5239b41aae2d840894165a79bd315e511d520
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 8 06:08:07 2009 +0000
lit needs bash for tcl-as-sh execution, we use set -o pipefail.
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commit 06418126b47276fa17a388ee789fdf2b65bf75e9
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 06:03:07 2009 +0000
ADd support for "lowering" the X86::MOVZX16rr8/X86::MOVZX16rm8
subreg32 modifiers.
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commit a2683c9d41df3f486f949333263ae6a1fd3e8289
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 05:49:25 2009 +0000
add a hack to lower MOV16r0 to MOV32r0 in MCInstLower, eliminating
the problem with subreg32 modifiers. This gets all of Olden working
with the new asmprinter.
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commit 926c3ff188a32c57f740994172fc2cde75504dfd
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 8 05:46:28 2009 +0000
Fix typo that worked on python 2.6.
Also, fix unit tests.
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commit 6ed791867cfb7fe82e3f9dd512efe4e33c4f6f51
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Tue Sep 8 05:46:15 2009 +0000
Hoist out the test+insert to CheckedTypes. This doesn't seem to affect
performance.
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commit c6be620e43ce72f3e7c4a0acf3f8d05020c5c536
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 8 05:37:51 2009 +0000
Fix a refactoro.
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commit 12ffa4de8df01f0dc0533945d05ea8466d79c104
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 8 05:31:44 2009 +0000
Add 'lit' support for llvm tests.
- This adds 'make check-lit' from the top-level Makefile.
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commit fb15e592d9d89cf2ad3949ecc601848c5d930f0f
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 8 05:31:18 2009 +0000
Add 'lit' testing tool.
- make install && man $(llvm-config --prefix)/share/man/man1/lit.1 for more
information.
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commit 599c392e8d93a229de7d1a6a7182b40e33791f3c
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 05:15:50 2009 +0000
llvm::cerr is gone.
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commit 1efd4fd6a1b967fc3f0dbbd0d9c835ea5eec4f21
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 05:14:44 2009 +0000
update this to use raw_ostream
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commit c3195875c346108303d315cac0c245d80f980dfb
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 04:55:44 2009 +0000
fix PR4767, a crash because fp stackifier visited blocks in
depth first order, so it wouldn't process unreachable blocks.
When compiling at -O0, late dead block elimination isn't done
and the bad instructions got to isel.
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commit d069a058917c5968774064354516f628159971c6
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 03:47:41 2009 +0000
remove a turd
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commit 1ba36b786d8c051e764fb39e0c2503ba1f19dc92
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 03:44:51 2009 +0000
instcombine transforms vector loads that are only used by
extractelement operations into a bitcast of the pointer,
then a gep, then a scalar load. Disable this when the vector
only has one element, because it leads to infinite loops in
instcombine (PR4908).
This transformation seems like a really bad idea to me, as it
will likely disable CSE of vector load/stores etc and can be
better done in the code generator when profitable. This
goes all the way back to the first days of packed types,
r25299 specifically.
I'll let those people who care about the performance of vector
code decide what to do with this.
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commit a48dd11cea464022adf7c557c46b28abf148283a
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 03:39:55 2009 +0000
fix pasto
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commit 1e63feec4518f1c1d86121cd8f7957cf1211f720
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 03:32:53 2009 +0000
add getVectorOperand/getIndexOperand accessors to ExtractElementInst.
Fix some const correctness problems in SelectInst.
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commit 134e5d925b66c14c38438c0beca9b0f3bc30db47
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Tue Sep 8 02:02:39 2009 +0000
Simplify from my last change. Assert1 is a macro that makes its caller return,
so "Assert1(isa<>); cast<>" is a valid idiom.
Actually check the PHI node's odd-numbered operands for BasicBlock-ness, like
the comment said.
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commit 1b9f83a3e87d2b6cbcf1af525f0b1796c17fd571
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 8 01:44:02 2009 +0000
Fix an abort on a store of an empty struct member. getValue returns
null in the case of an empty struct, so don't try to call getNumValues
on it.
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commit d95bc887780e7af86abcf45c64d8772936ed6475
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Tue Sep 8 01:23:52 2009 +0000
Verify types. Invalid types can be constructed when assertions are off.
Make the verifier more robust by avoiding unprotected cast<> calls. Notably,
Assert1(isa<>); cast<> is not safe as Assert1 does not terminate the program.
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commit d9ac5deabfa68d437de63461d45b9c2912f527b9
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 01:22:54 2009 +0000
fix PR4915, a crash in -debug mode.
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commit 4a748b0f120835f4e83b77cfa761b504125ec817
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 00:27:14 2009 +0000
Fix PR4882, by making MemCpyOpt not dereference removed stores to get the
context for the newly created operations.
Patch by Jakub Staszak!
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commit 1698f255e9973fbc44b66852770e289db3abfa83
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 00:13:52 2009 +0000
fix ComputeMaskedBits handling of zext/sext/trunc to work with vectors.
This fixes PR4905
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commit 6e27672525f06113d206f961212ccd7db9226240
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 8 00:06:16 2009 +0000
add some comments to describe the invariants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81173 91177308-0d34-0410-b5e6-96231b3b80d8
commit f3a08b82db22aa66dd10f9a939993c7797baf32e
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 7 23:54:19 2009 +0000
Reappy r80998, now that the GlobalOpt bug that it exposed on MiniSAT is fixed.
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commit c4d34a74cd602a2a0438efade40a536d67ed38a3
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 7 23:47:14 2009 +0000
Fix a thinko: When lowering fneg with xor, bitcast the operands
from floating-point to integer first, and bitcast the result
back to floating-point. Previously, this test was passing by
falling back to SelectionDAG lowering. The resulting code isn't
as nice, but it's correct and CodeGen now stays on the fast path.
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commit 466291fd5924c11599be837375214d41ef7f518a
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 7 23:33:52 2009 +0000
add some more notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81170 91177308-0d34-0410-b5e6-96231b3b80d8
commit fda03491a5933cb61d0c6a54edba4fac12b651e2
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 7 23:04:59 2009 +0000
Add a testcase for the GlobalOpt inbounds fix.
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commit 3d72cd8e173b1424d6e41eae1494268e457dc718
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 7 22:52:39 2009 +0000
describe undef semantics in some more detail.
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commit dabbeec685c1fa912aebc208f715ba9ee92a0899
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 7 22:45:41 2009 +0000
Add inbounds to these getelementptrs, now that GlobalOpt requires this,
to preserve the meaning of these tests.
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commit c2723ad812300b525b77334a4180d3531613ae3e
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 7 22:44:55 2009 +0000
Don't commit stores with addresses that have indices that are not
compile-time constant integers or that are out of bounds for their
corresponding static array types. These can cause aliasing that
GlobalOpt assumes won't happen.
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commit 9524ee6fbbe252887fc957b2d5612318abed5171
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 7 22:42:05 2009 +0000
Don't commit addresses of aggregate values. This avoids problems with
an aggregate store overlapping a different aggregate store, despite
the stores having distinct addresses.
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commit 0c834c07335e47546df1d9ef10f79b69cfee7651
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 7 22:40:13 2009 +0000
Fix GlobalOpt to avoid committing a store if the address getelementptr
is missing the inbounds flag. This is slightly conservative, but it
avoids problems with two constants pointing to the same address but
getting distinct entries in the Memory DenseMap.
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commit 6d907d00498eaaa2bf0d176adf73f66c0c80d8e8
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 7 22:34:43 2009 +0000
Preserve the InBounds flag when evaluating a getelementptr instruction
into a getelementptr ConstantExpr.
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commit 278fbe6ee2d970a5379dbeb8cf4e55a54e0421d6
Author: Dan Gohman <gohman at apple.com>
Date: Mon Sep 7 22:31:26 2009 +0000
Simplify this code by using hasDefinitiveInitializer().
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commit 706e47f84bb290a91bf2147c9e7f5c77deb6558f
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 7 22:15:23 2009 +0000
tighten test.
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commit 542cd205d82f4d38208ea64aed56c38434381539
Author: Chris Lattner <sabre at nondot.org>
Date: Mon Sep 7 22:14:41 2009 +0000
tweak test, add PR#
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commit 13c337ae0c3af6cadefd022baab370e558c00685
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Mon Sep 7 21:50:24 2009 +0000
Express this in the canonical way.
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commit f9c2f24ff7c9803f68be9a2dbf53c5157cf77c30
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Mon Sep 7 20:44:51 2009 +0000
Homogenize whitespace.
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commit 7201b61a736089675ab6bd04bd5fe92d9b42b76d
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 7 19:26:18 2009 +0000
Use -output-prefix in bugpoint tests so that outputs go in temp directory (and
we don't race on them).
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commit 377b5a388198dcfdba040b77352c6b4b2c7f577a
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 7 19:26:11 2009 +0000
Add -output-prefix option to bugpoint (to change the default output name).
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commit 741507d7505493a7b270ba9146f0ed6eeb1a27f8
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 7 19:26:02 2009 +0000
Don't depend on Tcl behavior of redirecting stderr for all commands in a
pipeline.
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commit 45983257e95b1350100ed50a1e207eb73db58ac8
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 7 19:25:54 2009 +0000
Avoid Tcl substitution, introduced %llvmgcc_only for this one little test
(%llvmgcc includes a '-w' argument, and this test looks for warnings).
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commit 104b3ff2dbe1f6e8f3b06f2027774ea79fca204e
Author: Duncan Sands <baldrick at free.fr>
Date: Mon Sep 7 05:58:25 2009 +0000
Using a signal handler that does nothing should be
equivalent to SIG_IGN.
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commit 6b778fd333ad44d9f1a8c05bc98fd42f5afc5b42
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 7 04:19:02 2009 +0000
Update unittests for MDNode uniquing disable.
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commit 41160673bbfa67301f5a3768d624a9bed81812b3
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 7 04:05:49 2009 +0000
Disable MDNode uniquing.
- Hopefully this unbreaks some llvm-gcc bootstraps.
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commit 1c40a1e0e73319536107388601b864e004cef4ad
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Sep 7 04:03:44 2009 +0000
Document opt -S argument.
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commit e187ef9ba5db756647acb2aff91123328e8feb38
Author: Eric Christopher <echristo at apple.com>
Date: Sun Sep 6 22:20:54 2009 +0000
Fix comment.
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commit 978451f1282a624bc18ae4daf3a1d2a4e32912e1
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Sun Sep 6 20:21:48 2009 +0000
Do not create calls via PLT in compilation callback - this is higly platform
dependent. Hopefully, this will fix PR3801.
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commit 65316a37fbf3d14b68a6f6812a429eac9ec82f3f
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 20:02:00 2009 +0000
Do not try to override non-virtual methods, especially
when the new method gives the same result as the original
(as far as I can see). This will hopefully pacify icc.
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commit 831102e53292a8cd36907a32ec96630bc5819378
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 19:29:07 2009 +0000
Remove a left over bit of code with no effect.
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commit 00caa72006e1ba4b2897461187fb18c060a36369
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 19:28:38 2009 +0000
Avoid warnings if assertions are off.
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commit 8297d720b3983c946376e590cfbac5918078a4af
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 19:27:53 2009 +0000
Remove unreachable code.
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commit 950b9861ba3a7964bc911df9b97fa8d136e0bcd5
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 18:03:32 2009 +0000
Simplify. Testing shows that this is not equivalent to BBI = CR.CaseBB + 1.
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commit e0a6add2ae24cc9270fc5c85b16a8836d9278064
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 16:27:34 2009 +0000
Avoid an unused variable warning when assertions are
disabled.
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commit fbc8e46ee99c6bc13b4cef2dabea28fa578f6c52
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 13:10:36 2009 +0000
Change "const static" to "static const", as warned about
by icc (#82). Patch by Erick Tryzelaar.
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commit dc94fb91bc0e3dba99c31b3b7f3b8e5048b0e137
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 12:56:52 2009 +0000
Mark more constants unsigned, as warned about by icc (#68).
Patch by Erick Tryzelaar.
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commit 05db668fe21feee223e19fe50ddeb6456ddebafb
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 12:41:19 2009 +0000
Remove some not-really-used variables, as warned
about by icc (#593, partial). Patch by Erick Tryzelaar.
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commit 7ac0e8af264c4ab82fb663d342011dfd18d4572d
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Sun Sep 6 12:26:28 2009 +0000
More MSVC warning fixes:
1. DUPMAX is defined in regcomp.c, no need to redefine it in regutils.
2. MSVC doesn't like snprintf, use _snprintf instead.
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commit cd67298c9746bc1e4ac6f730f7d10122f00072c1
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 12:16:26 2009 +0000
Remove strange 'const' qualifiers, as warned about by icc
(#411). Patch by Erick Tryzelaar.
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commit 0db71af6ee5f1ed8495222226db9e4c85eef4805
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Sun Sep 6 12:10:17 2009 +0000
It's a bool, so treat it like one. Fixes a MSVC warning.
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commit f6e467911587ca54f496958b9e844d566667017b
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 11:45:14 2009 +0000
Mark constants as unsigned, as pointed out by icc
warnings (#174). Patch by Erick Tryzelaar.
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commit 3872b7ec9730d0492e40ab8c279dd8d397d71d42
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 10:53:22 2009 +0000
Tweak code into an equivalent form for which icc
doesn't warn about unreachable instructions. Patch
by Erick Tryzelaar (#111).
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commit a118e65f108d5222f359ff32d24a27bdcaf27eb1
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Sun Sep 6 09:35:10 2009 +0000
Fix an integer truncation noticed by MSVC.
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commit defe7950099b9f472d0dc03d621b1c8cd72ecc4d
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Sun Sep 6 09:29:39 2009 +0000
Remove splint hints to silence warnings from ICC and MSVC.
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commit e0223c296633ecaa5712c129a4cab7a0d6a3a9bf
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 08:55:57 2009 +0000
Public and private corrections, warned about by icc (#304).
Patch by Erick Tryzelaar.
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commit 5c3f915679bede35de38a5702359ab5befc38b95
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 08:33:48 2009 +0000
Remove some unused variables and methods warned about by
icc (#177, partial). Patch by Erick Tryzelaar.
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commit bbfc76d44f8db3457b24e4c2fdfe0f7774a815a5
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Sep 6 07:23:28 2009 +0000
Remove unneeded declaration, as warned about by
icc (#1170). Patch by Erick Tryzelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81104 91177308-0d34-0410-b5e6-96231b3b80d8
commit cb834e9b6313111b17d9d8ee62ffe3cdf75568f8
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 6 02:31:36 2009 +0000
Fix a possible crash call setIsInBounds.
- I think there are more instances of this, but I think they are fixed in Dan's
incoming patch. This one was preventing me from doing a bugpoint reduction
though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81103 91177308-0d34-0410-b5e6-96231b3b80d8
commit 610b1c2a518c8aba64f3e0967b7fd5442efce0b7
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 6 02:31:26 2009 +0000
Simplify, now that gtest supports raw_ostream directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81102 91177308-0d34-0410-b5e6-96231b3b80d8
commit ed6987d5e1669a0dec12cb470c38a0340ceabb7d
Author: Evan Cheng <evan.cheng at apple.com>
Date: Sun Sep 6 02:26:10 2009 +0000
Revert r80926. It causes loop unswitch assertion and slow down some JIT tests significantly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81101 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4f3451886cd728c60d38f8eec7b6608acc684cc6
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 6 00:11:24 2009 +0000
Revert "Include optional subclass flags, such as inbounds, nsw, etc., ...", this
breaks MiniSAT on x86_64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81098 91177308-0d34-0410-b5e6-96231b3b80d8
commit b7fb353614ccc2574e85f2f4d972e5b452c0e6ec
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sun Sep 6 00:00:13 2009 +0000
Fix spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81097 91177308-0d34-0410-b5e6-96231b3b80d8
commit 6fb7ceecb1b05ddf1c78d5be285fcf38499bbcdf
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Sat Sep 5 18:27:40 2009 +0000
Now that googletest can print ConstantRange, use EXPECT_EQ when testing for
equality. Prefer EXPECT_EQ(foo, Full) over EXPECT_TRUE(foo.isFullSet()) because
the former will print out the contents of the constant range that failed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81094 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2539a0fd5649cc11926e0f8207c871509a064fc0
Author: Jeffrey Yasskin <jyasskin at google.com>
Date: Sat Sep 5 18:16:17 2009 +0000
Teach googletest to use raw_ostream instead of just std::ostream.
This can break when there are implicit conversions from types raw_ostream
understands but std::ostream doesn't, but it increases the number of cases that
Just Work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81093 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3a5a153ce6ed9029a7a27f45b531a434c6139a40
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 5 12:38:44 2009 +0000
Quote another '%S' in a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81088 91177308-0d34-0410-b5e6-96231b3b80d8
commit 568d974702d7ebfc70a6dfae1fae5d69ed6b9d7a
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 5 12:38:35 2009 +0000
Rename %S metavar to %M (clang uses %S for the basename of the test file).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81087 91177308-0d34-0410-b5e6-96231b3b80d8
commit c6af8408bd6fa8a5517b8f282f8f4519ccf1a7d4
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 5 12:38:26 2009 +0000
Temporary test files should use %t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81086 91177308-0d34-0410-b5e6-96231b3b80d8
commit f0edd5030da5e7f16bf7ae7728c55205bc2a45e7
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 5 11:53:06 2009 +0000
Don't depend on arch specific global prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81084 91177308-0d34-0410-b5e6-96231b3b80d8
commit b994d02f07d52dbb7876d2c273a278bf24d7cd22
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 5 11:35:16 2009 +0000
Eliminate uses of %prcontext.
- I'd appreciate it if someone else eyeballs my changes to make sure I captured
the intent of the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81083 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1a34ea6046da3f1645557e43e90ba92699ced486
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 5 11:34:53 2009 +0000
opt: Add -S option to print output as LLVM assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81082 91177308-0d34-0410-b5e6-96231b3b80d8
commit 0b4b45c440ef66927923db8c90555f4a84ad1b93
Author: Daniel Dunbar <daniel at zuster.org>
Date: Sat Sep 5 11:34:46 2009 +0000
Eliminate some Tclisms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81081 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2d876ee1f15217f2a537041f8d1e721dc8c20dc3
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Sat Sep 5 08:50:14 2009 +0000
Delete unused #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81076 91177308-0d34-0410-b5e6-96231b3b80d8
commit e509b44f6964be58d9d5204589d0e68b6ed9c432
Author: Bob Wilson <bob.wilson at apple.com>
Date: Sat Sep 5 01:19:16 2009 +0000
Stabilize the order of live intervals in the priority_queue used by the
linear scan reg alloc. This fixes a problem I ran into where extracting
a function from a larger file caused the generated code to change (masking
the problem I was trying to debug) because the allocator behaved differently.
This changes the results for two X86 regression checks. stack-color-with-reg
is improved, with one less instruction, but pr3495 is worse, with one more
copy. As far as I can tell, these tests were just getting lucky or unlucky,
so I've changed the expected results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81060 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5290ac201f2bd669d8e09cfc45f98b6f39784324
Author: Devang Patel <dpatel at apple.com>
Date: Sat Sep 5 00:34:14 2009 +0000
Detect VLAs.
Do not use DenseMap operator[] because it inserts new entry if lookup fails. Use find() to check an entry in a DenseMap first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81058 91177308-0d34-0410-b5e6-96231b3b80d8
commit 0c03f0626103c650db38940c5edf806648f6895d
Author: Devang Patel <dpatel at apple.com>
Date: Fri Sep 4 23:59:07 2009 +0000
Ignore malformed global variable debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81055 91177308-0d34-0410-b5e6-96231b3b80d8
commit 239b5780eeee253127897d0bcfe0386c483b784d
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Fri Sep 4 22:45:23 2009 +0000
Prune #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81052 91177308-0d34-0410-b5e6-96231b3b80d8
commit 92469fe6cc59a9f06e4d9f26d0047a6702dec6f3
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Fri Sep 4 22:44:03 2009 +0000
Remove an unneeded call to c_str().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81051 91177308-0d34-0410-b5e6-96231b3b80d8
commit 71743a46b89750f45c71aa694c103c86c247c040
Author: Kevin Enderby <enderby at apple.com>
Date: Fri Sep 4 22:40:31 2009 +0000
Added AsmToken enum constants to MCAsmLexer.h for '[', ']', '{', and '}' in
preparation of supporting other targets. Then changed the lexer to parse these
as tokens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81050 91177308-0d34-0410-b5e6-96231b3b80d8
commit 685689cae6703e4ca9fce5805b44e99ca8047d4e
Author: Kevin Enderby <enderby at apple.com>
Date: Fri Sep 4 21:45:34 2009 +0000
Added the AsmToken::Hash enum constant to MCAsmLexer.h in preparation of
supporting other targets. Changed the code to pass MCAsmInfo to the parser
and the lexer. Then changed the lexer to use CommentString from MCAsmInfo
instead of a literal '#' character.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81046 91177308-0d34-0410-b5e6-96231b3b80d8
commit 08fe10526f25d21437fd484b007a6ab772ef794d
Author: Devang Patel <dpatel at apple.com>
Date: Fri Sep 4 21:32:05 2009 +0000
While replacing an MDNode elment, properly update MDNode's operand list.
MDNode's operand list does not include all elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81045 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1573308b6dd6e548c3ac70d740579db0fb086c67
Author: Andreas Neustifter <astifter at gmx.at>
Date: Fri Sep 4 21:22:04 2009 +0000
Prevent warnings on compilers for which its not clear that assert won't return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81044 91177308-0d34-0410-b5e6-96231b3b80d8
commit 056fc97aaab9f2ae097ee243175fb21a871b5462
Author: Lang Hames <lhames at gmail.com>
Date: Fri Sep 4 21:03:07 2009 +0000
Removed yet another std::ostream reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81042 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5cd57b09b71bd03b36c5d64707d50d05ca34618c
Author: Lang Hames <lhames at gmail.com>
Date: Fri Sep 4 20:54:51 2009 +0000
Removed some junk and a std::ostream operator that was hanging around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81041 91177308-0d34-0410-b5e6-96231b3b80d8
commit d8f309943c6c05daa9e23f7bcb08cf5c18eb4a26
Author: Lang Hames <lhames at gmail.com>
Date: Fri Sep 4 20:41:11 2009 +0000
Replaces uses of unsigned for indexes in LiveInterval and VNInfo with
a new class, MachineInstrIndex, which hides arithmetic details from
most clients. This is a step towards allowing the register allocator
to update/insert code during allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81040 91177308-0d34-0410-b5e6-96231b3b80d8
commit d98806736fb1505ccad81879fdddb2cbd0ab4880
Author: Dale Johannesen <dalej at apple.com>
Date: Fri Sep 4 20:19:09 2009 +0000
Test for llvm-gcc commit 81037.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81038 91177308-0d34-0410-b5e6-96231b3b80d8
commit 19da904e44d1f35af13c72f0fc3bdd9ec3a0ba73
Author: Andreas Neustifter <astifter at gmx.at>
Date: Fri Sep 4 17:21:59 2009 +0000
Updated tests to use ProfileVerifer to test ProfileLoader and ProfileEstimator.
(Keep disabled test disabled until selfhosted build issue is resolved.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81008 91177308-0d34-0410-b5e6-96231b3b80d8
commit c2ae05a1c31ecc161fa2ddfec4d1ce8a7fc5c2eb
Author: Andreas Neustifter <astifter at gmx.at>
Date: Fri Sep 4 17:15:10 2009 +0000
Cleaned up ProfileVerifierPass.
(See http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090831/086219.html)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81007 91177308-0d34-0410-b5e6-96231b3b80d8
commit 68eca1aeb53324309e2cc7ec68a91423ec2e41e3
Author: Andreas Neustifter <astifter at gmx.at>
Date: Fri Sep 4 12:34:44 2009 +0000
Converted MaximumSpanningTree algorithm to a generic template, this could go
into llvm/ADT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81001 91177308-0d34-0410-b5e6-96231b3b80d8
commit 99da1c065b2d6e4c4a175ec585b7e24f0f8f453a
Author: Dan Gohman <gohman at apple.com>
Date: Fri Sep 4 12:08:11 2009 +0000
Include optional subclass flags, such as inbounds, nsw, etc., in the
Constant uniquing tables. This allows distinct ConstantExpr objects
with the same operation and different flags.
Even though a ConstantExpr "a + b" is either always overflowing or
never overflowing (due to being a ConstantExpr), it's still necessary
to be able to represent it both with and without overflow flags at
the same time within the IR, because the safety of the flag may
depend on the context of the use. If the constant really does overflow,
it wouldn't ever be safe to use with the flag set, however the use
may be in code that is never actually executed.
This also makes it possible to merge all the flags tests into a single test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80998 91177308-0d34-0410-b5e6-96231b3b80d8
commit 680c2a0652497c5b9b550a147c96e506facb854b
Author: Duncan Sands <baldrick at free.fr>
Date: Fri Sep 4 11:59:43 2009 +0000
Use delete[] to match new[] (found by valgrind).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80997 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9dcb760ccdb1e1418afe31c42e6b26d663b00cbf
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Sep 4 07:47:40 2009 +0000
Run branch folding if if-converter make some transformations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80994 91177308-0d34-0410-b5e6-96231b3b80d8
commit 368ddcb5b8995476324018aed319e36085de3411
Author: Evan Cheng <evan.cheng at apple.com>
Date: Fri Sep 4 07:46:30 2009 +0000
Fix comment for consistency sake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80993 91177308-0d34-0410-b5e6-96231b3b80d8
commit 02d88831d19f9f0a81518af2db01e206aaa26473
Author: Daniel Dunbar <daniel at zuster.org>
Date: Fri Sep 4 05:07:52 2009 +0000
Remove stale greps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80986 91177308-0d34-0410-b5e6-96231b3b80d8
commit b273bb5cd6ff131f608ec09f581d7db23d8cb530
Author: Daniel Dunbar <daniel at zuster.org>
Date: Fri Sep 4 05:07:44 2009 +0000
Update lib deps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80985 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5d7babb3ed71916bf46f347d4ff0e0ea2a809c15
Author: Bob Wilson <bob.wilson at apple.com>
Date: Fri Sep 4 04:07:19 2009 +0000
Convert tests to FileCheck.
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commit 9c2ed5cff22b49e07be176f3d4830b5bc67739c6
Author: Jim Grosbach <grosbach at apple.com>
Date: Fri Sep 4 01:38:51 2009 +0000
Whitespace cleanup
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commit 24fd31656faf1f70c5e4ade5b6462b2e66465748
Author: Eric Christopher <echristo at apple.com>
Date: Fri Sep 4 01:14:14 2009 +0000
If there's a calling convention attach it to the rewind function call.
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commit 4d47c5af7087d582a2ae89641051543689e2026b
Author: Bob Wilson <bob.wilson at apple.com>
Date: Fri Sep 4 00:32:31 2009 +0000
Convert a test to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80975 91177308-0d34-0410-b5e6-96231b3b80d8
commit fe0a279423e23454b9f41d59d2a86340fdceb8a8
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Sep 3 23:54:22 2009 +0000
Funky indentation.
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commit 146162cd340e559a31b8a3e3f67d358587a0f985
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 3 23:40:10 2009 +0000
Revert "--- Reverse-merging r80908 into '.':", I already "fixed" this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80970 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1046e41998ac9178d87226cb0869612c22f5c6d1
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 23:34:49 2009 +0000
Revert 80959. It isn't sufficient to solve the full problem. And it
introduced regressions in the Ocaml bindings tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80969 91177308-0d34-0410-b5e6-96231b3b80d8
commit c527d7e5a814b834aaece6e67d2447b9d2d2be5e
Author: Erick Tryzelaar <idadesub at users.sourceforge.net>
Date: Thu Sep 3 23:27:31 2009 +0000
Replace ocamlc tests with ocamlopt tests since they're less noisy.
There's a bug with ocamlc that uses "char*" instead of "const char*" for
global string variables. This causes g++ to be very noisy when linking
ocamlc programs. That's why the ocaml test used to cat to /dev/null.
ocamlopt doesn't have this problem, so we can get rid of the >/dev/null,
which may obscure some problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80968 91177308-0d34-0410-b5e6-96231b3b80d8
commit e76bfd9f87d7255a4f0940e3a5f911e22cba7f6c
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 3 23:13:46 2009 +0000
--- Reverse-merging r80908 into '.':
D test/Analysis/Profiling
--- Reverse-merging r80907 into '.':
U lib/Analysis/ProfileInfoLoaderPass.cpp
Attempt to remove failure in the self-hosting build bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80966 91177308-0d34-0410-b5e6-96231b3b80d8
commit f3ff0b0ad79a27cbcfbfa456ae031b310bd64d63
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 3 22:57:02 2009 +0000
Add test for PR4873, which works for me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80965 91177308-0d34-0410-b5e6-96231b3b80d8
commit f154271b8e81b6fc65137b7fda7c935b9fe93203
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 22:53:57 2009 +0000
LLVM currently represents floating-point negation as -0.0 - x. Fix
FastISel to recognize this pattern and emit a floating-point
negation using xor.
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commit 598ea31a7440ad0fae45e9fd4d7d640c431ef030
Author: David Goodwin <david_goodwin at apple.com>
Date: Thu Sep 3 22:48:51 2009 +0000
Don't crash when target has no itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80962 91177308-0d34-0410-b5e6-96231b3b80d8
commit c9ca26dded387110e8c7520f52bd635eb483d1ec
Author: Bill Wendling <isanbard at gmail.com>
Date: Thu Sep 3 22:19:22 2009 +0000
If we've pushed registers onto the stack, but aren't adjusting the stack pointer
(i.e., there are no local variables and stuff), we still need to output FDE
information for the pushed registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80960 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2f2ab4797b28ede081fda36855a26e8ec1b9357e
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 22:17:40 2009 +0000
Remove the API for creating ConstantExprs with the nsw, nuw, inbounds,
and exact flags. Because ConstantExprs are uniqued, creating an
expression with this flag causes all expressions with the same operands
to have the same flag, which may not be safe. Add, sub, mul, and sdiv
ConstantExprs are usually folded anyway, so the main interesting flag
here is inbounds, and the constant folder already knows how to set the
inbounds flag automatically in most cases, so there isn't an urgent need
for the API support.
This can be reconsidered in the future, but for now just removing these
API bits eliminates a source of potential trouble with little downside.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80959 91177308-0d34-0410-b5e6-96231b3b80d8
commit 856b38c3e9341ed6667788eb3c923be358ac5b71
Author: David Goodwin <david_goodwin at apple.com>
Date: Thu Sep 3 22:15:25 2009 +0000
Create our own block initializer for kill fixups as the scheduling one wasn't doing the right thing.
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commit 3d88e9179113826d90cfe1653b8497e59798858b
Author: David Goodwin <david_goodwin at apple.com>
Date: Thu Sep 3 22:12:28 2009 +0000
Calls clobber FPSCR.
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commit 637600a68adadef8e2f835a18a1193c6f8a1f0b5
Author: Ted Kremenek <kremenek at apple.com>
Date: Thu Sep 3 22:07:30 2009 +0000
Make ImmutableMap/ImmutableSet quicker by only canonicalizing the tree after an
Add or Remove operation complete, and not while building the intermediate tree.
This trades a little bit more memory usage for less accesses to the FoldingSet. On a benchmark for the clang static analyzer, this shaves off another 13% of execution time when using field/array sensitivity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80955 91177308-0d34-0410-b5e6-96231b3b80d8
commit bb45a492cfcb01b632213cf5e88f839f2ffb7a68
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 3 21:09:53 2009 +0000
Disable some parts of the profiling-tool-chain test, which is currently failing
on a self-hosted build (although it seems to work on non-self hosted). I'll work
with Andreas to figure this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80947 91177308-0d34-0410-b5e6-96231b3b80d8
commit c653c95f431b4526287d26cb7b5c16860d61ab0a
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 3 20:59:02 2009 +0000
Remove dead greps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80946 91177308-0d34-0410-b5e6-96231b3b80d8
commit fa196cc6a40c2f1146f336ee904688ab37d9ac0e
Author: Bob Wilson <bob.wilson at apple.com>
Date: Thu Sep 3 20:58:42 2009 +0000
Overhaul the TwoAddressInstructionPass to simplify the logic, especially
for the complicated case where one register is tied to multiple destinations.
This avoids the extra scan of instruction operands that was introduced by
my recent change. I also pulled some code out into a separate
TryInstructionTransform method, added more comments, and renamed some
variables.
Besides all those changes, this takes care of a FIXME in the code regarding
an assumption about there being a single tied use of a register when
converting to a 3-address form. I'm not aware of cases where that assumption
is violated, but the code now only attempts to transform an instruction,
either by commuting its operands or by converting to a 3-address form,
for the simple case where there is a single pair of tied operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80945 91177308-0d34-0410-b5e6-96231b3b80d8
commit ff6a63a57697e8f76e9188b34bc75486528e04ba
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 20:36:13 2009 +0000
Smallvectorize switchExitBlocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80942 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9f876cd88bcf8204ec52dfb03a474a154ad60617
Author: Devang Patel <dpatel at apple.com>
Date: Thu Sep 3 20:35:57 2009 +0000
There is not any need to copy metadata while merging modules.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80941 91177308-0d34-0410-b5e6-96231b3b80d8
commit 41b3f4abc695b3ce178e1db7610b34d3745ed22d
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 20:34:31 2009 +0000
Recognize more opportunities to use SSE min and max instructions,
swapping the operands if necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80940 91177308-0d34-0410-b5e6-96231b3b80d8
commit bc3c526a5b0a6c97231ab1af117053fc2c89c491
Author: Mon P Wang <wangmp at apple.com>
Date: Thu Sep 3 19:57:35 2009 +0000
Test cases for vector shifts changes r80935
Changed the old vector shift test to use FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80936 91177308-0d34-0410-b5e6-96231b3b80d8
commit 04c767e3a81142583c41927d68387f8663cda8e8
Author: Mon P Wang <wangmp at apple.com>
Date: Thu Sep 3 19:56:25 2009 +0000
Fixed a few problems with vector shifts
- when transforming a vector shift of a non-immediate scalar shift amount, zero
extend the i32 shift amount to i64 since the vector shift reads 64 bits
- when transforming i16 vectors to use a vector shift, zero extend i16 shift amount
- improve the code quality in some cases when transforming vectors to use a vector shift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80935 91177308-0d34-0410-b5e6-96231b3b80d8
commit e84197bc92efd8ee0a1ac63324783d6fcaf0ffd7
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 17:18:51 2009 +0000
Add a -disable-16bit flag and associated support for experimenting with
disabling the use of 16-bit operations on x86. This doesn't yet work for
inline asms with 16-bit constraints, vectors with 16-bit elements,
trampoline code, and perhaps other obscurities, but it's enough to try
some experiments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80930 91177308-0d34-0410-b5e6-96231b3b80d8
commit e71842bebb922af77f158cf2bb577575b51a4219
Author: Kevin Enderby <enderby at apple.com>
Date: Thu Sep 3 17:15:07 2009 +0000
Removed the non-target independent AsmToken::Register enum constant
from MCAsmLexer.h in preparation of supporting other targets. Changed the
X86AsmParser code to reflect this by removing AsmLexer::LexPercent and looking
for AsmToken::Percent when parsing in places that used AsmToken::Register.
Then changed X86ATTAsmParser::ParseRegister to parse out registers as an
AsmToken::Percent followed by an AsmToken::Identifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80929 91177308-0d34-0410-b5e6-96231b3b80d8
commit fb4fa6f860001c6f6663a5c782fae0fa0e83717b
Author: Devang Patel <dpatel at apple.com>
Date: Thu Sep 3 17:03:47 2009 +0000
Use WeakVH to hold dead mdnodes. Check use_empty() before deleting a node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80928 91177308-0d34-0410-b5e6-96231b3b80d8
commit 024ec13192dc9720da09edad698851bddf699c70
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 16:32:58 2009 +0000
Make bugpoint use ParseIRFile instead of doing the same thing manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80927 91177308-0d34-0410-b5e6-96231b3b80d8
commit da313a3723d8fa74893b2b902719daf1b0021e67
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 16:31:42 2009 +0000
Add a verifyAnalysis to LoopInfo, LoopSimplify, and LCSSA form that verify
that these passes are properly preserved.
Fix several transformation passes that claimed to preserve LoopSimplify
form but weren't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80926 91177308-0d34-0410-b5e6-96231b3b80d8
commit bad01c4020d7f8048903b13ad2457323f5ab0359
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 16:11:53 2009 +0000
Remove some unnecessary -f options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80924 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5c42c875f7b8a18b3f3945bf52bbab2fa59450c3
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 16:10:48 2009 +0000
Move getUniqueExitBlocks from LoopBase to Loop, since they depend on
LoopSimplify form, which is currently only available on Loops (and
not MachineLoops). Also, move the code out of the header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80923 91177308-0d34-0410-b5e6-96231b3b80d8
commit fb17470d7382d820c535988315c65da4e9de0b48
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 16:00:08 2009 +0000
Use IRReader.h in opt, to support reading of LLVM Assembly files directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80922 91177308-0d34-0410-b5e6-96231b3b80d8
commit 798e541fbdd6cdc2da6e6f153b3704d350bd3167
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 15:34:35 2009 +0000
Change PHINode::hasConstantValue to have a DominatorTree argument
instead of a bool argument, and to do the dominator check itself.
This makes it eaiser to use when DominatorTree information is
available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80920 91177308-0d34-0410-b5e6-96231b3b80d8
commit 242b4738d28335a58e08db01c2748d0488885348
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 15:09:24 2009 +0000
Don't try to verify a LoopPass analysis if the loop has been deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80919 91177308-0d34-0410-b5e6-96231b3b80d8
commit f925d7f97fdec5c23250d06d3f93ab41f58afb3f
Author: Dan Gohman <gohman at apple.com>
Date: Thu Sep 3 15:00:26 2009 +0000
Remove references to expression "handles", which are no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80918 91177308-0d34-0410-b5e6-96231b3b80d8
commit d809156d5c860a90cf7b1a8dfb9db62dcc5e6f06
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Thu Sep 3 14:58:24 2009 +0000
CppBackend: avoid printing unnecessary whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80917 91177308-0d34-0410-b5e6-96231b3b80d8
commit c50fa7ec0a396461d9addda9b078560e0a7d0e41
Author: Duncan Sands <baldrick at free.fr>
Date: Thu Sep 3 13:37:16 2009 +0000
Keep track of how many memmove calls were turned into
memcpy calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80915 91177308-0d34-0410-b5e6-96231b3b80d8
commit 551c462cc936f64e1462b7a973e54e340ae657a4
Author: Andreas Neustifter <astifter at gmx.at>
Date: Thu Sep 3 09:11:10 2009 +0000
Fix build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80912 91177308-0d34-0410-b5e6-96231b3b80d8
commit 34dd111c5c8a54d2b512999eb5179d42a746cf30
Author: Andreas Neustifter <astifter at gmx.at>
Date: Thu Sep 3 08:52:52 2009 +0000
Code Cleanup.
Removed inverted flag form MaximumSpanningTree, also do not handle so much
information to MaximumSpanningTree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80911 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3b8513dd94dfd5246166b2762638c05bb5b3a01a
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 3 08:41:19 2009 +0000
Filter out -fno-rtti from CXXFLAGS as well (in an expensive checks build).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80910 91177308-0d34-0410-b5e6-96231b3b80d8
commit 36079a8ecc6c65b737304e18dce9c336704a0200
Author: Andreas Neustifter <astifter at gmx.at>
Date: Thu Sep 3 08:41:05 2009 +0000
Code Cleanup.
(See http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090831/086139.html)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80909 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2b503ff0f62f1359cfc0f35ad36a376296c43b32
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 3 07:38:00 2009 +0000
Reapply profiling tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80908 91177308-0d34-0410-b5e6-96231b3b80d8
commit df7d5b1736f8fc99a8f5bedcd96559d099793d92
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 3 07:37:42 2009 +0000
Remove undefined behavior when loading optimal edge profile info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80907 91177308-0d34-0410-b5e6-96231b3b80d8
commit b55972f828465055a2e144cf74733abad3132534
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 07:36:42 2009 +0000
don't call getOffset() on jump tables, this fixes three failing olden benchmarks
with the new asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80906 91177308-0d34-0410-b5e6-96231b3b80d8
commit 02c96d78837bceaecb699bbd4e404403f8188c14
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 07:30:56 2009 +0000
Implement support for X86II::MO_GOT_ABSOLUTE_ADDRESS. We get very
different formatting from the old asmprinter, but it should be
semantically the same. We used to get:
popl %eax
addl $_GLOBAL_OFFSET_TABLE_ + [.-.Lllvm$6.$piclabel], %eax
...
Now we get:
popl %eax
.Lpicbaseref6:
addl $(_GLOBAL_OFFSET_TABLE_ + (.Lpicbaseref6 - .Lllvm$6.$piclabel)), %eax
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80905 91177308-0d34-0410-b5e6-96231b3b80d8
commit ba2cf3d635dcc68ac416f56b767fd79d77ea7c83
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Sep 3 07:04:02 2009 +0000
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80904 91177308-0d34-0410-b5e6-96231b3b80d8
commit 04791af064e508422996148f33ef1f5f48c29e5b
Author: Nick Lewycky <nicholas at mxc.ca>
Date: Thu Sep 3 06:43:15 2009 +0000
Remove VISIBILITY_HIDDEN from this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80903 91177308-0d34-0410-b5e6-96231b3b80d8
commit 93d228067020d3f32f6b45799ad394fa34b9b160
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 06:29:23 2009 +0000
merge all the basic linux/32 pic tests together into one test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80902 91177308-0d34-0410-b5e6-96231b3b80d8
commit c420c6c39eae9503d0a3054400fc5615b02bbf1c
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 06:16:49 2009 +0000
rename test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80901 91177308-0d34-0410-b5e6-96231b3b80d8
commit 53d76257db225c1ecc3de84096aae77c4493a962
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 06:15:11 2009 +0000
use a darwin triple
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80900 91177308-0d34-0410-b5e6-96231b3b80d8
commit c13d5b47266168db627ade3cf5a4157d61949af0
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 06:13:54 2009 +0000
TAI -> MAI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80899 91177308-0d34-0410-b5e6-96231b3b80d8
commit fba9e5022d361fa9d772c6b00881c8f1478f09ae
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 06:13:45 2009 +0000
adjust expected lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80898 91177308-0d34-0410-b5e6-96231b3b80d8
commit c5b06e6b2786ec34435e46720ba44a909193c018
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 06:00:00 2009 +0000
improve comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80897 91177308-0d34-0410-b5e6-96231b3b80d8
commit 648353a52f524287325e5f5af31aa88f40ed0f76
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 05:57:47 2009 +0000
fix MCSymbol printing to exactly match the normal mangler rules so
we can diff .s files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80894 91177308-0d34-0410-b5e6-96231b3b80d8
commit 90c1949efa972a6078654f6b766ff6b7808b3798
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 05:54:00 2009 +0000
remove extraneous hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80893 91177308-0d34-0410-b5e6-96231b3b80d8
commit 9cc58801a61ba37f4a90b6093ced685fa0197ff6
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 3 05:47:34 2009 +0000
Make these functions static and local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80892 91177308-0d34-0410-b5e6-96231b3b80d8
commit 43ba45cb0f893fd58a0a9f4e80bc455f36b6e46d
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 3 05:47:22 2009 +0000
Tweak comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80891 91177308-0d34-0410-b5e6-96231b3b80d8
commit 0fe3a1ed4567dfdd45125c95beed6c6b77be2088
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 05:46:51 2009 +0000
Thread an MCAsmInfo pointer through the various MC printing APIs,
and fix a few things using << on MCSymbols to use ->print(). No
functionality change other than unbreaking my previous patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80890 91177308-0d34-0410-b5e6-96231b3b80d8
commit ad1950e0138c65a6e0d329055b4f60402bc36cbb
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 05:39:09 2009 +0000
just use dump()
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commit 7c75f8d66dd9d6a2ff443ab2fbe16c4d30a8ea1e
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 05:33:01 2009 +0000
inline insertion operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80888 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2342099f65d7f45542126efa911117c0099a4f5d
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 05:19:59 2009 +0000
In C++, code is not allowed to call main. In C it is, this
simplifylibcalls optimization is thus valid for C++ but not C.
It's not important enough to worry about for C++ apps, so just
remove it.
rdar://7191924
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commit 3dccf61c7f1d8dbb338f4c0afa20408f53a095c8
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 05:06:07 2009 +0000
merge globaladdress symbol processing stuff into other stuff. Now
all global variable operand flag processing stuff is shared between
different operand types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80886 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2b6365ff99c7c321926f0c5b46536665a97f8676
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Sep 3 05:01:00 2009 +0000
Unbreak x86_64 build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80885 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5750f44c1063978fa51a46362c8c6a1c52445817
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 04:56:20 2009 +0000
Split the "operand -> symbol" logic from the "get offset and other munging
from operand" logic. GlobalAddress still todo.
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commit 9fb70d6e3120d738d14e0b8fa26e3e492cba6e5a
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 04:44:53 2009 +0000
implement lowering support for constant pool index operands, this gets a bunch more
olden programs working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80881 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5746a94642c6f34c8476fd113ad7913c27a5bc38
Author: Evan Cheng <evan.cheng at apple.com>
Date: Thu Sep 3 04:37:05 2009 +0000
X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget.
No functionality changes.
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commit bc699fcbd21999eeee0e6659b6aee4f7a9d8c8ec
Author: Ted Kremenek <kremenek at apple.com>
Date: Thu Sep 3 04:21:34 2009 +0000
Set the 'cached digest' flag after computing the digest for an
ImutAVLTree. This was accidentally left out, and essentially caused
digest caching to be ignored in ImmutableMap and ImmutableSet (this
bug was detected from shark traces that showed ComputeDigest was in
the hot path in the clang static analyzer).
This reduces the running time of the clang static analyzer on an
example benchmark by ~32% for both RegionStore (field-sensitivty) and
BasicStore (without field-sensitivity).
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commit 613e05408626a631c011a3f141eff2d6eea9f1f2
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 04:03:44 2009 +0000
update test for alignment value in hex
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commit 27f44adc3b16ead29795d1a06e6be88d8de21471
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 04:01:10 2009 +0000
output alignment value in hex so that we get:
.align 3, 0x90
instead of,
.align 3, 144
suggested by eric.
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commit 862164990329cfcc3dc83d595cb8304913f1218d
Author: Chris Lattner <sabre at nondot.org>
Date: Thu Sep 3 03:54:02 2009 +0000
simplify this by using SmallString::str(), much nicer!
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commit e86b0df8fc92fdeb05d03897afe4802ee5108dae
Author: Lang Hames <lhames at gmail.com>
Date: Thu Sep 3 02:52:02 2009 +0000
Fixed a test that ensures the LocalRewriter does not attempt to
avoid reloads by reusing clobbered registers.
This was causing issues in 256.bzip2 when compiled with PIC for
a while (starting at r78217), though the problem has since been masked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80872 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5a6b6b43459b875e88d598c232ddef7b805fe107
Author: Gabor Greif <ggreif at gmail.com>
Date: Thu Sep 3 02:02:59 2009 +0000
back out my recent commit (r80858), it seems to break self-hosting buildbot's stage 2 configure
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commit f0cb8b7ce425011e4caedfb841fdfc0aa38e6cff
Author: Devang Patel <dpatel at apple.com>
Date: Thu Sep 3 01:39:20 2009 +0000
Now Bitcode reader bug is fixed. Reapply 80839.
Use CallbackVH, instead of WeakVH, to hold MDNode elements.
Use FoldingSetNode to unique MDNodes in a context.
Use CallbackVH hooks to update context's MDNodeSet appropriately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80868 91177308-0d34-0410-b5e6-96231b3b80d8
commit deda3956ac6e8af372398bd9f4fd64c9cdf02711
Author: Devang Patel <dpatel at apple.com>
Date: Thu Sep 3 01:38:02 2009 +0000
Add new value for given index in MDValuePtrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80867 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1e48cf651240e745819e2cbf5cd837b4c24141b1
Author: Daniel Dunbar <daniel at zuster.org>
Date: Thu Sep 3 01:10:13 2009 +0000
Improve llvm::getHostTriple for some cases where the LLVM_HOSTTRIPLE is not
reliable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80863 91177308-0d34-0410-b5e6-96231b3b80d8
commit fe15ce4a51f0d83bd2a0bb788af70663fc8713aa
Author: Gabor Greif <ggreif at gmail.com>
Date: Thu Sep 3 00:18:58 2009 +0000
re-commit r66920 (which has been backed out in r66953) I may have more luck this time. I'll back out if needed...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80858 91177308-0d34-0410-b5e6-96231b3b80d8
commit 66fdfa0595d378249f8ff71168d0fe923a828b9a
Author: Sean Callanan <scallanan at apple.com>
Date: Thu Sep 3 00:04:47 2009 +0000
Added opaque 32-, 48-, and 80-bit memory operand types to the X86
instruction tables to support segmented addressing (and other objects
of obscure type).
Modified the X86 assembly printers to handle these new operand types.
Added JMP and CALL instructions that use segmented addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80857 91177308-0d34-0410-b5e6-96231b3b80d8
commit 401011eae07426d5669af7c96bb06e92cff60cfe
Author: Daniel Dunbar <daniel at zuster.org>
Date: Wed Sep 2 23:52:38 2009 +0000
Show derived host triple in --version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80855 91177308-0d34-0410-b5e6-96231b3b80d8
commit eba47222d28036cebbd582e4dc84fefa3f76de49
Author: Shantonu Sen <ssen at apple.com>
Date: Wed Sep 2 23:52:23 2009 +0000
Improve support for cross-hosted builds of LLVM.
--build=triple and other configure options are passed
to the BuildTools/ sub-invocation more consistently
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80854 91177308-0d34-0410-b5e6-96231b3b80d8
commit 66284fca05a7b78636f9f99a14bddf2e16f4f570
Author: Douglas Gregor <doug.gregor at gmail.com>
Date: Wed Sep 2 22:45:31 2009 +0000
Unbreak my CMake build. Say you'll link again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80842 91177308-0d34-0410-b5e6-96231b3b80d8
commit 03ebfa2ba332dcf86a3233b11397f6699c6ac157
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 2 21:49:26 2009 +0000
Revert 80839 for now. It causes test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80841 91177308-0d34-0410-b5e6-96231b3b80d8
commit 22d00c4b5b0845531feead561116ede02a7354b9
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 2 21:22:09 2009 +0000
Use CallbackVH, instead of WeakVH, to hold MDNode elements.
Use FoldingSetNode to unique MDNodes in a context.
Use CallbackVH hooks to update context's MDNodeSet appropriately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80839 91177308-0d34-0410-b5e6-96231b3b80d8
commit b261a1986acd86bb414d8e9e190a4e15742efc44
Author: Anton Korobeynikov <asl at math.spbu.ru>
Date: Wed Sep 2 21:21:28 2009 +0000
More missed vdup patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80838 91177308-0d34-0410-b5e6-96231b3b80d8
commit 22f2b1c131b207894d8167b516b11aa4c0776e90
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 2 19:35:19 2009 +0000
Switch llc from ParseBitcodeFile to ParseIRFile. This lets llc
transparently read either LLVM Assembly or LLVM Bitcode files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80829 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1bbc7078b1f3d61b52af07ff6ab8344c26d179a6
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 2 19:21:56 2009 +0000
Add a comment noting the memory ownership rules.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80827 91177308-0d34-0410-b5e6-96231b3b80d8
commit 56747f2521918e90a939a2db2d8c8e88f9688b89
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 2 17:54:06 2009 +0000
Add convenience functions for reading in LLVM IR that autodetect
and LLVM Assembly and LLVM Bitcode and automatically call the
corresponding reader.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80809 91177308-0d34-0410-b5e6-96231b3b80d8
commit b8f1df36008dbe45eb80c218979020088c800283
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 17:37:38 2009 +0000
switch from std::string to SmallString + raw_svector_ostream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80807 91177308-0d34-0410-b5e6-96231b3b80d8
commit b16f72e48e2ca32c5e795f7f302c1a7448c56b19
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 17:35:12 2009 +0000
split mcinst lowering stuff out to its own file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80806 91177308-0d34-0410-b5e6-96231b3b80d8
commit b3b034848455f9961fd34ec9cb6108095c8302cf
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 2 17:31:42 2009 +0000
Fix the syntax of add/sub/mul nsw/nuw and sdiv exact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80805 91177308-0d34-0410-b5e6-96231b3b80d8
commit 0f603892701d4630990e7a552354c8cf2b6374dd
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 2 17:21:29 2009 +0000
Add const qualifiers for isBitcodeWrapper, and add new functions
isRawBitcode and isBitcode to allow clients to test whether a given
memory buffer holds a bitcode image.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80804 91177308-0d34-0410-b5e6-96231b3b80d8
commit 18721d0596e31317458834d4d6bb0cbdd9d9a332
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 2 17:18:19 2009 +0000
Refactor common code from ParseAssemblyString and ParseAssemblyFile,
to expose a low-level interface for parsing from an existing MemoryBuffer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80803 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5c7b1d9dd31abf15bdeb32ec2dd09b666114da7e
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 2 17:05:05 2009 +0000
Add const qualifiers to dominates' arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80801 91177308-0d34-0410-b5e6-96231b3b80d8
commit c53892f60f8828b82695fff8895223bf6abdc1a4
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 2 16:47:24 2009 +0000
Removed temporarily because of breaking Darwin builds.
(See http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090831/086214.html)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80799 91177308-0d34-0410-b5e6-96231b3b80d8
commit fa2d3271d5e771007cf55840bb4eae119c02818c
Author: Bob Wilson <bob.wilson at apple.com>
Date: Wed Sep 2 16:35:35 2009 +0000
Rearrange code to eliminate redundancy and avoid gotos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80798 91177308-0d34-0410-b5e6-96231b3b80d8
commit 58837339ac130fbb4a0d1c6456584d7b6d933b71
Author: Nuno Lopes <nunoplopes at sapo.pt>
Date: Wed Sep 2 15:02:57 2009 +0000
plug another leak in LLParser::PerFunctionState::SetInstName()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80792 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2c6e434dc05bbb5cf3eac56dce1ad05d6c97e77f
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 2 14:24:08 2009 +0000
Changed profiling-tool-chain.ll test to use optimal-edge-profiling instead of
edge-profiling, this is more useful since the loading of the
optimal-edge-profiling is more complicated.
The edge-profiling is tested in edge-profiling.ll where only the
instrumentation is tested.
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commit f50aecf1cc4ff2b3272d1f4ed6c1783220152875
Author: Nuno Lopes <nunoplopes at sapo.pt>
Date: Wed Sep 2 14:22:03 2009 +0000
plug memory leak in LLParser::PerFunctionState::SetInstName() by deleting a value after replacing it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80790 91177308-0d34-0410-b5e6-96231b3b80d8
commit 46ef7bea5c421a06f05d376742413c18d82e35f6
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 2 14:03:11 2009 +0000
Sort edges in MaximumSpanningTree more stable in case of equal weight.
(See http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090824/085890.html)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80789 91177308-0d34-0410-b5e6-96231b3b80d8
commit f73818861a527851de1f63c34803548dc4844416
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 2 13:59:05 2009 +0000
Changed set of BlocksToInstrument to set of InsertedBlocks that do not have to
be instrumented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80788 91177308-0d34-0410-b5e6-96231b3b80d8
commit 98004cce823f3ae209052fb1229d516dfc0b22df
Author: Andreas Neustifter <astifter at gmx.at>
Date: Wed Sep 2 12:38:39 2009 +0000
Code cleanups and added comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80781 91177308-0d34-0410-b5e6-96231b3b80d8
commit b65febdbf1a37695e2dea5cee9e5dca9e181fb14
Author: Edwin Török <edwintorok at gmail.com>
Date: Wed Sep 2 12:23:05 2009 +0000
Opaque types didn't work if llvm_is_multithreaded().
AlwaysOpaqueTy is always NULL at this point, and it causes an assertion failure.
Fix it by using the just constructed tmp instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80780 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1298be5a7cc8edb31e1e825a7ddbc755a39bf2f0
Author: Nuno Lopes <nunoplopes at sapo.pt>
Date: Wed Sep 2 11:58:01 2009 +0000
set svn:ignore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80779 91177308-0d34-0410-b5e6-96231b3b80d8
commit 0aebd0cd8b56b87682114d314e77f13a5920f9db
Author: Edwin Török <edwintorok at gmail.com>
Date: Wed Sep 2 11:13:56 2009 +0000
Fix DbgStopPointInst->getFileName/getDirectory, broken by the MDNodification in
r80406, and readd a -print-dbginfo test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80778 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5838baa4a8aedfd453a5b0663425979c77e4e285
Author: Sandeep Patel <deeppatel1987 at gmail.com>
Date: Wed Sep 2 08:44:58 2009 +0000
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7c3d6c1f0cacdc5a01a66ce5f99e09848f0d58f3
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 06:34:22 2009 +0000
Fix month.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80769 91177308-0d34-0410-b5e6-96231b3b80d8
commit 47ecca719dca162477c10e787bb1ab0c4c571ece
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 06:31:02 2009 +0000
fix PR4815: some cases where DeleteDeadInstruction can delete
the instruction BBI points to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80768 91177308-0d34-0410-b5e6-96231b3b80d8
commit 77f1627b24f4256e414864513212cc4648e89dcc
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 06:15:37 2009 +0000
clean up this code a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80767 91177308-0d34-0410-b5e6-96231b3b80d8
commit fa2d1ba102a74ecb0444957e0e5e1e99b064bfc3
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 06:11:42 2009 +0000
eliminate VISIBILITY_HIDDEN from Transforms/Scalar. PR4861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80766 91177308-0d34-0410-b5e6-96231b3b80d8
commit 84a6720fa162828ccf52531135afc2449662a2cd
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 05:57:00 2009 +0000
refactor select 'sched insertion' out to its own method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80764 91177308-0d34-0410-b5e6-96231b3b80d8
commit 556464fc42a499f616530d6c9ec3ab698a05aa90
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 05:53:04 2009 +0000
Add support for modeling whether or not the processor has support for
conditional moves as a subtarget feature. This is the easy part of
PR4841.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80763 91177308-0d34-0410-b5e6-96231b3b80d8
commit 12aaa0197524bcbf878774e442335813667b8518
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 05:35:45 2009 +0000
fix PR4848 an infinite loop when indexing down through a recursive gep
and we get the original pointer type. This doesn't mean that we're
at the first pointer being indexed. Correct the predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80762 91177308-0d34-0410-b5e6-96231b3b80d8
commit 41c09930cfb4e36227f5f73bb618d2a7aa4da884
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 05:12:37 2009 +0000
fix PR4837, some bugs folding vector compares. These
return a vector of i1, not i1 itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80761 91177308-0d34-0410-b5e6-96231b3b80d8
commit bc05eef1c31d86b525f0d80429a13344b13192a2
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 04:39:04 2009 +0000
revert my patch, duncan points out what is wrong with my logic. Add
a comment so that I don't change this in the future :)
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commit 9d256f1e48cf074e739f478a48f9619797cbe4c1
Author: Chris Lattner <sabre at nondot.org>
Date: Wed Sep 2 04:34:06 2009 +0000
one more try at making this simpler, hopefully it won't break everything :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80759 91177308-0d34-0410-b5e6-96231b3b80d8
commit d1585abba762e44ee70734e77dded04d3a6a77a7
Author: Duncan Sands <baldrick at free.fr>
Date: Wed Sep 2 03:48:41 2009 +0000
Complicate Chris's simplification, avoiding complaints
about singular iterators when building with expensive
checks turned on.
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commit d7a9a27a450dce545da94ffc43df64c776eabaeb
Author: Daniel Dunbar <daniel at zuster.org>
Date: Wed Sep 2 02:43:11 2009 +0000
Don't force the triple or data layout in this test. We just have to get them
from the host and hope that works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80751 91177308-0d34-0410-b5e6-96231b3b80d8
commit 7b5cdc094c42b788e1c0d6708ba5fa077eca7f8a
Author: Dan Gohman <gohman at apple.com>
Date: Wed Sep 2 01:14:16 2009 +0000
Add a comment.
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commit 251676e7beab341460c562976a1f3f4a2f873929
Author: Sean Callanan <scallanan at apple.com>
Date: Wed Sep 2 00:55:49 2009 +0000
Fixed the asmstrings for 8-bit, 16-bit, and 32-bit ADD %rAX, imm instructions.
Added a 64-bit ADD %RAX, imm32 instruction.
Added all 4 forms for AND %rAX, imm and CMP %rAX, imm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80746 91177308-0d34-0410-b5e6-96231b3b80d8
commit 5f0d0810c3224d8296a90ee7c504d19f6b99ea89
Author: Evan Cheng <evan.cheng at apple.com>
Date: Wed Sep 2 00:19:03 2009 +0000
Fix PR4845: r77946 completely broke x86_64 Darwin (or any situation where the
desired triplet is a sub-target, e.g. thumbv7 vs. arm host). Reverting the
patch isn't quite right either since the previous behavior does not allow the
triplet to be overridden with -march.
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commit aae9da7d74762fa1aef3d9e9b3eba4657eb5bfd8
Author: Devang Patel <dpatel at apple.com>
Date: Wed Sep 2 00:16:33 2009 +0000
Disable uniqueness test for now.
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commit bd93206d2cd5cfc5482b8b9d17a9d7e2862fe26b
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 1 23:56:42 2009 +0000
For now disable MDNode uniquing. This fixes llvm-gcc bootstrap failure on certain Mac OS X 10.5. I am working on a proper fix.
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commit 2a073840a9863f7fde14aba104621ce546f35510
Author: Bob Wilson <bob.wilson at apple.com>
Date: Tue Sep 1 23:18:46 2009 +0000
Avoid calling removeVirtualRegisterKilled which iterates over the operands
to find the kill, since we already have the operand.
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commit 4868b2482d56166b836de78a4b35607a799f7958
Author: Bob Wilson <bob.wilson at apple.com>
Date: Tue Sep 1 22:51:08 2009 +0000
Refactor some code into separate functions. No functional changes.
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commit 432d176192c6a1707a9f714ea00ea500f1d9a6ee
Author: Bob Wilson <bob.wilson at apple.com>
Date: Tue Sep 1 22:19:00 2009 +0000
Move use of LV inside condition that guards for null LV.
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commit 7cc00874d5de3b00205dcce03e05205916697d38
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 1 22:07:12 2009 +0000
Fix build warning.
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commit 064aca1f4cb7a3ac916d665db62056008ecde927
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 1 22:07:06 2009 +0000
Simplify.
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commit 914bc71e34cfa976d86bcd7c95fafd794dcc2020
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 1 22:07:00 2009 +0000
Fix what I believe is a copy-n-pasto introduced in r78129.
- Bruno, please check!!
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commit 8ac6c04c49a83ce12779ca42416fe5512e69a01e
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 1 22:06:53 2009 +0000
X86/Encoding: Support ExternalSymbol operands in emitDisplacementField (for consistency).
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commit 9f086b93c3bb001b72590024114ac8c19f5abdaa
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 1 22:06:46 2009 +0000
Remove Offset from ExternalSybmol MachineOperands, this is unused (and at least partly unsupported, in X86 encoding at least).
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commit 3dfe01d21e412c113b13e222c0fde9970d258af2
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 1 21:37:50 2009 +0000
debug intrinsics do not go in the callgraph, this fixes a couple
clang regtest failures.
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commit 0934baa37a70c413600ebc3f2219822cbaf90830
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 1 20:33:43 2009 +0000
Fix a regression I introduced in r80708, found by llvm-test.
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commit 0c971ca2967e9dd20f26d8d68cacb131dd2fb7ca
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: Tue Sep 1 19:25:52 2009 +0000
Fix ELF Writter related memory leaks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80717 91177308-0d34-0410-b5e6-96231b3b80d8
commit 231d73422a43624472e0ff74a1d9ec30740c7adb
Author: Andreas Neustifter <astifter at gmx.at>
Date: Tue Sep 1 19:08:51 2009 +0000
OptimalEdgeProfiling: Reading in Profiles.
This enables LLVM to read the OptimalEdgeProfiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80715 91177308-0d34-0410-b5e6-96231b3b80d8
commit 595887666dae3198db047b6e718129fdcf45ab8a
Author: Andreas Neustifter <astifter at gmx.at>
Date: Tue Sep 1 19:05:58 2009 +0000
Addedum to r80712, forgot to add files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80713 91177308-0d34-0410-b5e6-96231b3b80d8
commit 10dd7a2d9c1c123260c8afd730be1c109a20bb2c
Author: Andreas Neustifter <astifter at gmx.at>
Date: Tue Sep 1 19:03:44 2009 +0000
OptimalEdgeProfiling: Creation of profiles.
This adds the instrumentation and runtime part of OptimalEdgeProfiling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80712 91177308-0d34-0410-b5e6-96231b3b80d8
commit 8093b5dc9a1e310a79fc7af83c1fc2e1867c2ef7
Author: Andreas Neustifter <astifter at gmx.at>
Date: Tue Sep 1 19:01:59 2009 +0000
Small fix in ProfileEstimator that eliminates duplicated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80711 91177308-0d34-0410-b5e6-96231b3b80d8
commit d5496d944b0095cfd0d1cc93386a3c569b7f06d5
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 1 18:55:08 2009 +0000
reduce size of SmallString to something more reasonable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80710 91177308-0d34-0410-b5e6-96231b3b80d8
commit b980f057d2ea2119836fbf39040ca8e49386d297
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 1 18:52:39 2009 +0000
remove CallGraphNode::replaceCallSite, it is redundant with other APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80708 91177308-0d34-0410-b5e6-96231b3b80d8
commit c2d6585e5e77e5b44a9440f7cb821dada5009692
Author: Bob Wilson <bob.wilson at apple.com>
Date: Tue Sep 1 18:51:56 2009 +0000
Add support for generating code for vst{234}lane intrinsics.
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commit 0b6ab543047eac94f4155297b7b12af78e0e6a6d
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 1 18:50:55 2009 +0000
cleanup/simplify
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80706 91177308-0d34-0410-b5e6-96231b3b80d8
commit 10d150b7c19caf36e4dbe6505c0b43cf62c0a858
Author: Bob Wilson <bob.wilson at apple.com>
Date: Tue Sep 1 18:50:43 2009 +0000
Fix incorrect declarations of intrinsics in this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80705 91177308-0d34-0410-b5e6-96231b3b80d8
commit 1e58780928c42ba7c34deb7bbb35c17391b3d36e
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 1 18:49:12 2009 +0000
Use raw_ostream instead of sstream
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commit ecd40faa95e178986ff2fec6c7eaae10692be6f9
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 1 18:44:06 2009 +0000
remove a bunch of explicit code previously needed to update the
callgraph. This is now dead because RAUW does the job.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80703 91177308-0d34-0410-b5e6-96231b3b80d8
commit 4b023dd6936966cce0cfea28c5148168f7a5b40e
Author: David Goodwin <david_goodwin at apple.com>
Date: Tue Sep 1 18:34:03 2009 +0000
Add hidden flags to allow binary search of post-RA scheduling errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80702 91177308-0d34-0410-b5e6-96231b3b80d8
commit 02b0e35f988abea2d6e5a07a854b4c6192872355
Author: David Goodwin <david_goodwin at apple.com>
Date: Tue Sep 1 18:32:09 2009 +0000
RRX reads CPSR.
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commit 1c79378308526587066ea216550858e780fd6423
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 1 18:32:03 2009 +0000
doxygenate RefreshCallGraph, add a new 'verification mode', and run it after
CGSCC passes make change to ensure they are updating the callgraph correctly
(when assertions are enabled).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80698 91177308-0d34-0410-b5e6-96231b3b80d8
commit 96d7ddc073ae2bdbf5e0bda96a5d7d8f7185ecb4
Author: Dan Gohman <gohman at apple.com>
Date: Tue Sep 1 18:29:01 2009 +0000
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80697 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3e4b1a34d5b499ec5547537b59505158e643305c
Author: Sean Callanan <scallanan at apple.com>
Date: Tue Sep 1 18:14:18 2009 +0000
Added TEST %rAX, $imm instructions to the Intel tables. These are required for the X86 disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80696 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2507c18bfc58d649a6ddd20b3e3ce41b2ed0793f
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 1 18:13:40 2009 +0000
simpler solution to iterator invalidation "problem" found
by expensive checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80695 91177308-0d34-0410-b5e6-96231b3b80d8
commit d23a9667c9e7f88f4cdb2befc3adc08a5b7df776
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 1 17:56:32 2009 +0000
enhance memcpy opt to turn memmoves into memcpy when the src/dest
don't alias. Remove an old and poorly reduced testcase that fails
with this transform for reasons unrelated to the original test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80693 91177308-0d34-0410-b5e6-96231b3b80d8
commit 8f43b86c52646711a6906e516e17b32224f1a104
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: Tue Sep 1 17:27:58 2009 +0000
Reapply 80278
Add MO flags to simplify the printing of relocations.
Remove the support for printing large code model relocs (which
aren't supported anyway).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80691 91177308-0d34-0410-b5e6-96231b3b80d8
commit 598082b1dd506ca0d6540f2bcaded867bfbf77af
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 1 17:19:13 2009 +0000
revert inadvertant change from previous commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80689 91177308-0d34-0410-b5e6-96231b3b80d8
commit 2e8a8c4cb8746fbe3d199d69b1efcabe557eec3f
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 1 17:09:55 2009 +0000
random code cleanups, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80682 91177308-0d34-0410-b5e6-96231b3b80d8
commit 3efbb51978df6a37350f8d9d8c67ff3a988ad585
Author: Ted Kremenek <kremenek at apple.com>
Date: Tue Sep 1 17:01:02 2009 +0000
Update CMake files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80680 91177308-0d34-0410-b5e6-96231b3b80d8
commit 90cc01b4e49618f75a3cb899cefaa0abe9ca7066
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 1 16:43:35 2009 +0000
Simply LSDA lable emission to use a direct special-case output instead of
EmitLabel()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80677 91177308-0d34-0410-b5e6-96231b3b80d8
commit ce59c1a172148acb3140cd46dcb94a9d225f31d5
Author: Duncan Sands <baldrick at free.fr>
Date: Tue Sep 1 15:13:02 2009 +0000
Do not manipulate invalid iterators. This fixes the
llvm-gcc build when expensive checking is turned on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80671 91177308-0d34-0410-b5e6-96231b3b80d8
commit 724c3211128a50b60e5e479d0e6b66de710a6470
Author: Sanjiv Gupta <sanjiv.gupta at microchip.com>
Date: Tue Sep 1 10:47:31 2009 +0000
Further refactoring of PIC16 Obj file code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80670 91177308-0d34-0410-b5e6-96231b3b80d8
commit ba2ab19fb3bd60795d5e5c84d5ada7121ab5d282
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: Tue Sep 1 10:24:10 2009 +0000
Update CMakeLists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80669 91177308-0d34-0410-b5e6-96231b3b80d8
commit 204b27e24b13676075ab11b149b3a67db3c59f03
Author: Andreas Neustifter <astifter at gmx.at>
Date: Tue Sep 1 10:08:39 2009 +0000
Preparation for Optimal Edge Profiling:
Add statistics for regular edge profiling, this enables the comparation of the
number of edges inserted by regular and optimal edge profiling.
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commit 09ae6e0d77d7eb3339a20c613a6f0a9c391dc9f3
Author: Andreas Neustifter <astifter at gmx.at>
Date: Tue Sep 1 10:06:05 2009 +0000
Preparation for Optimal Edge Profiling:
Optimal edge profiling is only possible when blocks with no predecessors get an
virtual edge (BB,0) that counts the execution frequencies of this
function-exiting blocks.
This patch makes the necessary changes before actually enabling optimal edge profiling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80667 91177308-0d34-0410-b5e6-96231b3b80d8
commit 76448f751688349d8dc7330dbe56ba0165878790
Author: Andreas Neustifter <astifter at gmx.at>
Date: Tue Sep 1 08:48:42 2009 +0000
Preparation for Optimal Edge Profiling:
This adds a pass to verify the current profile against the flow conditions.
This is very helpful when later on trying to perserve the profiling information
during all passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80666 91177308-0d34-0410-b5e6-96231b3b80d8
commit aabe25ea1ff3a49b6daa2e643cdb92ac8cc285f5
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 1 06:33:49 2009 +0000
testcase for PR3601
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commit a59b5decad2d3e3b9e2f565ff5d4e1857b9202a1
Author: Chris Lattner <sabre at nondot.org>
Date: Tue Sep 1 06:31:31 2009 +0000
Change CallGraphNode to maintain it's Function as an AssertingVH
for sanity. This didn't turn up any bugs.
Change CallGraphNode to maintain its "callsite" information in the
call edges list as a WeakVH instead of as an instruction*. This fixes
a broad class of dangling pointer bugs, and makes CallGraph have a number
of useful invariants again. This fixes the class of problem indicated
by PR4029 and PR3601.
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commit e18cb0735189d79b73d3643f9bfda482a82f498d
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 1 05:04:28 2009 +0000
Add virtual destructor.
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commit 56c573ec8f87ef5fe2d507b7fc1446efa1df0043
Author: Bob Wilson <bob.wilson at apple.com>
Date: Tue Sep 1 04:27:10 2009 +0000
Add test for vld{234}_lane instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80658 91177308-0d34-0410-b5e6-96231b3b80d8
commit d14b8b63b3557e85950beb061a1d8b01cff4eadf
Author: Bob Wilson <bob.wilson at apple.com>
Date: Tue Sep 1 04:26:28 2009 +0000
Generate code for vld{234}_lane intrinsics.
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commit 13099514dad37eb4e6f270fc84fb749c3eaeb487
Author: Bob Wilson <bob.wilson at apple.com>
Date: Tue Sep 1 04:18:40 2009 +0000
Fix pr4843: When an instruction has multiple destination registers that are
tied to different source registers, the TwoAddressInstructionPass needs to
be smarter. Change it to check before replacing a source register whether
that source register is tied to a different destination register, and if so,
defer handling it until a subsequent iteration.
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commit ef0f63722ac72a66dd4486e6ac8a1719d12e6e13
Author: Daniel Dunbar <daniel at zuster.org>
Date: Tue Sep 1 04:09:03 2009 +0000
llvm-mc: Store MCSymbolData value as a pointer (to make MSVC happy).
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commit 843c2a2675a78ce65e781d180fd284d4f4a2ff84
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 1 02:34:49 2009 +0000
SJLJ is arm/darwin only for now. force the triple for the test
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commit 4b673ee8fb5f7351de61d8bc06fb8958aa846d93
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 1 02:05:03 2009 +0000
Fix compiler warnings
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commit 5e0257f9b7567c8c285ee3115c10d552c7c037fb
Author: Jim Grosbach <grosbach at apple.com>
Date: Tue Sep 1 01:57:56 2009 +0000
Clean up LSDA name generation and use for SJLJ exception handling. This
makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
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commit 8a6a4f5d031875716e06bf7339708874e97d915b
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 1 01:14:15 2009 +0000
Introduce DILocation.
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commit d4794f1da6e32d0eda205da2f994a25d1632aea9
Author: Devang Patel <dpatel at apple.com>
Date: Tue Sep 1 00:53:21 2009 +0000
Add getDirectory() and getFilename() interface to DIScope.
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commit 318d70da84dd9c3371774284695e2f96613d68a9
Author: Devang Patel <dpatel at apple.com>
Date: Mon Aug 31 22:47:13 2009 +0000
Subprogram is a scope. Derive DISubprogram from DIScope.
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commit a53768e1e514ec9184b3e17c465b19f9334c1e5c
Author: Devang Patel <dpatel at apple.com>
Date: Mon Aug 31 22:00:15 2009 +0000
Rename DIBlock as DILexicalBlock.
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commit c8b451fceb3e26addeda713ec01dbaf1fa183711
Author: Dan Gohman <gohman at apple.com>
Date: Mon Aug 31 21:58:28 2009 +0000
Don't use an iterator which is potentially invalidated.
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commit acce6ef067e3e784306ea3e13c30913722a2207c
Author: Bob Wilson <bob.wilson at apple.com>
Date: Mon Aug 31 21:54:55 2009 +0000
Use early exit and reduce indentation.
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commit ce99fa7903584a25dd332004f3dcf639bbba91f6
Author: Bob Wilson <bob.wilson at apple.com>
Date: Mon Aug 31 21:54:16 2009 +0000
If the tied registers are already the same, there is no need to change
them. Move the code to make that change inside the conditional.
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commit 0b3e9544a8c01d83bb746e80ef380e570db47be6
Author: Richard Osborne <richard at xmos.com>
Date: Mon Aug 31 21:51:36 2009 +0000
Add triple parsing support for XCore.
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commit 4a47c2447110c5163806b46ee1be881adf70ce38
Author: Devang Patel <dpatel at apple.com>
Date: Mon Aug 31 21:34:44 2009 +0000
Derive DICompileUnit from DIScope.
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commit 248d5579576fdfb0f1dca59bc3c6cebb8a6976fc
Author: Caroline Tice <ctice at apple.com>
Date: Mon Aug 31 21:19:37 2009 +0000
Add flag to mark structs for Apple Block "byref" variables; also add code to
modify the type and location debug information for these variables to match the
programmer's expectations.
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commit 30e24e0e6f8e94a50ef6f08911724ef5d43762d7
Author: Dan Gohman <gohman at apple.com>
Date: Mon Aug 31 21:15:23 2009 +0000
Extend the ValuesAtScope cache to cover all expressions, not just
SCEVUnknowns, as the non-SCEVUnknown cases in the getSCEVAtScope code
can also end up repeatedly climing through the same expression trees,
which can be unusably slow when the trees are very tall.
Also, add a quick check for SCEV pointer equality to the main
SCEV comparison routine, as the full comparison code can be expensive
in the case of large expression trees.
These fix compile-time problems in some pathlogical cases.
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commit 21dde52e1976411d2f85eb2505d98d6b8d23baa6
Author: Gabor Greif <ggreif at gmail.com>
Date: Mon Aug 31 20:54:23 2009 +0000
restore semantics of operator* (removing a FIXME I had to introduce in r80224)
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commit 864c4b83472a97397039240f7d5e9c6e269174b1
Author: David Goodwin <david_goodwin at apple.com>
Date: Mon Aug 31 20:47:02 2009 +0000
Don't mark a register live at an undef use.
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commit 94f536e037d399e79afa64c060da2ac0d4d6b4a7
Author: Devang Patel <dpatel at apple.com>
Date: Mon Aug 31 20:44:45 2009 +0000
Introduce DIScope.
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commit c9db7a5b14625f78cbd619582db31a985eeddd7d
Author: Devang Patel <dpatel at apple.com>
Date: Mon Aug 31 20:27:49 2009 +0000
Oops. Fix inverted logic in assertion check.
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commit 08ed20d6841e1879cff1c6b7717b64fd400dc913
Author: Evan Cheng <evan.cheng at apple.com>
Date: Mon Aug 31 20:14:07 2009 +0000
Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
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commit 34a26db1f0520916f9f5d8a0f31fc9c34119bb05
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Aug 31 19:14:05 2009 +0000
X86/exp-asm-printer: Lower MachineOperand::MO_JumpTableIndex to MCOperand.
- Down to 7 failures on 403.gcc.
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commit 59c42d00cd177c318a10364ddea06290b1f9f320
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Aug 31 19:13:56 2009 +0000
Stop printing old asm printing code inline with -experimental-asm-printer (this allows diffing and assembling the .s)
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commit befe952c385a9e2f26212b3cdea6439323964a46
Author: Daniel Dunbar <daniel at zuster.org>
Date: Mon Aug 31 19:13:47 2009 +0000
Avoid unnecessary +0 in experimental-asm-printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80603 91177308-0d34-0410-b5e6-96231b3b80d8
commit 56843af6f90e5bdf7d79a271d2406f57e6674122
Author: Devang Patel <dpatel at apple.com>
Date: Mon Aug 31 18:49:10 2009 +0000
Simplify isDerivedType() and other predicate interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80602 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/libclamav/c++/llvm/CMakeLists.txt b/libclamav/c++/llvm/CMakeLists.txt
index c6036f0..c9c5272 100644
--- a/libclamav/c++/llvm/CMakeLists.txt
+++ b/libclamav/c++/llvm/CMakeLists.txt
@@ -70,6 +70,9 @@ else( MSVC )
CACHE STRING "Semicolon-separated list of targets to build, or \"all\".")
endif( MSVC )
+set(LLVM_TARGET_ARCH "host"
+ CACHE STRING "Set target to use for LLVM JIT or use \"host\" for automatic detection.")
+
option(LLVM_ENABLE_THREADS "Use threads if available." ON)
if( uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" )
@@ -142,7 +145,11 @@ else(WIN32)
if(UNIX)
set(LLVM_ON_WIN32 0)
set(LLVM_ON_UNIX 1)
- set(LTDL_SHLIB_EXT ".so")
+ if(APPLE)
+ set(LTDL_SHLIB_EXT ".dylib")
+ else(APPLE)
+ set(LTDL_SHLIB_EXT ".so")
+ endif(APPLE)
set(EXEEXT "")
# FIXME: Maximum path length is currently set to 'safe' fixed value
set(MAXPATHLEN 2024)
@@ -252,8 +259,11 @@ add_subdirectory(lib/Linker)
add_subdirectory(lib/Analysis)
add_subdirectory(lib/Analysis/IPA)
add_subdirectory(lib/MC)
+add_subdirectory(test)
add_subdirectory(utils/FileCheck)
+add_subdirectory(utils/count)
+add_subdirectory(utils/not)
set(LLVM_ENUM_ASM_PRINTERS "")
set(LLVM_ENUM_ASM_PARSERS "")
diff --git a/libclamav/c++/llvm/Makefile b/libclamav/c++/llvm/Makefile
index 5d10f8e..bd8552b 100644
--- a/libclamav/c++/llvm/Makefile
+++ b/libclamav/c++/llvm/Makefile
@@ -24,7 +24,7 @@ ifeq ($(BUILD_DIRS_ONLY),1)
OPTIONAL_DIRS :=
else
DIRS := lib/System lib/Support utils lib/VMCore lib tools/llvm-config \
- tools runtime docs
+ tools runtime docs unittests
OPTIONAL_DIRS := examples projects bindings
endif
@@ -62,7 +62,7 @@ ifeq ($(MAKECMDGOALS),install-clang)
endif
ifeq ($(MAKECMDGOALS),clang-only)
- DIRS := $(filter-out tools runtime docs, $(DIRS)) tools/clang
+ DIRS := $(filter-out tools runtime docs unittests, $(DIRS)) tools/clang
OPTIONAL_DIRS :=
endif
@@ -88,10 +88,19 @@ cross-compile-build-tools:
$(Verb) if [ ! -f BuildTools/Makefile ]; then \
$(MKDIR) BuildTools; \
cd BuildTools ; \
- $(PROJ_SRC_DIR)/configure ; \
+ $(PROJ_SRC_DIR)/configure --build=$(BUILD_TRIPLE) \
+ --host=$(BUILD_TRIPLE) --target=$(BUILD_TRIPLE); \
cd .. ; \
fi; \
- ($(MAKE) -C BuildTools BUILD_DIRS_ONLY=1 ) || exit 1;
+ ($(MAKE) -C BuildTools \
+ BUILD_DIRS_ONLY=1 \
+ UNIVERSAL= \
+ ENABLE_OPTIMIZED=$(ENABLE_OPTIMIZED) \
+ ENABLE_PROFILING=$(ENABLE_PROFILING) \
+ ENABLE_COVERAGE=$(ENABLE_COVERAGE) \
+ DISABLE_ASSERTIONS=$(DISABLE_ASSERTIONS) \
+ ENABLE_EXPENSIVE_CHECKS=$(ENABLE_EXPENSIVE_CHECKS) \
+ ) || exit 1;
endif
# Include the main makefile machinery.
diff --git a/libclamav/c++/llvm/Makefile.config.in b/libclamav/c++/llvm/Makefile.config.in
index ecd0595..fc84c0b 100644
--- a/libclamav/c++/llvm/Makefile.config.in
+++ b/libclamav/c++/llvm/Makefile.config.in
@@ -110,6 +110,9 @@ BUILD_EXEEXT=@BUILD_EXEEXT@
BUILD_CC=@BUILD_CC@
BUILD_CXX=@BUILD_CXX@
+# Triple for configuring build tools when cross-compiling
+BUILD_TRIPLE=@build@
+
# Target triple (cpu-vendor-os) for which we should generate code
TARGET_TRIPLE=@target@
@@ -242,6 +245,11 @@ RDYNAMIC := @RDYNAMIC@
#DEBUG_RUNTIME = 1
@DEBUG_RUNTIME@
+# When DEBUG_SYMBOLS is enabled, the compiler libraries will retain debug
+# symbols.
+#DEBUG_SYMBOLS = 1
+ at DEBUG_SYMBOLS@
+
# When ENABLE_PROFILING is enabled, the llvm source base is built with profile
# information to allow gprof to be used to get execution frequencies.
#ENABLE_PROFILING = 1
diff --git a/libclamav/c++/llvm/Makefile.rules b/libclamav/c++/llvm/Makefile.rules
index 23e554d..264bab8 100644
--- a/libclamav/c++/llvm/Makefile.rules
+++ b/libclamav/c++/llvm/Makefile.rules
@@ -19,10 +19,11 @@
#--------------------------------------------------------------------
# Define the various target sets
#--------------------------------------------------------------------
-RecursiveTargets := all clean clean-all install uninstall install-bytecode
+RecursiveTargets := all clean clean-all install uninstall install-bytecode \
+ unitcheck
LocalTargets := all-local clean-local clean-all-local check-local \
install-local printvars uninstall-local \
- install-bytecode-local unittests
+ install-bytecode-local
TopLevelTargets := check dist dist-check dist-clean dist-gzip dist-bzip2 \
dist-zip unittests
UserTargets := $(RecursiveTargets) $(LocalTargets) $(TopLevelTargets)
@@ -312,6 +313,13 @@ ifeq ($(ENABLE_OPTIMIZED),1)
CXX.Flags += $(OPTIMIZE_OPTION) $(OmitFramePointer)
C.Flags += $(OPTIMIZE_OPTION) $(OmitFramePointer)
LD.Flags += $(OPTIMIZE_OPTION)
+ ifdef DEBUG_SYMBOLS
+ BuildMode := $(BuildMode)+Debug
+ CXX.Flags += -g
+ C.Flags += -g
+ LD.Flags += -g
+ KEEP_SYMBOLS := 1
+ endif
else
BuildMode := Debug
CXX.Flags += -g
@@ -343,9 +351,10 @@ ifdef REQUIRES_FRAME_POINTER
LD.Flags := $(filter-out -fomit-frame-pointer,$(LD.Flags))
endif
-# IF REQUIRES_RTTI=1 is specified then don't disable run-time type id
-ifndef REQUIRES_RTTI
-# CXX.Flags += -fno-rtti
+# If REQUIRES_RTTI=1 is specified then don't disable run-time type id.
+ifeq ($(REQUIRES_RTTI), 1)
+ CXX.Flags := $(filter-out -fno-rtti,$(CXX.Flags))
+ CXXFLAGS := $(filter-out -fno-rtti,$(CXXFLAGS))
endif
ifdef ENABLE_COVERAGE
@@ -436,6 +445,7 @@ ifdef ENABLE_EXPENSIVE_CHECKS
# GNU libstdc++ uses RTTI if you define _GLIBCXX_DEBUG, which we did above.
# See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40160
CXX.Flags := $(filter-out -fno-rtti,$(CXX.Flags))
+ CXXFLAGS := $(filter-out -fno-rtti,$(CXXFLAGS))
endif
#--------------------------------------------------------------------
@@ -513,7 +523,10 @@ ifeq ($(HOST_OS),Darwin)
DARWIN_MAJVERS := $(shell echo $(DARWIN_VERSION)| sed -E 's/10.([0-9]).*/\1/')
SharedLinkOptions=-Wl,-flat_namespace -Wl,-undefined -Wl,suppress \
- -dynamiclib -mmacosx-version-min=$(DARWIN_VERSION)
+ -dynamiclib
+ ifneq ($(ARCH),ARM)
+ SharedLinkOptions += -mmacosx-version-min=$(DARWIN_VERSION)
+ endif
else
ifeq ($(HOST_OS),Cygwin)
SharedLinkOptions=-shared -nostdlib -Wl,--export-all-symbols \
@@ -524,7 +537,9 @@ else
endif
ifeq ($(TARGET_OS),Darwin)
- TargetCommonOpts += -mmacosx-version-min=$(DARWIN_VERSION)
+ ifneq ($(ARCH),ARM)
+ TargetCommonOpts += -mmacosx-version-min=$(DARWIN_VERSION)
+ endif
endif
# Adjust LD.Flags depending on the kind of library that is to be built. Note
@@ -793,6 +808,7 @@ clean-all:: $(addsuffix /.makeclean-all,$(PARALLEL_DIRS))
install :: $(addsuffix /.makeinstall ,$(PARALLEL_DIRS))
uninstall:: $(addsuffix /.makeuninstall,$(PARALLEL_DIRS))
install-bytecode :: $(addsuffix /.makeinstall-bytecode,$(PARALLEL_DIRS))
+unitcheck:: $(addsuffix /.makeunitcheck,$(PARALLEL_DIRS))
ParallelTargets := $(foreach T,$(RecursiveTargets),%/.make$(T))
@@ -1367,14 +1383,13 @@ $(ObjDir)/%.s: %.c $(ObjDir)/.dir $(BUILT_SOURCES)
# make the C and C++ compilers strip debug info out of bytecode libraries.
ifdef DEBUG_RUNTIME
-$(ObjectsBC): $(ObjDir)/%.bc: $(ObjDir)/%.ll $(LLVMAS) $(LOPT)
+$(ObjectsBC): $(ObjDir)/%.bc: $(ObjDir)/%.ll $(LOPT)
$(Echo) "Compiling $*.ll to $*.bc for $(BuildMode) build (bytecode)"
- $(Verb) $(LLVMAS) $< -o - | $(LOPT) -std-compile-opts -o $@ -f
+ $(Verb) $(LOPT) $< -std-compile-opts -o $@
else
-$(ObjectsBC): $(ObjDir)/%.bc: $(ObjDir)/%.ll $(LLVMAS) $(LOPT)
+$(ObjectsBC): $(ObjDir)/%.bc: $(ObjDir)/%.ll $(LOPT)
$(Echo) "Compiling $*.ll to $*.bc for $(BuildMode) build (bytecode)"
- $(Verb) $(LLVMAS) $< -o - | \
- $(LOPT) -std-compile-opts -strip-debug -o $@ -f
+ $(Verb) $(LOPT) $< -std-compile-opts -strip-debug -o $@
endif
@@ -1593,6 +1608,30 @@ check::
$(EchoCmd) No test directory ; \
fi
+check-lit::
+ $(Verb) if test -d "$(PROJ_OBJ_ROOT)/test" ; then \
+ if test -f "$(PROJ_OBJ_ROOT)/test/Makefile" ; then \
+ $(EchoCmd) Running test suite ; \
+ $(MAKE) -C $(PROJ_OBJ_ROOT)/test check-local-lit ; \
+ else \
+ $(EchoCmd) No Makefile in test directory ; \
+ fi ; \
+ else \
+ $(EchoCmd) No test directory ; \
+ fi
+
+check-all::
+ $(Verb) if test -d "$(PROJ_OBJ_ROOT)/test" ; then \
+ if test -f "$(PROJ_OBJ_ROOT)/test/Makefile" ; then \
+ $(EchoCmd) Running test suite ; \
+ $(MAKE) -C $(PROJ_OBJ_ROOT)/test check-local-all ; \
+ else \
+ $(EchoCmd) No Makefile in test directory ; \
+ fi ; \
+ else \
+ $(EchoCmd) No test directory ; \
+ fi
+
###############################################################################
# UNITTESTS: Running the unittests test suite
###############################################################################
@@ -1601,7 +1640,7 @@ unittests::
$(Verb) if test -d "$(PROJ_OBJ_ROOT)/unittests" ; then \
if test -f "$(PROJ_OBJ_ROOT)/unittests/Makefile" ; then \
$(EchoCmd) Running unittests test suite ; \
- $(MAKE) -C $(PROJ_OBJ_ROOT)/unittests ; \
+ $(MAKE) -C $(PROJ_OBJ_ROOT)/unittests unitcheck; \
else \
$(EchoCmd) No Makefile in unittests directory ; \
fi ; \
diff --git a/libclamav/c++/llvm/autoconf/AutoRegen.sh b/libclamav/c++/llvm/autoconf/AutoRegen.sh
index 07866e6..7809667 100755
--- a/libclamav/c++/llvm/autoconf/AutoRegen.sh
+++ b/libclamav/c++/llvm/autoconf/AutoRegen.sh
@@ -12,6 +12,8 @@ clean() {
### NOTE: ############################################################
### These variables specify the tool versions we want to use.
### Periods should be escaped with backslash for use by grep.
+###
+### If you update these, please also update docs/GettingStarted.html
want_autoconf_version='2\.60'
want_autoheader_version=$want_autoconf_version
want_aclocal_version='1\.9\.6'
diff --git a/libclamav/c++/llvm/autoconf/config.guess b/libclamav/c++/llvm/autoconf/config.guess
index 7d0185e..e792aac 100755
--- a/libclamav/c++/llvm/autoconf/config.guess
+++ b/libclamav/c++/llvm/autoconf/config.guess
@@ -1,9 +1,10 @@
#! /bin/sh
# Attempt to guess a canonical system name.
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-# 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+# Free Software Foundation, Inc.
-timestamp='2004-09-07'
+timestamp='2009-09-18'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
@@ -17,23 +18,25 @@ timestamp='2004-09-07'
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+# 02110-1301, USA.
#
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
# the same distribution terms that you use for the rest of that program.
-# Originally written by Per Bothner <per at bothner.com>.
-# Please send patches to <config-patches at gnu.org>. Submit a context
-# diff and a properly formatted ChangeLog entry.
+
+# Originally written by Per Bothner. Please send patches (context
+# diff format) to <config-patches at gnu.org> and include a ChangeLog
+# entry.
#
# This script attempts to guess a canonical system name similar to
# config.sub. If it succeeds, it prints the system name on stdout, and
# exits with 0. Otherwise, it exits with 1.
#
-# The plan is that this can be called by configure scripts if you
-# don't specify an explicit build system type.
+# You can get the latest version of this script from:
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD
me=`echo "$0" | sed -e 's,.*/,,'`
@@ -53,8 +56,8 @@ version="\
GNU config.guess ($timestamp)
Originally written by Per Bothner.
-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
-Free Software Foundation, Inc.
+Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
+2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -66,11 +69,11 @@ Try \`$me --help' for more information."
while test $# -gt 0 ; do
case $1 in
--time-stamp | --time* | -t )
- echo "$timestamp" ; exit 0 ;;
+ echo "$timestamp" ; exit ;;
--version | -v )
- echo "$version" ; exit 0 ;;
+ echo "$version" ; exit ;;
--help | --h* | -h )
- echo "$usage"; exit 0 ;;
+ echo "$usage"; exit ;;
-- ) # Stop option processing
shift; break ;;
- ) # Use stdin as input.
@@ -104,7 +107,7 @@ set_cc_for_build='
trap "exitcode=\$?; (rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null) && exit \$exitcode" 0 ;
trap "rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null; exit 1" 1 2 13 15 ;
: ${TMPDIR=/tmp} ;
- { tmp=`(umask 077 && mktemp -d -q "$TMPDIR/cgXXXXXX") 2>/dev/null` && test -n "$tmp" && test -d "$tmp" ; } ||
+ { tmp=`(umask 077 && mktemp -d "$TMPDIR/cgXXXXXX") 2>/dev/null` && test -n "$tmp" && test -d "$tmp" ; } ||
{ test -n "$RANDOM" && tmp=$TMPDIR/cg$$-$RANDOM && (umask 077 && mkdir $tmp) ; } ||
{ tmp=$TMPDIR/cg-$$ && (umask 077 && mkdir $tmp) && echo "Warning: creating insecure temp directory" >&2 ; } ||
{ echo "$me: cannot create a temporary directory in $TMPDIR" >&2 ; exit 1 ; } ;
@@ -123,7 +126,7 @@ case $CC_FOR_BUILD,$HOST_CC,$CC in
;;
,,*) CC_FOR_BUILD=$CC ;;
,*,*) CC_FOR_BUILD=$HOST_CC ;;
-esac ;'
+esac ; set_cc_for_build= ;'
# This is needed to find uname on a Pyramid OSx when run in the BSD universe.
# (ghazi at noc.rutgers.edu 1994-08-24)
@@ -158,6 +161,7 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
arm*) machine=arm-unknown ;;
sh3el) machine=shl-unknown ;;
sh3eb) machine=sh-unknown ;;
+ sh5el) machine=sh5le-unknown ;;
*) machine=${UNAME_MACHINE_ARCH}-unknown ;;
esac
# The Operating System including object format, if it has switched
@@ -166,7 +170,7 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
arm*|i386|m68k|ns32k|sh3*|sparc|vax)
eval $set_cc_for_build
if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \
- | grep __ELF__ >/dev/null
+ | grep -q __ELF__
then
# Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout).
# Return netbsd for either. FIX?
@@ -196,55 +200,23 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
# contains redundant information, the shorter form:
# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used.
echo "${machine}-${os}${release}"
- exit 0 ;;
- amd64:OpenBSD:*:*)
- echo x86_64-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
- amiga:OpenBSD:*:*)
- echo m68k-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
- cats:OpenBSD:*:*)
- echo arm-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
- hp300:OpenBSD:*:*)
- echo m68k-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
- luna88k:OpenBSD:*:*)
- echo m88k-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
- mac68k:OpenBSD:*:*)
- echo m68k-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
- macppc:OpenBSD:*:*)
- echo powerpc-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
- mvme68k:OpenBSD:*:*)
- echo m68k-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
- mvme88k:OpenBSD:*:*)
- echo m88k-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
- mvmeppc:OpenBSD:*:*)
- echo powerpc-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
- sgi:OpenBSD:*:*)
- echo mips64-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
- sun3:OpenBSD:*:*)
- echo m68k-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*:OpenBSD:*:*)
- echo ${UNAME_MACHINE}-unknown-openbsd${UNAME_RELEASE}
- exit 0 ;;
+ UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'`
+ echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE}
+ exit ;;
*:ekkoBSD:*:*)
echo ${UNAME_MACHINE}-unknown-ekkobsd${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
+ *:SolidBSD:*:*)
+ echo ${UNAME_MACHINE}-unknown-solidbsd${UNAME_RELEASE}
+ exit ;;
macppc:MirBSD:*:*)
- echo powerppc-unknown-mirbsd${UNAME_RELEASE}
- exit 0 ;;
+ echo powerpc-unknown-mirbsd${UNAME_RELEASE}
+ exit ;;
*:MirBSD:*:*)
echo ${UNAME_MACHINE}-unknown-mirbsd${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
alpha:OSF1:*:*)
case $UNAME_RELEASE in
*4.0)
@@ -297,37 +269,43 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
# A Xn.n version is an unreleased experimental baselevel.
# 1.2 uses "1.2" for uname -r.
echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'`
- exit 0 ;;
+ exit ;;
Alpha\ *:Windows_NT*:*)
# How do we know it's Interix rather than the generic POSIX subsystem?
# Should we change UNAME_MACHINE based on the output of uname instead
# of the specific Alpha model?
echo alpha-pc-interix
- exit 0 ;;
+ exit ;;
21064:Windows_NT:50:3)
echo alpha-dec-winnt3.5
- exit 0 ;;
+ exit ;;
Amiga*:UNIX_System_V:4.0:*)
echo m68k-unknown-sysv4
- exit 0;;
+ exit ;;
*:[Aa]miga[Oo][Ss]:*:*)
echo ${UNAME_MACHINE}-unknown-amigaos
- exit 0 ;;
+ exit ;;
*:[Mm]orph[Oo][Ss]:*:*)
echo ${UNAME_MACHINE}-unknown-morphos
- exit 0 ;;
+ exit ;;
*:OS/390:*:*)
echo i370-ibm-openedition
- exit 0 ;;
+ exit ;;
+ *:z/VM:*:*)
+ echo s390-ibm-zvmoe
+ exit ;;
*:OS400:*:*)
echo powerpc-ibm-os400
- exit 0 ;;
+ exit ;;
arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*)
echo arm-acorn-riscix${UNAME_RELEASE}
- exit 0;;
+ exit ;;
+ arm:riscos:*:*|arm:RISCOS:*:*)
+ echo arm-unknown-riscos
+ exit ;;
SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*)
echo hppa1.1-hitachi-hiuxmpp
- exit 0;;
+ exit ;;
Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*)
# akee at wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE.
if test "`(/bin/universe) 2>/dev/null`" = att ; then
@@ -335,32 +313,48 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
else
echo pyramid-pyramid-bsd
fi
- exit 0 ;;
+ exit ;;
NILE*:*:*:dcosx)
echo pyramid-pyramid-svr4
- exit 0 ;;
+ exit ;;
DRS?6000:unix:4.0:6*)
echo sparc-icl-nx6
- exit 0 ;;
- DRS?6000:UNIX_SV:4.2*:7*)
+ exit ;;
+ DRS?6000:UNIX_SV:4.2*:7* | DRS?6000:isis:4.2*:7*)
case `/usr/bin/uname -p` in
- sparc) echo sparc-icl-nx7 && exit 0 ;;
+ sparc) echo sparc-icl-nx7; exit ;;
esac ;;
+ s390x:SunOS:*:*)
+ echo ${UNAME_MACHINE}-ibm-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+ exit ;;
sun4H:SunOS:5.*:*)
echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
- exit 0 ;;
+ exit ;;
sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*)
echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
- exit 0 ;;
- i86pc:SunOS:5.*:*)
- echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
- exit 0 ;;
+ exit ;;
+ i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*)
+ eval $set_cc_for_build
+ SUN_ARCH="i386"
+ # If there is a compiler, see if it is configured for 64-bit objects.
+ # Note that the Sun cc does not turn __LP64__ into 1 like gcc does.
+ # This test works for both compilers.
+ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then
+ if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \
+ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \
+ grep IS_64BIT_ARCH >/dev/null
+ then
+ SUN_ARCH="x86_64"
+ fi
+ fi
+ echo ${SUN_ARCH}-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+ exit ;;
sun4*:SunOS:6*:*)
# According to config.sub, this is the proper way to canonicalize
# SunOS6. Hard to guess exactly what SunOS6 will be like, but
# it's likely to be more like Solaris than SunOS4.
echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
- exit 0 ;;
+ exit ;;
sun4*:SunOS:*:*)
case "`/usr/bin/arch -k`" in
Series*|S4*)
@@ -369,10 +363,10 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
esac
# Japanese Language versions have a version number like `4.1.3-JL'.
echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'`
- exit 0 ;;
+ exit ;;
sun3*:SunOS:*:*)
echo m68k-sun-sunos${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
sun*:*:4.2BSD:*)
UNAME_RELEASE=`(sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null`
test "x${UNAME_RELEASE}" = "x" && UNAME_RELEASE=3
@@ -384,10 +378,10 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
echo sparc-sun-sunos${UNAME_RELEASE}
;;
esac
- exit 0 ;;
+ exit ;;
aushp:SunOS:*:*)
echo sparc-auspex-sunos${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
# The situation for MiNT is a little confusing. The machine name
# can be virtually everything (everything which is not
# "atarist" or "atariste" at least should have a processor
@@ -398,40 +392,40 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
# be no problem.
atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*)
echo m68k-atari-mint${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*)
echo m68k-atari-mint${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*)
echo m68k-atari-mint${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*)
echo m68k-milan-mint${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*)
echo m68k-hades-mint${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*)
echo m68k-unknown-mint${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
m68k:machten:*:*)
echo m68k-apple-machten${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
powerpc:machten:*:*)
echo powerpc-apple-machten${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
RISC*:Mach:*:*)
echo mips-dec-mach_bsd4.3
- exit 0 ;;
+ exit ;;
RISC*:ULTRIX:*:*)
echo mips-dec-ultrix${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
VAX*:ULTRIX*:*:*)
echo vax-dec-ultrix${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
2020:CLIX:*:* | 2430:CLIX:*:*)
echo clipper-intergraph-clix${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
mips:*:*:UMIPS | mips:*:*:RISCos)
eval $set_cc_for_build
sed 's/^ //' << EOF >$dummy.c
@@ -455,32 +449,33 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
exit (-1);
}
EOF
- $CC_FOR_BUILD -o $dummy $dummy.c \
- && $dummy `echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` \
- && exit 0
+ $CC_FOR_BUILD -o $dummy $dummy.c &&
+ dummyarg=`echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` &&
+ SYSTEM_NAME=`$dummy $dummyarg` &&
+ { echo "$SYSTEM_NAME"; exit; }
echo mips-mips-riscos${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
Motorola:PowerMAX_OS:*:*)
echo powerpc-motorola-powermax
- exit 0 ;;
+ exit ;;
Motorola:*:4.3:PL8-*)
echo powerpc-harris-powermax
- exit 0 ;;
+ exit ;;
Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*)
echo powerpc-harris-powermax
- exit 0 ;;
+ exit ;;
Night_Hawk:Power_UNIX:*:*)
echo powerpc-harris-powerunix
- exit 0 ;;
+ exit ;;
m88k:CX/UX:7*:*)
echo m88k-harris-cxux7
- exit 0 ;;
+ exit ;;
m88k:*:4*:R4*)
echo m88k-motorola-sysv4
- exit 0 ;;
+ exit ;;
m88k:*:3*:R3*)
echo m88k-motorola-sysv3
- exit 0 ;;
+ exit ;;
AViiON:dgux:*:*)
# DG/UX returns AViiON for all architectures
UNAME_PROCESSOR=`/usr/bin/uname -p`
@@ -496,29 +491,29 @@ EOF
else
echo i586-dg-dgux${UNAME_RELEASE}
fi
- exit 0 ;;
+ exit ;;
M88*:DolphinOS:*:*) # DolphinOS (SVR3)
echo m88k-dolphin-sysv3
- exit 0 ;;
+ exit ;;
M88*:*:R3*:*)
# Delta 88k system running SVR3
echo m88k-motorola-sysv3
- exit 0 ;;
+ exit ;;
XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3)
echo m88k-tektronix-sysv3
- exit 0 ;;
+ exit ;;
Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD)
echo m68k-tektronix-bsd
- exit 0 ;;
+ exit ;;
*:IRIX*:*:*)
echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'`
- exit 0 ;;
+ exit ;;
????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX.
- echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id
- exit 0 ;; # Note that: echo "'`uname -s`'" gives 'AIX '
+ echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id
+ exit ;; # Note that: echo "'`uname -s`'" gives 'AIX '
i*86:AIX:*:*)
echo i386-ibm-aix
- exit 0 ;;
+ exit ;;
ia64:AIX:*:*)
if [ -x /usr/bin/oslevel ] ; then
IBM_REV=`/usr/bin/oslevel`
@@ -526,7 +521,7 @@ EOF
IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE}
fi
echo ${UNAME_MACHINE}-ibm-aix${IBM_REV}
- exit 0 ;;
+ exit ;;
*:AIX:2:3)
if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then
eval $set_cc_for_build
@@ -541,15 +536,19 @@ EOF
exit(0);
}
EOF
- $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0
- echo rs6000-ibm-aix3.2.5
+ if $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy`
+ then
+ echo "$SYSTEM_NAME"
+ else
+ echo rs6000-ibm-aix3.2.5
+ fi
elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then
echo rs6000-ibm-aix3.2.4
else
echo rs6000-ibm-aix3.2
fi
- exit 0 ;;
- *:AIX:*:[45])
+ exit ;;
+ *:AIX:*:[456])
IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'`
if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then
IBM_ARCH=rs6000
@@ -562,28 +561,28 @@ EOF
IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE}
fi
echo ${IBM_ARCH}-ibm-aix${IBM_REV}
- exit 0 ;;
+ exit ;;
*:AIX:*:*)
echo rs6000-ibm-aix
- exit 0 ;;
+ exit ;;
ibmrt:4.4BSD:*|romp-ibm:BSD:*)
echo romp-ibm-bsd4.4
- exit 0 ;;
+ exit ;;
ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and
echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to
- exit 0 ;; # report: romp-ibm BSD 4.3
+ exit ;; # report: romp-ibm BSD 4.3
*:BOSX:*:*)
echo rs6000-bull-bosx
- exit 0 ;;
+ exit ;;
DPX/2?00:B.O.S.:*:*)
echo m68k-bull-sysv3
- exit 0 ;;
+ exit ;;
9000/[34]??:4.3bsd:1.*:*)
echo m68k-hp-bsd
- exit 0 ;;
+ exit ;;
hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*)
echo m68k-hp-bsd4.4
- exit 0 ;;
+ exit ;;
9000/[34678]??:HP-UX:*:*)
HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'`
case "${UNAME_MACHINE}" in
@@ -645,9 +644,19 @@ EOF
esac
if [ ${HP_ARCH} = "hppa2.0w" ]
then
- # avoid double evaluation of $set_cc_for_build
- test -n "$CC_FOR_BUILD" || eval $set_cc_for_build
- if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E -) | grep __LP64__ >/dev/null
+ eval $set_cc_for_build
+
+ # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating
+ # 32-bit code. hppa64-hp-hpux* has the same kernel and a compiler
+ # generating 64-bit code. GNU and HP use different nomenclature:
+ #
+ # $ CC_FOR_BUILD=cc ./config.guess
+ # => hppa2.0w-hp-hpux11.23
+ # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess
+ # => hppa64-hp-hpux11.23
+
+ if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) |
+ grep -q __LP64__
then
HP_ARCH="hppa2.0w"
else
@@ -655,11 +664,11 @@ EOF
fi
fi
echo ${HP_ARCH}-hp-hpux${HPUX_REV}
- exit 0 ;;
+ exit ;;
ia64:HP-UX:*:*)
HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'`
echo ia64-hp-hpux${HPUX_REV}
- exit 0 ;;
+ exit ;;
3050*:HI-UX:*:*)
eval $set_cc_for_build
sed 's/^ //' << EOF >$dummy.c
@@ -687,216 +696,244 @@ EOF
exit (0);
}
EOF
- $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0
+ $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` &&
+ { echo "$SYSTEM_NAME"; exit; }
echo unknown-hitachi-hiuxwe2
- exit 0 ;;
+ exit ;;
9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* )
echo hppa1.1-hp-bsd
- exit 0 ;;
+ exit ;;
9000/8??:4.3bsd:*:*)
echo hppa1.0-hp-bsd
- exit 0 ;;
+ exit ;;
*9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*)
echo hppa1.0-hp-mpeix
- exit 0 ;;
+ exit ;;
hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* )
echo hppa1.1-hp-osf
- exit 0 ;;
+ exit ;;
hp8??:OSF1:*:*)
echo hppa1.0-hp-osf
- exit 0 ;;
+ exit ;;
i*86:OSF1:*:*)
if [ -x /usr/sbin/sysversion ] ; then
echo ${UNAME_MACHINE}-unknown-osf1mk
else
echo ${UNAME_MACHINE}-unknown-osf1
fi
- exit 0 ;;
+ exit ;;
parisc*:Lites*:*:*)
echo hppa1.1-hp-lites
- exit 0 ;;
+ exit ;;
C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*)
echo c1-convex-bsd
- exit 0 ;;
+ exit ;;
C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*)
if getsysinfo -f scalar_acc
then echo c32-convex-bsd
else echo c2-convex-bsd
fi
- exit 0 ;;
+ exit ;;
C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*)
echo c34-convex-bsd
- exit 0 ;;
+ exit ;;
C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*)
echo c38-convex-bsd
- exit 0 ;;
+ exit ;;
C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*)
echo c4-convex-bsd
- exit 0 ;;
+ exit ;;
CRAY*Y-MP:*:*:*)
echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
- exit 0 ;;
+ exit ;;
CRAY*[A-Z]90:*:*:*)
echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \
| sed -e 's/CRAY.*\([A-Z]90\)/\1/' \
-e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \
-e 's/\.[^.]*$/.X/'
- exit 0 ;;
+ exit ;;
CRAY*TS:*:*:*)
echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
- exit 0 ;;
+ exit ;;
CRAY*T3E:*:*:*)
echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
- exit 0 ;;
+ exit ;;
CRAY*SV1:*:*:*)
echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
- exit 0 ;;
+ exit ;;
*:UNICOS/mp:*:*)
echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
- exit 0 ;;
+ exit ;;
F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*)
FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'`
FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'`
FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'`
echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
- exit 0 ;;
+ exit ;;
5000:UNIX_System_V:4.*:*)
FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'`
FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'`
echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
- exit 0 ;;
+ exit ;;
i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*)
echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
sparc*:BSD/OS:*:*)
echo sparc-unknown-bsdi${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*:BSD/OS:*:*)
echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*:FreeBSD:*:*)
- echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`
- exit 0 ;;
+ case ${UNAME_MACHINE} in
+ pc98)
+ echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
+ amd64)
+ echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
+ *)
+ echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
+ esac
+ exit ;;
i*:CYGWIN*:*)
echo ${UNAME_MACHINE}-pc-cygwin
- exit 0 ;;
- i*:MINGW*:*)
+ exit ;;
+ *:MINGW*:*)
echo ${UNAME_MACHINE}-pc-mingw32
- exit 0 ;;
+ exit ;;
+ i*:windows32*:*)
+ # uname -m includes "-pc" on this system.
+ echo ${UNAME_MACHINE}-mingw32
+ exit ;;
i*:PW*:*)
echo ${UNAME_MACHINE}-pc-pw32
- exit 0 ;;
- x86:Interix*:[34]*)
- echo i586-pc-interix${UNAME_RELEASE}|sed -e 's/\..*//'
- exit 0 ;;
+ exit ;;
+ *:Interix*:[3456]*)
+ case ${UNAME_MACHINE} in
+ x86)
+ echo i586-pc-interix${UNAME_RELEASE}
+ exit ;;
+ EM64T | authenticamd | genuineintel)
+ echo x86_64-unknown-interix${UNAME_RELEASE}
+ exit ;;
+ IA64)
+ echo ia64-unknown-interix${UNAME_RELEASE}
+ exit ;;
+ esac ;;
[345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*)
echo i${UNAME_MACHINE}-pc-mks
- exit 0 ;;
+ exit ;;
+ 8664:Windows_NT:*)
+ echo x86_64-pc-mks
+ exit ;;
i*:Windows_NT*:* | Pentium*:Windows_NT*:*)
# How do we know it's Interix rather than the generic POSIX subsystem?
# It also conflicts with pre-2.0 versions of AT&T UWIN. Should we
# UNAME_MACHINE based on the output of uname instead of i386?
echo i586-pc-interix
- exit 0 ;;
+ exit ;;
i*:UWIN*:*)
echo ${UNAME_MACHINE}-pc-uwin
- exit 0 ;;
+ exit ;;
+ amd64:CYGWIN*:*:* | x86_64:CYGWIN*:*:*)
+ echo x86_64-unknown-cygwin
+ exit ;;
p*:CYGWIN*:*)
echo powerpcle-unknown-cygwin
- exit 0 ;;
+ exit ;;
prep*:SunOS:5.*:*)
echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
- exit 0 ;;
+ exit ;;
*:GNU:*:*)
# the GNU system
echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`
- exit 0 ;;
+ exit ;;
*:GNU/*:*:*)
# other systems with GNU libc and userland
echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu
- exit 0 ;;
+ exit ;;
i*86:Minix:*:*)
echo ${UNAME_MACHINE}-pc-minix
- exit 0 ;;
+ exit ;;
+ alpha:Linux:*:*)
+ case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
+ EV5) UNAME_MACHINE=alphaev5 ;;
+ EV56) UNAME_MACHINE=alphaev56 ;;
+ PCA56) UNAME_MACHINE=alphapca56 ;;
+ PCA57) UNAME_MACHINE=alphapca56 ;;
+ EV6) UNAME_MACHINE=alphaev6 ;;
+ EV67) UNAME_MACHINE=alphaev67 ;;
+ EV68*) UNAME_MACHINE=alphaev68 ;;
+ esac
+ objdump --private-headers /bin/sh | grep -q ld.so.1
+ if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi
+ echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC}
+ exit ;;
arm*:Linux:*:*)
+ eval $set_cc_for_build
+ if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \
+ | grep -q __ARM_EABI__
+ then
+ echo ${UNAME_MACHINE}-unknown-linux-gnu
+ else
+ echo ${UNAME_MACHINE}-unknown-linux-gnueabi
+ fi
+ exit ;;
+ avr32*:Linux:*:*)
echo ${UNAME_MACHINE}-unknown-linux-gnu
- exit 0 ;;
+ exit ;;
cris:Linux:*:*)
echo cris-axis-linux-gnu
- exit 0 ;;
+ exit ;;
crisv32:Linux:*:*)
echo crisv32-axis-linux-gnu
- exit 0 ;;
+ exit ;;
frv:Linux:*:*)
echo frv-unknown-linux-gnu
- exit 0 ;;
+ exit ;;
+ i*86:Linux:*:*)
+ echo ${UNAME_MACHINE}-pc-linux-gnu
+ exit ;;
ia64:Linux:*:*)
echo ${UNAME_MACHINE}-unknown-linux-gnu
- exit 0 ;;
+ exit ;;
m32r*:Linux:*:*)
echo ${UNAME_MACHINE}-unknown-linux-gnu
- exit 0 ;;
+ exit ;;
m68*:Linux:*:*)
echo ${UNAME_MACHINE}-unknown-linux-gnu
- exit 0 ;;
- mips:Linux:*:*)
- eval $set_cc_for_build
- sed 's/^ //' << EOF >$dummy.c
- #undef CPU
- #undef mips
- #undef mipsel
- #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL)
- CPU=mipsel
- #else
- #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB)
- CPU=mips
- #else
- CPU=
- #endif
- #endif
-EOF
- eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=`
- test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0
- ;;
- mips64:Linux:*:*)
+ exit ;;
+ mips:Linux:*:* | mips64:Linux:*:*)
eval $set_cc_for_build
sed 's/^ //' << EOF >$dummy.c
#undef CPU
- #undef mips64
- #undef mips64el
+ #undef ${UNAME_MACHINE}
+ #undef ${UNAME_MACHINE}el
#if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL)
- CPU=mips64el
+ CPU=${UNAME_MACHINE}el
#else
#if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB)
- CPU=mips64
+ CPU=${UNAME_MACHINE}
#else
CPU=
#endif
#endif
EOF
- eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=`
- test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0
+ eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n '
+ /^CPU/{
+ s: ::g
+ p
+ }'`"
+ test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; }
;;
- ppc:Linux:*:*)
- echo powerpc-unknown-linux-gnu
- exit 0 ;;
- ppc64:Linux:*:*)
- echo powerpc64-unknown-linux-gnu
- exit 0 ;;
- alpha:Linux:*:*)
- case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
- EV5) UNAME_MACHINE=alphaev5 ;;
- EV56) UNAME_MACHINE=alphaev56 ;;
- PCA56) UNAME_MACHINE=alphapca56 ;;
- PCA57) UNAME_MACHINE=alphapca56 ;;
- EV6) UNAME_MACHINE=alphaev6 ;;
- EV67) UNAME_MACHINE=alphaev67 ;;
- EV68*) UNAME_MACHINE=alphaev68 ;;
- esac
- objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null
- if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi
- echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC}
- exit 0 ;;
+ or32:Linux:*:*)
+ echo or32-unknown-linux-gnu
+ exit ;;
+ padre:Linux:*:*)
+ echo sparc-unknown-linux-gnu
+ exit ;;
+ parisc64:Linux:*:* | hppa64:Linux:*:*)
+ echo hppa64-unknown-linux-gnu
+ exit ;;
parisc:Linux:*:* | hppa:Linux:*:*)
# Look for CPU level
case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in
@@ -904,87 +941,40 @@ EOF
PA8*) echo hppa2.0-unknown-linux-gnu ;;
*) echo hppa-unknown-linux-gnu ;;
esac
- exit 0 ;;
- parisc64:Linux:*:* | hppa64:Linux:*:*)
- echo hppa64-unknown-linux-gnu
- exit 0 ;;
+ exit ;;
+ ppc64:Linux:*:*)
+ echo powerpc64-unknown-linux-gnu
+ exit ;;
+ ppc:Linux:*:*)
+ echo powerpc-unknown-linux-gnu
+ exit ;;
s390:Linux:*:* | s390x:Linux:*:*)
echo ${UNAME_MACHINE}-ibm-linux
- exit 0 ;;
+ exit ;;
sh64*:Linux:*:*)
echo ${UNAME_MACHINE}-unknown-linux-gnu
- exit 0 ;;
+ exit ;;
sh*:Linux:*:*)
echo ${UNAME_MACHINE}-unknown-linux-gnu
- exit 0 ;;
+ exit ;;
sparc:Linux:*:* | sparc64:Linux:*:*)
echo ${UNAME_MACHINE}-unknown-linux-gnu
- exit 0 ;;
+ exit ;;
+ vax:Linux:*:*)
+ echo ${UNAME_MACHINE}-dec-linux-gnu
+ exit ;;
x86_64:Linux:*:*)
echo x86_64-unknown-linux-gnu
- exit 0 ;;
- i*86:Linux:*:*)
- # The BFD linker knows what the default object file format is, so
- # first see if it will tell us. cd to the root directory to prevent
- # problems with other programs or directories called `ld' in the path.
- # Set LC_ALL=C to ensure ld outputs messages in English.
- ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \
- | sed -ne '/supported targets:/!d
- s/[ ][ ]*/ /g
- s/.*supported targets: *//
- s/ .*//
- p'`
- case "$ld_supported_targets" in
- elf32-i386)
- TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu"
- ;;
- a.out-i386-linux)
- echo "${UNAME_MACHINE}-pc-linux-gnuaout"
- exit 0 ;;
- coff-i386)
- echo "${UNAME_MACHINE}-pc-linux-gnucoff"
- exit 0 ;;
- "")
- # Either a pre-BFD a.out linker (linux-gnuoldld) or
- # one that does not give us useful --help.
- echo "${UNAME_MACHINE}-pc-linux-gnuoldld"
- exit 0 ;;
- esac
- # Determine whether the default compiler is a.out or elf
- eval $set_cc_for_build
- sed 's/^ //' << EOF >$dummy.c
- #include <features.h>
- #ifdef __ELF__
- # ifdef __GLIBC__
- # if __GLIBC__ >= 2
- LIBC=gnu
- # else
- LIBC=gnulibc1
- # endif
- # else
- LIBC=gnulibc1
- # endif
- #else
- #ifdef __INTEL_COMPILER
- LIBC=gnu
- #else
- LIBC=gnuaout
- #endif
- #endif
- #ifdef __dietlibc__
- LIBC=dietlibc
- #endif
-EOF
- eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^LIBC=`
- test x"${LIBC}" != x && echo "${UNAME_MACHINE}-pc-linux-${LIBC}" && exit 0
- test x"${TENTATIVE}" != x && echo "${TENTATIVE}" && exit 0
- ;;
+ exit ;;
+ xtensa*:Linux:*:*)
+ echo ${UNAME_MACHINE}-unknown-linux-gnu
+ exit ;;
i*86:DYNIX/ptx:4*:*)
# ptx 4.0 does uname -s correctly, with DYNIX/ptx in there.
# earlier versions are messed up and put the nodename in both
# sysname and nodename.
echo i386-sequent-sysv4
- exit 0 ;;
+ exit ;;
i*86:UNIX_SV:4.2MP:2.*)
# Unixware is an offshoot of SVR4, but it has its own version
# number series starting with 2...
@@ -992,27 +982,27 @@ EOF
# I just have to hope. -- rms.
# Use sysv4.2uw... so that sysv4* matches it.
echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION}
- exit 0 ;;
+ exit ;;
i*86:OS/2:*:*)
# If we were able to find `uname', then EMX Unix compatibility
# is probably installed.
echo ${UNAME_MACHINE}-pc-os2-emx
- exit 0 ;;
+ exit ;;
i*86:XTS-300:*:STOP)
echo ${UNAME_MACHINE}-unknown-stop
- exit 0 ;;
+ exit ;;
i*86:atheos:*:*)
echo ${UNAME_MACHINE}-unknown-atheos
- exit 0 ;;
- i*86:syllable:*:*)
+ exit ;;
+ i*86:syllable:*:*)
echo ${UNAME_MACHINE}-pc-syllable
- exit 0 ;;
- i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*)
+ exit ;;
+ i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.[02]*:*)
echo i386-unknown-lynxos${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
i*86:*DOS:*:*)
echo ${UNAME_MACHINE}-pc-msdosdjgpp
- exit 0 ;;
+ exit ;;
i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*)
UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'`
if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then
@@ -1020,15 +1010,16 @@ EOF
else
echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL}
fi
- exit 0 ;;
- i*86:*:5:[78]*)
+ exit ;;
+ i*86:*:5:[678]*)
+ # UnixWare 7.x, OpenUNIX and OpenServer 6.
case `/bin/uname -X | grep "^Machine"` in
*486*) UNAME_MACHINE=i486 ;;
*Pentium) UNAME_MACHINE=i586 ;;
*Pent*|*Celeron) UNAME_MACHINE=i686 ;;
esac
echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION}
- exit 0 ;;
+ exit ;;
i*86:*:3.2:*)
if test -f /usr/options/cb.name; then
UNAME_REL=`sed -n 's/.*Version //p' </usr/options/cb.name`
@@ -1046,73 +1037,86 @@ EOF
else
echo ${UNAME_MACHINE}-pc-sysv32
fi
- exit 0 ;;
+ exit ;;
pc:*:*:*)
# Left here for compatibility:
# uname -m prints for DJGPP always 'pc', but it prints nothing about
- # the processor, so we play safe by assuming i386.
- echo i386-pc-msdosdjgpp
- exit 0 ;;
+ # the processor, so we play safe by assuming i586.
+ # Note: whatever this is, it MUST be the same as what config.sub
+ # prints for the "djgpp" host, or else GDB configury will decide that
+ # this is a cross-build.
+ echo i586-pc-msdosdjgpp
+ exit ;;
Intel:Mach:3*:*)
echo i386-pc-mach3
- exit 0 ;;
+ exit ;;
paragon:*:*:*)
echo i860-intel-osf1
- exit 0 ;;
+ exit ;;
i860:*:4.*:*) # i860-SVR4
if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then
echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4
else # Add other i860-SVR4 vendors below as they are discovered.
echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4
fi
- exit 0 ;;
+ exit ;;
mini*:CTIX:SYS*5:*)
# "miniframe"
echo m68010-convergent-sysv
- exit 0 ;;
+ exit ;;
mc68k:UNIX:SYSTEM5:3.51m)
echo m68k-convergent-sysv
- exit 0 ;;
+ exit ;;
M680?0:D-NIX:5.3:*)
echo m68k-diab-dnix
- exit 0 ;;
+ exit ;;
M68*:*:R3V[5678]*:*)
- test -r /sysV68 && echo 'm68k-motorola-sysv' && exit 0 ;;
+ test -r /sysV68 && { echo 'm68k-motorola-sysv'; exit; } ;;
3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0)
OS_REL=''
test -r /etc/.relid \
&& OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid`
/bin/uname -p 2>/dev/null | grep 86 >/dev/null \
- && echo i486-ncr-sysv4.3${OS_REL} && exit 0
+ && { echo i486-ncr-sysv4.3${OS_REL}; exit; }
/bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \
- && echo i586-ncr-sysv4.3${OS_REL} && exit 0 ;;
+ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;;
3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*)
/bin/uname -p 2>/dev/null | grep 86 >/dev/null \
- && echo i486-ncr-sysv4 && exit 0 ;;
+ && { echo i486-ncr-sysv4; exit; } ;;
+ NCR*:*:4.2:* | MPRAS*:*:4.2:*)
+ OS_REL='.3'
+ test -r /etc/.relid \
+ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid`
+ /bin/uname -p 2>/dev/null | grep 86 >/dev/null \
+ && { echo i486-ncr-sysv4.3${OS_REL}; exit; }
+ /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \
+ && { echo i586-ncr-sysv4.3${OS_REL}; exit; }
+ /bin/uname -p 2>/dev/null | /bin/grep pteron >/dev/null \
+ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;;
m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*)
echo m68k-unknown-lynxos${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
mc68030:UNIX_System_V:4.*:*)
echo m68k-atari-sysv4
- exit 0 ;;
+ exit ;;
TSUNAMI:LynxOS:2.*:*)
echo sparc-unknown-lynxos${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
rs6000:LynxOS:2.*:*)
echo rs6000-unknown-lynxos${UNAME_RELEASE}
- exit 0 ;;
- PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*)
+ exit ;;
+ PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.[02]*:*)
echo powerpc-unknown-lynxos${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
SM[BE]S:UNIX_SV:*:*)
echo mips-dde-sysv${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
RM*:ReliantUNIX-*:*:*)
echo mips-sni-sysv4
- exit 0 ;;
+ exit ;;
RM*:SINIX-*:*:*)
echo mips-sni-sysv4
- exit 0 ;;
+ exit ;;
*:SINIX-*:*:*)
if uname -p 2>/dev/null >/dev/null ; then
UNAME_MACHINE=`(uname -p) 2>/dev/null`
@@ -1120,69 +1124,94 @@ EOF
else
echo ns32k-sni-sysv
fi
- exit 0 ;;
+ exit ;;
PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort
# says <Richard.M.Bartel at ccMail.Census.GOV>
echo i586-unisys-sysv4
- exit 0 ;;
+ exit ;;
*:UNIX_System_V:4*:FTX*)
# From Gerald Hewes <hewes at openmarket.com>.
# How about differentiating between stratus architectures? -djm
echo hppa1.1-stratus-sysv4
- exit 0 ;;
+ exit ;;
*:*:*:FTX*)
# From seanf at swdc.stratus.com.
echo i860-stratus-sysv4
- exit 0 ;;
+ exit ;;
+ i*86:VOS:*:*)
+ # From Paul.Green at stratus.com.
+ echo ${UNAME_MACHINE}-stratus-vos
+ exit ;;
*:VOS:*:*)
# From Paul.Green at stratus.com.
echo hppa1.1-stratus-vos
- exit 0 ;;
+ exit ;;
mc68*:A/UX:*:*)
echo m68k-apple-aux${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
news*:NEWS-OS:6*:*)
echo mips-sony-newsos6
- exit 0 ;;
+ exit ;;
R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*)
if [ -d /usr/nec ]; then
echo mips-nec-sysv${UNAME_RELEASE}
else
echo mips-unknown-sysv${UNAME_RELEASE}
fi
- exit 0 ;;
+ exit ;;
BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only.
echo powerpc-be-beos
- exit 0 ;;
+ exit ;;
BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only.
echo powerpc-apple-beos
- exit 0 ;;
+ exit ;;
BePC:BeOS:*:*) # BeOS running on Intel PC compatible.
echo i586-pc-beos
- exit 0 ;;
+ exit ;;
+ BePC:Haiku:*:*) # Haiku running on Intel PC compatible.
+ echo i586-pc-haiku
+ exit ;;
SX-4:SUPER-UX:*:*)
echo sx4-nec-superux${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
SX-5:SUPER-UX:*:*)
echo sx5-nec-superux${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
SX-6:SUPER-UX:*:*)
echo sx6-nec-superux${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
+ SX-7:SUPER-UX:*:*)
+ echo sx7-nec-superux${UNAME_RELEASE}
+ exit ;;
+ SX-8:SUPER-UX:*:*)
+ echo sx8-nec-superux${UNAME_RELEASE}
+ exit ;;
+ SX-8R:SUPER-UX:*:*)
+ echo sx8r-nec-superux${UNAME_RELEASE}
+ exit ;;
Power*:Rhapsody:*:*)
echo powerpc-apple-rhapsody${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*:Rhapsody:*:*)
echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*:Darwin:*:*)
UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown
case $UNAME_PROCESSOR in
- *86) UNAME_PROCESSOR=i686 ;;
+ i386)
+ eval $set_cc_for_build
+ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then
+ if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \
+ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \
+ grep IS_64BIT_ARCH >/dev/null
+ then
+ UNAME_PROCESSOR="x86_64"
+ fi
+ fi ;;
unknown) UNAME_PROCESSOR=powerpc ;;
esac
echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*:procnto*:*:* | *:QNX:[0123456789]*:*)
UNAME_PROCESSOR=`uname -p`
if test "$UNAME_PROCESSOR" = "x86"; then
@@ -1190,22 +1219,25 @@ EOF
UNAME_MACHINE=pc
fi
echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*:QNX:*:4*)
echo i386-pc-qnx
- exit 0 ;;
+ exit ;;
+ NSE-?:NONSTOP_KERNEL:*:*)
+ echo nse-tandem-nsk${UNAME_RELEASE}
+ exit ;;
NSR-?:NONSTOP_KERNEL:*:*)
echo nsr-tandem-nsk${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*:NonStop-UX:*:*)
echo mips-compaq-nonstopux
- exit 0 ;;
+ exit ;;
BS2000:POSIX*:*:*)
echo bs2000-siemens-sysv
- exit 0 ;;
+ exit ;;
DS/*:UNIX_System_V:*:*)
echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*:Plan9:*:*)
# "uname -m" is not consistent, so use $cputype instead. 386
# is converted to i386 for consistency with other x86
@@ -1216,38 +1248,50 @@ EOF
UNAME_MACHINE="$cputype"
fi
echo ${UNAME_MACHINE}-unknown-plan9
- exit 0 ;;
+ exit ;;
*:TOPS-10:*:*)
echo pdp10-unknown-tops10
- exit 0 ;;
+ exit ;;
*:TENEX:*:*)
echo pdp10-unknown-tenex
- exit 0 ;;
+ exit ;;
KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*)
echo pdp10-dec-tops20
- exit 0 ;;
+ exit ;;
XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*)
echo pdp10-xkl-tops20
- exit 0 ;;
+ exit ;;
*:TOPS-20:*:*)
echo pdp10-unknown-tops20
- exit 0 ;;
+ exit ;;
*:ITS:*:*)
echo pdp10-unknown-its
- exit 0 ;;
+ exit ;;
SEI:*:*:SEIUX)
echo mips-sei-seiux${UNAME_RELEASE}
- exit 0 ;;
+ exit ;;
*:DragonFly:*:*)
echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`
- exit 0 ;;
+ exit ;;
*:*VMS:*:*)
UNAME_MACHINE=`(uname -p) 2>/dev/null`
case "${UNAME_MACHINE}" in
- A*) echo alpha-dec-vms && exit 0 ;;
- I*) echo ia64-dec-vms && exit 0 ;;
- V*) echo vax-dec-vms && exit 0 ;;
- esac
+ A*) echo alpha-dec-vms ; exit ;;
+ I*) echo ia64-dec-vms ; exit ;;
+ V*) echo vax-dec-vms ; exit ;;
+ esac ;;
+ *:XENIX:*:SysV)
+ echo i386-pc-xenix
+ exit ;;
+ i*86:skyos:*:*)
+ echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE}` | sed -e 's/ .*$//'
+ exit ;;
+ i*86:rdos:*:*)
+ echo ${UNAME_MACHINE}-pc-rdos
+ exit ;;
+ i*86:AROS:*:*)
+ echo ${UNAME_MACHINE}-pc-aros
+ exit ;;
esac
#echo '(No uname command or uname output not recognized.)' 1>&2
@@ -1279,7 +1323,7 @@ main ()
#endif
#if defined (__arm) && defined (__acorn) && defined (__unix)
- printf ("arm-acorn-riscix"); exit (0);
+ printf ("arm-acorn-riscix\n"); exit (0);
#endif
#if defined (hp300) && !defined (hpux)
@@ -1368,11 +1412,12 @@ main ()
}
EOF
-$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && $dummy && exit 0
+$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` &&
+ { echo "$SYSTEM_NAME"; exit; }
# Apollos put the system type in the environment.
-test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit 0; }
+test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; }
# Convex versions that predate uname can use getsysinfo(1)
@@ -1381,22 +1426,22 @@ then
case `getsysinfo -f cpu_type` in
c1*)
echo c1-convex-bsd
- exit 0 ;;
+ exit ;;
c2*)
if getsysinfo -f scalar_acc
then echo c32-convex-bsd
else echo c2-convex-bsd
fi
- exit 0 ;;
+ exit ;;
c34*)
echo c34-convex-bsd
- exit 0 ;;
+ exit ;;
c38*)
echo c38-convex-bsd
- exit 0 ;;
+ exit ;;
c4*)
echo c4-convex-bsd
- exit 0 ;;
+ exit ;;
esac
fi
@@ -1407,7 +1452,9 @@ This script, last modified $timestamp, has failed to recognize
the operating system you are using. It is advised that you
download the most up to date version of the config scripts from
- ftp://ftp.gnu.org/pub/gnu/config/
+ http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD
+and
+ http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD
If the version you run ($0) is already up to date, please
send the following data and any information you think might be
diff --git a/libclamav/c++/llvm/autoconf/config.sub b/libclamav/c++/llvm/autoconf/config.sub
index edb6b66..8ca084b 100755
--- a/libclamav/c++/llvm/autoconf/config.sub
+++ b/libclamav/c++/llvm/autoconf/config.sub
@@ -1,9 +1,10 @@
#! /bin/sh
# Configuration validation subroutine script.
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-# 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+# Free Software Foundation, Inc.
-timestamp='2004-08-29'
+timestamp='2009-08-19'
# This file is (in principle) common to ALL GNU software.
# The presence of a machine in this file suggests that SOME GNU software
@@ -21,22 +22,26 @@ timestamp='2004-08-29'
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
-
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+# 02110-1301, USA.
+#
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
# the same distribution terms that you use for the rest of that program.
+
# Please send patches to <config-patches at gnu.org>. Submit a context
-# diff and a properly formatted ChangeLog entry.
+# diff and a properly formatted GNU ChangeLog entry.
#
# Configuration subroutine to validate and canonicalize a configuration type.
# Supply the specified configuration type as an argument.
# If it is invalid, we print an error message on stderr and exit with code 1.
# Otherwise, we print the canonical config type on stdout and succeed.
+# You can get the latest version of this script from:
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD
+
# This file is supposed to be the same for all GNU packages
# and recognize all the CPU types, system types and aliases
# that are meaningful with *any* GNU software.
@@ -70,8 +75,8 @@ Report bugs and patches to <config-patches at gnu.org>."
version="\
GNU config.sub ($timestamp)
-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
-Free Software Foundation, Inc.
+Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
+2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -83,11 +88,11 @@ Try \`$me --help' for more information."
while test $# -gt 0 ; do
case $1 in
--time-stamp | --time* | -t )
- echo "$timestamp" ; exit 0 ;;
+ echo "$timestamp" ; exit ;;
--version | -v )
- echo "$version" ; exit 0 ;;
+ echo "$version" ; exit ;;
--help | --h* | -h )
- echo "$usage"; exit 0 ;;
+ echo "$usage"; exit ;;
-- ) # Stop option processing
shift; break ;;
- ) # Use stdin as input.
@@ -99,7 +104,7 @@ while test $# -gt 0 ; do
*local*)
# First pass through any local machine types.
echo $1
- exit 0;;
+ exit ;;
* )
break ;;
@@ -118,8 +123,10 @@ esac
# Here we must recognize all the valid KERNEL-OS combinations.
maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
case $maybe_os in
- nto-qnx* | linux-gnu* | linux-dietlibc | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | \
- kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | storm-chaos* | os2-emx* | rtmk-nova*)
+ nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \
+ uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \
+ kopensolaris*-gnu* | \
+ storm-chaos* | os2-emx* | rtmk-nova*)
os=-$maybe_os
basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`
;;
@@ -145,10 +152,13 @@ case $os in
-convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\
-c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \
-harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \
- -apple | -axis | -knuth | -cray)
+ -apple | -axis | -knuth | -cray | -microblaze)
os=
basic_machine=$1
;;
+ -bluegene*)
+ os=-cnk
+ ;;
-sim | -cisco | -oki | -wec | -winbond)
os=
basic_machine=$1
@@ -170,6 +180,10 @@ case $os in
-hiux*)
os=-hiuxwe2
;;
+ -sco6)
+ os=-sco5v6
+ basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+ ;;
-sco5)
os=-sco3.2v5
basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
@@ -186,6 +200,10 @@ case $os in
# Don't forget version if it is 3.2v4 or newer.
basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
;;
+ -sco5v6*)
+ # Don't forget version if it is 3.2v4 or newer.
+ basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+ ;;
-sco*)
os=-sco3.2v2
basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
@@ -230,22 +248,28 @@ case $basic_machine in
| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
| am33_2.0 \
- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr \
+ | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \
+ | bfin \
| c4x | clipper \
| d10v | d30v | dlx | dsp16xx \
- | fr30 | frv \
+ | fido | fr30 | frv \
| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
| i370 | i860 | i960 | ia64 \
| ip2k | iq2000 \
- | m32r | m32rle | m68000 | m68k | m88k | mcore \
+ | lm32 \
+ | m32c | m32r | m32rle | m68000 | m68k | m88k \
+ | maxq | mb | microblaze | mcore | mep | metag \
| mips | mipsbe | mipseb | mipsel | mipsle \
| mips16 \
| mips64 | mips64el \
- | mips64vr | mips64vrel \
+ | mips64octeon | mips64octeonel \
| mips64orion | mips64orionel \
+ | mips64r5900 | mips64r5900el \
+ | mips64vr | mips64vrel \
| mips64vr4100 | mips64vr4100el \
| mips64vr4300 | mips64vr4300el \
| mips64vr5000 | mips64vr5000el \
+ | mips64vr5900 | mips64vr5900el \
| mipsisa32 | mipsisa32el \
| mipsisa32r2 | mipsisa32r2el \
| mipsisa64 | mipsisa64el \
@@ -254,21 +278,26 @@ case $basic_machine in
| mipsisa64sr71k | mipsisa64sr71kel \
| mipstx39 | mipstx39el \
| mn10200 | mn10300 \
+ | moxie \
+ | mt \
| msp430 \
+ | nios | nios2 \
| ns16k | ns32k \
- | openrisc | or32 \
+ | or32 \
| pdp10 | pdp11 | pj | pjl \
| powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
| pyramid \
- | sh | sh[1234] | sh[23]e | sh[34]eb | shbe | shle | sh[1234]le | sh3ele \
+ | score \
+ | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
| sh64 | sh64le \
- | sparc | sparc64 | sparc86x | sparclet | sparclite | sparcv8 | sparcv9 | sparcv9b \
- | strongarm \
+ | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
+ | sparcv8 | sparcv9 | sparcv9b | sparcv9v \
+ | spu | strongarm \
| tahoe | thumb | tic4x | tic80 | tron \
| v850 | v850e \
| we32k \
- | x86 | xscale | xstormy16 | xtensa \
- | z8k)
+ | x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \
+ | z8k | z80)
basic_machine=$basic_machine-unknown
;;
m6811 | m68hc11 | m6812 | m68hc12)
@@ -278,6 +307,9 @@ case $basic_machine in
;;
m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k)
;;
+ ms1)
+ basic_machine=mt-unknown
+ ;;
# We use `pc' rather than `unknown'
# because (1) that's what they normally are, and
@@ -297,28 +329,32 @@ case $basic_machine in
| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
| alphapca5[67]-* | alpha64pca5[67]-* | arc-* \
| arm-* | armbe-* | armle-* | armeb-* | armv*-* \
- | avr-* \
- | bs2000-* \
+ | avr-* | avr32-* \
+ | bfin-* | bs2000-* \
| c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \
| clipper-* | craynv-* | cydra-* \
| d10v-* | d30v-* | dlx-* \
| elxsi-* \
- | f30[01]-* | f700-* | fr30-* | frv-* | fx80-* \
+ | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \
| h8300-* | h8500-* \
| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
| i*86-* | i860-* | i960-* | ia64-* \
| ip2k-* | iq2000-* \
- | m32r-* | m32rle-* \
+ | lm32-* \
+ | m32c-* | m32r-* | m32rle-* \
| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
- | m88110-* | m88k-* | mcore-* \
+ | m88110-* | m88k-* | maxq-* | mcore-* | metag-* | microblaze-* \
| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
| mips16-* \
| mips64-* | mips64el-* \
- | mips64vr-* | mips64vrel-* \
+ | mips64octeon-* | mips64octeonel-* \
| mips64orion-* | mips64orionel-* \
+ | mips64r5900-* | mips64r5900el-* \
+ | mips64vr-* | mips64vrel-* \
| mips64vr4100-* | mips64vr4100el-* \
| mips64vr4300-* | mips64vr4300el-* \
| mips64vr5000-* | mips64vr5000el-* \
+ | mips64vr5900-* | mips64vr5900el-* \
| mipsisa32-* | mipsisa32el-* \
| mipsisa32r2-* | mipsisa32r2el-* \
| mipsisa64-* | mipsisa64el-* \
@@ -327,26 +363,33 @@ case $basic_machine in
| mipsisa64sr71k-* | mipsisa64sr71kel-* \
| mipstx39-* | mipstx39el-* \
| mmix-* \
+ | mt-* \
| msp430-* \
+ | nios-* | nios2-* \
| none-* | np1-* | ns16k-* | ns32k-* \
| orion-* \
| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \
| pyramid-* \
| romp-* | rs6000-* \
- | sh-* | sh[1234]-* | sh[23]e-* | sh[34]eb-* | shbe-* \
+ | sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
- | sparc-* | sparc64-* | sparc86x-* | sparclet-* | sparclite-* \
- | sparcv8-* | sparcv9-* | sparcv9b-* | strongarm-* | sv1-* | sx?-* \
+ | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
+ | sparclite-* \
+ | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \
| tahoe-* | thumb-* \
- | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \
+ | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* | tile-* \
| tron-* \
| v850-* | v850e-* | vax-* \
| we32k-* \
- | x86-* | x86_64-* | xps100-* | xscale-* | xstormy16-* \
- | xtensa-* \
+ | x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \
+ | xstormy16-* | xtensa*-* \
| ymp-* \
- | z8k-*)
+ | z8k-* | z80-*)
+ ;;
+ # Recognize the basic CPU types without company name, with glob match.
+ xtensa*)
+ basic_machine=$basic_machine-unknown
;;
# Recognize the various machine names and aliases which stand
# for a CPU type and a company and sometimes even an OS.
@@ -410,6 +453,10 @@ case $basic_machine in
basic_machine=m68k-apollo
os=-bsd
;;
+ aros)
+ basic_machine=i386-pc
+ os=-aros
+ ;;
aux)
basic_machine=m68k-apple
os=-aux
@@ -418,10 +465,26 @@ case $basic_machine in
basic_machine=ns32k-sequent
os=-dynix
;;
+ blackfin)
+ basic_machine=bfin-unknown
+ os=-linux
+ ;;
+ blackfin-*)
+ basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'`
+ os=-linux
+ ;;
+ bluegene*)
+ basic_machine=powerpc-ibm
+ os=-cnk
+ ;;
c90)
basic_machine=c90-cray
os=-unicos
;;
+ cegcc)
+ basic_machine=arm-unknown
+ os=-cegcc
+ ;;
convex-c1)
basic_machine=c1-convex
os=-bsd
@@ -450,8 +513,8 @@ case $basic_machine in
basic_machine=craynv-cray
os=-unicosmp
;;
- cr16c)
- basic_machine=cr16c-unknown
+ cr16)
+ basic_machine=cr16-unknown
os=-elf
;;
crds | unos)
@@ -489,6 +552,14 @@ case $basic_machine in
basic_machine=m88k-motorola
os=-sysv3
;;
+ dicos)
+ basic_machine=i686-pc
+ os=-dicos
+ ;;
+ djgpp)
+ basic_machine=i586-pc
+ os=-msdosdjgpp
+ ;;
dpx20 | dpx20-*)
basic_machine=rs6000-bull
os=-bosx
@@ -639,6 +710,14 @@ case $basic_machine in
basic_machine=m68k-isi
os=-sysv
;;
+ m68knommu)
+ basic_machine=m68k-unknown
+ os=-linux
+ ;;
+ m68knommu-*)
+ basic_machine=m68k-`echo $basic_machine | sed 's/^[^-]*-//'`
+ os=-linux
+ ;;
m88k-omron*)
basic_machine=m88k-omron
;;
@@ -650,10 +729,17 @@ case $basic_machine in
basic_machine=ns32k-utek
os=-sysv
;;
+ microblaze)
+ basic_machine=microblaze-xilinx
+ ;;
mingw32)
basic_machine=i386-pc
os=-mingw32
;;
+ mingw32ce)
+ basic_machine=arm-unknown
+ os=-mingw32ce
+ ;;
miniframe)
basic_machine=m68000-convergent
;;
@@ -679,6 +765,9 @@ case $basic_machine in
basic_machine=i386-pc
os=-msdos
;;
+ ms1-*)
+ basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'`
+ ;;
mvs)
basic_machine=i370-ibm
os=-mvs
@@ -754,9 +843,8 @@ case $basic_machine in
basic_machine=hppa1.1-oki
os=-proelf
;;
- or32 | or32-*)
+ openrisc | openrisc-*)
basic_machine=or32-unknown
- os=-coff
;;
os400)
basic_machine=powerpc-ibm
@@ -778,6 +866,14 @@ case $basic_machine in
basic_machine=i860-intel
os=-osf
;;
+ parisc)
+ basic_machine=hppa-unknown
+ os=-linux
+ ;;
+ parisc-*)
+ basic_machine=hppa-`echo $basic_machine | sed 's/^[^-]*-//'`
+ os=-linux
+ ;;
pbd)
basic_machine=sparc-tti
;;
@@ -787,6 +883,12 @@ case $basic_machine in
pc532 | pc532-*)
basic_machine=ns32k-pc532
;;
+ pc98)
+ basic_machine=i386-pc
+ ;;
+ pc98-*)
+ basic_machine=i386-`echo $basic_machine | sed 's/^[^-]*-//'`
+ ;;
pentium | p5 | k5 | k6 | nexgen | viac3)
basic_machine=i586-pc
;;
@@ -843,6 +945,10 @@ case $basic_machine in
basic_machine=i586-unknown
os=-pw32
;;
+ rdos)
+ basic_machine=i386-pc
+ os=-rdos
+ ;;
rom68k)
basic_machine=m68k-rom68k
os=-coff
@@ -869,6 +975,10 @@ case $basic_machine in
sb1el)
basic_machine=mipsisa64sb1el-unknown
;;
+ sde)
+ basic_machine=mipsisa32-sde
+ os=-elf
+ ;;
sei)
basic_machine=mips-sei
os=-seiux
@@ -880,6 +990,9 @@ case $basic_machine in
basic_machine=sh-hitachi
os=-hms
;;
+ sh5el)
+ basic_machine=sh5le-unknown
+ ;;
sh64)
basic_machine=sh64-unknown
;;
@@ -969,6 +1082,10 @@ case $basic_machine in
basic_machine=tic6x-unknown
os=-coff
;;
+ tile*)
+ basic_machine=tile-unknown
+ os=-linux-gnu
+ ;;
tx39)
basic_machine=mipstx39-unknown
;;
@@ -1029,6 +1146,10 @@ case $basic_machine in
basic_machine=hppa1.1-winbond
os=-proelf
;;
+ xbox)
+ basic_machine=i686-pc
+ os=-mingw32
+ ;;
xps | xps100)
basic_machine=xps100-honeywell
;;
@@ -1040,6 +1161,10 @@ case $basic_machine in
basic_machine=z8k-unknown
os=-sim
;;
+ z80-*-coff)
+ basic_machine=z80-unknown
+ os=-sim
+ ;;
none)
basic_machine=none-none
os=-none
@@ -1078,13 +1203,10 @@ case $basic_machine in
we32k)
basic_machine=we32k-att
;;
- sh3 | sh4 | sh[34]eb | sh[1234]le | sh[23]ele)
+ sh[1234] | sh[24]a | sh[24]aeb | sh[34]eb | sh[1234]le | sh[23]ele)
basic_machine=sh-unknown
;;
- sh64)
- basic_machine=sh64-unknown
- ;;
- sparc | sparcv8 | sparcv9 | sparcv9b)
+ sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v)
basic_machine=sparc-sun
;;
cydra)
@@ -1151,26 +1273,30 @@ case $os in
# Each alternative MUST END IN A *, to match a version number.
# -sysv* is not here because it comes later, after sysvr4.
-gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \
- | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\
+ | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\
| -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \
+ | -kopensolaris* \
| -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \
- | -aos* \
+ | -aos* | -aros* \
| -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \
| -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \
- | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* | -openbsd* \
+ | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \
+ | -openbsd* | -solidbsd* \
| -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \
| -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \
| -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \
| -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
- | -chorusos* | -chorusrdb* \
+ | -chorusos* | -chorusrdb* | -cegcc* \
| -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
- | -mingw32* | -linux-gnu* | -linux-uclibc* | -uxpv* | -beos* | -mpeix* | -udk* \
+ | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \
+ | -uxpv* | -beos* | -mpeix* | -udk* \
| -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \
| -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
| -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \
| -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \
| -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \
- | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly*)
+ | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \
+ | -skyos* | -haiku* | -rdos* | -toppers* | -drops*)
# Remember, each alternative MUST END IN *, to match a version number.
;;
-qnx*)
@@ -1188,7 +1314,7 @@ case $os in
os=`echo $os | sed -e 's|nto|nto-qnx|'`
;;
-sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \
- | -windows* | -osx | -abug | -netware* | -os9* | -beos* \
+ | -windows* | -osx | -abug | -netware* | -os9* | -beos* | -haiku* \
| -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*)
;;
-mac*)
@@ -1297,6 +1423,12 @@ case $os in
-kaos*)
os=-kaos
;;
+ -zvmoe)
+ os=-zvmoe
+ ;;
+ -dicos*)
+ os=-dicos
+ ;;
-none)
;;
*)
@@ -1319,6 +1451,12 @@ else
# system, and we'll never get to this point.
case $basic_machine in
+ score-*)
+ os=-elf
+ ;;
+ spu-*)
+ os=-elf
+ ;;
*-acorn)
os=-riscix1.2
;;
@@ -1328,9 +1466,9 @@ case $basic_machine in
arm*-semi)
os=-aout
;;
- c4x-* | tic4x-*)
- os=-coff
- ;;
+ c4x-* | tic4x-*)
+ os=-coff
+ ;;
# This must come before the *-dec entry.
pdp10-*)
os=-tops20
@@ -1356,6 +1494,9 @@ case $basic_machine in
m68*-cisco)
os=-aout
;;
+ mep-*)
+ os=-elf
+ ;;
mips*-cisco)
os=-elf
;;
@@ -1374,6 +1515,9 @@ case $basic_machine in
*-be)
os=-beos
;;
+ *-haiku)
+ os=-haiku
+ ;;
*-ibm)
os=-aix
;;
@@ -1482,7 +1626,7 @@ case $basic_machine in
-sunos*)
vendor=sun
;;
- -aix*)
+ -cnk*|-aix*)
vendor=ibm
;;
-beos*)
@@ -1545,7 +1689,7 @@ case $basic_machine in
esac
echo $basic_machine$os
-exit 0
+exit
# Local variables:
# eval: (add-hook 'write-file-hooks 'time-stamp)
diff --git a/libclamav/c++/llvm/autoconf/configure.ac b/libclamav/c++/llvm/autoconf/configure.ac
index 49ab037..dee9037 100644
--- a/libclamav/c++/llvm/autoconf/configure.ac
+++ b/libclamav/c++/llvm/autoconf/configure.ac
@@ -381,6 +381,16 @@ else
AC_SUBST(DEBUG_RUNTIME,[[DEBUG_RUNTIME=1]])
fi
+dnl --enable-debug-symbols : should even optimized compiler libraries
+dnl have debug symbols?
+AC_ARG_ENABLE(debug-symbols,
+ AS_HELP_STRING(--enable-debug-symbols,[Build compiler with debug symbols (default is NO if optimization is on and YES if it's off)]),,enableval=no)
+if test ${enableval} = "no" ; then
+ AC_SUBST(DEBUG_SYMBOLS,[[]])
+else
+ AC_SUBST(DEBUG_SYMBOLS,[[DEBUG_SYMBOLS=1]])
+fi
+
dnl --enable-jit: check whether they want to enable the jit
AC_ARG_ENABLE(jit,
AS_HELP_STRING(--enable-jit,
@@ -396,7 +406,7 @@ else
PowerPC) AC_SUBST(TARGET_HAS_JIT,1) ;;
x86_64) AC_SUBST(TARGET_HAS_JIT,1) ;;
Alpha) AC_SUBST(TARGET_HAS_JIT,1) ;;
- ARM) AC_SUBST(TARGET_HAS_JIT,0) ;;
+ ARM) AC_SUBST(TARGET_HAS_JIT,1) ;;
Mips) AC_SUBST(TARGET_HAS_JIT,0) ;;
PIC16) AC_SUBST(TARGET_HAS_JIT,0) ;;
XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -449,28 +459,15 @@ AC_DEFINE_UNQUOTED([ENABLE_PIC],$ENABLE_PIC,
dnl Allow specific targets to be specified for building (or not)
TARGETS_TO_BUILD=""
AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
- [Build specific host targets: all,host-only,{target-name} (default=all)]),,
+ [Build specific host targets: all or target1,target2,... Valid targets are:
+ host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu, pic16,
+ xcore, msp430, systemz, blackfin, cbe, msil, and cpp (default=all)]),,
enableval=all)
+if test "$enableval" = host-only ; then
+ enableval=host
+fi
case "$enableval" in
all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend MSIL CppBackend" ;;
- host-only)
- case "$llvm_cv_target_arch" in
- x86) TARGETS_TO_BUILD="X86" ;;
- x86_64) TARGETS_TO_BUILD="X86" ;;
- Sparc) TARGETS_TO_BUILD="Sparc" ;;
- PowerPC) TARGETS_TO_BUILD="PowerPC" ;;
- Alpha) TARGETS_TO_BUILD="Alpha" ;;
- ARM) TARGETS_TO_BUILD="ARM" ;;
- Mips) TARGETS_TO_BUILD="Mips" ;;
- CellSPU|SPU) TARGETS_TO_BUILD="CellSPU" ;;
- PIC16) TARGETS_TO_BUILD="PIC16" ;;
- XCore) TARGETS_TO_BUILD="XCore" ;;
- MSP430) TARGETS_TO_BUILD="MSP430" ;;
- SystemZ) TARGETS_TO_BUILD="SystemZ" ;;
- Blackfin) TARGETS_TO_BUILD="Blackfin" ;;
- *) AC_MSG_ERROR([Can not set target to build]) ;;
- esac
- ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -489,6 +486,22 @@ case "$enableval" in
cbe) TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
msil) TARGETS_TO_BUILD="MSIL $TARGETS_TO_BUILD" ;;
cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
+ host) case "$llvm_cv_target_arch" in
+ x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
+ x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
+ Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
+ PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
+ Alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
+ ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
+ Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
+ CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
+ PIC16) TARGETS_TO_BUILD="PIC16 $TARGETS_TO_BUILD" ;;
+ XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
+ MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
+ SystemZ) TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
+ Blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
+ *) AC_MSG_ERROR([Can not set target to build]) ;;
+ esac ;;
*) AC_MSG_ERROR([Unrecognized target $a_target]) ;;
esac
done
@@ -1077,7 +1090,7 @@ AC_CHECK_FUNCS([powf fmodf strtof round ])
AC_CHECK_FUNCS([getpagesize getrusage getrlimit setrlimit gettimeofday ])
AC_CHECK_FUNCS([isatty mkdtemp mkstemp ])
AC_CHECK_FUNCS([mktemp realpath sbrk setrlimit strdup ])
-AC_CHECK_FUNCS([strerror strerror_r strerror_s ])
+AC_CHECK_FUNCS([strerror strerror_r strerror_s setenv ])
AC_CHECK_FUNCS([strtoll strtoq sysconf malloc_zone_statistics ])
AC_CHECK_FUNCS([setjmp longjmp sigsetjmp siglongjmp])
AC_C_PRINTF_A
@@ -1137,6 +1150,16 @@ dnl=== SECTION 9: Additional checks, variables, etc.
dnl===
dnl===-----------------------------------------------------------------------===
+dnl Handle 32-bit linux systems running a 64-bit kernel.
+dnl This has to come after section 4 because it invokes the compiler.
+if test "$llvm_cv_os_type" = "Linux" -a "$llvm_cv_target_arch" = "x86_64" ; then
+ AC_IS_LINUX_MIXED
+ if test "$llvm_cv_linux_mixed" = "yes"; then
+ llvm_cv_target_arch="x86"
+ ARCH="x86"
+ fi
+fi
+
dnl Check, whether __dso_handle is present
AC_CHECK_FUNCS([__dso_handle])
diff --git a/libclamav/c++/llvm/autoconf/m4/linux_mixed_64_32.m4 b/libclamav/c++/llvm/autoconf/m4/linux_mixed_64_32.m4
new file mode 100644
index 0000000..123491f
--- /dev/null
+++ b/libclamav/c++/llvm/autoconf/m4/linux_mixed_64_32.m4
@@ -0,0 +1,17 @@
+#
+# Some Linux machines run a 64-bit kernel with a 32-bit userspace. 'uname -m'
+# shows these as x86_64. Ask the system 'gcc' what it thinks.
+#
+AC_DEFUN([AC_IS_LINUX_MIXED],
+[AC_CACHE_CHECK(for 32-bit userspace on 64-bit system,llvm_cv_linux_mixed,
+[ AC_LANG_PUSH([C])
+ AC_COMPILE_IFELSE([AC_LANG_PROGRAM(
+ [[#ifndef __x86_64__
+ error: Not x86-64 even if uname says so!
+ #endif
+ ]])],
+ [llvm_cv_linux_mixed=no],
+ [llvm_cv_linux_mixed=yes])
+ AC_LANG_POP([C])
+])
+])
diff --git a/libclamav/c++/llvm/cmake/config-ix.cmake b/libclamav/c++/llvm/cmake/config-ix.cmake
index 85f9470..17feffe 100755
--- a/libclamav/c++/llvm/cmake/config-ix.cmake
+++ b/libclamav/c++/llvm/cmake/config-ix.cmake
@@ -1,6 +1,28 @@
+include(CheckIncludeFile)
+include(CheckLibraryExists)
+include(CheckSymbolExists)
+include(CheckFunctionExists)
+include(CheckCXXSourceCompiles)
+
+# Helper macros and functions
+macro(add_cxx_include result files)
+ set(${result} "")
+ foreach (file_name ${files})
+ set(${result} "${${result}}#include<${file_name}>\n")
+ endforeach()
+endmacro(add_cxx_include files result)
+
+function(check_type_exists type files variable)
+ add_cxx_include(includes "${files}")
+ CHECK_CXX_SOURCE_COMPILES("
+ ${includes} ${type} typeVar;
+ int main() {
+ return 0;
+ }
+ " ${variable})
+endfunction()
# include checks
-include(CheckIncludeFile)
check_include_file(argz.h HAVE_ARGZ_H)
check_include_file(assert.h HAVE_ASSERT_H)
check_include_file(dirent.h HAVE_DIRENT_H)
@@ -41,15 +63,12 @@ check_include_file(utime.h HAVE_UTIME_H)
check_include_file(windows.h HAVE_WINDOWS_H)
# library checks
-include(CheckLibraryExists)
check_library_exists(pthread pthread_create "" HAVE_LIBPTHREAD)
check_library_exists(pthread pthread_getspecific "" HAVE_PTHREAD_GETSPECIFIC)
check_library_exists(pthread pthread_rwlock_init "" HAVE_PTHREAD_RWLOCK_INIT)
check_library_exists(dl dlopen "" HAVE_LIBDL)
# function checks
-include(CheckSymbolExists)
-include(CheckFunctionExists)
check_symbol_exists(getpagesize unistd.h HAVE_GETPAGESIZE)
check_symbol_exists(getrusage sys/resource.h HAVE_GETRUSAGE)
check_symbol_exists(setrlimit sys/resource.h HAVE_SETRLIMIT)
@@ -71,12 +90,34 @@ check_symbol_exists(strtoll stdlib.h HAVE_STRTOLL)
check_symbol_exists(strerror string.h HAVE_STRERROR)
check_symbol_exists(strerror_r string.h HAVE_STRERROR_R)
check_symbol_exists(strerror_s string.h HAVE_STRERROR_S)
+check_symbol_exists(setenv stdlib.h HAVE_SETENV)
check_symbol_exists(__GLIBC__ stdio.h LLVM_USING_GLIBC)
if( LLVM_USING_GLIBC )
add_llvm_definitions( -D_GNU_SOURCE )
endif()
+# Type checks
+check_type_exists(std::bidirectional_iterator<int,int> "iterator;iostream" HAVE_BI_ITERATOR)
+check_type_exists(std::iterator<int,int,int> iterator HAVE_STD_ITERATOR)
+check_type_exists(std::forward_iterator<int,int> iterator HAVE_FWD_ITERATOR)
+
+set(headers "")
+if (HAVE_SYS_TYPES_H)
+ set(headers ${headers} "sys/types.h")
+endif()
+
+if (HAVE_INTTYPES_H)
+ set(headers ${headers} "inttypes.h")
+endif()
+
+if (HAVE_STDINT_H)
+ set(headers ${headers} "stdint.h")
+endif()
+
+check_type_exists(uint64_t "${headers}" HAVE_UINT64_T)
+check_type_exists(u_int64_t "${headers}" HAVE_U_INT64_T)
+
# Define LLVM_MULTITHREADED if gcc atomic builtins exists.
include(CheckAtomic)
@@ -92,13 +133,18 @@ get_target_triple(LLVM_HOSTTRIPLE)
message(STATUS "LLVM_HOSTTRIPLE: ${LLVM_HOSTTRIPLE}")
# Determine the native architecture.
-# FIXME: this will have to change for cross-compiling.
-string(REGEX MATCH "^[^-]*" LLVM_NATIVE_ARCH ${LLVM_HOSTTRIPLE})
+string(TOLOWER "${LLVM_TARGET_ARCH}" LLVM_NATIVE_ARCH)
+if( LLVM_NATIVE_ARCH STREQUAL "host" )
+ string(REGEX MATCH "^[^-]*" LLVM_NATIVE_ARCH ${LLVM_HOSTTRIPLE})
+endif ()
+
if (LLVM_NATIVE_ARCH MATCHES "i[2-6]86")
set(LLVM_NATIVE_ARCH X86)
-elseif (LLVM_NATIVE_ARCH STREQUAL amd64)
+elseif (LLVM_NATIVE_ARCH STREQUAL "x86")
+ set(LLVM_NATIVE_ARCH X86)
+elseif (LLVM_NATIVE_ARCH STREQUAL "amd64")
set(LLVM_NATIVE_ARCH X86)
-elseif (LLVM_NATIVE_ARCH STREQUAL x86_64)
+elseif (LLVM_NATIVE_ARCH STREQUAL "x86_64")
set(LLVM_NATIVE_ARCH X86)
elseif (LLVM_NATIVE_ARCH MATCHES "sparc")
set(LLVM_NATIVE_ARCH Sparc)
diff --git a/libclamav/c++/llvm/cmake/modules/LLVMLibDeps.cmake b/libclamav/c++/llvm/cmake/modules/LLVMLibDeps.cmake
index ba353fd..fba999e 100644
--- a/libclamav/c++/llvm/cmake/modules/LLVMLibDeps.cmake
+++ b/libclamav/c++/llvm/cmake/modules/LLVMLibDeps.cmake
@@ -1,7 +1,8 @@
-set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMARMCodeGen LLVMARMInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMInfo LLVMMC)
+set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMARMCodeGen LLVMARMInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMARMInfo LLVMSupport)
-set(MSVC_LIB_DEPS_LLVMAlphaAsmPrinter LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMAlphaAsmPrinter LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget)
@@ -10,12 +11,12 @@ set(MSVC_LIB_DEPS_LLVMAsmParser LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMAsmPrinter LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMBitReader LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMBitWriter LLVMCore LLVMSupport LLVMSystem)
-set(MSVC_LIB_DEPS_LLVMBlackfinAsmPrinter LLVMAsmPrinter LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMBlackfinAsmPrinter LLVMAsmPrinter LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMCBackend LLVMAnalysis LLVMCBackendInfo LLVMCodeGen LLVMCore LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa)
set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMSupport)
-set(MSVC_LIB_DEPS_LLVMCellSPUAsmPrinter LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMCellSPUAsmPrinter LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils)
@@ -25,33 +26,33 @@ set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMDebugger LLVMAnalysis LLVMBitReader LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMHello LLVMCore LLVMSupport LLVMSystem)
-set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMCore LLVMScalarOpts LLVMSupport LLVMSystem LLVMTransformUtils)
+set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMAnalysis LLVMCore LLVMScalarOpts LLVMSupport LLVMSystem LLVMTransformUtils)
set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMJIT LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMMC LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMLinker LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMMSIL LLVMAnalysis LLVMCodeGen LLVMCore LLVMMSILInfo LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa)
set(MSVC_LIB_DEPS_LLVMMSILInfo LLVMSupport)
-set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMSP430Info LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430Info LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMCodeGen LLVMCore LLVMMC LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMSupport)
-set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMipsCodeGen LLVMMipsInfo LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsCodeGen LLVMMipsInfo LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMPIC16 LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMPIC16Info LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
-set(MSVC_LIB_DEPS_LLVMPIC16AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMPIC16 LLVMPIC16Info LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMPIC16AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPIC16 LLVMPIC16Info LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMPIC16Info LLVMSupport)
-set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMPowerPCInfo LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCInfo LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils)
set(MSVC_LIB_DEPS_LLVMSelectionDAG LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMSystem LLVMTarget)
-set(MSVC_LIB_DEPS_LLVMSparcAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSparcInfo LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMSparcAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSparcInfo LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMSparcCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSparcInfo LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMSystem )
-set(MSVC_LIB_DEPS_LLVMSystemZAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMSystem LLVMSystemZInfo LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMSystemZAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMSystemZInfo LLVMTarget)
set(MSVC_LIB_DEPS_LLVMSystemZCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystemZInfo LLVMTarget)
set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport LLVMSystem)
@@ -61,7 +62,7 @@ set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC L
set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86Info LLVMSupport)
set(MSVC_LIB_DEPS_LLVMXCore LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget LLVMXCoreInfo)
-set(MSVC_LIB_DEPS_LLVMXCoreAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMSystem LLVMTarget LLVMXCoreInfo)
+set(MSVC_LIB_DEPS_LLVMXCoreAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget LLVMXCoreInfo)
set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMipa LLVMAnalysis LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMipo LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa)
diff --git a/libclamav/c++/llvm/configure b/libclamav/c++/llvm/configure
index 2c15d16..a90d4c1 100755
--- a/libclamav/c++/llvm/configure
+++ b/libclamav/c++/llvm/configure
@@ -837,6 +837,7 @@ DISABLE_ASSERTIONS
ENABLE_EXPENSIVE_CHECKS
EXPENSIVE_CHECKS
DEBUG_RUNTIME
+DEBUG_SYMBOLS
JIT
TARGET_HAS_JIT
ENABLE_DOXYGEN
@@ -1554,13 +1555,18 @@ Optional Features:
is NO)
--enable-debug-runtime Build runtime libs with debug symbols (default is
NO)
+ --enable-debug-symbols Build compiler with debug symbols (default is NO if
+ optimization is on and YES if it's off)
--enable-jit Enable Just In Time Compiling (default is YES)
--enable-doxygen Build doxygen documentation (default is NO)
--enable-threads Use threads if available (default is YES)
--enable-pic Build LLVM with Position Independent Code (default
is YES)
- --enable-targets Build specific host targets:
- all,host-only,{target-name} (default=all)
+ --enable-targets Build specific host targets: all or
+ target1,target2,... Valid targets are: host, x86,
+ x86_64, sparc, powerpc, alpha, arm, mips, spu,
+ pic16, xcore, msp430, systemz, blackfin, cbe, msil,
+ and cpp (default=all)
--enable-cbe-printf-a Enable C Backend output with hex floating point via
%a (default is YES)
--enable-bindings Build specific language bindings:
@@ -4879,6 +4885,21 @@ else
fi
+# Check whether --enable-debug-symbols was given.
+if test "${enable_debug_symbols+set}" = set; then
+ enableval=$enable_debug_symbols;
+else
+ enableval=no
+fi
+
+if test ${enableval} = "no" ; then
+ DEBUG_SYMBOLS=
+
+else
+ DEBUG_SYMBOLS=DEBUG_SYMBOLS=1
+
+fi
+
# Check whether --enable-jit was given.
if test "${enable_jit+set}" = set; then
enableval=$enable_jit;
@@ -4902,7 +4923,7 @@ else
;;
Alpha) TARGET_HAS_JIT=1
;;
- ARM) TARGET_HAS_JIT=0
+ ARM) TARGET_HAS_JIT=1
;;
Mips) TARGET_HAS_JIT=0
;;
@@ -4996,28 +5017,11 @@ else
enableval=all
fi
+if test "$enableval" = host-only ; then
+ enableval=host
+fi
case "$enableval" in
all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend MSIL CppBackend" ;;
- host-only)
- case "$llvm_cv_target_arch" in
- x86) TARGETS_TO_BUILD="X86" ;;
- x86_64) TARGETS_TO_BUILD="X86" ;;
- Sparc) TARGETS_TO_BUILD="Sparc" ;;
- PowerPC) TARGETS_TO_BUILD="PowerPC" ;;
- Alpha) TARGETS_TO_BUILD="Alpha" ;;
- ARM) TARGETS_TO_BUILD="ARM" ;;
- Mips) TARGETS_TO_BUILD="Mips" ;;
- CellSPU|SPU) TARGETS_TO_BUILD="CellSPU" ;;
- PIC16) TARGETS_TO_BUILD="PIC16" ;;
- XCore) TARGETS_TO_BUILD="XCore" ;;
- MSP430) TARGETS_TO_BUILD="MSP430" ;;
- SystemZ) TARGETS_TO_BUILD="SystemZ" ;;
- Blackfin) TARGETS_TO_BUILD="Blackfin" ;;
- *) { { echo "$as_me:$LINENO: error: Can not set target to build" >&5
-echo "$as_me: error: Can not set target to build" >&2;}
- { (exit 1); exit 1; }; } ;;
- esac
- ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5036,6 +5040,24 @@ echo "$as_me: error: Can not set target to build" >&2;}
cbe) TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
msil) TARGETS_TO_BUILD="MSIL $TARGETS_TO_BUILD" ;;
cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
+ host) case "$llvm_cv_target_arch" in
+ x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
+ x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
+ Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
+ PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
+ Alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
+ ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
+ Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
+ CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
+ PIC16) TARGETS_TO_BUILD="PIC16 $TARGETS_TO_BUILD" ;;
+ XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
+ MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
+ SystemZ) TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
+ Blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
+ *) { { echo "$as_me:$LINENO: error: Can not set target to build" >&5
+echo "$as_me: error: Can not set target to build" >&2;}
+ { (exit 1); exit 1; }; } ;;
+ esac ;;
*) { { echo "$as_me:$LINENO: error: Unrecognized target $a_target" >&5
echo "$as_me: error: Unrecognized target $a_target" >&2;}
{ (exit 1); exit 1; }; } ;;
@@ -10972,7 +10994,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
-#line 10975 "configure"
+#line 10997 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -13116,7 +13138,7 @@ ia64-*-hpux*)
;;
*-*-irix6*)
# Find out which ABI we are using.
- echo '#line 13119 "configure"' > conftest.$ac_ext
+ echo '#line 13141 "configure"' > conftest.$ac_ext
if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
(eval $ac_compile) 2>&5
ac_status=$?
@@ -14834,11 +14856,11 @@ else
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:14837: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:14859: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
- echo "$as_me:14841: \$? = $ac_status" >&5
+ echo "$as_me:14863: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
@@ -15102,11 +15124,11 @@ else
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:15105: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:15127: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
- echo "$as_me:15109: \$? = $ac_status" >&5
+ echo "$as_me:15131: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
@@ -15206,11 +15228,11 @@ else
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:15209: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:15231: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
- echo "$as_me:15213: \$? = $ac_status" >&5
+ echo "$as_me:15235: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
@@ -17658,7 +17680,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
-#line 17661 "configure"
+#line 17683 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -17758,7 +17780,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
-#line 17761 "configure"
+#line 17783 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -20126,11 +20148,11 @@ else
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:20129: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:20151: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
- echo "$as_me:20133: \$? = $ac_status" >&5
+ echo "$as_me:20155: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
@@ -20230,11 +20252,11 @@ else
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:20233: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:20255: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
- echo "$as_me:20237: \$? = $ac_status" >&5
+ echo "$as_me:20259: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
@@ -21800,11 +21822,11 @@ else
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:21803: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:21825: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
- echo "$as_me:21807: \$? = $ac_status" >&5
+ echo "$as_me:21829: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
@@ -21904,11 +21926,11 @@ else
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:21907: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:21929: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
- echo "$as_me:21911: \$? = $ac_status" >&5
+ echo "$as_me:21933: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
@@ -24139,11 +24161,11 @@ else
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:24142: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:24164: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
- echo "$as_me:24146: \$? = $ac_status" >&5
+ echo "$as_me:24168: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
@@ -24407,11 +24429,11 @@ else
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:24410: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:24432: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
- echo "$as_me:24414: \$? = $ac_status" >&5
+ echo "$as_me:24436: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
@@ -24511,11 +24533,11 @@ else
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
- (eval echo "\"\$as_me:24514: $lt_compile\"" >&5)
+ (eval echo "\"\$as_me:24536: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
- echo "$as_me:24518: \$? = $ac_status" >&5
+ echo "$as_me:24540: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
@@ -32287,7 +32309,8 @@ done
-for ac_func in strerror strerror_r strerror_s
+
+for ac_func in strerror strerror_r strerror_s setenv
do
as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
{ echo "$as_me:$LINENO: checking for $ac_func" >&5
@@ -34879,6 +34902,96 @@ rm -f core conftest.err conftest.$ac_objext \
+if test "$llvm_cv_os_type" = "Linux" -a "$llvm_cv_target_arch" = "x86_64" ; then
+ { echo "$as_me:$LINENO: checking for 32-bit userspace on 64-bit system" >&5
+echo $ECHO_N "checking for 32-bit userspace on 64-bit system... $ECHO_C" >&6; }
+if test "${llvm_cv_linux_mixed+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#ifndef __x86_64__
+ error: Not x86-64 even if uname says so!
+ #endif
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_compile") 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err'
+ { (case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ llvm_cv_linux_mixed=no
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ llvm_cv_linux_mixed=yes
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+ ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+fi
+{ echo "$as_me:$LINENO: result: $llvm_cv_linux_mixed" >&5
+echo "${ECHO_T}$llvm_cv_linux_mixed" >&6; }
+
+ if test "$llvm_cv_linux_mixed" = "yes"; then
+ llvm_cv_target_arch="x86"
+ ARCH="x86"
+ fi
+fi
+
for ac_func in __dso_handle
do
@@ -36088,6 +36201,7 @@ DISABLE_ASSERTIONS!$DISABLE_ASSERTIONS$ac_delim
ENABLE_EXPENSIVE_CHECKS!$ENABLE_EXPENSIVE_CHECKS$ac_delim
EXPENSIVE_CHECKS!$EXPENSIVE_CHECKS$ac_delim
DEBUG_RUNTIME!$DEBUG_RUNTIME$ac_delim
+DEBUG_SYMBOLS!$DEBUG_SYMBOLS$ac_delim
JIT!$JIT$ac_delim
TARGET_HAS_JIT!$TARGET_HAS_JIT$ac_delim
ENABLE_DOXYGEN!$ENABLE_DOXYGEN$ac_delim
@@ -36103,7 +36217,6 @@ BINUTILS_INCDIR!$BINUTILS_INCDIR$ac_delim
ENABLE_LLVMC_DYNAMIC!$ENABLE_LLVMC_DYNAMIC$ac_delim
ENABLE_LLVMC_DYNAMIC_PLUGINS!$ENABLE_LLVMC_DYNAMIC_PLUGINS$ac_delim
CXX!$CXX$ac_delim
-CXXFLAGS!$CXXFLAGS$ac_delim
_ACEOF
if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 97; then
@@ -36145,6 +36258,7 @@ _ACEOF
ac_delim='%!_!# '
for ac_last_try in false false false false false :; do
cat >conf$$subs.sed <<_ACEOF
+CXXFLAGS!$CXXFLAGS$ac_delim
ac_ct_CXX!$ac_ct_CXX$ac_delim
NM!$NM$ac_delim
ifGNUmake!$ifGNUmake$ac_delim
@@ -36238,7 +36352,7 @@ LIBOBJS!$LIBOBJS$ac_delim
LTLIBOBJS!$LTLIBOBJS$ac_delim
_ACEOF
- if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 91; then
+ if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 92; then
break
elif $ac_last_try; then
{ { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5
diff --git a/libclamav/c++/llvm/docs/CMake.html b/libclamav/c++/llvm/docs/CMake.html
index 741e8da..25f4710 100644
--- a/libclamav/c++/llvm/docs/CMake.html
+++ b/libclamav/c++/llvm/docs/CMake.html
@@ -273,6 +273,13 @@
option is available only on some 64-bits unix systems. Defaults to
OFF.</dd>
+ <dt><b>LLVM_TARGET_ARCH</b>:STRING</dt>
+ <dd>LLVM target to use for native code generation. This is required
+ for JIT generation. It defaults to "host", meaning that it shall
+ pick the architecture of the machine where LLVM is being built. If
+ you are cross-compiling, set it to the target architecture
+ name.</dd>
+
<dt><b>LLVM_TABLEGEN</b>:STRING</dt>
<dd>Full path to a native TableGen executable (usually
named <i>tblgen</i>). This is intented for cross-compiling: if the
@@ -311,6 +318,9 @@
<a href="http://www.vtk.org/Wiki/CMake_Cross_Compiling#Information_how_to_set_up_various_cross_compiling_toolchains">this
section</a> for a quick solution.</p>
+<p>Also see the <a href="#llvmvars">LLVM-specific variables</a>
+ section for variables used when cross-compiling.</p>
+
</div>
<!-- *********************************************************************** -->
diff --git a/libclamav/c++/llvm/docs/CommandGuide/lit.pod b/libclamav/c++/llvm/docs/CommandGuide/lit.pod
new file mode 100644
index 0000000..a818302
--- /dev/null
+++ b/libclamav/c++/llvm/docs/CommandGuide/lit.pod
@@ -0,0 +1,222 @@
+=pod
+
+=head1 NAME
+
+lit - LLVM Integrated Tester
+
+=head1 SYNOPSIS
+
+B<lit> [I<options>] [I<tests>]
+
+=head1 DESCRIPTION
+
+B<lit> is a portable tool for executing LLVM and Clang style test suites,
+summarizing their results, and providing indication of failures. B<lit> is
+designed to be a lightweight testing tool with as simple a user interface as
+possible.
+
+B<lit> should be run with one or more I<tests> to run specified on the command
+line. Tests can be either individual test files or directories to search for
+tests (see L<"TEST DISCOVERY">).
+
+Each specified test will be executed (potentially in parallel) and once all
+tests have been run B<lit> will print summary information on the number of tests
+which passed or failed (see L<"TEST STATUS RESULTS">). The B<lit> program will
+execute with a non-zero exit code if any tests fail.
+
+By default B<lit> will use a succinct progress display and will only print
+summary information for test failures. See L<"OUTPUT OPTIONS"> for options
+controlling the B<lit> progress display and output.
+
+B<lit> also includes a number of options for controlling how tests are exected
+(specific features may depend on the particular test format). See L<"EXECUTION
+OPTIONS"> for more information.
+
+Finally, B<lit> also supports additional options for only running a subset of
+the options specified on the command line, see L<"SELECTION OPTIONS"> for
+more information.
+
+=head1 GENERAL OPTIONS
+
+=over
+
+=item B<-h>, B<--help>
+
+Show the B<lit> help message.
+
+=item B<-j> I<N>, B<--threads>=I<N>
+
+Run I<N> tests in parallel. By default, this is automatically chose to match the
+number of detected available CPUs.
+
+=back
+
+=head1 OUTPUT OPTIONS
+
+=over
+
+=item B<-q>, B<--quiet>
+
+Suppress any output except for test failures.
+
+=item B<-s>, B<--succinct>
+
+Show less output, for example don't show information on tests that pass.
+
+=item B<-v>, B<--verbose>
+
+Show more information on test failures, for example the entire test output
+instead of just the test result.
+
+=item B<--no-progress-bar>
+
+Do not use curses based progress bar.
+
+=back
+
+=head1 EXECUTION OPTIONS
+
+=over
+
+=item B<--path>=I<PATH>
+
+Specify an addition I<PATH> to use when searching for executables in tests.
+
+=item B<--vg>
+
+Run individual tests under valgrind (using the memcheck tool). The
+I<--error-exitcode> argument for valgrind is used so that valgrind failures will
+cause the program to exit with a non-zero status.
+
+=item B<--vg-arg>=I<ARG>
+
+When I<--vg> is used, specify an additional argument to pass to valgrind itself.
+
+=item B<--time-tests>
+
+Track the wall time individual tests take to execute and includes the results in
+the summary output. This is useful for determining which tests in a test suite
+take the most time to execute. Note that this option is most useful with I<-j
+1>.
+
+=back
+
+=head1 SELECTION OPTIONS
+
+=over
+
+=item B<--max-tests>=I<N>
+
+Run at most I<N> tests and then terminate.
+
+=item B<--max-time>=I<N>
+
+Spend at most I<N> seconds (approximately) running tests and then terminate.
+
+=item B<--shuffle>
+
+Run the tests in a random order.
+
+=back
+
+=head1 ADDITIONAL OPTIONS
+
+=over
+
+=item B<--debug>
+
+Run B<lit> in debug mode, for debugging configuration issues and B<lit> itself.
+
+=item B<--show-suites>
+
+List the discovered test suites as part of the standard output.
+
+=item B<--no-tcl-as-sh>
+
+Run Tcl scripts internally (instead of converting to shell scripts).
+
+=back
+
+=head1 EXIT STATUS
+
+B<lit> will exit with an exit code of 1 if there are any FAIL or XPASS
+results. Otherwise, it will exit with the status 0. Other exit codes used for
+non-test related failures (for example a user error or an internal program
+error).
+
+=head1 TEST DISCOVERY
+
+The inputs passed to B<lit> can be either individual tests, or entire
+directories or hierarchies of tests to run. When B<lit> starts up, the first
+thing it does is convert the inputs into a complete list of tests to run as part
+of I<test discovery>.
+
+In the B<lit> model, every test must exist inside some I<test suite>. B<lit>
+resolves the inputs specified on the command line to test suites by searching
+upwards from the input path until it finds a I<lit.cfg> or I<lit.site.cfg>
+file. These files serve as both a marker of test suites and as configuration
+files which B<lit> loads in order to understand how to find and run the tests
+inside the test suite.
+
+Once B<lit> has mapped the inputs into test suites it traverses the list of
+inputs adding tests for individual files and recursively searching for tests in
+directories.
+
+This behavior makes it easy to specify a subset of tests to run, while still
+allowing the test suite configuration to control exactly how tests are
+interpreted. In addition, B<lit> always identifies tests by the test suite they
+are in, and their relative path inside the test suite. For appropriately
+configured projects, this allows B<lit> to provide convenient and flexible
+support for out-of-tree builds.
+
+=head1 TEST STATUS RESULTS
+
+Each test ultimately produces one of the following six results:
+
+=over
+
+=item B<PASS>
+
+The test succeeded.
+
+=item B<XFAIL>
+
+The test failed, but that is expected. This is used for test formats which allow
+specifying that a test does not currently work, but wish to leave it in the test
+suite.
+
+=item B<XPASS>
+
+The test succeeded, but it was expected to fail. This is used for tests which
+were specified as expected to fail, but are now succeeding (generally because
+the feautre they test was broken and has been fixed).
+
+=item B<FAIL>
+
+The test failed.
+
+=item B<UNRESOLVED>
+
+The test result could not be determined. For example, this occurs when the test
+could not be run, the test itself is invalid, or the test was interrupted.
+
+=item B<UNSUPPORTED>
+
+The test is not supported in this environment. This is used by test formats
+which can report unsupported tests.
+
+=back
+
+Depending on the test format tests may produce additional information about
+their status (generally only for failures). See the L<Output|"LIT OUTPUT">
+section for more information.
+
+=head1 SEE ALSO
+
+L<valgrind(1)>
+
+=head1 AUTHOR
+
+Written by Daniel Dunbar and maintained by the LLVM Team (L<http://llvm.org>).
+
+=cut
diff --git a/libclamav/c++/llvm/docs/CommandGuide/llc.pod b/libclamav/c++/llvm/docs/CommandGuide/llc.pod
index 7a7bbca..8adfb68 100644
--- a/libclamav/c++/llvm/docs/CommandGuide/llc.pod
+++ b/libclamav/c++/llvm/docs/CommandGuide/llc.pod
@@ -10,18 +10,19 @@ B<llc> [I<options>] [I<filename>]
=head1 DESCRIPTION
-The B<llc> command compiles LLVM bitcode into assembly language for a
+The B<llc> command compiles LLVM source inputs into assembly language for a
specified architecture. The assembly language output can then be passed through
a native assembler and linker to generate a native executable.
The choice of architecture for the output assembly code is automatically
-determined from the input bitcode file, unless the B<-march> option is used to
-override the default.
+determined from the input file, unless the B<-march> option is used to override
+the default.
=head1 OPTIONS
-If I<filename> is - or omitted, B<llc> reads LLVM bitcode from standard input.
-Otherwise, it will read LLVM bitcode from I<filename>.
+If I<filename> is - or omitted, B<llc> reads from standard input. Otherwise, it
+will from I<filename>. Inputs can be in either the LLVM assembly language
+format (.ll) or the LLVM bitcode format (.bc).
If the B<-o> option is omitted, then B<llc> will send its output to standard
output if the input is from standard input. If the B<-o> option specifies -,
@@ -47,21 +48,15 @@ Generate code at different optimization levels. These correspond to the I<-O0>,
I<-O1>, I<-O2>, I<-O3>, and I<-O4> optimization levels used by B<llvm-gcc> and
B<clang>.
-=item B<-f>
-
-Enable binary output on terminals. Normally, B<llvm-extract> will refuse to
-write raw bitcode output if the output stream is a terminal. With this option,
-B<llvm-extract> will write raw bitcode regardless of the output device.
-
=item B<-mtriple>=I<target triple>
-Override the target triple specified in the input bitcode file with the
-specified string.
+Override the target triple specified in the input file with the specified
+string.
=item B<-march>=I<arch>
Specify the architecture for which to generate assembly, overriding the target
-encoded in the bitcode file. See the output of B<llc --help> for a list of
+encoded in the input file. See the output of B<llc --help> for a list of
valid architectures. By default this is inferred from the target triple or
autodetected to the current architecture.
diff --git a/libclamav/c++/llvm/docs/CommandGuide/llvm-extract.pod b/libclamav/c++/llvm/docs/CommandGuide/llvm-extract.pod
index c3bc019..b62e8ae 100644
--- a/libclamav/c++/llvm/docs/CommandGuide/llvm-extract.pod
+++ b/libclamav/c++/llvm/docs/CommandGuide/llvm-extract.pod
@@ -45,6 +45,10 @@ Print a summary of command line options.
Specify the output filename. If filename is "-" (the default), then
B<llvm-extract> sends its output to standard output.
+=item B<-S>
+
+Write output in LLVM intermediate language (instead of bitcode).
+
=back
=head1 EXIT STATUS
diff --git a/libclamav/c++/llvm/docs/CommandGuide/llvm-link.pod b/libclamav/c++/llvm/docs/CommandGuide/llvm-link.pod
index 8a2a8c5..e1a1267 100644
--- a/libclamav/c++/llvm/docs/CommandGuide/llvm-link.pod
+++ b/libclamav/c++/llvm/docs/CommandGuide/llvm-link.pod
@@ -42,6 +42,10 @@ B<llvm-link> will write raw bitcode regardless of the output device.
Specify the output file name. If F<filename> is C<->, then B<llvm-link> will
write its output to standard output.
+=item B<-S>
+
+Write output in LLVM intermediate language (instead of bitcode).
+
=item B<-d>
If specified, B<llvm-link> prints a human-readable version of the output
diff --git a/libclamav/c++/llvm/docs/CommandGuide/opt.pod b/libclamav/c++/llvm/docs/CommandGuide/opt.pod
index 3e23cd1..d1d1db5 100644
--- a/libclamav/c++/llvm/docs/CommandGuide/opt.pod
+++ b/libclamav/c++/llvm/docs/CommandGuide/opt.pod
@@ -11,24 +11,25 @@ B<opt> [I<options>] [I<filename>]
=head1 DESCRIPTION
The B<opt> command is the modular LLVM optimizer and analyzer. It takes LLVM
-bitcode as input, runs the specified optimizations or analyses on it, and then
-outputs the optimized LLVM bitcode or the analysis results. The function of
+source files as input, runs the specified optimizations or analyses on it, and then
+outputs the optimized file or the analysis results. The function of
B<opt> depends on whether the B<-analyze> option is given.
-When B<-analyze> is specified, B<opt> performs various analyses of LLVM
-bitcode. It will usually print the results on standard output, but in a few
-cases, it will print output to standard error or generate a file with the
-analysis output, which is usually done when the output is meant for another
-program.
+When B<-analyze> is specified, B<opt> performs various analyses of the input
+source. It will usually print the results on standard output, but in a few
+cases, it will print output to standard error or generate a file with the
+analysis output, which is usually done when the output is meant for another
+program.
While B<-analyze> is I<not> given, B<opt> attempts to produce an optimized
-bitcode file. The optimizations available via B<opt> depend upon what
+output file. The optimizations available via B<opt> depend upon what
libraries were linked into it as well as any additional libraries that have
been loaded with the B<-load> option. Use the B<-help> option to determine
what optimizations you can use.
If I<filename> is omitted from the command line or is I<->, B<opt> reads its
-input from standard input. The input must be an LLVM bitcode file.
+input from standard input. Inputs can be in either the LLVM assembly language
+format (.ll) or the LLVM bitcode format (.bc).
If an output filename is not specified with the B<-o> option, B<opt>
writes its output to the standard output.
@@ -51,6 +52,10 @@ Print a summary of command line options.
Specify the output filename.
+=item B<-S>
+
+Write output in LLVM intermediate language (instead of bitcode).
+
=item B<-{passname}>
B<opt> provides the ability to run any of LLVM's optimization or analysis passes
diff --git a/libclamav/c++/llvm/docs/CompilerDriver.html b/libclamav/c++/llvm/docs/CompilerDriver.html
index 5830a30..9bc08ac 100644
--- a/libclamav/c++/llvm/docs/CompilerDriver.html
+++ b/libclamav/c++/llvm/docs/CompilerDriver.html
@@ -438,15 +438,21 @@ user.
Example: <tt class="docutils literal"><span class="pre">(not_empty</span> <span class="pre">"o")</span></tt>.</li>
<li><tt class="docutils literal"><span class="pre">empty</span></tt> - The opposite of <tt class="docutils literal"><span class="pre">not_empty</span></tt>. Equivalent to <tt class="docutils literal"><span class="pre">(not</span> <span class="pre">(not_empty</span>
<span class="pre">X))</span></tt>. Provided for convenience.</li>
+<li><tt class="docutils literal"><span class="pre">single_input_file</span></tt> - Returns true if there was only one input file
+provided on the command-line. Used without arguments:
+<tt class="docutils literal"><span class="pre">(single_input_file)</span></tt>.</li>
+<li><tt class="docutils literal"><span class="pre">multiple_input_files</span></tt> - Equivalent to <tt class="docutils literal"><span class="pre">(not</span> <span class="pre">(single_input_file))</span></tt> (the
+case of zero input files is considered an error).</li>
<li><tt class="docutils literal"><span class="pre">default</span></tt> - Always evaluates to true. Should always be the last
test in the <tt class="docutils literal"><span class="pre">case</span></tt> expression.</li>
-<li><tt class="docutils literal"><span class="pre">and</span></tt> - A standard logical combinator that returns true iff all
-of its arguments return true. Used like this: <tt class="docutils literal"><span class="pre">(and</span> <span class="pre">(test1),</span>
-<span class="pre">(test2),</span> <span class="pre">...</span> <span class="pre">(testN))</span></tt>. Nesting of <tt class="docutils literal"><span class="pre">and</span></tt> and <tt class="docutils literal"><span class="pre">or</span></tt> is allowed,
-but not encouraged.</li>
-<li><tt class="docutils literal"><span class="pre">or</span></tt> - Another logical combinator that returns true only if any
-one of its arguments returns true. Example: <tt class="docutils literal"><span class="pre">(or</span> <span class="pre">(test1),</span>
-<span class="pre">(test2),</span> <span class="pre">...</span> <span class="pre">(testN))</span></tt>.</li>
+<li><tt class="docutils literal"><span class="pre">and</span></tt> - A standard binary logical combinator that returns true iff all of
+its arguments return true. Used like this: <tt class="docutils literal"><span class="pre">(and</span> <span class="pre">(test1),</span> <span class="pre">(test2),</span>
+<span class="pre">...</span> <span class="pre">(testN))</span></tt>. Nesting of <tt class="docutils literal"><span class="pre">and</span></tt> and <tt class="docutils literal"><span class="pre">or</span></tt> is allowed, but not
+encouraged.</li>
+<li><tt class="docutils literal"><span class="pre">or</span></tt> - A binary logical combinator that returns true iff any of its
+arguments returns true. Example: <tt class="docutils literal"><span class="pre">(or</span> <span class="pre">(test1),</span> <span class="pre">(test2),</span> <span class="pre">...</span> <span class="pre">(testN))</span></tt>.</li>
+<li><tt class="docutils literal"><span class="pre">not</span></tt> - Standard unary logical combinator that negates its
+argument. Example: <tt class="docutils literal"><span class="pre">(not</span> <span class="pre">(or</span> <span class="pre">(test1),</span> <span class="pre">(test2),</span> <span class="pre">...</span> <span class="pre">(testN)))</span></tt>.</li>
</ul>
</li>
</ul>
diff --git a/libclamav/c++/llvm/docs/DebuggingJITedCode.html b/libclamav/c++/llvm/docs/DebuggingJITedCode.html
new file mode 100644
index 0000000..92570f4
--- /dev/null
+++ b/libclamav/c++/llvm/docs/DebuggingJITedCode.html
@@ -0,0 +1,171 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
+ "http://www.w3.org/TR/html4/strict.dtd">
+<html>
+<head>
+ <title>Debugging JITed Code With GDB</title>
+ <link rel="stylesheet" href="llvm.css" type="text/css">
+</head>
+<body>
+
+<div class="doc_title">Debugging JITed Code With GDB</div>
+<ol>
+ <li><a href="#introduction">Introduction</a></li>
+ <li><a href="#quickstart">Quickstart</a></li>
+ <li><a href="#example">Example with clang and lli</a></li>
+</ol>
+<div class="doc_author">Written by Reid Kleckner</div>
+
+<!--=========================================================================-->
+<div class="doc_section"><a name="introduction">Introduction</a></div>
+<!--=========================================================================-->
+<div class="doc_text">
+
+<p>Without special runtime support, debugging dynamically generated code with
+GDB (as well as most debuggers) can be quite painful. Debuggers generally read
+debug information from the object file of the code, but for JITed code, there is
+no such file to look for.
+</p>
+
+<p>Depending on the architecture, this can impact the debugging experience in
+different ways. For example, on most 32-bit x86 architectures, you can simply
+compile with -fno-omit-framepointer for GCC and -fdisable-fp-elim for LLVM.
+When GDB creates a backtrace, it can properly unwind the stack, but the stack
+frames owned by JITed code have ??'s instead of the appropriate symbol name.
+However, on Linux x86_64 in particular, GDB relies on the DWARF CFA debug
+information to unwind the stack, so even if you compile your program to leave
+the frame pointer untouched, GDB will usually be unable to unwind the stack past
+any JITed code stack frames.
+</p>
+
+<p>In order to communicate the necessary debug info to GDB, an interface for
+registering JITed code with debuggers has been designed and implemented for
+GDB and LLVM. At a high level, whenever LLVM generates new machine code, it
+also generates an object file in memory containing the debug information. LLVM
+then adds the object file to the global list of object files and calls a special
+function (__jit_debug_register_code) marked noinline that GDB knows about. When
+GDB attaches to a process, it puts a breakpoint in this function and loads all
+of the object files in the global list. When LLVM calls the registration
+function, GDB catches the breakpoint signal, loads the new object file from
+LLVM's memory, and resumes the execution. In this way, GDB can get the
+necessary debug information.
+</p>
+
+<p>At the time of this writing, LLVM only supports architectures that use ELF
+object files and it only generates symbols and DWARF CFA information. However,
+it would be easy to add more information to the object file, so we don't need to
+coordinate with GDB to get better debug information.
+</p>
+</div>
+
+<!--=========================================================================-->
+<div class="doc_section"><a name="quickstart">Quickstart</a></div>
+<!--=========================================================================-->
+<div class="doc_text">
+
+<p>In order to debug code JITed by LLVM, you need to install a recent version
+of GDB. The interface was added on 2009-08-19, so you need a snapshot of GDB
+more recent than that. Either download a snapshot of GDB or checkout CVS as
+instructed <a href="http://www.gnu.org/software/gdb/current/">here</a>. Here
+are the commands for doing a checkout and building the code:
+</p>
+
+<pre class="doc_code">
+$ cvs -z 3 -d :pserver:anoncvs at sourceware.org:/cvs/src co gdb
+$ mv src gdb # You probably don't want this checkout called "src".
+$ cd gdb
+$ ./configure --prefix="$GDB_INSTALL"
+$ make
+$ make install
+</pre>
+
+<p>You can then use -jit-emit-debug in the LLVM command line arguments to enable
+the interface.
+</p>
+</div>
+
+<!--=========================================================================-->
+<div class="doc_section"><a name="example">Example with clang and lli</a></div>
+<!--=========================================================================-->
+<div class="doc_text">
+
+<p>For example, consider debugging running lli on the following C code in
+foo.c:
+</p>
+
+<pre class="doc_code">
+#include <stdio.h>
+
+void foo() {
+ printf("%d\n", *(int*)NULL); // Crash here
+}
+
+void bar() {
+ foo();
+}
+
+void baz() {
+ bar();
+}
+
+int main(int argc, char **argv) {
+ baz();
+}
+</pre>
+
+<p>Here are the commands to run that application under GDB and print the stack
+trace at the crash:
+</p>
+
+<pre class="doc_code">
+# Compile foo.c to bitcode. You can use either clang or llvm-gcc with this
+# command line. Both require -fexceptions, or the calls are all marked
+# 'nounwind' which disables DWARF CFA info.
+$ clang foo.c -fexceptions -emit-llvm -c -o foo.bc
+
+# Run foo.bc under lli with -jit-emit-debug. If you built lli in debug mode,
+# -jit-emit-debug defaults to true.
+$ $GDB_INSTALL/gdb --args lli -jit-emit-debug foo.bc
+...
+
+# Run the code.
+(gdb) run
+Starting program: /tmp/gdb/lli -jit-emit-debug foo.bc
+[Thread debugging using libthread_db enabled]
+
+Program received signal SIGSEGV, Segmentation fault.
+0x00007ffff7f55164 in foo ()
+
+# Print the backtrace, this time with symbols instead of ??.
+(gdb) bt
+#0 0x00007ffff7f55164 in foo ()
+#1 0x00007ffff7f550f9 in bar ()
+#2 0x00007ffff7f55099 in baz ()
+#3 0x00007ffff7f5502a in main ()
+#4 0x00000000007c0225 in llvm::JIT::runFunction(llvm::Function*,
+ std::vector<llvm::GenericValue,
+ std::allocator<llvm::GenericValue> > const&) ()
+#5 0x00000000007d6d98 in
+ llvm::ExecutionEngine::runFunctionAsMain(llvm::Function*,
+ std::vector<std::string,
+ std::allocator<std::string> > const&, char const* const*) ()
+#6 0x00000000004dab76 in main ()
+</pre>
+</div>
+
+<p>As you can see, GDB can correctly unwind the stack and has the appropriate
+function names.
+</p>
+
+<!-- *********************************************************************** -->
+<hr>
+<address>
+ <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
+ src="http://jigsaw.w3.org/css-validator/images/vcss-blue" alt="Valid CSS"></a>
+ <a href="http://validator.w3.org/check/referer"><img
+ src="http://www.w3.org/Icons/valid-html401-blue" alt="Valid HTML 4.01"></a>
+ <a href="mailto:reid.kleckner at gmail.com">Reid Kleckner</a><br>
+ <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
+ Last modified: $Date: 2009-01-01 23:10:51 -0800 (Thu, 01 Jan 2009) $
+</address>
+</body>
+</html>
diff --git a/libclamav/c++/llvm/docs/DeveloperPolicy.html b/libclamav/c++/llvm/docs/DeveloperPolicy.html
index dd20184..0c87a69 100644
--- a/libclamav/c++/llvm/docs/DeveloperPolicy.html
+++ b/libclamav/c++/llvm/docs/DeveloperPolicy.html
@@ -185,14 +185,18 @@ svn diff
else. The current code owners are:</p>
<ol>
+ <li><b>Evan Cheng</b>: Code generator and all targets.</li>
+
+ <li><b>Doug Gregor</b>: Clang Basic, Lex, Parse, and Sema Libraries.</li>
+
<li><b>Anton Korobeynikov</b>: Exception handling, debug information, and
Windows codegen.</li>
- <li><b>Duncan Sands</b>: llvm-gcc 4.2.</li>
-
- <li><b>Evan Cheng</b>: Code generator and all targets.</li>
+ <li><b>Ted Kremenek</b>: Clang Static Analyzer.</li>
- <li><b>Chris Lattner</b>: Everything else.</li>
+ <li><b>Chris Lattner</b>: Everything not covered by someone else.</li>
+
+ <li><b>Duncan Sands</b>: llvm-gcc 4.2.</li>
</ol>
<p>Note that code ownership is completely different than reviewers: anyone can
diff --git a/libclamav/c++/llvm/docs/ExceptionHandling.html b/libclamav/c++/llvm/docs/ExceptionHandling.html
index 72fb349..c57776c 100644
--- a/libclamav/c++/llvm/docs/ExceptionHandling.html
+++ b/libclamav/c++/llvm/docs/ExceptionHandling.html
@@ -4,7 +4,7 @@
<head>
<title>Exception Handling in LLVM</title>
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
- <meta name="description"
+ <meta name="description"
content="Exception Handling in LLVM.">
<link rel="stylesheet" href="llvm.css" type="text/css">
</head>
@@ -56,7 +56,7 @@
<!-- *********************************************************************** -->
-<div class="doc_section"><a name="introduction">Introduction</a></div>
+<div class="doc_section"><a name="introduction">Introduction</a></div>
<!-- *********************************************************************** -->
<div class="doc_text">
@@ -295,10 +295,17 @@
<li><tt>__cxa_begin_catch</tt> takes a exception structure reference as an
argument and returns the value of the exception object.</li>
- <li><tt>__cxa_end_catch</tt> takes a exception structure reference as an
- argument. This function clears the exception from the exception space.
- Note: a rethrow from within the catch may replace this call with
- a <tt>__cxa_rethrow</tt>.</li>
+ <li><tt>__cxa_end_catch</tt> takes no arguments. This function:<br><br>
+ <ol>
+ <li>Locates the most recently caught exception and decrements its handler
+ count,</li>
+ <li>Removes the exception from the "caught" stack if the handler count
+ goes to zero, and</li>
+ <li>Destroys the exception if the handler count goes to zero, and the
+ exception was not re-thrown by throw.</li>
+ </ol>
+ <p>Note: a rethrow from within the catch may replace this call with
+ a <tt>__cxa_rethrow</tt>.</p></li>
</ul>
</div>
diff --git a/libclamav/c++/llvm/docs/GettingStarted.html b/libclamav/c++/llvm/docs/GettingStarted.html
index e740a89..890d8f8 100644
--- a/libclamav/c++/llvm/docs/GettingStarted.html
+++ b/libclamav/c++/llvm/docs/GettingStarted.html
@@ -420,19 +420,19 @@ href="GCCFEBuildInstrs.html">try to compile it</a> on your platform.</p>
<tr>
<td><a href="http://www.gnu.org/software/autoconf">GNU Autoconf</a></td>
- <td>2.59</td>
+ <td>2.60</td>
<td>Configuration script builder<sup><a href="#sf4">4</a></sup></td>
</tr>
<tr>
<td><a href="http://www.gnu.org/software/automake">GNU Automake</a></td>
- <td>1.9.2</td>
+ <td>1.9.6</td>
<td>aclocal macro generator<sup><a href="#sf4">4</a></sup></td>
</tr>
<tr>
<td><a href="http://savannah.gnu.org/projects/libtool">libtool</a></td>
- <td>1.5.10</td>
+ <td>1.5.22</td>
<td>Shared library manager<sup><a href="#sf4">4</a></sup></td>
</tr>
@@ -558,9 +558,10 @@ as the previous one. It appears to work with ENABLE_OPTIMIZED=0 (the default).</
<p><b>Cygwin GCC 4.3.2 20080827 (beta) 2</b>:
Users <a href="http://llvm.org/PR4145">reported</a> various problems related
with link errors when using this GCC version.</p>
+<p><b>Debian GCC 4.3.2 on X86</b>: Crashes building some files in LLVM 2.6.</p>
<p><b>GCC 4.3.3 (Debian 4.3.3-10) on ARM</b>: Miscompiles parts of LLVM 2.6
when optimizations are turned on. The symptom is an infinite loop in
-FoldingSetImpl::RemoveNode while running the code generator.
+FoldingSetImpl::RemoveNode while running the code generator.</p>
<p><b>GNU ld 2.16.X</b>. Some 2.16.X versions of the ld linker will produce very
long warning messages complaining that some ".gnu.linkonce.t.*" symbol was
defined in a discarded section. You can safely ignore these messages as they are
diff --git a/libclamav/c++/llvm/docs/HistoricalNotes/2001-07-08-InstructionSelection.txt b/libclamav/c++/llvm/docs/HistoricalNotes/2001-07-08-InstructionSelection.txt
deleted file mode 100644
index 8cc75b8..0000000
--- a/libclamav/c++/llvm/docs/HistoricalNotes/2001-07-08-InstructionSelection.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-Date: Sun, 8 Jul 2001 09:37:22 -0500
-From: Vikram S. Adve <vadve at cs.uiuc.edu>
-To: Ruchira Sasanka <sasanka at students.uiuc.edu>
-Cc: Chris Lattner <lattner at cs.uiuc.edu>
-Subject: machine instruction operands
-
-Ruchira,
-
-When generating machine instructions, I have to make several choices about
-operands. For cases were a register is required, there are 3 cases:
-
-1. The register is for a Value* that is already in the VM code.
-
-2. The register is for a value that is not in the VM code, usually because 2
-machine instructions get generated for a single VM instruction (and the
-register holds the result of the first m/c instruction and is used by the
-second m/c instruction).
-
-3. The register is a pre-determined machine register.
-
-E.g, for this VM instruction:
- ptr = alloca type, numElements
-I have to generate 2 machine instructions:
- reg = mul constant, numElements
- ptr = add %sp, reg
-
-Each machine instruction is of class MachineInstr.
-It has a vector of operands. All register operands have type MO_REGISTER.
-The 3 types of register operands are marked using this enum:
-
- enum VirtualRegisterType {
- MO_VMVirtualReg, // virtual register for *value
- MO_MInstrVirtualReg, // virtual register for result of *minstr
- MO_MachineReg // pre-assigned machine register `regNum'
- } vregType;
-
-Here's how this affects register allocation:
-
-1. MO_VMVirtualReg is the standard case: you just do the register
-allocation.
-
-2. MO_MInstrVirtualReg is the case where there is a hidden register being
-used. You should decide how you want to handle it, e.g., do you want do
-create a Value object during the preprocessing phase to make the value
-explicit (like for address register for the RETURN instruction).
-
-3. For case MO_MachineReg, you don't need to do anything, at least for
-SPARC. The only machine regs I am using so far are %g0 and %sp.
-
---Vikram
-
diff --git a/libclamav/c++/llvm/docs/HistoricalNotes/2001-07-08-InstructionSelection2.txt b/libclamav/c++/llvm/docs/HistoricalNotes/2001-07-08-InstructionSelection2.txt
deleted file mode 100644
index 1ae006d..0000000
--- a/libclamav/c++/llvm/docs/HistoricalNotes/2001-07-08-InstructionSelection2.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Date: Sun, 8 Jul 2001 10:02:20 -0500
-From: Vikram S. Adve <vadve at cs.uiuc.edu>
-To: vadve at cs.uiuc.edu, Ruchira Sasanka <sasanka at students.uiuc.edu>
-Cc: Chris Lattner <lattner at cs.uiuc.edu>
-Subject: RE: machine instruction operands
-
-I got interrupted and forgot to explain the example. In that case:
-
- reg will be the 3rd operand of MUL and it will be of type
-MO_MInstrVirtualReg. The field MachineInstr* minstr will point to the
-instruction that computes reg.
-
- numElements will be an immediate constant, not a register.
-
- %sp will be operand 1 of ADD and it will be of type MO_MachineReg. The
-field regNum identifies the register.
-
- numElements will be operand 2 of ADD and it will be of type
-MO_VMVirtualReg. The field Value* value identifies the value.
-
- ptr will be operand 3 of ADD will also be %sp, i.e., of
- type MO_MachineReg. regNum identifies the register.
-
---Vikram
-
diff --git a/libclamav/c++/llvm/docs/HistoricalNotes/2007-OriginalClangReadme.txt b/libclamav/c++/llvm/docs/HistoricalNotes/2007-OriginalClangReadme.txt
new file mode 100644
index 0000000..611dc9d
--- /dev/null
+++ b/libclamav/c++/llvm/docs/HistoricalNotes/2007-OriginalClangReadme.txt
@@ -0,0 +1,178 @@
+//===----------------------------------------------------------------------===//
+// C Language Family Front-end
+//===----------------------------------------------------------------------===//
+ Chris Lattner
+
+I. Introduction:
+
+ clang: noun
+ 1. A loud, resonant, metallic sound.
+ 2. The strident call of a crane or goose.
+ 3. C-language family front-end toolkit.
+
+ The world needs better compiler tools, tools which are built as libraries. This
+ design point allows reuse of the tools in new and novel ways. However, building
+ the tools as libraries isn't enough: they must have clean APIs, be as
+ decoupled from each other as possible, and be easy to modify/extend. This
+ requires clean layering, decent design, and avoiding tying the libraries to a
+ specific use. Oh yeah, did I mention that we want the resultant libraries to
+ be as fast as possible? :)
+
+ This front-end is built as a component of the LLVM toolkit that can be used
+ with the LLVM backend or independently of it. In this spirit, the API has been
+ carefully designed as the following components:
+
+ libsupport - Basic support library, reused from LLVM.
+
+ libsystem - System abstraction library, reused from LLVM.
+
+ libbasic - Diagnostics, SourceLocations, SourceBuffer abstraction,
+ file system caching for input source files. This depends on
+ libsupport and libsystem.
+
+ libast - Provides classes to represent the C AST, the C type system,
+ builtin functions, and various helpers for analyzing and
+ manipulating the AST (visitors, pretty printers, etc). This
+ library depends on libbasic.
+
+
+ liblex - C/C++/ObjC lexing and preprocessing, identifier hash table,
+ pragma handling, tokens, and macros. This depends on libbasic.
+
+ libparse - C (for now) parsing and local semantic analysis. This library
+ invokes coarse-grained 'Actions' provided by the client to do
+ stuff (e.g. libsema builds ASTs). This depends on liblex.
+
+ libsema - Provides a set of parser actions to build a standardized AST
+ for programs. AST's are 'streamed' out a top-level declaration
+ at a time, allowing clients to use decl-at-a-time processing,
+ build up entire translation units, or even build 'whole
+ program' ASTs depending on how they use the APIs. This depends
+ on libast and libparse.
+
+ librewrite - Fast, scalable rewriting of source code. This operates on
+ the raw syntactic text of source code, allowing a client
+ to insert and delete text in very large source files using
+ the same source location information embedded in ASTs. This
+ is intended to be a low-level API that is useful for
+ higher-level clients and libraries such as code refactoring.
+
+ libanalysis - Source-level dataflow analysis useful for performing analyses
+ such as computing live variables. It also includes a
+ path-sensitive "graph-reachability" engine for writing
+ analyses that reason about different possible paths of
+ execution through source code. This is currently being
+ employed to write a set of checks for finding bugs in software.
+
+ libcodegen - Lower the AST to LLVM IR for optimization & codegen. Depends
+ on libast.
+
+ clang - An example driver, client of the libraries at various levels.
+ This depends on all these libraries, and on LLVM VMCore.
+
+ This front-end has been intentionally built as a DAG of libraries, making it
+ easy to reuse individual parts or replace pieces if desired. For example, to
+ build a preprocessor, you take the Basic and Lexer libraries. If you want an
+ indexer, you take those plus the Parser library and provide some actions for
+ indexing. If you want a refactoring, static analysis, or source-to-source
+ compiler tool, it makes sense to take those plus the AST building and semantic
+ analyzer library. Finally, if you want to use this with the LLVM backend,
+ you'd take these components plus the AST to LLVM lowering code.
+
+ In the future I hope this toolkit will grow to include new and interesting
+ components, including a C++ front-end, ObjC support, and a whole lot of other
+ things.
+
+ Finally, it should be pointed out that the goal here is to build something that
+ is high-quality and industrial-strength: all the obnoxious features of the C
+ family must be correctly supported (trigraphs, preprocessor arcana, K&R-style
+ prototypes, GCC/MS extensions, etc). It cannot be used if it is not 'real'.
+
+
+II. Usage of clang driver:
+
+ * Basic Command-Line Options:
+ - Help: clang --help
+ - Standard GCC options accepted: -E, -I*, -i*, -pedantic, -std=c90, etc.
+ - To make diagnostics more gcc-like: -fno-caret-diagnostics -fno-show-column
+ - Enable metric printing: -stats
+
+ * -fsyntax-only is currently the default mode.
+
+ * -E mode works the same way as GCC.
+
+ * -Eonly mode does all preprocessing, but does not print the output,
+ useful for timing the preprocessor.
+
+ * -fsyntax-only is currently partially implemented, lacking some
+ semantic analysis (some errors and warnings are not produced).
+
+ * -parse-noop parses code without building an AST. This is useful
+ for timing the cost of the parser without including AST building
+ time.
+
+ * -parse-ast builds ASTs, but doesn't print them. This is most
+ useful for timing AST building vs -parse-noop.
+
+ * -parse-ast-print pretty prints most expression and statements nodes.
+
+ * -parse-ast-check checks that diagnostic messages that are expected
+ are reported and that those which are reported are expected.
+
+ * -dump-cfg builds ASTs and then CFGs. CFGs are then pretty-printed.
+
+ * -view-cfg builds ASTs and then CFGs. CFGs are then visualized by
+ invoking Graphviz.
+
+ For more information on getting Graphviz to work with clang/LLVM,
+ see: http://llvm.org/docs/ProgrammersManual.html#ViewGraph
+
+
+III. Current advantages over GCC:
+
+ * Column numbers are fully tracked (no 256 col limit, no GCC-style pruning).
+ * All diagnostics have column numbers, includes 'caret diagnostics', and they
+ highlight regions of interesting code (e.g. the LHS and RHS of a binop).
+ * Full diagnostic customization by client (can format diagnostics however they
+ like, e.g. in an IDE or refactoring tool) through DiagnosticClient interface.
+ * Built as a framework, can be reused by multiple tools.
+ * All languages supported linked into same library (no cc1,cc1obj, ...).
+ * mmap's code in read-only, does not dirty the pages like GCC (mem footprint).
+ * LLVM License, can be linked into non-GPL projects.
+ * Full diagnostic control, per diagnostic. Diagnostics are identified by ID.
+ * Significantly faster than GCC at semantic analysis, parsing, preprocessing
+ and lexing.
+ * Defers exposing platform-specific stuff to as late as possible, tracks use of
+ platform-specific features (e.g. #ifdef PPC) to allow 'portable bytecodes'.
+ * The lexer doesn't rely on the "lexer hack": it has no notion of scope and
+ does not categorize identifiers as types or variables -- this is up to the
+ parser to decide.
+
+Potential Future Features:
+
+ * Fine grained diag control within the source (#pragma enable/disable warning).
+ * Better token tracking within macros? (Token came from this line, which is
+ a macro argument instantiated here, recursively instantiated here).
+ * Fast #import with a module system.
+ * Dependency tracking: change to header file doesn't recompile every function
+ that texually depends on it: recompile only those functions that need it.
+ This is aka 'incremental parsing'.
+
+
+IV. Missing Functionality / Improvements
+
+Lexer:
+ * Source character mapping. GCC supports ASCII and UTF-8.
+ See GCC options: -ftarget-charset and -ftarget-wide-charset.
+ * Universal character support. Experimental in GCC, enabled with
+ -fextended-identifiers.
+ * -fpreprocessed mode.
+
+Preprocessor:
+ * #assert/#unassert
+ * MSExtension: "L#param" stringizes to a wide string literal.
+ * Add support for -M*
+
+Traditional Preprocessor:
+ * Currently, we have none. :)
+
diff --git a/libclamav/c++/llvm/docs/LangRef.html b/libclamav/c++/llvm/docs/LangRef.html
index 44ef03b..3853692 100644
--- a/libclamav/c++/llvm/docs/LangRef.html
+++ b/libclamav/c++/llvm/docs/LangRef.html
@@ -56,6 +56,7 @@
<li><a href="#t_classifications">Type Classifications</a></li>
<li><a href="#t_primitive">Primitive Types</a>
<ol>
+ <li><a href="#t_integer">Integer Type</a></li>
<li><a href="#t_floating">Floating Point Types</a></li>
<li><a href="#t_void">Void Type</a></li>
<li><a href="#t_label">Label Type</a></li>
@@ -64,7 +65,6 @@
</li>
<li><a href="#t_derived">Derived Types</a>
<ol>
- <li><a href="#t_integer">Integer Type</a></li>
<li><a href="#t_array">Array Type</a></li>
<li><a href="#t_function">Function Type</a></li>
<li><a href="#t_pointer">Pointer Type</a></li>
@@ -1380,7 +1380,7 @@ Classifications</a> </div>
<p>The <a href="#t_firstclass">first class</a> types are perhaps the most
important. Values of these types are the only ones which can be produced by
- instructions, passed as arguments, or used as operands to instructions.</p>
+ instructions.</p>
</div>
@@ -1395,6 +1395,47 @@ Classifications</a> </div>
</div>
<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection"> <a name="t_integer">Integer Type</a> </div>
+
+<div class="doc_text">
+
+<h5>Overview:</h5>
+<p>The integer type is a very simple type that simply specifies an arbitrary
+ bit width for the integer type desired. Any bit width from 1 bit to
+ 2<sup>23</sup>-1 (about 8 million) can be specified.</p>
+
+<h5>Syntax:</h5>
+<pre>
+ iN
+</pre>
+
+<p>The number of bits the integer will occupy is specified by the <tt>N</tt>
+ value.</p>
+
+<h5>Examples:</h5>
+<table class="layout">
+ <tr class="layout">
+ <td class="left"><tt>i1</tt></td>
+ <td class="left">a single-bit integer.</td>
+ </tr>
+ <tr class="layout">
+ <td class="left"><tt>i32</tt></td>
+ <td class="left">a 32-bit integer.</td>
+ </tr>
+ <tr class="layout">
+ <td class="left"><tt>i1942652</tt></td>
+ <td class="left">a really big integer of over 1 million bits.</td>
+ </tr>
+</table>
+
+<p>Note that the code generator does not yet support large integer types to be
+ used as function return types. The specific limit on how large a return type
+ the code generator can currently handle is target-dependent; currently it's
+ often 64 bits for 32-bit targets and 128 bits for 64-bit targets.</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
<div class="doc_subsubsection"> <a name="t_floating">Floating Point Types</a> </div>
<div class="doc_text">
@@ -1448,9 +1489,9 @@ Classifications</a> </div>
<div class="doc_text">
<h5>Overview:</h5>
-<p>The metadata type represents embedded metadata. The only derived type that
- may contain metadata is <tt>metadata*</tt> or a function type that returns or
- takes metadata typed parameters, but not pointer to metadata types.</p>
+<p>The metadata type represents embedded metadata. No derived types may be
+ created from metadata except for <a href="#t_function">function</a>
+ arguments.
<h5>Syntax:</h5>
<pre>
@@ -1467,49 +1508,10 @@ Classifications</a> </div>
<p>The real power in LLVM comes from the derived types in the system. This is
what allows a programmer to represent arrays, functions, pointers, and other
- useful types. Note that these derived types may be recursive: For example,
- it is possible to have a two dimensional array.</p>
-
-</div>
-
-<!-- _______________________________________________________________________ -->
-<div class="doc_subsubsection"> <a name="t_integer">Integer Type</a> </div>
-
-<div class="doc_text">
-
-<h5>Overview:</h5>
-<p>The integer type is a very simple derived type that simply specifies an
- arbitrary bit width for the integer type desired. Any bit width from 1 bit to
- 2^23-1 (about 8 million) can be specified.</p>
-
-<h5>Syntax:</h5>
-<pre>
- iN
-</pre>
-
-<p>The number of bits the integer will occupy is specified by the <tt>N</tt>
- value.</p>
-
-<h5>Examples:</h5>
-<table class="layout">
- <tr class="layout">
- <td class="left"><tt>i1</tt></td>
- <td class="left">a single-bit integer.</td>
- </tr>
- <tr class="layout">
- <td class="left"><tt>i32</tt></td>
- <td class="left">a 32-bit integer.</td>
- </tr>
- <tr class="layout">
- <td class="left"><tt>i1942652</tt></td>
- <td class="left">a really big integer of over 1 million bits.</td>
- </tr>
-</table>
-
-<p>Note that the code generator does not yet support large integer types to be
- used as function return types. The specific limit on how large a return type
- the code generator can currently handle is target-dependent; currently it's
- often 64 bits for 32-bit targets and 128 bits for 64-bit targets.</p>
+ useful types. Each of these types contain one or more element types which
+ may be a primitive type, or another derived type. For example, it is
+ possible to have a two dimensional array, using an array as the element type
+ of another array.</p>
</div>
@@ -1590,7 +1592,7 @@ Classifications</a> </div>
<h5>Syntax:</h5>
<pre>
- <returntype list> (<parameter list>)
+ <returntype> (<parameter list>)
</pre>
<p>...where '<tt><parameter list></tt>' is a comma-separated list of type
@@ -1598,8 +1600,8 @@ Classifications</a> </div>
which indicates that the function takes a variable number of arguments.
Variable argument functions can access their arguments with
the <a href="#int_varargs">variable argument handling intrinsic</a>
- functions. '<tt><returntype list></tt>' is a comma-separated list of
- <a href="#t_firstclass">first class</a> type specifiers.</p>
+ functions. '<tt><returntype></tt>' is a any type except
+ <a href="#t_label">label</a>.</p>
<h5>Examples:</h5>
<table class="layout">
@@ -1624,8 +1626,8 @@ Classifications</a> </div>
</td>
</tr><tr class="layout">
<td class="left"><tt>{i32, i32} (i32)</tt></td>
- <td class="left">A function taking an <tt>i32</tt>, returning two
- <tt>i32</tt> values as an aggregate of type <tt>{ i32, i32 }</tt>
+ <td class="left">A function taking an <tt>i32</tt>, returning a
+ <a href="#t_struct">structure</a> containing two <tt>i32</tt> values
</td>
</tr>
</table>
@@ -1888,7 +1890,7 @@ Classifications</a> </div>
<dl>
<dt><b>Boolean constants</b></dt>
<dd>The two strings '<tt>true</tt>' and '<tt>false</tt>' are both valid
- constants of the <tt><a href="#t_primitive">i1</a></tt> type.</dd>
+ constants of the <tt><a href="#t_integer">i1</a></tt> type.</dd>
<dt><b>Integer constants</b></dt>
<dd>Standard integers (such as '4') are constants of
@@ -2016,12 +2018,148 @@ Classifications</a> </div>
<div class="doc_subsection"><a name="undefvalues">Undefined Values</a></div>
<div class="doc_text">
-<p>The string '<tt>undef</tt>' is recognized as a type-less constant that has no
- specific value. Undefined values may be of any type and be used anywhere a
- constant is permitted.</p>
+<p>The string '<tt>undef</tt>' can be used anywhere a constant is expected, and
+ indicates that the user of the value may recieve an unspecified bit-pattern.
+ Undefined values may be of any type (other than label or void) and be used
+ anywhere a constant is permitted.</p>
+
+<p>Undefined values are useful because they indicate to the compiler that the
+ program is well defined no matter what value is used. This gives the
+ compiler more freedom to optimize. Here are some examples of (potentially
+ surprising) transformations that are valid (in pseudo IR):</p>
+
+
+<div class="doc_code">
+<pre>
+ %A = add %X, undef
+ %B = sub %X, undef
+ %C = xor %X, undef
+Safe:
+ %A = undef
+ %B = undef
+ %C = undef
+</pre>
+</div>
+
+<p>This is safe because all of the output bits are affected by the undef bits.
+Any output bit can have a zero or one depending on the input bits.</p>
+
+<div class="doc_code">
+<pre>
+ %A = or %X, undef
+ %B = and %X, undef
+Safe:
+ %A = -1
+ %B = 0
+Unsafe:
+ %A = undef
+ %B = undef
+</pre>
+</div>
-<p>Undefined values indicate to the compiler that the program is well defined no
- matter what value is used, giving the compiler more freedom to optimize.</p>
+<p>These logical operations have bits that are not always affected by the input.
+For example, if "%X" has a zero bit, then the output of the 'and' operation will
+always be a zero, no matter what the corresponding bit from the undef is. As
+such, it is unsafe to optimize or assume that the result of the and is undef.
+However, it is safe to assume that all bits of the undef could be 0, and
+optimize the and to 0. Likewise, it is safe to assume that all the bits of
+the undef operand to the or could be set, allowing the or to be folded to
+-1.</p>
+
+<div class="doc_code">
+<pre>
+ %A = select undef, %X, %Y
+ %B = select undef, 42, %Y
+ %C = select %X, %Y, undef
+Safe:
+ %A = %X (or %Y)
+ %B = 42 (or %Y)
+ %C = %Y
+Unsafe:
+ %A = undef
+ %B = undef
+ %C = undef
+</pre>
+</div>
+
+<p>This set of examples show that undefined select (and conditional branch)
+conditions can go "either way" but they have to come from one of the two
+operands. In the %A example, if %X and %Y were both known to have a clear low
+bit, then %A would have to have a cleared low bit. However, in the %C example,
+the optimizer is allowed to assume that the undef operand could be the same as
+%Y, allowing the whole select to be eliminated.</p>
+
+
+<div class="doc_code">
+<pre>
+ %A = xor undef, undef
+
+ %B = undef
+ %C = xor %B, %B
+
+ %D = undef
+ %E = icmp lt %D, 4
+ %F = icmp gte %D, 4
+
+Safe:
+ %A = undef
+ %B = undef
+ %C = undef
+ %D = undef
+ %E = undef
+ %F = undef
+</pre>
+</div>
+
+<p>This example points out that two undef operands are not necessarily the same.
+This can be surprising to people (and also matches C semantics) where they
+assume that "X^X" is always zero, even if X is undef. This isn't true for a
+number of reasons, but the short answer is that an undef "variable" can
+arbitrarily change its value over its "live range". This is true because the
+"variable" doesn't actually <em>have a live range</em>. Instead, the value is
+logically read from arbitrary registers that happen to be around when needed,
+so the value is not neccesarily consistent over time. In fact, %A and %C need
+to have the same semantics or the core LLVM "replace all uses with" concept
+would not hold.</p>
+
+<div class="doc_code">
+<pre>
+ %A = fdiv undef, %X
+ %B = fdiv %X, undef
+Safe:
+ %A = undef
+b: unreachable
+</pre>
+</div>
+
+<p>These examples show the crucial difference between an <em>undefined
+value</em> and <em>undefined behavior</em>. An undefined value (like undef) is
+allowed to have an arbitrary bit-pattern. This means that the %A operation
+can be constant folded to undef because the undef could be an SNaN, and fdiv is
+not (currently) defined on SNaN's. However, in the second example, we can make
+a more aggressive assumption: because the undef is allowed to be an arbitrary
+value, we are allowed to assume that it could be zero. Since a divide by zero
+has <em>undefined behavior</em>, we are allowed to assume that the operation
+does not execute at all. This allows us to delete the divide and all code after
+it: since the undefined operation "can't happen", the optimizer can assume that
+it occurs in dead code.
+</p>
+
+<div class="doc_code">
+<pre>
+a: store undef -> %X
+b: store %X -> undef
+Safe:
+a: <deleted>
+b: unreachable
+</pre>
+</div>
+
+<p>These examples reiterate the fdiv example: a store "of" an undefined value
+can be assumed to not have any effect: we can assume that the value is
+overwritten with bits that happen to match what was already there. However, a
+store "to" an undefined location could clobber arbitrary memory, therefore, it
+has undefined behavior.</p>
</div>
@@ -2668,9 +2806,9 @@ Instruction</a> </div>
<h5>Syntax:</h5>
<pre>
<result> = add <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = nuw add <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = nsw add <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = nuw nsw add <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = add nuw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = add nsw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = add nuw nsw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@@ -2742,9 +2880,9 @@ Instruction</a> </div>
<h5>Syntax:</h5>
<pre>
<result> = sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = nuw sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = nsw sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = nuw nsw sub <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = sub nuw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = sub nsw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = sub nuw nsw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@@ -2829,9 +2967,9 @@ Instruction</a> </div>
<h5>Syntax:</h5>
<pre>
<result> = mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = nuw mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = nsw mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = nuw nsw mul <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = mul nuw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = mul nsw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = mul nuw nsw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@@ -2941,7 +3079,7 @@ Instruction</a> </div>
<h5>Syntax:</h5>
<pre>
<result> = sdiv <ty> <op1>, <op2> <i>; yields {ty}:result</i>
- <result> = exact sdiv <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = sdiv exact <ty> <op1>, <op2> <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@@ -4555,7 +4693,7 @@ entry:
<h5>Semantics:</h5>
<p>The '<tt>icmp</tt>' compares <tt>op1</tt> and <tt>op2</tt> according to the
condition code given as <tt>cond</tt>. The comparison performed always yields
- either an <a href="#t_primitive"><tt>i1</tt></a> or vector of <tt>i1</tt>
+ either an <a href="#t_integer"><tt>i1</tt></a> or vector of <tt>i1</tt>
result, as follows:</p>
<ol>
@@ -4632,7 +4770,7 @@ entry:
values based on comparison of its operands.</p>
<p>If the operands are floating point scalars, then the result type is a boolean
-(<a href="#t_primitive"><tt>i1</tt></a>).</p>
+(<a href="#t_integer"><tt>i1</tt></a>).</p>
<p>If the operands are floating point vectors, then the result type is a vector
of boolean with the same number of elements as the operands being
@@ -4674,7 +4812,7 @@ entry:
<p>The '<tt>fcmp</tt>' instruction compares <tt>op1</tt> and <tt>op2</tt>
according to the condition code given as <tt>cond</tt>. If the operands are
vectors, then the vectors are compared element by element. Each comparison
- performed always yields an <a href="#t_primitive">i1</a> result, as
+ performed always yields an <a href="#t_integer">i1</a> result, as
follows:</p>
<ol>
@@ -4909,6 +5047,12 @@ Loop: ; Infinite loop that counts from 0 on up...
%ZZ = call zeroext i32 @bar() <i>; Return value is %zero extended</i>
</pre>
+<p>llvm treats calls to some functions with names and arguments that match the
+standard C99 library as being the C99 library functions, and may perform
+optimizations or generate code for them under that assumption. This is
+something we'd like to change in the future to provide better support for
+freestanding environments and non-C-based langauges.</p>
+
</div>
<!-- _______________________________________________________________________ -->
diff --git a/libclamav/c++/llvm/docs/MakefileGuide.html b/libclamav/c++/llvm/docs/MakefileGuide.html
index f996144..ad44be8 100644
--- a/libclamav/c++/llvm/docs/MakefileGuide.html
+++ b/libclamav/c++/llvm/docs/MakefileGuide.html
@@ -626,6 +626,11 @@
<dd>If set to any value, causes a bitcode library (.bc) to be built.</dd>
<dt><a name="CONFIG_FILES"><tt>CONFIG_FILES</tt></a></dt>
<dd>Specifies a set of configuration files to be installed.</dd>
+ <dt><a name="DEBUG_SYMBOLS"><tt>DEBUG_SYMBOLS</tt></a></dt>
+ <dd>If set to any value, causes the build to include debugging
+ symbols even in optimized objects, libraries and executables. This
+ alters the flags specified to the compilers and linkers. Debugging
+ isn't fun in an optimized build, but it is possible.</dd>
<dt><a name="DIRS"><tt>DIRS</tt></a></dt>
<dd>Specifies a set of directories, usually children of the current
directory, that should also be made using the same goal. These directories
diff --git a/libclamav/c++/llvm/docs/ProgrammersManual.html b/libclamav/c++/llvm/docs/ProgrammersManual.html
index eaed402..4e97bc0 100644
--- a/libclamav/c++/llvm/docs/ProgrammersManual.html
+++ b/libclamav/c++/llvm/docs/ProgrammersManual.html
@@ -1654,7 +1654,7 @@ an example that prints the name of a <tt>BasicBlock</tt> and the number of
for (Function::iterator i = func->begin(), e = func->end(); i != e; ++i)
// <i>Print out the name of the basic block if it has one, and then the</i>
// <i>number of instructions that it contains</i>
- llvm::cerr << "Basic block (name=" << i->getName() << ") has "
+ errs() << "Basic block (name=" << i->getName() << ") has "
<< i->size() << " instructions.\n";
</pre>
</div>
@@ -1687,14 +1687,14 @@ a <tt>BasicBlock</tt>:</p>
for (BasicBlock::iterator i = blk->begin(), e = blk->end(); i != e; ++i)
// <i>The next statement works since operator<<(ostream&,...)</i>
// <i>is overloaded for Instruction&</i>
- llvm::cerr << *i << "\n";
+ errs() << *i << "\n";
</pre>
</div>
<p>However, this isn't really the best way to print out the contents of a
<tt>BasicBlock</tt>! Since the ostream operators are overloaded for virtually
anything you'll care about, you could have just invoked the print routine on the
-basic block itself: <tt>llvm::cerr << *blk << "\n";</tt>.</p>
+basic block itself: <tt>errs() << *blk << "\n";</tt>.</p>
</div>
@@ -1720,7 +1720,7 @@ small example that shows how to dump all instructions in a function to the stand
// <i>F is a pointer to a Function instance</i>
for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I)
- llvm::cerr << *I << "\n";
+ errs() << *I << "\n";
</pre>
</div>
@@ -1799,7 +1799,7 @@ without actually obtaining it via iteration over some structure:</p>
void printNextInstruction(Instruction* inst) {
BasicBlock::iterator it(inst);
++it; // <i>After this line, it refers to the instruction after *inst</i>
- if (it != inst->getParent()->end()) llvm::cerr << *it << "\n";
+ if (it != inst->getParent()->end()) errs() << *it << "\n";
}
</pre>
</div>
@@ -1917,8 +1917,8 @@ Function *F = ...;
for (Value::use_iterator i = F->use_begin(), e = F->use_end(); i != e; ++i)
if (Instruction *Inst = dyn_cast<Instruction>(*i)) {
- llvm::cerr << "F is used in instruction:\n";
- llvm::cerr << *Inst << "\n";
+ errs() << "F is used in instruction:\n";
+ errs() << *Inst << "\n";
}
</pre>
</div>
diff --git a/libclamav/c++/llvm/docs/ReleaseNotes-2.6.html b/libclamav/c++/llvm/docs/ReleaseNotes-2.6.html
index bd1d3cc..98e3565 100644
--- a/libclamav/c++/llvm/docs/ReleaseNotes-2.6.html
+++ b/libclamav/c++/llvm/docs/ReleaseNotes-2.6.html
@@ -119,7 +119,7 @@ list</a>.</p>
<ul>
<li>Something wonderful!</li>
-<li>AuroraUX / FreeBSD & OpenBSD Toolchain support.</li>
+<li>AuroraUX / FreeBSD & OpenBSD Toolchain support.</li>
<li>Many many bugs are fixed and many features have been added.</li>
</ul>
</div>
@@ -176,6 +176,29 @@ bug fixes, cleanup and new features. The major changes are:</p>
</div>
<!-- *********************************************************************** -->
+
+<!--=========================================================================-->
+<div class="doc_subsection">
+<a name="macruby">MacRuby</a>
+</div>
+
+<div class="doc_text">
+
+<p>
+<a href="http://macruby.org">MacRuby</a> is an implementation of Ruby on top of
+core Mac OS X technologies, such as the Objective-C common runtime and garbage
+collector, and the CoreFoundation framework. It is principally developed by
+Apple and aims at enabling the creation of full-fledged Mac OS X applications.
+</p>
+
+<p>
+MacRuby uses LLVM for optimization passes, JIT and AOT compilation of Ruby
+expressions. It also uses zero-cost DWARF exceptions to implement Ruby exception
+handling.</p>
+
+</div>
+
+
<!--=========================================================================-->
<div class="doc_subsection">
<a name="pure">Pure</a>
@@ -832,6 +855,20 @@ ignored</a>.</li>
</ul>
</div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="ocaml-bindingse">Known problems with the O'Caml bindings</a>
+</div>
+
+<div class="doc_text">
+
+<p>The Llvm.Linkage module is broken, and has incorrect values. Only
+Llvm.Linkage.External, Llvm.Linkage.Available_externally, and
+Llvm.Linkage.Link_once will be correct. If you need any of the other linkage
+modes, you'll have to write an external C library in order to expose the
+functionality. This has been fixed in the trunk.</p>
+</div>
+
<!-- *********************************************************************** -->
<div class="doc_section">
<a name="additionalinfo">Additional Information</a>
diff --git a/libclamav/c++/llvm/docs/TestingGuide.html b/libclamav/c++/llvm/docs/TestingGuide.html
index 51ffa45..43c414d 100644
--- a/libclamav/c++/llvm/docs/TestingGuide.html
+++ b/libclamav/c++/llvm/docs/TestingGuide.html
@@ -595,6 +595,109 @@ directive in a file.</p>
</div>
<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection"><a
+name="FileCheck-CHECK-NOT">The "CHECK-NOT:" directive</a></div>
+
+<div class="doc_text">
+
+<p>The CHECK-NOT: directive is used to verify that a string doesn't occur
+between two matches (or the first match and the beginning of the file). For
+example, to verify that a load is removed by a transformation, a test like this
+can be used:</p>
+
+<div class="doc_code">
+<pre>
+define i8 @coerce_offset0(i32 %V, i32* %P) {
+ store i32 %V, i32* %P
+
+ %P2 = bitcast i32* %P to i8*
+ %P3 = getelementptr i8* %P2, i32 2
+
+ %A = load i8* %P3
+ ret i8 %A
+; <b>CHECK:</b> @coerce_offset0
+; <b>CHECK-NOT:</b> load
+; <b>CHECK:</b> ret i8
+}
+</pre>
+</div>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection"><a
+name="FileCheck-Matching">FileCheck Pattern Matching Syntax</a></div>
+
+<div class="doc_text">
+
+<p>The CHECK: and CHECK-NOT: directives both take a pattern to match. For most
+uses of FileCheck, fixed string matching is perfectly sufficient. For some
+things, a more flexible form of matching is desired. To support this, FileCheck
+allows you to specify regular expressions in matching strings, surrounded by
+double braces: <b>{{yourregex}}</b>. Because we want to use fixed string
+matching for a majority of what we do, FileCheck has been designed to support
+mixing and matching fixed string matching with regular expressions. This allows
+you to write things like this:</p>
+
+<div class="doc_code">
+<pre>
+; CHECK: movhpd <b>{{[0-9]+}}</b>(%esp), <b>{{%xmm[0-7]}}</b>
+</pre>
+</div>
+
+<p>In this case, any offset from the ESP register will be allowed, and any xmm
+register will be allowed.</p>
+
+<p>Because regular expressions are enclosed with double braces, they are
+visually distinct, and you don't need to use escape characters within the double
+braces like you would in C. In the rare case that you want to match double
+braces explicitly from the input, you can use something ugly like
+<b>{{[{][{]}}</b> as your pattern.</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection"><a
+name="FileCheck-Variables">FileCheck Variables</a></div>
+
+<div class="doc_text">
+
+<p>It is often useful to match a pattern and then verify that it occurs again
+later in the file. For codegen tests, this can be useful to allow any register,
+but verify that that register is used consistently later. To do this, FileCheck
+allows named variables to be defined and substituted into patterns. Here is a
+simple example:</p>
+
+<div class="doc_code">
+<pre>
+; CHECK: test5:
+; CHECK: notw <b>[[REGISTER:%[a-z]+]]</b>
+; CHECK: andw {{.*}}<b>[[REGISTER]]</b>
+</pre>
+</div>
+
+<p>The first check line matches a regex (<tt>%[a-z]+</tt>) and captures it into
+the variables "REGISTER". The second line verifies that whatever is in REGISTER
+occurs later in the file after an "andw". FileCheck variable references are
+always contained in <tt>[[ ]]</tt> pairs, are named, and their names can be
+formed with the regex "<tt>[a-zA-Z][a-zA-Z0-9]*</tt>". If a colon follows the
+name, then it is a definition of the variable, if not, it is a use.</p>
+
+<p>FileCheck variables can be defined multiple times, and uses always get the
+latest value. Note that variables are all read at the start of a "CHECK" line
+and are all defined at the end. This means that if you have something like
+"<tt>CHECK: [[XYZ:.*]]x[[XYZ]]</tt>" that the check line will read the previous
+value of the XYZ variable and define a new one after the match is performed. If
+you need to do something like this you can probably take advantage of the fact
+that FileCheck is not actually line-oriented when it matches, this allows you to
+define two separate CHECK lines that match on the same line.
+</p>
+
+
+
+</div>
+
+<!-- _______________________________________________________________________ -->
<div class="doc_subsection"><a name="dgvars">Variables and
substitutions</a></div>
<!-- _______________________________________________________________________ -->
@@ -650,14 +753,6 @@ substitutions</a></div>
<dd>The target triplet that corresponds to the current host machine (the one
running the test cases). This should probably be called "host".<dd>
- <dt><b>prcontext</b> (%prcontext)</dt>
- <dd>Path to the prcontext tcl script that prints some context around a
- line that matches a pattern. This isn't strictly necessary as the test suite
- is run with its PATH altered to include the test/Scripts directory where
- the prcontext script is located. Note that this script is similar to
- <tt>grep -C</tt> but you should use the <tt>prcontext</tt> script because
- not all platforms support <tt>grep -C</tt>.</dd>
-
<dt><b>llvmgcc</b> (%llvmgcc)</dt>
<dd>The full path to the <tt>llvm-gcc</tt> executable as specified in the
configured LLVM environment</dd>
diff --git a/libclamav/c++/llvm/docs/WritingAnLLVMBackend.html b/libclamav/c++/llvm/docs/WritingAnLLVMBackend.html
index 5edc117..c0d6a12 100644
--- a/libclamav/c++/llvm/docs/WritingAnLLVMBackend.html
+++ b/libclamav/c++/llvm/docs/WritingAnLLVMBackend.html
@@ -2164,9 +2164,7 @@ in <tt>XXXGenAsmWriter.inc</tt> contains an implementation of the
The implementations of <tt>printDeclare</tt>, <tt>printImplicitDef</tt>,
<tt>printInlineAsm</tt>, and <tt>printLabel</tt> in <tt>AsmPrinter.cpp</tt> are
generally adequate for printing assembly and do not need to be
-overridden. (<tt>printBasicBlockLabel</tt> is another method that is implemented
-in <tt>AsmPrinter.cpp</tt> that may be directly used in an implementation of
-<tt>XXXAsmPrinter</tt>.)
+overridden.
</p>
<p>
diff --git a/libclamav/c++/llvm/docs/WritingAnLLVMPass.html b/libclamav/c++/llvm/docs/WritingAnLLVMPass.html
index ed6b4d6..f715a96 100644
--- a/libclamav/c++/llvm/docs/WritingAnLLVMPass.html
+++ b/libclamav/c++/llvm/docs/WritingAnLLVMPass.html
@@ -223,12 +223,14 @@ Start out with:</p>
<div class="doc_code"><pre>
<b>#include</b> "<a href="http://llvm.org/doxygen/Pass_8h-source.html">llvm/Pass.h</a>"
<b>#include</b> "<a href="http://llvm.org/doxygen/Function_8h-source.html">llvm/Function.h</a>"
+<b>#include</b> "<a href="http://llvm.org/doxygen/raw__ostream_8h.html">llvm/Support/raw_ostream.h</a>"
</pre></div>
<p>Which are needed because we are writing a <tt><a
-href="http://llvm.org/doxygen/classllvm_1_1Pass.html">Pass</a></tt>, and
+href="http://llvm.org/doxygen/classllvm_1_1Pass.html">Pass</a></tt>,
we are operating on <tt><a
-href="http://llvm.org/doxygen/classllvm_1_1Function.html">Function</a></tt>'s.</p>
+href="http://llvm.org/doxygen/classllvm_1_1Function.html">Function</a></tt>'s,
+and we will be doing some printing.</p>
<p>Next we have:</p>
<div class="doc_code"><pre>
@@ -273,7 +275,7 @@ avoid using expensive C++ runtime information.</p>
<div class="doc_code"><pre>
<b>virtual bool</b> <a href="#runOnFunction">runOnFunction</a>(Function &F) {
- llvm::cerr << "<i>Hello: </i>" << F.getName() << "\n";
+ errs() << "<i>Hello: </i>" << F.getName() << "\n";
<b>return false</b>;
}
}; <i>// end of struct Hello</i>
@@ -312,6 +314,7 @@ is supplied as fourth argument. </p>
<div class="doc_code"><pre>
<b>#include</b> "<a href="http://llvm.org/doxygen/Pass_8h-source.html">llvm/Pass.h</a>"
<b>#include</b> "<a href="http://llvm.org/doxygen/Function_8h-source.html">llvm/Function.h</a>"
+<b>#include</b> "<a href="http://llvm.org/doxygen/raw__ostream_8h.html">llvm/Support/raw_ostream.h</a>"
<b>using namespace llvm;</b>
@@ -322,7 +325,7 @@ is supplied as fourth argument. </p>
Hello() : FunctionPass(&ID) {}
<b>virtual bool</b> <a href="#runOnFunction">runOnFunction</a>(Function &F) {
- llvm::cerr << "<i>Hello: </i>" << F.getName() << "\n";
+ errs() << "<i>Hello: </i>" << F.getName() << "\n";
<b>return false</b>;
}
};
diff --git a/libclamav/c++/llvm/docs/index.html b/libclamav/c++/llvm/docs/index.html
index c41cc2c..5c50c41 100644
--- a/libclamav/c++/llvm/docs/index.html
+++ b/libclamav/c++/llvm/docs/index.html
@@ -233,6 +233,9 @@ the linker and its design</li>
<li><a href="GoldPlugin.html">The LLVM gold plugin</a> - How to build your
programs with link-time optimization on Linux.</li>
+
+<li><a href="DebuggingJITedCode.html">The GDB JIT interface</a> - How to debug
+JITed code with GDB.</li>
</ul>
diff --git a/libclamav/c++/llvm/docs/tutorial/LangImpl2.html b/libclamav/c++/llvm/docs/tutorial/LangImpl2.html
index 3021560..5bcd0dd 100644
--- a/libclamav/c++/llvm/docs/tutorial/LangImpl2.html
+++ b/libclamav/c++/llvm/docs/tutorial/LangImpl2.html
@@ -84,7 +84,7 @@ public:
class NumberExprAST : public ExprAST {
double Val;
public:
- explicit NumberExprAST(double val) : Val(val) {}
+ NumberExprAST(double val) : Val(val) {}
};
</pre>
</div>
@@ -107,7 +107,7 @@ in the basic form of the Kaleidoscope language:
class VariableExprAST : public ExprAST {
std::string Name;
public:
- explicit VariableExprAST(const std::string &name) : Name(name) {}
+ VariableExprAST(const std::string &name) : Name(name) {}
};
/// BinaryExprAST - Expression class for a binary operator.
@@ -333,9 +333,9 @@ static ExprAST *ParseIdentifierExpr() {
ExprAST *Arg = ParseExpression();
if (!Arg) return 0;
Args.push_back(Arg);
-
+
if (CurTok == ')') break;
-
+
if (CurTok != ',')
return Error("Expected ')' or ',' in argument list");
getNextToken();
@@ -833,7 +833,7 @@ enum Token {
tok_def = -2, tok_extern = -3,
// primary
- tok_identifier = -4, tok_number = -5,
+ tok_identifier = -4, tok_number = -5
};
static std::string IdentifierStr; // Filled in if tok_identifier
@@ -901,14 +901,14 @@ public:
class NumberExprAST : public ExprAST {
double Val;
public:
- explicit NumberExprAST(double val) : Val(val) {}
+ NumberExprAST(double val) : Val(val) {}
};
/// VariableExprAST - Expression class for referencing a variable, like "a".
class VariableExprAST : public ExprAST {
std::string Name;
public:
- explicit VariableExprAST(const std::string &name) : Name(name) {}
+ VariableExprAST(const std::string &name) : Name(name) {}
};
/// BinaryExprAST - Expression class for a binary operator.
@@ -1004,9 +1004,9 @@ static ExprAST *ParseIdentifierExpr() {
ExprAST *Arg = ParseExpression();
if (!Arg) return 0;
Args.push_back(Arg);
-
+
if (CurTok == ')') break;
-
+
if (CurTok != ',')
return Error("Expected ')' or ',' in argument list");
getNextToken();
@@ -1150,7 +1150,7 @@ static PrototypeAST *ParseExtern() {
//===----------------------------------------------------------------------===//
static void HandleDefinition() {
- if (FunctionAST *F = ParseDefinition()) {
+ if (ParseDefinition()) {
fprintf(stderr, "Parsed a function definition.\n");
} else {
// Skip token for error recovery.
@@ -1159,7 +1159,7 @@ static void HandleDefinition() {
}
static void HandleExtern() {
- if (PrototypeAST *P = ParseExtern()) {
+ if (ParseExtern()) {
fprintf(stderr, "Parsed an extern\n");
} else {
// Skip token for error recovery.
@@ -1169,7 +1169,7 @@ static void HandleExtern() {
static void HandleTopLevelExpression() {
// Evaluate a top-level expression into an anonymous function.
- if (FunctionAST *F = ParseTopLevelExpr()) {
+ if (ParseTopLevelExpr()) {
fprintf(stderr, "Parsed a top-level expr\n");
} else {
// Skip token for error recovery.
@@ -1207,7 +1207,9 @@ int main() {
fprintf(stderr, "ready> ");
getNextToken();
+ // Run the main "interpreter loop" now.
MainLoop();
+
return 0;
}
</pre>
diff --git a/libclamav/c++/llvm/docs/tutorial/LangImpl3.html b/libclamav/c++/llvm/docs/tutorial/LangImpl3.html
index 5978707..bc5db46 100644
--- a/libclamav/c++/llvm/docs/tutorial/LangImpl3.html
+++ b/libclamav/c++/llvm/docs/tutorial/LangImpl3.html
@@ -79,7 +79,7 @@ public:
class NumberExprAST : public ExprAST {
double Val;
public:
- explicit NumberExprAST(double val) : Val(val) {}
+ NumberExprAST(double val) : Val(val) {}
<b>virtual Value *Codegen();</b>
};
...
@@ -206,7 +206,8 @@ Value *BinaryExprAST::Codegen() {
case '<':
L = Builder.CreateFCmpULT(L, R, "cmptmp");
// Convert bool 0/1 to double 0.0 or 1.0
- return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()), "booltmp");
+ return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()),
+ "booltmp");
default: return ErrorV("invalid binary operator");
}
}
@@ -307,8 +308,10 @@ bodies and external function declarations. The code starts with:</p>
<pre>
Function *PrototypeAST::Codegen() {
// Make the function type: double(double,double) etc.
- std::vector<const Type*> Doubles(Args.size(), Type::getDoubleTy(getGlobalContext()));
- FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()), Doubles, false);
+ std::vector<const Type*> Doubles(Args.size(),
+ Type::getDoubleTy(getGlobalContext()));
+ FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()),
+ Doubles, false);
Function *F = Function::Create(FT, Function::ExternalLinkage, Name, TheModule);
</pre>
@@ -461,9 +464,10 @@ block at this point. We'll fix this in <a href="LangImpl5.html">Chapter 5</a> :
if (Value *RetVal = Body->Codegen()) {
// Finish off the function.
Builder.CreateRet(RetVal);
-
+
// Validate the generated code, checking for consistency.
verifyFunction(*TheFunction);
+
return TheFunction;
}
</pre>
@@ -705,7 +709,7 @@ enum Token {
tok_def = -2, tok_extern = -3,
// primary
- tok_identifier = -4, tok_number = -5,
+ tok_identifier = -4, tok_number = -5
};
static std::string IdentifierStr; // Filled in if tok_identifier
@@ -774,7 +778,7 @@ public:
class NumberExprAST : public ExprAST {
double Val;
public:
- explicit NumberExprAST(double val) : Val(val) {}
+ NumberExprAST(double val) : Val(val) {}
virtual Value *Codegen();
};
@@ -782,7 +786,7 @@ public:
class VariableExprAST : public ExprAST {
std::string Name;
public:
- explicit VariableExprAST(const std::string &name) : Name(name) {}
+ VariableExprAST(const std::string &name) : Name(name) {}
virtual Value *Codegen();
};
@@ -807,7 +811,8 @@ public:
};
/// PrototypeAST - This class represents the "prototype" for a function,
-/// which captures its argument names as well as if it is an operator.
+/// which captures its name, and its argument names (thus implicitly the number
+/// of arguments the function takes).
class PrototypeAST {
std::string Name;
std::vector<std::string> Args;
@@ -834,7 +839,7 @@ public:
//===----------------------------------------------------------------------===//
/// CurTok/getNextToken - Provide a simple token buffer. CurTok is the current
-/// token the parser it looking at. getNextToken reads another token from the
+/// token the parser is looking at. getNextToken reads another token from the
/// lexer and updates CurTok with its results.
static int CurTok;
static int getNextToken() {
@@ -882,9 +887,9 @@ static ExprAST *ParseIdentifierExpr() {
ExprAST *Arg = ParseExpression();
if (!Arg) return 0;
Args.push_back(Arg);
-
+
if (CurTok == ')') break;
-
+
if (CurTok != ',')
return Error("Expected ')' or ',' in argument list");
getNextToken();
@@ -1055,7 +1060,8 @@ Value *BinaryExprAST::Codegen() {
case '<':
L = Builder.CreateFCmpULT(L, R, "cmptmp");
// Convert bool 0/1 to double 0.0 or 1.0
- return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()), "booltmp");
+ return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()),
+ "booltmp");
default: return ErrorV("invalid binary operator");
}
}
@@ -1081,8 +1087,10 @@ Value *CallExprAST::Codegen() {
Function *PrototypeAST::Codegen() {
// Make the function type: double(double,double) etc.
- std::vector<const Type*> Doubles(Args.size(), Type::getDoubleTy(getGlobalContext()));
- FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()), Doubles, false);
+ std::vector<const Type*> Doubles(Args.size(),
+ Type::getDoubleTy(getGlobalContext()));
+ FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()),
+ Doubles, false);
Function *F = Function::Create(FT, Function::ExternalLinkage, Name, TheModule);
@@ -1133,9 +1141,10 @@ Function *FunctionAST::Codegen() {
if (Value *RetVal = Body->Codegen()) {
// Finish off the function.
Builder.CreateRet(RetVal);
-
+
// Validate the generated code, checking for consistency.
verifyFunction(*TheFunction);
+
return TheFunction;
}
@@ -1173,7 +1182,7 @@ static void HandleExtern() {
}
static void HandleTopLevelExpression() {
- // Evaluate a top level expression into an anonymous function.
+ // Evaluate a top-level expression into an anonymous function.
if (FunctionAST *F = ParseTopLevelExpr()) {
if (Function *LF = F->Codegen()) {
fprintf(stderr, "Read top-level expression:");
@@ -1191,7 +1200,7 @@ static void MainLoop() {
fprintf(stderr, "ready> ");
switch (CurTok) {
case tok_eof: return;
- case ';': getNextToken(); break; // ignore top level semicolons.
+ case ';': getNextToken(); break; // ignore top-level semicolons.
case tok_def: HandleDefinition(); break;
case tok_extern: HandleExtern(); break;
default: HandleTopLevelExpression(); break;
@@ -1199,8 +1208,6 @@ static void MainLoop() {
}
}
-
-
//===----------------------------------------------------------------------===//
// "Library" functions that can be "extern'd" from user code.
//===----------------------------------------------------------------------===//
@@ -1217,7 +1224,7 @@ double putchard(double X) {
//===----------------------------------------------------------------------===//
int main() {
- TheModule = new Module("my cool jit", getGlobalContext());
+ LLVMContext &Context = getGlobalContext();
// Install standard binary operators.
// 1 is lowest precedence.
@@ -1230,8 +1237,15 @@ int main() {
fprintf(stderr, "ready> ");
getNextToken();
+ // Make the module, which holds all the code.
+ TheModule = new Module("my cool jit", Context);
+
+ // Run the main "interpreter loop" now.
MainLoop();
+
+ // Print out all of the generated code.
TheModule->dump();
+
return 0;
}
</pre>
diff --git a/libclamav/c++/llvm/docs/tutorial/LangImpl4.html b/libclamav/c++/llvm/docs/tutorial/LangImpl4.html
index 0163b25..8310b61 100644
--- a/libclamav/c++/llvm/docs/tutorial/LangImpl4.html
+++ b/libclamav/c++/llvm/docs/tutorial/LangImpl4.html
@@ -188,6 +188,8 @@ add a set of optimizations to run. The code looks like this:</p>
// Simplify the control flow graph (deleting unreachable blocks, etc).
OurFPM.add(createCFGSimplificationPass());
+ OurFPM.doInitialization();
+
// Set the global so the code gen can use this.
TheFPM = &OurFPM;
@@ -322,7 +324,7 @@ top-level expression to look like this:</p>
<div class="doc_code">
<pre>
static void HandleTopLevelExpression() {
- // Evaluate a top level expression into an anonymous function.
+ // Evaluate a top-level expression into an anonymous function.
if (FunctionAST *F = ParseTopLevelExpr()) {
if (Function *LF = F->Codegen()) {
LF->dump(); // Dump the function for exposition purposes.
@@ -332,7 +334,7 @@ static void HandleTopLevelExpression() {
// Cast it to the right type (takes no arguments, returns a double) so we
// can call it as a native function.
- double (*FP)() = (double (*)())FPtr;
+ double (*FP)() = (double (*)())(intptr_t)FPtr;
fprintf(stderr, "Evaluated to %f\n", FP());</b>
}
</pre>
@@ -361,7 +363,7 @@ entry:
<p>Well this looks like it is basically working. The dump of the function
shows the "no argument function that always returns double" that we synthesize
-for each top level expression that is typed in. This demonstrates very basic
+for each top-level expression that is typed in. This demonstrates very basic
functionality, but can we do more?</p>
<div class="doc_code">
@@ -497,7 +499,7 @@ LLVM JIT and optimizer. To build this example, use:
<div class="doc_code">
<pre>
# Compile
- g++ -g toy.cpp `llvm-config --cppflags --ldflags --libs core jit native` -O3 -o toy
+ g++ -g toy.cpp `llvm-config --cppflags --ldflags --libs core jit interpreter native` -O3 -o toy
# Run
./toy
</pre>
@@ -514,12 +516,15 @@ at runtime.</p>
<pre>
#include "llvm/DerivedTypes.h"
#include "llvm/ExecutionEngine/ExecutionEngine.h"
+#include "llvm/ExecutionEngine/Interpreter.h"
+#include "llvm/ExecutionEngine/JIT.h"
#include "llvm/LLVMContext.h"
#include "llvm/Module.h"
#include "llvm/ModuleProvider.h"
#include "llvm/PassManager.h"
#include "llvm/Analysis/Verifier.h"
#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetSelect.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/IRBuilder.h"
#include <cstdio>
@@ -541,7 +546,7 @@ enum Token {
tok_def = -2, tok_extern = -3,
// primary
- tok_identifier = -4, tok_number = -5,
+ tok_identifier = -4, tok_number = -5
};
static std::string IdentifierStr; // Filled in if tok_identifier
@@ -643,7 +648,8 @@ public:
};
/// PrototypeAST - This class represents the "prototype" for a function,
-/// which captures its argument names as well as if it is an operator.
+/// which captures its name, and its argument names (thus implicitly the number
+/// of arguments the function takes).
class PrototypeAST {
std::string Name;
std::vector<std::string> Args;
@@ -670,7 +676,7 @@ public:
//===----------------------------------------------------------------------===//
/// CurTok/getNextToken - Provide a simple token buffer. CurTok is the current
-/// token the parser it looking at. getNextToken reads another token from the
+/// token the parser is looking at. getNextToken reads another token from the
/// lexer and updates CurTok with its results.
static int CurTok;
static int getNextToken() {
@@ -718,9 +724,9 @@ static ExprAST *ParseIdentifierExpr() {
ExprAST *Arg = ParseExpression();
if (!Arg) return 0;
Args.push_back(Arg);
-
+
if (CurTok == ')') break;
-
+
if (CurTok != ',')
return Error("Expected ')' or ',' in argument list");
getNextToken();
@@ -892,7 +898,8 @@ Value *BinaryExprAST::Codegen() {
case '<':
L = Builder.CreateFCmpULT(L, R, "cmptmp");
// Convert bool 0/1 to double 0.0 or 1.0
- return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()), "booltmp");
+ return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()),
+ "booltmp");
default: return ErrorV("invalid binary operator");
}
}
@@ -918,8 +925,10 @@ Value *CallExprAST::Codegen() {
Function *PrototypeAST::Codegen() {
// Make the function type: double(double,double) etc.
- std::vector<const Type*> Doubles(Args.size(), Type::getDoubleTy(getGlobalContext()));
- FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()), Doubles, false);
+ std::vector<const Type*> Doubles(Args.size(),
+ Type::getDoubleTy(getGlobalContext()));
+ FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()),
+ Doubles, false);
Function *F = Function::Create(FT, Function::ExternalLinkage, Name, TheModule);
@@ -1016,7 +1025,7 @@ static void HandleExtern() {
}
static void HandleTopLevelExpression() {
- // Evaluate a top level expression into an anonymous function.
+ // Evaluate a top-level expression into an anonymous function.
if (FunctionAST *F = ParseTopLevelExpr()) {
if (Function *LF = F->Codegen()) {
// JIT the function, returning a function pointer.
@@ -1024,7 +1033,7 @@ static void HandleTopLevelExpression() {
// Cast it to the right type (takes no arguments, returns a double) so we
// can call it as a native function.
- double (*FP)() = (double (*)())FPtr;
+ double (*FP)() = (double (*)())(intptr_t)FPtr;
fprintf(stderr, "Evaluated to %f\n", FP());
}
} else {
@@ -1039,7 +1048,7 @@ static void MainLoop() {
fprintf(stderr, "ready> ");
switch (CurTok) {
case tok_eof: return;
- case ';': getNextToken(); break; // ignore top level semicolons.
+ case ';': getNextToken(); break; // ignore top-level semicolons.
case tok_def: HandleDefinition(); break;
case tok_extern: HandleExtern(); break;
default: HandleTopLevelExpression(); break;
@@ -1047,8 +1056,6 @@ static void MainLoop() {
}
}
-
-
//===----------------------------------------------------------------------===//
// "Library" functions that can be "extern'd" from user code.
//===----------------------------------------------------------------------===//
@@ -1065,6 +1072,9 @@ double putchard(double X) {
//===----------------------------------------------------------------------===//
int main() {
+ InitializeNativeTarget();
+ LLVMContext &Context = getGlobalContext();
+
// Install standard binary operators.
// 1 is lowest precedence.
BinopPrecedence['<'] = 10;
@@ -1077,7 +1087,7 @@ int main() {
getNextToken();
// Make the module, which holds all the code.
- TheModule = new Module("my cool jit", getGlobalContext());
+ TheModule = new Module("my cool jit", Context);
ExistingModuleProvider *OurModuleProvider =
new ExistingModuleProvider(TheModule);
@@ -1099,6 +1109,8 @@ int main() {
// Simplify the control flow graph (deleting unreachable blocks, etc).
OurFPM.add(createCFGSimplificationPass());
+ OurFPM.doInitialization();
+
// Set the global so the code gen can use this.
TheFPM = &OurFPM;
diff --git a/libclamav/c++/llvm/docs/tutorial/LangImpl5.html b/libclamav/c++/llvm/docs/tutorial/LangImpl5.html
index 3ded139..f93b59b 100644
--- a/libclamav/c++/llvm/docs/tutorial/LangImpl5.html
+++ b/libclamav/c++/llvm/docs/tutorial/LangImpl5.html
@@ -472,7 +472,8 @@ are emitted, we can finish up with the merge code:</p>
// Emit merge block.
TheFunction->getBasicBlockList().push_back(MergeBB);
Builder.SetInsertPoint(MergeBB);
- PHINode *PN = Builder.CreatePHI(Type::getDoubleTy(getGlobalContext()), "iftmp");
+ PHINode *PN = Builder.CreatePHI(Type::getDoubleTy(getGlobalContext()),
+ "iftmp");
PN->addIncoming(ThenV, ThenBB);
PN->addIncoming(ElseV, ElseBB);
@@ -901,12 +902,15 @@ if/then/else and for expressions.. To build this example, use:
<pre>
#include "llvm/DerivedTypes.h"
#include "llvm/ExecutionEngine/ExecutionEngine.h"
+#include "llvm/ExecutionEngine/Interpreter.h"
+#include "llvm/ExecutionEngine/JIT.h"
#include "llvm/LLVMContext.h"
#include "llvm/Module.h"
#include "llvm/ModuleProvider.h"
#include "llvm/PassManager.h"
#include "llvm/Analysis/Verifier.h"
#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetSelect.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/IRBuilder.h"
#include <cstdio>
@@ -1059,7 +1063,8 @@ public:
};
/// PrototypeAST - This class represents the "prototype" for a function,
-/// which captures its argument names as well as if it is an operator.
+/// which captures its name, and its argument names (thus implicitly the number
+/// of arguments the function takes).
class PrototypeAST {
std::string Name;
std::vector<std::string> Args;
@@ -1086,7 +1091,7 @@ public:
//===----------------------------------------------------------------------===//
/// CurTok/getNextToken - Provide a simple token buffer. CurTok is the current
-/// token the parser it looking at. getNextToken reads another token from the
+/// token the parser is looking at. getNextToken reads another token from the
/// lexer and updates CurTok with its results.
static int CurTok;
static int getNextToken() {
@@ -1134,9 +1139,9 @@ static ExprAST *ParseIdentifierExpr() {
ExprAST *Arg = ParseExpression();
if (!Arg) return 0;
Args.push_back(Arg);
-
+
if (CurTok == ')') break;
-
+
if (CurTok != ',')
return Error("Expected ')' or ',' in argument list");
getNextToken();
@@ -1236,7 +1241,6 @@ static ExprAST *ParseForExpr() {
return new ForExprAST(IdName, Start, End, Step, Body);
}
-
/// primary
/// ::= identifierexpr
/// ::= numberexpr
@@ -1381,7 +1385,8 @@ Value *BinaryExprAST::Codegen() {
case '<':
L = Builder.CreateFCmpULT(L, R, "cmptmp");
// Convert bool 0/1 to double 0.0 or 1.0
- return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()), "booltmp");
+ return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()),
+ "booltmp");
default: return ErrorV("invalid binary operator");
}
}
@@ -1448,7 +1453,8 @@ Value *IfExprAST::Codegen() {
// Emit merge block.
TheFunction->getBasicBlockList().push_back(MergeBB);
Builder.SetInsertPoint(MergeBB);
- PHINode *PN = Builder.CreatePHI(Type::getDoubleTy(getGlobalContext()), "iftmp");
+ PHINode *PN = Builder.CreatePHI(Type::getDoubleTy(getGlobalContext()),
+ "iftmp");
PN->addIncoming(ThenV, ThenBB);
PN->addIncoming(ElseV, ElseBB);
@@ -1545,13 +1551,15 @@ Value *ForExprAST::Codegen() {
// for expr always returns 0.0.
- return getGlobalContext().getNullValue(Type::getDoubleTy(getGlobalContext()));
+ return Constant::getNullValue(Type::getDoubleTy(getGlobalContext()));
}
Function *PrototypeAST::Codegen() {
// Make the function type: double(double,double) etc.
- std::vector<const Type*> Doubles(Args.size(), Type::getDoubleTy(getGlobalContext()));
- FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()), Doubles, false);
+ std::vector<const Type*> Doubles(Args.size(),
+ Type::getDoubleTy(getGlobalContext()));
+ FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()),
+ Doubles, false);
Function *F = Function::Create(FT, Function::ExternalLinkage, Name, TheModule);
@@ -1648,7 +1656,7 @@ static void HandleExtern() {
}
static void HandleTopLevelExpression() {
- // Evaluate a top level expression into an anonymous function.
+ // Evaluate a top-level expression into an anonymous function.
if (FunctionAST *F = ParseTopLevelExpr()) {
if (Function *LF = F->Codegen()) {
// JIT the function, returning a function pointer.
@@ -1656,7 +1664,7 @@ static void HandleTopLevelExpression() {
// Cast it to the right type (takes no arguments, returns a double) so we
// can call it as a native function.
- double (*FP)() = (double (*)())FPtr;
+ double (*FP)() = (double (*)())(intptr_t)FPtr;
fprintf(stderr, "Evaluated to %f\n", FP());
}
} else {
@@ -1671,7 +1679,7 @@ static void MainLoop() {
fprintf(stderr, "ready> ");
switch (CurTok) {
case tok_eof: return;
- case ';': getNextToken(); break; // ignore top level semicolons.
+ case ';': getNextToken(); break; // ignore top-level semicolons.
case tok_def: HandleDefinition(); break;
case tok_extern: HandleExtern(); break;
default: HandleTopLevelExpression(); break;
@@ -1679,8 +1687,6 @@ static void MainLoop() {
}
}
-
-
//===----------------------------------------------------------------------===//
// "Library" functions that can be "extern'd" from user code.
//===----------------------------------------------------------------------===//
@@ -1697,6 +1703,9 @@ double putchard(double X) {
//===----------------------------------------------------------------------===//
int main() {
+ InitializeNativeTarget();
+ LLVMContext &Context = getGlobalContext();
+
// Install standard binary operators.
// 1 is lowest precedence.
BinopPrecedence['<'] = 10;
@@ -1709,7 +1718,7 @@ int main() {
getNextToken();
// Make the module, which holds all the code.
- TheModule = new Module("my cool jit", getGlobalContext());
+ TheModule = new Module("my cool jit", Context);
ExistingModuleProvider *OurModuleProvider =
new ExistingModuleProvider(TheModule);
@@ -1731,6 +1740,8 @@ int main() {
// Simplify the control flow graph (deleting unreachable blocks, etc).
OurFPM.add(createCFGSimplificationPass());
+ OurFPM.doInitialization();
+
// Set the global so the code gen can use this.
TheFPM = &OurFPM;
diff --git a/libclamav/c++/llvm/docs/tutorial/LangImpl6.html b/libclamav/c++/llvm/docs/tutorial/LangImpl6.html
index a61c82c..f113e96 100644
--- a/libclamav/c++/llvm/docs/tutorial/LangImpl6.html
+++ b/libclamav/c++/llvm/docs/tutorial/LangImpl6.html
@@ -207,7 +207,7 @@ the prototype for a user-defined operator, we need to parse it:</p>
static PrototypeAST *ParsePrototype() {
std::string FnName;
- <b>int Kind = 0; // 0 = identifier, 1 = unary, 2 = binary.
+ <b>unsigned Kind = 0; // 0 = identifier, 1 = unary, 2 = binary.
unsigned BinaryPrecedence = 30;</b>
switch (CurTok) {
@@ -283,7 +283,8 @@ Value *BinaryExprAST::Codegen() {
case '<':
L = Builder.CreateFCmpULT(L, R, "cmptmp");
// Convert bool 0/1 to double 0.0 or 1.0
- return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()), "booltmp");
+ return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()),
+ "booltmp");
<b>default: break;</b>
}
@@ -305,7 +306,7 @@ function call to it. Since user-defined operators are just built as normal
functions (because the "prototype" boils down to a function with the right
name) everything falls into place.</p>
-<p>The final piece of code we are missing, is a bit of top level magic:</p>
+<p>The final piece of code we are missing, is a bit of top-level magic:</p>
<div class="doc_code">
<pre>
@@ -438,7 +439,7 @@ with:</p>
static PrototypeAST *ParsePrototype() {
std::string FnName;
- int Kind = 0; // 0 = identifier, 1 = unary, 2 = binary.
+ unsigned Kind = 0; // 0 = identifier, 1 = unary, 2 = binary.
unsigned BinaryPrecedence = 30;
switch (CurTok) {
@@ -794,7 +795,6 @@ add variable mutation without building SSA in your front-end.</p>
</div>
-
<!-- *********************************************************************** -->
<div class="doc_section"><a name="code">Full Code Listing</a></div>
<!-- *********************************************************************** -->
@@ -821,12 +821,15 @@ if/then/else and for expressions.. To build this example, use:
<pre>
#include "llvm/DerivedTypes.h"
#include "llvm/ExecutionEngine/ExecutionEngine.h"
+#include "llvm/ExecutionEngine/Interpreter.h"
+#include "llvm/ExecutionEngine/JIT.h"
#include "llvm/LLVMContext.h"
#include "llvm/Module.h"
#include "llvm/ModuleProvider.h"
#include "llvm/PassManager.h"
#include "llvm/Analysis/Verifier.h"
#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetSelect.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/IRBuilder.h"
#include <cstdio>
@@ -994,7 +997,8 @@ public:
};
/// PrototypeAST - This class represents the "prototype" for a function,
-/// which captures its argument names as well as if it is an operator.
+/// which captures its name, and its argument names (thus implicitly the number
+/// of arguments the function takes), as well as if it is an operator.
class PrototypeAST {
std::string Name;
std::vector<std::string> Args;
@@ -1034,7 +1038,7 @@ public:
//===----------------------------------------------------------------------===//
/// CurTok/getNextToken - Provide a simple token buffer. CurTok is the current
-/// token the parser it looking at. getNextToken reads another token from the
+/// token the parser is looking at. getNextToken reads another token from the
/// lexer and updates CurTok with its results.
static int CurTok;
static int getNextToken() {
@@ -1082,9 +1086,9 @@ static ExprAST *ParseIdentifierExpr() {
ExprAST *Arg = ParseExpression();
if (!Arg) return 0;
Args.push_back(Arg);
-
+
if (CurTok == ')') break;
-
+
if (CurTok != ',')
return Error("Expected ')' or ',' in argument list");
getNextToken();
@@ -1184,7 +1188,6 @@ static ExprAST *ParseForExpr() {
return new ForExprAST(IdName, Start, End, Step, Body);
}
-
/// primary
/// ::= identifierexpr
/// ::= numberexpr
@@ -1268,7 +1271,7 @@ static ExprAST *ParseExpression() {
static PrototypeAST *ParsePrototype() {
std::string FnName;
- int Kind = 0; // 0 = identifier, 1 = unary, 2 = binary.
+ unsigned Kind = 0; // 0 = identifier, 1 = unary, 2 = binary.
unsigned BinaryPrecedence = 30;
switch (CurTok) {
@@ -1385,7 +1388,6 @@ Value *UnaryExprAST::Codegen() {
return Builder.CreateCall(F, OperandV, "unop");
}
-
Value *BinaryExprAST::Codegen() {
Value *L = LHS->Codegen();
Value *R = RHS->Codegen();
@@ -1398,7 +1400,8 @@ Value *BinaryExprAST::Codegen() {
case '<':
L = Builder.CreateFCmpULT(L, R, "cmptmp");
// Convert bool 0/1 to double 0.0 or 1.0
- return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()), "booltmp");
+ return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()),
+ "booltmp");
default: break;
}
@@ -1473,7 +1476,8 @@ Value *IfExprAST::Codegen() {
// Emit merge block.
TheFunction->getBasicBlockList().push_back(MergeBB);
Builder.SetInsertPoint(MergeBB);
- PHINode *PN = Builder.CreatePHI(Type::getDoubleTy(getGlobalContext()), "iftmp");
+ PHINode *PN = Builder.CreatePHI(Type::getDoubleTy(getGlobalContext()),
+ "iftmp");
PN->addIncoming(ThenV, ThenBB);
PN->addIncoming(ElseV, ElseBB);
@@ -1575,8 +1579,10 @@ Value *ForExprAST::Codegen() {
Function *PrototypeAST::Codegen() {
// Make the function type: double(double,double) etc.
- std::vector<const Type*> Doubles(Args.size(), Type::getDoubleTy(getGlobalContext()));
- FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()), Doubles, false);
+ std::vector<const Type*> Doubles(Args.size(),
+ Type::getDoubleTy(getGlobalContext()));
+ FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()),
+ Doubles, false);
Function *F = Function::Create(FT, Function::ExternalLinkage, Name, TheModule);
@@ -1680,7 +1686,7 @@ static void HandleExtern() {
}
static void HandleTopLevelExpression() {
- // Evaluate a top level expression into an anonymous function.
+ // Evaluate a top-level expression into an anonymous function.
if (FunctionAST *F = ParseTopLevelExpr()) {
if (Function *LF = F->Codegen()) {
// JIT the function, returning a function pointer.
@@ -1688,7 +1694,7 @@ static void HandleTopLevelExpression() {
// Cast it to the right type (takes no arguments, returns a double) so we
// can call it as a native function.
- double (*FP)() = (double (*)())FPtr;
+ double (*FP)() = (double (*)())(intptr_t)FPtr;
fprintf(stderr, "Evaluated to %f\n", FP());
}
} else {
@@ -1703,7 +1709,7 @@ static void MainLoop() {
fprintf(stderr, "ready> ");
switch (CurTok) {
case tok_eof: return;
- case ';': getNextToken(); break; // ignore top level semicolons.
+ case ';': getNextToken(); break; // ignore top-level semicolons.
case tok_def: HandleDefinition(); break;
case tok_extern: HandleExtern(); break;
default: HandleTopLevelExpression(); break;
@@ -1711,8 +1717,6 @@ static void MainLoop() {
}
}
-
-
//===----------------------------------------------------------------------===//
// "Library" functions that can be "extern'd" from user code.
//===----------------------------------------------------------------------===//
@@ -1736,6 +1740,9 @@ double printd(double X) {
//===----------------------------------------------------------------------===//
int main() {
+ InitializeNativeTarget();
+ LLVMContext &Context = getGlobalContext();
+
// Install standard binary operators.
// 1 is lowest precedence.
BinopPrecedence['<'] = 10;
@@ -1748,7 +1755,7 @@ int main() {
getNextToken();
// Make the module, which holds all the code.
- TheModule = new Module("my cool jit", getGlobalContext());
+ TheModule = new Module("my cool jit", Context);
ExistingModuleProvider *OurModuleProvider =
new ExistingModuleProvider(TheModule);
@@ -1770,6 +1777,8 @@ int main() {
// Simplify the control flow graph (deleting unreachable blocks, etc).
OurFPM.add(createCFGSimplificationPass());
+ OurFPM.doInitialization();
+
// Set the global so the code gen can use this.
TheFPM = &OurFPM;
diff --git a/libclamav/c++/llvm/docs/tutorial/LangImpl7.html b/libclamav/c++/llvm/docs/tutorial/LangImpl7.html
index 90925a9..ec07fa8 100644
--- a/libclamav/c++/llvm/docs/tutorial/LangImpl7.html
+++ b/libclamav/c++/llvm/docs/tutorial/LangImpl7.html
@@ -424,7 +424,8 @@ static AllocaInst *CreateEntryBlockAlloca(Function *TheFunction,
const std::string &VarName) {
IRBuilder<> TmpB(&TheFunction->getEntryBlock(),
TheFunction->getEntryBlock().begin());
- return TmpB.CreateAlloca(Type::getDoubleTy(getGlobalContext()), 0, VarName.c_str());
+ return TmpB.CreateAlloca(Type::getDoubleTy(getGlobalContext()), 0,
+ VarName.c_str());
}
</pre>
</div>
@@ -1003,12 +1004,15 @@ variables and var/in support. To build this example, use:
<pre>
#include "llvm/DerivedTypes.h"
#include "llvm/ExecutionEngine/ExecutionEngine.h"
+#include "llvm/ExecutionEngine/Interpreter.h"
+#include "llvm/ExecutionEngine/JIT.h"
#include "llvm/LLVMContext.h"
#include "llvm/Module.h"
#include "llvm/ModuleProvider.h"
#include "llvm/PassManager.h"
#include "llvm/Analysis/Verifier.h"
#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetSelect.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/IRBuilder.h"
#include <cstdio>
@@ -1193,7 +1197,8 @@ public:
};
/// PrototypeAST - This class represents the "prototype" for a function,
-/// which captures its argument names as well as if it is an operator.
+/// which captures its name, and its argument names (thus implicitly the number
+/// of arguments the function takes), as well as if it is an operator.
class PrototypeAST {
std::string Name;
std::vector<std::string> Args;
@@ -1235,7 +1240,7 @@ public:
//===----------------------------------------------------------------------===//
/// CurTok/getNextToken - Provide a simple token buffer. CurTok is the current
-/// token the parser it looking at. getNextToken reads another token from the
+/// token the parser is looking at. getNextToken reads another token from the
/// lexer and updates CurTok with its results.
static int CurTok;
static int getNextToken() {
@@ -1283,9 +1288,9 @@ static ExprAST *ParseIdentifierExpr() {
ExprAST *Arg = ParseExpression();
if (!Arg) return 0;
Args.push_back(Arg);
-
+
if (CurTok == ')') break;
-
+
if (CurTok != ',')
return Error("Expected ')' or ',' in argument list");
getNextToken();
@@ -1430,7 +1435,6 @@ static ExprAST *ParseVarExpr() {
return new VarExprAST(VarNames, Body);
}
-
/// primary
/// ::= identifierexpr
/// ::= numberexpr
@@ -1516,7 +1520,7 @@ static ExprAST *ParseExpression() {
static PrototypeAST *ParsePrototype() {
std::string FnName;
- int Kind = 0; // 0 = identifier, 1 = unary, 2 = binary.
+ unsigned Kind = 0; // 0 = identifier, 1 = unary, 2 = binary.
unsigned BinaryPrecedence = 30;
switch (CurTok) {
@@ -1618,10 +1622,10 @@ static AllocaInst *CreateEntryBlockAlloca(Function *TheFunction,
const std::string &VarName) {
IRBuilder<> TmpB(&TheFunction->getEntryBlock(),
TheFunction->getEntryBlock().begin());
- return TmpB.CreateAlloca(Type::getDoubleTy(getGlobalContext()), 0, VarName.c_str());
+ return TmpB.CreateAlloca(Type::getDoubleTy(getGlobalContext()), 0,
+ VarName.c_str());
}
-
Value *NumberExprAST::Codegen() {
return ConstantFP::get(getGlobalContext(), APFloat(Val));
}
@@ -1646,7 +1650,6 @@ Value *UnaryExprAST::Codegen() {
return Builder.CreateCall(F, OperandV, "unop");
}
-
Value *BinaryExprAST::Codegen() {
// Special case '=' because we don't want to emit the LHS as an expression.
if (Op == '=') {
@@ -1666,7 +1669,6 @@ Value *BinaryExprAST::Codegen() {
return Val;
}
-
Value *L = LHS->Codegen();
Value *R = RHS->Codegen();
if (L == 0 || R == 0) return 0;
@@ -1678,7 +1680,8 @@ Value *BinaryExprAST::Codegen() {
case '<':
L = Builder.CreateFCmpULT(L, R, "cmptmp");
// Convert bool 0/1 to double 0.0 or 1.0
- return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()), "booltmp");
+ return Builder.CreateUIToFP(L, Type::getDoubleTy(getGlobalContext()),
+ "booltmp");
default: break;
}
@@ -1753,7 +1756,8 @@ Value *IfExprAST::Codegen() {
// Emit merge block.
TheFunction->getBasicBlockList().push_back(MergeBB);
Builder.SetInsertPoint(MergeBB);
- PHINode *PN = Builder.CreatePHI(Type::getDoubleTy(getGlobalContext()), "iftmp");
+ PHINode *PN = Builder.CreatePHI(Type::getDoubleTy(getGlobalContext()),
+ "iftmp");
PN->addIncoming(ThenV, ThenBB);
PN->addIncoming(ElseV, ElseBB);
@@ -1795,7 +1799,6 @@ Value *ForExprAST::Codegen() {
// Make the new basic block for the loop header, inserting after current
// block.
- BasicBlock *PreheaderBB = Builder.GetInsertBlock();
BasicBlock *LoopBB = BasicBlock::Create(getGlobalContext(), "loop", TheFunction);
// Insert an explicit fall through from the current block to the LoopBB.
@@ -1841,7 +1844,6 @@ Value *ForExprAST::Codegen() {
"loopcond");
// Create the "after loop" block and insert it.
- BasicBlock *LoopEndBB = Builder.GetInsertBlock();
BasicBlock *AfterBB = BasicBlock::Create(getGlobalContext(), "afterloop", TheFunction);
// Insert the conditional branch into the end of LoopEndBB.
@@ -1907,11 +1909,12 @@ Value *VarExprAST::Codegen() {
return BodyVal;
}
-
Function *PrototypeAST::Codegen() {
// Make the function type: double(double,double) etc.
- std::vector<const Type*> Doubles(Args.size(), Type::getDoubleTy(getGlobalContext()));
- FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()), Doubles, false);
+ std::vector<const Type*> Doubles(Args.size(),
+ Type::getDoubleTy(getGlobalContext()));
+ FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()),
+ Doubles, false);
Function *F = Function::Create(FT, Function::ExternalLinkage, Name, TheModule);
@@ -1960,7 +1963,6 @@ void PrototypeAST::CreateArgumentAllocas(Function *F) {
}
}
-
Function *FunctionAST::Codegen() {
NamedValues.clear();
@@ -1978,7 +1980,7 @@ Function *FunctionAST::Codegen() {
// Add all arguments to the symbol table and create their allocas.
Proto->CreateArgumentAllocas(TheFunction);
-
+
if (Value *RetVal = Body->Codegen()) {
// Finish off the function.
Builder.CreateRet(RetVal);
@@ -2031,7 +2033,7 @@ static void HandleExtern() {
}
static void HandleTopLevelExpression() {
- // Evaluate a top level expression into an anonymous function.
+ // Evaluate a top-level expression into an anonymous function.
if (FunctionAST *F = ParseTopLevelExpr()) {
if (Function *LF = F->Codegen()) {
// JIT the function, returning a function pointer.
@@ -2039,7 +2041,7 @@ static void HandleTopLevelExpression() {
// Cast it to the right type (takes no arguments, returns a double) so we
// can call it as a native function.
- double (*FP)() = (double (*)())FPtr;
+ double (*FP)() = (double (*)())(intptr_t)FPtr;
fprintf(stderr, "Evaluated to %f\n", FP());
}
} else {
@@ -2054,7 +2056,7 @@ static void MainLoop() {
fprintf(stderr, "ready> ");
switch (CurTok) {
case tok_eof: return;
- case ';': getNextToken(); break; // ignore top level semicolons.
+ case ';': getNextToken(); break; // ignore top-level semicolons.
case tok_def: HandleDefinition(); break;
case tok_extern: HandleExtern(); break;
default: HandleTopLevelExpression(); break;
@@ -2062,8 +2064,6 @@ static void MainLoop() {
}
}
-
-
//===----------------------------------------------------------------------===//
// "Library" functions that can be "extern'd" from user code.
//===----------------------------------------------------------------------===//
@@ -2087,6 +2087,9 @@ double printd(double X) {
//===----------------------------------------------------------------------===//
int main() {
+ InitializeNativeTarget();
+ LLVMContext &Context = getGlobalContext();
+
// Install standard binary operators.
// 1 is lowest precedence.
BinopPrecedence['='] = 2;
@@ -2100,7 +2103,7 @@ int main() {
getNextToken();
// Make the module, which holds all the code.
- TheModule = new Module("my cool jit", getGlobalContext());
+ TheModule = new Module("my cool jit", Context);
ExistingModuleProvider *OurModuleProvider =
new ExistingModuleProvider(TheModule);
@@ -2113,6 +2116,8 @@ int main() {
// Set up the optimizer pipeline. Start with registering info about how the
// target lays out data structures.
OurFPM.add(new TargetData(*TheExecutionEngine->getTargetData()));
+ // Promote allocas to registers.
+ OurFPM.add(createPromoteMemoryToRegisterPass());
// Do simple "peephole" optimizations and bit-twiddling optzns.
OurFPM.add(createInstructionCombiningPass());
// Reassociate expressions.
@@ -2122,6 +2127,8 @@ int main() {
// Simplify the control flow graph (deleting unreachable blocks, etc).
OurFPM.add(createCFGSimplificationPass());
+ OurFPM.doInitialization();
+
// Set the global so the code gen can use this.
TheFPM = &OurFPM;
diff --git a/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl4.html b/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl4.html
index ec3c20b..238fc53 100644
--- a/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl4.html
+++ b/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl4.html
@@ -206,6 +206,8 @@ add a set of optimizations to run. The code looks like this:</p>
(* Simplify the control flow graph (deleting unreachable blocks, etc). *)
add_cfg_simplification the_fpm;
+ ignore (PassManager.initialize the_fpm);
+
(* Run the main "interpreter loop" now. *)
Toplevel.main_loop the_fpm the_execution_engine stream;
</pre>
@@ -960,6 +962,8 @@ open Llvm_target
open Llvm_scalar_opts
let main () =
+ ignore (initialize_native_target ());
+
(* Install standard binary operators.
* 1 is the lowest precedence. *)
Hashtbl.add Parser.binop_precedence '<' 10;
@@ -992,6 +996,8 @@ let main () =
(* Simplify the control flow graph (deleting unreachable blocks, etc). *)
add_cfg_simplification the_fpm;
+ ignore (PassManager.initialize the_fpm);
+
(* Run the main "interpreter loop" now. *)
Toplevel.main_loop the_fpm the_execution_engine stream;
diff --git a/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl5.html b/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl5.html
index 6c77e9f..f19e900 100644
--- a/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl5.html
+++ b/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl5.html
@@ -1487,6 +1487,8 @@ open Llvm_target
open Llvm_scalar_opts
let main () =
+ ignore (initialize_native_target ());
+
(* Install standard binary operators.
* 1 is the lowest precedence. *)
Hashtbl.add Parser.binop_precedence '<' 10;
@@ -1519,6 +1521,8 @@ let main () =
(* Simplify the control flow graph (deleting unreachable blocks, etc). *)
add_cfg_simplification the_fpm;
+ ignore (PassManager.initialize the_fpm);
+
(* Run the main "interpreter loop" now. *)
Toplevel.main_loop the_fpm the_execution_engine stream;
diff --git a/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl6.html b/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl6.html
index 8c6996f..2edb22e 100644
--- a/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl6.html
+++ b/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl6.html
@@ -1486,6 +1486,8 @@ open Llvm_target
open Llvm_scalar_opts
let main () =
+ ignore (initialize_native_target ());
+
(* Install standard binary operators.
* 1 is the lowest precedence. *)
Hashtbl.add Parser.binop_precedence '<' 10;
@@ -1518,6 +1520,8 @@ let main () =
(* Simplify the control flow graph (deleting unreachable blocks, etc). *)
add_cfg_simplification the_fpm;
+ ignore (PassManager.initialize the_fpm);
+
(* Run the main "interpreter loop" now. *)
Toplevel.main_loop the_fpm the_execution_engine stream;
diff --git a/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl7.html b/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl7.html
index dab3059..0776821 100644
--- a/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl7.html
+++ b/libclamav/c++/llvm/docs/tutorial/OCamlLangImpl7.html
@@ -1816,6 +1816,8 @@ open Llvm_target
open Llvm_scalar_opts
let main () =
+ ignore (initialize_native_target ());
+
(* Install standard binary operators.
* 1 is the lowest precedence. *)
Hashtbl.add Parser.binop_precedence '=' 2;
@@ -1852,6 +1854,8 @@ let main () =
(* Simplify the control flow graph (deleting unreachable blocks, etc). *)
add_cfg_simplification the_fpm;
+ ignore (PassManager.initialize the_fpm);
+
(* Run the main "interpreter loop" now. *)
Toplevel.main_loop the_fpm the_execution_engine stream;
diff --git a/libclamav/c++/llvm/include/llvm-c/Core.h b/libclamav/c++/llvm/include/llvm-c/Core.h
index 40696e0..a44afcd 100644
--- a/libclamav/c++/llvm/include/llvm-c/Core.h
+++ b/libclamav/c++/llvm/include/llvm-c/Core.h
@@ -736,6 +736,7 @@ LLVMValueRef LLVMBuildOr(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS,
LLVMValueRef LLVMBuildXor(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS,
const char *Name);
LLVMValueRef LLVMBuildNeg(LLVMBuilderRef, LLVMValueRef V, const char *Name);
+LLVMValueRef LLVMBuildFNeg(LLVMBuilderRef, LLVMValueRef V, const char *Name);
LLVMValueRef LLVMBuildNot(LLVMBuilderRef, LLVMValueRef V, const char *Name);
/* Memory */
diff --git a/libclamav/c++/llvm/include/llvm/ADT/APFloat.h b/libclamav/c++/llvm/include/llvm/ADT/APFloat.h
index d38d831..4d7e7ae 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/APFloat.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/APFloat.h
@@ -173,6 +173,7 @@ namespace llvm {
};
// Constructors.
+ APFloat(const fltSemantics &); // Default construct to 0.0
APFloat(const fltSemantics &, const StringRef &);
APFloat(const fltSemantics &, integerPart);
APFloat(const fltSemantics &, fltCategory, bool negative, unsigned type=0);
diff --git a/libclamav/c++/llvm/include/llvm/ADT/DenseMap.h b/libclamav/c++/llvm/include/llvm/ADT/DenseMap.h
index b220714..daeda28 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/DenseMap.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/DenseMap.h
@@ -17,10 +17,11 @@
#include "llvm/Support/PointerLikeTypeTraits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/ADT/DenseMapInfo.h"
+#include <iterator>
+#include <new>
+#include <utility>
#include <cassert>
#include <cstring>
-#include <utility>
-#include <new>
namespace llvm {
@@ -423,7 +424,9 @@ private:
};
template<typename KeyT, typename ValueT, typename KeyInfoT, typename ValueInfoT>
-class DenseMapIterator {
+class DenseMapIterator :
+ public std::iterator<std::forward_iterator_tag, std::pair<KeyT, ValueT>,
+ ptrdiff_t> {
typedef std::pair<KeyT, ValueT> BucketT;
protected:
const BucketT *Ptr, *End;
diff --git a/libclamav/c++/llvm/include/llvm/ADT/DenseMapInfo.h b/libclamav/c++/llvm/include/llvm/ADT/DenseMapInfo.h
index d76ebde..632728b 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/DenseMapInfo.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/DenseMapInfo.h
@@ -63,38 +63,38 @@ template<> struct DenseMapInfo<char> {
// Provide DenseMapInfo for unsigned ints.
template<> struct DenseMapInfo<unsigned> {
static inline unsigned getEmptyKey() { return ~0; }
- static inline unsigned getTombstoneKey() { return ~0 - 1; }
+ static inline unsigned getTombstoneKey() { return ~0U - 1; }
static unsigned getHashValue(const unsigned& Val) { return Val * 37; }
static bool isPod() { return true; }
static bool isEqual(const unsigned& LHS, const unsigned& RHS) {
- return LHS == RHS;
+ return LHS == RHS;
}
};
// Provide DenseMapInfo for unsigned longs.
template<> struct DenseMapInfo<unsigned long> {
- static inline unsigned long getEmptyKey() { return ~0L; }
- static inline unsigned long getTombstoneKey() { return ~0L - 1L; }
+ static inline unsigned long getEmptyKey() { return ~0UL; }
+ static inline unsigned long getTombstoneKey() { return ~0UL - 1L; }
static unsigned getHashValue(const unsigned long& Val) {
- return (unsigned)(Val * 37L);
+ return Val * 37UL;
}
static bool isPod() { return true; }
static bool isEqual(const unsigned long& LHS, const unsigned long& RHS) {
- return LHS == RHS;
+ return LHS == RHS;
}
};
// Provide DenseMapInfo for unsigned long longs.
template<> struct DenseMapInfo<unsigned long long> {
- static inline unsigned long long getEmptyKey() { return ~0LL; }
- static inline unsigned long long getTombstoneKey() { return ~0LL - 1LL; }
+ static inline unsigned long long getEmptyKey() { return ~0ULL; }
+ static inline unsigned long long getTombstoneKey() { return ~0ULL - 1ULL; }
static unsigned getHashValue(const unsigned long long& Val) {
- return (unsigned)(Val * 37LL);
+ return Val * 37ULL;
}
static bool isPod() { return true; }
static bool isEqual(const unsigned long long& LHS,
const unsigned long long& RHS) {
- return LHS == RHS;
+ return LHS == RHS;
}
};
diff --git a/libclamav/c++/llvm/include/llvm/ADT/EquivalenceClasses.h b/libclamav/c++/llvm/include/llvm/ADT/EquivalenceClasses.h
index bed99d3..ac9dd4d 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/EquivalenceClasses.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/EquivalenceClasses.h
@@ -234,8 +234,9 @@ public:
}
class member_iterator : public std::iterator<std::forward_iterator_tag,
- ElemTy, ptrdiff_t> {
- typedef std::iterator<std::forward_iterator_tag, ElemTy, ptrdiff_t> super;
+ const ElemTy, ptrdiff_t> {
+ typedef std::iterator<std::forward_iterator_tag,
+ const ElemTy, ptrdiff_t> super;
const ECValue *Node;
friend class EquivalenceClasses;
public:
@@ -249,7 +250,7 @@ public:
reference operator*() const {
assert(Node != 0 && "Dereferencing end()!");
- return const_cast<reference>(Node->getData()); // FIXME
+ return Node->getData();
}
reference operator->() const { return operator*(); }
diff --git a/libclamav/c++/llvm/include/llvm/ADT/FoldingSet.h b/libclamav/c++/llvm/include/llvm/ADT/FoldingSet.h
index 1465d04..c62c47d 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/FoldingSet.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/FoldingSet.h
@@ -18,7 +18,7 @@
#include "llvm/Support/DataTypes.h"
#include "llvm/ADT/SmallVector.h"
-#include <string>
+#include "llvm/ADT/StringRef.h"
#include <iterator>
namespace llvm {
@@ -227,9 +227,7 @@ public:
void AddInteger(long long I);
void AddInteger(unsigned long long I);
void AddBoolean(bool B) { AddInteger(B ? 1U : 0U); }
- void AddString(const char* String, const char* End);
- void AddString(const std::string &String);
- void AddString(const char* String);
+ void AddString(StringRef String);
template <typename T>
inline void Add(const T& x) { FoldingSetTrait<T>::Profile(x, *this); }
diff --git a/libclamav/c++/llvm/include/llvm/ADT/ImmutableMap.h b/libclamav/c++/llvm/include/llvm/ADT/ImmutableMap.h
index 52708bc..96bf012 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/ImmutableMap.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/ImmutableMap.h
@@ -90,12 +90,13 @@ public:
ImmutableMap GetEmptyMap() { return ImmutableMap(F.GetEmptyTree()); }
ImmutableMap Add(ImmutableMap Old, key_type_ref K, data_type_ref D) {
- return ImmutableMap(F.Add(Old.Root,
- std::make_pair<key_type,data_type>(K,D)));
+ TreeTy *T = F.Add(Old.Root, std::make_pair<key_type,data_type>(K,D));
+ return ImmutableMap(F.GetCanonicalTree(T));
}
ImmutableMap Remove(ImmutableMap Old, key_type_ref K) {
- return ImmutableMap(F.Remove(Old.Root,K));
+ TreeTy *T = F.Remove(Old.Root,K);
+ return ImmutableMap(F.GetCanonicalTree(T));
}
private:
diff --git a/libclamav/c++/llvm/include/llvm/ADT/ImmutableSet.h b/libclamav/c++/llvm/include/llvm/ADT/ImmutableSet.h
index 7c070d7..5aa1943 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/ImmutableSet.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/ImmutableSet.h
@@ -331,6 +331,7 @@ private:
uint32_t X = ComputeDigest(getLeft(), getRight(), getValue());
Digest = X;
+ MarkedCachedDigest();
return X;
}
};
@@ -430,58 +431,10 @@ private:
// returned to the caller.
//===--------------------------------------------------===//
- TreeTy* CreateNode(TreeTy* L, value_type_ref V, TreeTy* R) {
- // Search the FoldingSet bucket for a Tree with the same digest.
- FoldingSetNodeID ID;
- unsigned digest = TreeTy::ComputeDigest(L, R, V);
- ID.AddInteger(digest);
- unsigned hash = ID.ComputeHash();
-
- typename CacheTy::bucket_iterator I = Cache.bucket_begin(hash);
- typename CacheTy::bucket_iterator E = Cache.bucket_end(hash);
-
- for (; I != E; ++I) {
- TreeTy* T = &*I;
-
- if (T->ComputeDigest() != digest)
- continue;
-
- // We found a collision. Perform a comparison of Contents('T')
- // with Contents('L')+'V'+Contents('R').
- typename TreeTy::iterator TI = T->begin(), TE = T->end();
-
- // First compare Contents('L') with the (initial) contents of T.
- if (!CompareTreeWithSection(L, TI, TE))
- continue;
-
- // Now compare the new data element.
- if (TI == TE || !TI->ElementEqual(V))
- continue;
-
- ++TI;
-
- // Now compare the remainder of 'T' with 'R'.
- if (!CompareTreeWithSection(R, TI, TE))
- continue;
-
- if (TI != TE)
- continue; // Contents('R') did not match suffix of 'T'.
-
- // Trees did match! Return 'T'.
- return T;
- }
-
- // No tree with the contents: Contents('L')+'V'+Contents('R').
- // Create it. Allocate the new tree node and insert it into the cache.
+ TreeTy* CreateNode(TreeTy* L, value_type_ref V, TreeTy* R) {
BumpPtrAllocator& A = getAllocator();
TreeTy* T = (TreeTy*) A.Allocate<TreeTy>();
new (T) TreeTy(L,R,V,IncrementHeight(L,R));
-
- // We do not insert 'T' into the FoldingSet here. This is because
- // this tree is still mutable and things may get rebalanced.
- // Because our digest is associative and based on the contents of
- // the set, this should hopefully not cause any strange bugs.
- // 'T' is inserted by 'MarkImmutable'.
return T;
}
@@ -614,12 +567,56 @@ private:
T->MarkImmutable();
MarkImmutable(Left(T));
MarkImmutable(Right(T));
+ }
+
+public:
+ TreeTy *GetCanonicalTree(TreeTy *TNew) {
+ if (!TNew)
+ return NULL;
+
+ // Search the FoldingSet bucket for a Tree with the same digest.
+ FoldingSetNodeID ID;
+ unsigned digest = TNew->ComputeDigest();
+ ID.AddInteger(digest);
+ unsigned hash = ID.ComputeHash();
+
+ typename CacheTy::bucket_iterator I = Cache.bucket_begin(hash);
+ typename CacheTy::bucket_iterator E = Cache.bucket_end(hash);
+
+ for (; I != E; ++I) {
+ TreeTy *T = &*I;
+
+ if (T->ComputeDigest() != digest)
+ continue;
+
+ // We found a collision. Perform a comparison of Contents('T')
+ // with Contents('L')+'V'+Contents('R').
+ typename TreeTy::iterator TI = T->begin(), TE = T->end();
+
+ // First compare Contents('L') with the (initial) contents of T.
+ if (!CompareTreeWithSection(TNew->getLeft(), TI, TE))
+ continue;
+
+ // Now compare the new data element.
+ if (TI == TE || !TI->ElementEqual(TNew->getValue()))
+ continue;
+
+ ++TI;
+
+ // Now compare the remainder of 'T' with 'R'.
+ if (!CompareTreeWithSection(TNew->getRight(), TI, TE))
+ continue;
+
+ if (TI != TE)
+ continue; // Contents('R') did not match suffix of 'T'.
+
+ // Trees did match! Return 'T'.
+ return T;
+ }
- // Now that the node is immutable it can safely be inserted
- // into the node cache.
- llvm::FoldingSetNodeID ID;
- ID.AddInteger(T->ComputeDigest());
- Cache.InsertNode(T, (void*) &*Cache.bucket_end(ID.ComputeHash()));
+ // 'TNew' is the only tree of its kind. Return it.
+ Cache.InsertNode(TNew, (void*) &*Cache.bucket_end(hash));
+ return TNew;
}
};
@@ -939,8 +936,8 @@ public:
typedef ImutAVLTree<ValInfo> TreeTy;
private:
- TreeTy* Root;
-
+ TreeTy *Root;
+
public:
/// Constructs a set from a pointer to a tree root. In general one
/// should use a Factory object to create sets instead of directly
@@ -968,7 +965,7 @@ public:
/// The memory allocated to represent the set is released when the
/// factory object that created the set is destroyed.
ImmutableSet Add(ImmutableSet Old, value_type_ref V) {
- return ImmutableSet(F.Add(Old.Root,V));
+ return ImmutableSet(F.GetCanonicalTree(F.Add(Old.Root,V)));
}
/// Remove - Creates a new immutable set that contains all of the values
@@ -979,7 +976,7 @@ public:
/// The memory allocated to represent the set is released when the
/// factory object that created the set is destroyed.
ImmutableSet Remove(ImmutableSet Old, value_type_ref V) {
- return ImmutableSet(F.Remove(Old.Root,V));
+ return ImmutableSet(F.GetCanonicalTree(F.Remove(Old.Root,V)));
}
BumpPtrAllocator& getAllocator() { return F.getAllocator(); }
@@ -1004,7 +1001,9 @@ public:
return Root && RHS.Root ? Root->isNotEqual(*RHS.Root) : Root != RHS.Root;
}
- TreeTy* getRoot() const { return Root; }
+ TreeTy *getRoot() {
+ return Root;
+ }
/// isEmpty - Return true if the set contains no elements.
bool isEmpty() const { return !Root; }
diff --git a/libclamav/c++/llvm/include/llvm/ADT/IndexedMap.h b/libclamav/c++/llvm/include/llvm/ADT/IndexedMap.h
index ff5d3a1..89f0dfa 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/IndexedMap.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/IndexedMap.h
@@ -26,7 +26,7 @@
namespace llvm {
- struct IdentityFunctor : std::unary_function<unsigned, unsigned> {
+ struct IdentityFunctor : public std::unary_function<unsigned, unsigned> {
unsigned operator()(unsigned Index) const {
return Index;
}
diff --git a/libclamav/c++/llvm/include/llvm/ADT/PointerIntPair.h b/libclamav/c++/llvm/include/llvm/ADT/PointerIntPair.h
index 0aa478b..73ba3c7 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/PointerIntPair.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/PointerIntPair.h
@@ -65,7 +65,8 @@ public:
}
PointerTy getPointer() const {
- return reinterpret_cast<PointerTy>(Value & PointerBitMask);
+ return PtrTraits::getFromVoidPointer(
+ reinterpret_cast<void*>(Value & PointerBitMask));
}
IntType getInt() const {
@@ -73,7 +74,8 @@ public:
}
void setPointer(PointerTy Ptr) {
- intptr_t PtrVal = reinterpret_cast<intptr_t>(Ptr);
+ intptr_t PtrVal
+ = reinterpret_cast<intptr_t>(PtrTraits::getAsVoidPointer(Ptr));
assert((PtrVal & ((1 << PtrTraits::NumLowBitsAvailable)-1)) == 0 &&
"Pointer is not sufficiently aligned");
// Preserve all low bits, just update the pointer.
@@ -141,8 +143,7 @@ public:
return PointerIntPair<PointerTy, IntBits, IntType>::getFromOpaqueValue(P);
}
enum {
- NumLowBitsAvailable =
- PointerLikeTypeTraits<PointerTy>::NumLowBitsAvailable - IntBits
+ NumLowBitsAvailable = PtrTraits::NumLowBitsAvailable - IntBits
};
};
diff --git a/libclamav/c++/llvm/include/llvm/ADT/SCCIterator.h b/libclamav/c++/llvm/include/llvm/ADT/SCCIterator.h
index c0c6ba2..db985b5 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/SCCIterator.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/SCCIterator.h
@@ -22,7 +22,7 @@
#define LLVM_ADT_SCCITERATOR_H
#include "llvm/ADT/GraphTraits.h"
-#include <map>
+#include "llvm/ADT/DenseMap.h"
#include <vector>
namespace llvm {
@@ -48,7 +48,7 @@ class scc_iterator
// visitNum is the global counter.
// nodeVisitNumbers are per-node visit numbers, also used as DFS flags.
unsigned visitNum;
- std::map<NodeType *, unsigned> nodeVisitNumbers;
+ DenseMap<NodeType *, unsigned> nodeVisitNumbers;
// SCCNodeStack - Stack holding nodes of the SCC.
std::vector<NodeType *> SCCNodeStack;
diff --git a/libclamav/c++/llvm/include/llvm/ADT/SmallSet.h b/libclamav/c++/llvm/include/llvm/ADT/SmallSet.h
index caaa96c..d03f1be 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/SmallSet.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/SmallSet.h
@@ -30,7 +30,7 @@ namespace llvm {
template <typename T, unsigned N>
class SmallSet {
/// Use a SmallVector to hold the elements here (even though it will never
- /// reach it's 'large' stage) to avoid calling the default ctors of elements
+ /// reach its 'large' stage) to avoid calling the default ctors of elements
/// we will never use.
SmallVector<T, N> Vector;
std::set<T> Set;
diff --git a/libclamav/c++/llvm/include/llvm/ADT/SmallString.h b/libclamav/c++/llvm/include/llvm/ADT/SmallString.h
index d5856ac..0354625 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/SmallString.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/SmallString.h
@@ -16,8 +16,6 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
-#include "llvm/Support/DataTypes.h"
-#include <cstring>
namespace llvm {
@@ -40,6 +38,12 @@ public:
// Extra methods.
StringRef str() const { return StringRef(this->begin(), this->size()); }
+ const char *c_str() {
+ this->push_back(0);
+ this->pop_back();
+ return this->data();
+ }
+
// Extra operators.
const SmallString &operator=(StringRef RHS) {
this->clear();
@@ -56,7 +60,6 @@ public:
}
};
-
}
#endif
diff --git a/libclamav/c++/llvm/include/llvm/ADT/SparseBitVector.h b/libclamav/c++/llvm/include/llvm/ADT/SparseBitVector.h
index f5bf431..b7a6873 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/SparseBitVector.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/SparseBitVector.h
@@ -15,15 +15,14 @@
#ifndef LLVM_ADT_SPARSEBITVECTOR_H
#define LLVM_ADT_SPARSEBITVECTOR_H
-#include <cassert>
-#include <climits>
-#include <cstring>
-#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/ilist.h"
#include "llvm/ADT/ilist_node.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
+#include <cassert>
+#include <climits>
+#include <cstring>
namespace llvm {
@@ -43,7 +42,7 @@ namespace llvm {
template <unsigned ElementSize = 128>
struct SparseBitVectorElement
- : ilist_node<SparseBitVectorElement<ElementSize> > {
+ : public ilist_node<SparseBitVectorElement<ElementSize> > {
public:
typedef unsigned long BitWord;
enum {
diff --git a/libclamav/c++/llvm/include/llvm/ADT/StringRef.h b/libclamav/c++/llvm/include/llvm/ADT/StringRef.h
index acfc335..aa7d577 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/StringRef.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/StringRef.h
@@ -28,7 +28,8 @@ namespace llvm {
public:
typedef const char *iterator;
static const size_t npos = ~size_t(0);
-
+ typedef size_t size_type;
+
private:
/// The start of the string, in an external buffer.
const char *Data;
@@ -45,11 +46,11 @@ namespace llvm {
/// Construct a string ref from a cstring.
/*implicit*/ StringRef(const char *Str)
- : Data(Str), Length(::strlen(Str)) {}
+ : Data(Str) { if (Str) Length = ::strlen(Str); else Length = 0; }
/// Construct a string ref from a pointer and length.
- /*implicit*/ StringRef(const char *_Data, unsigned _Length)
- : Data(_Data), Length(_Length) {}
+ /*implicit*/ StringRef(const char *data, unsigned length)
+ : Data(data), Length(length) {}
/// Construct a string ref from an std::string.
/*implicit*/ StringRef(const std::string &Str)
@@ -147,7 +148,7 @@ namespace llvm {
/// @name String Searching
/// @{
- /// find - Search for the character \arg C in the string.
+ /// find - Search for the first character \arg C in the string.
///
/// \return - The index of the first occurence of \arg C, or npos if not
/// found.
@@ -158,20 +159,49 @@ namespace llvm {
return npos;
}
- /// find - Search for the string \arg Str in the string.
+ /// find - Search for the first string \arg Str in the string.
///
/// \return - The index of the first occurence of \arg Str, or npos if not
/// found.
- size_t find(const StringRef &Str) const {
- size_t N = Str.size();
- if (N > Length)
- return npos;
- for (size_t i = 0, e = Length - N + 1; i != e; ++i)
- if (substr(i, N).equals(Str))
+ size_t find(const StringRef &Str) const;
+
+ /// rfind - Search for the last character \arg C in the string.
+ ///
+ /// \return - The index of the last occurence of \arg C, or npos if not
+ /// found.
+ size_t rfind(char C, size_t From = npos) const {
+ From = std::min(From, Length);
+ size_t i = From;
+ while (i != 0) {
+ --i;
+ if (Data[i] == C)
return i;
+ }
return npos;
}
-
+
+ /// rfind - Search for the last string \arg Str in the string.
+ ///
+ /// \return - The index of the last occurence of \arg Str, or npos if not
+ /// found.
+ size_t rfind(const StringRef &Str) const;
+
+ /// find_first_of - Find the first instance of the specified character or
+ /// return npos if not in string. Same as find.
+ size_type find_first_of(char C) const { return find(C); }
+
+ /// find_first_of - Find the first character from the string 'Chars' in the
+ /// current string or return npos if not in string.
+ size_type find_first_of(StringRef Chars) const;
+
+ /// find_first_not_of - Find the first character in the string that is not
+ /// in the string 'Chars' or return npos if all are in string. Same as find.
+ size_type find_first_not_of(StringRef Chars) const;
+
+ /// @}
+ /// @name Helpful Algorithms
+ /// @{
+
/// count - Return the number of occurrences of \arg C in the string.
size_t count(char C) const {
size_t Count = 0;
@@ -180,20 +210,26 @@ namespace llvm {
++Count;
return Count;
}
-
+
/// count - Return the number of non-overlapped occurrences of \arg Str in
/// the string.
- size_t count(const StringRef &Str) const {
- size_t Count = 0;
- size_t N = Str.size();
- if (N > Length)
- return 0;
- for (size_t i = 0, e = Length - N + 1; i != e; ++i)
- if (substr(i, N).equals(Str))
- ++Count;
- return Count;
- }
+ size_t count(const StringRef &Str) const;
+
+ /// getAsInteger - Parse the current string as an integer of the specified
+ /// radix. If Radix is specified as zero, this does radix autosensing using
+ /// extended C rules: 0 is octal, 0x is hex, 0b is binary.
+ ///
+ /// If the string is invalid or if only a subset of the string is valid,
+ /// this returns true to signify the error. The string is considered
+ /// erroneous if empty.
+ ///
+ bool getAsInteger(unsigned Radix, long long &Result) const;
+ bool getAsInteger(unsigned Radix, unsigned long long &Result) const;
+ bool getAsInteger(unsigned Radix, int &Result) const;
+ bool getAsInteger(unsigned Radix, unsigned &Result) const;
+ // TODO: Provide overloads for int/unsigned that check for overflow.
+
/// @}
/// @name Substring Operations
/// @{
@@ -245,6 +281,23 @@ namespace llvm {
return std::make_pair(slice(0, Idx), slice(Idx+1, npos));
}
+ /// rsplit - Split into two substrings around the last occurence of a
+ /// separator character.
+ ///
+ /// If \arg Separator is in the string, then the result is a pair (LHS, RHS)
+ /// such that (*this == LHS + Separator + RHS) is true and RHS is
+ /// minimal. If \arg Separator is not in the string, then the result is a
+ /// pair (LHS, RHS) where (*this == LHS) and (RHS == "").
+ ///
+ /// \param Separator - The character to split on.
+ /// \return - The split substrings.
+ std::pair<StringRef, StringRef> rsplit(char Separator) const {
+ size_t Idx = rfind(Separator);
+ if (Idx == npos)
+ return std::make_pair(*this, StringRef());
+ return std::make_pair(slice(0, Idx), slice(Idx+1, npos));
+ }
+
/// @}
};
diff --git a/libclamav/c++/llvm/include/llvm/ADT/Triple.h b/libclamav/c++/llvm/include/llvm/ADT/Triple.h
index 03ecd70..89736bc 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/Triple.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/Triple.h
@@ -118,8 +118,8 @@ public:
/// @{
Triple() : Data(), Arch(InvalidArch) {}
- explicit Triple(const StringRef &Str) : Data(Str), Arch(InvalidArch) {}
- explicit Triple(const char *ArchStr, const char *VendorStr, const char *OSStr)
+ explicit Triple(StringRef Str) : Data(Str), Arch(InvalidArch) {}
+ explicit Triple(StringRef ArchStr, StringRef VendorStr, StringRef OSStr)
: Data(ArchStr), Arch(InvalidArch) {
Data += '-';
Data += VendorStr;
@@ -258,10 +258,19 @@ public:
/// getOSTypeName - Get the canonical name for the \arg Kind vendor.
static const char *getOSTypeName(OSType Kind);
+ /// @}
+ /// @name Static helpers for converting alternate architecture names.
+ /// @{
+
/// getArchTypeForLLVMName - The canonical type for the given LLVM
/// architecture name (e.g., "x86").
static ArchType getArchTypeForLLVMName(const StringRef &Str);
+ /// getArchTypeForDarwinArchName - Get the architecture type for a "Darwin"
+ /// architecture name, for example as accepted by "gcc -arch" (see also
+ /// arch(3)).
+ static ArchType getArchTypeForDarwinArchName(const StringRef &Str);
+
/// @}
};
diff --git a/libclamav/c++/llvm/include/llvm/ADT/ilist.h b/libclamav/c++/llvm/include/llvm/ADT/ilist.h
index 6e6f5d6..b3824a2 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/ilist.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/ilist.h
@@ -121,15 +121,15 @@ struct ilist_node_traits {
/// for all common operations.
///
template<typename NodeTy>
-struct ilist_default_traits : ilist_nextprev_traits<NodeTy>,
- ilist_sentinel_traits<NodeTy>,
- ilist_node_traits<NodeTy> {
+struct ilist_default_traits : public ilist_nextprev_traits<NodeTy>,
+ public ilist_sentinel_traits<NodeTy>,
+ public ilist_node_traits<NodeTy> {
};
// Template traits for intrusive list. By specializing this template class, you
// can change what next/prev fields are used to store the links...
template<typename NodeTy>
-struct ilist_traits : ilist_default_traits<NodeTy> {};
+struct ilist_traits : public ilist_default_traits<NodeTy> {};
// Const traits are the same as nonconst traits...
template<typename Ty>
diff --git a/libclamav/c++/llvm/include/llvm/ADT/ilist_node.h b/libclamav/c++/llvm/include/llvm/ADT/ilist_node.h
index c28169f..da25f95 100644
--- a/libclamav/c++/llvm/include/llvm/ADT/ilist_node.h
+++ b/libclamav/c++/llvm/include/llvm/ADT/ilist_node.h
@@ -40,7 +40,7 @@ struct ilist_nextprev_traits;
/// that use ilist_nextprev_traits or ilist_default_traits.
///
template<typename NodeTy>
-class ilist_node : ilist_half_node<NodeTy> {
+class ilist_node : private ilist_half_node<NodeTy> {
friend struct ilist_nextprev_traits<NodeTy>;
friend struct ilist_traits<NodeTy>;
NodeTy *Next;
diff --git a/libclamav/c++/llvm/include/llvm/AbstractTypeUser.h b/libclamav/c++/llvm/include/llvm/AbstractTypeUser.h
index c1216ba..b6cceb4 100644
--- a/libclamav/c++/llvm/include/llvm/AbstractTypeUser.h
+++ b/libclamav/c++/llvm/include/llvm/AbstractTypeUser.h
@@ -31,6 +31,7 @@
namespace llvm {
+class Value;
class Type;
class DerivedType;
template<typename T> struct simplify_type;
@@ -55,6 +56,12 @@ template<typename T> struct simplify_type;
class AbstractTypeUser {
protected:
virtual ~AbstractTypeUser(); // Derive from me
+
+ /// setType - It's normally not possible to change a Value's type in place,
+ /// but an AbstractTypeUser subclass that knows what its doing can be
+ /// permitted to do so with care.
+ void setType(Value *V, const Type *NewTy);
+
public:
/// refineAbstractType - The callback method invoked when an abstract type is
@@ -65,7 +72,7 @@ public:
const Type *NewTy) = 0;
/// The other case which AbstractTypeUsers must be aware of is when a type
- /// makes the transition from being abstract (where it has clients on it's
+ /// makes the transition from being abstract (where it has clients on its
/// AbstractTypeUsers list) to concrete (where it does not). This method
/// notifies ATU's when this occurs for a type.
///
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/CallGraph.h b/libclamav/c++/llvm/include/llvm/Analysis/CallGraph.h
index 0e997ca..bcb6dee 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/CallGraph.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/CallGraph.h
@@ -55,6 +55,7 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/Pass.h"
#include "llvm/Support/CallSite.h"
+#include "llvm/Support/ValueHandle.h"
#include "llvm/System/IncludeFile.h"
#include <map>
@@ -158,11 +159,16 @@ protected:
};
//===----------------------------------------------------------------------===//
-// CallGraphNode class definition
+// CallGraphNode class definition.
//
class CallGraphNode {
- Function *F;
- typedef std::pair<CallSite,CallGraphNode*> CallRecord;
+ AssertingVH<Function> F;
+
+ // CallRecord - This is a pair of the calling instruction (a call or invoke)
+ // and the callgraph node being called.
+public:
+ typedef std::pair<WeakVH, CallGraphNode*> CallRecord;
+private:
std::vector<CallRecord> CalledFunctions;
/// NumReferences - This is the number of times that this CallGraphNode occurs
@@ -240,19 +246,22 @@ public:
/// addCalledFunction - Add a function to the list of functions called by this
/// one.
void addCalledFunction(CallSite CS, CallGraphNode *M) {
- CalledFunctions.push_back(std::make_pair(CS, M));
+ CalledFunctions.push_back(std::make_pair(CS.getInstruction(), M));
M->AddRef();
}
+ void removeCallEdge(iterator I) {
+ I->second->DropRef();
+ *I = CalledFunctions.back();
+ CalledFunctions.pop_back();
+ }
+
+
/// removeCallEdgeFor - This method removes the edge in the node for the
/// specified call site. Note that this method takes linear time, so it
/// should be used sparingly.
void removeCallEdgeFor(CallSite CS);
- // FIXME: REMOVE THIS WHEN HACK IS REMOVED FROM CGSCCPASSMGR.
- void removeCallEdgeFor(Instruction *CS);
-
-
/// removeAnyCallEdgeTo - This method removes all call edges from this node
/// to the specified callee function. This takes more time to execute than
/// removeCallEdgeTo, so it should not be used unless necessary.
@@ -261,11 +270,12 @@ public:
/// removeOneAbstractEdgeTo - Remove one edge associated with a null callsite
/// from this node to the specified callee function.
void removeOneAbstractEdgeTo(CallGraphNode *Callee);
-
- /// replaceCallSite - Make the edge in the node for Old CallSite be for
- /// New CallSite instead. Note that this method takes linear time, so it
- /// should be used sparingly.
- void replaceCallSite(CallSite Old, CallSite New, CallGraphNode *NewCallee);
+
+ /// replaceCallEdge - This method replaces the edge in the node for the
+ /// specified call site with a new one. Note that this method takes linear
+ /// time, so it should be used sparingly.
+ void replaceCallEdge(CallSite CS, CallSite NewCS, CallGraphNode *NewNode);
+
};
//===----------------------------------------------------------------------===//
@@ -278,7 +288,7 @@ public:
template <> struct GraphTraits<CallGraphNode*> {
typedef CallGraphNode NodeType;
- typedef std::pair<CallSite, CallGraphNode*> CGNPairTy;
+ typedef CallGraphNode::CallRecord CGNPairTy;
typedef std::pointer_to_unary_function<CGNPairTy, CallGraphNode*> CGNDerefFun;
static NodeType *getEntryNode(CallGraphNode *CGN) { return CGN; }
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/ConstantFolding.h b/libclamav/c++/llvm/include/llvm/Analysis/ConstantFolding.h
index 3e393ff..263d42a 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/ConstantFolding.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/ConstantFolding.h
@@ -1,4 +1,4 @@
-//===-- ConstantFolding.h - Analyze constant folding possibilities --------===//
+//===-- ConstantFolding.h - Fold instructions into constants --------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,8 +7,12 @@
//
//===----------------------------------------------------------------------===//
//
-// This family of functions determines the possibility of performing constant
-// folding.
+// This file declares routines for folding instructions into constants.
+//
+// Also, to supplement the basic VMCore ConstantExpr simplifications,
+// this file declares some additional folding routines that can make use of
+// TargetData information. These functions cannot go in VMCore due to library
+// dependency issues.
//
//===----------------------------------------------------------------------===//
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/DebugInfo.h b/libclamav/c++/llvm/include/llvm/Analysis/DebugInfo.h
index 489c273..53c5120 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/DebugInfo.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/DebugInfo.h
@@ -24,6 +24,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/Support/Dwarf.h"
+#include "llvm/Support/ValueHandle.h"
namespace llvm {
class BasicBlock;
@@ -44,15 +45,15 @@ namespace llvm {
class LLVMContext;
class DIDescriptor {
- protected:
- MDNode *DbgNode;
+ protected:
+ TrackingVH<MDNode> DbgNode;
/// DIDescriptor constructor. If the specified node is non-null, check
/// to make sure that the tag in the descriptor matches 'RequiredTag'. If
/// not, the debug info is corrupt and we ignore it.
DIDescriptor(MDNode *N, unsigned RequiredTag);
- const std::string &getStringField(unsigned Elt, std::string &Result) const;
+ const char *getStringField(unsigned Elt) const;
unsigned getUnsignedField(unsigned Elt) const {
return (unsigned)getUInt64Field(Elt);
}
@@ -87,6 +88,20 @@ namespace llvm {
/// dump - print descriptor.
void dump() const;
+
+ bool isDerivedType() const;
+ bool isCompositeType() const;
+ bool isBasicType() const;
+ bool isVariable() const;
+ bool isSubprogram() const;
+ bool isGlobalVariable() const;
+ bool isScope() const;
+ bool isCompileUnit() const;
+ bool isLexicalBlock() const;
+ bool isSubrange() const;
+ bool isEnumerator() const;
+ bool isType() const;
+ bool isGlobal() const;
};
/// DISubrange - This is used to represent ranges, for array bounds.
@@ -102,7 +117,7 @@ namespace llvm {
/// DIArray - This descriptor holds an array of descriptors.
class DIArray : public DIDescriptor {
public:
- explicit DIArray(MDNode *N = 0)
+ explicit DIArray(MDNode *N = 0)
: DIDescriptor(N) {}
unsigned getNumElements() const;
@@ -111,37 +126,44 @@ namespace llvm {
}
};
+ /// DIScope - A base class for various scopes.
+ class DIScope : public DIDescriptor {
+ public:
+ explicit DIScope(MDNode *N = 0) : DIDescriptor (N) {
+ if (DbgNode && !isScope())
+ DbgNode = 0;
+ }
+ virtual ~DIScope() {}
+
+ const char *getFilename() const;
+ const char *getDirectory() const;
+ };
+
/// DICompileUnit - A wrapper for a compile unit.
- class DICompileUnit : public DIDescriptor {
+ class DICompileUnit : public DIScope {
public:
- explicit DICompileUnit(MDNode *N = 0)
- : DIDescriptor(N, dwarf::DW_TAG_compile_unit) {}
+ explicit DICompileUnit(MDNode *N = 0) : DIScope(N) {
+ if (DbgNode && !isCompileUnit())
+ DbgNode = 0;
+ }
unsigned getLanguage() const { return getUnsignedField(2); }
- const std::string &getFilename(std::string &F) const {
- return getStringField(3, F);
- }
- const std::string &getDirectory(std::string &F) const {
- return getStringField(4, F);
- }
- const std::string &getProducer(std::string &F) const {
- return getStringField(5, F);
- }
-
+ const char *getFilename() const { return getStringField(3); }
+ const char *getDirectory() const { return getStringField(4); }
+ const char *getProducer() const { return getStringField(5); }
+
/// isMain - Each input file is encoded as a separate compile unit in LLVM
/// debugging information output. However, many target specific tool chains
- /// prefer to encode only one compile unit in an object file. In this
+ /// prefer to encode only one compile unit in an object file. In this
/// situation, the LLVM code generator will include debugging information
- /// entities in the compile unit that is marked as main compile unit. The
+ /// entities in the compile unit that is marked as main compile unit. The
/// code generator accepts maximum one main compile unit per module. If a
- /// module does not contain any main compile unit then the code generator
+ /// module does not contain any main compile unit then the code generator
/// will emit multiple compile units in the output object file.
bool isMain() const { return getUnsignedField(6); }
bool isOptimized() const { return getUnsignedField(7); }
- const std::string &getFlags(std::string &F) const {
- return getStringField(8, F);
- }
+ const char *getFlags() const { return getStringField(8); }
unsigned getRunTimeVersion() const { return getUnsignedField(9); }
/// Verify - Verify that a compile unit is well formed.
@@ -159,10 +181,8 @@ namespace llvm {
explicit DIEnumerator(MDNode *N = 0)
: DIDescriptor(N, dwarf::DW_TAG_enumerator) {}
- const std::string &getName(std::string &F) const {
- return getStringField(1, F);
- }
- uint64_t getEnumValue() const { return getUInt64Field(2); }
+ const char *getName() const { return getStringField(1); }
+ uint64_t getEnumValue() const { return getUInt64Field(2); }
};
/// DIType - This is a wrapper for a type.
@@ -171,33 +191,21 @@ namespace llvm {
class DIType : public DIDescriptor {
public:
enum {
- FlagPrivate = 1 << 0,
- FlagProtected = 1 << 1,
- FlagFwdDecl = 1 << 2,
- FlagAppleBlock = 1 << 3
+ FlagPrivate = 1 << 0,
+ FlagProtected = 1 << 1,
+ FlagFwdDecl = 1 << 2,
+ FlagAppleBlock = 1 << 3,
+ FlagBlockByrefStruct = 1 << 4
};
protected:
- DIType(MDNode *N, unsigned Tag)
+ DIType(MDNode *N, unsigned Tag)
: DIDescriptor(N, Tag) {}
// This ctor is used when the Tag has already been validated by a derived
// ctor.
DIType(MDNode *N, bool, bool) : DIDescriptor(N) {}
public:
- /// isDerivedType - Return true if the specified tag is legal for
- /// DIDerivedType.
- static bool isDerivedType(unsigned TAG);
-
- /// isCompositeType - Return true if the specified tag is legal for
- /// DICompositeType.
- static bool isCompositeType(unsigned TAG);
-
- /// isBasicType - Return true if the specified tag is legal for
- /// DIBasicType.
- static bool isBasicType(unsigned TAG) {
- return TAG == dwarf::DW_TAG_base_type;
- }
/// Verify - Verify that a type descriptor is well formed.
bool Verify() const;
@@ -207,9 +215,7 @@ namespace llvm {
virtual ~DIType() {}
DIDescriptor getContext() const { return getDescriptorField(1); }
- const std::string &getName(std::string &F) const {
- return getStringField(2, F);
- }
+ const char *getName() const { return getStringField(2); }
DICompileUnit getCompileUnit() const{ return getFieldAs<DICompileUnit>(3); }
unsigned getLineNumber() const { return getUnsignedField(4); }
uint64_t getSizeInBits() const { return getUInt64Field(5); }
@@ -219,17 +225,20 @@ namespace llvm {
uint64_t getOffsetInBits() const { return getUInt64Field(7); }
unsigned getFlags() const { return getUnsignedField(8); }
bool isPrivate() const {
- return (getFlags() & FlagPrivate) != 0;
+ return (getFlags() & FlagPrivate) != 0;
}
bool isProtected() const {
- return (getFlags() & FlagProtected) != 0;
+ return (getFlags() & FlagProtected) != 0;
}
bool isForwardDecl() const {
- return (getFlags() & FlagFwdDecl) != 0;
+ return (getFlags() & FlagFwdDecl) != 0;
}
// isAppleBlock - Return true if this is the Apple Blocks extension.
bool isAppleBlockExtension() const {
- return (getFlags() & FlagAppleBlock) != 0;
+ return (getFlags() & FlagAppleBlock) != 0;
+ }
+ bool isBlockByrefStruct() const {
+ return (getFlags() & FlagBlockByrefStruct) != 0;
}
/// dump - print type.
@@ -257,7 +266,7 @@ namespace llvm {
public:
explicit DIDerivedType(MDNode *N = 0)
: DIType(N, true, true) {
- if (DbgNode && !isDerivedType(getTag()))
+ if (DbgNode && !isDerivedType())
DbgNode = 0;
}
@@ -282,7 +291,7 @@ namespace llvm {
public:
explicit DICompositeType(MDNode *N = 0)
: DIDerivedType(N, true, true) {
- if (N && !isCompositeType(getTag()))
+ if (N && !isCompositeType())
DbgNode = 0;
}
@@ -302,31 +311,13 @@ namespace llvm {
explicit DIGlobal(MDNode *N, unsigned RequiredTag)
: DIDescriptor(N, RequiredTag) {}
- /// isSubprogram - Return true if the specified tag is legal for
- /// DISubprogram.
- static bool isSubprogram(unsigned TAG) {
- return TAG == dwarf::DW_TAG_subprogram;
- }
-
- /// isGlobalVariable - Return true if the specified tag is legal for
- /// DIGlobalVariable.
- static bool isGlobalVariable(unsigned TAG) {
- return TAG == dwarf::DW_TAG_variable;
- }
-
public:
virtual ~DIGlobal() {}
DIDescriptor getContext() const { return getDescriptorField(2); }
- const std::string &getName(std::string &F) const {
- return getStringField(3, F);
- }
- const std::string &getDisplayName(std::string &F) const {
- return getStringField(4, F);
- }
- const std::string &getLinkageName(std::string &F) const {
- return getStringField(5, F);
- }
+ const char *getName() const { return getStringField(3); }
+ const char *getDisplayName() const { return getStringField(4); }
+ const char *getLinkageName() const { return getStringField(5); }
DICompileUnit getCompileUnit() const{ return getFieldAs<DICompileUnit>(6); }
unsigned getLineNumber() const { return getUnsignedField(7); }
DIType getType() const { return getFieldAs<DIType>(8); }
@@ -341,26 +332,41 @@ namespace llvm {
};
/// DISubprogram - This is a wrapper for a subprogram (e.g. a function).
- class DISubprogram : public DIGlobal {
+ class DISubprogram : public DIScope {
public:
- explicit DISubprogram(MDNode *N = 0)
- : DIGlobal(N, dwarf::DW_TAG_subprogram) {}
+ explicit DISubprogram(MDNode *N = 0) : DIScope(N) {
+ if (DbgNode && !isSubprogram())
+ DbgNode = 0;
+ }
+ DIDescriptor getContext() const { return getDescriptorField(2); }
+ const char *getName() const { return getStringField(3); }
+ const char *getDisplayName() const { return getStringField(4); }
+ const char *getLinkageName() const { return getStringField(5); }
+ DICompileUnit getCompileUnit() const{ return getFieldAs<DICompileUnit>(6); }
+ unsigned getLineNumber() const { return getUnsignedField(7); }
DICompositeType getType() const { return getFieldAs<DICompositeType>(8); }
/// getReturnTypeName - Subprogram return types are encoded either as
/// DIType or as DICompositeType.
- const std::string &getReturnTypeName(std::string &F) const {
+ const char *getReturnTypeName() const {
DICompositeType DCT(getFieldAs<DICompositeType>(8));
if (!DCT.isNull()) {
DIArray A = DCT.getTypeArray();
DIType T(A.getElement(0).getNode());
- return T.getName(F);
+ return T.getName();
}
DIType T(getFieldAs<DIType>(8));
- return T.getName(F);
+ return T.getName();
}
+ /// isLocalToUnit - Return true if this subprogram is local to the current
+ /// compile unit, like 'static' in C.
+ unsigned isLocalToUnit() const { return getUnsignedField(9); }
+ unsigned isDefinition() const { return getUnsignedField(10); }
+ const char *getFilename() const { return getCompileUnit().getFilename();}
+ const char *getDirectory() const { return getCompileUnit().getDirectory();}
+
/// Verify - Verify that a subprogram descriptor is well formed.
bool Verify() const;
@@ -393,35 +399,65 @@ namespace llvm {
public:
explicit DIVariable(MDNode *N = 0)
: DIDescriptor(N) {
- if (DbgNode && !isVariable(getTag()))
+ if (DbgNode && !isVariable())
DbgNode = 0;
}
DIDescriptor getContext() const { return getDescriptorField(1); }
- const std::string &getName(std::string &F) const {
- return getStringField(2, F);
- }
+ const char *getName() const { return getStringField(2); }
DICompileUnit getCompileUnit() const{ return getFieldAs<DICompileUnit>(3); }
unsigned getLineNumber() const { return getUnsignedField(4); }
DIType getType() const { return getFieldAs<DIType>(5); }
- /// isVariable - Return true if the specified tag is legal for DIVariable.
- static bool isVariable(unsigned Tag);
/// Verify - Verify that a variable descriptor is well formed.
bool Verify() const;
+ /// HasComplexAddr - Return true if the variable has a complex address.
+ bool hasComplexAddress() const {
+ return getNumAddrElements() > 0;
+ }
+
+ unsigned getNumAddrElements() const { return DbgNode->getNumElements()-6; }
+
+ uint64_t getAddrElement(unsigned Idx) const {
+ return getUInt64Field(Idx+6);
+ }
+
+ /// isBlockByrefVariable - Return true if the variable was declared as
+ /// a "__block" variable (Apple Blocks).
+ bool isBlockByrefVariable() const {
+ return getType().isBlockByrefStruct();
+ }
+
/// dump - print variable.
void dump() const;
};
- /// DIBlock - This is a wrapper for a block (e.g. a function, scope, etc).
- class DIBlock : public DIDescriptor {
+ /// DILexicalBlock - This is a wrapper for a lexical block.
+ class DILexicalBlock : public DIScope {
public:
- explicit DIBlock(MDNode *N = 0)
- : DIDescriptor(N, dwarf::DW_TAG_lexical_block) {}
+ explicit DILexicalBlock(MDNode *N = 0) : DIScope(N) {
+ if (DbgNode && !isLexicalBlock())
+ DbgNode = 0;
+ }
+ DIScope getContext() const { return getFieldAs<DIScope>(1); }
+ const char *getDirectory() const { return getContext().getDirectory(); }
+ const char *getFilename() const { return getContext().getFilename(); }
+ };
- DIDescriptor getContext() const { return getDescriptorField(1); }
+ /// DILocation - This object holds location information. This object
+ /// is not associated with any DWARF tag.
+ class DILocation : public DIDescriptor {
+ public:
+ explicit DILocation(MDNode *N) : DIDescriptor(N) { ; }
+
+ unsigned getLineNumber() const { return getUnsignedField(0); }
+ unsigned getColumnNumber() const { return getUnsignedField(1); }
+ DIScope getScope() const { return getFieldAs<DIScope>(2); }
+ DILocation getOrigLocation() const { return getFieldAs<DILocation>(3); }
+ const char *getFilename() const { return getScope().getFilename(); }
+ const char *getDirectory() const { return getScope().getDirectory(); }
};
/// DIFactory - This object assists with the construction of the various
@@ -429,7 +465,7 @@ namespace llvm {
class DIFactory {
Module &M;
LLVMContext& VMContext;
-
+
// Cached values for uniquing and faster lookups.
const Type *EmptyStructPtr; // "{}*".
Function *StopPointFn; // llvm.dbg.stoppoint
@@ -443,9 +479,11 @@ namespace llvm {
DIFactory(const DIFactory &); // DO NOT IMPLEMENT
void operator=(const DIFactory&); // DO NOT IMPLEMENT
public:
+ enum ComplexAddrKind { OpPlus=1, OpDeref };
+
explicit DIFactory(Module &m);
- /// GetOrCreateArray - Create an descriptor for an array of descriptors.
+ /// GetOrCreateArray - Create an descriptor for an array of descriptors.
/// This implicitly uniques the arrays created.
DIArray GetOrCreateArray(DIDescriptor *Tys, unsigned NumTys);
@@ -456,19 +494,19 @@ namespace llvm {
/// CreateCompileUnit - Create a new descriptor for the specified compile
/// unit.
DICompileUnit CreateCompileUnit(unsigned LangID,
- const std::string &Filename,
- const std::string &Directory,
- const std::string &Producer,
+ StringRef Filenae,
+ StringRef Directory,
+ StringRef Producer,
bool isMain = false,
bool isOptimized = false,
const char *Flags = "",
unsigned RunTimeVer = 0);
/// CreateEnumerator - Create a single enumerator value.
- DIEnumerator CreateEnumerator(const std::string &Name, uint64_t Val);
+ DIEnumerator CreateEnumerator(StringRef Name, uint64_t Val);
/// CreateBasicType - Create a basic type like int, float, etc.
- DIBasicType CreateBasicType(DIDescriptor Context, const std::string &Name,
+ DIBasicType CreateBasicType(DIDescriptor Context, StringRef Name,
DICompileUnit CompileUnit, unsigned LineNumber,
uint64_t SizeInBits, uint64_t AlignInBits,
uint64_t OffsetInBits, unsigned Flags,
@@ -477,7 +515,7 @@ namespace llvm {
/// CreateDerivedType - Create a derived type like const qualified type,
/// pointer, typedef, etc.
DIDerivedType CreateDerivedType(unsigned Tag, DIDescriptor Context,
- const std::string &Name,
+ StringRef Name,
DICompileUnit CompileUnit,
unsigned LineNumber,
uint64_t SizeInBits, uint64_t AlignInBits,
@@ -486,7 +524,7 @@ namespace llvm {
/// CreateCompositeType - Create a composite type like array, struct, etc.
DICompositeType CreateCompositeType(unsigned Tag, DIDescriptor Context,
- const std::string &Name,
+ StringRef Name,
DICompileUnit CompileUnit,
unsigned LineNumber,
uint64_t SizeInBits,
@@ -498,31 +536,43 @@ namespace llvm {
/// CreateSubprogram - Create a new descriptor for the specified subprogram.
/// See comments in DISubprogram for descriptions of these fields.
- DISubprogram CreateSubprogram(DIDescriptor Context, const std::string &Name,
- const std::string &DisplayName,
- const std::string &LinkageName,
+ DISubprogram CreateSubprogram(DIDescriptor Context, StringRef Name,
+ StringRef DisplayName,
+ StringRef LinkageName,
DICompileUnit CompileUnit, unsigned LineNo,
DIType Type, bool isLocalToUnit,
bool isDefinition);
/// CreateGlobalVariable - Create a new descriptor for the specified global.
DIGlobalVariable
- CreateGlobalVariable(DIDescriptor Context, const std::string &Name,
- const std::string &DisplayName,
- const std::string &LinkageName,
+ CreateGlobalVariable(DIDescriptor Context, StringRef Name,
+ StringRef DisplayName,
+ StringRef LinkageName,
DICompileUnit CompileUnit,
unsigned LineNo, DIType Type, bool isLocalToUnit,
bool isDefinition, llvm::GlobalVariable *GV);
/// CreateVariable - Create a new descriptor for the specified variable.
DIVariable CreateVariable(unsigned Tag, DIDescriptor Context,
- const std::string &Name,
+ StringRef Name,
DICompileUnit CompileUnit, unsigned LineNo,
DIType Type);
- /// CreateBlock - This creates a descriptor for a lexical block with the
- /// specified parent context.
- DIBlock CreateBlock(DIDescriptor Context);
+ /// CreateComplexVariable - Create a new descriptor for the specified
+ /// variable which has a complex address expression for its address.
+ DIVariable CreateComplexVariable(unsigned Tag, DIDescriptor Context,
+ const std::string &Name,
+ DICompileUnit CompileUnit, unsigned LineNo,
+ DIType Type,
+ SmallVector<Value *, 9> &addr);
+
+ /// CreateLexicalBlock - This creates a descriptor for a lexical block
+ /// with the specified parent context.
+ DILexicalBlock CreateLexicalBlock(DIDescriptor Context);
+
+ /// CreateLocation - Creates a debug info location.
+ DILocation CreateLocation(unsigned LineNo, unsigned ColumnNo,
+ DIScope S, DILocation OrigLoc);
/// InsertStopPoint - Create a new llvm.dbg.stoppoint intrinsic invocation,
/// inserting it at the end of the specified basic block.
@@ -542,17 +592,22 @@ namespace llvm {
void InsertRegionEnd(DIDescriptor D, BasicBlock *BB);
/// InsertDeclare - Insert a new llvm.dbg.declare intrinsic call.
- void InsertDeclare(llvm::Value *Storage, DIVariable D, BasicBlock *BB);
+ void InsertDeclare(llvm::Value *Storage, DIVariable D,
+ BasicBlock *InsertAtEnd);
+
+ /// InsertDeclare - Insert a new llvm.dbg.declare intrinsic call.
+ void InsertDeclare(llvm::Value *Storage, DIVariable D,
+ Instruction *InsertBefore);
private:
Constant *GetTagConstant(unsigned TAG);
};
/// Finds the stoppoint coressponding to this instruction, that is the
- /// stoppoint that dominates this instruction
+ /// stoppoint that dominates this instruction
const DbgStopPointInst *findStopPoint(const Instruction *Inst);
- /// Finds the stoppoint corresponding to first real (non-debug intrinsic)
+ /// Finds the stoppoint corresponding to first real (non-debug intrinsic)
/// instruction in this Basic Block, and returns the stoppoint for it.
const DbgStopPointInst *findBBStopPoint(const BasicBlock *BB);
@@ -563,41 +618,46 @@ namespace llvm {
/// Find the debug info descriptor corresponding to this global variable.
Value *findDbgGlobalDeclare(GlobalVariable *V);
- bool getLocationInfo(const Value *V, std::string &DisplayName,
- std::string &Type, unsigned &LineNo, std::string &File,
- std::string &Dir);
+bool getLocationInfo(const Value *V, std::string &DisplayName,
+ std::string &Type, unsigned &LineNo, std::string &File,
+ std::string &Dir);
- /// isValidDebugInfoIntrinsic - Return true if SPI is a valid debug
+ /// isValidDebugInfoIntrinsic - Return true if SPI is a valid debug
/// info intrinsic.
- bool isValidDebugInfoIntrinsic(DbgStopPointInst &SPI,
+ bool isValidDebugInfoIntrinsic(DbgStopPointInst &SPI,
CodeGenOpt::Level OptLev);
- /// isValidDebugInfoIntrinsic - Return true if FSI is a valid debug
+ /// isValidDebugInfoIntrinsic - Return true if FSI is a valid debug
/// info intrinsic.
bool isValidDebugInfoIntrinsic(DbgFuncStartInst &FSI,
CodeGenOpt::Level OptLev);
- /// isValidDebugInfoIntrinsic - Return true if RSI is a valid debug
+ /// isValidDebugInfoIntrinsic - Return true if RSI is a valid debug
/// info intrinsic.
bool isValidDebugInfoIntrinsic(DbgRegionStartInst &RSI,
CodeGenOpt::Level OptLev);
- /// isValidDebugInfoIntrinsic - Return true if REI is a valid debug
+ /// isValidDebugInfoIntrinsic - Return true if REI is a valid debug
/// info intrinsic.
bool isValidDebugInfoIntrinsic(DbgRegionEndInst &REI,
CodeGenOpt::Level OptLev);
- /// isValidDebugInfoIntrinsic - Return true if DI is a valid debug
+ /// isValidDebugInfoIntrinsic - Return true if DI is a valid debug
/// info intrinsic.
bool isValidDebugInfoIntrinsic(DbgDeclareInst &DI,
CodeGenOpt::Level OptLev);
- /// ExtractDebugLocation - Extract debug location information
+ /// ExtractDebugLocation - Extract debug location information
/// from llvm.dbg.stoppoint intrinsic.
DebugLoc ExtractDebugLocation(DbgStopPointInst &SPI,
DebugLocTracker &DebugLocInfo);
- /// ExtractDebugLocation - Extract debug location information
+ /// ExtractDebugLocation - Extract debug location information
+ /// from DILocation.
+ DebugLoc ExtractDebugLocation(DILocation &Loc,
+ DebugLocTracker &DebugLocInfo);
+
+ /// ExtractDebugLocation - Extract debug location information
/// from llvm.dbg.func_start intrinsic.
DebugLoc ExtractDebugLocation(DbgFuncStartInst &FSI,
DebugLocTracker &DebugLocInfo);
@@ -614,7 +674,7 @@ namespace llvm {
/// processModule - Process entire module and collect debug info
/// anchors.
void processModule(Module &M);
-
+
private:
/// processType - Process DIType.
void processType(DIType DT);
@@ -639,7 +699,7 @@ namespace llvm {
/// addCompileUnit - Add compile unit into CUs.
bool addCompileUnit(DICompileUnit CU);
-
+
/// addGlobalVariable - Add global variable into GVs.
bool addGlobalVariable(DIGlobalVariable DIG);
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/Dominators.h b/libclamav/c++/llvm/include/llvm/Analysis/Dominators.h
index 7622326..f63e31c 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/Dominators.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/Dominators.h
@@ -404,11 +404,15 @@ public:
return dominatedBySlowTreeWalk(A, B);
}
- inline bool dominates(NodeT *A, NodeT *B) {
+ inline bool dominates(const NodeT *A, const NodeT *B) {
if (A == B)
return true;
- return dominates(getNode(A), getNode(B));
+ // Cast away the const qualifiers here. This is ok since
+ // this function doesn't actually return the values returned
+ // from getNode.
+ return dominates(getNode(const_cast<NodeT *>(A)),
+ getNode(const_cast<NodeT *>(B)));
}
NodeT *getRoot() const {
@@ -544,7 +548,9 @@ public:
o << "DFSNumbers invalid: " << SlowQueries << " slow queries.";
o << "\n";
- PrintDomTree<NodeT>(getRootNode(), o, 1);
+ // The postdom tree can have a null root if there are no returns.
+ if (getRootNode())
+ PrintDomTree<NodeT>(getRootNode(), o, 1);
}
protected:
@@ -728,6 +734,8 @@ public:
virtual bool runOnFunction(Function &F);
+ virtual void verifyAnalysis() const;
+
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
}
@@ -736,40 +744,19 @@ public:
return DT->dominates(A, B);
}
- inline bool dominates(BasicBlock* A, BasicBlock* B) const {
+ inline bool dominates(const BasicBlock* A, const BasicBlock* B) const {
return DT->dominates(A, B);
}
// dominates - Return true if A dominates B. This performs the
// special checks necessary if A and B are in the same basic block.
- bool dominates(Instruction *A, Instruction *B) const {
- BasicBlock *BBA = A->getParent(), *BBB = B->getParent();
- if (BBA != BBB) return DT->dominates(BBA, BBB);
-
- // It is not possible to determine dominance between two PHI nodes
- // based on their ordering.
- if (isa<PHINode>(A) && isa<PHINode>(B))
- return false;
-
- // Loop through the basic block until we find A or B.
- BasicBlock::iterator I = BBA->begin();
- for (; &*I != A && &*I != B; ++I) /*empty*/;
+ bool dominates(const Instruction *A, const Instruction *B) const;
- //if(!DT.IsPostDominators) {
- // A dominates B if it is found first in the basic block.
- return &*I == A;
- //} else {
- // // A post-dominates B if B is found first in the basic block.
- // return &*I == B;
- //}
- }
-
- inline bool properlyDominates(const DomTreeNode* A,
- const DomTreeNode* B) const {
+ bool properlyDominates(const DomTreeNode *A, const DomTreeNode *B) const {
return DT->properlyDominates(A, B);
}
- inline bool properlyDominates(BasicBlock* A, BasicBlock* B) const {
+ bool properlyDominates(BasicBlock *A, BasicBlock *B) const {
return DT->properlyDominates(A, B);
}
@@ -1006,6 +993,8 @@ public:
return false;
}
+ virtual void verifyAnalysis() const;
+
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
AU.addRequired<DominatorTree>();
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/LibCallAliasAnalysis.h b/libclamav/c++/llvm/include/llvm/Analysis/LibCallAliasAnalysis.h
index ea17a23..7944af3 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/LibCallAliasAnalysis.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/LibCallAliasAnalysis.h
@@ -22,7 +22,7 @@ namespace llvm {
struct LibCallFunctionInfo;
/// LibCallAliasAnalysis - Alias analysis driven from LibCallInfo.
- struct LibCallAliasAnalysis : public FunctionPass, AliasAnalysis {
+ struct LibCallAliasAnalysis : public FunctionPass, public AliasAnalysis {
static char ID; // Class identification
LibCallInfo *LCI;
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/LoopInfo.h b/libclamav/c++/llvm/include/llvm/Analysis/LoopInfo.h
index b8617c1..7631110 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/LoopInfo.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/LoopInfo.h
@@ -8,7 +8,8 @@
//===----------------------------------------------------------------------===//
//
// This file defines the LoopInfo class that is used to identify natural loops
-// and determine the loop depth of various nodes of the CFG. Note that natural
+// and determine the loop depth of various nodes of the CFG. A natural loop
+// has exactly one entry-point, which is called the header. Note that natural
// loops may actually be several loops that share the same header node.
//
// This analysis calculates the nesting structure of loops in a function. For
@@ -230,74 +231,6 @@ public:
ExitEdges.push_back(std::make_pair(*BI, *I));
}
- /// getUniqueExitBlocks - Return all unique successor blocks of this loop.
- /// These are the blocks _outside of the current loop_ which are branched to.
- /// This assumes that loop is in canonical form.
- ///
- void getUniqueExitBlocks(SmallVectorImpl<BlockT*> &ExitBlocks) const {
- // Sort the blocks vector so that we can use binary search to do quick
- // lookups.
- SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
- std::sort(LoopBBs.begin(), LoopBBs.end());
-
- std::vector<BlockT*> switchExitBlocks;
-
- for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++BI) {
-
- BlockT *current = *BI;
- switchExitBlocks.clear();
-
- typedef GraphTraits<BlockT*> BlockTraits;
- typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;
- for (typename BlockTraits::ChildIteratorType I =
- BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);
- I != E; ++I) {
- if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I))
- // If block is inside the loop then it is not a exit block.
- continue;
-
- typename InvBlockTraits::ChildIteratorType PI =
- InvBlockTraits::child_begin(*I);
- BlockT *firstPred = *PI;
-
- // If current basic block is this exit block's first predecessor
- // then only insert exit block in to the output ExitBlocks vector.
- // This ensures that same exit block is not inserted twice into
- // ExitBlocks vector.
- if (current != firstPred)
- continue;
-
- // If a terminator has more then two successors, for example SwitchInst,
- // then it is possible that there are multiple edges from current block
- // to one exit block.
- if (std::distance(BlockTraits::child_begin(current),
- BlockTraits::child_end(current)) <= 2) {
- ExitBlocks.push_back(*I);
- continue;
- }
-
- // In case of multiple edges from current block to exit block, collect
- // only one edge in ExitBlocks. Use switchExitBlocks to keep track of
- // duplicate edges.
- if (std::find(switchExitBlocks.begin(), switchExitBlocks.end(), *I)
- == switchExitBlocks.end()) {
- switchExitBlocks.push_back(*I);
- ExitBlocks.push_back(*I);
- }
- }
- }
- }
-
- /// getUniqueExitBlock - If getUniqueExitBlocks would return exactly one
- /// block, return that block. Otherwise return null.
- BlockT *getUniqueExitBlock() const {
- SmallVector<BlockT*, 8> UniqueExitBlocks;
- getUniqueExitBlocks(UniqueExitBlocks);
- if (UniqueExitBlocks.size() == 1)
- return UniqueExitBlocks[0];
- return 0;
- }
-
/// getLoopPreheader - If there is a preheader for this loop, return it. A
/// loop has a preheader if there is only one edge to the header of the loop
/// from outside of the loop. If this is the case, the block branching to the
@@ -444,14 +377,84 @@ public:
/// verifyLoop - Verify loop structure
void verifyLoop() const {
#ifndef NDEBUG
- assert (getHeader() && "Loop header is missing");
- assert (getLoopPreheader() && "Loop preheader is missing");
- assert (getLoopLatch() && "Loop latch is missing");
- for (iterator I = SubLoops.begin(), E = SubLoops.end(); I != E; ++I)
- (*I)->verifyLoop();
+ assert(!Blocks.empty() && "Loop header is missing");
+
+ // Sort the blocks vector so that we can use binary search to do quick
+ // lookups.
+ SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
+ std::sort(LoopBBs.begin(), LoopBBs.end());
+
+ // Check the individual blocks.
+ for (block_iterator I = block_begin(), E = block_end(); I != E; ++I) {
+ BlockT *BB = *I;
+ bool HasInsideLoopSuccs = false;
+ bool HasInsideLoopPreds = false;
+ SmallVector<BlockT *, 2> OutsideLoopPreds;
+
+ typedef GraphTraits<BlockT*> BlockTraits;
+ for (typename BlockTraits::ChildIteratorType SI =
+ BlockTraits::child_begin(BB), SE = BlockTraits::child_end(BB);
+ SI != SE; ++SI)
+ if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), *SI)) {
+ HasInsideLoopSuccs = true;
+ break;
+ }
+ typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;
+ for (typename InvBlockTraits::ChildIteratorType PI =
+ InvBlockTraits::child_begin(BB), PE = InvBlockTraits::child_end(BB);
+ PI != PE; ++PI) {
+ if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), *PI))
+ HasInsideLoopPreds = true;
+ else
+ OutsideLoopPreds.push_back(*PI);
+ }
+
+ if (BB == getHeader()) {
+ assert(!OutsideLoopPreds.empty() && "Loop is unreachable!");
+ } else if (!OutsideLoopPreds.empty()) {
+ // A non-header loop shouldn't be reachable from outside the loop,
+ // though it is permitted if the predecessor is not itself actually
+ // reachable.
+ BlockT *EntryBB = BB->getParent()->begin();
+ for (df_iterator<BlockT *> NI = df_begin(EntryBB),
+ NE = df_end(EntryBB); NI != NE; ++NI)
+ for (unsigned i = 0, e = OutsideLoopPreds.size(); i != e; ++i)
+ assert(*NI != OutsideLoopPreds[i] &&
+ "Loop has multiple entry points!");
+ }
+ assert(HasInsideLoopPreds && "Loop block has no in-loop predecessors!");
+ assert(HasInsideLoopSuccs && "Loop block has no in-loop successors!");
+ assert(BB != getHeader()->getParent()->begin() &&
+ "Loop contains function entry block!");
+ }
+
+ // Check the subloops.
+ for (iterator I = begin(), E = end(); I != E; ++I)
+ // Each block in each subloop should be contained within this loop.
+ for (block_iterator BI = (*I)->block_begin(), BE = (*I)->block_end();
+ BI != BE; ++BI) {
+ assert(std::binary_search(LoopBBs.begin(), LoopBBs.end(), *BI) &&
+ "Loop does not contain all the blocks of a subloop!");
+ }
+
+ // Check the parent loop pointer.
+ if (ParentLoop) {
+ assert(std::find(ParentLoop->begin(), ParentLoop->end(), this) !=
+ ParentLoop->end() &&
+ "Loop is not a subloop of its parent!");
+ }
#endif
}
+ /// verifyLoop - Verify loop structure of this loop and all nested loops.
+ void verifyLoopNest() const {
+ // Verify this loop.
+ verifyLoop();
+ // Verify the subloops.
+ for (iterator I = begin(), E = end(); I != E; ++I)
+ (*I)->verifyLoopNest();
+ }
+
void print(raw_ostream &OS, unsigned Depth = 0) const {
OS.indent(Depth*2) << "Loop at depth " << getLoopDepth()
<< " containing: ";
@@ -569,6 +572,16 @@ public:
/// normal form.
bool isLoopSimplifyForm() const;
+ /// getUniqueExitBlocks - Return all unique successor blocks of this loop.
+ /// These are the blocks _outside of the current loop_ which are branched to.
+ /// This assumes that loop is in canonical form.
+ ///
+ void getUniqueExitBlocks(SmallVectorImpl<BasicBlock *> &ExitBlocks) const;
+
+ /// getUniqueExitBlock - If getUniqueExitBlocks would return exactly one
+ /// block, return that block. Otherwise return null.
+ BasicBlock *getUniqueExitBlock() const;
+
private:
friend class LoopInfoBase<BasicBlock, Loop>;
explicit Loop(BasicBlock *BB) : LoopBase<BasicBlock, Loop>(BB) {}
@@ -719,7 +732,7 @@ public:
for (typename InvBlockTraits::ChildIteratorType I =
InvBlockTraits::child_begin(BB), E = InvBlockTraits::child_end(BB);
I != E; ++I)
- if (DT.dominates(BB, *I)) // If BB dominates it's predecessor...
+ if (DT.dominates(BB, *I)) // If BB dominates its predecessor...
TodoStack.push_back(*I);
if (TodoStack.empty()) return 0; // No backedges to this block...
@@ -745,7 +758,7 @@ public:
if (LoopT *SubLoop =
const_cast<LoopT *>(getLoopFor(X)))
if (SubLoop->getHeader() == X && isNotAlreadyContainedIn(SubLoop, L)){
- // Remove the subloop from it's current parent...
+ // Remove the subloop from its current parent...
assert(SubLoop->ParentLoop && SubLoop->ParentLoop != L);
LoopT *SLP = SubLoop->ParentLoop; // SubLoopParent
typename std::vector<LoopT *>::iterator I =
@@ -931,6 +944,8 @@ public:
///
virtual bool runOnFunction(Function &F);
+ virtual void verifyAnalysis() const;
+
virtual void releaseMemory() { LI.releaseMemory(); }
virtual void print(raw_ostream &O, const Module* M = 0) const;
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/LoopPass.h b/libclamav/c++/llvm/include/llvm/Analysis/LoopPass.h
index 7659b5b..2eb329f 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/LoopPass.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/LoopPass.h
@@ -111,9 +111,13 @@ public:
// Delete loop from the loop queue and loop nest (LoopInfo).
void deleteLoopFromQueue(Loop *L);
- // Insert loop into the loop nest(LoopInfo) and loop queue(LQ).
+ // Insert loop into the loop queue and add it as a child of the
+ // given parent.
void insertLoop(Loop *L, Loop *ParentLoop);
+ // Insert a loop into the loop queue.
+ void insertLoopIntoQueue(Loop *L);
+
// Reoptimize this loop. LPPassManager will re-insert this loop into the
// queue. This allows LoopPass to change loop nest for the loop. This
// utility may send LPPassManager into infinite loops so use caution.
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/MallocHelper.h b/libclamav/c++/llvm/include/llvm/Analysis/MallocHelper.h
new file mode 100644
index 0000000..0588dff
--- /dev/null
+++ b/libclamav/c++/llvm/include/llvm/Analysis/MallocHelper.h
@@ -0,0 +1,86 @@
+//===- llvm/Analysis/MallocHelper.h ---- Identify malloc calls --*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This family of functions identifies calls to malloc, bitcasts of malloc
+// calls, and the types and array sizes associated with them.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_ANALYSIS_MALLOCHELPER_H
+#define LLVM_ANALYSIS_MALLOCHELPER_H
+
+namespace llvm {
+class CallInst;
+class LLVMContext;
+class PointerType;
+class TargetData;
+class Type;
+class Value;
+
+//===----------------------------------------------------------------------===//
+// malloc Call Utility Functions.
+//
+
+/// isMalloc - Returns true if the the value is either a malloc call or a
+/// bitcast of the result of a malloc call
+bool isMalloc(const Value* I);
+
+/// extractMallocCall - Returns the corresponding CallInst if the instruction
+/// is a malloc call. Since CallInst::CreateMalloc() only creates calls, we
+/// ignore InvokeInst here.
+const CallInst* extractMallocCall(const Value* I);
+CallInst* extractMallocCall(Value* I);
+
+/// extractMallocCallFromBitCast - Returns the corresponding CallInst if the
+/// instruction is a bitcast of the result of a malloc call.
+const CallInst* extractMallocCallFromBitCast(const Value* I);
+CallInst* extractMallocCallFromBitCast(Value* I);
+
+/// isArrayMalloc - Returns the corresponding CallInst if the instruction
+/// matches the malloc call IR generated by CallInst::CreateMalloc(). This
+/// means that it is a malloc call with one bitcast use AND the malloc call's
+/// size argument is:
+/// 1. a constant not equal to the malloc's allocated type
+/// or
+/// 2. the result of a multiplication by the malloc's allocated type
+/// Otherwise it returns NULL.
+/// The unique bitcast is needed to determine the type/size of the array
+/// allocation.
+CallInst* isArrayMalloc(Value* I, LLVMContext &Context, const TargetData* TD);
+const CallInst* isArrayMalloc(const Value* I, LLVMContext &Context,
+ const TargetData* TD);
+
+/// getMallocType - Returns the PointerType resulting from the malloc call.
+/// This PointerType is the result type of the call's only bitcast use.
+/// If there is no unique bitcast use, then return NULL.
+const PointerType* getMallocType(const CallInst* CI);
+
+/// getMallocAllocatedType - Returns the Type allocated by malloc call. This
+/// Type is the result type of the call's only bitcast use. If there is no
+/// unique bitcast use, then return NULL.
+const Type* getMallocAllocatedType(const CallInst* CI);
+
+/// getMallocArraySize - Returns the array size of a malloc call. The array
+/// size is computated in 1 of 3 ways:
+/// 1. If the element type if of size 1, then array size is the argument to
+/// malloc.
+/// 2. Else if the malloc's argument is a constant, the array size is that
+/// argument divided by the element type's size.
+/// 3. Else the malloc argument must be a multiplication and the array size is
+/// the first operand of the multiplication.
+/// This function returns constant 1 if:
+/// 1. The malloc call's allocated type cannot be determined.
+/// 2. IR wasn't created by a call to CallInst::CreateMalloc() with a non-NULL
+/// ArraySize.
+Value* getMallocArraySize(CallInst* CI, LLVMContext &Context,
+ const TargetData* TD);
+
+} // End llvm namespace
+
+#endif
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/Passes.h b/libclamav/c++/llvm/include/llvm/Analysis/Passes.h
index e687653..66ab3ea 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/Passes.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/Passes.h
@@ -109,6 +109,12 @@ namespace llvm {
//===--------------------------------------------------------------------===//
//
+ // createProfileVerifierPass - This pass verifies profiling information.
+ //
+ FunctionPass *createProfileVerifierPass();
+
+ //===--------------------------------------------------------------------===//
+ //
// createDSAAPass - This pass implements simple context sensitive alias
// analysis.
//
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/PostDominators.h b/libclamav/c++/llvm/include/llvm/Analysis/PostDominators.h
index 6c9e05f..171cfdb 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/PostDominators.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/PostDominators.h
@@ -49,6 +49,14 @@ struct PostDominatorTree : public FunctionPass {
return DT->getNode(BB);
}
+ inline bool dominates(DomTreeNode* A, DomTreeNode* B) const {
+ return DT->dominates(A, B);
+ }
+
+ inline bool dominates(const BasicBlock* A, const BasicBlock* B) const {
+ return DT->dominates(A, B);
+ }
+
inline bool properlyDominates(const DomTreeNode* A, DomTreeNode* B) const {
return DT->properlyDominates(A, B);
}
@@ -57,6 +65,10 @@ struct PostDominatorTree : public FunctionPass {
return DT->properlyDominates(A, B);
}
+ virtual void releaseMemory() {
+ DT->releaseMemory();
+ }
+
virtual void print(raw_ostream &OS, const Module*) const;
};
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfo.h b/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfo.h
index 16bfc13..2a80f3d 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfo.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfo.h
@@ -63,8 +63,13 @@ namespace llvm {
// getFunction() - Returns the Function for an Edge, checking for validity.
static const Function* getFunction(Edge e) {
- assert(e.second && "Invalid ProfileInfo::Edge");
- return e.second->getParent();
+ if (e.first) {
+ return e.first->getParent();
+ } else if (e.second) {
+ return e.second->getParent();
+ }
+ assert(0 && "Invalid ProfileInfo::Edge");
+ return (const Function*)0;
}
// getEdge() - Creates an Edge from two BasicBlocks.
@@ -97,7 +102,26 @@ namespace llvm {
//===------------------------------------------------------------------===//
/// Analysis Update Methods
///
+ void removeBlock(const BasicBlock *BB) {
+ std::map<const Function*, BlockCounts>::iterator J =
+ BlockInformation.find(BB->getParent());
+ if (J == BlockInformation.end()) return;
+ J->second.erase(BB);
+ }
+
+ void removeEdge(Edge e) {
+ std::map<const Function*, EdgeWeights>::iterator J =
+ EdgeInformation.find(getFunction(e));
+ if (J == EdgeInformation.end()) return;
+
+ J->second.erase(e);
+ }
+
+ void splitEdge(const BasicBlock *FirstBB, const BasicBlock *SecondBB,
+ const BasicBlock *NewBB, bool MergeIdenticalEdges = false);
+
+ void replaceAllUses(const BasicBlock *RmBB, const BasicBlock *DestBB);
};
/// createProfileLoaderPass - This function returns a Pass that loads the
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfoLoader.h b/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfoLoader.h
index 87faa3e..9e0c393 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfoLoader.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfoLoader.h
@@ -33,6 +33,7 @@ class ProfileInfoLoader {
std::vector<unsigned> FunctionCounts;
std::vector<unsigned> BlockCounts;
std::vector<unsigned> EdgeCounts;
+ std::vector<unsigned> OptimalEdgeCounts;
std::vector<unsigned> BBTrace;
bool Warned;
public:
@@ -41,6 +42,8 @@ public:
ProfileInfoLoader(const char *ToolName, const std::string &Filename,
Module &M);
+ static const unsigned Uncounted;
+
unsigned getNumExecutions() const { return CommandLines.size(); }
const std::string &getExecution(unsigned i) const { return CommandLines[i]; }
@@ -66,6 +69,14 @@ public:
const std::vector<unsigned> &getRawEdgeCounts() const {
return EdgeCounts;
}
+
+ // getEdgeOptimalCounts - This method is used by consumers of optimal edge
+ // counting information.
+ //
+ const std::vector<unsigned> &getRawOptimalEdgeCounts() const {
+ return OptimalEdgeCounts;
+ }
+
};
} // End llvm namespace
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfoTypes.h b/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfoTypes.h
index f311f8c..0d531d5 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfoTypes.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/ProfileInfoTypes.h
@@ -22,7 +22,8 @@ enum ProfilingType {
BlockInfo = 3, /* Block profiling information */
EdgeInfo = 4, /* Edge profiling information */
PathInfo = 5, /* Path profiling information */
- BBTraceInfo = 6 /* Basic block trace information */
+ BBTraceInfo = 6, /* Basic block trace information */
+ OptEdgeInfo = 7 /* Edge profiling information, optimal version */
};
#endif /* LLVM_ANALYSIS_PROFILEINFOTYPES_H */
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/ScalarEvolution.h b/libclamav/c++/llvm/include/llvm/Analysis/ScalarEvolution.h
index 8e5f540..cb4d7c1 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/ScalarEvolution.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/ScalarEvolution.h
@@ -104,6 +104,10 @@ namespace llvm {
/// the specified basic block.
virtual bool dominates(BasicBlock *BB, DominatorTree *DT) const = 0;
+ /// properlyDominates - Return true if elements that makes up this SCEV
+ /// properly dominate the specified basic block.
+ virtual bool properlyDominates(BasicBlock *BB, DominatorTree *DT) const = 0;
+
/// print - Print out the internal representation of this scalar to the
/// specified stream. This should really only be used for debugging
/// purposes.
@@ -138,6 +142,10 @@ namespace llvm {
return true;
}
+ virtual bool properlyDominates(BasicBlock *BB, DominatorTree *DT) const {
+ return true;
+ }
+
/// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVCouldNotCompute *S) { return true; }
static bool classof(const SCEV *S);
@@ -219,10 +227,11 @@ namespace llvm {
/// exit value.
std::map<PHINode*, Constant*> ConstantEvolutionLoopExitValue;
- /// ValuesAtScopes - This map contains entries for all the instructions
- /// that we attempt to compute getSCEVAtScope information for without
- /// using SCEV techniques, which can be expensive.
- std::map<Instruction *, std::map<const Loop *, Constant *> > ValuesAtScopes;
+ /// ValuesAtScopes - This map contains entries for all the expressions
+ /// that we attempt to compute getSCEVAtScope information for, which can
+ /// be expensive in extreme cases.
+ std::map<const SCEV *,
+ std::map<const Loop *, const SCEV *> > ValuesAtScopes;
/// createSCEV - We know that there is no SCEV for the specified value.
/// Analyze the expression.
@@ -236,6 +245,11 @@ namespace llvm {
/// SCEVs.
const SCEV *createNodeForGEP(Operator *GEP);
+ /// computeSCEVAtScope - Implementation code for getSCEVAtScope; called
+ /// at most once for each SCEV+Loop pair.
+ ///
+ const SCEV *computeSCEVAtScope(const SCEV *S, const Loop *L);
+
/// ForgetSymbolicValue - This looks up computed SCEV values for all
/// instructions that depend on the given instruction and removes them from
/// the Scalars map if they reference SymName. This is used during PHI
@@ -247,7 +261,8 @@ namespace llvm {
/// CouldNotCompute if an intermediate computation overflows.
const SCEV *getBECount(const SCEV *Start,
const SCEV *End,
- const SCEV *Step);
+ const SCEV *Step,
+ bool NoWrap);
/// getBackedgeTakenInfo - Return the BackedgeTakenInfo for the given
/// loop, lazily computing new values if the loop hasn't been analyzed
@@ -376,7 +391,7 @@ namespace llvm {
/// this is the pointer-sized integer type.
const Type *getEffectiveSCEVType(const Type *Ty) const;
- /// getSCEV - Return a SCEV expression handle for the full generality of the
+ /// getSCEV - Return a SCEV expression for the full generality of the
/// specified expression.
const SCEV *getSCEV(Value *V);
@@ -490,7 +505,7 @@ namespace llvm {
const SCEV *getUMinFromMismatchedTypes(const SCEV *LHS,
const SCEV *RHS);
- /// getSCEVAtScope - Return a SCEV expression handle for the specified value
+ /// getSCEVAtScope - Return a SCEV expression for the specified value
/// at the specified scope in the program. The L value specifies a loop
/// nest to evaluate the expression at, where null is the top-level or a
/// specified loop is immediately inside of the loop.
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h b/libclamav/c++/llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
index 447be0c..67f5e06 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
@@ -60,6 +60,10 @@ namespace llvm {
return true;
}
+ bool properlyDominates(BasicBlock *BB, DominatorTree *DT) const {
+ return true;
+ }
+
virtual void print(raw_ostream &OS) const;
/// Methods for support type inquiry through isa, cast, and dyn_cast:
@@ -98,6 +102,8 @@ namespace llvm {
virtual bool dominates(BasicBlock *BB, DominatorTree *DT) const;
+ virtual bool properlyDominates(BasicBlock *BB, DominatorTree *DT) const;
+
/// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVCastExpr *S) { return true; }
static inline bool classof(const SCEV *S) {
@@ -224,6 +230,8 @@ namespace llvm {
bool dominates(BasicBlock *BB, DominatorTree *DT) const;
+ bool properlyDominates(BasicBlock *BB, DominatorTree *DT) const;
+
virtual const Type *getType() const { return getOperand(0)->getType(); }
/// Methods for support type inquiry through isa, cast, and dyn_cast:
@@ -337,6 +345,8 @@ namespace llvm {
bool dominates(BasicBlock *BB, DominatorTree *DT) const;
+ bool properlyDominates(BasicBlock *BB, DominatorTree *DT) const;
+
virtual const Type *getType() const;
void print(raw_ostream &OS) const;
@@ -513,6 +523,10 @@ namespace llvm {
return true;
}
+ bool properlyDominates(BasicBlock *, DominatorTree *) const {
+ return true;
+ }
+
virtual const Type *getType() const { return Ty; }
/// Methods for support type inquiry through isa, cast, and dyn_cast:
@@ -575,7 +589,7 @@ namespace llvm {
//===--------------------------------------------------------------------===//
/// SCEVUnknown - This means that we are dealing with an entirely unknown SCEV
- /// value, and only represent it as it's LLVM Value. This is the "bottom"
+ /// value, and only represent it as its LLVM Value. This is the "bottom"
/// value for the analysis.
///
class SCEVUnknown : public SCEV {
@@ -599,6 +613,8 @@ namespace llvm {
bool dominates(BasicBlock *BB, DominatorTree *DT) const;
+ bool properlyDominates(BasicBlock *BB, DominatorTree *DT) const;
+
virtual const Type *getType() const;
virtual void print(raw_ostream &OS) const;
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/SparsePropagation.h b/libclamav/c++/llvm/include/llvm/Analysis/SparsePropagation.h
index cc655aa..820e1bd 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/SparsePropagation.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/SparsePropagation.h
@@ -72,6 +72,12 @@ public:
virtual LatticeVal ComputeConstant(Constant *C) {
return getOverdefinedVal(); // always safe
}
+
+ /// IsSpecialCasedPHI - Given a PHI node, determine whether this PHI node is
+ /// one that the we want to handle through ComputeInstructionState.
+ virtual bool IsSpecialCasedPHI(PHINode *PN) {
+ return false;
+ }
/// GetConstant - If the specified lattice value is representable as an LLVM
/// constant value, return it. Otherwise return null. The returned value
diff --git a/libclamav/c++/llvm/include/llvm/Analysis/ValueTracking.h b/libclamav/c++/llvm/include/llvm/Analysis/ValueTracking.h
index 6bb3b3c..212b5d1 100644
--- a/libclamav/c++/llvm/include/llvm/Analysis/ValueTracking.h
+++ b/libclamav/c++/llvm/include/llvm/Analysis/ValueTracking.h
@@ -29,6 +29,12 @@ namespace llvm {
/// known to be either zero or one and return them in the KnownZero/KnownOne
/// bit sets. This code only analyzes bits in Mask, in order to short-circuit
/// processing.
+ ///
+ /// This function is defined on values with integer type, values with pointer
+ /// type (but only if TD is non-null), and vectors of integers. In the case
+ /// where V is a vector, the mask, known zero, and known one values are the
+ /// same width as the vector element, and the bit is set only if it is true
+ /// for all of the elements in the vector.
void ComputeMaskedBits(Value *V, const APInt &Mask, APInt &KnownZero,
APInt &KnownOne, const TargetData *TD = 0,
unsigned Depth = 0);
@@ -36,6 +42,12 @@ namespace llvm {
/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
/// this predicate to simplify operations downstream. Mask is known to be
/// zero for bits that V cannot have.
+ ///
+ /// This function is defined on values with integer type, values with pointer
+ /// type (but only if TD is non-null), and vectors of integers. In the case
+ /// where V is a vector, the mask, known zero, and known one values are the
+ /// same width as the vector element, and the bit is set only if it is true
+ /// for all of the elements in the vector.
bool MaskedValueIsZero(Value *V, const APInt &Mask,
const TargetData *TD = 0, unsigned Depth = 0);
diff --git a/libclamav/c++/llvm/include/llvm/Assembly/Parser.h b/libclamav/c++/llvm/include/llvm/Assembly/Parser.h
index 966abaa..82ec6d8 100644
--- a/libclamav/c++/llvm/include/llvm/Assembly/Parser.h
+++ b/libclamav/c++/llvm/include/llvm/Assembly/Parser.h
@@ -19,6 +19,7 @@
namespace llvm {
class Module;
+class MemoryBuffer;
class SMDiagnostic;
class raw_ostream;
class LLVMContext;
@@ -48,6 +49,17 @@ Module *ParseAssemblyString(
LLVMContext &Context
);
+/// This function is the low-level interface to the LLVM Assembly Parser.
+/// ParseAssemblyFile and ParseAssemblyString are wrappers around this function.
+/// @brief Parse LLVM Assembly from a MemoryBuffer. This function *always*
+/// takes ownership of the MemoryBuffer.
+Module *ParseAssembly(
+ MemoryBuffer *F, ///< The MemoryBuffer containing assembly
+ Module *M, ///< A module to add the assembly too.
+ SMDiagnostic &Err, ///< Error result info.
+ LLVMContext &Context
+);
+
} // End llvm namespace
#endif
diff --git a/libclamav/c++/llvm/include/llvm/BasicBlock.h b/libclamav/c++/llvm/include/llvm/BasicBlock.h
index 3f53507..b497827 100644
--- a/libclamav/c++/llvm/include/llvm/BasicBlock.h
+++ b/libclamav/c++/llvm/include/llvm/BasicBlock.h
@@ -231,6 +231,9 @@ public:
/// cause a degenerate basic block to be formed, having a terminator inside of
/// the basic block).
///
+ /// Also note that this doesn't preserve any passes. To split blocks while
+ /// keeping loop information consistent, use the SplitBlock utility function.
+ ///
BasicBlock *splitBasicBlock(iterator I, const Twine &BBName = "");
};
diff --git a/libclamav/c++/llvm/include/llvm/Bitcode/LLVMBitCodes.h b/libclamav/c++/llvm/include/llvm/Bitcode/LLVMBitCodes.h
index 2f967d6..dccd8e0 100644
--- a/libclamav/c++/llvm/include/llvm/Bitcode/LLVMBitCodes.h
+++ b/libclamav/c++/llvm/include/llvm/Bitcode/LLVMBitCodes.h
@@ -34,7 +34,8 @@ namespace bitc {
FUNCTION_BLOCK_ID,
TYPE_SYMTAB_BLOCK_ID,
VALUE_SYMTAB_BLOCK_ID,
- METADATA_BLOCK_ID
+ METADATA_BLOCK_ID,
+ METADATA_ATTACHMENT_ID
};
@@ -111,7 +112,9 @@ namespace bitc {
METADATA_STRING = 1, // MDSTRING: [values]
METADATA_NODE = 2, // MDNODE: [n x (type num, value num)]
METADATA_NAME = 3, // STRING: [values]
- METADATA_NAMED_NODE = 4 // NAMEDMDNODE: [n x mdnodes]
+ METADATA_NAMED_NODE = 4, // NAMEDMDNODE: [n x mdnodes]
+ METADATA_KIND = 5, // [n x [id, name]]
+ METADATA_ATTACHMENT = 6 // [m x [value, [n x [id, mdnode]]]
};
// The constants block (CONSTANTS_BLOCK_ID) describes emission for each
// constant and maintains an implicit current type value.
diff --git a/libclamav/c++/llvm/include/llvm/Bitcode/ReaderWriter.h b/libclamav/c++/llvm/include/llvm/Bitcode/ReaderWriter.h
index ef32239..7b74bdf 100644
--- a/libclamav/c++/llvm/include/llvm/Bitcode/ReaderWriter.h
+++ b/libclamav/c++/llvm/include/llvm/Bitcode/ReaderWriter.h
@@ -53,14 +53,43 @@ namespace llvm {
ModulePass *createBitcodeWriterPass(raw_ostream &Str);
- /// isBitcodeWrapper - Return true fi this is a wrapper for LLVM IR bitcode
- /// files.
- static bool inline isBitcodeWrapper(unsigned char *BufPtr,
- unsigned char *BufEnd) {
- return (BufPtr != BufEnd && BufPtr[0] == 0xDE && BufPtr[1] == 0xC0 &&
- BufPtr[2] == 0x17 && BufPtr[3] == 0x0B);
+ /// isBitcodeWrapper - Return true if the given bytes are the magic bytes
+ /// for an LLVM IR bitcode wrapper.
+ ///
+ static inline bool isBitcodeWrapper(const unsigned char *BufPtr,
+ const unsigned char *BufEnd) {
+ // See if you can find the hidden message in the magic bytes :-).
+ // (Hint: it's a little-endian encoding.)
+ return BufPtr != BufEnd &&
+ BufPtr[0] == 0xDE &&
+ BufPtr[1] == 0xC0 &&
+ BufPtr[2] == 0x17 &&
+ BufPtr[3] == 0x0B;
}
-
+
+ /// isRawBitcode - Return true if the given bytes are the magic bytes for
+ /// raw LLVM IR bitcode (without a wrapper).
+ ///
+ static inline bool isRawBitcode(const unsigned char *BufPtr,
+ const unsigned char *BufEnd) {
+ // These bytes sort of have a hidden message, but it's not in
+ // little-endian this time, and it's a little redundant.
+ return BufPtr != BufEnd &&
+ BufPtr[0] == 'B' &&
+ BufPtr[1] == 'C' &&
+ BufPtr[2] == 0xc0 &&
+ BufPtr[3] == 0xde;
+ }
+
+ /// isBitcode - Return true if the given bytes are the magic bytes for
+ /// LLVM IR bitcode, either with or without a wrapper.
+ ///
+ static bool inline isBitcode(const unsigned char *BufPtr,
+ const unsigned char *BufEnd) {
+ return isBitcodeWrapper(BufPtr, BufEnd) ||
+ isRawBitcode(BufPtr, BufEnd);
+ }
+
/// SkipBitcodeWrapperHeader - Some systems wrap bc files with a special
/// header for padding or other reasons. The format of this header is:
///
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/AsmPrinter.h b/libclamav/c++/llvm/include/llvm/CodeGen/AsmPrinter.h
index 621b47d..2f0e8d0 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -46,6 +46,7 @@ namespace llvm {
class MCContext;
class MCSection;
class MCStreamer;
+ class MCSymbol;
class DwarfWriter;
class Mangler;
class MCAsmInfo;
@@ -75,10 +76,11 @@ namespace llvm {
///
MachineLoopInfo *LI;
- protected:
+ public:
/// MMI - If available, this is a pointer to the current MachineModuleInfo.
MachineModuleInfo *MMI;
+ protected:
/// DW - If available, this is a pointer to the current dwarf writer.
DwarfWriter *DW;
@@ -133,11 +135,6 @@ namespace llvm {
///
bool VerboseAsm;
- /// ExuberantAsm - Emit many more comments in assembly output if
- /// this is true.
- ///
- bool ExuberantAsm;
-
/// Private state for PrintSpecial()
// Assign a unique ID to this machine instruction.
mutable const MachineInstr *LastMI;
@@ -158,20 +155,10 @@ namespace llvm {
///
bool isVerbose() const { return VerboseAsm; }
- /// getGlobalLinkName - Returns the asm/link name of of the specified
- /// global variable. Should be overridden by each target asm printer to
- /// generate the appropriate value.
- virtual const std::string &getGlobalLinkName(const GlobalVariable *GV,
- std::string &LinkName) const;
-
- /// EmitExternalGlobal - Emit the external reference to a global variable.
- /// Should be overridden if an indirect reference should be used.
- virtual void EmitExternalGlobal(const GlobalVariable *GV);
-
- /// getCurrentFunctionEHName - Called to return the CurrentFnEHName.
- ///
- std::string getCurrentFunctionEHName(const MachineFunction *MF) const;
-
+ /// getFunctionNumber - Return a unique ID for the current function.
+ ///
+ unsigned getFunctionNumber() const { return FunctionNumber; }
+
protected:
/// getAnalysisUsage - Record analysis usage.
///
@@ -182,6 +169,14 @@ namespace llvm {
/// call this implementation.
bool doInitialization(Module &M);
+ /// EmitStartOfAsmFile - This virtual method can be overridden by targets
+ /// that want to emit something at the start of their file.
+ virtual void EmitStartOfAsmFile(Module &M) {}
+
+ /// EmitEndOfAsmFile - This virtual method can be overridden by targets that
+ /// want to emit something at the end of their file.
+ virtual void EmitEndOfAsmFile(Module &M) {}
+
/// doFinalization - Shut down the asmprinter. If you override this in your
/// pass, you must make sure to call it explicitly.
bool doFinalization(Module &M);
@@ -217,10 +212,6 @@ namespace llvm {
/// is being processed from runOnMachineFunction.
void SetupMachineFunction(MachineFunction &MF);
- /// getFunctionNumber - Return a unique ID for the current function.
- ///
- unsigned getFunctionNumber() const { return FunctionNumber; }
-
/// IncrementFunctionNumber - Increase Function Number. AsmPrinters should
/// not normally call this, as the counter is automatically bumped by
/// SetupMachineFunction.
@@ -336,17 +327,17 @@ namespace llvm {
/// EmitComments - Pretty-print comments for instructions
void EmitComments(const MachineInstr &MI) const;
- /// EmitComments - Pretty-print comments for instructions
- void EmitComments(const MCInst &MI) const;
/// EmitComments - Pretty-print comments for basic blocks
void EmitComments(const MachineBasicBlock &MBB) const;
- /// printMCInst - Print an MCInst for this target.
- ///
- /// Note, this is only a temporary hack to allow the MCStreamer to print
- /// instructions, do not use this function outside of llvm-mc.
- virtual void printMCInst(const MCInst *MI);
-
+ /// GetMBBSymbol - Return the MCSymbol corresponding to the specified basic
+ /// block label.
+ MCSymbol *GetMBBSymbol(unsigned MBBID) const;
+
+ /// EmitBasicBlockStart - This method prints the label for the specified
+ /// MachineBasicBlock, an alignment (if present) and a comment describing
+ /// it if appropriate.
+ void EmitBasicBlockStart(const MachineBasicBlock *MBB) const;
protected:
/// EmitZeros - Emit a block of zeros.
///
@@ -367,7 +358,7 @@ namespace llvm {
/// processDebugLoc - Processes the debug information of each machine
/// instruction's DebugLoc.
- void processDebugLoc(DebugLoc DL);
+ void processDebugLoc(const MachineInstr *MI);
/// printInlineAsm - This method formats and prints the specified machine
/// instruction that is an inline asm.
@@ -377,13 +368,7 @@ namespace llvm {
/// that is an implicit def.
virtual void printImplicitDef(const MachineInstr *MI) const;
- /// printBasicBlockLabel - This method prints the label for the specified
- /// MachineBasicBlock
- virtual void printBasicBlockLabel(const MachineBasicBlock *MBB,
- bool printAlign = false,
- bool printColon = false,
- bool printComment = true) const;
-
+
/// printPICJumpTableSetLabel - This method prints a set label for the
/// specified MachineBasicBlock for a jumptable entry.
virtual void printPICJumpTableSetLabel(unsigned uid,
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/CallingConvLower.h b/libclamav/c++/llvm/include/llvm/CodeGen/CallingConvLower.h
index eb91687..5e730fc 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/CallingConvLower.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/CallingConvLower.h
@@ -18,6 +18,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CallingConv.h"
namespace llvm {
class TargetRegisterInfo;
@@ -142,7 +143,7 @@ typedef bool CCCustomFn(unsigned &ValNo, EVT &ValVT,
/// return values. It captures which registers are already assigned and which
/// stack slots are used. It provides accessors to allocate these values.
class CCState {
- unsigned CallingConv;
+ CallingConv::ID CallingConv;
bool IsVarArg;
const TargetMachine &TM;
const TargetRegisterInfo &TRI;
@@ -152,7 +153,7 @@ class CCState {
unsigned StackOffset;
SmallVector<uint32_t, 16> UsedRegs;
public:
- CCState(unsigned CC, bool isVarArg, const TargetMachine &TM,
+ CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM,
SmallVector<CCValAssign, 16> &locs, LLVMContext &C);
void addLoc(const CCValAssign &V) {
@@ -161,7 +162,7 @@ public:
LLVMContext &getContext() const { return Context; }
const TargetMachine &getTarget() const { return TM; }
- unsigned getCallingConv() const { return CallingConv; }
+ CallingConv::ID getCallingConv() const { return CallingConv; }
bool isVarArg() const { return IsVarArg; }
unsigned getNextStackOffset() const { return StackOffset; }
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/DwarfWriter.h b/libclamav/c++/llvm/include/llvm/CodeGen/DwarfWriter.h
index 3635c4d..46be8d2 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/DwarfWriter.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/DwarfWriter.h
@@ -85,7 +85,7 @@ public:
/// RecordSourceLine - Register a source line with debug info. Returns a
/// unique label ID used to generate a label and provide correspondence to
/// the source line list.
- unsigned RecordSourceLine(unsigned Line, unsigned Col, DICompileUnit CU);
+ unsigned RecordSourceLine(unsigned Line, unsigned Col, MDNode *Scope);
/// RecordRegionStart - Indicate the start of a region.
unsigned RecordRegionStart(MDNode *N);
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/FastISel.h b/libclamav/c++/llvm/include/llvm/CodeGen/FastISel.h
index b2cc94d..6cd5519 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/FastISel.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/FastISel.h
@@ -300,6 +300,8 @@ protected:
private:
bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
+ bool SelectFNeg(User *I);
+
bool SelectGetElementPtr(User *I);
bool SelectCall(User *I);
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h b/libclamav/c++/llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h
index 1bf590a..4d2d0ee 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h
@@ -32,7 +32,6 @@ namespace {
(void) llvm::createDeadMachineInstructionElimPass();
- (void) llvm::createSimpleRegisterAllocator();
(void) llvm::createLocalRegisterAllocator();
(void) llvm::createLinearScanRegisterAllocator();
(void) llvm::createPBQPRegisterAllocator();
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/LiveInterval.h b/libclamav/c++/llvm/include/llvm/CodeGen/LiveInterval.h
index 9a9bc56..1878b2e 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/LiveInterval.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/LiveInterval.h
@@ -21,6 +21,7 @@
#ifndef LLVM_CODEGEN_LIVEINTERVAL_H
#define LLVM_CODEGEN_LIVEINTERVAL_H
+#include "llvm/ADT/DenseMapInfo.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/AlignOf.h"
@@ -32,6 +33,209 @@ namespace llvm {
class MachineRegisterInfo;
class TargetRegisterInfo;
class raw_ostream;
+
+ /// MachineInstrIndex - An opaque wrapper around machine indexes.
+ class MachineInstrIndex {
+ friend class VNInfo;
+ friend class LiveInterval;
+ friend class LiveIntervals;
+ friend struct DenseMapInfo<MachineInstrIndex>;
+
+ public:
+
+ enum Slot { LOAD, USE, DEF, STORE, NUM };
+
+ private:
+
+ unsigned index;
+
+ static const unsigned PHI_BIT = 1 << 31;
+
+ public:
+
+ /// Construct a default MachineInstrIndex pointing to a reserved index.
+ MachineInstrIndex() : index(0) {}
+
+ /// Construct an index from the given index, pointing to the given slot.
+ MachineInstrIndex(MachineInstrIndex m, Slot s)
+ : index((m.index / NUM) * NUM + s) {}
+
+ /// Print this index to the given raw_ostream.
+ void print(raw_ostream &os) const;
+
+ /// Compare two MachineInstrIndex objects for equality.
+ bool operator==(MachineInstrIndex other) const {
+ return ((index & ~PHI_BIT) == (other.index & ~PHI_BIT));
+ }
+ /// Compare two MachineInstrIndex objects for inequality.
+ bool operator!=(MachineInstrIndex other) const {
+ return ((index & ~PHI_BIT) != (other.index & ~PHI_BIT));
+ }
+
+ /// Compare two MachineInstrIndex objects. Return true if the first index
+ /// is strictly lower than the second.
+ bool operator<(MachineInstrIndex other) const {
+ return ((index & ~PHI_BIT) < (other.index & ~PHI_BIT));
+ }
+ /// Compare two MachineInstrIndex objects. Return true if the first index
+ /// is lower than, or equal to, the second.
+ bool operator<=(MachineInstrIndex other) const {
+ return ((index & ~PHI_BIT) <= (other.index & ~PHI_BIT));
+ }
+
+ /// Compare two MachineInstrIndex objects. Return true if the first index
+ /// is greater than the second.
+ bool operator>(MachineInstrIndex other) const {
+ return ((index & ~PHI_BIT) > (other.index & ~PHI_BIT));
+ }
+
+ /// Compare two MachineInstrIndex objects. Return true if the first index
+ /// is greater than, or equal to, the second.
+ bool operator>=(MachineInstrIndex other) const {
+ return ((index & ~PHI_BIT) >= (other.index & ~PHI_BIT));
+ }
+
+ /// Returns true if this index represents a load.
+ bool isLoad() const {
+ return ((index % NUM) == LOAD);
+ }
+
+ /// Returns true if this index represents a use.
+ bool isUse() const {
+ return ((index % NUM) == USE);
+ }
+
+ /// Returns true if this index represents a def.
+ bool isDef() const {
+ return ((index % NUM) == DEF);
+ }
+
+ /// Returns true if this index represents a store.
+ bool isStore() const {
+ return ((index % NUM) == STORE);
+ }
+
+ /// Returns the slot for this MachineInstrIndex.
+ Slot getSlot() const {
+ return static_cast<Slot>(index % NUM);
+ }
+
+ /// Returns true if this index represents a non-PHI use/def.
+ bool isNonPHIIndex() const {
+ return ((index & PHI_BIT) == 0);
+ }
+
+ /// Returns true if this index represents a PHI use/def.
+ bool isPHIIndex() const {
+ return ((index & PHI_BIT) == PHI_BIT);
+ }
+
+ private:
+
+ /// Construct an index from the given index, with its PHI kill marker set.
+ MachineInstrIndex(bool phi, MachineInstrIndex o) : index(o.index) {
+ if (phi)
+ index |= PHI_BIT;
+ else
+ index &= ~PHI_BIT;
+ }
+
+ explicit MachineInstrIndex(unsigned idx)
+ : index(idx & ~PHI_BIT) {}
+
+ MachineInstrIndex(bool phi, unsigned idx)
+ : index(idx & ~PHI_BIT) {
+ if (phi)
+ index |= PHI_BIT;
+ }
+
+ MachineInstrIndex(bool phi, unsigned idx, Slot slot)
+ : index(((idx / NUM) * NUM + slot) & ~PHI_BIT) {
+ if (phi)
+ index |= PHI_BIT;
+ }
+
+ MachineInstrIndex nextSlot_() const {
+ assert((index & PHI_BIT) == ((index + 1) & PHI_BIT) &&
+ "Index out of bounds.");
+ return MachineInstrIndex(index + 1);
+ }
+
+ MachineInstrIndex nextIndex_() const {
+ assert((index & PHI_BIT) == ((index + NUM) & PHI_BIT) &&
+ "Index out of bounds.");
+ return MachineInstrIndex(index + NUM);
+ }
+
+ MachineInstrIndex prevSlot_() const {
+ assert((index & PHI_BIT) == ((index - 1) & PHI_BIT) &&
+ "Index out of bounds.");
+ return MachineInstrIndex(index - 1);
+ }
+
+ MachineInstrIndex prevIndex_() const {
+ assert((index & PHI_BIT) == ((index - NUM) & PHI_BIT) &&
+ "Index out of bounds.");
+ return MachineInstrIndex(index - NUM);
+ }
+
+ int distance(MachineInstrIndex other) const {
+ return (other.index & ~PHI_BIT) - (index & ~PHI_BIT);
+ }
+
+ /// Returns an unsigned number suitable as an index into a
+ /// vector over all instructions.
+ unsigned getVecIndex() const {
+ return (index & ~PHI_BIT) / NUM;
+ }
+
+ /// Scale this index by the given factor.
+ MachineInstrIndex scale(unsigned factor) const {
+ unsigned i = (index & ~PHI_BIT) / NUM,
+ o = (index % ~PHI_BIT) % NUM;
+ assert(index <= (~0U & ~PHI_BIT) / (factor * NUM) &&
+ "Rescaled interval would overflow");
+ return MachineInstrIndex(i * NUM * factor, o);
+ }
+
+ static MachineInstrIndex emptyKey() {
+ return MachineInstrIndex(true, 0x7fffffff);
+ }
+
+ static MachineInstrIndex tombstoneKey() {
+ return MachineInstrIndex(true, 0x7ffffffe);
+ }
+
+ static unsigned getHashValue(const MachineInstrIndex &v) {
+ return v.index * 37;
+ }
+
+ };
+
+ inline raw_ostream& operator<<(raw_ostream &os, MachineInstrIndex mi) {
+ mi.print(os);
+ return os;
+ }
+
+ /// Densemap specialization for MachineInstrIndex.
+ template <>
+ struct DenseMapInfo<MachineInstrIndex> {
+ static inline MachineInstrIndex getEmptyKey() {
+ return MachineInstrIndex::emptyKey();
+ }
+ static inline MachineInstrIndex getTombstoneKey() {
+ return MachineInstrIndex::tombstoneKey();
+ }
+ static inline unsigned getHashValue(const MachineInstrIndex &v) {
+ return MachineInstrIndex::getHashValue(v);
+ }
+ static inline bool isEqual(const MachineInstrIndex &LHS,
+ const MachineInstrIndex &RHS) {
+ return (LHS == RHS);
+ }
+ static inline bool isPod() { return true; }
+ };
+
/// VNInfo - Value Number Information.
/// This class holds information about a machine level values, including
@@ -65,36 +269,24 @@ namespace llvm {
} cr;
public:
- /// Holds information about individual kills.
- struct KillInfo {
- bool isPHIKill : 1;
- unsigned killIdx : 31;
- KillInfo(bool isPHIKill, unsigned killIdx)
- : isPHIKill(isPHIKill), killIdx(killIdx) {
-
- assert(killIdx != 0 && "Zero kill indices are no longer permitted.");
- }
-
- };
-
- typedef SmallVector<KillInfo, 4> KillSet;
+ typedef SmallVector<MachineInstrIndex, 4> KillSet;
/// The ID number of this value.
unsigned id;
/// The index of the defining instruction (if isDefAccurate() returns true).
- unsigned def;
+ MachineInstrIndex def;
KillSet kills;
VNInfo()
- : flags(IS_UNUSED), id(~1U), def(0) { cr.copy = 0; }
+ : flags(IS_UNUSED), id(~1U) { cr.copy = 0; }
/// VNInfo constructor.
/// d is presumed to point to the actual defining instr. If it doesn't
/// setIsDefAccurate(false) should be called after construction.
- VNInfo(unsigned i, unsigned d, MachineInstr *c)
+ VNInfo(unsigned i, MachineInstrIndex d, MachineInstr *c)
: flags(IS_DEF_ACCURATE), id(i), def(d) { cr.copy = c; }
/// VNInfo construtor, copies values from orig, except for the value number.
@@ -134,6 +326,7 @@ namespace llvm {
/// Returns true if one or more kills are PHI nodes.
bool hasPHIKill() const { return flags & HAS_PHI_KILL; }
+ /// Set the PHI kill flag on this value.
void setHasPHIKill(bool hasKill) {
if (hasKill)
flags |= HAS_PHI_KILL;
@@ -144,6 +337,7 @@ namespace llvm {
/// Returns true if this value is re-defined by an early clobber somewhere
/// during the live range.
bool hasRedefByEC() const { return flags & REDEF_BY_EC; }
+ /// Set the "redef by early clobber" flag on this value.
void setHasRedefByEC(bool hasRedef) {
if (hasRedef)
flags |= REDEF_BY_EC;
@@ -154,6 +348,7 @@ namespace llvm {
/// Returns true if this value is defined by a PHI instruction (or was,
/// PHI instrucions may have been eliminated).
bool isPHIDef() const { return flags & IS_PHI_DEF; }
+ /// Set the "phi def" flag on this value.
void setIsPHIDef(bool phiDef) {
if (phiDef)
flags |= IS_PHI_DEF;
@@ -163,6 +358,7 @@ namespace llvm {
/// Returns true if this value is unused.
bool isUnused() const { return flags & IS_UNUSED; }
+ /// Set the "is unused" flag on this value.
void setIsUnused(bool unused) {
if (unused)
flags |= IS_UNUSED;
@@ -172,6 +368,7 @@ namespace llvm {
/// Returns true if the def is accurate.
bool isDefAccurate() const { return flags & IS_DEF_ACCURATE; }
+ /// Set the "is def accurate" flag on this value.
void setIsDefAccurate(bool defAccurate) {
if (defAccurate)
flags |= IS_DEF_ACCURATE;
@@ -179,38 +376,74 @@ namespace llvm {
flags &= ~IS_DEF_ACCURATE;
}
- };
+ /// Returns true if the given index is a kill of this value.
+ bool isKill(MachineInstrIndex k) const {
+ KillSet::const_iterator
+ i = std::lower_bound(kills.begin(), kills.end(), k);
+ return (i != kills.end() && *i == k);
+ }
- inline bool operator<(const VNInfo::KillInfo &k1, const VNInfo::KillInfo &k2){
- return k1.killIdx < k2.killIdx;
- }
-
- inline bool operator<(const VNInfo::KillInfo &k, unsigned idx) {
- return k.killIdx < idx;
- }
+ /// addKill - Add a kill instruction index to the specified value
+ /// number.
+ void addKill(MachineInstrIndex k) {
+ if (kills.empty()) {
+ kills.push_back(k);
+ } else {
+ KillSet::iterator
+ i = std::lower_bound(kills.begin(), kills.end(), k);
+ kills.insert(i, k);
+ }
+ }
- inline bool operator<(unsigned idx, const VNInfo::KillInfo &k) {
- return idx < k.killIdx;
- }
+ /// Remove the specified kill index from this value's kills list.
+ /// Returns true if the value was present, otherwise returns false.
+ bool removeKill(MachineInstrIndex k) {
+ KillSet::iterator i = std::lower_bound(kills.begin(), kills.end(), k);
+ if (i != kills.end() && *i == k) {
+ kills.erase(i);
+ return true;
+ }
+ return false;
+ }
+
+ /// Remove all kills in the range [s, e).
+ void removeKills(MachineInstrIndex s, MachineInstrIndex e) {
+ KillSet::iterator
+ si = std::lower_bound(kills.begin(), kills.end(), s),
+ se = std::upper_bound(kills.begin(), kills.end(), e);
+
+ kills.erase(si, se);
+ }
+
+ };
/// LiveRange structure - This represents a simple register range in the
/// program, with an inclusive start point and an exclusive end point.
/// These ranges are rendered as [start,end).
struct LiveRange {
- unsigned start; // Start point of the interval (inclusive)
- unsigned end; // End point of the interval (exclusive)
+ MachineInstrIndex start; // Start point of the interval (inclusive)
+ MachineInstrIndex end; // End point of the interval (exclusive)
VNInfo *valno; // identifier for the value contained in this interval.
- LiveRange(unsigned S, unsigned E, VNInfo *V) : start(S), end(E), valno(V) {
+ LiveRange(MachineInstrIndex S, MachineInstrIndex E, VNInfo *V)
+ : start(S), end(E), valno(V) {
+
assert(S < E && "Cannot create empty or backwards range");
}
/// contains - Return true if the index is covered by this range.
///
- bool contains(unsigned I) const {
+ bool contains(MachineInstrIndex I) const {
return start <= I && I < end;
}
+ /// containsRange - Return true if the given range, [S, E), is covered by
+ /// this range.
+ bool containsRange(MachineInstrIndex S, MachineInstrIndex E) const {
+ assert((S < E) && "Backwards interval?");
+ return (start <= S && S < end) && (start < E && E <= end);
+ }
+
bool operator<(const LiveRange &LR) const {
return start < LR.start || (start == LR.start && end < LR.end);
}
@@ -228,11 +461,11 @@ namespace llvm {
raw_ostream& operator<<(raw_ostream& os, const LiveRange &LR);
- inline bool operator<(unsigned V, const LiveRange &LR) {
+ inline bool operator<(MachineInstrIndex V, const LiveRange &LR) {
return V < LR.start;
}
- inline bool operator<(const LiveRange &LR, unsigned V) {
+ inline bool operator<(const LiveRange &LR, MachineInstrIndex V) {
return LR.start < V;
}
@@ -260,14 +493,6 @@ namespace llvm {
NUM = 4
};
- static unsigned scale(unsigned slot, unsigned factor) {
- unsigned index = slot / NUM,
- offset = slot % NUM;
- assert(index <= ~0U / (factor * NUM) &&
- "Rescaled interval would overflow");
- return index * NUM * factor + offset;
- }
-
};
LiveInterval(unsigned Reg, float Weight, bool IsSS = false)
@@ -297,8 +522,8 @@ namespace llvm {
/// end of the interval. If no LiveRange contains this position, but the
/// position is in a hole, this method returns an iterator pointing the the
/// LiveRange immediately after the hole.
- iterator advanceTo(iterator I, unsigned Pos) {
- if (Pos >= endNumber())
+ iterator advanceTo(iterator I, MachineInstrIndex Pos) {
+ if (Pos >= endIndex())
return end();
while (I->end <= Pos) ++I;
return I;
@@ -344,15 +569,12 @@ namespace llvm {
/// getNextValue - Create a new value number and return it. MIIdx specifies
/// the instruction that defines the value number.
- VNInfo *getNextValue(unsigned MIIdx, MachineInstr *CopyMI,
+ VNInfo *getNextValue(MachineInstrIndex def, MachineInstr *CopyMI,
bool isDefAccurate, BumpPtrAllocator &VNInfoAllocator){
-
- assert(MIIdx != ~0u && MIIdx != ~1u &&
- "PHI def / unused flags should now be passed explicitly.");
VNInfo *VNI =
static_cast<VNInfo*>(VNInfoAllocator.Allocate((unsigned)sizeof(VNInfo),
alignof<VNInfo>()));
- new (VNI) VNInfo((unsigned)valnos.size(), MIIdx, CopyMI);
+ new (VNI) VNInfo((unsigned)valnos.size(), def, CopyMI);
VNI->setIsDefAccurate(isDefAccurate);
valnos.push_back(VNI);
return VNI;
@@ -362,7 +584,6 @@ namespace llvm {
/// for the Value number.
VNInfo *createValueCopy(const VNInfo *orig,
BumpPtrAllocator &VNInfoAllocator) {
-
VNInfo *VNI =
static_cast<VNInfo*>(VNInfoAllocator.Allocate((unsigned)sizeof(VNInfo),
alignof<VNInfo>()));
@@ -372,68 +593,17 @@ namespace llvm {
return VNI;
}
- /// addKill - Add a kill instruction index to the specified value
- /// number.
- static void addKill(VNInfo *VNI, unsigned KillIdx, bool phiKill) {
- VNInfo::KillSet &kills = VNI->kills;
- VNInfo::KillInfo newKill(phiKill, KillIdx);
- if (kills.empty()) {
- kills.push_back(newKill);
- } else {
- VNInfo::KillSet::iterator
- I = std::lower_bound(kills.begin(), kills.end(), newKill);
- kills.insert(I, newKill);
- }
- }
-
/// addKills - Add a number of kills into the VNInfo kill vector. If this
/// interval is live at a kill point, then the kill is not added.
void addKills(VNInfo *VNI, const VNInfo::KillSet &kills) {
for (unsigned i = 0, e = static_cast<unsigned>(kills.size());
i != e; ++i) {
- const VNInfo::KillInfo &Kill = kills[i];
- if (!liveBeforeAndAt(Kill.killIdx)) {
- VNInfo::KillSet::iterator
- I = std::lower_bound(VNI->kills.begin(), VNI->kills.end(), Kill);
- VNI->kills.insert(I, Kill);
+ if (!liveBeforeAndAt(kills[i])) {
+ VNI->addKill(kills[i]);
}
}
}
- /// removeKill - Remove the specified kill from the list of kills of
- /// the specified val#.
- static bool removeKill(VNInfo *VNI, unsigned KillIdx) {
- VNInfo::KillSet &kills = VNI->kills;
- VNInfo::KillSet::iterator
- I = std::lower_bound(kills.begin(), kills.end(), KillIdx);
- if (I != kills.end() && I->killIdx == KillIdx) {
- kills.erase(I);
- return true;
- }
- return false;
- }
-
- /// removeKills - Remove all the kills in specified range
- /// [Start, End] of the specified val#.
- static void removeKills(VNInfo *VNI, unsigned Start, unsigned End) {
- VNInfo::KillSet &kills = VNI->kills;
-
- VNInfo::KillSet::iterator
- I = std::lower_bound(kills.begin(), kills.end(), Start);
- VNInfo::KillSet::iterator
- E = std::upper_bound(kills.begin(), kills.end(), End);
- kills.erase(I, E);
- }
-
- /// isKill - Return true if the specified index is a kill of the
- /// specified val#.
- static bool isKill(const VNInfo *VNI, unsigned KillIdx) {
- const VNInfo::KillSet &kills = VNI->kills;
- VNInfo::KillSet::const_iterator
- I = std::lower_bound(kills.begin(), kills.end(), KillIdx);
- return I != kills.end() && I->killIdx == KillIdx;
- }
-
/// isOnlyLROfValNo - Return true if the specified live range is the only
/// one defined by the its val#.
bool isOnlyLROfValNo(const LiveRange *LR) {
@@ -460,7 +630,8 @@ namespace llvm {
/// MergeInClobberRange - Same as MergeInClobberRanges except it merge in a
/// single LiveRange only.
- void MergeInClobberRange(unsigned Start, unsigned End,
+ void MergeInClobberRange(MachineInstrIndex Start,
+ MachineInstrIndex End,
BumpPtrAllocator &VNInfoAllocator);
/// MergeValueInAsValue - Merge all of the live ranges of a specific val#
@@ -485,58 +656,62 @@ namespace llvm {
bool empty() const { return ranges.empty(); }
- /// beginNumber - Return the lowest numbered slot covered by interval.
- unsigned beginNumber() const {
+ /// beginIndex - Return the lowest numbered slot covered by interval.
+ MachineInstrIndex beginIndex() const {
if (empty())
- return 0;
+ return MachineInstrIndex();
return ranges.front().start;
}
/// endNumber - return the maximum point of the interval of the whole,
/// exclusive.
- unsigned endNumber() const {
+ MachineInstrIndex endIndex() const {
if (empty())
- return 0;
+ return MachineInstrIndex();
return ranges.back().end;
}
- bool expiredAt(unsigned index) const {
- return index >= endNumber();
+ bool expiredAt(MachineInstrIndex index) const {
+ return index >= endIndex();
}
- bool liveAt(unsigned index) const;
+ bool liveAt(MachineInstrIndex index) const;
// liveBeforeAndAt - Check if the interval is live at the index and the
// index just before it. If index is liveAt, check if it starts a new live
// range.If it does, then check if the previous live range ends at index-1.
- bool liveBeforeAndAt(unsigned index) const;
+ bool liveBeforeAndAt(MachineInstrIndex index) const;
/// getLiveRangeContaining - Return the live range that contains the
/// specified index, or null if there is none.
- const LiveRange *getLiveRangeContaining(unsigned Idx) const {
+ const LiveRange *getLiveRangeContaining(MachineInstrIndex Idx) const {
const_iterator I = FindLiveRangeContaining(Idx);
return I == end() ? 0 : &*I;
}
/// getLiveRangeContaining - Return the live range that contains the
/// specified index, or null if there is none.
- LiveRange *getLiveRangeContaining(unsigned Idx) {
+ LiveRange *getLiveRangeContaining(MachineInstrIndex Idx) {
iterator I = FindLiveRangeContaining(Idx);
return I == end() ? 0 : &*I;
}
/// FindLiveRangeContaining - Return an iterator to the live range that
/// contains the specified index, or end() if there is none.
- const_iterator FindLiveRangeContaining(unsigned Idx) const;
+ const_iterator FindLiveRangeContaining(MachineInstrIndex Idx) const;
/// FindLiveRangeContaining - Return an iterator to the live range that
/// contains the specified index, or end() if there is none.
- iterator FindLiveRangeContaining(unsigned Idx);
+ iterator FindLiveRangeContaining(MachineInstrIndex Idx);
+
+ /// findDefinedVNInfo - Find the by the specified
+ /// index (register interval) or defined
+ VNInfo *findDefinedVNInfoForRegInt(MachineInstrIndex Idx) const;
+
+ /// findDefinedVNInfo - Find the VNInfo that's defined by the specified
+ /// register (stack inteval only).
+ VNInfo *findDefinedVNInfoForStackInt(unsigned Reg) const;
- /// findDefinedVNInfo - Find the VNInfo that's defined at the specified
- /// index (register interval) or defined by the specified register (stack
- /// inteval).
- VNInfo *findDefinedVNInfo(unsigned DefIdxOrReg) const;
/// overlaps - Return true if the intersection of the two live intervals is
/// not empty.
@@ -546,7 +721,7 @@ namespace llvm {
/// overlaps - Return true if the live interval overlaps a range specified
/// by [Start, End).
- bool overlaps(unsigned Start, unsigned End) const;
+ bool overlaps(MachineInstrIndex Start, MachineInstrIndex End) const;
/// overlapsFrom - Return true if the intersection of the two live intervals
/// is not empty. The specified iterator is a hint that we can begin
@@ -570,11 +745,12 @@ namespace llvm {
/// isInOneLiveRange - Return true if the range specified is entirely in the
/// a single LiveRange of the live interval.
- bool isInOneLiveRange(unsigned Start, unsigned End);
+ bool isInOneLiveRange(MachineInstrIndex Start, MachineInstrIndex End);
/// removeRange - Remove the specified range from this interval. Note that
/// the range must be a single LiveRange in its entirety.
- void removeRange(unsigned Start, unsigned End, bool RemoveDeadValNo = false);
+ void removeRange(MachineInstrIndex Start, MachineInstrIndex End,
+ bool RemoveDeadValNo = false);
void removeRange(LiveRange LR, bool RemoveDeadValNo = false) {
removeRange(LR.start, LR.end, RemoveDeadValNo);
@@ -597,7 +773,10 @@ namespace llvm {
void ComputeJoinedWeight(const LiveInterval &Other);
bool operator<(const LiveInterval& other) const {
- return beginNumber() < other.beginNumber();
+ const MachineInstrIndex &thisIndex = beginIndex();
+ const MachineInstrIndex &otherIndex = other.beginIndex();
+ return (thisIndex < otherIndex ||
+ (thisIndex == otherIndex && reg < other.reg));
}
void print(raw_ostream &OS, const TargetRegisterInfo *TRI = 0) const;
@@ -606,8 +785,8 @@ namespace llvm {
private:
Ranges::iterator addRangeFrom(LiveRange LR, Ranges::iterator From);
- void extendIntervalEndTo(Ranges::iterator I, unsigned NewEnd);
- Ranges::iterator extendIntervalStartTo(Ranges::iterator I, unsigned NewStr);
+ void extendIntervalEndTo(Ranges::iterator I, MachineInstrIndex NewEnd);
+ Ranges::iterator extendIntervalStartTo(Ranges::iterator I, MachineInstrIndex NewStr);
LiveInterval& operator=(const LiveInterval& rhs); // DO NOT IMPLEMENT
};
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h b/libclamav/c++/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h
index da9ff30..3311788 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h
@@ -40,13 +40,13 @@ namespace llvm {
class TargetInstrInfo;
class TargetRegisterClass;
class VirtRegMap;
- typedef std::pair<unsigned, MachineBasicBlock*> IdxMBBPair;
+ typedef std::pair<MachineInstrIndex, MachineBasicBlock*> IdxMBBPair;
- inline bool operator<(unsigned V, const IdxMBBPair &IM) {
+ inline bool operator<(MachineInstrIndex V, const IdxMBBPair &IM) {
return V < IM.first;
}
- inline bool operator<(const IdxMBBPair &IM, unsigned V) {
+ inline bool operator<(const IdxMBBPair &IM, MachineInstrIndex V) {
return IM.first < V;
}
@@ -71,7 +71,7 @@ namespace llvm {
/// MBB2IdxMap - The indexes of the first and last instructions in the
/// specified basic block.
- std::vector<std::pair<unsigned, unsigned> > MBB2IdxMap;
+ std::vector<std::pair<MachineInstrIndex, MachineInstrIndex> > MBB2IdxMap;
/// Idx2MBBMap - Sorted list of pairs of index of first instruction
/// and MBB id.
@@ -80,7 +80,7 @@ namespace llvm {
/// FunctionSize - The number of instructions present in the function
uint64_t FunctionSize;
- typedef DenseMap<const MachineInstr*, unsigned> Mi2IndexMap;
+ typedef DenseMap<const MachineInstr*, MachineInstrIndex> Mi2IndexMap;
Mi2IndexMap mi2iMap_;
typedef std::vector<MachineInstr*> Index2MiMap;
@@ -89,11 +89,16 @@ namespace llvm {
typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
Reg2IntervalMap r2iMap_;
- DenseMap<MachineBasicBlock*, unsigned> terminatorGaps;
+ DenseMap<MachineBasicBlock*, MachineInstrIndex> terminatorGaps;
+ /// phiJoinCopies - Copy instructions which are PHI joins.
+ SmallVector<MachineInstr*, 16> phiJoinCopies;
+
+ /// allocatableRegs_ - A bit vector of allocatable registers.
BitVector allocatableRegs_;
- std::vector<MachineInstr*> ClonedMIs;
+ /// CloneMIs - A list of clones as result of re-materialization.
+ std::vector<MachineInstr*> CloneMIs;
typedef LiveInterval::InstrSlots InstrSlots;
@@ -101,23 +106,40 @@ namespace llvm {
static char ID; // Pass identification, replacement for typeid
LiveIntervals() : MachineFunctionPass(&ID) {}
- static unsigned getBaseIndex(unsigned index) {
- return index - (index % InstrSlots::NUM);
+ MachineInstrIndex getBaseIndex(MachineInstrIndex index) {
+ return MachineInstrIndex(index, MachineInstrIndex::LOAD);
+ }
+ MachineInstrIndex getBoundaryIndex(MachineInstrIndex index) {
+ return MachineInstrIndex(index,
+ (MachineInstrIndex::Slot)(MachineInstrIndex::NUM - 1));
}
- static unsigned getBoundaryIndex(unsigned index) {
- return getBaseIndex(index + InstrSlots::NUM - 1);
+ MachineInstrIndex getLoadIndex(MachineInstrIndex index) {
+ return MachineInstrIndex(index, MachineInstrIndex::LOAD);
}
- static unsigned getLoadIndex(unsigned index) {
- return getBaseIndex(index) + InstrSlots::LOAD;
+ MachineInstrIndex getUseIndex(MachineInstrIndex index) {
+ return MachineInstrIndex(index, MachineInstrIndex::USE);
}
- static unsigned getUseIndex(unsigned index) {
- return getBaseIndex(index) + InstrSlots::USE;
+ MachineInstrIndex getDefIndex(MachineInstrIndex index) {
+ return MachineInstrIndex(index, MachineInstrIndex::DEF);
}
- static unsigned getDefIndex(unsigned index) {
- return getBaseIndex(index) + InstrSlots::DEF;
+ MachineInstrIndex getStoreIndex(MachineInstrIndex index) {
+ return MachineInstrIndex(index, MachineInstrIndex::STORE);
+ }
+
+ MachineInstrIndex getNextSlot(MachineInstrIndex m) const {
+ return m.nextSlot_();
}
- static unsigned getStoreIndex(unsigned index) {
- return getBaseIndex(index) + InstrSlots::STORE;
+
+ MachineInstrIndex getNextIndex(MachineInstrIndex m) const {
+ return m.nextIndex_();
+ }
+
+ MachineInstrIndex getPrevSlot(MachineInstrIndex m) const {
+ return m.prevSlot_();
+ }
+
+ MachineInstrIndex getPrevIndex(MachineInstrIndex m) const {
+ return m.prevIndex_();
}
static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
@@ -150,20 +172,20 @@ namespace llvm {
/// getMBBStartIdx - Return the base index of the first instruction in the
/// specified MachineBasicBlock.
- unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
+ MachineInstrIndex getMBBStartIdx(MachineBasicBlock *MBB) const {
return getMBBStartIdx(MBB->getNumber());
}
- unsigned getMBBStartIdx(unsigned MBBNo) const {
+ MachineInstrIndex getMBBStartIdx(unsigned MBBNo) const {
assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
return MBB2IdxMap[MBBNo].first;
}
/// getMBBEndIdx - Return the store index of the last instruction in the
/// specified MachineBasicBlock.
- unsigned getMBBEndIdx(MachineBasicBlock *MBB) const {
+ MachineInstrIndex getMBBEndIdx(MachineBasicBlock *MBB) const {
return getMBBEndIdx(MBB->getNumber());
}
- unsigned getMBBEndIdx(unsigned MBBNo) const {
+ MachineInstrIndex getMBBEndIdx(unsigned MBBNo) const {
assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
return MBB2IdxMap[MBBNo].second;
}
@@ -184,7 +206,7 @@ namespace llvm {
/// getMBBFromIndex - given an index in any instruction of an
/// MBB return a pointer the MBB
- MachineBasicBlock* getMBBFromIndex(unsigned index) const {
+ MachineBasicBlock* getMBBFromIndex(MachineInstrIndex index) const {
std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), index);
// Take the pair containing the index
@@ -192,14 +214,14 @@ namespace llvm {
((I != Idx2MBBMap.end() && I->first > index) ||
(I == Idx2MBBMap.end() && Idx2MBBMap.size()>0)) ? (I-1): I;
- assert(J != Idx2MBBMap.end() && J->first < index+1 &&
+ assert(J != Idx2MBBMap.end() && J->first <= index &&
index <= getMBBEndIdx(J->second) &&
"index does not correspond to an MBB");
return J->second;
}
/// getInstructionIndex - returns the base index of instr
- unsigned getInstructionIndex(const MachineInstr* instr) const {
+ MachineInstrIndex getInstructionIndex(const MachineInstr* instr) const {
Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
assert(it != mi2iMap_.end() && "Invalid instruction!");
return it->second;
@@ -207,48 +229,50 @@ namespace llvm {
/// getInstructionFromIndex - given an index in any slot of an
/// instruction return a pointer the instruction
- MachineInstr* getInstructionFromIndex(unsigned index) const {
- index /= InstrSlots::NUM; // convert index to vector index
- assert(index < i2miMap_.size() &&
+ MachineInstr* getInstructionFromIndex(MachineInstrIndex index) const {
+ // convert index to vector index
+ unsigned i = index.getVecIndex();
+ assert(i < i2miMap_.size() &&
"index does not correspond to an instruction");
- return i2miMap_[index];
+ return i2miMap_[i];
}
/// hasGapBeforeInstr - Return true if the previous instruction slot,
/// i.e. Index - InstrSlots::NUM, is not occupied.
- bool hasGapBeforeInstr(unsigned Index) {
- Index = getBaseIndex(Index - InstrSlots::NUM);
+ bool hasGapBeforeInstr(MachineInstrIndex Index) {
+ Index = getBaseIndex(getPrevIndex(Index));
return getInstructionFromIndex(Index) == 0;
}
/// hasGapAfterInstr - Return true if the successive instruction slot,
/// i.e. Index + InstrSlots::Num, is not occupied.
- bool hasGapAfterInstr(unsigned Index) {
- Index = getBaseIndex(Index + InstrSlots::NUM);
+ bool hasGapAfterInstr(MachineInstrIndex Index) {
+ Index = getBaseIndex(getNextIndex(Index));
return getInstructionFromIndex(Index) == 0;
}
/// findGapBeforeInstr - Find an empty instruction slot before the
/// specified index. If "Furthest" is true, find one that's furthest
/// away from the index (but before any index that's occupied).
- unsigned findGapBeforeInstr(unsigned Index, bool Furthest = false) {
- Index = getBaseIndex(Index - InstrSlots::NUM);
+ MachineInstrIndex findGapBeforeInstr(MachineInstrIndex Index,
+ bool Furthest = false) {
+ Index = getBaseIndex(getPrevIndex(Index));
if (getInstructionFromIndex(Index))
- return 0; // No gap!
+ return MachineInstrIndex(); // No gap!
if (!Furthest)
return Index;
- unsigned PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
+ MachineInstrIndex PrevIndex = getBaseIndex(getPrevIndex(Index));
while (getInstructionFromIndex(Index)) {
Index = PrevIndex;
- PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
+ PrevIndex = getBaseIndex(getPrevIndex(Index));
}
return Index;
}
/// InsertMachineInstrInMaps - Insert the specified machine instruction
/// into the instruction index map at the given index.
- void InsertMachineInstrInMaps(MachineInstr *MI, unsigned Index) {
- i2miMap_[Index / InstrSlots::NUM] = MI;
+ void InsertMachineInstrInMaps(MachineInstr *MI, MachineInstrIndex Index) {
+ i2miMap_[Index.getVecIndex()] = MI;
Mi2IndexMap::iterator it = mi2iMap_.find(MI);
assert(it == mi2iMap_.end() && "Already in map!");
mi2iMap_[MI] = Index;
@@ -268,12 +292,12 @@ namespace llvm {
/// findLiveInMBBs - Given a live range, if the value of the range
/// is live in any MBB returns true as well as the list of basic blocks
/// in which the value is live.
- bool findLiveInMBBs(unsigned Start, unsigned End,
+ bool findLiveInMBBs(MachineInstrIndex Start, MachineInstrIndex End,
SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
/// findReachableMBBs - Return a list MBB that can be reached via any
/// branch or fallthroughs. Return true if the list is not empty.
- bool findReachableMBBs(unsigned Start, unsigned End,
+ bool findReachableMBBs(MachineInstrIndex Start, MachineInstrIndex End,
SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
// Interval creation
@@ -292,7 +316,7 @@ namespace llvm {
/// addLiveRangeToEndOfBlock - Given a register and an instruction,
/// adds a live range from that instruction to the end of its MBB.
LiveRange addLiveRangeToEndOfBlock(unsigned reg,
- MachineInstr* startInst);
+ MachineInstr* startInst);
// Interval removal
@@ -315,7 +339,7 @@ namespace llvm {
// MachineInstr -> index mappings
Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
if (mi2i != mi2iMap_.end()) {
- i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
+ i2miMap_[mi2i->second.index/InstrSlots::NUM] = 0;
mi2iMap_.erase(mi2i);
}
}
@@ -326,10 +350,10 @@ namespace llvm {
Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
if (mi2i == mi2iMap_.end())
return;
- i2miMap_[mi2i->second/InstrSlots::NUM] = NewMI;
+ i2miMap_[mi2i->second.index/InstrSlots::NUM] = NewMI;
Mi2IndexMap::iterator it = mi2iMap_.find(MI);
assert(it != mi2iMap_.end() && "Invalid instruction!");
- unsigned Index = it->second;
+ MachineInstrIndex Index = it->second;
mi2iMap_.erase(it);
mi2iMap_[NewMI] = Index;
}
@@ -408,32 +432,40 @@ namespace llvm {
private:
/// computeIntervals - Compute live intervals.
void computeIntervals();
-
+
+ bool isProfitableToCoalesce(LiveInterval &DstInt, LiveInterval &SrcInt,
+ SmallVector<MachineInstr*,16> &IdentCopies,
+ SmallVector<MachineInstr*,16> &OtherCopies);
+
+ void performEarlyCoalescing();
+
/// handleRegisterDef - update intervals for a register def
/// (calls handlePhysicalRegisterDef and
/// handleVirtualRegisterDef)
void handleRegisterDef(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator MI, unsigned MIIdx,
+ MachineBasicBlock::iterator MI,
+ MachineInstrIndex MIIdx,
MachineOperand& MO, unsigned MOIdx);
/// handleVirtualRegisterDef - update intervals for a virtual
/// register def
void handleVirtualRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI,
- unsigned MIIdx, MachineOperand& MO,
- unsigned MOIdx, LiveInterval& interval);
+ MachineInstrIndex MIIdx, MachineOperand& MO,
+ unsigned MOIdx,
+ LiveInterval& interval);
/// handlePhysicalRegisterDef - update intervals for a physical register
/// def.
void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
MachineBasicBlock::iterator mi,
- unsigned MIIdx, MachineOperand& MO,
+ MachineInstrIndex MIIdx, MachineOperand& MO,
LiveInterval &interval,
MachineInstr *CopyMI);
/// handleLiveInRegister - Create interval for a livein register.
void handleLiveInRegister(MachineBasicBlock* mbb,
- unsigned MIIdx,
+ MachineInstrIndex MIIdx,
LiveInterval &interval, bool isAlias = false);
/// getReMatImplicitUse - If the remat definition MI has one (for now, we
@@ -446,7 +478,7 @@ namespace llvm {
/// which reaches the given instruction also reaches the specified use
/// index.
bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
- unsigned UseIdx) const;
+ MachineInstrIndex UseIdx) const;
/// isReMaterializable - Returns true if the definition MI of the specified
/// val# of the specified interval is re-materializable. Also returns true
@@ -461,9 +493,9 @@ namespace llvm {
/// MI. If it is successul, MI is updated with the newly created MI and
/// returns true.
bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
- MachineInstr *DefMI, unsigned InstrIdx,
+ MachineInstr *DefMI, MachineInstrIndex InstrIdx,
SmallVector<unsigned, 2> &Ops,
- bool isSS, int Slot, unsigned Reg);
+ bool isSS, int FrameIndex, unsigned Reg);
/// canFoldMemoryOperand - Return true if the specified load / store
/// folding is possible.
@@ -474,7 +506,8 @@ namespace llvm {
/// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
/// VNInfo that's after the specified index but is within the basic block.
bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
- MachineBasicBlock *MBB, unsigned Idx) const;
+ MachineBasicBlock *MBB,
+ MachineInstrIndex Idx) const;
/// hasAllocatableSuperReg - Return true if the specified physical register
/// has any super register that's allocatable.
@@ -482,16 +515,17 @@ namespace llvm {
/// SRInfo - Spill / restore info.
struct SRInfo {
- int index;
+ MachineInstrIndex index;
unsigned vreg;
bool canFold;
- SRInfo(int i, unsigned vr, bool f) : index(i), vreg(vr), canFold(f) {};
+ SRInfo(MachineInstrIndex i, unsigned vr, bool f)
+ : index(i), vreg(vr), canFold(f) {}
};
- bool alsoFoldARestore(int Id, int index, unsigned vr,
+ bool alsoFoldARestore(int Id, MachineInstrIndex index, unsigned vr,
BitVector &RestoreMBBs,
DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
- void eraseRestoreInfo(int Id, int index, unsigned vr,
+ void eraseRestoreInfo(int Id, MachineInstrIndex index, unsigned vr,
BitVector &RestoreMBBs,
DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
@@ -510,8 +544,9 @@ namespace llvm {
/// functions for addIntervalsForSpills to rewrite uses / defs for the given
/// live range.
bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
- bool TrySplit, unsigned index, unsigned end, MachineInstr *MI,
- MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
+ bool TrySplit, MachineInstrIndex index, MachineInstrIndex end,
+ MachineInstr *MI, MachineInstr *OrigDefMI, MachineInstr *DefMI,
+ unsigned Slot, int LdSlot,
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
VirtRegMap &vrm, const TargetRegisterClass* rc,
SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
@@ -533,7 +568,8 @@ namespace llvm {
static LiveInterval* createInterval(unsigned Reg);
- void printRegName(unsigned reg) const;
+ void printInstrs(raw_ostream &O) const;
+ void dumpInstrs() const;
};
} // End llvm namespace
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/LiveVariables.h b/libclamav/c++/llvm/include/llvm/CodeGen/LiveVariables.h
index 1c914d6..172fb75 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/LiveVariables.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/LiveVariables.h
@@ -34,6 +34,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseBitVector.h"
@@ -148,16 +149,14 @@ private: // Intermediate data structures
bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
- void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
+ void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
+ SmallVector<unsigned, 4> &Defs);
+ void UpdatePhysRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs);
/// FindLastPartialDef - Return the last partial def of the specified register.
- /// Also returns the sub-register that's defined.
- MachineInstr *FindLastPartialDef(unsigned Reg, unsigned &PartDefReg);
-
- /// hasRegisterUseBelow - Return true if the specified register is used after
- /// the current instruction and before it's next definition.
- bool hasRegisterUseBelow(unsigned Reg, MachineBasicBlock::iterator I,
- MachineBasicBlock *MBB);
+ /// Also returns the sub-registers that're defined by the instruction.
+ MachineInstr *FindLastPartialDef(unsigned Reg,
+ SmallSet<unsigned,4> &PartDefRegs);
/// analyzePHINodes - Gather information about the PHI nodes in here. In
/// particular, we want to map the variable information of a virtual
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/MachineConstantPool.h b/libclamav/c++/llvm/include/llvm/CodeGen/MachineConstantPool.h
index 59d8e63..8d6c1d1 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/MachineConstantPool.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/MachineConstantPool.h
@@ -89,7 +89,7 @@ public:
MachineConstantPoolEntry(MachineConstantPoolValue *V, unsigned A)
: Alignment(A) {
Val.MachineCPVal = V;
- Alignment |= 1 << (sizeof(unsigned)*CHAR_BIT-1);
+ Alignment |= 1U << (sizeof(unsigned)*CHAR_BIT-1);
}
bool isMachineConstantPoolEntry() const {
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/MachineFrameInfo.h b/libclamav/c++/llvm/include/llvm/CodeGen/MachineFrameInfo.h
index 05ab499..b5479ba 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/MachineFrameInfo.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/MachineFrameInfo.h
@@ -133,11 +133,14 @@ class MachineFrameInfo {
uint64_t StackSize;
/// OffsetAdjustment - The amount that a frame offset needs to be adjusted to
- /// have the actual offset from the stack/frame pointer. The calculation is
- /// MFI->getObjectOffset(Index) + StackSize - TFI.getOffsetOfLocalArea() +
- /// OffsetAdjustment. If OffsetAdjustment is zero (default) then offsets are
- /// away from TOS. If OffsetAdjustment == StackSize then offsets are toward
- /// TOS.
+ /// have the actual offset from the stack/frame pointer. The exact usage of
+ /// this is target-dependent, but it is typically used to adjust between
+ /// SP-relative and FP-relative offsets. E.G., if objects are accessed via
+ /// SP then OffsetAdjustment is zero; if FP is used, OffsetAdjustment is set
+ /// to the distance between the initial SP and the value in FP. For many
+ /// targets, this value is only used when generating debug info (via
+ /// TargetRegisterInfo::getFrameIndexOffset); when generating code, the
+ /// corresponding adjustments are performed directly.
int OffsetAdjustment;
/// MaxAlignment - The prolog/epilog code inserter may process objects
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/MachineFunction.h b/libclamav/c++/llvm/include/llvm/CodeGen/MachineFunction.h
index ce0a208..8b881f5 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -27,6 +27,7 @@
namespace llvm {
+class Value;
class Function;
class MachineRegisterInfo;
class MachineFrameInfo;
@@ -63,7 +64,7 @@ private:
/// of type are accessed/created with MF::getInfo and destroyed when the
/// MachineFunction is destroyed.
struct MachineFunctionInfo {
- virtual ~MachineFunctionInfo() {}
+ virtual ~MachineFunctionInfo();
};
class MachineFunction {
@@ -159,8 +160,8 @@ public:
///
void setAlignment(unsigned A) { Alignment = A; }
- /// MachineFunctionInfo - Keep track of various per-function pieces of
- /// information for backends that would like to do so.
+ /// getInfo - Keep track of various per-function pieces of information for
+ /// backends that would like to do so.
///
template<typename Ty>
Ty *getInfo() {
@@ -320,16 +321,28 @@ public:
///
void DeleteMachineBasicBlock(MachineBasicBlock *MBB);
+ /// getMachineMemOperand - Allocate a new MachineMemOperand.
+ /// MachineMemOperands are owned by the MachineFunction and need not be
+ /// explicitly deallocated.
+ MachineMemOperand *getMachineMemOperand(const Value *v, unsigned f,
+ int64_t o, uint64_t s,
+ unsigned base_alignment);
+
+ /// getMachineMemOperand - Allocate a new MachineMemOperand by copying
+ /// an existing one, adjusting by an offset and using the given EVT.
+ /// MachineMemOperands are owned by the MachineFunction and need not be
+ /// explicitly deallocated.
+ MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
+ int64_t Offset, uint64_t Size);
+
+ /// allocateMemRefsArray - Allocate an array to hold MachineMemOperand
+ /// pointers. This array is owned by the MachineFunction.
+ MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num);
+
//===--------------------------------------------------------------------===//
// Debug location.
//
- /// getOrCreateDebugLocID - Look up the DebugLocTuple index with the given
- /// source file, line, and column. If none currently exists, create a new
- /// DebugLocTuple, and insert it into the DebugIdMap.
- unsigned getOrCreateDebugLocID(MDNode *CompileUnit,
- unsigned Line, unsigned Col);
-
/// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc object.
DebugLocTuple getDebugLocTuple(DebugLoc DL) const;
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/MachineInstr.h b/libclamav/c++/llvm/include/llvm/CodeGen/MachineInstr.h
index 3b4411a..66af73e 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -20,10 +20,8 @@
#include "llvm/ADT/ilist_node.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineOperand.h"
-#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/Target/TargetInstrDesc.h"
#include "llvm/Support/DebugLoc.h"
-#include <list>
#include <vector>
namespace llvm {
@@ -32,17 +30,23 @@ class TargetInstrDesc;
class TargetInstrInfo;
class TargetRegisterInfo;
class MachineFunction;
+class MachineMemOperand;
//===----------------------------------------------------------------------===//
/// MachineInstr - Representation of each machine instruction.
///
class MachineInstr : public ilist_node<MachineInstr> {
+public:
+ typedef MachineMemOperand **mmo_iterator;
+
+private:
const TargetInstrDesc *TID; // Instruction descriptor.
unsigned short NumImplicitOps; // Number of implicit operands (which
// are determined at construction time).
std::vector<MachineOperand> Operands; // the operands
- std::list<MachineMemOperand> MemOperands; // information on memory references
+ mmo_iterator MemRefs; // information on memory references
+ mmo_iterator MemRefsEnd;
MachineBasicBlock *Parent; // Pointer to the owning basic block.
DebugLoc debugLoc; // Source line information.
@@ -132,21 +136,14 @@ public:
unsigned getNumExplicitOperands() const;
/// Access to memory operands of the instruction
- std::list<MachineMemOperand>::iterator memoperands_begin()
- { return MemOperands.begin(); }
- std::list<MachineMemOperand>::iterator memoperands_end()
- { return MemOperands.end(); }
- std::list<MachineMemOperand>::const_iterator memoperands_begin() const
- { return MemOperands.begin(); }
- std::list<MachineMemOperand>::const_iterator memoperands_end() const
- { return MemOperands.end(); }
- bool memoperands_empty() const { return MemOperands.empty(); }
+ mmo_iterator memoperands_begin() const { return MemRefs; }
+ mmo_iterator memoperands_end() const { return MemRefsEnd; }
+ bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
/// hasOneMemOperand - Return true if this instruction has exactly one
/// MachineMemOperand.
bool hasOneMemOperand() const {
- return !memoperands_empty() &&
- next(memoperands_begin()) == memoperands_end();
+ return MemRefsEnd - MemRefs == 1;
}
/// isIdenticalTo - Return true if this instruction is identical to (same
@@ -208,7 +205,7 @@ public:
}
/// findRegisterUseOperandIdx() - Returns the operand index that is a use of
- /// the specific register or -1 if it is not found. It further tightening
+ /// the specific register or -1 if it is not found. It further tightens
/// the search criteria to a use that kills the register if isKill is true.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
const TargetRegisterInfo *TRI = NULL) const;
@@ -319,13 +316,17 @@ public:
///
void RemoveOperand(unsigned i);
- /// addMemOperand - Add a MachineMemOperand to the machine instruction,
- /// referencing arbitrary storage.
- void addMemOperand(MachineFunction &MF,
- const MachineMemOperand &MO);
+ /// addMemOperand - Add a MachineMemOperand to the machine instruction.
+ /// This function should be used only occasionally. The setMemRefs function
+ /// is the primary method for setting up a MachineInstr's MemRefs list.
+ void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
- /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
- void clearMemOperands(MachineFunction &MF);
+ /// setMemRefs - Assign this MachineInstr's memory reference descriptor
+ /// list. This does not transfer ownership.
+ void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
+ MemRefs = NewMemRefs;
+ MemRefsEnd = NewMemRefsEnd;
+ }
private:
/// getRegInfo - If this instruction is embedded into a MachineFunction,
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/libclamav/c++/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
index 73611fe..7f681d7 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -109,20 +109,19 @@ public:
}
const MachineInstrBuilder &addMetadata(MDNode *N,
- int64_t Offset = 0,
- unsigned char TargetFlags = 0) const {
+ int64_t Offset = 0,
+ unsigned char TargetFlags = 0) const {
MI->addOperand(MachineOperand::CreateMDNode(N, Offset, TargetFlags));
return *this;
}
const MachineInstrBuilder &addExternalSymbol(const char *FnName,
- int64_t Offset = 0,
unsigned char TargetFlags = 0) const {
- MI->addOperand(MachineOperand::CreateES(FnName, Offset, TargetFlags));
+ MI->addOperand(MachineOperand::CreateES(FnName, TargetFlags));
return *this;
}
- const MachineInstrBuilder &addMemOperand(const MachineMemOperand &MMO) const {
+ const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
MI->addMemOperand(*MI->getParent()->getParent(), MMO);
return *this;
}
@@ -192,7 +191,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
/// BuildMI - This version of the builder inserts the newly-built
/// instruction at the end of the given MachineBasicBlock, and sets up the first
-/// operand as a destination virtual register.
+/// operand as a destination virtual register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
DebugLoc DL,
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/MachineMemOperand.h b/libclamav/c++/llvm/include/llvm/CodeGen/MachineMemOperand.h
index 4388c0a..b7e267d 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/MachineMemOperand.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/MachineMemOperand.h
@@ -20,6 +20,7 @@ namespace llvm {
class Value;
class FoldingSetNodeID;
+class raw_ostream;
//===----------------------------------------------------------------------===//
/// MachineMemOperand - A description of a memory reference used in the backend.
@@ -47,14 +48,17 @@ public:
};
/// MachineMemOperand - Construct an MachineMemOperand object with the
- /// specified address Value, flags, offset, size, and alignment.
+ /// specified address Value, flags, offset, size, and base alignment.
MachineMemOperand(const Value *v, unsigned int f, int64_t o, uint64_t s,
- unsigned int a);
+ unsigned int base_alignment);
- /// getValue - Return the base address of the memory access.
- /// Special values are PseudoSourceValue::FPRel, PseudoSourceValue::SPRel,
- /// and the other PseudoSourceValue members which indicate references to
- /// frame/stack pointer relative references and other special references.
+ /// getValue - Return the base address of the memory access. This may either
+ /// be a normal LLVM IR Value, or one of the special values used in CodeGen.
+ /// Special values are those obtained via
+ /// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, and
+ /// other PseudoSourceValue member functions which return objects which stand
+ /// for frame/stack pointer relative references and other special references
+ /// which are not representable in the high-level IR.
const Value *getValue() const { return V; }
/// getFlags - Return the raw flags of the source value, \see MemOperandFlags.
@@ -69,18 +73,34 @@ public:
uint64_t getSize() const { return Size; }
/// getAlignment - Return the minimum known alignment in bytes of the
- /// memory reference.
- unsigned int getAlignment() const { return (1u << (Flags >> 3)) >> 1; }
+ /// actual memory reference.
+ uint64_t getAlignment() const;
+
+ /// getBaseAlignment - Return the minimum known alignment in bytes of the
+ /// base address, without the offset.
+ uint64_t getBaseAlignment() const { return (1u << (Flags >> 3)) >> 1; }
bool isLoad() const { return Flags & MOLoad; }
bool isStore() const { return Flags & MOStore; }
bool isVolatile() const { return Flags & MOVolatile; }
+ /// refineAlignment - Update this MachineMemOperand to reflect the alignment
+ /// of MMO, if it has a greater alignment. This must only be used when the
+ /// new alignment applies to all users of this MachineMemOperand.
+ void refineAlignment(const MachineMemOperand *MMO);
+
+ /// setValue - Change the SourceValue for this MachineMemOperand. This
+ /// should only be used when an object is being relocated and all references
+ /// to it are being updated.
+ void setValue(const Value *NewSV) { V = NewSV; }
+
/// Profile - Gather unique data for the object.
///
void Profile(FoldingSetNodeID &ID) const;
};
+raw_ostream &operator<<(raw_ostream &OS, const MachineMemOperand &MRO);
+
} // End llvm namespace
#endif
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/MachineModuleInfo.h b/libclamav/c++/llvm/include/llvm/CodeGen/MachineModuleInfo.h
index 3618898..b7b9019 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/MachineModuleInfo.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/MachineModuleInfo.h
@@ -48,12 +48,25 @@ namespace llvm {
//===----------------------------------------------------------------------===//
// Forward declarations.
class Constant;
+class MDNode;
class GlobalVariable;
class MachineBasicBlock;
class MachineFunction;
class Module;
class PointerType;
class StructType;
+
+
+/// MachineModuleInfoImpl - This class can be derived from and used by targets
+/// to hold private target-specific information for each Module. Objects of
+/// type are accessed/created with MMI::getInfo and destroyed when the
+/// MachineModuleInfo is destroyed.
+class MachineModuleInfoImpl {
+public:
+ virtual ~MachineModuleInfoImpl();
+};
+
+
//===----------------------------------------------------------------------===//
/// LandingPadInfo - This structure is used to retain landing pad info for
@@ -80,7 +93,11 @@ struct LandingPadInfo {
/// schemes and reformated for specific use.
///
class MachineModuleInfo : public ImmutablePass {
-private:
+ /// ObjFileMMI - This is the object-file-format-specific implementation of
+ /// MachineModuleInfoImpl, which lets targets accumulate whatever info they
+ /// want.
+ MachineModuleInfoImpl *ObjFileMMI;
+
// LabelIDList - One entry per assigned label. Normally the entry is equal to
// the list index(+1). If the entry is zero then the label has been deleted.
// Any other value indicates the label has been deleted by is mapped to
@@ -126,28 +143,45 @@ private:
/// DbgInfoAvailable - True if debugging information is available
/// in this module.
bool DbgInfoAvailable;
+
public:
static char ID; // Pass identification, replacement for typeid
+ typedef DenseMap<MDNode *, std::pair<MDNode *, unsigned> > VariableDbgInfoMapTy;
+ VariableDbgInfoMapTy VariableDbgInfo;
+
MachineModuleInfo();
~MachineModuleInfo();
- /// doInitialization - Initialize the state for a new module.
- ///
bool doInitialization();
-
- /// doFinalization - Tear down the state after completion of a module.
- ///
bool doFinalization();
-
+
/// BeginFunction - Begin gathering function meta information.
///
- void BeginFunction(MachineFunction *MF);
+ void BeginFunction(MachineFunction *) {}
/// EndFunction - Discard function meta information.
///
void EndFunction();
+ /// getInfo - Keep track of various per-function pieces of information for
+ /// backends that would like to do so.
+ ///
+ template<typename Ty>
+ Ty &getObjFileInfo() {
+ if (ObjFileMMI == 0)
+ ObjFileMMI = new Ty(*this);
+
+ assert((void*)dynamic_cast<Ty*>(ObjFileMMI) == (void*)ObjFileMMI &&
+ "Invalid concrete type or multiple inheritence for getInfo");
+ return *static_cast<Ty*>(ObjFileMMI);
+ }
+
+ template<typename Ty>
+ const Ty &getObjFileInfo() const {
+ return const_cast<MachineModuleInfo*>(this)->getObjFileInfo<Ty>();
+ }
+
/// AnalyzeModule - Scan the module for global debug information.
///
void AnalyzeModule(Module &M);
@@ -296,6 +330,15 @@ public:
/// of one is required to emit exception handling info.
Function *getPersonality() const;
+ /// setVariableDbgInfo - Collect information used to emit debugging information
+ /// of a variable.
+ void setVariableDbgInfo(MDNode *N, MDNode *L, unsigned S) {
+ if (N && L)
+ VariableDbgInfo[N] = std::make_pair(L, S);
+ }
+
+ VariableDbgInfoMapTy &getVariableDbgInfo() { return VariableDbgInfo; }
+
}; // End class MachineModuleInfo
} // End llvm namespace
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/MachineModuleInfoImpls.h b/libclamav/c++/llvm/include/llvm/CodeGen/MachineModuleInfoImpls.h
new file mode 100644
index 0000000..44813cb
--- /dev/null
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/MachineModuleInfoImpls.h
@@ -0,0 +1,79 @@
+//===-- llvm/CodeGen/MachineModuleInfoImpls.h -------------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines object-file format specific implementations of
+// MachineModuleInfoImpl.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_MACHINEMODULEINFOIMPLS_H
+#define LLVM_CODEGEN_MACHINEMODULEINFOIMPLS_H
+
+#include "llvm/CodeGen/MachineModuleInfo.h"
+
+namespace llvm {
+ class MCSymbol;
+
+ /// MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation
+ /// for MachO targets.
+ class MachineModuleInfoMachO : public MachineModuleInfoImpl {
+ /// FnStubs - Darwin '$stub' stubs. The key is something like "Lfoo$stub",
+ /// the value is something like "_foo".
+ DenseMap<const MCSymbol*, const MCSymbol*> FnStubs;
+
+ /// GVStubs - Darwin '$non_lazy_ptr' stubs. The key is something like
+ /// "Lfoo$non_lazy_ptr", the value is something like "_foo".
+ DenseMap<const MCSymbol*, const MCSymbol*> GVStubs;
+
+ /// HiddenGVStubs - Darwin '$non_lazy_ptr' stubs. The key is something like
+ /// "Lfoo$non_lazy_ptr", the value is something like "_foo". Unlike GVStubs
+ /// these are for things with hidden visibility.
+ DenseMap<const MCSymbol*, const MCSymbol*> HiddenGVStubs;
+
+ virtual void Anchor(); // Out of line virtual method.
+ public:
+ MachineModuleInfoMachO(const MachineModuleInfo &) {}
+
+ const MCSymbol *&getFnStubEntry(const MCSymbol *Sym) {
+ assert(Sym && "Key cannot be null");
+ return FnStubs[Sym];
+ }
+
+ const MCSymbol *&getGVStubEntry(const MCSymbol *Sym) {
+ assert(Sym && "Key cannot be null");
+ return GVStubs[Sym];
+ }
+
+ const MCSymbol *&getHiddenGVStubEntry(const MCSymbol *Sym) {
+ assert(Sym && "Key cannot be null");
+ return HiddenGVStubs[Sym];
+ }
+
+ /// Accessor methods to return the set of stubs in sorted order.
+ typedef std::vector<std::pair<const MCSymbol*, const MCSymbol*> >
+ SymbolListTy;
+
+ SymbolListTy GetFnStubList() const {
+ return GetSortedStubs(FnStubs);
+ }
+ SymbolListTy GetGVStubList() const {
+ return GetSortedStubs(GVStubs);
+ }
+ SymbolListTy GetHiddenGVStubList() const {
+ return GetSortedStubs(HiddenGVStubs);
+ }
+
+ private:
+ static SymbolListTy
+ GetSortedStubs(const DenseMap<const MCSymbol*, const MCSymbol*> &Map);
+ };
+
+} // end namespace llvm
+
+#endif
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/MachineOperand.h b/libclamav/c++/llvm/include/llvm/CodeGen/MachineOperand.h
index e18cc86..f715c44 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/MachineOperand.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/MachineOperand.h
@@ -110,7 +110,7 @@ private:
GlobalValue *GV; // For MO_GlobalAddress.
MDNode *Node; // For MO_Metadata.
} Val;
- int64_t Offset; // An offset from the object.
+ int64_t Offset; // An offset from the object.
} OffsetedInfo;
} Contents;
@@ -298,6 +298,8 @@ public:
return Contents.OffsetedInfo.Val.Node;
}
+ /// getOffset - Return the offset from the symbol in this operand. This always
+ /// returns 0 for ExternalSymbol operands.
int64_t getOffset() const {
assert((isGlobal() || isSymbol() || isCPI()) &&
"Wrong MachineOperand accessor");
@@ -432,11 +434,11 @@ public:
Op.setTargetFlags(TargetFlags);
return Op;
}
- static MachineOperand CreateES(const char *SymName, int64_t Offset = 0,
+ static MachineOperand CreateES(const char *SymName,
unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_ExternalSymbol);
Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
- Op.setOffset(Offset);
+ Op.setOffset(0); // Offset is always 0.
Op.setTargetFlags(TargetFlags);
return Op;
}
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/Passes.h b/libclamav/c++/llvm/include/llvm/CodeGen/Passes.h
index b0db4c9..1e7115e 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/Passes.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/Passes.h
@@ -87,12 +87,6 @@ namespace llvm {
///
FunctionPass *createRegisterAllocator();
- /// SimpleRegisterAllocation Pass - This pass converts the input machine code
- /// from SSA form to use explicit registers by spilling every register. Wow,
- /// great policy huh?
- ///
- FunctionPass *createSimpleRegisterAllocator();
-
/// LocalRegisterAllocation Pass - This pass register allocates the input code
/// a basic block at a time, yielding code better than the simple register
/// allocator, but not as good as a global allocator.
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/PseudoSourceValue.h b/libclamav/c++/llvm/include/llvm/CodeGen/PseudoSourceValue.h
index 3ad2502..c6be645 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/PseudoSourceValue.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/PseudoSourceValue.h
@@ -25,18 +25,17 @@ namespace llvm {
/// stack frame (e.g., a spill slot), below the stack frame (e.g., argument
/// space), or constant pool.
class PseudoSourceValue : public Value {
+ private:
+ /// printCustom - Implement printing for PseudoSourceValue. This is called
+ /// from Value::print or Value's operator<<.
+ ///
+ virtual void printCustom(raw_ostream &O) const;
+
public:
PseudoSourceValue();
- /// dump - Support for debugging, callable in GDB: V->dump()
- //
- virtual void dump() const;
-
- /// print - Implement operator<< on PseudoSourceValue.
- ///
- virtual void print(raw_ostream &OS) const;
-
- /// isConstant - Test whether this PseudoSourceValue has a constant value.
+ /// isConstant - Test whether the memory pointed to by this
+ /// PseudoSourceValue has a constant value.
///
virtual bool isConstant(const MachineFrameInfo *) const;
@@ -52,18 +51,21 @@ namespace llvm {
/// e.g., a spill slot.
static const PseudoSourceValue *getFixedStack(int FI);
- /// A source value referencing the area below the stack frame of a function,
- /// e.g., the argument space.
+ /// A pseudo source value referencing the area below the stack frame of
+ /// a function, e.g., the argument space.
static const PseudoSourceValue *getStack();
- /// A source value referencing the global offset table (or something the
- /// like).
+ /// A pseudo source value referencing the global offset table
+ /// (or something the like).
static const PseudoSourceValue *getGOT();
- /// A SV referencing the constant pool
+ /// A pseudo source value referencing the constant pool. Since constant
+ /// pools are constant, this doesn't need to identify a specific constant
+ /// pool entry.
static const PseudoSourceValue *getConstantPool();
- /// A SV referencing the jump table
+ /// A pseudo source value referencing a jump table. Since jump tables are
+ /// constant, this doesn't need to identify a specific jump table.
static const PseudoSourceValue *getJumpTable();
};
} // End llvm namespace
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/RegisterScavenging.h b/libclamav/c++/llvm/include/llvm/CodeGen/RegisterScavenging.h
index 511b8bb..7aa1086 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/RegisterScavenging.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/RegisterScavenging.h
@@ -121,7 +121,7 @@ private:
/// isReserved - Returns true if a register is reserved. It is never "unused".
bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); }
- /// isUsed / isUsed - Test if a register is currently being used.
+ /// isUsed / isUnused - Test if a register is currently being used.
///
bool isUsed(unsigned Reg) const { return !RegsAvailable.test(Reg); }
bool isUnused(unsigned Reg) const { return RegsAvailable.test(Reg); }
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/ScheduleDAG.h b/libclamav/c++/llvm/include/llvm/CodeGen/ScheduleDAG.h
index af30948..2de095b 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -243,10 +243,10 @@ namespace llvm {
unsigned NodeNum; // Entry # of node in the node vector.
unsigned NodeQueueId; // Queue id of node.
unsigned short Latency; // Node latency.
- short NumPreds; // # of SDep::Data preds.
- short NumSuccs; // # of SDep::Data sucss.
- short NumPredsLeft; // # of preds not scheduled.
- short NumSuccsLeft; // # of succs not scheduled.
+ unsigned NumPreds; // # of SDep::Data preds.
+ unsigned NumSuccs; // # of SDep::Data sucss.
+ unsigned NumPredsLeft; // # of preds not scheduled.
+ unsigned NumSuccsLeft; // # of succs not scheduled.
bool isTwoAddress : 1; // Is a two-address instruction.
bool isCommutable : 1; // Is a commutable instruction.
bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
@@ -461,7 +461,8 @@ namespace llvm {
/// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
/// according to the order specified in Sequence.
///
- virtual MachineBasicBlock *EmitSchedule() = 0;
+ virtual MachineBasicBlock*
+ EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) = 0;
void dumpSchedule() const;
@@ -515,8 +516,6 @@ namespace llvm {
///
void EmitNoop();
- void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
-
void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
private:
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/SelectionDAG.h b/libclamav/c++/llvm/include/llvm/CodeGen/SelectionDAG.h
index 7ce8690..e1b9998 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -19,6 +19,7 @@
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/Support/RecyclingAllocator.h"
#include "llvm/Target/TargetMachine.h"
#include <cassert>
#include <vector>
@@ -514,15 +515,23 @@ public:
SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* PtrVal,
unsigned Alignment=0);
+ SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
+ SDValue Ptr, SDValue Cmp, SDValue Swp,
+ MachineMemOperand *MMO);
/// getAtomic - Gets a node for an atomic op, produces result and chain and
/// takes 2 operands.
SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
SDValue Ptr, SDValue Val, const Value* PtrVal,
unsigned Alignment = 0);
+ SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
+ SDValue Ptr, SDValue Val,
+ MachineMemOperand *MMO);
/// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a
- /// result and takes a list of operands.
+ /// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
+ /// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not
+ /// less than FIRST_TARGET_MEMORY_OPCODE.
SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
const EVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps,
@@ -536,6 +545,10 @@ public:
unsigned Align = 0, bool Vol = false,
bool ReadMem = true, bool WriteMem = true);
+ SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
+ const SDValue *Ops, unsigned NumOps,
+ EVT MemVT, MachineMemOperand *MMO);
+
/// getMergeValues - Create a MERGE_VALUES node from the given operands.
SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl);
@@ -547,34 +560,36 @@ public:
unsigned Alignment=0);
SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
SDValue Chain, SDValue Ptr, const Value *SV,
- int SVOffset, EVT EVT, bool isVolatile=false,
+ int SVOffset, EVT MemVT, bool isVolatile=false,
unsigned Alignment=0);
SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);
SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType,
- EVT VT, SDValue Chain,
- SDValue Ptr, SDValue Offset,
- const Value *SV, int SVOffset, EVT EVT,
- bool isVolatile=false, unsigned Alignment=0);
+ EVT VT, SDValue Chain, SDValue Ptr, SDValue Offset,
+ const Value *SV, int SVOffset, EVT MemVT,
+ bool isVolatile=false, unsigned Alignment=0);
+ SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType,
+ EVT VT, SDValue Chain, SDValue Ptr, SDValue Offset,
+ EVT MemVT, MachineMemOperand *MMO);
/// getStore - Helper function to build ISD::STORE nodes.
///
SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
+ SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
+ MachineMemOperand *MMO);
SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
const Value *SV, int SVOffset, EVT TVT,
bool isVolatile=false, unsigned Alignment=0);
+ SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
+ EVT TVT, MachineMemOperand *MMO);
SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);
/// getSrcValue - Construct a node to track a Value* through the backend.
SDValue getSrcValue(const Value *v);
- /// getMemOperand - Construct a node to track a memory reference
- /// through the backend.
- SDValue getMemOperand(const MachineMemOperand &MO);
-
/// getShiftAmountOperand - Return the specified value casted to
/// the target's desired shift amount type.
SDValue getShiftAmountOperand(SDValue Op);
@@ -651,40 +666,42 @@ public:
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs,
const SDValue *Ops, unsigned NumOps);
- /// getTargetNode - These are used for target selectors to create a new node
- /// with specified return type(s), target opcode, and operands.
+ /// getMachineNode - These are used for target selectors to create a new node
+ /// with specified return type(s), MachineInstr opcode, and operands.
///
- /// Note that getTargetNode returns the resultant node. If there is already a
- /// node of the specified opcode and operands, it returns that node instead of
- /// the current one.
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1,
- SDValue Op2);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
- SDValue Op1, SDValue Op2, SDValue Op3);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
- const SDValue *Ops, unsigned NumOps);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
- SDValue Op1);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
- EVT VT2, SDValue Op1, SDValue Op2);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
- EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
- const SDValue *Ops, unsigned NumOps);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
- SDValue Op1, SDValue Op2);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
- SDValue Op1, SDValue Op2, SDValue Op3);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
- const SDValue *Ops, unsigned NumOps);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
- EVT VT4, const SDValue *Ops, unsigned NumOps);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl,
- const std::vector<EVT> &ResultTys, const SDValue *Ops,
- unsigned NumOps);
+ /// Note that getMachineNode returns the resultant node. If there is already
+ /// a node of the specified opcode and operands, it returns that node instead
+ /// of the current one.
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1,
+ SDValue Op2);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT,
+ SDValue Op1, SDValue Op2, SDValue Op3);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT,
+ const SDValue *Ops, unsigned NumOps);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
+ SDValue Op1);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1, SDValue Op2);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
+ const SDValue *Ops, unsigned NumOps);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
+ EVT VT3, SDValue Op1, SDValue Op2);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
+ EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
+ EVT VT3, const SDValue *Ops, unsigned NumOps);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
+ EVT VT3, EVT VT4, const SDValue *Ops, unsigned NumOps);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl,
+ const std::vector<EVT> &ResultTys, const SDValue *Ops,
+ unsigned NumOps);
+ SDNode *getMachineNode(unsigned Opcode, DebugLoc dl, SDVTList VTs,
+ const SDValue *Ops, unsigned NumOps);
/// getTargetExtractSubreg - A convenience function for creating
/// TargetInstrInfo::EXTRACT_SUBREG nodes.
@@ -840,6 +857,9 @@ public:
/// class to allow target nodes to be understood.
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth = 0) const;
+ /// isKnownNeverNan - Test whether the given SDValue is known to never be NaN.
+ bool isKnownNeverNaN(SDValue Op) const;
+
/// isVerifiedDebugInfoDesc - Returns true if the specified SDValue has
/// been verified as a debug information descriptor.
bool isVerifiedDebugInfoDesc(SDValue Op) const;
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/libclamav/c++/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index c42ff38..604f065 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -27,12 +27,10 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGen/MachineMemOperand.h"
-#include "llvm/Support/Allocator.h"
-#include "llvm/Support/RecyclingAllocator.h"
+#include "llvm/Support/MathExtras.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/DebugLoc.h"
#include <cassert>
-#include <climits>
namespace llvm {
@@ -535,11 +533,6 @@ namespace ISD {
// make reference to a value in the LLVM IR.
SRCVALUE,
- // MEMOPERAND - This is a node that contains a MachineMemOperand which
- // records information about a memory reference. This is used to make
- // AliasAnalysis queries from the backend.
- MEMOPERAND,
-
// PCMARKER - This corresponds to the pcmarker intrinsic.
PCMARKER,
@@ -616,10 +609,17 @@ namespace ISD {
ATOMIC_LOAD_UMIN,
ATOMIC_LOAD_UMAX,
- // BUILTIN_OP_END - This must be the last enum value in this list.
+ /// BUILTIN_OP_END - This must be the last enum value in this list.
+ /// The target-specific pre-isel opcode values start here.
BUILTIN_OP_END
};
+ /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
+ /// which do not reference a specific memory location should be less than
+ /// this value. Those that do must not be less than this value, and can
+ /// be used with SelectionDAG::getMemIntrinsicNode.
+ static const int FIRST_TARGET_MEMORY_OPCODE = 1 << 14;
+
/// Node predicates
/// isBuildVectorAllOnes - Return true if the specified node is a
@@ -866,6 +866,7 @@ public:
inline unsigned getNumOperands() const;
inline const SDValue &getOperand(unsigned i) const;
inline uint64_t getConstantOperandVal(unsigned i) const;
+ inline bool isTargetMemoryOpcode() const;
inline bool isTargetOpcode() const;
inline bool isMachineOpcode() const;
inline unsigned getMachineOpcode() const;
@@ -1030,17 +1031,17 @@ class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
private:
/// NodeType - The operation that this node performs.
///
- short NodeType;
+ int16_t NodeType;
/// OperandsNeedDelete - This is true if OperandList was new[]'d. If true,
/// then they will be delete[]'d when the node is destroyed.
- unsigned short OperandsNeedDelete : 1;
+ uint16_t OperandsNeedDelete : 1;
protected:
/// SubclassData - This member is defined by this class, but is not used for
/// anything. Subclasses can use it to hold whatever state they find useful.
/// This field is initialized to zero by the ctor.
- unsigned short SubclassData : 15;
+ uint16_t SubclassData : 15;
private:
/// NodeId - Unique id per SDNode in the DAG.
@@ -1084,6 +1085,13 @@ public:
/// \<target\>ISD namespace).
bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
+ /// isTargetMemoryOpcode - Test if this node has a target-specific
+ /// memory-referencing opcode (in the \<target\>ISD namespace and
+ /// greater than FIRST_TARGET_MEMORY_OPCODE).
+ bool isTargetMemoryOpcode() const {
+ return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
+ }
+
/// isMachineOpcode - Test if this node has a post-isel opcode, directly
/// corresponding to a MachineInstr opcode.
bool isMachineOpcode() const { return NodeType < 0; }
@@ -1294,6 +1302,7 @@ public:
void dump() const;
void dumpr() const;
void dump(const SelectionDAG *G) const;
+ void dumpr(const SelectionDAG *G) const;
static bool classof(const SDNode *) { return true; }
@@ -1415,6 +1424,9 @@ inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
inline bool SDValue::isTargetOpcode() const {
return Node->isTargetOpcode();
}
+inline bool SDValue::isTargetMemoryOpcode() const {
+ return Node->isTargetMemoryOpcode();
+}
inline bool SDValue::isMachineOpcode() const {
return Node->isMachineOpcode();
}
@@ -1513,43 +1525,55 @@ private:
// MemoryVT - VT of in-memory value.
EVT MemoryVT;
- //! SrcValue - Memory location for alias analysis.
- const Value *SrcValue;
-
- //! SVOffset - Memory location offset. Note that base is defined in MemSDNode
- int SVOffset;
+protected:
+ /// MMO - Memory reference information.
+ MachineMemOperand *MMO;
public:
MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, EVT MemoryVT,
- const Value *srcValue, int SVOff,
- unsigned alignment, bool isvolatile);
+ MachineMemOperand *MMO);
MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops,
- unsigned NumOps, EVT MemoryVT, const Value *srcValue, int SVOff,
- unsigned alignment, bool isvolatile);
+ unsigned NumOps, EVT MemoryVT, MachineMemOperand *MMO);
+
+ bool readMem() const { return MMO->isLoad(); }
+ bool writeMem() const { return MMO->isStore(); }
/// Returns alignment and volatility of the memory access
- unsigned getAlignment() const { return (1u << (SubclassData >> 6)) >> 1; }
- bool isVolatile() const { return (SubclassData >> 5) & 1; }
+ unsigned getOriginalAlignment() const {
+ return MMO->getBaseAlignment();
+ }
+ unsigned getAlignment() const {
+ return MMO->getAlignment();
+ }
/// getRawSubclassData - Return the SubclassData value, which contains an
- /// encoding of the alignment and volatile information, as well as bits
- /// used by subclasses. This function should only be used to compute a
- /// FoldingSetNodeID value.
+ /// encoding of the volatile flag, as well as bits used by subclasses. This
+ /// function should only be used to compute a FoldingSetNodeID value.
unsigned getRawSubclassData() const {
return SubclassData;
}
+ bool isVolatile() const { return (SubclassData >> 5) & 1; }
+
/// Returns the SrcValue and offset that describes the location of the access
- const Value *getSrcValue() const { return SrcValue; }
- int getSrcValueOffset() const { return SVOffset; }
+ const Value *getSrcValue() const { return MMO->getValue(); }
+ int64_t getSrcValueOffset() const { return MMO->getOffset(); }
/// getMemoryVT - Return the type of the in-memory value.
EVT getMemoryVT() const { return MemoryVT; }
/// getMemOperand - Return a MachineMemOperand object describing the memory
/// reference performed by operation.
- MachineMemOperand getMemOperand() const;
+ MachineMemOperand *getMemOperand() const { return MMO; }
+
+ /// refineAlignment - Update this MemSDNode's MachineMemOperand information
+ /// to reflect the alignment of NewMMO, if it has a greater alignment.
+ /// This must only be used when the new alignment applies to all users of
+ /// this MachineMemOperand.
+ void refineAlignment(const MachineMemOperand *NewMMO) {
+ MMO->refineAlignment(NewMMO);
+ }
const SDValue &getChain() const { return getOperand(0); }
const SDValue &getBasePtr() const {
@@ -1577,7 +1601,7 @@ public:
N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
N->getOpcode() == ISD::INTRINSIC_W_CHAIN ||
N->getOpcode() == ISD::INTRINSIC_VOID ||
- N->isTargetOpcode();
+ N->isTargetMemoryOpcode();
}
};
@@ -1597,17 +1621,18 @@ public:
// Align: alignment of memory
AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,
SDValue Chain, SDValue Ptr,
- SDValue Cmp, SDValue Swp, const Value* SrcVal,
- unsigned Align=0)
- : MemSDNode(Opc, dl, VTL, MemVT, SrcVal, /*SVOffset=*/0,
- Align, /*isVolatile=*/true) {
+ SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
+ : MemSDNode(Opc, dl, VTL, MemVT, MMO) {
+ assert(readMem() && "Atomic MachineMemOperand is not a load!");
+ assert(writeMem() && "Atomic MachineMemOperand is not a store!");
InitOperands(Ops, Chain, Ptr, Cmp, Swp);
}
AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,
SDValue Chain, SDValue Ptr,
- SDValue Val, const Value* SrcVal, unsigned Align=0)
- : MemSDNode(Opc, dl, VTL, MemVT, SrcVal, /*SVOffset=*/0,
- Align, /*isVolatile=*/true) {
+ SDValue Val, MachineMemOperand *MMO)
+ : MemSDNode(Opc, dl, VTL, MemVT, MMO) {
+ assert(readMem() && "Atomic MachineMemOperand is not a load!");
+ assert(writeMem() && "Atomic MachineMemOperand is not a store!");
InitOperands(Ops, Chain, Ptr, Val);
}
@@ -1637,24 +1662,18 @@ public:
}
};
-/// MemIntrinsicSDNode - This SDNode is used for target intrinsic that touches
-/// memory and need an associated memory operand.
-///
+/// MemIntrinsicSDNode - This SDNode is used for target intrinsics that touch
+/// memory and need an associated MachineMemOperand. Its opcode may be
+/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, or a target-specific opcode with a
+/// value not less than FIRST_TARGET_MEMORY_OPCODE.
class MemIntrinsicSDNode : public MemSDNode {
- bool ReadMem; // Intrinsic reads memory
- bool WriteMem; // Intrinsic writes memory
public:
MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
const SDValue *Ops, unsigned NumOps,
- EVT MemoryVT, const Value *srcValue, int SVO,
- unsigned Align, bool Vol, bool ReadMem, bool WriteMem)
- : MemSDNode(Opc, dl, VTs, Ops, NumOps, MemoryVT, srcValue, SVO, Align, Vol),
- ReadMem(ReadMem), WriteMem(WriteMem) {
+ EVT MemoryVT, MachineMemOperand *MMO)
+ : MemSDNode(Opc, dl, VTs, Ops, NumOps, MemoryVT, MMO) {
}
- bool readMem() const { return ReadMem; }
- bool writeMem() const { return WriteMem; }
-
// Methods to support isa and dyn_cast
static bool classof(const MemIntrinsicSDNode *) { return true; }
static bool classof(const SDNode *N) {
@@ -1662,7 +1681,7 @@ public:
// early a node with a target opcode can be of this class
return N->getOpcode() == ISD::INTRINSIC_W_CHAIN ||
N->getOpcode() == ISD::INTRINSIC_VOID ||
- N->isTargetOpcode();
+ N->isTargetMemoryOpcode();
}
};
@@ -1950,10 +1969,6 @@ public:
/// used when the SelectionDAG needs to make a simple reference to something
/// in the LLVM IR representation.
///
-/// Note that this is not used for carrying alias information; that is done
-/// with MemOperandSDNode, which includes a Value which is required to be a
-/// pointer, and several other fields specific to memory references.
-///
class SrcValueSDNode : public SDNode {
const Value *V;
friend class SelectionDAG;
@@ -1973,28 +1988,6 @@ public:
};
-/// MemOperandSDNode - An SDNode that holds a MachineMemOperand. This is
-/// used to represent a reference to memory after ISD::LOAD
-/// and ISD::STORE have been lowered.
-///
-class MemOperandSDNode : public SDNode {
- friend class SelectionDAG;
- /// Create a MachineMemOperand node
- explicit MemOperandSDNode(const MachineMemOperand &mo)
- : SDNode(ISD::MEMOPERAND, DebugLoc::getUnknownLoc(),
- getSDVTList(MVT::Other)), MO(mo) {}
-
-public:
- /// MO - The contained MachineMemOperand.
- const MachineMemOperand MO;
-
- static bool classof(const MemOperandSDNode *) { return true; }
- static bool classof(const SDNode *N) {
- return N->getOpcode() == ISD::MEMOPERAND;
- }
-};
-
-
class RegisterSDNode : public SDNode {
unsigned Reg;
friend class SelectionDAG;
@@ -2263,9 +2256,8 @@ class LSBaseSDNode : public MemSDNode {
public:
LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands,
unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM,
- EVT VT, const Value *SV, int SVO, unsigned Align, bool Vol)
- : MemSDNode(NodeTy, dl, VTs, VT, SV, SVO, Align, Vol) {
- assert(Align != 0 && "Loads and stores should have non-zero aligment");
+ EVT MemVT, MachineMemOperand *MMO)
+ : MemSDNode(NodeTy, dl, VTs, MemVT, MMO) {
SubclassData |= AM << 2;
assert(getAddressingMode() == AM && "MemIndexedMode encoding error!");
InitOperands(Ops, Operands, numOperands);
@@ -2301,12 +2293,14 @@ public:
class LoadSDNode : public LSBaseSDNode {
friend class SelectionDAG;
LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs,
- ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT LVT,
- const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
+ ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
+ MachineMemOperand *MMO)
: LSBaseSDNode(ISD::LOAD, dl, ChainPtrOff, 3,
- VTs, AM, LVT, SV, O, Align, Vol) {
+ VTs, AM, MemVT, MMO) {
SubclassData |= (unsigned short)ETy;
assert(getExtensionType() == ETy && "LoadExtType encoding error!");
+ assert(readMem() && "Load MachineMemOperand is not a load!");
+ assert(!writeMem() && "Load MachineMemOperand is a store!");
}
public:
@@ -2330,12 +2324,14 @@ public:
class StoreSDNode : public LSBaseSDNode {
friend class SelectionDAG;
StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs,
- ISD::MemIndexedMode AM, bool isTrunc, EVT SVT,
- const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
+ ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
+ MachineMemOperand *MMO)
: LSBaseSDNode(ISD::STORE, dl, ChainValuePtrOff, 4,
- VTs, AM, SVT, SV, O, Align, Vol) {
+ VTs, AM, MemVT, MMO) {
SubclassData |= (unsigned short)isTrunc;
assert(isTruncatingStore() == isTrunc && "isTrunc encoding error!");
+ assert(!readMem() && "Store MachineMemOperand is a load!");
+ assert(writeMem() && "Store MachineMemOperand is not a store!");
}
public:
@@ -2354,6 +2350,44 @@ public:
}
};
+/// MachineSDNode - An SDNode that represents everything that will be needed
+/// to construct a MachineInstr. These nodes are created during the
+/// instruction selection proper phase.
+///
+class MachineSDNode : public SDNode {
+public:
+ typedef MachineMemOperand **mmo_iterator;
+
+private:
+ friend class SelectionDAG;
+ MachineSDNode(unsigned Opc, const DebugLoc DL, SDVTList VTs)
+ : SDNode(Opc, DL, VTs), MemRefs(0), MemRefsEnd(0) {}
+
+ /// LocalOperands - Operands for this instruction, if they fit here. If
+ /// they don't, this field is unused.
+ SDUse LocalOperands[4];
+
+ /// MemRefs - Memory reference descriptions for this instruction.
+ mmo_iterator MemRefs;
+ mmo_iterator MemRefsEnd;
+
+public:
+ mmo_iterator memoperands_begin() const { return MemRefs; }
+ mmo_iterator memoperands_end() const { return MemRefsEnd; }
+ bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
+
+ /// setMemRefs - Assign this MachineSDNodes's memory reference descriptor
+ /// list. This does not transfer ownership.
+ void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
+ MemRefs = NewMemRefs;
+ MemRefsEnd = NewMemRefsEnd;
+ }
+
+ static bool classof(const MachineSDNode *) { return true; }
+ static bool classof(const SDNode *N) {
+ return N->isMachineOpcode();
+ }
+};
class SDNodeIterator : public std::iterator<std::forward_iterator_tag,
SDNode, ptrdiff_t> {
diff --git a/libclamav/c++/llvm/include/llvm/CodeGen/ValueTypes.h b/libclamav/c++/llvm/include/llvm/CodeGen/ValueTypes.h
index 167a70e..1f0dd21 100644
--- a/libclamav/c++/llvm/include/llvm/CodeGen/ValueTypes.h
+++ b/libclamav/c++/llvm/include/llvm/CodeGen/ValueTypes.h
@@ -552,10 +552,16 @@ namespace llvm {
return getExtendedSizeInBits();
}
+ /// getStoreSize - Return the number of bytes overwritten by a store
+ /// of the specified value type.
+ unsigned getStoreSize() const {
+ return (getSizeInBits() + 7) / 8;
+ }
+
/// getStoreSizeInBits - Return the number of bits overwritten by a store
/// of the specified value type.
unsigned getStoreSizeInBits() const {
- return (getSizeInBits() + 7)/8*8;
+ return getStoreSize() * 8;
}
/// getRoundIntegerType - Rounds the bit-width of the given integer EVT up
diff --git a/libclamav/c++/llvm/include/llvm/CompilerDriver/Common.td b/libclamav/c++/llvm/include/llvm/CompilerDriver/Common.td
index 914249e..5b7c543 100644
--- a/libclamav/c++/llvm/include/llvm/CompilerDriver/Common.td
+++ b/libclamav/c++/llvm/include/llvm/CompilerDriver/Common.td
@@ -46,9 +46,6 @@ def really_hidden;
def required;
def zero_or_one;
-// Empty DAG marker.
-def empty;
-
// The 'case' construct.
def case;
@@ -59,14 +56,18 @@ def false;
// Boolean operators.
def and;
def or;
+def not;
// Primitive tests.
def switch_on;
def parameter_equals;
def element_in_list;
def input_languages_contain;
+def empty;
def not_empty;
def default;
+def single_input_file;
+def multiple_input_files;
// Possible actions.
@@ -81,6 +82,9 @@ def error;
def inc_weight;
def dec_weight;
+// Empty DAG marker.
+def empty_dag_marker;
+
// Used to specify plugin priority.
class PluginPriority<int p> {
int priority = p;
@@ -110,10 +114,10 @@ class EdgeBase<string t1, string t2, dag d> {
dag weight = d;
}
-class Edge<string t1, string t2> : EdgeBase<t1, t2, (empty)>;
+class Edge<string t1, string t2> : EdgeBase<t1, t2, (empty_dag_marker)>;
// Edge and SimpleEdge are synonyms.
-class SimpleEdge<string t1, string t2> : EdgeBase<t1, t2, (empty)>;
+class SimpleEdge<string t1, string t2> : EdgeBase<t1, t2, (empty_dag_marker)>;
// Optionally enabled edge.
class OptionalEdge<string t1, string t2, dag props> : EdgeBase<t1, t2, props>;
diff --git a/libclamav/c++/llvm/include/llvm/Config/config.h.cmake b/libclamav/c++/llvm/include/llvm/Config/config.h.cmake
index 360ca5d..d8de146 100644
--- a/libclamav/c++/llvm/include/llvm/Config/config.h.cmake
+++ b/libclamav/c++/llvm/include/llvm/Config/config.h.cmake
@@ -291,6 +291,9 @@
/* Define to 1 if you have the `sbrk' function. */
#undef HAVE_SBRK
+/* Define to 1 if you have the `setenv' function. */
+#cmakedefine HAVE_SETENV ${HAVE_SETENV}
+
/* Define to 1 if you have the `setjmp' function. */
#undef HAVE_SETJMP
diff --git a/libclamav/c++/llvm/include/llvm/Config/config.h.in b/libclamav/c++/llvm/include/llvm/Config/config.h.in
index f32f403..5257df9 100644
--- a/libclamav/c++/llvm/include/llvm/Config/config.h.in
+++ b/libclamav/c++/llvm/include/llvm/Config/config.h.in
@@ -321,6 +321,9 @@
/* Define to 1 if you have the `sbrk' function. */
#undef HAVE_SBRK
+/* Define to 1 if you have the `setenv' function. */
+#undef HAVE_SETENV
+
/* Define to 1 if you have the `setjmp' function. */
#undef HAVE_SETJMP
diff --git a/libclamav/c++/llvm/include/llvm/Constants.h b/libclamav/c++/llvm/include/llvm/Constants.h
index fdcc53b..260a89a 100644
--- a/libclamav/c++/llvm/include/llvm/Constants.h
+++ b/libclamav/c++/llvm/include/llvm/Constants.h
@@ -38,7 +38,7 @@ class VectorType;
template<class ConstantClass, class TypeClass, class ValType>
struct ConstantCreator;
template<class ConstantClass, class TypeClass>
-struct ConvertConstant;
+struct ConvertConstantType;
//===----------------------------------------------------------------------===//
/// This is the shared class of boolean and integer constants. This class
@@ -258,6 +258,7 @@ public:
static Constant* get(const Type* Ty, const StringRef& Str);
static ConstantFP* get(LLVMContext &Context, const APFloat& V);
static ConstantFP* getNegativeZero(const Type* Ty);
+ static ConstantFP* getInfinity(const Type* Ty, bool negative = false);
/// isValueValidForType - return true if Ty is big enough to represent V.
static bool isValueValidForType(const Type *Ty, const APFloat& V);
@@ -397,7 +398,7 @@ public:
};
template <>
-struct OperandTraits<ConstantArray> : VariadicOperandTraits<> {
+struct OperandTraits<ConstantArray> : public VariadicOperandTraits<> {
};
DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantArray, Constant)
@@ -415,11 +416,11 @@ public:
// ConstantStruct accessors
static Constant* get(const StructType* T, const std::vector<Constant*>& V);
static Constant* get(LLVMContext &Context,
- const std::vector<Constant*>& V, bool Packed = false);
+ const std::vector<Constant*>& V, bool Packed);
static Constant* get(LLVMContext &Context,
Constant* const *Vals, unsigned NumVals,
- bool Packed = false);
-
+ bool Packed);
+
/// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Constant);
@@ -447,7 +448,7 @@ public:
};
template <>
-struct OperandTraits<ConstantStruct> : VariadicOperandTraits<> {
+struct OperandTraits<ConstantStruct> : public VariadicOperandTraits<> {
};
DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantStruct, Constant)
@@ -503,7 +504,7 @@ public:
};
template <>
-struct OperandTraits<ConstantVector> : VariadicOperandTraits<> {
+struct OperandTraits<ConstantVector> : public VariadicOperandTraits<> {
};
DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantVector, Constant)
@@ -559,7 +560,7 @@ public:
class ConstantExpr : public Constant {
friend struct ConstantCreator<ConstantExpr,Type,
std::pair<unsigned, std::vector<Constant*> > >;
- friend struct ConvertConstant<ConstantExpr, Type>;
+ friend struct ConvertConstantType<ConstantExpr, Type>;
protected:
ConstantExpr(const Type *ty, unsigned Opcode, Use *Ops, unsigned NumOps)
@@ -571,13 +572,17 @@ protected:
// These private methods are used by the type resolution code to create
// ConstantExprs in intermediate forms.
static Constant *getTy(const Type *Ty, unsigned Opcode,
- Constant *C1, Constant *C2);
+ Constant *C1, Constant *C2,
+ unsigned Flags = 0);
static Constant *getCompareTy(unsigned short pred, Constant *C1,
Constant *C2);
static Constant *getSelectTy(const Type *Ty,
Constant *C1, Constant *C2, Constant *C3);
static Constant *getGetElementPtrTy(const Type *Ty, Constant *C,
Value* const *Idxs, unsigned NumIdxs);
+ static Constant *getInBoundsGetElementPtrTy(const Type *Ty, Constant *C,
+ Value* const *Idxs,
+ unsigned NumIdxs);
static Constant *getExtractElementTy(const Type *Ty, Constant *Val,
Constant *Idx);
static Constant *getInsertElementTy(const Type *Ty, Constant *Val,
@@ -649,6 +654,7 @@ public:
static Constant *getBitCast (Constant *C, const Type *Ty);
static Constant* getNSWAdd(Constant* C1, Constant* C2);
+ static Constant* getNSWSub(Constant* C1, Constant* C2);
static Constant* getExactSDiv(Constant* C1, Constant* C2);
/// Transparently provide more efficient getOperand methods.
@@ -709,6 +715,13 @@ public:
/// and the getIndices() method may be used.
bool hasIndices() const;
+ /// @brief Return true if this is a getelementptr expression and all
+ /// the index operands are compile-time known integers within the
+ /// corresponding notional static array extents. Note that this is
+ /// not equivalant to, a subset of, or a superset of the "inbounds"
+ /// property.
+ bool isGEPWithNoNotionalOverIndexing() const;
+
/// Select constant expr
///
static Constant *getSelect(Constant *C, Constant *V1, Constant *V2) {
@@ -718,7 +731,8 @@ public:
/// get - Return a binary or shift operator constant expression,
/// folding if possible.
///
- static Constant *get(unsigned Opcode, Constant *C1, Constant *C2);
+ static Constant *get(unsigned Opcode, Constant *C1, Constant *C2,
+ unsigned Flags = 0);
/// @brief Return an ICmp or FCmp comparison operator constant expression.
static Constant *getCompare(unsigned short pred, Constant *C1, Constant *C2);
@@ -795,7 +809,7 @@ public:
};
template <>
-struct OperandTraits<ConstantExpr> : VariadicOperandTraits<1> {
+struct OperandTraits<ConstantExpr> : public VariadicOperandTraits<1> {
};
DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantExpr, Constant)
diff --git a/libclamav/c++/llvm/include/llvm/Function.h b/libclamav/c++/llvm/include/llvm/Function.h
index 7ff18b3..088c999 100644
--- a/libclamav/c++/llvm/include/llvm/Function.h
+++ b/libclamav/c++/llvm/include/llvm/Function.h
@@ -19,6 +19,7 @@
#define LLVM_FUNCTION_H
#include "llvm/GlobalValue.h"
+#include "llvm/CallingConv.h"
#include "llvm/BasicBlock.h"
#include "llvm/Argument.h"
#include "llvm/Attributes.h"
@@ -86,7 +87,7 @@ private:
AttrListPtr AttributeList; ///< Parameter attributes
// The Calling Convention is stored in Value::SubclassData.
- /*unsigned CallingConvention;*/
+ /*CallingConv::ID CallingConvention;*/
friend class SymbolTableListTraits<Function, Module>;
@@ -150,12 +151,14 @@ public:
unsigned getIntrinsicID() const;
bool isIntrinsic() const { return getIntrinsicID() != 0; }
- /// getCallingConv()/setCallingConv(uint) - These method get and set the
+ /// getCallingConv()/setCallingConv(CC) - These method get and set the
/// calling convention of this function. The enum values for the known
/// calling conventions are defined in CallingConv.h.
- unsigned getCallingConv() const { return SubclassData >> 1; }
- void setCallingConv(unsigned CC) {
- SubclassData = (SubclassData & 1) | (CC << 1);
+ CallingConv::ID getCallingConv() const {
+ return static_cast<CallingConv::ID>(SubclassData >> 1);
+ }
+ void setCallingConv(CallingConv::ID CC) {
+ SubclassData = (SubclassData & 1) | (static_cast<unsigned>(CC) << 1);
}
/// getAttributes - Return the attribute list for this Function.
diff --git a/libclamav/c++/llvm/include/llvm/GlobalAlias.h b/libclamav/c++/llvm/include/llvm/GlobalAlias.h
index 91bd61b..9b3f450 100644
--- a/libclamav/c++/llvm/include/llvm/GlobalAlias.h
+++ b/libclamav/c++/llvm/include/llvm/GlobalAlias.h
@@ -88,7 +88,7 @@ public:
};
template <>
-struct OperandTraits<GlobalAlias> : FixedNumOperandTraits<1> {
+struct OperandTraits<GlobalAlias> : public FixedNumOperandTraits<1> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GlobalAlias, Value)
diff --git a/libclamav/c++/llvm/include/llvm/GlobalVariable.h b/libclamav/c++/llvm/include/llvm/GlobalVariable.h
index f18554d..56b2b9d 100644
--- a/libclamav/c++/llvm/include/llvm/GlobalVariable.h
+++ b/libclamav/c++/llvm/include/llvm/GlobalVariable.h
@@ -151,7 +151,7 @@ public:
};
template <>
-struct OperandTraits<GlobalVariable> : OptionalOperandTraits<> {
+struct OperandTraits<GlobalVariable> : public OptionalOperandTraits<> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GlobalVariable, Value)
diff --git a/libclamav/c++/llvm/include/llvm/InstrTypes.h b/libclamav/c++/llvm/include/llvm/InstrTypes.h
index 35d7534..cc923de 100644
--- a/libclamav/c++/llvm/include/llvm/InstrTypes.h
+++ b/libclamav/c++/llvm/include/llvm/InstrTypes.h
@@ -53,7 +53,7 @@ protected:
virtual void setSuccessorV(unsigned idx, BasicBlock *B) = 0;
public:
- virtual TerminatorInst *clone(LLVMContext &Context) const = 0;
+ virtual TerminatorInst *clone() const = 0;
/// getNumSuccessors - Return the number of successors that this terminator
/// has.
@@ -130,7 +130,7 @@ public:
};
template <>
-struct OperandTraits<UnaryInstruction> : FixedNumOperandTraits<1> {
+struct OperandTraits<UnaryInstruction> : public FixedNumOperandTraits<1> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(UnaryInstruction, Value)
@@ -200,19 +200,40 @@ public:
static BinaryOperator *CreateNSWAdd(Value *V1, Value *V2,
const Twine &Name = "") {
BinaryOperator *BO = CreateAdd(V1, V2, Name);
- cast<AddOperator>(BO)->setHasNoSignedWrap(true);
+ BO->setHasNoSignedWrap(true);
return BO;
}
static BinaryOperator *CreateNSWAdd(Value *V1, Value *V2,
const Twine &Name, BasicBlock *BB) {
BinaryOperator *BO = CreateAdd(V1, V2, Name, BB);
- cast<AddOperator>(BO)->setHasNoSignedWrap(true);
+ BO->setHasNoSignedWrap(true);
return BO;
}
static BinaryOperator *CreateNSWAdd(Value *V1, Value *V2,
const Twine &Name, Instruction *I) {
BinaryOperator *BO = CreateAdd(V1, V2, Name, I);
- cast<AddOperator>(BO)->setHasNoSignedWrap(true);
+ BO->setHasNoSignedWrap(true);
+ return BO;
+ }
+
+ /// CreateNSWSub - Create an Sub operator with the NSW flag set.
+ ///
+ static BinaryOperator *CreateNSWSub(Value *V1, Value *V2,
+ const Twine &Name = "") {
+ BinaryOperator *BO = CreateSub(V1, V2, Name);
+ BO->setHasNoSignedWrap(true);
+ return BO;
+ }
+ static BinaryOperator *CreateNSWSub(Value *V1, Value *V2,
+ const Twine &Name, BasicBlock *BB) {
+ BinaryOperator *BO = CreateSub(V1, V2, Name, BB);
+ BO->setHasNoSignedWrap(true);
+ return BO;
+ }
+ static BinaryOperator *CreateNSWSub(Value *V1, Value *V2,
+ const Twine &Name, Instruction *I) {
+ BinaryOperator *BO = CreateSub(V1, V2, Name, I);
+ BO->setHasNoSignedWrap(true);
return BO;
}
@@ -221,19 +242,19 @@ public:
static BinaryOperator *CreateExactSDiv(Value *V1, Value *V2,
const Twine &Name = "") {
BinaryOperator *BO = CreateSDiv(V1, V2, Name);
- cast<SDivOperator>(BO)->setIsExact(true);
+ BO->setIsExact(true);
return BO;
}
static BinaryOperator *CreateExactSDiv(Value *V1, Value *V2,
const Twine &Name, BasicBlock *BB) {
BinaryOperator *BO = CreateSDiv(V1, V2, Name, BB);
- cast<SDivOperator>(BO)->setIsExact(true);
+ BO->setIsExact(true);
return BO;
}
static BinaryOperator *CreateExactSDiv(Value *V1, Value *V2,
const Twine &Name, Instruction *I) {
BinaryOperator *BO = CreateSDiv(V1, V2, Name, I);
- cast<SDivOperator>(BO)->setIsExact(true);
+ BO->setIsExact(true);
return BO;
}
@@ -278,7 +299,7 @@ public:
return static_cast<BinaryOps>(Instruction::getOpcode());
}
- virtual BinaryOperator *clone(LLVMContext &Context) const;
+ virtual BinaryOperator *clone() const;
/// swapOperands - Exchange the two operands to this instruction.
/// This instruction is safe to use on any binary instruction and
@@ -287,6 +308,30 @@ public:
///
bool swapOperands();
+ /// setHasNoUnsignedWrap - Set or clear the nsw flag on this instruction,
+ /// which must be an operator which supports this flag. See LangRef.html
+ /// for the meaning of this flag.
+ void setHasNoUnsignedWrap(bool b = true);
+
+ /// setHasNoSignedWrap - Set or clear the nsw flag on this instruction,
+ /// which must be an operator which supports this flag. See LangRef.html
+ /// for the meaning of this flag.
+ void setHasNoSignedWrap(bool b = true);
+
+ /// setIsExact - Set or clear the exact flag on this instruction,
+ /// which must be an operator which supports this flag. See LangRef.html
+ /// for the meaning of this flag.
+ void setIsExact(bool b = true);
+
+ /// hasNoUnsignedWrap - Determine whether the no unsigned wrap flag is set.
+ bool hasNoUnsignedWrap() const;
+
+ /// hasNoSignedWrap - Determine whether the no signed wrap flag is set.
+ bool hasNoSignedWrap() const;
+
+ /// isExact - Determine whether the exact flag is set.
+ bool isExact() const;
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const BinaryOperator *) { return true; }
static inline bool classof(const Instruction *I) {
@@ -298,7 +343,7 @@ public:
};
template <>
-struct OperandTraits<BinaryOperator> : FixedNumOperandTraits<2> {
+struct OperandTraits<BinaryOperator> : public FixedNumOperandTraits<2> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BinaryOperator, Value)
@@ -711,7 +756,7 @@ public:
// FIXME: these are redundant if CmpInst < BinaryOperator
template <>
-struct OperandTraits<CmpInst> : FixedNumOperandTraits<2> {
+struct OperandTraits<CmpInst> : public FixedNumOperandTraits<2> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CmpInst, Value)
diff --git a/libclamav/c++/llvm/include/llvm/Instruction.h b/libclamav/c++/llvm/include/llvm/Instruction.h
index 189c34a..fdae3d7 100644
--- a/libclamav/c++/llvm/include/llvm/Instruction.h
+++ b/libclamav/c++/llvm/include/llvm/Instruction.h
@@ -47,7 +47,7 @@ public:
/// * The instruction has no parent
/// * The instruction has no name
///
- virtual Instruction *clone(LLVMContext &Context) const = 0;
+ virtual Instruction *clone() const = 0;
/// isIdenticalTo - Return true if the specified instruction is exactly
/// identical to the current one. This means that all operands match and any
diff --git a/libclamav/c++/llvm/include/llvm/Instructions.h b/libclamav/c++/llvm/include/llvm/Instructions.h
index 4460f88..c71d64a 100644
--- a/libclamav/c++/llvm/include/llvm/Instructions.h
+++ b/libclamav/c++/llvm/include/llvm/Instructions.h
@@ -20,6 +20,7 @@
#include "llvm/DerivedTypes.h"
#include "llvm/Attributes.h"
#include "llvm/BasicBlock.h"
+#include "llvm/CallingConv.h"
#include "llvm/LLVMContext.h"
#include "llvm/ADT/SmallVector.h"
#include <iterator>
@@ -30,6 +31,7 @@ class ConstantInt;
class ConstantRange;
class APInt;
class LLVMContext;
+class DominatorTree;
//===----------------------------------------------------------------------===//
// AllocationInst Class
@@ -78,7 +80,7 @@ public:
unsigned getAlignment() const { return (1u << SubclassData) >> 1; }
void setAlignment(unsigned Align);
- virtual AllocationInst *clone(LLVMContext &Context) const = 0;
+ virtual AllocationInst *clone() const = 0;
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const AllocationInst *) { return true; }
@@ -127,7 +129,7 @@ public:
: AllocationInst(Ty, ArraySize,
Malloc, Align, NameStr, InsertBefore) {}
- virtual MallocInst *clone(LLVMContext &Context) const;
+ virtual MallocInst *clone() const;
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const MallocInst *) { return true; }
@@ -177,7 +179,7 @@ public:
: AllocationInst(Ty, ArraySize, Alloca,
Align, NameStr, InsertAtEnd) {}
- virtual AllocaInst *clone(LLVMContext &Context) const;
+ virtual AllocaInst *clone() const;
/// isStaticAlloca - Return true if this alloca is in the entry block of the
/// function and is a constant size. If so, the code generator will fold it
@@ -207,7 +209,7 @@ public:
explicit FreeInst(Value *Ptr, Instruction *InsertBefore = 0);
FreeInst(Value *Ptr, BasicBlock *InsertAfter);
- virtual FreeInst *clone(LLVMContext &Context) const;
+ virtual FreeInst *clone() const;
// Accessor methods for consistency with other memory operations
Value *getPointerOperand() { return getOperand(0); }
@@ -263,7 +265,7 @@ public:
SubclassData = (SubclassData & ~1) | (V ? 1 : 0);
}
- virtual LoadInst *clone(LLVMContext &Context) const;
+ virtual LoadInst *clone() const;
/// getAlignment - Return the alignment of the access that is being performed
///
@@ -340,7 +342,7 @@ public:
void setAlignment(unsigned Align);
- virtual StoreInst *clone(LLVMContext &Context) const;
+ virtual StoreInst *clone() const;
Value *getPointerOperand() { return getOperand(1); }
const Value *getPointerOperand() const { return getOperand(1); }
@@ -361,7 +363,7 @@ public:
};
template <>
-struct OperandTraits<StoreInst> : FixedNumOperandTraits<2> {
+struct OperandTraits<StoreInst> : public FixedNumOperandTraits<2> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(StoreInst, Value)
@@ -494,7 +496,7 @@ public:
Instruction *InsertBefore = 0) {
GetElementPtrInst *GEP = Create(Ptr, IdxBegin, IdxEnd,
NameStr, InsertBefore);
- cast<GEPOperator>(GEP)->setIsInBounds(true);
+ GEP->setIsInBounds(true);
return GEP;
}
template<typename InputIterator>
@@ -505,25 +507,25 @@ public:
BasicBlock *InsertAtEnd) {
GetElementPtrInst *GEP = Create(Ptr, IdxBegin, IdxEnd,
NameStr, InsertAtEnd);
- cast<GEPOperator>(GEP)->setIsInBounds(true);
+ GEP->setIsInBounds(true);
return GEP;
}
static GetElementPtrInst *CreateInBounds(Value *Ptr, Value *Idx,
const Twine &NameStr = "",
Instruction *InsertBefore = 0) {
GetElementPtrInst *GEP = Create(Ptr, Idx, NameStr, InsertBefore);
- cast<GEPOperator>(GEP)->setIsInBounds(true);
+ GEP->setIsInBounds(true);
return GEP;
}
static GetElementPtrInst *CreateInBounds(Value *Ptr, Value *Idx,
const Twine &NameStr,
BasicBlock *InsertAtEnd) {
GetElementPtrInst *GEP = Create(Ptr, Idx, NameStr, InsertAtEnd);
- cast<GEPOperator>(GEP)->setIsInBounds(true);
+ GEP->setIsInBounds(true);
return GEP;
}
- virtual GetElementPtrInst *clone(LLVMContext &Context) const;
+ virtual GetElementPtrInst *clone() const;
/// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
@@ -600,6 +602,13 @@ public:
/// a constant offset between them.
bool hasAllConstantIndices() const;
+ /// setIsInBounds - Set or clear the inbounds flag on this GEP instruction.
+ /// See LangRef.html for the meaning of inbounds on a getelementptr.
+ void setIsInBounds(bool b = true);
+
+ /// isInBounds - Determine whether the GEP has the inbounds flag.
+ bool isInBounds() const;
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const GetElementPtrInst *) { return true; }
static inline bool classof(const Instruction *I) {
@@ -611,7 +620,7 @@ public:
};
template <>
-struct OperandTraits<GetElementPtrInst> : VariadicOperandTraits<1> {
+struct OperandTraits<GetElementPtrInst> : public VariadicOperandTraits<1> {
};
template<typename InputIterator>
@@ -816,7 +825,7 @@ public:
Op<0>().swap(Op<1>());
}
- virtual ICmpInst *clone(LLVMContext &Context) const;
+ virtual ICmpInst *clone() const;
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ICmpInst *) { return true; }
@@ -925,7 +934,7 @@ public:
Op<0>().swap(Op<1>());
}
- virtual FCmpInst *clone(LLVMContext &Context) const;
+ virtual FCmpInst *clone() const;
/// @brief Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const FCmpInst *) { return true; }
@@ -1027,6 +1036,18 @@ public:
BasicBlock *InsertAtEnd) {
return new(1) CallInst(F, NameStr, InsertAtEnd);
}
+ /// CreateMalloc - Generate the IR for a call to malloc:
+ /// 1. Compute the malloc call's argument as the specified type's size,
+ /// possibly multiplied by the array size if the array size is not
+ /// constant 1.
+ /// 2. Call malloc with that argument.
+ /// 3. Bitcast the result of the malloc call to the specified type.
+ static Value *CreateMalloc(Instruction *InsertBefore, const Type *IntPtrTy,
+ const Type *AllocTy, Value *ArraySize = 0,
+ const Twine &Name = "");
+ static Value *CreateMalloc(BasicBlock *InsertAtEnd, const Type *IntPtrTy,
+ const Type *AllocTy, Value *ArraySize = 0,
+ const Twine &Name = "");
~CallInst();
@@ -1035,16 +1056,18 @@ public:
SubclassData = (SubclassData & ~1) | unsigned(isTC);
}
- virtual CallInst *clone(LLVMContext &Context) const;
+ virtual CallInst *clone() const;
/// Provide fast operand accessors
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
/// getCallingConv/setCallingConv - Get or set the calling convention of this
/// function call.
- unsigned getCallingConv() const { return SubclassData >> 1; }
- void setCallingConv(unsigned CC) {
- SubclassData = (SubclassData & 1) | (CC << 1);
+ CallingConv::ID getCallingConv() const {
+ return static_cast<CallingConv::ID>(SubclassData >> 1);
+ }
+ void setCallingConv(CallingConv::ID CC) {
+ SubclassData = (SubclassData & 1) | (static_cast<unsigned>(CC) << 1);
}
/// getAttributes - Return the parameter attributes for this call.
@@ -1140,7 +1163,7 @@ public:
};
template <>
-struct OperandTraits<CallInst> : VariadicOperandTraits<1> {
+struct OperandTraits<CallInst> : public VariadicOperandTraits<1> {
};
template<typename InputIterator>
@@ -1209,10 +1232,13 @@ public:
return new(3) SelectInst(C, S1, S2, NameStr, InsertAtEnd);
}
- Value *getCondition() const { return Op<0>(); }
- Value *getTrueValue() const { return Op<1>(); }
- Value *getFalseValue() const { return Op<2>(); }
-
+ const Value *getCondition() const { return Op<0>(); }
+ const Value *getTrueValue() const { return Op<1>(); }
+ const Value *getFalseValue() const { return Op<2>(); }
+ Value *getCondition() { return Op<0>(); }
+ Value *getTrueValue() { return Op<1>(); }
+ Value *getFalseValue() { return Op<2>(); }
+
/// areInvalidOperands - Return a string if the specified operands are invalid
/// for a select operation, otherwise return null.
static const char *areInvalidOperands(Value *Cond, Value *True, Value *False);
@@ -1224,7 +1250,7 @@ public:
return static_cast<OtherOps>(Instruction::getOpcode());
}
- virtual SelectInst *clone(LLVMContext &Context) const;
+ virtual SelectInst *clone() const;
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SelectInst *) { return true; }
@@ -1237,7 +1263,7 @@ public:
};
template <>
-struct OperandTraits<SelectInst> : FixedNumOperandTraits<3> {
+struct OperandTraits<SelectInst> : public FixedNumOperandTraits<3> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SelectInst, Value)
@@ -1262,7 +1288,7 @@ public:
setName(NameStr);
}
- virtual VAArgInst *clone(LLVMContext &Context) const;
+ virtual VAArgInst *clone() const;
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const VAArgInst *) { return true; }
@@ -1302,8 +1328,18 @@ public:
/// formed with the specified operands.
static bool isValidOperands(const Value *Vec, const Value *Idx);
- virtual ExtractElementInst *clone(LLVMContext &Context) const;
+ virtual ExtractElementInst *clone() const;
+ Value *getVectorOperand() { return Op<0>(); }
+ Value *getIndexOperand() { return Op<1>(); }
+ const Value *getVectorOperand() const { return Op<0>(); }
+ const Value *getIndexOperand() const { return Op<1>(); }
+
+ const VectorType *getVectorOperandType() const {
+ return reinterpret_cast<const VectorType*>(getVectorOperand()->getType());
+ }
+
+
/// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
@@ -1318,7 +1354,7 @@ public:
};
template <>
-struct OperandTraits<ExtractElementInst> : FixedNumOperandTraits<2> {
+struct OperandTraits<ExtractElementInst> : public FixedNumOperandTraits<2> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ExtractElementInst, Value)
@@ -1353,7 +1389,7 @@ public:
static bool isValidOperands(const Value *Vec, const Value *NewElt,
const Value *Idx);
- virtual InsertElementInst *clone(LLVMContext &Context) const;
+ virtual InsertElementInst *clone() const;
/// getType - Overload to return most specific vector type.
///
@@ -1375,7 +1411,7 @@ public:
};
template <>
-struct OperandTraits<InsertElementInst> : FixedNumOperandTraits<3> {
+struct OperandTraits<InsertElementInst> : public FixedNumOperandTraits<3> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InsertElementInst, Value)
@@ -1404,7 +1440,7 @@ public:
static bool isValidOperands(const Value *V1, const Value *V2,
const Value *Mask);
- virtual ShuffleVectorInst *clone(LLVMContext &Context) const;
+ virtual ShuffleVectorInst *clone() const;
/// getType - Overload to return most specific vector type.
///
@@ -1431,7 +1467,7 @@ public:
};
template <>
-struct OperandTraits<ShuffleVectorInst> : FixedNumOperandTraits<3> {
+struct OperandTraits<ShuffleVectorInst> : public FixedNumOperandTraits<3> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ShuffleVectorInst, Value)
@@ -1548,7 +1584,7 @@ public:
return new ExtractValueInst(Agg, Idxs, Idxs + 1, NameStr, InsertAtEnd);
}
- virtual ExtractValueInst *clone(LLVMContext &Context) const;
+ virtual ExtractValueInst *clone() const;
/// getIndexedType - Returns the type of the element that would be extracted
/// with an extractvalue instruction with the specified parameters.
@@ -1718,7 +1754,7 @@ public:
return new InsertValueInst(Agg, Val, Idx, NameStr, InsertAtEnd);
}
- virtual InsertValueInst *clone(LLVMContext &Context) const;
+ virtual InsertValueInst *clone() const;
/// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
@@ -1766,7 +1802,7 @@ public:
};
template <>
-struct OperandTraits<InsertValueInst> : FixedNumOperandTraits<2> {
+struct OperandTraits<InsertValueInst> : public FixedNumOperandTraits<2> {
};
template<typename InputIterator>
@@ -1847,7 +1883,7 @@ public:
resizeOperands(NumValues*2);
}
- virtual PHINode *clone(LLVMContext &Context) const;
+ virtual PHINode *clone() const;
/// Provide fast operand accessors
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
@@ -1947,7 +1983,12 @@ public:
/// hasConstantValue - If the specified PHI node always merges together the
/// same value, return the value, otherwise return null.
///
- Value *hasConstantValue(bool AllowNonDominatingInstruction = false) const;
+ /// If the PHI has undef operands, but all the rest of the operands are
+ /// some unique value, return that value if it can be proved that the
+ /// value dominates the PHI. If DT is null, use a conservative check,
+ /// otherwise use DT to test for dominance.
+ ///
+ Value *hasConstantValue(DominatorTree *DT = 0) const;
/// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const PHINode *) { return true; }
@@ -1962,7 +2003,7 @@ public:
};
template <>
-struct OperandTraits<PHINode> : HungoffOperandTraits<2> {
+struct OperandTraits<PHINode> : public HungoffOperandTraits<2> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(PHINode, Value)
@@ -2009,7 +2050,7 @@ public:
}
virtual ~ReturnInst();
- virtual ReturnInst *clone(LLVMContext &Context) const;
+ virtual ReturnInst *clone() const;
/// Provide fast operand accessors
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
@@ -2038,7 +2079,7 @@ public:
};
template <>
-struct OperandTraits<ReturnInst> : OptionalOperandTraits<> {
+struct OperandTraits<ReturnInst> : public OptionalOperandTraits<> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ReturnInst, Value)
@@ -2091,7 +2132,7 @@ public:
/// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
- virtual BranchInst *clone(LLVMContext &Context) const;
+ virtual BranchInst *clone() const;
bool isUnconditional() const { return getNumOperands() == 1; }
bool isConditional() const { return getNumOperands() == 3; }
@@ -2146,7 +2187,7 @@ private:
};
template <>
-struct OperandTraits<BranchInst> : VariadicOperandTraits<1> {};
+struct OperandTraits<BranchInst> : public VariadicOperandTraits<1> {};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BranchInst, Value)
@@ -2261,7 +2302,7 @@ public:
///
void removeCase(unsigned idx);
- virtual SwitchInst *clone(LLVMContext &Context) const;
+ virtual SwitchInst *clone() const;
unsigned getNumSuccessors() const { return getNumOperands()/2; }
BasicBlock *getSuccessor(unsigned idx) const {
@@ -2295,7 +2336,7 @@ private:
};
template <>
-struct OperandTraits<SwitchInst> : HungoffOperandTraits<2> {
+struct OperandTraits<SwitchInst> : public HungoffOperandTraits<2> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SwitchInst, Value)
@@ -2375,16 +2416,18 @@ public:
Values, NameStr, InsertAtEnd);
}
- virtual InvokeInst *clone(LLVMContext &Context) const;
+ virtual InvokeInst *clone() const;
/// Provide fast operand accessors
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
/// getCallingConv/setCallingConv - Get or set the calling convention of this
/// function call.
- unsigned getCallingConv() const { return SubclassData; }
- void setCallingConv(unsigned CC) {
- SubclassData = CC;
+ CallingConv::ID getCallingConv() const {
+ return static_cast<CallingConv::ID>(SubclassData);
+ }
+ void setCallingConv(CallingConv::ID CC) {
+ SubclassData = static_cast<unsigned>(CC);
}
/// getAttributes - Return the parameter attributes for this invoke.
@@ -2511,7 +2554,7 @@ private:
};
template <>
-struct OperandTraits<InvokeInst> : VariadicOperandTraits<3> {
+struct OperandTraits<InvokeInst> : public VariadicOperandTraits<3> {
};
template<typename InputIterator>
@@ -2563,7 +2606,7 @@ public:
explicit UnwindInst(LLVMContext &C, Instruction *InsertBefore = 0);
explicit UnwindInst(LLVMContext &C, BasicBlock *InsertAtEnd);
- virtual UnwindInst *clone(LLVMContext &Context) const;
+ virtual UnwindInst *clone() const;
unsigned getNumSuccessors() const { return 0; }
@@ -2600,7 +2643,7 @@ public:
explicit UnreachableInst(LLVMContext &C, Instruction *InsertBefore = 0);
explicit UnreachableInst(LLVMContext &C, BasicBlock *InsertAtEnd);
- virtual UnreachableInst *clone(LLVMContext &Context) const;
+ virtual UnreachableInst *clone() const;
unsigned getNumSuccessors() const { return 0; }
@@ -2642,7 +2685,7 @@ public:
);
/// @brief Clone an identical TruncInst
- virtual TruncInst *clone(LLVMContext &Context) const;
+ virtual TruncInst *clone() const;
/// @brief Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const TruncInst *) { return true; }
@@ -2678,7 +2721,7 @@ public:
);
/// @brief Clone an identical ZExtInst
- virtual ZExtInst *clone(LLVMContext &Context) const;
+ virtual ZExtInst *clone() const;
/// @brief Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ZExtInst *) { return true; }
@@ -2714,7 +2757,7 @@ public:
);
/// @brief Clone an identical SExtInst
- virtual SExtInst *clone(LLVMContext &Context) const;
+ virtual SExtInst *clone() const;
/// @brief Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SExtInst *) { return true; }
@@ -2750,7 +2793,7 @@ public:
);
/// @brief Clone an identical FPTruncInst
- virtual FPTruncInst *clone(LLVMContext &Context) const;
+ virtual FPTruncInst *clone() const;
/// @brief Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const FPTruncInst *) { return true; }
@@ -2786,7 +2829,7 @@ public:
);
/// @brief Clone an identical FPExtInst
- virtual FPExtInst *clone(LLVMContext &Context) const;
+ virtual FPExtInst *clone() const;
/// @brief Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const FPExtInst *) { return true; }
@@ -2822,7 +2865,7 @@ public:
);
/// @brief Clone an identical UIToFPInst
- virtual UIToFPInst *clone(LLVMContext &Context) const;
+ virtual UIToFPInst *clone() const;
/// @brief Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const UIToFPInst *) { return true; }
@@ -2858,7 +2901,7 @@ public:
);
/// @brief Clone an identical SIToFPInst
- virtual SIToFPInst *clone(LLVMContext &Context) const;
+ virtual SIToFPInst *clone() const;
/// @brief Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SIToFPInst *) { return true; }
@@ -2894,7 +2937,7 @@ public:
);
/// @brief Clone an identical FPToUIInst
- virtual FPToUIInst *clone(LLVMContext &Context) const;
+ virtual FPToUIInst *clone() const;
/// @brief Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const FPToUIInst *) { return true; }
@@ -2930,7 +2973,7 @@ public:
);
/// @brief Clone an identical FPToSIInst
- virtual FPToSIInst *clone(LLVMContext &Context) const;
+ virtual FPToSIInst *clone() const;
/// @brief Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const FPToSIInst *) { return true; }
@@ -2966,7 +3009,7 @@ public:
);
/// @brief Clone an identical IntToPtrInst
- virtual IntToPtrInst *clone(LLVMContext &Context) const;
+ virtual IntToPtrInst *clone() const;
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const IntToPtrInst *) { return true; }
@@ -3002,7 +3045,7 @@ public:
);
/// @brief Clone an identical PtrToIntInst
- virtual PtrToIntInst *clone(LLVMContext &Context) const;
+ virtual PtrToIntInst *clone() const;
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const PtrToIntInst *) { return true; }
@@ -3038,7 +3081,7 @@ public:
);
/// @brief Clone an identical BitCastInst
- virtual BitCastInst *clone(LLVMContext &Context) const;
+ virtual BitCastInst *clone() const;
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const BitCastInst *) { return true; }
diff --git a/libclamav/c++/llvm/include/llvm/LLVMContext.h b/libclamav/c++/llvm/include/llvm/LLVMContext.h
index 56a640e..42b4ea6 100644
--- a/libclamav/c++/llvm/include/llvm/LLVMContext.h
+++ b/libclamav/c++/llvm/include/llvm/LLVMContext.h
@@ -18,7 +18,7 @@
namespace llvm {
class LLVMContextImpl;
-
+class MetadataContext;
/// This is an important class for using LLVM in a threaded context. It
/// (opaquely) owns and manages the core "global" data of LLVM's core
/// infrastructure, including the type and constant uniquing tables.
@@ -30,6 +30,7 @@ class LLVMContext {
void operator=(LLVMContext&);
public:
LLVMContextImpl* pImpl;
+ MetadataContext &getMetadata();
bool RemoveDeadMetadata();
LLVMContext();
~LLVMContext();
diff --git a/libclamav/c++/llvm/include/llvm/LinkAllPasses.h b/libclamav/c++/llvm/include/llvm/LinkAllPasses.h
index 347dba4..5854fc0 100644
--- a/libclamav/c++/llvm/include/llvm/LinkAllPasses.h
+++ b/libclamav/c++/llvm/include/llvm/LinkAllPasses.h
@@ -64,13 +64,13 @@ namespace {
(void) llvm::createDeadStoreEliminationPass();
(void) llvm::createDeadTypeEliminationPass();
(void) llvm::createEdgeProfilerPass();
+ (void) llvm::createOptimalEdgeProfilerPass();
(void) llvm::createFunctionInliningPass();
(void) llvm::createAlwaysInlinerPass();
(void) llvm::createFunctionProfilerPass();
(void) llvm::createGlobalDCEPass();
(void) llvm::createGlobalOptimizerPass();
(void) llvm::createGlobalsModRefPass();
- (void) llvm::createGVNPREPass();
(void) llvm::createIPConstantPropagationPass();
(void) llvm::createIPSCCPPass();
(void) llvm::createIndVarSimplifyPass();
@@ -94,6 +94,7 @@ namespace {
(void) llvm::createNoAAPass();
(void) llvm::createNoProfileInfoPass();
(void) llvm::createProfileEstimatorPass();
+ (void) llvm::createProfileVerifierPass();
(void) llvm::createProfileLoaderPass();
(void) llvm::createPromoteMemoryToRegisterPass();
(void) llvm::createDemoteRegisterToMemoryPass();
@@ -118,6 +119,7 @@ namespace {
(void) llvm::createIndMemRemPass();
(void) llvm::createInstCountPass();
(void) llvm::createPredicateSimplifierPass();
+ (void) llvm::createCodeGenLICMPass();
(void) llvm::createCodeGenPreparePass();
(void) llvm::createGVNPass();
(void) llvm::createMemCpyOptPass();
diff --git a/libclamav/c++/llvm/include/llvm/MC/MCAsmInfo.h b/libclamav/c++/llvm/include/llvm/MC/MCAsmInfo.h
index a3959e5..fb69630 100644
--- a/libclamav/c++/llvm/include/llvm/MC/MCAsmInfo.h
+++ b/libclamav/c++/llvm/include/llvm/MC/MCAsmInfo.h
@@ -84,33 +84,6 @@ namespace llvm {
/// is "l" on Darwin, currently used for some ObjC metadata.
const char *LinkerPrivateGlobalPrefix; // Defaults to ""
- /// JumpTableSpecialLabelPrefix - If not null, a extra (dead) label is
- /// emitted before jump tables with the specified prefix.
- const char *JumpTableSpecialLabelPrefix; // Default to null.
-
- /// GlobalVarAddrPrefix/Suffix - If these are nonempty, these strings
- /// will enclose any GlobalVariable (that isn't a function)
- ///
- const char *GlobalVarAddrPrefix; // Defaults to ""
- const char *GlobalVarAddrSuffix; // Defaults to ""
-
- /// FunctionAddrPrefix/Suffix - If these are nonempty, these strings
- /// will enclose any GlobalVariable that points to a function.
- ///
- const char *FunctionAddrPrefix; // Defaults to ""
- const char *FunctionAddrSuffix; // Defaults to ""
-
- /// PersonalityPrefix/Suffix - If these are nonempty, these strings will
- /// enclose any personality function in the common frame section.
- ///
- const char *PersonalityPrefix; // Defaults to ""
- const char *PersonalitySuffix; // Defaults to ""
-
- /// NeedsIndirectEncoding - If set, we need to set the indirect encoding bit
- /// for EH in Dwarf.
- ///
- bool NeedsIndirectEncoding; // Defaults to false
-
/// InlineAsmStart/End - If these are nonempty, they contain a directive to
/// emit before and after an inline assembly statement.
const char *InlineAsmStart; // Defaults to "#APP\n"
@@ -122,6 +95,10 @@ namespace llvm {
/// AllowQuotesInName - This is true if the assembler allows for complex
/// symbol names to be surrounded in quotes. This defaults to false.
bool AllowQuotesInName;
+
+ /// AllowNameToStartWithDigit - This is true if the assembler allows symbol
+ /// names to start with a digit (e.g., "0x0021"). This defaults to false.
+ bool AllowNameToStartWithDigit;
//===--- Data Emission Directives -------------------------------------===//
@@ -369,30 +346,6 @@ namespace llvm {
const char *getLinkerPrivateGlobalPrefix() const {
return LinkerPrivateGlobalPrefix;
}
- const char *getJumpTableSpecialLabelPrefix() const {
- return JumpTableSpecialLabelPrefix;
- }
- const char *getGlobalVarAddrPrefix() const {
- return GlobalVarAddrPrefix;
- }
- const char *getGlobalVarAddrSuffix() const {
- return GlobalVarAddrSuffix;
- }
- const char *getFunctionAddrPrefix() const {
- return FunctionAddrPrefix;
- }
- const char *getFunctionAddrSuffix() const {
- return FunctionAddrSuffix;
- }
- const char *getPersonalityPrefix() const {
- return PersonalityPrefix;
- }
- const char *getPersonalitySuffix() const {
- return PersonalitySuffix;
- }
- bool getNeedsIndirectEncoding() const {
- return NeedsIndirectEncoding;
- }
const char *getInlineAsmStart() const {
return InlineAsmStart;
}
@@ -405,6 +358,9 @@ namespace llvm {
bool doesAllowQuotesInName() const {
return AllowQuotesInName;
}
+ bool doesAllowNameToStartWithDigit() const {
+ return AllowNameToStartWithDigit;
+ }
const char *getZeroDirective() const {
return ZeroDirective;
}
diff --git a/libclamav/c++/llvm/include/llvm/MC/MCAsmLexer.h b/libclamav/c++/llvm/include/llvm/MC/MCAsmLexer.h
index 43bbfd2..e66425a 100644
--- a/libclamav/c++/llvm/include/llvm/MC/MCAsmLexer.h
+++ b/libclamav/c++/llvm/include/llvm/MC/MCAsmLexer.h
@@ -27,7 +27,6 @@ struct AsmToken {
// String values.
Identifier,
- Register,
String,
// Integer values.
@@ -38,11 +37,11 @@ struct AsmToken {
Colon,
Plus, Minus, Tilde,
Slash, // '/'
- LParen, RParen,
+ LParen, RParen, LBrac, RBrac, LCurly, RCurly,
Star, Comma, Dollar, Equal, EqualEqual,
Pipe, PipePipe, Caret,
- Amp, AmpAmp, Exclaim, ExclaimEqual, Percent,
+ Amp, AmpAmp, Exclaim, ExclaimEqual, Percent, Hash,
Less, LessEqual, LessLess, LessGreater,
Greater, GreaterEqual, GreaterGreater
};
diff --git a/libclamav/c++/llvm/include/llvm/MC/MCAsmParser.h b/libclamav/c++/llvm/include/llvm/MC/MCAsmParser.h
index 8c1b7b8..c1b5d13 100644
--- a/libclamav/c++/llvm/include/llvm/MC/MCAsmParser.h
+++ b/libclamav/c++/llvm/include/llvm/MC/MCAsmParser.h
@@ -16,6 +16,7 @@ namespace llvm {
class MCAsmLexer;
class MCContext;
class MCExpr;
+class MCStreamer;
class MCValue;
class SMLoc;
class Twine;
@@ -35,6 +36,9 @@ public:
virtual MCContext &getContext() = 0;
+ /// getSteamer - Return the output streamer for the assembler.
+ virtual MCStreamer &getStreamer() = 0;
+
/// Warning - Emit a warning at the location \arg L, with the message \arg
/// Msg.
virtual void Warning(SMLoc L, const Twine &Msg) = 0;
diff --git a/libclamav/c++/llvm/include/llvm/MC/MCAssembler.h b/libclamav/c++/llvm/include/llvm/MC/MCAssembler.h
index 44fc2e1..892f548 100644
--- a/libclamav/c++/llvm/include/llvm/MC/MCAssembler.h
+++ b/libclamav/c++/llvm/include/llvm/MC/MCAssembler.h
@@ -437,7 +437,7 @@ public:
// FIXME: Same concerns as with SectionData.
class MCSymbolData : public ilist_node<MCSymbolData> {
public:
- const MCSymbol &Symbol;
+ const MCSymbol *Symbol;
/// Fragment - The fragment this symbol's value is relative to, if any.
MCFragment *Fragment;
@@ -480,7 +480,7 @@ public:
/// @name Accessors
/// @{
- const MCSymbol &getSymbol() const { return Symbol; }
+ const MCSymbol &getSymbol() const { return *Symbol; }
MCFragment *getFragment() const { return Fragment; }
void setFragment(MCFragment *Value) { Fragment = Value; }
diff --git a/libclamav/c++/llvm/include/llvm/MC/MCDisassembler.h b/libclamav/c++/llvm/include/llvm/MC/MCDisassembler.h
new file mode 100644
index 0000000..ef10b80
--- /dev/null
+++ b/libclamav/c++/llvm/include/llvm/MC/MCDisassembler.h
@@ -0,0 +1,50 @@
+//===-- llvm/MC/MCDisassembler.h - Disassembler interface -------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+#ifndef MCDISASSEMBLER_H
+#define MCDISASSEMBLER_H
+
+#include "llvm/Support/DataTypes.h"
+
+namespace llvm {
+
+class MCInst;
+class MemoryObject;
+class raw_ostream;
+
+/// MCDisassembler - Superclass for all disassemblers. Consumes a memory region
+/// and provides an array of assembly instructions.
+class MCDisassembler {
+public:
+ /// Constructor - Performs initial setup for the disassembler.
+ MCDisassembler() {}
+
+ virtual ~MCDisassembler();
+
+ /// getInstruction - Returns the disassembly of a single instruction.
+ ///
+ /// @param instr - An MCInst to populate with the contents of the
+ /// instruction.
+ /// @param size - A value to populate with the size of the instruction, or
+ /// the number of bytes consumed while attempting to decode
+ /// an invalid instruction.
+ /// @param region - The memory object to use as a source for machine code.
+ /// @param address - The address, in the memory space of region, of the first
+ /// byte of the instruction.
+ /// @param vStream - The stream to print warnings and diagnostic messages on.
+ /// @return - True if the instruction is valid; false otherwise.
+ virtual bool getInstruction(MCInst& instr,
+ uint64_t& size,
+ const MemoryObject ®ion,
+ uint64_t address,
+ raw_ostream &vStream) const = 0;
+};
+
+} // namespace llvm
+
+#endif
diff --git a/libclamav/c++/llvm/include/llvm/MC/MCExpr.h b/libclamav/c++/llvm/include/llvm/MC/MCExpr.h
index 9f9f267..19a32e7 100644
--- a/libclamav/c++/llvm/include/llvm/MC/MCExpr.h
+++ b/libclamav/c++/llvm/include/llvm/MC/MCExpr.h
@@ -14,10 +14,12 @@
#include "llvm/Support/DataTypes.h"
namespace llvm {
+class MCAsmInfo;
class MCContext;
class MCSymbol;
class MCValue;
class raw_ostream;
+class StringRef;
/// MCExpr - Base class for the full range of assembler expressions which are
/// needed for parsing.
@@ -49,7 +51,7 @@ public:
/// @name Utility Methods
/// @{
- void print(raw_ostream &OS) const;
+ void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
void dump() const;
/// @}
@@ -118,7 +120,10 @@ public:
/// @{
static const MCSymbolRefExpr *Create(const MCSymbol *Symbol, MCContext &Ctx);
-
+ static const MCSymbolRefExpr *Create(const StringRef &Name, MCContext &Ctx);
+
+
+
/// @}
/// @name Accessors
/// @{
diff --git a/libclamav/c++/llvm/include/llvm/MC/MCInst.h b/libclamav/c++/llvm/include/llvm/MC/MCInst.h
index 7c1cb13..0fc4d18 100644
--- a/libclamav/c++/llvm/include/llvm/MC/MCInst.h
+++ b/libclamav/c++/llvm/include/llvm/MC/MCInst.h
@@ -18,10 +18,10 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/DataTypes.h"
-#include "llvm/Support/DebugLoc.h"
namespace llvm {
class raw_ostream;
+class MCAsmInfo;
class MCExpr;
/// MCOperand - Instances of this class represent operands of the MCInst class.
@@ -31,7 +31,6 @@ class MCOperand {
kInvalid, ///< Uninitialized.
kRegister, ///< Register operand.
kImmediate, ///< Immediate operand.
- kMBBLabel, ///< Basic block label.
kExpr ///< Relocatable immediate operand.
};
unsigned char Kind;
@@ -40,10 +39,6 @@ class MCOperand {
unsigned RegVal;
int64_t ImmVal;
const MCExpr *ExprVal;
- struct {
- unsigned FunctionNo;
- unsigned BlockNo;
- } MBBLabel;
};
public:
@@ -53,7 +48,6 @@ public:
bool isValid() const { return Kind != kInvalid; }
bool isReg() const { return Kind == kRegister; }
bool isImm() const { return Kind == kImmediate; }
- bool isMBBLabel() const { return Kind == kMBBLabel; }
bool isExpr() const { return Kind == kExpr; }
/// getReg - Returns the register number.
@@ -77,15 +71,6 @@ public:
ImmVal = Val;
}
- unsigned getMBBLabelFunction() const {
- assert(isMBBLabel() && "This is not a machine basic block");
- return MBBLabel.FunctionNo;
- }
- unsigned getMBBLabelBlock() const {
- assert(isMBBLabel() && "This is not a machine basic block");
- return MBBLabel.BlockNo;
- }
-
const MCExpr *getExpr() const {
assert(isExpr() && "This is not an expression");
return ExprVal;
@@ -107,13 +92,6 @@ public:
Op.ImmVal = Val;
return Op;
}
- static MCOperand CreateMBBLabel(unsigned Fn, unsigned MBB) {
- MCOperand Op;
- Op.Kind = kMBBLabel;
- Op.MBBLabel.FunctionNo = Fn;
- Op.MBBLabel.BlockNo = MBB;
- return Op;
- }
static MCOperand CreateExpr(const MCExpr *Val) {
MCOperand Op;
Op.Kind = kExpr;
@@ -121,7 +99,7 @@ public:
return Op;
}
- void print(raw_ostream &OS) const;
+ void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
void dump() const;
};
@@ -132,13 +110,12 @@ class MCInst {
unsigned Opcode;
SmallVector<MCOperand, 8> Operands;
public:
- MCInst() : Opcode(~0U) {}
+ MCInst() : Opcode(0) {}
void setOpcode(unsigned Op) { Opcode = Op; }
unsigned getOpcode() const { return Opcode; }
- DebugLoc getDebugLoc() const { return DebugLoc(); }
-
+
const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
MCOperand &getOperand(unsigned i) { return Operands[i]; }
unsigned getNumOperands() const { return Operands.size(); }
@@ -147,7 +124,7 @@ public:
Operands.push_back(Op);
}
- void print(raw_ostream &OS) const;
+ void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
void dump() const;
};
diff --git a/libclamav/c++/llvm/include/llvm/MC/MCInstPrinter.h b/libclamav/c++/llvm/include/llvm/MC/MCInstPrinter.h
new file mode 100644
index 0000000..d62a9da
--- /dev/null
+++ b/libclamav/c++/llvm/include/llvm/MC/MCInstPrinter.h
@@ -0,0 +1,37 @@
+//===-- MCInstPrinter.h - Convert an MCInst to target assembly syntax -----===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MC_MCINSTPRINTER_H
+#define LLVM_MC_MCINSTPRINTER_H
+
+namespace llvm {
+class MCInst;
+class raw_ostream;
+class MCAsmInfo;
+
+
+/// MCInstPrinter - This is an instance of a target assembly language printer
+/// that converts an MCInst to valid target assembly syntax.
+class MCInstPrinter {
+protected:
+ raw_ostream &O;
+ const MCAsmInfo &MAI;
+public:
+ MCInstPrinter(raw_ostream &o, const MCAsmInfo &mai) : O(o), MAI(mai) {}
+
+ virtual ~MCInstPrinter();
+
+ /// printInst - Print the specified MCInst to the current raw_ostream.
+ ///
+ virtual void printInst(const MCInst *MI) = 0;
+};
+
+} // namespace llvm
+
+#endif
diff --git a/libclamav/c++/llvm/include/llvm/MC/MCStreamer.h b/libclamav/c++/llvm/include/llvm/MC/MCStreamer.h
index 224fbf4..248e6b0 100644
--- a/libclamav/c++/llvm/include/llvm/MC/MCStreamer.h
+++ b/libclamav/c++/llvm/include/llvm/MC/MCStreamer.h
@@ -17,12 +17,12 @@
#include "llvm/Support/DataTypes.h"
namespace llvm {
- class AsmPrinter;
class MCAsmInfo;
class MCCodeEmitter;
class MCContext;
class MCExpr;
class MCInst;
+ class MCInstPrinter;
class MCSection;
class MCSymbol;
class StringRef;
@@ -217,10 +217,9 @@ namespace llvm {
/// createAsmStreamer - Create a machine code streamer which will print out
/// assembly for the native target, suitable for compiling with a native
/// assembler.
- ///
- /// \arg AP - If given, an AsmPrinter to use for printing instructions.
MCStreamer *createAsmStreamer(MCContext &Ctx, raw_ostream &OS,
- const MCAsmInfo &MAI, AsmPrinter *AP = 0,
+ const MCAsmInfo &MAI,
+ MCInstPrinter *InstPrint = 0,
MCCodeEmitter *CE = 0);
// FIXME: These two may end up getting rolled into a single
diff --git a/libclamav/c++/llvm/include/llvm/MC/MCSymbol.h b/libclamav/c++/llvm/include/llvm/MC/MCSymbol.h
index 631fa12..5dd7d68 100644
--- a/libclamav/c++/llvm/include/llvm/MC/MCSymbol.h
+++ b/libclamav/c++/llvm/include/llvm/MC/MCSymbol.h
@@ -19,6 +19,7 @@
#include "llvm/Support/DataTypes.h"
namespace llvm {
+ class MCAsmInfo;
class MCSection;
class MCContext;
class raw_ostream;
@@ -106,7 +107,7 @@ namespace llvm {
/// @}
/// print - Print the value to the stream \arg OS.
- void print(raw_ostream &OS) const;
+ void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
/// dump - Print the value to stderr.
void dump() const;
diff --git a/libclamav/c++/llvm/include/llvm/MC/MCValue.h b/libclamav/c++/llvm/include/llvm/MC/MCValue.h
index 9d71209..62aca6e 100644
--- a/libclamav/c++/llvm/include/llvm/MC/MCValue.h
+++ b/libclamav/c++/llvm/include/llvm/MC/MCValue.h
@@ -55,7 +55,7 @@ public:
const MCSection *getAssociatedSection() const;
/// print - Print the value to the stream \arg OS.
- void print(raw_ostream &OS) const;
+ void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
/// dump - Print the value to stderr.
void dump() const;
diff --git a/libclamav/c++/llvm/include/llvm/Metadata.h b/libclamav/c++/llvm/include/llvm/Metadata.h
index b38336b..e441481 100644
--- a/libclamav/c++/llvm/include/llvm/Metadata.h
+++ b/libclamav/c++/llvm/include/llvm/Metadata.h
@@ -19,16 +19,19 @@
#include "llvm/User.h"
#include "llvm/Type.h"
#include "llvm/OperandTraits.h"
+#include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/ilist_node.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/ValueHandle.h"
namespace llvm {
class Constant;
+class Instruction;
class LLVMContext;
-template<class ConstantClass, class TypeClass, class ValType>
-struct ConstantCreator;
//===----------------------------------------------------------------------===//
// MetadataBase - A base class for MDNode, MDString and NamedMDNode.
@@ -103,14 +106,32 @@ public:
/// MDNode - a tuple of other values.
/// These contain a list of the values that represent the metadata.
/// MDNode is always unnamed.
-class MDNode : public MetadataBase {
+class MDNode : public MetadataBase, public FoldingSetNode {
MDNode(const MDNode &); // DO NOT IMPLEMENT
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT
// getNumOperands - Make this only available for private uses.
unsigned getNumOperands() { return User::getNumOperands(); }
- SmallVector<WeakVH, 4> Node;
- friend struct ConstantCreator<MDNode, Type, std::vector<Value*> >;
+ friend class ElementVH;
+ // Use CallbackVH to hold MDNOde elements.
+ struct ElementVH : public CallbackVH {
+ MDNode *Parent;
+ ElementVH(Value *V, MDNode *P) : CallbackVH(V), Parent(P) {}
+ ~ElementVH() {}
+
+ virtual void deleted() {
+ Parent->replaceElement(this->operator Value*(), 0);
+ }
+
+ virtual void allUsesReplacedWith(Value *NV) {
+ Parent->replaceElement(this->operator Value*(), NV);
+ }
+ };
+ // Replace each instance of F from the element list of this node with T.
+ void replaceElement(Value *F, Value *T);
+
+ SmallVector<ElementVH, 4> Node;
+
protected:
explicit MDNode(LLVMContext &C, Value*const* Vals, unsigned NumVals);
public:
@@ -140,8 +161,8 @@ public:
}
// Element access
- typedef SmallVectorImpl<WeakVH>::const_iterator const_elem_iterator;
- typedef SmallVectorImpl<WeakVH>::iterator elem_iterator;
+ typedef SmallVectorImpl<ElementVH>::const_iterator const_elem_iterator;
+ typedef SmallVectorImpl<ElementVH>::iterator elem_iterator;
/// elem_empty - Return true if MDNode is empty.
bool elem_empty() const { return Node.empty(); }
const_elem_iterator elem_begin() const { return Node.begin(); }
@@ -156,6 +177,10 @@ public:
return false;
}
+ /// Profile - calculate a unique identifier for this MDNode to collapse
+ /// duplicates
+ void Profile(FoldingSetNodeID &ID) const;
+
virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U) {
llvm_unreachable("This should never be called because MDNodes have no ops");
}
@@ -278,6 +303,70 @@ public:
}
};
+//===----------------------------------------------------------------------===//
+/// MetadataContext -
+/// MetadataContext handles uniquing and assignment of IDs for custom metadata
+/// types. Custom metadata handler names do not contain spaces. And the name
+/// must start with an alphabet. The regular expression used to check name
+/// is [a-zA-Z$._][a-zA-Z$._0-9]*
+class MetadataContext {
+public:
+ typedef std::pair<unsigned, WeakVH> MDPairTy;
+ typedef SmallVector<MDPairTy, 2> MDMapTy;
+ typedef DenseMap<const Instruction *, MDMapTy> MDStoreTy;
+ friend class BitcodeReader;
+private:
+
+ /// MetadataStore - Collection of metadata used in this context.
+ MDStoreTy MetadataStore;
+
+ /// MDHandlerNames - Map to hold metadata handler names.
+ StringMap<unsigned> MDHandlerNames;
+
+public:
+ /// RegisterMDKind - Register a new metadata kind and return its ID.
+ /// A metadata kind can be registered only once.
+ unsigned RegisterMDKind(const char *Name);
+
+ /// getMDKind - Return metadata kind. If the requested metadata kind
+ /// is not registered then return 0.
+ unsigned getMDKind(const char *Name);
+
+ /// validName - Return true if Name is a valid custom metadata handler name.
+ bool validName(const char *Name);
+
+ /// getMD - Get the metadata of given kind attached with an Instruction.
+ /// If the metadata is not found then return 0.
+ MDNode *getMD(unsigned Kind, const Instruction *Inst);
+
+ /// getMDs - Get the metadata attached with an Instruction.
+ const MDMapTy *getMDs(const Instruction *Inst);
+
+ /// addMD - Attach the metadata of given kind with an Instruction.
+ void addMD(unsigned Kind, MDNode *Node, Instruction *Inst);
+
+ /// removeMD - Remove metadata of given kind attached with an instuction.
+ void removeMD(unsigned Kind, Instruction *Inst);
+
+ /// removeMDs - Remove all metadata attached with an instruction.
+ void removeMDs(const Instruction *Inst);
+
+ /// getHandlerNames - Get handler names. This is used by bitcode
+ /// writer.
+ const StringMap<unsigned> *getHandlerNames();
+
+ /// ValueIsDeleted - This handler is used to update metadata store
+ /// when a value is deleted.
+ void ValueIsDeleted(const Value *V) {}
+ void ValueIsDeleted(const Instruction *Inst) {
+ removeMDs(Inst);
+ }
+
+ /// ValueIsCloned - This handler is used to update metadata store
+ /// when In1 is cloned to create In2.
+ void ValueIsCloned(const Instruction *In1, Instruction *In2);
+};
+
} // end llvm namespace
#endif
diff --git a/libclamav/c++/llvm/include/llvm/OperandTraits.h b/libclamav/c++/llvm/include/llvm/OperandTraits.h
index 3702a01..7c879c8 100644
--- a/libclamav/c++/llvm/include/llvm/OperandTraits.h
+++ b/libclamav/c++/llvm/include/llvm/OperandTraits.h
@@ -44,7 +44,7 @@ struct FixedNumOperandTraits {
};
template <class U>
struct Layout {
- struct overlay : prefix, U {
+ struct overlay : public prefix, public U {
overlay(); // DO NOT IMPLEMENT
};
};
@@ -55,7 +55,7 @@ struct FixedNumOperandTraits {
//===----------------------------------------------------------------------===//
template <unsigned ARITY = 1>
-struct OptionalOperandTraits : FixedNumOperandTraits<ARITY> {
+struct OptionalOperandTraits : public FixedNumOperandTraits<ARITY> {
static unsigned operands(const User *U) {
return U->getNumOperands();
}
diff --git a/libclamav/c++/llvm/include/llvm/Operator.h b/libclamav/c++/llvm/include/llvm/Operator.h
index 48ac09d..2b5cc57 100644
--- a/libclamav/c++/llvm/include/llvm/Operator.h
+++ b/libclamav/c++/llvm/include/llvm/Operator.h
@@ -21,6 +21,8 @@
namespace llvm {
class GetElementPtrInst;
+class BinaryOperator;
+class ConstantExpr;
/// Operator - This is a utility class that provides an abstraction for the
/// common functionality between Instructions and ConstantExprs.
@@ -67,24 +69,37 @@ public:
/// despite that operator having the potential for overflow.
///
class OverflowingBinaryOperator : public Operator {
+public:
+ enum {
+ NoUnsignedWrap = (1 << 0),
+ NoSignedWrap = (1 << 1)
+ };
+
+private:
~OverflowingBinaryOperator(); // do not implement
+
+ friend class BinaryOperator;
+ friend class ConstantExpr;
+ void setHasNoUnsignedWrap(bool B) {
+ SubclassOptionalData =
+ (SubclassOptionalData & ~NoUnsignedWrap) | (B * NoUnsignedWrap);
+ }
+ void setHasNoSignedWrap(bool B) {
+ SubclassOptionalData =
+ (SubclassOptionalData & ~NoSignedWrap) | (B * NoSignedWrap);
+ }
+
public:
/// hasNoUnsignedWrap - Test whether this operation is known to never
/// undergo unsigned overflow, aka the nuw property.
bool hasNoUnsignedWrap() const {
- return SubclassOptionalData & (1 << 0);
- }
- void setHasNoUnsignedWrap(bool B) {
- SubclassOptionalData = (SubclassOptionalData & ~(1 << 0)) | (B << 0);
+ return SubclassOptionalData & NoUnsignedWrap;
}
/// hasNoSignedWrap - Test whether this operation is known to never
/// undergo signed overflow, aka the nsw property.
bool hasNoSignedWrap() const {
- return SubclassOptionalData & (1 << 1);
- }
- void setHasNoSignedWrap(bool B) {
- SubclassOptionalData = (SubclassOptionalData & ~(1 << 1)) | (B << 1);
+ return SubclassOptionalData & NoSignedWrap;
}
static inline bool classof(const OverflowingBinaryOperator *) { return true; }
@@ -161,15 +176,25 @@ public:
/// SDivOperator - An Operator with opcode Instruction::SDiv.
///
class SDivOperator : public Operator {
+public:
+ enum {
+ IsExact = (1 << 0)
+ };
+
+private:
~SDivOperator(); // do not implement
+
+ friend class BinaryOperator;
+ friend class ConstantExpr;
+ void setIsExact(bool B) {
+ SubclassOptionalData = (SubclassOptionalData & ~IsExact) | (B * IsExact);
+ }
+
public:
/// isExact - Test whether this division is known to be exact, with
/// zero remainder.
bool isExact() const {
- return SubclassOptionalData & (1 << 0);
- }
- void setIsExact(bool B) {
- SubclassOptionalData = (SubclassOptionalData & ~(1 << 0)) | (B << 0);
+ return SubclassOptionalData & IsExact;
}
// Methods for support type inquiry through isa, cast, and dyn_cast:
@@ -187,15 +212,24 @@ public:
};
class GEPOperator : public Operator {
+ enum {
+ IsInBounds = (1 << 0)
+ };
+
~GEPOperator(); // do not implement
+
+ friend class GetElementPtrInst;
+ friend class ConstantExpr;
+ void setIsInBounds(bool B) {
+ SubclassOptionalData =
+ (SubclassOptionalData & ~IsInBounds) | (B * IsInBounds);
+ }
+
public:
/// isInBounds - Test whether this is an inbounds GEP, as defined
/// by LangRef.html.
bool isInBounds() const {
- return SubclassOptionalData & (1 << 0);
- }
- void setIsInBounds(bool B) {
- SubclassOptionalData = (SubclassOptionalData & ~(1 << 0)) | (B << 0);
+ return SubclassOptionalData & IsInBounds;
}
inline op_iterator idx_begin() { return op_begin()+1; }
@@ -240,6 +274,18 @@ public:
return true;
}
+ /// hasAllConstantIndices - Return true if all of the indices of this GEP are
+ /// constant integers. If so, the result pointer and the first operand have
+ /// a constant offset between them.
+ bool hasAllConstantIndices() const {
+ for (const_op_iterator I = idx_begin(), E = idx_end(); I != E; ++I) {
+ if (!isa<ConstantInt>(I))
+ return false;
+ }
+ return true;
+ }
+
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const GEPOperator *) { return true; }
static inline bool classof(const GetElementPtrInst *) { return true; }
diff --git a/libclamav/c++/llvm/include/llvm/Pass.h b/libclamav/c++/llvm/include/llvm/Pass.h
index a214e4f..f3f71c8 100644
--- a/libclamav/c++/llvm/include/llvm/Pass.h
+++ b/libclamav/c++/llvm/include/llvm/Pass.h
@@ -191,7 +191,7 @@ public:
AnalysisType &getAnalysis() const; // Defined in PassAnalysisSupport.h
template<typename AnalysisType>
- AnalysisType &getAnalysis(Function &F); // Defined in PassanalysisSupport.h
+ AnalysisType &getAnalysis(Function &F); // Defined in PassAnalysisSupport.h
template<typename AnalysisType>
AnalysisType &getAnalysisID(const PassInfo *PI) const;
diff --git a/libclamav/c++/llvm/include/llvm/PassManagers.h b/libclamav/c++/llvm/include/llvm/PassManagers.h
index 1c4c741..5a8f555 100644
--- a/libclamav/c++/llvm/include/llvm/PassManagers.h
+++ b/libclamav/c++/llvm/include/llvm/PassManagers.h
@@ -95,6 +95,7 @@ namespace llvm {
class Pass;
class StringRef;
class Value;
+ class Timer;
/// FunctionPassManager and PassManager, two top level managers, serve
/// as the public interface of pass manager infrastructure.
@@ -279,16 +280,17 @@ public:
/// verifyPreservedAnalysis -- Verify analysis presreved by pass P.
void verifyPreservedAnalysis(Pass *P);
- /// verifyDomInfo -- Verify dominator information if it is available.
- void verifyDomInfo(Pass &P, Function &F);
-
/// Remove Analysis that is not preserved by the pass
void removeNotPreservedAnalysis(Pass *P);
- /// Remove dead passes
+ /// Remove dead passes used by P.
void removeDeadPasses(Pass *P, const StringRef &Msg,
enum PassDebuggingString);
+ /// Remove P.
+ void freePass(Pass *P, const StringRef &Msg,
+ enum PassDebuggingString);
+
/// Add pass P into the PassVector. Update
/// AvailableAnalysis appropriately if ProcessAnalysis is true.
void add(Pass *P, bool ProcessAnalysis = true);
@@ -380,6 +382,11 @@ protected:
// then PMT_Last active pass mangers.
std::map<AnalysisID, Pass *> *InheritedAnalysis[PMT_Last];
+
+ /// isPassDebuggingExecutionsOrMore - Return true if -debug-pass=Executions
+ /// or higher is specified.
+ bool isPassDebuggingExecutionsOrMore() const;
+
private:
void dumpAnalysisUsage(const StringRef &Msg, const Pass *P,
const AnalysisUsage::VectorType &Set) const;
@@ -451,8 +458,8 @@ public:
}
};
-extern void StartPassTimer(llvm::Pass *);
-extern void StopPassTimer(llvm::Pass *);
+extern Timer *StartPassTimer(Pass *);
+extern void StopPassTimer(Pass *, Timer *);
}
diff --git a/libclamav/c++/llvm/include/llvm/Support/CallSite.h b/libclamav/c++/llvm/include/llvm/Support/CallSite.h
index 0a21060..285b558 100644
--- a/libclamav/c++/llvm/include/llvm/Support/CallSite.h
+++ b/libclamav/c++/llvm/include/llvm/Support/CallSite.h
@@ -26,6 +26,7 @@
#include "llvm/Attributes.h"
#include "llvm/ADT/PointerIntPair.h"
#include "llvm/BasicBlock.h"
+#include "llvm/CallingConv.h"
#include "llvm/Instruction.h"
namespace llvm {
@@ -61,8 +62,8 @@ public:
/// getCallingConv/setCallingConv - get or set the calling convention of the
/// call.
- unsigned getCallingConv() const;
- void setCallingConv(unsigned CC);
+ CallingConv::ID getCallingConv() const;
+ void setCallingConv(CallingConv::ID CC);
/// getAttributes/setAttributes - get or set the parameter attributes of
/// the call.
diff --git a/libclamav/c++/llvm/include/llvm/Support/CommandLine.h b/libclamav/c++/llvm/include/llvm/Support/CommandLine.h
index de12f6f..4fcca1d 100644
--- a/libclamav/c++/llvm/include/llvm/Support/CommandLine.h
+++ b/libclamav/c++/llvm/include/llvm/Support/CommandLine.h
@@ -21,18 +21,17 @@
#define LLVM_SUPPORT_COMMANDLINE_H
#include "llvm/Support/type_traits.h"
-#include "llvm/Support/DataTypes.h"
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Twine.h"
#include <cassert>
#include <climits>
#include <cstdarg>
-#include <string>
#include <utility>
#include <vector>
namespace llvm {
-
+
/// cl Namespace - This namespace contains all of the command line option
/// processing machinery. It is intentionally a short name to make qualified
/// usage concise.
@@ -143,8 +142,8 @@ class Option {
// an argument. Should return true if there was an error processing the
// argument and the program should exit.
//
- virtual bool handleOccurrence(unsigned pos, const char *ArgName,
- const std::string &Arg) = 0;
+ virtual bool handleOccurrence(unsigned pos, StringRef ArgName,
+ StringRef Arg) = 0;
virtual enum ValueExpected getValueExpectedFlagDefault() const {
return ValueOptional;
@@ -215,8 +214,7 @@ protected:
getOptionHiddenFlag() != 0 && "Not all default flags specified!");
}
- inline void setNumAdditionalVals(unsigned n)
- { AdditionalVals = n; }
+ inline void setNumAdditionalVals(unsigned n) { AdditionalVals = n; }
public:
// addArgument - Register this argument with the commandline system.
//
@@ -232,15 +230,15 @@ public:
//
virtual void printOptionInfo(size_t GlobalWidth) const = 0;
- virtual void getExtraOptionNames(std::vector<const char*> &) {}
+ virtual void getExtraOptionNames(SmallVectorImpl<const char*> &) {}
- // addOccurrence - Wrapper around handleOccurrence that enforces Flags
+ // addOccurrence - Wrapper around handleOccurrence that enforces Flags.
//
- bool addOccurrence(unsigned pos, const char *ArgName,
- const std::string &Value, bool MultiArg = false);
+ bool addOccurrence(unsigned pos, StringRef ArgName,
+ StringRef Value, bool MultiArg = false);
// Prints option name followed by message. Always returns true.
- bool error(std::string Message, const char *ArgName = 0);
+ bool error(const Twine &Message, StringRef ArgName = StringRef());
public:
inline int getNumOccurrences() const { return NumOccurrences; }
@@ -399,7 +397,7 @@ struct generic_parser_base {
hasArgStr = O.hasArgStr();
}
- void getExtraOptionNames(std::vector<const char*> &OptionNames) {
+ void getExtraOptionNames(SmallVectorImpl<const char*> &OptionNames) {
// If there has been no argstr specified, that means that we need to add an
// argument for every possible option. This ensures that our options are
// vectored to us.
@@ -458,9 +456,8 @@ public:
}
// parse - Return true on error.
- bool parse(Option &O, const char *ArgName, const std::string &Arg,
- DataType &V) {
- std::string ArgVal;
+ bool parse(Option &O, StringRef ArgName, StringRef Arg, DataType &V) {
+ StringRef ArgVal;
if (hasArgStr)
ArgVal = Arg;
else
@@ -468,7 +465,7 @@ public:
for (unsigned i = 0, e = static_cast<unsigned>(Values.size());
i != e; ++i)
- if (ArgVal == Values[i].first) {
+ if (Values[i].first == ArgVal) {
V = Values[i].second.first;
return false;
}
@@ -505,7 +502,7 @@ struct basic_parser_impl { // non-template implementation of basic_parser<t>
return ValueRequired;
}
- void getExtraOptionNames(std::vector<const char*> &) {}
+ void getExtraOptionNames(SmallVectorImpl<const char*> &) {}
void initialize(Option &) {}
@@ -541,7 +538,7 @@ class parser<bool> : public basic_parser<bool> {
public:
// parse - Return true on error.
- bool parse(Option &O, const char *ArgName, const std::string &Arg, bool &Val);
+ bool parse(Option &O, StringRef ArgName, StringRef Arg, bool &Val);
template <class Opt>
void initialize(Opt &O) {
@@ -568,8 +565,7 @@ template<>
class parser<boolOrDefault> : public basic_parser<boolOrDefault> {
public:
// parse - Return true on error.
- bool parse(Option &O, const char *ArgName, const std::string &Arg,
- boolOrDefault &Val);
+ bool parse(Option &O, StringRef ArgName, StringRef Arg, boolOrDefault &Val);
enum ValueExpected getValueExpectedFlagDefault() const {
return ValueOptional;
@@ -591,7 +587,7 @@ template<>
class parser<int> : public basic_parser<int> {
public:
// parse - Return true on error.
- bool parse(Option &O, const char *ArgName, const std::string &Arg, int &Val);
+ bool parse(Option &O, StringRef ArgName, StringRef Arg, int &Val);
// getValueName - Overload in subclass to provide a better default value.
virtual const char *getValueName() const { return "int"; }
@@ -610,7 +606,7 @@ template<>
class parser<unsigned> : public basic_parser<unsigned> {
public:
// parse - Return true on error.
- bool parse(Option &O, const char *AN, const std::string &Arg, unsigned &Val);
+ bool parse(Option &O, StringRef ArgName, StringRef Arg, unsigned &Val);
// getValueName - Overload in subclass to provide a better default value.
virtual const char *getValueName() const { return "uint"; }
@@ -628,7 +624,7 @@ template<>
class parser<double> : public basic_parser<double> {
public:
// parse - Return true on error.
- bool parse(Option &O, const char *AN, const std::string &Arg, double &Val);
+ bool parse(Option &O, StringRef ArgName, StringRef Arg, double &Val);
// getValueName - Overload in subclass to provide a better default value.
virtual const char *getValueName() const { return "number"; }
@@ -646,7 +642,7 @@ template<>
class parser<float> : public basic_parser<float> {
public:
// parse - Return true on error.
- bool parse(Option &O, const char *AN, const std::string &Arg, float &Val);
+ bool parse(Option &O, StringRef ArgName, StringRef Arg, float &Val);
// getValueName - Overload in subclass to provide a better default value.
virtual const char *getValueName() const { return "number"; }
@@ -664,9 +660,8 @@ template<>
class parser<std::string> : public basic_parser<std::string> {
public:
// parse - Return true on error.
- bool parse(Option &, const char *, const std::string &Arg,
- std::string &Value) {
- Value = Arg;
+ bool parse(Option &, StringRef ArgName, StringRef Arg, std::string &Value) {
+ Value = Arg.str();
return false;
}
@@ -686,8 +681,7 @@ template<>
class parser<char> : public basic_parser<char> {
public:
// parse - Return true on error.
- bool parse(Option &, const char *, const std::string &Arg,
- char &Value) {
+ bool parse(Option &, StringRef ArgName, StringRef Arg, char &Value) {
Value = Arg[0];
return false;
}
@@ -833,8 +827,8 @@ class opt : public Option,
is_class<DataType>::value> {
ParserClass Parser;
- virtual bool handleOccurrence(unsigned pos, const char *ArgName,
- const std::string &Arg) {
+ virtual bool handleOccurrence(unsigned pos, StringRef ArgName,
+ StringRef Arg) {
typename ParserClass::parser_data_type Val =
typename ParserClass::parser_data_type();
if (Parser.parse(*this, ArgName, Arg, Val))
@@ -847,7 +841,7 @@ class opt : public Option,
virtual enum ValueExpected getValueExpectedFlagDefault() const {
return Parser.getValueExpectedFlagDefault();
}
- virtual void getExtraOptionNames(std::vector<const char*> &OptionNames) {
+ virtual void getExtraOptionNames(SmallVectorImpl<const char*> &OptionNames) {
return Parser.getExtraOptionNames(OptionNames);
}
@@ -1002,12 +996,11 @@ class list : public Option, public list_storage<DataType, Storage> {
virtual enum ValueExpected getValueExpectedFlagDefault() const {
return Parser.getValueExpectedFlagDefault();
}
- virtual void getExtraOptionNames(std::vector<const char*> &OptionNames) {
+ virtual void getExtraOptionNames(SmallVectorImpl<const char*> &OptionNames) {
return Parser.getExtraOptionNames(OptionNames);
}
- virtual bool handleOccurrence(unsigned pos, const char *ArgName,
- const std::string &Arg) {
+ virtual bool handleOccurrence(unsigned pos, StringRef ArgName, StringRef Arg){
typename ParserClass::parser_data_type Val =
typename ParserClass::parser_data_type();
if (Parser.parse(*this, ArgName, Arg, Val))
@@ -1202,12 +1195,11 @@ class bits : public Option, public bits_storage<DataType, Storage> {
virtual enum ValueExpected getValueExpectedFlagDefault() const {
return Parser.getValueExpectedFlagDefault();
}
- virtual void getExtraOptionNames(std::vector<const char*> &OptionNames) {
+ virtual void getExtraOptionNames(SmallVectorImpl<const char*> &OptionNames) {
return Parser.getExtraOptionNames(OptionNames);
}
- virtual bool handleOccurrence(unsigned pos, const char *ArgName,
- const std::string &Arg) {
+ virtual bool handleOccurrence(unsigned pos, StringRef ArgName, StringRef Arg){
typename ParserClass::parser_data_type Val =
typename ParserClass::parser_data_type();
if (Parser.parse(*this, ArgName, Arg, Val))
@@ -1307,8 +1299,8 @@ public:
class alias : public Option {
Option *AliasFor;
- virtual bool handleOccurrence(unsigned pos, const char * /*ArgName*/,
- const std::string &Arg) {
+ virtual bool handleOccurrence(unsigned pos, StringRef /*ArgName*/,
+ StringRef Arg) {
return AliasFor->handleOccurrence(pos, AliasFor->ArgStr, Arg);
}
// Handle printing stuff...
diff --git a/libclamav/c++/llvm/include/llvm/Support/Compiler.h b/libclamav/c++/llvm/include/llvm/Support/Compiler.h
index 8533246..342a97d 100644
--- a/libclamav/c++/llvm/include/llvm/Support/Compiler.h
+++ b/libclamav/c++/llvm/include/llvm/Support/Compiler.h
@@ -23,7 +23,7 @@
#define VISIBILITY_HIDDEN
#endif
-#if (__GNUC__ >= 4)
+#if (__GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1))
#define ATTRIBUTE_USED __attribute__((__used__))
#else
#define ATTRIBUTE_USED
diff --git a/libclamav/c++/llvm/include/llvm/Support/ConstantFolder.h b/libclamav/c++/llvm/include/llvm/Support/ConstantFolder.h
index 3c9278a..99cb920 100644
--- a/libclamav/c++/llvm/include/llvm/Support/ConstantFolder.h
+++ b/libclamav/c++/llvm/include/llvm/Support/ConstantFolder.h
@@ -44,6 +44,9 @@ public:
Constant *CreateSub(Constant *LHS, Constant *RHS) const {
return ConstantExpr::getSub(LHS, RHS);
}
+ Constant *CreateNSWSub(Constant *LHS, Constant *RHS) const {
+ return ConstantExpr::getNSWSub(LHS, RHS);
+ }
Constant *CreateFSub(Constant *LHS, Constant *RHS) const {
return ConstantExpr::getFSub(LHS, RHS);
}
diff --git a/libclamav/c++/llvm/include/llvm/Support/DataTypes.h.cmake b/libclamav/c++/llvm/include/llvm/Support/DataTypes.h.cmake
index a6d7478..ad210ed 100644
--- a/libclamav/c++/llvm/include/llvm/Support/DataTypes.h.cmake
+++ b/libclamav/c++/llvm/include/llvm/Support/DataTypes.h.cmake
@@ -27,11 +27,8 @@
#cmakedefine HAVE_SYS_TYPES_H ${HAVE_SYS_TYPES_H}
#cmakedefine HAVE_INTTYPES_H ${HAVE_INTTYPES_H}
#cmakedefine HAVE_STDINT_H ${HAVE_STDINT_H}
-#undef HAVE_UINT64_T
-#undef HAVE_U_INT64_T
-
-/* FIXME: UGLY HACK (Added by Kevin) */
-#define HAVE_UINT64_T 1
+#cmakedefine HAVE_UINT64_T ${HAVE_UINT64_T}
+#cmakedefine HAVE_U_INT64_T ${HAVE_U_INT64_T}
#ifdef __cplusplus
#include <cmath>
diff --git a/libclamav/c++/llvm/include/llvm/Support/DebugLoc.h b/libclamav/c++/llvm/include/llvm/Support/DebugLoc.h
index 0bfad7c..30590c7 100644
--- a/libclamav/c++/llvm/include/llvm/Support/DebugLoc.h
+++ b/libclamav/c++/llvm/include/llvm/Support/DebugLoc.h
@@ -25,17 +25,19 @@ namespace llvm {
///
struct DebugLocTuple {
MDNode *CompileUnit;
+ MDNode *InlinedLoc;
unsigned Line, Col;
DebugLocTuple()
- : CompileUnit(0), Line(~0U), Col(~0U) {};
+ : CompileUnit(0), InlinedLoc(0), Line(~0U), Col(~0U) {};
- DebugLocTuple(MDNode *n, unsigned l, unsigned c)
- : CompileUnit(n), Line(l), Col(c) {};
+ DebugLocTuple(MDNode *n, MDNode *i, unsigned l, unsigned c)
+ : CompileUnit(n), InlinedLoc(i), Line(l), Col(c) {};
bool operator==(const DebugLocTuple &DLT) const {
return CompileUnit == DLT.CompileUnit &&
- Line == DLT.Line && Col == DLT.Col;
+ InlinedLoc == DLT.InlinedLoc &&
+ Line == DLT.Line && Col == DLT.Col;
}
bool operator!=(const DebugLocTuple &DLT) const {
return !(*this == DLT);
@@ -63,21 +65,23 @@ namespace llvm {
bool operator!=(const DebugLoc &DL) const { return !(*this == DL); }
};
- // Partially specialize DenseMapInfo for DebugLocTyple.
+ // Specialize DenseMapInfo for DebugLocTuple.
template<> struct DenseMapInfo<DebugLocTuple> {
static inline DebugLocTuple getEmptyKey() {
- return DebugLocTuple(0, ~0U, ~0U);
+ return DebugLocTuple(0, 0, ~0U, ~0U);
}
static inline DebugLocTuple getTombstoneKey() {
- return DebugLocTuple((MDNode*)~1U, ~1U, ~1U);
+ return DebugLocTuple((MDNode*)~1U, (MDNode*)~1U, ~1U, ~1U);
}
static unsigned getHashValue(const DebugLocTuple &Val) {
return DenseMapInfo<MDNode*>::getHashValue(Val.CompileUnit) ^
+ DenseMapInfo<MDNode*>::getHashValue(Val.InlinedLoc) ^
DenseMapInfo<unsigned>::getHashValue(Val.Line) ^
DenseMapInfo<unsigned>::getHashValue(Val.Col);
}
static bool isEqual(const DebugLocTuple &LHS, const DebugLocTuple &RHS) {
return LHS.CompileUnit == RHS.CompileUnit &&
+ LHS.InlinedLoc == RHS.InlinedLoc &&
LHS.Line == RHS.Line &&
LHS.Col == RHS.Col;
}
diff --git a/libclamav/c++/llvm/include/llvm/Support/FormattedStream.h b/libclamav/c++/llvm/include/llvm/Support/FormattedStream.h
index 768b8ed..24a3546 100644
--- a/libclamav/c++/llvm/include/llvm/Support/FormattedStream.h
+++ b/libclamav/c++/llvm/include/llvm/Support/FormattedStream.h
@@ -26,12 +26,12 @@ namespace llvm
public:
/// DELETE_STREAM - Tell the destructor to delete the held stream.
///
- const static bool DELETE_STREAM = true;
+ static const bool DELETE_STREAM = true;
/// PRESERVE_STREAM - Tell the destructor to not delete the held
/// stream.
///
- const static bool PRESERVE_STREAM = false;
+ static const bool PRESERVE_STREAM = false;
private:
/// TheStream - The real stream we output to. We set it to be
diff --git a/libclamav/c++/llvm/include/llvm/Support/GraphWriter.h b/libclamav/c++/llvm/include/llvm/Support/GraphWriter.h
index d5f2e74..bd3fcea 100644
--- a/libclamav/c++/llvm/include/llvm/Support/GraphWriter.h
+++ b/libclamav/c++/llvm/include/llvm/Support/GraphWriter.h
@@ -45,7 +45,7 @@ namespace GraphProgram {
CIRCO
};
}
-
+
void DisplayGraph(const sys::Path& Filename, bool wait=true, GraphProgram::Name program = GraphProgram::DOT);
template<typename GraphType>
@@ -223,9 +223,9 @@ public:
O << " -> Node" << DestNodeID;
if (DestNodePort >= 0) {
if (DOTTraits::hasEdgeDestLabels())
- O << ":d" << DestNodePort;
+ O << ":d" << DestNodePort;
else
- O << ":s" << DestNodePort;
+ O << ":s" << DestNodePort;
}
if (!Attrs.empty())
diff --git a/libclamav/c++/llvm/include/llvm/Support/IRBuilder.h b/libclamav/c++/llvm/include/llvm/Support/IRBuilder.h
index 4080f90..1f65978 100644
--- a/libclamav/c++/llvm/include/llvm/Support/IRBuilder.h
+++ b/libclamav/c++/llvm/include/llvm/Support/IRBuilder.h
@@ -20,6 +20,7 @@
#include "llvm/GlobalAlias.h"
#include "llvm/GlobalVariable.h"
#include "llvm/Function.h"
+#include "llvm/Metadata.h"
#include "llvm/LLVMContext.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/ConstantFolder.h"
@@ -60,35 +61,40 @@ template<bool preserveNames = true, typename T = ConstantFolder,
class IRBuilder : public Inserter {
BasicBlock *BB;
BasicBlock::iterator InsertPt;
+ unsigned MDKind;
+ MDNode *CurDbgLocation;
LLVMContext &Context;
T Folder;
public:
IRBuilder(LLVMContext &C, const T &F, const Inserter &I = Inserter())
- : Inserter(I), Context(C), Folder(F) {
+ : Inserter(I), MDKind(0), CurDbgLocation(0), Context(C), Folder(F) {
ClearInsertionPoint();
}
- explicit IRBuilder(LLVMContext &C) : Context(C), Folder(C) {
+ explicit IRBuilder(LLVMContext &C)
+ : MDKind(0), CurDbgLocation(0), Context(C), Folder(C) {
ClearInsertionPoint();
}
explicit IRBuilder(BasicBlock *TheBB, const T &F)
- : Context(TheBB->getContext()), Folder(F) {
+ : MDKind(0), CurDbgLocation(0), Context(TheBB->getContext()), Folder(F) {
SetInsertPoint(TheBB);
}
explicit IRBuilder(BasicBlock *TheBB)
- : Context(TheBB->getContext()), Folder(Context) {
+ : MDKind(0), CurDbgLocation(0), Context(TheBB->getContext()),
+ Folder(Context) {
SetInsertPoint(TheBB);
}
IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP, const T& F)
- : Context(TheBB->getContext()), Folder(F) {
+ : MDKind(0), CurDbgLocation(0), Context(TheBB->getContext()), Folder(F) {
SetInsertPoint(TheBB, IP);
}
IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP)
- : Context(TheBB->getContext()), Folder(Context) {
+ : MDKind(0), CurDbgLocation(0), Context(TheBB->getContext()),
+ Folder(Context) {
SetInsertPoint(TheBB, IP);
}
@@ -127,10 +133,30 @@ public:
InsertPt = IP;
}
+ /// SetCurrentDebugLocation - Set location information used by debugging
+ /// information.
+ void SetCurrentDebugLocation(MDNode *L) {
+ if (MDKind == 0)
+ MDKind = Context.getMetadata().getMDKind("dbg");
+ if (MDKind == 0)
+ MDKind = Context.getMetadata().RegisterMDKind("dbg");
+ CurDbgLocation = L;
+ }
+
+ MDNode *getCurrentDebugLocation() const { return CurDbgLocation; }
+
+ /// SetDebugLocation - Set location information for the given instruction.
+ void SetDebugLocation(Instruction *I) {
+ if (CurDbgLocation)
+ Context.getMetadata().addMD(MDKind, CurDbgLocation, I);
+ }
+
/// Insert - Insert and return the specified instruction.
template<typename InstTy>
InstTy *Insert(InstTy *I, const Twine &Name = "") const {
this->InsertHelper(I, Name, BB, InsertPt);
+ if (CurDbgLocation)
+ Context.getMetadata().addMD(MDKind, CurDbgLocation, I);
return I;
}
@@ -272,6 +298,12 @@ public:
return Folder.CreateSub(LC, RC);
return Insert(BinaryOperator::CreateSub(LHS, RHS), Name);
}
+ Value *CreateNSWSub(Value *LHS, Value *RHS, const Twine &Name = "") {
+ if (Constant *LC = dyn_cast<Constant>(LHS))
+ if (Constant *RC = dyn_cast<Constant>(RHS))
+ return Folder.CreateNSWSub(LC, RC);
+ return Insert(BinaryOperator::CreateNSWSub(LHS, RHS), Name);
+ }
Value *CreateFSub(Value *LHS, Value *RHS, const Twine &Name = "") {
if (Constant *LC = dyn_cast<Constant>(LHS))
if (Constant *RC = dyn_cast<Constant>(RHS))
diff --git a/libclamav/c++/llvm/include/llvm/Support/IRReader.h b/libclamav/c++/llvm/include/llvm/Support/IRReader.h
new file mode 100644
index 0000000..e7780b0
--- /dev/null
+++ b/libclamav/c++/llvm/include/llvm/Support/IRReader.h
@@ -0,0 +1,115 @@
+//===---- llvm/Support/IRReader.h - Reader for LLVM IR files ----*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines functions for reading LLVM IR. They support both
+// Bitcode and Assembly, automatically detecting the input format.
+//
+// These functions must be defined in a header file in order to avoid
+// library dependencies, since they reference both Bitcode and Assembly
+// functions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SUPPORT_IRREADER_H
+#define LLVM_SUPPORT_IRREADER_H
+
+#include "llvm/Assembly/Parser.h"
+#include "llvm/Bitcode/ReaderWriter.h"
+#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/SourceMgr.h"
+#include "llvm/ModuleProvider.h"
+
+namespace llvm {
+
+ /// If the given MemoryBuffer holds a bitcode image, return a ModuleProvider
+ /// for it which does lazy deserialization of function bodies. Otherwise,
+ /// attempt to parse it as LLVM Assembly and return a fully populated
+ /// ModuleProvider. This function *always* takes ownership of the given
+ /// MemoryBuffer.
+ inline ModuleProvider *getIRModuleProvider(MemoryBuffer *Buffer,
+ SMDiagnostic &Err,
+ LLVMContext &Context) {
+ if (isBitcode((const unsigned char *)Buffer->getBufferStart(),
+ (const unsigned char *)Buffer->getBufferEnd())) {
+ std::string ErrMsg;
+ ModuleProvider *MP = getBitcodeModuleProvider(Buffer, Context, &ErrMsg);
+ if (MP == 0) {
+ Err = SMDiagnostic(Buffer->getBufferIdentifier(), -1, -1, ErrMsg, "");
+ // ParseBitcodeFile does not take ownership of the Buffer in the
+ // case of an error.
+ delete Buffer;
+ }
+ return MP;
+ }
+
+ Module *M = ParseAssembly(Buffer, 0, Err, Context);
+ if (M == 0)
+ return 0;
+ return new ExistingModuleProvider(M);
+ }
+
+ /// If the given file holds a bitcode image, return a ModuleProvider
+ /// for it which does lazy deserialization of function bodies. Otherwise,
+ /// attempt to parse it as LLVM Assembly and return a fully populated
+ /// ModuleProvider.
+ inline ModuleProvider *getIRFileModuleProvider(const std::string &Filename,
+ SMDiagnostic &Err,
+ LLVMContext &Context) {
+ std::string ErrMsg;
+ MemoryBuffer *F = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), &ErrMsg);
+ if (F == 0) {
+ Err = SMDiagnostic(Filename, -1, -1,
+ "Could not open input file '" + Filename + "'", "");
+ return 0;
+ }
+
+ return getIRModuleProvider(F, Err, Context);
+ }
+
+ /// If the given MemoryBuffer holds a bitcode image, return a Module
+ /// for it. Otherwise, attempt to parse it as LLVM Assembly and return
+ /// a Module for it. This function *always* takes ownership of the given
+ /// MemoryBuffer.
+ inline Module *ParseIR(MemoryBuffer *Buffer,
+ SMDiagnostic &Err,
+ LLVMContext &Context) {
+ if (isBitcode((const unsigned char *)Buffer->getBufferStart(),
+ (const unsigned char *)Buffer->getBufferEnd())) {
+ std::string ErrMsg;
+ Module *M = ParseBitcodeFile(Buffer, Context, &ErrMsg);
+ // ParseBitcodeFile does not take ownership of the Buffer.
+ delete Buffer;
+ if (M == 0)
+ Err = SMDiagnostic(Buffer->getBufferIdentifier(), -1, -1, ErrMsg, "");
+ return M;
+ }
+
+ return ParseAssembly(Buffer, 0, Err, Context);
+ }
+
+ /// If the given file holds a bitcode image, return a Module for it.
+ /// Otherwise, attempt to parse it as LLVM Assembly and return a Module
+ /// for it.
+ inline Module *ParseIRFile(const std::string &Filename,
+ SMDiagnostic &Err,
+ LLVMContext &Context) {
+ std::string ErrMsg;
+ MemoryBuffer *F = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), &ErrMsg);
+ if (F == 0) {
+ Err = SMDiagnostic(Filename, -1, -1,
+ "Could not open input file '" + Filename + "'", "");
+ return 0;
+ }
+
+ return ParseIR(F, Err, Context);
+ }
+
+}
+
+#endif
diff --git a/libclamav/c++/llvm/include/llvm/Support/Mangler.h b/libclamav/c++/llvm/include/llvm/Support/Mangler.h
index d9234ac..03c5648 100644
--- a/libclamav/c++/llvm/include/llvm/Support/Mangler.h
+++ b/libclamav/c++/llvm/include/llvm/Support/Mangler.h
@@ -23,6 +23,7 @@ class Type;
class Module;
class Value;
class GlobalValue;
+template <typename T> class SmallVectorImpl;
class Mangler {
public:
@@ -50,6 +51,10 @@ private:
/// the space character. By default, this is false.
bool UseQuotes;
+ /// SymbolsCanStartWithDigit - If this is set, the target allows symbols to
+ /// start with digits (e.g., "0x0021"). By default, this is false.
+ bool SymbolsCanStartWithDigit;
+
/// AnonGlobalIDs - We need to give global values the same name every time
/// they are mangled. This keeps track of the number we give to anonymous
/// ones.
@@ -74,9 +79,13 @@ public:
/// strings for assembler labels.
void setUseQuotes(bool Val) { UseQuotes = Val; }
+ /// setSymbolsCanStartWithDigit - If SymbolsCanStartWithDigit is set to true,
+ /// this target allows symbols to start with digits.
+ void setSymbolsCanStartWithDigit(bool Val) { SymbolsCanStartWithDigit = Val; }
+
/// Acceptable Characters - This allows the target to specify which characters
/// are acceptable to the assembler without being mangled. By default we
- /// allow letters, numbers, '_', '$', and '.', which is what GAS accepts.
+ /// allow letters, numbers, '_', '$', '.', which is what GAS accepts, and '@'.
void markCharAcceptable(unsigned char X) {
AcceptableChars[X/32] |= 1 << (X&31);
}
@@ -104,6 +113,12 @@ public:
///
std::string makeNameProper(const std::string &x,
ManglerPrefixTy PrefixTy = Mangler::Default);
+
+ /// getNameWithPrefix - Fill OutName with the name of the appropriate prefix
+ /// and the specified global variable's name. If the global variable doesn't
+ /// have a name, this fills in a unique name for the global.
+ void getNameWithPrefix(SmallVectorImpl<char> &OutName, const GlobalValue *GV,
+ bool isImplicitlyPrivate);
};
} // End llvm namespace
diff --git a/libclamav/c++/llvm/include/llvm/Support/MemoryObject.h b/libclamav/c++/llvm/include/llvm/Support/MemoryObject.h
index fd0e966..dec0f13 100644
--- a/libclamav/c++/llvm/include/llvm/Support/MemoryObject.h
+++ b/libclamav/c++/llvm/include/llvm/Support/MemoryObject.h
@@ -17,23 +17,24 @@ namespace llvm {
/// MemoryObject - Abstract base class for contiguous addressable memory.
/// Necessary for cases in which the memory is in another process, in a
/// file, or on a remote machine.
+/// All size and offset parameters are uint64_ts, to allow 32-bit processes
+/// access to 64-bit address spaces.
class MemoryObject {
public:
/// Destructor - Override as necessary.
- virtual ~MemoryObject() {
- }
+ virtual ~MemoryObject();
/// getBase - Returns the lowest valid address in the region.
///
/// @result - The lowest valid address.
- virtual uintptr_t getBase() const = 0;
+ virtual uint64_t getBase() const = 0;
/// getExtent - Returns the size of the region in bytes. (The region is
/// contiguous, so the highest valid address of the region
/// is getBase() + getExtent() - 1).
///
/// @result - The size of the region.
- virtual uintptr_t getExtent() const = 0;
+ virtual uint64_t getExtent() const = 0;
/// readByte - Tries to read a single byte from the region.
///
@@ -41,9 +42,9 @@ public:
/// @param ptr - A pointer to a byte to be filled in. Must be non-NULL.
/// @result - 0 if successful; -1 if not. Failure may be due to a
/// bounds violation or an implementation-specific error.
- virtual int readByte(uintptr_t address, uint8_t* ptr) const = 0;
+ virtual int readByte(uint64_t address, uint8_t* ptr) const = 0;
- /// readByte - Tries to read a contiguous range of bytes from the
+ /// readBytes - Tries to read a contiguous range of bytes from the
/// region, up to the end of the region.
/// You should override this function if there is a quicker
/// way than going back and forth with individual bytes.
@@ -53,25 +54,14 @@ public:
/// @param size - The maximum number of bytes to copy.
/// @param buf - A pointer to a buffer to be filled in. Must be non-NULL
/// and large enough to hold size bytes.
- /// @result - The number of bytes copied if successful; (uintptr_t)-1
- /// if not.
- /// Failure may be due to a bounds violation or an
- /// implementation-specific error.
- virtual uintptr_t readBytes(uintptr_t address,
- uintptr_t size,
- uint8_t* buf) const {
- uintptr_t current = address;
- uintptr_t limit = getBase() + getExtent();
-
- while(current - address < size && current < limit) {
- if(readByte(current, &buf[(current - address)]))
- return (uintptr_t)-1;
-
- current++;
- }
-
- return current - address;
- }
+ /// @param copied - A pointer to a nunber that is filled in with the number
+ /// of bytes actually read. May be NULL.
+ /// @result - 0 if successful; -1 if not. Failure may be due to a
+ /// bounds violation or an implementation-specific error.
+ virtual int readBytes(uint64_t address,
+ uint64_t size,
+ uint8_t* buf,
+ uint64_t* copied) const;
};
}
diff --git a/libclamav/c++/llvm/include/llvm/Support/NoFolder.h b/libclamav/c++/llvm/include/llvm/Support/NoFolder.h
index 4540f02..1f671c1 100644
--- a/libclamav/c++/llvm/include/llvm/Support/NoFolder.h
+++ b/libclamav/c++/llvm/include/llvm/Support/NoFolder.h
@@ -51,6 +51,9 @@ public:
Value *CreateSub(Constant *LHS, Constant *RHS) const {
return BinaryOperator::CreateSub(LHS, RHS);
}
+ Value *CreateNSWSub(Constant *LHS, Constant *RHS) const {
+ return BinaryOperator::CreateNSWSub(LHS, RHS);
+ }
Value *CreateFSub(Constant *LHS, Constant *RHS) const {
return BinaryOperator::CreateFSub(LHS, RHS);
}
diff --git a/libclamav/c++/llvm/include/llvm/Support/PatternMatch.h b/libclamav/c++/llvm/include/llvm/Support/PatternMatch.h
index f085b0f..eb393ac 100644
--- a/libclamav/c++/llvm/include/llvm/Support/PatternMatch.h
+++ b/libclamav/c++/llvm/include/llvm/Support/PatternMatch.h
@@ -58,7 +58,7 @@ struct constantint_ty {
if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
const APInt &CIV = CI->getValue();
if (Val >= 0)
- return CIV == Val;
+ return CIV == static_cast<uint64_t>(Val);
// If Val is negative, and CI is shorter than it, truncate to the right
// number of bits. If it is larger, then we have to sign extend. Just
// compare their negated values.
diff --git a/libclamav/c++/llvm/include/llvm/Support/PointerLikeTypeTraits.h b/libclamav/c++/llvm/include/llvm/Support/PointerLikeTypeTraits.h
index b0edd3b..d64993f 100644
--- a/libclamav/c++/llvm/include/llvm/Support/PointerLikeTypeTraits.h
+++ b/libclamav/c++/llvm/include/llvm/Support/PointerLikeTypeTraits.h
@@ -50,12 +50,16 @@ public:
// Provide PointerLikeTypeTraits for const pointers.
template<typename T>
class PointerLikeTypeTraits<const T*> {
+ typedef PointerLikeTypeTraits<T*> NonConst;
+
public:
- static inline const void *getAsVoidPointer(const T* P) { return P; }
+ static inline const void *getAsVoidPointer(const T* P) {
+ return NonConst::getAsVoidPointer(const_cast<T*>(P));
+ }
static inline const T *getFromVoidPointer(const void *P) {
- return static_cast<const T*>(P);
+ return NonConst::getFromVoidPointer(const_cast<void*>(P));
}
- enum { NumLowBitsAvailable = 2 };
+ enum { NumLowBitsAvailable = NonConst::NumLowBitsAvailable };
};
// Provide PointerLikeTypeTraits for uintptr_t.
diff --git a/libclamav/c++/llvm/include/llvm/Support/Recycler.h b/libclamav/c++/llvm/include/llvm/Support/Recycler.h
index 2fa0365..d8f8c78 100644
--- a/libclamav/c++/llvm/include/llvm/Support/Recycler.h
+++ b/libclamav/c++/llvm/include/llvm/Support/Recycler.h
@@ -34,7 +34,8 @@ struct RecyclerStruct {
};
template<>
-struct ilist_traits<RecyclerStruct> : ilist_default_traits<RecyclerStruct> {
+struct ilist_traits<RecyclerStruct> :
+ public ilist_default_traits<RecyclerStruct> {
static RecyclerStruct *getPrev(const RecyclerStruct *t) { return t->Prev; }
static RecyclerStruct *getNext(const RecyclerStruct *t) { return t->Next; }
static void setPrev(RecyclerStruct *t, RecyclerStruct *p) { t->Prev = p; }
diff --git a/libclamav/c++/llvm/include/llvm/Support/Regex.h b/libclamav/c++/llvm/include/llvm/Support/Regex.h
index 31fd3cc..c954c0d 100644
--- a/libclamav/c++/llvm/include/llvm/Support/Regex.h
+++ b/libclamav/c++/llvm/include/llvm/Support/Regex.h
@@ -11,54 +11,53 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringRef.h"
+#include <string>
struct llvm_regex;
+
namespace llvm {
+ class StringRef;
+ template<typename T> class SmallVectorImpl;
+
class Regex {
public:
enum {
- /// Compile with support for subgroup matches, this is just to make
- /// constructs like Regex("...", 0) more readable as Regex("...", Sub).
- Sub=0,
+ NoFlags=0,
/// Compile for matching that ignores upper/lower case distinctions.
IgnoreCase=1,
- /// Compile for matching that need only report success or failure,
- /// not what was matched.
- NoSub=2,
/// Compile for newline-sensitive matching. With this flag '[^' bracket
/// expressions and '.' never match newline. A ^ anchor matches the
/// null string after any newline in the string in addition to its normal
/// function, and the $ anchor matches the null string before any
/// newline in the string in addition to its normal function.
- Newline=4
+ Newline=2
};
/// Compiles the given POSIX Extended Regular Expression \arg Regex.
/// This implementation supports regexes and matching strings with embedded
/// NUL characters.
- Regex(const StringRef &Regex, unsigned Flags=NoSub);
+ Regex(const StringRef &Regex, unsigned Flags = NoFlags);
~Regex();
/// isValid - returns the error encountered during regex compilation, or
/// matching, if any.
bool isValid(std::string &Error);
+ /// getNumMatches - In a valid regex, return the number of parenthesized
+ /// matches it contains. The number filled in by match will include this
+ /// many entries plus one for the whole regex (as element 0).
+ unsigned getNumMatches() const;
+
/// matches - Match the regex against a given \arg String.
///
/// \param Matches - If given, on a succesful match this will be filled in
/// with references to the matched group expressions (inside \arg String),
/// the first group is always the entire pattern.
- /// By default the regex is compiled with NoSub, which disables support for
- /// Matches.
- /// For this feature to be enabled you must construct the regex using
- /// Regex("...", Regex::Sub) constructor.
-
+ ///
+ /// This returns true on a successful match.
bool match(const StringRef &String, SmallVectorImpl<StringRef> *Matches=0);
private:
struct llvm_regex *preg;
int error;
- bool sub;
};
}
diff --git a/libclamav/c++/llvm/include/llvm/Support/Registry.h b/libclamav/c++/llvm/include/llvm/Support/Registry.h
index 454679b..4db8882 100644
--- a/libclamav/c++/llvm/include/llvm/Support/Registry.h
+++ b/libclamav/c++/llvm/include/llvm/Support/Registry.h
@@ -77,9 +77,6 @@ namespace llvm {
static listener *ListenerHead, *ListenerTail;
public:
- class iterator;
-
-
/// Node in linked list of entries.
///
class node {
diff --git a/libclamav/c++/llvm/include/llvm/Support/StandardPasses.h b/libclamav/c++/llvm/include/llvm/Support/StandardPasses.h
index 3d25c6c..8c4f90b 100644
--- a/libclamav/c++/llvm/include/llvm/Support/StandardPasses.h
+++ b/libclamav/c++/llvm/include/llvm/Support/StandardPasses.h
@@ -80,6 +80,8 @@ namespace llvm {
}
}
+ /// createStandardModulePasses - Add the standard module passes. This is
+ /// expected to be run after the standard function passes.
static inline void createStandardModulePasses(PassManager *PM,
unsigned OptimizationLevel,
bool OptimizeSize,
@@ -91,70 +93,69 @@ namespace llvm {
if (OptimizationLevel == 0) {
if (InliningPass)
PM->add(InliningPass);
- } else {
- if (UnitAtATime)
- PM->add(createRaiseAllocationsPass()); // call %malloc -> malloc inst
- PM->add(createCFGSimplificationPass()); // Clean up disgusting code
- // Kill useless allocas
- PM->add(createPromoteMemoryToRegisterPass());
- if (UnitAtATime) {
- PM->add(createGlobalOptimizerPass()); // Optimize out global vars
- PM->add(createGlobalDCEPass()); // Remove unused fns and globs
- // IP Constant Propagation
- PM->add(createIPConstantPropagationPass());
- PM->add(createDeadArgEliminationPass()); // Dead argument elimination
- }
- PM->add(createInstructionCombiningPass()); // Clean up after IPCP & DAE
- PM->add(createCFGSimplificationPass()); // Clean up after IPCP & DAE
- if (UnitAtATime) {
- if (HaveExceptions)
- PM->add(createPruneEHPass()); // Remove dead EH info
- PM->add(createFunctionAttrsPass()); // Set readonly/readnone attrs
- }
- if (InliningPass)
- PM->add(InliningPass);
- if (OptimizationLevel > 2)
- PM->add(createArgumentPromotionPass()); // Scalarize uninlined fn args
- if (SimplifyLibCalls)
- PM->add(createSimplifyLibCallsPass()); // Library Call Optimizations
- PM->add(createInstructionCombiningPass()); // Cleanup for scalarrepl.
- PM->add(createJumpThreadingPass()); // Thread jumps.
- PM->add(createCFGSimplificationPass()); // Merge & remove BBs
- PM->add(createScalarReplAggregatesPass()); // Break up aggregate allocas
- PM->add(createInstructionCombiningPass()); // Combine silly seq's
- PM->add(createCondPropagationPass()); // Propagate conditionals
- PM->add(createTailCallEliminationPass()); // Eliminate tail calls
- PM->add(createCFGSimplificationPass()); // Merge & remove BBs
- PM->add(createReassociatePass()); // Reassociate expressions
- PM->add(createLoopRotatePass()); // Rotate Loop
- PM->add(createLICMPass()); // Hoist loop invariants
- PM->add(createLoopUnswitchPass(OptimizeSize));
- PM->add(createInstructionCombiningPass());
- PM->add(createIndVarSimplifyPass()); // Canonicalize indvars
- PM->add(createLoopDeletionPass()); // Delete dead loops
- if (UnrollLoops)
- PM->add(createLoopUnrollPass()); // Unroll small loops
- PM->add(createInstructionCombiningPass()); // Clean up after the unroller
- PM->add(createGVNPass()); // Remove redundancies
- PM->add(createMemCpyOptPass()); // Remove memcpy / form memset
- PM->add(createSCCPPass()); // Constant prop with SCCP
+ return;
+ }
- // Run instcombine after redundancy elimination to exploit opportunities
- // opened up by them.
- PM->add(createInstructionCombiningPass());
- PM->add(createCondPropagationPass()); // Propagate conditionals
- PM->add(createDeadStoreEliminationPass()); // Delete dead stores
- PM->add(createAggressiveDCEPass()); // Delete dead instructions
- PM->add(createCFGSimplificationPass()); // Merge & remove BBs
-
- if (UnitAtATime) {
- PM->add(createStripDeadPrototypesPass()); // Get rid of dead prototypes
- PM->add(createDeadTypeEliminationPass()); // Eliminate dead types
- }
-
- if (OptimizationLevel > 1 && UnitAtATime)
- PM->add(createConstantMergePass()); // Merge dup global constants
+ if (UnitAtATime)
+ PM->add(createRaiseAllocationsPass()); // call %malloc -> malloc inst
+ PM->add(createCFGSimplificationPass()); // Clean up disgusting code
+ if (UnitAtATime) {
+ PM->add(createGlobalOptimizerPass()); // Optimize out global vars
+ PM->add(createGlobalDCEPass()); // Remove unused fns and globs
+ // IP Constant Propagation
+ PM->add(createIPConstantPropagationPass());
+ PM->add(createDeadArgEliminationPass()); // Dead argument elimination
}
+ PM->add(createInstructionCombiningPass()); // Clean up after IPCP & DAE
+ PM->add(createCFGSimplificationPass()); // Clean up after IPCP & DAE
+ if (UnitAtATime) {
+ if (HaveExceptions)
+ PM->add(createPruneEHPass()); // Remove dead EH info
+ PM->add(createFunctionAttrsPass()); // Set readonly/readnone attrs
+ }
+ if (InliningPass)
+ PM->add(InliningPass);
+ if (OptimizationLevel > 2)
+ PM->add(createArgumentPromotionPass()); // Scalarize uninlined fn args
+ if (SimplifyLibCalls)
+ PM->add(createSimplifyLibCallsPass()); // Library Call Optimizations
+ PM->add(createInstructionCombiningPass()); // Cleanup for scalarrepl.
+ PM->add(createJumpThreadingPass()); // Thread jumps.
+ PM->add(createCFGSimplificationPass()); // Merge & remove BBs
+ PM->add(createScalarReplAggregatesPass()); // Break up aggregate allocas
+ PM->add(createInstructionCombiningPass()); // Combine silly seq's
+ PM->add(createCondPropagationPass()); // Propagate conditionals
+ PM->add(createTailCallEliminationPass()); // Eliminate tail calls
+ PM->add(createCFGSimplificationPass()); // Merge & remove BBs
+ PM->add(createReassociatePass()); // Reassociate expressions
+ PM->add(createLoopRotatePass()); // Rotate Loop
+ PM->add(createLICMPass()); // Hoist loop invariants
+ PM->add(createLoopUnswitchPass(OptimizeSize));
+ PM->add(createInstructionCombiningPass());
+ PM->add(createIndVarSimplifyPass()); // Canonicalize indvars
+ PM->add(createLoopDeletionPass()); // Delete dead loops
+ if (UnrollLoops)
+ PM->add(createLoopUnrollPass()); // Unroll small loops
+ PM->add(createInstructionCombiningPass()); // Clean up after the unroller
+ PM->add(createGVNPass()); // Remove redundancies
+ PM->add(createMemCpyOptPass()); // Remove memcpy / form memset
+ PM->add(createSCCPPass()); // Constant prop with SCCP
+
+ // Run instcombine after redundancy elimination to exploit opportunities
+ // opened up by them.
+ PM->add(createInstructionCombiningPass());
+ PM->add(createCondPropagationPass()); // Propagate conditionals
+ PM->add(createDeadStoreEliminationPass()); // Delete dead stores
+ PM->add(createAggressiveDCEPass()); // Delete dead instructions
+ PM->add(createCFGSimplificationPass()); // Merge & remove BBs
+
+ if (UnitAtATime) {
+ PM->add(createStripDeadPrototypesPass()); // Get rid of dead prototypes
+ PM->add(createDeadTypeEliminationPass()); // Eliminate dead types
+ }
+
+ if (OptimizationLevel > 1 && UnitAtATime)
+ PM->add(createConstantMergePass()); // Merge dup global constants
}
static inline void addOnePass(PassManager *PM, Pass *P, bool AndVerify) {
diff --git a/libclamav/c++/llvm/include/llvm/Support/TargetFolder.h b/libclamav/c++/llvm/include/llvm/Support/TargetFolder.h
index 77533c0..8e28632 100644
--- a/libclamav/c++/llvm/include/llvm/Support/TargetFolder.h
+++ b/libclamav/c++/llvm/include/llvm/Support/TargetFolder.h
@@ -60,6 +60,9 @@ public:
Constant *CreateSub(Constant *LHS, Constant *RHS) const {
return Fold(ConstantExpr::getSub(LHS, RHS));
}
+ Constant *CreateNSWSub(Constant *LHS, Constant *RHS) const {
+ return Fold(ConstantExpr::getNSWSub(LHS, RHS));
+ }
Constant *CreateFSub(Constant *LHS, Constant *RHS) const {
return Fold(ConstantExpr::getFSub(LHS, RHS));
}
diff --git a/libclamav/c++/llvm/include/llvm/Support/Timer.h b/libclamav/c++/llvm/include/llvm/Support/Timer.h
index 7240cb9..54f1da9 100644
--- a/libclamav/c++/llvm/include/llvm/Support/Timer.h
+++ b/libclamav/c++/llvm/include/llvm/Support/Timer.h
@@ -27,7 +27,7 @@ class TimerGroup;
class raw_ostream;
/// Timer - This class is used to track the amount of time spent between
-/// invocations of it's startTimer()/stopTimer() methods. Given appropriate OS
+/// invocations of its startTimer()/stopTimer() methods. Given appropriate OS
/// support it can also keep track of the RSS of the program at various points.
/// By default, the Timer will print the amount of time it has captured to
/// standard error when the laster timer is destroyed, otherwise it is printed
diff --git a/libclamav/c++/llvm/include/llvm/Support/TypeBuilder.h b/libclamav/c++/llvm/include/llvm/Support/TypeBuilder.h
index 64af647..fb22e3f 100644
--- a/libclamav/c++/llvm/include/llvm/Support/TypeBuilder.h
+++ b/libclamav/c++/llvm/include/llvm/Support/TypeBuilder.h
@@ -50,15 +50,14 @@ namespace llvm {
/// namespace llvm {
/// template<bool xcompile> class TypeBuilder<MyType, xcompile> {
/// public:
-/// static const StructType *get() {
-/// // Using the static result variable ensures that the type is
-/// // only looked up once.
-/// static const StructType *const result = StructType::get(
-/// TypeBuilder<types::i<32>, xcompile>::get(),
-/// TypeBuilder<types::i<32>*, xcompile>::get(),
-/// TypeBuilder<types::i<8>*[], xcompile>::get(),
+/// static const StructType *get(LLVMContext &Context) {
+/// // If you cache this result, be sure to cache it separately
+/// // for each LLVMContext.
+/// return StructType::get(
+/// TypeBuilder<types::i<32>, xcompile>::get(Context),
+/// TypeBuilder<types::i<32>*, xcompile>::get(Context),
+/// TypeBuilder<types::i<8>*[], xcompile>::get(Context),
/// NULL);
-/// return result;
/// }
///
/// // You may find this a convenient place to put some constants
@@ -72,9 +71,6 @@ namespace llvm {
/// }
/// } // namespace llvm
///
-/// Using the static result variable ensures that the type is only looked up
-/// once.
-///
/// TypeBuilder cannot handle recursive types or types you only know at runtime.
/// If you try to give it a recursive type, it will deadlock, infinitely
/// recurse, or throw a recursive_init exception.
@@ -106,9 +102,7 @@ template<typename T, bool cross> class TypeBuilder<const volatile T, cross>
template<typename T, bool cross> class TypeBuilder<T*, cross> {
public:
static const PointerType *get(LLVMContext &Context) {
- static const PointerType *const result =
- PointerType::getUnqual(TypeBuilder<T,cross>::get(Context));
- return result;
+ return PointerType::getUnqual(TypeBuilder<T,cross>::get(Context));
}
};
@@ -119,18 +113,14 @@ template<typename T, bool cross> class TypeBuilder<T&, cross> {};
template<typename T, size_t N, bool cross> class TypeBuilder<T[N], cross> {
public:
static const ArrayType *get(LLVMContext &Context) {
- static const ArrayType *const result =
- ArrayType::get(TypeBuilder<T, cross>::get(Context), N);
- return result;
+ return ArrayType::get(TypeBuilder<T, cross>::get(Context), N);
}
};
/// LLVM uses an array of length 0 to represent an unknown-length array.
template<typename T, bool cross> class TypeBuilder<T[], cross> {
public:
static const ArrayType *get(LLVMContext &Context) {
- static const ArrayType *const result =
- ArrayType::get(TypeBuilder<T, cross>::get(Context), 0);
- return result;
+ return ArrayType::get(TypeBuilder<T, cross>::get(Context), 0);
}
};
@@ -160,9 +150,7 @@ public:
template<> class TypeBuilder<T, false> { \
public: \
static const IntegerType *get(LLVMContext &Context) { \
- static const IntegerType *const result = \
- IntegerType::get(Context, sizeof(T) * CHAR_BIT); \
- return result; \
+ return IntegerType::get(Context, sizeof(T) * CHAR_BIT); \
} \
}; \
template<> class TypeBuilder<T, true> { \
@@ -191,8 +179,7 @@ template<uint32_t num_bits, bool cross>
class TypeBuilder<types::i<num_bits>, cross> {
public:
static const IntegerType *get(LLVMContext &C) {
- static const IntegerType *const result = IntegerType::get(C, num_bits);
- return result;
+ return IntegerType::get(C, num_bits);
}
};
@@ -248,24 +235,12 @@ template<> class TypeBuilder<void*, false>
template<typename R, bool cross> class TypeBuilder<R(), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
return FunctionType::get(TypeBuilder<R, cross>::get(Context), false);
}
};
template<typename R, typename A1, bool cross> class TypeBuilder<R(A1), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
std::vector<const Type*> params;
params.reserve(1);
params.push_back(TypeBuilder<A1, cross>::get(Context));
@@ -277,12 +252,6 @@ template<typename R, typename A1, typename A2, bool cross>
class TypeBuilder<R(A1, A2), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
std::vector<const Type*> params;
params.reserve(2);
params.push_back(TypeBuilder<A1, cross>::get(Context));
@@ -295,12 +264,6 @@ template<typename R, typename A1, typename A2, typename A3, bool cross>
class TypeBuilder<R(A1, A2, A3), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
std::vector<const Type*> params;
params.reserve(3);
params.push_back(TypeBuilder<A1, cross>::get(Context));
@@ -316,12 +279,6 @@ template<typename R, typename A1, typename A2, typename A3, typename A4,
class TypeBuilder<R(A1, A2, A3, A4), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
std::vector<const Type*> params;
params.reserve(4);
params.push_back(TypeBuilder<A1, cross>::get(Context));
@@ -338,12 +295,6 @@ template<typename R, typename A1, typename A2, typename A3, typename A4,
class TypeBuilder<R(A1, A2, A3, A4, A5), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
std::vector<const Type*> params;
params.reserve(5);
params.push_back(TypeBuilder<A1, cross>::get(Context));
@@ -359,12 +310,6 @@ private:
template<typename R, bool cross> class TypeBuilder<R(...), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
return FunctionType::get(TypeBuilder<R, cross>::get(Context), true);
}
};
@@ -372,12 +317,6 @@ template<typename R, typename A1, bool cross>
class TypeBuilder<R(A1, ...), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
std::vector<const Type*> params;
params.reserve(1);
params.push_back(TypeBuilder<A1, cross>::get(Context));
@@ -388,12 +327,6 @@ template<typename R, typename A1, typename A2, bool cross>
class TypeBuilder<R(A1, A2, ...), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
std::vector<const Type*> params;
params.reserve(2);
params.push_back(TypeBuilder<A1, cross>::get(Context));
@@ -406,12 +339,6 @@ template<typename R, typename A1, typename A2, typename A3, bool cross>
class TypeBuilder<R(A1, A2, A3, ...), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
std::vector<const Type*> params;
params.reserve(3);
params.push_back(TypeBuilder<A1, cross>::get(Context));
@@ -427,12 +354,6 @@ template<typename R, typename A1, typename A2, typename A3, typename A4,
class TypeBuilder<R(A1, A2, A3, A4, ...), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
std::vector<const Type*> params;
params.reserve(4);
params.push_back(TypeBuilder<A1, cross>::get(Context));
@@ -449,12 +370,6 @@ template<typename R, typename A1, typename A2, typename A3, typename A4,
class TypeBuilder<R(A1, A2, A3, A4, A5, ...), cross> {
public:
static const FunctionType *get(LLVMContext &Context) {
- static const FunctionType *const result = create(Context);
- return result;
- }
-
-private:
- static const FunctionType *create(LLVMContext &Context) {
std::vector<const Type*> params;
params.reserve(5);
params.push_back(TypeBuilder<A1, cross>::get(Context));
diff --git a/libclamav/c++/llvm/include/llvm/Support/ValueHandle.h b/libclamav/c++/llvm/include/llvm/Support/ValueHandle.h
index e0e06e1..d22b30a 100644
--- a/libclamav/c++/llvm/include/llvm/Support/ValueHandle.h
+++ b/libclamav/c++/llvm/include/llvm/Support/ValueHandle.h
@@ -45,11 +45,12 @@ protected:
/// fully general Callback version does have a vtable.
enum HandleBaseKind {
Assert,
- Weak,
- Callback
+ Callback,
+ Tracking,
+ Weak
};
private:
-
+
PointerIntPair<ValueHandleBase**, 2, HandleBaseKind> PrevPair;
ValueHandleBase *Next;
Value *VP;
@@ -68,9 +69,9 @@ public:
}
~ValueHandleBase() {
if (isValid(VP))
- RemoveFromUseList();
+ RemoveFromUseList();
}
-
+
Value *operator=(Value *RHS) {
if (VP == RHS) return RHS;
if (isValid(VP)) RemoveFromUseList();
@@ -86,38 +87,38 @@ public:
if (isValid(VP)) AddToExistingUseList(RHS.getPrevPtr());
return VP;
}
-
+
Value *operator->() const { return getValPtr(); }
Value &operator*() const { return *getValPtr(); }
protected:
Value *getValPtr() const { return VP; }
-private:
static bool isValid(Value *V) {
return V &&
V != DenseMapInfo<Value *>::getEmptyKey() &&
V != DenseMapInfo<Value *>::getTombstoneKey();
}
+private:
// Callbacks made from Value.
static void ValueIsDeleted(Value *V);
static void ValueIsRAUWd(Value *Old, Value *New);
-
+
// Internal implementation details.
ValueHandleBase **getPrevPtr() const { return PrevPair.getPointer(); }
HandleBaseKind getKind() const { return PrevPair.getInt(); }
void setPrevPtr(ValueHandleBase **Ptr) { PrevPair.setPointer(Ptr); }
-
+
/// AddToExistingUseList - Add this ValueHandle to the use list for VP,
/// where List is known to point into the existing use list.
void AddToExistingUseList(ValueHandleBase **List);
-
+
/// AddToUseList - Add this ValueHandle to the use list for VP.
void AddToUseList();
/// RemoveFromUseList - Remove this ValueHandle from its current use list.
void RemoveFromUseList();
};
-
+
/// WeakVH - This is a value handle that tries hard to point to a Value, even
/// across RAUW operations, but will null itself out if the value is destroyed.
/// this is useful for advisory sorts of information, but should not be used as
@@ -160,7 +161,7 @@ template<> struct simplify_type<WeakVH> : public simplify_type<const WeakVH> {};
/// AssertingVH's as it moves. This is required because in non-assert mode this
/// class turns into a trivial wrapper around a pointer.
template <typename ValueTy>
-class AssertingVH
+class AssertingVH
#ifndef NDEBUG
: public ValueHandleBase
#endif
@@ -202,7 +203,7 @@ public:
setValPtr(RHS);
return getValPtr();
}
- ValueTy *operator=(AssertingVH<ValueTy> &RHS) {
+ ValueTy *operator=(const AssertingVH<ValueTy> &RHS) {
setValPtr(RHS.getValPtr());
return getValPtr();
}
@@ -223,6 +224,88 @@ template<> struct simplify_type<const AssertingVH<Value> > {
template<> struct simplify_type<AssertingVH<Value> >
: public simplify_type<const AssertingVH<Value> > {};
+/// TrackingVH - This is a value handle that tracks a Value (or Value subclass),
+/// even across RAUW operations.
+///
+/// TrackingVH is designed for situations where a client needs to hold a handle
+/// to a Value (or subclass) across some operations which may move that value,
+/// but should never destroy it or replace it with some unacceptable type.
+///
+/// It is an error to do anything with a TrackingVH whose value has been
+/// destroyed, except to destruct it.
+///
+/// It is an error to attempt to replace a value with one of a type which is
+/// incompatible with any of its outstanding TrackingVHs.
+template<typename ValueTy>
+class TrackingVH : public ValueHandleBase {
+ void CheckValidity() const {
+ Value *VP = ValueHandleBase::getValPtr();
+
+ // Null is always ok.
+ if (!VP)
+ return;
+
+ // Check that this value is valid (i.e., it hasn't been deleted). We
+ // explicitly delay this check until access to avoid requiring clients to be
+ // unnecessarily careful w.r.t. destruction.
+ assert(ValueHandleBase::isValid(VP) && "Tracked Value was deleted!");
+
+ // Check that the value is a member of the correct subclass. We would like
+ // to check this property on assignment for better debugging, but we don't
+ // want to require a virtual interface on this VH. Instead we allow RAUW to
+ // replace this value with a value of an invalid type, and check it here.
+ assert(isa<ValueTy>(VP) &&
+ "Tracked Value was replaced by one with an invalid type!");
+ }
+
+ ValueTy *getValPtr() const {
+ CheckValidity();
+ return static_cast<ValueTy*>(ValueHandleBase::getValPtr());
+ }
+ void setValPtr(ValueTy *P) {
+ CheckValidity();
+ ValueHandleBase::operator=(GetAsValue(P));
+ }
+
+ // Convert a ValueTy*, which may be const, to the type the base
+ // class expects.
+ static Value *GetAsValue(Value *V) { return V; }
+ static Value *GetAsValue(const Value *V) { return const_cast<Value*>(V); }
+
+public:
+ TrackingVH() : ValueHandleBase(Tracking) {}
+ TrackingVH(ValueTy *P) : ValueHandleBase(Tracking, P) {}
+ TrackingVH(const TrackingVH &RHS) : ValueHandleBase(Tracking, RHS) {}
+
+ operator ValueTy*() const {
+ return getValPtr();
+ }
+
+ ValueTy *operator=(ValueTy *RHS) {
+ setValPtr(RHS);
+ return getValPtr();
+ }
+ ValueTy *operator=(const TrackingVH<ValueTy> &RHS) {
+ setValPtr(RHS.getValPtr());
+ return getValPtr();
+ }
+
+ ValueTy *operator->() const { return getValPtr(); }
+ ValueTy &operator*() const { return *getValPtr(); }
+};
+
+// Specialize simplify_type to allow TrackingVH to participate in
+// dyn_cast, isa, etc.
+template<typename From> struct simplify_type;
+template<> struct simplify_type<const TrackingVH<Value> > {
+ typedef Value* SimpleType;
+ static SimpleType getSimplifiedValue(const TrackingVH<Value> &AVH) {
+ return static_cast<Value *>(AVH);
+ }
+};
+template<> struct simplify_type<TrackingVH<Value> >
+ : public simplify_type<const TrackingVH<Value> > {};
+
/// CallbackVH - This is a value handle that allows subclasses to define
/// callbacks that run when the underlying Value has RAUW called on it or is
/// destroyed. This class can be used as the key of a map, as long as the user
diff --git a/libclamav/c++/llvm/include/llvm/Support/raw_ostream.h b/libclamav/c++/llvm/include/llvm/Support/raw_ostream.h
index a01d4cd..7827dd8 100644
--- a/libclamav/c++/llvm/include/llvm/Support/raw_ostream.h
+++ b/libclamav/c++/llvm/include/llvm/Support/raw_ostream.h
@@ -41,7 +41,7 @@ private:
/// 1. Unbuffered (BufferMode == Unbuffered)
/// 1. Uninitialized (BufferMode != Unbuffered && OutBufStart == 0).
/// 2. Buffered (BufferMode != Unbuffered && OutBufStart != 0 &&
- /// OutBufEnd - OutBufStart >= 64).
+ /// OutBufEnd - OutBufStart >= 1).
///
/// If buffered, then the raw_ostream owns the buffer if (BufferMode ==
/// InternalBuffer); otherwise the buffer has been set via SetBuffer and is
@@ -240,6 +240,11 @@ public:
/// outputting colored text, or before program exit.
virtual raw_ostream &resetColor() { return *this; }
+ /// This function determines if this stream is connected to a "tty" or
+ /// "console" window. That is, the output would be displayed to the user
+ /// rather than being put on a pipe or stored in a file.
+ virtual bool is_displayed() const { return false; }
+
//===--------------------------------------------------------------------===//
// Subclass Interface
//===--------------------------------------------------------------------===//
@@ -370,6 +375,8 @@ public:
virtual raw_ostream &changeColor(enum Colors colors, bool bold=false,
bool bg=false);
virtual raw_ostream &resetColor();
+
+ virtual bool is_displayed() const;
};
/// raw_stdout_ostream - This is a stream that always prints to stdout.
diff --git a/libclamav/c++/llvm/include/llvm/SymbolTableListTraits.h b/libclamav/c++/llvm/include/llvm/SymbolTableListTraits.h
index 337b76f..39953e1 100644
--- a/libclamav/c++/llvm/include/llvm/SymbolTableListTraits.h
+++ b/libclamav/c++/llvm/include/llvm/SymbolTableListTraits.h
@@ -28,7 +28,8 @@
#include "llvm/ADT/ilist.h"
namespace llvm {
-
+class ValueSymbolTable;
+
template<typename NodeTy> class ilist_iterator;
template<typename NodeTy, typename Traits> class iplist;
template<typename Ty> struct ilist_traits;
diff --git a/libclamav/c++/llvm/include/llvm/System/Mutex.h b/libclamav/c++/llvm/include/llvm/System/Mutex.h
index 9ef5942..71d1006 100644
--- a/libclamav/c++/llvm/include/llvm/System/Mutex.h
+++ b/libclamav/c++/llvm/include/llvm/System/Mutex.h
@@ -93,32 +93,36 @@ namespace llvm
MutexImpl(rec), acquired(0), recursive(rec) { }
bool acquire() {
- if (!mt_only || llvm_is_multithreaded())
+ if (!mt_only || llvm_is_multithreaded()) {
return MutexImpl::acquire();
-
- // Single-threaded debugging code. This would be racy in multithreaded
- // mode, but provides not sanity checks in single threaded mode.
- assert((recursive || acquired == 0) && "Lock already acquired!!");
- ++acquired;
- return true;
+ } else {
+ // Single-threaded debugging code. This would be racy in
+ // multithreaded mode, but provides not sanity checks in single
+ // threaded mode.
+ assert((recursive || acquired == 0) && "Lock already acquired!!");
+ ++acquired;
+ return true;
+ }
}
bool release() {
- if (!mt_only || llvm_is_multithreaded())
+ if (!mt_only || llvm_is_multithreaded()) {
return MutexImpl::release();
-
- // Single-threaded debugging code. This would be racy in multithreaded
- // mode, but provides not sanity checks in single threaded mode.
- assert(((recursive && acquired) || (acquired == 1)) &&
- "Lock not acquired before release!");
- --acquired;
- return true;
+ } else {
+ // Single-threaded debugging code. This would be racy in
+ // multithreaded mode, but provides not sanity checks in single
+ // threaded mode.
+ assert(((recursive && acquired) || (acquired == 1)) &&
+ "Lock not acquired before release!");
+ --acquired;
+ return true;
+ }
}
bool tryacquire() {
if (!mt_only || llvm_is_multithreaded())
return MutexImpl::tryacquire();
- return true;
+ else return true;
}
private:
diff --git a/libclamav/c++/llvm/include/llvm/System/Process.h b/libclamav/c++/llvm/include/llvm/System/Process.h
index 11dbf75..010499a 100644
--- a/libclamav/c++/llvm/include/llvm/System/Process.h
+++ b/libclamav/c++/llvm/include/llvm/System/Process.h
@@ -94,6 +94,11 @@ namespace sys {
/// the user rather than being put on a pipe or stored in a file.
static bool StandardErrIsDisplayed();
+ /// This function determines if the given file descriptor is connected to
+ /// a "tty" or "console" window. That is, the output would be displayed to
+ /// the user rather than being put on a pipe or stored in a file.
+ static bool FileDescriptorIsDisplayed(int fd);
+
/// This function determines the number of columns in the window
/// if standard output is connected to a "tty" or "console"
/// window. If standard output is not connected to a tty or
diff --git a/libclamav/c++/llvm/include/llvm/System/Program.h b/libclamav/c++/llvm/include/llvm/System/Program.h
index 7f96245..6799562 100644
--- a/libclamav/c++/llvm/include/llvm/System/Program.h
+++ b/libclamav/c++/llvm/include/llvm/System/Program.h
@@ -30,9 +30,7 @@ namespace sys {
/// @brief An abstraction for finding and executing programs.
class Program {
/// Opaque handle for target specific data.
- void *Data;
-
- unsigned Pid_;
+ void *Data_;
// Noncopyable.
Program(const Program& other);
@@ -43,10 +41,10 @@ namespace sys {
public:
Program();
- ~Program();
-
+ ~Program();
+
/// Return process ID of this program.
- unsigned GetPid() { return Pid_; }
+ unsigned GetPid() const;
/// This function executes the program using the \p arguments provided. The
/// invoked program will inherit the stdin, stdout, and stderr file
@@ -99,7 +97,17 @@ namespace sys {
///< it doesn't.
std::string* ErrMsg = 0 ///< If non-zero, provides a pointer to a string
///< instance in which error messages will be returned. If the string
- ///< is non-empty upon return an error occurred while invoking the
+ ///< is non-empty upon return an error occurred while waiting.
+ );
+
+ /// This function terminates the program.
+ /// @returns true if an error occured.
+ /// @see Execute
+ /// @brief Terminates the program.
+ bool Kill
+ ( std::string* ErrMsg = 0 ///< If non-zero, provides a pointer to a string
+ ///< instance in which error messages will be returned. If the string
+ ///< is non-empty upon return an error occurred while killing the
///< program.
);
diff --git a/libclamav/c++/llvm/include/llvm/Target/Target.td b/libclamav/c++/llvm/include/llvm/Target/Target.td
index 5a8707b..4d65b19 100644
--- a/libclamav/c++/llvm/include/llvm/Target/Target.td
+++ b/libclamav/c++/llvm/include/llvm/Target/Target.td
@@ -203,6 +203,8 @@ class Instruction {
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
+ bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
+ bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
// Side effect flags - When set, the flags have these meanings:
//
@@ -426,12 +428,12 @@ def GC_LABEL : Instruction {
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
}
-def DECLARE : Instruction {
+def KILL : Instruction {
let OutOperandList = (ops);
let InOperandList = (ops variable_ops);
let AsmString = "";
let Namespace = "TargetInstrInfo";
- let hasCtrlDep = 1;
+ let neverHasSideEffects = 1;
}
def EXTRACT_SUBREG : Instruction {
let OutOperandList = (ops unknown:$dst);
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetAsmParser.h b/libclamav/c++/llvm/include/llvm/Target/TargetAsmParser.h
index 8b8b210..ef1fc49 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetAsmParser.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetAsmParser.h
@@ -10,6 +10,8 @@
#ifndef LLVM_TARGET_TARGETPARSER_H
#define LLVM_TARGET_TARGETPARSER_H
+#include "llvm/MC/MCAsmLexer.h"
+
namespace llvm {
class MCAsmParser;
class MCInst;
@@ -44,6 +46,18 @@ public:
/// \param Inst [out] - On success, the parsed instruction.
/// \return True on failure.
virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst) = 0;
+
+ /// ParseDirective - Parse a target specific assembler directive
+ ///
+ /// The parser is positioned following the directive name. The target
+ /// specific directive parser should parse the entire directive doing or
+ /// recording any target specific work, or return true and do nothing if the
+ /// directive is not target specific. If the directive is specific for
+ /// the target, the entire line is parsed up to and including the
+ /// end-of-statement token and false is returned.
+ ///
+ /// \param ID - the identifier token of the directive.
+ virtual bool ParseDirective(AsmToken DirectiveID) = 0;
};
} // End llvm namespace
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetFrameInfo.h b/libclamav/c++/llvm/include/llvm/Target/TargetFrameInfo.h
index 3e26b9d..975d156 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetFrameInfo.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetFrameInfo.h
@@ -31,13 +31,22 @@ public:
StackGrowsUp, // Adding to the stack increases the stack address
StackGrowsDown // Adding to the stack decreases the stack address
};
+
+ // Maps a callee saved register to a stack slot with a fixed offset.
+ struct SpillSlot {
+ unsigned Reg;
+ int Offset; // Offset relative to stack pointer on function entry.
+ };
private:
StackDirection StackDir;
unsigned StackAlignment;
+ unsigned TransientStackAlignment;
int LocalAreaOffset;
public:
- TargetFrameInfo(StackDirection D, unsigned StackAl, int LAO)
- : StackDir(D), StackAlignment(StackAl), LocalAreaOffset(LAO) {}
+ TargetFrameInfo(StackDirection D, unsigned StackAl, int LAO,
+ unsigned TransAl = 1)
+ : StackDir(D), StackAlignment(StackAl), TransientStackAlignment(TransAl),
+ LocalAreaOffset(LAO) {}
virtual ~TargetFrameInfo();
@@ -48,12 +57,20 @@ public:
///
StackDirection getStackGrowthDirection() const { return StackDir; }
- /// getStackAlignment - This method returns the number of bytes that the stack
- /// pointer must be aligned to. Typically, this is the largest alignment for
- /// any data object in the target.
+ /// getStackAlignment - This method returns the number of bytes to which the
+ /// stack pointer must be aligned on entry to a function. Typically, this
+ /// is the largest alignment for any data object in the target.
///
unsigned getStackAlignment() const { return StackAlignment; }
+ /// getTransientStackAlignment - This method returns the number of bytes to
+ /// which the stack pointer must be aligned at all times, even between
+ /// calls.
+ ///
+ unsigned getTransientStackAlignment() const {
+ return TransientStackAlignment;
+ }
+
/// getOffsetOfLocalArea - This method returns the offset of the local area
/// from the stack pointer on entrance to a function.
///
@@ -65,10 +82,10 @@ public:
///
/// Each entry in this array contains a <register,offset> pair, indicating the
/// fixed offset from the incoming stack pointer that each register should be
- /// spilled at. If a register is not listed here, the code generator is
+ /// spilled at. If a register is not listed here, the code generator is
/// allowed to spill it anywhere it chooses.
///
- virtual const std::pair<unsigned, int> *
+ virtual const SpillSlot *
getCalleeSavedSpillSlots(unsigned &NumEntries) const {
NumEntries = 0;
return 0;
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetInstrDesc.h b/libclamav/c++/llvm/include/llvm/Target/TargetInstrDesc.h
index 431e6e8..d828a23 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetInstrDesc.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetInstrDesc.h
@@ -111,7 +111,9 @@ namespace TID {
ConvertibleTo3Addr,
UsesCustomDAGSchedInserter,
Rematerializable,
- CheapAsAMove
+ CheapAsAMove,
+ ExtraSrcRegAllocReq,
+ ExtraDefRegAllocReq
};
}
@@ -443,6 +445,26 @@ public:
bool isAsCheapAsAMove() const {
return Flags & (1 << TID::CheapAsAMove);
}
+
+ /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
+ /// have special register allocation requirements that are not captured by the
+ /// operand register classes. e.g. ARM::STRD's two source registers must be an
+ /// even / odd pair, ARM::STM registers have to be in ascending order.
+ /// Post-register allocation passes should not attempt to change allocations
+ /// for sources of instructions with this flag.
+ bool hasExtraSrcRegAllocReq() const {
+ return Flags & (1 << TID::ExtraSrcRegAllocReq);
+ }
+
+ /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
+ /// have special register allocation requirements that are not captured by the
+ /// operand register classes. e.g. ARM::LDRD's two def registers must be an
+ /// even / odd pair, ARM::LDM registers have to be in ascending order.
+ /// Post-register allocation passes should not attempt to change allocations
+ /// for definitions of instructions with this flag.
+ bool hasExtraDefRegAllocReq() const {
+ return Flags & (1 << TID::ExtraDefRegAllocReq);
+ }
};
} // end namespace llvm
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetInstrInfo.h b/libclamav/c++/llvm/include/llvm/Target/TargetInstrInfo.h
index 12d6e3b..2d21a9b 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetInstrInfo.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetInstrInfo.h
@@ -51,7 +51,10 @@ public:
DBG_LABEL = 2,
EH_LABEL = 3,
GC_LABEL = 4,
- // FIXME: DECLARE is removed. Readjust enum values ?
+
+ /// KILL - This instruction is a noop that is used only to adjust the liveness
+ /// of registers. This can be useful when dealing with sub-registers.
+ KILL = 5,
/// EXTRACT_SUBREG - This instruction takes two operands: a register
/// that has subregisters, and a subregister index. It returns the
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetInstrItineraries.h b/libclamav/c++/llvm/include/llvm/Target/TargetInstrItineraries.h
index 0e4ca98..420fa94 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetInstrItineraries.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetInstrItineraries.h
@@ -104,6 +104,14 @@ struct InstrItineraryData {
///
bool isEmpty() const { return Itineratries == 0; }
+ /// isEndMarker - Returns true if the index is for the end marker
+ /// itinerary.
+ ///
+ bool isEndMarker(unsigned ItinClassIndx) const {
+ return ((Itineratries[ItinClassIndx].FirstStage == ~0U) &&
+ (Itineratries[ItinClassIndx].LastStage == ~0U));
+ }
+
/// beginStage - Return the first stage of the itinerary.
///
const InstrStage *beginStage(unsigned ItinClassIndx) const {
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetLowering.h b/libclamav/c++/llvm/include/llvm/Target/TargetLowering.h
index 00a455c..4f567b0 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetLowering.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetLowering.h
@@ -1116,7 +1116,7 @@ public:
///
virtual SDValue
LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) {
@@ -1147,8 +1147,9 @@ public:
std::pair<SDValue, SDValue>
LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
bool isVarArg, bool isInreg, unsigned NumFixedArgs,
- unsigned CallConv, bool isTailCall, bool isReturnValueUsed,
- SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl);
+ CallingConv::ID CallConv, bool isTailCall,
+ bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
+ SelectionDAG &DAG, DebugLoc dl);
/// LowerCall - This hook must be implemented to lower calls into the
/// the specified DAG. The outgoing arguments to the call are described
@@ -1164,7 +1165,7 @@ public:
///
virtual SDValue
LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg, bool isTailCall,
+ CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -1179,7 +1180,7 @@ public:
/// value.
///
virtual SDValue
- LowerReturn(SDValue Chain, unsigned CallConv, bool isVarArg,
+ LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) {
assert(0 && "Not Implemented");
@@ -1283,7 +1284,7 @@ public:
/// should override this function.
virtual bool
IsEligibleForTailCallOptimization(SDValue Callee,
- unsigned CalleeCC,
+ CallingConv::ID CalleeCC,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const {
@@ -1439,8 +1440,12 @@ public:
// instructions are special in various ways, which require special support to
// insert. The specified MachineInstr is created but not inserted into any
// basic blocks, and the scheduler passes ownership of it to this method.
+ // When new basic blocks are inserted and the edges from MBB to its successors
+ // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
+ // DenseMap.
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
- MachineBasicBlock *MBB) const;
+ MachineBasicBlock *MBB,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
//===--------------------------------------------------------------------===//
// Addressing mode description hooks (used by LSR etc).
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetLoweringObjectFile.h b/libclamav/c++/llvm/include/llvm/Target/TargetLoweringObjectFile.h
index 7cb7b98..821e537 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetLoweringObjectFile.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetLoweringObjectFile.h
@@ -18,14 +18,16 @@
#include "llvm/MC/SectionKind.h"
namespace llvm {
+ class MachineModuleInfo;
class Mangler;
+ class MCAsmInfo;
+ class MCExpr;
class MCSection;
class MCSectionMachO;
class MCContext;
class GlobalValue;
class StringRef;
class TargetMachine;
- class MCAsmInfo;
class TargetLoweringObjectFile {
MCContext *Ctx;
@@ -173,6 +175,23 @@ public:
return 0;
}
+ /// getSymbolForDwarfGlobalReference - Return an MCExpr to use for a
+ /// pc-relative reference to the specified global variable from exception
+ /// handling information. In addition to the symbol, this returns
+ /// by-reference:
+ ///
+ /// IsIndirect - True if the returned symbol is actually a stub that contains
+ /// the address of the symbol, false if the symbol is the global itself.
+ ///
+ /// IsPCRel - True if the symbol reference is already pc-relative, false if
+ /// the caller needs to subtract off the address of the reference from the
+ /// symbol.
+ ///
+ virtual const MCExpr *
+ getSymbolForDwarfGlobalReference(const GlobalValue *GV, Mangler *Mang,
+ MachineModuleInfo *MMI,
+ bool &IsIndirect, bool &IsPCRel) const;
+
protected:
virtual const MCSection *
SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
@@ -282,11 +301,17 @@ public:
SectionKind K) const;
/// getTextCoalSection - Return the "__TEXT,__textcoal_nt" section we put weak
- /// symbols into.
+ /// text symbols into.
const MCSection *getTextCoalSection() const {
return TextCoalSection;
}
+ /// getConstTextCoalSection - Return the "__TEXT,__const_coal" section
+ /// we put weak read-only symbols into.
+ const MCSection *getConstTextCoalSection() const {
+ return ConstTextCoalSection;
+ }
+
/// getLazySymbolPointerSection - Return the section corresponding to
/// the .lazy_symbol_pointer directive.
const MCSection *getLazySymbolPointerSection() const {
@@ -298,6 +323,13 @@ public:
const MCSection *getNonLazySymbolPointerSection() const {
return NonLazySymbolPointerSection;
}
+
+ /// getSymbolForDwarfGlobalReference - The mach-o version of this method
+ /// defaults to returning a stub reference.
+ virtual const MCExpr *
+ getSymbolForDwarfGlobalReference(const GlobalValue *GV, Mangler *Mang,
+ MachineModuleInfo *MMI,
+ bool &IsIndirect, bool &IsPCRel) const;
};
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetMachine.h b/libclamav/c++/llvm/include/llvm/Target/TargetMachine.h
index 9614780..92b648c 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetMachine.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetMachine.h
@@ -362,20 +362,28 @@ public:
return true;
}
- /// addPreRegAllocPasses - This method may be implemented by targets that want
- /// to run passes immediately before register allocation. This should return
+ /// addPreRegAlloc - This method may be implemented by targets that want to
+ /// run passes immediately before register allocation. This should return
/// true if -print-machineinstrs should print after these passes.
virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
- /// addPostRegAllocPasses - This method may be implemented by targets that
- /// want to run passes after register allocation but before prolog-epilog
+ /// addPostRegAlloc - This method may be implemented by targets that want
+ /// to run passes after register allocation but before prolog-epilog
/// insertion. This should return true if -print-machineinstrs should print
/// after these passes.
virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
+
+ /// addPreSched2 - This method may be implemented by targets that want to
+ /// run passes after prolog-epilog insertion and before the second instruction
+ /// scheduling pass. This should return true if -print-machineinstrs should
+ /// print after these passes.
+ virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
+ return false;
+ }
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetOptions.h b/libclamav/c++/llvm/include/llvm/Target/TargetOptions.h
index b27d496..8d52dad 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetOptions.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetOptions.h
@@ -103,6 +103,15 @@ namespace llvm {
/// information should be emitted.
extern bool SjLjExceptionHandling;
+ /// JITEmitDebugInfo - This flag indicates that the JIT should try to emit
+ /// debug information and notify a debugger about it.
+ extern bool JITEmitDebugInfo;
+
+ /// JITEmitDebugInfoToDisk - This flag indicates that the JIT should write
+ /// the object files generated by the JITEmitDebugInfo flag to disk. This
+ /// flag is hidden and is only for debugging the debug info.
+ extern bool JITEmitDebugInfoToDisk;
+
/// UnwindTablesMandatory - This flag indicates that unwind tables should
/// be emitted for all functions.
extern bool UnwindTablesMandatory;
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetRegisterInfo.h b/libclamav/c++/llvm/include/llvm/Target/TargetRegisterInfo.h
index 1673c9a..6043ec8 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetRegisterInfo.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetRegisterInfo.h
@@ -41,7 +41,6 @@ class RegScavenger;
/// of AX.
///
struct TargetRegisterDesc {
- const char *AsmName; // Assembly language name for the register
const char *Name; // Printable name for the reg (for debugging)
const unsigned *AliasSet; // Register Alias Set, described above
const unsigned *SubRegs; // Sub-register set, described above
@@ -84,7 +83,7 @@ public:
RegSet.insert(*I);
}
virtual ~TargetRegisterClass() {} // Allow subclasses
-
+
/// getID() - Return the register class ID number.
///
unsigned getID() const { return ID; }
@@ -123,7 +122,7 @@ public:
return true;
return false;
}
-
+
/// vt_begin / vt_end - Loop over all of the value types that can be
/// represented by values in this register class.
vt_iterator vt_begin() const {
@@ -173,7 +172,7 @@ public:
/// hasSubClass - return true if the the specified TargetRegisterClass
/// is a proper subset of this TargetRegisterClass.
bool hasSubClass(const TargetRegisterClass *cs) const {
- for (int i = 0; SubClasses[i] != NULL; ++i)
+ for (int i = 0; SubClasses[i] != NULL; ++i)
if (SubClasses[i] == cs)
return true;
return false;
@@ -184,17 +183,17 @@ public:
sc_iterator subclasses_begin() const {
return SubClasses;
}
-
+
sc_iterator subclasses_end() const {
sc_iterator I = SubClasses;
while (*I != NULL) ++I;
return I;
}
-
+
/// hasSuperClass - return true if the specified TargetRegisterClass is a
/// proper superset of this TargetRegisterClass.
bool hasSuperClass(const TargetRegisterClass *cs) const {
- for (int i = 0; SuperClasses[i] != NULL; ++i)
+ for (int i = 0; SuperClasses[i] != NULL; ++i)
if (SuperClasses[i] == cs)
return true;
return false;
@@ -205,7 +204,7 @@ public:
sc_iterator superclasses_begin() const {
return SuperClasses;
}
-
+
sc_iterator superclasses_end() const {
sc_iterator I = SuperClasses;
while (*I != NULL) ++I;
@@ -217,7 +216,7 @@ public:
bool isASubClass() const {
return SuperClasses[0] != 0;
}
-
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
@@ -368,12 +367,6 @@ public:
return get(RegNo).SuperRegs;
}
- /// getAsmName - Return the symbolic target-specific name for the
- /// specified physical register.
- const char *getAsmName(unsigned RegNo) const {
- return get(RegNo).AsmName;
- }
-
/// getName - Return the human-readable symbolic target-specific name for the
/// specified physical register.
const char *getName(unsigned RegNo) const {
@@ -386,9 +379,16 @@ public:
return NumRegs;
}
- /// areAliases - Returns true if the two registers alias each other, false
- /// otherwise
- bool areAliases(unsigned regA, unsigned regB) const {
+ /// regsOverlap - Returns true if the two registers are equal or alias each
+ /// other. The registers may be virtual register.
+ bool regsOverlap(unsigned regA, unsigned regB) const {
+ if (regA == regB)
+ return true;
+
+ if (isVirtualRegister(regA) || isVirtualRegister(regB))
+ return false;
+
+ // regA and regB are distinct physical registers. Do they alias?
size_t index = (regA + regB * 37) & (AliasesHashSize-1);
unsigned ProbeAmt = 0;
while (AliasesHash[index*2] != 0 &&
@@ -403,17 +403,6 @@ public:
return false;
}
- /// regsOverlap - Returns true if the two registers are equal or alias each
- /// other. The registers may be virtual register.
- bool regsOverlap(unsigned regA, unsigned regB) const {
- if (regA == regB)
- return true;
-
- if (isVirtualRegister(regA) || isVirtualRegister(regB))
- return false;
- return areAliases(regA, regB);
- }
-
/// isSubRegister - Returns true if regB is a sub-register of regA.
///
bool isSubRegister(unsigned regA, unsigned regB) const {
@@ -424,11 +413,11 @@ public:
SubregHash[index*2+1] != 0) {
if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
return true;
-
+
index = (index + ProbeAmt) & (SubregHashSize-1);
ProbeAmt += 2;
}
-
+
return false;
}
@@ -442,11 +431,11 @@ public:
SuperregHash[index*2+1] != 0) {
if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB)
return true;
-
+
index = (index + ProbeAmt) & (SuperregHashSize-1);
ProbeAmt += 2;
}
-
+
return false;
}
@@ -476,7 +465,7 @@ public:
/// getMatchingSuperReg - Return a super-register of the specified register
/// Reg so its sub-register of index SubIdx is Reg.
- unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
+ unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
const TargetRegisterClass *RC) const {
for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
@@ -505,7 +494,7 @@ public:
unsigned getNumRegClasses() const {
return (unsigned)(regclass_end()-regclass_begin());
}
-
+
/// getRegClass - Returns the register class associated with the enumeration
/// value. See class TargetOperandInfo.
const TargetRegisterClass *getRegClass(unsigned i) const {
@@ -571,7 +560,7 @@ public:
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
return false;
}
-
+
/// hasFP - Return true if the specified function should have a dedicated
/// frame pointer register. For most targets this is true only if the function
/// has variable sized allocas or if frame pointer elimination is disabled.
@@ -661,10 +650,10 @@ public:
virtual void emitPrologue(MachineFunction &MF) const = 0;
virtual void emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const = 0;
-
+
//===--------------------------------------------------------------------===//
/// Debug information queries.
-
+
/// getDwarfRegNum - Map a target register to an equivalent dwarf register
/// number. Returns -1 if there is no equivalent value. The second
/// parameter allows targets to use different numberings for EH info and
@@ -678,11 +667,11 @@ public:
/// getFrameIndexOffset - Returns the displacement from the frame register to
/// the stack frame of the specified index.
virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
-
+
/// getRARegister - This method should return the register where the return
/// address can be found.
virtual unsigned getRARegister() const = 0;
-
+
/// getInitialFrameState - Returns a list of machine moves that are assumed
/// on entry to all functions. Note that LabelID is ignored (assumed to be
/// the beginning of the function.)
@@ -691,7 +680,7 @@ public:
// This is useful when building IndexedMaps keyed on virtual registers
-struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
+struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
unsigned operator()(unsigned Reg) const {
return Reg - TargetRegisterInfo::FirstVirtualRegister;
}
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetRegistry.h b/libclamav/c++/llvm/include/llvm/Target/TargetRegistry.h
index 5c89fa5..8042d23 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetRegistry.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetRegistry.h
@@ -29,9 +29,12 @@ namespace llvm {
class MCCodeEmitter;
class Module;
class MCAsmInfo;
+ class MCDisassembler;
+ class MCInstPrinter;
class TargetAsmParser;
class TargetMachine;
class formatted_raw_ostream;
+ class raw_ostream;
/// Target - Wrapper for Target specific information.
///
@@ -58,6 +61,11 @@ namespace llvm {
bool VerboseAsm);
typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,
MCAsmParser &P);
+ typedef const MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
+ typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI,
+ raw_ostream &O);
typedef MCCodeEmitter *(*CodeEmitterCtorTy)(const Target &T,
TargetMachine &TM);
@@ -92,7 +100,16 @@ namespace llvm {
/// AsmParserCtorFn - Construction function for this target's AsmParser,
/// if registered.
AsmParserCtorTy AsmParserCtorFn;
+
+ /// MCDisassemblerCtorFn - Construction function for this target's
+ /// MCDisassembler, if registered.
+ MCDisassemblerCtorTy MCDisassemblerCtorFn;
+
+ /// MCInstPrinterCtorFn - Construction function for this target's
+ /// MCInstPrinter, if registered.
+ MCInstPrinterCtorTy MCInstPrinterCtorFn;
+
/// CodeEmitterCtorFn - Construction function for this target's CodeEmitter,
/// if registered.
CodeEmitterCtorTy CodeEmitterCtorFn;
@@ -125,6 +142,12 @@ namespace llvm {
/// hasAsmParser - Check if this target supports .s parsing.
bool hasAsmParser() const { return AsmParserCtorFn != 0; }
+
+ /// hasMCDisassembler - Check if this target has a disassembler.
+ bool hasMCDisassembler() const { return MCDisassemblerCtorFn != 0; }
+
+ /// hasMCInstPrinter - Check if this target has an instruction printer.
+ bool hasMCInstPrinter() const { return MCInstPrinterCtorFn != 0; }
/// hasCodeEmitter - Check if this target supports instruction encoding.
bool hasCodeEmitter() const { return CodeEmitterCtorFn != 0; }
@@ -177,7 +200,22 @@ namespace llvm {
return 0;
return AsmParserCtorFn(*this, Parser);
}
+
+ const MCDisassembler *createMCDisassembler() const {
+ if (!MCDisassemblerCtorFn)
+ return 0;
+ return MCDisassemblerCtorFn(*this);
+ }
+ MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant,
+ const MCAsmInfo &MAI,
+ raw_ostream &O) const {
+ if (!MCInstPrinterCtorFn)
+ return 0;
+ return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, O);
+ }
+
+
/// createCodeEmitter - Create a target specific code emitter.
MCCodeEmitter *createCodeEmitter(TargetMachine &TM) const {
if (!CodeEmitterCtorFn)
@@ -333,7 +371,28 @@ namespace llvm {
if (!T.AsmParserCtorFn)
T.AsmParserCtorFn = Fn;
}
+
+ /// RegisterMCDisassembler - Register a MCDisassembler implementation for
+ /// the given target.
+ ///
+ /// Clients are responsible for ensuring that registration doesn't occur
+ /// while another thread is attempting to access the registry. Typically
+ /// this is done by initializing all targets at program startup.
+ ///
+ /// @param T - The target being registered.
+ /// @param Fn - A function to construct an MCDisassembler for the target.
+ static void RegisterMCDisassembler(Target &T,
+ Target::MCDisassemblerCtorTy Fn) {
+ if (!T.MCDisassemblerCtorFn)
+ T.MCDisassemblerCtorFn = Fn;
+ }
+ static void RegisterMCInstPrinter(Target &T,
+ Target::MCInstPrinterCtorTy Fn) {
+ if (!T.MCInstPrinterCtorFn)
+ T.MCInstPrinterCtorFn = Fn;
+ }
+
/// RegisterCodeEmitter - Register a MCCodeEmitter implementation for the
/// given target.
///
@@ -373,7 +432,7 @@ namespace llvm {
}
static unsigned getTripleMatchQuality(const std::string &TT) {
- if (Triple(TT.c_str()).getArch() == TargetArchType)
+ if (Triple(TT).getArch() == TargetArchType)
return 20;
return 0;
}
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetSchedule.td b/libclamav/c++/llvm/include/llvm/Target/TargetSchedule.td
index b3f566a..dcc0992 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetSchedule.td
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetSchedule.td
@@ -60,7 +60,7 @@ def NoItinerary : InstrItinClass;
//===----------------------------------------------------------------------===//
// Instruction itinerary data - These values provide a runtime map of an
-// instruction itinerary class (name) to it's itinerary data.
+// instruction itinerary class (name) to its itinerary data.
//
class InstrItinData<InstrItinClass Class, list<InstrStage> stages,
list<int> operandcycles = []> {
diff --git a/libclamav/c++/llvm/include/llvm/Target/TargetSubtarget.h b/libclamav/c++/llvm/include/llvm/Target/TargetSubtarget.h
index 14f612a..ac094f6 100644
--- a/libclamav/c++/llvm/include/llvm/Target/TargetSubtarget.h
+++ b/libclamav/c++/llvm/include/llvm/Target/TargetSubtarget.h
@@ -39,10 +39,14 @@ public:
/// should be attempted.
virtual unsigned getSpecialAddressLatency() const { return 0; }
+ // enablePostRAScheduler - Return true to enable
+ // post-register-allocation scheduling.
+ virtual bool enablePostRAScheduler() const { return false; }
+
// adjustSchedDependency - Perform target specific adjustments to
// the latency of a schedule dependency.
virtual void adjustSchedDependency(SUnit *def, SUnit *use,
- SDep& dep) const { };
+ SDep& dep) const { }
};
} // End llvm namespace
diff --git a/libclamav/c++/llvm/include/llvm/Transforms/IPO.h b/libclamav/c++/llvm/include/llvm/Transforms/IPO.h
index 750969b..d66ed89 100644
--- a/libclamav/c++/llvm/include/llvm/Transforms/IPO.h
+++ b/libclamav/c++/llvm/include/llvm/Transforms/IPO.h
@@ -19,7 +19,6 @@
namespace llvm {
-class FunctionPass;
class ModulePass;
class Pass;
class Function;
@@ -174,12 +173,12 @@ ModulePass *createIPSCCPPass();
/// createLoopExtractorPass - This pass extracts all natural loops from the
/// program into a function if it can.
///
-FunctionPass *createLoopExtractorPass();
+Pass *createLoopExtractorPass();
/// createSingleLoopExtractorPass - This pass extracts one natural loop from the
/// program into a function if it can. This is used by bugpoint.
///
-FunctionPass *createSingleLoopExtractorPass();
+Pass *createSingleLoopExtractorPass();
/// createBlockExtractorPass - This pass extracts all blocks (except those
/// specified in the argument list) from the functions in the module.
diff --git a/libclamav/c++/llvm/include/llvm/Transforms/Instrumentation.h b/libclamav/c++/llvm/include/llvm/Transforms/Instrumentation.h
index 698e248..9794ffd 100644
--- a/libclamav/c++/llvm/include/llvm/Transforms/Instrumentation.h
+++ b/libclamav/c++/llvm/include/llvm/Transforms/Instrumentation.h
@@ -28,6 +28,9 @@ ModulePass *createBlockProfilerPass();
// Insert edge profiling instrumentation
ModulePass *createEdgeProfilerPass();
+// Insert optimal edge profiling instrumentation
+ModulePass *createOptimalEdgeProfilerPass();
+
// Random Sampling Profiling Framework
ModulePass* createNullProfilerRSPass();
FunctionPass* createRSProfilingPass();
diff --git a/libclamav/c++/llvm/include/llvm/Transforms/Scalar.h b/libclamav/c++/llvm/include/llvm/Transforms/Scalar.h
index f193b8d..012f69b 100644
--- a/libclamav/c++/llvm/include/llvm/Transforms/Scalar.h
+++ b/libclamav/c++/llvm/include/llvm/Transforms/Scalar.h
@@ -220,7 +220,7 @@ extern const PassInfo *const BreakCriticalEdgesID;
//
// AU.addRequiredID(LoopSimplifyID);
//
-FunctionPass *createLoopSimplifyPass();
+Pass *createLoopSimplifyPass();
extern const PassInfo *const LoopSimplifyID;
//===----------------------------------------------------------------------===//
@@ -285,13 +285,6 @@ FunctionPass *createPredicateSimplifierPass();
//===----------------------------------------------------------------------===//
//
-// GVN-PRE - This pass performs global value numbering and partial redundancy
-// elimination.
-//
-FunctionPass *createGVNPREPass();
-
-//===----------------------------------------------------------------------===//
-//
// GVN - This pass performs global value numbering and redundant load
// elimination cotemporaneously.
//
@@ -329,6 +322,11 @@ FunctionPass *createSimplifyHalfPowrLibCallsPass();
//
FunctionPass *createCodeGenPreparePass(const TargetLowering *TLI = 0);
+//===----------------------------------------------------------------------===//
+//
+// CodeGenLICM - This pass performs late LICM; hoisting constants out of loops.
+//
+Pass *createCodeGenLICMPass();
//===----------------------------------------------------------------------===//
//
diff --git a/libclamav/c++/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h b/libclamav/c++/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
index 95ffa46..e766d72 100644
--- a/libclamav/c++/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
+++ b/libclamav/c++/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
@@ -126,10 +126,10 @@ bool isCriticalEdge(const TerminatorInst *TI, unsigned SuccNum,
/// dest go to one block instead of each going to a different block, but isn't
/// the standard definition of a "critical edge".
///
-bool SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum, Pass *P = 0,
- bool MergeIdenticalEdges = false);
+BasicBlock *SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum,
+ Pass *P = 0, bool MergeIdenticalEdges = false);
-inline bool SplitCriticalEdge(BasicBlock *BB, succ_iterator SI, Pass *P = 0) {
+inline BasicBlock *SplitCriticalEdge(BasicBlock *BB, succ_iterator SI, Pass *P = 0) {
return SplitCriticalEdge(BB->getTerminator(), SI.getSuccessorIndex(), P);
}
@@ -143,7 +143,7 @@ inline bool SplitCriticalEdge(BasicBlock *Succ, pred_iterator PI, Pass *P = 0) {
TerminatorInst *TI = (*PI)->getTerminator();
for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i)
if (TI->getSuccessor(i) == Succ)
- MadeChange |= SplitCriticalEdge(TI, i, P);
+ MadeChange |= !!SplitCriticalEdge(TI, i, P);
return MadeChange;
}
@@ -151,8 +151,9 @@ inline bool SplitCriticalEdge(BasicBlock *Succ, pred_iterator PI, Pass *P = 0) {
/// and return true, otherwise return false. This method requires that there be
/// an edge between the two blocks. If P is specified, it updates the analyses
/// described above.
-inline bool SplitCriticalEdge(BasicBlock *Src, BasicBlock *Dst, Pass *P = 0,
- bool MergeIdenticalEdges = false) {
+inline BasicBlock *SplitCriticalEdge(BasicBlock *Src, BasicBlock *Dst,
+ Pass *P = 0,
+ bool MergeIdenticalEdges = false) {
TerminatorInst *TI = Src->getTerminator();
unsigned i = 0;
while (1) {
@@ -180,8 +181,12 @@ BasicBlock *SplitBlock(BasicBlock *Old, Instruction *SplitPt, Pass *P);
/// Preds array, which has NumPreds elements in it. The new block is given a
/// suffix of 'Suffix'. This function returns the new block.
///
-/// This currently updates the LLVM IR, AliasAnalysis, DominatorTree and
-/// DominanceFrontier, but no other analyses.
+/// This currently updates the LLVM IR, AliasAnalysis, DominatorTree,
+/// DominanceFrontier, LoopInfo, and LCCSA but no other analyses.
+/// In particular, it does not preserve LoopSimplify (because it's
+/// complicated to handle the case where one of the edges being split
+/// is an exit of a loop with other exits).
+///
BasicBlock *SplitBlockPredecessors(BasicBlock *BB, BasicBlock *const *Preds,
unsigned NumPreds, const char *Suffix,
Pass *P = 0);
diff --git a/libclamav/c++/llvm/include/llvm/Transforms/Utils/Local.h b/libclamav/c++/llvm/include/llvm/Transforms/Utils/Local.h
index 32e7ae8..419029f 100644
--- a/libclamav/c++/llvm/include/llvm/Transforms/Utils/Local.h
+++ b/libclamav/c++/llvm/include/llvm/Transforms/Utils/Local.h
@@ -83,7 +83,7 @@ void RecursivelyDeleteDeadPHINode(PHINode *PN);
/// between them, moving the instructions in the predecessor into BB. This
/// deletes the predecessor block.
///
-void MergeBasicBlockIntoOnlyPred(BasicBlock *BB);
+void MergeBasicBlockIntoOnlyPred(BasicBlock *BB, Pass *P = 0);
/// SimplifyCFG - This function is used to do simplification of a CFG. For
diff --git a/libclamav/c++/llvm/include/llvm/Transforms/Utils/SSI.h b/libclamav/c++/llvm/include/llvm/Transforms/Utils/SSI.h
index a18930f..8b49aac 100644
--- a/libclamav/c++/llvm/include/llvm/Transforms/Utils/SSI.h
+++ b/libclamav/c++/llvm/include/llvm/Transforms/Utils/SSI.h
@@ -81,6 +81,7 @@ namespace llvm {
SmallVector<SmallVector<Instruction *, 1>, 0> value_stack;
void insertSigmaFunctions(SmallVectorImpl<Instruction *> &value);
+ void insertSigma(TerminatorInst *TI, Instruction *I, unsigned pos);
void insertPhiFunctions(SmallVectorImpl<Instruction *> &value);
void renameInit(SmallVectorImpl<Instruction *> &value);
void rename(BasicBlock *BB);
@@ -92,8 +93,6 @@ namespace llvm {
unsigned getPositionPhi(PHINode *PN);
unsigned getPositionSigma(PHINode *PN);
- unsigned isUsedInTerminator(CmpInst *CI);
-
void init(SmallVectorImpl<Instruction *> &value);
void clean();
};
diff --git a/libclamav/c++/llvm/include/llvm/Value.h b/libclamav/c++/llvm/include/llvm/Value.h
index fdc3aeb..6b393f6 100644
--- a/libclamav/c++/llvm/include/llvm/Value.h
+++ b/libclamav/c++/llvm/include/llvm/Value.h
@@ -42,6 +42,7 @@ class raw_ostream;
class AssemblyAnnotationWriter;
class ValueHandleBase;
class LLVMContext;
+class MetadataContext;
//===----------------------------------------------------------------------===//
// Value Class
@@ -63,6 +64,7 @@ class LLVMContext;
class Value {
const unsigned char SubclassID; // Subclass identifier (for isa/dyn_cast)
unsigned char HasValueHandle : 1; // Has a ValueHandle pointing to this?
+ unsigned char HasMetadata : 1; // Has a metadata attached to this ?
protected:
/// SubclassOptionalData - This member is similar to SubclassData, however it
/// is for holding information which may be used to aid optimization, but
@@ -81,18 +83,25 @@ private:
friend class ValueSymbolTable; // Allow ValueSymbolTable to directly mod Name.
friend class SymbolTable; // Allow SymbolTable to directly poke Name.
friend class ValueHandleBase;
+ friend class MetadataContext;
+ friend class AbstractTypeUser;
ValueName *Name;
void operator=(const Value &); // Do not implement
Value(const Value &); // Do not implement
+protected:
+ /// printCustom - Value subclasses can override this to implement custom
+ /// printing behavior.
+ virtual void printCustom(raw_ostream &O) const;
+
public:
Value(const Type *Ty, unsigned scid);
virtual ~Value();
/// dump - Support for debugging, callable in GDB: V->dump()
//
- virtual void dump() const;
+ void dump() const;
/// print - Implement operator<< on Value.
///
@@ -146,12 +155,6 @@ public:
// Only use when in type resolution situations!
void uncheckedReplaceAllUsesWith(Value *V);
- /// clearOptionalData - Clear any optional optimization data from this Value.
- /// Transformation passes must call this method whenever changing the IR
- /// in a way that would affect the values produced by this Value, unless
- /// it takes special care to ensure correctness in some other way.
- void clearOptionalData() { SubclassOptionalData = 0; }
-
//----------------------------------------------------------------------
// Methods for handling the chain of uses of this Value.
//
@@ -240,6 +243,13 @@ public:
return SubclassID;
}
+ /// getRawSubclassOptionalData - Return the raw optional flags value
+ /// contained in this value. This should only be used when testing two
+ /// Values for equivalence.
+ unsigned getRawSubclassOptionalData() const {
+ return SubclassOptionalData;
+ }
+
/// hasSameSubclassOptionalData - Test whether the optional flags contained
/// in this value are equal to the optional flags in the given value.
bool hasSameSubclassOptionalData(const Value *V) const {
@@ -288,6 +298,9 @@ public:
const BasicBlock *PredBB) const{
return const_cast<Value*>(this)->DoPHITranslation(CurBB, PredBB);
}
+
+ /// hasMetadata - Return true if metadata is attached with this value.
+ bool hasMetadata() const { return HasMetadata; }
};
inline raw_ostream &operator<<(raw_ostream &OS, const Value &V) {
diff --git a/libclamav/c++/llvm/lib/Analysis/AliasAnalysisCounter.cpp b/libclamav/c++/llvm/lib/Analysis/AliasAnalysisCounter.cpp
index 06827ae..272c871 100644
--- a/libclamav/c++/llvm/lib/Analysis/AliasAnalysisCounter.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/AliasAnalysisCounter.cpp
@@ -90,19 +90,6 @@ namespace {
bool pointsToConstantMemory(const Value *P) {
return getAnalysis<AliasAnalysis>().pointsToConstantMemory(P);
}
- bool doesNotAccessMemory(CallSite CS) {
- return getAnalysis<AliasAnalysis>().doesNotAccessMemory(CS);
- }
- bool doesNotAccessMemory(Function *F) {
- return getAnalysis<AliasAnalysis>().doesNotAccessMemory(F);
- }
- bool onlyReadsMemory(CallSite CS) {
- return getAnalysis<AliasAnalysis>().onlyReadsMemory(CS);
- }
- bool onlyReadsMemory(Function *F) {
- return getAnalysis<AliasAnalysis>().onlyReadsMemory(F);
- }
-
// Forwarding functions: just delegate to a real AA implementation, counting
// the number of responses...
diff --git a/libclamav/c++/llvm/lib/Analysis/BasicAliasAnalysis.cpp b/libclamav/c++/llvm/lib/Analysis/BasicAliasAnalysis.cpp
index 9e9d0f1..5fa87ff 100644
--- a/libclamav/c++/llvm/lib/Analysis/BasicAliasAnalysis.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/BasicAliasAnalysis.cpp
@@ -15,6 +15,7 @@
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/CaptureTracking.h"
+#include "llvm/Analysis/MallocHelper.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
@@ -102,7 +103,7 @@ static bool isNonEscapingLocalObject(const Value *V) {
/// isObjectSmallerThan - Return true if we can prove that the object specified
/// by V is smaller than Size.
static bool isObjectSmallerThan(const Value *V, unsigned Size,
- const TargetData &TD) {
+ LLVMContext &Context, const TargetData &TD) {
const Type *AccessTy;
if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(V)) {
AccessTy = GV->getType()->getElementType();
@@ -111,6 +112,12 @@ static bool isObjectSmallerThan(const Value *V, unsigned Size,
AccessTy = AI->getType()->getElementType();
else
return false;
+ } else if (const CallInst* CI = extractMallocCall(V)) {
+ if (!isArrayMalloc(V, Context, &TD))
+ // The size is the argument to the malloc call.
+ if (const ConstantInt* C = dyn_cast<ConstantInt>(CI->getOperand(1)))
+ return (C->getZExtValue() < Size);
+ return false;
} else if (const Argument *A = dyn_cast<Argument>(V)) {
if (A->hasByValAttr())
AccessTy = cast<PointerType>(A->getType())->getElementType();
@@ -340,9 +347,10 @@ BasicAliasAnalysis::alias(const Value *V1, unsigned V1Size,
// If the size of one access is larger than the entire object on the other
// side, then we know such behavior is undefined and can assume no alias.
+ LLVMContext &Context = V1->getContext();
if (TD)
- if ((V1Size != ~0U && isObjectSmallerThan(O2, V1Size, *TD)) ||
- (V2Size != ~0U && isObjectSmallerThan(O1, V2Size, *TD)))
+ if ((V1Size != ~0U && isObjectSmallerThan(O2, V1Size, Context, *TD)) ||
+ (V2Size != ~0U && isObjectSmallerThan(O1, V2Size, Context, *TD)))
return NoAlias;
// If one pointer is the result of a call/invoke and the other is a
diff --git a/libclamav/c++/llvm/lib/Analysis/CFGPrinter.cpp b/libclamav/c++/llvm/lib/Analysis/CFGPrinter.cpp
index 03cfb9d..6fed400 100644
--- a/libclamav/c++/llvm/lib/Analysis/CFGPrinter.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/CFGPrinter.cpp
@@ -110,7 +110,7 @@ namespace {
CFGOnlyViewer() : FunctionPass(&ID) {}
virtual bool runOnFunction(Function &F) {
- F.viewCFG();
+ F.viewCFGOnly();
return false;
}
diff --git a/libclamav/c++/llvm/lib/Analysis/CMakeLists.txt b/libclamav/c++/llvm/lib/Analysis/CMakeLists.txt
index 6120632..d233322 100644
--- a/libclamav/c++/llvm/lib/Analysis/CMakeLists.txt
+++ b/libclamav/c++/llvm/lib/Analysis/CMakeLists.txt
@@ -22,6 +22,7 @@ add_llvm_library(LLVMAnalysis
LoopInfo.cpp
LoopPass.cpp
LoopVR.cpp
+ MallocHelper.cpp
MemoryDependenceAnalysis.cpp
PointerTracking.cpp
PostDominators.cpp
@@ -29,6 +30,7 @@ add_llvm_library(LLVMAnalysis
ProfileInfo.cpp
ProfileInfoLoader.cpp
ProfileInfoLoaderPass.cpp
+ ProfileVerifierPass.cpp
ScalarEvolution.cpp
ScalarEvolutionAliasAnalysis.cpp
ScalarEvolutionExpander.cpp
diff --git a/libclamav/c++/llvm/lib/Analysis/ConstantFolding.cpp b/libclamav/c++/llvm/lib/Analysis/ConstantFolding.cpp
index 5dcb021..f911b66 100644
--- a/libclamav/c++/llvm/lib/Analysis/ConstantFolding.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/ConstantFolding.cpp
@@ -1,4 +1,4 @@
-//===-- ConstantFolding.cpp - Analyze constant folding possibilities ------===//
+//===-- ConstantFolding.cpp - Fold instructions into constants ------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,8 +7,12 @@
//
//===----------------------------------------------------------------------===//
//
-// This family of functions determines the possibility of performing constant
-// folding.
+// This file defines routines for folding instructions into constants.
+//
+// Also, to supplement the basic VMCore ConstantExpr simplifications,
+// this file defines some additional folding routines that can make use of
+// TargetData information. These functions cannot go in VMCore due to library
+// dependency issues.
//
//===----------------------------------------------------------------------===//
@@ -172,7 +176,7 @@ static Constant *SymbolicallyEvaluateGEP(Constant* const* Ops, unsigned NumOps,
do {
if (const SequentialType *ATy = dyn_cast<SequentialType>(Ty)) {
// The only pointer indexing we'll do is on the first index of the GEP.
- if (isa<PointerType>(ATy) && ATy != Ptr->getType())
+ if (isa<PointerType>(ATy) && !NewIdxs.empty())
break;
// Determine which element of the array the offset points into.
APInt ElemSize(BitWidth, TD->getTypeAllocSize(ATy->getElementType()));
@@ -203,12 +207,8 @@ static Constant *SymbolicallyEvaluateGEP(Constant* const* Ops, unsigned NumOps,
if (Offset != 0)
return 0;
- // If the base is the start of a GlobalVariable and all the array indices
- // remain in their static bounds, the GEP is inbounds. We can check that
- // all indices are in bounds by just checking the first index only
- // because we've just normalized all the indices.
- Constant *C = isa<GlobalVariable>(Ptr) && NewIdxs[0]->isNullValue() ?
- ConstantExpr::getInBoundsGetElementPtr(Ptr, &NewIdxs[0], NewIdxs.size()) :
+ // Create a GEP.
+ Constant *C =
ConstantExpr::getGetElementPtr(Ptr, &NewIdxs[0], NewIdxs.size());
assert(cast<PointerType>(C->getType())->getElementType() == Ty &&
"Computed GetElementPtr has unexpected type!");
@@ -379,9 +379,9 @@ Constant *llvm::ConstantFoldInstruction(Instruction *I, LLVMContext &Context,
return ConstantFoldCompareInstOperands(CI->getPredicate(),
Ops.data(), Ops.size(),
Context, TD);
- else
- return ConstantFoldInstOperands(I->getOpcode(), I->getType(),
- Ops.data(), Ops.size(), Context, TD);
+
+ return ConstantFoldInstOperands(I->getOpcode(), I->getType(),
+ Ops.data(), Ops.size(), Context, TD);
}
/// ConstantFoldConstantExpression - Attempt to fold the constant expression
@@ -398,9 +398,8 @@ Constant *llvm::ConstantFoldConstantExpression(ConstantExpr *CE,
return ConstantFoldCompareInstOperands(CE->getPredicate(),
Ops.data(), Ops.size(),
Context, TD);
- else
- return ConstantFoldInstOperands(CE->getOpcode(), CE->getType(),
- Ops.data(), Ops.size(), Context, TD);
+ return ConstantFoldInstOperands(CE->getOpcode(), CE->getType(),
+ Ops.data(), Ops.size(), Context, TD);
}
/// ConstantFoldInstOperands - Attempt to constant fold an instruction with the
diff --git a/libclamav/c++/llvm/lib/Analysis/DbgInfoPrinter.cpp b/libclamav/c++/llvm/lib/Analysis/DbgInfoPrinter.cpp
index 8063476..2bbe2e0 100644
--- a/libclamav/c++/llvm/lib/Analysis/DbgInfoPrinter.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/DbgInfoPrinter.cpp
@@ -91,9 +91,8 @@ void PrintDbgInfo::printStopPoint(const DbgStopPointInst *DSI) {
void PrintDbgInfo::printFuncStart(const DbgFuncStartInst *FS) {
DISubprogram Subprogram(FS->getSubprogram());
- std::string Res1, Res2;
- Out << "; fully qualified function name: " << Subprogram.getDisplayName(Res1)
- << " return type: " << Subprogram.getReturnTypeName(Res2)
+ Out << "; fully qualified function name: " << Subprogram.getDisplayName()
+ << " return type: " << Subprogram.getReturnTypeName()
<< " at line " << Subprogram.getLineNumber()
<< "\n\n";
}
diff --git a/libclamav/c++/llvm/lib/Analysis/DebugInfo.cpp b/libclamav/c++/llvm/lib/Analysis/DebugInfo.cpp
index 0d4b213..1d6e3a6 100644
--- a/libclamav/c++/llvm/lib/Analysis/DebugInfo.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/DebugInfo.cpp
@@ -71,41 +71,38 @@ bool DIDescriptor::ValidDebugInfo(MDNode *N, CodeGenOpt::Level OptLevel) {
DIDescriptor::DIDescriptor(MDNode *N, unsigned RequiredTag) {
DbgNode = N;
-
+
// If this is non-null, check to see if the Tag matches. If not, set to null.
if (N && getTag() != RequiredTag) {
DbgNode = 0;
}
}
-const std::string &
-DIDescriptor::getStringField(unsigned Elt, std::string &Result) const {
- Result.clear();
+const char *
+DIDescriptor::getStringField(unsigned Elt) const {
if (DbgNode == 0)
- return Result;
+ return NULL;
- if (Elt < DbgNode->getNumElements())
- if (MDString *MDS = dyn_cast_or_null<MDString>(DbgNode->getElement(Elt))) {
- Result.assign(MDS->begin(), MDS->begin() + MDS->length());
- return Result;
- }
-
- return Result;
+ if (Elt < DbgNode->getNumElements())
+ if (MDString *MDS = dyn_cast_or_null<MDString>(DbgNode->getElement(Elt)))
+ return MDS->getString().data();
+
+ return NULL;
}
uint64_t DIDescriptor::getUInt64Field(unsigned Elt) const {
- if (DbgNode == 0)
+ if (DbgNode == 0)
return 0;
if (Elt < DbgNode->getNumElements())
if (ConstantInt *CI = dyn_cast<ConstantInt>(DbgNode->getElement(Elt)))
return CI->getZExtValue();
-
+
return 0;
}
DIDescriptor DIDescriptor::getDescriptorField(unsigned Elt) const {
- if (DbgNode == 0)
+ if (DbgNode == 0)
return DIDescriptor();
if (Elt < DbgNode->getNumElements() && DbgNode->getElement(Elt))
@@ -115,7 +112,7 @@ DIDescriptor DIDescriptor::getDescriptorField(unsigned Elt) const {
}
GlobalVariable *DIDescriptor::getGlobalVariableField(unsigned Elt) const {
- if (DbgNode == 0)
+ if (DbgNode == 0)
return 0;
if (Elt < DbgNode->getNumElements())
@@ -124,22 +121,23 @@ GlobalVariable *DIDescriptor::getGlobalVariableField(unsigned Elt) const {
}
//===----------------------------------------------------------------------===//
-// Simple Descriptor Constructors and other Methods
+// Predicates
//===----------------------------------------------------------------------===//
-// Needed by DIVariable::getType().
-DIType::DIType(MDNode *N) : DIDescriptor(N) {
- if (!N) return;
- unsigned tag = getTag();
- if (tag != dwarf::DW_TAG_base_type && !DIDerivedType::isDerivedType(tag) &&
- !DICompositeType::isCompositeType(tag)) {
- DbgNode = 0;
- }
+/// isBasicType - Return true if the specified tag is legal for
+/// DIBasicType.
+bool DIDescriptor::isBasicType() const {
+ assert (!isNull() && "Invalid descriptor!");
+ unsigned Tag = getTag();
+
+ return Tag == dwarf::DW_TAG_base_type;
}
-/// isDerivedType - Return true if the specified tag is legal for
-/// DIDerivedType.
-bool DIType::isDerivedType(unsigned Tag) {
+/// isDerivedType - Return true if the specified tag is legal for DIDerivedType.
+bool DIDescriptor::isDerivedType() const {
+ assert (!isNull() && "Invalid descriptor!");
+ unsigned Tag = getTag();
+
switch (Tag) {
case dwarf::DW_TAG_typedef:
case dwarf::DW_TAG_pointer_type:
@@ -152,14 +150,17 @@ bool DIType::isDerivedType(unsigned Tag) {
return true;
default:
// CompositeTypes are currently modelled as DerivedTypes.
- return isCompositeType(Tag);
+ return isCompositeType();
}
}
/// isCompositeType - Return true if the specified tag is legal for
/// DICompositeType.
-bool DIType::isCompositeType(unsigned TAG) {
- switch (TAG) {
+bool DIDescriptor::isCompositeType() const {
+ assert (!isNull() && "Invalid descriptor!");
+ unsigned Tag = getTag();
+
+ switch (Tag) {
case dwarf::DW_TAG_array_type:
case dwarf::DW_TAG_structure_type:
case dwarf::DW_TAG_union_type:
@@ -174,7 +175,10 @@ bool DIType::isCompositeType(unsigned TAG) {
}
/// isVariable - Return true if the specified tag is legal for DIVariable.
-bool DIVariable::isVariable(unsigned Tag) {
+bool DIDescriptor::isVariable() const {
+ assert (!isNull() && "Invalid descriptor!");
+ unsigned Tag = getTag();
+
switch (Tag) {
case dwarf::DW_TAG_auto_variable:
case dwarf::DW_TAG_arg_variable:
@@ -185,6 +189,94 @@ bool DIVariable::isVariable(unsigned Tag) {
}
}
+/// isType - Return true if the specified tag is legal for DIType.
+bool DIDescriptor::isType() const {
+ return isBasicType() || isCompositeType() || isDerivedType();
+}
+
+/// isSubprogram - Return true if the specified tag is legal for
+/// DISubprogram.
+bool DIDescriptor::isSubprogram() const {
+ assert (!isNull() && "Invalid descriptor!");
+ unsigned Tag = getTag();
+
+ return Tag == dwarf::DW_TAG_subprogram;
+}
+
+/// isGlobalVariable - Return true if the specified tag is legal for
+/// DIGlobalVariable.
+bool DIDescriptor::isGlobalVariable() const {
+ assert (!isNull() && "Invalid descriptor!");
+ unsigned Tag = getTag();
+
+ return Tag == dwarf::DW_TAG_variable;
+}
+
+/// isGlobal - Return true if the specified tag is legal for DIGlobal.
+bool DIDescriptor::isGlobal() const {
+ return isGlobalVariable();
+}
+
+/// isScope - Return true if the specified tag is one of the scope
+/// related tag.
+bool DIDescriptor::isScope() const {
+ assert (!isNull() && "Invalid descriptor!");
+ unsigned Tag = getTag();
+
+ switch (Tag) {
+ case dwarf::DW_TAG_compile_unit:
+ case dwarf::DW_TAG_lexical_block:
+ case dwarf::DW_TAG_subprogram:
+ return true;
+ default:
+ break;
+ }
+ return false;
+}
+
+/// isCompileUnit - Return true if the specified tag is DW_TAG_compile_unit.
+bool DIDescriptor::isCompileUnit() const {
+ assert (!isNull() && "Invalid descriptor!");
+ unsigned Tag = getTag();
+
+ return Tag == dwarf::DW_TAG_compile_unit;
+}
+
+/// isLexicalBlock - Return true if the specified tag is DW_TAG_lexical_block.
+bool DIDescriptor::isLexicalBlock() const {
+ assert (!isNull() && "Invalid descriptor!");
+ unsigned Tag = getTag();
+
+ return Tag == dwarf::DW_TAG_lexical_block;
+}
+
+/// isSubrange - Return true if the specified tag is DW_TAG_subrange_type.
+bool DIDescriptor::isSubrange() const {
+ assert (!isNull() && "Invalid descriptor!");
+ unsigned Tag = getTag();
+
+ return Tag == dwarf::DW_TAG_subrange_type;
+}
+
+/// isEnumerator - Return true if the specified tag is DW_TAG_enumerator.
+bool DIDescriptor::isEnumerator() const {
+ assert (!isNull() && "Invalid descriptor!");
+ unsigned Tag = getTag();
+
+ return Tag == dwarf::DW_TAG_enumerator;
+}
+
+//===----------------------------------------------------------------------===//
+// Simple Descriptor Constructors and other Methods
+//===----------------------------------------------------------------------===//
+
+DIType::DIType(MDNode *N) : DIDescriptor(N) {
+ if (!N) return;
+ if (!isBasicType() && !isDerivedType() && !isCompositeType()) {
+ DbgNode = 0;
+ }
+}
+
unsigned DIArray::getNumElements() const {
assert (DbgNode && "Invalid DIArray");
return DbgNode->getNumElements();
@@ -198,16 +290,25 @@ void DIDerivedType::replaceAllUsesWith(DIDescriptor &D) {
return;
assert (!D.isNull() && "Can not replace with null");
- DbgNode->replaceAllUsesWith(D.getNode());
- delete DbgNode;
+
+ // Since we use a TrackingVH for the node, its easy for clients to manufacture
+ // legitimate situations where they want to replaceAllUsesWith() on something
+ // which, due to uniquing, has merged with the source. We shield clients from
+ // this detail by allowing a value to be replaced with replaceAllUsesWith()
+ // itself.
+ if (getNode() != D.getNode()) {
+ MDNode *Node = DbgNode;
+ Node->replaceAllUsesWith(D.getNode());
+ delete Node;
+ }
}
/// Verify - Verify that a compile unit is well formed.
bool DICompileUnit::Verify() const {
- if (isNull())
+ if (isNull())
return false;
- std::string Res;
- if (getFilename(Res).empty())
+ const char *N = getFilename();
+ if (!N)
return false;
// It is possible that directory and produce string is empty.
return true;
@@ -215,26 +316,26 @@ bool DICompileUnit::Verify() const {
/// Verify - Verify that a type descriptor is well formed.
bool DIType::Verify() const {
- if (isNull())
+ if (isNull())
return false;
- if (getContext().isNull())
+ if (getContext().isNull())
return false;
DICompileUnit CU = getCompileUnit();
- if (!CU.isNull() && !CU.Verify())
+ if (!CU.isNull() && !CU.Verify())
return false;
return true;
}
/// Verify - Verify that a composite type descriptor is well formed.
bool DICompositeType::Verify() const {
- if (isNull())
+ if (isNull())
return false;
- if (getContext().isNull())
+ if (getContext().isNull())
return false;
DICompileUnit CU = getCompileUnit();
- if (!CU.isNull() && !CU.Verify())
+ if (!CU.isNull() && !CU.Verify())
return false;
return true;
}
@@ -243,12 +344,12 @@ bool DICompositeType::Verify() const {
bool DISubprogram::Verify() const {
if (isNull())
return false;
-
+
if (getContext().isNull())
return false;
DICompileUnit CU = getCompileUnit();
- if (!CU.Verify())
+ if (!CU.Verify())
return false;
DICompositeType Ty = getType();
@@ -261,12 +362,12 @@ bool DISubprogram::Verify() const {
bool DIGlobalVariable::Verify() const {
if (isNull())
return false;
-
+
if (getContext().isNull())
return false;
DICompileUnit CU = getCompileUnit();
- if (!CU.isNull() && !CU.Verify())
+ if (!CU.isNull() && !CU.Verify())
return false;
DIType Ty = getType();
@@ -283,7 +384,7 @@ bool DIGlobalVariable::Verify() const {
bool DIVariable::Verify() const {
if (isNull())
return false;
-
+
if (getContext().isNull())
return false;
@@ -309,15 +410,38 @@ uint64_t DIDerivedType::getOriginalTypeSize() const {
/// information for the function F.
bool DISubprogram::describes(const Function *F) {
assert (F && "Invalid function");
- std::string Name;
- getLinkageName(Name);
- if (Name.empty())
- getName(Name);
- if (F->getName() == Name)
+ const char *Name = getLinkageName();
+ if (!Name)
+ Name = getName();
+ if (strcmp(F->getName().data(), Name) == 0)
return true;
return false;
}
+const char *DIScope::getFilename() const {
+ if (isLexicalBlock())
+ return DILexicalBlock(DbgNode).getFilename();
+ else if (isSubprogram())
+ return DISubprogram(DbgNode).getFilename();
+ else if (isCompileUnit())
+ return DICompileUnit(DbgNode).getFilename();
+ else
+ assert (0 && "Invalid DIScope!");
+ return NULL;
+}
+
+const char *DIScope::getDirectory() const {
+ if (isLexicalBlock())
+ return DILexicalBlock(DbgNode).getDirectory();
+ else if (isSubprogram())
+ return DISubprogram(DbgNode).getDirectory();
+ else if (isCompileUnit())
+ return DICompileUnit(DbgNode).getDirectory();
+ else
+ assert (0 && "Invalid DIScope!");
+ return NULL;
+}
+
//===----------------------------------------------------------------------===//
// DIDescriptor: dump routines for all descriptors.
//===----------------------------------------------------------------------===//
@@ -326,7 +450,7 @@ bool DISubprogram::describes(const Function *F) {
/// dump - Print descriptor.
void DIDescriptor::dump() const {
errs() << "[" << dwarf::TagString(getTag()) << "] ";
- errs().write_hex((intptr_t)DbgNode) << ']';
+ errs().write_hex((intptr_t) &*DbgNode) << ']';
}
/// dump - Print compile unit.
@@ -334,16 +458,14 @@ void DICompileUnit::dump() const {
if (getLanguage())
errs() << " [" << dwarf::LanguageString(getLanguage()) << "] ";
- std::string Res1, Res2;
- errs() << " [" << getDirectory(Res1) << "/" << getFilename(Res2) << " ]";
+ errs() << " [" << getDirectory() << "/" << getFilename() << " ]";
}
/// dump - Print type.
void DIType::dump() const {
if (isNull()) return;
- std::string Res;
- if (!getName(Res).empty())
+ if (const char *Res = getName())
errs() << " [" << Res << "] ";
unsigned Tag = getTag();
@@ -351,14 +473,14 @@ void DIType::dump() const {
// TODO : Print context
getCompileUnit().dump();
- errs() << " ["
- << getLineNumber() << ", "
+ errs() << " ["
+ << getLineNumber() << ", "
<< getSizeInBits() << ", "
<< getAlignInBits() << ", "
- << getOffsetInBits()
+ << getOffsetInBits()
<< "] ";
- if (isPrivate())
+ if (isPrivate())
errs() << " [private] ";
else if (isProtected())
errs() << " [protected] ";
@@ -366,11 +488,11 @@ void DIType::dump() const {
if (isForwardDecl())
errs() << " [fwd] ";
- if (isBasicType(Tag))
+ if (isBasicType())
DIBasicType(DbgNode).dump();
- else if (isDerivedType(Tag))
+ else if (isDerivedType())
DIDerivedType(DbgNode).dump();
- else if (isCompositeType(Tag))
+ else if (isCompositeType())
DICompositeType(DbgNode).dump();
else {
errs() << "Invalid DIType\n";
@@ -400,8 +522,7 @@ void DICompositeType::dump() const {
/// dump - Print global.
void DIGlobal::dump() const {
- std::string Res;
- if (!getName(Res).empty())
+ if (const char *Res = getName())
errs() << " [" << Res << "] ";
unsigned Tag = getTag();
@@ -417,7 +538,7 @@ void DIGlobal::dump() const {
if (isDefinition())
errs() << " [def] ";
- if (isGlobalVariable(Tag))
+ if (isGlobalVariable())
DIGlobalVariable(DbgNode).dump();
errs() << "\n";
@@ -425,7 +546,23 @@ void DIGlobal::dump() const {
/// dump - Print subprogram.
void DISubprogram::dump() const {
- DIGlobal::dump();
+ if (const char *Res = getName())
+ errs() << " [" << Res << "] ";
+
+ unsigned Tag = getTag();
+ errs() << " [" << dwarf::TagString(Tag) << "] ";
+
+ // TODO : Print context
+ getCompileUnit().dump();
+ errs() << " [" << getLineNumber() << "] ";
+
+ if (isLocalToUnit())
+ errs() << " [local] ";
+
+ if (isDefinition())
+ errs() << " [def] ";
+
+ errs() << "\n";
}
/// dump - Print global variable.
@@ -437,14 +574,15 @@ void DIGlobalVariable::dump() const {
/// dump - Print variable.
void DIVariable::dump() const {
- std::string Res;
- if (!getName(Res).empty())
+ if (const char *Res = getName())
errs() << " [" << Res << "] ";
getCompileUnit().dump();
errs() << " [" << getLineNumber() << "] ";
getType().dump();
errs() << "\n";
+
+ // FIXME: Dump complex addresses
}
//===----------------------------------------------------------------------===//
@@ -452,7 +590,7 @@ void DIVariable::dump() const {
//===----------------------------------------------------------------------===//
DIFactory::DIFactory(Module &m)
- : M(m), VMContext(M.getContext()), StopPointFn(0), FuncStartFn(0),
+ : M(m), VMContext(M.getContext()), StopPointFn(0), FuncStartFn(0),
RegionStartFn(0), RegionEndFn(0),
DeclareFn(0) {
EmptyStructPtr = PointerType::getUnqual(StructType::get(VMContext));
@@ -468,11 +606,11 @@ Constant *DIFactory::GetTagConstant(unsigned TAG) {
// DIFactory: Primary Constructors
//===----------------------------------------------------------------------===//
-/// GetOrCreateArray - Create an descriptor for an array of descriptors.
+/// GetOrCreateArray - Create an descriptor for an array of descriptors.
/// This implicitly uniques the arrays created.
DIArray DIFactory::GetOrCreateArray(DIDescriptor *Tys, unsigned NumTys) {
SmallVector<Value*, 16> Elts;
-
+
if (NumTys == 0)
Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)));
else
@@ -490,7 +628,7 @@ DISubrange DIFactory::GetOrCreateSubrange(int64_t Lo, int64_t Hi) {
ConstantInt::get(Type::getInt64Ty(VMContext), Lo),
ConstantInt::get(Type::getInt64Ty(VMContext), Hi)
};
-
+
return DISubrange(MDNode::get(VMContext, &Elts[0], 3));
}
@@ -499,9 +637,9 @@ DISubrange DIFactory::GetOrCreateSubrange(int64_t Lo, int64_t Hi) {
/// CreateCompileUnit - Create a new descriptor for the specified compile
/// unit. Note that this does not unique compile units within the module.
DICompileUnit DIFactory::CreateCompileUnit(unsigned LangID,
- const std::string &Filename,
- const std::string &Directory,
- const std::string &Producer,
+ StringRef Filename,
+ StringRef Directory,
+ StringRef Producer,
bool isMain,
bool isOptimized,
const char *Flags,
@@ -523,7 +661,7 @@ DICompileUnit DIFactory::CreateCompileUnit(unsigned LangID,
}
/// CreateEnumerator - Create a single enumerator value.
-DIEnumerator DIFactory::CreateEnumerator(const std::string &Name, uint64_t Val){
+DIEnumerator DIFactory::CreateEnumerator(StringRef Name, uint64_t Val){
Value *Elts[] = {
GetTagConstant(dwarf::DW_TAG_enumerator),
MDString::get(VMContext, Name),
@@ -535,7 +673,7 @@ DIEnumerator DIFactory::CreateEnumerator(const std::string &Name, uint64_t Val){
/// CreateBasicType - Create a basic type like int, float, etc.
DIBasicType DIFactory::CreateBasicType(DIDescriptor Context,
- const std::string &Name,
+ StringRef Name,
DICompileUnit CompileUnit,
unsigned LineNumber,
uint64_t SizeInBits,
@@ -561,7 +699,7 @@ DIBasicType DIFactory::CreateBasicType(DIDescriptor Context,
/// pointer, typedef, etc.
DIDerivedType DIFactory::CreateDerivedType(unsigned Tag,
DIDescriptor Context,
- const std::string &Name,
+ StringRef Name,
DICompileUnit CompileUnit,
unsigned LineNumber,
uint64_t SizeInBits,
@@ -587,7 +725,7 @@ DIDerivedType DIFactory::CreateDerivedType(unsigned Tag,
/// CreateCompositeType - Create a composite type like array, struct, etc.
DICompositeType DIFactory::CreateCompositeType(unsigned Tag,
DIDescriptor Context,
- const std::string &Name,
+ StringRef Name,
DICompileUnit CompileUnit,
unsigned LineNumber,
uint64_t SizeInBits,
@@ -619,10 +757,10 @@ DICompositeType DIFactory::CreateCompositeType(unsigned Tag,
/// CreateSubprogram - Create a new descriptor for the specified subprogram.
/// See comments in DISubprogram for descriptions of these fields. This
/// method does not unique the generated descriptors.
-DISubprogram DIFactory::CreateSubprogram(DIDescriptor Context,
- const std::string &Name,
- const std::string &DisplayName,
- const std::string &LinkageName,
+DISubprogram DIFactory::CreateSubprogram(DIDescriptor Context,
+ StringRef Name,
+ StringRef DisplayName,
+ StringRef LinkageName,
DICompileUnit CompileUnit,
unsigned LineNo, DIType Type,
bool isLocalToUnit,
@@ -646,13 +784,13 @@ DISubprogram DIFactory::CreateSubprogram(DIDescriptor Context,
/// CreateGlobalVariable - Create a new descriptor for the specified global.
DIGlobalVariable
-DIFactory::CreateGlobalVariable(DIDescriptor Context, const std::string &Name,
- const std::string &DisplayName,
- const std::string &LinkageName,
+DIFactory::CreateGlobalVariable(DIDescriptor Context, StringRef Name,
+ StringRef DisplayName,
+ StringRef LinkageName,
DICompileUnit CompileUnit,
unsigned LineNo, DIType Type,bool isLocalToUnit,
bool isDefinition, llvm::GlobalVariable *Val) {
- Value *Elts[] = {
+ Value *Elts[] = {
GetTagConstant(dwarf::DW_TAG_variable),
llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
Context.getNode(),
@@ -680,7 +818,7 @@ DIFactory::CreateGlobalVariable(DIDescriptor Context, const std::string &Name,
/// CreateVariable - Create a new descriptor for the specified variable.
DIVariable DIFactory::CreateVariable(unsigned Tag, DIDescriptor Context,
- const std::string &Name,
+ StringRef Name,
DICompileUnit CompileUnit, unsigned LineNo,
DIType Type) {
Value *Elts[] = {
@@ -695,14 +833,46 @@ DIVariable DIFactory::CreateVariable(unsigned Tag, DIDescriptor Context,
}
+/// CreateComplexVariable - Create a new descriptor for the specified variable
+/// which has a complex address expression for its address.
+DIVariable DIFactory::CreateComplexVariable(unsigned Tag, DIDescriptor Context,
+ const std::string &Name,
+ DICompileUnit CompileUnit,
+ unsigned LineNo,
+ DIType Type, SmallVector<Value *, 9> &addr) {
+ SmallVector<Value *, 9> Elts;
+ Elts.push_back(GetTagConstant(Tag));
+ Elts.push_back(Context.getNode());
+ Elts.push_back(MDString::get(VMContext, Name));
+ Elts.push_back(CompileUnit.getNode());
+ Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), LineNo));
+ Elts.push_back(Type.getNode());
+ Elts.insert(Elts.end(), addr.begin(), addr.end());
+
+ return DIVariable(MDNode::get(VMContext, &Elts[0], 6+addr.size()));
+}
+
+
/// CreateBlock - This creates a descriptor for a lexical block with the
/// specified parent VMContext.
-DIBlock DIFactory::CreateBlock(DIDescriptor Context) {
+DILexicalBlock DIFactory::CreateLexicalBlock(DIDescriptor Context) {
Value *Elts[] = {
GetTagConstant(dwarf::DW_TAG_lexical_block),
Context.getNode()
};
- return DIBlock(MDNode::get(VMContext, &Elts[0], 2));
+ return DILexicalBlock(MDNode::get(VMContext, &Elts[0], 2));
+}
+
+/// CreateLocation - Creates a debug info location.
+DILocation DIFactory::CreateLocation(unsigned LineNo, unsigned ColumnNo,
+ DIScope S, DILocation OrigLoc) {
+ Value *Elts[] = {
+ ConstantInt::get(Type::getInt32Ty(VMContext), LineNo),
+ ConstantInt::get(Type::getInt32Ty(VMContext), ColumnNo),
+ S.getNode(),
+ OrigLoc.getNode(),
+ };
+ return DILocation(MDNode::get(VMContext, &Elts[0], 4));
}
@@ -714,12 +884,12 @@ DIBlock DIFactory::CreateBlock(DIDescriptor Context) {
/// inserting it at the end of the specified basic block.
void DIFactory::InsertStopPoint(DICompileUnit CU, unsigned LineNo,
unsigned ColNo, BasicBlock *BB) {
-
+
// Lazily construct llvm.dbg.stoppoint function.
if (!StopPointFn)
- StopPointFn = llvm::Intrinsic::getDeclaration(&M,
+ StopPointFn = llvm::Intrinsic::getDeclaration(&M,
llvm::Intrinsic::dbg_stoppoint);
-
+
// Invoke llvm.dbg.stoppoint
Value *Args[] = {
ConstantInt::get(llvm::Type::getInt32Ty(VMContext), LineNo),
@@ -735,7 +905,7 @@ void DIFactory::InsertSubprogramStart(DISubprogram SP, BasicBlock *BB) {
// Lazily construct llvm.dbg.func.start.
if (!FuncStartFn)
FuncStartFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_func_start);
-
+
// Call llvm.dbg.func.start which also implicitly sets a stoppoint.
CallInst::Create(FuncStartFn, SP.getNode(), "", BB);
}
@@ -763,15 +933,29 @@ void DIFactory::InsertRegionEnd(DIDescriptor D, BasicBlock *BB) {
}
/// InsertDeclare - Insert a new llvm.dbg.declare intrinsic call.
-void DIFactory::InsertDeclare(Value *Storage, DIVariable D, BasicBlock *BB) {
+void DIFactory::InsertDeclare(Value *Storage, DIVariable D,
+ Instruction *InsertBefore) {
+ // Cast the storage to a {}* for the call to llvm.dbg.declare.
+ Storage = new BitCastInst(Storage, EmptyStructPtr, "", InsertBefore);
+
+ if (!DeclareFn)
+ DeclareFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_declare);
+
+ Value *Args[] = { Storage, D.getNode() };
+ CallInst::Create(DeclareFn, Args, Args+2, "", InsertBefore);
+}
+
+/// InsertDeclare - Insert a new llvm.dbg.declare intrinsic call.
+void DIFactory::InsertDeclare(Value *Storage, DIVariable D,
+ BasicBlock *InsertAtEnd) {
// Cast the storage to a {}* for the call to llvm.dbg.declare.
- Storage = new BitCastInst(Storage, EmptyStructPtr, "", BB);
-
+ Storage = new BitCastInst(Storage, EmptyStructPtr, "", InsertAtEnd);
+
if (!DeclareFn)
DeclareFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_declare);
Value *Args[] = { Storage, D.getNode() };
- CallInst::Create(DeclareFn, Args, Args+2, "", BB);
+ CallInst::Create(DeclareFn, Args, Args+2, "", InsertAtEnd);
}
@@ -782,7 +966,6 @@ void DIFactory::InsertDeclare(Value *Storage, DIVariable D, BasicBlock *BB) {
/// processModule - Process entire module and collect debug info.
void DebugInfoFinder::processModule(Module &M) {
-
for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
for (Function::iterator FI = (*I).begin(), FE = (*I).end(); FI != FE; ++FI)
for (BasicBlock::iterator BI = (*FI).begin(), BE = (*FI).end(); BI != BE;
@@ -811,14 +994,14 @@ void DebugInfoFinder::processModule(Module &M) {
}
}
}
-
+
/// processType - Process DIType.
void DebugInfoFinder::processType(DIType DT) {
if (!addType(DT))
return;
addCompileUnit(DT.getCompileUnit());
- if (DT.isCompositeType(DT.getTag())) {
+ if (DT.isCompositeType()) {
DICompositeType DCT(DT.getNode());
processType(DCT.getTypeDerivedFrom());
DIArray DA = DCT.getTypeArray();
@@ -828,12 +1011,12 @@ void DebugInfoFinder::processType(DIType DT) {
DIType TypeE = DIType(D.getNode());
if (!TypeE.isNull())
processType(TypeE);
- else
+ else
processSubprogram(DISubprogram(D.getNode()));
}
- } else if (DT.isDerivedType(DT.getTag())) {
+ } else if (DT.isDerivedType()) {
DIDerivedType DDT(DT.getNode());
- if (!DDT.isNull())
+ if (!DDT.isNull())
processType(DDT.getTypeDerivedFrom());
}
}
@@ -908,7 +1091,7 @@ bool DebugInfoFinder::addCompileUnit(DICompileUnit CU) {
CUs.push_back(CU.getNode());
return true;
}
-
+
/// addGlobalVariable - Add global variable into GVs.
bool DebugInfoFinder::addGlobalVariable(DIGlobalVariable DIG) {
if (DIG.isNull())
@@ -925,7 +1108,7 @@ bool DebugInfoFinder::addGlobalVariable(DIGlobalVariable DIG) {
bool DebugInfoFinder::addSubprogram(DISubprogram SP) {
if (SP.isNull())
return false;
-
+
if (!NodesSeen.insert(SP.getNode()))
return false;
@@ -985,7 +1168,7 @@ namespace llvm {
NamedMDNode *NMD = M->getNamedMetadata("llvm.dbg.gv");
if (!NMD)
return 0;
-
+
for (unsigned i = 0, e = NMD->getNumElements(); i != e; ++i) {
DIGlobalVariable DIG(cast_or_null<MDNode>(NMD->getElement(i)));
if (DIG.isNull())
@@ -1020,8 +1203,8 @@ namespace llvm {
return 0;
}
- bool getLocationInfo(const Value *V, std::string &DisplayName,
- std::string &Type, unsigned &LineNo, std::string &File,
+bool getLocationInfo(const Value *V, std::string &DisplayName,
+ std::string &Type, unsigned &LineNo, std::string &File,
std::string &Dir) {
DICompileUnit Unit;
DIType TypeD;
@@ -1031,7 +1214,8 @@ namespace llvm {
if (!DIGV) return false;
DIGlobalVariable Var(cast<MDNode>(DIGV));
- Var.getDisplayName(DisplayName);
+ if (const char *D = Var.getDisplayName())
+ DisplayName = D;
LineNo = Var.getLineNumber();
Unit = Var.getCompileUnit();
TypeD = Var.getType();
@@ -1040,40 +1224,44 @@ namespace llvm {
if (!DDI) return false;
DIVariable Var(cast<MDNode>(DDI->getVariable()));
- Var.getName(DisplayName);
+ if (const char *D = Var.getName())
+ DisplayName = D;
LineNo = Var.getLineNumber();
Unit = Var.getCompileUnit();
TypeD = Var.getType();
}
- TypeD.getName(Type);
- Unit.getFilename(File);
- Unit.getDirectory(Dir);
+ if (const char *T = TypeD.getName())
+ Type = T;
+ if (const char *F = Unit.getFilename())
+ File = F;
+ if (const char *D = Unit.getDirectory())
+ Dir = D;
return true;
}
- /// isValidDebugInfoIntrinsic - Return true if SPI is a valid debug
+ /// isValidDebugInfoIntrinsic - Return true if SPI is a valid debug
/// info intrinsic.
- bool isValidDebugInfoIntrinsic(DbgStopPointInst &SPI,
+ bool isValidDebugInfoIntrinsic(DbgStopPointInst &SPI,
CodeGenOpt::Level OptLev) {
return DIDescriptor::ValidDebugInfo(SPI.getContext(), OptLev);
}
- /// isValidDebugInfoIntrinsic - Return true if FSI is a valid debug
+ /// isValidDebugInfoIntrinsic - Return true if FSI is a valid debug
/// info intrinsic.
bool isValidDebugInfoIntrinsic(DbgFuncStartInst &FSI,
CodeGenOpt::Level OptLev) {
return DIDescriptor::ValidDebugInfo(FSI.getSubprogram(), OptLev);
}
- /// isValidDebugInfoIntrinsic - Return true if RSI is a valid debug
+ /// isValidDebugInfoIntrinsic - Return true if RSI is a valid debug
/// info intrinsic.
bool isValidDebugInfoIntrinsic(DbgRegionStartInst &RSI,
CodeGenOpt::Level OptLev) {
return DIDescriptor::ValidDebugInfo(RSI.getContext(), OptLev);
}
- /// isValidDebugInfoIntrinsic - Return true if REI is a valid debug
+ /// isValidDebugInfoIntrinsic - Return true if REI is a valid debug
/// info intrinsic.
bool isValidDebugInfoIntrinsic(DbgRegionEndInst &REI,
CodeGenOpt::Level OptLev) {
@@ -1081,14 +1269,14 @@ namespace llvm {
}
- /// isValidDebugInfoIntrinsic - Return true if DI is a valid debug
+ /// isValidDebugInfoIntrinsic - Return true if DI is a valid debug
/// info intrinsic.
bool isValidDebugInfoIntrinsic(DbgDeclareInst &DI,
CodeGenOpt::Level OptLev) {
return DIDescriptor::ValidDebugInfo(DI.getVariable(), OptLev);
}
- /// ExtractDebugLocation - Extract debug location information
+ /// ExtractDebugLocation - Extract debug location information
/// from llvm.dbg.stoppoint intrinsic.
DebugLoc ExtractDebugLocation(DbgStopPointInst &SPI,
DebugLocTracker &DebugLocInfo) {
@@ -1096,7 +1284,7 @@ namespace llvm {
Value *Context = SPI.getContext();
// If this location is already tracked then use it.
- DebugLocTuple Tuple(cast<MDNode>(Context), SPI.getLine(),
+ DebugLocTuple Tuple(cast<MDNode>(Context), NULL, SPI.getLine(),
SPI.getColumn());
DenseMap<DebugLocTuple, unsigned>::iterator II
= DebugLocInfo.DebugIdMap.find(Tuple);
@@ -1107,11 +1295,36 @@ namespace llvm {
unsigned Id = DebugLocInfo.DebugLocations.size();
DebugLocInfo.DebugLocations.push_back(Tuple);
DebugLocInfo.DebugIdMap[Tuple] = Id;
-
+
+ return DebugLoc::get(Id);
+ }
+
+ /// ExtractDebugLocation - Extract debug location information
+ /// from DILocation.
+ DebugLoc ExtractDebugLocation(DILocation &Loc,
+ DebugLocTracker &DebugLocInfo) {
+ DebugLoc DL;
+ MDNode *Context = Loc.getScope().getNode();
+ MDNode *InlinedLoc = NULL;
+ if (!Loc.getOrigLocation().isNull())
+ InlinedLoc = Loc.getOrigLocation().getNode();
+ // If this location is already tracked then use it.
+ DebugLocTuple Tuple(Context, InlinedLoc, Loc.getLineNumber(),
+ Loc.getColumnNumber());
+ DenseMap<DebugLocTuple, unsigned>::iterator II
+ = DebugLocInfo.DebugIdMap.find(Tuple);
+ if (II != DebugLocInfo.DebugIdMap.end())
+ return DebugLoc::get(II->second);
+
+ // Add a new location entry.
+ unsigned Id = DebugLocInfo.DebugLocations.size();
+ DebugLocInfo.DebugLocations.push_back(Tuple);
+ DebugLocInfo.DebugIdMap[Tuple] = Id;
+
return DebugLoc::get(Id);
}
- /// ExtractDebugLocation - Extract debug location information
+ /// ExtractDebugLocation - Extract debug location information
/// from llvm.dbg.func_start intrinsic.
DebugLoc ExtractDebugLocation(DbgFuncStartInst &FSI,
DebugLocTracker &DebugLocInfo) {
@@ -1123,7 +1336,7 @@ namespace llvm {
DICompileUnit CU(Subprogram.getCompileUnit());
// If this location is already tracked then use it.
- DebugLocTuple Tuple(CU.getNode(), Line, /* Column */ 0);
+ DebugLocTuple Tuple(CU.getNode(), NULL, Line, /* Column */ 0);
DenseMap<DebugLocTuple, unsigned>::iterator II
= DebugLocInfo.DebugIdMap.find(Tuple);
if (II != DebugLocInfo.DebugIdMap.end())
@@ -1133,7 +1346,7 @@ namespace llvm {
unsigned Id = DebugLocInfo.DebugLocations.size();
DebugLocInfo.DebugLocations.push_back(Tuple);
DebugLocInfo.DebugIdMap[Tuple] = Id;
-
+
return DebugLoc::get(Id);
}
diff --git a/libclamav/c++/llvm/lib/Analysis/IPA/Andersens.cpp b/libclamav/c++/llvm/lib/Analysis/IPA/Andersens.cpp
index 9de1fcc..1c9159d 100644
--- a/libclamav/c++/llvm/lib/Analysis/IPA/Andersens.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/IPA/Andersens.cpp
@@ -64,6 +64,7 @@
#include "llvm/Support/InstIterator.h"
#include "llvm/Support/InstVisitor.h"
#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/MallocHelper.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/Support/Debug.h"
#include "llvm/System/Atomic.h"
@@ -592,9 +593,12 @@ namespace {
friend class InstVisitor<Andersens>;
void visitReturnInst(ReturnInst &RI);
void visitInvokeInst(InvokeInst &II) { visitCallSite(CallSite(&II)); }
- void visitCallInst(CallInst &CI) { visitCallSite(CallSite(&CI)); }
+ void visitCallInst(CallInst &CI) {
+ if (isMalloc(&CI)) visitAllocationInst(CI);
+ else visitCallSite(CallSite(&CI));
+ }
void visitCallSite(CallSite CS);
- void visitAllocationInst(AllocationInst &AI);
+ void visitAllocationInst(Instruction &I);
void visitLoadInst(LoadInst &LI);
void visitStoreInst(StoreInst &SI);
void visitGetElementPtrInst(GetElementPtrInst &GEP);
@@ -790,6 +794,8 @@ void Andersens::IdentifyObjects(Module &M) {
ValueNodes[&*II] = NumObjects++;
if (AllocationInst *AI = dyn_cast<AllocationInst>(&*II))
ObjectNodes[AI] = NumObjects++;
+ else if (isMalloc(&*II))
+ ObjectNodes[&*II] = NumObjects++;
}
// Calls to inline asm need to be added as well because the callee isn't
@@ -1161,10 +1167,10 @@ void Andersens::visitInstruction(Instruction &I) {
}
}
-void Andersens::visitAllocationInst(AllocationInst &AI) {
- unsigned ObjectIndex = getObject(&AI);
- GraphNodes[ObjectIndex].setValue(&AI);
- Constraints.push_back(Constraint(Constraint::AddressOf, getNodeValue(AI),
+void Andersens::visitAllocationInst(Instruction &I) {
+ unsigned ObjectIndex = getObject(&I);
+ GraphNodes[ObjectIndex].setValue(&I);
+ Constraints.push_back(Constraint(Constraint::AddressOf, getNodeValue(I),
ObjectIndex));
}
@@ -2813,7 +2819,7 @@ void Andersens::PrintNode(const Node *N) const {
else
errs() << "(unnamed)";
- if (isa<GlobalValue>(V) || isa<AllocationInst>(V))
+ if (isa<GlobalValue>(V) || isa<AllocationInst>(V) || isMalloc(V))
if (N == &GraphNodes[getObject(V)])
errs() << "<mem>";
}
diff --git a/libclamav/c++/llvm/lib/Analysis/IPA/CallGraph.cpp b/libclamav/c++/llvm/lib/Analysis/IPA/CallGraph.cpp
index 5757bfd..e2b288d 100644
--- a/libclamav/c++/llvm/lib/Analysis/IPA/CallGraph.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/IPA/CallGraph.cpp
@@ -241,7 +241,7 @@ void CallGraphNode::dump() const { print(errs()); }
void CallGraphNode::removeCallEdgeFor(CallSite CS) {
for (CalledFunctionsVector::iterator I = CalledFunctions.begin(); ; ++I) {
assert(I != CalledFunctions.end() && "Cannot find callsite to remove!");
- if (I->first == CS) {
+ if (I->first == CS.getInstruction()) {
I->second->DropRef();
*I = CalledFunctions.back();
CalledFunctions.pop_back();
@@ -250,21 +250,6 @@ void CallGraphNode::removeCallEdgeFor(CallSite CS) {
}
}
-// FIXME: REMOVE THIS WHEN HACK IS REMOVED FROM CGSCCPASSMGR.
-void CallGraphNode::removeCallEdgeFor(Instruction *CS) {
- for (CalledFunctionsVector::iterator I = CalledFunctions.begin(); ; ++I) {
- assert(I != CalledFunctions.end() && "Cannot find callsite to remove!");
- if (I->first.getInstruction() == CS) {
- I->second->DropRef();
- *I = CalledFunctions.back();
- CalledFunctions.pop_back();
- return;
- }
- }
-
-}
-
-
// removeAnyCallEdgeTo - This method removes any call edges from this node to
// the specified callee function. This takes more time to execute than
@@ -285,7 +270,7 @@ void CallGraphNode::removeOneAbstractEdgeTo(CallGraphNode *Callee) {
for (CalledFunctionsVector::iterator I = CalledFunctions.begin(); ; ++I) {
assert(I != CalledFunctions.end() && "Cannot find callee to remove!");
CallRecord &CR = *I;
- if (CR.second == Callee && CR.first.getInstruction() == 0) {
+ if (CR.second == Callee && CR.first == 0) {
Callee->DropRef();
*I = CalledFunctions.back();
CalledFunctions.pop_back();
@@ -294,25 +279,20 @@ void CallGraphNode::removeOneAbstractEdgeTo(CallGraphNode *Callee) {
}
}
-/// replaceCallSite - Make the edge in the node for Old CallSite be for
-/// New CallSite instead. Note that this method takes linear time, so it
-/// should be used sparingly.
-void CallGraphNode::replaceCallSite(CallSite Old, CallSite New,
- CallGraphNode *NewCallee) {
+/// replaceCallEdge - This method replaces the edge in the node for the
+/// specified call site with a new one. Note that this method takes linear
+/// time, so it should be used sparingly.
+void CallGraphNode::replaceCallEdge(CallSite CS,
+ CallSite NewCS, CallGraphNode *NewNode){
for (CalledFunctionsVector::iterator I = CalledFunctions.begin(); ; ++I) {
- assert(I != CalledFunctions.end() && "Cannot find callsite to replace!");
- if (I->first != Old) continue;
-
- I->first = New;
-
- // If the callee is changing, not just the callsite, then update it as
- // well.
- if (NewCallee) {
+ assert(I != CalledFunctions.end() && "Cannot find callsite to remove!");
+ if (I->first == CS.getInstruction()) {
I->second->DropRef();
- I->second = NewCallee;
- I->second->AddRef();
+ I->first = NewCS.getInstruction();
+ I->second = NewNode;
+ NewNode->AddRef();
+ return;
}
- return;
}
}
diff --git a/libclamav/c++/llvm/lib/Analysis/IPA/CallGraphSCCPass.cpp b/libclamav/c++/llvm/lib/Analysis/IPA/CallGraphSCCPass.cpp
index 2d5600d..a96a5c5 100644
--- a/libclamav/c++/llvm/lib/Analysis/IPA/CallGraphSCCPass.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/IPA/CallGraphSCCPass.cpp
@@ -22,13 +22,14 @@
#include "llvm/PassManagers.h"
#include "llvm/Function.h"
#include "llvm/Support/Debug.h"
+#include "llvm/IntrinsicInst.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
// CGPassManager
//
-/// CGPassManager manages FPPassManagers and CalLGraphSCCPasses.
+/// CGPassManager manages FPPassManagers and CallGraphSCCPasses.
namespace {
@@ -78,7 +79,8 @@ public:
private:
bool RunPassOnSCC(Pass *P, std::vector<CallGraphNode*> &CurSCC,
CallGraph &CG, bool &CallGraphUpToDate);
- void RefreshCallGraph(std::vector<CallGraphNode*> &CurSCC, CallGraph &CG);
+ void RefreshCallGraph(std::vector<CallGraphNode*> &CurSCC, CallGraph &CG,
+ bool IsCheckingMode);
};
} // end anonymous namespace.
@@ -90,17 +92,24 @@ bool CGPassManager::RunPassOnSCC(Pass *P, std::vector<CallGraphNode*> &CurSCC,
bool Changed = false;
if (CallGraphSCCPass *CGSP = dynamic_cast<CallGraphSCCPass*>(P)) {
if (!CallGraphUpToDate) {
- RefreshCallGraph(CurSCC, CG);
+ RefreshCallGraph(CurSCC, CG, false);
CallGraphUpToDate = true;
}
-
- StartPassTimer(P);
+
+ Timer *T = StartPassTimer(CGSP);
Changed = CGSP->runOnSCC(CurSCC);
- StopPassTimer(P);
+ StopPassTimer(CGSP, T);
+
+ // After the CGSCCPass is done, when assertions are enabled, use
+ // RefreshCallGraph to verify that the callgraph was correctly updated.
+#ifndef NDEBUG
+ if (Changed)
+ RefreshCallGraph(CurSCC, CG, true);
+#endif
+
return Changed;
}
- StartPassTimer(P);
FPPassManager *FPP = dynamic_cast<FPPassManager *>(P);
assert(FPP && "Invalid CGPassManager member");
@@ -108,10 +117,11 @@ bool CGPassManager::RunPassOnSCC(Pass *P, std::vector<CallGraphNode*> &CurSCC,
for (unsigned i = 0, e = CurSCC.size(); i != e; ++i) {
if (Function *F = CurSCC[i]->getFunction()) {
dumpPassInfo(P, EXECUTION_MSG, ON_FUNCTION_MSG, F->getName());
+ Timer *T = StartPassTimer(FPP);
Changed |= FPP->runOnFunction(*F);
+ StopPassTimer(FPP, T);
}
}
- StopPassTimer(P);
// The function pass(es) modified the IR, they may have clobbered the
// callgraph.
@@ -123,9 +133,15 @@ bool CGPassManager::RunPassOnSCC(Pass *P, std::vector<CallGraphNode*> &CurSCC,
return Changed;
}
+
+/// RefreshCallGraph - Scan the functions in the specified CFG and resync the
+/// callgraph with the call sites found in it. This is used after
+/// FunctionPasses have potentially munged the callgraph, and can be used after
+/// CallGraphSCC passes to verify that they correctly updated the callgraph.
+///
void CGPassManager::RefreshCallGraph(std::vector<CallGraphNode*> &CurSCC,
- CallGraph &CG) {
- DenseMap<Instruction*, CallGraphNode*> CallSites;
+ CallGraph &CG, bool CheckingMode) {
+ DenseMap<Value*, CallGraphNode*> CallSites;
DEBUG(errs() << "CGSCCPASSMGR: Refreshing SCC with " << CurSCC.size()
<< " nodes:\n";
@@ -145,24 +161,51 @@ void CGPassManager::RefreshCallGraph(std::vector<CallGraphNode*> &CurSCC,
// CGN with those actually in the function.
// Get the set of call sites currently in the function.
- for (CallGraphNode::iterator I = CGN->begin(), E = CGN->end(); I != E; ++I){
- assert(I->first.getInstruction() &&
- "Call site record in function should not be abstract");
- assert(!CallSites.count(I->first.getInstruction()) &&
+ for (CallGraphNode::iterator I = CGN->begin(), E = CGN->end(); I != E; ) {
+ // If this call site is null, then the function pass deleted the call
+ // entirely and the WeakVH nulled it out.
+ if (I->first == 0 ||
+ // If we've already seen this call site, then the FunctionPass RAUW'd
+ // one call with another, which resulted in two "uses" in the edge
+ // list of the same call.
+ CallSites.count(I->first) ||
+
+ // If the call edge is not from a call or invoke, then the function
+ // pass RAUW'd a call with another value. This can happen when
+ // constant folding happens of well known functions etc.
+ CallSite::get(I->first).getInstruction() == 0) {
+ assert(!CheckingMode &&
+ "CallGraphSCCPass did not update the CallGraph correctly!");
+
+ // Just remove the edge from the set of callees, keep track of whether
+ // I points to the last element of the vector.
+ bool WasLast = I + 1 == E;
+ CGN->removeCallEdge(I);
+
+ // If I pointed to the last element of the vector, we have to bail out:
+ // iterator checking rejects comparisons of the resultant pointer with
+ // end.
+ if (WasLast)
+ break;
+ E = CGN->end();
+ continue;
+ }
+
+ assert(!CallSites.count(I->first) &&
"Call site occurs in node multiple times");
- CallSites.insert(std::make_pair(I->first.getInstruction(),
- I->second));
+ CallSites.insert(std::make_pair(I->first, I->second));
+ ++I;
}
// Loop over all of the instructions in the function, getting the callsites.
for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB)
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
CallSite CS = CallSite::get(I);
- if (!CS.getInstruction()) continue;
+ if (!CS.getInstruction() || isa<DbgInfoIntrinsic>(I)) continue;
// If this call site already existed in the callgraph, just verify it
// matches up to expectations and remove it from CallSites.
- DenseMap<Instruction*, CallGraphNode*>::iterator ExistingIt =
+ DenseMap<Value*, CallGraphNode*>::iterator ExistingIt =
CallSites.find(CS.getInstruction());
if (ExistingIt != CallSites.end()) {
CallGraphNode *ExistingNode = ExistingIt->second;
@@ -174,6 +217,18 @@ void CGPassManager::RefreshCallGraph(std::vector<CallGraphNode*> &CurSCC,
if (ExistingNode->getFunction() == CS.getCalledFunction())
continue;
+ // If we are in checking mode, we are not allowed to actually mutate
+ // the callgraph. If this is a case where we can infer that the
+ // callgraph is less precise than it could be (e.g. an indirect call
+ // site could be turned direct), don't reject it in checking mode, and
+ // don't tweak it to be more precise.
+ if (CheckingMode && CS.getCalledFunction() &&
+ ExistingNode->getFunction() == 0)
+ continue;
+
+ assert(!CheckingMode &&
+ "CallGraphSCCPass did not update the CallGraph correctly!");
+
// If not, we either went from a direct call to indirect, indirect to
// direct, or direct to different direct.
CallGraphNode *CalleeNode;
@@ -181,12 +236,22 @@ void CGPassManager::RefreshCallGraph(std::vector<CallGraphNode*> &CurSCC,
CalleeNode = CG.getOrInsertFunction(Callee);
else
CalleeNode = CG.getCallsExternalNode();
-
- CGN->replaceCallSite(CS, CS, CalleeNode);
+
+ // Update the edge target in CGN.
+ for (CallGraphNode::iterator I = CGN->begin(); ; ++I) {
+ assert(I != CGN->end() && "Didn't find call entry");
+ if (I->first == CS.getInstruction()) {
+ I->second = CalleeNode;
+ break;
+ }
+ }
MadeChange = true;
continue;
}
+ assert(!CheckingMode &&
+ "CallGraphSCCPass did not update the CallGraph correctly!");
+
// If the call site didn't exist in the CGN yet, add it. We assume that
// newly introduced call sites won't be indirect. This could be fixed
// in the future.
@@ -201,18 +266,14 @@ void CGPassManager::RefreshCallGraph(std::vector<CallGraphNode*> &CurSCC,
}
// After scanning this function, if we still have entries in callsites, then
- // they are dangling pointers. Crap. Well, until we change CallGraph to
- // use CallbackVH, we'll just zap them here. When we have that, this should
- // turn into an assertion.
- if (CallSites.empty()) continue;
+ // they are dangling pointers. WeakVH should save us for this, so abort if
+ // this happens.
+ assert(CallSites.empty() && "Dangling pointers found in call sites map");
- for (DenseMap<Instruction*, CallGraphNode*>::iterator I = CallSites.begin(),
- E = CallSites.end(); I != E; ++I)
- // FIXME: I had to add a special horrible form of removeCallEdgeFor to
- // support this. Remove the Instruction* version of it when we can.
- CGN->removeCallEdgeFor(I->first);
- MadeChange = true;
- CallSites.clear();
+ // Periodically do an explicit clear to remove tombstones when processing
+ // large scc's.
+ if ((sccidx & 15) == 0)
+ CallSites.clear();
}
DEBUG(if (MadeChange) {
@@ -256,7 +317,20 @@ bool CGPassManager::runOnModule(Module &M) {
PassNo != e; ++PassNo) {
Pass *P = getContainedPass(PassNo);
- dumpPassInfo(P, EXECUTION_MSG, ON_CG_MSG, "");
+ // If we're in -debug-pass=Executions mode, construct the SCC node list,
+ // otherwise avoid constructing this string as it is expensive.
+ if (isPassDebuggingExecutionsOrMore()) {
+ std::string Functions;
+#ifndef NDEBUG
+ raw_string_ostream OS(Functions);
+ for (unsigned i = 0, e = CurSCC.size(); i != e; ++i) {
+ if (i) OS << ", ";
+ CurSCC[i]->print(OS);
+ }
+ OS.flush();
+#endif
+ dumpPassInfo(P, EXECUTION_MSG, ON_CG_MSG, Functions);
+ }
dumpRequiredSet(P);
initializeAnalysisImpl(P);
@@ -277,7 +351,7 @@ bool CGPassManager::runOnModule(Module &M) {
// If the callgraph was left out of date (because the last pass run was a
// functionpass), refresh it before we move on to the next SCC.
if (!CallGraphUpToDate)
- RefreshCallGraph(CurSCC, CG);
+ RefreshCallGraph(CurSCC, CG, false);
}
Changed |= doFinalization(CG);
return Changed;
diff --git a/libclamav/c++/llvm/lib/Analysis/IPA/GlobalsModRef.cpp b/libclamav/c++/llvm/lib/Analysis/IPA/GlobalsModRef.cpp
index 2e9884a..f5c1108 100644
--- a/libclamav/c++/llvm/lib/Analysis/IPA/GlobalsModRef.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/IPA/GlobalsModRef.cpp
@@ -23,6 +23,7 @@
#include "llvm/DerivedTypes.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/CallGraph.h"
+#include "llvm/Analysis/MallocHelper.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/InstIterator.h"
@@ -236,6 +237,9 @@ bool GlobalsModRef::AnalyzeUsesOfPointer(Value *V,
}
} else if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(*UI)) {
if (AnalyzeUsesOfPointer(GEP, Readers, Writers)) return true;
+ } else if (BitCastInst *BCI = dyn_cast<BitCastInst>(*UI)) {
+ if (AnalyzeUsesOfPointer(BCI, Readers, Writers, OkayStoreDest))
+ return true;
} else if (CallInst *CI = dyn_cast<CallInst>(*UI)) {
// Make sure that this is just the function being called, not that it is
// passing into the function.
@@ -299,7 +303,7 @@ bool GlobalsModRef::AnalyzeIndirectGlobalMemory(GlobalValue *GV) {
// Check the value being stored.
Value *Ptr = SI->getOperand(0)->getUnderlyingObject();
- if (isa<MallocInst>(Ptr)) {
+ if (isa<MallocInst>(Ptr) || isMalloc(Ptr)) {
// Okay, easy case.
} else if (CallInst *CI = dyn_cast<CallInst>(Ptr)) {
Function *F = CI->getCalledFunction();
@@ -435,7 +439,8 @@ void GlobalsModRef::AnalyzeCallGraph(CallGraph &CG, Module &M) {
if (cast<StoreInst>(*II).isVolatile())
// Treat volatile stores as reading memory somewhere.
FunctionEffect |= Ref;
- } else if (isa<MallocInst>(*II) || isa<FreeInst>(*II)) {
+ } else if (isa<MallocInst>(*II) || isa<FreeInst>(*II) ||
+ isMalloc(&cast<Instruction>(*II))) {
FunctionEffect |= ModRef;
}
diff --git a/libclamav/c++/llvm/lib/Analysis/IVUsers.cpp b/libclamav/c++/llvm/lib/Analysis/IVUsers.cpp
index 927740b..543e017 100644
--- a/libclamav/c++/llvm/lib/Analysis/IVUsers.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/IVUsers.cpp
@@ -19,7 +19,6 @@
#include "llvm/Type.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Analysis/Dominators.h"
-#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/LoopPass.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
#include "llvm/ADT/STLExtras.h"
@@ -122,11 +121,11 @@ static bool getSCEVStartAndStride(const SCEV *&SH, Loop *L, Loop *UseLoop,
Start = SE->getAddExpr(Start, AddRecStart);
- // If stride is an instruction, make sure it dominates the loop preheader.
+ // If stride is an instruction, make sure it properly dominates the header.
// Otherwise we could end up with a use before def situation.
if (!isa<SCEVConstant>(AddRecStride)) {
- BasicBlock *Preheader = L->getLoopPreheader();
- if (!AddRecStride->dominates(Preheader, DT))
+ BasicBlock *Header = L->getHeader();
+ if (!AddRecStride->properlyDominates(Header, DT))
return false;
DEBUG(errs() << "[" << L->getHeader()->getName()
diff --git a/libclamav/c++/llvm/lib/Analysis/LoopInfo.cpp b/libclamav/c++/llvm/lib/Analysis/LoopInfo.cpp
index 2526480..ce2d29f 100644
--- a/libclamav/c++/llvm/lib/Analysis/LoopInfo.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/LoopInfo.cpp
@@ -20,11 +20,22 @@
#include "llvm/Analysis/Dominators.h"
#include "llvm/Assembly/Writer.h"
#include "llvm/Support/CFG.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/SmallPtrSet.h"
#include <algorithm>
using namespace llvm;
+// Always verify loopinfo if expensive checking is enabled.
+#ifdef XDEBUG
+bool VerifyLoopInfo = true;
+#else
+bool VerifyLoopInfo = false;
+#endif
+static cl::opt<bool,true>
+VerifyLoopInfoX("verify-loop-info", cl::location(VerifyLoopInfo),
+ cl::desc("Verify loop info (time consuming)"));
+
char LoopInfo::ID = 0;
static RegisterPass<LoopInfo>
X("loops", "Natural Loop Information", true, true);
@@ -294,6 +305,77 @@ bool Loop::isLoopSimplifyForm() const {
return true;
}
+/// getUniqueExitBlocks - Return all unique successor blocks of this loop.
+/// These are the blocks _outside of the current loop_ which are branched to.
+/// This assumes that loop is in canonical form.
+///
+void
+Loop::getUniqueExitBlocks(SmallVectorImpl<BasicBlock *> &ExitBlocks) const {
+ assert(isLoopSimplifyForm() &&
+ "getUniqueExitBlocks assumes the loop is in canonical form!");
+
+ // Sort the blocks vector so that we can use binary search to do quick
+ // lookups.
+ SmallVector<BasicBlock *, 128> LoopBBs(block_begin(), block_end());
+ std::sort(LoopBBs.begin(), LoopBBs.end());
+
+ SmallVector<BasicBlock *, 32> switchExitBlocks;
+
+ for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++BI) {
+
+ BasicBlock *current = *BI;
+ switchExitBlocks.clear();
+
+ typedef GraphTraits<BasicBlock *> BlockTraits;
+ typedef GraphTraits<Inverse<BasicBlock *> > InvBlockTraits;
+ for (BlockTraits::ChildIteratorType I =
+ BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);
+ I != E; ++I) {
+ // If block is inside the loop then it is not a exit block.
+ if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I))
+ continue;
+
+ InvBlockTraits::ChildIteratorType PI = InvBlockTraits::child_begin(*I);
+ BasicBlock *firstPred = *PI;
+
+ // If current basic block is this exit block's first predecessor
+ // then only insert exit block in to the output ExitBlocks vector.
+ // This ensures that same exit block is not inserted twice into
+ // ExitBlocks vector.
+ if (current != firstPred)
+ continue;
+
+ // If a terminator has more then two successors, for example SwitchInst,
+ // then it is possible that there are multiple edges from current block
+ // to one exit block.
+ if (std::distance(BlockTraits::child_begin(current),
+ BlockTraits::child_end(current)) <= 2) {
+ ExitBlocks.push_back(*I);
+ continue;
+ }
+
+ // In case of multiple edges from current block to exit block, collect
+ // only one edge in ExitBlocks. Use switchExitBlocks to keep track of
+ // duplicate edges.
+ if (std::find(switchExitBlocks.begin(), switchExitBlocks.end(), *I)
+ == switchExitBlocks.end()) {
+ switchExitBlocks.push_back(*I);
+ ExitBlocks.push_back(*I);
+ }
+ }
+ }
+}
+
+/// getUniqueExitBlock - If getUniqueExitBlocks would return exactly one
+/// block, return that block. Otherwise return null.
+BasicBlock *Loop::getUniqueExitBlock() const {
+ SmallVector<BasicBlock *, 8> UniqueExitBlocks;
+ getUniqueExitBlocks(UniqueExitBlocks);
+ if (UniqueExitBlocks.size() == 1)
+ return UniqueExitBlocks[0];
+ return 0;
+}
+
//===----------------------------------------------------------------------===//
// LoopInfo implementation
//
@@ -303,6 +385,23 @@ bool LoopInfo::runOnFunction(Function &) {
return false;
}
+void LoopInfo::verifyAnalysis() const {
+ // LoopInfo is a FunctionPass, but verifying every loop in the function
+ // each time verifyAnalysis is called is very expensive. The
+ // -verify-loop-info option can enable this. In order to perform some
+ // checking by default, LoopPass has been taught to call verifyLoop
+ // manually during loop pass sequences.
+
+ if (!VerifyLoopInfo) return;
+
+ for (iterator I = begin(), E = end(); I != E; ++I) {
+ assert(!(*I)->getParentLoop() && "Top-level loop has a parent!");
+ (*I)->verifyLoopNest();
+ }
+
+ // TODO: check BBMap consistency.
+}
+
void LoopInfo::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
AU.addRequired<DominatorTree>();
diff --git a/libclamav/c++/llvm/lib/Analysis/LoopPass.cpp b/libclamav/c++/llvm/lib/Analysis/LoopPass.cpp
index 0007ade..43463cd 100644
--- a/libclamav/c++/llvm/lib/Analysis/LoopPass.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/LoopPass.cpp
@@ -21,7 +21,6 @@ using namespace llvm;
//
char LPPassManager::ID = 0;
-/// LPPassManager manages FPPassManagers and CalLGraphSCCPasses.
LPPassManager::LPPassManager(int Depth)
: FunctionPass(&ID), PMDataManager(Depth) {
@@ -111,17 +110,21 @@ void LPPassManager::insertLoop(Loop *L, Loop *ParentLoop) {
else
LI->addTopLevelLoop(L);
+ insertLoopIntoQueue(L);
+}
+
+void LPPassManager::insertLoopIntoQueue(Loop *L) {
// Insert L into loop queue
if (L == CurrentLoop)
redoLoop(L);
- else if (!ParentLoop)
+ else if (!L->getParentLoop())
// This is top level loop.
LQ.push_front(L);
else {
- // Insert L after ParentLoop
+ // Insert L after the parent loop.
for (std::deque<Loop *>::iterator I = LQ.begin(),
E = LQ.end(); I != E; ++I) {
- if (*I == ParentLoop) {
+ if (*I == L->getParentLoop()) {
// deque does not support insert after.
++I;
LQ.insert(I, 1, L);
@@ -217,41 +220,66 @@ bool LPPassManager::runOnFunction(Function &F) {
skipThisLoop = false;
redoThisLoop = false;
- // Run all passes on current SCC
+ // Run all passes on the current Loop.
for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
Pass *P = getContainedPass(Index);
- dumpPassInfo(P, EXECUTION_MSG, ON_LOOP_MSG, "");
+ dumpPassInfo(P, EXECUTION_MSG, ON_LOOP_MSG,
+ CurrentLoop->getHeader()->getNameStr());
dumpRequiredSet(P);
initializeAnalysisImpl(P);
LoopPass *LP = dynamic_cast<LoopPass *>(P);
+ assert(LP && "Invalid LPPassManager member");
{
PassManagerPrettyStackEntry X(LP, *CurrentLoop->getHeader());
- StartPassTimer(P);
- assert(LP && "Invalid LPPassManager member");
+ Timer *T = StartPassTimer(P);
Changed |= LP->runOnLoop(CurrentLoop, *this);
- StopPassTimer(P);
+ StopPassTimer(P, T);
}
if (Changed)
- dumpPassInfo(P, MODIFICATION_MSG, ON_LOOP_MSG, "");
+ dumpPassInfo(P, MODIFICATION_MSG, ON_LOOP_MSG,
+ skipThisLoop ? "<deleted>" :
+ CurrentLoop->getHeader()->getNameStr());
dumpPreservedSet(P);
- verifyPreservedAnalysis(LP);
+ if (!skipThisLoop) {
+ // Manually check that this loop is still healthy. This is done
+ // instead of relying on LoopInfo::verifyLoop since LoopInfo
+ // is a function pass and it's really expensive to verify every
+ // loop in the function every time. That level of checking can be
+ // enabled with the -verify-loop-info option.
+ Timer *T = StartPassTimer(LI);
+ CurrentLoop->verifyLoop();
+ StopPassTimer(LI, T);
+
+ // Then call the regular verifyAnalysis functions.
+ verifyPreservedAnalysis(LP);
+ }
+
removeNotPreservedAnalysis(P);
recordAvailableAnalysis(P);
- removeDeadPasses(P, "", ON_LOOP_MSG);
-
- // If dominator information is available then verify the info if requested.
- verifyDomInfo(*LP, F);
+ removeDeadPasses(P,
+ skipThisLoop ? "<deleted>" :
+ CurrentLoop->getHeader()->getNameStr(),
+ ON_LOOP_MSG);
if (skipThisLoop)
// Do not run other passes on this loop.
break;
}
+ // If the loop was deleted, release all the loop passes. This frees up
+ // some memory, and avoids trouble with the pass manager trying to call
+ // verifyAnalysis on them.
+ if (skipThisLoop)
+ for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
+ Pass *P = getContainedPass(Index);
+ freePass(P, "<deleted>", ON_LOOP_MSG);
+ }
+
// Pop the loop from queue after running all passes.
LQ.pop_back();
diff --git a/libclamav/c++/llvm/lib/Analysis/MallocHelper.cpp b/libclamav/c++/llvm/lib/Analysis/MallocHelper.cpp
new file mode 100644
index 0000000..ab6239e
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Analysis/MallocHelper.cpp
@@ -0,0 +1,218 @@
+//===-- MallocHelper.cpp - Functions to identify malloc calls -------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This family of functions identifies calls to malloc, bitcasts of malloc
+// calls, and the types and array sizes associated with them.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Analysis/MallocHelper.h"
+#include "llvm/Constants.h"
+#include "llvm/Instructions.h"
+#include "llvm/Module.h"
+#include "llvm/Analysis/ConstantFolding.h"
+using namespace llvm;
+
+//===----------------------------------------------------------------------===//
+// malloc Call Utility Functions.
+//
+
+/// isMalloc - Returns true if the the value is either a malloc call or a
+/// bitcast of the result of a malloc call.
+bool llvm::isMalloc(const Value* I) {
+ return extractMallocCall(I) || extractMallocCallFromBitCast(I);
+}
+
+static bool isMallocCall(const CallInst *CI) {
+ if (!CI)
+ return false;
+
+ const Module* M = CI->getParent()->getParent()->getParent();
+ Constant *MallocFunc = M->getFunction("malloc");
+
+ if (CI->getOperand(0) != MallocFunc)
+ return false;
+
+ return true;
+}
+
+/// extractMallocCall - Returns the corresponding CallInst if the instruction
+/// is a malloc call. Since CallInst::CreateMalloc() only creates calls, we
+/// ignore InvokeInst here.
+const CallInst* llvm::extractMallocCall(const Value* I) {
+ const CallInst *CI = dyn_cast<CallInst>(I);
+ return (isMallocCall(CI)) ? CI : NULL;
+}
+
+CallInst* llvm::extractMallocCall(Value* I) {
+ CallInst *CI = dyn_cast<CallInst>(I);
+ return (isMallocCall(CI)) ? CI : NULL;
+}
+
+static bool isBitCastOfMallocCall(const BitCastInst* BCI) {
+ if (!BCI)
+ return false;
+
+ return isMallocCall(dyn_cast<CallInst>(BCI->getOperand(0)));
+}
+
+/// extractMallocCallFromBitCast - Returns the corresponding CallInst if the
+/// instruction is a bitcast of the result of a malloc call.
+CallInst* llvm::extractMallocCallFromBitCast(Value* I) {
+ BitCastInst *BCI = dyn_cast<BitCastInst>(I);
+ return (isBitCastOfMallocCall(BCI)) ? cast<CallInst>(BCI->getOperand(0))
+ : NULL;
+}
+
+const CallInst* llvm::extractMallocCallFromBitCast(const Value* I) {
+ const BitCastInst *BCI = dyn_cast<BitCastInst>(I);
+ return (isBitCastOfMallocCall(BCI)) ? cast<CallInst>(BCI->getOperand(0))
+ : NULL;
+}
+
+static bool isArrayMallocHelper(const CallInst *CI, LLVMContext &Context,
+ const TargetData* TD) {
+ if (!CI)
+ return false;
+
+ const Type* T = getMallocAllocatedType(CI);
+
+ // We can only indentify an array malloc if we know the type of the malloc
+ // call.
+ if (!T) return false;
+
+ Value* MallocArg = CI->getOperand(1);
+ Constant *ElementSize = ConstantExpr::getSizeOf(T);
+ ElementSize = ConstantExpr::getTruncOrBitCast(ElementSize,
+ MallocArg->getType());
+ Constant *FoldedElementSize = ConstantFoldConstantExpression(
+ cast<ConstantExpr>(ElementSize),
+ Context, TD);
+
+
+ if (isa<ConstantExpr>(MallocArg))
+ return (MallocArg != ElementSize);
+
+ BinaryOperator *BI = dyn_cast<BinaryOperator>(MallocArg);
+ if (!BI)
+ return false;
+
+ if (BI->getOpcode() == Instruction::Mul)
+ // ArraySize * ElementSize
+ if (BI->getOperand(1) == ElementSize ||
+ (FoldedElementSize && BI->getOperand(1) == FoldedElementSize))
+ return true;
+
+ // TODO: Detect case where MallocArg mul has been transformed to shl.
+
+ return false;
+}
+
+/// isArrayMalloc - Returns the corresponding CallInst if the instruction
+/// matches the malloc call IR generated by CallInst::CreateMalloc(). This
+/// means that it is a malloc call with one bitcast use AND the malloc call's
+/// size argument is:
+/// 1. a constant not equal to the malloc's allocated type
+/// or
+/// 2. the result of a multiplication by the malloc's allocated type
+/// Otherwise it returns NULL.
+/// The unique bitcast is needed to determine the type/size of the array
+/// allocation.
+CallInst* llvm::isArrayMalloc(Value* I, LLVMContext &Context,
+ const TargetData* TD) {
+ CallInst *CI = extractMallocCall(I);
+ return (isArrayMallocHelper(CI, Context, TD)) ? CI : NULL;
+}
+
+const CallInst* llvm::isArrayMalloc(const Value* I, LLVMContext &Context,
+ const TargetData* TD) {
+ const CallInst *CI = extractMallocCall(I);
+ return (isArrayMallocHelper(CI, Context, TD)) ? CI : NULL;
+}
+
+/// getMallocType - Returns the PointerType resulting from the malloc call.
+/// This PointerType is the result type of the call's only bitcast use.
+/// If there is no unique bitcast use, then return NULL.
+const PointerType* llvm::getMallocType(const CallInst* CI) {
+ assert(isMalloc(CI) && "GetMallocType and not malloc call");
+
+ const BitCastInst* BCI = NULL;
+
+ // Determine if CallInst has a bitcast use.
+ for (Value::use_const_iterator UI = CI->use_begin(), E = CI->use_end();
+ UI != E; )
+ if ((BCI = dyn_cast<BitCastInst>(cast<Instruction>(*UI++))))
+ break;
+
+ // Malloc call has 1 bitcast use and no other uses, so type is the bitcast's
+ // destination type.
+ if (BCI && CI->hasOneUse())
+ return cast<PointerType>(BCI->getDestTy());
+
+ // Malloc call was not bitcast, so type is the malloc function's return type.
+ if (!BCI)
+ return cast<PointerType>(CI->getType());
+
+ // Type could not be determined.
+ return NULL;
+}
+
+/// getMallocAllocatedType - Returns the Type allocated by malloc call. This
+/// Type is the result type of the call's only bitcast use. If there is no
+/// unique bitcast use, then return NULL.
+const Type* llvm::getMallocAllocatedType(const CallInst* CI) {
+ const PointerType* PT = getMallocType(CI);
+ return PT ? PT->getElementType() : NULL;
+}
+
+/// isConstantOne - Return true only if val is constant int 1.
+static bool isConstantOne(Value *val) {
+ return isa<ConstantInt>(val) && cast<ConstantInt>(val)->isOne();
+}
+
+/// getMallocArraySize - Returns the array size of a malloc call. The array
+/// size is computated in 1 of 3 ways:
+/// 1. If the element type if of size 1, then array size is the argument to
+/// malloc.
+/// 2. Else if the malloc's argument is a constant, the array size is that
+/// argument divided by the element type's size.
+/// 3. Else the malloc argument must be a multiplication and the array size is
+/// the first operand of the multiplication.
+/// This function returns constant 1 if:
+/// 1. The malloc call's allocated type cannot be determined.
+/// 2. IR wasn't created by a call to CallInst::CreateMalloc() with a non-NULL
+/// ArraySize.
+Value* llvm::getMallocArraySize(CallInst* CI, LLVMContext &Context,
+ const TargetData* TD) {
+ // Match CreateMalloc's use of constant 1 array-size for non-array mallocs.
+ if (!isArrayMalloc(CI, Context, TD))
+ return ConstantInt::get(CI->getOperand(1)->getType(), 1);
+
+ Value* MallocArg = CI->getOperand(1);
+ assert(getMallocAllocatedType(CI) && "getMallocArraySize and no type");
+ Constant *ElementSize = ConstantExpr::getSizeOf(getMallocAllocatedType(CI));
+ ElementSize = ConstantExpr::getTruncOrBitCast(ElementSize,
+ MallocArg->getType());
+
+ Constant* CO = dyn_cast<Constant>(MallocArg);
+ BinaryOperator* BO = dyn_cast<BinaryOperator>(MallocArg);
+ assert((isConstantOne(ElementSize) || CO || BO) &&
+ "getMallocArraySize and malformed malloc IR");
+
+ if (isConstantOne(ElementSize))
+ return MallocArg;
+
+ if (CO)
+ return CO->getOperand(0);
+
+ // TODO: Detect case where MallocArg mul has been transformed to shl.
+
+ assert(BO && "getMallocArraySize not constant but not multiplication either");
+ return BO->getOperand(0);
+}
diff --git a/libclamav/c++/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp b/libclamav/c++/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
index 2ac101e..97b791c 100644
--- a/libclamav/c++/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
@@ -20,6 +20,7 @@
#include "llvm/IntrinsicInst.h"
#include "llvm/Function.h"
#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/MallocHelper.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/PredIteratorCache.h"
@@ -233,6 +234,15 @@ getPointerDependencyFrom(Value *MemPtr, uint64_t MemSize, bool isLoad,
continue;
}
+ if (isMalloc(Inst)) {
+ Value *AccessPtr = MemPtr->getUnderlyingObject();
+
+ if (AccessPtr == Inst ||
+ AA->alias(Inst, 1, AccessPtr, 1) == AliasAnalysis::MustAlias)
+ return MemDepResult::getDef(Inst);
+ continue;
+ }
+
// See if this instruction (e.g. a call or vaarg) mod/ref's the pointer.
switch (AA->getModRefInfo(Inst, MemPtr, MemSize)) {
case AliasAnalysis::NoModRef:
diff --git a/libclamav/c++/llvm/lib/Analysis/PointerTracking.cpp b/libclamav/c++/llvm/lib/Analysis/PointerTracking.cpp
index e098647..2281836 100644
--- a/libclamav/c++/llvm/lib/Analysis/PointerTracking.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/PointerTracking.cpp
@@ -13,6 +13,7 @@
#include "llvm/Analysis/ConstantFolding.h"
#include "llvm/Analysis/Dominators.h"
#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/MallocHelper.h"
#include "llvm/Analysis/PointerTracking.h"
#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
@@ -99,6 +100,14 @@ const SCEV *PointerTracking::computeAllocationCount(Value *P,
return SE->getSCEV(arraySize);
}
+ if (CallInst *CI = extractMallocCall(V)) {
+ Value *arraySize = getMallocArraySize(CI, P->getContext(), TD);
+ Ty = getMallocAllocatedType(CI);
+ if (!Ty || !arraySize) return SE->getCouldNotCompute();
+ // arraySize elements of type Ty.
+ return SE->getSCEV(arraySize);
+ }
+
if (GlobalVariable *GV = dyn_cast<GlobalVariable>(V)) {
if (GV->hasDefinitiveInitializer()) {
Constant *C = GV->getInitializer();
diff --git a/libclamav/c++/llvm/lib/Analysis/ProfileEstimatorPass.cpp b/libclamav/c++/llvm/lib/Analysis/ProfileEstimatorPass.cpp
index 8f5313f..c585c1d 100644
--- a/libclamav/c++/llvm/lib/Analysis/ProfileEstimatorPass.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/ProfileEstimatorPass.cpp
@@ -34,7 +34,7 @@ namespace {
public FunctionPass, public ProfileInfo {
double ExecCount;
LoopInfo *LI;
- std::set<BasicBlock*> BBisVisited;
+ std::set<BasicBlock*> BBToVisit;
std::map<Loop*,double> LoopExitWeights;
public:
static char ID; // Class identification, replacement for typeinfo
@@ -86,9 +86,8 @@ static double ignoreMissing(double w) {
return w;
}
-static void inline printEdgeError(BasicBlock *V1, BasicBlock *V2) {
- DEBUG(errs() << "-- Edge (" <<(V1)->getName() << "," << (V2)->getName() \
- << ") is not calculated, returning\n");
+static void inline printEdgeError(ProfileInfo::Edge e, const char *M) {
+ DEBUG(errs() << "-- Edge " << e << " is not calculated, " << M << "\n");
}
void inline ProfileEstimatorPass::printEdgeWeight(Edge E) {
@@ -98,30 +97,44 @@ void inline ProfileEstimatorPass::printEdgeWeight(Edge E) {
// recurseBasicBlock() - This calculates the ProfileInfo estimation for a
// single block and then recurses into the successors.
+// The algorithm preserves the flow condition, meaning that the sum of the
+// weight of the incoming edges must be equal the block weight which must in
+// turn be equal to the sume of the weights of the outgoing edges.
+// Since the flow of an block is deterimined from the current state of the
+// flow, once an edge has a flow assigned this flow is never changed again,
+// otherwise it would be possible to violate the flow condition in another
+// block.
void ProfileEstimatorPass::recurseBasicBlock(BasicBlock *BB) {
// Break the recursion if this BasicBlock was already visited.
- if (BBisVisited.find(BB) != BBisVisited.end()) return;
+ if (BBToVisit.find(BB) == BBToVisit.end()) return;
- // Check if incoming edges are calculated already, if BB is header allow
- // backedges that are uncalculated for now.
+ // Read the LoopInfo for this block.
bool BBisHeader = LI->isLoopHeader(BB);
Loop* BBLoop = LI->getLoopFor(BB);
+ // To get the block weight, read all incoming edges.
double BBWeight = 0;
std::set<BasicBlock*> ProcessedPreds;
for ( pred_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
bbi != bbe; ++bbi ) {
+ // If this block was not considered already, add weight.
+ Edge edge = getEdge(*bbi,BB);
+ double w = getEdgeWeight(edge);
if (ProcessedPreds.insert(*bbi).second) {
- Edge edge = getEdge(*bbi,BB);
- BBWeight += ignoreMissing(getEdgeWeight(edge));
+ BBWeight += ignoreMissing(w);
}
- if (BBisHeader && BBLoop == LI->getLoopFor(*bbi)) {
- printEdgeError(*bbi,BB);
+ // If this block is a loop header and the predecessor is contained in this
+ // loop, thus the edge is a backedge, continue and do not check if the
+ // value is valid.
+ if (BBisHeader && BBLoop->contains(*bbi)) {
+ printEdgeError(edge, "but is backedge, continueing");
continue;
}
- if (BBisVisited.find(*bbi) == BBisVisited.end()) {
- printEdgeError(*bbi,BB);
+ // If the edges value is missing (and this is no loop header, and this is
+ // no backedge) return, this block is currently non estimatable.
+ if (w == MissingValue) {
+ printEdgeError(edge, "returning");
return;
}
}
@@ -136,20 +149,47 @@ void ProfileEstimatorPass::recurseBasicBlock(BasicBlock *BB) {
BBLoop->getExitEdges(ExitEdges);
}
- // If block is an loop header, first subtract all weights from edges that
- // exit this loop, then distribute remaining weight on to the edges exiting
- // this loop. Finally the weight of the block is increased, to simulate
- // several executions of this loop.
+ // If this is a loop header, consider the following:
+ // Exactly the flow that is entering this block, must exit this block too. So
+ // do the following:
+ // *) get all the exit edges, read the flow that is already leaving this
+ // loop, remember the edges that do not have any flow on them right now.
+ // (The edges that have already flow on them are most likely exiting edges of
+ // other loops, do not touch those flows because the previously caclulated
+ // loopheaders would not be exact anymore.)
+ // *) In case there is not a single exiting edge left, create one at the loop
+ // latch to prevent the flow from building up in the loop.
+ // *) Take the flow that is not leaving the loop already and distribute it on
+ // the remaining exiting edges.
+ // (This ensures that all flow that enters the loop also leaves it.)
+ // *) Increase the flow into the loop by increasing the weight of this block.
+ // There is at least one incoming backedge that will bring us this flow later
+ // on. (So that the flow condition in this node is valid again.)
if (BBisHeader) {
double incoming = BBWeight;
// Subtract the flow leaving the loop.
+ std::set<Edge> ProcessedExits;
for (SmallVector<Edge, 8>::iterator ei = ExitEdges.begin(),
ee = ExitEdges.end(); ei != ee; ++ei) {
- double w = getEdgeWeight(*ei);
- if (w == MissingValue) {
- Edges.push_back(*ei);
- } else {
- incoming -= w;
+ if (ProcessedExits.insert(*ei).second) {
+ double w = getEdgeWeight(*ei);
+ if (w == MissingValue) {
+ Edges.push_back(*ei);
+ } else {
+ incoming -= w;
+ }
+ }
+ }
+ // If no exit edges, create one:
+ if (Edges.size() == 0) {
+ BasicBlock *Latch = BBLoop->getLoopLatch();
+ if (Latch) {
+ Edge edge = getEdge(Latch,0);
+ EdgeInformation[BB->getParent()][edge] = BBWeight;
+ printEdgeWeight(edge);
+ edge = getEdge(Latch, BB);
+ EdgeInformation[BB->getParent()][edge] = BBWeight * ExecCount;
+ printEdgeWeight(edge);
}
}
// Distribute remaining weight onto the exit edges.
@@ -162,15 +202,23 @@ void ProfileEstimatorPass::recurseBasicBlock(BasicBlock *BB) {
BBWeight *= (ExecCount+1);
}
- // Remove from current flow of block all the successor edges that already
- // have some flow on them.
+ BlockInformation[BB->getParent()][BB] = BBWeight;
+ // Up until now we considered only the loop exiting edges, now we have a
+ // definite block weight and must ditribute this onto the outgoing edges.
+ // Since there may be already flow attached to some of the edges, read this
+ // flow first and remember the edges that have still now flow attached.
Edges.clear();
std::set<BasicBlock*> ProcessedSuccs;
- // Otherwise consider weight of outgoing edges and store them for
- // distribution of remaining weight.
- for ( succ_iterator bbi = succ_begin(BB), bbe = succ_end(BB);
- bbi != bbe; ++bbi ) {
+ succ_iterator bbi = succ_begin(BB), bbe = succ_end(BB);
+ // Also check for (BB,0) edges that may already contain some flow. (But only
+ // in case there are no successors.)
+ if (bbi == bbe) {
+ Edge edge = getEdge(BB,0);
+ EdgeInformation[BB->getParent()][edge] = BBWeight;
+ printEdgeWeight(edge);
+ }
+ for ( ; bbi != bbe; ++bbi ) {
if (ProcessedSuccs.insert(*bbi).second) {
Edge edge = getEdge(BB,*bbi);
double w = getEdgeWeight(edge);
@@ -182,18 +230,20 @@ void ProfileEstimatorPass::recurseBasicBlock(BasicBlock *BB) {
}
}
- // Distribute remaining flow onto the outgoing edges.
+ // Finally we know what flow is still not leaving the block, distribute this
+ // flow onto the empty edges.
for (SmallVector<Edge, 8>::iterator ei = Edges.begin(), ee = Edges.end();
ei != ee; ++ei) {
EdgeInformation[BB->getParent()][*ei] += BBWeight/Edges.size();
printEdgeWeight(*ei);
}
- // Mark this Block visited and recurse into successors.
- BBisVisited.insert(BB);
- for ( succ_iterator bbi = succ_begin(BB), bbe = succ_end(BB);
- bbi != bbe;
- ++bbi ) {
+ // This block is visited, mark this before the recursion.
+ BBToVisit.erase(BB);
+
+ // Recurse into successors.
+ for (succ_iterator bbi = succ_begin(BB), bbe = succ_end(BB);
+ bbi != bbe; ++bbi) {
recurseBasicBlock(*bbi);
}
}
@@ -201,11 +251,15 @@ void ProfileEstimatorPass::recurseBasicBlock(BasicBlock *BB) {
bool ProfileEstimatorPass::runOnFunction(Function &F) {
if (F.isDeclaration()) return false;
+ // Fetch LoopInfo and clear ProfileInfo for this function.
LI = &getAnalysis<LoopInfo>();
FunctionInformation.erase(&F);
BlockInformation[&F].clear();
EdgeInformation[&F].clear();
- BBisVisited.clear();
+
+ // Mark all blocks as to visit.
+ for (Function::iterator bi = F.begin(), be = F.end(); bi != be; ++bi)
+ BBToVisit.insert(bi);
DEBUG(errs() << "Working on function " << F.getNameStr() << "\n");
@@ -213,29 +267,41 @@ bool ProfileEstimatorPass::runOnFunction(Function &F) {
// (0,entry) is inserted with the starting weight of 1.
BasicBlock *entry = &F.getEntryBlock();
BlockInformation[&F][entry] = 1;
-
Edge edge = getEdge(0,entry);
- EdgeInformation[&F][edge] = 1; printEdgeWeight(edge);
+ EdgeInformation[&F][edge] = 1;
+ printEdgeWeight(edge);
+
+ // Since recurseBasicBlock() maybe returns with a block which was not fully
+ // estimated, use recurseBasicBlock() until everything is calculated.
recurseBasicBlock(entry);
+ while (BBToVisit.size() > 0) {
+ // Remember number of open blocks, this is later used to check if progress
+ // was made.
+ unsigned size = BBToVisit.size();
+
+ // Try to calculate all blocks in turn.
+ for (std::set<BasicBlock*>::iterator bi = BBToVisit.begin(),
+ be = BBToVisit.end(); bi != be; ++bi) {
+ recurseBasicBlock(*bi);
+ // If at least one block was finished, break because iterator may be
+ // invalid.
+ if (BBToVisit.size() < size) break;
+ }
- // In case something went wrong, clear all results, not profiling info is
- // available.
- if (BBisVisited.size() != F.size()) {
- DEBUG(errs() << "-- could not estimate profile, using default profile\n");
- FunctionInformation.erase(&F);
- BlockInformation[&F].clear();
- for (Function::iterator BB = F.begin(), BBE = F.end(); BB != BBE; ++BB) {
+ // If there was not a single block resovled, make some assumptions.
+ if (BBToVisit.size() == size) {
+ BasicBlock *BB = *(BBToVisit.begin());
+ // Since this BB was not calculated because of missing incoming edges,
+ // set these edges to zero.
for (pred_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
bbi != bbe; ++bbi) {
Edge e = getEdge(*bbi,BB);
- EdgeInformation[&F][e] = 1;
- printEdgeWeight(e);
- }
- for (succ_iterator bbi = succ_begin(BB), bbe = succ_end(BB);
- bbi != bbe; ++bbi) {
- Edge e = getEdge(BB,*bbi);
- EdgeInformation[&F][e] = 1;
- printEdgeWeight(e);
+ double w = getEdgeWeight(e);
+ if (w == MissingValue) {
+ EdgeInformation[&F][e] = 0;
+ DEBUG(errs() << "Assuming edge weight: ");
+ printEdgeWeight(e);
+ }
}
}
}
diff --git a/libclamav/c++/llvm/lib/Analysis/ProfileInfo.cpp b/libclamav/c++/llvm/lib/Analysis/ProfileInfo.cpp
index 55c5cab..9efdd23 100644
--- a/libclamav/c++/llvm/lib/Analysis/ProfileInfo.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/ProfileInfo.cpp
@@ -17,7 +17,9 @@
#include "llvm/Pass.h"
#include "llvm/Support/CFG.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/Format.h"
#include <set>
using namespace llvm;
@@ -82,6 +84,87 @@ double ProfileInfo::getExecutionCount(const Function *F) {
return Count;
}
+/// Replaces all occurences of RmBB in the ProfilingInfo with DestBB.
+/// This checks all edges of the function the blocks reside in and replaces the
+/// occurences of RmBB with DestBB.
+void ProfileInfo::replaceAllUses(const BasicBlock *RmBB,
+ const BasicBlock *DestBB) {
+ DEBUG(errs() << "Replacing " << RmBB->getNameStr()
+ << " with " << DestBB->getNameStr() << "\n");
+ const Function *F = DestBB->getParent();
+ std::map<const Function*, EdgeWeights>::iterator J =
+ EdgeInformation.find(F);
+ if (J == EdgeInformation.end()) return;
+
+ for (EdgeWeights::iterator I = J->second.begin(), E = J->second.end();
+ I != E; ++I) {
+ Edge e = I->first;
+ Edge newedge; bool foundedge = false;
+ if (e.first == RmBB) {
+ newedge = getEdge(DestBB, e.second);
+ foundedge = true;
+ }
+ if (e.second == RmBB) {
+ newedge = getEdge(e.first, DestBB);
+ foundedge = true;
+ }
+ if (foundedge) {
+ double w = getEdgeWeight(e);
+ EdgeInformation[F][newedge] = w;
+ DEBUG(errs() << "Replacing " << e << " with " << newedge << "\n");
+ J->second.erase(e);
+ }
+ }
+}
+
+/// Splits an edge in the ProfileInfo and redirects flow over NewBB.
+/// Since its possible that there is more than one edge in the CFG from FristBB
+/// to SecondBB its necessary to redirect the flow proporionally.
+void ProfileInfo::splitEdge(const BasicBlock *FirstBB,
+ const BasicBlock *SecondBB,
+ const BasicBlock *NewBB,
+ bool MergeIdenticalEdges) {
+ const Function *F = FirstBB->getParent();
+ std::map<const Function*, EdgeWeights>::iterator J =
+ EdgeInformation.find(F);
+ if (J == EdgeInformation.end()) return;
+
+ // Generate edges and read current weight.
+ Edge e = getEdge(FirstBB, SecondBB);
+ Edge n1 = getEdge(FirstBB, NewBB);
+ Edge n2 = getEdge(NewBB, SecondBB);
+ EdgeWeights &ECs = J->second;
+ double w = ECs[e];
+
+ int succ_count = 0;
+ if (!MergeIdenticalEdges) {
+ // First count the edges from FristBB to SecondBB, if there is more than
+ // one, only slice out a proporional part for NewBB.
+ for(succ_const_iterator BBI = succ_begin(FirstBB), BBE = succ_end(FirstBB);
+ BBI != BBE; ++BBI) {
+ if (*BBI == SecondBB) succ_count++;
+ }
+ // When the NewBB is completely new, increment the count by one so that
+ // the counts are properly distributed.
+ if (getExecutionCount(NewBB) == ProfileInfo::MissingValue) succ_count++;
+ } else {
+ // When the edges are merged anyway, then redirect all flow.
+ succ_count = 1;
+ }
+
+ // We know now how many edges there are from FirstBB to SecondBB, reroute a
+ // proportional part of the edge weight over NewBB.
+ double neww = w / succ_count;
+ ECs[n1] += neww;
+ ECs[n2] += neww;
+ BlockInformation[F][NewBB] += neww;
+ if (succ_count == 1) {
+ ECs.erase(e);
+ } else {
+ ECs[e] -= neww;
+ }
+}
+
raw_ostream& llvm::operator<<(raw_ostream &O, ProfileInfo::Edge E) {
O << "(";
O << (E.first ? E.first->getNameStr() : "0");
diff --git a/libclamav/c++/llvm/lib/Analysis/ProfileInfoLoader.cpp b/libclamav/c++/llvm/lib/Analysis/ProfileInfoLoader.cpp
index f0641cf..25481b2 100644
--- a/libclamav/c++/llvm/lib/Analysis/ProfileInfoLoader.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/ProfileInfoLoader.cpp
@@ -26,10 +26,17 @@ using namespace llvm;
//
static inline unsigned ByteSwap(unsigned Var, bool Really) {
if (!Really) return Var;
- return ((Var & (255<< 0)) << 24) |
- ((Var & (255<< 8)) << 8) |
- ((Var & (255<<16)) >> 8) |
- ((Var & (255<<24)) >> 24);
+ return ((Var & (255U<< 0U)) << 24U) |
+ ((Var & (255U<< 8U)) << 8U) |
+ ((Var & (255U<<16U)) >> 8U) |
+ ((Var & (255U<<24U)) >> 24U);
+}
+
+static unsigned AddCounts(unsigned A, unsigned B) {
+ // If either value is undefined, use the other.
+ if (A == ProfileInfoLoader::Uncounted) return B;
+ if (B == ProfileInfoLoader::Uncounted) return A;
+ return A + B;
}
static void ReadProfilingBlock(const char *ToolName, FILE *F,
@@ -54,20 +61,25 @@ static void ReadProfilingBlock(const char *ToolName, FILE *F,
exit(1);
}
- // Make sure we have enough space...
+ // Make sure we have enough space... The space is initialised to -1 to
+ // facitiltate the loading of missing values for OptimalEdgeProfiling.
if (Data.size() < NumEntries)
- Data.resize(NumEntries);
+ Data.resize(NumEntries, ProfileInfoLoader::Uncounted);
// Accumulate the data we just read into the data.
if (!ShouldByteSwap) {
- for (unsigned i = 0; i != NumEntries; ++i)
- Data[i] += TempSpace[i];
+ for (unsigned i = 0; i != NumEntries; ++i) {
+ Data[i] = AddCounts(TempSpace[i], Data[i]);
+ }
} else {
- for (unsigned i = 0; i != NumEntries; ++i)
- Data[i] += ByteSwap(TempSpace[i], true);
+ for (unsigned i = 0; i != NumEntries; ++i) {
+ Data[i] = AddCounts(ByteSwap(TempSpace[i], true), Data[i]);
+ }
}
}
+const unsigned ProfileInfoLoader::Uncounted = ~0U;
+
// ProfileInfoLoader ctor - Read the specified profiling data file, exiting the
// program if the file is invalid or broken.
//
@@ -127,6 +139,10 @@ ProfileInfoLoader::ProfileInfoLoader(const char *ToolName,
ReadProfilingBlock(ToolName, F, ShouldByteSwap, EdgeCounts);
break;
+ case OptEdgeInfo:
+ ReadProfilingBlock(ToolName, F, ShouldByteSwap, OptimalEdgeCounts);
+ break;
+
case BBTraceInfo:
ReadProfilingBlock(ToolName, F, ShouldByteSwap, BBTrace);
break;
diff --git a/libclamav/c++/llvm/lib/Analysis/ProfileInfoLoaderPass.cpp b/libclamav/c++/llvm/lib/Analysis/ProfileInfoLoaderPass.cpp
index 8a8683b..89d90bc 100644
--- a/libclamav/c++/llvm/lib/Analysis/ProfileInfoLoaderPass.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/ProfileInfoLoaderPass.cpp
@@ -11,7 +11,7 @@
// loads the information from a profile dump file.
//
//===----------------------------------------------------------------------===//
-
+#define DEBUG_TYPE "profile-loader"
#include "llvm/BasicBlock.h"
#include "llvm/InstrTypes.h"
#include "llvm/Module.h"
@@ -21,9 +21,17 @@
#include "llvm/Analysis/ProfileInfoLoader.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/CFG.h"
+#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/Format.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/SmallSet.h"
+#include <set>
using namespace llvm;
+STATISTIC(NumEdgesRead, "The # of edges read.");
+
static cl::opt<std::string>
ProfileInfoFilename("profile-info-file", cl::init("llvmprof.out"),
cl::value_desc("filename"),
@@ -32,6 +40,9 @@ ProfileInfoFilename("profile-info-file", cl::init("llvmprof.out"),
namespace {
class VISIBILITY_HIDDEN LoaderPass : public ModulePass, public ProfileInfo {
std::string Filename;
+ std::set<Edge> SpanningTree;
+ std::set<const BasicBlock*> BBisUnvisited;
+ unsigned ReadCount;
public:
static char ID; // Class identification, replacement for typeinfo
explicit LoaderPass(const std::string &filename = "")
@@ -47,6 +58,12 @@ namespace {
return "Profiling information loader";
}
+ // recurseBasicBlock() - Calculates the edge weights for as much basic
+ // blocks as possbile.
+ virtual void recurseBasicBlock(const BasicBlock *BB);
+ virtual void readEdgeOrRemember(Edge, Edge&, unsigned &, unsigned &);
+ virtual void readEdge(ProfileInfo::Edge, std::vector<unsigned>&);
+
/// run - Load the profile information from the specified file.
virtual bool runOnModule(Module &M);
};
@@ -67,62 +84,208 @@ Pass *llvm::createProfileLoaderPass(const std::string &Filename) {
return new LoaderPass(Filename);
}
+void LoaderPass::readEdgeOrRemember(Edge edge, Edge &tocalc,
+ unsigned &uncalc, unsigned &count) {
+ double w;
+ if ((w = getEdgeWeight(edge)) == MissingValue) {
+ tocalc = edge;
+ uncalc++;
+ } else {
+ count+=w;
+ }
+}
+
+// recurseBasicBlock - Visits all neighbours of a block and then tries to
+// calculate the missing edge values.
+void LoaderPass::recurseBasicBlock(const BasicBlock *BB) {
+
+ // break recursion if already visited
+ if (BBisUnvisited.find(BB) == BBisUnvisited.end()) return;
+ BBisUnvisited.erase(BB);
+ if (!BB) return;
+
+ for (succ_const_iterator bbi = succ_begin(BB), bbe = succ_end(BB);
+ bbi != bbe; ++bbi) {
+ recurseBasicBlock(*bbi);
+ }
+ for (pred_const_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
+ bbi != bbe; ++bbi) {
+ recurseBasicBlock(*bbi);
+ }
+
+ Edge edgetocalc;
+ unsigned uncalculated = 0;
+
+ // collect weights of all incoming and outgoing edges, rememer edges that
+ // have no value
+ unsigned incount = 0;
+ SmallSet<const BasicBlock*,8> pred_visited;
+ pred_const_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
+ if (bbi==bbe) {
+ readEdgeOrRemember(getEdge(0, BB),edgetocalc,uncalculated,incount);
+ }
+ for (;bbi != bbe; ++bbi) {
+ if (pred_visited.insert(*bbi)) {
+ readEdgeOrRemember(getEdge(*bbi, BB),edgetocalc,uncalculated,incount);
+ }
+ }
+
+ unsigned outcount = 0;
+ SmallSet<const BasicBlock*,8> succ_visited;
+ succ_const_iterator sbbi = succ_begin(BB), sbbe = succ_end(BB);
+ if (sbbi==sbbe) {
+ readEdgeOrRemember(getEdge(BB, 0),edgetocalc,uncalculated,outcount);
+ }
+ for (;sbbi != sbbe; ++sbbi) {
+ if (succ_visited.insert(*sbbi)) {
+ readEdgeOrRemember(getEdge(BB, *sbbi),edgetocalc,uncalculated,outcount);
+ }
+ }
+
+ // if exactly one edge weight was missing, calculate it and remove it from
+ // spanning tree
+ if (uncalculated == 1) {
+ if (incount < outcount) {
+ EdgeInformation[BB->getParent()][edgetocalc] = outcount-incount;
+ } else {
+ EdgeInformation[BB->getParent()][edgetocalc] = incount-outcount;
+ }
+ DEBUG(errs() << "--Calc Edge Counter for " << edgetocalc << ": "
+ << format("%g", getEdgeWeight(edgetocalc)) << "\n");
+ SpanningTree.erase(edgetocalc);
+ }
+}
+
+void LoaderPass::readEdge(ProfileInfo::Edge e,
+ std::vector<unsigned> &ECs) {
+ if (ReadCount < ECs.size()) {
+ double weight = ECs[ReadCount++];
+ if (weight != ProfileInfoLoader::Uncounted) {
+ // Here the data realm changes from the unsigned of the file to the
+ // double of the ProfileInfo. This conversion is save because we know
+ // that everything thats representable in unsinged is also representable
+ // in double.
+ EdgeInformation[getFunction(e)][e] += (double)weight;
+
+ DEBUG(errs() << "--Read Edge Counter for " << e
+ << " (# "<< (ReadCount-1) << "): "
+ << (unsigned)getEdgeWeight(e) << "\n");
+ } else {
+ // This happens only if reading optimal profiling information, not when
+ // reading regular profiling information.
+ SpanningTree.insert(e);
+ }
+ }
+}
+
bool LoaderPass::runOnModule(Module &M) {
ProfileInfoLoader PIL("profile-loader", Filename, M);
EdgeInformation.clear();
- std::vector<unsigned> ECs = PIL.getRawEdgeCounts();
- if (ECs.size() > 0) {
- unsigned ei = 0;
+ std::vector<unsigned> Counters = PIL.getRawEdgeCounts();
+ if (Counters.size() > 0) {
+ ReadCount = 0;
for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
if (F->isDeclaration()) continue;
- if (ei < ECs.size())
- EdgeInformation[F][ProfileInfo::getEdge(0, &F->getEntryBlock())] +=
- ECs[ei++];
+ DEBUG(errs()<<"Working on "<<F->getNameStr()<<"\n");
+ readEdge(getEdge(0,&F->getEntryBlock()), Counters);
for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
- // Okay, we have to add a counter of each outgoing edge. If the
- // outgoing edge is not critical don't split it, just insert the counter
- // in the source or destination of the edge.
TerminatorInst *TI = BB->getTerminator();
for (unsigned s = 0, e = TI->getNumSuccessors(); s != e; ++s) {
- if (ei < ECs.size())
- EdgeInformation[F][ProfileInfo::getEdge(BB, TI->getSuccessor(s))] +=
- ECs[ei++];
+ readEdge(getEdge(BB,TI->getSuccessor(s)), Counters);
+ }
+ }
+ }
+ if (ReadCount != Counters.size()) {
+ errs() << "WARNING: profile information is inconsistent with "
+ << "the current program!\n";
+ }
+ NumEdgesRead = ReadCount;
+ }
+
+ Counters = PIL.getRawOptimalEdgeCounts();
+ if (Counters.size() > 0) {
+ ReadCount = 0;
+ for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
+ if (F->isDeclaration()) continue;
+ DEBUG(errs()<<"Working on "<<F->getNameStr()<<"\n");
+ readEdge(getEdge(0,&F->getEntryBlock()), Counters);
+ for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
+ TerminatorInst *TI = BB->getTerminator();
+ if (TI->getNumSuccessors() == 0) {
+ readEdge(getEdge(BB,0), Counters);
+ }
+ for (unsigned s = 0, e = TI->getNumSuccessors(); s != e; ++s) {
+ readEdge(getEdge(BB,TI->getSuccessor(s)), Counters);
+ }
+ }
+ while (SpanningTree.size() > 0) {
+#if 0
+ unsigned size = SpanningTree.size();
+#endif
+ BBisUnvisited.clear();
+ for (std::set<Edge>::iterator ei = SpanningTree.begin(),
+ ee = SpanningTree.end(); ei != ee; ++ei) {
+ BBisUnvisited.insert(ei->first);
+ BBisUnvisited.insert(ei->second);
+ }
+ while (BBisUnvisited.size() > 0) {
+ recurseBasicBlock(*BBisUnvisited.begin());
+ }
+#if 0
+ if (SpanningTree.size() == size) {
+ DEBUG(errs()<<"{");
+ for (std::set<Edge>::iterator ei = SpanningTree.begin(),
+ ee = SpanningTree.end(); ei != ee; ++ei) {
+ DEBUG(errs()<<"("<<(ei->first?ei->first->getName():"0")<<","
+ <<(ei->second?ei->second->getName():"0")<<"),");
+ }
+ assert(0 && "No edge calculated!");
}
+#endif
}
}
- if (ei != ECs.size()) {
+ if (ReadCount != Counters.size()) {
errs() << "WARNING: profile information is inconsistent with "
<< "the current program!\n";
}
+ NumEdgesRead = ReadCount;
}
BlockInformation.clear();
- std::vector<unsigned> BCs = PIL.getRawBlockCounts();
- if (BCs.size() > 0) {
- unsigned bi = 0;
+ Counters = PIL.getRawBlockCounts();
+ if (Counters.size() > 0) {
+ ReadCount = 0;
for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
if (F->isDeclaration()) continue;
for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB)
- if (bi < BCs.size())
- BlockInformation[F][BB] = BCs[bi++];
+ if (ReadCount < Counters.size())
+ // Here the data realm changes from the unsigned of the file to the
+ // double of the ProfileInfo. This conversion is save because we know
+ // that everything thats representable in unsinged is also
+ // representable in double.
+ BlockInformation[F][BB] = (double)Counters[ReadCount++];
}
- if (bi != BCs.size()) {
+ if (ReadCount != Counters.size()) {
errs() << "WARNING: profile information is inconsistent with "
<< "the current program!\n";
}
}
FunctionInformation.clear();
- std::vector<unsigned> FCs = PIL.getRawFunctionCounts();
- if (FCs.size() > 0) {
- unsigned fi = 0;
+ Counters = PIL.getRawFunctionCounts();
+ if (Counters.size() > 0) {
+ ReadCount = 0;
for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
if (F->isDeclaration()) continue;
- if (fi < FCs.size())
- FunctionInformation[F] = FCs[fi++];
+ if (ReadCount < Counters.size())
+ // Here the data realm changes from the unsigned of the file to the
+ // double of the ProfileInfo. This conversion is save because we know
+ // that everything thats representable in unsinged is also
+ // representable in double.
+ FunctionInformation[F] = (double)Counters[ReadCount++];
}
- if (fi != FCs.size()) {
+ if (ReadCount != Counters.size()) {
errs() << "WARNING: profile information is inconsistent with "
<< "the current program!\n";
}
diff --git a/libclamav/c++/llvm/lib/Analysis/ProfileVerifierPass.cpp b/libclamav/c++/llvm/lib/Analysis/ProfileVerifierPass.cpp
new file mode 100644
index 0000000..9766da5
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Analysis/ProfileVerifierPass.cpp
@@ -0,0 +1,343 @@
+//===- ProfileVerifierPass.cpp - LLVM Pass to estimate profile info -------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a pass that checks profiling information for
+// plausibility.
+//
+//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "profile-verifier"
+#include "llvm/Instructions.h"
+#include "llvm/Module.h"
+#include "llvm/Pass.h"
+#include "llvm/Analysis/ProfileInfo.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/CallSite.h"
+#include "llvm/Support/CFG.h"
+#include "llvm/Support/InstIterator.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/Debug.h"
+#include <set>
+using namespace llvm;
+
+static cl::opt<bool,false>
+ProfileVerifierDisableAssertions("profile-verifier-noassert",
+ cl::desc("Disable assertions"));
+
+namespace {
+ class VISIBILITY_HIDDEN ProfileVerifierPass : public FunctionPass {
+
+ struct DetailedBlockInfo {
+ const BasicBlock *BB;
+ double BBWeight;
+ double inWeight;
+ int inCount;
+ double outWeight;
+ int outCount;
+ };
+
+ ProfileInfo *PI;
+ std::set<const BasicBlock*> BBisVisited;
+ std::set<const Function*> FisVisited;
+ bool DisableAssertions;
+
+ // When debugging is enabled, the verifier prints a whole slew of debug
+ // information, otherwise its just the assert. These are all the helper
+ // functions.
+ bool PrintedDebugTree;
+ std::set<const BasicBlock*> BBisPrinted;
+ void debugEntry(DetailedBlockInfo*);
+ void printDebugInfo(const BasicBlock *BB);
+
+ public:
+ static char ID; // Class identification, replacement for typeinfo
+
+ explicit ProfileVerifierPass () : FunctionPass(&ID) {
+ DisableAssertions = ProfileVerifierDisableAssertions;
+ }
+ explicit ProfileVerifierPass (bool da) : FunctionPass(&ID),
+ DisableAssertions(da) {
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesAll();
+ AU.addRequired<ProfileInfo>();
+ }
+
+ const char *getPassName() const {
+ return "Profiling information verifier";
+ }
+
+ /// run - Verify the profile information.
+ bool runOnFunction(Function &F);
+ void recurseBasicBlock(const BasicBlock*);
+
+ bool exitReachable(const Function*);
+ double ReadOrAssert(ProfileInfo::Edge);
+ void CheckValue(bool, const char*, DetailedBlockInfo*);
+ };
+} // End of anonymous namespace
+
+char ProfileVerifierPass::ID = 0;
+static RegisterPass<ProfileVerifierPass>
+X("profile-verifier", "Verify profiling information", false, true);
+
+namespace llvm {
+ FunctionPass *createProfileVerifierPass() {
+ return new ProfileVerifierPass(ProfileVerifierDisableAssertions);
+ }
+}
+
+void ProfileVerifierPass::printDebugInfo(const BasicBlock *BB) {
+
+ if (BBisPrinted.find(BB) != BBisPrinted.end()) return;
+
+ double BBWeight = PI->getExecutionCount(BB);
+ if (BBWeight == ProfileInfo::MissingValue) { BBWeight = 0; }
+ double inWeight = 0;
+ int inCount = 0;
+ std::set<const BasicBlock*> ProcessedPreds;
+ for ( pred_const_iterator bbi = pred_begin(BB), bbe = pred_end(BB);
+ bbi != bbe; ++bbi ) {
+ if (ProcessedPreds.insert(*bbi).second) {
+ ProfileInfo::Edge E = PI->getEdge(*bbi,BB);
+ double EdgeWeight = PI->getEdgeWeight(E);
+ if (EdgeWeight == ProfileInfo::MissingValue) { EdgeWeight = 0; }
+ errs() << "calculated in-edge " << E << ": " << EdgeWeight << "\n";
+ inWeight += EdgeWeight;
+ inCount++;
+ }
+ }
+ double outWeight = 0;
+ int outCount = 0;
+ std::set<const BasicBlock*> ProcessedSuccs;
+ for ( succ_const_iterator bbi = succ_begin(BB), bbe = succ_end(BB);
+ bbi != bbe; ++bbi ) {
+ if (ProcessedSuccs.insert(*bbi).second) {
+ ProfileInfo::Edge E = PI->getEdge(BB,*bbi);
+ double EdgeWeight = PI->getEdgeWeight(E);
+ if (EdgeWeight == ProfileInfo::MissingValue) { EdgeWeight = 0; }
+ errs() << "calculated out-edge " << E << ": " << EdgeWeight << "\n";
+ outWeight += EdgeWeight;
+ outCount++;
+ }
+ }
+ errs()<<"Block "<<BB->getNameStr()<<" in "<<BB->getParent()->getNameStr()
+ <<",BBWeight="<<BBWeight<<",inWeight="<<inWeight<<",inCount="<<inCount
+ <<",outWeight="<<outWeight<<",outCount"<<outCount<<"\n";
+
+ // mark as visited and recurse into subnodes
+ BBisPrinted.insert(BB);
+ for ( succ_const_iterator bbi = succ_begin(BB), bbe = succ_end(BB);
+ bbi != bbe; ++bbi ) {
+ printDebugInfo(*bbi);
+ }
+}
+
+void ProfileVerifierPass::debugEntry (DetailedBlockInfo *DI) {
+ errs() << "TROUBLE: Block " << DI->BB->getNameStr() << " in "
+ << DI->BB->getParent()->getNameStr() << ":";
+ errs() << "BBWeight=" << DI->BBWeight << ",";
+ errs() << "inWeight=" << DI->inWeight << ",";
+ errs() << "inCount=" << DI->inCount << ",";
+ errs() << "outWeight=" << DI->outWeight << ",";
+ errs() << "outCount=" << DI->outCount << "\n";
+ if (!PrintedDebugTree) {
+ PrintedDebugTree = true;
+ printDebugInfo(&(DI->BB->getParent()->getEntryBlock()));
+ }
+}
+
+// This compares A and B but considering maybe small differences.
+static bool Equals(double A, double B) {
+ double maxRelativeError = 0.0000001;
+ if (A == B)
+ return true;
+ double relativeError;
+ if (fabs(B) > fabs(A))
+ relativeError = fabs((A - B) / B);
+ else
+ relativeError = fabs((A - B) / A);
+ if (relativeError <= maxRelativeError) return true;
+ return false;
+}
+
+// This checks if the function "exit" is reachable from an given function
+// via calls, this is necessary to check if a profile is valid despite the
+// counts not fitting exactly.
+bool ProfileVerifierPass::exitReachable(const Function *F) {
+ if (!F) return false;
+
+ if (FisVisited.count(F)) return false;
+
+ Function *Exit = F->getParent()->getFunction("exit");
+ if (Exit == F) {
+ return true;
+ }
+
+ FisVisited.insert(F);
+ bool exits = false;
+ for (const_inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I) {
+ if (const CallInst *CI = dyn_cast<CallInst>(&*I)) {
+ exits |= exitReachable(CI->getCalledFunction());
+ if (exits) break;
+ }
+ }
+ return exits;
+}
+
+#define ASSERTMESSAGE(M) \
+ errs() << (M) << "\n"; \
+ if (!DisableAssertions) assert(0 && (M));
+
+double ProfileVerifierPass::ReadOrAssert(ProfileInfo::Edge E) {
+ double EdgeWeight = PI->getEdgeWeight(E);
+ if (EdgeWeight == ProfileInfo::MissingValue) {
+ errs() << "Edge " << E << " in Function "
+ << ProfileInfo::getFunction(E)->getNameStr() << ": ";
+ ASSERTMESSAGE("ASSERT:Edge has missing value");
+ return 0;
+ } else {
+ return EdgeWeight;
+ }
+}
+
+void ProfileVerifierPass::CheckValue(bool Error, const char *Message,
+ DetailedBlockInfo *DI) {
+ if (Error) {
+ DEBUG(debugEntry(DI));
+ errs() << "Block " << DI->BB->getNameStr() << " in Function "
+ << DI->BB->getParent()->getNameStr() << ": ";
+ ASSERTMESSAGE(Message);
+ }
+ return;
+}
+
+// This calculates the Information for a block and then recurses into the
+// successors.
+void ProfileVerifierPass::recurseBasicBlock(const BasicBlock *BB) {
+
+ // Break the recursion by remembering all visited blocks.
+ if (BBisVisited.find(BB) != BBisVisited.end()) return;
+
+ // Use a data structure to store all the information, this can then be handed
+ // to debug printers.
+ DetailedBlockInfo DI;
+ DI.BB = BB;
+ DI.outCount = DI.inCount = DI.inWeight = DI.outWeight = 0;
+
+ // Read predecessors.
+ std::set<const BasicBlock*> ProcessedPreds;
+ pred_const_iterator bpi = pred_begin(BB), bpe = pred_end(BB);
+ // If there are none, check for (0,BB) edge.
+ if (bpi == bpe) {
+ DI.inWeight += ReadOrAssert(PI->getEdge(0,BB));
+ DI.inCount++;
+ }
+ for (;bpi != bpe; ++bpi) {
+ if (ProcessedPreds.insert(*bpi).second) {
+ DI.inWeight += ReadOrAssert(PI->getEdge(*bpi,BB));
+ DI.inCount++;
+ }
+ }
+
+ // Read successors.
+ std::set<const BasicBlock*> ProcessedSuccs;
+ succ_const_iterator bbi = succ_begin(BB), bbe = succ_end(BB);
+ // If there is an (0,BB) edge, consider it too. (This is done not only when
+ // there are no successors, but every time; not every function contains
+ // return blocks with no successors (think loop latch as return block)).
+ double w = PI->getEdgeWeight(PI->getEdge(BB,0));
+ if (w != ProfileInfo::MissingValue) {
+ DI.outWeight += w;
+ DI.outCount++;
+ }
+ for (;bbi != bbe; ++bbi) {
+ if (ProcessedSuccs.insert(*bbi).second) {
+ DI.outWeight += ReadOrAssert(PI->getEdge(BB,*bbi));
+ DI.outCount++;
+ }
+ }
+
+ // Read block weight.
+ DI.BBWeight = PI->getExecutionCount(BB);
+ CheckValue(DI.BBWeight == ProfileInfo::MissingValue,
+ "ASSERT:BasicBlock has missing value", &DI);
+
+ // Check if this block is a setjmp target.
+ bool isSetJmpTarget = false;
+ if (DI.outWeight > DI.inWeight) {
+ for (BasicBlock::const_iterator i = BB->begin(), ie = BB->end();
+ i != ie; ++i) {
+ if (const CallInst *CI = dyn_cast<CallInst>(&*i)) {
+ Function *F = CI->getCalledFunction();
+ if (F && (F->getNameStr() == "_setjmp")) {
+ isSetJmpTarget = true; break;
+ }
+ }
+ }
+ }
+ // Check if this block is eventually reaching exit.
+ bool isExitReachable = false;
+ if (DI.inWeight > DI.outWeight) {
+ for (BasicBlock::const_iterator i = BB->begin(), ie = BB->end();
+ i != ie; ++i) {
+ if (const CallInst *CI = dyn_cast<CallInst>(&*i)) {
+ FisVisited.clear();
+ isExitReachable |= exitReachable(CI->getCalledFunction());
+ if (isExitReachable) break;
+ }
+ }
+ }
+
+ if (DI.inCount > 0 && DI.outCount == 0) {
+ // If this is a block with no successors.
+ if (!isSetJmpTarget) {
+ CheckValue(!Equals(DI.inWeight,DI.BBWeight),
+ "ASSERT:inWeight and BBWeight do not match", &DI);
+ }
+ } else if (DI.inCount == 0 && DI.outCount > 0) {
+ // If this is a block with no predecessors.
+ if (!isExitReachable)
+ CheckValue(!Equals(DI.BBWeight,DI.outWeight),
+ "ASSERT:BBWeight and outWeight do not match", &DI);
+ } else {
+ // If this block has successors and predecessors.
+ if (DI.inWeight > DI.outWeight && !isExitReachable)
+ CheckValue(!Equals(DI.inWeight,DI.outWeight),
+ "ASSERT:inWeight and outWeight do not match", &DI);
+ if (DI.inWeight < DI.outWeight && !isSetJmpTarget)
+ CheckValue(!Equals(DI.inWeight,DI.outWeight),
+ "ASSERT:inWeight and outWeight do not match", &DI);
+ }
+
+
+ // Mark this block as visited, rescurse into successors.
+ BBisVisited.insert(BB);
+ for ( succ_const_iterator bbi = succ_begin(BB), bbe = succ_end(BB);
+ bbi != bbe; ++bbi ) {
+ recurseBasicBlock(*bbi);
+ }
+}
+
+bool ProfileVerifierPass::runOnFunction(Function &F) {
+ PI = &getAnalysis<ProfileInfo>();
+
+ // Prepare global variables.
+ PrintedDebugTree = false;
+ BBisVisited.clear();
+
+ // Fetch entry block and recurse into it.
+ const BasicBlock *entry = &F.getEntryBlock();
+ recurseBasicBlock(entry);
+
+ if (!DisableAssertions)
+ assert((PI->getExecutionCount(&F)==PI->getExecutionCount(entry)) &&
+ "Function count and entry block count do not match");
+ return false;
+}
diff --git a/libclamav/c++/llvm/lib/Analysis/README.txt b/libclamav/c++/llvm/lib/Analysis/README.txt
new file mode 100644
index 0000000..c401090
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Analysis/README.txt
@@ -0,0 +1,18 @@
+Analysis Opportunities:
+
+//===---------------------------------------------------------------------===//
+
+In test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll, the
+ScalarEvolution expression for %r is this:
+
+ {1,+,3,+,2}<loop>
+
+Outside the loop, this could be evaluated simply as (%n * %n), however
+ScalarEvolution currently evaluates it as
+
+ (-2 + (2 * (trunc i65 (((zext i64 (-2 + %n) to i65) * (zext i64 (-1 + %n) to i65)) /u 2) to i64)) + (3 * %n))
+
+In addition to being much more complicated, it involves i65 arithmetic,
+which is very inefficient when expanded into code.
+
+//===---------------------------------------------------------------------===//
diff --git a/libclamav/c++/llvm/lib/Analysis/ScalarEvolution.cpp b/libclamav/c++/llvm/lib/Analysis/ScalarEvolution.cpp
index d639aee..12ad429 100644
--- a/libclamav/c++/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -207,6 +207,10 @@ bool SCEVCastExpr::dominates(BasicBlock *BB, DominatorTree *DT) const {
return Op->dominates(BB, DT);
}
+bool SCEVCastExpr::properlyDominates(BasicBlock *BB, DominatorTree *DT) const {
+ return Op->properlyDominates(BB, DT);
+}
+
SCEVTruncateExpr::SCEVTruncateExpr(const FoldingSetNodeID &ID,
const SCEV *op, const Type *ty)
: SCEVCastExpr(ID, scTruncate, op, ty) {
@@ -260,10 +264,22 @@ bool SCEVNAryExpr::dominates(BasicBlock *BB, DominatorTree *DT) const {
return true;
}
+bool SCEVNAryExpr::properlyDominates(BasicBlock *BB, DominatorTree *DT) const {
+ for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
+ if (!getOperand(i)->properlyDominates(BB, DT))
+ return false;
+ }
+ return true;
+}
+
bool SCEVUDivExpr::dominates(BasicBlock *BB, DominatorTree *DT) const {
return LHS->dominates(BB, DT) && RHS->dominates(BB, DT);
}
+bool SCEVUDivExpr::properlyDominates(BasicBlock *BB, DominatorTree *DT) const {
+ return LHS->properlyDominates(BB, DT) && RHS->properlyDominates(BB, DT);
+}
+
void SCEVUDivExpr::print(raw_ostream &OS) const {
OS << "(" << *LHS << " /u " << *RHS << ")";
}
@@ -328,6 +344,12 @@ bool SCEVUnknown::dominates(BasicBlock *BB, DominatorTree *DT) const {
return true;
}
+bool SCEVUnknown::properlyDominates(BasicBlock *BB, DominatorTree *DT) const {
+ if (Instruction *I = dyn_cast<Instruction>(getValue()))
+ return DT->properlyDominates(I->getParent(), BB);
+ return true;
+}
+
const Type *SCEVUnknown::getType() const {
return V->getType();
}
@@ -385,6 +407,10 @@ namespace {
explicit SCEVComplexityCompare(LoopInfo *li) : LI(li) {}
bool operator()(const SCEV *LHS, const SCEV *RHS) const {
+ // Fast-path: SCEVs are uniqued so we can do a quick equality check.
+ if (LHS == RHS)
+ return false;
+
// Primarily, sort the SCEVs by their getSCEVType().
if (LHS->getSCEVType() != RHS->getSCEVType())
return LHS->getSCEVType() < RHS->getSCEVType();
@@ -2420,9 +2446,10 @@ ScalarEvolution::ForgetSymbolicName(Instruction *I, const SCEV *SymName) {
// count information isn't going to change anything. In the later
// case, createNodeForPHI will perform the necessary updates on its
// own when it gets to that point.
- if (!isa<PHINode>(I) || !isa<SCEVUnknown>(It->second))
+ if (!isa<PHINode>(I) || !isa<SCEVUnknown>(It->second)) {
+ ValuesAtScopes.erase(It->second);
Scalars.erase(It);
- ValuesAtScopes.erase(I);
+ }
}
PushDefUseChildren(I, Worklist);
@@ -2967,8 +2994,20 @@ const SCEV *ScalarEvolution::createSCEV(Value *V) {
const SCEV *LHS = getSCEV(U->getOperand(0));
const APInt &CIVal = CI->getValue();
if (GetMinTrailingZeros(LHS) >=
- (CIVal.getBitWidth() - CIVal.countLeadingZeros()))
- return getAddExpr(LHS, getSCEV(U->getOperand(1)));
+ (CIVal.getBitWidth() - CIVal.countLeadingZeros())) {
+ // Build a plain add SCEV.
+ const SCEV *S = getAddExpr(LHS, getSCEV(CI));
+ // If the LHS of the add was an addrec and it has no-wrap flags,
+ // transfer the no-wrap flags, since an or won't introduce a wrap.
+ if (const SCEVAddRecExpr *NewAR = dyn_cast<SCEVAddRecExpr>(S)) {
+ const SCEVAddRecExpr *OldAR = cast<SCEVAddRecExpr>(LHS);
+ if (OldAR->hasNoUnsignedWrap())
+ const_cast<SCEVAddRecExpr *>(NewAR)->setHasNoUnsignedWrap(true);
+ if (OldAR->hasNoSignedWrap())
+ const_cast<SCEVAddRecExpr *>(NewAR)->setHasNoSignedWrap(true);
+ }
+ return S;
+ }
}
break;
case Instruction::Xor:
@@ -3232,9 +3271,10 @@ ScalarEvolution::getBackedgeTakenInfo(const Loop *L) {
// count information isn't going to change anything. In the later
// case, createNodeForPHI will perform the necessary updates on its
// own when it gets to that point.
- if (!isa<PHINode>(I) || !isa<SCEVUnknown>(It->second))
+ if (!isa<PHINode>(I) || !isa<SCEVUnknown>(It->second)) {
+ ValuesAtScopes.erase(It->second);
Scalars.erase(It);
- ValuesAtScopes.erase(I);
+ }
if (PHINode *PN = dyn_cast<PHINode>(I))
ConstantEvolutionLoopExitValue.erase(PN);
}
@@ -3264,8 +3304,8 @@ void ScalarEvolution::forgetLoopBackedgeTakenCount(const Loop *L) {
std::map<SCEVCallbackVH, const SCEV*>::iterator It =
Scalars.find(static_cast<Value *>(I));
if (It != Scalars.end()) {
+ ValuesAtScopes.erase(It->second);
Scalars.erase(It);
- ValuesAtScopes.erase(I);
if (PHINode *PN = dyn_cast<PHINode>(I))
ConstantEvolutionLoopExitValue.erase(PN);
}
@@ -3886,7 +3926,7 @@ ScalarEvolution::ComputeBackedgeTakenCountExhaustively(const Loop *L,
return getCouldNotCompute();
}
-/// getSCEVAtScope - Return a SCEV expression handle for the specified value
+/// getSCEVAtScope - Return a SCEV expression for the specified value
/// at the specified scope in the program. The L value specifies a loop
/// nest to evaluate the expression at, where null is the top-level or a
/// specified loop is immediately inside of the loop.
@@ -3897,8 +3937,20 @@ ScalarEvolution::ComputeBackedgeTakenCountExhaustively(const Loop *L,
/// In the case that a relevant loop exit value cannot be computed, the
/// original value V is returned.
const SCEV *ScalarEvolution::getSCEVAtScope(const SCEV *V, const Loop *L) {
- // FIXME: this should be turned into a virtual method on SCEV!
+ // Check to see if we've folded this expression at this loop before.
+ std::map<const Loop *, const SCEV *> &Values = ValuesAtScopes[V];
+ std::pair<std::map<const Loop *, const SCEV *>::iterator, bool> Pair =
+ Values.insert(std::make_pair(L, static_cast<const SCEV *>(0)));
+ if (!Pair.second)
+ return Pair.first->second ? Pair.first->second : V;
+ // Otherwise compute it.
+ const SCEV *C = computeSCEVAtScope(V, L);
+ ValuesAtScopes[V][L] = C;
+ return C;
+}
+
+const SCEV *ScalarEvolution::computeSCEVAtScope(const SCEV *V, const Loop *L) {
if (isa<SCEVConstant>(V)) return V;
// If this instruction is evolved from a constant-evolving PHI, compute the
@@ -3931,13 +3983,6 @@ const SCEV *ScalarEvolution::getSCEVAtScope(const SCEV *V, const Loop *L) {
// the arguments into constants, and if so, try to constant propagate the
// result. This is particularly useful for computing loop exit values.
if (CanConstantFold(I)) {
- // Check to see if we've folded this instruction at this loop before.
- std::map<const Loop *, Constant *> &Values = ValuesAtScopes[I];
- std::pair<std::map<const Loop *, Constant *>::iterator, bool> Pair =
- Values.insert(std::make_pair(L, static_cast<Constant *>(0)));
- if (!Pair.second)
- return Pair.first->second ? &*getSCEV(Pair.first->second) : V;
-
std::vector<Constant*> Operands;
Operands.reserve(I->getNumOperands());
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
@@ -3986,7 +4031,6 @@ const SCEV *ScalarEvolution::getSCEVAtScope(const SCEV *V, const Loop *L) {
C = ConstantFoldInstOperands(I->getOpcode(), I->getType(),
&Operands[0], Operands.size(),
getContext());
- Pair.first->second = C;
return getSCEV(C);
}
}
@@ -4785,7 +4829,8 @@ ScalarEvolution::isImpliedCondOperandsHelper(ICmpInst::Predicate Pred,
/// CouldNotCompute if an intermediate computation overflows.
const SCEV *ScalarEvolution::getBECount(const SCEV *Start,
const SCEV *End,
- const SCEV *Step) {
+ const SCEV *Step,
+ bool NoWrap) {
const Type *Ty = Start->getType();
const SCEV *NegOne = getIntegerSCEV(-1, Ty);
const SCEV *Diff = getMinusSCEV(End, Start);
@@ -4795,15 +4840,17 @@ const SCEV *ScalarEvolution::getBECount(const SCEV *Start,
// the division will effectively round up.
const SCEV *Add = getAddExpr(Diff, RoundUp);
- // Check Add for unsigned overflow.
- // TODO: More sophisticated things could be done here.
- const Type *WideTy = IntegerType::get(getContext(),
- getTypeSizeInBits(Ty) + 1);
- const SCEV *EDiff = getZeroExtendExpr(Diff, WideTy);
- const SCEV *ERoundUp = getZeroExtendExpr(RoundUp, WideTy);
- const SCEV *OperandExtendedAdd = getAddExpr(EDiff, ERoundUp);
- if (getZeroExtendExpr(Add, WideTy) != OperandExtendedAdd)
- return getCouldNotCompute();
+ if (!NoWrap) {
+ // Check Add for unsigned overflow.
+ // TODO: More sophisticated things could be done here.
+ const Type *WideTy = IntegerType::get(getContext(),
+ getTypeSizeInBits(Ty) + 1);
+ const SCEV *EDiff = getZeroExtendExpr(Diff, WideTy);
+ const SCEV *ERoundUp = getZeroExtendExpr(RoundUp, WideTy);
+ const SCEV *OperandExtendedAdd = getAddExpr(EDiff, ERoundUp);
+ if (getZeroExtendExpr(Add, WideTy) != OperandExtendedAdd)
+ return getCouldNotCompute();
+ }
return getUDivExpr(Add, Step);
}
@@ -4821,6 +4868,10 @@ ScalarEvolution::HowManyLessThans(const SCEV *LHS, const SCEV *RHS,
if (!AddRec || AddRec->getLoop() != L)
return getCouldNotCompute();
+ // Check to see if we have a flag which makes analysis easy.
+ bool NoWrap = isSigned ? AddRec->hasNoSignedWrap() :
+ AddRec->hasNoUnsignedWrap();
+
if (AddRec->isAffine()) {
// FORNOW: We only support unit strides.
unsigned BitWidth = getTypeSizeInBits(AddRec->getType());
@@ -4833,7 +4884,10 @@ ScalarEvolution::HowManyLessThans(const SCEV *LHS, const SCEV *RHS,
if (CStep->isOne()) {
// With unit stride, the iteration never steps past the limit value.
} else if (CStep->getValue()->getValue().isStrictlyPositive()) {
- if (const SCEVConstant *CLimit = dyn_cast<SCEVConstant>(RHS)) {
+ if (NoWrap) {
+ // We know the iteration won't step past the maximum value for its type.
+ ;
+ } else if (const SCEVConstant *CLimit = dyn_cast<SCEVConstant>(RHS)) {
// Test whether a positive iteration iteration can step past the limit
// value and past the maximum value for its type in a single step.
if (isSigned) {
@@ -4886,11 +4940,11 @@ ScalarEvolution::HowManyLessThans(const SCEV *LHS, const SCEV *RHS,
// Finally, we subtract these two values and divide, rounding up, to get
// the number of times the backedge is executed.
- const SCEV *BECount = getBECount(Start, End, Step);
+ const SCEV *BECount = getBECount(Start, End, Step, NoWrap);
// The maximum backedge count is similar, except using the minimum start
// value and the maximum end value.
- const SCEV *MaxBECount = getBECount(MinStart, MaxEnd, Step);
+ const SCEV *MaxBECount = getBECount(MinStart, MaxEnd, Step, NoWrap);
return BackedgeTakenInfo(BECount, MaxBECount);
}
@@ -5031,8 +5085,6 @@ void ScalarEvolution::SCEVCallbackVH::deleted() {
assert(SE && "SCEVCallbackVH called with a null ScalarEvolution!");
if (PHINode *PN = dyn_cast<PHINode>(getValPtr()))
SE->ConstantEvolutionLoopExitValue.erase(PN);
- if (Instruction *I = dyn_cast<Instruction>(getValPtr()))
- SE->ValuesAtScopes.erase(I);
SE->Scalars.erase(getValPtr());
// this now dangles!
}
@@ -5062,8 +5114,6 @@ void ScalarEvolution::SCEVCallbackVH::allUsesReplacedWith(Value *) {
continue;
if (PHINode *PN = dyn_cast<PHINode>(U))
SE->ConstantEvolutionLoopExitValue.erase(PN);
- if (Instruction *I = dyn_cast<Instruction>(U))
- SE->ValuesAtScopes.erase(I);
SE->Scalars.erase(U);
for (Value::use_iterator UI = U->use_begin(), UE = U->use_end();
UI != UE; ++UI)
@@ -5073,8 +5123,6 @@ void ScalarEvolution::SCEVCallbackVH::allUsesReplacedWith(Value *) {
if (DeleteOld) {
if (PHINode *PN = dyn_cast<PHINode>(Old))
SE->ConstantEvolutionLoopExitValue.erase(PN);
- if (Instruction *I = dyn_cast<Instruction>(Old))
- SE->ValuesAtScopes.erase(I);
SE->Scalars.erase(Old);
// this now dangles!
}
diff --git a/libclamav/c++/llvm/lib/Analysis/ScalarEvolutionExpander.cpp b/libclamav/c++/llvm/lib/Analysis/ScalarEvolutionExpander.cpp
index 3472470..f5df026 100644
--- a/libclamav/c++/llvm/lib/Analysis/ScalarEvolutionExpander.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/ScalarEvolutionExpander.cpp
@@ -508,20 +508,37 @@ Value *SCEVExpander::expandAddToGEP(const SCEV *const *op_begin,
}
Value *SCEVExpander::visitAddExpr(const SCEVAddExpr *S) {
+ int NumOperands = S->getNumOperands();
const Type *Ty = SE.getEffectiveSCEVType(S->getType());
- Value *V = expand(S->getOperand(S->getNumOperands()-1));
+
+ // Find the index of an operand to start with. Choose the operand with
+ // pointer type, if there is one, or the last operand otherwise.
+ int PIdx = 0;
+ for (; PIdx != NumOperands - 1; ++PIdx)
+ if (isa<PointerType>(S->getOperand(PIdx)->getType())) break;
+
+ // Expand code for the operand that we chose.
+ Value *V = expand(S->getOperand(PIdx));
// Turn things like ptrtoint+arithmetic+inttoptr into GEP. See the
// comments on expandAddToGEP for details.
if (const PointerType *PTy = dyn_cast<PointerType>(V->getType())) {
+ // Take the operand at PIdx out of the list.
const SmallVectorImpl<const SCEV *> &Ops = S->getOperands();
- return expandAddToGEP(&Ops[0], &Ops[Ops.size() - 1], PTy, Ty, V);
+ SmallVector<const SCEV *, 8> NewOps;
+ NewOps.insert(NewOps.end(), Ops.begin(), Ops.begin() + PIdx);
+ NewOps.insert(NewOps.end(), Ops.begin() + PIdx + 1, Ops.end());
+ // Make a GEP.
+ return expandAddToGEP(NewOps.begin(), NewOps.end(), PTy, Ty, V);
}
+ // Otherwise, we'll expand the rest of the SCEVAddExpr as plain integer
+ // arithmetic.
V = InsertNoopCastOfTo(V, Ty);
// Emit a bunch of add instructions
- for (int i = S->getNumOperands()-2; i >= 0; --i) {
+ for (int i = NumOperands-1; i >= 0; --i) {
+ if (i == PIdx) continue;
Value *W = expandCodeFor(S->getOperand(i), Ty);
V = InsertBinop(Instruction::Add, V, W);
}
@@ -603,11 +620,11 @@ Value *SCEVExpander::visitAddRecExpr(const SCEVAddRecExpr *S) {
if (CanonicalIV &&
SE.getTypeSizeInBits(CanonicalIV->getType()) >
SE.getTypeSizeInBits(Ty)) {
- const SCEV *Start = SE.getAnyExtendExpr(S->getStart(),
- CanonicalIV->getType());
- const SCEV *Step = SE.getAnyExtendExpr(S->getStepRecurrence(SE),
- CanonicalIV->getType());
- Value *V = expand(SE.getAddRecExpr(Start, Step, S->getLoop()));
+ const SmallVectorImpl<const SCEV *> &Ops = S->getOperands();
+ SmallVector<const SCEV *, 4> NewOps(Ops.size());
+ for (unsigned i = 0, e = Ops.size(); i != e; ++i)
+ NewOps[i] = SE.getAnyExtendExpr(Ops[i], CanonicalIV->getType());
+ Value *V = expand(SE.getAddRecExpr(NewOps, S->getLoop()));
BasicBlock *SaveInsertBB = Builder.GetInsertBlock();
BasicBlock::iterator SaveInsertPt = Builder.GetInsertPoint();
BasicBlock::iterator NewInsertPt =
@@ -663,29 +680,22 @@ Value *SCEVExpander::visitAddRecExpr(const SCEVAddRecExpr *S) {
// Create and insert the PHI node for the induction variable in the
// specified loop.
BasicBlock *Header = L->getHeader();
- BasicBlock *Preheader = L->getLoopPreheader();
PHINode *PN = PHINode::Create(Ty, "indvar", Header->begin());
InsertedValues.insert(PN);
- PN->addIncoming(Constant::getNullValue(Ty), Preheader);
- pred_iterator HPI = pred_begin(Header);
- assert(HPI != pred_end(Header) && "Loop with zero preds???");
- if (!L->contains(*HPI)) ++HPI;
- assert(HPI != pred_end(Header) && L->contains(*HPI) &&
- "No backedge in loop?");
-
- // Insert a unit add instruction right before the terminator corresponding
- // to the back-edge.
Constant *One = ConstantInt::get(Ty, 1);
- Instruction *Add = BinaryOperator::CreateAdd(PN, One, "indvar.next",
- (*HPI)->getTerminator());
- InsertedValues.insert(Add);
-
- pred_iterator PI = pred_begin(Header);
- if (*PI == Preheader)
- ++PI;
- PN->addIncoming(Add, *PI);
- return PN;
+ for (pred_iterator HPI = pred_begin(Header), HPE = pred_end(Header);
+ HPI != HPE; ++HPI)
+ if (L->contains(*HPI)) {
+ // Insert a unit add instruction right before the terminator corresponding
+ // to the back-edge.
+ Instruction *Add = BinaryOperator::CreateAdd(PN, One, "indvar.next",
+ (*HPI)->getTerminator());
+ InsertedValues.insert(Add);
+ PN->addIncoming(Add, *HPI);
+ } else {
+ PN->addIncoming(Constant::getNullValue(Ty), *HPI);
+ }
}
// {0,+,F} --> {0,+,1} * F
diff --git a/libclamav/c++/llvm/lib/Analysis/SparsePropagation.cpp b/libclamav/c++/llvm/lib/Analysis/SparsePropagation.cpp
index 8db6071..b7844f0 100644
--- a/libclamav/c++/llvm/lib/Analysis/SparsePropagation.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/SparsePropagation.cpp
@@ -223,6 +223,16 @@ void SparseSolver::visitTerminatorInst(TerminatorInst &TI) {
}
void SparseSolver::visitPHINode(PHINode &PN) {
+ // The lattice function may store more information on a PHINode than could be
+ // computed from its incoming values. For example, SSI form stores its sigma
+ // functions as PHINodes with a single incoming value.
+ if (LatticeFunc->IsSpecialCasedPHI(&PN)) {
+ LatticeVal IV = LatticeFunc->ComputeInstructionState(PN, *this);
+ if (IV != LatticeFunc->getUntrackedVal())
+ UpdateState(PN, IV);
+ return;
+ }
+
LatticeVal PNIV = getOrInitValueState(&PN);
LatticeVal Overdefined = LatticeFunc->getOverdefinedVal();
@@ -285,7 +295,7 @@ void SparseSolver::Solve(Function &F) {
Instruction *I = InstWorkList.back();
InstWorkList.pop_back();
- DEBUG(errs() << "\nPopped off I-WL: " << *I);
+ DEBUG(errs() << "\nPopped off I-WL: " << *I << "\n");
// "I" got into the work list because it made a transition. See if any
// users are both live and in need of updating.
@@ -324,7 +334,7 @@ void SparseSolver::Print(Function &F, raw_ostream &OS) const {
OS << "; anon bb\n";
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
LatticeFunc->PrintValue(getLatticeState(I), OS);
- OS << *I;
+ OS << *I << "\n";
}
OS << "\n";
diff --git a/libclamav/c++/llvm/lib/Analysis/ValueTracking.cpp b/libclamav/c++/llvm/lib/Analysis/ValueTracking.cpp
index cb2d624..baa347a 100644
--- a/libclamav/c++/llvm/lib/Analysis/ValueTracking.cpp
+++ b/libclamav/c++/llvm/lib/Analysis/ValueTracking.cpp
@@ -16,6 +16,7 @@
#include "llvm/Constants.h"
#include "llvm/Instructions.h"
#include "llvm/GlobalVariable.h"
+#include "llvm/GlobalAlias.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/LLVMContext.h"
#include "llvm/Operator.h"
@@ -35,6 +36,12 @@ using namespace llvm;
/// optimized based on the contradictory assumption that it is non-zero.
/// Because instcombine aggressively folds operations with undef args anyway,
/// this won't lose us code quality.
+///
+/// This function is defined on values with integer type, values with pointer
+/// type (but only if TD is non-null), and vectors of integers. In the case
+/// where V is a vector, the mask, known zero, and known one values are the
+/// same width as the vector element, and the bit is set only if it is true
+/// for all of the elements in the vector.
void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
APInt &KnownZero, APInt &KnownOne,
const TargetData *TD, unsigned Depth) {
@@ -99,6 +106,17 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
KnownOne.clear();
return;
}
+ // A weak GlobalAlias is totally unknown. A non-weak GlobalAlias has
+ // the bits of its aliasee.
+ if (GlobalAlias *GA = dyn_cast<GlobalAlias>(V)) {
+ if (GA->mayBeOverridden()) {
+ KnownZero.clear(); KnownOne.clear();
+ } else {
+ ComputeMaskedBits(GA->getAliasee(), Mask, KnownZero, KnownOne,
+ TD, Depth+1);
+ }
+ return;
+ }
KnownZero.clear(); KnownOne.clear(); // Start out not knowing anything.
@@ -226,12 +244,16 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
// FALL THROUGH and handle them the same as zext/trunc.
case Instruction::ZExt:
case Instruction::Trunc: {
+ const Type *SrcTy = I->getOperand(0)->getType();
+
+ unsigned SrcBitWidth;
// Note that we handle pointer operands here because of inttoptr/ptrtoint
// which fall through here.
- const Type *SrcTy = I->getOperand(0)->getType();
- unsigned SrcBitWidth = TD ?
- TD->getTypeSizeInBits(SrcTy) :
- SrcTy->getScalarSizeInBits();
+ if (isa<PointerType>(SrcTy))
+ SrcBitWidth = TD->getTypeSizeInBits(SrcTy);
+ else
+ SrcBitWidth = SrcTy->getScalarSizeInBits();
+
APInt MaskIn(Mask);
MaskIn.zextOrTrunc(SrcBitWidth);
KnownZero.zextOrTrunc(SrcBitWidth);
@@ -259,8 +281,7 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
}
case Instruction::SExt: {
// Compute the bits in the result that are not present in the input.
- const IntegerType *SrcTy = cast<IntegerType>(I->getOperand(0)->getType());
- unsigned SrcBitWidth = SrcTy->getBitWidth();
+ unsigned SrcBitWidth = I->getOperand(0)->getType()->getScalarSizeInBits();
APInt MaskIn(Mask);
MaskIn.trunc(SrcBitWidth);
@@ -608,6 +629,12 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
/// this predicate to simplify operations downstream. Mask is known to be zero
/// for bits that V cannot have.
+///
+/// This function is defined on values with integer type, values with pointer
+/// type (but only if TD is non-null), and vectors of integers. In the case
+/// where V is a vector, the mask, known zero, and known one values are the
+/// same width as the vector element, and the bit is set only if it is true
+/// for all of the elements in the vector.
bool llvm::MaskedValueIsZero(Value *V, const APInt &Mask,
const TargetData *TD, unsigned Depth) {
APInt KnownZero(Mask.getBitWidth(), 0), KnownOne(Mask.getBitWidth(), 0);
@@ -813,9 +840,13 @@ bool llvm::CannotBeNegativeZero(const Value *V, unsigned Depth) {
if (F->isDeclaration()) {
// abs(x) != -0.0
if (F->getName() == "abs") return true;
- // abs[lf](x) != -0.0
- if (F->getName() == "absf") return true;
- if (F->getName() == "absl") return true;
+ // fabs[lf](x) != -0.0
+ if (F->getName() == "fabs") return true;
+ if (F->getName() == "fabsf") return true;
+ if (F->getName() == "fabsl") return true;
+ if (F->getName() == "sqrt" || F->getName() == "sqrtf" ||
+ F->getName() == "sqrtl")
+ return CannotBeNegativeZero(CI->getOperand(1), Depth+1);
}
}
@@ -1058,6 +1089,11 @@ bool llvm::GetConstantStringInfo(Value *V, std::string &Str, uint64_t Offset,
StopAtNul);
}
+ if (MDString *MDStr = dyn_cast<MDString>(V)) {
+ Str = MDStr->getString();
+ return true;
+ }
+
// The GEP instruction, constant or instruction, must reference a global
// variable that is a constant and is initialized. The referenced constant
// initializer is the array that we'll use for optimization.
diff --git a/libclamav/c++/llvm/lib/AsmParser/LLLexer.cpp b/libclamav/c++/llvm/lib/AsmParser/LLLexer.cpp
index 23d7f19..16e0bd7 100644
--- a/libclamav/c++/llvm/lib/AsmParser/LLLexer.cpp
+++ b/libclamav/c++/llvm/lib/AsmParser/LLLexer.cpp
@@ -434,7 +434,7 @@ lltok::Kind LLLexer::LexMetadata() {
++CurPtr;
StrVal.assign(TokStart+1, CurPtr); // Skip !
- return lltok::NamedMD;
+ return lltok::NamedOrCustomMD;
}
return lltok::Metadata;
}
diff --git a/libclamav/c++/llvm/lib/AsmParser/LLParser.cpp b/libclamav/c++/llvm/lib/AsmParser/LLParser.cpp
index 4f7a440..42ce953 100644
--- a/libclamav/c++/llvm/lib/AsmParser/LLParser.cpp
+++ b/libclamav/c++/llvm/lib/AsmParser/LLParser.cpp
@@ -45,7 +45,7 @@ namespace llvm {
t_InlineAsm, // Value in StrVal/StrVal2/UIntVal.
t_Metadata // Value in MetadataVal.
} Kind;
-
+
LLParser::LocTy Loc;
unsigned UIntVal;
std::string StrVal, StrVal2;
@@ -77,27 +77,27 @@ bool LLParser::ValidateEndOfModule() {
return Error(ForwardRefTypeIDs.begin()->second.second,
"use of undefined type '%" +
utostr(ForwardRefTypeIDs.begin()->first) + "'");
-
+
if (!ForwardRefVals.empty())
return Error(ForwardRefVals.begin()->second.second,
"use of undefined value '@" + ForwardRefVals.begin()->first +
"'");
-
+
if (!ForwardRefValIDs.empty())
return Error(ForwardRefValIDs.begin()->second.second,
"use of undefined value '@" +
utostr(ForwardRefValIDs.begin()->first) + "'");
-
+
if (!ForwardRefMDNodes.empty())
return Error(ForwardRefMDNodes.begin()->second.second,
"use of undefined metadata '!" +
utostr(ForwardRefMDNodes.begin()->first) + "'");
-
+
// Look for intrinsic functions and CallInst that need to be upgraded
for (Module::iterator FI = M->begin(), FE = M->end(); FI != FE; )
UpgradeCallsToIntrinsic(FI++); // must be post-increment, as we remove
-
+
// Check debug info intrinsics.
CheckDebugInfoIntrinsics(M);
return false;
@@ -125,7 +125,7 @@ bool LLParser::ParseTopLevelEntities() {
case lltok::GlobalID: if (ParseUnnamedGlobal()) return true; break;
case lltok::GlobalVar: if (ParseNamedGlobal()) return true; break;
case lltok::Metadata: if (ParseStandaloneMetadata()) return true; break;
- case lltok::NamedMD: if (ParseNamedMetadata()) return true; break;
+ case lltok::NamedOrCustomMD: if (ParseNamedMetadata()) return true; break;
// The Global variable production with no name can have many different
// optional leading prefixes, the production is:
@@ -160,7 +160,7 @@ bool LLParser::ParseTopLevelEntities() {
return true;
break;
}
-
+
case lltok::kw_thread_local: // OptionalThreadLocal
case lltok::kw_addrspace: // OptionalAddrSpace
case lltok::kw_constant: // GlobalType
@@ -177,11 +177,11 @@ bool LLParser::ParseTopLevelEntities() {
bool LLParser::ParseModuleAsm() {
assert(Lex.getKind() == lltok::kw_module);
Lex.Lex();
-
- std::string AsmStr;
+
+ std::string AsmStr;
if (ParseToken(lltok::kw_asm, "expected 'module asm'") ||
ParseStringConstant(AsmStr)) return true;
-
+
const std::string &AsmSoFar = M->getModuleInlineAsm();
if (AsmSoFar.empty())
M->setModuleInlineAsm(AsmStr);
@@ -227,7 +227,7 @@ bool LLParser::ParseDepLibs() {
if (EatIfPresent(lltok::rsquare))
return false;
-
+
std::string Str;
if (ParseStringConstant(Str)) return true;
M->addLibrary(Str);
@@ -263,21 +263,21 @@ bool LLParser::ParseUnnamedType() {
PATypeHolder Ty(Type::getVoidTy(Context));
if (ParseType(Ty)) return true;
-
+
// See if this type was previously referenced.
std::map<unsigned, std::pair<PATypeHolder, LocTy> >::iterator
FI = ForwardRefTypeIDs.find(TypeID);
if (FI != ForwardRefTypeIDs.end()) {
if (FI->second.first.get() == Ty)
return Error(TypeLoc, "self referential type is invalid");
-
+
cast<DerivedType>(FI->second.first.get())->refineAbstractTypeTo(Ty);
Ty = FI->second.first.get();
ForwardRefTypeIDs.erase(FI);
}
-
+
NumberedTypes.push_back(Ty);
-
+
return false;
}
@@ -287,14 +287,14 @@ bool LLParser::ParseNamedType() {
std::string Name = Lex.getStrVal();
LocTy NameLoc = Lex.getLoc();
Lex.Lex(); // eat LocalVar.
-
+
PATypeHolder Ty(Type::getVoidTy(Context));
-
+
if (ParseToken(lltok::equal, "expected '=' after name") ||
ParseToken(lltok::kw_type, "expected 'type' after name") ||
ParseType(Ty))
return true;
-
+
// Set the type name, checking for conflicts as we do so.
bool AlreadyExists = M->addTypeName(Name, Ty);
if (!AlreadyExists) return false;
@@ -311,16 +311,16 @@ bool LLParser::ParseNamedType() {
Ty = FI->second.first.get();
ForwardRefTypes.erase(FI);
}
-
+
// Inserting a name that is already defined, get the existing name.
const Type *Existing = M->getTypeByName(Name);
assert(Existing && "Conflict but no matching type?!");
-
+
// Otherwise, this is an attempt to redefine a type. That's okay if
// the redefinition is identical to the original.
// FIXME: REMOVE REDEFINITIONS IN LLVM 3.0
if (Existing == Ty) return false;
-
+
// Any other kind of (non-equivalent) redefinition is an error.
return Error(NameLoc, "redefinition of type named '" + Name + "' of type '" +
Ty->getDescription() + "'");
@@ -332,7 +332,7 @@ bool LLParser::ParseNamedType() {
bool LLParser::ParseDeclare() {
assert(Lex.getKind() == lltok::kw_declare);
Lex.Lex();
-
+
Function *F;
return ParseFunctionHeader(F, false);
}
@@ -342,7 +342,7 @@ bool LLParser::ParseDeclare() {
bool LLParser::ParseDefine() {
assert(Lex.getKind() == lltok::kw_define);
Lex.Lex();
-
+
Function *F;
return ParseFunctionHeader(F, true) ||
ParseFunctionBody(*F);
@@ -390,7 +390,7 @@ bool LLParser::ParseUnnamedGlobal() {
if (ParseOptionalLinkage(Linkage, HasLinkage) ||
ParseOptionalVisibility(Visibility))
return true;
-
+
if (HasLinkage || Lex.getKind() != lltok::kw_alias)
return ParseGlobal(Name, NameLoc, Linkage, HasLinkage, Visibility);
return ParseAlias(Name, NameLoc, Visibility);
@@ -404,14 +404,14 @@ bool LLParser::ParseNamedGlobal() {
LocTy NameLoc = Lex.getLoc();
std::string Name = Lex.getStrVal();
Lex.Lex();
-
+
bool HasLinkage;
unsigned Linkage, Visibility;
if (ParseToken(lltok::equal, "expected '=' in global variable") ||
ParseOptionalLinkage(Linkage, HasLinkage) ||
ParseOptionalVisibility(Visibility))
return true;
-
+
if (HasLinkage || Lex.getKind() != lltok::kw_alias)
return ParseGlobal(Name, NameLoc, Linkage, HasLinkage, Visibility);
return ParseAlias(Name, NameLoc, Visibility);
@@ -432,7 +432,7 @@ bool LLParser::ParseMDNode(MetadataBase *&Node) {
// !{ ..., !42, ... }
unsigned MID = 0;
if (ParseUInt32(MID)) return true;
-
+
// Check existing MDNode.
std::map<unsigned, MetadataBase *>::iterator I = MetadataCache.find(MID);
if (I != MetadataCache.end()) {
@@ -456,12 +456,12 @@ bool LLParser::ParseMDNode(MetadataBase *&Node) {
ForwardRefMDNodes[MID] = std::make_pair(FwdNode, Lex.getLoc());
Node = FwdNode;
return false;
-}
+}
///ParseNamedMetadata:
/// !foo = !{ !1, !2 }
bool LLParser::ParseNamedMetadata() {
- assert(Lex.getKind() == lltok::NamedMD);
+ assert(Lex.getKind() == lltok::NamedOrCustomMD);
Lex.Lex();
std::string Name = Lex.getStrVal();
@@ -493,7 +493,7 @@ bool LLParser::ParseNamedMetadata() {
}
/// ParseStandaloneMetadata:
-/// !42 = !{...}
+/// !42 = !{...}
bool LLParser::ParseStandaloneMetadata() {
assert(Lex.getKind() == lltok::Metadata);
Lex.Lex();
@@ -509,7 +509,7 @@ bool LLParser::ParseStandaloneMetadata() {
PATypeHolder Ty(Type::getVoidTy(Context));
if (ParseType(Ty, TyLoc))
return true;
-
+
if (Lex.getKind() != lltok::Metadata)
return TokError("Expected metadata here");
@@ -518,7 +518,7 @@ bool LLParser::ParseStandaloneMetadata() {
return TokError("Expected '{' here");
SmallVector<Value *, 16> Elts;
- if (ParseMDNodeVector(Elts)
+ if (ParseMDNodeVector(Elts)
|| ParseToken(lltok::rbrace, "expected end of metadata node"))
return true;
@@ -560,7 +560,7 @@ bool LLParser::ParseAlias(const std::string &Name, LocTy NameLoc,
Linkage != GlobalValue::PrivateLinkage &&
Linkage != GlobalValue::LinkerPrivateLinkage)
return Error(LinkageLoc, "invalid linkage type for alias");
-
+
Constant *Aliasee;
LocTy AliaseeLoc = Lex.getLoc();
if (Lex.getKind() != lltok::kw_bitcast &&
@@ -574,7 +574,7 @@ bool LLParser::ParseAlias(const std::string &Name, LocTy NameLoc,
return Error(AliaseeLoc, "invalid aliasee");
Aliasee = ID.ConstantVal;
}
-
+
if (!isa<PointerType>(Aliasee->getType()))
return Error(AliaseeLoc, "alias must have pointer type");
@@ -583,7 +583,7 @@ bool LLParser::ParseAlias(const std::string &Name, LocTy NameLoc,
(GlobalValue::LinkageTypes)Linkage, Name,
Aliasee);
GA->setVisibility((GlobalValue::VisibilityTypes)Visibility);
-
+
// See if this value already exists in the symbol table. If so, it is either
// a redefinition or a definition of a forward reference.
if (GlobalValue *Val =
@@ -600,18 +600,18 @@ bool LLParser::ParseAlias(const std::string &Name, LocTy NameLoc,
if (Val->getType() != GA->getType())
return Error(NameLoc,
"forward reference and definition of alias have different types");
-
+
// If they agree, just RAUW the old value with the alias and remove the
// forward ref info.
Val->replaceAllUsesWith(GA);
Val->eraseFromParent();
ForwardRefVals.erase(I);
}
-
+
// Insert into the module, we know its name won't collide now.
M->getAliasList().push_back(GA);
assert(GA->getNameStr() == Name && "Should not be a name conflict!");
-
+
return false;
}
@@ -629,14 +629,14 @@ bool LLParser::ParseGlobal(const std::string &Name, LocTy NameLoc,
unsigned AddrSpace;
bool ThreadLocal, IsConstant;
LocTy TyLoc;
-
+
PATypeHolder Ty(Type::getVoidTy(Context));
if (ParseOptionalToken(lltok::kw_thread_local, ThreadLocal) ||
ParseOptionalAddrSpace(AddrSpace) ||
ParseGlobalType(IsConstant) ||
ParseType(Ty, TyLoc))
return true;
-
+
// If the linkage is specified and is external, then no initializer is
// present.
Constant *Init = 0;
@@ -649,7 +649,7 @@ bool LLParser::ParseGlobal(const std::string &Name, LocTy NameLoc,
if (isa<FunctionType>(Ty) || Ty == Type::getLabelTy(Context))
return Error(TyLoc, "invalid type for global variable");
-
+
GlobalVariable *GV = 0;
// See if the global was forward referenced, if so, use the global.
@@ -667,20 +667,20 @@ bool LLParser::ParseGlobal(const std::string &Name, LocTy NameLoc,
}
if (GV == 0) {
- GV = new GlobalVariable(*M, Ty, false, GlobalValue::ExternalLinkage, 0,
+ GV = new GlobalVariable(*M, Ty, false, GlobalValue::ExternalLinkage, 0,
Name, 0, false, AddrSpace);
} else {
if (GV->getType()->getElementType() != Ty)
return Error(TyLoc,
"forward reference and definition of global have different types");
-
+
// Move the forward-reference to the correct spot in the module.
M->getGlobalList().splice(M->global_end(), M->getGlobalList(), GV);
}
if (Name.empty())
NumberedVals.push_back(GV);
-
+
// Set the parsed properties on the global.
if (Init)
GV->setInitializer(Init);
@@ -688,11 +688,11 @@ bool LLParser::ParseGlobal(const std::string &Name, LocTy NameLoc,
GV->setLinkage((GlobalValue::LinkageTypes)Linkage);
GV->setVisibility((GlobalValue::VisibilityTypes)Visibility);
GV->setThreadLocal(ThreadLocal);
-
+
// Parse attributes on the global.
while (Lex.getKind() == lltok::comma) {
Lex.Lex();
-
+
if (Lex.getKind() == lltok::kw_section) {
Lex.Lex();
GV->setSection(Lex.getStrVal());
@@ -706,7 +706,7 @@ bool LLParser::ParseGlobal(const std::string &Name, LocTy NameLoc,
TokError("unknown global variable property!");
}
}
-
+
return false;
}
@@ -725,11 +725,11 @@ GlobalValue *LLParser::GetGlobalVal(const std::string &Name, const Type *Ty,
Error(Loc, "global variable reference must have pointer type");
return 0;
}
-
+
// Look this name up in the normal function symbol table.
GlobalValue *Val =
cast_or_null<GlobalValue>(M->getValueSymbolTable().lookup(Name));
-
+
// If this is a forward reference for the value, see if we already created a
// forward ref record.
if (Val == 0) {
@@ -738,7 +738,7 @@ GlobalValue *LLParser::GetGlobalVal(const std::string &Name, const Type *Ty,
if (I != ForwardRefVals.end())
Val = I->second.first;
}
-
+
// If we have the value in the symbol table or fwd-ref table, return it.
if (Val) {
if (Val->getType() == Ty) return Val;
@@ -746,7 +746,7 @@ GlobalValue *LLParser::GetGlobalVal(const std::string &Name, const Type *Ty,
Val->getType()->getDescription() + "'");
return 0;
}
-
+
// Otherwise, create a new forward reference for this value and remember it.
GlobalValue *FwdVal;
if (const FunctionType *FT = dyn_cast<FunctionType>(PTy->getElementType())) {
@@ -755,13 +755,13 @@ GlobalValue *LLParser::GetGlobalVal(const std::string &Name, const Type *Ty,
Error(Loc, "function may not return opaque type");
return 0;
}
-
+
FwdVal = Function::Create(FT, GlobalValue::ExternalWeakLinkage, Name, M);
} else {
FwdVal = new GlobalVariable(*M, PTy->getElementType(), false,
GlobalValue::ExternalWeakLinkage, 0, Name);
}
-
+
ForwardRefVals[Name] = std::make_pair(FwdVal, Loc);
return FwdVal;
}
@@ -772,9 +772,9 @@ GlobalValue *LLParser::GetGlobalVal(unsigned ID, const Type *Ty, LocTy Loc) {
Error(Loc, "global variable reference must have pointer type");
return 0;
}
-
+
GlobalValue *Val = ID < NumberedVals.size() ? NumberedVals[ID] : 0;
-
+
// If this is a forward reference for the value, see if we already created a
// forward ref record.
if (Val == 0) {
@@ -783,7 +783,7 @@ GlobalValue *LLParser::GetGlobalVal(unsigned ID, const Type *Ty, LocTy Loc) {
if (I != ForwardRefValIDs.end())
Val = I->second.first;
}
-
+
// If we have the value in the symbol table or fwd-ref table, return it.
if (Val) {
if (Val->getType() == Ty) return Val;
@@ -791,7 +791,7 @@ GlobalValue *LLParser::GetGlobalVal(unsigned ID, const Type *Ty, LocTy Loc) {
Val->getType()->getDescription() + "'");
return 0;
}
-
+
// Otherwise, create a new forward reference for this value and remember it.
GlobalValue *FwdVal;
if (const FunctionType *FT = dyn_cast<FunctionType>(PTy->getElementType())) {
@@ -805,7 +805,7 @@ GlobalValue *LLParser::GetGlobalVal(unsigned ID, const Type *Ty, LocTy Loc) {
FwdVal = new GlobalVariable(*M, PTy->getElementType(), false,
GlobalValue::ExternalWeakLinkage, 0, "");
}
-
+
ForwardRefValIDs[ID] = std::make_pair(FwdVal, Loc);
return FwdVal;
}
@@ -858,7 +858,7 @@ bool LLParser::ParseOptionalAddrSpace(unsigned &AddrSpace) {
return ParseToken(lltok::lparen, "expected '(' in address space") ||
ParseUInt32(AddrSpace) ||
ParseToken(lltok::rparen, "expected ')' in address space");
-}
+}
/// ParseOptionalAttrs - Parse a potentially empty attribute list. AttrKind
/// indicates what kind of attribute list this is: 0: function arg, 1: result,
@@ -867,7 +867,7 @@ bool LLParser::ParseOptionalAddrSpace(unsigned &AddrSpace) {
bool LLParser::ParseOptionalAttrs(unsigned &Attrs, unsigned AttrKind) {
Attrs = Attribute::None;
LocTy AttrLoc = Lex.getLoc();
-
+
while (1) {
switch (Lex.getKind()) {
case lltok::kw_sext:
@@ -888,10 +888,10 @@ bool LLParser::ParseOptionalAttrs(unsigned &Attrs, unsigned AttrKind) {
default: // End of attributes.
if (AttrKind != 2 && (Attrs & Attribute::FunctionOnly))
return Error(AttrLoc, "invalid use of function-only attribute");
-
+
if (AttrKind != 0 && AttrKind != 3 && (Attrs & Attribute::ParameterOnly))
return Error(AttrLoc, "invalid use of parameter-only attribute");
-
+
return false;
case lltok::kw_zeroext: Attrs |= Attribute::ZExt; break;
case lltok::kw_signext: Attrs |= Attribute::SExt; break;
@@ -915,7 +915,7 @@ bool LLParser::ParseOptionalAttrs(unsigned &Attrs, unsigned AttrKind) {
case lltok::kw_noredzone: Attrs |= Attribute::NoRedZone; break;
case lltok::kw_noimplicitfloat: Attrs |= Attribute::NoImplicitFloat; break;
case lltok::kw_naked: Attrs |= Attribute::Naked; break;
-
+
case lltok::kw_align: {
unsigned Alignment;
if (ParseOptionalAlignment(Alignment))
@@ -974,7 +974,7 @@ bool LLParser::ParseOptionalLinkage(unsigned &Res, bool &HasLinkage) {
/// ::= 'default'
/// ::= 'hidden'
/// ::= 'protected'
-///
+///
bool LLParser::ParseOptionalVisibility(unsigned &Res) {
switch (Lex.getKind()) {
default: Res = GlobalValue::DefaultVisibility; return false;
@@ -998,7 +998,7 @@ bool LLParser::ParseOptionalVisibility(unsigned &Res) {
/// ::= 'arm_aapcs_vfpcc'
/// ::= 'cc' UINT
///
-bool LLParser::ParseOptionalCallingConv(unsigned &CC) {
+bool LLParser::ParseOptionalCallingConv(CallingConv::ID &CC) {
switch (Lex.getKind()) {
default: CC = CallingConv::C; return false;
case lltok::kw_ccc: CC = CallingConv::C; break;
@@ -1009,12 +1009,50 @@ bool LLParser::ParseOptionalCallingConv(unsigned &CC) {
case lltok::kw_arm_apcscc: CC = CallingConv::ARM_APCS; break;
case lltok::kw_arm_aapcscc: CC = CallingConv::ARM_AAPCS; break;
case lltok::kw_arm_aapcs_vfpcc:CC = CallingConv::ARM_AAPCS_VFP; break;
- case lltok::kw_cc: Lex.Lex(); return ParseUInt32(CC);
+ case lltok::kw_cc: {
+ unsigned ArbitraryCC;
+ Lex.Lex();
+ if (ParseUInt32(ArbitraryCC)) {
+ return true;
+ } else
+ CC = static_cast<CallingConv::ID>(ArbitraryCC);
+ return false;
+ }
+ break;
}
+
Lex.Lex();
return false;
}
+/// ParseOptionalCustomMetadata
+/// ::= /* empty */
+/// ::= !dbg !42
+bool LLParser::ParseOptionalCustomMetadata() {
+
+ std::string Name;
+ if (Lex.getKind() == lltok::NamedOrCustomMD) {
+ Name = Lex.getStrVal();
+ Lex.Lex();
+ } else
+ return false;
+
+ if (Lex.getKind() != lltok::Metadata)
+ return TokError("Expected '!' here");
+ Lex.Lex();
+
+ MetadataBase *Node;
+ if (ParseMDNode(Node)) return true;
+
+ MetadataContext &TheMetadata = M->getContext().getMetadata();
+ unsigned MDK = TheMetadata.getMDKind(Name.c_str());
+ if (!MDK)
+ MDK = TheMetadata.RegisterMDKind(Name.c_str());
+ MDsOnInst.push_back(std::make_pair(MDK, cast<MDNode>(Node)));
+
+ return false;
+}
+
/// ParseOptionalAlignment
/// ::= /* empty */
/// ::= 'align' 4
@@ -1029,29 +1067,36 @@ bool LLParser::ParseOptionalAlignment(unsigned &Alignment) {
return false;
}
-/// ParseOptionalCommaAlignment
-/// ::= /* empty */
-/// ::= ',' 'align' 4
-bool LLParser::ParseOptionalCommaAlignment(unsigned &Alignment) {
- Alignment = 0;
- if (!EatIfPresent(lltok::comma))
- return false;
- return ParseToken(lltok::kw_align, "expected 'align'") ||
- ParseUInt32(Alignment);
+/// ParseOptionalInfo
+/// ::= OptionalInfo (',' OptionalInfo)+
+bool LLParser::ParseOptionalInfo(unsigned &Alignment) {
+
+ // FIXME: Handle customized metadata info attached with an instruction.
+ do {
+ if (Lex.getKind() == lltok::NamedOrCustomMD) {
+ if (ParseOptionalCustomMetadata()) return true;
+ } else if (Lex.getKind() == lltok::kw_align) {
+ if (ParseOptionalAlignment(Alignment)) return true;
+ } else
+ return true;
+ } while (EatIfPresent(lltok::comma));
+
+ return false;
}
+
/// ParseIndexList
/// ::= (',' uint32)+
bool LLParser::ParseIndexList(SmallVectorImpl<unsigned> &Indices) {
if (Lex.getKind() != lltok::comma)
return TokError("expected ',' as start of index list");
-
+
while (EatIfPresent(lltok::comma)) {
unsigned Idx;
if (ParseUInt32(Idx)) return true;
Indices.push_back(Idx);
}
-
+
return false;
}
@@ -1063,14 +1108,14 @@ bool LLParser::ParseIndexList(SmallVectorImpl<unsigned> &Indices) {
bool LLParser::ParseType(PATypeHolder &Result, bool AllowVoid) {
LocTy TypeLoc = Lex.getLoc();
if (ParseTypeRec(Result)) return true;
-
+
// Verify no unresolved uprefs.
if (!UpRefs.empty())
return Error(UpRefs.back().Loc, "invalid unresolved type up reference");
-
+
if (!AllowVoid && Result.get() == Type::getVoidTy(Context))
return Error(TypeLoc, "void type only allowed for function results");
-
+
return false;
}
@@ -1085,26 +1130,26 @@ PATypeHolder LLParser::HandleUpRefs(const Type *ty) {
// If Ty isn't abstract, or if there are no up-references in it, then there is
// nothing to resolve here.
if (!ty->isAbstract() || UpRefs.empty()) return ty;
-
+
PATypeHolder Ty(ty);
#if 0
errs() << "Type '" << Ty->getDescription()
<< "' newly formed. Resolving upreferences.\n"
<< UpRefs.size() << " upreferences active!\n";
#endif
-
+
// If we find any resolvable upreferences (i.e., those whose NestingLevel goes
// to zero), we resolve them all together before we resolve them to Ty. At
// the end of the loop, if there is anything to resolve to Ty, it will be in
// this variable.
OpaqueType *TypeToResolve = 0;
-
+
for (unsigned i = 0; i != UpRefs.size(); ++i) {
// Determine if 'Ty' directly contains this up-references 'LastContainedTy'.
bool ContainsType =
std::find(Ty->subtype_begin(), Ty->subtype_end(),
UpRefs[i].LastContainedTy) != Ty->subtype_end();
-
+
#if 0
errs() << " UR#" << i << " - TypeContains(" << Ty->getDescription() << ", "
<< UpRefs[i].LastContainedTy->getDescription() << ") = "
@@ -1113,15 +1158,15 @@ PATypeHolder LLParser::HandleUpRefs(const Type *ty) {
#endif
if (!ContainsType)
continue;
-
+
// Decrement level of upreference
unsigned Level = --UpRefs[i].NestingLevel;
UpRefs[i].LastContainedTy = Ty;
-
+
// If the Up-reference has a non-zero level, it shouldn't be resolved yet.
if (Level != 0)
continue;
-
+
#if 0
errs() << " * Resolving upreference for " << UpRefs[i].UpRefTy << "\n";
#endif
@@ -1132,10 +1177,10 @@ PATypeHolder LLParser::HandleUpRefs(const Type *ty) {
UpRefs.erase(UpRefs.begin()+i); // Remove from upreference list.
--i; // Do not skip the next element.
}
-
+
if (TypeToResolve)
TypeToResolve->refineAbstractTypeTo(Ty);
-
+
return Ty;
}
@@ -1149,7 +1194,7 @@ bool LLParser::ParseTypeRec(PATypeHolder &Result) {
case lltok::Type:
// TypeRec ::= 'float' | 'void' (etc)
Result = Lex.getTyVal();
- Lex.Lex();
+ Lex.Lex();
break;
case lltok::kw_opaque:
// TypeRec ::= 'opaque'
@@ -1191,7 +1236,7 @@ bool LLParser::ParseTypeRec(PATypeHolder &Result) {
}
Lex.Lex();
break;
-
+
case lltok::LocalVarID:
// TypeRec ::= %4
if (Lex.getUIntVal() < NumberedTypes.size())
@@ -1221,12 +1266,12 @@ bool LLParser::ParseTypeRec(PATypeHolder &Result) {
break;
}
}
-
- // Parse the type suffixes.
+
+ // Parse the type suffixes.
while (1) {
switch (Lex.getKind()) {
// End of type.
- default: return false;
+ default: return false;
// TypeRec ::= TypeRec '*'
case lltok::star:
@@ -1256,7 +1301,7 @@ bool LLParser::ParseTypeRec(PATypeHolder &Result) {
Result = HandleUpRefs(PointerType::get(Result.get(), AddrSpace));
break;
}
-
+
/// Types '(' ArgTypeListI ')' OptFuncAttrs
case lltok::lparen:
if (ParseFunctionType(Result))
@@ -1275,13 +1320,13 @@ bool LLParser::ParseParameterList(SmallVectorImpl<ParamInfo> &ArgList,
PerFunctionState &PFS) {
if (ParseToken(lltok::lparen, "expected '(' in call"))
return true;
-
+
while (Lex.getKind() != lltok::rparen) {
// If this isn't the first argument, we need a comma.
if (!ArgList.empty() &&
ParseToken(lltok::comma, "expected ',' in argument list"))
return true;
-
+
// Parse the argument.
LocTy ArgLoc;
PATypeHolder ArgTy(Type::getVoidTy(Context));
@@ -1317,7 +1362,7 @@ bool LLParser::ParseArgumentList(std::vector<ArgInfo> &ArgList,
isVarArg = false;
assert(Lex.getKind() == lltok::lparen);
Lex.Lex(); // eat the (.
-
+
if (Lex.getKind() == lltok::rparen) {
// empty
} else if (Lex.getKind() == lltok::dotdotdot) {
@@ -1328,16 +1373,16 @@ bool LLParser::ParseArgumentList(std::vector<ArgInfo> &ArgList,
PATypeHolder ArgTy(Type::getVoidTy(Context));
unsigned Attrs;
std::string Name;
-
+
// If we're parsing a type, use ParseTypeRec, because we allow recursive
// types (such as a function returning a pointer to itself). If parsing a
// function prototype, we require fully resolved types.
if ((inType ? ParseTypeRec(ArgTy) : ParseType(ArgTy)) ||
ParseOptionalAttrs(Attrs, 0)) return true;
-
+
if (ArgTy == Type::getVoidTy(Context))
return Error(TypeLoc, "argument can not have void type");
-
+
if (Lex.getKind() == lltok::LocalVar ||
Lex.getKind() == lltok::StringConstant) { // FIXME: REMOVE IN LLVM 3.0
Name = Lex.getStrVal();
@@ -1346,16 +1391,16 @@ bool LLParser::ParseArgumentList(std::vector<ArgInfo> &ArgList,
if (!FunctionType::isValidArgumentType(ArgTy))
return Error(TypeLoc, "invalid type for function argument");
-
+
ArgList.push_back(ArgInfo(TypeLoc, ArgTy, Attrs, Name));
-
+
while (EatIfPresent(lltok::comma)) {
// Handle ... at end of arg list.
if (EatIfPresent(lltok::dotdotdot)) {
isVarArg = true;
break;
}
-
+
// Otherwise must be an argument type.
TypeLoc = Lex.getLoc();
if ((inType ? ParseTypeRec(ArgTy) : ParseType(ArgTy)) ||
@@ -1374,14 +1419,14 @@ bool LLParser::ParseArgumentList(std::vector<ArgInfo> &ArgList,
if (!ArgTy->isFirstClassType() && !isa<OpaqueType>(ArgTy))
return Error(TypeLoc, "invalid type for function argument");
-
+
ArgList.push_back(ArgInfo(TypeLoc, ArgTy, Attrs, Name));
}
}
-
+
return ParseToken(lltok::rparen, "expected ')' at end of argument list");
}
-
+
/// ParseFunctionType
/// ::= Type ArgumentList OptionalAttrs
bool LLParser::ParseFunctionType(PATypeHolder &Result) {
@@ -1389,7 +1434,7 @@ bool LLParser::ParseFunctionType(PATypeHolder &Result) {
if (!FunctionType::isValidReturnType(Result))
return TokError("invalid function return type");
-
+
std::vector<ArgInfo> ArgList;
bool isVarArg;
unsigned Attrs;
@@ -1398,7 +1443,7 @@ bool LLParser::ParseFunctionType(PATypeHolder &Result) {
// FIXME: Remove in LLVM 3.0
ParseOptionalAttrs(Attrs, 2))
return true;
-
+
// Reject names on the arguments lists.
for (unsigned i = 0, e = ArgList.size(); i != e; ++i) {
if (!ArgList[i].Name.empty())
@@ -1409,11 +1454,11 @@ bool LLParser::ParseFunctionType(PATypeHolder &Result) {
// FIXME: REJECT ATTRIBUTES ON FUNCTION TYPES in LLVM 3.0
}
}
-
+
std::vector<const Type*> ArgListTy;
for (unsigned i = 0, e = ArgList.size(); i != e; ++i)
ArgListTy.push_back(ArgList[i].Type);
-
+
Result = HandleUpRefs(FunctionType::get(Result.get(),
ArgListTy, isVarArg));
return false;
@@ -1428,7 +1473,7 @@ bool LLParser::ParseFunctionType(PATypeHolder &Result) {
bool LLParser::ParseStructType(PATypeHolder &Result, bool Packed) {
assert(Lex.getKind() == lltok::lbrace);
Lex.Lex(); // Consume the '{'
-
+
if (EatIfPresent(lltok::rbrace)) {
Result = StructType::get(Context, Packed);
return false;
@@ -1438,27 +1483,27 @@ bool LLParser::ParseStructType(PATypeHolder &Result, bool Packed) {
LocTy EltTyLoc = Lex.getLoc();
if (ParseTypeRec(Result)) return true;
ParamsList.push_back(Result);
-
+
if (Result == Type::getVoidTy(Context))
return Error(EltTyLoc, "struct element can not have void type");
if (!StructType::isValidElementType(Result))
return Error(EltTyLoc, "invalid element type for struct");
-
+
while (EatIfPresent(lltok::comma)) {
EltTyLoc = Lex.getLoc();
if (ParseTypeRec(Result)) return true;
-
+
if (Result == Type::getVoidTy(Context))
return Error(EltTyLoc, "struct element can not have void type");
if (!StructType::isValidElementType(Result))
return Error(EltTyLoc, "invalid element type for struct");
-
+
ParamsList.push_back(Result);
}
-
+
if (ParseToken(lltok::rbrace, "expected '}' at end of struct"))
return true;
-
+
std::vector<const Type*> ParamsListTy;
for (unsigned i = 0, e = ParamsList.size(); i != e; ++i)
ParamsListTy.push_back(ParamsList[i].get());
@@ -1468,32 +1513,32 @@ bool LLParser::ParseStructType(PATypeHolder &Result, bool Packed) {
/// ParseArrayVectorType - Parse an array or vector type, assuming the first
/// token has already been consumed.
-/// TypeRec
+/// TypeRec
/// ::= '[' APSINTVAL 'x' Types ']'
/// ::= '<' APSINTVAL 'x' Types '>'
bool LLParser::ParseArrayVectorType(PATypeHolder &Result, bool isVector) {
if (Lex.getKind() != lltok::APSInt || Lex.getAPSIntVal().isSigned() ||
Lex.getAPSIntVal().getBitWidth() > 64)
return TokError("expected number in address space");
-
+
LocTy SizeLoc = Lex.getLoc();
uint64_t Size = Lex.getAPSIntVal().getZExtValue();
Lex.Lex();
-
+
if (ParseToken(lltok::kw_x, "expected 'x' after element count"))
return true;
LocTy TypeLoc = Lex.getLoc();
PATypeHolder EltTy(Type::getVoidTy(Context));
if (ParseTypeRec(EltTy)) return true;
-
+
if (EltTy == Type::getVoidTy(Context))
return Error(TypeLoc, "array and vector element type cannot be void");
if (ParseToken(isVector ? lltok::greater : lltok::rsquare,
"expected end of sequential type"))
return true;
-
+
if (isVector) {
if (Size == 0)
return Error(SizeLoc, "zero element vector is illegal");
@@ -1534,7 +1579,7 @@ LLParser::PerFunctionState::~PerFunctionState() {
delete I->second.first;
I->second.first = 0;
}
-
+
for (std::map<unsigned, std::pair<Value*, LocTy> >::iterator
I = ForwardRefValIDs.begin(), E = ForwardRefValIDs.end(); I != E; ++I)
if (!isa<BasicBlock>(I->second.first)) {
@@ -1565,7 +1610,7 @@ Value *LLParser::PerFunctionState::GetVal(const std::string &Name,
const Type *Ty, LocTy Loc) {
// Look this name up in the normal function symbol table.
Value *Val = F.getValueSymbolTable().lookup(Name);
-
+
// If this is a forward reference for the value, see if we already created a
// forward ref record.
if (Val == 0) {
@@ -1574,7 +1619,7 @@ Value *LLParser::PerFunctionState::GetVal(const std::string &Name,
if (I != ForwardRefVals.end())
Val = I->second.first;
}
-
+
// If we have the value in the symbol table or fwd-ref table, return it.
if (Val) {
if (Val->getType() == Ty) return Val;
@@ -1585,21 +1630,21 @@ Value *LLParser::PerFunctionState::GetVal(const std::string &Name,
Val->getType()->getDescription() + "'");
return 0;
}
-
+
// Don't make placeholders with invalid type.
if (!Ty->isFirstClassType() && !isa<OpaqueType>(Ty) &&
Ty != Type::getLabelTy(F.getContext())) {
P.Error(Loc, "invalid use of a non-first-class type");
return 0;
}
-
+
// Otherwise, create a new forward reference for this value and remember it.
Value *FwdVal;
- if (Ty == Type::getLabelTy(F.getContext()))
+ if (Ty == Type::getLabelTy(F.getContext()))
FwdVal = BasicBlock::Create(F.getContext(), Name, &F);
else
FwdVal = new Argument(Ty, Name);
-
+
ForwardRefVals[Name] = std::make_pair(FwdVal, Loc);
return FwdVal;
}
@@ -1608,7 +1653,7 @@ Value *LLParser::PerFunctionState::GetVal(unsigned ID, const Type *Ty,
LocTy Loc) {
// Look this name up in the normal function symbol table.
Value *Val = ID < NumberedVals.size() ? NumberedVals[ID] : 0;
-
+
// If this is a forward reference for the value, see if we already created a
// forward ref record.
if (Val == 0) {
@@ -1617,7 +1662,7 @@ Value *LLParser::PerFunctionState::GetVal(unsigned ID, const Type *Ty,
if (I != ForwardRefValIDs.end())
Val = I->second.first;
}
-
+
// If we have the value in the symbol table or fwd-ref table, return it.
if (Val) {
if (Val->getType() == Ty) return Val;
@@ -1628,20 +1673,20 @@ Value *LLParser::PerFunctionState::GetVal(unsigned ID, const Type *Ty,
Val->getType()->getDescription() + "'");
return 0;
}
-
+
if (!Ty->isFirstClassType() && !isa<OpaqueType>(Ty) &&
Ty != Type::getLabelTy(F.getContext())) {
P.Error(Loc, "invalid use of a non-first-class type");
return 0;
}
-
+
// Otherwise, create a new forward reference for this value and remember it.
Value *FwdVal;
- if (Ty == Type::getLabelTy(F.getContext()))
+ if (Ty == Type::getLabelTy(F.getContext()))
FwdVal = BasicBlock::Create(F.getContext(), "", &F);
else
FwdVal = new Argument(Ty);
-
+
ForwardRefValIDs[ID] = std::make_pair(FwdVal, Loc);
return FwdVal;
}
@@ -1657,25 +1702,26 @@ bool LLParser::PerFunctionState::SetInstName(int NameID,
return P.Error(NameLoc, "instructions returning void cannot have a name");
return false;
}
-
+
// If this was a numbered instruction, verify that the instruction is the
// expected value and resolve any forward references.
if (NameStr.empty()) {
// If neither a name nor an ID was specified, just use the next ID.
if (NameID == -1)
NameID = NumberedVals.size();
-
+
if (unsigned(NameID) != NumberedVals.size())
return P.Error(NameLoc, "instruction expected to be numbered '%" +
utostr(NumberedVals.size()) + "'");
-
+
std::map<unsigned, std::pair<Value*, LocTy> >::iterator FI =
ForwardRefValIDs.find(NameID);
if (FI != ForwardRefValIDs.end()) {
if (FI->second.first->getType() != Inst->getType())
- return P.Error(NameLoc, "instruction forward referenced with type '" +
+ return P.Error(NameLoc, "instruction forward referenced with type '" +
FI->second.first->getType()->getDescription() + "'");
FI->second.first->replaceAllUsesWith(Inst);
+ delete FI->second.first;
ForwardRefValIDs.erase(FI);
}
@@ -1688,17 +1734,18 @@ bool LLParser::PerFunctionState::SetInstName(int NameID,
FI = ForwardRefVals.find(NameStr);
if (FI != ForwardRefVals.end()) {
if (FI->second.first->getType() != Inst->getType())
- return P.Error(NameLoc, "instruction forward referenced with type '" +
+ return P.Error(NameLoc, "instruction forward referenced with type '" +
FI->second.first->getType()->getDescription() + "'");
FI->second.first->replaceAllUsesWith(Inst);
+ delete FI->second.first;
ForwardRefVals.erase(FI);
}
-
+
// Set the name on the instruction.
Inst->setName(NameStr);
-
+
if (Inst->getNameStr() != NameStr)
- return P.Error(NameLoc, "multiple definition of local value named '" +
+ return P.Error(NameLoc, "multiple definition of local value named '" +
NameStr + "'");
return false;
}
@@ -1727,11 +1774,11 @@ BasicBlock *LLParser::PerFunctionState::DefineBB(const std::string &Name,
else
BB = GetBB(Name, Loc);
if (BB == 0) return 0; // Already diagnosed error.
-
+
// Move the block to the end of the function. Forward ref'd blocks are
// inserted wherever they happen to be referenced.
F.getBasicBlockList().splice(F.end(), F.getBasicBlockList(), BB);
-
+
// Remove the block from forward ref sets.
if (Name.empty()) {
ForwardRefValIDs.erase(NumberedVals.size());
@@ -1740,7 +1787,7 @@ BasicBlock *LLParser::PerFunctionState::DefineBB(const std::string &Name,
// BB forward references are already in the function symbol table.
ForwardRefVals.erase(Name);
}
-
+
return BB;
}
@@ -1798,7 +1845,7 @@ bool LLParser::ParseValID(ValID &ID) {
return false;
}
case lltok::APSInt:
- ID.APSIntVal = Lex.getAPSIntVal();
+ ID.APSIntVal = Lex.getAPSIntVal();
ID.Kind = ValID::t_APSInt;
break;
case lltok::APFloat:
@@ -1816,7 +1863,7 @@ bool LLParser::ParseValID(ValID &ID) {
case lltok::kw_null: ID.Kind = ValID::t_Null; break;
case lltok::kw_undef: ID.Kind = ValID::t_Undef; break;
case lltok::kw_zeroinitializer: ID.Kind = ValID::t_Zero; break;
-
+
case lltok::lbrace: {
// ValID ::= '{' ConstVector '}'
Lex.Lex();
@@ -1824,7 +1871,7 @@ bool LLParser::ParseValID(ValID &ID) {
if (ParseGlobalValueVector(Elts) ||
ParseToken(lltok::rbrace, "expected end of struct constant"))
return true;
-
+
ID.ConstantVal = ConstantStruct::get(Context, Elts.data(),
Elts.size(), false);
ID.Kind = ValID::t_Constant;
@@ -1835,7 +1882,7 @@ bool LLParser::ParseValID(ValID &ID) {
// ValID ::= '<' '{' ConstVector '}' '>' --> Packed Struct.
Lex.Lex();
bool isPackedStruct = EatIfPresent(lltok::lbrace);
-
+
SmallVector<Constant*, 16> Elts;
LocTy FirstEltLoc = Lex.getLoc();
if (ParseGlobalValueVector(Elts) ||
@@ -1843,14 +1890,14 @@ bool LLParser::ParseValID(ValID &ID) {
ParseToken(lltok::rbrace, "expected end of packed struct")) ||
ParseToken(lltok::greater, "expected end of constant"))
return true;
-
+
if (isPackedStruct) {
ID.ConstantVal =
ConstantStruct::get(Context, Elts.data(), Elts.size(), true);
ID.Kind = ValID::t_Constant;
return false;
}
-
+
if (Elts.empty())
return Error(ID.Loc, "constant vector must not be empty");
@@ -1858,14 +1905,14 @@ bool LLParser::ParseValID(ValID &ID) {
!Elts[0]->getType()->isFloatingPoint())
return Error(FirstEltLoc,
"vector elements must have integer or floating point type");
-
+
// Verify that all the vector elements have the same type.
for (unsigned i = 1, e = Elts.size(); i != e; ++i)
if (Elts[i]->getType() != Elts[0]->getType())
return Error(FirstEltLoc,
"vector element #" + utostr(i) +
" is not of type '" + Elts[0]->getType()->getDescription());
-
+
ID.ConstantVal = ConstantVector::get(Elts.data(), Elts.size());
ID.Kind = ValID::t_Constant;
return false;
@@ -1885,13 +1932,13 @@ bool LLParser::ParseValID(ValID &ID) {
ID.Kind = ValID::t_EmptyArray;
return false;
}
-
+
if (!Elts[0]->getType()->isFirstClassType())
- return Error(FirstEltLoc, "invalid array element type: " +
+ return Error(FirstEltLoc, "invalid array element type: " +
Elts[0]->getType()->getDescription());
-
+
ArrayType *ATy = ArrayType::get(Elts[0]->getType(), Elts.size());
-
+
// Verify all elements are correct type!
for (unsigned i = 0, e = Elts.size(); i != e; ++i) {
if (Elts[i]->getType() != Elts[0]->getType())
@@ -1899,7 +1946,7 @@ bool LLParser::ParseValID(ValID &ID) {
"array element #" + utostr(i) +
" is not of type '" +Elts[0]->getType()->getDescription());
}
-
+
ID.ConstantVal = ConstantArray::get(ATy, Elts.data(), Elts.size());
ID.Kind = ValID::t_Constant;
return false;
@@ -1925,7 +1972,7 @@ bool LLParser::ParseValID(ValID &ID) {
ID.Kind = ValID::t_InlineAsm;
return false;
}
-
+
case lltok::kw_trunc:
case lltok::kw_zext:
case lltok::kw_sext:
@@ -1935,9 +1982,9 @@ bool LLParser::ParseValID(ValID &ID) {
case lltok::kw_uitofp:
case lltok::kw_sitofp:
case lltok::kw_fptoui:
- case lltok::kw_fptosi:
+ case lltok::kw_fptosi:
case lltok::kw_inttoptr:
- case lltok::kw_ptrtoint: {
+ case lltok::kw_ptrtoint: {
unsigned Opc = Lex.getUIntVal();
PATypeHolder DestTy(Type::getVoidTy(Context));
Constant *SrcVal;
@@ -1952,7 +1999,7 @@ bool LLParser::ParseValID(ValID &ID) {
return Error(ID.Loc, "invalid cast opcode for cast from '" +
SrcVal->getType()->getDescription() + "' to '" +
DestTy->getDescription() + "'");
- ID.ConstantVal = ConstantExpr::getCast((Instruction::CastOps)Opc,
+ ID.ConstantVal = ConstantExpr::getCast((Instruction::CastOps)Opc,
SrcVal, DestTy);
ID.Kind = ValID::t_Constant;
return false;
@@ -2009,12 +2056,12 @@ bool LLParser::ParseValID(ValID &ID) {
ParseGlobalTypeAndValue(Val1) ||
ParseToken(lltok::rparen, "expected ')' in compare constantexpr"))
return true;
-
+
if (Val0->getType() != Val1->getType())
return Error(ID.Loc, "compare operands must have the same type");
-
+
CmpInst::Predicate Pred = (CmpInst::Predicate)PredVal;
-
+
if (Opc == Instruction::FCmp) {
if (!Val0->getType()->isFPOrFPVector())
return Error(ID.Loc, "fcmp requires floating point operands");
@@ -2029,7 +2076,7 @@ bool LLParser::ParseValID(ValID &ID) {
ID.Kind = ValID::t_Constant;
return false;
}
-
+
// Binary Operators.
case lltok::kw_add:
case lltok::kw_fadd:
@@ -2083,18 +2130,16 @@ bool LLParser::ParseValID(ValID &ID) {
if (!Val0->getType()->isIntOrIntVector() &&
!Val0->getType()->isFPOrFPVector())
return Error(ID.Loc,"constexpr requires integer, fp, or vector operands");
- Constant *C = ConstantExpr::get(Opc, Val0, Val1);
- if (NUW)
- cast<OverflowingBinaryOperator>(C)->setHasNoUnsignedWrap(true);
- if (NSW)
- cast<OverflowingBinaryOperator>(C)->setHasNoSignedWrap(true);
- if (Exact)
- cast<SDivOperator>(C)->setIsExact(true);
+ unsigned Flags = 0;
+ if (NUW) Flags |= OverflowingBinaryOperator::NoUnsignedWrap;
+ if (NSW) Flags |= OverflowingBinaryOperator::NoSignedWrap;
+ if (Exact) Flags |= SDivOperator::IsExact;
+ Constant *C = ConstantExpr::get(Opc, Val0, Val1, Flags);
ID.ConstantVal = C;
ID.Kind = ValID::t_Constant;
return false;
}
-
+
// Logical Operations
case lltok::kw_shl:
case lltok::kw_lshr:
@@ -2119,8 +2164,8 @@ bool LLParser::ParseValID(ValID &ID) {
ID.ConstantVal = ConstantExpr::get(Opc, Val0, Val1);
ID.Kind = ValID::t_Constant;
return false;
- }
-
+ }
+
case lltok::kw_getelementptr:
case lltok::kw_shufflevector:
case lltok::kw_insertelement:
@@ -2136,19 +2181,21 @@ bool LLParser::ParseValID(ValID &ID) {
ParseGlobalValueVector(Elts) ||
ParseToken(lltok::rparen, "expected ')' in constantexpr"))
return true;
-
+
if (Opc == Instruction::GetElementPtr) {
if (Elts.size() == 0 || !isa<PointerType>(Elts[0]->getType()))
return Error(ID.Loc, "getelementptr requires pointer operand");
-
+
if (!GetElementPtrInst::getIndexedType(Elts[0]->getType(),
(Value**)(Elts.data() + 1),
Elts.size() - 1))
return Error(ID.Loc, "invalid indices for getelementptr");
- ID.ConstantVal = ConstantExpr::getGetElementPtr(Elts[0],
- Elts.data() + 1, Elts.size() - 1);
- if (InBounds)
- cast<GEPOperator>(ID.ConstantVal)->setIsInBounds(true);
+ ID.ConstantVal = InBounds ?
+ ConstantExpr::getInBoundsGetElementPtr(Elts[0],
+ Elts.data() + 1,
+ Elts.size() - 1) :
+ ConstantExpr::getGetElementPtr(Elts[0],
+ Elts.data() + 1, Elts.size() - 1);
} else if (Opc == Instruction::Select) {
if (Elts.size() != 3)
return Error(ID.Loc, "expected three operands to select");
@@ -2178,12 +2225,12 @@ bool LLParser::ParseValID(ValID &ID) {
ID.ConstantVal =
ConstantExpr::getInsertElement(Elts[0], Elts[1],Elts[2]);
}
-
+
ID.Kind = ValID::t_Constant;
return false;
}
}
-
+
Lex.Lex();
return false;
}
@@ -2202,9 +2249,9 @@ bool LLParser::ConvertGlobalValIDToValue(const Type *Ty, ValID &ID,
Constant *&V) {
if (isa<FunctionType>(Ty))
return Error(ID.Loc, "functions are not values, refer to them as pointers");
-
+
switch (ID.Kind) {
- default: llvm_unreachable("Unknown ValID!");
+ default: llvm_unreachable("Unknown ValID!");
case ValID::t_Metadata:
return Error(ID.Loc, "invalid use of metadata");
case ValID::t_LocalID:
@@ -2228,7 +2275,7 @@ bool LLParser::ConvertGlobalValIDToValue(const Type *Ty, ValID &ID,
if (!Ty->isFloatingPoint() ||
!ConstantFP::isValueValidForType(Ty, ID.APFloatVal))
return Error(ID.Loc, "floating point constant invalid for type");
-
+
// The lexer has no type info, so builds all float and double FP constants
// as double. Fix this here. Long double does not need this.
if (&ID.APFloatVal.getSemantics() == &APFloat::IEEEdouble &&
@@ -2238,11 +2285,11 @@ bool LLParser::ConvertGlobalValIDToValue(const Type *Ty, ValID &ID,
&Ignored);
}
V = ConstantFP::get(Context, ID.APFloatVal);
-
+
if (V->getType() != Ty)
return Error(ID.Loc, "floating point constant does not have type '" +
Ty->getDescription() + "'");
-
+
return false;
case ValID::t_Null:
if (!isa<PointerType>(Ty))
@@ -2274,12 +2321,12 @@ bool LLParser::ConvertGlobalValIDToValue(const Type *Ty, ValID &ID,
return false;
}
}
-
+
bool LLParser::ParseGlobalTypeAndValue(Constant *&V) {
PATypeHolder Type(Type::getVoidTy(Context));
return ParseType(Type) ||
ParseGlobalValue(Type, V);
-}
+}
/// ParseGlobalValueVector
/// ::= /*empty*/
@@ -2291,16 +2338,16 @@ bool LLParser::ParseGlobalValueVector(SmallVectorImpl<Constant*> &Elts) {
Lex.getKind() == lltok::greater ||
Lex.getKind() == lltok::rparen)
return false;
-
+
Constant *C;
if (ParseGlobalTypeAndValue(C)) return true;
Elts.push_back(C);
-
+
while (EatIfPresent(lltok::comma)) {
if (ParseGlobalTypeAndValue(C)) return true;
Elts.push_back(C);
}
-
+
return false;
}
@@ -2356,8 +2403,9 @@ bool LLParser::ParseFunctionHeader(Function *&Fn, bool isDefine) {
// Parse the linkage.
LocTy LinkageLoc = Lex.getLoc();
unsigned Linkage;
-
- unsigned Visibility, CC, RetAttrs;
+
+ unsigned Visibility, RetAttrs;
+ CallingConv::ID CC;
PATypeHolder RetType(Type::getVoidTy(Context));
LocTy RetTypeLoc = Lex.getLoc();
if (ParseOptionalLinkage(Linkage) ||
@@ -2393,11 +2441,11 @@ bool LLParser::ParseFunctionHeader(Function *&Fn, bool isDefine) {
case GlobalValue::CommonLinkage:
return Error(LinkageLoc, "invalid function linkage type");
}
-
+
if (!FunctionType::isValidReturnType(RetType) ||
isa<OpaqueType>(RetType))
return Error(RetTypeLoc, "invalid function return type");
-
+
LocTy NameLoc = Lex.getLoc();
std::string FunctionName;
@@ -2412,12 +2460,12 @@ bool LLParser::ParseFunctionHeader(Function *&Fn, bool isDefine) {
} else {
return TokError("expected function name");
}
-
+
Lex.Lex();
-
+
if (Lex.getKind() != lltok::lparen)
return TokError("expected '(' in function argument list");
-
+
std::vector<ArgInfo> ArgList;
bool isVarArg;
unsigned FuncAttrs;
@@ -2439,22 +2487,22 @@ bool LLParser::ParseFunctionHeader(Function *&Fn, bool isDefine) {
Alignment = Attribute::getAlignmentFromAttrs(FuncAttrs);
FuncAttrs &= ~Attribute::Alignment;
}
-
+
// Okay, if we got here, the function is syntactically valid. Convert types
// and do semantic checks.
std::vector<const Type*> ParamTypeList;
SmallVector<AttributeWithIndex, 8> Attrs;
- // FIXME : In 3.0, stop accepting zext, sext and inreg as optional function
+ // FIXME : In 3.0, stop accepting zext, sext and inreg as optional function
// attributes.
unsigned ObsoleteFuncAttrs = Attribute::ZExt|Attribute::SExt|Attribute::InReg;
if (FuncAttrs & ObsoleteFuncAttrs) {
RetAttrs |= FuncAttrs & ObsoleteFuncAttrs;
FuncAttrs &= ~ObsoleteFuncAttrs;
}
-
+
if (RetAttrs != Attribute::None)
Attrs.push_back(AttributeWithIndex::get(0, RetAttrs));
-
+
for (unsigned i = 0, e = ArgList.size(); i != e; ++i) {
ParamTypeList.push_back(ArgList[i].Type);
if (ArgList[i].Attrs != Attribute::None)
@@ -2465,11 +2513,11 @@ bool LLParser::ParseFunctionHeader(Function *&Fn, bool isDefine) {
Attrs.push_back(AttributeWithIndex::get(~0, FuncAttrs));
AttrListPtr PAL = AttrListPtr::get(Attrs.begin(), Attrs.end());
-
+
if (PAL.paramHasAttr(1, Attribute::StructRet) &&
RetType != Type::getVoidTy(Context))
- return Error(RetTypeLoc, "functions with 'sret' argument must return void");
-
+ return Error(RetTypeLoc, "functions with 'sret' argument must return void");
+
const FunctionType *FT =
FunctionType::get(RetType, ParamTypeList, isVarArg);
const PointerType *PFT = PointerType::getUnqual(FT);
@@ -2500,7 +2548,7 @@ bool LLParser::ParseFunctionHeader(Function *&Fn, bool isDefine) {
AI->setName("");
}
}
-
+
} else {
// If this is a definition of a forward referenced function, make sure the
// types agree.
@@ -2522,7 +2570,7 @@ bool LLParser::ParseFunctionHeader(Function *&Fn, bool isDefine) {
if (FunctionName.empty())
NumberedVals.push_back(Fn);
-
+
Fn->setLinkage((GlobalValue::LinkageTypes)Linkage);
Fn->setVisibility((GlobalValue::VisibilityTypes)Visibility);
Fn->setCallingConv(CC);
@@ -2530,21 +2578,21 @@ bool LLParser::ParseFunctionHeader(Function *&Fn, bool isDefine) {
Fn->setAlignment(Alignment);
Fn->setSection(Section);
if (!GC.empty()) Fn->setGC(GC.c_str());
-
+
// Add all of the arguments we parsed to the function.
Function::arg_iterator ArgIt = Fn->arg_begin();
for (unsigned i = 0, e = ArgList.size(); i != e; ++i, ++ArgIt) {
// If the argument has a name, insert it into the argument symbol table.
if (ArgList[i].Name.empty()) continue;
-
+
// Set the name, if it conflicted, it will be auto-renamed.
ArgIt->setName(ArgList[i].Name);
-
+
if (ArgIt->getNameStr() != ArgList[i].Name)
return Error(ArgList[i].Loc, "redefinition of argument '%" +
ArgList[i].Name + "'");
}
-
+
return false;
}
@@ -2557,15 +2605,15 @@ bool LLParser::ParseFunctionBody(Function &Fn) {
if (Lex.getKind() != lltok::lbrace && Lex.getKind() != lltok::kw_begin)
return TokError("expected '{' in function body");
Lex.Lex(); // eat the {.
-
+
PerFunctionState PFS(*this, Fn);
-
+
while (Lex.getKind() != lltok::rbrace && Lex.getKind() != lltok::kw_end)
if (ParseBasicBlock(PFS)) return true;
-
+
// Eat the }.
Lex.Lex();
-
+
// Verify function is ok.
return PFS.VerifyFunctionComplete();
}
@@ -2580,12 +2628,12 @@ bool LLParser::ParseBasicBlock(PerFunctionState &PFS) {
Name = Lex.getStrVal();
Lex.Lex();
}
-
+
BasicBlock *BB = PFS.DefineBB(Name, NameLoc);
if (BB == 0) return true;
-
+
std::string NameStr;
-
+
// Parse the instructions in this block until we get a terminator.
Instruction *Inst;
do {
@@ -2594,7 +2642,7 @@ bool LLParser::ParseBasicBlock(PerFunctionState &PFS) {
LocTy NameLoc = Lex.getLoc();
int NameID = -1;
NameStr = "";
-
+
if (Lex.getKind() == lltok::LocalVarID) {
NameID = Lex.getUIntVal();
Lex.Lex();
@@ -2608,15 +2656,24 @@ bool LLParser::ParseBasicBlock(PerFunctionState &PFS) {
if (ParseToken(lltok::equal, "expected '=' after instruction name"))
return true;
}
-
+
if (ParseInstruction(Inst, BB, PFS)) return true;
-
+ if (EatIfPresent(lltok::comma))
+ ParseOptionalCustomMetadata();
+
+ // Set metadata attached with this instruction.
+ MetadataContext &TheMetadata = M->getContext().getMetadata();
+ for (SmallVector<std::pair<unsigned, MDNode *>, 2>::iterator
+ MDI = MDsOnInst.begin(), MDE = MDsOnInst.end(); MDI != MDE; ++MDI)
+ TheMetadata.addMD(MDI->first, MDI->second, Inst);
+ MDsOnInst.clear();
+
BB->getInstList().push_back(Inst);
// Set the name on the instruction.
if (PFS.SetInstName(NameID, NameStr, NameLoc, Inst)) return true;
} while (!isa<TerminatorInst>(Inst));
-
+
return false;
}
@@ -2634,7 +2691,7 @@ bool LLParser::ParseInstruction(Instruction *&Inst, BasicBlock *BB,
LocTy Loc = Lex.getLoc();
unsigned KeywordVal = Lex.getUIntVal();
Lex.Lex(); // Eat the keyword.
-
+
switch (Token) {
default: return Error(Loc, "expected instruction opcode");
// Terminator Instructions.
@@ -2668,9 +2725,9 @@ bool LLParser::ParseInstruction(Instruction *&Inst, BasicBlock *BB,
return Error(ModifierLoc, "nsw only applies to integer operations");
}
if (NUW)
- cast<OverflowingBinaryOperator>(Inst)->setHasNoUnsignedWrap(true);
+ cast<BinaryOperator>(Inst)->setHasNoUnsignedWrap(true);
if (NSW)
- cast<OverflowingBinaryOperator>(Inst)->setHasNoSignedWrap(true);
+ cast<BinaryOperator>(Inst)->setHasNoSignedWrap(true);
}
return Result;
}
@@ -2685,7 +2742,7 @@ bool LLParser::ParseInstruction(Instruction *&Inst, BasicBlock *BB,
bool Result = ParseArithmetic(Inst, PFS, KeywordVal, 1);
if (!Result)
if (Exact)
- cast<SDivOperator>(Inst)->setIsExact(true);
+ cast<BinaryOperator>(Inst)->setIsExact(true);
return Result;
}
@@ -2712,7 +2769,7 @@ bool LLParser::ParseInstruction(Instruction *&Inst, BasicBlock *BB,
case lltok::kw_uitofp:
case lltok::kw_sitofp:
case lltok::kw_fptoui:
- case lltok::kw_fptosi:
+ case lltok::kw_fptosi:
case lltok::kw_inttoptr:
case lltok::kw_ptrtoint: return ParseCast(Inst, PFS, KeywordVal);
// Other.
@@ -2790,41 +2847,56 @@ bool LLParser::ParseCmpPredicate(unsigned &P, unsigned Opc) {
//===----------------------------------------------------------------------===//
/// ParseRet - Parse a return instruction.
-/// ::= 'ret' void
-/// ::= 'ret' TypeAndValue
-/// ::= 'ret' TypeAndValue (',' TypeAndValue)+ [[obsolete: LLVM 3.0]]
+/// ::= 'ret' void (',' !dbg, !1)
+/// ::= 'ret' TypeAndValue (',' !dbg, !1)
+/// ::= 'ret' TypeAndValue (',' TypeAndValue)+ (',' !dbg, !1)
+/// [[obsolete: LLVM 3.0]]
bool LLParser::ParseRet(Instruction *&Inst, BasicBlock *BB,
PerFunctionState &PFS) {
PATypeHolder Ty(Type::getVoidTy(Context));
if (ParseType(Ty, true /*void allowed*/)) return true;
-
+
if (Ty == Type::getVoidTy(Context)) {
+ if (EatIfPresent(lltok::comma))
+ if (ParseOptionalCustomMetadata()) return true;
Inst = ReturnInst::Create(Context);
return false;
}
-
+
Value *RV;
if (ParseValue(Ty, RV, PFS)) return true;
-
- // The normal case is one return value.
- if (Lex.getKind() == lltok::comma) {
- // FIXME: LLVM 3.0 remove MRV support for 'ret i32 1, i32 2', requiring use
- // of 'ret {i32,i32} {i32 1, i32 2}'
- SmallVector<Value*, 8> RVs;
- RVs.push_back(RV);
-
- while (EatIfPresent(lltok::comma)) {
- if (ParseTypeAndValue(RV, PFS)) return true;
+
+ if (EatIfPresent(lltok::comma)) {
+ // Parse optional custom metadata, e.g. !dbg
+ if (Lex.getKind() == lltok::NamedOrCustomMD) {
+ if (ParseOptionalCustomMetadata()) return true;
+ } else {
+ // The normal case is one return value.
+ // FIXME: LLVM 3.0 remove MRV support for 'ret i32 1, i32 2', requiring use
+ // of 'ret {i32,i32} {i32 1, i32 2}'
+ SmallVector<Value*, 8> RVs;
RVs.push_back(RV);
- }
- RV = UndefValue::get(PFS.getFunction().getReturnType());
- for (unsigned i = 0, e = RVs.size(); i != e; ++i) {
- Instruction *I = InsertValueInst::Create(RV, RVs[i], i, "mrv");
- BB->getInstList().push_back(I);
- RV = I;
+ do {
+ // If optional custom metadata, e.g. !dbg is seen then this is the
+ // end of MRV.
+ if (Lex.getKind() == lltok::NamedOrCustomMD)
+ break;
+ if (ParseTypeAndValue(RV, PFS)) return true;
+ RVs.push_back(RV);
+ } while (EatIfPresent(lltok::comma));
+
+ RV = UndefValue::get(PFS.getFunction().getReturnType());
+ for (unsigned i = 0, e = RVs.size(); i != e; ++i) {
+ Instruction *I = InsertValueInst::Create(RV, RVs[i], i, "mrv");
+ BB->getInstList().push_back(I);
+ RV = I;
+ }
}
}
+ if (EatIfPresent(lltok::comma))
+ if (ParseOptionalCustomMetadata()) return true;
+
Inst = ReturnInst::Create(Context, RV);
return false;
}
@@ -2837,26 +2909,26 @@ bool LLParser::ParseBr(Instruction *&Inst, PerFunctionState &PFS) {
LocTy Loc, Loc2;
Value *Op0, *Op1, *Op2;
if (ParseTypeAndValue(Op0, Loc, PFS)) return true;
-
+
if (BasicBlock *BB = dyn_cast<BasicBlock>(Op0)) {
Inst = BranchInst::Create(BB);
return false;
}
-
+
if (Op0->getType() != Type::getInt1Ty(Context))
return Error(Loc, "branch condition must have 'i1' type");
-
+
if (ParseToken(lltok::comma, "expected ',' after branch condition") ||
ParseTypeAndValue(Op1, Loc, PFS) ||
ParseToken(lltok::comma, "expected ',' after true destination") ||
ParseTypeAndValue(Op2, Loc2, PFS))
return true;
-
+
if (!isa<BasicBlock>(Op1))
return Error(Loc, "true destination of branch must be a basic block");
if (!isa<BasicBlock>(Op2))
return Error(Loc2, "true destination of branch must be a basic block");
-
+
Inst = BranchInst::Create(cast<BasicBlock>(Op1), cast<BasicBlock>(Op2), Op0);
return false;
}
@@ -2879,13 +2951,13 @@ bool LLParser::ParseSwitch(Instruction *&Inst, PerFunctionState &PFS) {
return Error(CondLoc, "switch condition must have integer type");
if (!isa<BasicBlock>(DefaultBB))
return Error(BBLoc, "default destination must be a basic block");
-
+
// Parse the jump table pairs.
SmallPtrSet<Value*, 32> SeenCases;
SmallVector<std::pair<ConstantInt*, BasicBlock*>, 32> Table;
while (Lex.getKind() != lltok::rsquare) {
Value *Constant, *DestBB;
-
+
if (ParseTypeAndValue(Constant, CondLoc, PFS) ||
ParseToken(lltok::comma, "expected ',' after case value") ||
ParseTypeAndValue(DestBB, BBLoc, PFS))
@@ -2897,13 +2969,13 @@ bool LLParser::ParseSwitch(Instruction *&Inst, PerFunctionState &PFS) {
return Error(CondLoc, "case value is not a constant integer");
if (!isa<BasicBlock>(DestBB))
return Error(BBLoc, "case destination is not a basic block");
-
+
Table.push_back(std::make_pair(cast<ConstantInt>(Constant),
cast<BasicBlock>(DestBB)));
}
-
+
Lex.Lex(); // Eat the ']'.
-
+
SwitchInst *SI = SwitchInst::Create(Cond, cast<BasicBlock>(DefaultBB),
Table.size());
for (unsigned i = 0, e = Table.size(); i != e; ++i)
@@ -2917,7 +2989,8 @@ bool LLParser::ParseSwitch(Instruction *&Inst, PerFunctionState &PFS) {
/// OptionalAttrs 'to' TypeAndValue 'unwind' TypeAndValue
bool LLParser::ParseInvoke(Instruction *&Inst, PerFunctionState &PFS) {
LocTy CallLoc = Lex.getLoc();
- unsigned CC, RetAttrs, FnAttrs;
+ unsigned RetAttrs, FnAttrs;
+ CallingConv::ID CC;
PATypeHolder RetType(Type::getVoidTy(Context));
LocTy RetTypeLoc;
ValID CalleeID;
@@ -2935,12 +3008,12 @@ bool LLParser::ParseInvoke(Instruction *&Inst, PerFunctionState &PFS) {
ParseToken(lltok::kw_unwind, "expected 'unwind' in invoke") ||
ParseTypeAndValue(UnwindBB, PFS))
return true;
-
+
if (!isa<BasicBlock>(NormalBB))
return Error(CallLoc, "normal destination is not a basic block");
if (!isa<BasicBlock>(UnwindBB))
return Error(CallLoc, "unwind destination is not a basic block");
-
+
// If RetType is a non-function pointer type, then this is the short syntax
// for the call, which means that RetType is just the return type. Infer the
// rest of the function argument types from the arguments that are present.
@@ -2952,18 +3025,18 @@ bool LLParser::ParseInvoke(Instruction *&Inst, PerFunctionState &PFS) {
std::vector<const Type*> ParamTypes;
for (unsigned i = 0, e = ArgList.size(); i != e; ++i)
ParamTypes.push_back(ArgList[i].V->getType());
-
+
if (!FunctionType::isValidReturnType(RetType))
return Error(RetTypeLoc, "Invalid result type for LLVM function");
-
+
Ty = FunctionType::get(RetType, ParamTypes, false);
PFTy = PointerType::getUnqual(Ty);
}
-
+
// Look up the callee.
Value *Callee;
if (ConvertValIDToValue(PFTy, CalleeID, Callee, PFS)) return true;
-
+
// FIXME: In LLVM 3.0, stop accepting zext, sext and inreg as optional
// function attributes.
unsigned ObsoleteFuncAttrs = Attribute::ZExt|Attribute::SExt|Attribute::InReg;
@@ -2971,14 +3044,14 @@ bool LLParser::ParseInvoke(Instruction *&Inst, PerFunctionState &PFS) {
RetAttrs |= FnAttrs & ObsoleteFuncAttrs;
FnAttrs &= ~ObsoleteFuncAttrs;
}
-
+
// Set up the Attributes for the function.
SmallVector<AttributeWithIndex, 8> Attrs;
if (RetAttrs != Attribute::None)
Attrs.push_back(AttributeWithIndex::get(0, RetAttrs));
-
+
SmallVector<Value*, 8> Args;
-
+
// Loop through FunctionType's arguments and ensure they are specified
// correctly. Also, gather any parameter attributes.
FunctionType::param_iterator I = Ty->param_begin();
@@ -2990,7 +3063,7 @@ bool LLParser::ParseInvoke(Instruction *&Inst, PerFunctionState &PFS) {
} else if (!Ty->isVarArg()) {
return Error(ArgList[i].Loc, "too many arguments specified");
}
-
+
if (ExpectedTy && ExpectedTy != ArgList[i].V->getType())
return Error(ArgList[i].Loc, "argument is not of expected type '" +
ExpectedTy->getDescription() + "'");
@@ -2998,16 +3071,16 @@ bool LLParser::ParseInvoke(Instruction *&Inst, PerFunctionState &PFS) {
if (ArgList[i].Attrs != Attribute::None)
Attrs.push_back(AttributeWithIndex::get(i+1, ArgList[i].Attrs));
}
-
+
if (I != E)
return Error(CallLoc, "not enough parameters specified for call");
-
+
if (FnAttrs != Attribute::None)
Attrs.push_back(AttributeWithIndex::get(~0, FnAttrs));
-
+
// Finish off the Attributes and check them
AttrListPtr PAL = AttrListPtr::get(Attrs.begin(), Attrs.end());
-
+
InvokeInst *II = InvokeInst::Create(Callee, cast<BasicBlock>(NormalBB),
cast<BasicBlock>(UnwindBB),
Args.begin(), Args.end());
@@ -3046,10 +3119,10 @@ bool LLParser::ParseArithmetic(Instruction *&Inst, PerFunctionState &PFS,
case 1: Valid = LHS->getType()->isIntOrIntVector(); break;
case 2: Valid = LHS->getType()->isFPOrFPVector(); break;
}
-
+
if (!Valid)
return Error(Loc, "invalid operand type for instruction");
-
+
Inst = BinaryOperator::Create((Instruction::BinaryOps)Opc, LHS, RHS);
return false;
}
@@ -3086,7 +3159,7 @@ bool LLParser::ParseCompare(Instruction *&Inst, PerFunctionState &PFS,
ParseToken(lltok::comma, "expected ',' after compare value") ||
ParseValue(LHS->getType(), RHS, PFS))
return true;
-
+
if (Opc == Instruction::FCmp) {
if (!LHS->getType()->isFPOrFPVector())
return Error(Loc, "fcmp requires floating point operands");
@@ -3116,7 +3189,7 @@ bool LLParser::ParseCast(Instruction *&Inst, PerFunctionState &PFS,
ParseToken(lltok::kw_to, "expected 'to' after cast value") ||
ParseType(DestTy))
return true;
-
+
if (!CastInst::castIsValid((Instruction::CastOps)Opc, Op, DestTy)) {
CastInst::castIsValid((Instruction::CastOps)Opc, Op, DestTy);
return Error(Loc, "invalid cast opcode for cast from '" +
@@ -3138,10 +3211,10 @@ bool LLParser::ParseSelect(Instruction *&Inst, PerFunctionState &PFS) {
ParseToken(lltok::comma, "expected ',' after select value") ||
ParseTypeAndValue(Op2, PFS))
return true;
-
+
if (const char *Reason = SelectInst::areInvalidOperands(Op0, Op1, Op2))
return Error(Loc, Reason);
-
+
Inst = SelectInst::Create(Op0, Op1, Op2);
return false;
}
@@ -3156,7 +3229,7 @@ bool LLParser::ParseVA_Arg(Instruction *&Inst, PerFunctionState &PFS) {
ParseToken(lltok::comma, "expected ',' after vaarg operand") ||
ParseType(EltTy, TypeLoc))
return true;
-
+
if (!EltTy->isFirstClassType())
return Error(TypeLoc, "va_arg requires operand with first class type");
@@ -3173,10 +3246,10 @@ bool LLParser::ParseExtractElement(Instruction *&Inst, PerFunctionState &PFS) {
ParseToken(lltok::comma, "expected ',' after extract value") ||
ParseTypeAndValue(Op1, PFS))
return true;
-
+
if (!ExtractElementInst::isValidOperands(Op0, Op1))
return Error(Loc, "invalid extractelement operands");
-
+
Inst = ExtractElementInst::Create(Op0, Op1);
return false;
}
@@ -3192,10 +3265,10 @@ bool LLParser::ParseInsertElement(Instruction *&Inst, PerFunctionState &PFS) {
ParseToken(lltok::comma, "expected ',' after insertelement value") ||
ParseTypeAndValue(Op2, PFS))
return true;
-
+
if (!InsertElementInst::isValidOperands(Op0, Op1, Op2))
return Error(Loc, "invalid insertelement operands");
-
+
Inst = InsertElementInst::Create(Op0, Op1, Op2);
return false;
}
@@ -3211,10 +3284,10 @@ bool LLParser::ParseShuffleVector(Instruction *&Inst, PerFunctionState &PFS) {
ParseToken(lltok::comma, "expected ',' after shuffle value") ||
ParseTypeAndValue(Op2, PFS))
return true;
-
+
if (!ShuffleVectorInst::isValidOperands(Op0, Op1, Op2))
return Error(Loc, "invalid extractelement operands");
-
+
Inst = new ShuffleVectorInst(Op0, Op1, Op2);
return false;
}
@@ -3225,7 +3298,7 @@ bool LLParser::ParsePHI(Instruction *&Inst, PerFunctionState &PFS) {
PATypeHolder Ty(Type::getVoidTy(Context));
Value *Op0, *Op1;
LocTy TypeLoc = Lex.getLoc();
-
+
if (ParseType(Ty) ||
ParseToken(lltok::lsquare, "expected '[' in phi value list") ||
ParseValue(Ty, Op0, PFS) ||
@@ -3233,11 +3306,11 @@ bool LLParser::ParsePHI(Instruction *&Inst, PerFunctionState &PFS) {
ParseValue(Type::getLabelTy(Context), Op1, PFS) ||
ParseToken(lltok::rsquare, "expected ']' in phi value list"))
return true;
-
+
SmallVector<std::pair<Value*, BasicBlock*>, 16> PHIVals;
while (1) {
PHIVals.push_back(std::make_pair(Op0, cast<BasicBlock>(Op1)));
-
+
if (!EatIfPresent(lltok::comma))
break;
@@ -3248,7 +3321,7 @@ bool LLParser::ParsePHI(Instruction *&Inst, PerFunctionState &PFS) {
ParseToken(lltok::rsquare, "expected ']' in phi value list"))
return true;
}
-
+
if (!Ty->isFirstClassType())
return Error(TypeLoc, "phi node must have first class type");
@@ -3265,13 +3338,14 @@ bool LLParser::ParsePHI(Instruction *&Inst, PerFunctionState &PFS) {
/// ParameterList OptionalAttrs
bool LLParser::ParseCall(Instruction *&Inst, PerFunctionState &PFS,
bool isTail) {
- unsigned CC, RetAttrs, FnAttrs;
+ unsigned RetAttrs, FnAttrs;
+ CallingConv::ID CC;
PATypeHolder RetType(Type::getVoidTy(Context));
LocTy RetTypeLoc;
ValID CalleeID;
SmallVector<ParamInfo, 16> ArgList;
LocTy CallLoc = Lex.getLoc();
-
+
if ((isTail && ParseToken(lltok::kw_call, "expected 'tail call'")) ||
ParseOptionalCallingConv(CC) ||
ParseOptionalAttrs(RetAttrs, 1) ||
@@ -3280,7 +3354,7 @@ bool LLParser::ParseCall(Instruction *&Inst, PerFunctionState &PFS,
ParseParameterList(ArgList, PFS) ||
ParseOptionalAttrs(FnAttrs, 2))
return true;
-
+
// If RetType is a non-function pointer type, then this is the short syntax
// for the call, which means that RetType is just the return type. Infer the
// rest of the function argument types from the arguments that are present.
@@ -3292,18 +3366,18 @@ bool LLParser::ParseCall(Instruction *&Inst, PerFunctionState &PFS,
std::vector<const Type*> ParamTypes;
for (unsigned i = 0, e = ArgList.size(); i != e; ++i)
ParamTypes.push_back(ArgList[i].V->getType());
-
+
if (!FunctionType::isValidReturnType(RetType))
return Error(RetTypeLoc, "Invalid result type for LLVM function");
-
+
Ty = FunctionType::get(RetType, ParamTypes, false);
PFTy = PointerType::getUnqual(Ty);
}
-
+
// Look up the callee.
Value *Callee;
if (ConvertValIDToValue(PFTy, CalleeID, Callee, PFS)) return true;
-
+
// FIXME: In LLVM 3.0, stop accepting zext, sext and inreg as optional
// function attributes.
unsigned ObsoleteFuncAttrs = Attribute::ZExt|Attribute::SExt|Attribute::InReg;
@@ -3316,9 +3390,9 @@ bool LLParser::ParseCall(Instruction *&Inst, PerFunctionState &PFS,
SmallVector<AttributeWithIndex, 8> Attrs;
if (RetAttrs != Attribute::None)
Attrs.push_back(AttributeWithIndex::get(0, RetAttrs));
-
+
SmallVector<Value*, 8> Args;
-
+
// Loop through FunctionType's arguments and ensure they are specified
// correctly. Also, gather any parameter attributes.
FunctionType::param_iterator I = Ty->param_begin();
@@ -3330,7 +3404,7 @@ bool LLParser::ParseCall(Instruction *&Inst, PerFunctionState &PFS,
} else if (!Ty->isVarArg()) {
return Error(ArgList[i].Loc, "too many arguments specified");
}
-
+
if (ExpectedTy && ExpectedTy != ArgList[i].V->getType())
return Error(ArgList[i].Loc, "argument is not of expected type '" +
ExpectedTy->getDescription() + "'");
@@ -3338,7 +3412,7 @@ bool LLParser::ParseCall(Instruction *&Inst, PerFunctionState &PFS,
if (ArgList[i].Attrs != Attribute::None)
Attrs.push_back(AttributeWithIndex::get(i+1, ArgList[i].Attrs));
}
-
+
if (I != E)
return Error(CallLoc, "not enough parameters specified for call");
@@ -3347,7 +3421,7 @@ bool LLParser::ParseCall(Instruction *&Inst, PerFunctionState &PFS,
// Finish off the Attributes and check them
AttrListPtr PAL = AttrListPtr::get(Attrs.begin(), Attrs.end());
-
+
CallInst *CI = CallInst::Create(Callee, Args.begin(), Args.end());
CI->setTailCall(isTail);
CI->setCallingConv(CC);
@@ -3361,8 +3435,8 @@ bool LLParser::ParseCall(Instruction *&Inst, PerFunctionState &PFS,
//===----------------------------------------------------------------------===//
/// ParseAlloc
-/// ::= 'malloc' Type (',' TypeAndValue)? (',' OptionalAlignment)?
-/// ::= 'alloca' Type (',' TypeAndValue)? (',' OptionalAlignment)?
+/// ::= 'malloc' Type (',' TypeAndValue)? (',' OptionalInfo)?
+/// ::= 'alloca' Type (',' TypeAndValue)? (',' OptionalInfo)?
bool LLParser::ParseAlloc(Instruction *&Inst, PerFunctionState &PFS,
unsigned Opc) {
PATypeHolder Ty(Type::getVoidTy(Context));
@@ -3372,11 +3446,13 @@ bool LLParser::ParseAlloc(Instruction *&Inst, PerFunctionState &PFS,
if (ParseType(Ty)) return true;
if (EatIfPresent(lltok::comma)) {
- if (Lex.getKind() == lltok::kw_align) {
- if (ParseOptionalAlignment(Alignment)) return true;
- } else if (ParseTypeAndValue(Size, SizeLoc, PFS) ||
- ParseOptionalCommaAlignment(Alignment)) {
- return true;
+ if (Lex.getKind() == lltok::kw_align
+ || Lex.getKind() == lltok::NamedOrCustomMD) {
+ if (ParseOptionalInfo(Alignment)) return true;
+ } else {
+ if (ParseTypeAndValue(Size, SizeLoc, PFS)) return true;
+ if (EatIfPresent(lltok::comma))
+ if (ParseOptionalInfo(Alignment)) return true;
}
}
@@ -3402,19 +3478,20 @@ bool LLParser::ParseFree(Instruction *&Inst, PerFunctionState &PFS) {
}
/// ParseLoad
-/// ::= 'volatile'? 'load' TypeAndValue (',' 'align' i32)?
+/// ::= 'volatile'? 'load' TypeAndValue (',' OptionalInfo)?
bool LLParser::ParseLoad(Instruction *&Inst, PerFunctionState &PFS,
bool isVolatile) {
Value *Val; LocTy Loc;
- unsigned Alignment;
- if (ParseTypeAndValue(Val, Loc, PFS) ||
- ParseOptionalCommaAlignment(Alignment))
- return true;
+ unsigned Alignment = 0;
+ if (ParseTypeAndValue(Val, Loc, PFS)) return true;
+
+ if (EatIfPresent(lltok::comma))
+ if (ParseOptionalInfo(Alignment)) return true;
if (!isa<PointerType>(Val->getType()) ||
!cast<PointerType>(Val->getType())->getElementType()->isFirstClassType())
return Error(Loc, "load operand must be a pointer to a first class type");
-
+
Inst = new LoadInst(Val, "", isVolatile, Alignment);
return false;
}
@@ -3424,20 +3501,22 @@ bool LLParser::ParseLoad(Instruction *&Inst, PerFunctionState &PFS,
bool LLParser::ParseStore(Instruction *&Inst, PerFunctionState &PFS,
bool isVolatile) {
Value *Val, *Ptr; LocTy Loc, PtrLoc;
- unsigned Alignment;
+ unsigned Alignment = 0;
if (ParseTypeAndValue(Val, Loc, PFS) ||
ParseToken(lltok::comma, "expected ',' after store operand") ||
- ParseTypeAndValue(Ptr, PtrLoc, PFS) ||
- ParseOptionalCommaAlignment(Alignment))
+ ParseTypeAndValue(Ptr, PtrLoc, PFS))
return true;
-
+
+ if (EatIfPresent(lltok::comma))
+ if (ParseOptionalInfo(Alignment)) return true;
+
if (!isa<PointerType>(Ptr->getType()))
return Error(PtrLoc, "store operand must be a pointer");
if (!Val->getType()->isFirstClassType())
return Error(Loc, "store operand must be a first class value");
if (cast<PointerType>(Ptr->getType())->getElementType() != Val->getType())
return Error(Loc, "stored value and pointer type do not match");
-
+
Inst = new StoreInst(Val, Ptr, isVolatile, Alignment);
return false;
}
@@ -3452,7 +3531,7 @@ bool LLParser::ParseGetResult(Instruction *&Inst, PerFunctionState &PFS) {
ParseToken(lltok::comma, "expected ',' after getresult operand") ||
ParseUInt32(Element, EltLoc))
return true;
-
+
if (!isa<StructType>(Val->getType()) && !isa<ArrayType>(Val->getType()))
return Error(ValLoc, "getresult inst requires an aggregate operand");
if (!ExtractValueInst::getIndexedType(Val->getType(), Element))
@@ -3469,10 +3548,10 @@ bool LLParser::ParseGetElementPtr(Instruction *&Inst, PerFunctionState &PFS) {
bool InBounds = EatIfPresent(lltok::kw_inbounds);
if (ParseTypeAndValue(Ptr, Loc, PFS)) return true;
-
+
if (!isa<PointerType>(Ptr->getType()))
return Error(Loc, "base of getelementptr must be a pointer");
-
+
SmallVector<Value*, 16> Indices;
while (EatIfPresent(lltok::comma)) {
if (ParseTypeAndValue(Val, EltLoc, PFS)) return true;
@@ -3480,13 +3559,13 @@ bool LLParser::ParseGetElementPtr(Instruction *&Inst, PerFunctionState &PFS) {
return Error(EltLoc, "getelementptr index must be an integer");
Indices.push_back(Val);
}
-
+
if (!GetElementPtrInst::getIndexedType(Ptr->getType(),
Indices.begin(), Indices.end()))
return Error(Loc, "invalid getelementptr indices");
Inst = GetElementPtrInst::Create(Ptr, Indices.begin(), Indices.end());
if (InBounds)
- cast<GEPOperator>(Inst)->setIsInBounds(true);
+ cast<GetElementPtrInst>(Inst)->setIsInBounds(true);
return false;
}
@@ -3519,10 +3598,10 @@ bool LLParser::ParseInsertValue(Instruction *&Inst, PerFunctionState &PFS) {
ParseTypeAndValue(Val1, Loc1, PFS) ||
ParseIndexList(Indices))
return true;
-
+
if (!isa<StructType>(Val0->getType()) && !isa<ArrayType>(Val0->getType()))
return Error(Loc0, "extractvalue operand must be array or struct");
-
+
if (!ExtractValueInst::getIndexedType(Val0->getType(), Indices.begin(),
Indices.end()))
return Error(Loc0, "invalid indices for insertvalue");
diff --git a/libclamav/c++/llvm/lib/AsmParser/LLParser.h b/libclamav/c++/llvm/lib/AsmParser/LLParser.h
index 4bdbbfe..97bf2f3 100644
--- a/libclamav/c++/llvm/lib/AsmParser/LLParser.h
+++ b/libclamav/c++/llvm/lib/AsmParser/LLParser.h
@@ -48,7 +48,7 @@ namespace llvm {
/// MetadataCache - This map keeps track of parsed metadata constants.
std::map<unsigned, MetadataBase *> MetadataCache;
std::map<unsigned, std::pair<MetadataBase *, LocTy> > ForwardRefMDNodes;
-
+ SmallVector<std::pair<unsigned, MDNode *>, 2> MDsOnInst;
struct UpRefRecord {
/// Loc - This is the location of the upref.
LocTy Loc;
@@ -126,9 +126,10 @@ namespace llvm {
bool HasLinkage; return ParseOptionalLinkage(Linkage, HasLinkage);
}
bool ParseOptionalVisibility(unsigned &Visibility);
- bool ParseOptionalCallingConv(unsigned &CC);
+ bool ParseOptionalCallingConv(CallingConv::ID &CC);
bool ParseOptionalAlignment(unsigned &Alignment);
- bool ParseOptionalCommaAlignment(unsigned &Alignment);
+ bool ParseOptionalCustomMetadata();
+ bool ParseOptionalInfo(unsigned &Alignment);
bool ParseIndexList(SmallVectorImpl<unsigned> &Indices);
// Top-Level Entities
diff --git a/libclamav/c++/llvm/lib/AsmParser/LLToken.h b/libclamav/c++/llvm/lib/AsmParser/LLToken.h
index b053cca..bfcb58e 100644
--- a/libclamav/c++/llvm/lib/AsmParser/LLToken.h
+++ b/libclamav/c++/llvm/lib/AsmParser/LLToken.h
@@ -63,6 +63,7 @@ namespace lltok {
kw_asm,
kw_sideeffect,
kw_gc,
+ kw_dbg,
kw_c,
kw_cc, kw_ccc, kw_fastcc, kw_coldcc,
@@ -126,7 +127,7 @@ namespace lltok {
GlobalVar, // @foo @"foo"
LocalVar, // %foo %"foo"
StringConstant, // "foo"
- NamedMD, // !foo
+ NamedOrCustomMD, // !foo
// Metadata valued tokens.
Metadata, // !"foo" !{i8 42}
diff --git a/libclamav/c++/llvm/lib/AsmParser/Parser.cpp b/libclamav/c++/llvm/lib/AsmParser/Parser.cpp
index d66c13d..331a233 100644
--- a/libclamav/c++/llvm/lib/AsmParser/Parser.cpp
+++ b/libclamav/c++/llvm/lib/AsmParser/Parser.cpp
@@ -21,6 +21,24 @@
#include <cstring>
using namespace llvm;
+Module *llvm::ParseAssembly(MemoryBuffer *F,
+ Module *M,
+ SMDiagnostic &Err,
+ LLVMContext &Context) {
+ SourceMgr SM;
+ SM.AddNewSourceBuffer(F, SMLoc());
+
+ // If we are parsing into an existing module, do it.
+ if (M)
+ return LLParser(F, SM, Err, M).Run() ? 0 : M;
+
+ // Otherwise create a new module.
+ OwningPtr<Module> M2(new Module(F->getBufferIdentifier(), Context));
+ if (LLParser(F, SM, Err, M2.get()).Run())
+ return 0;
+ return M2.take();
+}
+
Module *llvm::ParseAssemblyFile(const std::string &Filename, SMDiagnostic &Err,
LLVMContext &Context) {
std::string ErrorStr;
@@ -31,13 +49,7 @@ Module *llvm::ParseAssemblyFile(const std::string &Filename, SMDiagnostic &Err,
return 0;
}
- SourceMgr SM;
- SM.AddNewSourceBuffer(F, SMLoc());
-
- OwningPtr<Module> M(new Module(Filename, Context));
- if (LLParser(F, SM, Err, M.get()).Run())
- return 0;
- return M.take();
+ return ParseAssembly(F, 0, Err, Context);
}
Module *llvm::ParseAssemblyString(const char *AsmString, Module *M,
@@ -45,17 +57,6 @@ Module *llvm::ParseAssemblyString(const char *AsmString, Module *M,
MemoryBuffer *F =
MemoryBuffer::getMemBuffer(AsmString, AsmString+strlen(AsmString),
"<string>");
-
- SourceMgr SM;
- SM.AddNewSourceBuffer(F, SMLoc());
- // If we are parsing into an existing module, do it.
- if (M)
- return LLParser(F, SM, Err, M).Run() ? 0 : M;
-
- // Otherwise create a new module.
- OwningPtr<Module> M2(new Module("<string>", Context));
- if (LLParser(F, SM, Err, M2.get()).Run())
- return 0;
- return M2.take();
+ return ParseAssembly(F, M, Err, Context);
}
diff --git a/libclamav/c++/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/libclamav/c++/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index f9cfe91..fe0366f 100644
--- a/libclamav/c++/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/libclamav/c++/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -35,7 +35,7 @@ void BitcodeReader::FreeState() {
std::vector<PATypeHolder>().swap(TypeList);
ValueList.clear();
MDValueList.clear();
-
+
std::vector<AttrListPtr>().swap(MAttributes);
std::vector<BasicBlock*>().swap(FunctionBBs);
std::vector<Function*>().swap(FunctionsWithBodies);
@@ -53,7 +53,7 @@ static bool ConvertToString(SmallVector<uint64_t, 64> &Record, unsigned Idx,
StrTy &Result) {
if (Idx > Record.size())
return true;
-
+
for (unsigned i = Idx, e = Record.size(); i != e; ++i)
Result += (char)Record[i];
return false;
@@ -145,15 +145,15 @@ namespace {
: ConstantExpr(Ty, Instruction::UserOp1, &Op<0>(), 1) {
Op<0>() = UndefValue::get(Type::getInt32Ty(Context));
}
-
+
/// @brief Methods to support type inquiry through isa, cast, and dyn_cast.
static inline bool classof(const ConstantPlaceHolder *) { return true; }
static bool classof(const Value *V) {
- return isa<ConstantExpr>(V) &&
+ return isa<ConstantExpr>(V) &&
cast<ConstantExpr>(V)->getOpcode() == Instruction::UserOp1;
}
-
-
+
+
/// Provide fast operand accessors
//DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
};
@@ -161,7 +161,7 @@ namespace {
// FIXME: can we inherit this from ConstantExpr?
template <>
-struct OperandTraits<ConstantPlaceHolder> : FixedNumOperandTraits<1> {
+struct OperandTraits<ConstantPlaceHolder> : public FixedNumOperandTraits<1> {
};
}
@@ -171,16 +171,16 @@ void BitcodeReaderValueList::AssignValue(Value *V, unsigned Idx) {
push_back(V);
return;
}
-
+
if (Idx >= size())
resize(Idx+1);
-
+
WeakVH &OldV = ValuePtrs[Idx];
if (OldV == 0) {
OldV = V;
return;
}
-
+
// Handle constants and non-constants (e.g. instrs) differently for
// efficiency.
if (Constant *PHC = dyn_cast<Constant>(&*OldV)) {
@@ -193,7 +193,7 @@ void BitcodeReaderValueList::AssignValue(Value *V, unsigned Idx) {
delete PrevVal;
}
}
-
+
Constant *BitcodeReaderValueList::getConstantFwdRef(unsigned Idx,
const Type *Ty) {
@@ -214,15 +214,15 @@ Constant *BitcodeReaderValueList::getConstantFwdRef(unsigned Idx,
Value *BitcodeReaderValueList::getValueFwdRef(unsigned Idx, const Type *Ty) {
if (Idx >= size())
resize(Idx + 1);
-
+
if (Value *V = ValuePtrs[Idx]) {
assert((Ty == 0 || Ty == V->getType()) && "Type mismatch in value table!");
return V;
}
-
+
// No type specified, must be invalid reference.
if (Ty == 0) return 0;
-
+
// Create and return a placeholder, which will later be RAUW'd.
Value *V = new Argument(Ty);
ValuePtrs[Idx] = V;
@@ -237,30 +237,30 @@ Value *BitcodeReaderValueList::getValueFwdRef(unsigned Idx, const Type *Ty) {
/// uses and rewrite all the place holders at once for any constant that uses
/// a placeholder.
void BitcodeReaderValueList::ResolveConstantForwardRefs() {
- // Sort the values by-pointer so that they are efficient to look up with a
+ // Sort the values by-pointer so that they are efficient to look up with a
// binary search.
std::sort(ResolveConstants.begin(), ResolveConstants.end());
-
+
SmallVector<Constant*, 64> NewOps;
-
+
while (!ResolveConstants.empty()) {
Value *RealVal = operator[](ResolveConstants.back().second);
Constant *Placeholder = ResolveConstants.back().first;
ResolveConstants.pop_back();
-
+
// Loop over all users of the placeholder, updating them to reference the
// new value. If they reference more than one placeholder, update them all
// at once.
while (!Placeholder->use_empty()) {
Value::use_iterator UI = Placeholder->use_begin();
-
+
// If the using object isn't uniqued, just update the operands. This
// handles instructions and initializers for global variables.
if (!isa<Constant>(*UI) || isa<GlobalValue>(*UI)) {
UI.getUse().set(RealVal);
continue;
}
-
+
// Otherwise, we have a constant that uses the placeholder. Replace that
// constant with a new constant that has *all* placeholder uses updated.
Constant *UserC = cast<Constant>(*UI);
@@ -275,8 +275,8 @@ void BitcodeReaderValueList::ResolveConstantForwardRefs() {
NewOp = RealVal;
} else {
// Otherwise, look up the placeholder in ResolveConstants.
- ResolveConstantsTy::iterator It =
- std::lower_bound(ResolveConstants.begin(), ResolveConstants.end(),
+ ResolveConstantsTy::iterator It =
+ std::lower_bound(ResolveConstants.begin(), ResolveConstants.end(),
std::pair<Constant*, unsigned>(cast<Constant>(*I),
0));
assert(It != ResolveConstants.end() && It->first == *I);
@@ -301,12 +301,12 @@ void BitcodeReaderValueList::ResolveConstantForwardRefs() {
NewC = cast<ConstantExpr>(UserC)->getWithOperands(&NewOps[0],
NewOps.size());
}
-
+
UserC->replaceAllUsesWith(NewC);
UserC->destroyConstant();
NewOps.clear();
}
-
+
// Update all ValueHandles, they should be the only users at this point.
Placeholder->replaceAllUsesWith(RealVal);
delete Placeholder;
@@ -318,31 +318,34 @@ void BitcodeReaderMDValueList::AssignValue(Value *V, unsigned Idx) {
push_back(V);
return;
}
-
+
if (Idx >= size())
resize(Idx+1);
-
+
WeakVH &OldV = MDValuePtrs[Idx];
if (OldV == 0) {
OldV = V;
return;
}
-
+
// If there was a forward reference to this value, replace it.
Value *PrevVal = OldV;
OldV->replaceAllUsesWith(V);
delete PrevVal;
+ // Deleting PrevVal sets Idx value in MDValuePtrs to null. Set new
+ // value for Idx.
+ MDValuePtrs[Idx] = V;
}
Value *BitcodeReaderMDValueList::getValueFwdRef(unsigned Idx) {
if (Idx >= size())
resize(Idx + 1);
-
+
if (Value *V = MDValuePtrs[Idx]) {
assert(V->getType() == Type::getMetadataTy(Context) && "Type mismatch in value table!");
return V;
}
-
+
// Create and return a placeholder, which will later be RAUW'd.
Value *V = new Argument(Type::getMetadataTy(Context));
MDValuePtrs[Idx] = V;
@@ -354,7 +357,7 @@ const Type *BitcodeReader::getTypeByID(unsigned ID, bool isTypeTable) {
if (ID < TypeList.size())
return TypeList[ID].get();
if (!isTypeTable) return 0;
-
+
// The type table allows forward references. Push as many Opaque types as
// needed to get up to ID.
while (TypeList.size() <= ID)
@@ -369,14 +372,14 @@ const Type *BitcodeReader::getTypeByID(unsigned ID, bool isTypeTable) {
bool BitcodeReader::ParseAttributeBlock() {
if (Stream.EnterSubBlock(bitc::PARAMATTR_BLOCK_ID))
return Error("Malformed block record");
-
+
if (!MAttributes.empty())
return Error("Multiple PARAMATTR blocks found!");
-
+
SmallVector<uint64_t, 64> Record;
-
+
SmallVector<AttributeWithIndex, 8> Attrs;
-
+
// Read all the records.
while (1) {
unsigned Code = Stream.ReadCode();
@@ -385,7 +388,7 @@ bool BitcodeReader::ParseAttributeBlock() {
return Error("Error at end of PARAMATTR block");
return false;
}
-
+
if (Code == bitc::ENTER_SUBBLOCK) {
// No known subblocks, always skip them.
Stream.ReadSubBlockID();
@@ -393,12 +396,12 @@ bool BitcodeReader::ParseAttributeBlock() {
return Error("Malformed block record");
continue;
}
-
+
if (Code == bitc::DEFINE_ABBREV) {
Stream.ReadAbbrevRecord();
continue;
}
-
+
// Read a record.
Record.clear();
switch (Stream.ReadRecord(Code, Record)) {
@@ -437,14 +440,14 @@ bool BitcodeReader::ParseAttributeBlock() {
unsigned OldRetAttrs = (Attribute::NoUnwind|Attribute::NoReturn|
Attribute::ReadOnly|Attribute::ReadNone);
-
+
if (FnAttribute == Attribute::None && RetAttribute != Attribute::None &&
(RetAttribute & OldRetAttrs) != 0) {
if (FnAttribute == Attribute::None) { // add a slot so they get added.
Record.push_back(~0U);
Record.push_back(0);
}
-
+
FnAttribute |= RetAttribute & OldRetAttrs;
RetAttribute &= ~OldRetAttrs;
}
@@ -472,7 +475,7 @@ bool BitcodeReader::ParseAttributeBlock() {
bool BitcodeReader::ParseTypeTable() {
if (Stream.EnterSubBlock(bitc::TYPE_BLOCK_ID))
return Error("Malformed block record");
-
+
if (!TypeList.empty())
return Error("Multiple TYPE_BLOCKs found!");
@@ -489,7 +492,7 @@ bool BitcodeReader::ParseTypeTable() {
return Error("Error at end of type table block");
return false;
}
-
+
if (Code == bitc::ENTER_SUBBLOCK) {
// No known subblocks, always skip them.
Stream.ReadSubBlockID();
@@ -497,12 +500,12 @@ bool BitcodeReader::ParseTypeTable() {
return Error("Malformed block record");
continue;
}
-
+
if (Code == bitc::DEFINE_ABBREV) {
Stream.ReadAbbrevRecord();
continue;
}
-
+
// Read a record.
Record.clear();
const Type *ResultTy = 0;
@@ -547,10 +550,10 @@ bool BitcodeReader::ParseTypeTable() {
case bitc::TYPE_CODE_INTEGER: // INTEGER: [width]
if (Record.size() < 1)
return Error("Invalid Integer type record");
-
+
ResultTy = IntegerType::get(Context, Record[0]);
break;
- case bitc::TYPE_CODE_POINTER: { // POINTER: [pointee type] or
+ case bitc::TYPE_CODE_POINTER: { // POINTER: [pointee type] or
// [pointee type, address space]
if (Record.size() < 1)
return Error("Invalid POINTER type record");
@@ -569,7 +572,7 @@ bool BitcodeReader::ParseTypeTable() {
std::vector<const Type*> ArgTys;
for (unsigned i = 3, e = Record.size(); i != e; ++i)
ArgTys.push_back(getTypeByID(Record[i], true));
-
+
ResultTy = FunctionType::get(getTypeByID(Record[2], true), ArgTys,
Record[0]);
break;
@@ -594,7 +597,7 @@ bool BitcodeReader::ParseTypeTable() {
ResultTy = VectorType::get(getTypeByID(Record[1], true), Record[0]);
break;
}
-
+
if (NumRecords == TypeList.size()) {
// If this is a new type slot, just append it.
TypeList.push_back(ResultTy ? ResultTy : OpaqueType::get(Context));
@@ -609,14 +612,14 @@ bool BitcodeReader::ParseTypeTable() {
// Resolve the opaque type to the real type now.
assert(NumRecords < TypeList.size() && "Typelist imbalance");
const OpaqueType *OldTy = cast<OpaqueType>(TypeList[NumRecords++].get());
-
+
// Don't directly push the new type on the Tab. Instead we want to replace
// the opaque type we previously inserted with the new concrete value. The
// refinement from the abstract (opaque) type to the new type causes all
// uses of the abstract type to use the concrete type (NewTy). This will
// also cause the opaque type to be deleted.
const_cast<OpaqueType*>(OldTy)->refineAbstractTypeTo(ResultTy);
-
+
// This should have replaced the old opaque type with the new type in the
// value table... or with a preexisting type that was already in the
// system. Let's just make sure it did.
@@ -630,9 +633,9 @@ bool BitcodeReader::ParseTypeTable() {
bool BitcodeReader::ParseTypeSymbolTable() {
if (Stream.EnterSubBlock(bitc::TYPE_SYMTAB_BLOCK_ID))
return Error("Malformed block record");
-
+
SmallVector<uint64_t, 64> Record;
-
+
// Read all the records for this type table.
std::string TypeName;
while (1) {
@@ -642,7 +645,7 @@ bool BitcodeReader::ParseTypeSymbolTable() {
return Error("Error at end of type symbol table block");
return false;
}
-
+
if (Code == bitc::ENTER_SUBBLOCK) {
// No known subblocks, always skip them.
Stream.ReadSubBlockID();
@@ -650,12 +653,12 @@ bool BitcodeReader::ParseTypeSymbolTable() {
return Error("Malformed block record");
continue;
}
-
+
if (Code == bitc::DEFINE_ABBREV) {
Stream.ReadAbbrevRecord();
continue;
}
-
+
// Read a record.
Record.clear();
switch (Stream.ReadRecord(Code, Record)) {
@@ -680,7 +683,7 @@ bool BitcodeReader::ParseValueSymbolTable() {
return Error("Malformed block record");
SmallVector<uint64_t, 64> Record;
-
+
// Read all the records for this value table.
SmallString<128> ValueName;
while (1) {
@@ -689,7 +692,7 @@ bool BitcodeReader::ParseValueSymbolTable() {
if (Stream.ReadBlockEnd())
return Error("Error at end of value symbol table block");
return false;
- }
+ }
if (Code == bitc::ENTER_SUBBLOCK) {
// No known subblocks, always skip them.
Stream.ReadSubBlockID();
@@ -697,12 +700,12 @@ bool BitcodeReader::ParseValueSymbolTable() {
return Error("Malformed block record");
continue;
}
-
+
if (Code == bitc::DEFINE_ABBREV) {
Stream.ReadAbbrevRecord();
continue;
}
-
+
// Read a record.
Record.clear();
switch (Stream.ReadRecord(Code, Record)) {
@@ -715,7 +718,7 @@ bool BitcodeReader::ParseValueSymbolTable() {
if (ValueID >= ValueList.size())
return Error("Invalid Value ID in VST_ENTRY record");
Value *V = ValueList[ValueID];
-
+
V->setName(StringRef(ValueName.data(), ValueName.size()));
ValueName.clear();
break;
@@ -726,7 +729,7 @@ bool BitcodeReader::ParseValueSymbolTable() {
BasicBlock *BB = getBasicBlock(Record[0]);
if (BB == 0)
return Error("Invalid BB ID in VST_BBENTRY record");
-
+
BB->setName(StringRef(ValueName.data(), ValueName.size()));
ValueName.clear();
break;
@@ -740,9 +743,9 @@ bool BitcodeReader::ParseMetadata() {
if (Stream.EnterSubBlock(bitc::METADATA_BLOCK_ID))
return Error("Malformed block record");
-
+
SmallVector<uint64_t, 64> Record;
-
+
// Read all the records.
while (1) {
unsigned Code = Stream.ReadCode();
@@ -751,7 +754,7 @@ bool BitcodeReader::ParseMetadata() {
return Error("Error at end of PARAMATTR block");
return false;
}
-
+
if (Code == bitc::ENTER_SUBBLOCK) {
// No known subblocks, always skip them.
Stream.ReadSubBlockID();
@@ -759,12 +762,12 @@ bool BitcodeReader::ParseMetadata() {
return Error("Malformed block record");
continue;
}
-
+
if (Code == bitc::DEFINE_ABBREV) {
Stream.ReadAbbrevRecord();
continue;
}
-
+
// Read a record.
Record.clear();
switch (Stream.ReadRecord(Code, Record)) {
@@ -792,7 +795,7 @@ bool BitcodeReader::ParseMetadata() {
if (MetadataBase *B = dyn_cast<MetadataBase>(MD))
Elts.push_back(B);
}
- Value *V = NamedMDNode::Create(Context, Name.str(), Elts.data(),
+ Value *V = NamedMDNode::Create(Context, Name.str(), Elts.data(),
Elts.size(), TheModule);
MDValueList.AssignValue(V, NextValueNo++);
break;
@@ -800,7 +803,7 @@ bool BitcodeReader::ParseMetadata() {
case bitc::METADATA_NODE: {
if (Record.empty() || Record.size() % 2 == 1)
return Error("Invalid METADATA_NODE record");
-
+
unsigned Size = Record.size();
SmallVector<Value*, 8> Elts;
for (unsigned i = 0; i != Size; i += 2) {
@@ -822,11 +825,27 @@ bool BitcodeReader::ParseMetadata() {
String.resize(MDStringLength);
for (unsigned i = 0; i != MDStringLength; ++i)
String[i] = Record[i];
- Value *V = MDString::get(Context,
+ Value *V = MDString::get(Context,
StringRef(String.data(), String.size()));
MDValueList.AssignValue(V, NextValueNo++);
break;
}
+ case bitc::METADATA_KIND: {
+ unsigned RecordLength = Record.size();
+ if (Record.empty() || RecordLength < 2)
+ return Error("Invalid METADATA_KIND record");
+ SmallString<8> Name;
+ Name.resize(RecordLength-1);
+ unsigned Kind = Record[0];
+ for (unsigned i = 1; i != RecordLength; ++i)
+ Name[i-1] = Record[i];
+ MetadataContext &TheMetadata = Context.getMetadata();
+ assert(TheMetadata.MDHandlerNames.find(Name.str())
+ == TheMetadata.MDHandlerNames.end() &&
+ "Already registered MDKind!");
+ TheMetadata.MDHandlerNames[Name.str()] = Kind;
+ break;
+ }
}
}
}
@@ -836,7 +855,7 @@ bool BitcodeReader::ParseMetadata() {
static uint64_t DecodeSignRotatedValue(uint64_t V) {
if ((V & 1) == 0)
return V >> 1;
- if (V != 1)
+ if (V != 1)
return -(V >> 1);
// There is no such thing as -0 with integers. "-0" really means MININT.
return 1ULL << 63;
@@ -847,7 +866,7 @@ static uint64_t DecodeSignRotatedValue(uint64_t V) {
bool BitcodeReader::ResolveGlobalAndAliasInits() {
std::vector<std::pair<GlobalVariable*, unsigned> > GlobalInitWorklist;
std::vector<std::pair<GlobalAlias*, unsigned> > AliasInitWorklist;
-
+
GlobalInitWorklist.swap(GlobalInits);
AliasInitWorklist.swap(AliasInits);
@@ -862,7 +881,7 @@ bool BitcodeReader::ResolveGlobalAndAliasInits() {
else
return Error("Global variable initializer is not a constant!");
}
- GlobalInitWorklist.pop_back();
+ GlobalInitWorklist.pop_back();
}
while (!AliasInitWorklist.empty()) {
@@ -875,30 +894,17 @@ bool BitcodeReader::ResolveGlobalAndAliasInits() {
else
return Error("Alias initializer is not a constant!");
}
- AliasInitWorklist.pop_back();
+ AliasInitWorklist.pop_back();
}
return false;
}
-static void SetOptimizationFlags(Value *V, uint64_t Flags) {
- if (OverflowingBinaryOperator *OBO =
- dyn_cast<OverflowingBinaryOperator>(V)) {
- if (Flags & (1 << bitc::OBO_NO_SIGNED_WRAP))
- OBO->setHasNoSignedWrap(true);
- if (Flags & (1 << bitc::OBO_NO_UNSIGNED_WRAP))
- OBO->setHasNoUnsignedWrap(true);
- } else if (SDivOperator *Div = dyn_cast<SDivOperator>(V)) {
- if (Flags & (1 << bitc::SDIV_EXACT))
- Div->setIsExact(true);
- }
-}
-
bool BitcodeReader::ParseConstants() {
if (Stream.EnterSubBlock(bitc::CONSTANTS_BLOCK_ID))
return Error("Malformed block record");
SmallVector<uint64_t, 64> Record;
-
+
// Read all the records for this value table.
const Type *CurTy = Type::getInt32Ty(Context);
unsigned NextCstNo = ValueList.size();
@@ -906,7 +912,7 @@ bool BitcodeReader::ParseConstants() {
unsigned Code = Stream.ReadCode();
if (Code == bitc::END_BLOCK)
break;
-
+
if (Code == bitc::ENTER_SUBBLOCK) {
// No known subblocks, always skip them.
Stream.ReadSubBlockID();
@@ -914,12 +920,12 @@ bool BitcodeReader::ParseConstants() {
return Error("Malformed block record");
continue;
}
-
+
if (Code == bitc::DEFINE_ABBREV) {
Stream.ReadAbbrevRecord();
continue;
}
-
+
// Read a record.
Record.clear();
Value *V = 0;
@@ -947,13 +953,13 @@ bool BitcodeReader::ParseConstants() {
case bitc::CST_CODE_WIDE_INTEGER: {// WIDE_INTEGER: [n x intval]
if (!isa<IntegerType>(CurTy) || Record.empty())
return Error("Invalid WIDE_INTEGER record");
-
+
unsigned NumWords = Record.size();
SmallVector<uint64_t, 8> Words;
Words.resize(NumWords);
for (unsigned i = 0; i != NumWords; ++i)
Words[i] = DecodeSignRotatedValue(Record[i]);
- V = ConstantInt::get(Context,
+ V = ConstantInt::get(Context,
APInt(cast<IntegerType>(CurTy)->getBitWidth(),
NumWords, &Words[0]));
break;
@@ -979,14 +985,14 @@ bool BitcodeReader::ParseConstants() {
V = UndefValue::get(CurTy);
break;
}
-
+
case bitc::CST_CODE_AGGREGATE: {// AGGREGATE: [n x value number]
if (Record.empty())
return Error("Invalid CST_AGGREGATE record");
-
+
unsigned Size = Record.size();
std::vector<Constant*> Elts;
-
+
if (const StructType *STy = dyn_cast<StructType>(CurTy)) {
for (unsigned i = 0; i != Size; ++i)
Elts.push_back(ValueList.getConstantFwdRef(Record[i],
@@ -1013,7 +1019,7 @@ bool BitcodeReader::ParseConstants() {
const ArrayType *ATy = cast<ArrayType>(CurTy);
const Type *EltTy = ATy->getElementType();
-
+
unsigned Size = Record.size();
std::vector<Constant*> Elts;
for (unsigned i = 0; i != Size; ++i)
@@ -1024,10 +1030,10 @@ bool BitcodeReader::ParseConstants() {
case bitc::CST_CODE_CSTRING: { // CSTRING: [values]
if (Record.empty())
return Error("Invalid CST_AGGREGATE record");
-
+
const ArrayType *ATy = cast<ArrayType>(CurTy);
const Type *EltTy = ATy->getElementType();
-
+
unsigned Size = Record.size();
std::vector<Constant*> Elts;
for (unsigned i = 0; i != Size; ++i)
@@ -1044,12 +1050,24 @@ bool BitcodeReader::ParseConstants() {
} else {
Constant *LHS = ValueList.getConstantFwdRef(Record[1], CurTy);
Constant *RHS = ValueList.getConstantFwdRef(Record[2], CurTy);
- V = ConstantExpr::get(Opc, LHS, RHS);
+ unsigned Flags = 0;
+ if (Record.size() >= 4) {
+ if (Opc == Instruction::Add ||
+ Opc == Instruction::Sub ||
+ Opc == Instruction::Mul) {
+ if (Record[3] & (1 << bitc::OBO_NO_SIGNED_WRAP))
+ Flags |= OverflowingBinaryOperator::NoSignedWrap;
+ if (Record[3] & (1 << bitc::OBO_NO_UNSIGNED_WRAP))
+ Flags |= OverflowingBinaryOperator::NoUnsignedWrap;
+ } else if (Opc == Instruction::SDiv) {
+ if (Record[3] & (1 << bitc::SDIV_EXACT))
+ Flags |= SDivOperator::IsExact;
+ }
+ }
+ V = ConstantExpr::get(Opc, LHS, RHS, Flags);
}
- if (Record.size() >= 4)
- SetOptimizationFlags(V, Record[3]);
break;
- }
+ }
case bitc::CST_CODE_CE_CAST: { // CE_CAST: [opcode, opty, opval]
if (Record.size() < 3) return Error("Invalid CE_CAST record");
int Opc = GetDecodedCastOpcode(Record[0]);
@@ -1062,7 +1080,7 @@ bool BitcodeReader::ParseConstants() {
V = ConstantExpr::getCast(Opc, Op, CurTy);
}
break;
- }
+ }
case bitc::CST_CODE_CE_INBOUNDS_GEP:
case bitc::CST_CODE_CE_GEP: { // CE_GEP: [n x operands]
if (Record.size() & 1) return Error("Invalid CE_GEP record");
@@ -1072,10 +1090,12 @@ bool BitcodeReader::ParseConstants() {
if (!ElTy) return Error("Invalid CE_GEP record");
Elts.push_back(ValueList.getConstantFwdRef(Record[i+1], ElTy));
}
- V = ConstantExpr::getGetElementPtr(Elts[0], &Elts[1],
- Elts.size()-1);
if (BitCode == bitc::CST_CODE_CE_INBOUNDS_GEP)
- cast<GEPOperator>(V)->setIsInBounds(true);
+ V = ConstantExpr::getInBoundsGetElementPtr(Elts[0], &Elts[1],
+ Elts.size()-1);
+ else
+ V = ConstantExpr::getGetElementPtr(Elts[0], &Elts[1],
+ Elts.size()-1);
break;
}
case bitc::CST_CODE_CE_SELECT: // CE_SELECT: [opval#, opval#, opval#]
@@ -1087,7 +1107,7 @@ bool BitcodeReader::ParseConstants() {
break;
case bitc::CST_CODE_CE_EXTRACTELT: { // CE_EXTRACTELT: [opty, opval, opval]
if (Record.size() < 3) return Error("Invalid CE_EXTRACTELT record");
- const VectorType *OpTy =
+ const VectorType *OpTy =
dyn_cast_or_null<VectorType>(getTypeByID(Record[0]));
if (OpTy == 0) return Error("Invalid CE_EXTRACTELT record");
Constant *Op0 = ValueList.getConstantFwdRef(Record[1], OpTy);
@@ -1112,7 +1132,7 @@ bool BitcodeReader::ParseConstants() {
return Error("Invalid CE_SHUFFLEVEC record");
Constant *Op0 = ValueList.getConstantFwdRef(Record[0], OpTy);
Constant *Op1 = ValueList.getConstantFwdRef(Record[1], OpTy);
- const Type *ShufTy = VectorType::get(Type::getInt32Ty(Context),
+ const Type *ShufTy = VectorType::get(Type::getInt32Ty(Context),
OpTy->getNumElements());
Constant *Op2 = ValueList.getConstantFwdRef(Record[2], ShufTy);
V = ConstantExpr::getShuffleVector(Op0, Op1, Op2);
@@ -1125,7 +1145,7 @@ bool BitcodeReader::ParseConstants() {
return Error("Invalid CE_SHUFVEC_EX record");
Constant *Op0 = ValueList.getConstantFwdRef(Record[1], OpTy);
Constant *Op1 = ValueList.getConstantFwdRef(Record[2], OpTy);
- const Type *ShufTy = VectorType::get(Type::getInt32Ty(Context),
+ const Type *ShufTy = VectorType::get(Type::getInt32Ty(Context),
RTy->getNumElements());
Constant *Op2 = ValueList.getConstantFwdRef(Record[3], ShufTy);
V = ConstantExpr::getShuffleVector(Op0, Op1, Op2);
@@ -1154,7 +1174,7 @@ bool BitcodeReader::ParseConstants() {
unsigned ConstStrSize = Record[2+AsmStrSize];
if (3+AsmStrSize+ConstStrSize > Record.size())
return Error("Invalid INLINEASM record");
-
+
for (unsigned i = 0; i != AsmStrSize; ++i)
AsmStr += (char)Record[2+i];
for (unsigned i = 0; i != ConstStrSize; ++i)
@@ -1165,17 +1185,17 @@ bool BitcodeReader::ParseConstants() {
break;
}
}
-
+
ValueList.AssignValue(V, NextCstNo);
++NextCstNo;
}
-
+
if (NextCstNo != ValueList.size())
return Error("Invalid constant reference!");
-
+
if (Stream.ReadBlockEnd())
return Error("Error at end of constants block");
-
+
// Once all the constants have been read, go through and resolve forward
// references.
ValueList.ResolveConstantForwardRefs();
@@ -1189,18 +1209,18 @@ bool BitcodeReader::RememberAndSkipFunctionBody() {
// Get the function we are talking about.
if (FunctionsWithBodies.empty())
return Error("Insufficient function protos");
-
+
Function *Fn = FunctionsWithBodies.back();
FunctionsWithBodies.pop_back();
-
+
// Save the current stream state.
uint64_t CurBit = Stream.GetCurrentBitNo();
DeferredFunctionInfo[Fn] = std::make_pair(CurBit, Fn->getLinkage());
-
+
// Set the functions linkage to GhostLinkage so we know it is lazily
// deserialized.
Fn->setLinkage(GlobalValue::GhostLinkage);
-
+
// Skip over the function block for now.
if (Stream.SkipBlock())
return Error("Malformed block record");
@@ -1211,13 +1231,13 @@ bool BitcodeReader::ParseModule(const std::string &ModuleID) {
// Reject multiple MODULE_BLOCK's in a single bitstream.
if (TheModule)
return Error("Multiple MODULE_BLOCKs in same stream");
-
+
if (Stream.EnterSubBlock(bitc::MODULE_BLOCK_ID))
return Error("Malformed block record");
// Otherwise, create the module.
TheModule = new Module(ModuleID, Context);
-
+
SmallVector<uint64_t, 64> Record;
std::vector<std::string> SectionTable;
std::vector<std::string> GCTable;
@@ -1251,7 +1271,7 @@ bool BitcodeReader::ParseModule(const std::string &ModuleID) {
std::vector<Function*>().swap(FunctionsWithBodies);
return false;
}
-
+
if (Code == bitc::ENTER_SUBBLOCK) {
switch (Stream.ReadSubBlockID()) {
default: // Skip unknown content.
@@ -1293,19 +1313,19 @@ bool BitcodeReader::ParseModule(const std::string &ModuleID) {
std::reverse(FunctionsWithBodies.begin(), FunctionsWithBodies.end());
HasReversedFunctionsWithBodies = true;
}
-
+
if (RememberAndSkipFunctionBody())
return true;
break;
}
continue;
}
-
+
if (Code == bitc::DEFINE_ABBREV) {
Stream.ReadAbbrevRecord();
continue;
}
-
+
// Read a record.
switch (Stream.ReadRecord(Code, Record)) {
default: break; // Default behavior, ignore unknown content.
@@ -1368,7 +1388,7 @@ bool BitcodeReader::ParseModule(const std::string &ModuleID) {
return Error("Global not a pointer type!");
unsigned AddressSpace = cast<PointerType>(Ty)->getAddressSpace();
Ty = cast<PointerType>(Ty)->getElementType();
-
+
bool isConstant = Record[1];
GlobalValue::LinkageTypes Linkage = GetDecodedLinkage(Record[3]);
unsigned Alignment = (1 << Record[4]) >> 1;
@@ -1386,16 +1406,16 @@ bool BitcodeReader::ParseModule(const std::string &ModuleID) {
isThreadLocal = Record[7];
GlobalVariable *NewGV =
- new GlobalVariable(*TheModule, Ty, isConstant, Linkage, 0, "", 0,
+ new GlobalVariable(*TheModule, Ty, isConstant, Linkage, 0, "", 0,
isThreadLocal, AddressSpace);
NewGV->setAlignment(Alignment);
if (!Section.empty())
NewGV->setSection(Section);
NewGV->setVisibility(Visibility);
NewGV->setThreadLocal(isThreadLocal);
-
+
ValueList.push_back(NewGV);
-
+
// Remember which value to use for the global initializer.
if (unsigned InitID = Record[2])
GlobalInits.push_back(std::make_pair(NewGV, InitID-1));
@@ -1417,11 +1437,11 @@ bool BitcodeReader::ParseModule(const std::string &ModuleID) {
Function *Func = Function::Create(FTy, GlobalValue::ExternalLinkage,
"", TheModule);
- Func->setCallingConv(Record[1]);
+ Func->setCallingConv(static_cast<CallingConv::ID>(Record[1]));
bool isProto = Record[2];
Func->setLinkage(GetDecodedLinkage(Record[3]));
Func->setAttributes(getAttributes(Record[4]));
-
+
Func->setAlignment((1 << Record[5]) >> 1);
if (Record[6]) {
if (Record[6]-1 >= SectionTable.size())
@@ -1435,7 +1455,7 @@ bool BitcodeReader::ParseModule(const std::string &ModuleID) {
Func->setGC(GCTable[Record[8]-1].c_str());
}
ValueList.push_back(Func);
-
+
// If this is a function with a body, remember the prototype we are
// creating now, so that we can match up the body with them later.
if (!isProto)
@@ -1450,7 +1470,7 @@ bool BitcodeReader::ParseModule(const std::string &ModuleID) {
const Type *Ty = getTypeByID(Record[0]);
if (!isa<PointerType>(Ty))
return Error("Function not a pointer type!");
-
+
GlobalAlias *NewGA = new GlobalAlias(Ty, GetDecodedLinkage(Record[2]),
"", 0, TheModule);
// Old bitcode files didn't have visibility field.
@@ -1470,28 +1490,28 @@ bool BitcodeReader::ParseModule(const std::string &ModuleID) {
}
Record.clear();
}
-
+
return Error("Premature end of bitstream");
}
bool BitcodeReader::ParseBitcode() {
TheModule = 0;
-
+
if (Buffer->getBufferSize() & 3)
return Error("Bitcode stream should be a multiple of 4 bytes in length");
-
+
unsigned char *BufPtr = (unsigned char *)Buffer->getBufferStart();
unsigned char *BufEnd = BufPtr+Buffer->getBufferSize();
-
+
// If we have a wrapper header, parse it and ignore the non-bc file contents.
// The magic number is 0x0B17C0DE stored in little endian.
if (isBitcodeWrapper(BufPtr, BufEnd))
if (SkipBitcodeWrapperHeader(BufPtr, BufEnd))
return Error("Invalid bitcode wrapper header");
-
+
StreamFile.init(BufPtr, BufEnd);
Stream.init(StreamFile);
-
+
// Sniff for the signature.
if (Stream.Read(8) != 'B' ||
Stream.Read(8) != 'C' ||
@@ -1500,17 +1520,17 @@ bool BitcodeReader::ParseBitcode() {
Stream.Read(4) != 0xE ||
Stream.Read(4) != 0xD)
return Error("Invalid bitcode signature");
-
+
// We expect a number of well-defined blocks, though we don't necessarily
// need to understand them all.
while (!Stream.AtEndOfStream()) {
unsigned Code = Stream.ReadCode();
-
+
if (Code != bitc::ENTER_SUBBLOCK)
return Error("Invalid record at top-level");
-
+
unsigned BlockID = Stream.ReadSubBlockID();
-
+
// We only know the MODULE subblock ID.
switch (BlockID) {
case bitc::BLOCKINFO_BLOCK_ID:
@@ -1527,22 +1547,61 @@ bool BitcodeReader::ParseBitcode() {
break;
}
}
-
+
return false;
}
+/// ParseMetadataAttachment - Parse metadata attachments.
+bool BitcodeReader::ParseMetadataAttachment() {
+ if (Stream.EnterSubBlock(bitc::METADATA_ATTACHMENT_ID))
+ return Error("Malformed block record");
+
+ MetadataContext &TheMetadata = Context.getMetadata();
+ SmallVector<uint64_t, 64> Record;
+ while(1) {
+ unsigned Code = Stream.ReadCode();
+ if (Code == bitc::END_BLOCK) {
+ if (Stream.ReadBlockEnd())
+ return Error("Error at end of PARAMATTR block");
+ break;
+ }
+ if (Code == bitc::DEFINE_ABBREV) {
+ Stream.ReadAbbrevRecord();
+ continue;
+ }
+ // Read a metadata attachment record.
+ Record.clear();
+ switch (Stream.ReadRecord(Code, Record)) {
+ default: // Default behavior: ignore.
+ break;
+ case bitc::METADATA_ATTACHMENT: {
+ unsigned RecordLength = Record.size();
+ if (Record.empty() || (RecordLength - 1) % 2 == 1)
+ return Error ("Invalid METADATA_ATTACHMENT reader!");
+ Instruction *Inst = InstructionList[Record[0]];
+ for (unsigned i = 1; i != RecordLength; i = i+2) {
+ unsigned Kind = Record[i];
+ Value *Node = MDValueList.getValueFwdRef(Record[i+1]);
+ TheMetadata.addMD(Kind, cast<MDNode>(Node), Inst);
+ }
+ break;
+ }
+ }
+ }
+ return false;
+}
/// ParseFunctionBody - Lazily parse the specified function body block.
bool BitcodeReader::ParseFunctionBody(Function *F) {
if (Stream.EnterSubBlock(bitc::FUNCTION_BLOCK_ID))
return Error("Malformed block record");
-
+
unsigned ModuleValueListSize = ValueList.size();
-
+
// Add all the function arguments to the value table.
for(Function::arg_iterator I = F->arg_begin(), E = F->arg_end(); I != E; ++I)
ValueList.push_back(I);
-
+
unsigned NextValueNo = ValueList.size();
BasicBlock *CurBB = 0;
unsigned CurBBNo = 0;
@@ -1556,7 +1615,7 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
return Error("Error at end of function block");
break;
}
-
+
if (Code == bitc::ENTER_SUBBLOCK) {
switch (Stream.ReadSubBlockID()) {
default: // Skip unknown content.
@@ -1570,15 +1629,18 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
case bitc::VALUE_SYMTAB_BLOCK_ID:
if (ParseValueSymbolTable()) return true;
break;
+ case bitc::METADATA_ATTACHMENT_ID:
+ if (ParseMetadataAttachment()) return true;
+ break;
}
continue;
}
-
+
if (Code == bitc::DEFINE_ABBREV) {
Stream.ReadAbbrevRecord();
continue;
}
-
+
// Read a record.
Record.clear();
Instruction *I = 0;
@@ -1595,7 +1657,7 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
FunctionBBs[i] = BasicBlock::Create(Context, "", F);
CurBB = FunctionBBs[0];
continue;
-
+
case bitc::FUNC_CODE_INST_BINOP: { // BINOP: [opval, ty, opval, opcode]
unsigned OpNum = 0;
Value *LHS, *RHS;
@@ -1603,12 +1665,24 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
getValue(Record, OpNum, LHS->getType(), RHS) ||
OpNum+1 > Record.size())
return Error("Invalid BINOP record");
-
+
int Opc = GetDecodedBinaryOpcode(Record[OpNum++], LHS->getType());
if (Opc == -1) return Error("Invalid BINOP record");
I = BinaryOperator::Create((Instruction::BinaryOps)Opc, LHS, RHS);
- if (OpNum < Record.size())
- SetOptimizationFlags(I, Record[3]);
+ InstructionList.push_back(I);
+ if (OpNum < Record.size()) {
+ if (Opc == Instruction::Add ||
+ Opc == Instruction::Sub ||
+ Opc == Instruction::Mul) {
+ if (Record[3] & (1 << bitc::OBO_NO_SIGNED_WRAP))
+ cast<BinaryOperator>(I)->setHasNoSignedWrap(true);
+ if (Record[3] & (1 << bitc::OBO_NO_UNSIGNED_WRAP))
+ cast<BinaryOperator>(I)->setHasNoUnsignedWrap(true);
+ } else if (Opc == Instruction::SDiv) {
+ if (Record[3] & (1 << bitc::SDIV_EXACT))
+ cast<BinaryOperator>(I)->setIsExact(true);
+ }
+ }
break;
}
case bitc::FUNC_CODE_INST_CAST: { // CAST: [opval, opty, destty, castopc]
@@ -1617,12 +1691,13 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
if (getValueTypePair(Record, OpNum, NextValueNo, Op) ||
OpNum+2 != Record.size())
return Error("Invalid CAST record");
-
+
const Type *ResTy = getTypeByID(Record[OpNum]);
int Opc = GetDecodedCastOpcode(Record[OpNum+1]);
if (Opc == -1 || ResTy == 0)
return Error("Invalid CAST record");
I = CastInst::Create((Instruction::CastOps)Opc, Op, ResTy);
+ InstructionList.push_back(I);
break;
}
case bitc::FUNC_CODE_INST_INBOUNDS_GEP:
@@ -1641,11 +1716,12 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
}
I = GetElementPtrInst::Create(BasePtr, GEPIdx.begin(), GEPIdx.end());
+ InstructionList.push_back(I);
if (BitCode == bitc::FUNC_CODE_INST_INBOUNDS_GEP)
- cast<GEPOperator>(I)->setIsInBounds(true);
+ cast<GetElementPtrInst>(I)->setIsInBounds(true);
break;
}
-
+
case bitc::FUNC_CODE_INST_EXTRACTVAL: {
// EXTRACTVAL: [opty, opval, n x indices]
unsigned OpNum = 0;
@@ -1664,9 +1740,10 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
I = ExtractValueInst::Create(Agg,
EXTRACTVALIdx.begin(), EXTRACTVALIdx.end());
+ InstructionList.push_back(I);
break;
}
-
+
case bitc::FUNC_CODE_INST_INSERTVAL: {
// INSERTVAL: [opty, opval, opty, opval, n x indices]
unsigned OpNum = 0;
@@ -1688,9 +1765,10 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
I = InsertValueInst::Create(Agg, Val,
INSERTVALIdx.begin(), INSERTVALIdx.end());
+ InstructionList.push_back(I);
break;
}
-
+
case bitc::FUNC_CODE_INST_SELECT: { // SELECT: [opval, ty, opval, opval]
// obsolete form of select
// handles select i1 ... in old bitcode
@@ -1700,11 +1778,12 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
getValue(Record, OpNum, TrueVal->getType(), FalseVal) ||
getValue(Record, OpNum, Type::getInt1Ty(Context), Cond))
return Error("Invalid SELECT record");
-
+
I = SelectInst::Create(Cond, TrueVal, FalseVal);
+ InstructionList.push_back(I);
break;
}
-
+
case bitc::FUNC_CODE_INST_VSELECT: {// VSELECT: [ty,opval,opval,predty,pred]
// new form of select
// handles select i1 or select [N x i1]
@@ -1719,18 +1798,19 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
if (const VectorType* vector_type =
dyn_cast<const VectorType>(Cond->getType())) {
// expect <n x i1>
- if (vector_type->getElementType() != Type::getInt1Ty(Context))
+ if (vector_type->getElementType() != Type::getInt1Ty(Context))
return Error("Invalid SELECT condition type");
} else {
// expect i1
- if (Cond->getType() != Type::getInt1Ty(Context))
+ if (Cond->getType() != Type::getInt1Ty(Context))
return Error("Invalid SELECT condition type");
- }
-
+ }
+
I = SelectInst::Create(Cond, TrueVal, FalseVal);
+ InstructionList.push_back(I);
break;
}
-
+
case bitc::FUNC_CODE_INST_EXTRACTELT: { // EXTRACTELT: [opty, opval, opval]
unsigned OpNum = 0;
Value *Vec, *Idx;
@@ -1738,21 +1818,23 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
getValue(Record, OpNum, Type::getInt32Ty(Context), Idx))
return Error("Invalid EXTRACTELT record");
I = ExtractElementInst::Create(Vec, Idx);
+ InstructionList.push_back(I);
break;
}
-
+
case bitc::FUNC_CODE_INST_INSERTELT: { // INSERTELT: [ty, opval,opval,opval]
unsigned OpNum = 0;
Value *Vec, *Elt, *Idx;
if (getValueTypePair(Record, OpNum, NextValueNo, Vec) ||
- getValue(Record, OpNum,
+ getValue(Record, OpNum,
cast<VectorType>(Vec->getType())->getElementType(), Elt) ||
getValue(Record, OpNum, Type::getInt32Ty(Context), Idx))
return Error("Invalid INSERTELT record");
I = InsertElementInst::Create(Vec, Elt, Idx);
+ InstructionList.push_back(I);
break;
}
-
+
case bitc::FUNC_CODE_INST_SHUFFLEVEC: {// SHUFFLEVEC: [opval,ty,opval,opval]
unsigned OpNum = 0;
Value *Vec1, *Vec2, *Mask;
@@ -1763,6 +1845,7 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
if (getValueTypePair(Record, OpNum, NextValueNo, Mask))
return Error("Invalid SHUFFLEVEC record");
I = new ShuffleVectorInst(Vec1, Vec2, Mask);
+ InstructionList.push_back(I);
break;
}
@@ -1779,11 +1862,12 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
getValue(Record, OpNum, LHS->getType(), RHS) ||
OpNum+1 != Record.size())
return Error("Invalid CMP record");
-
+
if (LHS->getType()->isFPOrFPVector())
I = new FCmpInst((FCmpInst::Predicate)Record[OpNum], LHS, RHS);
else
I = new ICmpInst((ICmpInst::Predicate)Record[OpNum], LHS, RHS);
+ InstructionList.push_back(I);
break;
}
@@ -1795,14 +1879,16 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
getValueTypePair(Record, OpNum, NextValueNo, Op);
unsigned Index = Record[1];
I = ExtractValueInst::Create(Op, Index);
+ InstructionList.push_back(I);
break;
}
-
+
case bitc::FUNC_CODE_INST_RET: // RET: [opty,opval<optional>]
{
unsigned Size = Record.size();
if (Size == 0) {
I = ReturnInst::Create(Context);
+ InstructionList.push_back(I);
break;
}
@@ -1822,15 +1908,18 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
Value *RV = UndefValue::get(ReturnType);
for (unsigned i = 0, e = Vs.size(); i != e; ++i) {
I = InsertValueInst::Create(RV, Vs[i], i, "mrv");
+ InstructionList.push_back(I);
CurBB->getInstList().push_back(I);
ValueList.AssignValue(I, NextValueNo++);
RV = I;
}
I = ReturnInst::Create(Context, RV);
+ InstructionList.push_back(I);
break;
}
I = ReturnInst::Create(Context, Vs[0]);
+ InstructionList.push_back(I);
break;
}
case bitc::FUNC_CODE_INST_BR: { // BR: [bb#, bb#, opval] or [bb#]
@@ -1840,14 +1929,17 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
if (TrueDest == 0)
return Error("Invalid BR record");
- if (Record.size() == 1)
+ if (Record.size() == 1) {
I = BranchInst::Create(TrueDest);
+ InstructionList.push_back(I);
+ }
else {
BasicBlock *FalseDest = getBasicBlock(Record[1]);
Value *Cond = getFnValueByID(Record[2], Type::getInt1Ty(Context));
if (FalseDest == 0 || Cond == 0)
return Error("Invalid BR record");
I = BranchInst::Create(TrueDest, FalseDest, Cond);
+ InstructionList.push_back(I);
}
break;
}
@@ -1861,8 +1953,9 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
return Error("Invalid SWITCH record");
unsigned NumCases = (Record.size()-3)/2;
SwitchInst *SI = SwitchInst::Create(Cond, Default, NumCases);
+ InstructionList.push_back(SI);
for (unsigned i = 0, e = NumCases; i != e; ++i) {
- ConstantInt *CaseVal =
+ ConstantInt *CaseVal =
dyn_cast_or_null<ConstantInt>(getFnValueByID(Record[3+i*2], OpTy));
BasicBlock *DestBB = getBasicBlock(Record[1+3+i*2]);
if (CaseVal == 0 || DestBB == 0) {
@@ -1874,7 +1967,7 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
I = SI;
break;
}
-
+
case bitc::FUNC_CODE_INST_INVOKE: {
// INVOKE: [attrs, cc, normBB, unwindBB, fnty, op0,op1,op2, ...]
if (Record.size() < 4) return Error("Invalid INVOKE record");
@@ -1882,12 +1975,12 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
unsigned CCInfo = Record[1];
BasicBlock *NormalBB = getBasicBlock(Record[2]);
BasicBlock *UnwindBB = getBasicBlock(Record[3]);
-
+
unsigned OpNum = 4;
Value *Callee;
if (getValueTypePair(Record, OpNum, NextValueNo, Callee))
return Error("Invalid INVOKE record");
-
+
const PointerType *CalleeTy = dyn_cast<PointerType>(Callee->getType());
const FunctionType *FTy = !CalleeTy ? 0 :
dyn_cast<FunctionType>(CalleeTy->getElementType());
@@ -1896,13 +1989,13 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
if (FTy == 0 || NormalBB == 0 || UnwindBB == 0 ||
Record.size() < OpNum+FTy->getNumParams())
return Error("Invalid INVOKE record");
-
+
SmallVector<Value*, 16> Ops;
for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i, ++OpNum) {
Ops.push_back(getFnValueByID(Record[OpNum], FTy->getParamType(i)));
if (Ops.back() == 0) return Error("Invalid INVOKE record");
}
-
+
if (!FTy->isVarArg()) {
if (Record.size() != OpNum)
return Error("Invalid INVOKE record");
@@ -1915,28 +2008,33 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
Ops.push_back(Op);
}
}
-
+
I = InvokeInst::Create(Callee, NormalBB, UnwindBB,
Ops.begin(), Ops.end());
- cast<InvokeInst>(I)->setCallingConv(CCInfo);
+ InstructionList.push_back(I);
+ cast<InvokeInst>(I)->setCallingConv(
+ static_cast<CallingConv::ID>(CCInfo));
cast<InvokeInst>(I)->setAttributes(PAL);
break;
}
case bitc::FUNC_CODE_INST_UNWIND: // UNWIND
I = new UnwindInst(Context);
+ InstructionList.push_back(I);
break;
case bitc::FUNC_CODE_INST_UNREACHABLE: // UNREACHABLE
I = new UnreachableInst(Context);
+ InstructionList.push_back(I);
break;
case bitc::FUNC_CODE_INST_PHI: { // PHI: [ty, val0,bb0, ...]
if (Record.size() < 1 || ((Record.size()-1)&1))
return Error("Invalid PHI record");
const Type *Ty = getTypeByID(Record[0]);
if (!Ty) return Error("Invalid PHI record");
-
+
PHINode *PN = PHINode::Create(Ty);
+ InstructionList.push_back(PN);
PN->reserveOperandSpace((Record.size()-1)/2);
-
+
for (unsigned i = 0, e = Record.size()-1; i != e; i += 2) {
Value *V = getFnValueByID(Record[1+i], Ty);
BasicBlock *BB = getBasicBlock(Record[2+i]);
@@ -1946,7 +2044,7 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
I = PN;
break;
}
-
+
case bitc::FUNC_CODE_INST_MALLOC: { // MALLOC: [instty, op, align]
if (Record.size() < 3)
return Error("Invalid MALLOC record");
@@ -1956,6 +2054,7 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
unsigned Align = Record[2];
if (!Ty || !Size) return Error("Invalid MALLOC record");
I = new MallocInst(Ty->getElementType(), Size, (1 << Align) >> 1);
+ InstructionList.push_back(I);
break;
}
case bitc::FUNC_CODE_INST_FREE: { // FREE: [op, opty]
@@ -1965,6 +2064,7 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
OpNum != Record.size())
return Error("Invalid FREE record");
I = new FreeInst(Op);
+ InstructionList.push_back(I);
break;
}
case bitc::FUNC_CODE_INST_ALLOCA: { // ALLOCA: [instty, op, align]
@@ -1976,6 +2076,7 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
unsigned Align = Record[2];
if (!Ty || !Size) return Error("Invalid ALLOCA record");
I = new AllocaInst(Ty->getElementType(), Size, (1 << Align) >> 1);
+ InstructionList.push_back(I);
break;
}
case bitc::FUNC_CODE_INST_LOAD: { // LOAD: [opty, op, align, vol]
@@ -1984,20 +2085,22 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
if (getValueTypePair(Record, OpNum, NextValueNo, Op) ||
OpNum+2 != Record.size())
return Error("Invalid LOAD record");
-
+
I = new LoadInst(Op, "", Record[OpNum+1], (1 << Record[OpNum]) >> 1);
+ InstructionList.push_back(I);
break;
}
case bitc::FUNC_CODE_INST_STORE2: { // STORE2:[ptrty, ptr, val, align, vol]
unsigned OpNum = 0;
Value *Val, *Ptr;
if (getValueTypePair(Record, OpNum, NextValueNo, Ptr) ||
- getValue(Record, OpNum,
+ getValue(Record, OpNum,
cast<PointerType>(Ptr->getType())->getElementType(), Val) ||
OpNum+2 != Record.size())
return Error("Invalid STORE record");
-
+
I = new StoreInst(Val, Ptr, Record[OpNum+1], (1 << Record[OpNum]) >> 1);
+ InstructionList.push_back(I);
break;
}
case bitc::FUNC_CODE_INST_STORE: { // STORE:[val, valty, ptr, align, vol]
@@ -2005,33 +2108,34 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
unsigned OpNum = 0;
Value *Val, *Ptr;
if (getValueTypePair(Record, OpNum, NextValueNo, Val) ||
- getValue(Record, OpNum,
+ getValue(Record, OpNum,
PointerType::getUnqual(Val->getType()), Ptr)||
OpNum+2 != Record.size())
return Error("Invalid STORE record");
-
+
I = new StoreInst(Val, Ptr, Record[OpNum+1], (1 << Record[OpNum]) >> 1);
+ InstructionList.push_back(I);
break;
}
case bitc::FUNC_CODE_INST_CALL: {
// CALL: [paramattrs, cc, fnty, fnid, arg0, arg1...]
if (Record.size() < 3)
return Error("Invalid CALL record");
-
+
AttrListPtr PAL = getAttributes(Record[0]);
unsigned CCInfo = Record[1];
-
+
unsigned OpNum = 2;
Value *Callee;
if (getValueTypePair(Record, OpNum, NextValueNo, Callee))
return Error("Invalid CALL record");
-
+
const PointerType *OpTy = dyn_cast<PointerType>(Callee->getType());
const FunctionType *FTy = 0;
if (OpTy) FTy = dyn_cast<FunctionType>(OpTy->getElementType());
if (!FTy || Record.size() < FTy->getNumParams()+OpNum)
return Error("Invalid CALL record");
-
+
SmallVector<Value*, 16> Args;
// Read the fixed params.
for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i, ++OpNum) {
@@ -2041,7 +2145,7 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
Args.push_back(getFnValueByID(Record[OpNum], FTy->getParamType(i)));
if (Args.back() == 0) return Error("Invalid CALL record");
}
-
+
// Read type/value pairs for varargs params.
if (!FTy->isVarArg()) {
if (OpNum != Record.size())
@@ -2054,9 +2158,11 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
Args.push_back(Op);
}
}
-
+
I = CallInst::Create(Callee, Args.begin(), Args.end());
- cast<CallInst>(I)->setCallingConv(CCInfo>>1);
+ InstructionList.push_back(I);
+ cast<CallInst>(I)->setCallingConv(
+ static_cast<CallingConv::ID>(CCInfo>>1));
cast<CallInst>(I)->setTailCall(CCInfo & 1);
cast<CallInst>(I)->setAttributes(PAL);
break;
@@ -2070,6 +2176,7 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
if (!OpTy || !Op || !ResTy)
return Error("Invalid VAARG record");
I = new VAArgInst(Op, ResTy);
+ InstructionList.push_back(I);
break;
}
}
@@ -2081,18 +2188,18 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
return Error("Invalid instruction with no BB");
}
CurBB->getInstList().push_back(I);
-
+
// If this was a terminator instruction, move to the next block.
if (isa<TerminatorInst>(I)) {
++CurBBNo;
CurBB = CurBBNo < FunctionBBs.size() ? FunctionBBs[CurBBNo] : 0;
}
-
+
// Non-void values get registered in the value table for future use.
if (I && I->getType() != Type::getVoidTy(Context))
ValueList.AssignValue(I, NextValueNo++);
}
-
+
// Check the function list for unresolved values.
if (Argument *A = dyn_cast<Argument>(ValueList.back())) {
if (A->getParent() == 0) {
@@ -2106,11 +2213,11 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
return Error("Never resolved value found in function!");
}
}
-
+
// Trim the value list down to the size it was before we parsed this function.
ValueList.shrinkTo(ModuleValueListSize);
std::vector<BasicBlock*>().swap(FunctionBBs);
-
+
return false;
}
@@ -2122,16 +2229,16 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
bool BitcodeReader::materializeFunction(Function *F, std::string *ErrInfo) {
// If it already is material, ignore the request.
if (!F->hasNotBeenReadFromBitcode()) return false;
-
- DenseMap<Function*, std::pair<uint64_t, unsigned> >::iterator DFII =
+
+ DenseMap<Function*, std::pair<uint64_t, unsigned> >::iterator DFII =
DeferredFunctionInfo.find(F);
assert(DFII != DeferredFunctionInfo.end() && "Deferred function not found!");
-
+
// Move the bit stream to the saved position of the deferred function body and
// restore the real linkage type for the function.
Stream.JumpToBit(DFII->second.first);
F->setLinkage((GlobalValue::LinkageTypes)DFII->second.second);
-
+
if (ParseFunctionBody(F)) {
if (ErrInfo) *ErrInfo = ErrorString;
return true;
@@ -2148,7 +2255,7 @@ bool BitcodeReader::materializeFunction(Function *F, std::string *ErrInfo) {
}
}
}
-
+
return false;
}
@@ -2156,9 +2263,9 @@ void BitcodeReader::dematerializeFunction(Function *F) {
// If this function isn't materialized, or if it is a proto, this is a noop.
if (F->hasNotBeenReadFromBitcode() || F->isDeclaration())
return;
-
+
assert(DeferredFunctionInfo.count(F) && "No info to read function later?");
-
+
// Just forget the function body, we can remat it later.
F->deleteBody();
F->setLinkage(GlobalValue::GhostLinkage);
@@ -2174,9 +2281,9 @@ Module *BitcodeReader::materializeModule(std::string *ErrInfo) {
materializeFunction(F, ErrInfo))
return 0;
- // Upgrade any intrinsic calls that slipped through (should not happen!) and
- // delete the old functions to clean up. We can't do this unless the entire
- // module is materialized because there could always be another function body
+ // Upgrade any intrinsic calls that slipped through (should not happen!) and
+ // delete the old functions to clean up. We can't do this unless the entire
+ // module is materialized because there could always be another function body
// with calls to the old function.
for (std::vector<std::pair<Function*, Function*> >::iterator I =
UpgradedIntrinsics.begin(), E = UpgradedIntrinsics.end(); I != E; ++I) {
@@ -2225,7 +2332,7 @@ ModuleProvider *llvm::getBitcodeModuleProvider(MemoryBuffer *Buffer,
if (R->ParseBitcode()) {
if (ErrMsg)
*ErrMsg = R->getErrorString();
-
+
// Don't let the BitcodeReader dtor delete 'Buffer'.
R->releaseMemoryBuffer();
delete R;
@@ -2236,25 +2343,25 @@ ModuleProvider *llvm::getBitcodeModuleProvider(MemoryBuffer *Buffer,
/// ParseBitcodeFile - Read the specified bitcode file, returning the module.
/// If an error occurs, return null and fill in *ErrMsg if non-null.
-Module *llvm::ParseBitcodeFile(MemoryBuffer *Buffer, LLVMContext& Context,
+Module *llvm::ParseBitcodeFile(MemoryBuffer *Buffer, LLVMContext& Context,
std::string *ErrMsg){
BitcodeReader *R;
- R = static_cast<BitcodeReader*>(getBitcodeModuleProvider(Buffer, Context,
+ R = static_cast<BitcodeReader*>(getBitcodeModuleProvider(Buffer, Context,
ErrMsg));
if (!R) return 0;
-
+
// Read in the entire module.
Module *M = R->materializeModule(ErrMsg);
// Don't let the BitcodeReader dtor delete 'Buffer', regardless of whether
// there was an error.
R->releaseMemoryBuffer();
-
+
// If there was no error, tell ModuleProvider not to delete it when its dtor
// is run.
if (M)
M = R->releaseModule(ErrMsg);
-
+
delete R;
return M;
}
diff --git a/libclamav/c++/llvm/lib/Bitcode/Reader/BitcodeReader.h b/libclamav/c++/llvm/lib/Bitcode/Reader/BitcodeReader.h
index a7853ab..eefc7bd 100644
--- a/libclamav/c++/llvm/lib/Bitcode/Reader/BitcodeReader.h
+++ b/libclamav/c++/llvm/lib/Bitcode/Reader/BitcodeReader.h
@@ -132,6 +132,8 @@ class BitcodeReader : public ModuleProvider {
std::vector<PATypeHolder> TypeList;
BitcodeReaderValueList ValueList;
BitcodeReaderMDValueList MDValueList;
+ SmallVector<Instruction *, 64> InstructionList;
+
std::vector<std::pair<GlobalVariable*, unsigned> > GlobalInits;
std::vector<std::pair<GlobalAlias*, unsigned> > AliasInits;
@@ -250,6 +252,7 @@ private:
bool ParseFunctionBody(Function *F);
bool ResolveGlobalAndAliasInits();
bool ParseMetadata();
+ bool ParseMetadataAttachment();
};
} // End llvm namespace
diff --git a/libclamav/c++/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/libclamav/c++/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
index 9cb5758..5857c59 100644
--- a/libclamav/c++/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+++ b/libclamav/c++/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
@@ -34,19 +34,19 @@ using namespace llvm;
/// be kept in sync with the reader, but need to be consistent within this file.
enum {
CurVersion = 0,
-
+
// VALUE_SYMTAB_BLOCK abbrev id's.
VST_ENTRY_8_ABBREV = bitc::FIRST_APPLICATION_ABBREV,
VST_ENTRY_7_ABBREV,
VST_ENTRY_6_ABBREV,
VST_BBENTRY_6_ABBREV,
-
+
// CONSTANTS_BLOCK abbrev id's.
CONSTANTS_SETTYPE_ABBREV = bitc::FIRST_APPLICATION_ABBREV,
CONSTANTS_INTEGER_ABBREV,
CONSTANTS_CE_CAST_Abbrev,
CONSTANTS_NULL_Abbrev,
-
+
// FUNCTION_BLOCK abbrev id's.
FUNCTION_INST_LOAD_ABBREV = bitc::FIRST_APPLICATION_ABBREV,
FUNCTION_INST_BINOP_ABBREV,
@@ -102,24 +102,24 @@ static unsigned GetEncodedBinaryOpcode(unsigned Opcode) {
-static void WriteStringRecord(unsigned Code, const std::string &Str,
+static void WriteStringRecord(unsigned Code, const std::string &Str,
unsigned AbbrevToUse, BitstreamWriter &Stream) {
SmallVector<unsigned, 64> Vals;
-
+
// Code: [strchar x N]
for (unsigned i = 0, e = Str.size(); i != e; ++i)
Vals.push_back(Str[i]);
-
+
// Emit the finished record.
Stream.EmitRecord(Code, Vals, AbbrevToUse);
}
// Emit information about parameter attributes.
-static void WriteAttributeTable(const ValueEnumerator &VE,
+static void WriteAttributeTable(const ValueEnumerator &VE,
BitstreamWriter &Stream) {
const std::vector<AttrListPtr> &Attrs = VE.getAttributes();
if (Attrs.empty()) return;
-
+
Stream.EnterSubblock(bitc::PARAMATTR_BLOCK_ID, 3);
SmallVector<uint64_t, 64> Record;
@@ -140,21 +140,21 @@ static void WriteAttributeTable(const ValueEnumerator &VE,
Record.push_back(FauxAttr);
}
-
+
Stream.EmitRecord(bitc::PARAMATTR_CODE_ENTRY, Record);
Record.clear();
}
-
+
Stream.ExitBlock();
}
/// WriteTypeTable - Write out the type table for a module.
static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
const ValueEnumerator::TypeList &TypeList = VE.getTypes();
-
+
Stream.EnterSubblock(bitc::TYPE_BLOCK_ID, 4 /*count from # abbrevs */);
SmallVector<uint64_t, 64> TypeVals;
-
+
// Abbrev for TYPE_CODE_POINTER.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_POINTER));
@@ -162,7 +162,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Log2_32_Ceil(VE.getTypes().size()+1)));
Abbv->Add(BitCodeAbbrevOp(0)); // Addrspace = 0
unsigned PtrAbbrev = Stream.EmitAbbrev(Abbv);
-
+
// Abbrev for TYPE_CODE_FUNCTION.
Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_FUNCTION));
@@ -172,7 +172,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
Log2_32_Ceil(VE.getTypes().size()+1)));
unsigned FunctionAbbrev = Stream.EmitAbbrev(Abbv);
-
+
// Abbrev for TYPE_CODE_STRUCT.
Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_STRUCT));
@@ -181,7 +181,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
Log2_32_Ceil(VE.getTypes().size()+1)));
unsigned StructAbbrev = Stream.EmitAbbrev(Abbv);
-
+
// Abbrev for TYPE_CODE_ARRAY.
Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_ARRAY));
@@ -189,18 +189,18 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
Log2_32_Ceil(VE.getTypes().size()+1)));
unsigned ArrayAbbrev = Stream.EmitAbbrev(Abbv);
-
+
// Emit an entry count so the reader can reserve space.
TypeVals.push_back(TypeList.size());
Stream.EmitRecord(bitc::TYPE_CODE_NUMENTRY, TypeVals);
TypeVals.clear();
-
+
// Loop over all of the types, emitting each in turn.
for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
const Type *T = TypeList[i].first;
int AbbrevToUse = 0;
unsigned Code = 0;
-
+
switch (T->getTypeID()) {
default: llvm_unreachable("Unknown type!");
case Type::VoidTyID: Code = bitc::TYPE_CODE_VOID; break;
@@ -274,7 +274,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Stream.EmitRecord(Code, TypeVals, AbbrevToUse);
TypeVals.clear();
}
-
+
Stream.ExitBlock();
}
@@ -337,7 +337,7 @@ static void WriteModuleInfo(const Module *M, const ValueEnumerator &VE,
GV != E; ++GV) {
MaxAlignment = std::max(MaxAlignment, GV->getAlignment());
MaxGlobalType = std::max(MaxGlobalType, VE.getTypeID(GV->getType()));
-
+
if (!GV->hasSection()) continue;
// Give section names unique ID's.
unsigned &Entry = SectionMap[GV->getSection()];
@@ -367,10 +367,10 @@ static void WriteModuleInfo(const Module *M, const ValueEnumerator &VE,
}
}
}
-
+
// Emit abbrev for globals, now that we know # sections and max alignment.
unsigned SimpleGVarAbbrev = 0;
- if (!M->global_empty()) {
+ if (!M->global_empty()) {
// Add an abbrev for common globals with no visibility or thread localness.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::MODULE_CODE_GLOBALVAR));
@@ -394,14 +394,14 @@ static void WriteModuleInfo(const Module *M, const ValueEnumerator &VE,
// Don't bother emitting vis + thread local.
SimpleGVarAbbrev = Stream.EmitAbbrev(Abbv);
}
-
+
// Emit the global variable information.
SmallVector<unsigned, 64> Vals;
for (Module::const_global_iterator GV = M->global_begin(),E = M->global_end();
GV != E; ++GV) {
unsigned AbbrevToUse = 0;
- // GLOBALVAR: [type, isconst, initid,
+ // GLOBALVAR: [type, isconst, initid,
// linkage, alignment, section, visibility, threadlocal]
Vals.push_back(VE.getTypeID(GV->getType()));
Vals.push_back(GV->isConstant());
@@ -410,14 +410,14 @@ static void WriteModuleInfo(const Module *M, const ValueEnumerator &VE,
Vals.push_back(getEncodedLinkage(GV));
Vals.push_back(Log2_32(GV->getAlignment())+1);
Vals.push_back(GV->hasSection() ? SectionMap[GV->getSection()] : 0);
- if (GV->isThreadLocal() ||
+ if (GV->isThreadLocal() ||
GV->getVisibility() != GlobalValue::DefaultVisibility) {
Vals.push_back(getEncodedVisibility(GV));
Vals.push_back(GV->isThreadLocal());
} else {
AbbrevToUse = SimpleGVarAbbrev;
}
-
+
Stream.EmitRecord(bitc::MODULE_CODE_GLOBALVAR, Vals, AbbrevToUse);
Vals.clear();
}
@@ -435,13 +435,13 @@ static void WriteModuleInfo(const Module *M, const ValueEnumerator &VE,
Vals.push_back(F->hasSection() ? SectionMap[F->getSection()] : 0);
Vals.push_back(getEncodedVisibility(F));
Vals.push_back(F->hasGC() ? GCMap[F->getGC()] : 0);
-
+
unsigned AbbrevToUse = 0;
Stream.EmitRecord(bitc::MODULE_CODE_FUNCTION, Vals, AbbrevToUse);
Vals.clear();
}
-
-
+
+
// Emit the alias information.
for (Module::const_alias_iterator AI = M->alias_begin(), E = M->alias_end();
AI != E; ++AI) {
@@ -496,7 +496,7 @@ static void WriteModuleMetadata(const ValueEnumerator &VE,
unsigned MDSAbbrev = 0;
SmallVector<uint64_t, 64> Record;
for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
-
+
if (const MDNode *N = dyn_cast<MDNode>(Vals[i].first)) {
if (!StartedMetadataBlock) {
Stream.EnterSubblock(bitc::METADATA_BLOCK_ID, 3);
@@ -506,7 +506,7 @@ static void WriteModuleMetadata(const ValueEnumerator &VE,
} else if (const MDString *MDS = dyn_cast<MDString>(Vals[i].first)) {
if (!StartedMetadataBlock) {
Stream.EnterSubblock(bitc::METADATA_BLOCK_ID, 3);
-
+
// Abbrev for METADATA_STRING.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::METADATA_STRING));
@@ -515,12 +515,12 @@ static void WriteModuleMetadata(const ValueEnumerator &VE,
MDSAbbrev = Stream.EmitAbbrev(Abbv);
StartedMetadataBlock = true;
}
-
+
// Code: [strchar x N]
const char *StrBegin = MDS->begin();
for (unsigned i = 0, e = MDS->length(); i != e; ++i)
Record.push_back(StrBegin[i]);
-
+
// Emit the finished record.
Stream.EmitRecord(bitc::METADATA_STRING, Record, MDSAbbrev);
Record.clear();
@@ -540,25 +540,92 @@ static void WriteModuleMetadata(const ValueEnumerator &VE,
// Write named metadata elements.
for (unsigned i = 0, e = NMD->getNumElements(); i != e; ++i) {
- if (NMD->getElement(i))
+ if (NMD->getElement(i))
Record.push_back(VE.getValueID(NMD->getElement(i)));
- else
+ else
Record.push_back(0);
}
Stream.EmitRecord(bitc::METADATA_NAMED_NODE, Record, 0);
Record.clear();
}
}
-
+
+ if (StartedMetadataBlock)
+ Stream.ExitBlock();
+}
+
+static void WriteMetadataAttachment(const Function &F,
+ const ValueEnumerator &VE,
+ BitstreamWriter &Stream) {
+ bool StartedMetadataBlock = false;
+ SmallVector<uint64_t, 64> Record;
+
+ // Write metadata attachments
+ // METADATA_ATTACHMENT - [m x [value, [n x [id, mdnode]]]
+ MetadataContext &TheMetadata = F.getContext().getMetadata();
+ for (Function::const_iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
+ for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
+ I != E; ++I) {
+ const MetadataContext::MDMapTy *P = TheMetadata.getMDs(I);
+ if (!P) continue;
+ bool RecordedInstruction = false;
+ for (MetadataContext::MDMapTy::const_iterator PI = P->begin(),
+ PE = P->end(); PI != PE; ++PI) {
+ if (MDNode *ND = dyn_cast_or_null<MDNode>(PI->second)) {
+ if (RecordedInstruction == false) {
+ Record.push_back(VE.getInstructionID(I));
+ RecordedInstruction = true;
+ }
+ Record.push_back(PI->first);
+ Record.push_back(VE.getValueID(ND));
+ }
+ }
+ if (!StartedMetadataBlock) {
+ Stream.EnterSubblock(bitc::METADATA_ATTACHMENT_ID, 3);
+ StartedMetadataBlock = true;
+ }
+ Stream.EmitRecord(bitc::METADATA_ATTACHMENT, Record, 0);
+ Record.clear();
+ }
+
+ if (StartedMetadataBlock)
+ Stream.ExitBlock();
+}
+
+static void WriteModuleMetadataStore(const Module *M,
+ const ValueEnumerator &VE,
+ BitstreamWriter &Stream) {
+
+ bool StartedMetadataBlock = false;
+ SmallVector<uint64_t, 64> Record;
+
+ // Write metadata kinds
+ // METADATA_KIND - [n x [id, name]]
+ MetadataContext &TheMetadata = M->getContext().getMetadata();
+ const StringMap<unsigned> *Kinds = TheMetadata.getHandlerNames();
+ for (StringMap<unsigned>::const_iterator
+ I = Kinds->begin(), E = Kinds->end(); I != E; ++I) {
+ Record.push_back(I->second);
+ StringRef KName = I->first();
+ for (unsigned i = 0, e = KName.size(); i != e; ++i)
+ Record.push_back(KName[i]);
+ if (!StartedMetadataBlock) {
+ Stream.EnterSubblock(bitc::METADATA_BLOCK_ID, 3);
+ StartedMetadataBlock = true;
+ }
+ Stream.EmitRecord(bitc::METADATA_KIND, Record, 0);
+ Record.clear();
+ }
+
if (StartedMetadataBlock)
- Stream.ExitBlock();
+ Stream.ExitBlock();
}
static void WriteConstants(unsigned FirstVal, unsigned LastVal,
const ValueEnumerator &VE,
BitstreamWriter &Stream, bool isGlobal) {
if (FirstVal == LastVal) return;
-
+
Stream.EnterSubblock(bitc::CONSTANTS_BLOCK_ID, 4);
unsigned AggregateAbbrev = 0;
@@ -592,8 +659,8 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Char6));
CString6Abbrev = Stream.EmitAbbrev(Abbv);
- }
-
+ }
+
SmallVector<uint64_t, 64> Record;
const ValueEnumerator::ValueList &Vals = VE.getValues();
@@ -608,16 +675,16 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
CONSTANTS_SETTYPE_ABBREV);
Record.clear();
}
-
+
if (const InlineAsm *IA = dyn_cast<InlineAsm>(V)) {
Record.push_back(unsigned(IA->hasSideEffects()));
-
+
// Add the asm string.
const std::string &AsmStr = IA->getAsmString();
Record.push_back(AsmStr.size());
for (unsigned i = 0, e = AsmStr.size(); i != e; ++i)
Record.push_back(AsmStr[i]);
-
+
// Add the constraint string.
const std::string &ConstraintStr = IA->getConstraintString();
Record.push_back(ConstraintStr.size());
@@ -644,11 +711,11 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
Code = bitc::CST_CODE_INTEGER;
AbbrevToUse = CONSTANTS_INTEGER_ABBREV;
} else { // Wide integers, > 64 bits in size.
- // We have an arbitrary precision integer value to write whose
- // bit width is > 64. However, in canonical unsigned integer
+ // We have an arbitrary precision integer value to write whose
+ // bit width is > 64. However, in canonical unsigned integer
// format it is likely that the high bits are going to be zero.
// So, we only write the number of active words.
- unsigned NWords = IV->getValue().getActiveWords();
+ unsigned NWords = IV->getValue().getActiveWords();
const uint64_t *RawWords = IV->getValue().getRawData();
for (unsigned i = 0; i != NWords; ++i) {
int64_t V = RawWords[i];
@@ -698,10 +765,10 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
unsigned char V = cast<ConstantInt>(C->getOperand(i))->getZExtValue();
Record.push_back(V);
isCStr7 &= (V & 128) == 0;
- if (isCStrChar6)
+ if (isCStrChar6)
isCStrChar6 = BitCodeAbbrevOp::isChar6(V);
}
-
+
if (isCStrChar6)
AbbrevToUse = CString6Abbrev;
else if (isCStr7)
@@ -796,7 +863,7 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
static void WriteModuleConstants(const ValueEnumerator &VE,
BitstreamWriter &Stream) {
const ValueEnumerator::ValueList &Vals = VE.getValues();
-
+
// Find the first constant to emit, which is the first non-globalvalue value.
// We know globalvalues have been emitted by WriteModuleInfo.
for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
@@ -816,7 +883,7 @@ static void WriteModuleConstants(const ValueEnumerator &VE,
/// instruction ID, then it is a forward reference, and it also includes the
/// type ID.
static bool PushValueAndType(const Value *V, unsigned InstID,
- SmallVector<unsigned, 64> &Vals,
+ SmallVector<unsigned, 64> &Vals,
ValueEnumerator &VE) {
unsigned ValID = VE.getValueID(V);
Vals.push_back(ValID);
@@ -833,6 +900,7 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
SmallVector<unsigned, 64> &Vals) {
unsigned Code = 0;
unsigned AbbrevToUse = 0;
+ VE.setInstructionID(&I);
switch (I.getOpcode()) {
default:
if (Instruction::isCast(I.getOpcode())) {
@@ -913,7 +981,7 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
Vals.push_back(cast<CmpInst>(I).getPredicate());
break;
- case Instruction::Ret:
+ case Instruction::Ret:
{
Code = bitc::FUNC_CODE_INST_RET;
unsigned NumOperands = I.getNumOperands();
@@ -951,13 +1019,13 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
const PointerType *PTy = cast<PointerType>(Callee->getType());
const FunctionType *FTy = cast<FunctionType>(PTy->getElementType());
Code = bitc::FUNC_CODE_INST_INVOKE;
-
+
Vals.push_back(VE.getAttributeID(II->getAttributes()));
Vals.push_back(II->getCallingConv());
Vals.push_back(VE.getValueID(II->getNormalDest()));
Vals.push_back(VE.getValueID(II->getUnwindDest()));
PushValueAndType(Callee, InstID, Vals, VE);
-
+
// Emit value #'s for the fixed parameters.
for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
Vals.push_back(VE.getValueID(I.getOperand(i+3))); // fixed param.
@@ -977,38 +1045,38 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
Code = bitc::FUNC_CODE_INST_UNREACHABLE;
AbbrevToUse = FUNCTION_INST_UNREACHABLE_ABBREV;
break;
-
+
case Instruction::PHI:
Code = bitc::FUNC_CODE_INST_PHI;
Vals.push_back(VE.getTypeID(I.getType()));
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i)
Vals.push_back(VE.getValueID(I.getOperand(i)));
break;
-
+
case Instruction::Malloc:
Code = bitc::FUNC_CODE_INST_MALLOC;
Vals.push_back(VE.getTypeID(I.getType()));
Vals.push_back(VE.getValueID(I.getOperand(0))); // size.
Vals.push_back(Log2_32(cast<MallocInst>(I).getAlignment())+1);
break;
-
+
case Instruction::Free:
Code = bitc::FUNC_CODE_INST_FREE;
PushValueAndType(I.getOperand(0), InstID, Vals, VE);
break;
-
+
case Instruction::Alloca:
Code = bitc::FUNC_CODE_INST_ALLOCA;
Vals.push_back(VE.getTypeID(I.getType()));
Vals.push_back(VE.getValueID(I.getOperand(0))); // size.
Vals.push_back(Log2_32(cast<AllocaInst>(I).getAlignment())+1);
break;
-
+
case Instruction::Load:
Code = bitc::FUNC_CODE_INST_LOAD;
if (!PushValueAndType(I.getOperand(0), InstID, Vals, VE)) // ptr
AbbrevToUse = FUNCTION_INST_LOAD_ABBREV;
-
+
Vals.push_back(Log2_32(cast<LoadInst>(I).getAlignment())+1);
Vals.push_back(cast<LoadInst>(I).isVolatile());
break;
@@ -1024,16 +1092,16 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
const FunctionType *FTy = cast<FunctionType>(PTy->getElementType());
Code = bitc::FUNC_CODE_INST_CALL;
-
+
const CallInst *CI = cast<CallInst>(&I);
Vals.push_back(VE.getAttributeID(CI->getAttributes()));
Vals.push_back((CI->getCallingConv() << 1) | unsigned(CI->isTailCall()));
PushValueAndType(CI->getOperand(0), InstID, Vals, VE); // Callee
-
+
// Emit value #'s for the fixed parameters.
for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
Vals.push_back(VE.getValueID(I.getOperand(i+1))); // fixed param.
-
+
// Emit type/value pairs for varargs params.
if (FTy->isVarArg()) {
unsigned NumVarargs = I.getNumOperands()-1-FTy->getNumParams();
@@ -1050,7 +1118,7 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
Vals.push_back(VE.getTypeID(I.getType())); // restype.
break;
}
-
+
Stream.EmitRecord(Code, Vals, AbbrevToUse);
Vals.clear();
}
@@ -1065,27 +1133,27 @@ static void WriteValueSymbolTable(const ValueSymbolTable &VST,
// FIXME: Set up the abbrev, we know how many values there are!
// FIXME: We know if the type names can use 7-bit ascii.
SmallVector<unsigned, 64> NameVals;
-
+
for (ValueSymbolTable::const_iterator SI = VST.begin(), SE = VST.end();
SI != SE; ++SI) {
-
+
const ValueName &Name = *SI;
-
+
// Figure out the encoding to use for the name.
bool is7Bit = true;
bool isChar6 = true;
for (const char *C = Name.getKeyData(), *E = C+Name.getKeyLength();
C != E; ++C) {
- if (isChar6)
+ if (isChar6)
isChar6 = BitCodeAbbrevOp::isChar6(*C);
if ((unsigned char)*C & 128) {
is7Bit = false;
break; // don't bother scanning the rest.
}
}
-
+
unsigned AbbrevToUse = VST_ENTRY_8_ABBREV;
-
+
// VST_ENTRY: [valueid, namechar x N]
// VST_BBENTRY: [bbid, namechar x N]
unsigned Code;
@@ -1100,12 +1168,12 @@ static void WriteValueSymbolTable(const ValueSymbolTable &VST,
else if (is7Bit)
AbbrevToUse = VST_ENTRY_7_ABBREV;
}
-
+
NameVals.push_back(VE.getValueID(SI->getValue()));
for (const char *P = Name.getKeyData(),
*E = Name.getKeyData()+Name.getKeyLength(); P != E; ++P)
NameVals.push_back((unsigned char)*P);
-
+
// Emit the finished record.
Stream.EmitRecord(Code, NameVals, AbbrevToUse);
NameVals.clear();
@@ -1114,27 +1182,27 @@ static void WriteValueSymbolTable(const ValueSymbolTable &VST,
}
/// WriteFunction - Emit a function body to the module stream.
-static void WriteFunction(const Function &F, ValueEnumerator &VE,
+static void WriteFunction(const Function &F, ValueEnumerator &VE,
BitstreamWriter &Stream) {
Stream.EnterSubblock(bitc::FUNCTION_BLOCK_ID, 4);
VE.incorporateFunction(F);
SmallVector<unsigned, 64> Vals;
-
+
// Emit the number of basic blocks, so the reader can create them ahead of
// time.
Vals.push_back(VE.getBasicBlocks().size());
Stream.EmitRecord(bitc::FUNC_CODE_DECLAREBLOCKS, Vals);
Vals.clear();
-
+
// If there are function-local constants, emit them now.
unsigned CstStart, CstEnd;
VE.getFunctionConstantRange(CstStart, CstEnd);
WriteConstants(CstStart, CstEnd, VE, Stream, false);
-
- // Keep a running idea of what the instruction ID is.
+
+ // Keep a running idea of what the instruction ID is.
unsigned InstID = CstEnd;
-
+
// Finally, emit all the instructions, in order.
for (Function::const_iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
@@ -1143,10 +1211,11 @@ static void WriteFunction(const Function &F, ValueEnumerator &VE,
if (I->getType() != Type::getVoidTy(F.getContext()))
++InstID;
}
-
+
// Emit names for all the instructions etc.
WriteValueSymbolTable(F.getValueSymbolTable(), VE, Stream);
-
+
+ WriteMetadataAttachment(F, VE, Stream);
VE.purgeFunction();
Stream.ExitBlock();
}
@@ -1156,9 +1225,9 @@ static void WriteTypeSymbolTable(const TypeSymbolTable &TST,
const ValueEnumerator &VE,
BitstreamWriter &Stream) {
if (TST.empty()) return;
-
+
Stream.EnterSubblock(bitc::TYPE_SYMTAB_BLOCK_ID, 3);
-
+
// 7-bit fixed width VST_CODE_ENTRY strings.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::VST_CODE_ENTRY));
@@ -1167,14 +1236,14 @@ static void WriteTypeSymbolTable(const TypeSymbolTable &TST,
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 7));
unsigned V7Abbrev = Stream.EmitAbbrev(Abbv);
-
+
SmallVector<unsigned, 64> NameVals;
-
- for (TypeSymbolTable::const_iterator TI = TST.begin(), TE = TST.end();
+
+ for (TypeSymbolTable::const_iterator TI = TST.begin(), TE = TST.end();
TI != TE; ++TI) {
// TST_ENTRY: [typeid, namechar x N]
NameVals.push_back(VE.getTypeID(TI->second));
-
+
const std::string &Str = TI->first;
bool is7Bit = true;
for (unsigned i = 0, e = Str.size(); i != e; ++i) {
@@ -1182,12 +1251,12 @@ static void WriteTypeSymbolTable(const TypeSymbolTable &TST,
if (Str[i] & 128)
is7Bit = false;
}
-
+
// Emit the finished record.
Stream.EmitRecord(bitc::VST_CODE_ENTRY, NameVals, is7Bit ? V7Abbrev : 0);
NameVals.clear();
}
-
+
Stream.ExitBlock();
}
@@ -1197,18 +1266,18 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
// instances: CONSTANTS_BLOCK, FUNCTION_BLOCK and VALUE_SYMTAB_BLOCK. Other
// blocks can defined their abbrevs inline.
Stream.EnterBlockInfoBlock(2);
-
+
{ // 8-bit fixed-width VST_ENTRY/VST_BBENTRY strings.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3));
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8));
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 8));
- if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
+ if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
Abbv) != VST_ENTRY_8_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
-
+
{ // 7-bit fixed width VST_ENTRY strings.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::VST_CODE_ENTRY));
@@ -1239,9 +1308,9 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != VST_BBENTRY_6_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
-
-
-
+
+
+
{ // SETTYPE abbrev for CONSTANTS_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_SETTYPE));
@@ -1251,7 +1320,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != CONSTANTS_SETTYPE_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
-
+
{ // INTEGER abbrev for CONSTANTS_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_INTEGER));
@@ -1260,7 +1329,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != CONSTANTS_INTEGER_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
-
+
{ // CE_CAST abbrev for CONSTANTS_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_CE_CAST));
@@ -1280,9 +1349,9 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != CONSTANTS_NULL_Abbrev)
llvm_unreachable("Unexpected abbrev ordering!");
}
-
+
// FIXME: This should only use space for first class types!
-
+
{ // INST_LOAD abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_LOAD));
@@ -1325,7 +1394,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != FUNCTION_INST_CAST_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
-
+
{ // INST_RET abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_RET));
@@ -1348,7 +1417,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != FUNCTION_INST_UNREACHABLE_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
-
+
Stream.ExitBlock();
}
@@ -1356,26 +1425,26 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
/// WriteModule - Emit the specified module to the bitstream.
static void WriteModule(const Module *M, BitstreamWriter &Stream) {
Stream.EnterSubblock(bitc::MODULE_BLOCK_ID, 3);
-
+
// Emit the version number if it is non-zero.
if (CurVersion) {
SmallVector<unsigned, 1> Vals;
Vals.push_back(CurVersion);
Stream.EmitRecord(bitc::MODULE_CODE_VERSION, Vals);
}
-
+
// Analyze the module, enumerating globals, functions, etc.
ValueEnumerator VE(M);
// Emit blockinfo, which defines the standard abbreviations etc.
WriteBlockInfo(VE, Stream);
-
+
// Emit information about parameter attributes.
WriteAttributeTable(VE, Stream);
-
+
// Emit information describing all of the types in the module.
WriteTypeTable(VE, Stream);
-
+
// Emit top-level description of module, including target triple, inline asm,
// descriptors for global variables, and function prototype info.
WriteModuleInfo(M, VE, Stream);
@@ -1390,13 +1459,16 @@ static void WriteModule(const Module *M, BitstreamWriter &Stream) {
for (Module::const_iterator I = M->begin(), E = M->end(); I != E; ++I)
if (!I->isDeclaration())
WriteFunction(*I, VE, Stream);
-
+
+ // Emit metadata.
+ WriteModuleMetadataStore(M, VE, Stream);
+
// Emit the type symbol table information.
WriteTypeSymbolTable(M->getTypeSymbolTable(), VE, Stream);
-
+
// Emit names for globals/functions etc.
WriteValueSymbolTable(M->getValueSymbolTable(), VE, Stream);
-
+
Stream.ExitBlock();
}
@@ -1404,7 +1476,7 @@ static void WriteModule(const Module *M, BitstreamWriter &Stream) {
/// header and trailer to make it compatible with the system archiver. To do
/// this we emit the following header, and then emit a trailer that pads the
/// file out to be a multiple of 16 bytes.
-///
+///
/// struct bc_header {
/// uint32_t Magic; // 0x0B17C0DE
/// uint32_t Version; // Version, currently always 0.
@@ -1421,7 +1493,7 @@ enum {
static void EmitDarwinBCHeader(BitstreamWriter &Stream,
const std::string &TT) {
unsigned CPUType = ~0U;
-
+
// Match x86_64-*, i[3-9]86-*, powerpc-*, powerpc64-*. The CPUType is a
// magic number from /usr/include/mach/machine.h. It is ok to reproduce the
// specific constants here because they are implicitly part of the Darwin ABI.
@@ -1430,7 +1502,7 @@ static void EmitDarwinBCHeader(BitstreamWriter &Stream,
DARWIN_CPU_TYPE_X86 = 7,
DARWIN_CPU_TYPE_POWERPC = 18
};
-
+
if (TT.find("x86_64-") == 0)
CPUType = DARWIN_CPU_TYPE_X86 | DARWIN_CPU_ARCH_ABI64;
else if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' &&
@@ -1440,10 +1512,10 @@ static void EmitDarwinBCHeader(BitstreamWriter &Stream,
CPUType = DARWIN_CPU_TYPE_POWERPC;
else if (TT.find("powerpc64-") == 0)
CPUType = DARWIN_CPU_TYPE_POWERPC | DARWIN_CPU_ARCH_ABI64;
-
+
// Traditional Bitcode starts after header.
unsigned BCOffset = DarwinBCHeaderSize;
-
+
Stream.Emit(0x0B17C0DE, 32);
Stream.Emit(0 , 32); // Version.
Stream.Emit(BCOffset , 32);
@@ -1456,7 +1528,7 @@ static void EmitDarwinBCHeader(BitstreamWriter &Stream,
static void EmitDarwinBCTrailer(BitstreamWriter &Stream, unsigned BufferSize) {
// Update the size field in the header.
Stream.BackpatchWord(DarwinBCSizeFieldOffset, BufferSize-DarwinBCHeaderSize);
-
+
// If the file is not a multiple of 16 bytes, insert dummy padding.
while (BufferSize & 15) {
Stream.Emit(0, 8);
@@ -1470,18 +1542,18 @@ static void EmitDarwinBCTrailer(BitstreamWriter &Stream, unsigned BufferSize) {
void llvm::WriteBitcodeToFile(const Module *M, raw_ostream &Out) {
std::vector<unsigned char> Buffer;
BitstreamWriter Stream(Buffer);
-
+
Buffer.reserve(256*1024);
WriteBitcodeToStream( M, Stream );
-
+
// If writing to stdout, set binary mode.
if (&llvm::outs() == &Out)
sys::Program::ChangeStdoutToBinary();
// Write the generated bitstream to "Out".
Out.write((char*)&Buffer.front(), Buffer.size());
-
+
// Make sure it hits disk now.
Out.flush();
}
@@ -1493,7 +1565,7 @@ void llvm::WriteBitcodeToStream(const Module *M, BitstreamWriter &Stream) {
bool isDarwin = M->getTargetTriple().find("-darwin") != std::string::npos;
if (isDarwin)
EmitDarwinBCHeader(Stream, M->getTargetTriple());
-
+
// Emit the file header.
Stream.Emit((unsigned)'B', 8);
Stream.Emit((unsigned)'C', 8);
diff --git a/libclamav/c++/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp b/libclamav/c++/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp
index 783022c..60253ad 100644
--- a/libclamav/c++/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp
+++ b/libclamav/c++/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp
@@ -40,6 +40,8 @@ static bool CompareByFrequency(const std::pair<const llvm::Type*,
/// ValueEnumerator - Enumerate module-level information.
ValueEnumerator::ValueEnumerator(const Module *M) {
+ InstructionCount = 0;
+
// Enumerate the global variables.
for (Module::const_global_iterator I = M->global_begin(),
E = M->global_end(); I != E; ++I)
@@ -55,10 +57,10 @@ ValueEnumerator::ValueEnumerator(const Module *M) {
for (Module::const_alias_iterator I = M->alias_begin(), E = M->alias_end();
I != E; ++I)
EnumerateValue(I);
-
+
// Remember what is the cutoff between globalvalue's and other constants.
unsigned FirstConstant = Values.size();
-
+
// Enumerate the global variable initializers.
for (Module::const_global_iterator I = M->global_begin(),
E = M->global_end(); I != E; ++I)
@@ -69,24 +71,25 @@ ValueEnumerator::ValueEnumerator(const Module *M) {
for (Module::const_alias_iterator I = M->alias_begin(), E = M->alias_end();
I != E; ++I)
EnumerateValue(I->getAliasee());
-
+
// Enumerate types used by the type symbol table.
EnumerateTypeSymbolTable(M->getTypeSymbolTable());
// Insert constants that are named at module level into the slot pool so that
// the module symbol table can refer to them...
EnumerateValueSymbolTable(M->getValueSymbolTable());
-
+
// Enumerate types used by function bodies and argument lists.
for (Module::const_iterator F = M->begin(), E = M->end(); F != E; ++F) {
-
+
for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
I != E; ++I)
EnumerateType(I->getType());
-
+
+ MetadataContext &TheMetadata = F->getContext().getMetadata();
for (Function::const_iterator BB = F->begin(), E = F->end(); BB != E; ++BB)
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I!=E;++I){
- for (User::const_op_iterator OI = I->op_begin(), E = I->op_end();
+ for (User::const_op_iterator OI = I->op_begin(), E = I->op_end();
OI != E; ++OI)
EnumerateOperandType(*OI);
EnumerateType(I->getType());
@@ -94,16 +97,24 @@ ValueEnumerator::ValueEnumerator(const Module *M) {
EnumerateAttributes(CI->getAttributes());
else if (const InvokeInst *II = dyn_cast<InvokeInst>(I))
EnumerateAttributes(II->getAttributes());
+
+ // Enumerate metadata attached with this instruction.
+ const MetadataContext::MDMapTy *MDs = TheMetadata.getMDs(I);
+ if (MDs)
+ for (MetadataContext::MDMapTy::const_iterator MI = MDs->begin(),
+ ME = MDs->end(); MI != ME; ++MI)
+ if (MDNode *MDN = dyn_cast_or_null<MDNode>(MI->second))
+ EnumerateMetadata(MDN);
}
}
-
+
// Optimize constant ordering.
OptimizeConstants(FirstConstant, Values.size());
-
+
// Sort the type table by frequency so that most commonly used types are early
// in the table (have low bit-width).
std::stable_sort(Types.begin(), Types.end(), CompareByFrequency);
-
+
// Partition the Type ID's so that the single-value types occur before the
// aggregate types. This allows the aggregate types to be dropped from the
// type table after parsing the global variable initializers.
@@ -114,18 +125,28 @@ ValueEnumerator::ValueEnumerator(const Module *M) {
TypeMap[Types[i].first] = i+1;
}
+unsigned ValueEnumerator::getInstructionID(const Instruction *Inst) const {
+ InstructionMapType::const_iterator I = InstructionMap.find(Inst);
+ assert (I != InstructionMap.end() && "Instruction is not mapped!");
+ return I->second;
+}
+
+void ValueEnumerator::setInstructionID(const Instruction *I) {
+ InstructionMap[I] = InstructionCount++;
+}
+
unsigned ValueEnumerator::getValueID(const Value *V) const {
if (isa<MetadataBase>(V)) {
ValueMapType::const_iterator I = MDValueMap.find(V);
assert(I != MDValueMap.end() && "Value not in slotcalculator!");
return I->second-1;
}
-
+
ValueMapType::const_iterator I = ValueMap.find(V);
assert(I != ValueMap.end() && "Value not in slotcalculator!");
return I->second-1;
}
-
+
// Optimize constant ordering.
namespace {
struct CstSortPredicate {
@@ -135,7 +156,7 @@ namespace {
const std::pair<const Value*, unsigned> &RHS) {
// Sort by plane.
if (LHS.first->getType() != RHS.first->getType())
- return VE.getTypeID(LHS.first->getType()) <
+ return VE.getTypeID(LHS.first->getType()) <
VE.getTypeID(RHS.first->getType());
// Then by frequency.
return LHS.second > RHS.second;
@@ -146,15 +167,15 @@ namespace {
/// OptimizeConstants - Reorder constant pool for denser encoding.
void ValueEnumerator::OptimizeConstants(unsigned CstStart, unsigned CstEnd) {
if (CstStart == CstEnd || CstStart+1 == CstEnd) return;
-
+
CstSortPredicate P(*this);
std::stable_sort(Values.begin()+CstStart, Values.begin()+CstEnd, P);
-
+
// Ensure that integer constants are at the start of the constant pool. This
// is important so that GEP structure indices come before gep constant exprs.
std::partition(Values.begin()+CstStart, Values.begin()+CstEnd,
isIntegerValue);
-
+
// Rebuild the modified portion of ValueMap.
for (; CstStart != CstEnd; ++CstStart)
ValueMap[Values[CstStart].first] = CstStart+1;
@@ -164,7 +185,7 @@ void ValueEnumerator::OptimizeConstants(unsigned CstStart, unsigned CstEnd) {
/// EnumerateTypeSymbolTable - Insert all of the types in the specified symbol
/// table.
void ValueEnumerator::EnumerateTypeSymbolTable(const TypeSymbolTable &TST) {
- for (TypeSymbolTable::const_iterator TI = TST.begin(), TE = TST.end();
+ for (TypeSymbolTable::const_iterator TI = TST.begin(), TE = TST.end();
TI != TE; ++TI)
EnumerateType(TI->second);
}
@@ -172,7 +193,7 @@ void ValueEnumerator::EnumerateTypeSymbolTable(const TypeSymbolTable &TST) {
/// EnumerateValueSymbolTable - Insert all of the values in the specified symbol
/// table into the values table.
void ValueEnumerator::EnumerateValueSymbolTable(const ValueSymbolTable &VST) {
- for (ValueSymbolTable::const_iterator VI = VST.begin(), VE = VST.end();
+ for (ValueSymbolTable::const_iterator VI = VST.begin(), VE = VST.end();
VI != VE; ++VI)
EnumerateValue(VI->getValue());
}
@@ -233,7 +254,7 @@ void ValueEnumerator::EnumerateValue(const Value *V) {
// Enumerate the type of this value.
EnumerateType(V->getType());
-
+
if (const Constant *C = dyn_cast<Constant>(V)) {
if (isa<GlobalValue>(C)) {
// Initializers for globals are handled explicitly elsewhere.
@@ -245,7 +266,7 @@ void ValueEnumerator::EnumerateValue(const Value *V) {
// If a constant has operands, enumerate them. This makes sure that if a
// constant has uses (for example an array of const ints), that they are
// inserted also.
-
+
// We prefer to enumerate them with values before we enumerate the user
// itself. This makes it more likely that we can avoid forward references
// in the reader. We know that there can be no cycles in the constants
@@ -253,7 +274,7 @@ void ValueEnumerator::EnumerateValue(const Value *V) {
for (User::const_op_iterator I = C->op_begin(), E = C->op_end();
I != E; ++I)
EnumerateValue(*I);
-
+
// Finally, add the value. Doing this could make the ValueID reference be
// dangling, don't reuse it.
Values.push_back(std::make_pair(V, 1U));
@@ -270,17 +291,17 @@ void ValueEnumerator::EnumerateValue(const Value *V) {
void ValueEnumerator::EnumerateType(const Type *Ty) {
unsigned &TypeID = TypeMap[Ty];
-
+
if (TypeID) {
// If we've already seen this type, just increase its occurrence count.
Types[TypeID-1].second++;
return;
}
-
+
// First time we saw this type, add it.
Types.push_back(std::make_pair(Ty, 1U));
TypeID = Types.size();
-
+
// Enumerate subtypes.
for (Type::subtype_iterator I = Ty->subtype_begin(), E = Ty->subtype_end();
I != E; ++I)
@@ -326,18 +347,18 @@ void ValueEnumerator::EnumerateAttributes(const AttrListPtr &PAL) {
void ValueEnumerator::incorporateFunction(const Function &F) {
NumModuleValues = Values.size();
-
+
// Adding function arguments to the value table.
for(Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
I != E; ++I)
EnumerateValue(I);
FirstFuncConstantID = Values.size();
-
+
// Add all function-level constants to the value table.
for (Function::const_iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
- for (User::const_op_iterator OI = I->op_begin(), E = I->op_end();
+ for (User::const_op_iterator OI = I->op_begin(), E = I->op_end();
OI != E; ++OI) {
if ((isa<Constant>(*OI) && !isa<GlobalValue>(*OI)) ||
isa<InlineAsm>(*OI))
@@ -346,16 +367,16 @@ void ValueEnumerator::incorporateFunction(const Function &F) {
BasicBlocks.push_back(BB);
ValueMap[BB] = BasicBlocks.size();
}
-
+
// Optimize the constant layout.
OptimizeConstants(FirstFuncConstantID, Values.size());
-
+
// Add the function's parameter attributes so they are available for use in
// the function's instruction.
EnumerateAttributes(F.getAttributes());
FirstInstID = Values.size();
-
+
// Add all of the instructions.
for (Function::const_iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I!=E; ++I) {
@@ -371,8 +392,7 @@ void ValueEnumerator::purgeFunction() {
ValueMap.erase(Values[i].first);
for (unsigned i = 0, e = BasicBlocks.size(); i != e; ++i)
ValueMap.erase(BasicBlocks[i]);
-
+
Values.resize(NumModuleValues);
BasicBlocks.clear();
}
-
diff --git a/libclamav/c++/llvm/lib/Bitcode/Writer/ValueEnumerator.h b/libclamav/c++/llvm/lib/Bitcode/Writer/ValueEnumerator.h
index b5106f0..da63dde 100644
--- a/libclamav/c++/llvm/lib/Bitcode/Writer/ValueEnumerator.h
+++ b/libclamav/c++/llvm/lib/Bitcode/Writer/ValueEnumerator.h
@@ -22,6 +22,7 @@ namespace llvm {
class Type;
class Value;
+class Instruction;
class BasicBlock;
class Function;
class Module;
@@ -47,11 +48,15 @@ private:
ValueList Values;
ValueList MDValues;
ValueMapType MDValueMap;
-
+
typedef DenseMap<void*, unsigned> AttributeMapType;
AttributeMapType AttributeMap;
std::vector<AttrListPtr> Attributes;
+ typedef DenseMap<const Instruction*, unsigned> InstructionMapType;
+ InstructionMapType InstructionMap;
+ unsigned InstructionCount;
+
/// BasicBlocks - This contains all the basic blocks for the currently
/// incorporated function. Their reverse mapping is stored in ValueMap.
std::vector<const BasicBlock*> BasicBlocks;
@@ -74,7 +79,10 @@ public:
assert(I != TypeMap.end() && "Type not in ValueEnumerator!");
return I->second-1;
}
-
+
+ unsigned getInstructionID(const Instruction *I) const;
+ void setInstructionID(const Instruction *I);
+
unsigned getAttributeID(const AttrListPtr &PAL) const {
if (PAL.isEmpty()) return 0; // Null maps to zero.
AttributeMapType::const_iterator I = AttributeMap.find(PAL.getRawPointer());
diff --git a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index a92d923..7e83473 100644
--- a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -28,6 +28,7 @@
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSection.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormattedStream.h"
@@ -55,10 +56,11 @@ AsmPrinter::AsmPrinter(formatted_raw_ostream &o, TargetMachine &tm,
TM(tm), MAI(T), TRI(tm.getRegisterInfo()),
OutContext(*new MCContext()),
- OutStreamer(*createAsmStreamer(OutContext, O, *T, this)),
+ // FIXME: Pass instprinter to streamer.
+ OutStreamer(*createAsmStreamer(OutContext, O, *T, 0)),
LastMI(0), LastFn(0), Counter(~0U),
- PrevDLT(0, ~0U, ~0U) {
+ PrevDLT(0, 0, ~0U, ~0U) {
DW = 0; MMI = 0;
switch (AsmVerbose) {
case cl::BOU_UNSET: VerboseAsm = VDef; break;
@@ -104,17 +106,22 @@ bool AsmPrinter::doInitialization(Module &M) {
if (MAI->doesAllowQuotesInName())
Mang->setUseQuotes(true);
+
+ if (MAI->doesAllowNameToStartWithDigit())
+ Mang->setSymbolsCanStartWithDigit(true);
- GCModuleInfo *MI = getAnalysisIfAvailable<GCModuleInfo>();
- assert(MI && "AsmPrinter didn't require GCModuleInfo?");
+ // Allow the target to emit any magic that it wants at the start of the file.
+ EmitStartOfAsmFile(M);
if (MAI->hasSingleParameterDotFile()) {
/* Very minimal debug info. It is ignored if we emit actual
- debug info. If we don't, this at helps the user find where
+ debug info. If we don't, this at least helps the user find where
a function came from. */
O << "\t.file\t\"" << M.getModuleIdentifier() << "\"\n";
}
+ GCModuleInfo *MI = getAnalysisIfAvailable<GCModuleInfo>();
+ assert(MI && "AsmPrinter didn't require GCModuleInfo?");
for (GCModuleInfo::iterator I = MI->begin(), E = MI->end(); I != E; ++I)
if (GCMetadataPrinter *MP = GetOrCreateGCPrinter(*I))
MP->beginAssembly(O, *this, *MAI);
@@ -125,15 +132,12 @@ bool AsmPrinter::doInitialization(Module &M) {
<< '\n' << MAI->getCommentString()
<< " End of file scope inline assembly\n";
- if (MAI->doesSupportDebugInformation() ||
- MAI->doesSupportExceptionHandling()) {
- MMI = getAnalysisIfAvailable<MachineModuleInfo>();
- if (MMI)
- MMI->AnalyzeModule(M);
- DW = getAnalysisIfAvailable<DwarfWriter>();
- if (DW)
- DW->BeginModule(&M, MMI, O, this, MAI);
- }
+ MMI = getAnalysisIfAvailable<MachineModuleInfo>();
+ if (MMI)
+ MMI->AnalyzeModule(M);
+ DW = getAnalysisIfAvailable<DwarfWriter>();
+ if (DW)
+ DW->BeginModule(&M, MMI, O, this, MAI);
return false;
}
@@ -203,6 +207,11 @@ bool AsmPrinter::doFinalization(Module &M) {
if (MAI->getNonexecutableStackDirective())
O << MAI->getNonexecutableStackDirective() << '\n';
+
+ // Allow the target to emit any magic that it wants at the end of the file,
+ // after everything else has gone out.
+ EmitEndOfAsmFile(M);
+
delete Mang; Mang = 0;
DW = 0; MMI = 0;
@@ -210,21 +219,13 @@ bool AsmPrinter::doFinalization(Module &M) {
return false;
}
-std::string
-AsmPrinter::getCurrentFunctionEHName(const MachineFunction *MF) const {
- assert(MF && "No machine function?");
- return Mang->getMangledName(MF->getFunction(), ".eh",
- MAI->is_EHSymbolPrivate());
-}
-
void AsmPrinter::SetupMachineFunction(MachineFunction &MF) {
// What's my mangled name?
CurrentFnName = Mang->getMangledName(MF.getFunction());
IncrementFunctionNumber();
- if (VerboseAsm) {
+ if (VerboseAsm)
LI = &getAnalysis<MachineLoopInfo>();
- }
}
namespace {
@@ -374,13 +375,13 @@ void AsmPrinter::EmitJumpTableInfo(MachineJumpTableInfo *MJTI,
if (EmittedSets.insert(JTBBs[ii]))
printPICJumpTableSetLabel(i, JTBBs[ii]);
- // On some targets (e.g. darwin) we want to emit two consequtive labels
+ // On some targets (e.g. Darwin) we want to emit two consequtive labels
// before each jump table. The first label is never referenced, but tells
// the assembler and linker the extents of the jump table object. The
// second label is actually referenced by the code.
- if (JTInDiffSection) {
- if (const char *JTLabelPrefix = MAI->getJumpTableSpecialLabelPrefix())
- O << JTLabelPrefix << "JTI" << getFunctionNumber() << '_' << i << ":\n";
+ if (JTInDiffSection && MAI->getLinkerPrivateGlobalPrefix()[0]) {
+ O << MAI->getLinkerPrivateGlobalPrefix()
+ << "JTI" << getFunctionNumber() << '_' << i << ":\n";
}
O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
@@ -415,12 +416,12 @@ void AsmPrinter::printPICJumpTableEntry(const MachineJumpTableInfo *MJTI,
// If we're emitting non-PIC code, then emit the entries as direct
// references to the target basic blocks.
if (!isPIC) {
- printBasicBlockLabel(MBB, false, false, false);
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
} else if (MAI->getSetDirective()) {
O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
<< '_' << uid << "_set_" << MBB->getNumber();
} else {
- printBasicBlockLabel(MBB, false, false, false);
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
// If the arch uses custom Jump Table directives, don't calc relative to
// JT
if (!HadJTEntryDirective)
@@ -507,32 +508,6 @@ void AsmPrinter::EmitXXStructorList(Constant *List) {
}
}
-/// getGlobalLinkName - Returns the asm/link name of of the specified
-/// global variable. Should be overridden by each target asm printer to
-/// generate the appropriate value.
-const std::string &AsmPrinter::getGlobalLinkName(const GlobalVariable *GV,
- std::string &LinkName) const {
- if (isa<Function>(GV)) {
- LinkName += MAI->getFunctionAddrPrefix();
- LinkName += Mang->getMangledName(GV);
- LinkName += MAI->getFunctionAddrSuffix();
- } else {
- LinkName += MAI->getGlobalVarAddrPrefix();
- LinkName += Mang->getMangledName(GV);
- LinkName += MAI->getGlobalVarAddrSuffix();
- }
-
- return LinkName;
-}
-
-/// EmitExternalGlobal - Emit the external reference to a global variable.
-/// Should be overridden if an indirect reference should be used.
-void AsmPrinter::EmitExternalGlobal(const GlobalVariable *GV) {
- std::string GLN;
- O << getGlobalLinkName(GV, GLN);
-}
-
-
//===----------------------------------------------------------------------===//
/// LEB 128 number encoding.
@@ -612,6 +587,14 @@ static const char *DecodeDWARFEncoding(unsigned Encoding) {
return "omit";
case dwarf::DW_EH_PE_pcrel:
return "pcrel";
+ case dwarf::DW_EH_PE_udata4:
+ return "udata4";
+ case dwarf::DW_EH_PE_udata8:
+ return "udata8";
+ case dwarf::DW_EH_PE_sdata4:
+ return "sdata4";
+ case dwarf::DW_EH_PE_sdata8:
+ return "sdata8";
case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4:
return "pcrel udata4";
case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4:
@@ -828,18 +811,8 @@ void AsmPrinter::EmitConstantValueOnly(const Constant *CV) {
O << CI->getZExtValue();
} else if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
// This is a constant address for a global variable or function. Use the
- // name of the variable or function as the address value, possibly
- // decorating it with GlobalVarAddrPrefix/Suffix or
- // FunctionAddrPrefix/Suffix (these all default to "" )
- if (isa<Function>(GV)) {
- O << MAI->getFunctionAddrPrefix()
- << Mang->getMangledName(GV)
- << MAI->getFunctionAddrSuffix();
- } else {
- O << MAI->getGlobalVarAddrPrefix()
- << Mang->getMangledName(GV)
- << MAI->getGlobalVarAddrSuffix();
- }
+ // name of the variable or function as the address value.
+ O << Mang->getMangledName(GV);
} else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) {
const TargetData *TD = TM.getTargetData();
unsigned Opcode = CE->getOpcode();
@@ -1374,17 +1347,19 @@ void AsmPrinter::PrintSpecial(const MachineInstr *MI, const char *Code) const {
/// processDebugLoc - Processes the debug information of each machine
/// instruction's DebugLoc.
-void AsmPrinter::processDebugLoc(DebugLoc DL) {
+void AsmPrinter::processDebugLoc(const MachineInstr *MI) {
if (!MAI || !DW)
return;
-
+ DebugLoc DL = MI->getDebugLoc();
if (MAI->doesSupportDebugInformation() && DW->ShouldEmitDwarfDebug()) {
if (!DL.isUnknown()) {
DebugLocTuple CurDLT = MF->getDebugLocTuple(DL);
- if (CurDLT.CompileUnit != 0 && PrevDLT != CurDLT)
- printLabel(DW->RecordSourceLine(CurDLT.Line, CurDLT.Col,
- DICompileUnit(CurDLT.CompileUnit)));
+ if (CurDLT.CompileUnit != 0 && PrevDLT != CurDLT) {
+ printLabel(DW->RecordSourceLine(CurDLT.Line, CurDLT.Col,
+ CurDLT.CompileUnit));
+ O << '\n';
+ }
PrevDLT = CurDLT;
}
@@ -1560,8 +1535,8 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
++OpNo; // Skip over the ID number.
if (Modifier[0]=='l') // labels are target independent
- printBasicBlockLabel(MI->getOperand(OpNo).getMBB(),
- false, false, false);
+ GetMBBSymbol(MI->getOperand(OpNo).getMBB()
+ ->getNumber())->print(O, MAI);
else {
AsmPrinter *AP = const_cast<AsmPrinter*>(this);
if ((OpFlags & 7) == 4) {
@@ -1586,17 +1561,16 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
}
}
}
- O << "\n\t" << MAI->getCommentString() << MAI->getInlineAsmEnd() << '\n';
+ O << "\n\t" << MAI->getCommentString() << MAI->getInlineAsmEnd();
}
/// printImplicitDef - This method prints the specified machine instruction
/// that is an implicit def.
void AsmPrinter::printImplicitDef(const MachineInstr *MI) const {
- if (VerboseAsm) {
- O.PadToColumn(MAI->getCommentColumn());
- O << MAI->getCommentString() << " implicit-def: "
- << TRI->getAsmName(MI->getOperand(0).getReg()) << '\n';
- }
+ if (!VerboseAsm) return;
+ O.PadToColumn(MAI->getCommentColumn());
+ O << MAI->getCommentString() << " implicit-def: "
+ << TRI->getName(MI->getOperand(0).getReg());
}
/// printLabel - This method prints a local label used by debug and
@@ -1606,7 +1580,7 @@ void AsmPrinter::printLabel(const MachineInstr *MI) const {
}
void AsmPrinter::printLabel(unsigned Id) const {
- O << MAI->getPrivateGlobalPrefix() << "label" << Id << ":\n";
+ O << MAI->getPrivateGlobalPrefix() << "label" << Id << ':';
}
/// PrintAsmOperand - Print the specified operand of MI, an INLINEASM
@@ -1625,23 +1599,26 @@ bool AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
return true;
}
-/// printBasicBlockLabel - This method prints the label for the specified
-/// MachineBasicBlock
-void AsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB,
- bool printAlign,
- bool printColon,
- bool printComment) const {
- if (printAlign) {
- unsigned Align = MBB->getAlignment();
- if (Align)
- EmitAlignment(Log2_32(Align));
- }
+MCSymbol *AsmPrinter::GetMBBSymbol(unsigned MBBID) const {
+ SmallString<60> Name;
+ raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "BB"
+ << getFunctionNumber() << '_' << MBBID;
+
+ return OutContext.GetOrCreateSymbol(Name.str());
+}
+
+
+/// EmitBasicBlockStart - This method prints the label for the specified
+/// MachineBasicBlock, an alignment (if present) and a comment describing
+/// it if appropriate.
+void AsmPrinter::EmitBasicBlockStart(const MachineBasicBlock *MBB) const {
+ if (unsigned Align = MBB->getAlignment())
+ EmitAlignment(Log2_32(Align));
- O << MAI->getPrivateGlobalPrefix() << "BB" << getFunctionNumber() << '_'
- << MBB->getNumber();
- if (printColon)
- O << ':';
- if (printComment) {
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
+ O << ':';
+
+ if (VerboseAsm) {
if (const BasicBlock *BB = MBB->getBasicBlock())
if (BB->hasName()) {
O.PadToColumn(MAI->getCommentColumn());
@@ -1649,8 +1626,7 @@ void AsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB,
WriteAsOperand(O, BB, /*PrintType=*/false);
}
- if (printColon)
- EmitComments(*MBB);
+ EmitComments(*MBB);
}
}
@@ -1663,7 +1639,7 @@ void AsmPrinter::printPICJumpTableSetLabel(unsigned uid,
O << MAI->getSetDirective() << ' ' << MAI->getPrivateGlobalPrefix()
<< getFunctionNumber() << '_' << uid << "_set_" << MBB->getNumber() << ',';
- printBasicBlockLabel(MBB, false, false, false);
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
O << '-' << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< '_' << uid << '\n';
}
@@ -1676,7 +1652,7 @@ void AsmPrinter::printPICJumpTableSetLabel(unsigned uid, unsigned uid2,
O << MAI->getSetDirective() << ' ' << MAI->getPrivateGlobalPrefix()
<< getFunctionNumber() << '_' << uid << '_' << uid2
<< "_set_" << MBB->getNumber() << ',';
- printBasicBlockLabel(MBB, false, false, false);
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
O << '-' << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< '_' << uid << '_' << uid2 << '\n';
}
@@ -1742,10 +1718,6 @@ void AsmPrinter::printOffset(int64_t Offset) const {
O << Offset;
}
-void AsmPrinter::printMCInst(const MCInst *MI) {
- llvm_unreachable("MCInst printing unavailable on this target!");
-}
-
GCMetadataPrinter *AsmPrinter::GetOrCreateGCPrinter(GCStrategy *S) {
if (!S->usesMetadata())
return 0;
@@ -1772,9 +1744,7 @@ GCMetadataPrinter *AsmPrinter::GetOrCreateGCPrinter(GCStrategy *S) {
/// EmitComments - Pretty-print comments for instructions
void AsmPrinter::EmitComments(const MachineInstr &MI) const {
- if (!VerboseAsm ||
- MI.getDebugLoc().isUnknown())
- return;
+ assert(VerboseAsm && !MI.getDebugLoc().isUnknown());
DebugLocTuple DLT = MF->getDebugLocTuple(MI.getDebugLoc());
@@ -1782,30 +1752,8 @@ void AsmPrinter::EmitComments(const MachineInstr &MI) const {
O.PadToColumn(MAI->getCommentColumn());
O << MAI->getCommentString() << " SrcLine ";
if (DLT.CompileUnit) {
- std::string Str;
- DICompileUnit CU(DLT.CompileUnit);
- O << CU.getFilename(Str) << " ";
- }
- O << DLT.Line;
- if (DLT.Col != 0)
- O << ":" << DLT.Col;
-}
-
-/// EmitComments - Pretty-print comments for instructions
-void AsmPrinter::EmitComments(const MCInst &MI) const {
- if (!VerboseAsm ||
- MI.getDebugLoc().isUnknown())
- return;
-
- DebugLocTuple DLT = MF->getDebugLocTuple(MI.getDebugLoc());
-
- // Print source line info
- O.PadToColumn(MAI->getCommentColumn());
- O << MAI->getCommentString() << " SrcLine ";
- if (DLT.CompileUnit) {
- std::string Str;
DICompileUnit CU(DLT.CompileUnit);
- O << CU.getFilename(Str) << " ";
+ O << CU.getFilename() << " ";
}
O << DLT.Line;
if (DLT.Col != 0)
diff --git a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index efa7577..bbaf1ad 100644
--- a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -23,6 +23,7 @@
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/StringExtras.h"
+#include "llvm/Support/Mangler.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/Debug.h"
#include "llvm/System/Path.h"
@@ -146,15 +147,18 @@ class VISIBILITY_HIDDEN DbgScope {
// Either subprogram or block.
unsigned StartLabelID; // Label ID of the beginning of scope.
unsigned EndLabelID; // Label ID of the end of scope.
+ const MachineInstr *LastInsn; // Last instruction of this scope.
+ const MachineInstr *FirstInsn; // First instruction of this scope.
SmallVector<DbgScope *, 4> Scopes; // Scopes defined in scope.
SmallVector<DbgVariable *, 8> Variables;// Variables declared in scope.
SmallVector<DbgConcreteScope *, 8> ConcreteInsts;// Concrete insts of funcs.
-
+
// Private state for dump()
mutable unsigned IndentLevel;
public:
DbgScope(DbgScope *P, DIDescriptor D)
- : Parent(P), Desc(D), StartLabelID(0), EndLabelID(0), IndentLevel(0) {}
+ : Parent(P), Desc(D), StartLabelID(0), EndLabelID(0), LastInsn(0),
+ FirstInsn(0), IndentLevel(0) {}
virtual ~DbgScope();
// Accessors.
@@ -167,7 +171,10 @@ public:
SmallVector<DbgConcreteScope*,8> &getConcreteInsts() { return ConcreteInsts; }
void setStartLabelID(unsigned S) { StartLabelID = S; }
void setEndLabelID(unsigned E) { EndLabelID = E; }
-
+ void setLastInsn(const MachineInstr *MI) { LastInsn = MI; }
+ const MachineInstr *getLastInsn() { return LastInsn; }
+ void setFirstInsn(const MachineInstr *MI) { FirstInsn = MI; }
+ const MachineInstr *getFirstInsn() { return FirstInsn; }
/// AddScope - Add a scope to the scope.
///
void AddScope(DbgScope *S) { Scopes.push_back(S); }
@@ -180,6 +187,21 @@ public:
///
void AddConcreteInst(DbgConcreteScope *C) { ConcreteInsts.push_back(C); }
+ void FixInstructionMarkers() {
+ assert (getFirstInsn() && "First instruction is missing!");
+ if (getLastInsn())
+ return;
+
+ // If a scope does not have an instruction to mark an end then use
+ // the end of last child scope.
+ SmallVector<DbgScope *, 4> &Scopes = getScopes();
+ assert (!Scopes.empty() && "Inner most scope does not have last insn!");
+ DbgScope *L = Scopes.back();
+ if (!L->getLastInsn())
+ L->FixInstructionMarkers();
+ setLastInsn(L->getLastInsn());
+ }
+
#ifndef NDEBUG
void dump() const;
#endif
@@ -231,7 +253,7 @@ DbgScope::~DbgScope() {
DwarfDebug::DwarfDebug(raw_ostream &OS, AsmPrinter *A, const MCAsmInfo *T)
: Dwarf(OS, A, T, "dbg"), ModuleCU(0),
AbbreviationsSet(InitAbbreviationsSetSize), Abbreviations(),
- ValuesSet(InitValuesSetSize), Values(), StringPool(),
+ ValuesSet(InitValuesSetSize), Values(), StringPool(),
SectionSourceLines(), didInitial(false), shouldEmit(false),
FunctionDbgScope(0), DebugTimer(0) {
if (TimePassesIsEnabled)
@@ -487,6 +509,27 @@ void DwarfDebug::AddSourceLine(DIE *Die, const DIGlobal *G) {
AddUInt(Die, dwarf::DW_AT_decl_file, 0, FileID);
AddUInt(Die, dwarf::DW_AT_decl_line, 0, Line);
}
+
+/// AddSourceLine - Add location information to specified debug information
+/// entry.
+void DwarfDebug::AddSourceLine(DIE *Die, const DISubprogram *SP) {
+ // If there is no compile unit specified, don't add a line #.
+ if (SP->getCompileUnit().isNull())
+ return;
+ // If the line number is 0, don't add it.
+ if (SP->getLineNumber() == 0)
+ return;
+
+
+ unsigned Line = SP->getLineNumber();
+ unsigned FileID = FindCompileUnit(SP->getCompileUnit()).getID();
+ assert(FileID && "Invalid file id");
+ AddUInt(Die, dwarf::DW_AT_decl_file, 0, FileID);
+ AddUInt(Die, dwarf::DW_AT_decl_line, 0, Line);
+}
+
+/// AddSourceLine - Add location information to specified debug information
+/// entry.
void DwarfDebug::AddSourceLine(DIE *Die, const DIType *Ty) {
// If there is no compile unit specified, don't add a line #.
DICompileUnit CU = Ty->getCompileUnit();
@@ -500,6 +543,270 @@ void DwarfDebug::AddSourceLine(DIE *Die, const DIType *Ty) {
AddUInt(Die, dwarf::DW_AT_decl_line, 0, Line);
}
+/* Byref variables, in Blocks, are declared by the programmer as
+ "SomeType VarName;", but the compiler creates a
+ __Block_byref_x_VarName struct, and gives the variable VarName
+ either the struct, or a pointer to the struct, as its type. This
+ is necessary for various behind-the-scenes things the compiler
+ needs to do with by-reference variables in blocks.
+
+ However, as far as the original *programmer* is concerned, the
+ variable should still have type 'SomeType', as originally declared.
+
+ The following function dives into the __Block_byref_x_VarName
+ struct to find the original type of the variable. This will be
+ passed back to the code generating the type for the Debug
+ Information Entry for the variable 'VarName'. 'VarName' will then
+ have the original type 'SomeType' in its debug information.
+
+ The original type 'SomeType' will be the type of the field named
+ 'VarName' inside the __Block_byref_x_VarName struct.
+
+ NOTE: In order for this to not completely fail on the debugger
+ side, the Debug Information Entry for the variable VarName needs to
+ have a DW_AT_location that tells the debugger how to unwind through
+ the pointers and __Block_byref_x_VarName struct to find the actual
+ value of the variable. The function AddBlockByrefType does this. */
+
+/// Find the type the programmer originally declared the variable to be
+/// and return that type.
+///
+DIType DwarfDebug::GetBlockByrefType(DIType Ty, std::string Name) {
+
+ DIType subType = Ty;
+ unsigned tag = Ty.getTag();
+
+ if (tag == dwarf::DW_TAG_pointer_type) {
+ DIDerivedType DTy = DIDerivedType(Ty.getNode());
+ subType = DTy.getTypeDerivedFrom();
+ }
+
+ DICompositeType blockStruct = DICompositeType(subType.getNode());
+
+ DIArray Elements = blockStruct.getTypeArray();
+
+ if (Elements.isNull())
+ return Ty;
+
+ for (unsigned i = 0, N = Elements.getNumElements(); i < N; ++i) {
+ DIDescriptor Element = Elements.getElement(i);
+ DIDerivedType DT = DIDerivedType(Element.getNode());
+ if (strcmp(Name.c_str(), DT.getName()) == 0)
+ return (DT.getTypeDerivedFrom());
+ }
+
+ return Ty;
+}
+
+/// AddComplexAddress - Start with the address based on the location provided,
+/// and generate the DWARF information necessary to find the actual variable
+/// given the extra address information encoded in the DIVariable, starting from
+/// the starting location. Add the DWARF information to the die.
+///
+void DwarfDebug::AddComplexAddress(DbgVariable *&DV, DIE *Die,
+ unsigned Attribute,
+ const MachineLocation &Location) {
+ const DIVariable &VD = DV->getVariable();
+ DIType Ty = VD.getType();
+
+ // Decode the original location, and use that as the start of the byref
+ // variable's location.
+ unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false);
+ DIEBlock *Block = new DIEBlock();
+
+ if (Location.isReg()) {
+ if (Reg < 32) {
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + Reg);
+ } else {
+ Reg = Reg - dwarf::DW_OP_reg0;
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg);
+ AddUInt(Block, 0, dwarf::DW_FORM_udata, Reg);
+ }
+ } else {
+ if (Reg < 32)
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg);
+ else {
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_bregx);
+ AddUInt(Block, 0, dwarf::DW_FORM_udata, Reg);
+ }
+
+ AddUInt(Block, 0, dwarf::DW_FORM_sdata, Location.getOffset());
+ }
+
+ for (unsigned i = 0, N = VD.getNumAddrElements(); i < N; ++i) {
+ uint64_t Element = VD.getAddrElement(i);
+
+ if (Element == DIFactory::OpPlus) {
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst);
+ AddUInt(Block, 0, dwarf::DW_FORM_udata, VD.getAddrElement(++i));
+ } else if (Element == DIFactory::OpDeref) {
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_deref);
+ } else llvm_unreachable("unknown DIFactory Opcode");
+ }
+
+ // Now attach the location information to the DIE.
+ AddBlock(Die, Attribute, 0, Block);
+}
+
+/* Byref variables, in Blocks, are declared by the programmer as "SomeType
+ VarName;", but the compiler creates a __Block_byref_x_VarName struct, and
+ gives the variable VarName either the struct, or a pointer to the struct, as
+ its type. This is necessary for various behind-the-scenes things the
+ compiler needs to do with by-reference variables in Blocks.
+
+ However, as far as the original *programmer* is concerned, the variable
+ should still have type 'SomeType', as originally declared.
+
+ The function GetBlockByrefType dives into the __Block_byref_x_VarName
+ struct to find the original type of the variable, which is then assigned to
+ the variable's Debug Information Entry as its real type. So far, so good.
+ However now the debugger will expect the variable VarName to have the type
+ SomeType. So we need the location attribute for the variable to be an
+ expression that explains to the debugger how to navigate through the
+ pointers and struct to find the actual variable of type SomeType.
+
+ The following function does just that. We start by getting
+ the "normal" location for the variable. This will be the location
+ of either the struct __Block_byref_x_VarName or the pointer to the
+ struct __Block_byref_x_VarName.
+
+ The struct will look something like:
+
+ struct __Block_byref_x_VarName {
+ ... <various fields>
+ struct __Block_byref_x_VarName *forwarding;
+ ... <various other fields>
+ SomeType VarName;
+ ... <maybe more fields>
+ };
+
+ If we are given the struct directly (as our starting point) we
+ need to tell the debugger to:
+
+ 1). Add the offset of the forwarding field.
+
+ 2). Follow that pointer to get the the real __Block_byref_x_VarName
+ struct to use (the real one may have been copied onto the heap).
+
+ 3). Add the offset for the field VarName, to find the actual variable.
+
+ If we started with a pointer to the struct, then we need to
+ dereference that pointer first, before the other steps.
+ Translating this into DWARF ops, we will need to append the following
+ to the current location description for the variable:
+
+ DW_OP_deref -- optional, if we start with a pointer
+ DW_OP_plus_uconst <forward_fld_offset>
+ DW_OP_deref
+ DW_OP_plus_uconst <varName_fld_offset>
+
+ That is what this function does. */
+
+/// AddBlockByrefAddress - Start with the address based on the location
+/// provided, and generate the DWARF information necessary to find the
+/// actual Block variable (navigating the Block struct) based on the
+/// starting location. Add the DWARF information to the die. For
+/// more information, read large comment just above here.
+///
+void DwarfDebug::AddBlockByrefAddress(DbgVariable *&DV, DIE *Die,
+ unsigned Attribute,
+ const MachineLocation &Location) {
+ const DIVariable &VD = DV->getVariable();
+ DIType Ty = VD.getType();
+ DIType TmpTy = Ty;
+ unsigned Tag = Ty.getTag();
+ bool isPointer = false;
+
+ const char *varName = VD.getName();
+
+ if (Tag == dwarf::DW_TAG_pointer_type) {
+ DIDerivedType DTy = DIDerivedType(Ty.getNode());
+ TmpTy = DTy.getTypeDerivedFrom();
+ isPointer = true;
+ }
+
+ DICompositeType blockStruct = DICompositeType(TmpTy.getNode());
+
+ // Find the __forwarding field and the variable field in the __Block_byref
+ // struct.
+ DIArray Fields = blockStruct.getTypeArray();
+ DIDescriptor varField = DIDescriptor();
+ DIDescriptor forwardingField = DIDescriptor();
+
+
+ for (unsigned i = 0, N = Fields.getNumElements(); i < N; ++i) {
+ DIDescriptor Element = Fields.getElement(i);
+ DIDerivedType DT = DIDerivedType(Element.getNode());
+ const char *fieldName = DT.getName();
+ if (strcmp(fieldName, "__forwarding") == 0)
+ forwardingField = Element;
+ else if (strcmp(fieldName, varName) == 0)
+ varField = Element;
+ }
+
+ assert(!varField.isNull() && "Can't find byref variable in Block struct");
+ assert(!forwardingField.isNull()
+ && "Can't find forwarding field in Block struct");
+
+ // Get the offsets for the forwarding field and the variable field.
+ unsigned int forwardingFieldOffset =
+ DIDerivedType(forwardingField.getNode()).getOffsetInBits() >> 3;
+ unsigned int varFieldOffset =
+ DIDerivedType(varField.getNode()).getOffsetInBits() >> 3;
+
+ // Decode the original location, and use that as the start of the byref
+ // variable's location.
+ unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false);
+ DIEBlock *Block = new DIEBlock();
+
+ if (Location.isReg()) {
+ if (Reg < 32)
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + Reg);
+ else {
+ Reg = Reg - dwarf::DW_OP_reg0;
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg);
+ AddUInt(Block, 0, dwarf::DW_FORM_udata, Reg);
+ }
+ } else {
+ if (Reg < 32)
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + Reg);
+ else {
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_bregx);
+ AddUInt(Block, 0, dwarf::DW_FORM_udata, Reg);
+ }
+
+ AddUInt(Block, 0, dwarf::DW_FORM_sdata, Location.getOffset());
+ }
+
+ // If we started with a pointer to the __Block_byref... struct, then
+ // the first thing we need to do is dereference the pointer (DW_OP_deref).
+ if (isPointer)
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_deref);
+
+ // Next add the offset for the '__forwarding' field:
+ // DW_OP_plus_uconst ForwardingFieldOffset. Note there's no point in
+ // adding the offset if it's 0.
+ if (forwardingFieldOffset > 0) {
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst);
+ AddUInt(Block, 0, dwarf::DW_FORM_udata, forwardingFieldOffset);
+ }
+
+ // Now dereference the __forwarding field to get to the real __Block_byref
+ // struct: DW_OP_deref.
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_deref);
+
+ // Now that we've got the real __Block_byref... struct, add the offset
+ // for the variable's field to get to the location of the actual variable:
+ // DW_OP_plus_uconst varFieldOffset. Again, don't add if it's 0.
+ if (varFieldOffset > 0) {
+ AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus_uconst);
+ AddUInt(Block, 0, dwarf::DW_FORM_udata, varFieldOffset);
+ }
+
+ // Now attach the location information to the DIE.
+ AddBlock(Die, Attribute, 0, Block);
+}
+
/// AddAddress - Add an address attribute to a die based on the location
/// provided.
void DwarfDebug::AddAddress(DIE *Die, unsigned Attribute,
@@ -547,14 +854,13 @@ void DwarfDebug::AddType(CompileUnit *DW_Unit, DIE *Entity, DIType Ty) {
// Construct type.
DIE Buffer(dwarf::DW_TAG_base_type);
- if (Ty.isBasicType(Ty.getTag()))
+ if (Ty.isBasicType())
ConstructTypeDIE(DW_Unit, Buffer, DIBasicType(Ty.getNode()));
- else if (Ty.isCompositeType(Ty.getTag()))
+ else if (Ty.isCompositeType())
ConstructTypeDIE(DW_Unit, Buffer, DICompositeType(Ty.getNode()));
else {
- assert(Ty.isDerivedType(Ty.getTag()) && "Unknown kind of DIType");
+ assert(Ty.isDerivedType() && "Unknown kind of DIType");
ConstructTypeDIE(DW_Unit, Buffer, DIDerivedType(Ty.getNode()));
-
}
// Add debug information entry to entity and appropriate context.
@@ -580,14 +886,13 @@ void DwarfDebug::AddType(CompileUnit *DW_Unit, DIE *Entity, DIType Ty) {
void DwarfDebug::ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer,
DIBasicType BTy) {
// Get core information.
- std::string Name;
- BTy.getName(Name);
+ const char *Name = BTy.getName();
Buffer.setTag(dwarf::DW_TAG_base_type);
AddUInt(&Buffer, dwarf::DW_AT_encoding, dwarf::DW_FORM_data1,
BTy.getEncoding());
// Add name if not anonymous or intermediate type.
- if (!Name.empty())
+ if (Name)
AddString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
uint64_t Size = BTy.getSizeInBits() >> 3;
AddUInt(&Buffer, dwarf::DW_AT_byte_size, 0, Size);
@@ -597,8 +902,7 @@ void DwarfDebug::ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer,
void DwarfDebug::ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer,
DIDerivedType DTy) {
// Get core information.
- std::string Name;
- DTy.getName(Name);
+ const char *Name = DTy.getName();
uint64_t Size = DTy.getSizeInBits() >> 3;
unsigned Tag = DTy.getTag();
@@ -612,7 +916,7 @@ void DwarfDebug::ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer,
AddType(DW_Unit, &Buffer, FromTy);
// Add name if not anonymous or intermediate type.
- if (!Name.empty())
+ if (Name)
AddString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
// Add size if non-zero (derived types might be zero-sized.)
@@ -628,8 +932,7 @@ void DwarfDebug::ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer,
void DwarfDebug::ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer,
DICompositeType CTy) {
// Get core information.
- std::string Name;
- CTy.getName(Name);
+ const char *Name = CTy.getName();
uint64_t Size = CTy.getSizeInBits() >> 3;
unsigned Tag = CTy.getTag();
@@ -709,7 +1012,7 @@ void DwarfDebug::ConstructTypeDIE(CompileUnit *DW_Unit, DIE &Buffer,
}
// Add name if not anonymous or intermediate type.
- if (!Name.empty())
+ if (Name)
AddString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
if (Tag == dwarf::DW_TAG_enumeration_type ||
@@ -741,7 +1044,7 @@ void DwarfDebug::ConstructSubrangeDIE(DIE &Buffer, DISubrange SR, DIE *IndexTy){
if (L)
AddSInt(DW_Subrange, dwarf::DW_AT_lower_bound, 0, L);
if (H)
- AddSInt(DW_Subrange, dwarf::DW_AT_upper_bound, 0, H);
+ AddSInt(DW_Subrange, dwarf::DW_AT_upper_bound, 0, H);
Buffer.AddChild(DW_Subrange);
}
@@ -775,8 +1078,7 @@ void DwarfDebug::ConstructArrayTypeDIE(CompileUnit *DW_Unit, DIE &Buffer,
/// ConstructEnumTypeDIE - Construct enum type DIE from DIEnumerator.
DIE *DwarfDebug::ConstructEnumTypeDIE(CompileUnit *DW_Unit, DIEnumerator *ETy) {
DIE *Enumerator = new DIE(dwarf::DW_TAG_enumerator);
- std::string Name;
- ETy->getName(Name);
+ const char *Name = ETy->getName();
AddString(Enumerator, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
int64_t Value = ETy->getEnumValue();
AddSInt(Enumerator, dwarf::DW_AT_const_value, dwarf::DW_FORM_sdata, Value);
@@ -787,12 +1089,11 @@ DIE *DwarfDebug::ConstructEnumTypeDIE(CompileUnit *DW_Unit, DIEnumerator *ETy) {
DIE *DwarfDebug::CreateGlobalVariableDIE(CompileUnit *DW_Unit,
const DIGlobalVariable &GV) {
DIE *GVDie = new DIE(dwarf::DW_TAG_variable);
- std::string Name;
- GV.getDisplayName(Name);
- AddString(GVDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
- std::string LinkageName;
- GV.getLinkageName(LinkageName);
- if (!LinkageName.empty()) {
+ AddString(GVDie, dwarf::DW_AT_name, dwarf::DW_FORM_string,
+ GV.getDisplayName());
+
+ const char *LinkageName = GV.getLinkageName();
+ if (LinkageName) {
// Skip special LLVM prefix that is used to inform the asm printer to not
// emit usual symbol prefix before the symbol name. This happens for
// Objective-C symbol names and symbol whose name is replaced using GCC's
@@ -802,7 +1103,7 @@ DIE *DwarfDebug::CreateGlobalVariableDIE(CompileUnit *DW_Unit,
AddString(GVDie, dwarf::DW_AT_MIPS_linkage_name, dwarf::DW_FORM_string,
LinkageName);
}
- AddType(DW_Unit, GVDie, GV.getType());
+ AddType(DW_Unit, GVDie, GV.getType());
if (!GV.isLocalToUnit())
AddUInt(GVDie, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1);
AddSourceLine(GVDie, &GV);
@@ -812,9 +1113,7 @@ DIE *DwarfDebug::CreateGlobalVariableDIE(CompileUnit *DW_Unit,
/// CreateMemberDIE - Create new member DIE.
DIE *DwarfDebug::CreateMemberDIE(CompileUnit *DW_Unit, const DIDerivedType &DT){
DIE *MemberDie = new DIE(DT.getTag());
- std::string Name;
- DT.getName(Name);
- if (!Name.empty())
+ if (const char *Name = DT.getName())
AddString(MemberDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
AddType(DW_Unit, MemberDie, DT.getTypeDerivedFrom());
@@ -863,13 +1162,11 @@ DIE *DwarfDebug::CreateSubprogramDIE(CompileUnit *DW_Unit,
bool IsInlined) {
DIE *SPDie = new DIE(dwarf::DW_TAG_subprogram);
- std::string Name;
- SP.getName(Name);
+ const char * Name = SP.getName();
AddString(SPDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
- std::string LinkageName;
- SP.getLinkageName(LinkageName);
- if (!LinkageName.empty()) {
+ const char *LinkageName = SP.getLinkageName();
+ if (LinkageName) {
// Skip special LLVM prefix that is used to inform the asm printer to not emit
// usual symbol prefix before the symbol name. This happens for Objective-C
// symbol names and symbol whose name is replaced using GCC's __asm__ attribute.
@@ -953,15 +1250,18 @@ DIE *DwarfDebug::CreateDbgScopeVariable(DbgVariable *DV, CompileUnit *Unit) {
// Define variable debug information entry.
DIE *VariableDie = new DIE(Tag);
- std::string Name;
- VD.getName(Name);
+ const char *Name = VD.getName();
AddString(VariableDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
// Add source line info if available.
AddSourceLine(VariableDie, &VD);
// Add variable type.
- AddType(Unit, VariableDie, VD.getType());
+ // FIXME: isBlockByrefVariable should be reformulated in terms of complex addresses instead.
+ if (VD.isBlockByrefVariable())
+ AddType(Unit, VariableDie, GetBlockByrefType(VD.getType(), Name));
+ else
+ AddType(Unit, VariableDie, VD.getType());
// Add variable address.
if (!DV->isInlinedFnVar()) {
@@ -970,7 +1270,14 @@ DIE *DwarfDebug::CreateDbgScopeVariable(DbgVariable *DV, CompileUnit *Unit) {
MachineLocation Location;
Location.set(RI->getFrameRegister(*MF),
RI->getFrameIndexOffset(*MF, DV->getFrameIndex()));
- AddAddress(VariableDie, dwarf::DW_AT_location, Location);
+
+
+ if (VD.hasComplexAddress())
+ AddComplexAddress(DV, VariableDie, dwarf::DW_AT_location, Location);
+ else if (VD.isBlockByrefVariable())
+ AddBlockByrefAddress(DV, VariableDie, dwarf::DW_AT_location, Location);
+ else
+ AddAddress(VariableDie, dwarf::DW_AT_location, Location);
}
return VariableDie;
@@ -978,12 +1285,51 @@ DIE *DwarfDebug::CreateDbgScopeVariable(DbgVariable *DV, CompileUnit *Unit) {
/// getOrCreateScope - Returns the scope associated with the given descriptor.
///
+DbgScope *DwarfDebug::getDbgScope(MDNode *N, const MachineInstr *MI) {
+ DbgScope *&Slot = DbgScopeMap[N];
+ if (Slot) return Slot;
+
+ DbgScope *Parent = NULL;
+
+ DIDescriptor Scope(N);
+ if (Scope.isCompileUnit()) {
+ return NULL;
+ } else if (Scope.isSubprogram()) {
+ DISubprogram SP(N);
+ DIDescriptor ParentDesc = SP.getContext();
+ if (!ParentDesc.isNull() && !ParentDesc.isCompileUnit())
+ Parent = getDbgScope(ParentDesc.getNode(), MI);
+ } else if (Scope.isLexicalBlock()) {
+ DILexicalBlock DB(N);
+ DIDescriptor ParentDesc = DB.getContext();
+ if (!ParentDesc.isNull())
+ Parent = getDbgScope(ParentDesc.getNode(), MI);
+ } else
+ assert (0 && "Unexpected scope info");
+
+ Slot = new DbgScope(Parent, DIDescriptor(N));
+ Slot->setFirstInsn(MI);
+
+ if (Parent)
+ Parent->AddScope(Slot);
+ else
+ // First function is top level function.
+ // FIXME - Dpatel - What is FunctionDbgScope ?
+ if (!FunctionDbgScope)
+ FunctionDbgScope = Slot;
+
+ return Slot;
+}
+
+
+/// getOrCreateScope - Returns the scope associated with the given descriptor.
+/// FIXME - Remove this method.
DbgScope *DwarfDebug::getOrCreateScope(MDNode *N) {
DbgScope *&Slot = DbgScopeMap[N];
if (Slot) return Slot;
DbgScope *Parent = NULL;
- DIBlock Block(N);
+ DILexicalBlock Block(N);
// Don't create a new scope if we already created one for an inlined function.
DenseMap<const MDNode *, DbgScope *>::iterator
@@ -1132,13 +1478,13 @@ void DwarfDebug::ConstructDefaultDbgScope(MachineFunction *MF) {
StringMap<DIE*>::iterator GI = Globals.find(MF->getFunction()->getName());
if (GI != Globals.end()) {
DIE *SPDie = GI->second;
-
+
// Add the function bounds.
AddLabel(SPDie, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr,
DWLabel("func_begin", SubprogramCount));
AddLabel(SPDie, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr,
DWLabel("func_end", SubprogramCount));
-
+
MachineLocation Location(RI->getFrameRegister(*MF));
AddAddress(SPDie, dwarf::DW_AT_frame_base, Location);
}
@@ -1148,8 +1494,8 @@ void DwarfDebug::ConstructDefaultDbgScope(MachineFunction *MF) {
/// source file names. If none currently exists, create a new id and insert it
/// in the SourceIds map. This can update DirectoryNames and SourceFileNames
/// maps as well.
-unsigned DwarfDebug::GetOrCreateSourceID(const std::string &DirName,
- const std::string &FileName) {
+unsigned DwarfDebug::GetOrCreateSourceID(const char *DirName,
+ const char *FileName) {
unsigned DId;
StringMap<unsigned>::iterator DI = DirectoryIdMap.find(DirName);
if (DI != DirectoryIdMap.end()) {
@@ -1184,28 +1530,26 @@ unsigned DwarfDebug::GetOrCreateSourceID(const std::string &DirName,
void DwarfDebug::ConstructCompileUnit(MDNode *N) {
DICompileUnit DIUnit(N);
- std::string Dir, FN, Prod;
- unsigned ID = GetOrCreateSourceID(DIUnit.getDirectory(Dir),
- DIUnit.getFilename(FN));
+ const char *FN = DIUnit.getFilename();
+ const char *Dir = DIUnit.getDirectory();
+ unsigned ID = GetOrCreateSourceID(Dir, FN);
DIE *Die = new DIE(dwarf::DW_TAG_compile_unit);
AddSectionOffset(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4,
DWLabel("section_line", 0), DWLabel("section_line", 0),
false);
AddString(Die, dwarf::DW_AT_producer, dwarf::DW_FORM_string,
- DIUnit.getProducer(Prod));
+ DIUnit.getProducer());
AddUInt(Die, dwarf::DW_AT_language, dwarf::DW_FORM_data1,
DIUnit.getLanguage());
AddString(Die, dwarf::DW_AT_name, dwarf::DW_FORM_string, FN);
- if (!Dir.empty())
+ if (Dir)
AddString(Die, dwarf::DW_AT_comp_dir, dwarf::DW_FORM_string, Dir);
if (DIUnit.isOptimized())
AddUInt(Die, dwarf::DW_AT_APPLE_optimized, dwarf::DW_FORM_flag, 1);
- std::string Flags;
- DIUnit.getFlags(Flags);
- if (!Flags.empty())
+ if (const char *Flags = DIUnit.getFlags())
AddString(Die, dwarf::DW_AT_APPLE_flags, dwarf::DW_FORM_string, Flags);
unsigned RVer = DIUnit.getRunTimeVersion();
@@ -1227,6 +1571,10 @@ void DwarfDebug::ConstructCompileUnit(MDNode *N) {
void DwarfDebug::ConstructGlobalVariableDIE(MDNode *N) {
DIGlobalVariable DI_GV(N);
+ // If debug information is malformed then ignore it.
+ if (DI_GV.Verify() == false)
+ return;
+
// Check for pre-existence.
DIE *&Slot = ModuleCU->getDieMapSlotFor(DI_GV.getNode());
if (Slot)
@@ -1237,9 +1585,8 @@ void DwarfDebug::ConstructGlobalVariableDIE(MDNode *N) {
// Add address.
DIEBlock *Block = new DIEBlock();
AddUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_addr);
- std::string GLN;
AddObjectLabel(Block, 0, dwarf::DW_FORM_udata,
- Asm->getGlobalLinkName(DI_GV.getGlobal(), GLN));
+ Asm->Mang->getMangledName(DI_GV.getGlobal()));
AddBlock(VariableDie, dwarf::DW_AT_location, 0, Block);
// Add to map.
@@ -1249,8 +1596,7 @@ void DwarfDebug::ConstructGlobalVariableDIE(MDNode *N) {
ModuleCU->getDie()->AddChild(VariableDie);
// Expose as global. FIXME - need to check external flag.
- std::string Name;
- ModuleCU->AddGlobal(DI_GV.getName(Name), VariableDie);
+ ModuleCU->AddGlobal(DI_GV.getName(), VariableDie);
return;
}
@@ -1276,14 +1622,13 @@ void DwarfDebug::ConstructSubprogram(MDNode *N) {
ModuleCU->getDie()->AddChild(SubprogramDie);
// Expose as global.
- std::string Name;
- ModuleCU->AddGlobal(SP.getName(Name), SubprogramDie);
+ ModuleCU->AddGlobal(SP.getName(), SubprogramDie);
return;
}
- /// BeginModule - Emit all Dwarf sections that should come prior to the
- /// content. Create global DIEs and emit initial debug info sections.
- /// This is inovked by the target AsmPrinter.
+/// BeginModule - Emit all Dwarf sections that should come prior to the
+/// content. Create global DIEs and emit initial debug info sections.
+/// This is inovked by the target AsmPrinter.
void DwarfDebug::BeginModule(Module *M, MachineModuleInfo *mmi) {
this->M = M;
@@ -1318,7 +1663,7 @@ void DwarfDebug::BeginModule(Module *M, MachineModuleInfo *mmi) {
DebugTimer->stopTimer();
return;
}
-
+
// Create DIEs for each of the externally visible global variables.
for (DebugInfoFinder::iterator I = DbgFinder.global_variable_begin(),
E = DbgFinder.global_variable_end(); I != E; ++I)
@@ -1425,6 +1770,77 @@ void DwarfDebug::EndModule() {
DebugTimer->stopTimer();
}
+/// ExtractScopeInformation - Scan machine instructions in this function
+/// and collect DbgScopes. Return true, if atleast one scope was found.
+bool DwarfDebug::ExtractScopeInformation(MachineFunction *MF) {
+ // If scope information was extracted using .dbg intrinsics then there is not
+ // any need to extract these information by scanning each instruction.
+ if (!DbgScopeMap.empty())
+ return false;
+
+ // Scan each instruction and create scopes.
+ for (MachineFunction::const_iterator I = MF->begin(), E = MF->end();
+ I != E; ++I) {
+ for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
+ II != IE; ++II) {
+ const MachineInstr *MInsn = II;
+ DebugLoc DL = MInsn->getDebugLoc();
+ if (DL.isUnknown())
+ continue;
+ DebugLocTuple DLT = MF->getDebugLocTuple(DL);
+ if (!DLT.CompileUnit)
+ continue;
+ // There is no need to create another DIE for compile unit. For all
+ // other scopes, create one DbgScope now. This will be translated
+ // into a scope DIE at the end.
+ DIDescriptor D(DLT.CompileUnit);
+ if (!D.isCompileUnit()) {
+ DbgScope *Scope = getDbgScope(DLT.CompileUnit, MInsn);
+ Scope->setLastInsn(MInsn);
+ }
+ }
+ }
+
+ // If a scope's last instruction is not set then use its child scope's
+ // last instruction as this scope's last instrunction.
+ for (DenseMap<MDNode *, DbgScope *>::iterator DI = DbgScopeMap.begin(),
+ DE = DbgScopeMap.end(); DI != DE; ++DI) {
+ assert (DI->second->getFirstInsn() && "Invalid first instruction!");
+ DI->second->FixInstructionMarkers();
+ assert (DI->second->getLastInsn() && "Invalid last instruction!");
+ }
+
+ // Each scope has first instruction and last instruction to mark beginning
+ // and end of a scope respectively. Create an inverse map that list scopes
+ // starts (and ends) with an instruction. One instruction may start (or end)
+ // multiple scopes.
+ for (DenseMap<MDNode *, DbgScope *>::iterator DI = DbgScopeMap.begin(),
+ DE = DbgScopeMap.end(); DI != DE; ++DI) {
+ DbgScope *S = DI->second;
+ assert (S && "DbgScope is missing!");
+ const MachineInstr *MI = S->getFirstInsn();
+ assert (MI && "DbgScope does not have first instruction!");
+
+ InsnToDbgScopeMapTy::iterator IDI = DbgScopeBeginMap.find(MI);
+ if (IDI != DbgScopeBeginMap.end())
+ IDI->second.push_back(S);
+ else
+ DbgScopeBeginMap.insert(std::make_pair(MI,
+ SmallVector<DbgScope *, 2>(2, S)));
+
+ MI = S->getLastInsn();
+ assert (MI && "DbgScope does not have last instruction!");
+ IDI = DbgScopeEndMap.find(MI);
+ if (IDI != DbgScopeEndMap.end())
+ IDI->second.push_back(S);
+ else
+ DbgScopeEndMap.insert(std::make_pair(MI,
+ SmallVector<DbgScope *, 2>(2, S)));
+ }
+
+ return !DbgScopeMap.empty();
+}
+
/// BeginFunction - Gather pre-function debug information. Assumes being
/// emitted immediately after the function entry point.
void DwarfDebug::BeginFunction(MachineFunction *MF) {
@@ -1446,9 +1862,9 @@ void DwarfDebug::BeginFunction(MachineFunction *MF) {
DebugLoc FDL = MF->getDefaultDebugLoc();
if (!FDL.isUnknown()) {
DebugLocTuple DLT = MF->getDebugLocTuple(FDL);
- unsigned LabelID = RecordSourceLine(DLT.Line, DLT.Col,
- DICompileUnit(DLT.CompileUnit));
+ unsigned LabelID = RecordSourceLine(DLT.Line, DLT.Col, DLT.CompileUnit);
Asm->printLabel(LabelID);
+ O << '\n';
}
if (TimePassesIsEnabled)
@@ -1504,6 +1920,8 @@ void DwarfDebug::EndFunction(MachineFunction *MF) {
if (FunctionDbgScope) {
delete FunctionDbgScope;
DbgScopeMap.clear();
+ DbgScopeBeginMap.clear();
+ DbgScopeEndMap.clear();
DbgAbstractScopeMap.clear();
DbgConcreteScopeMap.clear();
FunctionDbgScope = NULL;
@@ -1539,17 +1957,17 @@ unsigned DwarfDebug::RecordSourceLine(Value *V, unsigned Line, unsigned Col) {
/// RecordSourceLine - Records location information and associates it with a
/// label. Returns a unique label ID used to generate a label and provide
/// correspondence to the source line list.
-unsigned DwarfDebug::RecordSourceLine(unsigned Line, unsigned Col,
- DICompileUnit CU) {
+unsigned DwarfDebug::RecordSourceLine(unsigned Line, unsigned Col,
+ MDNode *Scope) {
if (!MMI)
return 0;
if (TimePassesIsEnabled)
DebugTimer->startTimer();
- std::string Dir, Fn;
- unsigned Src = GetOrCreateSourceID(CU.getDirectory(Dir),
- CU.getFilename(Fn));
+ DICompileUnit CU(Scope);
+ unsigned Src = GetOrCreateSourceID(CU.getDirectory(),
+ CU.getFilename());
unsigned ID = MMI->NextLabelID();
Lines.push_back(SrcLineInfo(Line, Col, Src, ID));
@@ -1569,7 +1987,7 @@ unsigned DwarfDebug::getOrCreateSourceID(const std::string &DirName,
if (TimePassesIsEnabled)
DebugTimer->startTimer();
- unsigned SrcId = GetOrCreateSourceID(DirName, FileName);
+ unsigned SrcId = GetOrCreateSourceID(DirName.c_str(), FileName.c_str());
if (TimePassesIsEnabled)
DebugTimer->stopTimer();
@@ -1639,7 +2057,7 @@ void DwarfDebug::RecordVariable(MDNode *N, unsigned FrameIndex) {
Scope = I->second;
}
}
- if (!InlinedVar)
+ if (!InlinedVar)
Scope = getOrCreateScope(Context);
}
@@ -1844,7 +2262,7 @@ void DwarfDebug::EmitInitial() {
didInitial = true;
const TargetLoweringObjectFile &TLOF = Asm->getObjFileLowering();
-
+
// Dwarf sections base addresses.
if (MAI->doesDwarfRequireFrameSection()) {
Asm->OutStreamer.SwitchSection(TLOF.getDwarfFrameSection());
@@ -2133,6 +2551,8 @@ void DwarfDebug::EmitDebugLines() {
unsigned LabelID = MMI->MappedLabel(LineInfo.getLabelID());
if (!LabelID) continue;
+ if (LineInfo.getLine() == 0) continue;
+
if (!Asm->isVerbose())
Asm->EOL();
else {
@@ -2402,7 +2822,7 @@ void DwarfDebug::EmitDebugRanges() {
/// EmitDebugMacInfo - Emit visible names into a debug macinfo section.
///
void DwarfDebug::EmitDebugMacInfo() {
- if (const MCSection *LineInfo =
+ if (const MCSection *LineInfo =
Asm->getObjFileLowering().getDwarfMacroInfoSection()) {
// Start the dwarf macinfo section.
Asm->OutStreamer.SwitchSection(LineInfo);
@@ -2452,13 +2872,10 @@ void DwarfDebug::EmitDebugInlineInfo() {
MDNode *Node = I->first;
SmallVector<unsigned, 4> &Labels = I->second;
DISubprogram SP(Node);
- std::string Name;
- std::string LName;
-
- SP.getLinkageName(LName);
- SP.getName(Name);
+ const char *LName = SP.getLinkageName();
+ const char *Name = SP.getName();
- if (LName.empty())
+ if (!LName)
Asm->EmitString(Name);
else {
// Skip special LLVM prefix that is used to inform the asm printer to not
diff --git a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
index 917d6ef..f671ae3 100644
--- a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
+++ b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
@@ -141,6 +141,15 @@ class VISIBILITY_HIDDEN DwarfDebug : public Dwarf {
/// DbgScopeMap - Tracks the scopes in the current function.
DenseMap<MDNode *, DbgScope *> DbgScopeMap;
+ typedef DenseMap<const MachineInstr *, SmallVector<DbgScope *, 2> >
+ InsnToDbgScopeMapTy;
+
+ /// DbgScopeBeginMap - Maps instruction with a list DbgScopes it starts.
+ InsnToDbgScopeMapTy DbgScopeBeginMap;
+
+ /// DbgScopeEndMap - Maps instruction with a list DbgScopes it ends.
+ InsnToDbgScopeMapTy DbgScopeEndMap;
+
/// DbgAbstractScopeMap - Tracks abstract instance scopes in the current
/// function.
DenseMap<MDNode *, DbgScope *> DbgAbstractScopeMap;
@@ -275,11 +284,8 @@ class VISIBILITY_HIDDEN DwarfDebug : public Dwarf {
/// AddSourceLine - Add location information to specified debug information
/// entry.
void AddSourceLine(DIE *Die, const DIVariable *V);
-
- /// AddSourceLine - Add location information to specified debug information
- /// entry.
void AddSourceLine(DIE *Die, const DIGlobal *G);
-
+ void AddSourceLine(DIE *Die, const DISubprogram *SP);
void AddSourceLine(DIE *Die, const DIType *Ty);
/// AddAddress - Add an address attribute to a die based on the location
@@ -287,6 +293,24 @@ class VISIBILITY_HIDDEN DwarfDebug : public Dwarf {
void AddAddress(DIE *Die, unsigned Attribute,
const MachineLocation &Location);
+ /// AddComplexAddress - Start with the address based on the location provided,
+ /// and generate the DWARF information necessary to find the actual variable
+ /// (navigating the extra location information encoded in the type) based on
+ /// the starting location. Add the DWARF information to the die.
+ ///
+ void AddComplexAddress(DbgVariable *&DV, DIE *Die, unsigned Attribute,
+ const MachineLocation &Location);
+
+ // FIXME: Should be reformulated in terms of AddComplexAddress.
+ /// AddBlockByrefAddress - Start with the address based on the location
+ /// provided, and generate the DWARF information necessary to find the
+ /// actual Block variable (navigating the Block struct) based on the
+ /// starting location. Add the DWARF information to the die. Obsolete,
+ /// please use AddComplexAddress instead.
+ ///
+ void AddBlockByrefAddress(DbgVariable *&DV, DIE *Die, unsigned Attribute,
+ const MachineLocation &Location);
+
/// AddType - Add a new type attribute to the specified entity.
void AddType(CompileUnit *DW_Unit, DIE *Entity, DIType Ty);
@@ -333,9 +357,10 @@ class VISIBILITY_HIDDEN DwarfDebug : public Dwarf {
///
DIE *CreateDbgScopeVariable(DbgVariable *DV, CompileUnit *Unit);
- /// getOrCreateScope - Returns the scope associated with the given descriptor.
+ /// getDbgScope - Returns the scope associated with the given descriptor.
///
DbgScope *getOrCreateScope(MDNode *N);
+ DbgScope *getDbgScope(MDNode *N, const MachineInstr *MI);
/// ConstructDbgScope - Construct the components of a scope.
///
@@ -445,8 +470,8 @@ class VISIBILITY_HIDDEN DwarfDebug : public Dwarf {
/// source file names. If none currently exists, create a new id and insert it
/// in the SourceIds map. This can update DirectoryNames and SourceFileNames maps
/// as well.
- unsigned GetOrCreateSourceID(const std::string &DirName,
- const std::string &FileName);
+ unsigned GetOrCreateSourceID(const char *DirName,
+ const char *FileName);
void ConstructCompileUnit(MDNode *N);
@@ -454,6 +479,12 @@ class VISIBILITY_HIDDEN DwarfDebug : public Dwarf {
void ConstructSubprogram(MDNode *N);
+ // FIXME: This should go away in favor of complex addresses.
+ /// Find the type the programmer originally declared the variable to be
+ /// and return that type. Obsolete, use GetComplexAddrType instead.
+ ///
+ DIType GetBlockByrefType(DIType Ty, std::string Name);
+
public:
//===--------------------------------------------------------------------===//
// Main entry points.
@@ -489,7 +520,7 @@ public:
/// RecordSourceLine - Records location information and associates it with a
/// label. Returns a unique label ID used to generate a label and provide
/// correspondence to the source line list.
- unsigned RecordSourceLine(unsigned Line, unsigned Col, DICompileUnit CU);
+ unsigned RecordSourceLine(unsigned Line, unsigned Col, MDNode *Scope);
/// getRecordSourceLineCount - Return the number of source lines in the debug
/// info.
@@ -521,6 +552,11 @@ public:
/// RecordInlinedFnEnd - Indicate the end of inlined subroutine.
unsigned RecordInlinedFnEnd(DISubprogram &SP);
+ /// ExtractScopeInformation - Scan machine instructions in this function
+ /// and collect DbgScopes. Return true, if atleast one scope was found.
+ bool ExtractScopeInformation(MachineFunction *MF);
+
+ void SetDbgScopeLabels(const MachineInstr *MI, unsigned Label);
};
} // End of namespace llvm
diff --git a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfException.cpp b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfException.cpp
index f6feccd..626523b 100644
--- a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfException.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfException.cpp
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This file contains support for writing dwarf exception info into asm files.
+// This file contains support for writing DWARF exception info into asm files.
//
//===----------------------------------------------------------------------===//
@@ -17,21 +17,26 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineLocation.h"
-#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCSection.h"
+#include "llvm/MC/MCStreamer.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/Dwarf.h"
+#include "llvm/Support/Mangler.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringExtras.h"
using namespace llvm;
static TimerGroup &getDwarfTimerGroup() {
- static TimerGroup DwarfTimerGroup("Dwarf Exception");
+ static TimerGroup DwarfTimerGroup("DWARF Exception");
return DwarfTimerGroup;
}
@@ -41,7 +46,7 @@ DwarfException::DwarfException(raw_ostream &OS, AsmPrinter *A,
shouldEmitTableModule(false), shouldEmitMovesModule(false),
ExceptionTimer(0) {
if (TimePassesIsEnabled)
- ExceptionTimer = new Timer("Dwarf Exception Writer",
+ ExceptionTimer = new Timer("DWARF Exception Writer",
getDwarfTimerGroup());
}
@@ -49,23 +54,45 @@ DwarfException::~DwarfException() {
delete ExceptionTimer;
}
+/// SizeOfEncodedValue - Return the size of the encoding in bytes.
+unsigned DwarfException::SizeOfEncodedValue(unsigned Encoding) {
+ if (Encoding == dwarf::DW_EH_PE_omit)
+ return 0;
+
+ switch (Encoding & 0x07) {
+ case dwarf::DW_EH_PE_absptr:
+ return TD->getPointerSize();
+ case dwarf::DW_EH_PE_udata2:
+ return 2;
+ case dwarf::DW_EH_PE_udata4:
+ return 4;
+ case dwarf::DW_EH_PE_udata8:
+ return 8;
+ }
+
+ assert(0 && "Invalid encoded value.");
+ return 0;
+}
+
/// EmitCIE - Emit a Common Information Entry (CIE). This holds information that
/// is shared among many Frame Description Entries. There is at least one CIE
/// in every non-empty .debug_frame section.
-void DwarfException::EmitCIE(const Function *Personality, unsigned Index) {
+void DwarfException::EmitCIE(const Function *PersonalityFn, unsigned Index) {
// Size and sign of stack growth.
int stackGrowth =
Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
TargetFrameInfo::StackGrowsUp ?
TD->getPointerSize() : -TD->getPointerSize();
+ const TargetLoweringObjectFile &TLOF = Asm->getObjFileLowering();
+
// Begin eh frame section.
- Asm->OutStreamer.SwitchSection(Asm->getObjFileLowering().getEHFrameSection());
+ Asm->OutStreamer.SwitchSection(TLOF.getEHFrameSection());
if (MAI->is_EHSymbolPrivate())
O << MAI->getPrivateGlobalPrefix();
-
O << "EH_frame" << Index << ":\n";
+
EmitLabel("section_eh_frame", Index);
// Define base labels.
@@ -84,8 +111,53 @@ void DwarfException::EmitCIE(const Function *Personality, unsigned Index) {
Asm->EOL("CIE Version");
// The personality presence indicates that language specific information will
- // show up in the eh frame.
- Asm->EmitString(Personality ? "zPLR" : "zR");
+ // show up in the eh frame. Find out how we are supposed to lower the
+ // personality function reference:
+ const MCExpr *PersonalityRef = 0;
+ bool IsPersonalityIndirect = false, IsPersonalityPCRel = false;
+ if (PersonalityFn) {
+ // FIXME: HANDLE STATIC CODEGEN MODEL HERE.
+
+ // In non-static mode, ask the object file how to represent this reference.
+ PersonalityRef =
+ TLOF.getSymbolForDwarfGlobalReference(PersonalityFn, Asm->Mang,
+ Asm->MMI,
+ IsPersonalityIndirect,
+ IsPersonalityPCRel);
+ }
+
+ unsigned PerEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
+ if (IsPersonalityIndirect)
+ PerEncoding |= dwarf::DW_EH_PE_indirect;
+ unsigned LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
+ unsigned FDEEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
+
+ char Augmentation[5] = { 0 };
+ unsigned AugmentationSize = 0;
+ char *APtr = Augmentation + 1;
+
+ if (PersonalityRef) {
+ // There is a personality function.
+ *APtr++ = 'P';
+ AugmentationSize += 1 + SizeOfEncodedValue(PerEncoding);
+ }
+
+ if (UsesLSDA[Index]) {
+ // An LSDA pointer is in the FDE augmentation.
+ *APtr++ = 'L';
+ ++AugmentationSize;
+ }
+
+ if (FDEEncoding != dwarf::DW_EH_PE_absptr) {
+ // A non-default pointer encoding for the FDE.
+ *APtr++ = 'R';
+ ++AugmentationSize;
+ }
+
+ if (APtr != Augmentation + 1)
+ Augmentation[0] = 'z';
+
+ Asm->EmitString(Augmentation);
Asm->EOL("CIE Augmentation");
// Round out reader.
@@ -96,39 +168,41 @@ void DwarfException::EmitCIE(const Function *Personality, unsigned Index) {
Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), true));
Asm->EOL("CIE Return Address Column");
+ Asm->EmitULEB128Bytes(AugmentationSize);
+ Asm->EOL("Augmentation Size");
+
+ Asm->EmitInt8(PerEncoding);
+ Asm->EOL("Personality", PerEncoding);
+
// If there is a personality, we need to indicate the function's location.
- if (Personality) {
- Asm->EmitULEB128Bytes(7);
- Asm->EOL("Augmentation Size");
-
- if (MAI->getNeedsIndirectEncoding()) {
- Asm->EmitInt8(dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4 |
- dwarf::DW_EH_PE_indirect);
- Asm->EOL("Personality (pcrel sdata4 indirect)");
- } else {
- Asm->EmitInt8(dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4);
- Asm->EOL("Personality (pcrel sdata4)");
+ if (PersonalityRef) {
+ // If the reference to the personality function symbol is not already
+ // pc-relative, then we need to subtract our current address from it. Do
+ // this by emitting a label and subtracting it from the expression we
+ // already have. This is equivalent to emitting "foo - .", but we have to
+ // emit the label for "." directly.
+ if (!IsPersonalityPCRel) {
+ SmallString<64> Name;
+ raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
+ << "personalityref_addr" << Asm->getFunctionNumber() << "_" << Index;
+ MCSymbol *DotSym = Asm->OutContext.GetOrCreateSymbol(Name.str());
+ Asm->OutStreamer.EmitLabel(DotSym);
+
+ PersonalityRef =
+ MCBinaryExpr::CreateSub(PersonalityRef,
+ MCSymbolRefExpr::Create(DotSym,Asm->OutContext),
+ Asm->OutContext);
}
-
- PrintRelDirective(true);
- O << MAI->getPersonalityPrefix();
- Asm->EmitExternalGlobal((const GlobalVariable *)(Personality));
- O << MAI->getPersonalitySuffix();
- if (strcmp(MAI->getPersonalitySuffix(), "+4 at GOTPCREL"))
- O << "-" << MAI->getPCSymbol();
+
+ O << MAI->getData32bitsDirective();
+ PersonalityRef->print(O, MAI);
Asm->EOL("Personality");
- Asm->EmitInt8(dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4);
- Asm->EOL("LSDA Encoding (pcrel sdata4)");
-
- Asm->EmitInt8(dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4);
- Asm->EOL("FDE Encoding (pcrel sdata4)");
- } else {
- Asm->EmitULEB128Bytes(1);
- Asm->EOL("Augmentation Size");
+ Asm->EmitInt8(LSDAEncoding);
+ Asm->EOL("LSDA Encoding", LSDAEncoding);
- Asm->EmitInt8(dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4);
- Asm->EOL("FDE Encoding (pcrel sdata4)");
+ Asm->EmitInt8(FDEEncoding);
+ Asm->EOL("FDE Encoding", FDEEncoding);
}
// Indicate locations of general callee saved registers in frame.
@@ -139,8 +213,7 @@ void DwarfException::EmitCIE(const Function *Personality, unsigned Index) {
// On Darwin the linker honors the alignment of eh_frame, which means it must
// be 8-byte on 64-bit targets to match what gcc does. Otherwise you get
// holes which confuse readers of eh_frame.
- Asm->EmitAlignment(TD->getPointerSize() == sizeof(int32_t) ? 2 : 3,
- 0, 0, false);
+ Asm->EmitAlignment(TD->getPointerSize() == 4 ? 2 : 3, 0, 0, false);
EmitLabel("eh_frame_common_end", Index);
Asm->EOL();
@@ -212,10 +285,10 @@ void DwarfException::EmitFDE(const FunctionEHFrameInfo &EHFrameInfo) {
if (EHFrameInfo.hasLandingPads)
EmitReference("exception", EHFrameInfo.Number, true, false);
else {
- if (is4Byte)
- Asm->EmitInt32((int)0);
- else
- Asm->EmitInt64((int)0);
+ if (is4Byte)
+ Asm->EmitInt32((int)0);
+ else
+ Asm->EmitInt64((int)0);
}
Asm->EOL("Language Specific Data Area");
} else {
@@ -504,10 +577,10 @@ ComputeCallSiteTable(SmallVectorImpl<CallSiteEntry> &CallSites,
/// site, each type ID is checked for a match to the current exception. If
/// it matches then the exception and type id are passed on to the landing
/// pad. Otherwise the next action is looked up. This chain is terminated
-/// with a next action of zero. If no type id is found the the frame is
+/// with a next action of zero. If no type id is found then the frame is
/// unwound and handling continues.
/// 3. Type ID table contains references to all the C++ typeinfo for all
-/// catches in the function. This tables is reversed indexed base 1.
+/// catches in the function. This tables is reverse indexed base 1.
void DwarfException::EmitExceptionTable() {
const std::vector<GlobalVariable *> &TypeInfos = MMI->getTypeInfos();
const std::vector<unsigned> &FilterIds = MMI->getFilterIds();
@@ -528,11 +601,12 @@ void DwarfException::EmitExceptionTable() {
// landing pad site.
SmallVector<ActionEntry, 32> Actions;
SmallVector<unsigned, 64> FirstActions;
- unsigned SizeActions = ComputeActionsTable(LandingPads, Actions, FirstActions);
+ unsigned SizeActions = ComputeActionsTable(LandingPads, Actions,
+ FirstActions);
// Invokes and nounwind calls have entries in PadMap (due to being bracketed
// by try-range labels when lowered). Ordinary calls do not, so appropriate
- // try-ranges for them need be deduced when using Dwarf exception handling.
+ // try-ranges for them need be deduced when using DWARF exception handling.
RangeMapType PadMap;
for (unsigned i = 0, N = LandingPads.size(); i != N; ++i) {
const LandingPadInfo *LandingPad = LandingPads[i];
@@ -551,69 +625,35 @@ void DwarfException::EmitExceptionTable() {
// Final tallies.
// Call sites.
- const unsigned SiteStartSize = sizeof(int32_t); // DW_EH_PE_udata4
- const unsigned SiteLengthSize = sizeof(int32_t); // DW_EH_PE_udata4
- const unsigned LandingPadSize = sizeof(int32_t); // DW_EH_PE_udata4
+ const unsigned SiteStartSize = SizeOfEncodedValue(dwarf::DW_EH_PE_udata4);
+ const unsigned SiteLengthSize = SizeOfEncodedValue(dwarf::DW_EH_PE_udata4);
+ const unsigned LandingPadSize = SizeOfEncodedValue(dwarf::DW_EH_PE_udata4);
+ bool IsSJLJ = MAI->getExceptionHandlingType() == ExceptionHandling::SjLj;
+ bool HaveTTData = IsSJLJ ? (!TypeInfos.empty() || !FilterIds.empty()) : true;
unsigned SizeSites;
- bool HaveTTData = (MAI->getExceptionHandlingType() == ExceptionHandling::SjLj)
- ? (!TypeInfos.empty() || !FilterIds.empty()) : true;
-
-
- if (MAI->getExceptionHandlingType() == ExceptionHandling::SjLj) {
+ if (IsSJLJ)
SizeSites = 0;
- } else
+ else
SizeSites = CallSites.size() *
(SiteStartSize + SiteLengthSize + LandingPadSize);
+
for (unsigned i = 0, e = CallSites.size(); i < e; ++i) {
SizeSites += MCAsmInfo::getULEB128Size(CallSites[i].Action);
- if (MAI->getExceptionHandlingType() == ExceptionHandling::SjLj)
+ if (IsSJLJ)
SizeSites += MCAsmInfo::getULEB128Size(i);
}
- // Type infos.
- const unsigned TypeInfoSize = TD->getPointerSize(); // DW_EH_PE_absptr
- unsigned SizeTypes = TypeInfos.size() * TypeInfoSize;
-
- unsigned TypeOffset = sizeof(int8_t) + // Call site format
- MCAsmInfo::getULEB128Size(SizeSites) + // Call-site table length
- SizeSites + SizeActions + SizeTypes;
- unsigned TotalSize = sizeof(int8_t) + // LPStart format
- sizeof(int8_t) + // TType format
- (HaveTTData ?
- MCAsmInfo::getULEB128Size(TypeOffset) : 0) + // TType base offset
- TypeOffset;
-
- unsigned SizeAlign = (4 - TotalSize) & 3;
-
- // Begin the exception table.
+ // Type infos.
const MCSection *LSDASection = Asm->getObjFileLowering().getLSDASection();
- Asm->OutStreamer.SwitchSection(LSDASection);
- Asm->EmitAlignment(2, 0, 0, false);
- O << "GCC_except_table" << SubprogramCount << ":\n";
-
- for (unsigned i = 0; i != SizeAlign; ++i) {
- Asm->EmitInt8(0);
- Asm->EOL("Padding");
- }
+ unsigned TTypeFormat;
+ unsigned TypeFormatSize;
- EmitLabel("exception", SubprogramCount);
- if (MAI->getExceptionHandlingType() == ExceptionHandling::SjLj) {
- std::string SjLjName = "_lsda_";
- SjLjName += MF->getFunction()->getName().str();
- EmitLabel(SjLjName.c_str(), 0);
- }
-
- // Emit the header.
- Asm->EmitInt8(dwarf::DW_EH_PE_omit);
- Asm->EOL("@LPStart format (DW_EH_PE_omit)");
-
-#if 0
- if (TypeInfos.empty() && FilterIds.empty()) {
- // If there are no typeinfos or filters, there is nothing to emit, optimize
- // by specifying the "omit" encoding.
- Asm->EmitInt8(dwarf::DW_EH_PE_omit);
- Asm->EOL("@TType format (DW_EH_PE_omit)");
+ if (!HaveTTData) {
+ // For SjLj exceptions, if there is no TypeInfo, then we just explicitly say
+ // that we're omitting that bit.
+ TTypeFormat = dwarf::DW_EH_PE_omit;
+ TypeFormatSize = SizeOfEncodedValue(dwarf::DW_EH_PE_absptr);
} else {
// Okay, we have actual filters or typeinfos to emit. As such, we need to
// pick a type encoding for them. We're about to emit a list of pointers to
@@ -621,12 +661,15 @@ void DwarfException::EmitExceptionTable() {
// mode, this reference will require a relocation by the dynamic linker.
//
// Because of this, we have a couple of options:
+ //
// 1) If we are in -static mode, we can always use an absolute reference
// from the LSDA, because the static linker will resolve it.
+ //
// 2) Otherwise, if the LSDA section is writable, we can output the direct
// reference to the typeinfo and allow the dynamic linker to relocate
// it. Since it is in a writable section, the dynamic linker won't
// have a problem.
+ //
// 3) Finally, if we're in PIC mode and the LDSA section isn't writable,
// we need to use some form of indirection. For example, on Darwin,
// we can output a statically-relocatable reference to a dyld stub. The
@@ -635,41 +678,82 @@ void DwarfException::EmitExceptionTable() {
// need to tell the personality function of the unwinder to indirect
// through the dyld stub.
//
- // FIXME: When this is actually implemented, we'll have to emit the stubs
+ // FIXME: When (3) is actually implemented, we'll have to emit the stubs
// somewhere. This predicate should be moved to a shared location that is
// in target-independent code.
//
- if (LSDASection->isWritable() ||
- Asm->TM.getRelocationModel() == Reloc::Static) {
- Asm->EmitInt8(DW_EH_PE_absptr);
- Asm->EOL("TType format (DW_EH_PE_absptr)");
- } else {
- Asm->EmitInt8(DW_EH_PE_pcrel | DW_EH_PE_indirect | DW_EH_PE_sdata4);
- Asm->EOL("TType format (DW_EH_PE_pcrel | DW_EH_PE_indirect"
- " | DW_EH_PE_sdata4)");
- }
- Asm->EmitULEB128Bytes(TypeOffset);
- Asm->EOL("TType base offset");
+ if (LSDASection->getKind().isWriteable() ||
+ Asm->TM.getRelocationModel() == Reloc::Static)
+ TTypeFormat = dwarf::DW_EH_PE_absptr;
+ else
+ TTypeFormat = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel |
+ dwarf::DW_EH_PE_sdata4;
+
+ TypeFormatSize = SizeOfEncodedValue(TTypeFormat);
}
-#else
- // For SjLj exceptions, if there is no TypeInfo, then we just explicitly
- // say that we're omitting that bit.
- // FIXME: does this apply to Dwarf also? The above #if 0 implies yes?
- if (!HaveTTData) {
- Asm->EmitInt8(dwarf::DW_EH_PE_omit);
- Asm->EOL("@TType format (DW_EH_PE_omit)");
- } else {
- Asm->EmitInt8(dwarf::DW_EH_PE_absptr);
- Asm->EOL("@TType format (DW_EH_PE_absptr)");
- Asm->EmitULEB128Bytes(TypeOffset);
+
+ // Begin the exception table.
+ Asm->OutStreamer.SwitchSection(LSDASection);
+ Asm->EmitAlignment(2, 0, 0, false);
+
+ O << "GCC_except_table" << SubprogramCount << ":\n";
+
+ // The type infos need to be aligned. GCC does this by inserting padding just
+ // before the type infos. However, this changes the size of the exception
+ // table, so you need to take this into account when you output the exception
+ // table size. However, the size is output using a variable length encoding.
+ // So by increasing the size by inserting padding, you may increase the number
+ // of bytes used for writing the size. If it increases, say by one byte, then
+ // you now need to output one less byte of padding to get the type infos
+ // aligned. However this decreases the size of the exception table. This
+ // changes the value you have to output for the exception table size. Due to
+ // the variable length encoding, the number of bytes used for writing the
+ // length may decrease. If so, you then have to increase the amount of
+ // padding. And so on. If you look carefully at the GCC code you will see that
+ // it indeed does this in a loop, going on and on until the values stabilize.
+ // We chose another solution: don't output padding inside the table like GCC
+ // does, instead output it before the table.
+ unsigned SizeTypes = TypeInfos.size() * TypeFormatSize;
+ unsigned TyOffset = sizeof(int8_t) + // Call site format
+ MCAsmInfo::getULEB128Size(SizeSites) + // Call-site table length
+ SizeSites + SizeActions + SizeTypes;
+ unsigned TotalSize = sizeof(int8_t) + // LPStart format
+ sizeof(int8_t) + // TType format
+ (HaveTTData ?
+ MCAsmInfo::getULEB128Size(TyOffset) : 0) + // TType base offset
+ TyOffset;
+ unsigned SizeAlign = (4 - TotalSize) & 3;
+
+ for (unsigned i = 0; i != SizeAlign; ++i) {
+ Asm->EmitInt8(0);
+ Asm->EOL("Padding");
+ }
+
+ EmitLabel("exception", SubprogramCount);
+
+ if (IsSJLJ) {
+ SmallString<16> LSDAName;
+ raw_svector_ostream(LSDAName) << MAI->getPrivateGlobalPrefix() <<
+ "_LSDA_" << Asm->getFunctionNumber();
+ O << LSDAName.str() << ":\n";
+ }
+
+ // Emit the header.
+ Asm->EmitInt8(dwarf::DW_EH_PE_omit);
+ Asm->EOL("@LPStart format", dwarf::DW_EH_PE_omit);
+
+ Asm->EmitInt8(TTypeFormat);
+ Asm->EOL("@TType format", TTypeFormat);
+
+ if (HaveTTData) {
+ Asm->EmitULEB128Bytes(TyOffset);
Asm->EOL("@TType base offset");
}
-#endif
- // SjLj Exception handilng
- if (MAI->getExceptionHandlingType() == ExceptionHandling::SjLj) {
+ // SjLj Exception handling
+ if (IsSJLJ) {
Asm->EmitInt8(dwarf::DW_EH_PE_udata4);
- Asm->EOL("Call site format (DW_EH_PE_udata4)");
+ Asm->EOL("Call site format", dwarf::DW_EH_PE_udata4);
Asm->EmitULEB128Bytes(SizeSites);
Asm->EOL("Call site table length");
@@ -710,19 +794,11 @@ void DwarfException::EmitExceptionTable() {
// * The first action record for that call site.
//
// A missing entry in the call-site table indicates that a call is not
- // supposed to throw. Such calls include:
- //
- // * Calls to destructors within cleanup code. C++ semantics forbids these
- // calls to throw.
- // * Calls to intrinsic routines in the standard library which are known
- // not to throw (sin, memcpy, et al).
- //
- // If the runtime does not find the call-site entry for a given call, it
- // will call `terminate()'.
+ // supposed to throw.
// Emit the landing pad call site table.
Asm->EmitInt8(dwarf::DW_EH_PE_udata4);
- Asm->EOL("Call site format (DW_EH_PE_udata4)");
+ Asm->EOL("Call site format", dwarf::DW_EH_PE_udata4);
Asm->EmitULEB128Bytes(SizeSites);
Asm->EOL("Call site table size");
@@ -823,8 +899,7 @@ void DwarfException::EmitExceptionTable() {
PrintRelDirective();
if (GV) {
- std::string GLN;
- O << Asm->getGlobalLinkName(GV, GLN);
+ O << Asm->Mang->getMangledName(GV);
} else {
O << "0x0";
}
@@ -848,48 +923,51 @@ void DwarfException::EmitExceptionTable() {
void DwarfException::EndModule() {
if (MAI->getExceptionHandlingType() != ExceptionHandling::Dwarf)
return;
+
+ if (!shouldEmitMovesModule && !shouldEmitTableModule)
+ return;
+
if (TimePassesIsEnabled)
ExceptionTimer->startTimer();
- if (shouldEmitMovesModule || shouldEmitTableModule) {
- const std::vector<Function *> Personalities = MMI->getPersonalities();
- for (unsigned i = 0; i < Personalities.size(); ++i)
- EmitCIE(Personalities[i], i);
+ const std::vector<Function *> Personalities = MMI->getPersonalities();
- for (std::vector<FunctionEHFrameInfo>::iterator I = EHFrames.begin(),
- E = EHFrames.end(); I != E; ++I)
- EmitFDE(*I);
- }
+ for (unsigned I = 0, E = Personalities.size(); I < E; ++I)
+ EmitCIE(Personalities[I], I);
+
+ for (std::vector<FunctionEHFrameInfo>::iterator
+ I = EHFrames.begin(), E = EHFrames.end(); I != E; ++I)
+ EmitFDE(*I);
if (TimePassesIsEnabled)
ExceptionTimer->stopTimer();
}
-/// BeginFunction - Gather pre-function exception information. Assumes being
-/// emitted immediately after the function entry point.
+/// BeginFunction - Gather pre-function exception information. Assumes it's
+/// being emitted immediately after the function entry point.
void DwarfException::BeginFunction(MachineFunction *MF) {
+ if (!MMI || !MAI->doesSupportExceptionHandling()) return;
+
if (TimePassesIsEnabled)
ExceptionTimer->startTimer();
this->MF = MF;
shouldEmitTable = shouldEmitMoves = false;
- if (MMI && MAI->doesSupportExceptionHandling()) {
- // Map all labels and get rid of any dead landing pads.
- MMI->TidyLandingPads();
+ // Map all labels and get rid of any dead landing pads.
+ MMI->TidyLandingPads();
- // If any landing pads survive, we need an EH table.
- if (MMI->getLandingPads().size())
- shouldEmitTable = true;
+ // If any landing pads survive, we need an EH table.
+ if (!MMI->getLandingPads().empty())
+ shouldEmitTable = true;
- // See if we need frame move info.
- if (!MF->getFunction()->doesNotThrow() || UnwindTablesMandatory)
- shouldEmitMoves = true;
+ // See if we need frame move info.
+ if (!MF->getFunction()->doesNotThrow() || UnwindTablesMandatory)
+ shouldEmitMoves = true;
- if (shouldEmitMoves || shouldEmitTable)
- // Assumes in correct section after the entry point.
- EmitLabel("eh_func_begin", ++SubprogramCount);
- }
+ if (shouldEmitMoves || shouldEmitTable)
+ // Assumes in correct section after the entry point.
+ EmitLabel("eh_func_begin", ++SubprogramCount);
shouldEmitTableModule |= shouldEmitTable;
shouldEmitMovesModule |= shouldEmitMoves;
@@ -901,23 +979,28 @@ void DwarfException::BeginFunction(MachineFunction *MF) {
/// EndFunction - Gather and emit post-function exception information.
///
void DwarfException::EndFunction() {
+ if (!shouldEmitMoves && !shouldEmitTable) return;
+
if (TimePassesIsEnabled)
ExceptionTimer->startTimer();
- if (shouldEmitMoves || shouldEmitTable) {
- EmitLabel("eh_func_end", SubprogramCount);
- EmitExceptionTable();
-
- // Save EH frame information
- EHFrames.push_back(
- FunctionEHFrameInfo(getAsm()->getCurrentFunctionEHName(MF),
- SubprogramCount,
- MMI->getPersonalityIndex(),
- MF->getFrameInfo()->hasCalls(),
- !MMI->getLandingPads().empty(),
- MMI->getFrameMoves(),
- MF->getFunction()));
- }
+ EmitLabel("eh_func_end", SubprogramCount);
+ EmitExceptionTable();
+
+ std::string FunctionEHName =
+ Asm->Mang->getMangledName(MF->getFunction(), ".eh",
+ Asm->MAI->is_EHSymbolPrivate());
+
+ // Save EH frame information
+ EHFrames.push_back(FunctionEHFrameInfo(FunctionEHName, SubprogramCount,
+ MMI->getPersonalityIndex(),
+ MF->getFrameInfo()->hasCalls(),
+ !MMI->getLandingPads().empty(),
+ MMI->getFrameMoves(),
+ MF->getFunction()));
+
+ // Record if this personality index uses a landing pad.
+ UsesLSDA[MMI->getPersonalityIndex()] |= !MMI->getLandingPads().empty();
if (TimePassesIsEnabled)
ExceptionTimer->stopTimer();
diff --git a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfException.h b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfException.h
index b1820b7..f6f5025 100644
--- a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfException.h
+++ b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfException.h
@@ -51,6 +51,11 @@ class VISIBILITY_HIDDEN DwarfException : public Dwarf {
std::vector<FunctionEHFrameInfo> EHFrames;
+ /// UsesLSDA - Indicates whether an FDE that uses the CIE at the given index
+ /// uses an LSDA. If so, then we need to encode that information in the CIE's
+ /// augmentation.
+ DenseMap<unsigned, bool> UsesLSDA;
+
/// shouldEmitTable - Per-function flag to indicate if EH tables should
/// be emitted.
bool shouldEmitTable;
@@ -70,6 +75,9 @@ class VISIBILITY_HIDDEN DwarfException : public Dwarf {
/// ExceptionTimer - Timer for the Dwarf exception writer.
Timer *ExceptionTimer;
+ /// SizeOfEncodedValue - Return the size of the encoding in bytes.
+ unsigned SizeOfEncodedValue(unsigned Encoding);
+
/// EmitCIE - Emit a Common Information Entry (CIE). This holds information
/// that is shared among many Frame Description Entries. There is at least
/// one CIE in every non-empty .debug_frame section.
diff --git a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfWriter.cpp b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
index aafac71..bebf8e0 100644
--- a/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
@@ -51,6 +51,8 @@ void DwarfWriter::BeginModule(Module *M,
void DwarfWriter::EndModule() {
DE->EndModule();
DD->EndModule();
+ delete DD; DD = 0;
+ delete DE; DE = 0;
}
/// BeginFunction - Gather pre-function debug information. Assumes being
@@ -75,8 +77,8 @@ void DwarfWriter::EndFunction(MachineFunction *MF) {
/// label. Returns a unique label ID used to generate a label and provide
/// correspondence to the source line list.
unsigned DwarfWriter::RecordSourceLine(unsigned Line, unsigned Col,
- DICompileUnit CU) {
- return DD->RecordSourceLine(Line, Col, CU);
+ MDNode *Scope) {
+ return DD->RecordSourceLine(Line, Col, Scope);
}
/// RecordRegionStart - Indicate the start of a region.
diff --git a/libclamav/c++/llvm/lib/CodeGen/BranchFolding.cpp b/libclamav/c++/llvm/lib/CodeGen/BranchFolding.cpp
index c117650..f9abeac 100644
--- a/libclamav/c++/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/BranchFolding.cpp
@@ -17,6 +17,7 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "branchfolding"
+#include "BranchFolding.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -46,64 +47,29 @@ TailMergeThreshold("tail-merge-threshold",
cl::desc("Max number of predecessors to consider tail merging"),
cl::init(150), cl::Hidden);
-namespace {
- struct VISIBILITY_HIDDEN BranchFolder : public MachineFunctionPass {
- static char ID;
- explicit BranchFolder(bool defaultEnableTailMerge) :
- MachineFunctionPass(&ID) {
- switch (FlagEnableTailMerge) {
- case cl::BOU_UNSET: EnableTailMerge = defaultEnableTailMerge; break;
- case cl::BOU_TRUE: EnableTailMerge = true; break;
- case cl::BOU_FALSE: EnableTailMerge = false; break;
- }
- }
- virtual bool runOnMachineFunction(MachineFunction &MF);
- virtual const char *getPassName() const { return "Control Flow Optimizer"; }
- const TargetInstrInfo *TII;
- MachineModuleInfo *MMI;
- bool MadeChange;
- private:
- // Tail Merging.
- bool EnableTailMerge;
- bool TailMergeBlocks(MachineFunction &MF);
- bool TryMergeBlocks(MachineBasicBlock* SuccBB,
- MachineBasicBlock* PredBB);
- void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
- MachineBasicBlock *NewDest);
- MachineBasicBlock *SplitMBBAt(MachineBasicBlock &CurMBB,
- MachineBasicBlock::iterator BBI1);
- unsigned ComputeSameTails(unsigned CurHash, unsigned minCommonTailLength);
- void RemoveBlocksWithHash(unsigned CurHash, MachineBasicBlock* SuccBB,
- MachineBasicBlock* PredBB);
- unsigned CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
- unsigned maxCommonTailLength);
-
- typedef std::pair<unsigned,MachineBasicBlock*> MergePotentialsElt;
- typedef std::vector<MergePotentialsElt>::iterator MPIterator;
- std::vector<MergePotentialsElt> MergePotentials;
-
- typedef std::pair<MPIterator, MachineBasicBlock::iterator> SameTailElt;
- std::vector<SameTailElt> SameTails;
-
- const TargetRegisterInfo *RegInfo;
- RegScavenger *RS;
- // Branch optzn.
- bool OptimizeBranches(MachineFunction &MF);
- void OptimizeBlock(MachineBasicBlock *MBB);
- void RemoveDeadBlock(MachineBasicBlock *MBB);
- bool OptimizeImpDefsBlock(MachineBasicBlock *MBB);
-
- bool CanFallThrough(MachineBasicBlock *CurBB);
- bool CanFallThrough(MachineBasicBlock *CurBB, bool BranchUnAnalyzable,
- MachineBasicBlock *TBB, MachineBasicBlock *FBB,
- const SmallVectorImpl<MachineOperand> &Cond);
- };
- char BranchFolder::ID = 0;
-}
+char BranchFolderPass::ID = 0;
FunctionPass *llvm::createBranchFoldingPass(bool DefaultEnableTailMerge) {
- return new BranchFolder(DefaultEnableTailMerge); }
+ return new BranchFolderPass(DefaultEnableTailMerge);
+}
+
+bool BranchFolderPass::runOnMachineFunction(MachineFunction &MF) {
+ return OptimizeFunction(MF,
+ MF.getTarget().getInstrInfo(),
+ MF.getTarget().getRegisterInfo(),
+ getAnalysisIfAvailable<MachineModuleInfo>());
+}
+
+
+
+BranchFolder::BranchFolder(bool defaultEnableTailMerge) {
+ switch (FlagEnableTailMerge) {
+ case cl::BOU_UNSET: EnableTailMerge = defaultEnableTailMerge; break;
+ case cl::BOU_TRUE: EnableTailMerge = true; break;
+ case cl::BOU_FALSE: EnableTailMerge = false; break;
+ }
+}
/// RemoveDeadBlock - Remove the specified dead machine basic block from the
/// function, updating the CFG.
@@ -148,7 +114,7 @@ bool BranchFolder::OptimizeImpDefsBlock(MachineBasicBlock *MBB) {
break;
unsigned Reg = I->getOperand(0).getReg();
ImpDefRegs.insert(Reg);
- for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
+ for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
ImpDefRegs.insert(SubReg);
++I;
@@ -182,32 +148,37 @@ bool BranchFolder::OptimizeImpDefsBlock(MachineBasicBlock *MBB) {
return true;
}
-bool BranchFolder::runOnMachineFunction(MachineFunction &MF) {
- TII = MF.getTarget().getInstrInfo();
- if (!TII) return false;
+/// OptimizeFunction - Perhaps branch folding, tail merging and other
+/// CFG optimizations on the given function.
+bool BranchFolder::OptimizeFunction(MachineFunction &MF,
+ const TargetInstrInfo *tii,
+ const TargetRegisterInfo *tri,
+ MachineModuleInfo *mmi) {
+ if (!tii) return false;
- RegInfo = MF.getTarget().getRegisterInfo();
+ TII = tii;
+ TRI = tri;
+ MMI = mmi;
+
+ RS = TRI->requiresRegisterScavenging(MF) ? new RegScavenger() : NULL;
// Fix CFG. The later algorithms expect it to be right.
- bool EverMadeChange = false;
+ bool MadeChange = false;
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; I++) {
MachineBasicBlock *MBB = I, *TBB = 0, *FBB = 0;
SmallVector<MachineOperand, 4> Cond;
if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true))
- EverMadeChange |= MBB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
- EverMadeChange |= OptimizeImpDefsBlock(MBB);
+ MadeChange |= MBB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
+ MadeChange |= OptimizeImpDefsBlock(MBB);
}
- RS = RegInfo->requiresRegisterScavenging(MF) ? new RegScavenger() : NULL;
-
- MMI = getAnalysisIfAvailable<MachineModuleInfo>();
bool MadeChangeThisIteration = true;
while (MadeChangeThisIteration) {
MadeChangeThisIteration = false;
MadeChangeThisIteration |= TailMergeBlocks(MF);
MadeChangeThisIteration |= OptimizeBranches(MF);
- EverMadeChange |= MadeChangeThisIteration;
+ MadeChange |= MadeChangeThisIteration;
}
// See if any jump tables have become mergable or dead as the code generator
@@ -224,8 +195,12 @@ bool BranchFolder::runOnMachineFunction(MachineFunction &MF) {
// Scan the jump tables, seeing if there are any duplicates. Note that this
// is N^2, which should be fixed someday.
- for (unsigned i = 1, e = JTs.size(); i != e; ++i)
- JTMapping.push_back(JTI->getJumpTableIndex(JTs[i].MBBs));
+ for (unsigned i = 1, e = JTs.size(); i != e; ++i) {
+ if (JTs[i].MBBs.empty())
+ JTMapping.push_back(i);
+ else
+ JTMapping.push_back(JTI->getJumpTableIndex(JTs[i].MBBs));
+ }
// If a jump table was merge with another one, walk the function rewriting
// references to jump tables to reference the new JT ID's. Keep track of
@@ -252,12 +227,12 @@ bool BranchFolder::runOnMachineFunction(MachineFunction &MF) {
for (unsigned i = 0, e = JTIsLive.size(); i != e; ++i)
if (!JTIsLive.test(i)) {
JTI->RemoveJumpTable(i);
- EverMadeChange = true;
+ MadeChange = true;
}
}
-
+
delete RS;
- return EverMadeChange;
+ return MadeChange;
}
//===----------------------------------------------------------------------===//
@@ -397,9 +372,9 @@ MachineBasicBlock *BranchFolder::SplitMBBAt(MachineBasicBlock &CurMBB,
RS->enterBasicBlock(&CurMBB);
if (!CurMBB.empty())
RS->forward(prior(CurMBB.end()));
- BitVector RegsLiveAtExit(RegInfo->getNumRegs());
+ BitVector RegsLiveAtExit(TRI->getNumRegs());
RS->getRegsUsed(RegsLiveAtExit, false);
- for (unsigned int i=0, e=RegInfo->getNumRegs(); i!=e; i++)
+ for (unsigned int i=0, e=TRI->getNumRegs(); i!=e; i++)
if (RegsLiveAtExit[i])
NewMBB->addLiveIn(i);
}
@@ -592,11 +567,12 @@ unsigned BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
bool BranchFolder::TryMergeBlocks(MachineBasicBlock *SuccBB,
MachineBasicBlock* PredBB) {
+ bool MadeChange = false;
+
// It doesn't make sense to save a single instruction since tail merging
// will add a jump.
// FIXME: Ask the target to provide the threshold?
unsigned minCommonTailLength = (SuccBB ? 1 : 2) + 1;
- MadeChange = false;
DEBUG(errs() << "\nTryMergeBlocks " << MergePotentials.size() << '\n');
@@ -667,7 +643,7 @@ bool BranchFolder::TailMergeBlocks(MachineFunction &MF) {
if (!EnableTailMerge) return false;
- MadeChange = false;
+ bool MadeChange = false;
// First find blocks with no successors.
MergePotentials.clear();
@@ -778,14 +754,14 @@ bool BranchFolder::TailMergeBlocks(MachineFunction &MF) {
//===----------------------------------------------------------------------===//
bool BranchFolder::OptimizeBranches(MachineFunction &MF) {
- MadeChange = false;
+ bool MadeChange = false;
// Make sure blocks are numbered in order
MF.RenumberBlocks();
for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ) {
MachineBasicBlock *MBB = I++;
- OptimizeBlock(MBB);
+ MadeChange |= OptimizeBlock(MBB);
// If it is dead, remove it.
if (MBB->pred_empty()) {
@@ -879,7 +855,9 @@ static bool IsBetterFallthrough(MachineBasicBlock *MBB1,
/// OptimizeBlock - Analyze and optimize control flow related to the specified
/// block. This is never called on the entry block.
-void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
+bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
+ bool MadeChange = false;
+
MachineFunction::iterator FallThrough = MBB;
++FallThrough;
@@ -888,7 +866,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
// points to this block.
if (MBB->empty() && !MBB->isLandingPad()) {
// Dead block? Leave for cleanup later.
- if (MBB->pred_empty()) return;
+ if (MBB->pred_empty()) return MadeChange;
if (FallThrough == MBB->getParent()->end()) {
// TODO: Simplify preds to not branch here if possible!
@@ -905,7 +883,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
ReplaceMBBInJumpTables(MBB, FallThrough);
MadeChange = true;
}
- return;
+ return MadeChange;
}
// Check to see if we can simplify the terminator of the block before this
@@ -1019,7 +997,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
MBB->moveAfter(--MBB->getParent()->end());
MadeChange = true;
++NumBranchOpts;
- return;
+ return MadeChange;
}
}
}
@@ -1121,7 +1099,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
if (DidChange) {
++NumBranchOpts;
MadeChange = true;
- if (!HasBranchToSelf) return;
+ if (!HasBranchToSelf) return MadeChange;
}
}
}
@@ -1202,8 +1180,10 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
PrevBB.isSuccessor(FallThrough)) {
MBB->moveAfter(--MBB->getParent()->end());
MadeChange = true;
- return;
+ return MadeChange;
}
}
}
+
+ return MadeChange;
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/BranchFolding.h b/libclamav/c++/llvm/lib/CodeGen/BranchFolding.h
new file mode 100644
index 0000000..9763e33
--- /dev/null
+++ b/libclamav/c++/llvm/lib/CodeGen/BranchFolding.h
@@ -0,0 +1,84 @@
+//===-- BranchFolding.h - Fold machine code branch instructions --*- C++ -*===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_BRANCHFOLDING_HPP
+#define LLVM_CODEGEN_BRANCHFOLDING_HPP
+
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include <vector>
+
+namespace llvm {
+ class MachineFunction;
+ class MachineModuleInfo;
+ class RegScavenger;
+ class TargetInstrInfo;
+ class TargetRegisterInfo;
+
+ class BranchFolder {
+ public:
+ explicit BranchFolder(bool defaultEnableTailMerge);
+
+ bool OptimizeFunction(MachineFunction &MF,
+ const TargetInstrInfo *tii,
+ const TargetRegisterInfo *tri,
+ MachineModuleInfo *mmi);
+ private:
+ typedef std::pair<unsigned,MachineBasicBlock*> MergePotentialsElt;
+ typedef std::vector<MergePotentialsElt>::iterator MPIterator;
+ std::vector<MergePotentialsElt> MergePotentials;
+
+ typedef std::pair<MPIterator, MachineBasicBlock::iterator> SameTailElt;
+ std::vector<SameTailElt> SameTails;
+
+ bool EnableTailMerge;
+ const TargetInstrInfo *TII;
+ const TargetRegisterInfo *TRI;
+ MachineModuleInfo *MMI;
+ RegScavenger *RS;
+
+ bool TailMergeBlocks(MachineFunction &MF);
+ bool TryMergeBlocks(MachineBasicBlock* SuccBB,
+ MachineBasicBlock* PredBB);
+ void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
+ MachineBasicBlock *NewDest);
+ MachineBasicBlock *SplitMBBAt(MachineBasicBlock &CurMBB,
+ MachineBasicBlock::iterator BBI1);
+ unsigned ComputeSameTails(unsigned CurHash, unsigned minCommonTailLength);
+ void RemoveBlocksWithHash(unsigned CurHash, MachineBasicBlock* SuccBB,
+ MachineBasicBlock* PredBB);
+ unsigned CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
+ unsigned maxCommonTailLength);
+
+ bool OptimizeBranches(MachineFunction &MF);
+ bool OptimizeBlock(MachineBasicBlock *MBB);
+ void RemoveDeadBlock(MachineBasicBlock *MBB);
+ bool OptimizeImpDefsBlock(MachineBasicBlock *MBB);
+
+ bool CanFallThrough(MachineBasicBlock *CurBB);
+ bool CanFallThrough(MachineBasicBlock *CurBB, bool BranchUnAnalyzable,
+ MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+ const SmallVectorImpl<MachineOperand> &Cond);
+ };
+
+
+ /// BranchFolderPass - Wrap branch folder in a machine function pass.
+ class BranchFolderPass : public MachineFunctionPass,
+ public BranchFolder {
+ public:
+ static char ID;
+ explicit BranchFolderPass(bool defaultEnableTailMerge)
+ : MachineFunctionPass(&ID), BranchFolder(defaultEnableTailMerge) {}
+
+ virtual bool runOnMachineFunction(MachineFunction &MF);
+ virtual const char *getPassName() const { return "Control Flow Optimizer"; }
+ };
+}
+
+#endif /* LLVM_CODEGEN_BRANCHFOLDING_HPP */
diff --git a/libclamav/c++/llvm/lib/CodeGen/CMakeLists.txt b/libclamav/c++/llvm/lib/CodeGen/CMakeLists.txt
index 7eae520..5b116e9 100644
--- a/libclamav/c++/llvm/lib/CodeGen/CMakeLists.txt
+++ b/libclamav/c++/llvm/lib/CodeGen/CMakeLists.txt
@@ -30,6 +30,7 @@ add_llvm_library(LLVMCodeGen
MachineLICM.cpp
MachineLoopInfo.cpp
MachineModuleInfo.cpp
+ MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp
@@ -45,7 +46,6 @@ add_llvm_library(LLVMCodeGen
RegAllocLinearScan.cpp
RegAllocLocal.cpp
RegAllocPBQP.cpp
- RegAllocSimple.cpp
RegisterCoalescer.cpp
RegisterScavenging.cpp
ScheduleDAG.cpp
diff --git a/libclamav/c++/llvm/lib/CodeGen/DwarfEHPrepare.cpp b/libclamav/c++/llvm/lib/CodeGen/DwarfEHPrepare.cpp
index 1658111..0ae7b35 100644
--- a/libclamav/c++/llvm/lib/CodeGen/DwarfEHPrepare.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/DwarfEHPrepare.cpp
@@ -107,7 +107,9 @@ FunctionPass *llvm::createDwarfEHPass(const TargetLowering *tli, bool fast) {
/// NormalizeLandingPads - Normalize and discover landing pads, noting them
/// in the LandingPads set. A landing pad is normal if the only CFG edges
-/// that end at it are unwind edges from invoke instructions.
+/// that end at it are unwind edges from invoke instructions. If we inlined
+/// through an invoke we could have a normal branch from the previous
+/// unwind block through to the landing pad for the original invoke.
/// Abnormal landing pads are fixed up by redirecting all unwind edges to
/// a new basic block which falls through to the original.
bool DwarfEHPrepare::NormalizeLandingPads() {
@@ -132,6 +134,7 @@ bool DwarfEHPrepare::NormalizeLandingPads() {
break;
}
}
+
if (OnlyUnwoundTo) {
// Only unwind edges lead to the landing pad. Remember the landing pad.
LandingPads.insert(LPad);
@@ -219,28 +222,41 @@ bool DwarfEHPrepare::NormalizeLandingPads() {
/// at runtime if there is no such exception: using unwind to throw a new
/// exception is currently not supported.
bool DwarfEHPrepare::LowerUnwinds() {
- bool Changed = false;
+ SmallVector<TerminatorInst*, 16> UnwindInsts;
for (Function::iterator I = F->begin(), E = F->end(); I != E; ++I) {
TerminatorInst *TI = I->getTerminator();
- if (!isa<UnwindInst>(TI))
- continue;
+ if (isa<UnwindInst>(TI))
+ UnwindInsts.push_back(TI);
+ }
+
+ if (UnwindInsts.empty()) return false;
+
+ // Find the rewind function if we didn't already.
+ if (!RewindFunction) {
+ LLVMContext &Ctx = UnwindInsts[0]->getContext();
+ std::vector<const Type*>
+ Params(1, PointerType::getUnqual(Type::getInt8Ty(Ctx)));
+ FunctionType *FTy = FunctionType::get(Type::getVoidTy(Ctx),
+ Params, false);
+ const char *RewindName = TLI->getLibcallName(RTLIB::UNWIND_RESUME);
+ RewindFunction = F->getParent()->getOrInsertFunction(RewindName, FTy);
+ }
+
+ bool Changed = false;
+
+ for (SmallVectorImpl<TerminatorInst*>::iterator
+ I = UnwindInsts.begin(), E = UnwindInsts.end(); I != E; ++I) {
+ TerminatorInst *TI = *I;
// Replace the unwind instruction with a call to _Unwind_Resume (or the
// appropriate target equivalent) followed by an UnreachableInst.
- // Find the rewind function if we didn't already.
- if (!RewindFunction) {
- std::vector<const Type*> Params(1,
- PointerType::getUnqual(Type::getInt8Ty(TI->getContext())));
- FunctionType *FTy = FunctionType::get(Type::getVoidTy(TI->getContext()),
- Params, false);
- const char *RewindName = TLI->getLibcallName(RTLIB::UNWIND_RESUME);
- RewindFunction = F->getParent()->getOrInsertFunction(RewindName, FTy);
- }
-
// Create the call...
- CallInst::Create(RewindFunction, CreateReadOfExceptionValue(I), "", TI);
+ CallInst *CI = CallInst::Create(RewindFunction,
+ CreateReadOfExceptionValue(TI->getParent()),
+ "", TI);
+ CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME));
// ...followed by an UnreachableInst.
new UnreachableInst(TI->getContext(), TI);
diff --git a/libclamav/c++/llvm/lib/CodeGen/ELFWriter.cpp b/libclamav/c++/llvm/lib/CodeGen/ELFWriter.cpp
index b1842ff..55a2f70 100644
--- a/libclamav/c++/llvm/lib/CodeGen/ELFWriter.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/ELFWriter.cpp
@@ -93,6 +93,24 @@ ELFWriter::ELFWriter(raw_ostream &o, TargetMachine &tm)
ELFWriter::~ELFWriter() {
delete ElfCE;
delete &OutContext;
+
+ while(!SymbolList.empty()) {
+ delete SymbolList.back();
+ SymbolList.pop_back();
+ }
+
+ while(!PrivateSyms.empty()) {
+ delete PrivateSyms.back();
+ PrivateSyms.pop_back();
+ }
+
+ while(!SectionList.empty()) {
+ delete SectionList.back();
+ SectionList.pop_back();
+ }
+
+ // Release the name mangler object.
+ delete Mang; Mang = 0;
}
// doInitialization - Emit the file header and all of the global variables for
@@ -714,13 +732,6 @@ bool ELFWriter::doFinalization(Module &M) {
// Dump the sections and section table to the .o file.
OutputSectionsAndSectionTable();
- // We are done with the abstract symbols.
- SymbolList.clear();
- SectionList.clear();
- NumSections = 0;
-
- // Release the name mangler object.
- delete Mang; Mang = 0;
return false;
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/ELFWriter.h b/libclamav/c++/llvm/lib/CodeGen/ELFWriter.h
index e44ab3f..b61b484 100644
--- a/libclamav/c++/llvm/lib/CodeGen/ELFWriter.h
+++ b/libclamav/c++/llvm/lib/CodeGen/ELFWriter.h
@@ -28,6 +28,7 @@ namespace llvm {
class ELFSection;
struct ELFSym;
class GlobalVariable;
+ class JITDebugRegisterer;
class Mangler;
class MachineCodeEmitter;
class MachineConstantPoolEntry;
@@ -51,6 +52,7 @@ namespace llvm {
///
class ELFWriter : public MachineFunctionPass {
friend class ELFCodeEmitter;
+ friend class JITDebugRegisterer;
public:
static char ID;
diff --git a/libclamav/c++/llvm/lib/CodeGen/ExactHazardRecognizer.cpp b/libclamav/c++/llvm/lib/CodeGen/ExactHazardRecognizer.cpp
index 2d07b76..4f32c2b 100644
--- a/libclamav/c++/llvm/lib/CodeGen/ExactHazardRecognizer.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/ExactHazardRecognizer.cpp
@@ -31,13 +31,11 @@ ExactHazardRecognizer::ExactHazardRecognizer(const InstrItineraryData &LItinData
ScoreboardDepth = 1;
if (!ItinData.isEmpty()) {
for (unsigned idx = 0; ; ++idx) {
- // If the begin stage of an itinerary has 0 cycles and units,
- // then we have reached the end of the itineraries.
- const InstrStage *IS = ItinData.beginStage(idx);
- const InstrStage *E = ItinData.endStage(idx);
- if ((IS->getCycles() == 0) && (IS->getUnits() == 0))
+ if (ItinData.isEndMarker(idx))
break;
+ const InstrStage *IS = ItinData.beginStage(idx);
+ const InstrStage *E = ItinData.endStage(idx);
unsigned ItinDepth = 0;
for (; IS != E; ++IS)
ItinDepth += IS->getCycles();
@@ -54,7 +52,7 @@ ExactHazardRecognizer::ExactHazardRecognizer(const InstrItineraryData &LItinData
}
ExactHazardRecognizer::~ExactHazardRecognizer() {
- delete Scoreboard;
+ delete [] Scoreboard;
}
void ExactHazardRecognizer::Reset() {
@@ -83,6 +81,9 @@ void ExactHazardRecognizer::dumpScoreboard() {
}
ExactHazardRecognizer::HazardType ExactHazardRecognizer::getHazardType(SUnit *SU) {
+ if (ItinData.isEmpty())
+ return NoHazard;
+
unsigned cycle = 0;
// Use the itinerary for the underlying instruction to check for
@@ -96,7 +97,7 @@ ExactHazardRecognizer::HazardType ExactHazardRecognizer::getHazardType(SUnit *SU
for (unsigned int i = 0; i < IS->getCycles(); ++i) {
assert(((cycle + i) < ScoreboardDepth) &&
"Scoreboard depth exceeded!");
-
+
unsigned index = getFutureIndex(cycle + i);
unsigned freeUnits = IS->getUnits() & ~Scoreboard[index];
if (!freeUnits) {
@@ -106,7 +107,7 @@ ExactHazardRecognizer::HazardType ExactHazardRecognizer::getHazardType(SUnit *SU
return Hazard;
}
}
-
+
// Advance the cycle to the next stage.
cycle += IS->getNextCycles();
}
@@ -115,6 +116,9 @@ ExactHazardRecognizer::HazardType ExactHazardRecognizer::getHazardType(SUnit *SU
}
void ExactHazardRecognizer::EmitInstruction(SUnit *SU) {
+ if (ItinData.isEmpty())
+ return;
+
unsigned cycle = 0;
// Use the itinerary for the underlying instruction to reserve FU's
@@ -128,7 +132,7 @@ void ExactHazardRecognizer::EmitInstruction(SUnit *SU) {
for (unsigned int i = 0; i < IS->getCycles(); ++i) {
assert(((cycle + i) < ScoreboardDepth) &&
"Scoreboard depth exceeded!");
-
+
unsigned index = getFutureIndex(cycle + i);
unsigned freeUnits = IS->getUnits() & ~Scoreboard[index];
@@ -138,15 +142,15 @@ void ExactHazardRecognizer::EmitInstruction(SUnit *SU) {
freeUnit = freeUnits;
freeUnits = freeUnit & (freeUnit - 1);
} while (freeUnits);
-
+
assert(freeUnit && "No function unit available!");
Scoreboard[index] |= freeUnit;
}
-
+
// Advance the cycle to the next stage.
cycle += IS->getNextCycles();
}
-
+
DEBUG(dumpScoreboard());
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/GCStrategy.cpp b/libclamav/c++/llvm/lib/CodeGen/GCStrategy.cpp
index 2529e4f..6d0de41 100644
--- a/libclamav/c++/llvm/lib/CodeGen/GCStrategy.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/GCStrategy.cpp
@@ -72,7 +72,8 @@ namespace {
void FindSafePoints(MachineFunction &MF);
void VisitCallPoint(MachineBasicBlock::iterator MI);
unsigned InsertLabel(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI) const;
+ MachineBasicBlock::iterator MI,
+ DebugLoc DL) const;
void FindStackOffsets(MachineFunction &MF);
@@ -329,11 +330,13 @@ void MachineCodeAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
}
unsigned MachineCodeAnalysis::InsertLabel(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI) const {
+ MachineBasicBlock::iterator MI,
+ DebugLoc DL) const {
unsigned Label = MMI->NextLabelID();
- // N.B. we assume that MI is *not* equal to the "end()" iterator.
- BuildMI(MBB, MI, MI->getDebugLoc(),
+
+ BuildMI(MBB, MI, DL,
TII->get(TargetInstrInfo::GC_LABEL)).addImm(Label);
+
return Label;
}
@@ -344,10 +347,12 @@ void MachineCodeAnalysis::VisitCallPoint(MachineBasicBlock::iterator CI) {
++RAI;
if (FI->getStrategy().needsSafePoint(GC::PreCall))
- FI->addSafePoint(GC::PreCall, InsertLabel(*CI->getParent(), CI));
+ FI->addSafePoint(GC::PreCall, InsertLabel(*CI->getParent(), CI,
+ CI->getDebugLoc()));
if (FI->getStrategy().needsSafePoint(GC::PostCall))
- FI->addSafePoint(GC::PostCall, InsertLabel(*CI->getParent(), RAI));
+ FI->addSafePoint(GC::PostCall, InsertLabel(*CI->getParent(), RAI,
+ CI->getDebugLoc()));
}
void MachineCodeAnalysis::FindSafePoints(MachineFunction &MF) {
diff --git a/libclamav/c++/llvm/lib/CodeGen/IfConversion.cpp b/libclamav/c++/llvm/lib/CodeGen/IfConversion.cpp
index 62bde60..7b613ff 100644
--- a/libclamav/c++/llvm/lib/CodeGen/IfConversion.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/IfConversion.cpp
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "ifcvt"
+#include "BranchFolding.h"
#include "llvm/Function.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
@@ -360,6 +361,13 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
Roots.clear();
BBAnalysis.clear();
+ if (MadeChange) {
+ BranchFolder BF(false);
+ BF.OptimizeFunction(MF, TII,
+ MF.getTarget().getRegisterInfo(),
+ getAnalysisIfAvailable<MachineModuleInfo>());
+ }
+
return MadeChange;
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/libclamav/c++/llvm/lib/CodeGen/LLVMTargetMachine.cpp
index 5b6cfdc..4e713a6 100644
--- a/libclamav/c++/llvm/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/LLVMTargetMachine.cpp
@@ -39,16 +39,12 @@ static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
cl::desc("Dump emitter generated instructions as assembly"));
static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
cl::desc("Dump garbage collector data"));
+static cl::opt<bool> HoistConstants("hoist-constants", cl::Hidden,
+ cl::desc("Hoist constants out of loops"));
static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
cl::desc("Verify generated machine code"),
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
-// When this works it will be on by default.
-static cl::opt<bool>
-DisablePostRAScheduler("disable-post-RA-scheduler",
- cl::desc("Disable scheduling after register allocation"),
- cl::init(true));
-
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
// able to enable or disable fast-isel independently from -O0.
@@ -259,8 +255,11 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
- if (OptLevel != CodeGenOpt::None)
+ if (OptLevel != CodeGenOpt::None) {
+ if (HoistConstants)
+ PM.add(createCodeGenLICMPass());
PM.add(createCodeGenPreparePass(getTargetLowering()));
+ }
PM.add(createStackProtectorPass(getTargetLowering()));
@@ -318,8 +317,12 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
PM.add(createPrologEpilogCodeInserter());
printAndVerify(PM);
+ // Run pre-sched2 passes.
+ if (addPreSched2(PM, OptLevel))
+ printAndVerify(PM);
+
// Second pass scheduler.
- if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
+ if (OptLevel != CodeGenOpt::None) {
PM.add(createPostRAScheduler());
printAndVerify(PM);
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/LiveInterval.cpp b/libclamav/c++/llvm/lib/CodeGen/LiveInterval.cpp
index 805b672..38b9401 100644
--- a/libclamav/c++/llvm/lib/CodeGen/LiveInterval.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/LiveInterval.cpp
@@ -28,6 +28,11 @@
#include <algorithm>
using namespace llvm;
+// Print a MachineInstrIndex to a raw_ostream.
+void MachineInstrIndex::print(raw_ostream &os) const {
+ os << (index & ~PHI_BIT);
+}
+
// An example for liveAt():
//
// this = [1,4), liveAt(0) will return false. The instruction defining this
@@ -35,7 +40,7 @@ using namespace llvm;
// variable it represents. This is because slot 1 is used (def slot) and spans
// up to slot 3 (store slot).
//
-bool LiveInterval::liveAt(unsigned I) const {
+bool LiveInterval::liveAt(MachineInstrIndex I) const {
Ranges::const_iterator r = std::upper_bound(ranges.begin(), ranges.end(), I);
if (r == ranges.begin())
@@ -48,7 +53,7 @@ bool LiveInterval::liveAt(unsigned I) const {
// liveBeforeAndAt - Check if the interval is live at the index and the index
// just before it. If index is liveAt, check if it starts a new live range.
// If it does, then check if the previous live range ends at index-1.
-bool LiveInterval::liveBeforeAndAt(unsigned I) const {
+bool LiveInterval::liveBeforeAndAt(MachineInstrIndex I) const {
Ranges::const_iterator r = std::upper_bound(ranges.begin(), ranges.end(), I);
if (r == ranges.begin())
@@ -126,7 +131,7 @@ bool LiveInterval::overlapsFrom(const LiveInterval& other,
/// overlaps - Return true if the live interval overlaps a range specified
/// by [Start, End).
-bool LiveInterval::overlaps(unsigned Start, unsigned End) const {
+bool LiveInterval::overlaps(MachineInstrIndex Start, MachineInstrIndex End) const {
assert(Start < End && "Invalid range");
const_iterator I = begin();
const_iterator E = end();
@@ -144,10 +149,10 @@ bool LiveInterval::overlaps(unsigned Start, unsigned End) const {
/// specified by I to end at the specified endpoint. To do this, we should
/// merge and eliminate all ranges that this will overlap with. The iterator is
/// not invalidated.
-void LiveInterval::extendIntervalEndTo(Ranges::iterator I, unsigned NewEnd) {
+void LiveInterval::extendIntervalEndTo(Ranges::iterator I, MachineInstrIndex NewEnd) {
assert(I != ranges.end() && "Not a valid interval!");
VNInfo *ValNo = I->valno;
- unsigned OldEnd = I->end;
+ MachineInstrIndex OldEnd = I->end;
// Search for the first interval that we can't merge with.
Ranges::iterator MergeTo = next(I);
@@ -162,7 +167,7 @@ void LiveInterval::extendIntervalEndTo(Ranges::iterator I, unsigned NewEnd) {
ranges.erase(next(I), MergeTo);
// Update kill info.
- removeKills(ValNo, OldEnd, I->end-1);
+ ValNo->removeKills(OldEnd, I->end.prevSlot_());
// If the newly formed range now touches the range after it and if they have
// the same value number, merge the two ranges into one range.
@@ -178,7 +183,7 @@ void LiveInterval::extendIntervalEndTo(Ranges::iterator I, unsigned NewEnd) {
/// specified by I to start at the specified endpoint. To do this, we should
/// merge and eliminate all ranges that this will overlap with.
LiveInterval::Ranges::iterator
-LiveInterval::extendIntervalStartTo(Ranges::iterator I, unsigned NewStart) {
+LiveInterval::extendIntervalStartTo(Ranges::iterator I, MachineInstrIndex NewStart) {
assert(I != ranges.end() && "Not a valid interval!");
VNInfo *ValNo = I->valno;
@@ -211,7 +216,7 @@ LiveInterval::extendIntervalStartTo(Ranges::iterator I, unsigned NewStart) {
LiveInterval::iterator
LiveInterval::addRangeFrom(LiveRange LR, iterator From) {
- unsigned Start = LR.start, End = LR.end;
+ MachineInstrIndex Start = LR.start, End = LR.end;
iterator it = std::upper_bound(From, ranges.end(), Start);
// If the inserted interval starts in the middle or right at the end of
@@ -245,7 +250,7 @@ LiveInterval::addRangeFrom(LiveRange LR, iterator From) {
extendIntervalEndTo(it, End);
else if (End < it->end)
// Overlapping intervals, there might have been a kill here.
- removeKill(it->valno, End);
+ it->valno->removeKill(End);
return it;
}
} else {
@@ -261,33 +266,32 @@ LiveInterval::addRangeFrom(LiveRange LR, iterator From) {
return ranges.insert(it, LR);
}
-/// isInOneLiveRange - Return true if the range specified is entirely in the
+/// isInOneLiveRange - Return true if the range specified is entirely in
/// a single LiveRange of the live interval.
-bool LiveInterval::isInOneLiveRange(unsigned Start, unsigned End) {
+bool LiveInterval::isInOneLiveRange(MachineInstrIndex Start, MachineInstrIndex End) {
Ranges::iterator I = std::upper_bound(ranges.begin(), ranges.end(), Start);
if (I == ranges.begin())
return false;
--I;
- return I->contains(Start) && I->contains(End-1);
+ return I->containsRange(Start, End);
}
/// removeRange - Remove the specified range from this interval. Note that
/// the range must be in a single LiveRange in its entirety.
-void LiveInterval::removeRange(unsigned Start, unsigned End,
+void LiveInterval::removeRange(MachineInstrIndex Start, MachineInstrIndex End,
bool RemoveDeadValNo) {
// Find the LiveRange containing this span.
Ranges::iterator I = std::upper_bound(ranges.begin(), ranges.end(), Start);
assert(I != ranges.begin() && "Range is not in interval!");
--I;
- assert(I->contains(Start) && I->contains(End-1) &&
- "Range is not entirely in interval!");
+ assert(I->containsRange(Start, End) && "Range is not entirely in interval!");
// If the span we are removing is at the start of the LiveRange, adjust it.
VNInfo *ValNo = I->valno;
if (I->start == Start) {
if (I->end == End) {
- removeKills(I->valno, Start, End);
+ ValNo->removeKills(Start, End);
if (RemoveDeadValNo) {
// Check if val# is dead.
bool isDead = true;
@@ -321,13 +325,13 @@ void LiveInterval::removeRange(unsigned Start, unsigned End,
// Otherwise if the span we are removing is at the end of the LiveRange,
// adjust the other way.
if (I->end == End) {
- removeKills(ValNo, Start, End);
+ ValNo->removeKills(Start, End);
I->end = Start;
return;
}
// Otherwise, we are splitting the LiveRange into two pieces.
- unsigned OldEnd = I->end;
+ MachineInstrIndex OldEnd = I->end;
I->end = Start; // Trim the old interval.
// Insert the new one.
@@ -361,11 +365,12 @@ void LiveInterval::removeValNo(VNInfo *ValNo) {
/// scaleNumbering - Renumber VNI and ranges to provide gaps for new
/// instructions.
+
void LiveInterval::scaleNumbering(unsigned factor) {
// Scale ranges.
for (iterator RI = begin(), RE = end(); RI != RE; ++RI) {
- RI->start = InstrSlots::scale(RI->start, factor);
- RI->end = InstrSlots::scale(RI->end, factor);
+ RI->start = RI->start.scale(factor);
+ RI->end = RI->end.scale(factor);
}
// Scale VNI info.
@@ -373,20 +378,20 @@ void LiveInterval::scaleNumbering(unsigned factor) {
VNInfo *vni = *VNI;
if (vni->isDefAccurate())
- vni->def = InstrSlots::scale(vni->def, factor);
+ vni->def = vni->def.scale(factor);
for (unsigned i = 0; i < vni->kills.size(); ++i) {
- if (!vni->kills[i].isPHIKill)
- vni->kills[i].killIdx =
- InstrSlots::scale(vni->kills[i].killIdx, factor);
+ if (!vni->kills[i].isPHIIndex())
+ vni->kills[i] = vni->kills[i].scale(factor);
}
}
}
+
/// getLiveRangeContaining - Return the live range that contains the
/// specified index, or null if there is none.
LiveInterval::const_iterator
-LiveInterval::FindLiveRangeContaining(unsigned Idx) const {
+LiveInterval::FindLiveRangeContaining(MachineInstrIndex Idx) const {
const_iterator It = std::upper_bound(begin(), end(), Idx);
if (It != ranges.begin()) {
--It;
@@ -398,7 +403,7 @@ LiveInterval::FindLiveRangeContaining(unsigned Idx) const {
}
LiveInterval::iterator
-LiveInterval::FindLiveRangeContaining(unsigned Idx) {
+LiveInterval::FindLiveRangeContaining(MachineInstrIndex Idx) {
iterator It = std::upper_bound(begin(), end(), Idx);
if (It != begin()) {
--It;
@@ -409,17 +414,27 @@ LiveInterval::FindLiveRangeContaining(unsigned Idx) {
return end();
}
-/// findDefinedVNInfo - Find the VNInfo that's defined at the specified index
-/// (register interval) or defined by the specified register (stack inteval).
-VNInfo *LiveInterval::findDefinedVNInfo(unsigned DefIdxOrReg) const {
- VNInfo *VNI = NULL;
+/// findDefinedVNInfo - Find the VNInfo defined by the specified
+/// index (register interval).
+VNInfo *LiveInterval::findDefinedVNInfoForRegInt(MachineInstrIndex Idx) const {
for (LiveInterval::const_vni_iterator i = vni_begin(), e = vni_end();
- i != e; ++i)
- if ((*i)->def == DefIdxOrReg) {
- VNI = *i;
- break;
- }
- return VNI;
+ i != e; ++i) {
+ if ((*i)->def == Idx)
+ return *i;
+ }
+
+ return 0;
+}
+
+/// findDefinedVNInfo - Find the VNInfo defined by the specified
+/// register (stack inteval).
+VNInfo *LiveInterval::findDefinedVNInfoForStackInt(unsigned reg) const {
+ for (LiveInterval::const_vni_iterator i = vni_begin(), e = vni_end();
+ i != e; ++i) {
+ if ((*i)->getReg() == reg)
+ return *i;
+ }
+ return 0;
}
/// join - Join two live intervals (this, and other) together. This applies
@@ -546,7 +561,7 @@ void LiveInterval::MergeValueInAsValue(const LiveInterval &RHS,
for (const_iterator I = RHS.begin(), E = RHS.end(); I != E; ++I) {
if (I->valno != RHSValNo)
continue;
- unsigned Start = I->start, End = I->end;
+ MachineInstrIndex Start = I->start, End = I->end;
IP = std::upper_bound(IP, end(), Start);
// If the start of this range overlaps with an existing liverange, trim it.
if (IP != begin() && IP[-1].end > Start) {
@@ -622,20 +637,21 @@ void LiveInterval::MergeInClobberRanges(const LiveInterval &Clobbers,
else if (UnusedValNo)
ClobberValNo = UnusedValNo;
else {
- UnusedValNo = ClobberValNo = getNextValue(0, 0, false, VNInfoAllocator);
+ UnusedValNo = ClobberValNo =
+ getNextValue(MachineInstrIndex(), 0, false, VNInfoAllocator);
ValNoMaps.insert(std::make_pair(I->valno, ClobberValNo));
}
bool Done = false;
- unsigned Start = I->start, End = I->end;
+ MachineInstrIndex Start = I->start, End = I->end;
// If a clobber range starts before an existing range and ends after
// it, the clobber range will need to be split into multiple ranges.
// Loop until the entire clobber range is handled.
while (!Done) {
Done = true;
IP = std::upper_bound(IP, end(), Start);
- unsigned SubRangeStart = Start;
- unsigned SubRangeEnd = End;
+ MachineInstrIndex SubRangeStart = Start;
+ MachineInstrIndex SubRangeEnd = End;
// If the start of this range overlaps with an existing liverange, trim it.
if (IP != begin() && IP[-1].end > SubRangeStart) {
@@ -671,11 +687,13 @@ void LiveInterval::MergeInClobberRanges(const LiveInterval &Clobbers,
}
}
-void LiveInterval::MergeInClobberRange(unsigned Start, unsigned End,
+void LiveInterval::MergeInClobberRange(MachineInstrIndex Start,
+ MachineInstrIndex End,
BumpPtrAllocator &VNInfoAllocator) {
// Find a value # to use for the clobber ranges. If there is already a value#
// for unknown values, use it.
- VNInfo *ClobberValNo = getNextValue(0, 0, false, VNInfoAllocator);
+ VNInfo *ClobberValNo =
+ getNextValue(MachineInstrIndex(), 0, false, VNInfoAllocator);
iterator IP = begin();
IP = std::upper_bound(IP, end(), Start);
@@ -788,7 +806,7 @@ void LiveInterval::Copy(const LiveInterval &RHS,
unsigned LiveInterval::getSize() const {
unsigned Sum = 0;
for (const_iterator I = begin(), E = end(); I != E; ++I)
- Sum += I->end - I->start;
+ Sum += I->start.distance(I->end);
return Sum;
}
@@ -862,8 +880,8 @@ void LiveInterval::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
if (ee || vni->hasPHIKill()) {
OS << "-(";
for (unsigned j = 0; j != ee; ++j) {
- OS << vni->kills[j].killIdx;
- if (vni->kills[j].isPHIKill)
+ OS << vni->kills[j];
+ if (vni->kills[j].isPHIIndex())
OS << "*";
if (j != ee-1)
OS << " ";
diff --git a/libclamav/c++/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp b/libclamav/c++/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
index 96afda4..4f4bb9b 100644
--- a/libclamav/c++/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -25,6 +25,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
@@ -49,19 +50,20 @@ using namespace llvm;
static cl::opt<bool> DisableReMat("disable-rematerialization",
cl::init(false), cl::Hidden);
-static cl::opt<bool> SplitAtBB("split-intervals-at-bb",
- cl::init(true), cl::Hidden);
-static cl::opt<int> SplitLimit("split-limit",
- cl::init(-1), cl::Hidden);
-
static cl::opt<bool> EnableAggressiveRemat("aggressive-remat", cl::Hidden);
static cl::opt<bool> EnableFastSpilling("fast-spill",
cl::init(false), cl::Hidden);
-STATISTIC(numIntervals, "Number of original intervals");
-STATISTIC(numFolds , "Number of loads/stores folded into instructions");
-STATISTIC(numSplits , "Number of intervals split");
+static cl::opt<bool> EarlyCoalescing("early-coalescing", cl::init(false));
+
+static cl::opt<int> CoalescingLimit("early-coalescing-limit",
+ cl::init(-1), cl::Hidden);
+
+STATISTIC(numIntervals , "Number of original intervals");
+STATISTIC(numFolds , "Number of loads/stores folded into instructions");
+STATISTIC(numSplits , "Number of intervals split");
+STATISTIC(numCoalescing, "Number of early coalescing performed");
char LiveIntervals::ID = 0;
static RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
@@ -96,29 +98,27 @@ void LiveIntervals::releaseMemory() {
i2miMap_.clear();
r2iMap_.clear();
terminatorGaps.clear();
+ phiJoinCopies.clear();
// Release VNInfo memroy regions after all VNInfo objects are dtor'd.
VNInfoAllocator.Reset();
- while (!ClonedMIs.empty()) {
- MachineInstr *MI = ClonedMIs.back();
- ClonedMIs.pop_back();
+ while (!CloneMIs.empty()) {
+ MachineInstr *MI = CloneMIs.back();
+ CloneMIs.pop_back();
mf_->DeleteMachineInstr(MI);
}
}
static bool CanTurnIntoImplicitDef(MachineInstr *MI, unsigned Reg,
- const TargetInstrInfo *tii_) {
+ unsigned OpIdx, const TargetInstrInfo *tii_){
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
Reg == SrcReg)
return true;
- if ((MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
- MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
- MI->getOperand(2).getReg() == Reg)
+ if (OpIdx == 2 && MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG)
return true;
- if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
- MI->getOperand(1).getReg() == Reg)
+ if (OpIdx == 1 && MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)
return true;
return false;
}
@@ -142,10 +142,28 @@ void LiveIntervals::processImplicitDefs() {
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
unsigned Reg = MI->getOperand(0).getReg();
ImpDefRegs.insert(Reg);
+ if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
+ for (const unsigned *SS = tri_->getSubRegisters(Reg); *SS; ++SS)
+ ImpDefRegs.insert(*SS);
+ }
ImpDefMIs.push_back(MI);
continue;
}
+ if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
+ MachineOperand &MO = MI->getOperand(2);
+ if (ImpDefRegs.count(MO.getReg())) {
+ // %reg1032<def> = INSERT_SUBREG %reg1032, undef, 2
+ // This is an identity copy, eliminate it now.
+ if (MO.isKill()) {
+ LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
+ vi.removeKill(MI);
+ }
+ MI->eraseFromParent();
+ continue;
+ }
+ }
+
bool ChangedToImpDef = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
@@ -157,13 +175,16 @@ void LiveIntervals::processImplicitDefs() {
if (!ImpDefRegs.count(Reg))
continue;
// Use is a copy, just turn it into an implicit_def.
- if (CanTurnIntoImplicitDef(MI, Reg, tii_)) {
+ if (CanTurnIntoImplicitDef(MI, Reg, i, tii_)) {
bool isKill = MO.isKill();
MI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
MI->RemoveOperand(j);
- if (isKill)
+ if (isKill) {
ImpDefRegs.erase(Reg);
+ LiveVariables::VarInfo& vi = lv_->getVarInfo(Reg);
+ vi.removeKill(MI);
+ }
ChangedToImpDef = true;
break;
}
@@ -254,6 +275,7 @@ void LiveIntervals::processImplicitDefs() {
}
}
+
void LiveIntervals::computeNumbering() {
Index2MiMap OldI2MI = i2miMap_;
std::vector<IdxMBBPair> OldI2MBB = Idx2MBBMap;
@@ -263,20 +285,22 @@ void LiveIntervals::computeNumbering() {
mi2iMap_.clear();
i2miMap_.clear();
terminatorGaps.clear();
+ phiJoinCopies.clear();
FunctionSize = 0;
// Number MachineInstrs and MachineBasicBlocks.
// Initialize MBB indexes to a sentinal.
- MBB2IdxMap.resize(mf_->getNumBlockIDs(), std::make_pair(~0U,~0U));
+ MBB2IdxMap.resize(mf_->getNumBlockIDs(),
+ std::make_pair(MachineInstrIndex(),MachineInstrIndex()));
- unsigned MIIndex = 0;
+ MachineInstrIndex MIIndex;
for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
MBB != E; ++MBB) {
- unsigned StartIdx = MIIndex;
+ MachineInstrIndex StartIdx = MIIndex;
// Insert an empty slot at the beginning of each block.
- MIIndex += InstrSlots::NUM;
+ MIIndex = getNextIndex(MIIndex);
i2miMap_.push_back(0);
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
@@ -285,47 +309,51 @@ void LiveIntervals::computeNumbering() {
if (I == MBB->getFirstTerminator()) {
// Leave a gap for before terminators, this is where we will point
// PHI kills.
+ MachineInstrIndex tGap(true, MIIndex);
bool inserted =
- terminatorGaps.insert(std::make_pair(&*MBB, MIIndex)).second;
+ terminatorGaps.insert(std::make_pair(&*MBB, tGap)).second;
assert(inserted &&
"Multiple 'first' terminators encountered during numbering.");
inserted = inserted; // Avoid compiler warning if assertions turned off.
i2miMap_.push_back(0);
- MIIndex += InstrSlots::NUM;
+ MIIndex = getNextIndex(MIIndex);
}
bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
assert(inserted && "multiple MachineInstr -> index mappings");
inserted = true;
i2miMap_.push_back(I);
- MIIndex += InstrSlots::NUM;
+ MIIndex = getNextIndex(MIIndex);
FunctionSize++;
// Insert max(1, numdefs) empty slots after every instruction.
unsigned Slots = I->getDesc().getNumDefs();
if (Slots == 0)
Slots = 1;
- MIIndex += InstrSlots::NUM * Slots;
- while (Slots--)
+ while (Slots--) {
+ MIIndex = getNextIndex(MIIndex);
i2miMap_.push_back(0);
+ }
+
}
if (MBB->getFirstTerminator() == MBB->end()) {
// Leave a gap for before terminators, this is where we will point
// PHI kills.
+ MachineInstrIndex tGap(true, MIIndex);
bool inserted =
- terminatorGaps.insert(std::make_pair(&*MBB, MIIndex)).second;
+ terminatorGaps.insert(std::make_pair(&*MBB, tGap)).second;
assert(inserted &&
"Multiple 'first' terminators encountered during numbering.");
inserted = inserted; // Avoid compiler warning if assertions turned off.
i2miMap_.push_back(0);
- MIIndex += InstrSlots::NUM;
+ MIIndex = getNextIndex(MIIndex);
}
// Set the MBB2IdxMap entry for this MBB.
- MBB2IdxMap[MBB->getNumber()] = std::make_pair(StartIdx, MIIndex - 1);
+ MBB2IdxMap[MBB->getNumber()] = std::make_pair(StartIdx, getPrevSlot(MIIndex));
Idx2MBBMap.push_back(std::make_pair(StartIdx, MBB));
}
@@ -340,9 +368,9 @@ void LiveIntervals::computeNumbering() {
// number, or our best guess at what it _should_ correspond to if the
// original instruction has been erased. This is either the following
// instruction or its predecessor.
- unsigned index = LI->start / InstrSlots::NUM;
- unsigned offset = LI->start % InstrSlots::NUM;
- if (offset == InstrSlots::LOAD) {
+ unsigned index = LI->start.getVecIndex();
+ MachineInstrIndex::Slot offset = LI->start.getSlot();
+ if (LI->start.isLoad()) {
std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), LI->start);
// Take the pair containing the index
@@ -351,29 +379,34 @@ void LiveIntervals::computeNumbering() {
LI->start = getMBBStartIdx(J->second);
} else {
- LI->start = mi2iMap_[OldI2MI[index]] + offset;
+ LI->start = MachineInstrIndex(
+ MachineInstrIndex(mi2iMap_[OldI2MI[index]]),
+ (MachineInstrIndex::Slot)offset);
}
// Remap the ending index in the same way that we remapped the start,
// except for the final step where we always map to the immediately
// following instruction.
- index = (LI->end - 1) / InstrSlots::NUM;
- offset = LI->end % InstrSlots::NUM;
- if (offset == InstrSlots::LOAD) {
+ index = (getPrevSlot(LI->end)).getVecIndex();
+ offset = LI->end.getSlot();
+ if (LI->end.isLoad()) {
// VReg dies at end of block.
std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), LI->end);
--I;
- LI->end = getMBBEndIdx(I->second) + 1;
+ LI->end = getNextSlot(getMBBEndIdx(I->second));
} else {
unsigned idx = index;
while (index < OldI2MI.size() && !OldI2MI[index]) ++index;
if (index != OldI2MI.size())
- LI->end = mi2iMap_[OldI2MI[index]] + (idx == index ? offset : 0);
+ LI->end =
+ MachineInstrIndex(mi2iMap_[OldI2MI[index]],
+ (idx == index ? offset : MachineInstrIndex::LOAD));
else
- LI->end = InstrSlots::NUM * i2miMap_.size();
+ LI->end =
+ MachineInstrIndex(MachineInstrIndex::NUM * i2miMap_.size());
}
}
@@ -385,9 +418,9 @@ void LiveIntervals::computeNumbering() {
// start indices above. VN's with special sentinel defs
// don't need to be remapped.
if (vni->isDefAccurate() && !vni->isUnused()) {
- unsigned index = vni->def / InstrSlots::NUM;
- unsigned offset = vni->def % InstrSlots::NUM;
- if (offset == InstrSlots::LOAD) {
+ unsigned index = vni->def.getVecIndex();
+ MachineInstrIndex::Slot offset = vni->def.getSlot();
+ if (vni->def.isLoad()) {
std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), vni->def);
// Take the pair containing the index
@@ -396,19 +429,17 @@ void LiveIntervals::computeNumbering() {
vni->def = getMBBStartIdx(J->second);
} else {
- vni->def = mi2iMap_[OldI2MI[index]] + offset;
+ vni->def = MachineInstrIndex(mi2iMap_[OldI2MI[index]], offset);
}
}
// Remap the VNInfo kill indices, which works the same as
// the end indices above.
for (size_t i = 0; i < vni->kills.size(); ++i) {
- unsigned killIdx = vni->kills[i].killIdx;
+ unsigned index = getPrevSlot(vni->kills[i]).getVecIndex();
+ MachineInstrIndex::Slot offset = vni->kills[i].getSlot();
- unsigned index = (killIdx - 1) / InstrSlots::NUM;
- unsigned offset = killIdx % InstrSlots::NUM;
-
- if (offset == InstrSlots::LOAD) {
+ if (vni->kills[i].isLoad()) {
assert("Value killed at a load slot.");
/*std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), vni->kills[i]);
@@ -416,15 +447,15 @@ void LiveIntervals::computeNumbering() {
vni->kills[i] = getMBBEndIdx(I->second);*/
} else {
- if (vni->kills[i].isPHIKill) {
+ if (vni->kills[i].isPHIIndex()) {
std::vector<IdxMBBPair>::const_iterator I =
- std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), index);
+ std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), vni->kills[i]);
--I;
- vni->kills[i].killIdx = terminatorGaps[I->second];
+ vni->kills[i] = terminatorGaps[I->second];
} else {
assert(OldI2MI[index] != 0 &&
"Kill refers to instruction not present in index maps.");
- vni->kills[i].killIdx = mi2iMap_[OldI2MI[index]] + offset;
+ vni->kills[i] = MachineInstrIndex(mi2iMap_[OldI2MI[index]], offset);
}
/*
@@ -454,18 +485,18 @@ void LiveIntervals::scaleNumbering(int factor) {
Idx2MBBMap.clear();
for (MachineFunction::iterator MBB = mf_->begin(), MBBE = mf_->end();
MBB != MBBE; ++MBB) {
- std::pair<unsigned, unsigned> &mbbIndices = MBB2IdxMap[MBB->getNumber()];
- mbbIndices.first = InstrSlots::scale(mbbIndices.first, factor);
- mbbIndices.second = InstrSlots::scale(mbbIndices.second, factor);
+ std::pair<MachineInstrIndex, MachineInstrIndex> &mbbIndices = MBB2IdxMap[MBB->getNumber()];
+ mbbIndices.first = mbbIndices.first.scale(factor);
+ mbbIndices.second = mbbIndices.second.scale(factor);
Idx2MBBMap.push_back(std::make_pair(mbbIndices.first, MBB));
}
std::sort(Idx2MBBMap.begin(), Idx2MBBMap.end(), Idx2MBBCompare());
// Scale terminator gaps.
- for (DenseMap<MachineBasicBlock*, unsigned>::iterator
+ for (DenseMap<MachineBasicBlock*, MachineInstrIndex>::iterator
TGI = terminatorGaps.begin(), TGE = terminatorGaps.end();
TGI != TGE; ++TGI) {
- terminatorGaps[TGI->first] = InstrSlots::scale(TGI->second, factor);
+ terminatorGaps[TGI->first] = TGI->second.scale(factor);
}
// Scale the intervals.
@@ -475,19 +506,20 @@ void LiveIntervals::scaleNumbering(int factor) {
// Scale MachineInstrs.
Mi2IndexMap oldmi2iMap = mi2iMap_;
- unsigned highestSlot = 0;
+ MachineInstrIndex highestSlot;
for (Mi2IndexMap::iterator MI = oldmi2iMap.begin(), ME = oldmi2iMap.end();
MI != ME; ++MI) {
- unsigned newSlot = InstrSlots::scale(MI->second, factor);
+ MachineInstrIndex newSlot = MI->second.scale(factor);
mi2iMap_[MI->first] = newSlot;
highestSlot = std::max(highestSlot, newSlot);
}
+ unsigned highestVIndex = highestSlot.getVecIndex();
i2miMap_.clear();
- i2miMap_.resize(highestSlot + 1);
+ i2miMap_.resize(highestVIndex + 1);
for (Mi2IndexMap::iterator MI = mi2iMap_.begin(), ME = mi2iMap_.end();
MI != ME; ++MI) {
- i2miMap_[MI->second] = const_cast<MachineInstr *>(MI->first);
+ i2miMap_[MI->second.getVecIndex()] = const_cast<MachineInstr *>(MI->first);
}
}
@@ -508,6 +540,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
processImplicitDefs();
computeNumbering();
computeIntervals();
+ performEarlyCoalescing();
numIntervals += getNumIntervals();
@@ -523,6 +556,10 @@ void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
OS << "\n";
}
+ printInstrs(OS);
+}
+
+void LiveIntervals::printInstrs(raw_ostream &OS) const {
OS << "********** MACHINEINSTRS **********\n";
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
@@ -535,18 +572,22 @@ void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
}
}
+void LiveIntervals::dumpInstrs() const {
+ printInstrs(errs());
+}
+
/// conflictsWithPhysRegDef - Returns true if the specified register
/// is defined during the duration of the specified interval.
bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li,
VirtRegMap &vrm, unsigned reg) {
for (LiveInterval::Ranges::const_iterator
I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
- for (unsigned index = getBaseIndex(I->start),
- end = getBaseIndex(I->end-1) + InstrSlots::NUM; index != end;
- index += InstrSlots::NUM) {
+ for (MachineInstrIndex index = getBaseIndex(I->start),
+ end = getNextIndex(getBaseIndex(getPrevSlot(I->end))); index != end;
+ index = getNextIndex(index)) {
// skip deleted instructions
while (index != end && !getInstructionFromIndex(index))
- index += InstrSlots::NUM;
+ index = getNextIndex(index);
if (index == end) break;
MachineInstr *MI = getInstructionFromIndex(index);
@@ -582,16 +623,16 @@ bool LiveIntervals::conflictsWithPhysRegRef(LiveInterval &li,
SmallPtrSet<MachineInstr*,32> &JoinedCopies) {
for (LiveInterval::Ranges::const_iterator
I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
- for (unsigned index = getBaseIndex(I->start),
- end = getBaseIndex(I->end-1) + InstrSlots::NUM; index != end;
- index += InstrSlots::NUM) {
+ for (MachineInstrIndex index = getBaseIndex(I->start),
+ end = getNextIndex(getBaseIndex(getPrevSlot(I->end))); index != end;
+ index = getNextIndex(index)) {
// Skip deleted instructions.
MachineInstr *MI = 0;
while (index != end) {
MI = getInstructionFromIndex(index);
if (MI)
break;
- index += InstrSlots::NUM;
+ index = getNextIndex(index);
}
if (index == end) break;
@@ -615,22 +656,24 @@ bool LiveIntervals::conflictsWithPhysRegRef(LiveInterval &li,
return false;
}
-
-void LiveIntervals::printRegName(unsigned reg) const {
+#ifndef NDEBUG
+static void printRegName(unsigned reg, const TargetRegisterInfo* tri_) {
if (TargetRegisterInfo::isPhysicalRegister(reg))
errs() << tri_->getName(reg);
else
errs() << "%reg" << reg;
}
+#endif
void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
MachineBasicBlock::iterator mi,
- unsigned MIIdx, MachineOperand& MO,
+ MachineInstrIndex MIIdx,
+ MachineOperand& MO,
unsigned MOIdx,
LiveInterval &interval) {
DEBUG({
errs() << "\t\tregister: ";
- printRegName(interval.reg);
+ printRegName(interval.reg, tri_);
});
// Virtual registers may be defined multiple times (due to phi
@@ -640,8 +683,9 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
if (interval.empty()) {
// Get the Idx of the defining instructions.
- unsigned defIndex = getDefIndex(MIIdx);
- // Earlyclobbers move back one.
+ MachineInstrIndex defIndex = getDefIndex(MIIdx);
+ // Earlyclobbers move back one, so that they overlap the live range
+ // of inputs.
if (MO.isEarlyClobber())
defIndex = getUseIndex(MIIdx);
VNInfo *ValNo;
@@ -663,11 +707,16 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// will be a single kill, in MBB, which comes after the definition.
if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
// FIXME: what about dead vars?
- unsigned killIdx;
+ MachineInstrIndex killIdx;
if (vi.Kills[0] != mi)
- killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
+ killIdx = getNextSlot(getUseIndex(getInstructionIndex(vi.Kills[0])));
+ else if (MO.isEarlyClobber())
+ // Earlyclobbers that die in this instruction move up one extra, to
+ // compensate for having the starting point moved back one. This
+ // gets them to overlap the live range of other outputs.
+ killIdx = getNextSlot(getNextSlot(defIndex));
else
- killIdx = defIndex+1;
+ killIdx = getNextSlot(defIndex);
// If the kill happens after the definition, we have an intra-block
// live range.
@@ -677,7 +726,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
LiveRange LR(defIndex, killIdx, ValNo);
interval.addRange(LR);
DEBUG(errs() << " +" << LR << "\n");
- interval.addKill(ValNo, killIdx, false);
+ ValNo->addKill(killIdx);
return;
}
}
@@ -686,7 +735,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// of the defining block, potentially live across some blocks, then is
// live into some number of blocks, but gets killed. Start by adding a
// range that goes from this definition to the end of the defining block.
- LiveRange NewLR(defIndex, getMBBEndIdx(mbb)+1, ValNo);
+ LiveRange NewLR(defIndex, getNextSlot(getMBBEndIdx(mbb)), ValNo);
DEBUG(errs() << " +" << NewLR);
interval.addRange(NewLR);
@@ -696,7 +745,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
E = vi.AliveBlocks.end(); I != E; ++I) {
LiveRange LR(getMBBStartIdx(*I),
- getMBBEndIdx(*I)+1, // MBB ends at -1.
+ getNextSlot(getMBBEndIdx(*I)), // MBB ends at -1.
ValNo);
interval.addRange(LR);
DEBUG(errs() << " +" << LR);
@@ -706,11 +755,11 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// block to the 'use' slot of the killing instruction.
for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
MachineInstr *Kill = vi.Kills[i];
- unsigned killIdx = getUseIndex(getInstructionIndex(Kill))+1;
- LiveRange LR(getMBBStartIdx(Kill->getParent()),
- killIdx, ValNo);
+ MachineInstrIndex killIdx =
+ getNextSlot(getUseIndex(getInstructionIndex(Kill)));
+ LiveRange LR(getMBBStartIdx(Kill->getParent()), killIdx, ValNo);
interval.addRange(LR);
- interval.addKill(ValNo, killIdx, false);
+ ValNo->addKill(killIdx);
DEBUG(errs() << " +" << LR);
}
@@ -726,12 +775,13 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// need to take the LiveRegion that defines this register and split it
// into two values.
assert(interval.containsOneValue());
- unsigned DefIndex = getDefIndex(interval.getValNumInfo(0)->def);
- unsigned RedefIndex = getDefIndex(MIIdx);
+ MachineInstrIndex DefIndex = getDefIndex(interval.getValNumInfo(0)->def);
+ MachineInstrIndex RedefIndex = getDefIndex(MIIdx);
if (MO.isEarlyClobber())
RedefIndex = getUseIndex(MIIdx);
- const LiveRange *OldLR = interval.getLiveRangeContaining(RedefIndex-1);
+ const LiveRange *OldLR =
+ interval.getLiveRangeContaining(getPrevSlot(RedefIndex));
VNInfo *OldValNo = OldLR->valno;
// Delete the initial value, which should be short and continuous,
@@ -759,12 +809,15 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
LiveRange LR(DefIndex, RedefIndex, ValNo);
DEBUG(errs() << " replace range with " << LR);
interval.addRange(LR);
- interval.addKill(ValNo, RedefIndex, false);
+ ValNo->addKill(RedefIndex);
// If this redefinition is dead, we need to add a dummy unit live
// range covering the def slot.
if (MO.isDead())
- interval.addRange(LiveRange(RedefIndex, RedefIndex+1, OldValNo));
+ interval.addRange(
+ LiveRange(RedefIndex, MO.isEarlyClobber() ?
+ getNextSlot(getNextSlot(RedefIndex)) :
+ getNextSlot(RedefIndex), OldValNo));
DEBUG({
errs() << " RESULT: ";
@@ -775,14 +828,13 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// first redefinition of the vreg that we have seen, go back and change
// the live range in the PHI block to be a different value number.
if (interval.containsOneValue()) {
- assert(vi.Kills.size() == 1 &&
- "PHI elimination vreg should have one kill, the PHI itself!");
-
// Remove the old range that we now know has an incorrect number.
VNInfo *VNI = interval.getValNumInfo(0);
MachineInstr *Killer = vi.Kills[0];
- unsigned Start = getMBBStartIdx(Killer->getParent());
- unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
+ phiJoinCopies.push_back(Killer);
+ MachineInstrIndex Start = getMBBStartIdx(Killer->getParent());
+ MachineInstrIndex End =
+ getNextSlot(getUseIndex(getInstructionIndex(Killer)));
DEBUG({
errs() << " Removing [" << Start << "," << End << "] from: ";
interval.print(errs(), tri_);
@@ -790,9 +842,9 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
});
interval.removeRange(Start, End);
assert(interval.ranges.size() == 1 &&
- "newly discovered PHI interval has >1 ranges.");
- MachineBasicBlock *killMBB = getMBBFromIndex(interval.endNumber());
- interval.addKill(VNI, terminatorGaps[killMBB], true);
+ "Newly discovered PHI interval has >1 ranges.");
+ MachineBasicBlock *killMBB = getMBBFromIndex(interval.endIndex());
+ VNI->addKill(terminatorGaps[killMBB]);
VNI->setHasPHIKill(true);
DEBUG({
errs() << " RESULT: ";
@@ -802,11 +854,12 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// Replace the interval with one of a NEW value number. Note that this
// value number isn't actually defined by an instruction, weird huh? :)
LiveRange LR(Start, End,
- interval.getNextValue(mbb->getNumber(), 0, false, VNInfoAllocator));
+ interval.getNextValue(MachineInstrIndex(mbb->getNumber()),
+ 0, false, VNInfoAllocator));
LR.valno->setIsPHIDef(true);
DEBUG(errs() << " replace range with " << LR);
interval.addRange(LR);
- interval.addKill(LR.valno, End, false);
+ LR.valno->addKill(End);
DEBUG({
errs() << " RESULT: ";
interval.print(errs(), tri_);
@@ -816,10 +869,10 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
// In the case of PHI elimination, each variable definition is only
// live until the end of the block. We've already taken care of the
// rest of the live range.
- unsigned defIndex = getDefIndex(MIIdx);
+ MachineInstrIndex defIndex = getDefIndex(MIIdx);
if (MO.isEarlyClobber())
defIndex = getUseIndex(MIIdx);
-
+
VNInfo *ValNo;
MachineInstr *CopyMI = NULL;
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
@@ -830,10 +883,10 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
CopyMI = mi;
ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator);
- unsigned killIndex = getMBBEndIdx(mbb) + 1;
+ MachineInstrIndex killIndex = getNextSlot(getMBBEndIdx(mbb));
LiveRange LR(defIndex, killIndex, ValNo);
interval.addRange(LR);
- interval.addKill(ValNo, terminatorGaps[mbb], true);
+ ValNo->addKill(terminatorGaps[mbb]);
ValNo->setHasPHIKill(true);
DEBUG(errs() << " +" << LR);
}
@@ -844,7 +897,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator mi,
- unsigned MIIdx,
+ MachineInstrIndex MIIdx,
MachineOperand& MO,
LiveInterval &interval,
MachineInstr *CopyMI) {
@@ -852,36 +905,41 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
// lifetime must end somewhere in its defining basic block.
DEBUG({
errs() << "\t\tregister: ";
- printRegName(interval.reg);
+ printRegName(interval.reg, tri_);
});
- unsigned baseIndex = MIIdx;
- unsigned start = getDefIndex(baseIndex);
+ MachineInstrIndex baseIndex = MIIdx;
+ MachineInstrIndex start = getDefIndex(baseIndex);
// Earlyclobbers move back one.
if (MO.isEarlyClobber())
start = getUseIndex(MIIdx);
- unsigned end = start;
+ MachineInstrIndex end = start;
// If it is not used after definition, it is considered dead at
// the instruction defining it. Hence its interval is:
// [defSlot(def), defSlot(def)+1)
+ // For earlyclobbers, the defSlot was pushed back one; the extra
+ // advance below compensates.
if (MO.isDead()) {
DEBUG(errs() << " dead");
- end = start + 1;
+ if (MO.isEarlyClobber())
+ end = getNextSlot(getNextSlot(start));
+ else
+ end = getNextSlot(start);
goto exit;
}
// If it is not dead on definition, it must be killed by a
// subsequent instruction. Hence its interval is:
// [defSlot(def), useSlot(kill)+1)
- baseIndex += InstrSlots::NUM;
+ baseIndex = getNextIndex(baseIndex);
while (++mi != MBB->end()) {
- while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
+ while (baseIndex.getVecIndex() < i2miMap_.size() &&
getInstructionFromIndex(baseIndex) == 0)
- baseIndex += InstrSlots::NUM;
+ baseIndex = getNextIndex(baseIndex);
if (mi->killsRegister(interval.reg, tri_)) {
DEBUG(errs() << " killed");
- end = getUseIndex(baseIndex) + 1;
+ end = getNextSlot(getUseIndex(baseIndex));
goto exit;
} else {
int DefIdx = mi->findRegisterDefOperandIdx(interval.reg, false, tri_);
@@ -897,20 +955,20 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
// it. Hence its interval is:
// [defSlot(def), defSlot(def)+1)
DEBUG(errs() << " dead");
- end = start + 1;
+ end = getNextSlot(start);
}
goto exit;
}
}
- baseIndex += InstrSlots::NUM;
+ baseIndex = getNextIndex(baseIndex);
}
// The only case we should have a dead physreg here without a killing or
// instruction where we know it's dead is if it is live-in to the function
// and never used. Another possible case is the implicit use of the
// physical register has been deleted by two-address pass.
- end = start + 1;
+ end = getNextSlot(start);
exit:
assert(start < end && "did not find end of interval?");
@@ -924,13 +982,13 @@ exit:
ValNo->setHasRedefByEC(true);
LiveRange LR(start, end, ValNo);
interval.addRange(LR);
- interval.addKill(LR.valno, end, false);
+ LR.valno->addKill(end);
DEBUG(errs() << " +" << LR << '\n');
}
void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI,
- unsigned MIIdx,
+ MachineInstrIndex MIIdx,
MachineOperand& MO,
unsigned MOIdx) {
if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
@@ -957,28 +1015,28 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
}
void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
- unsigned MIIdx,
+ MachineInstrIndex MIIdx,
LiveInterval &interval, bool isAlias) {
DEBUG({
errs() << "\t\tlivein register: ";
- printRegName(interval.reg);
+ printRegName(interval.reg, tri_);
});
// Look for kills, if it reaches a def before it's killed, then it shouldn't
// be considered a livein.
MachineBasicBlock::iterator mi = MBB->begin();
- unsigned baseIndex = MIIdx;
- unsigned start = baseIndex;
- while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
+ MachineInstrIndex baseIndex = MIIdx;
+ MachineInstrIndex start = baseIndex;
+ while (baseIndex.getVecIndex() < i2miMap_.size() &&
getInstructionFromIndex(baseIndex) == 0)
- baseIndex += InstrSlots::NUM;
- unsigned end = baseIndex;
+ baseIndex = getNextIndex(baseIndex);
+ MachineInstrIndex end = baseIndex;
bool SeenDefUse = false;
while (mi != MBB->end()) {
if (mi->killsRegister(interval.reg, tri_)) {
DEBUG(errs() << " killed");
- end = getUseIndex(baseIndex) + 1;
+ end = getNextSlot(getUseIndex(baseIndex));
SeenDefUse = true;
break;
} else if (mi->modifiesRegister(interval.reg, tri_)) {
@@ -987,17 +1045,17 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
// it. Hence its interval is:
// [defSlot(def), defSlot(def)+1)
DEBUG(errs() << " dead");
- end = getDefIndex(start) + 1;
+ end = getNextSlot(getDefIndex(start));
SeenDefUse = true;
break;
}
- baseIndex += InstrSlots::NUM;
+ baseIndex = getNextIndex(baseIndex);
++mi;
if (mi != MBB->end()) {
- while (baseIndex / InstrSlots::NUM < i2miMap_.size() &&
+ while (baseIndex.getVecIndex() < i2miMap_.size() &&
getInstructionFromIndex(baseIndex) == 0)
- baseIndex += InstrSlots::NUM;
+ baseIndex = getNextIndex(baseIndex);
}
}
@@ -1005,7 +1063,7 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
if (!SeenDefUse) {
if (isAlias) {
DEBUG(errs() << " dead");
- end = getDefIndex(MIIdx) + 1;
+ end = getNextSlot(getDefIndex(MIIdx));
} else {
DEBUG(errs() << " live through");
end = baseIndex;
@@ -1013,15 +1071,142 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
}
VNInfo *vni =
- interval.getNextValue(MBB->getNumber(), 0, false, VNInfoAllocator);
+ interval.getNextValue(MachineInstrIndex(MBB->getNumber()),
+ 0, false, VNInfoAllocator);
vni->setIsPHIDef(true);
LiveRange LR(start, end, vni);
interval.addRange(LR);
- interval.addKill(LR.valno, end, false);
+ LR.valno->addKill(end);
DEBUG(errs() << " +" << LR << '\n');
}
+bool
+LiveIntervals::isProfitableToCoalesce(LiveInterval &DstInt, LiveInterval &SrcInt,
+ SmallVector<MachineInstr*,16> &IdentCopies,
+ SmallVector<MachineInstr*,16> &OtherCopies) {
+ bool HaveConflict = false;
+ unsigned NumIdent = 0;
+ for (MachineRegisterInfo::def_iterator ri = mri_->def_begin(SrcInt.reg),
+ re = mri_->def_end(); ri != re; ++ri) {
+ MachineInstr *MI = &*ri;
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+ if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
+ return false;
+ if (SrcReg != DstInt.reg) {
+ OtherCopies.push_back(MI);
+ HaveConflict |= DstInt.liveAt(getInstructionIndex(MI));
+ } else {
+ IdentCopies.push_back(MI);
+ ++NumIdent;
+ }
+ }
+
+ if (!HaveConflict)
+ return false; // Let coalescer handle it
+ return IdentCopies.size() > OtherCopies.size();
+}
+
+void LiveIntervals::performEarlyCoalescing() {
+ if (!EarlyCoalescing)
+ return;
+
+ /// Perform early coalescing: eliminate copies which feed into phi joins
+ /// and whose sources are defined by the phi joins.
+ for (unsigned i = 0, e = phiJoinCopies.size(); i != e; ++i) {
+ MachineInstr *Join = phiJoinCopies[i];
+ if (CoalescingLimit != -1 && (int)numCoalescing == CoalescingLimit)
+ break;
+
+ unsigned PHISrc, PHIDst, SrcSubReg, DstSubReg;
+ bool isMove= tii_->isMoveInstr(*Join, PHISrc, PHIDst, SrcSubReg, DstSubReg);
+#ifndef NDEBUG
+ assert(isMove && "PHI join instruction must be a move!");
+#else
+ isMove = isMove;
+#endif
+
+ LiveInterval &DstInt = getInterval(PHIDst);
+ LiveInterval &SrcInt = getInterval(PHISrc);
+ SmallVector<MachineInstr*, 16> IdentCopies;
+ SmallVector<MachineInstr*, 16> OtherCopies;
+ if (!isProfitableToCoalesce(DstInt, SrcInt, IdentCopies, OtherCopies))
+ continue;
+
+ DEBUG(errs() << "PHI Join: " << *Join);
+ assert(DstInt.containsOneValue() && "PHI join should have just one val#!");
+ VNInfo *VNI = DstInt.getValNumInfo(0);
+
+ // Change the non-identity copies to directly target the phi destination.
+ for (unsigned i = 0, e = OtherCopies.size(); i != e; ++i) {
+ MachineInstr *PHICopy = OtherCopies[i];
+ DEBUG(errs() << "Moving: " << *PHICopy);
+
+ MachineInstrIndex MIIndex = getInstructionIndex(PHICopy);
+ MachineInstrIndex DefIndex = getDefIndex(MIIndex);
+ LiveRange *SLR = SrcInt.getLiveRangeContaining(DefIndex);
+ MachineInstrIndex StartIndex = SLR->start;
+ MachineInstrIndex EndIndex = SLR->end;
+
+ // Delete val# defined by the now identity copy and add the range from
+ // beginning of the mbb to the end of the range.
+ SrcInt.removeValNo(SLR->valno);
+ DEBUG(errs() << " added range [" << StartIndex << ','
+ << EndIndex << "] to reg" << DstInt.reg << '\n');
+ if (DstInt.liveAt(StartIndex))
+ DstInt.removeRange(StartIndex, EndIndex);
+ VNInfo *NewVNI = DstInt.getNextValue(DefIndex, PHICopy, true,
+ VNInfoAllocator);
+ NewVNI->setHasPHIKill(true);
+ DstInt.addRange(LiveRange(StartIndex, EndIndex, NewVNI));
+ for (unsigned j = 0, ee = PHICopy->getNumOperands(); j != ee; ++j) {
+ MachineOperand &MO = PHICopy->getOperand(j);
+ if (!MO.isReg() || MO.getReg() != PHISrc)
+ continue;
+ MO.setReg(PHIDst);
+ }
+ }
+
+ // Now let's eliminate all the would-be identity copies.
+ for (unsigned i = 0, e = IdentCopies.size(); i != e; ++i) {
+ MachineInstr *PHICopy = IdentCopies[i];
+ DEBUG(errs() << "Coalescing: " << *PHICopy);
+
+ MachineInstrIndex MIIndex = getInstructionIndex(PHICopy);
+ MachineInstrIndex DefIndex = getDefIndex(MIIndex);
+ LiveRange *SLR = SrcInt.getLiveRangeContaining(DefIndex);
+ MachineInstrIndex StartIndex = SLR->start;
+ MachineInstrIndex EndIndex = SLR->end;
+
+ // Delete val# defined by the now identity copy and add the range from
+ // beginning of the mbb to the end of the range.
+ SrcInt.removeValNo(SLR->valno);
+ RemoveMachineInstrFromMaps(PHICopy);
+ PHICopy->eraseFromParent();
+ DEBUG(errs() << " added range [" << StartIndex << ','
+ << EndIndex << "] to reg" << DstInt.reg << '\n');
+ DstInt.addRange(LiveRange(StartIndex, EndIndex, VNI));
+ }
+
+ // Remove the phi join and update the phi block liveness.
+ MachineInstrIndex MIIndex = getInstructionIndex(Join);
+ MachineInstrIndex UseIndex = getUseIndex(MIIndex);
+ MachineInstrIndex DefIndex = getDefIndex(MIIndex);
+ LiveRange *SLR = SrcInt.getLiveRangeContaining(UseIndex);
+ LiveRange *DLR = DstInt.getLiveRangeContaining(DefIndex);
+ DLR->valno->setCopy(0);
+ DLR->valno->setIsDefAccurate(false);
+ DstInt.addRange(LiveRange(SLR->start, SLR->end, DLR->valno));
+ SrcInt.removeRange(SLR->start, SLR->end);
+ assert(SrcInt.empty());
+ removeInterval(PHISrc);
+ RemoveMachineInstrFromMaps(Join);
+ Join->eraseFromParent();
+
+ ++numCoalescing;
+ }
+}
+
/// computeIntervals - computes the live intervals for virtual
/// registers. for some ordering of the machine instructions [1,N] a
/// live interval is an interval [i, j) where 1 <= i <= j < N for
@@ -1036,7 +1221,7 @@ void LiveIntervals::computeIntervals() {
MBBI != E; ++MBBI) {
MachineBasicBlock *MBB = MBBI;
// Track the index of the current machine instr.
- unsigned MIIndex = getMBBStartIdx(MBB);
+ MachineInstrIndex MIIndex = getMBBStartIdx(MBB);
DEBUG(errs() << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
@@ -1053,9 +1238,9 @@ void LiveIntervals::computeIntervals() {
}
// Skip over empty initial indices.
- while (MIIndex / InstrSlots::NUM < i2miMap_.size() &&
+ while (MIIndex.getVecIndex() < i2miMap_.size() &&
getInstructionFromIndex(MIIndex) == 0)
- MIIndex += InstrSlots::NUM;
+ MIIndex = getNextIndex(MIIndex);
for (; MI != miEnd; ++MI) {
DEBUG(errs() << MIIndex << "\t" << *MI);
@@ -1077,12 +1262,14 @@ void LiveIntervals::computeIntervals() {
unsigned Slots = MI->getDesc().getNumDefs();
if (Slots == 0)
Slots = 1;
- MIIndex += InstrSlots::NUM * Slots;
+
+ while (Slots--)
+ MIIndex = getNextIndex(MIIndex);
// Skip over empty indices.
- while (MIIndex / InstrSlots::NUM < i2miMap_.size() &&
+ while (MIIndex.getVecIndex() < i2miMap_.size() &&
getInstructionFromIndex(MIIndex) == 0)
- MIIndex += InstrSlots::NUM;
+ MIIndex = getNextIndex(MIIndex);
}
}
@@ -1095,7 +1282,8 @@ void LiveIntervals::computeIntervals() {
}
}
-bool LiveIntervals::findLiveInMBBs(unsigned Start, unsigned End,
+bool LiveIntervals::findLiveInMBBs(
+ MachineInstrIndex Start, MachineInstrIndex End,
SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), Start);
@@ -1111,7 +1299,8 @@ bool LiveIntervals::findLiveInMBBs(unsigned Start, unsigned End,
return ResVal;
}
-bool LiveIntervals::findReachableMBBs(unsigned Start, unsigned End,
+bool LiveIntervals::findReachableMBBs(
+ MachineInstrIndex Start, MachineInstrIndex End,
SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), Start);
@@ -1203,8 +1392,8 @@ unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
/// isValNoAvailableAt - Return true if the val# of the specified interval
/// which reaches the given instruction also reaches the specified use index.
bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
- unsigned UseIdx) const {
- unsigned Index = getInstructionIndex(MI);
+ MachineInstrIndex UseIdx) const {
+ MachineInstrIndex Index = getInstructionIndex(MI);
VNInfo *ValNo = li.FindLiveRangeContaining(Index)->valno;
LiveInterval::const_iterator UI = li.FindLiveRangeContaining(UseIdx);
return UI != li.end() && UI->valno == ValNo;
@@ -1251,12 +1440,12 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
// If the instruction accesses memory and the memory could be non-constant,
// assume the instruction is not rematerializable.
- for (std::list<MachineMemOperand>::const_iterator
- I = MI->memoperands_begin(), E = MI->memoperands_end(); I != E; ++I){
- const MachineMemOperand &MMO = *I;
- if (MMO.isVolatile() || MMO.isStore())
+ for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
+ E = MI->memoperands_end(); I != E; ++I){
+ const MachineMemOperand *MMO = *I;
+ if (MMO->isVolatile() || MMO->isStore())
return false;
- const Value *V = MMO.getValue();
+ const Value *V = MMO->getValue();
if (!V)
return false;
if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
@@ -1314,7 +1503,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
for (MachineRegisterInfo::use_iterator ri = mri_->use_begin(li.reg),
re = mri_->use_end(); ri != re; ++ri) {
MachineInstr *UseMI = &*ri;
- unsigned UseIdx = getInstructionIndex(UseMI);
+ MachineInstrIndex UseIdx = getInstructionIndex(UseMI);
if (li.FindLiveRangeContaining(UseIdx)->valno != ValNo)
continue;
if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
@@ -1399,7 +1588,7 @@ static bool FilterFoldedOps(MachineInstr *MI,
/// returns true.
bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
VirtRegMap &vrm, MachineInstr *DefMI,
- unsigned InstrIdx,
+ MachineInstrIndex InstrIdx,
SmallVector<unsigned, 2> &Ops,
bool isSS, int Slot, unsigned Reg) {
// If it is an implicit def instruction, just delete it.
@@ -1438,7 +1627,7 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
vrm.transferRestorePts(MI, fmi);
vrm.transferEmergencySpills(MI, fmi);
mi2iMap_.erase(MI);
- i2miMap_[InstrIdx /InstrSlots::NUM] = fmi;
+ i2miMap_[InstrIdx.getVecIndex()] = fmi;
mi2iMap_[fmi] = InstrIdx;
MI = MBB.insert(MBB.erase(MI), fmi);
++numFolds;
@@ -1511,7 +1700,8 @@ void LiveIntervals::rewriteImplicitOps(const LiveInterval &li,
/// for addIntervalsForSpills to rewrite uses / defs for the given live range.
bool LiveIntervals::
rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
- bool TrySplit, unsigned index, unsigned end, MachineInstr *MI,
+ bool TrySplit, MachineInstrIndex index, MachineInstrIndex end,
+ MachineInstr *MI,
MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI,
unsigned Slot, int LdSlot,
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
@@ -1687,13 +1877,14 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
if (HasUse) {
if (CreatedNewVReg) {
- LiveRange LR(getLoadIndex(index), getUseIndex(index)+1,
- nI.getNextValue(0, 0, false, VNInfoAllocator));
+ LiveRange LR(getLoadIndex(index), getNextSlot(getUseIndex(index)),
+ nI.getNextValue(MachineInstrIndex(), 0, false,
+ VNInfoAllocator));
DEBUG(errs() << " +" << LR);
nI.addRange(LR);
} else {
// Extend the split live interval to this def / use.
- unsigned End = getUseIndex(index)+1;
+ MachineInstrIndex End = getNextSlot(getUseIndex(index));
LiveRange LR(nI.ranges[nI.ranges.size()-1].end, End,
nI.getValNumInfo(nI.getNumValNums()-1));
DEBUG(errs() << " +" << LR);
@@ -1702,7 +1893,8 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
}
if (HasDef) {
LiveRange LR(getDefIndex(index), getStoreIndex(index),
- nI.getNextValue(0, 0, false, VNInfoAllocator));
+ nI.getNextValue(MachineInstrIndex(), 0, false,
+ VNInfoAllocator));
DEBUG(errs() << " +" << LR);
nI.addRange(LR);
}
@@ -1717,13 +1909,14 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
}
bool LiveIntervals::anyKillInMBBAfterIdx(const LiveInterval &li,
const VNInfo *VNI,
- MachineBasicBlock *MBB, unsigned Idx) const {
- unsigned End = getMBBEndIdx(MBB);
+ MachineBasicBlock *MBB,
+ MachineInstrIndex Idx) const {
+ MachineInstrIndex End = getMBBEndIdx(MBB);
for (unsigned j = 0, ee = VNI->kills.size(); j != ee; ++j) {
- if (VNI->kills[j].isPHIKill)
+ if (VNI->kills[j].isPHIIndex())
continue;
- unsigned KillIdx = VNI->kills[j].killIdx;
+ MachineInstrIndex KillIdx = VNI->kills[j];
if (KillIdx > Idx && KillIdx < End)
return true;
}
@@ -1734,11 +1927,11 @@ bool LiveIntervals::anyKillInMBBAfterIdx(const LiveInterval &li,
/// during spilling.
namespace {
struct RewriteInfo {
- unsigned Index;
+ MachineInstrIndex Index;
MachineInstr *MI;
bool HasUse;
bool HasDef;
- RewriteInfo(unsigned i, MachineInstr *mi, bool u, bool d)
+ RewriteInfo(MachineInstrIndex i, MachineInstr *mi, bool u, bool d)
: Index(i), MI(mi), HasUse(u), HasDef(d) {}
};
@@ -1767,8 +1960,8 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
std::vector<LiveInterval*> &NewLIs) {
bool AllCanFold = true;
unsigned NewVReg = 0;
- unsigned start = getBaseIndex(I->start);
- unsigned end = getBaseIndex(I->end-1) + InstrSlots::NUM;
+ MachineInstrIndex start = getBaseIndex(I->start);
+ MachineInstrIndex end = getNextIndex(getBaseIndex(getPrevSlot(I->end)));
// First collect all the def / use in this live range that will be rewritten.
// Make sure they are sorted according to instruction index.
@@ -1779,7 +1972,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
MachineOperand &O = ri.getOperand();
++ri;
assert(!O.isImplicit() && "Spilling register that's used as implicit use?");
- unsigned index = getInstructionIndex(MI);
+ MachineInstrIndex index = getInstructionIndex(MI);
if (index < start || index >= end)
continue;
@@ -1803,7 +1996,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
for (unsigned i = 0, e = RewriteMIs.size(); i != e; ) {
RewriteInfo &rwi = RewriteMIs[i];
++i;
- unsigned index = rwi.Index;
+ MachineInstrIndex index = rwi.Index;
bool MIHasUse = rwi.HasUse;
bool MIHasDef = rwi.HasDef;
MachineInstr *MI = rwi.MI;
@@ -1889,7 +2082,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
HasKill = anyKillInMBBAfterIdx(li, I->valno, MBB, getDefIndex(index));
else {
// If this is a two-address code, then this index starts a new VNInfo.
- const VNInfo *VNI = li.findDefinedVNInfo(getDefIndex(index));
+ const VNInfo *VNI = li.findDefinedVNInfoForRegInt(getDefIndex(index));
if (VNI)
HasKill = anyKillInMBBAfterIdx(li, VNI, MBB, getDefIndex(index));
}
@@ -1902,7 +2095,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
SpillIdxes.insert(std::make_pair(MBBId, S));
} else if (SII->second.back().vreg != NewVReg) {
SII->second.push_back(SRInfo(index, NewVReg, true));
- } else if ((int)index > SII->second.back().index) {
+ } else if (index > SII->second.back().index) {
// If there is an earlier def and this is a two-address
// instruction, then it's not possible to fold the store (which
// would also fold the load).
@@ -1913,7 +2106,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
SpillMBBs.set(MBBId);
} else if (SII != SpillIdxes.end() &&
SII->second.back().vreg == NewVReg &&
- (int)index > SII->second.back().index) {
+ index > SII->second.back().index) {
// There is an earlier def that's not killed (must be two-address).
// The spill is no longer needed.
SII->second.pop_back();
@@ -1930,7 +2123,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
SpillIdxes.find(MBBId);
if (SII != SpillIdxes.end() &&
SII->second.back().vreg == NewVReg &&
- (int)index > SII->second.back().index)
+ index > SII->second.back().index)
// Use(s) following the last def, it's not safe to fold the spill.
SII->second.back().canFold = false;
DenseMap<unsigned, std::vector<SRInfo> >::iterator RII =
@@ -1964,8 +2157,8 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
}
}
-bool LiveIntervals::alsoFoldARestore(int Id, int index, unsigned vr,
- BitVector &RestoreMBBs,
+bool LiveIntervals::alsoFoldARestore(int Id, MachineInstrIndex index,
+ unsigned vr, BitVector &RestoreMBBs,
DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
if (!RestoreMBBs[Id])
return false;
@@ -1978,15 +2171,15 @@ bool LiveIntervals::alsoFoldARestore(int Id, int index, unsigned vr,
return false;
}
-void LiveIntervals::eraseRestoreInfo(int Id, int index, unsigned vr,
- BitVector &RestoreMBBs,
+void LiveIntervals::eraseRestoreInfo(int Id, MachineInstrIndex index,
+ unsigned vr, BitVector &RestoreMBBs,
DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
if (!RestoreMBBs[Id])
return;
std::vector<SRInfo> &Restores = RestoreIdxes[Id];
for (unsigned i = 0, e = Restores.size(); i != e; ++i)
if (Restores[i].index == index && Restores[i].vreg)
- Restores[i].index = -1;
+ Restores[i].index = MachineInstrIndex();
}
/// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
@@ -2085,17 +2278,19 @@ addIntervalsForSpillsFast(const LiveInterval &li,
}
// Fill in the new live interval.
- unsigned index = getInstructionIndex(MI);
+ MachineInstrIndex index = getInstructionIndex(MI);
if (HasUse) {
LiveRange LR(getLoadIndex(index), getUseIndex(index),
- nI.getNextValue(0, 0, false, getVNInfoAllocator()));
+ nI.getNextValue(MachineInstrIndex(), 0, false,
+ getVNInfoAllocator()));
DEBUG(errs() << " +" << LR);
nI.addRange(LR);
vrm.addRestorePoint(NewVReg, MI);
}
if (HasDef) {
LiveRange LR(getDefIndex(index), getStoreIndex(index),
- nI.getNextValue(0, 0, false, getVNInfoAllocator()));
+ nI.getNextValue(MachineInstrIndex(), 0, false,
+ getVNInfoAllocator()));
DEBUG(errs() << " +" << LR);
nI.addRange(LR);
vrm.addSpillPoint(NewVReg, true, MI);
@@ -2158,8 +2353,8 @@ addIntervalsForSpills(const LiveInterval &li,
if (vrm.getPreSplitReg(li.reg)) {
vrm.setIsSplitFromReg(li.reg, 0);
// Unset the split kill marker on the last use.
- unsigned KillIdx = vrm.getKillPoint(li.reg);
- if (KillIdx) {
+ MachineInstrIndex KillIdx = vrm.getKillPoint(li.reg);
+ if (KillIdx != MachineInstrIndex()) {
MachineInstr *KillMI = getInstructionFromIndex(KillIdx);
assert(KillMI && "Last use disappeared?");
int KillOp = KillMI->findRegisterUseOperandIdx(li.reg, true);
@@ -2203,9 +2398,7 @@ addIntervalsForSpills(const LiveInterval &li,
return NewLIs;
}
- bool TrySplit = SplitAtBB && !intervalIsInOneMBB(li);
- if (SplitLimit != -1 && (int)numSplits >= SplitLimit)
- TrySplit = false;
+ bool TrySplit = !intervalIsInOneMBB(li);
if (TrySplit)
++numSplits;
bool NeedStackSlot = false;
@@ -2224,7 +2417,7 @@ addIntervalsForSpills(const LiveInterval &li,
ReMatOrigDefs[VN] = ReMatDefMI;
// Original def may be modified so we have to make a copy here.
MachineInstr *Clone = mf_->CloneMachineInstr(ReMatDefMI);
- ClonedMIs.push_back(Clone);
+ CloneMIs.push_back(Clone);
ReMatDefs[VN] = Clone;
bool CanDelete = true;
@@ -2287,7 +2480,7 @@ addIntervalsForSpills(const LiveInterval &li,
while (Id != -1) {
std::vector<SRInfo> &spills = SpillIdxes[Id];
for (unsigned i = 0, e = spills.size(); i != e; ++i) {
- int index = spills[i].index;
+ MachineInstrIndex index = spills[i].index;
unsigned VReg = spills[i].vreg;
LiveInterval &nI = getOrCreateInterval(VReg);
bool isReMat = vrm.isReMaterialized(VReg);
@@ -2325,7 +2518,7 @@ addIntervalsForSpills(const LiveInterval &li,
if (FoundUse) {
// Also folded uses, do not issue a load.
eraseRestoreInfo(Id, index, VReg, RestoreMBBs, RestoreIdxes);
- nI.removeRange(getLoadIndex(index), getUseIndex(index)+1);
+ nI.removeRange(getLoadIndex(index), getNextSlot(getUseIndex(index)));
}
nI.removeRange(getDefIndex(index), getStoreIndex(index));
}
@@ -2350,8 +2543,8 @@ addIntervalsForSpills(const LiveInterval &li,
while (Id != -1) {
std::vector<SRInfo> &restores = RestoreIdxes[Id];
for (unsigned i = 0, e = restores.size(); i != e; ++i) {
- int index = restores[i].index;
- if (index == -1)
+ MachineInstrIndex index = restores[i].index;
+ if (index == MachineInstrIndex())
continue;
unsigned VReg = restores[i].vreg;
LiveInterval &nI = getOrCreateInterval(VReg);
@@ -2406,7 +2599,7 @@ addIntervalsForSpills(const LiveInterval &li,
// If folding is not possible / failed, then tell the spiller to issue a
// load / rematerialization for us.
if (Folded)
- nI.removeRange(getLoadIndex(index), getUseIndex(index)+1);
+ nI.removeRange(getLoadIndex(index), getNextSlot(getUseIndex(index)));
else
vrm.addRestorePoint(VReg, MI);
}
@@ -2422,7 +2615,7 @@ addIntervalsForSpills(const LiveInterval &li,
LI->weight /= InstrSlots::NUM * getApproximateInstructionCount(*LI);
if (!AddedKill.count(LI)) {
LiveRange *LR = &LI->ranges[LI->ranges.size()-1];
- unsigned LastUseIdx = getBaseIndex(LR->end);
+ MachineInstrIndex LastUseIdx = getBaseIndex(LR->end);
MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg, false);
assert(UseIdx != -1);
@@ -2473,7 +2666,7 @@ unsigned LiveIntervals::getNumConflictsWithPhysReg(const LiveInterval &li,
E = mri_->reg_end(); I != E; ++I) {
MachineOperand &O = I.getOperand();
MachineInstr *MI = O.getParent();
- unsigned Index = getInstructionIndex(MI);
+ MachineInstrIndex Index = getInstructionIndex(MI);
if (pli.liveAt(Index))
++NumConflicts;
}
@@ -2504,11 +2697,11 @@ bool LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li,
if (SeenMIs.count(MI))
continue;
SeenMIs.insert(MI);
- unsigned Index = getInstructionIndex(MI);
+ MachineInstrIndex Index = getInstructionIndex(MI);
if (pli.liveAt(Index)) {
vrm.addEmergencySpill(SpillReg, MI);
- unsigned StartIdx = getLoadIndex(Index);
- unsigned EndIdx = getStoreIndex(Index)+1;
+ MachineInstrIndex StartIdx = getLoadIndex(Index);
+ MachineInstrIndex EndIdx = getNextSlot(getStoreIndex(Index));
if (pli.isInOneLiveRange(StartIdx, EndIdx)) {
pli.removeRange(StartIdx, EndIdx);
Cut = true;
@@ -2528,7 +2721,7 @@ bool LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li,
continue;
LiveInterval &spli = getInterval(*AS);
if (spli.liveAt(Index))
- spli.removeRange(getLoadIndex(Index), getStoreIndex(Index)+1);
+ spli.removeRange(getLoadIndex(Index), getNextSlot(getStoreIndex(Index)));
}
}
}
@@ -2539,13 +2732,13 @@ LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
MachineInstr* startInst) {
LiveInterval& Interval = getOrCreateInterval(reg);
VNInfo* VN = Interval.getNextValue(
- getInstructionIndex(startInst) + InstrSlots::DEF,
- startInst, true, getVNInfoAllocator());
+ MachineInstrIndex(getInstructionIndex(startInst), MachineInstrIndex::DEF),
+ startInst, true, getVNInfoAllocator());
VN->setHasPHIKill(true);
- VN->kills.push_back(
- VNInfo::KillInfo(terminatorGaps[startInst->getParent()], true));
- LiveRange LR(getInstructionIndex(startInst) + InstrSlots::DEF,
- getMBBEndIdx(startInst->getParent()) + 1, VN);
+ VN->kills.push_back(terminatorGaps[startInst->getParent()]);
+ LiveRange LR(
+ MachineInstrIndex(getInstructionIndex(startInst), MachineInstrIndex::DEF),
+ getNextSlot(getMBBEndIdx(startInst->getParent())), VN);
Interval.addRange(LR);
return LR;
diff --git a/libclamav/c++/llvm/lib/CodeGen/LiveVariables.cpp b/libclamav/c++/llvm/lib/CodeGen/LiveVariables.cpp
index 2da1be9..139e029 100644
--- a/libclamav/c++/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/LiveVariables.cpp
@@ -180,9 +180,9 @@ void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
}
/// FindLastPartialDef - Return the last partial def of the specified register.
-/// Also returns the sub-register that's defined.
+/// Also returns the sub-registers that're defined by the instruction.
MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
- unsigned &PartDefReg) {
+ SmallSet<unsigned,4> &PartDefRegs) {
unsigned LastDefReg = 0;
unsigned LastDefDist = 0;
MachineInstr *LastDef = NULL;
@@ -198,7 +198,23 @@ MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
LastDefDist = Dist;
}
}
- PartDefReg = LastDefReg;
+
+ if (!LastDef)
+ return 0;
+
+ PartDefRegs.insert(LastDefReg);
+ for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = LastDef->getOperand(i);
+ if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
+ continue;
+ unsigned DefReg = MO.getReg();
+ if (TRI->isSubRegister(Reg, DefReg)) {
+ PartDefRegs.insert(DefReg);
+ for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg);
+ unsigned SubReg = *SubRegs; ++SubRegs)
+ PartDefRegs.insert(SubReg);
+ }
+ }
return LastDef;
}
@@ -216,8 +232,8 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
// ...
// = EAX
// All of the sub-registers must have been defined before the use of Reg!
- unsigned PartDefReg = 0;
- MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefReg);
+ SmallSet<unsigned, 4> PartDefRegs;
+ MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
// If LastPartialDef is NULL, it must be using a livein register.
if (LastPartialDef) {
LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
@@ -228,7 +244,7 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
unsigned SubReg = *SubRegs; ++SubRegs) {
if (Processed.count(SubReg))
continue;
- if (SubReg == PartDefReg || TRI->isSubRegister(PartDefReg, SubReg))
+ if (PartDefRegs.count(SubReg))
continue;
// This part of Reg was defined before the last partial def. It's killed
// here.
@@ -249,78 +265,13 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
PhysRegUse[SubReg] = MI;
}
-/// hasRegisterUseBelow - Return true if the specified register is used after
-/// the current instruction and before it's next definition.
-bool LiveVariables::hasRegisterUseBelow(unsigned Reg,
- MachineBasicBlock::iterator I,
- MachineBasicBlock *MBB) {
- if (I == MBB->end())
- return false;
-
- // First find out if there are any uses / defs below.
- bool hasDistInfo = true;
- unsigned CurDist = DistanceMap[I];
- SmallVector<MachineInstr*, 4> Uses;
- SmallVector<MachineInstr*, 4> Defs;
- for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
- RE = MRI->reg_end(); RI != RE; ++RI) {
- MachineOperand &UDO = RI.getOperand();
- MachineInstr *UDMI = &*RI;
- if (UDMI->getParent() != MBB)
- continue;
- DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
- bool isBelow = false;
- if (DI == DistanceMap.end()) {
- // Must be below if it hasn't been assigned a distance yet.
- isBelow = true;
- hasDistInfo = false;
- } else if (DI->second > CurDist)
- isBelow = true;
- if (isBelow) {
- if (UDO.isUse())
- Uses.push_back(UDMI);
- if (UDO.isDef())
- Defs.push_back(UDMI);
- }
- }
-
- if (Uses.empty())
- // No uses below.
- return false;
- else if (!Uses.empty() && Defs.empty())
- // There are uses below but no defs below.
- return true;
- // There are both uses and defs below. We need to know which comes first.
- if (!hasDistInfo) {
- // Complete DistanceMap for this MBB. This information is computed only
- // once per MBB.
- ++I;
- ++CurDist;
- for (MachineBasicBlock::iterator E = MBB->end(); I != E; ++I, ++CurDist)
- DistanceMap.insert(std::make_pair(I, CurDist));
- }
-
- unsigned EarliestUse = DistanceMap[Uses[0]];
- for (unsigned i = 1, e = Uses.size(); i != e; ++i) {
- unsigned Dist = DistanceMap[Uses[i]];
- if (Dist < EarliestUse)
- EarliestUse = Dist;
- }
- for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
- unsigned Dist = DistanceMap[Defs[i]];
- if (Dist < EarliestUse)
- // The register is defined before its first use below.
- return false;
- }
- return true;
-}
-
bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
- if (!PhysRegUse[Reg] && !PhysRegDef[Reg])
+ MachineInstr *LastDef = PhysRegDef[Reg];
+ MachineInstr *LastUse = PhysRegUse[Reg];
+ if (!LastDef && !LastUse)
return false;
- MachineInstr *LastRefOrPartRef = PhysRegUse[Reg]
- ? PhysRegUse[Reg] : PhysRegDef[Reg];
+ MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
// The whole register is used.
// AL =
@@ -339,9 +290,22 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
// AX<dead> = AL<imp-def>
// = AL<kill>
// AX =
+ MachineInstr *LastPartDef = 0;
+ unsigned LastPartDefDist = 0;
SmallSet<unsigned, 8> PartUses;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) {
+ MachineInstr *Def = PhysRegDef[SubReg];
+ if (Def && Def != LastDef) {
+ // There was a def of this sub-register in between. This is a partial
+ // def, keep track of the last one.
+ unsigned Dist = DistanceMap[Def];
+ if (Dist > LastPartDefDist) {
+ LastPartDefDist = Dist;
+ LastPartDef = Def;
+ }
+ continue;
+ }
if (MachineInstr *Use = PhysRegUse[SubReg]) {
PartUses.insert(SubReg);
for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
@@ -354,44 +318,47 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
}
}
- if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI)
- // If the last reference is the last def, then it's not used at all.
- // That is, unless we are currently processing the last reference itself.
- LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
-
- // Partial uses. Mark register def dead and add implicit def of
- // sub-registers which are used.
- // EAX<dead> = op AL<imp-def>
- // That is, EAX def is dead but AL def extends pass it.
- // Enable this after live interval analysis is fixed to improve codegen!
- else if (!PhysRegUse[Reg]) {
+ if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
+ if (LastPartDef)
+ // The last partial def kills the register.
+ LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
+ true/*IsImp*/, true/*IsKill*/));
+ else
+ // If the last reference is the last def, then it's not used at all.
+ // That is, unless we are currently processing the last reference itself.
+ LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
+ } else if (!PhysRegUse[Reg]) {
+ // Partial uses. Mark register def dead and add implicit def of
+ // sub-registers which are used.
+ // EAX<dead> = op AL<imp-def>
+ // That is, EAX def is dead but AL def extends pass it.
PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) {
- if (PartUses.count(SubReg)) {
- bool NeedDef = true;
- if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
- MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
- if (MO) {
- NeedDef = false;
- assert(!MO->isDead());
- }
+ if (!PartUses.count(SubReg))
+ continue;
+ bool NeedDef = true;
+ if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
+ MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
+ if (MO) {
+ NeedDef = false;
+ assert(!MO->isDead());
}
- if (NeedDef)
- PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
- true, true));
- LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
- for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
- PartUses.erase(*SS);
}
+ if (NeedDef)
+ PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
+ true/*IsDef*/, true/*IsImp*/));
+ LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
+ for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
+ PartUses.erase(*SS);
}
- }
- else
+ } else
LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
return true;
}
-void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
+void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
+ SmallVector<unsigned, 4> &Defs) {
// What parts of the register are previously defined?
SmallSet<unsigned, 32> Live;
if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
@@ -407,6 +374,8 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
// AL =
// AH =
// = AX
+ if (Live.count(SubReg))
+ continue;
if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
Live.insert(SubReg);
for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
@@ -417,68 +386,25 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
// Start from the largest piece, find the last time any part of the register
// is referenced.
- if (!HandlePhysRegKill(Reg, MI)) {
- // Only some of the sub-registers are used.
- for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs) {
- if (!Live.count(SubReg))
- // Skip if this sub-register isn't defined.
- continue;
- if (HandlePhysRegKill(SubReg, MI)) {
- Live.erase(SubReg);
- for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
- Live.erase(*SS);
- }
- }
- assert(Live.empty() && "Not all defined registers are killed / dead?");
+ HandlePhysRegKill(Reg, MI);
+ // Only some of the sub-registers are used.
+ for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs) {
+ if (!Live.count(SubReg))
+ // Skip if this sub-register isn't defined.
+ continue;
+ HandlePhysRegKill(SubReg, MI);
}
- if (MI) {
- // Does this extend the live range of a super-register?
- SmallSet<unsigned, 8> Processed;
- for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
- unsigned SuperReg = *SuperRegs; ++SuperRegs) {
- if (Processed.count(SuperReg))
- continue;
- MachineInstr *LastRef = PhysRegUse[SuperReg]
- ? PhysRegUse[SuperReg] : PhysRegDef[SuperReg];
- if (LastRef && LastRef != MI) {
- // The larger register is previously defined. Now a smaller part is
- // being re-defined. Treat it as read/mod/write if there are uses
- // below.
- // EAX =
- // AX = EAX<imp-use,kill>, EAX<imp-def>
- // ...
- /// = EAX
- if (hasRegisterUseBelow(SuperReg, MI, MI->getParent())) {
- MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
- true/*IsImp*/,true/*IsKill*/));
- MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
- true/*IsImp*/));
- PhysRegDef[SuperReg] = MI;
- PhysRegUse[SuperReg] = NULL;
- Processed.insert(SuperReg);
- for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
- PhysRegDef[*SS] = MI;
- PhysRegUse[*SS] = NULL;
- Processed.insert(*SS);
- }
- } else {
- // Otherwise, the super register is killed.
- if (HandlePhysRegKill(SuperReg, MI)) {
- PhysRegDef[SuperReg] = NULL;
- PhysRegUse[SuperReg] = NULL;
- for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
- PhysRegDef[*SS] = NULL;
- PhysRegUse[*SS] = NULL;
- Processed.insert(*SS);
- }
- }
- }
- }
- }
+ if (MI)
+ Defs.push_back(Reg); // Remember this def.
+}
- // Remember this def.
+void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
+ SmallVector<unsigned, 4> &Defs) {
+ while (!Defs.empty()) {
+ unsigned Reg = Defs.back();
+ Defs.pop_back();
PhysRegDef[Reg] = MI;
PhysRegUse[Reg] = NULL;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
@@ -489,6 +415,21 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
}
}
+namespace {
+ struct RegSorter {
+ const TargetRegisterInfo *TRI;
+
+ RegSorter(const TargetRegisterInfo *tri) : TRI(tri) { }
+ bool operator()(unsigned A, unsigned B) {
+ if (TRI->isSubRegister(A, B))
+ return true;
+ else if (TRI->isSubRegister(B, A))
+ return false;
+ return A < B;
+ }
+ };
+}
+
bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
MRI = &mf.getRegInfo();
@@ -521,11 +462,12 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
MachineBasicBlock *MBB = *DFI;
// Mark live-in registers as live-in.
+ SmallVector<unsigned, 4> Defs;
for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
EE = MBB->livein_end(); II != EE; ++II) {
assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
"Cannot have a live-in virtual register!");
- HandlePhysRegDef(*II, 0);
+ HandlePhysRegDef(*II, 0, Defs);
}
// Loop over all of the instructions, processing them.
@@ -572,8 +514,9 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
if (TargetRegisterInfo::isVirtualRegister(MOReg))
HandleVirtRegDef(MOReg, MI);
else if (!ReservedRegisters[MOReg])
- HandlePhysRegDef(MOReg, MI);
+ HandlePhysRegDef(MOReg, MI, Defs);
}
+ UpdatePhysRegDefs(MI, Defs);
}
// Handle any virtual assignments from PHI nodes which might be at the
@@ -612,7 +555,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
// available at the end of the basic block.
for (unsigned i = 0; i != NumRegs; ++i)
if (PhysRegDef[i] || PhysRegUse[i])
- HandlePhysRegDef(i, 0);
+ HandlePhysRegDef(i, 0, Defs);
std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
diff --git a/libclamav/c++/llvm/lib/CodeGen/LowerSubregs.cpp b/libclamav/c++/llvm/lib/CodeGen/LowerSubregs.cpp
index 812d97d..8486bb0 100644
--- a/libclamav/c++/llvm/lib/CodeGen/LowerSubregs.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/LowerSubregs.cpp
@@ -126,9 +126,9 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
if (SrcReg == DstReg) {
// No need to insert an identity copy instruction.
if (MI->getOperand(1).isKill()) {
- // We must make sure the super-register gets killed.Replace the
- // instruction with IMPLICIT_DEF.
- MI->setDesc(TII.get(TargetInstrInfo::IMPLICIT_DEF));
+ // We must make sure the super-register gets killed. Replace the
+ // instruction with KILL.
+ MI->setDesc(TII.get(TargetInstrInfo::KILL));
MI->RemoveOperand(2); // SubIdx
DEBUG(errs() << "subreg: replace by: " << *MI);
return true;
@@ -242,14 +242,14 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
if (DstSubReg == InsReg) {
// No need to insert an identity copy instruction. If the SrcReg was
- // <undef>, we need to make sure it is alive by inserting an IMPLICIT_DEF
+ // <undef>, we need to make sure it is alive by inserting a KILL
if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
- TII.get(TargetInstrInfo::IMPLICIT_DEF), DstReg);
+ TII.get(TargetInstrInfo::KILL), DstReg);
if (MI->getOperand(2).isUndef())
- MIB.addReg(InsReg, RegState::Implicit | RegState::Undef);
+ MIB.addReg(InsReg, RegState::Undef);
else
- MIB.addReg(InsReg, RegState::ImplicitKill);
+ MIB.addReg(InsReg, RegState::Kill);
} else {
DEBUG(errs() << "subreg: eliminated!\n");
MBB->erase(MI);
@@ -260,10 +260,10 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
if (MI->getOperand(2).isUndef())
- // If the source register being inserted is undef, then this becomes an
- // implicit_def.
+ // If the source register being inserted is undef, then this becomes a
+ // KILL.
BuildMI(*MBB, MI, MI->getDebugLoc(),
- TII.get(TargetInstrInfo::IMPLICIT_DEF), DstSubReg);
+ TII.get(TargetInstrInfo::KILL), DstSubReg);
else
TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
MachineBasicBlock::iterator CopyMI = MI;
diff --git a/libclamav/c++/llvm/lib/CodeGen/MachineFunction.cpp b/libclamav/c++/llvm/lib/CodeGen/MachineFunction.cpp
index 14ba360..2ff20f2 100644
--- a/libclamav/c++/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/MachineFunction.cpp
@@ -73,6 +73,9 @@ FunctionPass *llvm::createMachineFunctionPrinterPass(raw_ostream &OS,
// MachineFunction implementation
//===---------------------------------------------------------------------===//
+// Out of line virtual method.
+MachineFunctionInfo::~MachineFunctionInfo() {}
+
void ilist_traits<MachineBasicBlock>::deleteNode(MachineBasicBlock *MBB) {
MBB->getParent()->DeleteMachineBasicBlock(MBB);
}
@@ -187,11 +190,6 @@ MachineFunction::CloneMachineInstr(const MachineInstr *Orig) {
///
void
MachineFunction::DeleteMachineInstr(MachineInstr *MI) {
- // Clear the instructions memoperands. This must be done manually because
- // the instruction's parent pointer is now null, so it can't properly
- // deallocate them on its own.
- MI->clearMemOperands(*this);
-
MI->~MachineInstr();
InstructionRecycler.Deallocate(Allocator, MI);
}
@@ -214,6 +212,29 @@ MachineFunction::DeleteMachineBasicBlock(MachineBasicBlock *MBB) {
BasicBlockRecycler.Deallocate(Allocator, MBB);
}
+MachineMemOperand *
+MachineFunction::getMachineMemOperand(const Value *v, unsigned f,
+ int64_t o, uint64_t s,
+ unsigned base_alignment) {
+ return new (Allocator.Allocate<MachineMemOperand>())
+ MachineMemOperand(v, f, o, s, base_alignment);
+}
+
+MachineMemOperand *
+MachineFunction::getMachineMemOperand(const MachineMemOperand *MMO,
+ int64_t Offset, uint64_t Size) {
+ return new (Allocator.Allocate<MachineMemOperand>())
+ MachineMemOperand(MMO->getValue(), MMO->getFlags(),
+ int64_t(uint64_t(MMO->getOffset()) +
+ uint64_t(Offset)),
+ Size, MMO->getBaseAlignment());
+}
+
+MachineInstr::mmo_iterator
+MachineFunction::allocateMemRefsArray(unsigned long Num) {
+ return Allocator.Allocate<MachineMemOperand *>(Num);
+}
+
void MachineFunction::dump() const {
print(errs());
}
@@ -330,23 +351,6 @@ unsigned MachineFunction::addLiveIn(unsigned PReg,
return VReg;
}
-/// getOrCreateDebugLocID - Look up the DebugLocTuple index with the given
-/// source file, line, and column. If none currently exists, create a new
-/// DebugLocTuple, and insert it into the DebugIdMap.
-unsigned MachineFunction::getOrCreateDebugLocID(MDNode *CompileUnit,
- unsigned Line, unsigned Col) {
- DebugLocTuple Tuple(CompileUnit, Line, Col);
- DenseMap<DebugLocTuple, unsigned>::iterator II
- = DebugLocInfo.DebugIdMap.find(Tuple);
- if (II != DebugLocInfo.DebugIdMap.end())
- return II->second;
- // Add a new tuple.
- unsigned Id = DebugLocInfo.DebugLocations.size();
- DebugLocInfo.DebugLocations.push_back(Tuple);
- DebugLocInfo.DebugIdMap[Tuple] = Id;
- return Id;
-}
-
/// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc object.
DebugLocTuple MachineFunction::getDebugLocTuple(DebugLoc DL) const {
unsigned Idx = DL.getIndex();
diff --git a/libclamav/c++/llvm/lib/CodeGen/MachineInstr.cpp b/libclamav/c++/llvm/lib/CodeGen/MachineInstr.cpp
index 792a2e0..3d1c221 100644
--- a/libclamav/c++/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/MachineInstr.cpp
@@ -15,7 +15,9 @@
#include "llvm/Constants.h"
#include "llvm/InlineAsm.h"
#include "llvm/Value.h"
+#include "llvm/Assembly/Writer.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Target/TargetMachine.h"
@@ -284,7 +286,7 @@ MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
int64_t o, uint64_t s, unsigned int a)
: Offset(o), Size(s), V(v),
Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
- assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
+ assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
assert((isLoad() || isStore()) && "Not a load/store!");
}
@@ -297,6 +299,66 @@ void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
ID.AddInteger(Flags);
}
+void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
+ // The Value and Offset may differ due to CSE. But the flags and size
+ // should be the same.
+ assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
+ assert(MMO->getSize() == getSize() && "Size mismatch!");
+
+ if (MMO->getBaseAlignment() >= getBaseAlignment()) {
+ // Update the alignment value.
+ Flags = (Flags & 7) | ((Log2_32(MMO->getBaseAlignment()) + 1) << 3);
+ // Also update the base and offset, because the new alignment may
+ // not be applicable with the old ones.
+ V = MMO->getValue();
+ Offset = MMO->getOffset();
+ }
+}
+
+/// getAlignment - Return the minimum known alignment in bytes of the
+/// actual memory reference.
+uint64_t MachineMemOperand::getAlignment() const {
+ return MinAlign(getBaseAlignment(), getOffset());
+}
+
+raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
+ assert((MMO.isLoad() || MMO.isStore()) &&
+ "SV has to be a load, store or both.");
+
+ if (MMO.isVolatile())
+ OS << "Volatile ";
+
+ if (MMO.isLoad())
+ OS << "LD";
+ if (MMO.isStore())
+ OS << "ST";
+ OS << MMO.getSize();
+
+ // Print the address information.
+ OS << "[";
+ if (!MMO.getValue())
+ OS << "<unknown>";
+ else
+ WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
+
+ // If the alignment of the memory reference itself differs from the alignment
+ // of the base pointer, print the base alignment explicitly, next to the base
+ // pointer.
+ if (MMO.getBaseAlignment() != MMO.getAlignment())
+ OS << "(align=" << MMO.getBaseAlignment() << ")";
+
+ if (MMO.getOffset() != 0)
+ OS << "+" << MMO.getOffset();
+ OS << "]";
+
+ // Print the alignment of the reference.
+ if (MMO.getBaseAlignment() != MMO.getAlignment() ||
+ MMO.getBaseAlignment() != MMO.getSize())
+ OS << "(align=" << MMO.getAlignment() << ")";
+
+ return OS;
+}
+
//===----------------------------------------------------------------------===//
// MachineInstr Implementation
//===----------------------------------------------------------------------===//
@@ -304,7 +366,8 @@ void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
/// TID NULL and no operands.
MachineInstr::MachineInstr()
- : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
+ : TID(0), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0),
+ Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
// Make sure that we get added to a machine basicblock
LeakDetector::addGarbageObject(this);
}
@@ -323,7 +386,7 @@ void MachineInstr::addImplicitDefUseOperands() {
/// TargetInstrDesc or the numOperands if it is not zero. (for
/// instructions with variable number of operands).
MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
- : TID(&tid), NumImplicitOps(0), Parent(0),
+ : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), Parent(0),
debugLoc(DebugLoc::getUnknownLoc()) {
if (!NoImp && TID->getImplicitDefs())
for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
@@ -341,7 +404,8 @@ MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
/// MachineInstr ctor - As above, but with a DebugLoc.
MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
bool NoImp)
- : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
+ : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0),
+ Parent(0), debugLoc(dl) {
if (!NoImp && TID->getImplicitDefs())
for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
NumImplicitOps++;
@@ -360,7 +424,7 @@ MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
/// basic block.
///
MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
- : TID(&tid), NumImplicitOps(0), Parent(0),
+ : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), Parent(0),
debugLoc(DebugLoc::getUnknownLoc()) {
assert(MBB && "Cannot use inserting ctor with null basic block!");
if (TID->ImplicitDefs)
@@ -380,7 +444,8 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
///
MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
const TargetInstrDesc &tid)
- : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
+ : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0),
+ Parent(0), debugLoc(dl) {
assert(MBB && "Cannot use inserting ctor with null basic block!");
if (TID->ImplicitDefs)
for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
@@ -398,8 +463,9 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
/// MachineInstr ctor - Copies MachineInstr arg exactly
///
MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
- : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0),
- debugLoc(MI.getDebugLoc()) {
+ : TID(&MI.getDesc()), NumImplicitOps(0),
+ MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
+ Parent(0), debugLoc(MI.getDebugLoc()) {
Operands.reserve(MI.getNumOperands());
// Add operands
@@ -407,11 +473,6 @@ MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
addOperand(MI.getOperand(i));
NumImplicitOps = MI.NumImplicitOps;
- // Add memory operands.
- for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
- j = MI.memoperands_end(); i != j; ++i)
- addMemOperand(MF, *i);
-
// Set parent to null.
Parent = 0;
@@ -420,8 +481,6 @@ MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
MachineInstr::~MachineInstr() {
LeakDetector::removeGarbageObject(this);
- assert(MemOperands.empty() &&
- "MachineInstr being deleted with live memoperands!");
#ifndef NDEBUG
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
@@ -582,18 +641,24 @@ void MachineInstr::RemoveOperand(unsigned OpNo) {
}
}
-/// addMemOperand - Add a MachineMemOperand to the machine instruction,
-/// referencing arbitrary storage.
+/// addMemOperand - Add a MachineMemOperand to the machine instruction.
+/// This function should be used only occasionally. The setMemRefs function
+/// is the primary method for setting up a MachineInstr's MemRefs list.
void MachineInstr::addMemOperand(MachineFunction &MF,
- const MachineMemOperand &MO) {
- MemOperands.push_back(MO);
-}
+ MachineMemOperand *MO) {
+ mmo_iterator OldMemRefs = MemRefs;
+ mmo_iterator OldMemRefsEnd = MemRefsEnd;
-/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
-void MachineInstr::clearMemOperands(MachineFunction &MF) {
- MemOperands.clear();
-}
+ size_t NewNum = (MemRefsEnd - MemRefs) + 1;
+ mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
+ mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
+ std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
+ NewMemRefs[NewNum - 1] = MO;
+
+ MemRefs = NewMemRefs;
+ MemRefsEnd = NewMemRefsEnd;
+}
/// removeFromParent - This method unlinks 'this' from the containing basic
/// block, and returns it, but does not delete it.
@@ -652,7 +717,7 @@ bool MachineInstr::isDebugLabel() const {
}
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
-/// the specific register or -1 if it is not found. It further tightening
+/// the specific register or -1 if it is not found. It further tightens
/// the search criteria to a use that kills the register if isKill is true.
int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
const TargetRegisterInfo *TRI) const {
@@ -933,9 +998,8 @@ bool MachineInstr::hasVolatileMemoryRef() const {
return true;
// Check the memory reference information for volatile references.
- for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
- E = memoperands_end(); I != E; ++I)
- if (I->isVolatile())
+ for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
+ if ((*I)->isVolatile())
return true;
return false;
@@ -965,34 +1029,11 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
if (!memoperands_empty()) {
OS << ", Mem:";
- for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
- e = memoperands_end(); i != e; ++i) {
- const MachineMemOperand &MRO = *i;
- const Value *V = MRO.getValue();
-
- assert((MRO.isLoad() || MRO.isStore()) &&
- "SV has to be a load, store or both.");
-
- if (MRO.isVolatile())
- OS << "Volatile ";
-
- if (MRO.isLoad())
- OS << "LD";
- if (MRO.isStore())
- OS << "ST";
-
- OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
-
- if (!V)
- OS << "<unknown>";
- else if (!V->getName().empty())
- OS << V->getName();
- else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
- PSV->print(OS);
- } else
- OS << V;
-
- OS << " + " << MRO.getOffset() << "]";
+ for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
+ i != e; ++i) {
+ OS << **i;
+ if (next(i) != e)
+ OS << " ";
}
}
@@ -1000,9 +1041,8 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
const MachineFunction *MF = getParent()->getParent();
DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
DICompileUnit CU(DLT.CompileUnit);
- std::string Dir, Fn;
OS << " [dbg: "
- << CU.getDirectory(Dir) << '/' << CU.getFilename(Fn) << ","
+ << CU.getDirectory() << '/' << CU.getFilename() << ","
<< DLT.Line << ","
<< DLT.Col << "]";
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/MachineLICM.cpp b/libclamav/c++/llvm/lib/CodeGen/MachineLICM.cpp
index bb0d832..61678f1 100644
--- a/libclamav/c++/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/MachineLICM.cpp
@@ -43,6 +43,8 @@ namespace {
class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass {
const TargetMachine *TM;
const TargetInstrInfo *TII;
+ const TargetRegisterInfo *TRI;
+ BitVector AllocatableSet;
// Various analyses that we use...
MachineLoopInfo *LI; // Current MachineLoopInfo
@@ -135,7 +137,9 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
Changed = false;
TM = &MF.getTarget();
TII = TM->getInstrInfo();
+ TRI = TM->getRegisterInfo();
RegInfo = &MF.getRegInfo();
+ AllocatableSet = TRI->getAllocatableSet(MF);
// Get our Loop information...
LI = &getAnalysis<MachineLoopInfo>();
@@ -254,8 +258,32 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
if (Reg == 0) continue;
// Don't hoist an instruction that uses or defines a physical register.
- if (TargetRegisterInfo::isPhysicalRegister(Reg))
- return false;
+ if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
+ // If this is a physical register use, we can't move it. If it is a def,
+ // we can move it, but only if the def is dead.
+ if (MO.isUse()) {
+ // If the physreg has no defs anywhere, it's just an ambient register
+ // and we can freely move its uses. Alternatively, if it's allocatable,
+ // it could get allocated to something with a def during allocation.
+ if (!RegInfo->def_empty(Reg))
+ return false;
+ if (AllocatableSet.test(Reg))
+ return false;
+ // Check for a def among the register's aliases too.
+ for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
+ unsigned AliasReg = *Alias;
+ if (!RegInfo->def_empty(AliasReg))
+ return false;
+ if (AllocatableSet.test(AliasReg))
+ return false;
+ }
+ // Otherwise it's safe to move.
+ continue;
+ } else if (!MO.isDead()) {
+ // A def that isn't dead. We can't move it.
+ return false;
+ }
+ }
if (!MO.isUse())
continue;
diff --git a/libclamav/c++/llvm/lib/CodeGen/MachineModuleInfo.cpp b/libclamav/c++/llvm/lib/CodeGen/MachineModuleInfo.cpp
index a673d17..8661b9e 100644
--- a/libclamav/c++/llvm/lib/CodeGen/MachineModuleInfo.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/MachineModuleInfo.cpp
@@ -32,23 +32,23 @@ static RegisterPass<MachineModuleInfo>
X("machinemoduleinfo", "Module Information");
char MachineModuleInfo::ID = 0;
+// Out of line virtual method.
+MachineModuleInfoImpl::~MachineModuleInfoImpl() {}
+
//===----------------------------------------------------------------------===//
MachineModuleInfo::MachineModuleInfo()
: ImmutablePass(&ID)
-, LabelIDList()
-, FrameMoves()
-, LandingPads()
-, Personalities()
+, ObjFileMMI(0)
, CallsEHReturn(0)
, CallsUnwindInit(0)
-, DbgInfoAvailable(false)
-{
+, DbgInfoAvailable(false) {
// Always emit some info, by default "no personality" info.
Personalities.push_back(NULL);
}
-MachineModuleInfo::~MachineModuleInfo() {
+MachineModuleInfo::~MachineModuleInfo() {
+ delete ObjFileMMI;
}
/// doInitialization - Initialize the state for a new module.
@@ -63,12 +63,6 @@ bool MachineModuleInfo::doFinalization() {
return false;
}
-/// BeginFunction - Begin gathering function meta information.
-///
-void MachineModuleInfo::BeginFunction(MachineFunction *MF) {
- // Coming soon.
-}
-
/// EndFunction - Discard function meta information.
///
void MachineModuleInfo::EndFunction() {
diff --git a/libclamav/c++/llvm/lib/CodeGen/MachineModuleInfoImpls.cpp b/libclamav/c++/llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
new file mode 100644
index 0000000..7a62929
--- /dev/null
+++ b/libclamav/c++/llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
@@ -0,0 +1,45 @@
+//===-- llvm/CodeGen/MachineModuleInfoImpls.cpp ---------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements object-file format specific implementations of
+// MachineModuleInfoImpl.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/MachineModuleInfoImpls.h"
+#include "llvm/MC/MCSymbol.h"
+using namespace llvm;
+
+//===----------------------------------------------------------------------===//
+// MachineModuleInfoMachO
+//===----------------------------------------------------------------------===//
+
+// Out of line virtual method.
+void MachineModuleInfoMachO::Anchor() {}
+
+
+static int SortSymbolPair(const void *LHS, const void *RHS) {
+ const MCSymbol *LHSS =
+ ((const std::pair<const MCSymbol*, const MCSymbol*>*)LHS)->first;
+ const MCSymbol *RHSS =
+ ((const std::pair<const MCSymbol*, const MCSymbol*>*)RHS)->first;
+ return LHSS->getName().compare(RHSS->getName());
+}
+
+/// GetSortedStubs - Return the entries from a DenseMap in a deterministic
+/// sorted orer.
+MachineModuleInfoMachO::SymbolListTy
+MachineModuleInfoMachO::GetSortedStubs(const DenseMap<const MCSymbol*,
+ const MCSymbol*> &Map) {
+ MachineModuleInfoMachO::SymbolListTy List(Map.begin(), Map.end());
+ if (!List.empty())
+ qsort(&List[0], List.size(), sizeof(List[0]), SortSymbolPair);
+ return List;
+}
+
diff --git a/libclamav/c++/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/libclamav/c++/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index 544d83a..b31973e 100644
--- a/libclamav/c++/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -110,11 +110,9 @@ void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
"Invalid vreg!");
- for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
- // Since we are in SSA form, we can stop at the first definition.
- if (I.getOperand().isDef())
- return &*I;
- }
+ // Since we are in SSA form, we can use the first definition.
+ if (!def_empty(Reg))
+ return &*def_begin(Reg);
return 0;
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/MachineSink.cpp b/libclamav/c++/llvm/lib/CodeGen/MachineSink.cpp
index 7fb33c6..636dad8 100644
--- a/libclamav/c++/llvm/lib/CodeGen/MachineSink.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/MachineSink.cpp
@@ -35,9 +35,11 @@ namespace {
class VISIBILITY_HIDDEN MachineSinking : public MachineFunctionPass {
const TargetMachine *TM;
const TargetInstrInfo *TII;
+ const TargetRegisterInfo *TRI;
MachineFunction *CurMF; // Current MachineFunction
MachineRegisterInfo *RegInfo; // Machine register information
MachineDominatorTree *DT; // Machine dominator tree
+ BitVector AllocatableSet; // Which physregs are allocatable?
public:
static char ID; // Pass identification
@@ -70,10 +72,8 @@ bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
MachineBasicBlock *MBB) const {
assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
"Only makes sense for vregs");
- for (MachineRegisterInfo::reg_iterator I = RegInfo->reg_begin(Reg),
- E = RegInfo->reg_end(); I != E; ++I) {
- if (I.getOperand().isDef()) continue; // ignore def.
-
+ for (MachineRegisterInfo::use_iterator I = RegInfo->use_begin(Reg),
+ E = RegInfo->use_end(); I != E; ++I) {
// Determine the block of the use.
MachineInstr *UseInst = &*I;
MachineBasicBlock *UseBlock = UseInst->getParent();
@@ -97,8 +97,10 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
CurMF = &MF;
TM = &CurMF->getTarget();
TII = TM->getInstrInfo();
+ TRI = TM->getRegisterInfo();
RegInfo = &CurMF->getRegInfo();
DT = &getAnalysis<MachineDominatorTree>();
+ AllocatableSet = TRI->getAllocatableSet(*CurMF);
bool EverMadeChange = false;
@@ -178,8 +180,26 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
// If this is a physical register use, we can't move it. If it is a def,
// we can move it, but only if the def is dead.
- if (MO.isUse() || !MO.isDead())
+ if (MO.isUse()) {
+ // If the physreg has no defs anywhere, it's just an ambient register
+ // and we can freely move its uses. Alternatively, if it's allocatable,
+ // it could get allocated to something with a def during allocation.
+ if (!RegInfo->def_empty(Reg))
+ return false;
+ if (AllocatableSet.test(Reg))
+ return false;
+ // Check for a def among the register's aliases too.
+ for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
+ unsigned AliasReg = *Alias;
+ if (!RegInfo->def_empty(AliasReg))
+ return false;
+ if (AllocatableSet.test(AliasReg))
+ return false;
+ }
+ } else if (!MO.isDead()) {
+ // A def that isn't dead. We can't move it.
return false;
+ }
} else {
// Virtual register uses are always safe to sink.
if (MO.isUse()) continue;
diff --git a/libclamav/c++/llvm/lib/CodeGen/MachineVerifier.cpp b/libclamav/c++/llvm/lib/CodeGen/MachineVerifier.cpp
index f43a370..02e48dd 100644
--- a/libclamav/c++/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -466,18 +466,11 @@ void
MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
{
const TargetInstrDesc &TI = MI->getDesc();
- if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
+ if (MI->getNumOperands() < TI.getNumOperands()) {
report("Too few operands", MI);
*OS << TI.getNumOperands() << " operands expected, but "
<< MI->getNumExplicitOperands() << " given.\n";
}
- if (!TI.isVariadic()) {
- if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
- report("Too many operands", MI);
- *OS << TI.getNumOperands() << " operands expected, but "
- << MI->getNumExplicitOperands() << " given.\n";
- }
- }
}
void
@@ -494,6 +487,16 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
report("Explicit definition marked as use", MO, MONum);
else if (MO->isImplicit())
report("Explicit definition marked as implicit", MO, MONum);
+ } else if (MONum < TI.getNumOperands()) {
+ if (MO->isReg()) {
+ if (MO->isDef())
+ report("Explicit operand marked as def", MO, MONum);
+ if (MO->isImplicit())
+ report("Explicit operand marked as implicit", MO, MONum);
+ }
+ } else {
+ if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic())
+ report("Extra explicit operand on non-variadic instruction", MO, MONum);
}
switch (MO->getType()) {
@@ -592,13 +595,14 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
}
break;
}
- // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
- // case MachineOperand::MO_MachineBasicBlock:
- // if (MI->getOpcode() == TargetInstrInfo::PHI) {
- // if (!MO->getMBB()->isSuccessor(MI->getParent()))
- // report("PHI operand is not in the CFG", MO, MONum);
- // }
- // break;
+
+ case MachineOperand::MO_MachineBasicBlock:
+ if (MI->getOpcode() == TargetInstrInfo::PHI) {
+ if (!MO->getMBB()->isSuccessor(MI->getParent()))
+ report("PHI operand is not in the CFG", MO, MONum);
+ }
+ break;
+
default:
break;
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/PBQP/Heuristics/Briggs.h b/libclamav/c++/llvm/lib/CodeGen/PBQP/Heuristics/Briggs.h
index 255ffef..3ac9e70 100644
--- a/libclamav/c++/llvm/lib/CodeGen/PBQP/Heuristics/Briggs.h
+++ b/libclamav/c++/llvm/lib/CodeGen/PBQP/Heuristics/Briggs.h
@@ -118,7 +118,7 @@ class Briggs {
if (!add) {
udTarget = 1;
- dir = -1;
+ dir = ~0;
}
EdgeData &linkEdgeData = g.getEdgeData(edgeItr).getHeuristicData();
diff --git a/libclamav/c++/llvm/lib/CodeGen/PHIElimination.h b/libclamav/c++/llvm/lib/CodeGen/PHIElimination.h
index b06435f..3d02dfd 100644
--- a/libclamav/c++/llvm/lib/CodeGen/PHIElimination.h
+++ b/libclamav/c++/llvm/lib/CodeGen/PHIElimination.h
@@ -122,4 +122,4 @@ namespace llvm {
}
-#endif /* PHIELIMINATION_H */
+#endif /* LLVM_CODEGEN_PHIELIMINATION_HPP */
diff --git a/libclamav/c++/llvm/lib/CodeGen/PostRASchedulerList.cpp b/libclamav/c++/llvm/lib/CodeGen/PostRASchedulerList.cpp
index 4b4c076..902f505 100644
--- a/libclamav/c++/llvm/lib/CodeGen/PostRASchedulerList.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/PostRASchedulerList.cpp
@@ -26,6 +26,7 @@
#include "llvm/CodeGen/LatencyPriorityQueue.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -34,6 +35,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtarget.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
@@ -46,15 +48,31 @@ using namespace llvm;
STATISTIC(NumNoops, "Number of noops inserted");
STATISTIC(NumStalls, "Number of pipeline stalls");
+// Post-RA scheduling is enabled with
+// TargetSubtarget.enablePostRAScheduler(). This flag can be used to
+// override the target.
+static cl::opt<bool>
+EnablePostRAScheduler("post-RA-scheduler",
+ cl::desc("Enable scheduling after register allocation"),
+ cl::init(false), cl::Hidden);
static cl::opt<bool>
EnableAntiDepBreaking("break-anti-dependencies",
cl::desc("Break post-RA scheduling anti-dependencies"),
cl::init(true), cl::Hidden);
-
static cl::opt<bool>
EnablePostRAHazardAvoidance("avoid-hazards",
cl::desc("Enable exact hazard avoidance"),
- cl::init(false), cl::Hidden);
+ cl::init(true), cl::Hidden);
+
+// If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
+static cl::opt<int>
+DebugDiv("postra-sched-debugdiv",
+ cl::desc("Debug control MBBs that are scheduled"),
+ cl::init(0), cl::Hidden);
+static cl::opt<int>
+DebugMod("postra-sched-debugmod",
+ cl::desc("Debug control MBBs that are scheduled"),
+ cl::init(0), cl::Hidden);
namespace {
class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
@@ -112,14 +130,18 @@ namespace {
/// RegRegs - Map registers to all their references within a live range.
std::multimap<unsigned, MachineOperand *> RegRefs;
- /// The index of the most recent kill (proceding bottom-up), or ~0u if
- /// the register is not live.
+ /// KillIndices - The index of the most recent kill (proceding bottom-up),
+ /// or ~0u if the register is not live.
unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
- /// The index of the most recent complete def (proceding bottom up), or ~0u
- /// if the register is live.
+ /// DefIndices - The index of the most recent complete def (proceding bottom
+ /// up), or ~0u if the register is live.
unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
+ /// KeepRegs - A set of registers which are live and cannot be changed to
+ /// break anti-dependencies.
+ SmallSet<unsigned, 4> KeepRegs;
+
public:
SchedulePostRATDList(MachineFunction &MF,
const MachineLoopInfo &MLI,
@@ -156,11 +178,6 @@ namespace {
///
void FinishBlock();
- /// GenerateLivenessForKills - If true then generate Def/Kill
- /// information for use in updating register kill. If false then
- /// generate Def/Kill information for anti-dependence breaking.
- bool GenerateLivenessForKills;
-
private:
void PrescanInstruction(MachineInstr *MI);
void ScanInstruction(MachineInstr *MI, unsigned Count);
@@ -172,6 +189,12 @@ namespace {
unsigned findSuitableFreeRegister(unsigned AntiDepReg,
unsigned LastNewReg,
const TargetRegisterClass *);
+ void StartBlockForKills(MachineBasicBlock *BB);
+
+ // ToggleKillFlag - Toggle a register operand kill flag. Other
+ // adjustments may be made to the instruction if necessary. Return
+ // true if the operand has been deleted, false if not.
+ bool ToggleKillFlag(MachineInstr *MI, MachineOperand &MO);
};
}
@@ -198,6 +221,17 @@ static bool isSchedulingBoundary(const MachineInstr *MI,
}
bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
+ // Check for explicit enable/disable of post-ra scheduling.
+ if (EnablePostRAScheduler.getPosition() > 0) {
+ if (!EnablePostRAScheduler)
+ return true;
+ } else {
+ // Check that post-RA scheduling is enabled for this function
+ const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
+ if (!ST.enablePostRAScheduler())
+ return true;
+ }
+
DEBUG(errs() << "PostRAScheduler\n");
const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
@@ -212,8 +246,18 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
// Loop over all of the basic blocks
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB) {
+#ifndef NDEBUG
+ // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
+ if (DebugDiv > 0) {
+ static int bbcnt = 0;
+ if (bbcnt++ % DebugDiv != DebugMod)
+ continue;
+ errs() << "*** DEBUG scheduling " << Fn.getFunction()->getNameStr() <<
+ ":MBB ID#" << MBB->getNumber() << " ***\n";
+ }
+#endif
+
// Initialize register live-range state for scheduling in this block.
- Scheduler.GenerateLivenessForKills = false;
Scheduler.StartBlock(MBB);
// Schedule each sequence of instructions not interrupted by a label
@@ -224,7 +268,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
MachineInstr *MI = prior(I);
if (isSchedulingBoundary(MI, Fn)) {
Scheduler.Run(MBB, I, Current, CurrentCount);
- Scheduler.EmitSchedule();
+ Scheduler.EmitSchedule(0);
Current = MI;
CurrentCount = Count - 1;
Scheduler.Observe(MI, CurrentCount);
@@ -236,16 +280,13 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
assert((MBB->begin() == Current || CurrentCount != 0) &&
"Instruction count mismatch!");
Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
- Scheduler.EmitSchedule();
+ Scheduler.EmitSchedule(0);
// Clean up register live-range state.
Scheduler.FinishBlock();
- // Initialize register live-range state again and update register kills
- Scheduler.GenerateLivenessForKills = true;
- Scheduler.StartBlock(MBB);
+ // Update register kills
Scheduler.FixupKills(MBB);
- Scheduler.FinishBlock();
}
return true;
@@ -269,8 +310,13 @@ void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
std::fill(KillIndices, array_endof(KillIndices), ~0u);
std::fill(DefIndices, array_endof(DefIndices), BB->size());
+ // Clear "do not change" set.
+ KeepRegs.clear();
+
+ bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
+
// Determine the live-out physregs for this block.
- if (!BB->empty() && BB->back().getDesc().isReturn())
+ if (IsReturnBlock) {
// In a return block, examine the function live-out regs.
for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
E = MRI.liveout_end(); I != E; ++I) {
@@ -286,7 +332,7 @@ void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
DefIndices[AliasReg] = ~0u;
}
}
- else
+ } else {
// In a non-return block, examine the live-in regs of all successors.
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
SE = BB->succ_end(); SI != SE; ++SI)
@@ -304,29 +350,25 @@ void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
DefIndices[AliasReg] = ~0u;
}
}
+ }
- if (!GenerateLivenessForKills) {
- // Consider callee-saved registers as live-out, since we're running after
- // prologue/epilogue insertion so there's no way to add additional
- // saved registers.
- //
- // TODO: If the callee saves and restores these, then we can potentially
- // use them between the save and the restore. To do that, we could scan
- // the exit blocks to see which of these registers are defined.
- // Alternatively, callee-saved registers that aren't saved and restored
- // could be marked live-in in every block.
- for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
- unsigned Reg = *I;
- Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
- KillIndices[Reg] = BB->size();
- DefIndices[Reg] = ~0u;
- // Repeat, for all aliases.
- for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
- unsigned AliasReg = *Alias;
- Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
- KillIndices[AliasReg] = BB->size();
- DefIndices[AliasReg] = ~0u;
- }
+ // Mark live-out callee-saved registers. In a return block this is
+ // all callee-saved registers. In non-return this is any
+ // callee-saved register that is not saved in the prolog.
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ BitVector Pristine = MFI->getPristineRegs(BB);
+ for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
+ unsigned Reg = *I;
+ if (!IsReturnBlock && !Pristine.test(Reg)) continue;
+ Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
+ KillIndices[Reg] = BB->size();
+ DefIndices[Reg] = ~0u;
+ // Repeat, for all aliases.
+ for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
+ unsigned AliasReg = *Alias;
+ Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
+ KillIndices[AliasReg] = BB->size();
+ DefIndices[AliasReg] = ~0u;
}
}
}
@@ -454,6 +496,16 @@ void SchedulePostRATDList::PrescanInstruction(MachineInstr *MI) {
// If we're still willing to consider this register, note the reference.
if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
RegRefs.insert(std::make_pair(Reg, &MO));
+
+ // It's not safe to change register allocation for source operands of
+ // that have special allocation requirements.
+ if (MO.isUse() && MI->getDesc().hasExtraSrcRegAllocReq()) {
+ if (KeepRegs.insert(Reg)) {
+ for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
+ *Subreg; ++Subreg)
+ KeepRegs.insert(*Subreg);
+ }
+ }
}
}
@@ -473,9 +525,10 @@ void SchedulePostRATDList::ScanInstruction(MachineInstr *MI,
DefIndices[Reg] = Count;
KillIndices[Reg] = ~0u;
- assert(((KillIndices[Reg] == ~0u) !=
- (DefIndices[Reg] == ~0u)) &&
- "Kill and Def maps aren't consistent for Reg!");
+ assert(((KillIndices[Reg] == ~0u) !=
+ (DefIndices[Reg] == ~0u)) &&
+ "Kill and Def maps aren't consistent for Reg!");
+ KeepRegs.erase(Reg);
Classes[Reg] = 0;
RegRefs.erase(Reg);
// Repeat, for all subregs.
@@ -484,6 +537,7 @@ void SchedulePostRATDList::ScanInstruction(MachineInstr *MI,
unsigned SubregReg = *Subreg;
DefIndices[SubregReg] = Count;
KillIndices[SubregReg] = ~0u;
+ KeepRegs.erase(SubregReg);
Classes[SubregReg] = 0;
RegRefs.erase(SubregReg);
}
@@ -639,13 +693,6 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
I != E; --Count) {
MachineInstr *MI = --I;
- // After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
- // dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
- // is left behind appearing to clobber the super-register, while the
- // subregister needs to remain live. So we just ignore them.
- if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
- continue;
-
// Check if this instruction has a dependence on the critical path that
// is an anti-dependence that we may be able to break. If it is, set
// AntiDepReg to the non-zero register associated with the anti-dependence.
@@ -668,8 +715,12 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
if (Edge->getKind() == SDep::Anti) {
AntiDepReg = Edge->getReg();
assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
- // Don't break anti-dependencies on non-allocatable registers.
if (!AllocatableSet.test(AntiDepReg))
+ // Don't break anti-dependencies on non-allocatable registers.
+ AntiDepReg = 0;
+ else if (KeepRegs.count(AntiDepReg))
+ // Don't break anti-dependencies if an use down below requires
+ // this exact register.
AntiDepReg = 0;
else {
// If the SUnit has other dependencies on the SUnit that it
@@ -701,16 +752,22 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
PrescanInstruction(MI);
- // If this instruction has a use of AntiDepReg, breaking it
- // is invalid.
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
- if (Reg == 0) continue;
- if (MO.isUse() && AntiDepReg == Reg) {
- AntiDepReg = 0;
- break;
+ if (MI->getDesc().hasExtraDefRegAllocReq())
+ // If this instruction's defs have special allocation requirement, don't
+ // break this anti-dependency.
+ AntiDepReg = 0;
+ else if (AntiDepReg) {
+ // If this instruction has a use of AntiDepReg, breaking it
+ // is invalid.
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isReg()) continue;
+ unsigned Reg = MO.getReg();
+ if (Reg == 0) continue;
+ if (MO.isUse() && AntiDepReg == Reg) {
+ AntiDepReg = 0;
+ break;
+ }
}
}
@@ -773,6 +830,78 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
return Changed;
}
+/// StartBlockForKills - Initialize register live-range state for updating kills
+///
+void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
+ // Initialize the indices to indicate that no registers are live.
+ std::fill(KillIndices, array_endof(KillIndices), ~0u);
+
+ // Determine the live-out physregs for this block.
+ if (!BB->empty() && BB->back().getDesc().isReturn()) {
+ // In a return block, examine the function live-out regs.
+ for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
+ E = MRI.liveout_end(); I != E; ++I) {
+ unsigned Reg = *I;
+ KillIndices[Reg] = BB->size();
+ // Repeat, for all subregs.
+ for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
+ *Subreg; ++Subreg) {
+ KillIndices[*Subreg] = BB->size();
+ }
+ }
+ }
+ else {
+ // In a non-return block, examine the live-in regs of all successors.
+ for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
+ SE = BB->succ_end(); SI != SE; ++SI) {
+ for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
+ E = (*SI)->livein_end(); I != E; ++I) {
+ unsigned Reg = *I;
+ KillIndices[Reg] = BB->size();
+ // Repeat, for all subregs.
+ for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
+ *Subreg; ++Subreg) {
+ KillIndices[*Subreg] = BB->size();
+ }
+ }
+ }
+ }
+}
+
+bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
+ MachineOperand &MO) {
+ // Setting kill flag...
+ if (!MO.isKill()) {
+ MO.setIsKill(true);
+ return false;
+ }
+
+ // If MO itself is live, clear the kill flag...
+ if (KillIndices[MO.getReg()] != ~0u) {
+ MO.setIsKill(false);
+ return false;
+ }
+
+ // If any subreg of MO is live, then create an imp-def for that
+ // subreg and keep MO marked as killed.
+ bool AllDead = true;
+ const unsigned SuperReg = MO.getReg();
+ for (const unsigned *Subreg = TRI->getSubRegisters(SuperReg);
+ *Subreg; ++Subreg) {
+ if (KillIndices[*Subreg] != ~0u) {
+ MI->addOperand(MachineOperand::CreateReg(*Subreg,
+ true /*IsDef*/,
+ true /*IsImp*/,
+ false /*IsKill*/,
+ false /*IsDead*/));
+ AllDead = false;
+ }
+ }
+
+ MO.setIsKill(AllDead);
+ return false;
+}
+
/// FixupKills - Fix the register kill flags, they may have been made
/// incorrect by instruction reordering.
///
@@ -781,6 +910,8 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
std::set<unsigned> killedRegs;
BitVector ReservedRegs = TRI->getReservedRegs(MF);
+
+ StartBlockForKills(MBB);
// Examine block from end to start...
unsigned Count = MBB->size();
@@ -788,7 +919,6 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
I != E; --Count) {
MachineInstr *MI = --I;
- DEBUG(MI->dump());
// Update liveness. Registers that are defed but not used in this
// instruction are now dead. Mark register and all subregs as they
// are completely defined.
@@ -801,8 +931,6 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
// Ignore two-addr defs.
if (MI->isRegTiedToUseOperand(i)) continue;
- DEBUG(errs() << "*** Handling Defs " << TM.getRegisterInfo()->get(Reg).Name << '\n');
-
KillIndices[Reg] = ~0u;
// Repeat for all subregs.
@@ -812,9 +940,9 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
}
}
- // Examine all used registers and set kill flag. When a register
- // is used multiple times we only set the kill flag on the first
- // use.
+ // Examine all used registers and set/clear kill flag. When a
+ // register is used multiple times we only set the kill flag on
+ // the first use.
killedRegs.clear();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
@@ -822,8 +950,6 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
unsigned Reg = MO.getReg();
if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
- DEBUG(errs() << "*** Handling Uses " << TM.getRegisterInfo()->get(Reg).Name << '\n');
-
bool kill = false;
if (killedRegs.find(Reg) == killedRegs.end()) {
kill = true;
@@ -843,22 +969,26 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
}
if (MO.isKill() != kill) {
- MO.setIsKill(kill);
- DEBUG(errs() << "Fixed " << MO << " in ");
+ bool removed = ToggleKillFlag(MI, MO);
+ if (removed) {
+ DEBUG(errs() << "Fixed <removed> in ");
+ } else {
+ DEBUG(errs() << "Fixed " << MO << " in ");
+ }
DEBUG(MI->dump());
}
killedRegs.insert(Reg);
}
- // Mark any used register and subregs as now live...
+ // Mark any used register (that is not using undef) and subregs as
+ // now live...
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isUse()) continue;
+ if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
unsigned Reg = MO.getReg();
if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
- DEBUG(errs() << "Killing " << TM.getRegisterInfo()->get(Reg).Name << '\n');
KillIndices[Reg] = Count;
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
@@ -877,17 +1007,17 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
/// the PendingQueue if the count reaches zero. Also update its cycle bound.
void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
SUnit *SuccSU = SuccEdge->getSUnit();
- --SuccSU->NumPredsLeft;
-
+
#ifndef NDEBUG
- if (SuccSU->NumPredsLeft < 0) {
+ if (SuccSU->NumPredsLeft == 0) {
errs() << "*** Scheduling failed! ***\n";
SuccSU->dump(this);
errs() << " has been released too many times!\n";
llvm_unreachable(0);
}
#endif
-
+ --SuccSU->NumPredsLeft;
+
// Compute how many cycles it will be before this actually becomes
// available. This is the max of the start time of all predecessors plus
// their latencies.
@@ -941,7 +1071,7 @@ void SchedulePostRATDList::ListScheduleTopDown() {
// In any cycle where we can't schedule any instructions, we must
// stall or emit a noop, depending on the target.
- bool CycleInstCnt = 0;
+ bool CycleHasInsts = false;
// While Available queue is not empty, grab the node with the highest
// priority. If it is not ready put it back. Schedule the node.
@@ -999,7 +1129,7 @@ void SchedulePostRATDList::ListScheduleTopDown() {
if (FoundSUnit) {
ScheduleNodeTopDown(FoundSUnit, CurCycle);
HazardRec->EmitInstruction(FoundSUnit);
- CycleInstCnt++;
+ CycleHasInsts = true;
// If we are using the target-specific hazards, then don't
// advance the cycle time just because we schedule a node. If
@@ -1010,7 +1140,7 @@ void SchedulePostRATDList::ListScheduleTopDown() {
++CurCycle;
}
} else {
- if (CycleInstCnt > 0) {
+ if (CycleHasInsts) {
DEBUG(errs() << "*** Finished cycle " << CurCycle << '\n');
HazardRec->AdvanceCycle();
} else if (!HasNoopHazards) {
@@ -1030,7 +1160,7 @@ void SchedulePostRATDList::ListScheduleTopDown() {
}
++CurCycle;
- CycleInstCnt = 0;
+ CycleHasInsts = false;
}
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/PreAllocSplitting.cpp b/libclamav/c++/llvm/lib/CodeGen/PreAllocSplitting.cpp
index f12ad77..2e20dc1 100644
--- a/libclamav/c++/llvm/lib/CodeGen/PreAllocSplitting.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/PreAllocSplitting.cpp
@@ -68,7 +68,7 @@ namespace {
MachineBasicBlock *BarrierMBB;
// Barrier - Current barrier index.
- unsigned BarrierIdx;
+ MachineInstrIndex BarrierIdx;
// CurrLI - Current live interval being split.
LiveInterval *CurrLI;
@@ -83,7 +83,7 @@ namespace {
DenseMap<unsigned, int> IntervalSSMap;
// Def2SpillMap - A map from a def instruction index to spill index.
- DenseMap<unsigned, unsigned> Def2SpillMap;
+ DenseMap<MachineInstrIndex, MachineInstrIndex> Def2SpillMap;
public:
static char ID;
@@ -129,22 +129,23 @@ namespace {
private:
MachineBasicBlock::iterator
findNextEmptySlot(MachineBasicBlock*, MachineInstr*,
- unsigned&);
+ MachineInstrIndex&);
MachineBasicBlock::iterator
findSpillPoint(MachineBasicBlock*, MachineInstr*, MachineInstr*,
- SmallPtrSet<MachineInstr*, 4>&, unsigned&);
+ SmallPtrSet<MachineInstr*, 4>&, MachineInstrIndex&);
MachineBasicBlock::iterator
- findRestorePoint(MachineBasicBlock*, MachineInstr*, unsigned,
- SmallPtrSet<MachineInstr*, 4>&, unsigned&);
+ findRestorePoint(MachineBasicBlock*, MachineInstr*, MachineInstrIndex,
+ SmallPtrSet<MachineInstr*, 4>&, MachineInstrIndex&);
int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
- bool IsAvailableInStack(MachineBasicBlock*, unsigned, unsigned, unsigned,
- unsigned&, int&) const;
+ bool IsAvailableInStack(MachineBasicBlock*, unsigned,
+ MachineInstrIndex, MachineInstrIndex,
+ MachineInstrIndex&, int&) const;
- void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned);
+ void UpdateSpillSlotInterval(VNInfo*, MachineInstrIndex, MachineInstrIndex);
bool SplitRegLiveInterval(LiveInterval*);
@@ -156,7 +157,7 @@ namespace {
bool Rematerialize(unsigned vreg, VNInfo* ValNo,
MachineInstr* DefMI,
MachineBasicBlock::iterator RestorePt,
- unsigned RestoreIdx,
+ MachineInstrIndex RestoreIdx,
SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
MachineInstr* FoldSpill(unsigned vreg, const TargetRegisterClass* RC,
MachineInstr* DefMI,
@@ -208,11 +209,12 @@ const PassInfo *const llvm::PreAllocSplittingID = &X;
/// instruction index map. If there isn't one, return end().
MachineBasicBlock::iterator
PreAllocSplitting::findNextEmptySlot(MachineBasicBlock *MBB, MachineInstr *MI,
- unsigned &SpotIndex) {
+ MachineInstrIndex &SpotIndex) {
MachineBasicBlock::iterator MII = MI;
if (++MII != MBB->end()) {
- unsigned Index = LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
- if (Index) {
+ MachineInstrIndex Index =
+ LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
+ if (Index != MachineInstrIndex()) {
SpotIndex = Index;
return MII;
}
@@ -228,7 +230,7 @@ MachineBasicBlock::iterator
PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
MachineInstr *DefMI,
SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
- unsigned &SpillIndex) {
+ MachineInstrIndex &SpillIndex) {
MachineBasicBlock::iterator Pt = MBB->begin();
MachineBasicBlock::iterator MII = MI;
@@ -241,7 +243,7 @@ PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
while (MII != EndPt && !RefsInMBB.count(MII)) {
- unsigned Index = LIs->getInstructionIndex(MII);
+ MachineInstrIndex Index = LIs->getInstructionIndex(MII);
// We can't insert the spill between the barrier (a call), and its
// corresponding call frame setup.
@@ -274,9 +276,9 @@ PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
/// found.
MachineBasicBlock::iterator
PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
- unsigned LastIdx,
+ MachineInstrIndex LastIdx,
SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
- unsigned &RestoreIndex) {
+ MachineInstrIndex &RestoreIndex) {
// FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
// begin index accordingly.
MachineBasicBlock::iterator Pt = MBB->end();
@@ -297,10 +299,10 @@ PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
// FIXME: Limit the number of instructions to examine to reduce
// compile time?
while (MII != EndPt) {
- unsigned Index = LIs->getInstructionIndex(MII);
+ MachineInstrIndex Index = LIs->getInstructionIndex(MII);
if (Index > LastIdx)
break;
- unsigned Gap = LIs->findGapBeforeInstr(Index);
+ MachineInstrIndex Gap = LIs->findGapBeforeInstr(Index);
// We can't insert a restore between the barrier (a call) and its
// corresponding call frame teardown.
@@ -309,7 +311,7 @@ PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
++MII;
} while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode());
- } else if (Gap) {
+ } else if (Gap != MachineInstrIndex()) {
Pt = MII;
RestoreIndex = Gap;
}
@@ -342,7 +344,8 @@ int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
if (CurrSLI->hasAtLeastOneValue())
CurrSValNo = CurrSLI->getValNumInfo(0);
else
- CurrSValNo = CurrSLI->getNextValue(0, 0, false, LSs->getVNInfoAllocator());
+ CurrSValNo = CurrSLI->getNextValue(MachineInstrIndex(), 0, false,
+ LSs->getVNInfoAllocator());
return SS;
}
@@ -350,8 +353,9 @@ int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
/// slot at the specified index.
bool
PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
- unsigned Reg, unsigned DefIndex,
- unsigned RestoreIndex, unsigned &SpillIndex,
+ unsigned Reg, MachineInstrIndex DefIndex,
+ MachineInstrIndex RestoreIndex,
+ MachineInstrIndex &SpillIndex,
int& SS) const {
if (!DefMBB)
return false;
@@ -359,7 +363,8 @@ PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
if (I == IntervalSSMap.end())
return false;
- DenseMap<unsigned, unsigned>::iterator II = Def2SpillMap.find(DefIndex);
+ DenseMap<MachineInstrIndex, MachineInstrIndex>::iterator
+ II = Def2SpillMap.find(DefIndex);
if (II == Def2SpillMap.end())
return false;
@@ -379,8 +384,8 @@ PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
/// interval being split, and the spill and restore indicies, update the live
/// interval of the spill stack slot.
void
-PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
- unsigned RestoreIndex) {
+PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, MachineInstrIndex SpillIndex,
+ MachineInstrIndex RestoreIndex) {
assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
"Expect restore in the barrier mbb");
@@ -393,8 +398,8 @@ PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
}
SmallPtrSet<MachineBasicBlock*, 4> Processed;
- unsigned EndIdx = LIs->getMBBEndIdx(MBB);
- LiveRange SLR(SpillIndex, EndIdx+1, CurrSValNo);
+ MachineInstrIndex EndIdx = LIs->getMBBEndIdx(MBB);
+ LiveRange SLR(SpillIndex, LIs->getNextSlot(EndIdx), CurrSValNo);
CurrSLI->addRange(SLR);
Processed.insert(MBB);
@@ -413,7 +418,7 @@ PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
WorkList.pop_back();
if (Processed.count(MBB))
continue;
- unsigned Idx = LIs->getMBBStartIdx(MBB);
+ MachineInstrIndex Idx = LIs->getMBBStartIdx(MBB);
LR = CurrLI->getLiveRangeContaining(Idx);
if (LR && LR->valno == ValNo) {
EndIdx = LIs->getMBBEndIdx(MBB);
@@ -423,7 +428,7 @@ PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
CurrSLI->addRange(SLR);
} else if (LR->end > EndIdx) {
// Live range extends beyond end of mbb, process successors.
- LiveRange SLR(Idx, EndIdx+1, CurrSValNo);
+ LiveRange SLR(Idx, LIs->getNextIndex(EndIdx), CurrSValNo);
CurrSLI->addRange(SLR);
for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
SE = MBB->succ_end(); SI != SE; ++SI)
@@ -486,12 +491,12 @@ PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI,
}
// Once we've found it, extend its VNInfo to our instruction.
- unsigned DefIndex = LIs->getInstructionIndex(Walker);
- DefIndex = LiveIntervals::getDefIndex(DefIndex);
- unsigned EndIndex = LIs->getMBBEndIdx(MBB);
+ MachineInstrIndex DefIndex = LIs->getInstructionIndex(Walker);
+ DefIndex = LIs->getDefIndex(DefIndex);
+ MachineInstrIndex EndIndex = LIs->getMBBEndIdx(MBB);
RetVNI = NewVNs[Walker];
- LI->addRange(LiveRange(DefIndex, EndIndex+1, RetVNI));
+ LI->addRange(LiveRange(DefIndex, LIs->getNextSlot(EndIndex), RetVNI));
} else if (!ContainsDefs && ContainsUses) {
SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
@@ -523,12 +528,12 @@ PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI,
IsTopLevel, IsIntraBlock);
}
- unsigned UseIndex = LIs->getInstructionIndex(Walker);
- UseIndex = LiveIntervals::getUseIndex(UseIndex);
- unsigned EndIndex = 0;
+ MachineInstrIndex UseIndex = LIs->getInstructionIndex(Walker);
+ UseIndex = LIs->getUseIndex(UseIndex);
+ MachineInstrIndex EndIndex;
if (IsIntraBlock) {
EndIndex = LIs->getInstructionIndex(UseI);
- EndIndex = LiveIntervals::getUseIndex(EndIndex);
+ EndIndex = LIs->getUseIndex(EndIndex);
} else
EndIndex = LIs->getMBBEndIdx(MBB);
@@ -537,12 +542,12 @@ PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI,
RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
NewVNs, LiveOut, Phis, false, true);
- LI->addRange(LiveRange(UseIndex, EndIndex+1, RetVNI));
+ LI->addRange(LiveRange(UseIndex, LIs->getNextSlot(EndIndex), RetVNI));
// FIXME: Need to set kills properly for inter-block stuff.
- if (LI->isKill(RetVNI, UseIndex)) LI->removeKill(RetVNI, UseIndex);
+ if (RetVNI->isKill(UseIndex)) RetVNI->removeKill(UseIndex);
if (IsIntraBlock)
- LI->addKill(RetVNI, EndIndex, false);
+ RetVNI->addKill(EndIndex);
} else if (ContainsDefs && ContainsUses) {
SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
@@ -583,13 +588,13 @@ PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI,
IsTopLevel, IsIntraBlock);
}
- unsigned StartIndex = LIs->getInstructionIndex(Walker);
- StartIndex = foundDef ? LiveIntervals::getDefIndex(StartIndex) :
- LiveIntervals::getUseIndex(StartIndex);
- unsigned EndIndex = 0;
+ MachineInstrIndex StartIndex = LIs->getInstructionIndex(Walker);
+ StartIndex = foundDef ? LIs->getDefIndex(StartIndex) :
+ LIs->getUseIndex(StartIndex);
+ MachineInstrIndex EndIndex;
if (IsIntraBlock) {
EndIndex = LIs->getInstructionIndex(UseI);
- EndIndex = LiveIntervals::getUseIndex(EndIndex);
+ EndIndex = LIs->getUseIndex(EndIndex);
} else
EndIndex = LIs->getMBBEndIdx(MBB);
@@ -599,12 +604,12 @@ PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI,
RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
NewVNs, LiveOut, Phis, false, true);
- LI->addRange(LiveRange(StartIndex, EndIndex+1, RetVNI));
+ LI->addRange(LiveRange(StartIndex, LIs->getNextSlot(EndIndex), RetVNI));
- if (foundUse && LI->isKill(RetVNI, StartIndex))
- LI->removeKill(RetVNI, StartIndex);
+ if (foundUse && RetVNI->isKill(StartIndex))
+ RetVNI->removeKill(StartIndex);
if (IsIntraBlock) {
- LI->addKill(RetVNI, EndIndex, false);
+ RetVNI->addKill(EndIndex);
}
}
@@ -635,9 +640,10 @@ PreAllocSplitting::PerformPHIConstructionFallBack(MachineBasicBlock::iterator Us
// assume that we are not intrablock here.
if (Phis.count(MBB)) return Phis[MBB];
- unsigned StartIndex = LIs->getMBBStartIdx(MBB);
+ MachineInstrIndex StartIndex = LIs->getMBBStartIdx(MBB);
VNInfo *RetVNI = Phis[MBB] =
- LI->getNextValue(0, /*FIXME*/ 0, false, LIs->getVNInfoAllocator());
+ LI->getNextValue(MachineInstrIndex(), /*FIXME*/ 0, false,
+ LIs->getVNInfoAllocator());
if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
@@ -679,21 +685,21 @@ PreAllocSplitting::PerformPHIConstructionFallBack(MachineBasicBlock::iterator Us
for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator I =
IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) {
I->second->setHasPHIKill(true);
- unsigned KillIndex = LIs->getMBBEndIdx(I->first);
- if (!LiveInterval::isKill(I->second, KillIndex))
- LI->addKill(I->second, KillIndex, false);
+ MachineInstrIndex KillIndex = LIs->getMBBEndIdx(I->first);
+ if (!I->second->isKill(KillIndex))
+ I->second->addKill(KillIndex);
}
}
- unsigned EndIndex = 0;
+ MachineInstrIndex EndIndex;
if (IsIntraBlock) {
EndIndex = LIs->getInstructionIndex(UseI);
- EndIndex = LiveIntervals::getUseIndex(EndIndex);
+ EndIndex = LIs->getUseIndex(EndIndex);
} else
EndIndex = LIs->getMBBEndIdx(MBB);
- LI->addRange(LiveRange(StartIndex, EndIndex+1, RetVNI));
+ LI->addRange(LiveRange(StartIndex, LIs->getNextSlot(EndIndex), RetVNI));
if (IsIntraBlock)
- LI->addKill(RetVNI, EndIndex, false);
+ RetVNI->addKill(EndIndex);
// Memoize results so we don't have to recompute them.
if (!IsIntraBlock)
@@ -727,8 +733,8 @@ void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) {
DE = MRI->def_end(); DI != DE; ++DI) {
Defs[(*DI).getParent()].insert(&*DI);
- unsigned DefIdx = LIs->getInstructionIndex(&*DI);
- DefIdx = LiveIntervals::getDefIndex(DefIdx);
+ MachineInstrIndex DefIdx = LIs->getInstructionIndex(&*DI);
+ DefIdx = LIs->getDefIndex(DefIdx);
assert(DI->getOpcode() != TargetInstrInfo::PHI &&
"Following NewVN isPHIDef flag incorrect. Fix me!");
@@ -763,14 +769,14 @@ void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) {
// Add ranges for dead defs
for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
DE = MRI->def_end(); DI != DE; ++DI) {
- unsigned DefIdx = LIs->getInstructionIndex(&*DI);
- DefIdx = LiveIntervals::getDefIndex(DefIdx);
+ MachineInstrIndex DefIdx = LIs->getInstructionIndex(&*DI);
+ DefIdx = LIs->getDefIndex(DefIdx);
if (LI->liveAt(DefIdx)) continue;
VNInfo* DeadVN = NewVNs[&*DI];
- LI->addRange(LiveRange(DefIdx, DefIdx+1, DeadVN));
- LI->addKill(DeadVN, DefIdx, false);
+ LI->addRange(LiveRange(DefIdx, LIs->getNextSlot(DefIdx), DeadVN));
+ DeadVN->addKill(DefIdx);
}
}
@@ -802,13 +808,14 @@ void PreAllocSplitting::RenumberValno(VNInfo* VN) {
// Locate two-address redefinitions
for (VNInfo::KillSet::iterator KI = OldVN->kills.begin(),
KE = OldVN->kills.end(); KI != KE; ++KI) {
- assert(!KI->isPHIKill && "VN previously reported having no PHI kills.");
- MachineInstr* MI = LIs->getInstructionFromIndex(KI->killIdx);
+ assert(!KI->isPHIIndex() &&
+ "VN previously reported having no PHI kills.");
+ MachineInstr* MI = LIs->getInstructionFromIndex(*KI);
unsigned DefIdx = MI->findRegisterDefOperandIdx(CurrLI->reg);
if (DefIdx == ~0U) continue;
if (MI->isRegTiedToUseOperand(DefIdx)) {
VNInfo* NextVN =
- CurrLI->findDefinedVNInfo(LiveIntervals::getDefIndex(KI->killIdx));
+ CurrLI->findDefinedVNInfoForRegInt(LIs->getDefIndex(*KI));
if (NextVN == OldVN) continue;
Stack.push_back(NextVN);
}
@@ -840,10 +847,10 @@ void PreAllocSplitting::RenumberValno(VNInfo* VN) {
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
E = MRI->reg_end(); I != E; ++I) {
MachineOperand& MO = I.getOperand();
- unsigned InstrIdx = LIs->getInstructionIndex(&*I);
+ MachineInstrIndex InstrIdx = LIs->getInstructionIndex(&*I);
- if ((MO.isUse() && NewLI.liveAt(LiveIntervals::getUseIndex(InstrIdx))) ||
- (MO.isDef() && NewLI.liveAt(LiveIntervals::getDefIndex(InstrIdx))))
+ if ((MO.isUse() && NewLI.liveAt(LIs->getUseIndex(InstrIdx))) ||
+ (MO.isDef() && NewLI.liveAt(LIs->getDefIndex(InstrIdx))))
OpsToChange.push_back(std::make_pair(&*I, I.getOperandNo()));
}
@@ -868,12 +875,12 @@ void PreAllocSplitting::RenumberValno(VNInfo* VN) {
bool PreAllocSplitting::Rematerialize(unsigned VReg, VNInfo* ValNo,
MachineInstr* DefMI,
MachineBasicBlock::iterator RestorePt,
- unsigned RestoreIdx,
+ MachineInstrIndex RestoreIdx,
SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
MachineBasicBlock& MBB = *RestorePt->getParent();
MachineBasicBlock::iterator KillPt = BarrierMBB->end();
- unsigned KillIdx = 0;
+ MachineInstrIndex KillIdx;
if (!ValNo->isDefAccurate() || DefMI->getParent() == BarrierMBB)
KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, KillIdx);
else
@@ -886,9 +893,9 @@ bool PreAllocSplitting::Rematerialize(unsigned VReg, VNInfo* ValNo,
LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx);
ReconstructLiveInterval(CurrLI);
- unsigned RematIdx = LIs->getInstructionIndex(prior(RestorePt));
- RematIdx = LiveIntervals::getDefIndex(RematIdx);
- RenumberValno(CurrLI->findDefinedVNInfo(RematIdx));
+ MachineInstrIndex RematIdx = LIs->getInstructionIndex(prior(RestorePt));
+ RematIdx = LIs->getDefIndex(RematIdx);
+ RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RematIdx));
++NumSplits;
++NumRemats;
@@ -943,7 +950,8 @@ MachineInstr* PreAllocSplitting::FoldSpill(unsigned vreg,
if (CurrSLI->hasAtLeastOneValue())
CurrSValNo = CurrSLI->getValNumInfo(0);
else
- CurrSValNo = CurrSLI->getNextValue(0, 0, false, LSs->getVNInfoAllocator());
+ CurrSValNo = CurrSLI->getNextValue(MachineInstrIndex(), 0, false,
+ LSs->getVNInfoAllocator());
}
return FMI;
@@ -1052,7 +1060,7 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
}
// Find a point to restore the value after the barrier.
- unsigned RestoreIndex = 0;
+ MachineInstrIndex RestoreIndex;
MachineBasicBlock::iterator RestorePt =
findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB, RestoreIndex);
if (RestorePt == BarrierMBB->end())
@@ -1066,7 +1074,7 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
// Add a spill either before the barrier or after the definition.
MachineBasicBlock *DefMBB = DefMI ? DefMI->getParent() : NULL;
const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg);
- unsigned SpillIndex = 0;
+ MachineInstrIndex SpillIndex;
MachineInstr *SpillMI = NULL;
int SS = -1;
if (!ValNo->isDefAccurate()) {
@@ -1138,15 +1146,15 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
}
// Update spill stack slot live interval.
- UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
+ UpdateSpillSlotInterval(ValNo, LIs->getNextSlot(LIs->getUseIndex(SpillIndex)),
LIs->getDefIndex(RestoreIndex));
ReconstructLiveInterval(CurrLI);
if (!FoldedRestore) {
- unsigned RestoreIdx = LIs->getInstructionIndex(prior(RestorePt));
- RestoreIdx = LiveIntervals::getDefIndex(RestoreIdx);
- RenumberValno(CurrLI->findDefinedVNInfo(RestoreIdx));
+ MachineInstrIndex RestoreIdx = LIs->getInstructionIndex(prior(RestorePt));
+ RestoreIdx = LIs->getDefIndex(RestoreIdx);
+ RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RestoreIdx));
}
++NumSplits;
@@ -1232,8 +1240,8 @@ bool PreAllocSplitting::removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split) {
// reaching definition (VNInfo).
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin((*LI)->reg),
UE = MRI->use_end(); UI != UE; ++UI) {
- unsigned index = LIs->getInstructionIndex(&*UI);
- index = LiveIntervals::getUseIndex(index);
+ MachineInstrIndex index = LIs->getInstructionIndex(&*UI);
+ index = LIs->getUseIndex(index);
const LiveRange* LR = (*LI)->getLiveRangeContaining(index);
VNUseCount[LR->valno].insert(&*UI);
@@ -1382,7 +1390,7 @@ bool PreAllocSplitting::createsNewJoin(LiveRange* LR,
if (LR->valno->hasPHIKill())
return false;
- unsigned MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
+ MachineInstrIndex MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
if (LR->end < MBBEnd)
return false;
diff --git a/libclamav/c++/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/libclamav/c++/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 061ac2a..51c78a1 100644
--- a/libclamav/c++/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -31,7 +31,9 @@
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/STLExtras.h"
#include <climits>
@@ -42,6 +44,16 @@ char PEI::ID = 0;
static RegisterPass<PEI>
X("prologepilog", "Prologue/Epilogue Insertion");
+// FIXME: For now, the frame index scavenging is off by default and only
+// used by the Thumb1 target. When it's the default and replaces the current
+// on-the-fly PEI scavenging for all targets, requiresRegisterScavenging()
+// will replace this.
+cl::opt<bool>
+FrameIndexVirtualScavenging("enable-frame-index-scavenging",
+ cl::Hidden,
+ cl::desc("Enable frame index elimination with"
+ "virtual register scavenging"));
+
/// createPrologEpilogCodeInserter - This function returns a pass that inserts
/// prolog and epilog code, and eliminates abstract frame references.
///
@@ -104,6 +116,12 @@ bool PEI::runOnMachineFunction(MachineFunction &Fn) {
//
replaceFrameIndices(Fn);
+ // If register scavenging is needed, as we've enabled doing it as a
+ // post-pass, scavenge the virtual registers that frame index elimiation
+ // inserted.
+ if (TRI->requiresRegisterScavenging(Fn) && FrameIndexVirtualScavenging)
+ scavengeFrameVirtualRegs(Fn);
+
delete RS;
clearAllSets();
return true;
@@ -218,7 +236,7 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
return; // Early exit if no callee saved registers are modified!
unsigned NumFixedSpillSlots;
- const std::pair<unsigned,int> *FixedSpillSlots =
+ const TargetFrameInfo::SpillSlot *FixedSpillSlots =
TFI->getCalleeSavedSpillSlots(NumFixedSpillSlots);
// Now that we know which registers need to be saved and restored, allocate
@@ -236,9 +254,9 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
// Check to see if this physreg must be spilled to a particular stack slot
// on this target.
- const std::pair<unsigned,int> *FixedSlot = FixedSpillSlots;
+ const TargetFrameInfo::SpillSlot *FixedSlot = FixedSpillSlots;
while (FixedSlot != FixedSpillSlots+NumFixedSpillSlots &&
- FixedSlot->first != Reg)
+ FixedSlot->Reg != Reg)
++FixedSlot;
if (FixedSlot == FixedSpillSlots + NumFixedSpillSlots) {
@@ -255,7 +273,7 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
if ((unsigned)FrameIdx > MaxCSFrameIndex) MaxCSFrameIndex = FrameIdx;
} else {
// Spill it to the stack where we must.
- FrameIdx = FFI->CreateFixedObject(RC->getSize(), FixedSlot->second);
+ FrameIdx = FFI->CreateFixedObject(RC->getSize(), FixedSlot->Offset);
}
I->setFrameIdx(FrameIdx);
@@ -433,8 +451,7 @@ static inline void
AdjustStackOffset(MachineFrameInfo *FFI, int FrameIdx,
bool StackGrowsDown, int64_t &Offset,
unsigned &MaxAlign) {
- // If stack grows down, we need to add size of find the lowest address of the
- // object.
+ // If the stack grows down, add the object size to find the lowest address.
if (StackGrowsDown)
Offset += FFI->getObjectSize(FrameIdx);
@@ -467,16 +484,17 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
// Loop over all of the stack objects, assigning sequential addresses...
MachineFrameInfo *FFI = Fn.getFrameInfo();
- unsigned MaxAlign = FFI->getMaxAlignment();
+ unsigned MaxAlign = 1;
// Start at the beginning of the local area.
// The Offset is the distance from the stack top in the direction
// of stack growth -- so it's always nonnegative.
- int64_t Offset = TFI.getOffsetOfLocalArea();
+ int LocalAreaOffset = TFI.getOffsetOfLocalArea();
if (StackGrowsDown)
- Offset = -Offset;
- assert(Offset >= 0
+ LocalAreaOffset = -LocalAreaOffset;
+ assert(LocalAreaOffset >= 0
&& "Local area offset should be in direction of stack growth");
+ int64_t Offset = LocalAreaOffset;
// If there are fixed sized objects that are preallocated in the local area,
// non-fixed objects can't be allocated right at the start of local area.
@@ -568,32 +586,38 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
AdjustStackOffset(FFI, SFI, StackGrowsDown, Offset, MaxAlign);
}
- // Round up the size to a multiple of the alignment, but only if there are
- // calls or alloca's in the function. This ensures that any calls to
- // subroutines have their stack frames suitable aligned.
- // Also do this if we need runtime alignment of the stack. In this case
- // offsets will be relative to SP not FP; round up the stack size so this
- // works.
- if (!RegInfo->targetHandlesStackFrameRounding() &&
- (FFI->hasCalls() || FFI->hasVarSizedObjects() ||
- (RegInfo->needsStackRealignment(Fn) &&
- FFI->getObjectIndexEnd() != 0))) {
+ if (!RegInfo->targetHandlesStackFrameRounding()) {
// If we have reserved argument space for call sites in the function
// immediately on entry to the current function, count it as part of the
// overall stack size.
- if (RegInfo->hasReservedCallFrame(Fn))
+ if (FFI->hasCalls() && RegInfo->hasReservedCallFrame(Fn))
Offset += FFI->getMaxCallFrameSize();
- unsigned AlignMask = std::max(TFI.getStackAlignment(),MaxAlign) - 1;
+ // Round up the size to a multiple of the alignment. If the function has
+ // any calls or alloca's, align to the target's StackAlignment value to
+ // ensure that the callee's frame or the alloca data is suitably aligned;
+ // otherwise, for leaf functions, align to the TransientStackAlignment
+ // value.
+ unsigned StackAlign;
+ if (FFI->hasCalls() || FFI->hasVarSizedObjects() ||
+ (RegInfo->needsStackRealignment(Fn) && FFI->getObjectIndexEnd() != 0))
+ StackAlign = TFI.getStackAlignment();
+ else
+ StackAlign = TFI.getTransientStackAlignment();
+ // If the frame pointer is eliminated, all frame offsets will be relative
+ // to SP not FP; align to MaxAlign so this works.
+ StackAlign = std::max(StackAlign, MaxAlign);
+ unsigned AlignMask = StackAlign - 1;
Offset = (Offset + AlignMask) & ~uint64_t(AlignMask);
}
// Update frame info to pretend that this is part of the stack...
- FFI->setStackSize(Offset+TFI.getOffsetOfLocalArea());
+ FFI->setStackSize(Offset - LocalAreaOffset);
// Remember the required stack alignment in case targets need it to perform
// dynamic stack alignment.
- FFI->setMaxAlignment(MaxAlign);
+ if (MaxAlign > FFI->getMaxAlignment())
+ FFI->setMaxAlignment(MaxAlign);
}
@@ -634,7 +658,7 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) {
for (MachineFunction::iterator BB = Fn.begin(),
E = Fn.end(); BB != E; ++BB) {
int SPAdj = 0; // SP offset due to call frame setup / destroy.
- if (RS) RS->enterBasicBlock(BB);
+ if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB);
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) {
@@ -680,7 +704,8 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) {
// use that target machine register info object to eliminate
// it.
- TRI.eliminateFrameIndex(MI, SPAdj, RS);
+ TRI.eliminateFrameIndex(MI, SPAdj, FrameIndexVirtualScavenging ?
+ NULL : RS);
// Reset the iterator if we were at the beginning of the BB.
if (AtBeginning) {
@@ -695,10 +720,66 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) {
if (DoIncr && I != BB->end()) ++I;
// Update register states.
- if (RS && MI) RS->forward(MI);
+ if (RS && !FrameIndexVirtualScavenging && MI) RS->forward(MI);
}
assert(SPAdj == 0 && "Unbalanced call frame setup / destroy pairs?");
}
}
+/// scavengeFrameVirtualRegs - Replace all frame index virtual registers
+/// with physical registers. Use the register scavenger to find an
+/// appropriate register to use.
+void PEI::scavengeFrameVirtualRegs(MachineFunction &Fn) {
+ // Run through the instructions and find any virtual registers.
+ for (MachineFunction::iterator BB = Fn.begin(),
+ E = Fn.end(); BB != E; ++BB) {
+ RS->enterBasicBlock(BB);
+
+ unsigned CurrentVirtReg = 0;
+ unsigned CurrentScratchReg = 0;
+
+ for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I) {
+ MachineInstr *MI = I;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
+ if (MI->getOperand(i).isReg()) {
+ unsigned Reg = MI->getOperand(i).getReg();
+ if (Reg == 0)
+ continue;
+ if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
+ // If we have an active scavenged register, we shouldn't be
+ // seeing any references to it.
+ assert (Reg != CurrentScratchReg
+ && "overlapping use of scavenged frame index register!");
+ continue;
+ }
+
+ // If we already have a scratch for this virtual register, use it
+ if (Reg != CurrentVirtReg) {
+ // When we first encounter a new virtual register, it
+ // must be a definition.
+ assert(MI->getOperand(i).isDef() &&
+ "frame index virtual missing def!");
+ // We can't have nested virtual register live ranges because
+ // there's only a guarantee of one scavenged register at a time.
+ assert (CurrentVirtReg == 0 &&
+ "overlapping frame index virtual registers!");
+ CurrentVirtReg = Reg;
+ const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
+ CurrentScratchReg = RS->FindUnusedReg(RC);
+ if (CurrentScratchReg == 0)
+ // No register is "free". Scavenge a register.
+ // FIXME: Track SPAdj. Zero won't always be right
+ CurrentScratchReg = RS->scavengeRegister(RC, I, 0);
+ }
+ assert (CurrentScratchReg && "Missing scratch register!");
+ MI->getOperand(i).setReg(CurrentScratchReg);
+
+ // If this is the last use of the register, stop tracking it.
+ if (MI->getOperand(i).isKill())
+ CurrentScratchReg = CurrentVirtReg = 0;
+ }
+ RS->forward(MI);
+ }
+ }
+}
diff --git a/libclamav/c++/llvm/lib/CodeGen/PrologEpilogInserter.h b/libclamav/c++/llvm/lib/CodeGen/PrologEpilogInserter.h
index b143554..d0a68e1 100644
--- a/libclamav/c++/llvm/lib/CodeGen/PrologEpilogInserter.h
+++ b/libclamav/c++/llvm/lib/CodeGen/PrologEpilogInserter.h
@@ -123,6 +123,7 @@ namespace llvm {
void insertCSRSpillsAndRestores(MachineFunction &Fn);
void calculateFrameObjectOffsets(MachineFunction &Fn);
void replaceFrameIndices(MachineFunction &Fn);
+ void scavengeFrameVirtualRegs(MachineFunction &Fn);
void insertPrologEpilogCode(MachineFunction &Fn);
// Initialize DFA sets, called before iterations.
diff --git a/libclamav/c++/llvm/lib/CodeGen/PseudoSourceValue.cpp b/libclamav/c++/llvm/lib/CodeGen/PseudoSourceValue.cpp
index c440936..3728b7f 100644
--- a/libclamav/c++/llvm/lib/CodeGen/PseudoSourceValue.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/PseudoSourceValue.cpp
@@ -47,12 +47,8 @@ PseudoSourceValue::PseudoSourceValue() :
Value(PointerType::getUnqual(Type::getInt8Ty(getGlobalContext())),
PseudoSourceValueVal) {}
-void PseudoSourceValue::dump() const {
- print(errs()); errs() << '\n';
-}
-
-void PseudoSourceValue::print(raw_ostream &OS) const {
- OS << PSVNames[this - *PSVs];
+void PseudoSourceValue::printCustom(raw_ostream &O) const {
+ O << PSVNames[this - *PSVs];
}
namespace {
@@ -67,7 +63,7 @@ namespace {
virtual bool isConstant(const MachineFrameInfo *MFI) const;
- virtual void print(raw_ostream &OS) const {
+ virtual void printCustom(raw_ostream &OS) const {
OS << "FixedStack" << FI;
}
};
diff --git a/libclamav/c++/llvm/lib/CodeGen/RegAllocLinearScan.cpp b/libclamav/c++/llvm/lib/CodeGen/RegAllocLinearScan.cpp
index b2a20a7..9d22e13 100644
--- a/libclamav/c++/llvm/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/RegAllocLinearScan.cpp
@@ -176,11 +176,11 @@ namespace {
/// processActiveIntervals - expire old intervals and move non-overlapping
/// ones to the inactive list.
- void processActiveIntervals(unsigned CurPoint);
+ void processActiveIntervals(MachineInstrIndex CurPoint);
/// processInactiveIntervals - expire old intervals and move overlapping
/// ones to the active list.
- void processInactiveIntervals(unsigned CurPoint);
+ void processInactiveIntervals(MachineInstrIndex CurPoint);
/// hasNextReloadInterval - Return the next liveinterval that's being
/// defined by a reload from the same SS as the specified one.
@@ -366,7 +366,8 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
return Reg;
VNInfo *vni = cur.begin()->valno;
- if (!vni->def || vni->isUnused() || !vni->isDefAccurate())
+ if ((vni->def == MachineInstrIndex()) ||
+ vni->isUnused() || !vni->isDefAccurate())
return Reg;
MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
@@ -396,10 +397,10 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
// Remove unnecessary kills since a copy does not clobber the register.
if (li_->hasInterval(SrcReg)) {
LiveInterval &SrcLI = li_->getInterval(SrcReg);
- for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
- E = mri_->reg_end(); I != E; ++I) {
+ for (MachineRegisterInfo::use_iterator I = mri_->use_begin(cur.reg),
+ E = mri_->use_end(); I != E; ++I) {
MachineOperand &O = I.getOperand();
- if (!O.isUse() || !O.isKill())
+ if (!O.isKill())
continue;
MachineInstr *MI = &*I;
if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
@@ -503,8 +504,8 @@ void RALinScan::linearScan() {
DEBUG(errs() << "\n*** CURRENT ***: " << *cur << '\n');
if (!cur->empty()) {
- processActiveIntervals(cur->beginNumber());
- processInactiveIntervals(cur->beginNumber());
+ processActiveIntervals(cur->beginIndex());
+ processInactiveIntervals(cur->beginIndex());
assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
"Can only allocate virtual registers!");
@@ -585,7 +586,7 @@ void RALinScan::linearScan() {
/// processActiveIntervals - expire old intervals and move non-overlapping ones
/// to the inactive list.
-void RALinScan::processActiveIntervals(unsigned CurPoint)
+void RALinScan::processActiveIntervals(MachineInstrIndex CurPoint)
{
DEBUG(errs() << "\tprocessing active intervals:\n");
@@ -631,7 +632,7 @@ void RALinScan::processActiveIntervals(unsigned CurPoint)
/// processInactiveIntervals - expire old intervals and move overlapping
/// ones to the active list.
-void RALinScan::processInactiveIntervals(unsigned CurPoint)
+void RALinScan::processInactiveIntervals(MachineInstrIndex CurPoint)
{
DEBUG(errs() << "\tprocessing inactive intervals:\n");
@@ -712,7 +713,7 @@ FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
return IP.end();
}
-static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
+static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, MachineInstrIndex Point){
for (unsigned i = 0, e = V.size(); i != e; ++i) {
RALinScan::IntervalPtr &IP = V[i];
LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
@@ -738,7 +739,8 @@ static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
if (SI.hasAtLeastOneValue())
VNI = SI.getValNumInfo(0);
else
- VNI = SI.getNextValue(0, 0, false, ls_->getVNInfoAllocator());
+ VNI = SI.getNextValue(MachineInstrIndex(), 0, false,
+ ls_->getVNInfoAllocator());
LiveInterval &RI = li_->getInterval(cur->reg);
// FIXME: This may be overly conservative.
@@ -880,7 +882,7 @@ void RALinScan::UpgradeRegister(unsigned Reg) {
namespace {
struct LISorter {
bool operator()(LiveInterval* A, LiveInterval* B) {
- return A->beginNumber() < B->beginNumber();
+ return A->beginIndex() < B->beginIndex();
}
};
}
@@ -905,7 +907,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
backUpRegUses();
std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
- unsigned StartPosition = cur->beginNumber();
+ MachineInstrIndex StartPosition = cur->beginIndex();
const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
// If start of this live interval is defined by a move instruction and its
@@ -915,7 +917,8 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
// one, e.g. X86::mov32to32_. These move instructions are not coalescable.
if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
VNInfo *vni = cur->begin()->valno;
- if (vni->def && !vni->isUnused() && vni->isDefAccurate()) {
+ if ((vni->def != MachineInstrIndex()) && !vni->isUnused() &&
+ vni->isDefAccurate()) {
MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (CopyMI &&
@@ -977,7 +980,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
// Okay, this reg is on the fixed list. Check to see if we actually
// conflict.
LiveInterval *I = IP.first;
- if (I->endNumber() > StartPosition) {
+ if (I->endIndex() > StartPosition) {
LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
IP.second = II;
if (II != I->begin() && II->start > StartPosition)
@@ -1002,7 +1005,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
- I->endNumber() > StartPosition) {
+ I->endIndex() > StartPosition) {
LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
IP.second = II;
if (II != I->begin() && II->start > StartPosition)
@@ -1170,14 +1173,14 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
LiveInterval *ReloadLi = added[i];
if (ReloadLi->weight == HUGE_VALF &&
li_->getApproximateInstructionCount(*ReloadLi) == 0) {
- unsigned ReloadIdx = ReloadLi->beginNumber();
+ MachineInstrIndex ReloadIdx = ReloadLi->beginIndex();
MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
// Last reload of same SS is in the same MBB. We want to try to
// allocate both reloads the same register and make sure the reg
// isn't clobbered in between if at all possible.
- assert(LastReload->beginNumber() < ReloadIdx);
+ assert(LastReload->beginIndex() < ReloadIdx);
NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
}
LastReloadMBB = ReloadMBB;
@@ -1226,7 +1229,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
spillIs.pop_back();
DEBUG(errs() << "\t\t\tspilling(a): " << *sli << '\n');
earliestStartInterval =
- (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
+ (earliestStartInterval->beginIndex() < sli->beginIndex()) ?
earliestStartInterval : sli;
std::vector<LiveInterval*> newIs;
@@ -1240,7 +1243,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
spilled.insert(sli->reg);
}
- unsigned earliestStart = earliestStartInterval->beginNumber();
+ MachineInstrIndex earliestStart = earliestStartInterval->beginIndex();
DEBUG(errs() << "\t\trolling back to: " << earliestStart << '\n');
@@ -1250,7 +1253,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
while (!handled_.empty()) {
LiveInterval* i = handled_.back();
// If this interval starts before t we are done.
- if (i->beginNumber() < earliestStart)
+ if (i->beginIndex() < earliestStart)
break;
DEBUG(errs() << "\t\t\tundo changes for: " << *i << '\n');
handled_.pop_back();
@@ -1301,7 +1304,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
LiveInterval *HI = handled_[i];
if (!HI->expiredAt(earliestStart) &&
- HI->expiredAt(cur->beginNumber())) {
+ HI->expiredAt(cur->beginIndex())) {
DEBUG(errs() << "\t\t\tundo changes for: " << *HI << '\n');
active_.push_back(std::make_pair(HI, HI->begin()));
assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
@@ -1321,14 +1324,14 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
LiveInterval *ReloadLi = added[i];
if (ReloadLi->weight == HUGE_VALF &&
li_->getApproximateInstructionCount(*ReloadLi) == 0) {
- unsigned ReloadIdx = ReloadLi->beginNumber();
+ MachineInstrIndex ReloadIdx = ReloadLi->beginIndex();
MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
// Last reload of same SS is in the same MBB. We want to try to
// allocate both reloads the same register and make sure the reg
// isn't clobbered in between if at all possible.
- assert(LastReload->beginNumber() < ReloadIdx);
+ assert(LastReload->beginIndex() < ReloadIdx);
NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
}
LastReloadMBB = ReloadMBB;
diff --git a/libclamav/c++/llvm/lib/CodeGen/RegAllocPBQP.cpp b/libclamav/c++/llvm/lib/CodeGen/RegAllocPBQP.cpp
index 853192c..33d82d0 100644
--- a/libclamav/c++/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -74,7 +74,7 @@ namespace {
public:
static char ID;
-
+
/// Construct a PBQP register allocator.
PBQPRegAlloc() : MachineFunctionPass(&ID) {}
@@ -269,7 +269,7 @@ PBQP::Matrix* PBQPRegAlloc::buildInterferenceMatrix(
unsigned reg2 = *a2Itr;
// If the row/column regs are identical or alias insert an infinity.
- if ((reg1 == reg2) || tri->areAliases(reg1, reg2)) {
+ if (tri->regsOverlap(reg1, reg2)) {
(*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity();
isZeroMatrix = false;
}
@@ -683,23 +683,20 @@ void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled,
if (stackInterval.getNumValNums() != 0)
vni = stackInterval.getValNumInfo(0);
else
- vni = stackInterval.getNextValue(0, 0, false, lss->getVNInfoAllocator());
+ vni = stackInterval.getNextValue(
+ MachineInstrIndex(), 0, false, lss->getVNInfoAllocator());
LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
stackInterval.MergeRangesInAsValue(rhsInterval, vni);
}
bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) {
-
- static unsigned round = 0;
- (void) round;
-
// Set to true if we have any spills
bool anotherRoundNeeded = false;
// Clear the existing allocation.
vrm->clearAllVirt();
-
+
// Iterate over the nodes mapping the PBQP solution to a register assignment.
for (unsigned node = 0; node < node2LI.size(); ++node) {
unsigned virtReg = node2LI[node]->reg,
@@ -767,7 +764,7 @@ void PBQPRegAlloc::finalizeAlloc() const {
// First allocate registers for the empty intervals.
for (LiveIntervalSet::const_iterator
- itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
+ itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
itr != end; ++itr) {
LiveInterval *li = *itr;
diff --git a/libclamav/c++/llvm/lib/CodeGen/RegAllocSimple.cpp b/libclamav/c++/llvm/lib/CodeGen/RegAllocSimple.cpp
deleted file mode 100644
index 5abeb7c..0000000
--- a/libclamav/c++/llvm/lib/CodeGen/RegAllocSimple.cpp
+++ /dev/null
@@ -1,261 +0,0 @@
-//===-- RegAllocSimple.cpp - A simple generic register allocator ----------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements a simple register allocator. *Very* simple: It immediate
-// spills every value right after it is computed, and it reloads all used
-// operands from the spill area to temporary registers before each instruction.
-// It does not keep values in registers across instructions.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "regalloc"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/RegAllocRegistry.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/ADT/STLExtras.h"
-#include <map>
-using namespace llvm;
-
-STATISTIC(NumStores, "Number of stores added");
-STATISTIC(NumLoads , "Number of loads added");
-
-namespace {
- static RegisterRegAlloc
- simpleRegAlloc("simple", "simple register allocator",
- createSimpleRegisterAllocator);
-
- class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
- public:
- static char ID;
- RegAllocSimple() : MachineFunctionPass(&ID) {}
- private:
- MachineFunction *MF;
- const TargetMachine *TM;
- const TargetRegisterInfo *TRI;
- const TargetInstrInfo *TII;
-
- // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
- // these values are spilled
- std::map<unsigned, int> StackSlotForVirtReg;
-
- // RegsUsed - Keep track of what registers are currently in use. This is a
- // bitset.
- std::vector<bool> RegsUsed;
-
- // RegClassIdx - Maps RegClass => which index we can take a register
- // from. Since this is a simple register allocator, when we need a register
- // of a certain class, we just take the next available one.
- std::map<const TargetRegisterClass*, unsigned> RegClassIdx;
-
- public:
- virtual const char *getPassName() const {
- return "Simple Register Allocator";
- }
-
- /// runOnMachineFunction - Register allocate the whole function
- bool runOnMachineFunction(MachineFunction &Fn);
-
- virtual void getAnalysisUsage(AnalysisUsage &AU) const {
- AU.setPreservesCFG();
- AU.addRequiredID(PHIEliminationID); // Eliminate PHI nodes
- MachineFunctionPass::getAnalysisUsage(AU);
- }
- private:
- /// AllocateBasicBlock - Register allocate the specified basic block.
- void AllocateBasicBlock(MachineBasicBlock &MBB);
-
- /// getStackSpaceFor - This returns the offset of the specified virtual
- /// register on the stack, allocating space if necessary.
- int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
-
- /// Given a virtual register, return a compatible physical register that is
- /// currently unused.
- ///
- /// Side effect: marks that register as being used until manually cleared
- ///
- unsigned getFreeReg(unsigned virtualReg);
-
- /// Moves value from memory into that register
- unsigned reloadVirtReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I, unsigned VirtReg);
-
- /// Saves reg value on the stack (maps virtual register to stack value)
- void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned VirtReg, unsigned PhysReg);
- };
- char RegAllocSimple::ID = 0;
-}
-
-/// getStackSpaceFor - This allocates space for the specified virtual
-/// register to be held on the stack.
-int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
- const TargetRegisterClass *RC) {
- // Find the location VirtReg would belong...
- std::map<unsigned, int>::iterator I = StackSlotForVirtReg.find(VirtReg);
-
- if (I != StackSlotForVirtReg.end())
- return I->second; // Already has space allocated?
-
- // Allocate a new stack object for this spill location...
- int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
- RC->getAlignment());
-
- // Assign the slot...
- StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
-
- return FrameIdx;
-}
-
-unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
- const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg);
- TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
-#ifndef NDEBUG
- TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
-#endif
-
- while (1) {
- unsigned regIdx = RegClassIdx[RC]++;
- assert(RI+regIdx != RE && "Not enough registers!");
- unsigned PhysReg = *(RI+regIdx);
-
- if (!RegsUsed[PhysReg]) {
- MF->getRegInfo().setPhysRegUsed(PhysReg);
- return PhysReg;
- }
- }
-}
-
-unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- unsigned VirtReg) {
- const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
- int FrameIdx = getStackSpaceFor(VirtReg, RC);
- unsigned PhysReg = getFreeReg(VirtReg);
-
- // Add move instruction(s)
- ++NumLoads;
- TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
- return PhysReg;
-}
-
-void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- unsigned VirtReg, unsigned PhysReg) {
- const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
-
- int FrameIdx = getStackSpaceFor(VirtReg, RC);
-
- // Add move instruction(s)
- ++NumStores;
- TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
-}
-
-
-void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
- // loop over each instruction
- for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
- // Made to combat the incorrect allocation of r2 = add r1, r1
- std::map<unsigned, unsigned> Virt2PhysRegMap;
-
- RegsUsed.resize(TRI->getNumRegs());
-
- // This is a preliminary pass that will invalidate any registers that are
- // used by the instruction (including implicit uses).
- const TargetInstrDesc &Desc = MI->getDesc();
- const unsigned *Regs;
- if (Desc.ImplicitUses) {
- for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
- RegsUsed[*Regs] = true;
- }
-
- if (Desc.ImplicitDefs) {
- for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
- RegsUsed[*Regs] = true;
- MF->getRegInfo().setPhysRegUsed(*Regs);
- }
- }
-
- // Loop over uses, move from memory into registers.
- for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
- MachineOperand &MO = MI->getOperand(i);
-
- if (MO.isReg() && MO.getReg() &&
- TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
- unsigned virtualReg = (unsigned) MO.getReg();
- DEBUG({
- errs() << "op: " << MO << "\n" << "\t inst[" << i << "]: ";
- MI->print(errs(), TM);
- });
-
- // make sure the same virtual register maps to the same physical
- // register in any given instruction
- unsigned physReg = Virt2PhysRegMap[virtualReg];
- if (physReg == 0) {
- if (MO.isDef()) {
- unsigned TiedOp;
- if (!MI->isRegTiedToUseOperand(i, &TiedOp)) {
- physReg = getFreeReg(virtualReg);
- } else {
- // must be same register number as the source operand that is
- // tied to. This maps a = b + c into b = b + c, and saves b into
- // a's spot.
- assert(MI->getOperand(TiedOp).isReg() &&
- MI->getOperand(TiedOp).getReg() &&
- MI->getOperand(TiedOp).isUse() &&
- "Two address instruction invalid!");
-
- physReg = MI->getOperand(TiedOp).getReg();
- }
- spillVirtReg(MBB, next(MI), virtualReg, physReg);
- } else {
- physReg = reloadVirtReg(MBB, MI, virtualReg);
- Virt2PhysRegMap[virtualReg] = physReg;
- }
- }
- MO.setReg(physReg);
- DEBUG(errs() << "virt: " << virtualReg
- << ", phys: " << MO.getReg() << "\n");
- }
- }
- RegClassIdx.clear();
- RegsUsed.clear();
- }
-}
-
-
-/// runOnMachineFunction - Register allocate the whole function
-///
-bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
- DEBUG(errs() << "Machine Function\n");
- MF = &Fn;
- TM = &MF->getTarget();
- TRI = TM->getRegisterInfo();
- TII = TM->getInstrInfo();
-
- // Loop over all of the basic blocks, eliminating virtual register references
- for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
- MBB != MBBe; ++MBB)
- AllocateBasicBlock(*MBB);
-
- StackSlotForVirtReg.clear();
- return true;
-}
-
-FunctionPass *llvm::createSimpleRegisterAllocator() {
- return new RegAllocSimple();
-}
diff --git a/libclamav/c++/llvm/lib/CodeGen/RegisterScavenging.cpp b/libclamav/c++/llvm/lib/CodeGen/RegisterScavenging.cpp
index 29628f1..9fc3da3 100644
--- a/libclamav/c++/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -109,45 +109,6 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
Tracking = false;
}
-#ifndef NDEBUG
-/// isLiveInButUnusedBefore - Return true if register is livein the MBB not
-/// not used before it reaches the MI that defines register.
-static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
- MachineBasicBlock *MBB,
- const TargetRegisterInfo *TRI,
- MachineRegisterInfo* MRI) {
- // First check if register is livein.
- bool isLiveIn = false;
- for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
- E = MBB->livein_end(); I != E; ++I)
- if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
- isLiveIn = true;
- break;
- }
- if (!isLiveIn)
- return false;
-
- // Is there any use of it before the specified MI?
- SmallPtrSet<MachineInstr*, 4> UsesInMBB;
- for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
- UE = MRI->use_end(); UI != UE; ++UI) {
- MachineOperand &UseMO = UI.getOperand();
- if (UseMO.isReg() && UseMO.isUndef())
- continue;
- MachineInstr *UseMI = &*UI;
- if (UseMI->getParent() == MBB)
- UsesInMBB.insert(UseMI);
- }
- if (UsesInMBB.empty())
- return true;
-
- for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
- if (UsesInMBB.count(&*I))
- return false;
- return true;
-}
-#endif
-
void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
BV.set(Reg);
for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
@@ -221,9 +182,13 @@ void RegScavenger::forward() {
"Using an early clobbered register!");
} else {
assert(MO.isDef());
+#if 0
+ // FIXME: Enable this once we've figured out how to correctly transfer
+ // implicit kills during codegen passes like the coalescer.
assert((KillRegs.test(Reg) || isUnused(Reg) ||
isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
"Re-defining a live register!");
+#endif
}
}
@@ -276,7 +241,8 @@ unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator MI,
// Remove any candidates touched by instruction.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || MO.isUndef() || !MO.getReg())
+ if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
+ TargetRegisterInfo::isVirtualRegister(MO.getReg()))
continue;
Candidates.reset(MO.getReg());
for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++)
@@ -314,7 +280,8 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
- if (MO.isReg())
+ if (MO.isReg() && MO.getReg() != 0 &&
+ !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
Candidates.reset(MO.getReg());
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/ScheduleDAG.cpp b/libclamav/c++/llvm/lib/CodeGen/ScheduleDAG.cpp
index ff5c236..5a59862 100644
--- a/libclamav/c++/llvm/lib/CodeGen/ScheduleDAG.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/ScheduleDAG.cpp
@@ -82,13 +82,19 @@ void SUnit::addPred(const SDep &D) {
SUnit *N = D.getSUnit();
// Update the bookkeeping.
if (D.getKind() == SDep::Data) {
+ assert(NumPreds < UINT_MAX && "NumPreds will overflow!");
+ assert(N->NumSuccs < UINT_MAX && "NumSuccs will overflow!");
++NumPreds;
++N->NumSuccs;
}
- if (!N->isScheduled)
+ if (!N->isScheduled) {
+ assert(NumPredsLeft < UINT_MAX && "NumPredsLeft will overflow!");
++NumPredsLeft;
- if (!isScheduled)
+ }
+ if (!isScheduled) {
+ assert(N->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");
++N->NumSuccsLeft;
+ }
Preds.push_back(D);
N->Succs.push_back(P);
if (P.getLatency() != 0) {
@@ -121,13 +127,19 @@ void SUnit::removePred(const SDep &D) {
Preds.erase(I);
// Update the bookkeeping.
if (P.getKind() == SDep::Data) {
+ assert(NumPreds > 0 && "NumPreds will underflow!");
+ assert(N->NumSuccs > 0 && "NumSuccs will underflow!");
--NumPreds;
--N->NumSuccs;
}
- if (!N->isScheduled)
+ if (!N->isScheduled) {
+ assert(NumPredsLeft > 0 && "NumPredsLeft will underflow!");
--NumPredsLeft;
- if (!isScheduled)
+ }
+ if (!isScheduled) {
+ assert(N->NumSuccsLeft > 0 && "NumSuccsLeft will underflow!");
--N->NumSuccsLeft;
+ }
if (P.getLatency() != 0) {
this->setDepthDirty();
N->setHeightDirty();
diff --git a/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGEmit.cpp b/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGEmit.cpp
index 770f5bb..0d15c02 100644
--- a/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGEmit.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGEmit.cpp
@@ -28,10 +28,6 @@
#include "llvm/Support/MathExtras.h"
using namespace llvm;
-void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
- MI->addMemOperand(MF, MO);
-}
-
void ScheduleDAG::EmitNoop() {
TII->insertNoop(*BB, InsertPos);
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 1aceda5..b55e606 100644
--- a/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -17,6 +17,7 @@
#include "llvm/Operator.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Target/TargetMachine.h"
@@ -96,11 +97,11 @@ static const Value *getUnderlyingObject(const Value *V) {
/// object, return the Value for that object. Otherwise return null.
static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI) {
if (!MI->hasOneMemOperand() ||
- !MI->memoperands_begin()->getValue() ||
- MI->memoperands_begin()->isVolatile())
+ !(*MI->memoperands_begin())->getValue() ||
+ (*MI->memoperands_begin())->isVolatile())
return 0;
- const Value *V = MI->memoperands_begin()->getValue();
+ const Value *V = (*MI->memoperands_begin())->getValue();
if (!V)
return 0;
@@ -335,10 +336,10 @@ void ScheduleDAGInstrs::BuildSchedGraph() {
if (!ChainTID.isCall() &&
!ChainTID.hasUnmodeledSideEffects() &&
ChainMI->hasOneMemOperand() &&
- !ChainMI->memoperands_begin()->isVolatile() &&
- ChainMI->memoperands_begin()->getValue())
+ !(*ChainMI->memoperands_begin())->isVolatile() &&
+ (*ChainMI->memoperands_begin())->getValue())
// We know that the Chain accesses one specific memory location.
- ChainMMO = &*ChainMI->memoperands_begin();
+ ChainMMO = *ChainMI->memoperands_begin();
else
// Unknown memory accesses. Assume the worst.
ChainMMO = 0;
@@ -493,7 +494,8 @@ std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
}
// EmitSchedule - Emit the machine code in scheduled order.
-MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
+MachineBasicBlock *ScheduleDAGInstrs::
+EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
// For MachineInstr-based scheduling, we're rescheduling the instructions in
// the block, so start by removing them from the block.
while (Begin != InsertPos) {
diff --git a/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGInstrs.h b/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGInstrs.h
index 929bdaa..e928ca1 100644
--- a/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGInstrs.h
+++ b/libclamav/c++/llvm/lib/CodeGen/ScheduleDAGInstrs.h
@@ -15,12 +15,13 @@
#ifndef SCHEDULEDAGINSTRS_H
#define SCHEDULEDAGINSTRS_H
-#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallSet.h"
#include <map>
namespace llvm {
@@ -166,7 +167,8 @@ namespace llvm {
virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
SDep& dep) const;
- virtual MachineBasicBlock *EmitSchedule();
+ virtual MachineBasicBlock*
+ EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*>*);
/// StartBlock - Prepare to perform scheduling in the given block.
///
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
index 60c3056..fbe40b6 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
@@ -20,7 +20,7 @@
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
-CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm,
+CCState::CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &tm,
SmallVector<CCValAssign, 16> &locs, LLVMContext &C)
: CallingConv(CC), IsVarArg(isVarArg), TM(tm),
TRI(*TM.getRegisterInfo()), Locs(locs), Context(C) {
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 749170f..f04ab68 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -239,14 +239,17 @@ namespace {
/// overlap.
bool isAlias(SDValue Ptr1, int64_t Size1,
const Value *SrcValue1, int SrcValueOffset1,
+ unsigned SrcValueAlign1,
SDValue Ptr2, int64_t Size2,
- const Value *SrcValue2, int SrcValueOffset2) const;
+ const Value *SrcValue2, int SrcValueOffset2,
+ unsigned SrcValueAlign2) const;
/// FindAliasInfo - Extracts the relevant alias information from the memory
/// node. Returns true if the operand was a load.
bool FindAliasInfo(SDNode *N,
SDValue &Ptr, int64_t &Size,
- const Value *&SrcValue, int &SrcValueOffset) const;
+ const Value *&SrcValue, int &SrcValueOffset,
+ unsigned &SrcValueAlignment) const;
/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
/// looking for a better chain (aliasing node.)
@@ -886,7 +889,7 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
break;
case ISD::TokenFactor:
- if ((CombinerAA || Op.hasOneUse()) &&
+ if (Op.hasOneUse() &&
std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
// Queue up for processing.
TFs.push_back(Op.getNode());
@@ -907,7 +910,7 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
}
}
}
-
+
SDValue Result;
// If we've change things around then replace token factor.
@@ -1836,18 +1839,18 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// fold (zext_inreg (extload x)) -> (zextload x)
if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- EVT EVT = LN0->getMemoryVT();
+ EVT MemVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
unsigned BitWidth = N1.getValueSizeInBits();
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
- BitWidth - EVT.getSizeInBits())) &&
+ BitWidth - MemVT.getSizeInBits())) &&
((!LegalOperations && !LN0->isVolatile()) ||
- TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
+ TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT,
+ LN0->getSrcValueOffset(), MemVT,
LN0->isVolatile(), LN0->getAlignment());
AddToWorkList(N);
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
@@ -1858,18 +1861,18 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- EVT EVT = LN0->getMemoryVT();
+ EVT MemVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
unsigned BitWidth = N1.getValueSizeInBits();
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
- BitWidth - EVT.getSizeInBits())) &&
+ BitWidth - MemVT.getSizeInBits())) &&
((!LegalOperations && !LN0->isVolatile()) ||
- TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
+ TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT,
+ LN0->getSrcValueOffset(), MemVT,
LN0->isVolatile(), LN0->getAlignment());
AddToWorkList(N);
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
@@ -1901,8 +1904,8 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// For big endian targets, we need to add an offset to the pointer to
// load the correct bytes. For little endian systems, we merely need to
// read fewer bytes from the same pointer.
- unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
- unsigned EVTStoreBytes = ExtVT.getStoreSizeInBits()/8;
+ unsigned LVTStoreBytes = LoadedVT.getStoreSize();
+ unsigned EVTStoreBytes = ExtVT.getStoreSize();
unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
unsigned Alignment = LN0->getAlignment();
SDValue NewPtr = LN0->getBasePtr();
@@ -3083,13 +3086,13 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- EVT EVT = LN0->getMemoryVT();
+ EVT MemVT = LN0->getMemoryVT();
if ((!LegalOperations && !LN0->isVolatile()) ||
- TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
+ TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT,
+ LN0->getSrcValueOffset(), MemVT,
LN0->isVolatile(), LN0->getAlignment());
CombineTo(N, ExtLoad);
CombineTo(N0.getNode(),
@@ -3243,13 +3246,13 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- EVT EVT = LN0->getMemoryVT();
+ EVT MemVT = LN0->getMemoryVT();
if ((!LegalOperations && !LN0->isVolatile()) ||
- TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
+ TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT,
+ LN0->getSrcValueOffset(), MemVT,
LN0->isVolatile(), LN0->getAlignment());
CombineTo(N, ExtLoad);
CombineTo(N0.getNode(),
@@ -3379,11 +3382,11 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
!ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- EVT EVT = LN0->getMemoryVT();
+ EVT MemVT = LN0->getMemoryVT();
SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
VT, LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT,
+ LN0->getSrcValueOffset(), MemVT,
LN0->isVolatile(), LN0->getAlignment());
CombineTo(N, ExtLoad);
CombineTo(N0.getNode(),
@@ -4481,7 +4484,6 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) {
if (Op0.getOpcode() == ISD::AND &&
Op0.hasOneUse() &&
Op1.getOpcode() == ISD::Constant) {
- SDValue AndOp0 = Op0.getOperand(0);
SDValue AndOp1 = Op0.getOperand(1);
if (AndOp1.getOpcode() == ISD::Constant) {
@@ -4716,7 +4718,7 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
SDValue Offset;
ISD::MemIndexedMode AM = ISD::UNINDEXED;
if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
- if (Ptr == Offset)
+ if (Ptr == Offset && Op->getOpcode() == ISD::ADD)
std::swap(BasePtr, Offset);
if (Ptr != BasePtr)
continue;
@@ -4960,7 +4962,10 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
// Create token factor to keep old chain connected.
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
MVT::Other, Chain, ReplLoad.getValue(1));
-
+
+ // Make sure the new and old chains are cleaned up.
+ AddToWorkList(Token.getNode());
+
// Replace uses with load result and token factor. Don't add users
// to work list.
return CombineTo(N, ReplLoad.getValue(0), Token, false);
@@ -5181,8 +5186,9 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
// If there is a better chain.
if (Chain != BetterChain) {
- // Replace the chain to avoid dependency.
SDValue ReplStore;
+
+ // Replace the chain to avoid dependency.
if (ST->isTruncatingStore()) {
ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
ST->getSrcValue(),ST->getSrcValueOffset(),
@@ -5198,6 +5204,9 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
MVT::Other, Chain, ReplStore);
+ // Make sure the new and old chains are cleaned up.
+ AddToWorkList(Token.getNode());
+
// Don't add users to work list.
return CombineTo(N, Token, false);
}
@@ -5282,9 +5291,9 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
isa<ConstantSDNode>(EltNo)) {
EVT VT = InVec.getValueType();
- EVT EVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
- SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT));
+ SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
if (Elt < Ops.size())
@@ -5405,7 +5414,6 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
unsigned NumInScalars = N->getNumOperands();
EVT VT = N->getValueType(0);
- EVT EltType = VT.getVectorElementType();
// Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
// operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
@@ -5506,7 +5514,6 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
unsigned NumElts = VT.getVectorNumElements();
SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
assert(N0.getValueType().getVectorNumElements() == NumElts &&
"Vector shuffle must be normalized in DAG");
@@ -5592,9 +5599,9 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
return SDValue();
// Return the new VECTOR_SHUFFLE node.
- EVT EVT = RVT.getVectorElementType();
+ EVT EltVT = RVT.getVectorElementType();
SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
- DAG.getConstant(0, EVT));
+ DAG.getConstant(0, EltVT));
SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
RVT, &ZeroOps[0], ZeroOps.size());
LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
@@ -6082,11 +6089,12 @@ SDValue DAGCombiner::BuildUDIV(SDNode *N) {
return S;
}
-/// FindBaseOffset - Return true if base is known not to alias with anything
-/// but itself. Provides base object and offset as results.
-static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
+/// FindBaseOffset - Return true if base is a frame index, which is known not
+// to alias with anything but itself. Provides base object and offset as results.
+static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
+ GlobalValue *&GV, void *&CV) {
// Assume it is a primitive operation.
- Base = Ptr; Offset = 0;
+ Base = Ptr; Offset = 0; GV = 0; CV = 0;
// If it's an adding a simple constant then integrate the offset.
if (Base.getOpcode() == ISD::ADD) {
@@ -6095,36 +6103,73 @@ static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
Offset += C->getZExtValue();
}
}
+
+ // Return the underlying GlobalValue, and update the Offset. Return false
+ // for GlobalAddressSDNode since the same GlobalAddress may be represented
+ // by multiple nodes with different offsets.
+ if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
+ GV = G->getGlobal();
+ Offset += G->getOffset();
+ return false;
+ }
+ // Return the underlying Constant value, and update the Offset. Return false
+ // for ConstantSDNodes since the same constant pool entry may be represented
+ // by multiple nodes with different offsets.
+ if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
+ CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
+ : (void *)C->getConstVal();
+ Offset += C->getOffset();
+ return false;
+ }
// If it's any of the following then it can't alias with anything but itself.
- return isa<FrameIndexSDNode>(Base) ||
- isa<ConstantPoolSDNode>(Base) ||
- isa<GlobalAddressSDNode>(Base);
+ return isa<FrameIndexSDNode>(Base);
}
/// isAlias - Return true if there is any possibility that the two addresses
/// overlap.
bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
const Value *SrcValue1, int SrcValueOffset1,
+ unsigned SrcValueAlign1,
SDValue Ptr2, int64_t Size2,
- const Value *SrcValue2, int SrcValueOffset2) const {
+ const Value *SrcValue2, int SrcValueOffset2,
+ unsigned SrcValueAlign2) const {
// If they are the same then they must be aliases.
if (Ptr1 == Ptr2) return true;
// Gather base node and offset information.
SDValue Base1, Base2;
int64_t Offset1, Offset2;
- bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
- bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
+ GlobalValue *GV1, *GV2;
+ void *CV1, *CV2;
+ bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
+ bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
- // If they have a same base address then...
- if (Base1 == Base2)
- // Check to see if the addresses overlap.
+ // If they have a same base address then check to see if they overlap.
+ if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
- // If we know both bases then they can't alias.
- if (KnownBase1 && KnownBase2) return false;
+ // If we know what the bases are, and they aren't identical, then we know they
+ // cannot alias.
+ if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
+ return false;
+ // If we know required SrcValue1 and SrcValue2 have relatively large alignment
+ // compared to the size and offset of the access, we may be able to prove they
+ // do not alias. This check is conservative for now to catch cases created by
+ // splitting vector types.
+ if ((SrcValueAlign1 == SrcValueAlign2) &&
+ (SrcValueOffset1 != SrcValueOffset2) &&
+ (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
+ int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
+ int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
+
+ // There is no overlap between these relatively aligned accesses of similar
+ // size, return no alias.
+ if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
+ return false;
+ }
+
if (CombinerGlobalAA) {
// Use alias analysis information.
int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
@@ -6144,18 +6189,22 @@ bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
/// node. Returns true if the operand was a load.
bool DAGCombiner::FindAliasInfo(SDNode *N,
SDValue &Ptr, int64_t &Size,
- const Value *&SrcValue, int &SrcValueOffset) const {
+ const Value *&SrcValue,
+ int &SrcValueOffset,
+ unsigned &SrcValueAlign) const {
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
Size = LD->getMemoryVT().getSizeInBits() >> 3;
SrcValue = LD->getSrcValue();
SrcValueOffset = LD->getSrcValueOffset();
+ SrcValueAlign = LD->getOriginalAlignment();
return true;
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
Ptr = ST->getBasePtr();
Size = ST->getMemoryVT().getSizeInBits() >> 3;
SrcValue = ST->getSrcValue();
SrcValueOffset = ST->getSrcValueOffset();
+ SrcValueAlign = ST->getOriginalAlignment();
} else {
llvm_unreachable("FindAliasInfo expected a memory operand");
}
@@ -6168,14 +6217,16 @@ bool DAGCombiner::FindAliasInfo(SDNode *N,
void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
SmallVector<SDValue, 8> &Aliases) {
SmallVector<SDValue, 8> Chains; // List of chains to visit.
- std::set<SDNode *> Visited; // Visited node set.
+ SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
// Get alias information for node.
SDValue Ptr;
- int64_t Size = 0;
- const Value *SrcValue = 0;
- int SrcValueOffset = 0;
- bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
+ int64_t Size;
+ const Value *SrcValue;
+ int SrcValueOffset;
+ unsigned SrcValueAlign;
+ bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
+ SrcValueAlign);
// Starting off.
Chains.push_back(OriginalChain);
@@ -6187,9 +6238,9 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
SDValue Chain = Chains.back();
Chains.pop_back();
- // Don't bother if we've been before.
- if (Visited.find(Chain.getNode()) != Visited.end()) continue;
- Visited.insert(Chain.getNode());
+ // Don't bother if we've been before.
+ if (!Visited.insert(Chain.getNode()))
+ continue;
switch (Chain.getOpcode()) {
case ISD::EntryToken:
@@ -6200,16 +6251,19 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
case ISD::STORE: {
// Get alias information for Chain.
SDValue OpPtr;
- int64_t OpSize = 0;
- const Value *OpSrcValue = 0;
- int OpSrcValueOffset = 0;
+ int64_t OpSize;
+ const Value *OpSrcValue;
+ int OpSrcValueOffset;
+ unsigned OpSrcValueAlign;
bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
- OpSrcValue, OpSrcValueOffset);
+ OpSrcValue, OpSrcValueOffset,
+ OpSrcValueAlign);
// If chain is alias then stop here.
if (!(IsLoad && IsOpLoad) &&
- isAlias(Ptr, Size, SrcValue, SrcValueOffset,
- OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
+ isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
+ OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
+ OpSrcValueAlign)) {
Aliases.push_back(Chain);
} else {
// Look further up the chain.
@@ -6221,10 +6275,14 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
}
case ISD::TokenFactor:
- // We have to check each of the operands of the token factor, so we queue
- // then up. Adding the operands to the queue (stack) in reverse order
- // maintains the original order and increases the likelihood that getNode
- // will find a matching token factor (CSE.)
+ // We have to check each of the operands of the token factor for "small"
+ // token factors, so we queue them up. Adding the operands to the queue
+ // (stack) in reverse order maintains the original order and increases the
+ // likelihood that getNode will find a matching token factor (CSE.)
+ if (Chain.getNumOperands() > 16) {
+ Aliases.push_back(Chain);
+ break;
+ }
for (unsigned n = Chain.getNumOperands(); n;)
Chains.push_back(Chain.getOperand(--n));
// Eliminate the token factor if we can.
@@ -6256,13 +6314,8 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
}
// Construct a custom tailored token factor.
- SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
- &Aliases[0], Aliases.size());
-
- // Make sure the old chain gets cleaned up.
- if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
-
- return NewChain;
+ return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
+ &Aliases[0], Aliases.size());
}
// SelectionDAG::Combine - This is the entry point for the file.
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 5b4c79a..0bec2cf 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -407,7 +407,6 @@ bool FastISel::SelectCall(User *I) {
|| !DW->ShouldEmitDwarfDebug())
return true;
- Value *Variable = DI->getVariable();
Value *Address = DI->getAddress();
if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
Address = BCI->getOperand(0);
@@ -418,8 +417,15 @@ bool FastISel::SelectCall(User *I) {
StaticAllocaMap.find(AI);
if (SI == StaticAllocaMap.end()) break; // VLAs.
int FI = SI->second;
-
- DW->RecordVariable(cast<MDNode>(Variable), FI);
+ if (MMI) {
+ MetadataContext &TheMetadata = AI->getContext().getMetadata();
+ unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
+ MDNode *AllocaLocation =
+ dyn_cast_or_null<MDNode>(TheMetadata.getMD(MDDbgKind, AI));
+ if (AllocaLocation)
+ MMI->setVariableDbgInfo(DI->getVariable(), AllocaLocation, FI);
+ }
+ DW->RecordVariable(DI->getVariable(), FI);
return true;
}
case Intrinsic::eh_exception: {
@@ -608,6 +614,49 @@ FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
MBB->addSuccessor(MSucc);
}
+/// SelectFNeg - Emit an FNeg operation.
+///
+bool
+FastISel::SelectFNeg(User *I) {
+ unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
+ if (OpReg == 0) return false;
+
+ // If the target has ISD::FNEG, use it.
+ EVT VT = TLI.getValueType(I->getType());
+ unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
+ ISD::FNEG, OpReg);
+ if (ResultReg != 0) {
+ UpdateValueMap(I, ResultReg);
+ return true;
+ }
+
+ // Bitcast the value to integer, twiddle the sign bit with xor,
+ // and then bitcast it back to floating-point.
+ if (VT.getSizeInBits() > 64) return false;
+ EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
+ if (!TLI.isTypeLegal(IntVT))
+ return false;
+
+ unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
+ ISD::BIT_CONVERT, OpReg);
+ if (IntReg == 0)
+ return false;
+
+ unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
+ UINT64_C(1) << (VT.getSizeInBits()-1),
+ IntVT.getSimpleVT());
+ if (IntResultReg == 0)
+ return false;
+
+ ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
+ ISD::BIT_CONVERT, IntResultReg);
+ if (ResultReg == 0)
+ return false;
+
+ UpdateValueMap(I, ResultReg);
+ return true;
+}
+
bool
FastISel::SelectOperator(User *I, unsigned Opcode) {
switch (Opcode) {
@@ -618,6 +667,9 @@ FastISel::SelectOperator(User *I, unsigned Opcode) {
case Instruction::Sub:
return SelectBinaryOp(I, ISD::SUB);
case Instruction::FSub:
+ // FNeg is currently represented in LLVM IR as a special case of FSub.
+ if (BinaryOperator::isFNeg(I))
+ return SelectFNeg(I);
return SelectBinaryOp(I, ISD::FSUB);
case Instruction::Mul:
return SelectBinaryOp(I, ISD::MUL);
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 4ed83db..fc01b07 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1598,7 +1598,6 @@ SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) {
const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
MDNode *CU_Node = DSP->getCompileUnit();
if (DW && (useDEBUG_LOC || useLABEL)) {
- DICompileUnit CU(CU_Node);
unsigned Line = DSP->getLine();
unsigned Col = DSP->getColumn();
@@ -1610,9 +1609,9 @@ SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) {
return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
DAG.getConstant(Line, MVT::i32),
DAG.getConstant(Col, MVT::i32),
- DAG.getSrcValue(CU.getNode()));
+ DAG.getSrcValue(CU_Node));
} else {
- unsigned ID = DW->RecordSourceLine(Line, Col, CU);
+ unsigned ID = DW->RecordSourceLine(Line, Col, CU_Node);
return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID);
}
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 28b06de..8ac8063 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1498,10 +1498,10 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
assert(NVT.isByteSized() && "Expanded type not byte sized!");
if (N->getMemoryVT().bitsLE(NVT)) {
- EVT EVT = N->getMemoryVT();
+ EVT MemVT = N->getMemoryVT();
Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
- EVT, isVolatile, Alignment);
+ MemVT, isVolatile, Alignment);
// Remember the chain.
Ch = Lo.getValue(1);
@@ -1544,14 +1544,15 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
} else {
// Big-endian - high bits are at low addresses. Favor aligned loads at
// the cost of some bit-fiddling.
- EVT EVT = N->getMemoryVT();
- unsigned EBytes = EVT.getStoreSizeInBits()/8;
+ EVT MemVT = N->getMemoryVT();
+ unsigned EBytes = MemVT.getStoreSize();
unsigned IncrementSize = NVT.getSizeInBits()/8;
unsigned ExcessBits = (EBytes - IncrementSize)*8;
// Load both the high bits and maybe some of the low bits.
Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
- EVT::getIntegerVT(*DAG.getContext(), EVT.getSizeInBits() - ExcessBits),
+ EVT::getIntegerVT(*DAG.getContext(),
+ MemVT.getSizeInBits() - ExcessBits),
isVolatile, Alignment);
// Increment the pointer to the other half.
@@ -2229,7 +2230,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
GetExpandedInteger(N->getValue(), Lo, Hi);
EVT ExtVT = N->getMemoryVT();
- unsigned EBytes = ExtVT.getStoreSizeInBits()/8;
+ unsigned EBytes = ExtVT.getStoreSize();
unsigned IncrementSize = NVT.getSizeInBits()/8;
unsigned ExcessBits = (EBytes - IncrementSize)*8;
EVT HiVT = EVT::getIntegerVT(*DAG.getContext(), ExtVT.getSizeInBits() - ExcessBits);
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 13f8ff7..a03f825 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -170,7 +170,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
DAG.getUNDEF(N->getBasePtr().getValueType()),
N->getSrcValue(), N->getSrcValueOffset(),
N->getMemoryVT().getVectorElementType(),
- N->isVolatile(), N->getAlignment());
+ N->isVolatile(), N->getOriginalAlignment());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
@@ -360,7 +360,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
- N->isVolatile(), N->getAlignment());
+ N->isVolatile(), N->getOriginalAlignment());
}
@@ -714,7 +714,7 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
const Value *SV = LD->getSrcValue();
int SVOffset = LD->getSrcValueOffset();
EVT MemoryVT = LD->getMemoryVT();
- unsigned Alignment = LD->getAlignment();
+ unsigned Alignment = LD->getOriginalAlignment();
bool isVolatile = LD->isVolatile();
EVT LoMemVT, HiMemVT;
@@ -727,7 +727,6 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
SVOffset += IncrementSize;
- Alignment = MinAlign(Alignment, IncrementSize);
Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, HiVT, Ch, Ptr, Offset,
SV, SVOffset, HiMemVT, isVolatile, Alignment);
@@ -1078,7 +1077,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
SDValue Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
EVT MemoryVT = N->getMemoryVT();
- unsigned Alignment = N->getAlignment();
+ unsigned Alignment = N->getOriginalAlignment();
bool isVol = N->isVolatile();
SDValue Lo, Hi;
GetSplitVector(N->getOperand(1), Lo, Hi);
@@ -1098,15 +1097,14 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
// Increment the pointer to the other half.
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
+ SVOffset += IncrementSize;
if (isTruncating)
- Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
- N->getSrcValue(), SVOffset+IncrementSize,
- HiMemVT,
- isVol, MinAlign(Alignment, IncrementSize));
+ Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset,
+ HiMemVT, isVol, Alignment);
else
- Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
- isVol, MinAlign(Alignment, IncrementSize));
+ Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset,
+ isVol, Alignment);
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
@@ -1678,7 +1676,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
// Modified the chain - switch anything that used the old chain to use
// the new one.
- ReplaceValueWith(SDValue(N, 1), Chain);
+ ReplaceValueWith(SDValue(N, 1), NewChain);
return Result;
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index c724fe2..7eac4d8 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -134,17 +134,17 @@ void ScheduleDAGFast::Schedule() {
/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) {
SUnit *PredSU = PredEdge->getSUnit();
- --PredSU->NumSuccsLeft;
-
+
#ifndef NDEBUG
- if (PredSU->NumSuccsLeft < 0) {
+ if (PredSU->NumSuccsLeft == 0) {
errs() << "*** Scheduling failed! ***\n";
PredSU->dump(this);
errs() << " has been released too many times!\n";
llvm_unreachable(0);
}
#endif
-
+ --PredSU->NumSuccsLeft;
+
// If all the node's successors are scheduled, this node is ready
// to be scheduled. Ignore the special EntrySU node.
if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
@@ -588,41 +588,11 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
++CurCycle;
}
- // Reverse the order if it is bottom up.
+ // Reverse the order since it is bottom up.
std::reverse(Sequence.begin(), Sequence.end());
-
-
+
#ifndef NDEBUG
- // Verify that all SUnits were scheduled.
- bool AnyNotSched = false;
- unsigned DeadNodes = 0;
- unsigned Noops = 0;
- for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
- if (!SUnits[i].isScheduled) {
- if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) {
- ++DeadNodes;
- continue;
- }
- if (!AnyNotSched)
- errs() << "*** List scheduling failed! ***\n";
- SUnits[i].dump(this);
- errs() << "has not been scheduled!\n";
- AnyNotSched = true;
- }
- if (SUnits[i].NumSuccsLeft != 0) {
- if (!AnyNotSched)
- errs() << "*** List scheduling failed! ***\n";
- SUnits[i].dump(this);
- errs() << "has successors left!\n";
- AnyNotSched = true;
- }
- }
- for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
- if (!Sequence[i])
- ++Noops;
- assert(!AnyNotSched);
- assert(Sequence.size() + DeadNodes - Noops == SUnits.size() &&
- "The number of nodes scheduled doesn't match the expected number!");
+ VerifySchedule(/*isBottomUp=*/true);
#endif
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index 628a2a8..f17fe23 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -108,17 +108,17 @@ void ScheduleDAGList::Schedule() {
/// the PendingQueue if the count reaches zero. Also update its cycle bound.
void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) {
SUnit *SuccSU = D.getSUnit();
- --SuccSU->NumPredsLeft;
-
+
#ifndef NDEBUG
- if (SuccSU->NumPredsLeft < 0) {
+ if (SuccSU->NumPredsLeft == 0) {
errs() << "*** Scheduling failed! ***\n";
SuccSU->dump(this);
errs() << " has been released too many times!\n";
llvm_unreachable(0);
}
#endif
-
+ --SuccSU->NumPredsLeft;
+
SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
// If all the node's predecessors are scheduled, this node is ready
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index a9d1878..cd91b84 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -197,17 +197,17 @@ void ScheduleDAGRRList::Schedule() {
/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
SUnit *PredSU = PredEdge->getSUnit();
- --PredSU->NumSuccsLeft;
-
+
#ifndef NDEBUG
- if (PredSU->NumSuccsLeft < 0) {
+ if (PredSU->NumSuccsLeft == 0) {
errs() << "*** Scheduling failed! ***\n";
PredSU->dump(this);
errs() << " has been released too many times!\n";
llvm_unreachable(0);
}
#endif
-
+ --PredSU->NumSuccsLeft;
+
// If all the node's successors are scheduled, this node is ready
// to be scheduled. Ignore the special EntrySU node.
if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
@@ -278,6 +278,7 @@ void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
AvailableQueue->remove(PredSU);
}
+ assert(PredSU->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");
++PredSU->NumSuccsLeft;
}
@@ -824,17 +825,17 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) {
SUnit *SuccSU = SuccEdge->getSUnit();
- --SuccSU->NumPredsLeft;
-
+
#ifndef NDEBUG
- if (SuccSU->NumPredsLeft < 0) {
+ if (SuccSU->NumPredsLeft == 0) {
errs() << "*** Scheduling failed! ***\n";
SuccSU->dump(this);
errs() << " has been released too many times!\n";
llvm_unreachable(0);
}
#endif
-
+ --SuccSU->NumPredsLeft;
+
// If all the node's predecessors are scheduled, this node is ready
// to be scheduled. Ignore the special ExitSU node.
if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) {
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index a580b93..3e2101a 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -243,10 +243,8 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
// Compute the latency for the node. We use the sum of the latencies for
// all nodes flagged together into this SUnit.
SU->Latency = 0;
- bool SawMachineOpcode = false;
for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
if (N->isMachineOpcode()) {
- SawMachineOpcode = true;
SU->Latency += InstrItins.
getStageLatency(TII->get(N->getMachineOpcode()).getSchedClass());
}
@@ -265,19 +263,10 @@ unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
}
/// CountOperands - The inputs to target nodes have any actual inputs first,
-/// followed by special operands that describe memory references, then an
-/// optional chain operand, then an optional flag operand. Compute the number
-/// of actual operands that will go into the resulting MachineInstr.
+/// followed by an optional chain operand, then an optional flag operand.
+/// Compute the number of actual operands that will go into the resulting
+/// MachineInstr.
unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) {
- unsigned N = ComputeMemOperandsEnd(Node);
- while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode()))
- --N; // Ignore MEMOPERAND nodes
- return N;
-}
-
-/// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
-/// operand
-unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
unsigned N = Node->getNumOperands();
while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
--N;
@@ -286,7 +275,6 @@ unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
return N;
}
-
void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
if (!SU->getNode()) {
errs() << "PHYS REG COPY\n";
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
index 2a278b7..0a6816a 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
@@ -58,7 +58,6 @@ namespace llvm {
if (isa<ConstantPoolSDNode>(Node)) return true;
if (isa<JumpTableSDNode>(Node)) return true;
if (isa<ExternalSymbolSDNode>(Node)) return true;
- if (isa<MemOperandSDNode>(Node)) return true;
if (Node->getOpcode() == ISD::EntryToken) return true;
return false;
}
@@ -99,23 +98,21 @@ namespace llvm {
static unsigned CountResults(SDNode *Node);
/// CountOperands - The inputs to target nodes have any actual inputs first,
- /// followed by special operands that describe memory references, then an
- /// optional chain operand, then flag operands. Compute the number of
- /// actual operands that will go into the resulting MachineInstr.
+ /// followed by an optional chain operand, then flag operands. Compute
+ /// the number of actual operands that will go into the resulting
+ /// MachineInstr.
static unsigned CountOperands(SDNode *Node);
- /// ComputeMemOperandsEnd - Find the index one past the last
- /// MemOperandSDNode operand
- static unsigned ComputeMemOperandsEnd(SDNode *Node);
-
/// EmitNode - Generate machine code for an node and needed dependencies.
/// VRBaseMap contains, for each already emitted node, the first virtual
/// register number for the results of the node.
///
void EmitNode(SDNode *Node, bool IsClone, bool HasClone,
- DenseMap<SDValue, unsigned> &VRBaseMap);
+ DenseMap<SDValue, unsigned> &VRBaseMap,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
- virtual MachineBasicBlock *EmitSchedule();
+ virtual MachineBasicBlock *
+ EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
/// Schedule - Order nodes according to selected style, filling
/// in the Sequence member.
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index 17684f5..c9e40ff 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
@@ -282,7 +282,7 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
if (Op.isMachineOpcode()) {
AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
} else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
- MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
+ MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
} else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
const ConstantFP *CFP = F->getConstantFPValue();
MI->addOperand(MachineOperand::CreateFPImm(CFP));
@@ -319,7 +319,7 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
CP->getTargetFlags()));
} else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
- MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 0,
+ MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
ES->getTargetFlags()));
} else {
assert(Op.getValueType() != MVT::Other &&
@@ -470,7 +470,8 @@ ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node,
/// EmitNode - Generate machine code for an node and needed dependencies.
///
void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
- DenseMap<SDValue, unsigned> &VRBaseMap) {
+ DenseMap<SDValue, unsigned> &VRBaseMap,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
// If machine instruction
if (Node->isMachineOpcode()) {
unsigned Opc = Node->getMachineOpcode();
@@ -496,7 +497,6 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
const TargetInstrDesc &II = TII->get(Opc);
unsigned NumResults = CountResults(Node);
unsigned NodeOperands = CountOperands(Node);
- unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
II.getImplicitDefs() != 0;
#ifndef NDEBUG
@@ -524,14 +524,14 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
VRBaseMap);
- // Emit all of the memory operands of this instruction
- for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
- AddMemOperand(MI,cast<MemOperandSDNode>(Node->getOperand(i+NumSkip))->MO);
+ // Transfer all of the memory reference descriptions of this instruction.
+ MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
+ cast<MachineSDNode>(Node)->memoperands_end());
if (II.usesCustomDAGSchedInsertionHook()) {
// Insert this instruction into the basic block using a target
// specific inserter which may returns a new basic block.
- BB = TLI->EmitInstrWithCustomInserter(MI, BB);
+ BB = TLI->EmitInstrWithCustomInserter(MI, BB, EM);
InsertPos = BB->end();
} else {
BB->insert(InsertPos, MI);
@@ -652,7 +652,8 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
}
/// EmitSchedule - Emit the machine code in scheduled order.
-MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
+MachineBasicBlock *ScheduleDAGSDNodes::
+EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
DenseMap<SDValue, unsigned> VRBaseMap;
DenseMap<SUnit*, unsigned> CopyVRBaseMap;
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
@@ -676,10 +677,11 @@ MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
N = N->getFlaggedNode())
FlaggedNodes.push_back(N);
while (!FlaggedNodes.empty()) {
- EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,VRBaseMap);
+ EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,
+ VRBaseMap, EM);
FlaggedNodes.pop_back();
}
- EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap);
+ EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap, EM);
}
return BB;
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 11f12c9..f6fed21 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -402,11 +402,6 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
case ISD::SRCVALUE:
ID.AddPointer(cast<SrcValueSDNode>(N)->getValue());
break;
- case ISD::MEMOPERAND: {
- const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO;
- MO.Profile(ID);
- break;
- }
case ISD::FrameIndex:
case ISD::TargetFrameIndex:
ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex());
@@ -481,20 +476,18 @@ static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) {
}
/// encodeMemSDNodeFlags - Generic routine for computing a value for use in
-/// the CSE map that carries alignment, volatility, indexing mode, and
+/// the CSE map that carries volatility, indexing mode, and
/// extension/truncation information.
///
static inline unsigned
-encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM,
- bool isVolatile, unsigned Alignment) {
+encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile) {
assert((ConvType & 3) == ConvType &&
"ConvType may not require more than 2 bits!");
assert((AM & 7) == AM &&
"AM may not require more than 3 bits!");
return ConvType |
(AM << 2) |
- (isVolatile << 5) |
- ((Log2_32(Alignment) + 1) << 6);
+ (isVolatile << 5);
}
//===----------------------------------------------------------------------===//
@@ -1330,28 +1323,6 @@ SDValue SelectionDAG::getSrcValue(const Value *V) {
return SDValue(N, 0);
}
-SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) {
-#ifndef NDEBUG
- const Value *v = MO.getValue();
- assert((!v || isa<PointerType>(v->getType())) &&
- "SrcValue is not a pointer?");
-#endif
-
- FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0);
- MO.Profile(ID);
-
- void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDValue(E, 0);
-
- SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>();
- new (N) MemOperandSDNode(MO);
- CSEMap.InsertNode(N, IP);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
/// getShiftAmountOperand - Return the specified value casted to
/// the target's desired shift amount type.
SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) {
@@ -1367,7 +1338,7 @@ SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) {
/// specified value type.
SDValue SelectionDAG::CreateStackTemporary(EVT VT, unsigned minAlign) {
MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
- unsigned ByteSize = VT.getStoreSizeInBits()/8;
+ unsigned ByteSize = VT.getStoreSize();
const Type *Ty = VT.getTypeForEVT(*getContext());
unsigned StackAlign =
std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign);
@@ -2198,6 +2169,19 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros()));
}
+bool SelectionDAG::isKnownNeverNaN(SDValue Op) const {
+ // If we're told that NaNs won't happen, assume they won't.
+ if (FiniteOnlyFPMath())
+ return true;
+
+ // If the value is a constant, we can obviously see if it is a NaN or not.
+ if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op))
+ return !C->getValueAPF().isNaN();
+
+ // TODO: Recognize more cases here.
+
+ return false;
+}
bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const {
GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
@@ -3034,8 +3018,8 @@ static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG,
/// used when a memcpy is turned into a memset when the source is a constant
/// string ptr.
static SDValue getMemsetStringVal(EVT VT, DebugLoc dl, SelectionDAG &DAG,
- const TargetLowering &TLI,
- std::string &Str, unsigned Offset) {
+ const TargetLowering &TLI,
+ std::string &Str, unsigned Offset) {
// Handle vector with all elements zero.
if (Str.empty()) {
if (VT.isInteger())
@@ -3206,7 +3190,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
SmallVector<SDValue, 8> OutChains;
unsigned NumMemOps = MemOps.size();
uint64_t SrcOff = 0, DstOff = 0;
- for (unsigned i = 0; i < NumMemOps; i++) {
+ for (unsigned i = 0; i != NumMemOps; ++i) {
EVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value, Store;
@@ -3510,25 +3494,49 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
SDValue Ptr, SDValue Cmp,
SDValue Swp, const Value* PtrVal,
unsigned Alignment) {
+ if (Alignment == 0) // Ensure that codegen never sees alignment 0
+ Alignment = getEVTAlignment(MemVT);
+
+ // Check if the memory reference references a frame index
+ if (!PtrVal)
+ if (const FrameIndexSDNode *FI =
+ dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
+ PtrVal = PseudoSourceValue::getFixedStack(FI->getIndex());
+
+ MachineFunction &MF = getMachineFunction();
+ unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
+
+ // For now, atomics are considered to be volatile always.
+ Flags |= MachineMemOperand::MOVolatile;
+
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(PtrVal, Flags, 0,
+ MemVT.getStoreSize(), Alignment);
+
+ return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Cmp, Swp, MMO);
+}
+
+SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
+ SDValue Chain,
+ SDValue Ptr, SDValue Cmp,
+ SDValue Swp, MachineMemOperand *MMO) {
assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
EVT VT = Cmp.getValueType();
- if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getEVTAlignment(MemVT);
-
SDVTList VTs = getVTList(VT, MVT::Other);
FoldingSetNodeID ID;
ID.AddInteger(MemVT.getRawBits());
SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
AddNodeIDNode(ID, Opcode, VTs, Ops, 4);
void* IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+ if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
+ cast<AtomicSDNode>(E)->refineAlignment(MMO);
return SDValue(E, 0);
+ }
SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
- new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
- Chain, Ptr, Cmp, Swp, PtrVal, Alignment);
+ new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, Chain, Ptr, Cmp, Swp, MMO);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
return SDValue(N, 0);
@@ -3539,6 +3547,32 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
SDValue Ptr, SDValue Val,
const Value* PtrVal,
unsigned Alignment) {
+ if (Alignment == 0) // Ensure that codegen never sees alignment 0
+ Alignment = getEVTAlignment(MemVT);
+
+ // Check if the memory reference references a frame index
+ if (!PtrVal)
+ if (const FrameIndexSDNode *FI =
+ dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
+ PtrVal = PseudoSourceValue::getFixedStack(FI->getIndex());
+
+ MachineFunction &MF = getMachineFunction();
+ unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
+
+ // For now, atomics are considered to be volatile always.
+ Flags |= MachineMemOperand::MOVolatile;
+
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(PtrVal, Flags, 0,
+ MemVT.getStoreSize(), Alignment);
+
+ return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Val, MMO);
+}
+
+SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
+ SDValue Chain,
+ SDValue Ptr, SDValue Val,
+ MachineMemOperand *MMO) {
assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
Opcode == ISD::ATOMIC_LOAD_SUB ||
Opcode == ISD::ATOMIC_LOAD_AND ||
@@ -3554,20 +3588,18 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
EVT VT = Val.getValueType();
- if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getEVTAlignment(MemVT);
-
SDVTList VTs = getVTList(VT, MVT::Other);
FoldingSetNodeID ID;
ID.AddInteger(MemVT.getRawBits());
SDValue Ops[] = {Chain, Ptr, Val};
AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
void* IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+ if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
+ cast<AtomicSDNode>(E)->refineAlignment(MMO);
return SDValue(E, 0);
+ }
SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
- new (N) AtomicSDNode(Opcode, dl, VTs, MemVT,
- Chain, Ptr, Val, PtrVal, Alignment);
+ new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, Chain, Ptr, Val, MMO);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
return SDValue(N, 0);
@@ -3606,23 +3638,51 @@ SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
EVT MemVT, const Value *srcValue, int SVOff,
unsigned Align, bool Vol,
bool ReadMem, bool WriteMem) {
+ if (Align == 0) // Ensure that codegen never sees alignment 0
+ Align = getEVTAlignment(MemVT);
+
+ MachineFunction &MF = getMachineFunction();
+ unsigned Flags = 0;
+ if (WriteMem)
+ Flags |= MachineMemOperand::MOStore;
+ if (ReadMem)
+ Flags |= MachineMemOperand::MOLoad;
+ if (Vol)
+ Flags |= MachineMemOperand::MOVolatile;
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(srcValue, Flags, SVOff,
+ MemVT.getStoreSize(), Align);
+
+ return getMemIntrinsicNode(Opcode, dl, VTList, Ops, NumOps, MemVT, MMO);
+}
+
+SDValue
+SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
+ const SDValue *Ops, unsigned NumOps,
+ EVT MemVT, MachineMemOperand *MMO) {
+ assert((Opcode == ISD::INTRINSIC_VOID ||
+ Opcode == ISD::INTRINSIC_W_CHAIN ||
+ (Opcode <= INT_MAX &&
+ (int)Opcode >= ISD::FIRST_TARGET_MEMORY_OPCODE)) &&
+ "Opcode is not a memory-accessing opcode!");
+
// Memoize the node unless it returns a flag.
MemIntrinsicSDNode *N;
if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+ if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
+ cast<MemIntrinsicSDNode>(E)->refineAlignment(MMO);
return SDValue(E, 0);
+ }
N = NodeAllocator.Allocate<MemIntrinsicSDNode>();
- new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
- srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
+ new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, MMO);
CSEMap.InsertNode(N, IP);
} else {
N = NodeAllocator.Allocate<MemIntrinsicSDNode>();
- new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
- srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
+ new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, MMO);
}
AllNodes.push_back(N);
return SDValue(N, 0);
@@ -3632,26 +3692,47 @@ SDValue
SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
ISD::LoadExtType ExtType, EVT VT, SDValue Chain,
SDValue Ptr, SDValue Offset,
- const Value *SV, int SVOffset, EVT EVT,
+ const Value *SV, int SVOffset, EVT MemVT,
bool isVolatile, unsigned Alignment) {
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getEVTAlignment(VT);
- if (VT == EVT) {
+ // Check if the memory reference references a frame index
+ if (!SV)
+ if (const FrameIndexSDNode *FI =
+ dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
+ SV = PseudoSourceValue::getFixedStack(FI->getIndex());
+
+ MachineFunction &MF = getMachineFunction();
+ unsigned Flags = MachineMemOperand::MOLoad;
+ if (isVolatile)
+ Flags |= MachineMemOperand::MOVolatile;
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(SV, Flags, SVOffset,
+ MemVT.getStoreSize(), Alignment);
+ return getLoad(AM, dl, ExtType, VT, Chain, Ptr, Offset, MemVT, MMO);
+}
+
+SDValue
+SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
+ ISD::LoadExtType ExtType, EVT VT, SDValue Chain,
+ SDValue Ptr, SDValue Offset, EVT MemVT,
+ MachineMemOperand *MMO) {
+ if (VT == MemVT) {
ExtType = ISD::NON_EXTLOAD;
} else if (ExtType == ISD::NON_EXTLOAD) {
- assert(VT == EVT && "Non-extending load from different memory type!");
+ assert(VT == MemVT && "Non-extending load from different memory type!");
} else {
// Extending load.
if (VT.isVector())
- assert(EVT.getVectorNumElements() == VT.getVectorNumElements() &&
+ assert(MemVT.getVectorNumElements() == VT.getVectorNumElements() &&
"Invalid vector extload!");
else
- assert(EVT.bitsLT(VT) &&
+ assert(MemVT.bitsLT(VT) &&
"Should only be an extending load, not truncating!");
assert((ExtType == ISD::EXTLOAD || VT.isInteger()) &&
"Cannot sign/zero extend a FP/Vector load!");
- assert(VT.isInteger() == EVT.isInteger() &&
+ assert(VT.isInteger() == MemVT.isInteger() &&
"Cannot convert from FP to Int or Int -> FP!");
}
@@ -3664,14 +3745,15 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
SDValue Ops[] = { Chain, Ptr, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
- ID.AddInteger(EVT.getRawBits());
- ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment));
+ ID.AddInteger(MemVT.getRawBits());
+ ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, MMO->isVolatile()));
void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+ if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
+ cast<LoadSDNode>(E)->refineAlignment(MMO);
return SDValue(E, 0);
+ }
SDNode *N = NodeAllocator.Allocate<LoadSDNode>();
- new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset,
- Alignment, isVolatile);
+ new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, MemVT, MMO);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
return SDValue(N, 0);
@@ -3689,11 +3771,11 @@ SDValue SelectionDAG::getLoad(EVT VT, DebugLoc dl,
SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
SDValue Chain, SDValue Ptr,
const Value *SV,
- int SVOffset, EVT EVT,
+ int SVOffset, EVT MemVT,
bool isVolatile, unsigned Alignment) {
SDValue Undef = getUNDEF(Ptr.getValueType());
return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
- SV, SVOffset, EVT, isVolatile, Alignment);
+ SV, SVOffset, MemVT, isVolatile, Alignment);
}
SDValue
@@ -3711,25 +3793,43 @@ SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
SDValue Ptr, const Value *SV, int SVOffset,
bool isVolatile, unsigned Alignment) {
- EVT VT = Val.getValueType();
-
if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getEVTAlignment(VT);
+ Alignment = getEVTAlignment(Val.getValueType());
+
+ // Check if the memory reference references a frame index
+ if (!SV)
+ if (const FrameIndexSDNode *FI =
+ dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
+ SV = PseudoSourceValue::getFixedStack(FI->getIndex());
+
+ MachineFunction &MF = getMachineFunction();
+ unsigned Flags = MachineMemOperand::MOStore;
+ if (isVolatile)
+ Flags |= MachineMemOperand::MOVolatile;
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(SV, Flags, SVOffset,
+ Val.getValueType().getStoreSize(), Alignment);
+ return getStore(Chain, dl, Val, Ptr, MMO);
+}
+
+SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
+ SDValue Ptr, MachineMemOperand *MMO) {
+ EVT VT = Val.getValueType();
SDVTList VTs = getVTList(MVT::Other);
SDValue Undef = getUNDEF(Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
ID.AddInteger(VT.getRawBits());
- ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED,
- isVolatile, Alignment));
+ ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile()));
void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+ if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
+ cast<StoreSDNode>(E)->refineAlignment(MMO);
return SDValue(E, 0);
+ }
SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
- new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false,
- VT, SV, SVOffset, Alignment, isVolatile);
+ new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, VT, MMO);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
return SDValue(N, 0);
@@ -3739,17 +3839,37 @@ SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
SDValue Ptr, const Value *SV,
int SVOffset, EVT SVT,
bool isVolatile, unsigned Alignment) {
+ if (Alignment == 0) // Ensure that codegen never sees alignment 0
+ Alignment = getEVTAlignment(SVT);
+
+ // Check if the memory reference references a frame index
+ if (!SV)
+ if (const FrameIndexSDNode *FI =
+ dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
+ SV = PseudoSourceValue::getFixedStack(FI->getIndex());
+
+ MachineFunction &MF = getMachineFunction();
+ unsigned Flags = MachineMemOperand::MOStore;
+ if (isVolatile)
+ Flags |= MachineMemOperand::MOVolatile;
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(SV, Flags, SVOffset, SVT.getStoreSize(), Alignment);
+
+ return getTruncStore(Chain, dl, Val, Ptr, SVT, MMO);
+}
+
+SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
+ SDValue Ptr, EVT SVT,
+ MachineMemOperand *MMO) {
EVT VT = Val.getValueType();
if (VT == SVT)
- return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment);
+ return getStore(Chain, dl, Val, Ptr, MMO);
assert(VT.bitsGT(SVT) && "Not a truncation?");
assert(VT.isInteger() == SVT.isInteger() &&
"Can't do FP-INT conversion!");
- if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getEVTAlignment(VT);
SDVTList VTs = getVTList(MVT::Other);
SDValue Undef = getUNDEF(Ptr.getValueType());
@@ -3757,14 +3877,14 @@ SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
ID.AddInteger(SVT.getRawBits());
- ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED,
- isVolatile, Alignment));
+ ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile()));
void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+ if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
+ cast<StoreSDNode>(E)->refineAlignment(MMO);
return SDValue(E, 0);
+ }
SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
- new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true,
- SVT, SV, SVOffset, Alignment, isVolatile);
+ new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, SVT, MMO);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
return SDValue(N, 0);
@@ -3788,8 +3908,7 @@ SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base,
SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
new (N) StoreSDNode(Ops, dl, VTs, AM,
ST->isTruncatingStore(), ST->getMemoryVT(),
- ST->getSrcValue(), ST->getSrcValueOffset(),
- ST->getAlignment(), ST->isVolatile());
+ ST->getMemOperand());
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
return SDValue(N, 0);
@@ -4441,29 +4560,35 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
DeadNodeSet.insert(Used);
}
- // If NumOps is larger than the # of operands we currently have, reallocate
- // the operand list.
- if (NumOps > N->NumOperands) {
- if (N->OperandsNeedDelete)
- delete[] N->OperandList;
-
- if (N->isMachineOpcode()) {
- // We're creating a final node that will live unmorphed for the
- // remainder of the current SelectionDAG iteration, so we can allocate
- // the operands directly out of a pool with no recycling metadata.
- N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps);
- N->OperandsNeedDelete = false;
- } else {
- N->OperandList = new SDUse[NumOps];
+ if (MachineSDNode *MN = dyn_cast<MachineSDNode>(N)) {
+ // Initialize the memory references information.
+ MN->setMemRefs(0, 0);
+ // If NumOps is larger than the # of operands we can have in a
+ // MachineSDNode, reallocate the operand list.
+ if (NumOps > MN->NumOperands || !MN->OperandsNeedDelete) {
+ if (MN->OperandsNeedDelete)
+ delete[] MN->OperandList;
+ if (NumOps > array_lengthof(MN->LocalOperands))
+ // We're creating a final node that will live unmorphed for the
+ // remainder of the current SelectionDAG iteration, so we can allocate
+ // the operands directly out of a pool with no recycling metadata.
+ MN->InitOperands(OperandAllocator.Allocate<SDUse>(NumOps),
+ Ops, NumOps);
+ else
+ MN->InitOperands(MN->LocalOperands, Ops, NumOps);
+ MN->OperandsNeedDelete = false;
+ } else
+ MN->InitOperands(MN->OperandList, Ops, NumOps);
+ } else {
+ // If NumOps is larger than the # of operands we currently have, reallocate
+ // the operand list.
+ if (NumOps > N->NumOperands) {
+ if (N->OperandsNeedDelete)
+ delete[] N->OperandList;
+ N->InitOperands(new SDUse[NumOps], Ops, NumOps);
N->OperandsNeedDelete = true;
- }
- }
-
- // Assign the new operands.
- N->NumOperands = NumOps;
- for (unsigned i = 0, e = NumOps; i != e; ++i) {
- N->OperandList[i].setUser(N);
- N->OperandList[i].setInitial(Ops[i]);
+ } else
+ MN->InitOperands(MN->OperandList, Ops, NumOps);
}
// Delete any nodes that are still dead after adding the uses for the
@@ -4481,108 +4606,156 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
}
-/// getTargetNode - These are used for target selectors to create a new node
-/// with specified return type(s), target opcode, and operands.
+/// getMachineNode - These are used for target selectors to create a new node
+/// with specified return type(s), MachineInstr opcode, and operands.
///
-/// Note that getTargetNode returns the resultant node. If there is already a
+/// Note that getMachineNode returns the resultant node. If there is already a
/// node of the specified opcode and operands, it returns that node instead of
/// the current one.
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT) {
- return getNode(~Opcode, dl, VT).getNode();
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT) {
+ SDVTList VTs = getVTList(VT);
+ return getMachineNode(Opcode, dl, VTs, 0, 0);
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
- SDValue Op1) {
- return getNode(~Opcode, dl, VT, Op1).getNode();
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT,
+ SDValue Op1) {
+ SDVTList VTs = getVTList(VT);
+ SDValue Ops[] = { Op1 };
+ return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops));
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
- SDValue Op1, SDValue Op2) {
- return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT,
+ SDValue Op1, SDValue Op2) {
+ SDVTList VTs = getVTList(VT);
+ SDValue Ops[] = { Op1, Op2 };
+ return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops));
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
- SDValue Op1, SDValue Op2,
- SDValue Op3) {
- return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT,
+ SDValue Op1, SDValue Op2,
+ SDValue Op3) {
+ SDVTList VTs = getVTList(VT);
+ SDValue Ops[] = { Op1, Op2, Op3 };
+ return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops));
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
- const SDValue *Ops, unsigned NumOps) {
- return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT,
+ const SDValue *Ops, unsigned NumOps) {
+ SDVTList VTs = getVTList(VT);
+ return getMachineNode(Opcode, dl, VTs, Ops, NumOps);
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- EVT VT1, EVT VT2) {
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl,
+ EVT VT1, EVT VT2) {
SDVTList VTs = getVTList(VT1, VT2);
- SDValue Op;
- return getNode(~Opcode, dl, VTs, &Op, 0).getNode();
+ return getMachineNode(Opcode, dl, VTs, 0, 0);
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
- EVT VT2, SDValue Op1) {
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1) {
SDVTList VTs = getVTList(VT1, VT2);
- return getNode(~Opcode, dl, VTs, &Op1, 1).getNode();
+ SDValue Ops[] = { Op1 };
+ return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops));
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
- EVT VT2, SDValue Op1,
- SDValue Op2) {
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1,
+ SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2 };
- return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
+ return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops));
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
- EVT VT2, SDValue Op1,
- SDValue Op2, SDValue Op3) {
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1,
+ SDValue Op2, SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2, Op3 };
- return getNode(~Opcode, dl, VTs, Ops, 3).getNode();
+ return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops));
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- EVT VT1, EVT VT2,
- const SDValue *Ops, unsigned NumOps) {
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl,
+ EVT VT1, EVT VT2,
+ const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2);
- return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
+ return getMachineNode(Opcode, dl, VTs, Ops, NumOps);
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- EVT VT1, EVT VT2, EVT VT3,
- SDValue Op1, SDValue Op2) {
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl,
+ EVT VT1, EVT VT2, EVT VT3,
+ SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
SDValue Ops[] = { Op1, Op2 };
- return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
+ return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops));
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- EVT VT1, EVT VT2, EVT VT3,
- SDValue Op1, SDValue Op2,
- SDValue Op3) {
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl,
+ EVT VT1, EVT VT2, EVT VT3,
+ SDValue Op1, SDValue Op2,
+ SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
SDValue Ops[] = { Op1, Op2, Op3 };
- return getNode(~Opcode, dl, VTs, Ops, 3).getNode();
+ return getMachineNode(Opcode, dl, VTs, Ops, array_lengthof(Ops));
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- EVT VT1, EVT VT2, EVT VT3,
- const SDValue *Ops, unsigned NumOps) {
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl,
+ EVT VT1, EVT VT2, EVT VT3,
+ const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
- return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
+ return getMachineNode(Opcode, dl, VTs, Ops, NumOps);
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
- EVT VT2, EVT VT3, EVT VT4,
- const SDValue *Ops, unsigned NumOps) {
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, EVT VT3, EVT VT4,
+ const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
- return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
+ return getMachineNode(Opcode, dl, VTs, Ops, NumOps);
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- const std::vector<EVT> &ResultTys,
- const SDValue *Ops, unsigned NumOps) {
- return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode();
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl,
+ const std::vector<EVT> &ResultTys,
+ const SDValue *Ops, unsigned NumOps) {
+ SDVTList VTs = getVTList(&ResultTys[0], ResultTys.size());
+ return getMachineNode(Opcode, dl, VTs, Ops, NumOps);
+}
+
+SDNode *SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
+ const SDValue *Ops, unsigned NumOps) {
+ bool DoCSE = VTs.VTs[VTs.NumVTs-1] != MVT::Flag;
+ MachineSDNode *N;
+ void *IP;
+
+ if (DoCSE) {
+ FoldingSetNodeID ID;
+ AddNodeIDNode(ID, ~Opcode, VTs, Ops, NumOps);
+ IP = 0;
+ if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+ return E;
+ }
+
+ // Allocate a new MachineSDNode.
+ N = NodeAllocator.Allocate<MachineSDNode>();
+ new (N) MachineSDNode(~Opcode, DL, VTs);
+
+ // Initialize the operands list.
+ if (NumOps > array_lengthof(N->LocalOperands))
+ // We're creating a final node that will live unmorphed for the
+ // remainder of the current SelectionDAG iteration, so we can allocate
+ // the operands directly out of a pool with no recycling metadata.
+ N->InitOperands(OperandAllocator.Allocate<SDUse>(NumOps),
+ Ops, NumOps);
+ else
+ N->InitOperands(N->LocalOperands, Ops, NumOps);
+ N->OperandsNeedDelete = false;
+
+ if (DoCSE)
+ CSEMap.InsertNode(N, IP);
+
+ AllNodes.push_back(N);
+#ifndef NDEBUG
+ VerifyNode(N);
+#endif
+ return N;
}
/// getTargetExtractSubreg - A convenience function for creating
@@ -4591,8 +4764,8 @@ SDValue
SelectionDAG::getTargetExtractSubreg(int SRIdx, DebugLoc DL, EVT VT,
SDValue Operand) {
SDValue SRIdxVal = getTargetConstant(SRIdx, MVT::i32);
- SDNode *Subreg = getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, DL,
- VT, Operand, SRIdxVal);
+ SDNode *Subreg = getMachineNode(TargetInstrInfo::EXTRACT_SUBREG, DL,
+ VT, Operand, SRIdxVal);
return SDValue(Subreg, 0);
}
@@ -4955,57 +5128,21 @@ GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA,
}
MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, EVT memvt,
- const Value *srcValue, int SVO,
- unsigned alignment, bool vol)
- : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
- SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment);
- assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
- assert(getAlignment() == alignment && "Alignment representation error!");
- assert(isVolatile() == vol && "Volatile representation error!");
+ MachineMemOperand *mmo)
+ : SDNode(Opc, dl, VTs), MemoryVT(memvt), MMO(mmo) {
+ SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile());
+ assert(isVolatile() == MMO->isVolatile() && "Volatile encoding error!");
+ assert(memvt.getStoreSize() == MMO->getSize() && "Size mismatch!");
}
MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
- const SDValue *Ops,
- unsigned NumOps, EVT memvt, const Value *srcValue,
- int SVO, unsigned alignment, bool vol)
+ const SDValue *Ops, unsigned NumOps, EVT memvt,
+ MachineMemOperand *mmo)
: SDNode(Opc, dl, VTs, Ops, NumOps),
- MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
- SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment);
- assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
- assert(getAlignment() == alignment && "Alignment representation error!");
- assert(isVolatile() == vol && "Volatile representation error!");
-}
-
-/// getMemOperand - Return a MachineMemOperand object describing the memory
-/// reference performed by this memory reference.
-MachineMemOperand MemSDNode::getMemOperand() const {
- int Flags = 0;
- if (isa<LoadSDNode>(this))
- Flags = MachineMemOperand::MOLoad;
- else if (isa<StoreSDNode>(this))
- Flags = MachineMemOperand::MOStore;
- else if (isa<AtomicSDNode>(this)) {
- Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
- }
- else {
- const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this);
- assert(MemIntrinNode && "Unknown MemSDNode opcode!");
- if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad;
- if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore;
- }
-
- int Size = (getMemoryVT().getSizeInBits() + 7) >> 3;
- if (isVolatile()) Flags |= MachineMemOperand::MOVolatile;
-
- // Check if the memory reference references a frame index
- const FrameIndexSDNode *FI =
- dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode());
- if (!getSrcValue() && FI)
- return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()),
- Flags, 0, Size, getAlignment());
- else
- return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(),
- Size, getAlignment());
+ MemoryVT(memvt), MMO(mmo) {
+ SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile());
+ assert(isVolatile() == MMO->isVolatile() && "Volatile encoding error!");
+ assert(memvt.getStoreSize() == MMO->getSize() && "Size mismatch!");
}
/// Profile - Gather unique data for the node.
@@ -5208,7 +5345,6 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::PCMARKER: return "PCMarker";
case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
case ISD::SRCVALUE: return "SrcValue";
- case ISD::MEMOPERAND: return "MemOperand";
case ISD::EntryToken: return "EntryToken";
case ISD::TokenFactor: return "TokenFactor";
case ISD::AssertSext: return "AssertSext";
@@ -5487,8 +5623,20 @@ void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const {
}
void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
- if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) {
- const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(this);
+ if (const MachineSDNode *MN = dyn_cast<MachineSDNode>(this)) {
+ if (!MN->memoperands_empty()) {
+ OS << "<";
+ OS << "Mem:";
+ for (MachineSDNode::mmo_iterator i = MN->memoperands_begin(),
+ e = MN->memoperands_end(); i != e; ++i) {
+ OS << **i;
+ if (next(i) != e)
+ OS << " ";
+ }
+ OS << ">";
+ }
+ } else if (const ShuffleVectorSDNode *SVN =
+ dyn_cast<ShuffleVectorSDNode>(this)) {
OS << "<";
for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) {
int Idx = SVN->getMaskElt(i);
@@ -5499,9 +5647,7 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
OS << Idx;
}
OS << ">";
- }
-
- if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) {
+ } else if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) {
OS << '<' << CSDN->getAPIntValue() << '>';
} else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle)
@@ -5566,71 +5712,40 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
OS << "<" << M->getValue() << ">";
else
OS << "<null>";
- } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) {
- if (M->MO.getValue())
- OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">";
- else
- OS << "<null:" << M->MO.getOffset() << ">";
} else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
OS << ":" << N->getVT().getEVTString();
}
else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
- const Value *SrcValue = LD->getSrcValue();
- int SrcOffset = LD->getSrcValueOffset();
- OS << " <";
- if (SrcValue)
- OS << SrcValue;
- else
- OS << "null";
- OS << ":" << SrcOffset << ">";
+ OS << " <" << *LD->getMemOperand();
bool doExt = true;
switch (LD->getExtensionType()) {
default: doExt = false; break;
- case ISD::EXTLOAD: OS << " <anyext "; break;
- case ISD::SEXTLOAD: OS << " <sext "; break;
- case ISD::ZEXTLOAD: OS << " <zext "; break;
+ case ISD::EXTLOAD: OS << ", anyext"; break;
+ case ISD::SEXTLOAD: OS << ", sext"; break;
+ case ISD::ZEXTLOAD: OS << ", zext"; break;
}
if (doExt)
- OS << LD->getMemoryVT().getEVTString() << ">";
+ OS << " from " << LD->getMemoryVT().getEVTString();
const char *AM = getIndexedModeName(LD->getAddressingMode());
if (*AM)
- OS << " " << AM;
- if (LD->isVolatile())
- OS << " <volatile>";
- OS << " alignment=" << LD->getAlignment();
+ OS << ", " << AM;
+
+ OS << ">";
} else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) {
- const Value *SrcValue = ST->getSrcValue();
- int SrcOffset = ST->getSrcValueOffset();
- OS << " <";
- if (SrcValue)
- OS << SrcValue;
- else
- OS << "null";
- OS << ":" << SrcOffset << ">";
+ OS << " <" << *ST->getMemOperand();
if (ST->isTruncatingStore())
- OS << " <trunc " << ST->getMemoryVT().getEVTString() << ">";
+ OS << ", trunc to " << ST->getMemoryVT().getEVTString();
const char *AM = getIndexedModeName(ST->getAddressingMode());
if (*AM)
- OS << " " << AM;
- if (ST->isVolatile())
- OS << " <volatile>";
- OS << " alignment=" << ST->getAlignment();
- } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) {
- const Value *SrcValue = AT->getSrcValue();
- int SrcOffset = AT->getSrcValueOffset();
- OS << " <";
- if (SrcValue)
- OS << SrcValue;
- else
- OS << "null";
- OS << ":" << SrcOffset << ">";
- if (AT->isVolatile())
- OS << " <volatile>";
- OS << " alignment=" << AT->getAlignment();
+ OS << ", " << AM;
+
+ OS << ">";
+ } else if (const MemSDNode* M = dyn_cast<MemSDNode>(this)) {
+ OS << " <" << *M->getMemOperand() << ">";
}
}
@@ -5716,6 +5831,11 @@ void SDNode::dumpr() const {
DumpNodesr(errs(), this, 0, 0, once);
}
+void SDNode::dumpr(const SelectionDAG *G) const {
+ VisitedSDNodeSet once;
+ DumpNodesr(errs(), this, 0, G, once);
+}
+
// getAddressSpace - Return the address space this GlobalAddress belongs to.
unsigned GlobalAddressSDNode::getAddressSpace() const {
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 0a161d0..a27fbe6 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -751,6 +751,7 @@ void SelectionDAGLowering::clear() {
NodeMap.clear();
PendingLoads.clear();
PendingExports.clear();
+ EdgeMapping.clear();
DAG.clear();
CurDebugLoc = DebugLoc::getUnknownLoc();
HasTailCall = false;
@@ -861,6 +862,10 @@ SDValue SelectionDAGLowering::getValue(const Value *V) {
for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
OI != OE; ++OI) {
SDNode *Val = getValue(*OI).getNode();
+ // If the operand is an empty aggregate, there are no values.
+ if (!Val) continue;
+ // Add each leaf value from the operand to the Constants list
+ // to form a flattened list of all the values.
for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
Constants.push_back(SDValue(Val, i));
}
@@ -989,7 +994,8 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
}
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
- unsigned CallConv = DAG.getMachineFunction().getFunction()->getCallingConv();
+ CallingConv::ID CallConv =
+ DAG.getMachineFunction().getFunction()->getCallingConv();
Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
Outs, getCurDebugLoc(), DAG);
@@ -1713,11 +1719,8 @@ bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
MachineFunction *CurMF = FuncInfo.MF;
// Figure out which block is immediately after the current one.
- MachineBasicBlock *NextBlock = 0;
MachineFunction::iterator BBI = CR.CaseBB;
-
- if (++BBI != FuncInfo.MF->end())
- NextBlock = BBI;
+ ++BBI;
const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
@@ -1786,11 +1789,8 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
MachineFunction *CurMF = FuncInfo.MF;
// Figure out which block is immediately after the current one.
- MachineBasicBlock *NextBlock = 0;
MachineFunction::iterator BBI = CR.CaseBB;
-
- if (++BBI != FuncInfo.MF->end())
- NextBlock = BBI;
+ ++BBI;
Case& FrontCase = *CR.Range.first;
Case& BackCase = *(CR.Range.second-1);
@@ -2813,11 +2813,10 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) {
EVT PtrVT = Ptr.getValueType();
for (unsigned i = 0; i != NumValues; ++i) {
SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
- DAG.getNode(ISD::ADD, getCurDebugLoc(),
- PtrVT, Ptr,
- DAG.getConstant(Offsets[i], PtrVT)),
- SV, Offsets[i],
- isVolatile, Alignment);
+ DAG.getNode(ISD::ADD, getCurDebugLoc(),
+ PtrVT, Ptr,
+ DAG.getConstant(Offsets[i], PtrVT)),
+ SV, Offsets[i], isVolatile, Alignment);
Values[i] = L;
Chains[i] = L.getValue(1);
}
@@ -2866,8 +2865,7 @@ void SelectionDAGLowering::visitStore(StoreInst &I) {
DAG.getNode(ISD::ADD, getCurDebugLoc(),
PtrVT, Ptr,
DAG.getConstant(Offsets[i], PtrVT)),
- PtrV, Offsets[i],
- isVolatile, Alignment);
+ PtrV, Offsets[i], isVolatile, Alignment);
DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
MVT::Other, &Chains[0], NumValues));
@@ -3980,7 +3978,11 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
// Don't handle byval struct arguments or VLAs, for example.
if (!AI)
return 0;
- int FI = FuncInfo.StaticAllocaMap[AI];
+ DenseMap<const AllocaInst*, int>::iterator SI =
+ FuncInfo.StaticAllocaMap.find(AI);
+ if (SI == FuncInfo.StaticAllocaMap.end())
+ return 0; // VLAs.
+ int FI = SI->second;
DW->RecordVariable(cast<MDNode>(Variable), FI);
return 0;
}
@@ -3999,32 +4001,35 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
case Intrinsic::eh_selector_i32:
case Intrinsic::eh_selector_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
- EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? MVT::i32 : MVT::i64);
- if (MMI) {
- if (CurMBB->isLandingPad())
- AddCatchInfo(I, MMI, CurMBB);
- else {
+ if (CurMBB->isLandingPad())
+ AddCatchInfo(I, MMI, CurMBB);
+ else {
#ifndef NDEBUG
- FuncInfo.CatchInfoLost.insert(&I);
+ FuncInfo.CatchInfoLost.insert(&I);
#endif
- // FIXME: Mark exception selector register as live in. Hack for PR1508.
- unsigned Reg = TLI.getExceptionSelectorRegister();
- if (Reg) CurMBB->addLiveIn(Reg);
- }
-
- // Insert the EHSELECTION instruction.
- SDVTList VTs = DAG.getVTList(VT, MVT::Other);
- SDValue Ops[2];
- Ops[0] = getValue(I.getOperand(1));
- Ops[1] = getRoot();
- SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
- setValue(&I, Op);
- DAG.setRoot(Op.getValue(1));
- } else {
- setValue(&I, DAG.getConstant(0, VT));
+ // FIXME: Mark exception selector register as live in. Hack for PR1508.
+ unsigned Reg = TLI.getExceptionSelectorRegister();
+ if (Reg) CurMBB->addLiveIn(Reg);
}
+ // Insert the EHSELECTION instruction.
+ SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
+ SDValue Ops[2];
+ Ops[0] = getValue(I.getOperand(1));
+ Ops[1] = getRoot();
+ SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
+
+ DAG.setRoot(Op.getValue(1));
+
+ MVT::SimpleValueType VT =
+ (Intrinsic == Intrinsic::eh_selector_i32 ? MVT::i32 : MVT::i64);
+ if (Op.getValueType().getSimpleVT() < VT)
+ Op = DAG.getNode(ISD::SIGN_EXTEND, dl, VT, Op);
+ else if (Op.getValueType().getSimpleVT() < VT)
+ Op = DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
+
+ setValue(&I, Op);
return 0;
}
@@ -4556,7 +4561,8 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
} else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
if (I.getNumOperands() == 2 && // Basic sanity checks.
I.getOperand(1)->getType()->isFloatingPoint() &&
- I.getType() == I.getOperand(1)->getType()) {
+ I.getType() == I.getOperand(1)->getType() &&
+ I.onlyReadsMemory()) {
SDValue Tmp = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
Tmp.getValueType(), Tmp));
@@ -4565,12 +4571,23 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
} else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
if (I.getNumOperands() == 2 && // Basic sanity checks.
I.getOperand(1)->getType()->isFloatingPoint() &&
- I.getType() == I.getOperand(1)->getType()) {
+ I.getType() == I.getOperand(1)->getType() &&
+ I.onlyReadsMemory()) {
SDValue Tmp = getValue(I.getOperand(1));
setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
Tmp.getValueType(), Tmp));
return;
}
+ } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
+ if (I.getNumOperands() == 2 && // Basic sanity checks.
+ I.getOperand(1)->getType()->isFloatingPoint() &&
+ I.getType() == I.getOperand(1)->getType() &&
+ I.onlyReadsMemory()) {
+ SDValue Tmp = getValue(I.getOperand(1));
+ setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
+ Tmp.getValueType(), Tmp));
+ return;
+ }
}
}
} else if (isa<InlineAsm>(I.getOperand(0))) {
@@ -5613,7 +5630,7 @@ std::pair<SDValue, SDValue>
TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg,
bool isInreg, unsigned NumFixedArgs,
- unsigned CallConv, bool isTailCall,
+ CallingConv::ID CallConv, bool isTailCall,
bool isReturnValueUsed,
SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
index 9a079d6..06acc8a 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
@@ -345,9 +345,15 @@ public:
/// BitTestCases - Vector of BitTestBlock structures used to communicate
/// SwitchInst code generation information.
std::vector<BitTestBlock> BitTestCases;
-
+
+ /// PHINodesToUpdate - A list of phi instructions whose operand list will
+ /// be updated after processing the current basic block.
std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
+ /// EdgeMapping - If an edge from CurMBB to any MBB is changed (e.g. due to
+ /// scheduler custom lowering), track the change here.
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> EdgeMapping;
+
// Emit PHI-node-operand constants only once even if used by multiple
// PHI nodes.
DenseMap<Constant*, unsigned> ConstantsOut;
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 8eb16e5..8591da7 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -16,6 +16,7 @@
#include "SelectionDAGBuild.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/DebugInfo.h"
#include "llvm/Constants.h"
#include "llvm/CallingConv.h"
#include "llvm/DerivedTypes.h"
@@ -153,14 +154,15 @@ namespace llvm {
// insert. The specified MachineInstr is created but not inserted into any
// basic blocks, and the scheduler passes ownership of it to this method.
MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
- MachineBasicBlock *MBB) const {
+ MachineBasicBlock *MBB,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
#ifndef NDEBUG
errs() << "If a target marks an instruction with "
"'usesCustomDAGSchedInserter', it must implement "
"TargetLowering::EmitInstrWithCustomInserter!";
#endif
llvm_unreachable(0);
- return 0;
+ return 0;
}
/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
@@ -223,7 +225,7 @@ static void EmitLiveInCopy(MachineBasicBlock *MBB,
bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
assert(Emitted && "Unable to issue a live-in copy instruction!\n");
(void) Emitted;
-
+
CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
if (Coalesced) {
if (&*InsertPos == UseMI) ++InsertPos;
@@ -370,12 +372,24 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
BasicBlock::iterator Begin,
BasicBlock::iterator End) {
SDL->setCurrentBasicBlock(BB);
+ MetadataContext &TheMetadata = LLVMBB->getParent()->getContext().getMetadata();
+ unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
// Lower all of the non-terminator instructions. If a call is emitted
// as a tail call, cease emitting nodes for this block.
- for (BasicBlock::iterator I = Begin; I != End && !SDL->HasTailCall; ++I)
+ for (BasicBlock::iterator I = Begin; I != End && !SDL->HasTailCall; ++I) {
+ if (MDDbgKind) {
+ // Update DebugLoc if debug information is attached with this
+ // instruction.
+ if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, I)) {
+ DILocation DILoc(Dbg);
+ DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
+ SDL->setCurDebugLoc(Loc);
+ }
+ }
if (!isa<TerminatorInst>(I))
SDL->visit(*I);
+ }
if (!SDL->HasTailCall) {
// Ensure that all instructions which are used outside of their defining
@@ -392,7 +406,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
SDL->visit(*LLVMBB->getTerminator());
}
}
-
+
// Make sure the root of the DAG is up-to-date.
CurDAG->setRoot(SDL->getControlRoot());
@@ -404,44 +418,44 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
void SelectionDAGISel::ComputeLiveOutVRegInfo() {
SmallPtrSet<SDNode*, 128> VisitedNodes;
SmallVector<SDNode*, 128> Worklist;
-
+
Worklist.push_back(CurDAG->getRoot().getNode());
-
+
APInt Mask;
APInt KnownZero;
APInt KnownOne;
-
+
while (!Worklist.empty()) {
SDNode *N = Worklist.back();
Worklist.pop_back();
-
+
// If we've already seen this node, ignore it.
if (!VisitedNodes.insert(N))
continue;
-
+
// Otherwise, add all chain operands to the worklist.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
if (N->getOperand(i).getValueType() == MVT::Other)
Worklist.push_back(N->getOperand(i).getNode());
-
+
// If this is a CopyToReg with a vreg dest, process it.
if (N->getOpcode() != ISD::CopyToReg)
continue;
-
+
unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
if (!TargetRegisterInfo::isVirtualRegister(DestReg))
continue;
-
+
// Ignore non-scalar or non-integer values.
SDValue Src = N->getOperand(2);
EVT SrcVT = Src.getValueType();
if (!SrcVT.isInteger() || SrcVT.isVector())
continue;
-
+
unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
-
+
// Only install this information if it tells us something.
if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
DestReg -= TargetRegisterInfo::FirstVirtualRegister;
@@ -479,10 +493,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
} else {
CurDAG->Combine(Unrestricted, *AA, OptLevel);
}
-
+
DEBUG(errs() << "Optimized lowered selection DAG:\n");
DEBUG(CurDAG->dump());
-
+
// Second step, hack on the DAG until it only uses operations and types that
// the target supports.
if (!DisableLegalizeTypes) {
@@ -546,7 +560,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
DEBUG(CurDAG->dump());
}
}
-
+
if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
if (TimePassesIsEnabled) {
@@ -555,10 +569,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
} else {
CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
}
-
+
DEBUG(errs() << "Legalized selection DAG:\n");
DEBUG(CurDAG->dump());
-
+
if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
// Run the DAG combiner in post-legalize mode.
@@ -568,12 +582,12 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
} else {
CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
}
-
+
DEBUG(errs() << "Optimized legalized selection DAG:\n");
DEBUG(CurDAG->dump());
if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
-
+
if (OptLevel != CodeGenOpt::None)
ComputeLiveOutVRegInfo();
@@ -602,13 +616,13 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
if (ViewSUnitDAGs) Scheduler->viewGraph();
- // Emit machine code to BB. This can change 'BB' to the last block being
+ // Emit machine code to BB. This can change 'BB' to the last block being
// inserted into.
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Creation", GroupName);
- BB = Scheduler->EmitSchedule();
+ BB = Scheduler->EmitSchedule(&SDL->EdgeMapping);
} else {
- BB = Scheduler->EmitSchedule();
+ BB = Scheduler->EmitSchedule(&SDL->EdgeMapping);
}
// Free the scheduler state.
@@ -621,7 +635,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
DEBUG(errs() << "Selected machine code:\n");
DEBUG(BB->dump());
-}
+}
void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
MachineFunction &MF,
@@ -640,6 +654,9 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
#endif
);
+ MetadataContext &TheMetadata = Fn.getContext().getMetadata();
+ unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
+
// Iterate over all basic blocks in the function.
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
BasicBlock *LLVMBB = &*I;
@@ -722,6 +739,17 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
FastIS->startNewBlock(BB);
// Do FastISel on as many instructions as possible.
for (; BI != End; ++BI) {
+ if (MDDbgKind) {
+ // Update DebugLoc if debug information is attached with this
+ // instruction.
+ if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, BI)) {
+ DILocation DILoc(Dbg);
+ DebugLoc Loc = ExtractDebugLocation(DILoc,
+ MF.getDebugLocInfo());
+ FastIS->setCurDebugLoc(Loc);
+ }
+ }
+
// Just before the terminator instruction, insert instructions to
// feed PHI nodes in successor blocks.
if (isa<TerminatorInst>(BI))
@@ -730,7 +758,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
errs() << "FastISel miss: ";
BI->dump();
}
- assert(!EnableFastISelAbort &&
+ assert(!EnableFastISelAbort &&
"FastISel didn't handle a PHI in a successor");
break;
}
@@ -808,7 +836,7 @@ SelectionDAGISel::FinishBasicBlock() {
errs() << "Node " << i << " : ("
<< SDL->PHINodesToUpdate[i].first
<< ", " << SDL->PHINodesToUpdate[i].second << ")\n");
-
+
// Next, now that we know what the last MBB the LLVM BB expanded is, update
// PHI nodes in successors.
if (SDL->SwitchCases.empty() &&
@@ -837,7 +865,7 @@ SelectionDAGISel::FinishBasicBlock() {
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
SDL->clear();
- }
+ }
for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
// Set the current basic block to the mbb we wish to insert the code into
@@ -852,8 +880,8 @@ SelectionDAGISel::FinishBasicBlock() {
SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
SDL->BitTestCases[i].Reg,
SDL->BitTestCases[i].Cases[j]);
-
-
+
+
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
SDL->clear();
@@ -906,7 +934,7 @@ SelectionDAGISel::FinishBasicBlock() {
CodeGenAndEmitDAG();
SDL->clear();
}
-
+
// Set the current basic block to the mbb we wish to insert the code into
BB = SDL->JTCases[i].second.MBB;
SDL->setCurrentBasicBlock(BB);
@@ -915,7 +943,7 @@ SelectionDAGISel::FinishBasicBlock() {
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
SDL->clear();
-
+
// Update PHI Nodes
for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
@@ -924,20 +952,21 @@ SelectionDAGISel::FinishBasicBlock() {
"This is not a machine PHI node that we are updating!");
// "default" BB. We can go there only from header BB.
if (PHIBB == SDL->JTCases[i].second.Default) {
- PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
- false));
- PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
+ PHI->addOperand
+ (MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, false));
+ PHI->addOperand
+ (MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
}
// JT BB. Just iterate over successors here
if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
- PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
- false));
+ PHI->addOperand
+ (MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second, false));
PHI->addOperand(MachineOperand::CreateMBB(BB));
}
}
}
SDL->JTCases.clear();
-
+
// If the switch block involved a branch to one of the actual successors, we
// need to update PHI nodes in that block.
for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
@@ -950,25 +979,31 @@ SelectionDAGISel::FinishBasicBlock() {
PHI->addOperand(MachineOperand::CreateMBB(BB));
}
}
-
+
// If we generated any switch lowering information, build and codegen any
// additional DAGs necessary.
for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
// Set the current basic block to the mbb we wish to insert the code into
- BB = SDL->SwitchCases[i].ThisBB;
+ MachineBasicBlock *ThisBB = BB = SDL->SwitchCases[i].ThisBB;
SDL->setCurrentBasicBlock(BB);
-
+
// Emit the code
SDL->visitSwitchCase(SDL->SwitchCases[i]);
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
- SDL->clear();
-
+
// Handle any PHI nodes in successors of this chunk, as if we were coming
// from the original BB before switch expansion. Note that PHI nodes can
// occur multiple times in PHINodesToUpdate. We have to be very careful to
// handle them the right number of times.
while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
+ // If new BB's are created during scheduling, the edges may have been
+ // updated. That is, the edge from ThisBB to BB may have been split and
+ // BB's predecessor is now another block.
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
+ SDL->EdgeMapping.find(BB);
+ if (EI != SDL->EdgeMapping.end())
+ ThisBB = EI->second;
for (MachineBasicBlock::iterator Phi = BB->begin();
Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
// This value for this PHI node is recorded in PHINodesToUpdate, get it.
@@ -978,21 +1013,22 @@ SelectionDAGISel::FinishBasicBlock() {
if (SDL->PHINodesToUpdate[pn].first == Phi) {
Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
second, false));
- Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
+ Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
break;
}
}
}
-
+
// Don't process RHS if same block as LHS.
if (BB == SDL->SwitchCases[i].FalseBB)
SDL->SwitchCases[i].FalseBB = 0;
-
+
// If we haven't handled the RHS, do so now. Otherwise, we're done.
SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
SDL->SwitchCases[i].FalseBB = 0;
}
assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
+ SDL->clear();
}
SDL->SwitchCases.clear();
@@ -1006,12 +1042,12 @@ SelectionDAGISel::FinishBasicBlock() {
///
ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
-
+
if (!Ctor) {
Ctor = ISHeuristic;
RegisterScheduler::setDefault(Ctor);
}
-
+
return Ctor(this, OptLevel);
}
@@ -1028,25 +1064,25 @@ ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
/// the dag combiner simplified the 255, we still want to match. RHS is the
/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
/// specified in the .td file (e.g. 255).
-bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
+bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const {
const APInt &ActualMask = RHS->getAPIntValue();
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
-
+
// If the actual mask exactly matches, success!
if (ActualMask == DesiredMask)
return true;
-
+
// If the actual AND mask is allowing unallowed bits, this doesn't match.
if (ActualMask.intersects(~DesiredMask))
return false;
-
+
// Otherwise, the DAG Combiner may have proven that the value coming in is
// either already zero or is not demanded. Check for known zero input bits.
APInt NeededMask = DesiredMask & ~ActualMask;
if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
return true;
-
+
// TODO: check to see if missing bits are just not demanded.
// Otherwise, this pattern doesn't match.
@@ -1057,32 +1093,32 @@ bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
/// the dag combiner simplified the 255, we still want to match. RHS is the
/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
/// specified in the .td file (e.g. 255).
-bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
+bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const {
const APInt &ActualMask = RHS->getAPIntValue();
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
-
+
// If the actual mask exactly matches, success!
if (ActualMask == DesiredMask)
return true;
-
+
// If the actual AND mask is allowing unallowed bits, this doesn't match.
if (ActualMask.intersects(~DesiredMask))
return false;
-
+
// Otherwise, the DAG Combiner may have proven that the value coming in is
// either already zero or is not demanded. Check for known zero input bits.
APInt NeededMask = DesiredMask & ~ActualMask;
-
+
APInt KnownZero, KnownOne;
CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
-
+
// If all the missing bits in the or are already known to be set, match!
if ((NeededMask & KnownOne) == NeededMask)
return true;
-
+
// TODO: check to see if missing bits are just not demanded.
-
+
// Otherwise, this pattern doesn't match.
return false;
}
@@ -1101,7 +1137,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
unsigned i = 2, e = InOps.size();
if (InOps[e-1].getValueType() == MVT::Flag)
--e; // Don't process a flag operand if it is here.
-
+
while (i != e) {
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
if ((Flags & 7) != 4 /*MEM*/) {
@@ -1118,7 +1154,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
llvm_report_error("Could not match memory address. Inline asm"
" failure!");
}
-
+
// Add this to the output node.
EVT IntPtrTy = TLI.getPointerTy();
Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
@@ -1127,7 +1163,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
i += 2;
}
}
-
+
// Add the flag input back if present.
if (e != InOps.size())
Ops.push_back(InOps.back());
diff --git a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index e60a945..a2baee4 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -606,13 +606,13 @@ void TargetLowering::computeRegisterProperties() {
// Every integer value type larger than this largest register takes twice as
// many registers to represent as the previous ValueType.
for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
- EVT EVT = (MVT::SimpleValueType)ExpandedReg;
- if (!EVT.isInteger())
+ EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
+ if (!ExpandedVT.isInteger())
break;
NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
- ValueTypeActions.setTypeAction(EVT, Expand);
+ ValueTypeActions.setTypeAction(ExpandedVT, Expand);
}
// Inspect all of the ValueType's smaller than the largest integer
@@ -1922,6 +1922,43 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// materialize 0.0.
if (Cond == ISD::SETO || Cond == ISD::SETUO)
return DAG.getSetCC(dl, VT, N0, N0, Cond);
+
+ // If the condition is not legal, see if we can find an equivalent one
+ // which is legal.
+ if (!isCondCodeLegal(Cond, N0.getValueType())) {
+ // If the comparison was an awkward floating-point == or != and one of
+ // the comparison operands is infinity or negative infinity, convert the
+ // condition to a less-awkward <= or >=.
+ if (CFP->getValueAPF().isInfinity()) {
+ if (CFP->getValueAPF().isNegative()) {
+ if (Cond == ISD::SETOEQ &&
+ isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
+ return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
+ if (Cond == ISD::SETUEQ &&
+ isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
+ return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
+ if (Cond == ISD::SETUNE &&
+ isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
+ return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
+ if (Cond == ISD::SETONE &&
+ isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
+ return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
+ } else {
+ if (Cond == ISD::SETOEQ &&
+ isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
+ return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
+ if (Cond == ISD::SETUEQ &&
+ isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
+ return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
+ if (Cond == ISD::SETUNE &&
+ isCondCodeLegal(ISD::SETULT, N0.getValueType()))
+ return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
+ if (Cond == ISD::SETONE &&
+ isCondCodeLegal(ISD::SETULT, N0.getValueType()))
+ return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
+ }
+ }
+ }
}
if (N0 == N1) {
@@ -2346,7 +2383,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint,
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
I != E; ++I) {
- if (StringsEqualNoCase(RegName, RI->get(*I).AsmName))
+ if (StringsEqualNoCase(RegName, RI->getName(*I)))
return std::make_pair(*I, RC);
}
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/ShadowStackGC.cpp b/libclamav/c++/llvm/lib/CodeGen/ShadowStackGC.cpp
index 18c4936..541ab9a 100644
--- a/libclamav/c++/llvm/lib/CodeGen/ShadowStackGC.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/ShadowStackGC.cpp
@@ -207,12 +207,13 @@ Constant *ShadowStackGC::GetFrameMap(Function &F) {
};
Constant *DescriptorElts[] = {
- ConstantStruct::get(F.getContext(), BaseElts, 2),
+ ConstantStruct::get(F.getContext(), BaseElts, 2, false),
ConstantArray::get(ArrayType::get(VoidPtr, NumMeta),
Metadata.begin(), NumMeta)
};
- Constant *FrameMap = ConstantStruct::get(F.getContext(), DescriptorElts, 2);
+ Constant *FrameMap = ConstantStruct::get(F.getContext(), DescriptorElts, 2,
+ false);
std::string TypeName("gc_map.");
TypeName += utostr(NumMeta);
diff --git a/libclamav/c++/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp b/libclamav/c++/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
index 1a7fc11..ac70893 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -53,11 +53,6 @@ EnableJoining("join-liveintervals",
cl::init(true));
static cl::opt<bool>
-NewHeuristic("new-coalescer-heuristic",
- cl::desc("Use new coalescer heuristic"),
- cl::init(false), cl::Hidden);
-
-static cl::opt<bool>
DisableCrossClassJoin("disable-cross-class-join",
cl::desc("Avoid coalescing cross register class copies"),
cl::init(false), cl::Hidden);
@@ -67,7 +62,7 @@ PhysJoinTweak("tweak-phys-join-heuristics",
cl::desc("Tweak heuristics for joining phys reg with vr"),
cl::init(false), cl::Hidden);
-static RegisterPass<SimpleRegisterCoalescing>
+static RegisterPass<SimpleRegisterCoalescing>
X("simple-register-coalescing", "Simple Register Coalescing");
// Declare that we implement the RegisterCoalescer interface
@@ -108,22 +103,22 @@ void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
LiveInterval &IntB,
MachineInstr *CopyMI) {
- unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
+ MachineInstrIndex CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
// BValNo is a value number in B that is defined by a copy from A. 'B3' in
// the example above.
LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
assert(BLR != IntB.end() && "Live range not found!");
VNInfo *BValNo = BLR->valno;
-
+
// Get the location that B is defined at. Two options: either this value has
- // an unknown definition point or it is defined at CopyIdx. If unknown, we
+ // an unknown definition point or it is defined at CopyIdx. If unknown, we
// can't process it.
if (!BValNo->getCopy()) return false;
assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
-
+
// AValNo is the value number in A that defines the copy, A3 in the example.
- unsigned CopyUseIdx = li_->getUseIndex(CopyIdx);
+ MachineInstrIndex CopyUseIdx = li_->getUseIndex(CopyIdx);
LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
assert(ALR != IntA.end() && "Live range not found!");
VNInfo *AValNo = ALR->valno;
@@ -147,26 +142,28 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
// The coalescer has no idea there was a def in the middle of [174,230].
if (AValNo->hasRedefByEC())
return false;
-
- // If AValNo is defined as a copy from IntB, we can potentially process this.
+
+ // If AValNo is defined as a copy from IntB, we can potentially process this.
// Get the instruction that defines this value number.
unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
if (!SrcReg) return false; // Not defined by a copy.
-
+
// If the value number is not defined by a copy instruction, ignore it.
// If the source register comes from an interval other than IntB, we can't
// handle this.
if (SrcReg != IntB.reg) return false;
-
+
// Get the LiveRange in IntB that this value number starts with.
- LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
+ LiveInterval::iterator ValLR =
+ IntB.FindLiveRangeContaining(li_->getPrevSlot(AValNo->def));
assert(ValLR != IntB.end() && "Live range not found!");
-
+
// Make sure that the end of the live range is inside the same block as
// CopyMI.
- MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
- if (!ValLREndInst ||
+ MachineInstr *ValLREndInst =
+ li_->getInstructionFromIndex(li_->getPrevSlot(ValLR->end));
+ if (!ValLREndInst ||
ValLREndInst->getParent() != CopyMI->getParent()) return false;
// Okay, we now know that ValLR ends in the same block that the CopyMI
@@ -188,26 +185,26 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
return false;
}
}
-
+
DEBUG({
errs() << "\nExtending: ";
IntB.print(errs(), tri_);
});
-
- unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
+
+ MachineInstrIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
// We are about to delete CopyMI, so need to remove it as the 'instruction
// that defines this value #'. Update the the valnum with the new defining
// instruction #.
BValNo->def = FillerStart;
BValNo->setCopy(0);
-
+
// Okay, we can merge them. We need to insert a new liverange:
// [ValLR.end, BLR.begin) of either value number, then we merge the
// two value numbers.
IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
// If the IntB live range is assigned to a physical register, and if that
- // physreg has sub-registers, update their live intervals as well.
+ // physreg has sub-registers, update their live intervals as well.
if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
LiveInterval &SRLI = li_->getInterval(*SR);
@@ -233,7 +230,7 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
if (UIdx != -1) {
ValLREndInst->getOperand(UIdx).setIsKill(false);
- IntB.removeKill(ValLR->valno, FillerStart);
+ ValLR->valno->removeKill(FillerStart);
}
// If the copy instruction was killing the destination register before the
@@ -271,6 +268,16 @@ bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
return false;
}
+static void
+TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
+ for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
+ i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isImplicit())
+ NewMI->addOperand(MO);
+ }
+}
+
/// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
/// being the source and IntB being the dest, thus this defines a value number
/// in IntB. If the source value number (in IntA) is defined by a commutable
@@ -297,7 +304,8 @@ bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
LiveInterval &IntB,
MachineInstr *CopyMI) {
- unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
+ MachineInstrIndex CopyIdx =
+ li_->getDefIndex(li_->getInstructionIndex(CopyMI));
// FIXME: For now, only eliminate the copy by commuting its def when the
// source register is a virtual register. We want to guard against cases
@@ -311,15 +319,17 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
assert(BLR != IntB.end() && "Live range not found!");
VNInfo *BValNo = BLR->valno;
-
+
// Get the location that B is defined at. Two options: either this value has
- // an unknown definition point or it is defined at CopyIdx. If unknown, we
+ // an unknown definition point or it is defined at CopyIdx. If unknown, we
// can't process it.
if (!BValNo->getCopy()) return false;
assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
-
+
// AValNo is the value number in A that defines the copy, A3 in the example.
- LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
+ LiveInterval::iterator ALR =
+ IntA.FindLiveRangeContaining(li_->getPrevSlot(CopyIdx));
+
assert(ALR != IntA.end() && "Live range not found!");
VNInfo *AValNo = ALR->valno;
// If other defs can reach uses of this def, then it's not safe to perform
@@ -364,7 +374,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
UE = mri_->use_end(); UI != UE; ++UI) {
MachineInstr *UseMI = &*UI;
- unsigned UseIdx = li_->getInstructionIndex(UseMI);
+ MachineInstrIndex UseIdx = li_->getInstructionIndex(UseMI);
LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
if (ULR == IntA.end())
continue;
@@ -389,7 +399,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
bool BHasPHIKill = BValNo->hasPHIKill();
SmallVector<VNInfo*, 4> BDeadValNos;
VNInfo::KillSet BKills;
- std::map<unsigned, unsigned> BExtend;
+ std::map<MachineInstrIndex, MachineInstrIndex> BExtend;
// If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
// A = or A, B
@@ -416,7 +426,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
++UI;
if (JoinedCopies.count(UseMI))
continue;
- unsigned UseIdx = li_->getInstructionIndex(UseMI);
+ MachineInstrIndex UseIdx= li_->getUseIndex(li_->getInstructionIndex(UseMI));
LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
if (ULR == IntA.end() || ULR->valno != AValNo)
continue;
@@ -427,7 +437,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
if (Extended)
UseMO.setIsKill(false);
else
- BKills.push_back(VNInfo::KillInfo(false, li_->getUseIndex(UseIdx)+1));
+ BKills.push_back(li_->getNextSlot(UseIdx));
}
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
@@ -436,7 +446,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
// This copy will become a noop. If it's defining a new val#,
// remove that val# as well. However this live range is being
// extended to the end of the existing live range defined by the copy.
- unsigned DefIdx = li_->getDefIndex(UseIdx);
+ MachineInstrIndex DefIdx = li_->getDefIndex(UseIdx);
const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
BHasPHIKill |= DLR->valno->hasPHIKill();
assert(DLR->valno->def == DefIdx);
@@ -476,22 +486,22 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
ValNo->def = AValNo->def;
ValNo->setCopy(0);
for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
- unsigned Kill = ValNo->kills[j].killIdx;
- if (Kill != BLR->end)
- BKills.push_back(VNInfo::KillInfo(ValNo->kills[j].isPHIKill, Kill));
+ if (ValNo->kills[j] != BLR->end)
+ BKills.push_back(ValNo->kills[j]);
}
ValNo->kills.clear();
for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
AI != AE; ++AI) {
if (AI->valno != AValNo) continue;
- unsigned End = AI->end;
- std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
+ MachineInstrIndex End = AI->end;
+ std::map<MachineInstrIndex, MachineInstrIndex>::iterator
+ EI = BExtend.find(End);
if (EI != BExtend.end())
End = EI->second;
IntB.addRange(LiveRange(AI->start, End, ValNo));
// If the IntB live range is assigned to a physical register, and if that
- // physreg has sub-registers, update their live intervals as well.
+ // physreg has sub-registers, update their live intervals as well.
if (BHasSubRegs) {
for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
LiveInterval &SRLI = li_->getInterval(*SR);
@@ -538,7 +548,8 @@ static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
/// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
/// from a physical register live interval as well as from the live intervals
/// of its sub-registers.
-static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
+static void removeRange(LiveInterval &li,
+ MachineInstrIndex Start, MachineInstrIndex End,
LiveIntervals *li_, const TargetRegisterInfo *tri_) {
li.removeRange(Start, End, true);
if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
@@ -546,14 +557,15 @@ static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
if (!li_->hasInterval(*SR))
continue;
LiveInterval &sli = li_->getInterval(*SR);
- unsigned RemoveEnd = Start;
+ MachineInstrIndex RemoveStart = Start;
+ MachineInstrIndex RemoveEnd = Start;
while (RemoveEnd != End) {
- LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
+ LiveInterval::iterator LR = sli.FindLiveRangeContaining(RemoveStart);
if (LR == sli.end())
break;
RemoveEnd = (LR->end < End) ? LR->end : End;
- sli.removeRange(Start, RemoveEnd, true);
- Start = RemoveEnd;
+ sli.removeRange(RemoveStart, RemoveEnd, true);
+ RemoveStart = RemoveEnd;
}
}
}
@@ -563,14 +575,14 @@ static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
/// as the copy instruction, trim the live interval to the last use and return
/// true.
bool
-SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx,
+SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(MachineInstrIndex CopyIdx,
MachineBasicBlock *CopyMBB,
LiveInterval &li,
const LiveRange *LR) {
- unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
- unsigned LastUseIdx;
- MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
- LastUseIdx);
+ MachineInstrIndex MBBStart = li_->getMBBStartIdx(CopyMBB);
+ MachineInstrIndex LastUseIdx;
+ MachineOperand *LastUse =
+ lastRegisterUse(LR->start, li_->getPrevSlot(CopyIdx), li.reg, LastUseIdx);
if (LastUse) {
MachineInstr *LastUseMI = LastUse->getParent();
if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
@@ -590,7 +602,7 @@ SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx,
// of last use.
LastUse->setIsKill();
removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
- li.addKill(LR->valno, LastUseIdx+1, false);
+ LR->valno->addKill(li_->getNextSlot(LastUseIdx));
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
DstReg == li.reg) {
@@ -603,7 +615,7 @@ SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx,
// Is it livein?
if (LR->start <= MBBStart && LR->end > MBBStart) {
- if (LR->start == 0) {
+ if (LR->start == MachineInstrIndex()) {
assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
// Live-in to the function but dead. Remove it from entry live-in set.
mf_->begin()->removeLiveIn(li.reg);
@@ -620,7 +632,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
unsigned DstReg,
unsigned DstSubIdx,
MachineInstr *CopyMI) {
- unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
+ MachineInstrIndex CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
assert(SrcLR != SrcInt.end() && "Live range not found!");
VNInfo *ValNo = SrcLR->valno;
@@ -654,7 +666,23 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
return false;
}
- unsigned DefIdx = li_->getDefIndex(CopyIdx);
+ // If destination register has a sub-register index on it, make sure it mtches
+ // the instruction register class.
+ if (DstSubIdx) {
+ const TargetInstrDesc &TID = DefMI->getDesc();
+ if (TID.getNumDefs() != 1)
+ return false;
+ const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
+ const TargetRegisterClass *DstSubRC =
+ DstRC->getSubRegisterRegClass(DstSubIdx);
+ const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
+ if (DefRC == DstRC)
+ DstSubIdx = 0;
+ else if (DefRC != DstSubRC)
+ return false;
+ }
+
+ MachineInstrIndex DefIdx = li_->getDefIndex(CopyIdx);
const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
DLR->valno->setCopy(0);
// Don't forget to update sub-register intervals.
@@ -687,7 +715,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
// should mark it dead:
if (DefMI->getParent() == MBB) {
DefMI->addRegisterDead(SrcInt.reg, tri_);
- SrcLR->end = SrcLR->start + 1;
+ SrcLR->end = li_->getNextSlot(SrcLR->start);
}
}
@@ -706,6 +734,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
}
}
+ TransferImplicitOps(CopyMI, NewMI);
li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
CopyMI->eraseFromParent();
ReMatCopies.insert(CopyMI);
@@ -714,28 +743,6 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
return true;
}
-/// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
-///
-bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
- unsigned DstReg) const {
- MachineBasicBlock *MBB = CopyMI->getParent();
- const MachineLoop *L = loopInfo->getLoopFor(MBB);
- if (!L)
- return false;
- if (MBB != L->getLoopLatch())
- return false;
-
- LiveInterval &LI = li_->getInterval(DstReg);
- unsigned DefIdx = li_->getInstructionIndex(CopyMI);
- LiveInterval::const_iterator DstLR =
- LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
- if (DstLR == LI.end())
- return false;
- if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0].isPHIKill)
- return true;
- return false;
-}
-
/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
/// update the subregister number if it is not zero. If DstReg is a
/// physical register and the existing subregister number of the def / use
@@ -807,7 +814,8 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
(TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
allocatableRegs_[CopyDstReg])) {
LiveInterval &LI = li_->getInterval(CopyDstReg);
- unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
+ MachineInstrIndex DefIdx =
+ li_->getDefIndex(li_->getInstructionIndex(UseMI));
if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
if (DLR->valno->def == DefIdx)
DLR->valno->setCopy(UseMI);
@@ -826,23 +834,24 @@ void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
if (!UseMO.isKill())
continue;
MachineInstr *UseMI = UseMO.getParent();
- unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
+ MachineInstrIndex UseIdx =
+ li_->getUseIndex(li_->getInstructionIndex(UseMI));
const LiveRange *LR = LI.getLiveRangeContaining(UseIdx);
- if (!LR || !LI.isKill(LR->valno, UseIdx+1)) {
- if (LR->valno->def != UseIdx+1) {
- // Interesting problem. After coalescing reg1027's def and kill are both
- // at the same point: %reg1027,0.000000e+00 = [56,814:0) 0 at 70-(814)
- //
- // bb5:
- // 60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
- // 68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
- // 76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
- // 84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
- // 96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>
- //
- // Do not remove the kill marker on t2LDRi12.
- UseMO.setIsKill(false);
- }
+ if (!LR ||
+ (!LR->valno->isKill(li_->getNextSlot(UseIdx)) &&
+ LR->valno->def != li_->getNextSlot(UseIdx))) {
+ // Interesting problem. After coalescing reg1027's def and kill are both
+ // at the same point: %reg1027,0.000000e+00 = [56,814:0) 0 at 70-(814)
+ //
+ // bb5:
+ // 60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
+ // 68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
+ // 76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
+ // 84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
+ // 96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>
+ //
+ // Do not remove the kill marker on t2LDRi12.
+ UseMO.setIsKill(false);
}
}
}
@@ -871,16 +880,16 @@ static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
/// Return true if live interval is removed.
bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
MachineInstr *CopyMI) {
- unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
+ MachineInstrIndex CopyIdx = li_->getInstructionIndex(CopyMI);
LiveInterval::iterator MLR =
li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
if (MLR == li.end())
return false; // Already removed by ShortenDeadCopySrcLiveRange.
- unsigned RemoveStart = MLR->start;
- unsigned RemoveEnd = MLR->end;
- unsigned DefIdx = li_->getDefIndex(CopyIdx);
+ MachineInstrIndex RemoveStart = MLR->start;
+ MachineInstrIndex RemoveEnd = MLR->end;
+ MachineInstrIndex DefIdx = li_->getDefIndex(CopyIdx);
// Remove the liverange that's defined by this.
- if (RemoveStart == DefIdx && RemoveEnd == DefIdx+1) {
+ if (RemoveStart == DefIdx && RemoveEnd == li_->getNextSlot(DefIdx)) {
removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
return removeIntervalIfEmpty(li, li_, tri_);
}
@@ -891,7 +900,7 @@ bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
/// the val# it defines. If the live interval becomes empty, remove it as well.
bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
MachineInstr *DefMI) {
- unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
+ MachineInstrIndex DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
if (DefIdx != MLR->valno->def)
return false;
@@ -902,7 +911,7 @@ bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
/// PropagateDeadness - Propagate the dead marker to the instruction which
/// defines the val#.
static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
- unsigned &LRStart, LiveIntervals *li_,
+ MachineInstrIndex &LRStart, LiveIntervals *li_,
const TargetRegisterInfo* tri_) {
MachineInstr *DefMI =
li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
@@ -913,7 +922,7 @@ static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
else
DefMI->addOperand(MachineOperand::CreateReg(li.reg,
true, true, false, true));
- ++LRStart;
+ LRStart = li_->getNextSlot(LRStart);
}
}
@@ -924,8 +933,8 @@ static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
bool
SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
MachineInstr *CopyMI) {
- unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
- if (CopyIdx == 0) {
+ MachineInstrIndex CopyIdx = li_->getInstructionIndex(CopyMI);
+ if (CopyIdx == MachineInstrIndex()) {
// FIXME: special case: function live in. It can be a general case if the
// first instruction index starts at > 0 value.
assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
@@ -937,13 +946,14 @@ SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
return removeIntervalIfEmpty(li, li_, tri_);
}
- LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
+ LiveInterval::iterator LR =
+ li.FindLiveRangeContaining(li_->getPrevSlot(CopyIdx));
if (LR == li.end())
// Livein but defined by a phi.
return false;
- unsigned RemoveStart = LR->start;
- unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
+ MachineInstrIndex RemoveStart = LR->start;
+ MachineInstrIndex RemoveEnd = li_->getNextSlot(li_->getDefIndex(CopyIdx));
if (LR->end > RemoveEnd)
// More uses past this copy? Nothing to do.
return false;
@@ -963,7 +973,7 @@ SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
// If the live range starts in another mbb and the copy mbb is not a fall
// through mbb, then we can only cut the range from the beginning of the
// copy mbb.
- RemoveStart = li_->getMBBStartIdx(CopyMBB) + 1;
+ RemoveStart = li_->getNextSlot(li_->getMBBStartIdx(CopyMBB));
if (LR->valno->def == RemoveStart) {
// If the def MI defines the val# and this copy is the only kill of the
@@ -971,8 +981,8 @@ SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
++numDeadValNo;
- if (li.isKill(LR->valno, RemoveEnd))
- li.removeKill(LR->valno, RemoveEnd);
+ if (LR->valno->isKill(RemoveEnd))
+ LR->valno->removeKill(RemoveEnd);
}
removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
@@ -1019,13 +1029,14 @@ SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
// If the virtual register live interval extends into a loop, turn down
// aggressiveness.
- unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
+ MachineInstrIndex CopyIdx =
+ li_->getDefIndex(li_->getInstructionIndex(CopyMI));
const MachineLoop *L = loopInfo->getLoopFor(CopyMBB);
if (!L) {
// Let's see if the virtual register live interval extends into the loop.
LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx);
assert(DLR != DstInt.end() && "Live range not found!");
- DLR = DstInt.FindLiveRangeContaining(DLR->end+1);
+ DLR = DstInt.FindLiveRangeContaining(li_->getNextSlot(DLR->end));
if (DLR != DstInt.end()) {
CopyMBB = li_->getMBBFromIndex(DLR->start);
L = loopInfo->getLoopFor(CopyMBB);
@@ -1035,7 +1046,7 @@ SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
if (!L || Length <= Threshold)
return true;
- unsigned UseIdx = li_->getUseIndex(CopyIdx);
+ MachineInstrIndex UseIdx = li_->getUseIndex(CopyIdx);
LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
if (loopInfo->getLoopFor(SMBB) != L) {
@@ -1048,7 +1059,7 @@ SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
if (SuccMBB == CopyMBB)
continue;
if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB),
- li_->getMBBEndIdx(SuccMBB)+1))
+ li_->getNextSlot(li_->getMBBEndIdx(SuccMBB))))
return false;
}
}
@@ -1079,11 +1090,12 @@ SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
// If the virtual register live interval is defined or cross a loop, turn
// down aggressiveness.
- unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
- unsigned UseIdx = li_->getUseIndex(CopyIdx);
+ MachineInstrIndex CopyIdx =
+ li_->getDefIndex(li_->getInstructionIndex(CopyMI));
+ MachineInstrIndex UseIdx = li_->getUseIndex(CopyIdx);
LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
assert(SLR != SrcInt.end() && "Live range not found!");
- SLR = SrcInt.FindLiveRangeContaining(SLR->start-1);
+ SLR = SrcInt.FindLiveRangeContaining(li_->getPrevSlot(SLR->start));
if (SLR == SrcInt.end())
return true;
MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
@@ -1103,7 +1115,7 @@ SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
if (PredMBB == SMBB)
continue;
if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB),
- li_->getMBBEndIdx(PredMBB)+1))
+ li_->getNextSlot(li_->getMBBEndIdx(PredMBB))))
return false;
}
}
@@ -1295,8 +1307,8 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
// r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
// coalesced to a larger register so the subreg indices cancel out.
- DEBUG(errs() << "\tSource of insert_subreg is already coalesced "
- << "to another register.\n");
+ DEBUG(errs() << "\tSource of insert_subreg or subreg_to_reg is already "
+ "coalesced to another register.\n");
return false; // Not coalescable.
}
} else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
@@ -1308,7 +1320,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
DEBUG(errs() << "\tCopy already coalesced.\n");
return false; // Not coalescable.
}
-
+
bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
@@ -1317,7 +1329,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
DEBUG(errs() << "\tCan not coalesce physregs.\n");
return false; // Not coalescable.
}
-
+
// We only join virtual registers with allocatable physical registers.
if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
DEBUG(errs() << "\tSrc reg is unallocatable physreg.\n");
@@ -1542,7 +1554,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
return false;
if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
return false;
-
+
LiveInterval &SrcInt = li_->getInterval(SrcReg);
LiveInterval &DstInt = li_->getInterval(DstReg);
assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
@@ -1604,9 +1616,6 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
- if (TheCopy.isBackEdge)
- Threshold *= 2; // Favors back edge copies.
-
unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
float Ratio = 1.0 / Threshold;
if (Length > Threshold &&
@@ -1645,7 +1654,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
return true;
-
+
// If we can eliminate the copy without merging the live ranges, do so now.
if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
(AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
@@ -1653,7 +1662,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
JoinedCopies.insert(CopyMI);
return true;
}
-
+
// Otherwise, we are unable to join the intervals.
DEBUG(errs() << "Interference!\n");
Again = true; // May be possible to coalesce later.
@@ -1668,7 +1677,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
}
assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
"LiveInterval::join didn't work right!");
-
+
// If we're about to merge live ranges into a physical register live interval,
// we have to update any aliased register's live ranges to indicate that they
// have clobbered values for this range.
@@ -1689,7 +1698,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
RealInt.addKills(NewValNo, ValNo->kills);
RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
}
- RealInt.weight += SavedLI->weight;
+ RealInt.weight += SavedLI->weight;
DstReg = RealDstReg ? RealDstReg : RealSrcReg;
}
@@ -1723,27 +1732,6 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
if (NewRC)
mri_->setRegClass(DstReg, NewRC);
- if (NewHeuristic) {
- // Add all copies that define val# in the source interval into the queue.
- for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
- e = ResSrcInt->vni_end(); i != e; ++i) {
- const VNInfo *vni = *i;
- // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
- if (!vni->def || vni->isUnused() || vni->isPHIDef() || !vni->isDefAccurate())
- continue;
- MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
- unsigned NewSrcReg, NewDstReg, NewSrcSubIdx, NewDstSubIdx;
- if (CopyMI &&
- JoinedCopies.count(CopyMI) == 0 &&
- tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg,
- NewSrcSubIdx, NewDstSubIdx)) {
- unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
- JoinQueue->push(CopyRec(CopyMI, LoopDepth,
- isBackEdgeCopy(CopyMI, DstReg)));
- }
- }
- }
-
// Remember to delete the copy instruction.
JoinedCopies.insert(CopyMI);
@@ -1829,7 +1817,7 @@ static unsigned ComputeUltimateVN(VNInfo *VNI,
// been computed, return it.
if (OtherValNoAssignments[OtherValNo->id] >= 0)
return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
-
+
// Mark this value number as currently being computed, then ask what the
// ultimate value # of the other value is.
ThisValNoAssignments[VN] = -2;
@@ -1879,16 +1867,16 @@ bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
/// joins them and returns true.
bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
assert(RHS.containsOneValue());
-
+
// Some number (potentially more than one) value numbers in the current
// interval may be defined as copies from the RHS. Scan the overlapping
// portions of the LHS and RHS, keeping track of this and looking for
// overlapping live ranges that are NOT defined as copies. If these exist, we
// cannot coalesce.
-
+
LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
-
+
if (LHSIt->start < RHSIt->start) {
LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
if (LHSIt != LHS.begin()) --LHSIt;
@@ -1896,9 +1884,9 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
if (RHSIt != RHS.begin()) --RHSIt;
}
-
+
SmallVector<VNInfo*, 8> EliminatedLHSVals;
-
+
while (1) {
// Determine if these live intervals overlap.
bool Overlaps = false;
@@ -1906,7 +1894,7 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
Overlaps = LHSIt->end > RHSIt->start;
else
Overlaps = RHSIt->end > LHSIt->start;
-
+
// If the live intervals overlap, there are two interesting cases: if the
// LHS interval is defined by a copy from the RHS, it's ok and we record
// that the LHS value # is the same as the RHS. If it's not, then we cannot
@@ -1924,7 +1912,7 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
// vr1025 = copy vr1024
// ..
// BB2:
- // vr1024 = op
+ // vr1024 = op
// = vr1025
// Even though vr1025 is copied from vr1024, it's not safe to
// coalesce them since the live range of vr1025 intersects the
@@ -1933,12 +1921,12 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
return false;
EliminatedLHSVals.push_back(LHSIt->valno);
}
-
+
// We know this entire LHS live range is okay, so skip it now.
if (++LHSIt == LHSEnd) break;
continue;
}
-
+
if (LHSIt->end < RHSIt->end) {
if (++LHSIt == LHSEnd) break;
} else {
@@ -1962,7 +1950,7 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
// vr1025 = copy vr1024
// ..
// BB2:
- // vr1024 = op
+ // vr1024 = op
// = vr1025
// Even though vr1025 is copied from vr1024, it's not safe to
// coalesced them since live range of vr1025 intersects the
@@ -1976,11 +1964,11 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
}
}
}
-
+
if (++RHSIt == RHSEnd) break;
}
}
-
+
// If we got here, we know that the coalescing will be successful and that
// the value numbers in EliminatedLHSVals will all be merged together. Since
// the most common case is that EliminatedLHSVals has a single number, we
@@ -2012,14 +2000,14 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
} else {
LHSValNo = EliminatedLHSVals[0];
}
-
+
// Okay, now that there is a single LHS value number that we're merging the
// RHS into, update the value number info for the LHS to indicate that the
// value number is defined where the RHS value number was.
const VNInfo *VNI = RHS.getValNumInfo(0);
LHSValNo->def = VNI->def;
LHSValNo->setCopy(VNI->getCopy());
-
+
// Okay, the final step is to loop over the RHS live intervals, adding them to
// the LHS.
if (VNI->hasPHIKill())
@@ -2030,7 +2018,7 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
LHS.ComputeJoinedWeight(RHS);
// Update regalloc hint if both are virtual registers.
- if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
+ if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
@@ -2117,13 +2105,13 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
}
}
}
-
+
// Compute ultimate value numbers for the LHS and RHS values.
if (RHS.containsOneValue()) {
// Copies from a liveinterval with a single value are simple to handle and
// very common, handle the special case here. This is important, because
// often RHS is small and LHS is large (e.g. a physreg).
-
+
// Find out if the RHS is defined as a copy from some value in the LHS.
int RHSVal0DefinedFromLHS = -1;
int RHSValID = -1;
@@ -2141,15 +2129,16 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
}
} else {
// It was defined as a copy from the LHS, find out what value # it is.
- RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
+ RHSValNoInfo =
+ LHS.getLiveRangeContaining(li_->getPrevSlot(RHSValNoInfo0->def))->valno;
RHSValID = RHSValNoInfo->id;
RHSVal0DefinedFromLHS = RHSValID;
}
-
+
LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
NewVNInfo.resize(LHS.getNumValNums(), NULL);
-
+
// Okay, *all* of the values in LHS that are defined as a copy from RHS
// should now get updated.
for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
@@ -2181,7 +2170,7 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
LHSValNoAssignments[VN] = VN;
}
}
-
+
assert(RHSValID != -1 && "Didn't find value #?");
RHSValNoAssignments[0] = RHSValID;
if (RHSVal0DefinedFromLHS != -1) {
@@ -2197,16 +2186,17 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
VNInfo *VNI = *i;
if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
continue;
-
+
// DstReg is known to be a register in the LHS interval. If the src is
// from the RHS interval, we can use its value #.
if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
continue;
-
+
// Figure out the value # from the RHS.
- LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
+ LHSValsDefinedFromRHS[VNI]=
+ RHS.getLiveRangeContaining(li_->getPrevSlot(VNI->def))->valno;
}
-
+
// Loop over the value numbers of the RHS, seeing if any are defined from
// the LHS.
for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
@@ -2214,25 +2204,26 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
VNInfo *VNI = *i;
if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
continue;
-
+
// DstReg is known to be a register in the RHS interval. If the src is
// from the LHS interval, we can use its value #.
if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
continue;
-
+
// Figure out the value # from the LHS.
- RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
+ RHSValsDefinedFromLHS[VNI]=
+ LHS.getLiveRangeContaining(li_->getPrevSlot(VNI->def))->valno;
}
-
+
LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
-
+
for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
i != e; ++i) {
VNInfo *VNI = *i;
unsigned VN = VNI->id;
- if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
+ if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
continue;
ComputeUltimateVN(VNI, NewVNInfo,
LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
@@ -2250,20 +2241,20 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
RHSValNoAssignments[VN] = NewVNInfo.size()-1;
continue;
}
-
+
ComputeUltimateVN(VNI, NewVNInfo,
RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
RHSValNoAssignments, LHSValNoAssignments);
}
}
-
+
// Armed with the mappings of LHS/RHS values to ultimate values, walk the
// interval lists to see if these intervals are coalescable.
LiveInterval::const_iterator I = LHS.begin();
LiveInterval::const_iterator IE = LHS.end();
LiveInterval::const_iterator J = RHS.begin();
LiveInterval::const_iterator JE = RHS.end();
-
+
// Skip ahead until the first place of potential sharing.
if (I->start < J->start) {
I = std::upper_bound(I, IE, J->start);
@@ -2272,7 +2263,7 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
J = std::upper_bound(J, JE, I->start);
if (J != RHS.begin()) --J;
}
-
+
while (1) {
// Determine if these two live ranges overlap.
bool Overlaps;
@@ -2290,7 +2281,7 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
RHSValNoAssignments[J->valno->id])
return false;
}
-
+
if (I->end < J->end) {
++I;
if (I == IE) break;
@@ -2305,7 +2296,7 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
VNInfo *VNI = I->first;
unsigned LHSValID = LHSValNoAssignments[VNI->id];
- LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
+ NewVNInfo[LHSValID]->removeKill(VNI->def);
if (VNI->hasPHIKill())
NewVNInfo[LHSValID]->setHasPHIKill(true);
RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
@@ -2316,7 +2307,7 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
VNInfo *VNI = I->first;
unsigned RHSValID = RHSValNoAssignments[VNI->id];
- LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
+ NewVNInfo[RHSValID]->removeKill(VNI->def);
if (VNI->hasPHIKill())
NewVNInfo[RHSValID]->setHasPHIKill(true);
LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
@@ -2351,25 +2342,6 @@ namespace {
};
}
-/// getRepIntervalSize - Returns the size of the interval that represents the
-/// specified register.
-template<class SF>
-unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
- return Rc->getRepIntervalSize(Reg);
-}
-
-/// CopyRecSort::operator - Join priority queue sorting function.
-///
-bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
- // Inner loops first.
- if (left.LoopDepth > right.LoopDepth)
- return false;
- else if (left.LoopDepth == right.LoopDepth)
- if (left.isBackEdge && !right.isBackEdge)
- return false;
- return true;
-}
-
void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
std::vector<CopyRec> &TryAgain) {
DEBUG(errs() << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
@@ -2377,11 +2349,10 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
std::vector<CopyRec> VirtCopies;
std::vector<CopyRec> PhysCopies;
std::vector<CopyRec> ImpDefCopies;
- unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
MII != E;) {
MachineInstr *Inst = MII++;
-
+
// If this isn't a copy nor a extract_subreg, we can't join intervals.
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
@@ -2396,21 +2367,14 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
- if (NewHeuristic) {
- JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
- } else {
- if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
- ImpDefCopies.push_back(CopyRec(Inst, 0, false));
- else if (SrcIsPhys || DstIsPhys)
- PhysCopies.push_back(CopyRec(Inst, 0, false));
- else
- VirtCopies.push_back(CopyRec(Inst, 0, false));
- }
+ if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
+ ImpDefCopies.push_back(CopyRec(Inst, 0));
+ else if (SrcIsPhys || DstIsPhys)
+ PhysCopies.push_back(CopyRec(Inst, 0));
+ else
+ VirtCopies.push_back(CopyRec(Inst, 0));
}
- if (NewHeuristic)
- return;
-
// Try coalescing implicit copies first, followed by copies to / from
// physical registers, then finally copies from virtual registers to
// virtual registers.
@@ -2440,9 +2404,6 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
void SimpleRegisterCoalescing::joinIntervals() {
DEBUG(errs() << "********** JOINING INTERVALS ***********\n");
- if (NewHeuristic)
- JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
-
std::vector<CopyRec> TryAgainList;
if (loopInfo->empty()) {
// If there are no loops in the function, join intervals in function order.
@@ -2469,52 +2430,26 @@ void SimpleRegisterCoalescing::joinIntervals() {
for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
}
-
+
// Joining intervals can allow other intervals to be joined. Iteratively join
// until we make no progress.
- if (NewHeuristic) {
- SmallVector<CopyRec, 16> TryAgain;
- bool ProgressMade = true;
- while (ProgressMade) {
- ProgressMade = false;
- while (!JoinQueue->empty()) {
- CopyRec R = JoinQueue->pop();
- bool Again = false;
- bool Success = JoinCopy(R, Again);
- if (Success)
- ProgressMade = true;
- else if (Again)
- TryAgain.push_back(R);
- }
+ bool ProgressMade = true;
+ while (ProgressMade) {
+ ProgressMade = false;
- if (ProgressMade) {
- while (!TryAgain.empty()) {
- JoinQueue->push(TryAgain.back());
- TryAgain.pop_back();
- }
- }
- }
- } else {
- bool ProgressMade = true;
- while (ProgressMade) {
- ProgressMade = false;
-
- for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
- CopyRec &TheCopy = TryAgainList[i];
- if (TheCopy.MI) {
- bool Again = false;
- bool Success = JoinCopy(TheCopy, Again);
- if (Success || !Again) {
- TheCopy.MI = 0; // Mark this one as done.
- ProgressMade = true;
- }
- }
+ for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
+ CopyRec &TheCopy = TryAgainList[i];
+ if (!TheCopy.MI)
+ continue;
+
+ bool Again = false;
+ bool Success = JoinCopy(TheCopy, Again);
+ if (Success || !Again) {
+ TheCopy.MI = 0; // Mark this one as done.
+ ProgressMade = true;
}
}
}
-
- if (NewHeuristic)
- delete JoinQueue;
}
/// Return true if the two specified registers belong to different register
@@ -2541,9 +2476,11 @@ SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
/// lastRegisterUse - Returns the last use of the specific register between
/// cycles Start and End or NULL if there are no uses.
MachineOperand *
-SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
- unsigned Reg, unsigned &UseIdx) const{
- UseIdx = 0;
+SimpleRegisterCoalescing::lastRegisterUse(MachineInstrIndex Start,
+ MachineInstrIndex End,
+ unsigned Reg,
+ MachineInstrIndex &UseIdx) const{
+ UseIdx = MachineInstrIndex();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
MachineOperand *LastUse = NULL;
for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
@@ -2555,7 +2492,7 @@ SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
SrcReg == DstReg)
// Ignore identity copies.
continue;
- unsigned Idx = li_->getInstructionIndex(UseMI);
+ MachineInstrIndex Idx = li_->getInstructionIndex(UseMI);
if (Idx >= Start && Idx < End && Idx >= UseIdx) {
LastUse = &Use;
UseIdx = li_->getUseIndex(Idx);
@@ -2564,13 +2501,13 @@ SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
return LastUse;
}
- int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
- int s = Start;
+ MachineInstrIndex s = Start;
+ MachineInstrIndex e = li_->getBaseIndex(li_->getPrevSlot(End));
while (e >= s) {
// Skip deleted instructions
MachineInstr *MI = li_->getInstructionFromIndex(e);
- while ((e - InstrSlots::NUM) >= s && !MI) {
- e -= InstrSlots::NUM;
+ while (e != MachineInstrIndex() && li_->getPrevIndex(e) >= s && !MI) {
+ e = li_->getPrevIndex(e);
MI = li_->getInstructionFromIndex(e);
}
if (e < s || MI == NULL)
@@ -2589,7 +2526,7 @@ SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
}
}
- e -= InstrSlots::NUM;
+ e = li_->getPrevIndex(e);
}
return NULL;
@@ -2609,14 +2546,108 @@ void SimpleRegisterCoalescing::releaseMemory() {
ReMatDefs.clear();
}
-static bool isZeroLengthInterval(LiveInterval *li) {
+/// Returns true if the given live interval is zero length.
+static bool isZeroLengthInterval(LiveInterval *li, LiveIntervals *li_) {
for (LiveInterval::Ranges::const_iterator
i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
- if (i->end - i->start > LiveInterval::InstrSlots::NUM)
+ if (li_->getPrevIndex(i->end) > i->start)
return false;
return true;
}
+void SimpleRegisterCoalescing::CalculateSpillWeights() {
+ SmallSet<unsigned, 4> Processed;
+ for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
+ mbbi != mbbe; ++mbbi) {
+ MachineBasicBlock* MBB = mbbi;
+ MachineInstrIndex MBBEnd = li_->getMBBEndIdx(MBB);
+ MachineLoop* loop = loopInfo->getLoopFor(MBB);
+ unsigned loopDepth = loop ? loop->getLoopDepth() : 0;
+ bool isExit = loop ? loop->isLoopExit(MBB) : false;
+
+ for (MachineBasicBlock::iterator mii = MBB->begin(), mie = MBB->end();
+ mii != mie; ++mii) {
+ MachineInstr *MI = mii;
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &mopi = MI->getOperand(i);
+ if (!mopi.isReg() || mopi.getReg() == 0)
+ continue;
+ unsigned Reg = mopi.getReg();
+ if (!TargetRegisterInfo::isVirtualRegister(mopi.getReg()))
+ continue;
+ // Multiple uses of reg by the same instruction. It should not
+ // contribute to spill weight again.
+ if (!Processed.insert(Reg))
+ continue;
+
+ bool HasDef = mopi.isDef();
+ bool HasUse = !HasDef;
+ for (unsigned j = i+1; j != e; ++j) {
+ const MachineOperand &mopj = MI->getOperand(j);
+ if (!mopj.isReg() || mopj.getReg() != Reg)
+ continue;
+ HasDef |= mopj.isDef();
+ HasUse |= mopj.isUse();
+ if (HasDef && HasUse)
+ break;
+ }
+
+ LiveInterval &RegInt = li_->getInterval(Reg);
+ float Weight = li_->getSpillWeight(HasDef, HasUse, loopDepth);
+ if (HasDef && isExit) {
+ // Looks like this is a loop count variable update.
+ MachineInstrIndex DefIdx =
+ li_->getDefIndex(li_->getInstructionIndex(MI));
+ const LiveRange *DLR =
+ li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
+ if (DLR->end > MBBEnd)
+ Weight *= 3.0F;
+ }
+ RegInt.weight += Weight;
+ }
+ Processed.clear();
+ }
+ }
+
+ for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
+ LiveInterval &LI = *I->second;
+ if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
+ // If the live interval length is essentially zero, i.e. in every live
+ // range the use follows def immediately, it doesn't make sense to spill
+ // it and hope it will be easier to allocate for this li.
+ if (isZeroLengthInterval(&LI, li_)) {
+ LI.weight = HUGE_VALF;
+ continue;
+ }
+
+ bool isLoad = false;
+ SmallVector<LiveInterval*, 4> SpillIs;
+ if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
+ // If all of the definitions of the interval are re-materializable,
+ // it is a preferred candidate for spilling. If non of the defs are
+ // loads, then it's potentially very cheap to re-materialize.
+ // FIXME: this gets much more complicated once we support non-trivial
+ // re-materialization.
+ if (isLoad)
+ LI.weight *= 0.9F;
+ else
+ LI.weight *= 0.5F;
+ }
+
+ // Slightly prefer live interval that has been assigned a preferred reg.
+ std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(LI.reg);
+ if (Hint.first || Hint.second)
+ LI.weight *= 1.01F;
+
+ // Divide the weight of the interval by its size. This encourages
+ // spilling of intervals that are large and have few uses, and
+ // discourages spilling of small intervals with many uses.
+ LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
+ }
+ }
+}
+
bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
mf_ = &fn;
@@ -2655,29 +2686,40 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
mbbi != mbbe; ++mbbi) {
MachineBasicBlock* mbb = mbbi;
- unsigned loopDepth = loopInfo->getLoopDepth(mbb);
-
for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
mii != mie; ) {
MachineInstr *MI = mii;
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (JoinedCopies.count(MI)) {
// Delete all coalesced copies.
+ bool DoDelete = true;
if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
"Unrecognized copy instruction");
DstReg = MI->getOperand(0).getReg();
+ if (TargetRegisterInfo::isPhysicalRegister(DstReg))
+ // Do not delete extract_subreg, insert_subreg of physical
+ // registers unless the definition is dead. e.g.
+ // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
+ // or else the scavenger may complain. LowerSubregs will
+ // change this to an IMPLICIT_DEF later.
+ DoDelete = false;
}
if (MI->registerDefIsDead(DstReg)) {
LiveInterval &li = li_->getInterval(DstReg);
if (!ShortenDeadCopySrcLiveRange(li, MI))
ShortenDeadCopyLiveRange(li, MI);
+ DoDelete = true;
+ }
+ if (!DoDelete)
+ mii = next(mii);
+ else {
+ li_->RemoveMachineInstrFromMaps(MI);
+ mii = mbbi->erase(mii);
+ ++numPeep;
}
- li_->RemoveMachineInstrFromMaps(MI);
- mii = mbbi->erase(mii);
- ++numPeep;
continue;
}
@@ -2730,62 +2772,12 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
mii = mbbi->erase(mii);
++numPeep;
} else {
- SmallSet<unsigned, 4> UniqueUses;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &mop = MI->getOperand(i);
- if (mop.isReg() && mop.getReg() &&
- TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
- unsigned reg = mop.getReg();
- // Multiple uses of reg by the same instruction. It should not
- // contribute to spill weight again.
- if (UniqueUses.count(reg) != 0)
- continue;
- LiveInterval &RegInt = li_->getInterval(reg);
- RegInt.weight +=
- li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
- UniqueUses.insert(reg);
- }
- }
++mii;
}
}
}
- for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
- LiveInterval &LI = *I->second;
- if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
- // If the live interval length is essentially zero, i.e. in every live
- // range the use follows def immediately, it doesn't make sense to spill
- // it and hope it will be easier to allocate for this li.
- if (isZeroLengthInterval(&LI))
- LI.weight = HUGE_VALF;
- else {
- bool isLoad = false;
- SmallVector<LiveInterval*, 4> SpillIs;
- if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
- // If all of the definitions of the interval are re-materializable,
- // it is a preferred candidate for spilling. If non of the defs are
- // loads, then it's potentially very cheap to re-materialize.
- // FIXME: this gets much more complicated once we support non-trivial
- // re-materialization.
- if (isLoad)
- LI.weight *= 0.9F;
- else
- LI.weight *= 0.5F;
- }
- }
-
- // Slightly prefer live interval that has been assigned a preferred reg.
- std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(LI.reg);
- if (Hint.first || Hint.second)
- LI.weight *= 1.01F;
-
- // Divide the weight of the interval by its size. This encourages
- // spilling of intervals that are large and have few uses, and
- // discourages spilling of small intervals with many uses.
- LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
- }
- }
+ CalculateSpillWeights();
DEBUG(dump());
return true;
diff --git a/libclamav/c++/llvm/lib/CodeGen/SimpleRegisterCoalescing.h b/libclamav/c++/llvm/lib/CodeGen/SimpleRegisterCoalescing.h
index 1830353..20b8eb2 100644
--- a/libclamav/c++/llvm/lib/CodeGen/SimpleRegisterCoalescing.h
+++ b/libclamav/c++/llvm/lib/CodeGen/SimpleRegisterCoalescing.h
@@ -18,7 +18,6 @@
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/RegisterCoalescer.h"
#include "llvm/ADT/BitVector.h"
-#include <queue>
namespace llvm {
class SimpleRegisterCoalescing;
@@ -33,44 +32,8 @@ namespace llvm {
struct CopyRec {
MachineInstr *MI;
unsigned LoopDepth;
- bool isBackEdge;
- CopyRec(MachineInstr *mi, unsigned depth, bool be)
- : MI(mi), LoopDepth(depth), isBackEdge(be) {};
- };
-
- template<class SF> class JoinPriorityQueue;
-
- /// CopyRecSort - Sorting function for coalescer queue.
- ///
- struct CopyRecSort : public std::binary_function<CopyRec,CopyRec,bool> {
- JoinPriorityQueue<CopyRecSort> *JPQ;
- explicit CopyRecSort(JoinPriorityQueue<CopyRecSort> *jpq) : JPQ(jpq) {}
- CopyRecSort(const CopyRecSort &RHS) : JPQ(RHS.JPQ) {}
- bool operator()(CopyRec left, CopyRec right) const;
- };
-
- /// JoinQueue - A priority queue of copy instructions the coalescer is
- /// going to process.
- template<class SF>
- class JoinPriorityQueue {
- SimpleRegisterCoalescing *Rc;
- std::priority_queue<CopyRec, std::vector<CopyRec>, SF> Queue;
-
- public:
- explicit JoinPriorityQueue(SimpleRegisterCoalescing *rc)
- : Rc(rc), Queue(SF(this)) {}
-
- bool empty() const { return Queue.empty(); }
- void push(CopyRec R) { Queue.push(R); }
- CopyRec pop() {
- if (empty()) return CopyRec(0, 0, false);
- CopyRec R = Queue.top();
- Queue.pop();
- return R;
- }
-
- // Callbacks to SimpleRegisterCoalescing.
- unsigned getRepIntervalSize(unsigned Reg);
+ CopyRec(MachineInstr *mi, unsigned depth)
+ : MI(mi), LoopDepth(depth) {};
};
class SimpleRegisterCoalescing : public MachineFunctionPass,
@@ -86,10 +49,6 @@ namespace llvm {
BitVector allocatableRegs_;
DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
- /// JoinQueue - A priority queue of copy instructions the coalescer is
- /// going to process.
- JoinPriorityQueue<CopyRecSort> *JoinQueue;
-
/// JoinedCopies - Keep track of copies eliminated due to coalescing.
///
SmallPtrSet<MachineInstr*, 32> JoinedCopies;
@@ -127,15 +86,6 @@ namespace llvm {
return false;
};
- /// getRepIntervalSize - Called from join priority queue sorting function.
- /// It returns the size of the interval that represent the given register.
- unsigned getRepIntervalSize(unsigned Reg) {
- if (!li_->hasInterval(Reg))
- return 0;
- return li_->getApproximateInstructionCount(li_->getInterval(Reg)) *
- LiveInterval::InstrSlots::NUM;
- }
-
/// print - Implement the dump method.
virtual void print(raw_ostream &O, const Module* = 0) const;
@@ -173,7 +123,6 @@ namespace llvm {
/// classes. The registers may be either phys or virt regs.
bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
-
/// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
/// the source value number is defined by a copy from the destination reg
/// see if we can merge these two destination reg valno# into a single
@@ -196,7 +145,7 @@ namespace llvm {
/// TrimLiveIntervalToLastUse - If there is a last use in the same basic
/// block as the copy instruction, trim the ive interval to the last use
/// and return true.
- bool TrimLiveIntervalToLastUse(unsigned CopyIdx,
+ bool TrimLiveIntervalToLastUse(MachineInstrIndex CopyIdx,
MachineBasicBlock *CopyMBB,
LiveInterval &li, const LiveRange *LR);
@@ -257,10 +206,6 @@ namespace llvm {
bool RangeIsDefinedByCopyFromReg(LiveInterval &li, LiveRange *LR,
unsigned Reg);
- /// isBackEdgeCopy - Return true if CopyMI is a back edge copy.
- ///
- bool isBackEdgeCopy(MachineInstr *CopyMI, unsigned DstReg) const;
-
/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
/// update the subregister number if it is not zero. If DstReg is a
/// physical register and the existing subregister number of the def / use
@@ -289,8 +234,13 @@ namespace llvm {
/// lastRegisterUse - Returns the last use of the specific register between
/// cycles Start and End or NULL if there are no uses.
- MachineOperand *lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
- unsigned &LastUseIdx) const;
+ MachineOperand *lastRegisterUse(MachineInstrIndex Start,
+ MachineInstrIndex End, unsigned Reg,
+ MachineInstrIndex &LastUseIdx) const;
+
+ /// CalculateSpillWeights - Compute spill weights for all virtual register
+ /// live intervals.
+ void CalculateSpillWeights();
void printRegName(unsigned reg) const;
};
diff --git a/libclamav/c++/llvm/lib/CodeGen/Spiller.cpp b/libclamav/c++/llvm/lib/CodeGen/Spiller.cpp
index 19cba9e..4326a89 100644
--- a/libclamav/c++/llvm/lib/CodeGen/Spiller.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/Spiller.cpp
@@ -51,13 +51,13 @@ protected:
/// Ensures there is space before the given machine instruction, returns the
/// instruction's new number.
- unsigned makeSpaceBefore(MachineInstr *mi) {
+ MachineInstrIndex makeSpaceBefore(MachineInstr *mi) {
if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) {
lis->scaleNumbering(2);
ls->scaleNumbering(2);
}
- unsigned miIdx = lis->getInstructionIndex(mi);
+ MachineInstrIndex miIdx = lis->getInstructionIndex(mi);
assert(lis->hasGapBeforeInstr(miIdx));
@@ -66,13 +66,13 @@ protected:
/// Ensure there is space after the given machine instruction, returns the
/// instruction's new number.
- unsigned makeSpaceAfter(MachineInstr *mi) {
+ MachineInstrIndex makeSpaceAfter(MachineInstr *mi) {
if (!lis->hasGapAfterInstr(lis->getInstructionIndex(mi))) {
lis->scaleNumbering(2);
ls->scaleNumbering(2);
}
- unsigned miIdx = lis->getInstructionIndex(mi);
+ MachineInstrIndex miIdx = lis->getInstructionIndex(mi);
assert(lis->hasGapAfterInstr(miIdx));
@@ -83,19 +83,19 @@ protected:
/// after the given instruction. Returns the base index of the inserted
/// instruction. The caller is responsible for adding an appropriate
/// LiveInterval to the LiveIntervals analysis.
- unsigned insertStoreAfter(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
+ MachineInstrIndex insertStoreAfter(MachineInstr *mi, unsigned ss,
+ unsigned vreg,
+ const TargetRegisterClass *trc) {
MachineBasicBlock::iterator nextInstItr(next(mi));
- unsigned miIdx = makeSpaceAfter(mi);
+ MachineInstrIndex miIdx = makeSpaceAfter(mi);
tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, vreg,
true, ss, trc);
MachineBasicBlock::iterator storeInstItr(next(mi));
MachineInstr *storeInst = &*storeInstItr;
- unsigned storeInstIdx = miIdx + LiveInterval::InstrSlots::NUM;
+ MachineInstrIndex storeInstIdx = lis->getNextIndex(miIdx);
assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
"Store inst index already in use.");
@@ -108,15 +108,15 @@ protected:
/// Insert a store of the given vreg to the given stack slot immediately
/// before the given instructnion. Returns the base index of the inserted
/// Instruction.
- unsigned insertStoreBefore(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
- unsigned miIdx = makeSpaceBefore(mi);
+ MachineInstrIndex insertStoreBefore(MachineInstr *mi, unsigned ss,
+ unsigned vreg,
+ const TargetRegisterClass *trc) {
+ MachineInstrIndex miIdx = makeSpaceBefore(mi);
tii->storeRegToStackSlot(*mi->getParent(), mi, vreg, true, ss, trc);
MachineBasicBlock::iterator storeInstItr(prior(mi));
MachineInstr *storeInst = &*storeInstItr;
- unsigned storeInstIdx = miIdx - LiveInterval::InstrSlots::NUM;
+ MachineInstrIndex storeInstIdx = lis->getPrevIndex(miIdx);
assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
"Store inst index already in use.");
@@ -131,13 +131,13 @@ protected:
unsigned vreg,
const TargetRegisterClass *trc) {
- unsigned storeInstIdx = insertStoreAfter(mi, ss, vreg, trc);
- unsigned start = lis->getDefIndex(lis->getInstructionIndex(mi)),
- end = lis->getUseIndex(storeInstIdx);
+ MachineInstrIndex storeInstIdx = insertStoreAfter(mi, ss, vreg, trc);
+ MachineInstrIndex start = lis->getDefIndex(lis->getInstructionIndex(mi)),
+ end = lis->getUseIndex(storeInstIdx);
VNInfo *vni =
li->getNextValue(storeInstIdx, 0, true, lis->getVNInfoAllocator());
- li->addKill(vni, storeInstIdx, false);
+ vni->addKill(storeInstIdx);
DEBUG(errs() << " Inserting store range: [" << start
<< ", " << end << ")\n");
LiveRange lr(start, end, vni);
@@ -149,18 +149,18 @@ protected:
/// after the given instruction. Returns the base index of the inserted
/// instruction. The caller is responsibel for adding/removing an appropriate
/// range vreg's LiveInterval.
- unsigned insertLoadAfter(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
+ MachineInstrIndex insertLoadAfter(MachineInstr *mi, unsigned ss,
+ unsigned vreg,
+ const TargetRegisterClass *trc) {
MachineBasicBlock::iterator nextInstItr(next(mi));
- unsigned miIdx = makeSpaceAfter(mi);
+ MachineInstrIndex miIdx = makeSpaceAfter(mi);
tii->loadRegFromStackSlot(*mi->getParent(), nextInstItr, vreg, ss, trc);
MachineBasicBlock::iterator loadInstItr(next(mi));
MachineInstr *loadInst = &*loadInstItr;
- unsigned loadInstIdx = miIdx + LiveInterval::InstrSlots::NUM;
+ MachineInstrIndex loadInstIdx = lis->getNextIndex(miIdx);
assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
"Store inst index already in use.");
@@ -174,15 +174,15 @@ protected:
/// before the given instruction. Returns the base index of the inserted
/// instruction. The caller is responsible for adding an appropriate
/// LiveInterval to the LiveIntervals analysis.
- unsigned insertLoadBefore(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
- unsigned miIdx = makeSpaceBefore(mi);
+ MachineInstrIndex insertLoadBefore(MachineInstr *mi, unsigned ss,
+ unsigned vreg,
+ const TargetRegisterClass *trc) {
+ MachineInstrIndex miIdx = makeSpaceBefore(mi);
tii->loadRegFromStackSlot(*mi->getParent(), mi, vreg, ss, trc);
MachineBasicBlock::iterator loadInstItr(prior(mi));
MachineInstr *loadInst = &*loadInstItr;
- unsigned loadInstIdx = miIdx - LiveInterval::InstrSlots::NUM;
+ MachineInstrIndex loadInstIdx = lis->getPrevIndex(miIdx);
assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
"Load inst index already in use.");
@@ -197,13 +197,13 @@ protected:
unsigned vreg,
const TargetRegisterClass *trc) {
- unsigned loadInstIdx = insertLoadBefore(mi, ss, vreg, trc);
- unsigned start = lis->getDefIndex(loadInstIdx),
- end = lis->getUseIndex(lis->getInstructionIndex(mi));
+ MachineInstrIndex loadInstIdx = insertLoadBefore(mi, ss, vreg, trc);
+ MachineInstrIndex start = lis->getDefIndex(loadInstIdx),
+ end = lis->getUseIndex(lis->getInstructionIndex(mi));
VNInfo *vni =
li->getNextValue(loadInstIdx, 0, true, lis->getVNInfoAllocator());
- li->addKill(vni, lis->getInstructionIndex(mi), false);
+ vni->addKill(lis->getInstructionIndex(mi));
DEBUG(errs() << " Intserting load range: [" << start
<< ", " << end << ")\n");
LiveRange lr(start, end, vni);
@@ -321,23 +321,21 @@ public:
vrm->assignVirt2StackSlot(li->reg, ss);
MachineInstr *mi = 0;
- unsigned storeIdx = 0;
+ MachineInstrIndex storeIdx = MachineInstrIndex();
if (valno->isDefAccurate()) {
// If we have an accurate def we can just grab an iterator to the instr
// after the def.
mi = lis->getInstructionFromIndex(valno->def);
- storeIdx = insertStoreAfter(mi, ss, li->reg, trc) +
- LiveInterval::InstrSlots::DEF;
+ storeIdx = lis->getDefIndex(insertStoreAfter(mi, ss, li->reg, trc));
} else {
// if we get here we have a PHI def.
mi = &lis->getMBBFromIndex(valno->def)->front();
- storeIdx = insertStoreBefore(mi, ss, li->reg, trc) +
- LiveInterval::InstrSlots::DEF;
+ storeIdx = lis->getDefIndex(insertStoreBefore(mi, ss, li->reg, trc));
}
MachineBasicBlock *defBlock = mi->getParent();
- unsigned loadIdx = 0;
+ MachineInstrIndex loadIdx = MachineInstrIndex();
// Now we need to find the load...
MachineBasicBlock::iterator useItr(mi);
@@ -345,13 +343,11 @@ public:
if (useItr != defBlock->end()) {
MachineInstr *loadInst = useItr;
- loadIdx = insertLoadBefore(loadInst, ss, li->reg, trc) +
- LiveInterval::InstrSlots::USE;
+ loadIdx = lis->getUseIndex(insertLoadBefore(loadInst, ss, li->reg, trc));
}
else {
MachineInstr *loadInst = &defBlock->back();
- loadIdx = insertLoadAfter(loadInst, ss, li->reg, trc) +
- LiveInterval::InstrSlots::USE;
+ loadIdx = lis->getUseIndex(insertLoadAfter(loadInst, ss, li->reg, trc));
}
li->removeRange(storeIdx, loadIdx, true);
diff --git a/libclamav/c++/llvm/lib/CodeGen/StackSlotColoring.cpp b/libclamav/c++/llvm/lib/CodeGen/StackSlotColoring.cpp
index 5884b82..fad0808 100644
--- a/libclamav/c++/llvm/lib/CodeGen/StackSlotColoring.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/StackSlotColoring.cpp
@@ -18,6 +18,7 @@
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Support/CommandLine.h"
@@ -451,6 +452,7 @@ bool StackSlotColoring::AllMemRefsCanBeUnfolded(int SS) {
/// to old frame index with new one.
void StackSlotColoring::RewriteInstruction(MachineInstr *MI, int OldFI,
int NewFI, MachineFunction &MF) {
+ // Update the operands.
for (unsigned i = 0, ee = MI->getNumOperands(); i != ee; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isFI())
@@ -461,22 +463,15 @@ void StackSlotColoring::RewriteInstruction(MachineInstr *MI, int OldFI,
MO.setIndex(NewFI);
}
- // Update the MachineMemOperand for the new memory location.
- // FIXME: We need a better method of managing these too.
- SmallVector<MachineMemOperand, 2> MMOs(MI->memoperands_begin(),
- MI->memoperands_end());
- MI->clearMemOperands(MF);
+ // Update the memory references. This changes the MachineMemOperands
+ // directly. They may be in use by multiple instructions, however all
+ // instructions using OldFI are being rewritten to use NewFI.
const Value *OldSV = PseudoSourceValue::getFixedStack(OldFI);
- for (unsigned i = 0, ee = MMOs.size(); i != ee; ++i) {
- if (MMOs[i].getValue() != OldSV)
- MI->addMemOperand(MF, MMOs[i]);
- else {
- MachineMemOperand MMO(PseudoSourceValue::getFixedStack(NewFI),
- MMOs[i].getFlags(), MMOs[i].getOffset(),
- MMOs[i].getSize(), MMOs[i].getAlignment());
- MI->addMemOperand(MF, MMO);
- }
- }
+ const Value *NewSV = PseudoSourceValue::getFixedStack(NewFI);
+ for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
+ E = MI->memoperands_end(); I != E; ++I)
+ if ((*I)->getValue() == OldSV)
+ (*I)->setValue(NewSV);
}
/// PropagateBackward - Traverse backward and look for the definition of
@@ -558,7 +553,6 @@ bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII,
SmallVector<MachineOperand*, 4> Uses;
while (++MII != MBB->end()) {
- bool FoundUse = false;
bool FoundKill = false;
const TargetInstrDesc &TID = MII->getDesc();
for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
@@ -581,7 +575,6 @@ bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII,
const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
if (RC && !RC->contains(NewReg))
return false;
- FoundUse = true;
if (MO.isKill())
FoundKill = true;
diff --git a/libclamav/c++/llvm/lib/CodeGen/StrongPHIElimination.cpp b/libclamav/c++/llvm/lib/CodeGen/StrongPHIElimination.cpp
index fee71b0..d2f93fc 100644
--- a/libclamav/c++/llvm/lib/CodeGen/StrongPHIElimination.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/StrongPHIElimination.cpp
@@ -295,7 +295,7 @@ StrongPHIElimination::computeDomForest(
static bool isLiveIn(unsigned r, MachineBasicBlock* MBB,
LiveIntervals& LI) {
LiveInterval& I = LI.getOrCreateInterval(r);
- unsigned idx = LI.getMBBStartIdx(MBB);
+ MachineInstrIndex idx = LI.getMBBStartIdx(MBB);
return I.liveAt(idx);
}
@@ -428,7 +428,7 @@ void StrongPHIElimination::processBlock(MachineBasicBlock* MBB) {
}
LiveInterval& PI = LI.getOrCreateInterval(DestReg);
- unsigned pIdx = LI.getDefIndex(LI.getInstructionIndex(P));
+ MachineInstrIndex pIdx = LI.getDefIndex(LI.getInstructionIndex(P));
VNInfo* PVN = PI.getLiveRangeContaining(pIdx)->valno;
PhiValueNumber.insert(std::make_pair(DestReg, PVN->id));
@@ -748,7 +748,7 @@ void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
LiveInterval& I = LI.getInterval(curr.second);
MachineBasicBlock::iterator term = MBB->getFirstTerminator();
- unsigned endIdx = 0;
+ MachineInstrIndex endIdx = MachineInstrIndex();
if (term != MBB->end())
endIdx = LI.getInstructionIndex(term);
else
@@ -784,16 +784,15 @@ void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
InsertedPHIDests.begin(), E = InsertedPHIDests.end(); I != E; ++I) {
if (RegHandled.insert(I->first).second) {
LiveInterval& Int = LI.getOrCreateInterval(I->first);
- unsigned instrIdx = LI.getInstructionIndex(I->second);
- if (Int.liveAt(LiveIntervals::getDefIndex(instrIdx)))
- Int.removeRange(LiveIntervals::getDefIndex(instrIdx),
- LI.getMBBEndIdx(I->second->getParent())+1,
+ MachineInstrIndex instrIdx = LI.getInstructionIndex(I->second);
+ if (Int.liveAt(LI.getDefIndex(instrIdx)))
+ Int.removeRange(LI.getDefIndex(instrIdx),
+ LI.getNextSlot(LI.getMBBEndIdx(I->second->getParent())),
true);
LiveRange R = LI.addLiveRangeToEndOfBlock(I->first, I->second);
R.valno->setCopy(I->second);
- R.valno->def =
- LiveIntervals::getDefIndex(LI.getInstructionIndex(I->second));
+ R.valno->def = LI.getDefIndex(LI.getInstructionIndex(I->second));
}
}
}
@@ -819,7 +818,7 @@ void StrongPHIElimination::InsertCopies(MachineDomTreeNode* MDTN,
// Remove the live range for the old vreg.
LiveInterval& OldInt = LI.getInterval(I->getOperand(i).getReg());
LiveInterval::iterator OldLR = OldInt.FindLiveRangeContaining(
- LiveIntervals::getUseIndex(LI.getInstructionIndex(I)));
+ LI.getUseIndex(LI.getInstructionIndex(I)));
if (OldLR != OldInt.end())
OldInt.removeRange(*OldLR, true);
@@ -831,11 +830,11 @@ void StrongPHIElimination::InsertCopies(MachineDomTreeNode* MDTN,
VNInfo* FirstVN = *Int.vni_begin();
FirstVN->setHasPHIKill(false);
if (I->getOperand(i).isKill())
- Int.addKill(FirstVN,
- LiveIntervals::getUseIndex(LI.getInstructionIndex(I)), false);
+ FirstVN->addKill(
+ LI.getUseIndex(LI.getInstructionIndex(I)));
LiveRange LR (LI.getMBBStartIdx(I->getParent()),
- LiveIntervals::getUseIndex(LI.getInstructionIndex(I))+1,
+ LI.getNextSlot(LI.getUseIndex(LI.getInstructionIndex(I))),
FirstVN);
Int.addRange(LR);
@@ -870,8 +869,8 @@ bool StrongPHIElimination::mergeLiveIntervals(unsigned primary,
for (LiveInterval::iterator I = RHS.begin(), E = RHS.end(); I != E; ++I) {
LiveRange R = *I;
- unsigned Start = R.start;
- unsigned End = R.end;
+ MachineInstrIndex Start = R.start;
+ MachineInstrIndex End = R.end;
if (LHS.getLiveRangeContaining(Start))
return false;
@@ -968,16 +967,16 @@ bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) {
LI.computeNumbering();
LiveInterval& Int = LI.getOrCreateInterval(I->first);
- unsigned instrIdx =
+ MachineInstrIndex instrIdx =
LI.getInstructionIndex(--SI->second->getFirstTerminator());
- if (Int.liveAt(LiveIntervals::getDefIndex(instrIdx)))
- Int.removeRange(LiveIntervals::getDefIndex(instrIdx),
- LI.getMBBEndIdx(SI->second)+1, true);
+ if (Int.liveAt(LI.getDefIndex(instrIdx)))
+ Int.removeRange(LI.getDefIndex(instrIdx),
+ LI.getNextSlot(LI.getMBBEndIdx(SI->second)), true);
LiveRange R = LI.addLiveRangeToEndOfBlock(I->first,
--SI->second->getFirstTerminator());
R.valno->setCopy(--SI->second->getFirstTerminator());
- R.valno->def = LiveIntervals::getDefIndex(instrIdx);
+ R.valno->def = LI.getDefIndex(instrIdx);
DEBUG(errs() << "Renaming failed: " << SI->first << " -> "
<< I->first << "\n");
@@ -1012,7 +1011,7 @@ bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) {
if (PI.containsOneValue()) {
LI.removeInterval(DestReg);
} else {
- unsigned idx = LI.getDefIndex(LI.getInstructionIndex(PInstr));
+ MachineInstrIndex idx = LI.getDefIndex(LI.getInstructionIndex(PInstr));
PI.removeRange(*PI.getLiveRangeContaining(idx), true);
}
} else {
@@ -1026,8 +1025,7 @@ bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) {
LiveInterval& InputI = LI.getInterval(reg);
if (MBB != PInstr->getParent() &&
InputI.liveAt(LI.getMBBStartIdx(PInstr->getParent())) &&
- InputI.expiredAt(LI.getInstructionIndex(PInstr) +
- LiveInterval::InstrSlots::NUM))
+ InputI.expiredAt(LI.getNextIndex(LI.getInstructionIndex(PInstr))))
InputI.removeRange(LI.getMBBStartIdx(PInstr->getParent()),
LI.getInstructionIndex(PInstr),
true);
@@ -1035,7 +1033,7 @@ bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) {
// If the PHI is not dead, then the valno defined by the PHI
// now has an unknown def.
- unsigned idx = LI.getDefIndex(LI.getInstructionIndex(PInstr));
+ MachineInstrIndex idx = LI.getDefIndex(LI.getInstructionIndex(PInstr));
const LiveRange* PLR = PI.getLiveRangeContaining(idx);
PLR->valno->setIsPHIDef(true);
LiveRange R (LI.getMBBStartIdx(PInstr->getParent()),
diff --git a/libclamav/c++/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp b/libclamav/c++/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
index 8aca0cc..ab67cd2 100644
--- a/libclamav/c++/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -17,6 +17,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
@@ -203,11 +204,11 @@ TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
"Folded a use to a non-load!");
const MachineFrameInfo &MFI = *MF.getFrameInfo();
assert(MFI.getObjectOffset(FrameIndex) != -1);
- MachineMemOperand MMO(PseudoSourceValue::getFixedStack(FrameIndex),
- Flags,
- MFI.getObjectOffset(FrameIndex),
- MFI.getObjectSize(FrameIndex),
- MFI.getObjectAlignment(FrameIndex));
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIndex),
+ Flags, /*Offset=*/0,
+ MFI.getObjectSize(FrameIndex),
+ MFI.getObjectAlignment(FrameIndex));
NewMI->addMemOperand(MF, MMO);
return NewMI;
@@ -232,9 +233,8 @@ TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
if (!NewMI) return 0;
// Copy the memoperands from the load to the folded instruction.
- for (std::list<MachineMemOperand>::iterator I = LoadMI->memoperands_begin(),
- E = LoadMI->memoperands_end(); I != E; ++I)
- NewMI->addMemOperand(MF, *I);
+ NewMI->setMemRefs(LoadMI->memoperands_begin(),
+ LoadMI->memoperands_end());
return NewMI;
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/libclamav/c++/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 738b3c9..a343fa4 100644
--- a/libclamav/c++/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -106,6 +106,21 @@ namespace {
MachineFunction::iterator &mbbi,
unsigned RegB, unsigned Dist);
+ typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill;
+ bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
+ SmallVector<NewKill, 4> &NewKills,
+ MachineBasicBlock *MBB, unsigned Dist);
+ bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
+ MachineBasicBlock::iterator &nmi,
+ MachineFunction::iterator &mbbi,
+ unsigned regB, unsigned regBIdx, unsigned Dist);
+
+ bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
+ MachineBasicBlock::iterator &nmi,
+ MachineFunction::iterator &mbbi,
+ unsigned SrcIdx, unsigned DstIdx,
+ unsigned Dist);
+
void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
SmallPtrSet<MachineInstr*, 8> &Processed);
@@ -736,6 +751,149 @@ static bool isSafeToDelete(MachineInstr *MI, unsigned Reg,
return true;
}
+/// canUpdateDeletedKills - Check if all the registers listed in Kills are
+/// killed by instructions in MBB preceding the current instruction at
+/// position Dist. If so, return true and record information about the
+/// preceding kills in NewKills.
+bool TwoAddressInstructionPass::
+canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
+ SmallVector<NewKill, 4> &NewKills,
+ MachineBasicBlock *MBB, unsigned Dist) {
+ while (!Kills.empty()) {
+ unsigned Kill = Kills.back();
+ Kills.pop_back();
+ if (TargetRegisterInfo::isPhysicalRegister(Kill))
+ return false;
+
+ MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist);
+ if (!LastKill)
+ return false;
+
+ bool isModRef = LastKill->modifiesRegister(Kill);
+ NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef),
+ LastKill));
+ }
+ return true;
+}
+
+/// DeleteUnusedInstr - If an instruction with a tied register operand can
+/// be safely deleted, just delete it.
+bool
+TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
+ MachineBasicBlock::iterator &nmi,
+ MachineFunction::iterator &mbbi,
+ unsigned regB, unsigned regBIdx,
+ unsigned Dist) {
+ // Check if the instruction has no side effects and if all its defs are dead.
+ SmallVector<unsigned, 4> Kills;
+ if (!isSafeToDelete(mi, regB, TII, Kills))
+ return false;
+
+ // If this instruction kills some virtual registers, we need to
+ // update the kill information. If it's not possible to do so,
+ // then bail out.
+ SmallVector<NewKill, 4> NewKills;
+ if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist))
+ return false;
+
+ if (LV) {
+ while (!NewKills.empty()) {
+ MachineInstr *NewKill = NewKills.back().second;
+ unsigned Kill = NewKills.back().first.first;
+ bool isDead = NewKills.back().first.second;
+ NewKills.pop_back();
+ if (LV->removeVirtualRegisterKilled(Kill, mi)) {
+ if (isDead)
+ LV->addVirtualRegisterDead(Kill, NewKill);
+ else
+ LV->addVirtualRegisterKilled(Kill, NewKill);
+ }
+ }
+
+ // If regB was marked as a kill, update its Kills list.
+ if (mi->getOperand(regBIdx).isKill())
+ LV->removeVirtualRegisterKilled(regB, mi);
+ }
+
+ mbbi->erase(mi); // Nuke the old inst.
+ mi = nmi;
+ return true;
+}
+
+/// TryInstructionTransform - For the case where an instruction has a single
+/// pair of tied register operands, attempt some transformations that may
+/// either eliminate the tied operands or improve the opportunities for
+/// coalescing away the register copy. Returns true if the tied operands
+/// are eliminated altogether.
+bool TwoAddressInstructionPass::
+TryInstructionTransform(MachineBasicBlock::iterator &mi,
+ MachineBasicBlock::iterator &nmi,
+ MachineFunction::iterator &mbbi,
+ unsigned SrcIdx, unsigned DstIdx, unsigned Dist) {
+ const TargetInstrDesc &TID = mi->getDesc();
+ unsigned regA = mi->getOperand(DstIdx).getReg();
+ unsigned regB = mi->getOperand(SrcIdx).getReg();
+
+ assert(TargetRegisterInfo::isVirtualRegister(regB) &&
+ "cannot make instruction into two-address form");
+
+ // If regA is dead and the instruction can be deleted, just delete
+ // it so it doesn't clobber regB.
+ bool regBKilled = isKilled(*mi, regB, MRI, TII);
+ if (!regBKilled && mi->getOperand(DstIdx).isDead() &&
+ DeleteUnusedInstr(mi, nmi, mbbi, regB, SrcIdx, Dist)) {
+ ++NumDeletes;
+ return true; // Done with this instruction.
+ }
+
+ // Check if it is profitable to commute the operands.
+ unsigned SrcOp1, SrcOp2;
+ unsigned regC = 0;
+ unsigned regCIdx = ~0U;
+ bool TryCommute = false;
+ bool AggressiveCommute = false;
+ if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
+ TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
+ if (SrcIdx == SrcOp1)
+ regCIdx = SrcOp2;
+ else if (SrcIdx == SrcOp2)
+ regCIdx = SrcOp1;
+
+ if (regCIdx != ~0U) {
+ regC = mi->getOperand(regCIdx).getReg();
+ if (!regBKilled && isKilled(*mi, regC, MRI, TII))
+ // If C dies but B does not, swap the B and C operands.
+ // This makes the live ranges of A and C joinable.
+ TryCommute = true;
+ else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) {
+ TryCommute = true;
+ AggressiveCommute = true;
+ }
+ }
+ }
+
+ // If it's profitable to commute, try to do so.
+ if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
+ ++NumCommuted;
+ if (AggressiveCommute)
+ ++NumAggrCommuted;
+ return false;
+ }
+
+ if (TID.isConvertibleTo3Addr()) {
+ // This instruction is potentially convertible to a true
+ // three-address instruction. Check if it is profitable.
+ if (!regBKilled || isProfitableToConv3Addr(regA)) {
+ // Try to convert it.
+ if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
+ ++NumConvertedTo3Addr;
+ return true; // Done with this instruction.
+ }
+ }
+ }
+ return false;
+}
+
/// runOnMachineFunction - Reduce two-address instructions to two operands.
///
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
@@ -756,6 +914,10 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
BitVector ReMatRegs;
ReMatRegs.resize(MRI->getLastVirtReg()+1);
+ typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
+ TiedOperandMap;
+ TiedOperandMap TiedOperands(4);
+
SmallPtrSet<MachineInstr*, 8> Processed;
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
mbbi != mbbe; ++mbbi) {
@@ -774,178 +936,92 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
ProcessCopy(&*mi, &*mbbi, Processed);
+ // First scan through all the tied register uses in this instruction
+ // and record a list of pairs of tied operands for each register.
unsigned NumOps = (mi->getOpcode() == TargetInstrInfo::INLINEASM)
? mi->getNumOperands() : TID.getNumOperands();
- for (unsigned si = 0; si < NumOps; ++si) {
- unsigned ti = 0;
- if (!mi->isRegTiedToDefOperand(si, &ti))
+ for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
+ unsigned DstIdx = 0;
+ if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
continue;
if (FirstTied) {
+ FirstTied = false;
++NumTwoAddressInstrs;
DEBUG(errs() << '\t' << *mi);
}
- FirstTied = false;
+ assert(mi->getOperand(SrcIdx).isReg() &&
+ mi->getOperand(SrcIdx).getReg() &&
+ mi->getOperand(SrcIdx).isUse() &&
+ "two address instruction invalid");
+
+ unsigned regB = mi->getOperand(SrcIdx).getReg();
+ TiedOperandMap::iterator OI = TiedOperands.find(regB);
+ if (OI == TiedOperands.end()) {
+ SmallVector<std::pair<unsigned, unsigned>, 4> TiedPair;
+ OI = TiedOperands.insert(std::make_pair(regB, TiedPair)).first;
+ }
+ OI->second.push_back(std::make_pair(SrcIdx, DstIdx));
+ }
- assert(mi->getOperand(si).isReg() && mi->getOperand(si).getReg() &&
- mi->getOperand(si).isUse() && "two address instruction invalid");
+ // Now iterate over the information collected above.
+ for (TiedOperandMap::iterator OI = TiedOperands.begin(),
+ OE = TiedOperands.end(); OI != OE; ++OI) {
+ SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
+
+ // If the instruction has a single pair of tied operands, try some
+ // transformations that may either eliminate the tied operands or
+ // improve the opportunities for coalescing away the register copy.
+ if (TiedOperands.size() == 1 && TiedPairs.size() == 1) {
+ unsigned SrcIdx = TiedPairs[0].first;
+ unsigned DstIdx = TiedPairs[0].second;
+
+ // If the registers are already equal, nothing needs to be done.
+ if (mi->getOperand(SrcIdx).getReg() ==
+ mi->getOperand(DstIdx).getReg())
+ break; // Done with this instruction.
+
+ if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist))
+ break; // The tied operands have been eliminated.
+ }
- // If the two operands are the same we just remove the use
- // and mark the def as def&use, otherwise we have to insert a copy.
- if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
- // Rewrite:
- // a = b op c
- // to:
- // a = b
- // a = a op c
- unsigned regA = mi->getOperand(ti).getReg();
- unsigned regB = mi->getOperand(si).getReg();
- unsigned regASubIdx = mi->getOperand(ti).getSubReg();
+ bool RemovedKillFlag = false;
+ bool AllUsesCopied = true;
+ unsigned LastCopiedReg = 0;
+ unsigned regB = OI->first;
+ for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
+ unsigned SrcIdx = TiedPairs[tpi].first;
+ unsigned DstIdx = TiedPairs[tpi].second;
+ unsigned regA = mi->getOperand(DstIdx).getReg();
+ // Grab regB from the instruction because it may have changed if the
+ // instruction was commuted.
+ regB = mi->getOperand(SrcIdx).getReg();
+
+ if (regA == regB) {
+ // The register is tied to multiple destinations (or else we would
+ // not have continued this far), but this use of the register
+ // already matches the tied destination. Leave it.
+ AllUsesCopied = false;
+ continue;
+ }
+ LastCopiedReg = regA;
assert(TargetRegisterInfo::isVirtualRegister(regB) &&
"cannot make instruction into two-address form");
#ifndef NDEBUG
- // First, verify that we don't have a use of a in the instruction (a =
- // b + a for example) because our transformation will not work. This
- // should never occur because we are in SSA form.
+ // First, verify that we don't have a use of "a" in the instruction
+ // (a = b + a for example) because our transformation will not
+ // work. This should never occur because we are in SSA form.
for (unsigned i = 0; i != mi->getNumOperands(); ++i)
- assert(i == ti ||
+ assert(i == DstIdx ||
!mi->getOperand(i).isReg() ||
mi->getOperand(i).getReg() != regA);
#endif
- // If this instruction is not the killing user of B, see if we can
- // rearrange the code to make it so. Making it the killing user will
- // allow us to coalesce A and B together, eliminating the copy we are
- // about to insert.
- if (!isKilled(*mi, regB, MRI, TII)) {
- // If regA is dead and the instruction can be deleted, just delete
- // it so it doesn't clobber regB.
- SmallVector<unsigned, 4> Kills;
- if (mi->getOperand(ti).isDead() &&
- isSafeToDelete(mi, regB, TII, Kills)) {
- SmallVector<std::pair<std::pair<unsigned, bool>
- ,MachineInstr*>, 4> NewKills;
- bool ReallySafe = true;
- // If this instruction kills some virtual registers, we need
- // update the kill information. If it's not possible to do so,
- // then bail out.
- while (!Kills.empty()) {
- unsigned Kill = Kills.back();
- Kills.pop_back();
- if (TargetRegisterInfo::isPhysicalRegister(Kill)) {
- ReallySafe = false;
- break;
- }
- MachineInstr *LastKill = FindLastUseInMBB(Kill, &*mbbi, Dist);
- if (LastKill) {
- bool isModRef = LastKill->modifiesRegister(Kill);
- NewKills.push_back(std::make_pair(std::make_pair(Kill,isModRef),
- LastKill));
- } else {
- ReallySafe = false;
- break;
- }
- }
-
- if (ReallySafe) {
- if (LV) {
- while (!NewKills.empty()) {
- MachineInstr *NewKill = NewKills.back().second;
- unsigned Kill = NewKills.back().first.first;
- bool isDead = NewKills.back().first.second;
- NewKills.pop_back();
- if (LV->removeVirtualRegisterKilled(Kill, mi)) {
- if (isDead)
- LV->addVirtualRegisterDead(Kill, NewKill);
- else
- LV->addVirtualRegisterKilled(Kill, NewKill);
- }
- }
- }
-
- // We're really going to nuke the old inst. If regB was marked
- // as a kill we need to update its Kills list.
- if (mi->getOperand(si).isKill())
- LV->removeVirtualRegisterKilled(regB, mi);
-
- mbbi->erase(mi); // Nuke the old inst.
- mi = nmi;
- ++NumDeletes;
- break; // Done with this instruction.
- }
- }
-
- // If this instruction is commutative, check to see if C dies. If
- // so, swap the B and C operands. This makes the live ranges of A
- // and C joinable.
- // FIXME: This code also works for A := B op C instructions.
- unsigned SrcOp1, SrcOp2;
- if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
- TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
- unsigned regC = 0;
- if (si == SrcOp1)
- regC = mi->getOperand(SrcOp2).getReg();
- else if (si == SrcOp2)
- regC = mi->getOperand(SrcOp1).getReg();
- if (isKilled(*mi, regC, MRI, TII)) {
- if (CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
- ++NumCommuted;
- regB = regC;
- goto InstructionRearranged;
- }
- }
- }
-
- // If this instruction is potentially convertible to a true
- // three-address instruction,
- if (TID.isConvertibleTo3Addr()) {
- // FIXME: This assumes there are no more operands which are tied
- // to another register.
-#ifndef NDEBUG
- for (unsigned i = si + 1, e = TID.getNumOperands(); i < e; ++i)
- assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
-#endif
-
- if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
- ++NumConvertedTo3Addr;
- break; // Done with this instruction.
- }
- }
- }
-
- // If it's profitable to commute the instruction, do so.
- unsigned SrcOp1, SrcOp2;
- if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
- TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
- unsigned regC = 0;
- if (si == SrcOp1)
- regC = mi->getOperand(SrcOp2).getReg();
- else if (si == SrcOp2)
- regC = mi->getOperand(SrcOp1).getReg();
-
- if (regC && isProfitableToCommute(regB, regC, mi, mbbi, Dist))
- if (CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
- ++NumAggrCommuted;
- ++NumCommuted;
- regB = regC;
- goto InstructionRearranged;
- }
- }
-
- // If it's profitable to convert the 2-address instruction to a
- // 3-address one, do so.
- if (TID.isConvertibleTo3Addr() && isProfitableToConv3Addr(regA)) {
- if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
- ++NumConvertedTo3Addr;
- break; // Done with this instruction.
- }
- }
-
- InstructionRearranged:
- const TargetRegisterClass* rc = MRI->getRegClass(regB);
+ // Emit a copy or rematerialize the definition.
+ const TargetRegisterClass *rc = MRI->getRegClass(regB);
MachineInstr *DefMI = MRI->getVRegDef(regB);
// If it's safe and profitable, remat the definition instead of
// copying it.
@@ -954,6 +1030,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
DefMI->isSafeToReMat(TII, regB) &&
isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
DEBUG(errs() << "2addr: REMATTING : " << *DefMI << "\n");
+ unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI);
ReMatRegs.set(regB);
++NumReMats;
@@ -968,32 +1045,57 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
DistanceMap.insert(std::make_pair(prevMI, Dist));
DistanceMap[mi] = ++Dist;
- // Update live variables for regB.
- if (LV) {
- if (LV->removeVirtualRegisterKilled(regB, mi))
- LV->addVirtualRegisterKilled(regB, prevMI);
+ DEBUG(errs() << "\t\tprepend:\t" << *prevMI);
- if (LV->removeVirtualRegisterDead(regB, mi))
- LV->addVirtualRegisterDead(regB, prevMI);
+ MachineOperand &MO = mi->getOperand(SrcIdx);
+ assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
+ "inconsistent operand info for 2-reg pass");
+ if (MO.isKill()) {
+ MO.setIsKill(false);
+ RemovedKillFlag = true;
}
+ MO.setReg(regA);
+ }
- DEBUG(errs() << "\t\tprepend:\t" << *prevMI);
-
- // Replace all occurences of regB with regA.
+ if (AllUsesCopied) {
+ // Replace other (un-tied) uses of regB with LastCopiedReg.
for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
- if (mi->getOperand(i).isReg() &&
- mi->getOperand(i).getReg() == regB)
- mi->getOperand(i).setReg(regA);
+ MachineOperand &MO = mi->getOperand(i);
+ if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
+ if (MO.isKill()) {
+ MO.setIsKill(false);
+ RemovedKillFlag = true;
+ }
+ MO.setReg(LastCopiedReg);
+ }
}
- }
- assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
- mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
+ // Update live variables for regB.
+ if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
+ LV->addVirtualRegisterKilled(regB, prior(mi));
+
+ } else if (RemovedKillFlag) {
+ // Some tied uses of regB matched their destination registers, so
+ // regB is still used in this instruction, but a kill flag was
+ // removed from a different tied use of regB, so now we need to add
+ // a kill flag to one of the remaining uses of regB.
+ for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = mi->getOperand(i);
+ if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
+ MO.setIsKill(true);
+ break;
+ }
+ }
+ }
+
MadeChange = true;
DEBUG(errs() << "\t\trewrite to:\t" << *mi);
}
+ // Clear TiedOperands here instead of at the top of the loop
+ // since most instructions do not have tied operands.
+ TiedOperands.clear();
mi = nmi;
}
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/UnreachableBlockElim.cpp b/libclamav/c++/llvm/lib/CodeGen/UnreachableBlockElim.cpp
index 8fe1554..e7c3412 100644
--- a/libclamav/c++/llvm/lib/CodeGen/UnreachableBlockElim.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/UnreachableBlockElim.cpp
@@ -26,6 +26,7 @@
#include "llvm/Function.h"
#include "llvm/Pass.h"
#include "llvm/Type.h"
+#include "llvm/Analysis/ProfileInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
@@ -44,6 +45,10 @@ namespace {
public:
static char ID; // Pass identification, replacement for typeid
UnreachableBlockElim() : FunctionPass(&ID) {}
+
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addPreserved<ProfileInfo>();
+ }
};
}
char UnreachableBlockElim::ID = 0;
@@ -79,8 +84,11 @@ bool UnreachableBlockElim::runOnFunction(Function &F) {
}
// Actually remove the blocks now.
- for (unsigned i = 0, e = DeadBlocks.size(); i != e; ++i)
+ ProfileInfo *PI = getAnalysisIfAvailable<ProfileInfo>();
+ for (unsigned i = 0, e = DeadBlocks.size(); i != e; ++i) {
+ if (PI) PI->removeBlock(DeadBlocks[i]);
DeadBlocks[i]->eraseFromParent();
+ }
return DeadBlocks.size();
}
diff --git a/libclamav/c++/llvm/lib/CodeGen/VirtRegMap.h b/libclamav/c++/llvm/lib/CodeGen/VirtRegMap.h
index 482ba1b..ca174d5 100644
--- a/libclamav/c++/llvm/lib/CodeGen/VirtRegMap.h
+++ b/libclamav/c++/llvm/lib/CodeGen/VirtRegMap.h
@@ -18,6 +18,7 @@
#define LLVM_CODEGEN_VIRTREGMAP_H
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
@@ -79,7 +80,7 @@ namespace llvm {
/// Virt2SplitKillMap - This is splitted virtual register to its last use
/// (kill) index mapping.
- IndexedMap<unsigned> Virt2SplitKillMap;
+ IndexedMap<MachineInstrIndex> Virt2SplitKillMap;
/// ReMatMap - This is virtual register to re-materialized instruction
/// mapping. Each virtual register whose definition is going to be
@@ -141,7 +142,7 @@ namespace llvm {
VirtRegMap() : MachineFunctionPass(&ID), Virt2PhysMap(NO_PHYS_REG),
Virt2StackSlotMap(NO_STACK_SLOT),
Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
- Virt2SplitKillMap(0), ReMatMap(NULL),
+ Virt2SplitKillMap(MachineInstrIndex()), ReMatMap(NULL),
ReMatId(MAX_STACK_SLOT+1),
LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { }
virtual bool runOnMachineFunction(MachineFunction &MF);
@@ -265,17 +266,17 @@ namespace llvm {
}
/// @brief record the last use (kill) of a split virtual register.
- void addKillPoint(unsigned virtReg, unsigned index) {
+ void addKillPoint(unsigned virtReg, MachineInstrIndex index) {
Virt2SplitKillMap[virtReg] = index;
}
- unsigned getKillPoint(unsigned virtReg) const {
+ MachineInstrIndex getKillPoint(unsigned virtReg) const {
return Virt2SplitKillMap[virtReg];
}
/// @brief remove the last use (kill) of a split virtual register.
void removeKillPoint(unsigned virtReg) {
- Virt2SplitKillMap[virtReg] = 0;
+ Virt2SplitKillMap[virtReg] = MachineInstrIndex();
}
/// @brief returns true if the specified MachineInstr is a spill point.
diff --git a/libclamav/c++/llvm/lib/CodeGen/VirtRegRewriter.cpp b/libclamav/c++/llvm/lib/CodeGen/VirtRegRewriter.cpp
index 6da6a9b..670e1cb 100644
--- a/libclamav/c++/llvm/lib/CodeGen/VirtRegRewriter.cpp
+++ b/libclamav/c++/llvm/lib/CodeGen/VirtRegRewriter.cpp
@@ -797,7 +797,7 @@ unsigned ReuseInfo::GetRegForReload(const TargetRegisterClass *RC,
// value aliases the new register. If so, codegen the previous reload
// and use this one.
unsigned PRRU = Op.PhysRegReused;
- if (TRI->areAliases(PRRU, PhysReg)) {
+ if (TRI->regsOverlap(PRRU, PhysReg)) {
// Okay, we found out that an alias of a reused register
// was used. This isn't good because it means we have
// to undo a previous reuse.
@@ -1128,8 +1128,7 @@ private:
return false;
// Back-schedule reloads and remats.
- MachineBasicBlock::iterator InsertLoc =
- ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, false, SS, TII, MF);
+ ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, false, SS, TII, MF);
// Load from SS to the spare physical register.
TII->loadRegFromStackSlot(MBB, MII, PhysReg, SS, RC);
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/ExecutionEngine.cpp b/libclamav/c++/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
index 5be3aa8..335d4de 100644
--- a/libclamav/c++/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
@@ -269,7 +269,8 @@ static void *CreateArgv(LLVMContext &C, ExecutionEngine *EE,
/// runStaticConstructorsDestructors - This method is used to execute all of
/// the static constructors or destructors for a module, depending on the
/// value of isDtors.
-void ExecutionEngine::runStaticConstructorsDestructors(Module *module, bool isDtors) {
+void ExecutionEngine::runStaticConstructorsDestructors(Module *module,
+ bool isDtors) {
const char *Name = isDtors ? "llvm.global_dtors" : "llvm.global_ctors";
// Execute global ctors/dtors for each module in the program.
@@ -425,30 +426,41 @@ ExecutionEngine *EngineBuilder::create() {
// create, we assume they only want the JIT, and we fail if they only want
// the interpreter.
if (JMM) {
- if (WhichEngine & EngineKind::JIT) {
+ if (WhichEngine & EngineKind::JIT)
WhichEngine = EngineKind::JIT;
- } else {
- *ErrorStr = "Cannot create an interpreter with a memory manager.";
+ else {
+ if (ErrorStr)
+ *ErrorStr = "Cannot create an interpreter with a memory manager.";
+ return 0;
}
}
- ExecutionEngine *EE = 0;
-
// Unless the interpreter was explicitly selected or the JIT is not linked,
// try making a JIT.
- if (WhichEngine & EngineKind::JIT && ExecutionEngine::JITCtor) {
- EE = ExecutionEngine::JITCtor(MP, ErrorStr, JMM, OptLevel,
- AllocateGVsWithCode);
+ if (WhichEngine & EngineKind::JIT) {
+ if (ExecutionEngine::JITCtor) {
+ ExecutionEngine *EE =
+ ExecutionEngine::JITCtor(MP, ErrorStr, JMM, OptLevel,
+ AllocateGVsWithCode);
+ if (EE) return EE;
+ }
}
// If we can't make a JIT and we didn't request one specifically, try making
// an interpreter instead.
- if (WhichEngine & EngineKind::Interpreter && EE == 0 &&
- ExecutionEngine::InterpCtor) {
- EE = ExecutionEngine::InterpCtor(MP, ErrorStr);
+ if (WhichEngine & EngineKind::Interpreter) {
+ if (ExecutionEngine::InterpCtor)
+ return ExecutionEngine::InterpCtor(MP, ErrorStr);
+ if (ErrorStr)
+ *ErrorStr = "Interpreter has not been linked in.";
+ return 0;
}
- return EE;
+ if ((WhichEngine & EngineKind::JIT) && ExecutionEngine::JITCtor == 0) {
+ if (ErrorStr)
+ *ErrorStr = "JIT has not been linked in.";
+ }
+ return 0;
}
/// getPointerToGlobal - This returns the address of the specified global
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp b/libclamav/c++/llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
index 12ca9cd..8c45a36 100644
--- a/libclamav/c++/llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
@@ -203,9 +203,10 @@ static bool ffiInvoke(RawFunc Fn, Function *F,
ArgBytes += TD->getTypeStoreSize(ArgTy);
}
- uint8_t *ArgData = (uint8_t*) alloca(ArgBytes);
- uint8_t *ArgDataPtr = ArgData;
- std::vector<void*> values(NumArgs);
+ SmallVector<uint8_t, 128> ArgData;
+ ArgData.resize(ArgBytes);
+ uint8_t *ArgDataPtr = ArgData.data();
+ SmallVector<void*, 16> values(NumArgs);
for (Function::const_arg_iterator A = F->arg_begin(), E = F->arg_end();
A != E; ++A) {
const unsigned ArgNo = A->getArgNo();
@@ -218,22 +219,22 @@ static bool ffiInvoke(RawFunc Fn, Function *F,
ffi_type *rtype = ffiTypeFor(RetTy);
if (ffi_prep_cif(&cif, FFI_DEFAULT_ABI, NumArgs, rtype, &args[0]) == FFI_OK) {
- void *ret = NULL;
+ SmallVector<uint8_t, 128> ret;
if (RetTy->getTypeID() != Type::VoidTyID)
- ret = alloca(TD->getTypeStoreSize(RetTy));
- ffi_call(&cif, Fn, ret, &values[0]);
+ ret.resize(TD->getTypeStoreSize(RetTy));
+ ffi_call(&cif, Fn, ret.data(), values.data());
switch (RetTy->getTypeID()) {
case Type::IntegerTyID:
switch (cast<IntegerType>(RetTy)->getBitWidth()) {
- case 8: Result.IntVal = APInt(8 , *(int8_t *) ret); break;
- case 16: Result.IntVal = APInt(16, *(int16_t*) ret); break;
- case 32: Result.IntVal = APInt(32, *(int32_t*) ret); break;
- case 64: Result.IntVal = APInt(64, *(int64_t*) ret); break;
+ case 8: Result.IntVal = APInt(8 , *(int8_t *) ret.data()); break;
+ case 16: Result.IntVal = APInt(16, *(int16_t*) ret.data()); break;
+ case 32: Result.IntVal = APInt(32, *(int32_t*) ret.data()); break;
+ case 64: Result.IntVal = APInt(64, *(int64_t*) ret.data()); break;
}
break;
- case Type::FloatTyID: Result.FloatVal = *(float *) ret; break;
- case Type::DoubleTyID: Result.DoubleVal = *(double*) ret; break;
- case Type::PointerTyID: Result.PointerVal = *(void **) ret; break;
+ case Type::FloatTyID: Result.FloatVal = *(float *) ret.data(); break;
+ case Type::DoubleTyID: Result.DoubleVal = *(double*) ret.data(); break;
+ case Type::PointerTyID: Result.PointerVal = *(void **) ret.data(); break;
default: break;
}
return true;
@@ -269,7 +270,7 @@ GenericValue Interpreter::callExternalFunction(Function *F,
} else {
RawFn = RF->second;
}
-
+
FunctionsLock->release();
GenericValue Result;
@@ -334,7 +335,7 @@ GenericValue lle_X_sprintf(const FunctionType *FT,
// printf should return # chars printed. This is completely incorrect, but
// close enough for now.
- GenericValue GV;
+ GenericValue GV;
GV.IntVal = APInt(32, strlen(FmtStr));
while (1) {
switch (*FmtStr) {
@@ -566,4 +567,3 @@ void Interpreter::initializeExternalFunctions() {
FuncNames["lle_X_scanf"] = lle_X_scanf;
FuncNames["lle_X_fprintf"] = lle_X_fprintf;
}
-
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/CMakeLists.txt b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/CMakeLists.txt
index 7f15b4c..41b3b4e 100644
--- a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/CMakeLists.txt
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/CMakeLists.txt
@@ -4,6 +4,7 @@ add_definitions(-DENABLE_X86_JIT)
add_llvm_library(LLVMJIT
Intercept.cpp
JIT.cpp
+ JITDebugRegisterer.cpp
JITDwarfEmitter.cpp
JITEmitter.cpp
JITMemoryManager.cpp
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JIT.cpp b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JIT.cpp
index 3743350..b2a268b 100644
--- a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JIT.cpp
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JIT.cpp
@@ -234,7 +234,7 @@ JIT::JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
jitstate = new JITState(MP);
// Initialize JCE
- JCE = createEmitter(*this, JMM);
+ JCE = createEmitter(*this, JMM, TM);
// Add target data
MutexGuard locked(lock);
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JIT.h b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JIT.h
index e3ab9e2..dfeffb5 100644
--- a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JIT.h
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JIT.h
@@ -185,7 +185,8 @@ public:
void NotifyFreeingMachineCode(const Function &F, void *OldPtr);
private:
- static JITCodeEmitter *createEmitter(JIT &J, JITMemoryManager *JMM);
+ static JITCodeEmitter *createEmitter(JIT &J, JITMemoryManager *JMM,
+ TargetMachine &tm);
void runJITOnFunctionUnlocked(Function *F, const MutexGuard &locked);
void updateFunctionStub(Function *F);
void updateDlsymStubTable();
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp
new file mode 100644
index 0000000..fa64010
--- /dev/null
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp
@@ -0,0 +1,208 @@
+//===-- JITDebugRegisterer.cpp - Register debug symbols for JIT -----------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines a JITDebugRegisterer object that is used by the JIT to
+// register debug info with debuggers like GDB.
+//
+//===----------------------------------------------------------------------===//
+
+#include "JITDebugRegisterer.h"
+#include "../../CodeGen/ELF.h"
+#include "../../CodeGen/ELFWriter.h"
+#include "llvm/LLVMContext.h"
+#include "llvm/Function.h"
+#include "llvm/Module.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/OwningPtr.h"
+#include "llvm/Support/MutexGuard.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/System/Mutex.h"
+#include <string>
+#include <vector>
+
+namespace llvm {
+
+// This must be kept in sync with gdb/gdb/jit.h .
+extern "C" {
+
+ // Debuggers puts a breakpoint in this function.
+ void DISABLE_INLINE __jit_debug_register_code() { }
+
+ // We put information about the JITed function in this global, which the
+ // debugger reads. Make sure to specify the version statically, because the
+ // debugger checks the version before we can set it during runtime.
+ struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 };
+
+}
+
+namespace {
+
+ /// JITDebugLock - Used to serialize all code registration events, since they
+ /// modify global variables.
+ sys::Mutex JITDebugLock;
+
+}
+
+JITDebugRegisterer::JITDebugRegisterer(TargetMachine &tm) : TM(tm), FnMap() { }
+
+JITDebugRegisterer::~JITDebugRegisterer() {
+ // Free all ELF memory.
+ for (RegisteredFunctionsMap::iterator I = FnMap.begin(), E = FnMap.end();
+ I != E; ++I) {
+ // Call the private method that doesn't update the map so our iterator
+ // doesn't break.
+ UnregisterFunctionInternal(I);
+ }
+ FnMap.clear();
+}
+
+std::string JITDebugRegisterer::MakeELF(const Function *F, DebugInfo &I) {
+ // Stack allocate an empty module with an empty LLVMContext for the ELFWriter
+ // API. We don't use the real module because then the ELFWriter would write
+ // out unnecessary GlobalValues during finalization.
+ LLVMContext Context;
+ Module M("", Context);
+
+ // Make a buffer for the ELF in memory.
+ std::string Buffer;
+ raw_string_ostream O(Buffer);
+ ELFWriter EW(O, TM);
+ EW.doInitialization(M);
+
+ // Copy the binary into the .text section. This isn't necessary, but it's
+ // useful to be able to disassemble the ELF by hand.
+ ELFSection &Text = EW.getTextSection((Function *)F);
+ Text.Addr = (uint64_t)I.FnStart;
+ // TODO: We could eliminate this copy if we somehow used a pointer/size pair
+ // instead of a vector.
+ Text.getData().assign(I.FnStart, I.FnEnd);
+
+ // Copy the exception handling call frame information into the .eh_frame
+ // section. This allows GDB to get a good stack trace, particularly on
+ // linux x86_64. Mark this as a PROGBITS section that needs to be loaded
+ // into memory at runtime.
+ ELFSection &EH = EW.getSection(".eh_frame", ELFSection::SHT_PROGBITS,
+ ELFSection::SHF_ALLOC);
+ // Pointers in the DWARF EH info are all relative to the EH frame start,
+ // which is stored here.
+ EH.Addr = (uint64_t)I.EhStart;
+ // TODO: We could eliminate this copy if we somehow used a pointer/size pair
+ // instead of a vector.
+ EH.getData().assign(I.EhStart, I.EhEnd);
+
+ // Add this single function to the symbol table, so the debugger prints the
+ // name instead of '???'. We give the symbol default global visibility.
+ ELFSym *FnSym = ELFSym::getGV(F,
+ ELFSym::STB_GLOBAL,
+ ELFSym::STT_FUNC,
+ ELFSym::STV_DEFAULT);
+ FnSym->SectionIdx = Text.SectionIdx;
+ FnSym->Size = I.FnEnd - I.FnStart;
+ FnSym->Value = 0; // Offset from start of section.
+ EW.SymbolList.push_back(FnSym);
+
+ EW.doFinalization(M);
+ O.flush();
+
+ // When trying to debug why GDB isn't getting the debug info right, it's
+ // awfully helpful to write the object file to disk so that it can be
+ // inspected with readelf and objdump.
+ if (JITEmitDebugInfoToDisk) {
+ std::string Filename;
+ raw_string_ostream O2(Filename);
+ O2 << "/tmp/llvm_function_" << I.FnStart << "_" << F->getNameStr() << ".o";
+ O2.flush();
+ std::string Errors;
+ raw_fd_ostream O3(Filename.c_str(), Errors);
+ O3 << Buffer;
+ O3.close();
+ }
+
+ return Buffer;
+}
+
+void JITDebugRegisterer::RegisterFunction(const Function *F, DebugInfo &I) {
+ // TODO: Support non-ELF platforms.
+ if (!TM.getELFWriterInfo())
+ return;
+
+ std::string Buffer = MakeELF(F, I);
+
+ jit_code_entry *JITCodeEntry = new jit_code_entry();
+ JITCodeEntry->symfile_addr = Buffer.c_str();
+ JITCodeEntry->symfile_size = Buffer.size();
+
+ // Add a mapping from F to the entry and buffer, so we can delete this
+ // info later.
+ FnMap[F] = std::make_pair<std::string, jit_code_entry*>(Buffer, JITCodeEntry);
+
+ // Acquire the lock and do the registration.
+ {
+ MutexGuard locked(JITDebugLock);
+ __jit_debug_descriptor.action_flag = JIT_REGISTER_FN;
+
+ // Insert this entry at the head of the list.
+ JITCodeEntry->prev_entry = NULL;
+ jit_code_entry *NextEntry = __jit_debug_descriptor.first_entry;
+ JITCodeEntry->next_entry = NextEntry;
+ if (NextEntry != NULL) {
+ NextEntry->prev_entry = JITCodeEntry;
+ }
+ __jit_debug_descriptor.first_entry = JITCodeEntry;
+ __jit_debug_descriptor.relevant_entry = JITCodeEntry;
+ __jit_debug_register_code();
+ }
+}
+
+void JITDebugRegisterer::UnregisterFunctionInternal(
+ RegisteredFunctionsMap::iterator I) {
+ jit_code_entry *JITCodeEntry = I->second.second;
+
+ // Acquire the lock and do the unregistration.
+ {
+ MutexGuard locked(JITDebugLock);
+ __jit_debug_descriptor.action_flag = JIT_UNREGISTER_FN;
+
+ // Remove the jit_code_entry from the linked list.
+ jit_code_entry *PrevEntry = JITCodeEntry->prev_entry;
+ jit_code_entry *NextEntry = JITCodeEntry->next_entry;
+ if (NextEntry) {
+ NextEntry->prev_entry = PrevEntry;
+ }
+ if (PrevEntry) {
+ PrevEntry->next_entry = NextEntry;
+ } else {
+ assert(__jit_debug_descriptor.first_entry == JITCodeEntry);
+ __jit_debug_descriptor.first_entry = NextEntry;
+ }
+
+ // Tell GDB which entry we removed, and unregister the code.
+ __jit_debug_descriptor.relevant_entry = JITCodeEntry;
+ __jit_debug_register_code();
+ }
+
+ // Free the ELF file in memory.
+ std::string &Buffer = I->second.first;
+ Buffer.clear();
+}
+
+void JITDebugRegisterer::UnregisterFunction(const Function *F) {
+ // TODO: Support non-ELF platforms.
+ if (!TM.getELFWriterInfo())
+ return;
+
+ RegisteredFunctionsMap::iterator I = FnMap.find(F);
+ if (I == FnMap.end()) return;
+ UnregisterFunctionInternal(I);
+ FnMap.erase(I);
+}
+
+} // end namespace llvm
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.h b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.h
new file mode 100644
index 0000000..dce506b
--- /dev/null
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.h
@@ -0,0 +1,116 @@
+//===-- JITDebugRegisterer.h - Register debug symbols for JIT -------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines a JITDebugRegisterer object that is used by the JIT to
+// register debug info with debuggers like GDB.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_EXECUTION_ENGINE_JIT_DEBUGREGISTERER_H
+#define LLVM_EXECUTION_ENGINE_JIT_DEBUGREGISTERER_H
+
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/Support/DataTypes.h"
+#include <string>
+
+// This must be kept in sync with gdb/gdb/jit.h .
+extern "C" {
+
+ typedef enum {
+ JIT_NOACTION = 0,
+ JIT_REGISTER_FN,
+ JIT_UNREGISTER_FN
+ } jit_actions_t;
+
+ struct jit_code_entry {
+ struct jit_code_entry *next_entry;
+ struct jit_code_entry *prev_entry;
+ const char *symfile_addr;
+ uint64_t symfile_size;
+ };
+
+ struct jit_descriptor {
+ uint32_t version;
+ // This should be jit_actions_t, but we want to be specific about the
+ // bit-width.
+ uint32_t action_flag;
+ struct jit_code_entry *relevant_entry;
+ struct jit_code_entry *first_entry;
+ };
+
+}
+
+namespace llvm {
+
+class ELFSection;
+class Function;
+class TargetMachine;
+
+
+/// This class encapsulates information we want to send to the debugger.
+///
+struct DebugInfo {
+ uint8_t *FnStart;
+ uint8_t *FnEnd;
+ uint8_t *EhStart;
+ uint8_t *EhEnd;
+
+ DebugInfo() : FnStart(0), FnEnd(0), EhStart(0), EhEnd(0) {}
+};
+
+typedef DenseMap< const Function*, std::pair<std::string, jit_code_entry*> >
+ RegisteredFunctionsMap;
+
+/// This class registers debug info for JITed code with an attached debugger.
+/// Without proper debug info, GDB can't do things like source level debugging
+/// or even produce a proper stack trace on linux-x86_64. To use this class,
+/// whenever a function is JITed, create a DebugInfo struct and pass it to the
+/// RegisterFunction method. The method will then do whatever is necessary to
+/// inform the debugger about the JITed function.
+class JITDebugRegisterer {
+
+ TargetMachine &TM;
+
+ /// FnMap - A map of functions that have been registered to the associated
+ /// temporary files. Used for cleanup.
+ RegisteredFunctionsMap FnMap;
+
+ /// MakeELF - Builds the ELF file in memory and returns a std::string that
+ /// contains the ELF.
+ std::string MakeELF(const Function *F, DebugInfo &I);
+
+public:
+ JITDebugRegisterer(TargetMachine &tm);
+
+ /// ~JITDebugRegisterer - Unregisters all code and frees symbol files.
+ ///
+ ~JITDebugRegisterer();
+
+ /// RegisterFunction - Register debug info for the given function with an
+ /// attached debugger. Clients must call UnregisterFunction on all
+ /// registered functions before deleting them to free the associated symbol
+ /// file and unregister it from the debugger.
+ void RegisterFunction(const Function *F, DebugInfo &I);
+
+ /// UnregisterFunction - Unregister the debug info for the given function
+ /// from the debugger and free associated memory.
+ void UnregisterFunction(const Function *F);
+
+private:
+ /// UnregisterFunctionInternal - Unregister the debug info for the given
+ /// function from the debugger and delete any temporary files. The private
+ /// version of this method does not remove the function from FnMap so that it
+ /// can be called while iterating over FnMap.
+ void UnregisterFunctionInternal(RegisteredFunctionsMap::iterator I);
+
+};
+
+} // end namespace llvm
+
+#endif // LLVM_EXECUTION_ENGINE_JIT_DEBUGREGISTERER_H
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
index f7fb983..f2b28ad 100644
--- a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
@@ -28,19 +28,20 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
-
using namespace llvm;
-JITDwarfEmitter::JITDwarfEmitter(JIT& theJit) : Jit(theJit) {}
+JITDwarfEmitter::JITDwarfEmitter(JIT& theJit) : MMI(0), Jit(theJit) {}
unsigned char* JITDwarfEmitter::EmitDwarfTable(MachineFunction& F,
JITCodeEmitter& jce,
unsigned char* StartFunction,
- unsigned char* EndFunction) {
+ unsigned char* EndFunction,
+ unsigned char* &EHFramePtr) {
+ assert(MMI && "MachineModuleInfo not registered!");
+
const TargetMachine& TM = F.getTarget();
TD = TM.getTargetData();
- needsIndirectEncoding = TM.getMCAsmInfo()->getNeedsIndirectEncoding();
stackGrowthDirection = TM.getFrameInfo()->getStackGrowthDirection();
RI = TM.getRegisterInfo();
JCE = &jce;
@@ -49,14 +50,13 @@ unsigned char* JITDwarfEmitter::EmitDwarfTable(MachineFunction& F,
EndFunction);
unsigned char* Result = 0;
- unsigned char* EHFramePtr = 0;
const std::vector<Function *> Personalities = MMI->getPersonalities();
EHFramePtr = EmitCommonEHFrame(Personalities[MMI->getPersonalityIndex()]);
Result = EmitEHFrame(Personalities[MMI->getPersonalityIndex()], EHFramePtr,
StartFunction, EndFunction, ExceptionTable);
-
+
return Result;
}
@@ -107,11 +107,9 @@ JITDwarfEmitter::EmitFrameMoves(intptr_t BaseLabelPtr,
JCE->emitULEB128Bytes(RI->getDwarfRegNum(Src.getReg(), true));
}
- int Offset = -Src.getOffset();
-
- JCE->emitULEB128Bytes(Offset);
+ JCE->emitULEB128Bytes(-Src.getOffset());
} else {
- llvm_unreachable("Machine move no supported yet.");
+ llvm_unreachable("Machine move not supported yet.");
}
} else if (Src.isReg() &&
Src.getReg() == MachineLocation::VirtualFP) {
@@ -119,7 +117,7 @@ JITDwarfEmitter::EmitFrameMoves(intptr_t BaseLabelPtr,
JCE->emitByte(dwarf::DW_CFA_def_cfa_register);
JCE->emitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), true));
} else {
- llvm_unreachable("Machine move no supported yet.");
+ llvm_unreachable("Machine move not supported yet.");
}
} else {
unsigned Reg = RI->getDwarfRegNum(Src.getReg(), true);
@@ -210,6 +208,8 @@ struct CallSiteEntry {
unsigned char* JITDwarfEmitter::EmitExceptionTable(MachineFunction* MF,
unsigned char* StartFunction,
unsigned char* EndFunction) const {
+ assert(MMI && "MachineModuleInfo not registered!");
+
// Map all labels and get rid of any dead landing pads.
MMI->TidyLandingPads();
@@ -466,11 +466,10 @@ unsigned char* JITDwarfEmitter::EmitExceptionTable(MachineFunction* MF,
GlobalVariable *GV = TypeInfos[M - 1];
if (GV) {
- if (TD->getPointerSize() == sizeof(int32_t)) {
+ if (TD->getPointerSize() == sizeof(int32_t))
JCE->emitInt32((intptr_t)Jit.getOrEmitGlobalVariable(GV));
- } else {
+ else
JCE->emitInt64((intptr_t)Jit.getOrEmitGlobalVariable(GV));
- }
} else {
if (TD->getPointerSize() == sizeof(int32_t))
JCE->emitInt32(0);
@@ -508,7 +507,7 @@ JITDwarfEmitter::EmitCommonEHFrame(const Function* Personality) const {
JCE->emitULEB128Bytes(1);
JCE->emitSLEB128Bytes(stackGrowth);
JCE->emitByte(RI->getDwarfRegNum(RI->getRARegister(), true));
-
+
if (Personality) {
// Augmentation Size: 3 small ULEBs of one byte each, and the personality
// function which size is PointerSize.
@@ -524,10 +523,9 @@ JITDwarfEmitter::EmitCommonEHFrame(const Function* Personality) const {
JCE->emitByte(dwarf::DW_EH_PE_sdata8);
JCE->emitInt64(((intptr_t)Jit.getPointerToGlobal(Personality)));
}
-
+
JCE->emitULEB128Bytes(dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4);
JCE->emitULEB128Bytes(dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4);
-
} else {
JCE->emitULEB128Bytes(1);
JCE->emitULEB128Bytes(dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4);
@@ -566,13 +564,19 @@ JITDwarfEmitter::EmitEHFrame(const Function* Personality,
// If there is a personality and landing pads then point to the language
// specific data area in the exception table.
- if (MMI->getPersonalityIndex()) {
- JCE->emitULEB128Bytes(4);
+ if (Personality) {
+ JCE->emitULEB128Bytes(PointerSize == 4 ? 4 : 8);
- if (!MMI->getLandingPads().empty()) {
- JCE->emitInt32(ExceptionTable - (unsigned char*)JCE->getCurrentPCValue());
+ if (PointerSize == 4) {
+ if (!MMI->getLandingPads().empty())
+ JCE->emitInt32(ExceptionTable-(unsigned char*)JCE->getCurrentPCValue());
+ else
+ JCE->emitInt32((int)0);
} else {
- JCE->emitInt32((int)0);
+ if (!MMI->getLandingPads().empty())
+ JCE->emitInt64(ExceptionTable-(unsigned char*)JCE->getCurrentPCValue());
+ else
+ JCE->emitInt64((int)0);
}
} else {
JCE->emitULEB128Bytes(0);
@@ -607,7 +611,6 @@ unsigned JITDwarfEmitter::GetDwarfTableSizeInBytes(MachineFunction& F,
unsigned char* EndFunction) {
const TargetMachine& TM = F.getTarget();
TD = TM.getTargetData();
- needsIndirectEncoding = TM.getMCAsmInfo()->getNeedsIndirectEncoding();
stackGrowthDirection = TM.getFrameInfo()->getStackGrowthDirection();
RI = TM.getRegisterInfo();
JCE = &jce;
@@ -621,7 +624,7 @@ unsigned JITDwarfEmitter::GetDwarfTableSizeInBytes(MachineFunction& F,
FinalSize += GetEHFrameSizeInBytes(Personalities[MMI->getPersonalityIndex()],
StartFunction);
-
+
return FinalSize;
}
@@ -644,7 +647,7 @@ JITDwarfEmitter::GetEHFrameSizeInBytes(const Function* Personality,
FinalSize += 3 * PointerSize;
// If there is a personality and landing pads then point to the language
// specific data area in the exception table.
- if (MMI->getPersonalityIndex()) {
+ if (Personality) {
FinalSize += MCAsmInfo::getULEB128Size(4);
FinalSize += PointerSize;
} else {
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDwarfEmitter.h b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDwarfEmitter.h
index 9120ed4..e627550 100644
--- a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDwarfEmitter.h
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITDwarfEmitter.h
@@ -32,7 +32,6 @@ class JITDwarfEmitter {
const TargetRegisterInfo* RI;
MachineModuleInfo* MMI;
JIT& Jit;
- bool needsIndirectEncoding;
bool stackGrowthDirection;
unsigned char* EmitExceptionTable(MachineFunction* MF,
@@ -68,7 +67,8 @@ public:
unsigned char* EmitDwarfTable(MachineFunction& F,
JITCodeEmitter& JCE,
unsigned char* StartFunction,
- unsigned char* EndFunction);
+ unsigned char* EndFunction,
+ unsigned char* &EHFramePtr);
unsigned GetDwarfTableSizeInBytes(MachineFunction& F,
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp
index e179960..590846b 100644
--- a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp
@@ -14,7 +14,9 @@
#define DEBUG_TYPE "jit"
#include "JIT.h"
+#include "JITDebugRegisterer.h"
#include "JITDwarfEmitter.h"
+#include "llvm/ADT/OwningPtr.h"
#include "llvm/Constants.h"
#include "llvm/Module.h"
#include "llvm/DerivedTypes.h"
@@ -464,9 +466,12 @@ namespace {
/// Resolver - This contains info about the currently resolved functions.
JITResolver Resolver;
-
+
/// DE - The dwarf emitter for the jit.
- JITDwarfEmitter *DE;
+ OwningPtr<JITDwarfEmitter> DE;
+
+ /// DR - The debug registerer for the jit.
+ OwningPtr<JITDebugRegisterer> DR;
/// LabelLocations - This vector is a mapping from Label ID's to their
/// address.
@@ -504,7 +509,7 @@ namespace {
DebugLocTuple PrevDLT;
public:
- JITEmitter(JIT &jit, JITMemoryManager *JMM)
+ JITEmitter(JIT &jit, JITMemoryManager *JMM, TargetMachine &TM)
: SizeEstimate(0), Resolver(jit), MMI(0), CurFn(0) {
MemMgr = JMM ? JMM : JITMemoryManager::CreateDefaultMemManager();
if (jit.getJITInfo().needsGOT()) {
@@ -512,11 +517,15 @@ namespace {
DEBUG(errs() << "JIT is managing a GOT\n");
}
- if (DwarfExceptionHandling) DE = new JITDwarfEmitter(jit);
+ if (DwarfExceptionHandling || JITEmitDebugInfo) {
+ DE.reset(new JITDwarfEmitter(jit));
+ }
+ if (JITEmitDebugInfo) {
+ DR.reset(new JITDebugRegisterer(TM));
+ }
}
~JITEmitter() {
delete MemMgr;
- if (DwarfExceptionHandling) delete DE;
}
/// classof - Methods for support type inquiry through isa, cast, and
@@ -604,7 +613,7 @@ namespace {
virtual void setModuleInfo(MachineModuleInfo* Info) {
MMI = Info;
- if (DwarfExceptionHandling) DE->setModuleInfo(Info);
+ if (DE.get()) DE->setModuleInfo(Info);
}
void setMemoryExecutable() {
@@ -1124,12 +1133,12 @@ bool JITEmitter::finishFunction(MachineFunction &F) {
}
);
- if (DwarfExceptionHandling) {
+ if (DwarfExceptionHandling || JITEmitDebugInfo) {
uintptr_t ActualSize = 0;
SavedBufferBegin = BufferBegin;
SavedBufferEnd = BufferEnd;
SavedCurBufferPtr = CurBufferPtr;
-
+
if (MemMgr->NeedsExactSize()) {
ActualSize = DE->GetDwarfTableSizeInBytes(F, *this, FnStart, FnEnd);
}
@@ -1137,14 +1146,28 @@ bool JITEmitter::finishFunction(MachineFunction &F) {
BufferBegin = CurBufferPtr = MemMgr->startExceptionTable(F.getFunction(),
ActualSize);
BufferEnd = BufferBegin+ActualSize;
- uint8_t* FrameRegister = DE->EmitDwarfTable(F, *this, FnStart, FnEnd);
+ uint8_t *EhStart;
+ uint8_t *FrameRegister = DE->EmitDwarfTable(F, *this, FnStart, FnEnd,
+ EhStart);
MemMgr->endExceptionTable(F.getFunction(), BufferBegin, CurBufferPtr,
FrameRegister);
+ uint8_t *EhEnd = CurBufferPtr;
BufferBegin = SavedBufferBegin;
BufferEnd = SavedBufferEnd;
CurBufferPtr = SavedCurBufferPtr;
- TheJIT->RegisterTable(FrameRegister);
+ if (DwarfExceptionHandling) {
+ TheJIT->RegisterTable(FrameRegister);
+ }
+
+ if (JITEmitDebugInfo) {
+ DebugInfo I;
+ I.FnStart = FnStart;
+ I.FnEnd = FnEnd;
+ I.EhStart = EhStart;
+ I.EhEnd = EhEnd;
+ DR->RegisterFunction(F.getFunction(), I);
+ }
}
if (MMI)
@@ -1168,6 +1191,13 @@ void JITEmitter::retryWithMoreMemory(MachineFunction &F) {
void JITEmitter::deallocateMemForFunction(const Function *F) {
MemMgr->deallocateMemForFunction(F);
+ // TODO: Do we need to unregister exception handling information from libgcc
+ // here?
+
+ if (JITEmitDebugInfo) {
+ DR->UnregisterFunction(F);
+ }
+
// If the function did not reference any stubs, return.
if (CurFnStubUses.find(F) == CurFnStubUses.end())
return;
@@ -1390,8 +1420,9 @@ uintptr_t JITEmitter::getJumpTableEntryAddress(unsigned Index) const {
// Public interface to this file
//===----------------------------------------------------------------------===//
-JITCodeEmitter *JIT::createEmitter(JIT &jit, JITMemoryManager *JMM) {
- return new JITEmitter(jit, JMM);
+JITCodeEmitter *JIT::createEmitter(JIT &jit, JITMemoryManager *JMM,
+ TargetMachine &tm) {
+ return new JITEmitter(jit, JMM, tm);
}
// getPointerToNamedFunction - This function is used as a global wrapper to
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/OProfileJITEventListener.cpp b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/OProfileJITEventListener.cpp
index 740dcfc..69398be 100644
--- a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/OProfileJITEventListener.cpp
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/OProfileJITEventListener.cpp
@@ -72,21 +72,19 @@ class FilenameCache {
// Holds the filename of each CompileUnit, so that we can pass the
// pointer into oprofile. These char*s are freed in the destructor.
DenseMap<MDNode*, char*> Filenames;
- // Used as the scratch space in DICompileUnit::getFilename().
- std::string TempFilename;
public:
- const char* getFilename(MDNode *CompileUnit) {
+ const char *getFilename(MDNode *CompileUnit) {
char *&Filename = Filenames[CompileUnit];
if (Filename == NULL) {
DICompileUnit CU(CompileUnit);
- Filename = strdup(CU.getFilename(TempFilename).c_str());
+ Filename = strdup(CU.getFilename());
}
return Filename;
}
~FilenameCache() {
for (DenseMap<MDNode*, char*>::iterator
- I = Filenames.begin(), E = Filenames.end(); I != E;++I) {
+ I = Filenames.begin(), E = Filenames.end(); I != E; ++I) {
free(I->second);
}
}
@@ -97,7 +95,7 @@ static debug_line_info LineStartToOProfileFormat(
uintptr_t Address, DebugLoc Loc) {
debug_line_info Result;
Result.vma = Address;
- const DebugLocTuple& tuple = MF.getDebugLocTuple(Loc);
+ const DebugLocTuple &tuple = MF.getDebugLocTuple(Loc);
Result.lineno = tuple.Line;
Result.filename = Filenames.getFilename(tuple.CompileUnit);
DEBUG(errs() << "Mapping " << reinterpret_cast<void*>(Result.vma) << " to "
diff --git a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/TargetSelect.cpp b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/TargetSelect.cpp
index c2d5a14..8bed33b 100644
--- a/libclamav/c++/llvm/lib/ExecutionEngine/JIT/TargetSelect.cpp
+++ b/libclamav/c++/llvm/lib/ExecutionEngine/JIT/TargetSelect.cpp
@@ -26,7 +26,8 @@
using namespace llvm;
static cl::opt<std::string>
-MArch("march", cl::desc("Architecture to generate assembly for (see --version)"));
+MArch("march",
+ cl::desc("Architecture to generate assembly for (see --version)"));
static cl::opt<std::string>
MCPU("mcpu",
@@ -43,19 +44,42 @@ MAttrs("mattr",
/// selectTarget - Pick a target either via -march or by guessing the native
/// arch. Add any CPU features specified via -mcpu or -mattr.
TargetMachine *JIT::selectTarget(ModuleProvider *MP, std::string *ErrorStr) {
- Triple TheTriple(sys::getHostTriple());
+ Module &Mod = *MP->getModule();
+
+ Triple TheTriple(Mod.getTargetTriple());
+ if (TheTriple.getTriple().empty())
+ TheTriple.setTriple(sys::getHostTriple());
// Adjust the triple to match what the user requested.
- if (!MArch.empty())
- TheTriple.setArch(Triple::getArchTypeForLLVMName(MArch));
+ const Target *TheTarget = 0;
+ if (!MArch.empty()) {
+ for (TargetRegistry::iterator it = TargetRegistry::begin(),
+ ie = TargetRegistry::end(); it != ie; ++it) {
+ if (MArch == it->getName()) {
+ TheTarget = &*it;
+ break;
+ }
+ }
+
+ if (!TheTarget) {
+ *ErrorStr = "No available targets are compatible with this -march, "
+ "see -version for the available targets.\n";
+ return 0;
+ }
- std::string Error;
- const Target *TheTarget =
- TargetRegistry::lookupTarget(TheTriple.getTriple(), Error);
- if (TheTarget == 0) {
- if (ErrorStr)
- *ErrorStr = Error;
- return 0;
+ // Adjust the triple to match (if known), otherwise stick with the
+ // module/host triple.
+ Triple::ArchType Type = Triple::getArchTypeForLLVMName(MArch);
+ if (Type != Triple::UnknownArch)
+ TheTriple.setArch(Type);
+ } else {
+ std::string Error;
+ TheTarget = TargetRegistry::lookupTarget(TheTriple.getTriple(), Error);
+ if (TheTarget == 0) {
+ if (ErrorStr)
+ *ErrorStr = Error;
+ return 0;
+ }
}
if (!TheTarget->hasJIT()) {
diff --git a/libclamav/c++/llvm/lib/MC/CMakeLists.txt b/libclamav/c++/llvm/lib/MC/CMakeLists.txt
index 4fc9993..8a1a058 100644
--- a/libclamav/c++/llvm/lib/MC/CMakeLists.txt
+++ b/libclamav/c++/llvm/lib/MC/CMakeLists.txt
@@ -8,8 +8,10 @@ add_llvm_library(LLVMMC
MCAssembler.cpp
MCCodeEmitter.cpp
MCContext.cpp
+ MCDisassembler.cpp
MCExpr.cpp
MCInst.cpp
+ MCInstPrinter.cpp
MCMachOStreamer.cpp
MCNullStreamer.cpp
MCSection.cpp
diff --git a/libclamav/c++/llvm/lib/MC/MCAsmInfo.cpp b/libclamav/c++/llvm/lib/MC/MCAsmInfo.cpp
index 6562560..74fb930 100644
--- a/libclamav/c++/llvm/lib/MC/MCAsmInfo.cpp
+++ b/libclamav/c++/llvm/lib/MC/MCAsmInfo.cpp
@@ -30,18 +30,11 @@ MCAsmInfo::MCAsmInfo() {
GlobalPrefix = "";
PrivateGlobalPrefix = ".";
LinkerPrivateGlobalPrefix = "";
- JumpTableSpecialLabelPrefix = 0;
- GlobalVarAddrPrefix = "";
- GlobalVarAddrSuffix = "";
- FunctionAddrPrefix = "";
- FunctionAddrSuffix = "";
- PersonalityPrefix = "";
- PersonalitySuffix = "";
- NeedsIndirectEncoding = false;
InlineAsmStart = "APP";
InlineAsmEnd = "NO_APP";
AssemblerDialect = 0;
AllowQuotesInName = false;
+ AllowNameToStartWithDigit = false;
ZeroDirective = "\t.zero\t";
ZeroDirectiveSuffix = 0;
AsciiDirective = "\t.ascii\t";
diff --git a/libclamav/c++/llvm/lib/MC/MCAsmInfoDarwin.cpp b/libclamav/c++/llvm/lib/MC/MCAsmInfoDarwin.cpp
index 38b9e5b..d99120d 100644
--- a/libclamav/c++/llvm/lib/MC/MCAsmInfoDarwin.cpp
+++ b/libclamav/c++/llvm/lib/MC/MCAsmInfoDarwin.cpp
@@ -20,9 +20,8 @@ MCAsmInfoDarwin::MCAsmInfoDarwin() {
// Syntax:
GlobalPrefix = "_";
PrivateGlobalPrefix = "L";
- LinkerPrivateGlobalPrefix = "l"; // Marker for some ObjC metadata
+ LinkerPrivateGlobalPrefix = "l";
NeedsSet = true;
- NeedsIndirectEncoding = true;
AllowQuotesInName = true;
HasSingleParameterDotFile = false;
@@ -30,11 +29,6 @@ MCAsmInfoDarwin::MCAsmInfoDarwin() {
InlineAsmStart = " InlineAsm Start";
InlineAsmEnd = " InlineAsm End";
- // In non-PIC modes, emit a special label before jump tables so that the
- // linker can perform more accurate dead code stripping. We do not check the
- // relocation model here since it can be overridden later.
- JumpTableSpecialLabelPrefix = "l";
-
// Directives:
WeakDefDirective = "\t.weak_definition ";
WeakRefDirective = "\t.weak_reference ";
@@ -54,6 +48,5 @@ MCAsmInfoDarwin::MCAsmInfoDarwin() {
Is_EHSymbolPrivate = false;
GlobalEHDirective = "\t.globl\t";
SupportsWeakOmittedEHFrame = false;
-
}
diff --git a/libclamav/c++/llvm/lib/MC/MCAsmStreamer.cpp b/libclamav/c++/llvm/lib/MC/MCAsmStreamer.cpp
index d976028..e56e968 100644
--- a/libclamav/c++/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/libclamav/c++/llvm/lib/MC/MCAsmStreamer.cpp
@@ -9,12 +9,12 @@
#include "llvm/MC/MCStreamer.h"
#include "llvm/ADT/SmallString.h"
-#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/ErrorHandling.h"
@@ -28,12 +28,12 @@ namespace {
class MCAsmStreamer : public MCStreamer {
raw_ostream &OS;
const MCAsmInfo &MAI;
- AsmPrinter *Printer;
+ MCInstPrinter *InstPrinter;
MCCodeEmitter *Emitter;
public:
MCAsmStreamer(MCContext &Context, raw_ostream &_OS, const MCAsmInfo &tai,
- AsmPrinter *_Printer, MCCodeEmitter *_Emitter)
- : MCStreamer(Context), OS(_OS), MAI(tai), Printer(_Printer),
+ MCInstPrinter *_Printer, MCCodeEmitter *_Emitter)
+ : MCStreamer(Context), OS(_OS), MAI(tai), InstPrinter(_Printer),
Emitter(_Emitter) {}
~MCAsmStreamer() {}
@@ -78,18 +78,6 @@ public:
} // end anonymous namespace.
-/// Allow printing symbols directly to a raw_ostream with proper quoting.
-static inline raw_ostream &operator<<(raw_ostream &os, const MCSymbol *S) {
- S->print(os);
- return os;
-}
-
-/// Allow printing values directly to a raw_ostream.
-static inline raw_ostream &operator<<(raw_ostream &os, const MCExpr &Value) {
- Value.print(os);
- return os;
-}
-
static inline int64_t truncateToSize(int64_t Value, unsigned Bytes) {
assert(Bytes && "Invalid size!");
return Value & ((uint64_t) (int64_t) -1 >> (64 - Bytes * 8));
@@ -113,7 +101,8 @@ void MCAsmStreamer::EmitLabel(MCSymbol *Symbol) {
assert(Symbol->isUndefined() && "Cannot define a symbol twice!");
assert(CurSection && "Cannot emit before setting section!");
- OS << Symbol << ":\n";
+ Symbol->print(OS, &MAI);
+ OS << ":\n";
Symbol->setSection(*CurSection);
}
@@ -130,7 +119,10 @@ void MCAsmStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) {
assert((Symbol->isUndefined() || Symbol->isAbsolute()) &&
"Cannot define a symbol twice!");
- OS << Symbol << " = " << *Value << '\n';
+ Symbol->print(OS, &MAI);
+ OS << " = ";
+ Value->print(OS, &MAI);
+ OS << '\n';
}
void MCAsmStreamer::EmitSymbolAttribute(MCSymbol *Symbol,
@@ -150,17 +142,22 @@ void MCAsmStreamer::EmitSymbolAttribute(MCSymbol *Symbol,
case WeakReference: OS << ".weak_reference"; break;
}
- OS << ' ' << Symbol << '\n';
+ OS << ' ';
+ Symbol->print(OS, &MAI);
+ OS << '\n';
}
void MCAsmStreamer::EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue) {
- OS << ".desc" << ' ' << Symbol << ',' << DescValue << '\n';
+ OS << ".desc" << ' ';
+ Symbol->print(OS, &MAI);
+ OS << ',' << DescValue << '\n';
}
void MCAsmStreamer::EmitCommonSymbol(MCSymbol *Symbol, unsigned Size,
unsigned ByteAlignment) {
- OS << ".comm";
- OS << ' ' << Symbol << ',' << Size;
+ OS << ".comm ";
+ Symbol->print(OS, &MAI);
+ OS << ',' << Size;
if (ByteAlignment != 0)
OS << ',' << Log2_32(ByteAlignment);
OS << '\n';
@@ -176,7 +173,9 @@ void MCAsmStreamer::EmitZerofill(const MCSection *Section, MCSymbol *Symbol,
OS << MOSection->getSegmentName() << "," << MOSection->getSectionName();
if (Symbol != NULL) {
- OS << ',' << Symbol << ',' << Size;
+ OS << ',';
+ Symbol->print(OS, &MAI);
+ OS << ',' << Size;
if (ByteAlignment != 0)
OS << ',' << Log2_32(ByteAlignment);
}
@@ -201,7 +200,9 @@ void MCAsmStreamer::EmitValue(const MCExpr *Value, unsigned Size) {
case 8: OS << ".quad"; break;
}
- OS << ' ' << *truncateToSize(Value, Size) << '\n';
+ OS << ' ';
+ truncateToSize(Value, Size)->print(OS, &MAI);
+ OS << '\n';
}
void MCAsmStreamer::EmitValueToAlignment(unsigned ByteAlignment, int64_t Value,
@@ -225,7 +226,8 @@ void MCAsmStreamer::EmitValueToAlignment(unsigned ByteAlignment, int64_t Value,
OS << Log2_32(ByteAlignment);
if (Value || MaxBytesToEmit) {
- OS << ", " << truncateToSize(Value, ValueSize);
+ OS << ", 0x";
+ OS.write_hex(truncateToSize(Value, ValueSize));
if (MaxBytesToEmit)
OS << ", " << MaxBytesToEmit;
@@ -254,15 +256,18 @@ void MCAsmStreamer::EmitValueToAlignment(unsigned ByteAlignment, int64_t Value,
void MCAsmStreamer::EmitValueToOffset(const MCExpr *Offset,
unsigned char Value) {
// FIXME: Verify that Offset is associated with the current section.
- OS << ".org " << *Offset << ", " << (unsigned) Value << '\n';
+ OS << ".org ";
+ Offset->print(OS, &MAI);
+ OS << ", " << (unsigned) Value << '\n';
}
void MCAsmStreamer::EmitInstruction(const MCInst &Inst) {
assert(CurSection && "Cannot emit contents before setting section!");
// If we have an AsmPrinter, use that to print.
- if (Printer) {
- Printer->printMCInst(&Inst);
+ if (InstPrinter) {
+ InstPrinter->printInst(&Inst);
+ OS << '\n';
// Show the encoding if we have a code emitter.
if (Emitter) {
@@ -286,7 +291,7 @@ void MCAsmStreamer::EmitInstruction(const MCInst &Inst) {
// Otherwise fall back to a structural printing for now. Eventually we should
// always have access to the target specific printer.
- Inst.print(OS);
+ Inst.print(OS, &MAI);
OS << '\n';
}
@@ -295,7 +300,7 @@ void MCAsmStreamer::Finish() {
}
MCStreamer *llvm::createAsmStreamer(MCContext &Context, raw_ostream &OS,
- const MCAsmInfo &MAI, AsmPrinter *AP,
+ const MCAsmInfo &MAI, MCInstPrinter *IP,
MCCodeEmitter *CE) {
- return new MCAsmStreamer(Context, OS, MAI, AP, CE);
+ return new MCAsmStreamer(Context, OS, MAI, IP, CE);
}
diff --git a/libclamav/c++/llvm/lib/MC/MCAssembler.cpp b/libclamav/c++/llvm/lib/MC/MCAssembler.cpp
index 21246cc..0afdf98 100644
--- a/libclamav/c++/llvm/lib/MC/MCAssembler.cpp
+++ b/libclamav/c++/llvm/lib/MC/MCAssembler.cpp
@@ -926,11 +926,11 @@ MCSectionData::LookupFixup(const MCFragment *Fragment, uint64_t Offset) const {
/* *** */
-MCSymbolData::MCSymbolData() : Symbol(*(const MCSymbol*)0) {}
+MCSymbolData::MCSymbolData() : Symbol(0) {}
MCSymbolData::MCSymbolData(const MCSymbol &_Symbol, MCFragment *_Fragment,
uint64_t _Offset, MCAssembler *A)
- : Symbol(_Symbol), Fragment(_Fragment), Offset(_Offset),
+ : Symbol(&_Symbol), Fragment(_Fragment), Offset(_Offset),
IsExternal(false), IsPrivateExtern(false),
CommonSize(0), CommonAlign(0), Flags(0), Index(0)
{
diff --git a/libclamav/c++/llvm/lib/MC/MCDisassembler.cpp b/libclamav/c++/llvm/lib/MC/MCDisassembler.cpp
new file mode 100644
index 0000000..0985602
--- /dev/null
+++ b/libclamav/c++/llvm/lib/MC/MCDisassembler.cpp
@@ -0,0 +1,14 @@
+//===-- lib/MC/MCDisassembler.cpp - Disassembler interface ------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MC/MCDisassembler.h"
+using namespace llvm;
+
+MCDisassembler::~MCDisassembler() {
+}
\ No newline at end of file
diff --git a/libclamav/c++/llvm/lib/MC/MCExpr.cpp b/libclamav/c++/llvm/lib/MC/MCExpr.cpp
index bc42415..0f3e053 100644
--- a/libclamav/c++/llvm/lib/MC/MCExpr.cpp
+++ b/libclamav/c++/llvm/lib/MC/MCExpr.cpp
@@ -14,15 +14,26 @@
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
-void MCExpr::print(raw_ostream &OS) const {
+void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI) const {
switch (getKind()) {
case MCExpr::Constant:
OS << cast<MCConstantExpr>(*this).getValue();
return;
- case MCExpr::SymbolRef:
- cast<MCSymbolRefExpr>(*this).getSymbol().print(OS);
+ case MCExpr::SymbolRef: {
+ const MCSymbol &Sym = cast<MCSymbolRefExpr>(*this).getSymbol();
+
+ // Parenthesize names that start with $ so that they don't look like
+ // absolute names.
+ if (Sym.getName()[0] == '$') {
+ OS << '(';
+ Sym.print(OS, MAI);
+ OS << ')';
+ } else {
+ Sym.print(OS, MAI);
+ }
return;
+ }
case MCExpr::Unary: {
const MCUnaryExpr &UE = cast<MCUnaryExpr>(*this);
@@ -33,18 +44,35 @@ void MCExpr::print(raw_ostream &OS) const {
case MCUnaryExpr::Not: OS << '~'; break;
case MCUnaryExpr::Plus: OS << '+'; break;
}
- UE.getSubExpr()->print(OS);
+ UE.getSubExpr()->print(OS, MAI);
return;
}
case MCExpr::Binary: {
const MCBinaryExpr &BE = cast<MCBinaryExpr>(*this);
- OS << '(';
- BE.getLHS()->print(OS);
- OS << ' ';
+
+ // Only print parens around the LHS if it is non-trivial.
+ if (isa<MCConstantExpr>(BE.getLHS()) || isa<MCSymbolRefExpr>(BE.getLHS())) {
+ BE.getLHS()->print(OS, MAI);
+ } else {
+ OS << '(';
+ BE.getLHS()->print(OS, MAI);
+ OS << ')';
+ }
+
switch (BE.getOpcode()) {
default: assert(0 && "Invalid opcode!");
- case MCBinaryExpr::Add: OS << '+'; break;
+ case MCBinaryExpr::Add:
+ // Print "X-42" instead of "X+-42".
+ if (const MCConstantExpr *RHSC = dyn_cast<MCConstantExpr>(BE.getRHS())) {
+ if (RHSC->getValue() < 0) {
+ OS << RHSC->getValue();
+ return;
+ }
+ }
+
+ OS << '+';
+ break;
case MCBinaryExpr::And: OS << '&'; break;
case MCBinaryExpr::Div: OS << '/'; break;
case MCBinaryExpr::EQ: OS << "=="; break;
@@ -63,9 +91,15 @@ void MCExpr::print(raw_ostream &OS) const {
case MCBinaryExpr::Sub: OS << '-'; break;
case MCBinaryExpr::Xor: OS << '^'; break;
}
- OS << ' ';
- BE.getRHS()->print(OS);
- OS << ')';
+
+ // Only print parens around the LHS if it is non-trivial.
+ if (isa<MCConstantExpr>(BE.getRHS()) || isa<MCSymbolRefExpr>(BE.getRHS())) {
+ BE.getRHS()->print(OS, MAI);
+ } else {
+ OS << '(';
+ BE.getRHS()->print(OS, MAI);
+ OS << ')';
+ }
return;
}
}
@@ -74,22 +108,19 @@ void MCExpr::print(raw_ostream &OS) const {
}
void MCExpr::dump() const {
- print(errs());
+ print(errs(), 0);
errs() << '\n';
}
/* *** */
-const MCBinaryExpr * MCBinaryExpr::Create(Opcode Opc,
- const MCExpr *LHS,
- const MCExpr *RHS,
- MCContext &Ctx) {
+const MCBinaryExpr *MCBinaryExpr::Create(Opcode Opc, const MCExpr *LHS,
+ const MCExpr *RHS, MCContext &Ctx) {
return new (Ctx) MCBinaryExpr(Opc, LHS, RHS);
}
-const MCUnaryExpr * MCUnaryExpr::Create(Opcode Opc,
- const MCExpr *Expr,
- MCContext &Ctx) {
+const MCUnaryExpr *MCUnaryExpr::Create(Opcode Opc, const MCExpr *Expr,
+ MCContext &Ctx) {
return new (Ctx) MCUnaryExpr(Opc, Expr);
}
@@ -102,6 +133,12 @@ const MCSymbolRefExpr *MCSymbolRefExpr::Create(const MCSymbol *Sym,
return new (Ctx) MCSymbolRefExpr(Sym);
}
+const MCSymbolRefExpr *MCSymbolRefExpr::Create(const StringRef &Name,
+ MCContext &Ctx) {
+ return Create(Ctx.GetOrCreateSymbol(Name), Ctx);
+}
+
+
/* *** */
bool MCExpr::EvaluateAsAbsolute(MCContext &Ctx, int64_t &Res) const {
diff --git a/libclamav/c++/llvm/lib/MC/MCInst.cpp b/libclamav/c++/llvm/lib/MC/MCInst.cpp
index ec06146..d050318 100644
--- a/libclamav/c++/llvm/lib/MC/MCInst.cpp
+++ b/libclamav/c++/llvm/lib/MC/MCInst.cpp
@@ -13,7 +13,7 @@
using namespace llvm;
-void MCOperand::print(raw_ostream &OS) const {
+void MCOperand::print(raw_ostream &OS, const MCAsmInfo *MAI) const {
OS << "<MCOperand ";
if (!isValid())
OS << "INVALID";
@@ -21,12 +21,9 @@ void MCOperand::print(raw_ostream &OS) const {
OS << "Reg:" << getReg();
else if (isImm())
OS << "Imm:" << getImm();
- else if (isMBBLabel())
- OS << "MBB:(" << getMBBLabelFunction() << ","
- << getMBBLabelBlock() << ")";
else if (isExpr()) {
OS << "Expr:(";
- getExpr()->print(OS);
+ getExpr()->print(OS, MAI);
OS << ")";
} else
OS << "UNDEFINED";
@@ -34,20 +31,20 @@ void MCOperand::print(raw_ostream &OS) const {
}
void MCOperand::dump() const {
- print(errs());
+ print(errs(), 0);
errs() << "\n";
}
-void MCInst::print(raw_ostream &OS) const {
+void MCInst::print(raw_ostream &OS, const MCAsmInfo *MAI) const {
OS << "<MCInst " << getOpcode();
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
OS << " ";
- getOperand(i).print(OS);
+ getOperand(i).print(OS, MAI);
}
OS << ">";
}
void MCInst::dump() const {
- print(errs());
+ print(errs(), 0);
errs() << "\n";
}
diff --git a/libclamav/c++/llvm/lib/MC/MCInstPrinter.cpp b/libclamav/c++/llvm/lib/MC/MCInstPrinter.cpp
new file mode 100644
index 0000000..6c33216
--- /dev/null
+++ b/libclamav/c++/llvm/lib/MC/MCInstPrinter.cpp
@@ -0,0 +1,14 @@
+//===-- MCInstPrinter.cpp - Convert an MCInst to target assembly syntax ---===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MC/MCInstPrinter.h"
+using namespace llvm;
+
+MCInstPrinter::~MCInstPrinter() {
+}
\ No newline at end of file
diff --git a/libclamav/c++/llvm/lib/MC/MCSectionMachO.cpp b/libclamav/c++/llvm/lib/MC/MCSectionMachO.cpp
index 32d908f..33f5087 100644
--- a/libclamav/c++/llvm/lib/MC/MCSectionMachO.cpp
+++ b/libclamav/c++/llvm/lib/MC/MCSectionMachO.cpp
@@ -260,18 +260,8 @@ std::string MCSectionMachO::ParseSectionSpecifier(StringRef Spec, // In.
StringRef StubSizeStr = Comma.second;
StripSpaces(StubSizeStr);
- // Convert the a null terminated buffer for strtoul.
- char TmpBuffer[32];
- if (StubSizeStr.size() >= 32)
- return"mach-o section specifier has a stub size specifier that is too long";
-
- memcpy(TmpBuffer, StubSizeStr.data(), StubSizeStr.size());
- TmpBuffer[StubSizeStr.size()] = 0;
-
- char *EndPtr;
- StubSize = strtoul(TmpBuffer, &EndPtr, 0);
-
- if (EndPtr[0] != 0)
+ // Convert the stub size from a string to an integer.
+ if (StubSizeStr.getAsInteger(0, StubSize))
return "mach-o section specifier has a malformed stub size";
return "";
diff --git a/libclamav/c++/llvm/lib/MC/MCSymbol.cpp b/libclamav/c++/llvm/lib/MC/MCSymbol.cpp
index 3c9894b..86ff3f3 100644
--- a/libclamav/c++/llvm/lib/MC/MCSymbol.cpp
+++ b/libclamav/c++/llvm/lib/MC/MCSymbol.cpp
@@ -8,46 +8,103 @@
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/raw_ostream.h"
-
using namespace llvm;
// Sentinel value for the absolute pseudo section.
const MCSection *MCSymbol::AbsolutePseudoSection =
reinterpret_cast<const MCSection *>(1);
-/// NeedsQuoting - Return true if the string \arg Str needs quoting, i.e., it
-/// does not match [a-zA-Z_.][a-zA-Z0-9_.]*.
-//
-// FIXME: This could be more permissive, do we care?
-static inline bool NeedsQuoting(const StringRef &Str) {
- if (Str.empty())
- return true;
+static bool isAcceptableChar(char C) {
+ if ((C < 'a' || C > 'z') &&
+ (C < 'A' || C > 'Z') &&
+ (C < '0' || C > '9') &&
+ C != '_' && C != '$' && C != '.' && C != '@')
+ return false;
+ return true;
+}
- // Check that first character is in [a-zA-Z_.].
- if (!((Str[0] >= 'a' && Str[0] <= 'z') ||
- (Str[0] >= 'A' && Str[0] <= 'Z') ||
- (Str[0] == '_' || Str[0] == '.')))
+static char HexDigit(int V) {
+ return V < 10 ? V+'0' : V+'A'-10;
+}
+
+static void MangleLetter(raw_ostream &OS, unsigned char C) {
+ OS << '_' << HexDigit(C >> 4) << HexDigit(C & 15) << '_';
+}
+
+/// NameNeedsEscaping - Return true if the identifier \arg Str needs quotes
+/// for this assembler.
+static bool NameNeedsEscaping(const StringRef &Str, const MCAsmInfo &MAI) {
+ assert(!Str.empty() && "Cannot create an empty MCSymbol");
+
+ // If the first character is a number and the target does not allow this, we
+ // need quotes.
+ if (!MAI.doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9')
return true;
- // Check subsequent characters are in [a-zA-Z0-9_.].
- for (unsigned i = 1, e = Str.size(); i != e; ++i)
- if (!((Str[i] >= 'a' && Str[i] <= 'z') ||
- (Str[i] >= 'A' && Str[i] <= 'Z') ||
- (Str[i] >= '0' && Str[i] <= '9') ||
- (Str[i] == '_' || Str[i] == '.')))
+ // If any of the characters in the string is an unacceptable character, force
+ // quotes.
+ for (unsigned i = 0, e = Str.size(); i != e; ++i)
+ if (!isAcceptableChar(Str[i]))
return true;
-
return false;
}
-void MCSymbol::print(raw_ostream &OS) const {
- if (NeedsQuoting(getName()))
- OS << '"' << getName() << '"';
- else
+static void PrintMangledName(raw_ostream &OS, StringRef Str,
+ const MCAsmInfo &MAI) {
+ // The first character is not allowed to be a number unless the target
+ // explicitly allows it.
+ if (!MAI.doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9') {
+ MangleLetter(OS, Str[0]);
+ Str = Str.substr(1);
+ }
+
+ for (unsigned i = 0, e = Str.size(); i != e; ++i) {
+ if (!isAcceptableChar(Str[i]))
+ MangleLetter(OS, Str[i]);
+ else
+ OS << Str[i];
+ }
+}
+
+/// PrintMangledQuotedName - On systems that support quoted symbols, we still
+/// have to escape some (obscure) characters like " and \n which would break the
+/// assembler's lexing.
+static void PrintMangledQuotedName(raw_ostream &OS, StringRef Str) {
+ OS << '"';
+
+ for (unsigned i = 0, e = Str.size(); i != e; ++i) {
+ if (Str[i] == '"')
+ OS << "_QQ_";
+ else if (Str[i] == '\n')
+ OS << "_NL_";
+ else
+ OS << Str[i];
+ }
+ OS << '"';
+}
+
+
+void MCSymbol::print(raw_ostream &OS, const MCAsmInfo *MAI) const {
+ if (MAI == 0 || !NameNeedsEscaping(getName(), *MAI)) {
OS << getName();
+ return;
+ }
+
+ // On systems that do not allow quoted names, print with mangling.
+ if (!MAI->doesAllowQuotesInName())
+ return PrintMangledName(OS, getName(), *MAI);
+
+ // If the string contains a double quote or newline, we still have to mangle
+ // it.
+ if (getName().find('"') != std::string::npos ||
+ getName().find('\n') != std::string::npos)
+ return PrintMangledQuotedName(OS, getName());
+
+ OS << '"' << getName() << '"';
}
void MCSymbol::dump() const {
- print(errs());
+ print(errs(), 0);
}
diff --git a/libclamav/c++/llvm/lib/MC/MCValue.cpp b/libclamav/c++/llvm/lib/MC/MCValue.cpp
index c7923da..69bd10c 100644
--- a/libclamav/c++/llvm/lib/MC/MCValue.cpp
+++ b/libclamav/c++/llvm/lib/MC/MCValue.cpp
@@ -12,17 +12,17 @@
using namespace llvm;
-void MCValue::print(raw_ostream &OS) const {
+void MCValue::print(raw_ostream &OS, const MCAsmInfo *MAI) const {
if (isAbsolute()) {
OS << getConstant();
return;
}
- getSymA()->print(OS);
+ getSymA()->print(OS, MAI);
if (getSymB()) {
OS << " - ";
- getSymB()->print(OS);
+ getSymB()->print(OS, MAI);
}
if (getConstant())
@@ -30,5 +30,5 @@ void MCValue::print(raw_ostream &OS) const {
}
void MCValue::dump() const {
- print(errs());
+ print(errs(), 0);
}
diff --git a/libclamav/c++/llvm/lib/Support/APFloat.cpp b/libclamav/c++/llvm/lib/Support/APFloat.cpp
index d50e4e5..e431d27 100644
--- a/libclamav/c++/llvm/lib/Support/APFloat.cpp
+++ b/libclamav/c++/llvm/lib/Support/APFloat.cpp
@@ -692,6 +692,14 @@ APFloat::APFloat(const fltSemantics &ourSemantics, integerPart value)
normalize(rmNearestTiesToEven, lfExactlyZero);
}
+APFloat::APFloat(const fltSemantics &ourSemantics) {
+ assertArithmeticOK(ourSemantics);
+ initialize(&ourSemantics);
+ category = fcZero;
+ sign = false;
+}
+
+
APFloat::APFloat(const fltSemantics &ourSemantics,
fltCategory ourCategory, bool negative, unsigned type)
{
@@ -2831,7 +2839,8 @@ APFloat::bitcastToAPInt() const
float
APFloat::convertToFloat() const
{
- assert(semantics == (const llvm::fltSemantics*)&IEEEsingle && "Float semantics are not IEEEsingle");
+ assert(semantics == (const llvm::fltSemantics*)&IEEEsingle &&
+ "Float semantics are not IEEEsingle");
APInt api = bitcastToAPInt();
return api.bitsToFloat();
}
@@ -2839,7 +2848,8 @@ APFloat::convertToFloat() const
double
APFloat::convertToDouble() const
{
- assert(semantics == (const llvm::fltSemantics*)&IEEEdouble && "Float semantics are not IEEEdouble");
+ assert(semantics == (const llvm::fltSemantics*)&IEEEdouble &&
+ "Float semantics are not IEEEdouble");
APInt api = bitcastToAPInt();
return api.bitsToDouble();
}
diff --git a/libclamav/c++/llvm/lib/Support/APInt.cpp b/libclamav/c++/llvm/lib/Support/APInt.cpp
index 5f744e7..56d4773 100644
--- a/libclamav/c++/llvm/lib/Support/APInt.cpp
+++ b/libclamav/c++/llvm/lib/Support/APInt.cpp
@@ -1481,9 +1481,7 @@ APInt::ms APInt::magic() const {
const APInt& d = *this;
unsigned p;
APInt ad, anc, delta, q1, r1, q2, r2, t;
- APInt allOnes = APInt::getAllOnesValue(d.getBitWidth());
APInt signedMin = APInt::getSignedMinValue(d.getBitWidth());
- APInt signedMax = APInt::getSignedMaxValue(d.getBitWidth());
struct ms mag;
ad = d.abs();
@@ -2056,7 +2054,7 @@ void APInt::fromString(unsigned numbits, const StringRef& str, uint8_t radix) {
assert(((slen-1)*3 <= numbits || radix != 8) && "Insufficient bit width");
assert(((slen-1)*4 <= numbits || radix != 16) && "Insufficient bit width");
assert((((slen-1)*64)/22 <= numbits || radix != 10)
- && "Insufficient bit width");
+ && "Insufficient bit width");
// Allocate memory
if (!isSingleWord())
diff --git a/libclamav/c++/llvm/lib/Support/Allocator.cpp b/libclamav/c++/llvm/lib/Support/Allocator.cpp
index 36da443..7a3fd87 100644
--- a/libclamav/c++/llvm/lib/Support/Allocator.cpp
+++ b/libclamav/c++/llvm/lib/Support/Allocator.cpp
@@ -15,6 +15,7 @@
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/Recycler.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/System/Memory.h"
#include <cstring>
namespace llvm {
@@ -60,6 +61,7 @@ void BumpPtrAllocator::DeallocateSlabs(MemSlab *Slab) {
#ifndef NDEBUG
// Poison the memory so stale pointers crash sooner. Note we must
// preserve the Size and NextPtr fields at the beginning.
+ sys::Memory::setRangeWritable(Slab + 1, Slab->Size - sizeof(MemSlab));
memset(Slab + 1, 0xCD, Slab->Size - sizeof(MemSlab));
#endif
Allocator.Deallocate(Slab);
diff --git a/libclamav/c++/llvm/lib/Support/CMakeLists.txt b/libclamav/c++/llvm/lib/Support/CMakeLists.txt
index 0144b28..cd355ff 100644
--- a/libclamav/c++/llvm/lib/Support/CMakeLists.txt
+++ b/libclamav/c++/llvm/lib/Support/CMakeLists.txt
@@ -16,8 +16,10 @@ add_llvm_library(LLVMSupport
IsNAN.cpp
ManagedStatic.cpp
MemoryBuffer.cpp
+ MemoryObject.cpp
PluginLoader.cpp
PrettyStackTrace.cpp
+ Regex.cpp
SlowOperationInformer.cpp
SmallPtrSet.cpp
SourceMgr.cpp
@@ -25,6 +27,7 @@ add_llvm_library(LLVMSupport
StringExtras.cpp
StringMap.cpp
StringPool.cpp
+ StringRef.cpp
SystemUtils.cpp
TargetRegistry.cpp
Timer.cpp
@@ -32,7 +35,6 @@ add_llvm_library(LLVMSupport
Twine.cpp
raw_os_ostream.cpp
raw_ostream.cpp
- Regex.cpp
regcomp.c
regerror.c
regexec.c
diff --git a/libclamav/c++/llvm/lib/Support/CommandLine.cpp b/libclamav/c++/llvm/lib/Support/CommandLine.cpp
index d45694b..187024f 100644
--- a/libclamav/c++/llvm/lib/Support/CommandLine.cpp
+++ b/libclamav/c++/llvm/lib/Support/CommandLine.cpp
@@ -22,11 +22,14 @@
#include "llvm/Support/ManagedStatic.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegistry.h"
+#include "llvm/System/Host.h"
#include "llvm/System/Path.h"
#include "llvm/ADT/OwningPtr.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/Twine.h"
#include "llvm/Config/config.h"
-#include <map>
-#include <set>
#include <cerrno>
#include <cstdlib>
using namespace llvm;
@@ -102,10 +105,10 @@ void Option::addArgument() {
/// GetOptionInfo - Scan the list of registered options, turning them into data
/// structures that are easier to handle.
-static void GetOptionInfo(std::vector<Option*> &PositionalOpts,
- std::vector<Option*> &SinkOpts,
- std::map<std::string, Option*> &OptionsMap) {
- std::vector<const char*> OptionNames;
+static void GetOptionInfo(SmallVectorImpl<Option*> &PositionalOpts,
+ SmallVectorImpl<Option*> &SinkOpts,
+ StringMap<Option*> &OptionsMap) {
+ SmallVector<const char*, 16> OptionNames;
Option *CAOpt = 0; // The ConsumeAfter option if it exists.
for (Option *O = RegisteredOptionList; O; O = O->getNextRegisteredOption()) {
// If this option wants to handle multiple option names, get the full set.
@@ -117,8 +120,7 @@ static void GetOptionInfo(std::vector<Option*> &PositionalOpts,
// Handle named options.
for (size_t i = 0, e = OptionNames.size(); i != e; ++i) {
// Add argument to the argument map!
- if (!OptionsMap.insert(std::pair<std::string,Option*>(OptionNames[i],
- O)).second) {
+ if (OptionsMap.GetOrCreateValue(OptionNames[i], O).second != O) {
errs() << ProgramName << ": CommandLine Error: Argument '"
<< OptionNames[i] << "' defined more than once!\n";
}
@@ -148,29 +150,39 @@ static void GetOptionInfo(std::vector<Option*> &PositionalOpts,
/// LookupOption - Lookup the option specified by the specified option on the
/// command line. If there is a value specified (after an equal sign) return
-/// that as well.
-static Option *LookupOption(const char *&Arg, const char *&Value,
- std::map<std::string, Option*> &OptionsMap) {
- while (*Arg == '-') ++Arg; // Eat leading dashes
-
- const char *ArgEnd = Arg;
- while (*ArgEnd && *ArgEnd != '=')
- ++ArgEnd; // Scan till end of argument name.
-
- if (*ArgEnd == '=') // If we have an equals sign...
- Value = ArgEnd+1; // Get the value, not the equals
+/// that as well. This assumes that leading dashes have already been stripped.
+static Option *LookupOption(StringRef &Arg, StringRef &Value,
+ const StringMap<Option*> &OptionsMap) {
+ // Reject all dashes.
+ if (Arg.empty()) return 0;
+
+ size_t EqualPos = Arg.find('=');
+
+ // If we have an equals sign, remember the value.
+ if (EqualPos == StringRef::npos) {
+ // Look up the option.
+ StringMap<Option*>::const_iterator I = OptionsMap.find(Arg);
+ return I != OptionsMap.end() ? I->second : 0;
+ }
+ // If the argument before the = is a valid option name, we match. If not,
+ // return Arg unmolested.
+ StringMap<Option*>::const_iterator I =
+ OptionsMap.find(Arg.substr(0, EqualPos));
+ if (I == OptionsMap.end()) return 0;
+
+ Value = Arg.substr(EqualPos+1);
+ Arg = Arg.substr(0, EqualPos);
+ return I->second;
+}
- if (*Arg == 0) return 0;
- // Look up the option.
- std::map<std::string, Option*>::iterator I =
- OptionsMap.find(std::string(Arg, ArgEnd));
- return I != OptionsMap.end() ? I->second : 0;
-}
-static inline bool ProvideOption(Option *Handler, const char *ArgName,
- const char *Value, int argc, char **argv,
+/// ProvideOption - For Value, this differentiates between an empty value ("")
+/// and a null value (StringRef()). The later is accepted for arguments that
+/// don't allow a value (-foo) the former is rejected (-foo=).
+static inline bool ProvideOption(Option *Handler, StringRef ArgName,
+ StringRef Value, int argc, char **argv,
int &i) {
// Is this a multi-argument option?
unsigned NumAdditionalVals = Handler->getNumAdditionalVals();
@@ -178,25 +190,25 @@ static inline bool ProvideOption(Option *Handler, const char *ArgName,
// Enforce value requirements
switch (Handler->getValueExpectedFlag()) {
case ValueRequired:
- if (Value == 0) { // No value specified?
- if (i+1 < argc) { // Steal the next argument, like for '-o filename'
- Value = argv[++i];
- } else {
+ if (Value.data() == 0) { // No value specified?
+ if (i+1 >= argc)
return Handler->error("requires a value!");
- }
+ // Steal the next argument, like for '-o filename'
+ Value = argv[++i];
}
break;
case ValueDisallowed:
if (NumAdditionalVals > 0)
return Handler->error("multi-valued option specified"
- " with ValueDisallowed modifier!");
+ " with ValueDisallowed modifier!");
- if (Value)
+ if (Value.data())
return Handler->error("does not allow a value! '" +
- std::string(Value) + "' specified.");
+ Twine(Value) + "' specified.");
break;
case ValueOptional:
break;
+
default:
errs() << ProgramName
<< ": Bad ValueMask flag! CommandLine usage error:"
@@ -205,40 +217,35 @@ static inline bool ProvideOption(Option *Handler, const char *ArgName,
}
// If this isn't a multi-arg option, just run the handler.
- if (NumAdditionalVals == 0) {
- return Handler->addOccurrence(i, ArgName, Value ? Value : "");
- }
+ if (NumAdditionalVals == 0)
+ return Handler->addOccurrence(i, ArgName, Value);
+
// If it is, run the handle several times.
- else {
- bool MultiArg = false;
-
- if (Value) {
- if (Handler->addOccurrence(i, ArgName, Value, MultiArg))
- return true;
- --NumAdditionalVals;
- MultiArg = true;
- }
+ bool MultiArg = false;
- while (NumAdditionalVals > 0) {
+ if (Value.data()) {
+ if (Handler->addOccurrence(i, ArgName, Value, MultiArg))
+ return true;
+ --NumAdditionalVals;
+ MultiArg = true;
+ }
- if (i+1 < argc) {
- Value = argv[++i];
- } else {
- return Handler->error("not enough values!");
- }
- if (Handler->addOccurrence(i, ArgName, Value, MultiArg))
- return true;
- MultiArg = true;
- --NumAdditionalVals;
- }
- return false;
+ while (NumAdditionalVals > 0) {
+ if (i+1 >= argc)
+ return Handler->error("not enough values!");
+ Value = argv[++i];
+
+ if (Handler->addOccurrence(i, ArgName, Value, MultiArg))
+ return true;
+ MultiArg = true;
+ --NumAdditionalVals;
}
+ return false;
}
-static bool ProvidePositionalOption(Option *Handler, const std::string &Arg,
- int i) {
+static bool ProvidePositionalOption(Option *Handler, StringRef Arg, int i) {
int Dummy = i;
- return ProvideOption(Handler, Handler->ArgStr, Arg.c_str(), 0, 0, Dummy);
+ return ProvideOption(Handler, Handler->ArgStr, Arg, 0, 0, Dummy);
}
@@ -256,33 +263,78 @@ static inline bool isPrefixedOrGrouping(const Option *O) {
// see if there options that satisfy the predicate. If we find one, return it,
// otherwise return null.
//
-static Option *getOptionPred(std::string Name, size_t &Length,
+static Option *getOptionPred(StringRef Name, size_t &Length,
bool (*Pred)(const Option*),
- std::map<std::string, Option*> &OptionsMap) {
+ const StringMap<Option*> &OptionsMap) {
- std::map<std::string, Option*>::iterator OMI = OptionsMap.find(Name);
- if (OMI != OptionsMap.end() && Pred(OMI->second)) {
- Length = Name.length();
- return OMI->second;
- }
+ StringMap<Option*>::const_iterator OMI = OptionsMap.find(Name);
- if (Name.size() == 1) return 0;
- do {
- Name.erase(Name.end()-1, Name.end()); // Chop off the last character...
+ // Loop while we haven't found an option and Name still has at least two
+ // characters in it (so that the next iteration will not be the empty
+ // string.
+ while (OMI == OptionsMap.end() && Name.size() > 1) {
+ Name = Name.substr(0, Name.size()-1); // Chop off the last character.
OMI = OptionsMap.find(Name);
-
- // Loop while we haven't found an option and Name still has at least two
- // characters in it (so that the next iteration will not be the empty
- // string...
- } while ((OMI == OptionsMap.end() || !Pred(OMI->second)) && Name.size() > 1);
+ }
if (OMI != OptionsMap.end() && Pred(OMI->second)) {
- Length = Name.length();
+ Length = Name.size();
return OMI->second; // Found one!
}
return 0; // No option found!
}
+/// HandlePrefixedOrGroupedOption - The specified argument string (which started
+/// with at least one '-') does not fully match an available option. Check to
+/// see if this is a prefix or grouped option. If so, split arg into output an
+/// Arg/Value pair and return the Option to parse it with.
+static Option *HandlePrefixedOrGroupedOption(StringRef &Arg, StringRef &Value,
+ bool &ErrorParsing,
+ const StringMap<Option*> &OptionsMap) {
+ if (Arg.size() == 1) return 0;
+
+ // Do the lookup!
+ size_t Length = 0;
+ Option *PGOpt = getOptionPred(Arg, Length, isPrefixedOrGrouping, OptionsMap);
+ if (PGOpt == 0) return 0;
+
+ // If the option is a prefixed option, then the value is simply the
+ // rest of the name... so fall through to later processing, by
+ // setting up the argument name flags and value fields.
+ if (PGOpt->getFormattingFlag() == cl::Prefix) {
+ Value = Arg.substr(Length);
+ Arg = Arg.substr(0, Length);
+ assert(OptionsMap.count(Arg) && OptionsMap.find(Arg)->second == PGOpt);
+ return PGOpt;
+ }
+
+ // This must be a grouped option... handle them now. Grouping options can't
+ // have values.
+ assert(isGrouping(PGOpt) && "Broken getOptionPred!");
+
+ do {
+ // Move current arg name out of Arg into OneArgName.
+ StringRef OneArgName = Arg.substr(0, Length);
+ Arg = Arg.substr(Length);
+
+ // Because ValueRequired is an invalid flag for grouped arguments,
+ // we don't need to pass argc/argv in.
+ assert(PGOpt->getValueExpectedFlag() != cl::ValueRequired &&
+ "Option can not be cl::Grouping AND cl::ValueRequired!");
+ int Dummy;
+ ErrorParsing |= ProvideOption(PGOpt, OneArgName,
+ StringRef(), 0, 0, Dummy);
+
+ // Get the next grouping option.
+ PGOpt = getOptionPred(Arg, Length, isGrouping, OptionsMap);
+ } while (PGOpt && Length != Arg.size());
+
+ // Return the last option with Arg cut down to just the last one.
+ return PGOpt;
+}
+
+
+
static bool RequiresValue(const Option *O) {
return O->getNumOccurrencesFlag() == cl::Required ||
O->getNumOccurrencesFlag() == cl::OneOrMore;
@@ -296,45 +348,35 @@ static bool EatsUnboundedNumberOfValues(const Option *O) {
/// ParseCStringVector - Break INPUT up wherever one or more
/// whitespace characters are found, and store the resulting tokens in
/// OUTPUT. The tokens stored in OUTPUT are dynamically allocated
-/// using strdup (), so it is the caller's responsibility to free ()
+/// using strdup(), so it is the caller's responsibility to free()
/// them later.
///
-static void ParseCStringVector(std::vector<char *> &output,
- const char *input) {
+static void ParseCStringVector(std::vector<char *> &OutputVector,
+ const char *Input) {
// Characters which will be treated as token separators:
- static const char *const delims = " \v\f\t\r\n";
-
- std::string work (input);
- // Skip past any delims at head of input string.
- size_t pos = work.find_first_not_of (delims);
- // If the string consists entirely of delims, then exit early.
- if (pos == std::string::npos) return;
- // Otherwise, jump forward to beginning of first word.
- work = work.substr (pos);
- // Find position of first delimiter.
- pos = work.find_first_of (delims);
-
- while (!work.empty() && pos != std::string::npos) {
- // Everything from 0 to POS is the next word to copy.
- output.push_back (strdup (work.substr (0,pos).c_str ()));
- // Is there another word in the string?
- size_t nextpos = work.find_first_not_of (delims, pos + 1);
- if (nextpos != std::string::npos) {
- // Yes? Then remove delims from beginning ...
- work = work.substr (work.find_first_not_of (delims, pos + 1));
- // and find the end of the word.
- pos = work.find_first_of (delims);
- } else {
- // No? (Remainder of string is delims.) End the loop.
- work = "";
- pos = std::string::npos;
+ StringRef Delims = " \v\f\t\r\n";
+
+ StringRef WorkStr(Input);
+ while (!WorkStr.empty()) {
+ // If the first character is a delimiter, strip them off.
+ if (Delims.find(WorkStr[0]) != StringRef::npos) {
+ size_t Pos = WorkStr.find_first_not_of(Delims);
+ if (Pos == StringRef::npos) Pos = WorkStr.size();
+ WorkStr = WorkStr.substr(Pos);
+ continue;
}
- }
-
- // If `input' ended with non-delim char, then we'll get here with
- // the last word of `input' in `work'; copy it now.
- if (!work.empty ()) {
- output.push_back (strdup (work.c_str ()));
+
+ // Find position of first delimiter.
+ size_t Pos = WorkStr.find_first_of(Delims);
+ if (Pos == StringRef::npos) Pos = WorkStr.size();
+
+ // Everything from 0 to Pos is the next word to copy.
+ char *NewStr = (char*)malloc(Pos+1);
+ memcpy(NewStr, WorkStr.data(), Pos);
+ NewStr[Pos] = 0;
+ OutputVector.push_back(NewStr);
+
+ WorkStr = WorkStr.substr(Pos);
}
}
@@ -368,20 +410,19 @@ void cl::ParseEnvironmentOptions(const char *progName, const char *envVar,
// Free all the strdup()ed strings.
for (std::vector<char*>::iterator i = newArgv.begin(), e = newArgv.end();
i != e; ++i)
- free (*i);
+ free(*i);
}
/// ExpandResponseFiles - Copy the contents of argv into newArgv,
/// substituting the contents of the response files for the arguments
/// of type @file.
-static void ExpandResponseFiles(int argc, char** argv,
+static void ExpandResponseFiles(unsigned argc, char** argv,
std::vector<char*>& newArgv) {
- for (int i = 1; i != argc; ++i) {
- char* arg = argv[i];
+ for (unsigned i = 1; i != argc; ++i) {
+ char *arg = argv[i];
if (arg[0] == '@') {
-
sys::PathWithStatus respFile(++arg);
// Check that the response file is not empty (mmap'ing empty
@@ -414,9 +455,9 @@ static void ExpandResponseFiles(int argc, char** argv,
void cl::ParseCommandLineOptions(int argc, char **argv,
const char *Overview, bool ReadResponseFiles) {
// Process all registered options.
- std::vector<Option*> PositionalOpts;
- std::vector<Option*> SinkOpts;
- std::map<std::string, Option*> Opts;
+ SmallVector<Option*, 4> PositionalOpts;
+ SmallVector<Option*, 4> SinkOpts;
+ StringMap<Option*> Opts;
GetOptionInfo(PositionalOpts, SinkOpts, Opts);
assert((!Opts.empty() || !PositionalOpts.empty()) &&
@@ -484,9 +525,9 @@ void cl::ParseCommandLineOptions(int argc, char **argv,
}
// PositionalVals - A vector of "positional" arguments we accumulate into
- // the process at the end...
+ // the process at the end.
//
- std::vector<std::pair<std::string,unsigned> > PositionalVals;
+ SmallVector<std::pair<StringRef,unsigned>, 4> PositionalVals;
// If the program has named positional arguments, and the name has been run
// across, keep track of which positional argument was named. Otherwise put
@@ -497,8 +538,8 @@ void cl::ParseCommandLineOptions(int argc, char **argv,
bool DashDashFound = false; // Have we read '--'?
for (int i = 1; i < argc; ++i) {
Option *Handler = 0;
- const char *Value = 0;
- const char *ArgName = "";
+ StringRef Value;
+ StringRef ArgName = "";
// If the option list changed, this means that some command line
// option has just been registered or deregistered. This can occur in
@@ -520,7 +561,9 @@ void cl::ParseCommandLineOptions(int argc, char **argv,
if (ActivePositionalArg) {
ProvidePositionalOption(ActivePositionalArg, argv[i], i);
continue; // We are done!
- } else if (!PositionalOpts.empty()) {
+ }
+
+ if (!PositionalOpts.empty()) {
PositionalVals.push_back(std::make_pair(argv[i],i));
// All of the positional arguments have been fulfulled, give the rest to
@@ -546,60 +589,28 @@ void cl::ParseCommandLineOptions(int argc, char **argv,
// option is another positional argument. If so, treat it as an argument,
// otherwise feed it to the eating positional.
ArgName = argv[i]+1;
+ // Eat leading dashes.
+ while (!ArgName.empty() && ArgName[0] == '-')
+ ArgName = ArgName.substr(1);
+
Handler = LookupOption(ArgName, Value, Opts);
if (!Handler || Handler->getFormattingFlag() != cl::Positional) {
ProvidePositionalOption(ActivePositionalArg, argv[i], i);
continue; // We are done!
}
- } else { // We start with a '-', must be an argument...
+ } else { // We start with a '-', must be an argument.
ArgName = argv[i]+1;
+ // Eat leading dashes.
+ while (!ArgName.empty() && ArgName[0] == '-')
+ ArgName = ArgName.substr(1);
+
Handler = LookupOption(ArgName, Value, Opts);
// Check to see if this "option" is really a prefixed or grouped argument.
- if (Handler == 0) {
- std::string RealName(ArgName);
- if (RealName.size() > 1) {
- size_t Length = 0;
- Option *PGOpt = getOptionPred(RealName, Length, isPrefixedOrGrouping,
- Opts);
-
- // If the option is a prefixed option, then the value is simply the
- // rest of the name... so fall through to later processing, by
- // setting up the argument name flags and value fields.
- //
- if (PGOpt && PGOpt->getFormattingFlag() == cl::Prefix) {
- Value = ArgName+Length;
- assert(Opts.find(std::string(ArgName, Value)) != Opts.end() &&
- Opts.find(std::string(ArgName, Value))->second == PGOpt);
- Handler = PGOpt;
- } else if (PGOpt) {
- // This must be a grouped option... handle them now.
- assert(isGrouping(PGOpt) && "Broken getOptionPred!");
-
- do {
- // Move current arg name out of RealName into RealArgName...
- std::string RealArgName(RealName.begin(),
- RealName.begin() + Length);
- RealName.erase(RealName.begin(), RealName.begin() + Length);
-
- // Because ValueRequired is an invalid flag for grouped arguments,
- // we don't need to pass argc/argv in...
- //
- assert(PGOpt->getValueExpectedFlag() != cl::ValueRequired &&
- "Option can not be cl::Grouping AND cl::ValueRequired!");
- int Dummy;
- ErrorParsing |= ProvideOption(PGOpt, RealArgName.c_str(),
- 0, 0, 0, Dummy);
-
- // Get the next grouping option...
- PGOpt = getOptionPred(RealName, Length, isGrouping, Opts);
- } while (PGOpt && Length != RealName.size());
-
- Handler = PGOpt; // Ate all of the options.
- }
- }
- }
+ if (Handler == 0)
+ Handler = HandlePrefixedOrGroupedOption(ArgName, Value,
+ ErrorParsing, Opts);
}
if (Handler == 0) {
@@ -608,7 +619,7 @@ void cl::ParseCommandLineOptions(int argc, char **argv,
<< argv[i] << "'. Try: '" << argv[0] << " --help'\n";
ErrorParsing = true;
} else {
- for (std::vector<Option*>::iterator I = SinkOpts.begin(),
+ for (SmallVectorImpl<Option*>::iterator I = SinkOpts.begin(),
E = SinkOpts.end(); I != E ; ++I)
(*I)->addOccurrence(i, "", argv[i]);
}
@@ -616,22 +627,20 @@ void cl::ParseCommandLineOptions(int argc, char **argv,
}
// Check to see if this option accepts a comma separated list of values. If
- // it does, we have to split up the value into multiple values...
- if (Value && Handler->getMiscFlags() & CommaSeparated) {
- std::string Val(Value);
- std::string::size_type Pos = Val.find(',');
-
- while (Pos != std::string::npos) {
- // Process the portion before the comma...
- ErrorParsing |= ProvideOption(Handler, ArgName,
- std::string(Val.begin(),
- Val.begin()+Pos).c_str(),
+ // it does, we have to split up the value into multiple values.
+ if (Handler->getMiscFlags() & CommaSeparated) {
+ StringRef Val(Value);
+ StringRef::size_type Pos = Val.find(',');
+
+ while (Pos != StringRef::npos) {
+ // Process the portion before the comma.
+ ErrorParsing |= ProvideOption(Handler, ArgName, Val.substr(0, Pos),
argc, argv, i);
- // Erase the portion before the comma, AND the comma...
- Val.erase(Val.begin(), Val.begin()+Pos+1);
- Value += Pos+1; // Increment the original value pointer as well...
+ // Erase the portion before the comma, AND the comma.
+ Val = Val.substr(Pos+1);
+ Value.substr(Pos+1); // Increment the original value pointer as well.
- // Check for another comma...
+ // Check for another comma.
Pos = Val.find(',');
}
}
@@ -661,7 +670,7 @@ void cl::ParseCommandLineOptions(int argc, char **argv,
ErrorParsing = true;
} else if (ConsumeAfterOpt == 0) {
- // Positional args have already been handled if ConsumeAfter is specified...
+ // Positional args have already been handled if ConsumeAfter is specified.
unsigned ValNo = 0, NumVals = static_cast<unsigned>(PositionalVals.size());
for (size_t i = 0, e = PositionalOpts.size(); i != e; ++i) {
if (RequiresValue(PositionalOpts[i])) {
@@ -726,7 +735,7 @@ void cl::ParseCommandLineOptions(int argc, char **argv,
}
// Loop over args and make sure all required args are specified!
- for (std::map<std::string, Option*>::iterator I = Opts.begin(),
+ for (StringMap<Option*>::iterator I = Opts.begin(),
E = Opts.end(); I != E; ++I) {
switch (I->second->getNumOccurrencesFlag()) {
case Required:
@@ -752,7 +761,7 @@ void cl::ParseCommandLineOptions(int argc, char **argv,
// Free all the strdup()ed strings.
for (std::vector<char*>::iterator i = newArgv.begin(), e = newArgv.end();
i != e; ++i)
- free (*i);
+ free(*i);
}
// If we had an error processing our arguments, don't let the program execute
@@ -763,9 +772,9 @@ void cl::ParseCommandLineOptions(int argc, char **argv,
// Option Base class implementation
//
-bool Option::error(std::string Message, const char *ArgName) {
- if (ArgName == 0) ArgName = ArgStr;
- if (ArgName[0] == 0)
+bool Option::error(const Twine &Message, StringRef ArgName) {
+ if (ArgName.data() == 0) ArgName = ArgStr;
+ if (ArgName.empty())
errs() << HelpStr; // Be nice for positional arguments
else
errs() << ProgramName << ": for the -" << ArgName;
@@ -774,9 +783,8 @@ bool Option::error(std::string Message, const char *ArgName) {
return true;
}
-bool Option::addOccurrence(unsigned pos, const char *ArgName,
- const std::string &Value,
- bool MultiArg) {
+bool Option::addOccurrence(unsigned pos, StringRef ArgName,
+ StringRef Value, bool MultiArg) {
if (!MultiArg)
NumOccurrences++; // Increment the number of times we have been seen
@@ -819,8 +827,8 @@ size_t alias::getOptionWidth() const {
// Print out the option for the alias.
void alias::printOptionInfo(size_t GlobalWidth) const {
size_t L = std::strlen(ArgStr);
- errs() << " -" << ArgStr << std::string(GlobalWidth-L-6, ' ') << " - "
- << HelpStr << "\n";
+ errs() << " -" << ArgStr;
+ errs().indent(GlobalWidth-L-6) << " - " << HelpStr << "\n";
}
@@ -859,67 +867,64 @@ void basic_parser_impl::printOptionInfo(const Option &O,
// parser<bool> implementation
//
-bool parser<bool>::parse(Option &O, const char *ArgName,
- const std::string &Arg, bool &Value) {
+bool parser<bool>::parse(Option &O, StringRef ArgName,
+ StringRef Arg, bool &Value) {
if (Arg == "" || Arg == "true" || Arg == "TRUE" || Arg == "True" ||
Arg == "1") {
Value = true;
- } else if (Arg == "false" || Arg == "FALSE" || Arg == "False" || Arg == "0") {
+ return false;
+ }
+
+ if (Arg == "false" || Arg == "FALSE" || Arg == "False" || Arg == "0") {
Value = false;
- } else {
- return O.error("'" + Arg +
- "' is invalid value for boolean argument! Try 0 or 1");
+ return false;
}
- return false;
+ return O.error("'" + Arg +
+ "' is invalid value for boolean argument! Try 0 or 1");
}
// parser<boolOrDefault> implementation
//
-bool parser<boolOrDefault>::parse(Option &O, const char *ArgName,
- const std::string &Arg, boolOrDefault &Value) {
+bool parser<boolOrDefault>::parse(Option &O, StringRef ArgName,
+ StringRef Arg, boolOrDefault &Value) {
if (Arg == "" || Arg == "true" || Arg == "TRUE" || Arg == "True" ||
Arg == "1") {
Value = BOU_TRUE;
- } else if (Arg == "false" || Arg == "FALSE"
- || Arg == "False" || Arg == "0") {
+ return false;
+ }
+ if (Arg == "false" || Arg == "FALSE" || Arg == "False" || Arg == "0") {
Value = BOU_FALSE;
- } else {
- return O.error("'" + Arg +
- "' is invalid value for boolean argument! Try 0 or 1");
+ return false;
}
- return false;
+
+ return O.error("'" + Arg +
+ "' is invalid value for boolean argument! Try 0 or 1");
}
// parser<int> implementation
//
-bool parser<int>::parse(Option &O, const char *ArgName,
- const std::string &Arg, int &Value) {
- char *End;
- Value = (int)strtol(Arg.c_str(), &End, 0);
- if (*End != 0)
+bool parser<int>::parse(Option &O, StringRef ArgName,
+ StringRef Arg, int &Value) {
+ if (Arg.getAsInteger(0, Value))
return O.error("'" + Arg + "' value invalid for integer argument!");
return false;
}
// parser<unsigned> implementation
//
-bool parser<unsigned>::parse(Option &O, const char *ArgName,
- const std::string &Arg, unsigned &Value) {
- char *End;
- errno = 0;
- unsigned long V = strtoul(Arg.c_str(), &End, 0);
- Value = (unsigned)V;
- if (((V == ULONG_MAX) && (errno == ERANGE))
- || (*End != 0)
- || (Value != V))
+bool parser<unsigned>::parse(Option &O, StringRef ArgName,
+ StringRef Arg, unsigned &Value) {
+
+ if (Arg.getAsInteger(0, Value))
return O.error("'" + Arg + "' value invalid for uint argument!");
return false;
}
// parser<double>/parser<float> implementation
//
-static bool parseDouble(Option &O, const std::string &Arg, double &Value) {
- const char *ArgStart = Arg.c_str();
+static bool parseDouble(Option &O, StringRef Arg, double &Value) {
+ SmallString<32> TmpStr(Arg.begin(), Arg.end());
+ const char *ArgStart = TmpStr.c_str();
char *End;
Value = strtod(ArgStart, &End);
if (*End != 0)
@@ -927,13 +932,13 @@ static bool parseDouble(Option &O, const std::string &Arg, double &Value) {
return false;
}
-bool parser<double>::parse(Option &O, const char *AN,
- const std::string &Arg, double &Val) {
+bool parser<double>::parse(Option &O, StringRef ArgName,
+ StringRef Arg, double &Val) {
return parseDouble(O, Arg, Val);
}
-bool parser<float>::parse(Option &O, const char *AN,
- const std::string &Arg, float &Val) {
+bool parser<float>::parse(Option &O, StringRef ArgName,
+ StringRef Arg, float &Val) {
double dVal;
if (parseDouble(O, Arg, dVal))
return true;
@@ -950,14 +955,12 @@ bool parser<float>::parse(Option &O, const char *AN,
// argument string. If the option is not found, getNumOptions() is returned.
//
unsigned generic_parser_base::findOption(const char *Name) {
- unsigned i = 0, e = getNumOptions();
- std::string N(Name);
+ unsigned e = getNumOptions();
- while (i != e)
- if (getOption(i) == N)
+ for (unsigned i = 0; i != e; ++i) {
+ if (strcmp(getOption(i), Name) == 0)
return i;
- else
- ++i;
+ }
return e;
}
@@ -984,21 +987,21 @@ void generic_parser_base::printOptionInfo(const Option &O,
size_t GlobalWidth) const {
if (O.hasArgStr()) {
size_t L = std::strlen(O.ArgStr);
- outs() << " -" << O.ArgStr << std::string(GlobalWidth-L-6, ' ')
- << " - " << O.HelpStr << '\n';
+ outs() << " -" << O.ArgStr;
+ outs().indent(GlobalWidth-L-6) << " - " << O.HelpStr << '\n';
for (unsigned i = 0, e = getNumOptions(); i != e; ++i) {
size_t NumSpaces = GlobalWidth-strlen(getOption(i))-8;
- outs() << " =" << getOption(i) << std::string(NumSpaces, ' ')
- << " - " << getDescription(i) << '\n';
+ outs() << " =" << getOption(i);
+ outs().indent(NumSpaces) << " - " << getDescription(i) << '\n';
}
} else {
if (O.HelpStr[0])
- outs() << " " << O.HelpStr << "\n";
+ outs() << " " << O.HelpStr << '\n';
for (unsigned i = 0, e = getNumOptions(); i != e; ++i) {
size_t L = std::strlen(getOption(i));
- outs() << " -" << getOption(i) << std::string(GlobalWidth-L-8, ' ')
- << " - " << getDescription(i) << "\n";
+ outs() << " -" << getOption(i);
+ outs().indent(GlobalWidth-L-8) << " - " << getDescription(i) << '\n';
}
}
}
@@ -1008,6 +1011,12 @@ void generic_parser_base::printOptionInfo(const Option &O,
// --help and --help-hidden option implementation
//
+static int OptNameCompare(const void *LHS, const void *RHS) {
+ typedef std::pair<const char *, Option*> pair_ty;
+
+ return strcmp(((pair_ty*)LHS)->first, ((pair_ty*)RHS)->first);
+}
+
namespace {
class HelpPrinter {
@@ -1015,14 +1024,6 @@ class HelpPrinter {
const Option *EmptyArg;
const bool ShowHidden;
- // isHidden/isReallyHidden - Predicates to be used to filter down arg lists.
- inline static bool isHidden(std::pair<std::string, Option *> &OptPair) {
- return OptPair.second->getOptionHiddenFlag() >= Hidden;
- }
- inline static bool isReallyHidden(std::pair<std::string, Option *> &OptPair) {
- return OptPair.second->getOptionHiddenFlag() == ReallyHidden;
- }
-
public:
explicit HelpPrinter(bool showHidden) : ShowHidden(showHidden) {
EmptyArg = 0;
@@ -1032,29 +1033,35 @@ public:
if (Value == false) return;
// Get all the options.
- std::vector<Option*> PositionalOpts;
- std::vector<Option*> SinkOpts;
- std::map<std::string, Option*> OptMap;
+ SmallVector<Option*, 4> PositionalOpts;
+ SmallVector<Option*, 4> SinkOpts;
+ StringMap<Option*> OptMap;
GetOptionInfo(PositionalOpts, SinkOpts, OptMap);
- // Copy Options into a vector so we can sort them as we like...
- std::vector<std::pair<std::string, Option*> > Opts;
- copy(OptMap.begin(), OptMap.end(), std::back_inserter(Opts));
-
- // Eliminate Hidden or ReallyHidden arguments, depending on ShowHidden
- Opts.erase(std::remove_if(Opts.begin(), Opts.end(),
- std::ptr_fun(ShowHidden ? isReallyHidden : isHidden)),
- Opts.end());
-
- // Eliminate duplicate entries in table (from enum flags options, f.e.)
- { // Give OptionSet a scope
- std::set<Option*> OptionSet;
- for (unsigned i = 0; i != Opts.size(); ++i)
- if (OptionSet.count(Opts[i].second) == 0)
- OptionSet.insert(Opts[i].second); // Add new entry to set
- else
- Opts.erase(Opts.begin()+i--); // Erase duplicate
+ // Copy Options into a vector so we can sort them as we like.
+ SmallVector<std::pair<const char *, Option*>, 128> Opts;
+ SmallPtrSet<Option*, 128> OptionSet; // Duplicate option detection.
+
+ for (StringMap<Option*>::iterator I = OptMap.begin(), E = OptMap.end();
+ I != E; ++I) {
+ // Ignore really-hidden options.
+ if (I->second->getOptionHiddenFlag() == ReallyHidden)
+ continue;
+
+ // Unless showhidden is set, ignore hidden flags.
+ if (I->second->getOptionHiddenFlag() == Hidden && !ShowHidden)
+ continue;
+
+ // If we've already seen this option, don't add it to the list again.
+ if (!OptionSet.insert(I->second))
+ continue;
+
+ Opts.push_back(std::pair<const char *, Option*>(I->getKey().data(),
+ I->second));
}
+
+ // Sort the options list alphabetically.
+ qsort(Opts.data(), Opts.size(), sizeof(Opts[0]), OptNameCompare);
if (ProgramOverview)
outs() << "OVERVIEW: " << ProgramOverview << "\n";
@@ -1115,56 +1122,64 @@ HHOp("help-hidden", cl::desc("Display all available options"),
static void (*OverrideVersionPrinter)() = 0;
+static int TargetArraySortFn(const void *LHS, const void *RHS) {
+ typedef std::pair<const char *, const Target*> pair_ty;
+ return strcmp(((const pair_ty*)LHS)->first, ((const pair_ty*)RHS)->first);
+}
+
namespace {
class VersionPrinter {
public:
void print() {
- outs() << "Low Level Virtual Machine (http://llvm.org/):\n"
- << " " << PACKAGE_NAME << " version " << PACKAGE_VERSION;
+ raw_ostream &OS = outs();
+ OS << "Low Level Virtual Machine (http://llvm.org/):\n"
+ << " " << PACKAGE_NAME << " version " << PACKAGE_VERSION;
#ifdef LLVM_VERSION_INFO
- outs() << LLVM_VERSION_INFO;
+ OS << LLVM_VERSION_INFO;
#endif
- outs() << "\n ";
+ OS << "\n ";
#ifndef __OPTIMIZE__
- outs() << "DEBUG build";
+ OS << "DEBUG build";
#else
- outs() << "Optimized build";
+ OS << "Optimized build";
#endif
#ifndef NDEBUG
- outs() << " with assertions";
+ OS << " with assertions";
#endif
- outs() << ".\n"
- << " Built " << __DATE__ << " (" << __TIME__ << ").\n"
- << "\n"
- << " Registered Targets:\n";
+ OS << ".\n"
+ << " Built " << __DATE__ << " (" << __TIME__ << ").\n"
+ << " Host: " << sys::getHostTriple() << '\n'
+ << '\n'
+ << " Registered Targets:\n";
- std::vector<std::pair<std::string, const Target*> > Targets;
+ std::vector<std::pair<const char *, const Target*> > Targets;
size_t Width = 0;
for (TargetRegistry::iterator it = TargetRegistry::begin(),
ie = TargetRegistry::end(); it != ie; ++it) {
Targets.push_back(std::make_pair(it->getName(), &*it));
- Width = std::max(Width, Targets.back().first.length());
+ Width = std::max(Width, strlen(Targets.back().first));
}
- std::sort(Targets.begin(), Targets.end());
+ if (!Targets.empty())
+ qsort(&Targets[0], Targets.size(), sizeof(Targets[0]),
+ TargetArraySortFn);
for (unsigned i = 0, e = Targets.size(); i != e; ++i) {
- outs() << " " << Targets[i].first
- << std::string(Width - Targets[i].first.length(), ' ') << " - "
- << Targets[i].second->getShortDescription() << "\n";
+ OS << " " << Targets[i].first;
+ OS.indent(Width - strlen(Targets[i].first)) << " - "
+ << Targets[i].second->getShortDescription() << '\n';
}
if (Targets.empty())
- outs() << " (none)\n";
+ OS << " (none)\n";
}
void operator=(bool OptionWasSpecified) {
- if (OptionWasSpecified) {
- if (OverrideVersionPrinter == 0) {
- print();
- exit(1);
- } else {
- (*OverrideVersionPrinter)();
- exit(1);
- }
+ if (!OptionWasSpecified) return;
+
+ if (OverrideVersionPrinter == 0) {
+ print();
+ exit(1);
}
+ (*OverrideVersionPrinter)();
+ exit(1);
}
};
} // End anonymous namespace
diff --git a/libclamav/c++/llvm/lib/Support/FoldingSet.cpp b/libclamav/c++/llvm/lib/Support/FoldingSet.cpp
index 187ecdb..954dc77 100644
--- a/libclamav/c++/llvm/lib/Support/FoldingSet.cpp
+++ b/libclamav/c++/llvm/lib/Support/FoldingSet.cpp
@@ -63,14 +63,14 @@ void FoldingSetNodeID::AddInteger(unsigned long long I) {
Bits.push_back(unsigned(I >> 32));
}
-void FoldingSetNodeID::AddString(const char *String, const char *End) {
- unsigned Size = static_cast<unsigned>(End - String);
+void FoldingSetNodeID::AddString(StringRef String) {
+ unsigned Size = String.size();
Bits.push_back(Size);
if (!Size) return;
unsigned Units = Size / 4;
unsigned Pos = 0;
- const unsigned *Base = (const unsigned *)String;
+ const unsigned *Base = (const unsigned*) String.data();
// If the string is aligned do a bulk transfer.
if (!((intptr_t)Base & 3)) {
@@ -100,14 +100,6 @@ void FoldingSetNodeID::AddString(const char *String, const char *End) {
Bits.push_back(V);
}
-void FoldingSetNodeID::AddString(const char *String) {
- AddString(String, String + strlen(String));
-}
-
-void FoldingSetNodeID::AddString(const std::string &String) {
- AddString(&*String.begin(), &*String.end());
-}
-
/// ComputeHash - Compute a strong hash value for this FoldingSetNodeID, used to
/// lookup the node in the FoldingSetImpl.
unsigned FoldingSetNodeID::ComputeHash() const {
diff --git a/libclamav/c++/llvm/lib/Support/MemoryObject.cpp b/libclamav/c++/llvm/lib/Support/MemoryObject.cpp
new file mode 100644
index 0000000..91e3ecd
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Support/MemoryObject.cpp
@@ -0,0 +1,34 @@
+//===- MemoryObject.cpp - Abstract memory interface -----------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/MemoryObject.h"
+using namespace llvm;
+
+MemoryObject::~MemoryObject() {
+}
+
+int MemoryObject::readBytes(uint64_t address,
+ uint64_t size,
+ uint8_t* buf,
+ uint64_t* copied) const {
+ uint64_t current = address;
+ uint64_t limit = getBase() + getExtent();
+
+ while (current - address < size && current < limit) {
+ if (readByte(current, &buf[(current - address)]))
+ return -1;
+
+ current++;
+ }
+
+ if (copied)
+ *copied = current - address;
+
+ return 0;
+}
diff --git a/libclamav/c++/llvm/lib/Support/Regex.cpp b/libclamav/c++/llvm/lib/Support/Regex.cpp
index f8b2446..618ca05 100644
--- a/libclamav/c++/llvm/lib/Support/Regex.cpp
+++ b/libclamav/c++/llvm/lib/Support/Regex.cpp
@@ -10,60 +10,53 @@
// This file implements a POSIX regular expression matcher.
//
//===----------------------------------------------------------------------===//
+
#include "llvm/Support/Regex.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/ADT/SmallVector.h"
#include "regex_impl.h"
#include <string>
-
using namespace llvm;
-Regex::Regex(const StringRef ®ex, unsigned Flags)
-{
+
+Regex::Regex(const StringRef ®ex, unsigned Flags) {
unsigned flags = 0;
- preg = new struct llvm_regex;
+ preg = new llvm_regex();
preg->re_endp = regex.end();
if (Flags & IgnoreCase)
flags |= REG_ICASE;
- if (Flags & NoSub) {
- flags |= REG_NOSUB;
- sub = false;
- } else {
- sub = true;
- }
if (Flags & Newline)
flags |= REG_NEWLINE;
error = llvm_regcomp(preg, regex.data(), flags|REG_EXTENDED|REG_PEND);
}
-bool Regex::isValid(std::string &Error)
-{
+Regex::~Regex() {
+ llvm_regfree(preg);
+ delete preg;
+}
+
+bool Regex::isValid(std::string &Error) {
if (!error)
return true;
-
+
size_t len = llvm_regerror(error, preg, NULL, 0);
- char *errbuff = new char[len];
- llvm_regerror(error, preg, errbuff, len);
- Error.assign(errbuff);
+
+ Error.resize(len);
+ llvm_regerror(error, preg, &Error[0], len);
return false;
}
-Regex::~Regex()
-{
- llvm_regfree(preg);
- delete preg;
+/// getNumMatches - In a valid regex, return the number of parenthesized
+/// matches it contains.
+unsigned Regex::getNumMatches() const {
+ return preg->re_nsub;
}
-bool Regex::match(const StringRef &String, SmallVectorImpl<StringRef> *Matches)
-{
+bool Regex::match(const StringRef &String, SmallVectorImpl<StringRef> *Matches){
unsigned nmatch = Matches ? preg->re_nsub+1 : 0;
- if (Matches) {
- assert(sub && "Substring matching requested but pattern compiled without");
- Matches->clear();
- }
-
// pmatch needs to have at least one element.
- SmallVector<llvm_regmatch_t, 2> pm;
+ SmallVector<llvm_regmatch_t, 8> pm;
pm.resize(nmatch > 0 ? nmatch : 1);
pm[0].rm_so = 0;
pm[0].rm_eo = String.size();
@@ -81,7 +74,9 @@ bool Regex::match(const StringRef &String, SmallVectorImpl<StringRef> *Matches)
// There was a match.
if (Matches) { // match position requested
- for (unsigned i=0;i<nmatch; i++) {
+ Matches->clear();
+
+ for (unsigned i = 0; i != nmatch; ++i) {
if (pm[i].rm_so == -1) {
// this group didn't match
Matches->push_back(StringRef());
diff --git a/libclamav/c++/llvm/lib/Support/Statistic.cpp b/libclamav/c++/llvm/lib/Support/Statistic.cpp
index 5ad5698..14f94bc 100644
--- a/libclamav/c++/llvm/lib/Support/Statistic.cpp
+++ b/libclamav/c++/llvm/lib/Support/Statistic.cpp
@@ -57,14 +57,14 @@ public:
}
static ManagedStatic<StatisticInfo> StatInfo;
-static ManagedStatic<sys::Mutex> StatLock;
+static ManagedStatic<sys::SmartMutex<true> > StatLock;
/// RegisterStatistic - The first time a statistic is bumped, this method is
/// called.
void Statistic::RegisterStatistic() {
// If stats are enabled, inform StatInfo that this statistic should be
// printed.
- sys::ScopedLock Writer(*StatLock);
+ sys::SmartScopedLock<true> Writer(*StatLock);
if (!Initialized) {
if (Enabled)
StatInfo->addStatistic(this);
diff --git a/libclamav/c++/llvm/lib/Support/StringRef.cpp b/libclamav/c++/llvm/lib/Support/StringRef.cpp
new file mode 100644
index 0000000..deaa19e
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Support/StringRef.cpp
@@ -0,0 +1,188 @@
+//===-- StringRef.cpp - Lightweight String References ---------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/StringRef.h"
+using namespace llvm;
+
+// MSVC emits references to this into the translation units which reference it.
+#ifndef _MSC_VER
+const size_t StringRef::npos;
+#endif
+
+//===----------------------------------------------------------------------===//
+// String Searching
+//===----------------------------------------------------------------------===//
+
+
+/// find - Search for the first string \arg Str in the string.
+///
+/// \return - The index of the first occurence of \arg Str, or npos if not
+/// found.
+size_t StringRef::find(const StringRef &Str) const {
+ size_t N = Str.size();
+ if (N > Length)
+ return npos;
+ for (size_t i = 0, e = Length - N + 1; i != e; ++i)
+ if (substr(i, N).equals(Str))
+ return i;
+ return npos;
+}
+
+/// rfind - Search for the last string \arg Str in the string.
+///
+/// \return - The index of the last occurence of \arg Str, or npos if not
+/// found.
+size_t StringRef::rfind(const StringRef &Str) const {
+ size_t N = Str.size();
+ if (N > Length)
+ return npos;
+ for (size_t i = Length - N + 1, e = 0; i != e;) {
+ --i;
+ if (substr(i, N).equals(Str))
+ return i;
+ }
+ return npos;
+}
+
+/// find_first_of - Find the first character from the string 'Chars' in the
+/// current string or return npos if not in string.
+StringRef::size_type StringRef::find_first_of(StringRef Chars) const {
+ for (size_type i = 0, e = Length; i != e; ++i)
+ if (Chars.find(Data[i]) != npos)
+ return i;
+ return npos;
+}
+
+/// find_first_not_of - Find the first character in the string that is not
+/// in the string 'Chars' or return npos if all are in string. Same as find.
+StringRef::size_type StringRef::find_first_not_of(StringRef Chars) const {
+ for (size_type i = 0, e = Length; i != e; ++i)
+ if (Chars.find(Data[i]) == npos)
+ return i;
+ return npos;
+}
+
+
+//===----------------------------------------------------------------------===//
+// Helpful Algorithms
+//===----------------------------------------------------------------------===//
+
+/// count - Return the number of non-overlapped occurrences of \arg Str in
+/// the string.
+size_t StringRef::count(const StringRef &Str) const {
+ size_t Count = 0;
+ size_t N = Str.size();
+ if (N > Length)
+ return 0;
+ for (size_t i = 0, e = Length - N + 1; i != e; ++i)
+ if (substr(i, N).equals(Str))
+ ++Count;
+ return Count;
+}
+
+/// GetAsUnsignedInteger - Workhorse method that converts a integer character
+/// sequence of radix up to 36 to an unsigned long long value.
+static bool GetAsUnsignedInteger(StringRef Str, unsigned Radix,
+ unsigned long long &Result) {
+ // Autosense radix if not specified.
+ if (Radix == 0) {
+ if (Str.startswith("0x")) {
+ Str = Str.substr(2);
+ Radix = 16;
+ } else if (Str.startswith("0b")) {
+ Str = Str.substr(2);
+ Radix = 2;
+ } else if (Str.startswith("0"))
+ Radix = 8;
+ else
+ Radix = 10;
+ }
+
+ // Empty strings (after the radix autosense) are invalid.
+ if (Str.empty()) return true;
+
+ // Parse all the bytes of the string given this radix. Watch for overflow.
+ Result = 0;
+ while (!Str.empty()) {
+ unsigned CharVal;
+ if (Str[0] >= '0' && Str[0] <= '9')
+ CharVal = Str[0]-'0';
+ else if (Str[0] >= 'a' && Str[0] <= 'z')
+ CharVal = Str[0]-'a'+10;
+ else if (Str[0] >= 'A' && Str[0] <= 'Z')
+ CharVal = Str[0]-'A'+10;
+ else
+ return true;
+
+ // If the parsed value is larger than the integer radix, the string is
+ // invalid.
+ if (CharVal >= Radix)
+ return true;
+
+ // Add in this character.
+ unsigned long long PrevResult = Result;
+ Result = Result*Radix+CharVal;
+
+ // Check for overflow.
+ if (Result < PrevResult)
+ return true;
+
+ Str = Str.substr(1);
+ }
+
+ return false;
+}
+
+bool StringRef::getAsInteger(unsigned Radix, unsigned long long &Result) const {
+ return GetAsUnsignedInteger(*this, Radix, Result);
+}
+
+
+bool StringRef::getAsInteger(unsigned Radix, long long &Result) const {
+ unsigned long long ULLVal;
+
+ // Handle positive strings first.
+ if (empty() || front() != '-') {
+ if (GetAsUnsignedInteger(*this, Radix, ULLVal) ||
+ // Check for value so large it overflows a signed value.
+ (long long)ULLVal < 0)
+ return true;
+ Result = ULLVal;
+ return false;
+ }
+
+ // Get the positive part of the value.
+ if (GetAsUnsignedInteger(substr(1), Radix, ULLVal) ||
+ // Reject values so large they'd overflow as negative signed, but allow
+ // "-0". This negates the unsigned so that the negative isn't undefined
+ // on signed overflow.
+ (long long)-ULLVal > 0)
+ return true;
+
+ Result = -ULLVal;
+ return false;
+}
+
+bool StringRef::getAsInteger(unsigned Radix, int &Result) const {
+ long long Val;
+ if (getAsInteger(Radix, Val) ||
+ (int)Val != Val)
+ return true;
+ Result = Val;
+ return false;
+}
+
+bool StringRef::getAsInteger(unsigned Radix, unsigned &Result) const {
+ unsigned long long Val;
+ if (getAsInteger(Radix, Val) ||
+ (unsigned)Val != Val)
+ return true;
+ Result = Val;
+ return false;
+}
diff --git a/libclamav/c++/llvm/lib/Support/SystemUtils.cpp b/libclamav/c++/llvm/lib/Support/SystemUtils.cpp
index 3d3649e..299032f 100644
--- a/libclamav/c++/llvm/lib/Support/SystemUtils.cpp
+++ b/libclamav/c++/llvm/lib/Support/SystemUtils.cpp
@@ -20,8 +20,7 @@ using namespace llvm;
bool llvm::CheckBitcodeOutputToConsole(raw_ostream &stream_to_check,
bool print_warning) {
- if (&stream_to_check == &outs() &&
- sys::Process::StandardOutIsDisplayed()) {
+ if (stream_to_check.is_displayed()) {
if (print_warning) {
errs() << "WARNING: You're attempting to print out a bitcode file.\n"
<< "This is inadvisable as it may cause display problems. If\n"
diff --git a/libclamav/c++/llvm/lib/Support/TargetRegistry.cpp b/libclamav/c++/llvm/lib/Support/TargetRegistry.cpp
index 79f30a7..5896447 100644
--- a/libclamav/c++/llvm/lib/Support/TargetRegistry.cpp
+++ b/libclamav/c++/llvm/lib/Support/TargetRegistry.cpp
@@ -40,7 +40,8 @@ const Target *TargetRegistry::lookupTarget(const std::string &TT,
}
if (!Best) {
- Error = "No available targets are compatible with this triple";
+ Error = "No available targets are compatible with this triple, "
+ "see -version for the available targets.";
return 0;
}
diff --git a/libclamav/c++/llvm/lib/Support/Triple.cpp b/libclamav/c++/llvm/lib/Support/Triple.cpp
index c4792e3..fc3b3f7 100644
--- a/libclamav/c++/llvm/lib/Support/Triple.cpp
+++ b/libclamav/c++/llvm/lib/Support/Triple.cpp
@@ -139,6 +139,43 @@ Triple::ArchType Triple::getArchTypeForLLVMName(const StringRef &Name) {
return UnknownArch;
}
+Triple::ArchType Triple::getArchTypeForDarwinArchName(const StringRef &Str) {
+ // See arch(3) and llvm-gcc's driver-driver.c. We don't implement support for
+ // archs which Darwin doesn't use.
+
+ // The matching this routine does is fairly pointless, since it is neither the
+ // complete architecture list, nor a reasonable subset. The problem is that
+ // historically the driver driver accepts this and also ties its -march=
+ // handling to the architecture name, so we need to be careful before removing
+ // support for it.
+
+ // This code must be kept in sync with Clang's Darwin specific argument
+ // translation.
+
+ if (Str == "ppc" || Str == "ppc601" || Str == "ppc603" || Str == "ppc604" ||
+ Str == "ppc604e" || Str == "ppc750" || Str == "ppc7400" ||
+ Str == "ppc7450" || Str == "ppc970")
+ return Triple::ppc;
+
+ if (Str == "ppc64")
+ return Triple::ppc64;
+
+ if (Str == "i386" || Str == "i486" || Str == "i486SX" || Str == "pentium" ||
+ Str == "i586" || Str == "pentpro" || Str == "i686" || Str == "pentIIm3" ||
+ Str == "pentIIm5" || Str == "pentium4")
+ return Triple::x86;
+
+ if (Str == "x86_64")
+ return Triple::x86_64;
+
+ // This is derived from the driver driver.
+ if (Str == "arm" || Str == "armv4t" || Str == "armv5" || Str == "xscale" ||
+ Str == "armv6" || Str == "armv7")
+ return Triple::arm;
+
+ return Triple::UnknownArch;
+}
+
//
void Triple::Parse() const {
@@ -186,6 +223,8 @@ void Triple::Parse() const {
Arch = systemz;
else if (ArchName == "tce")
Arch = tce;
+ else if (ArchName == "xcore")
+ Arch = xcore;
else
Arch = UnknownArch;
diff --git a/libclamav/c++/llvm/lib/Support/raw_ostream.cpp b/libclamav/c++/llvm/lib/Support/raw_ostream.cpp
index a229efd..0a82cc1 100644
--- a/libclamav/c++/llvm/lib/Support/raw_ostream.cpp
+++ b/libclamav/c++/llvm/lib/Support/raw_ostream.cpp
@@ -84,8 +84,8 @@ void raw_ostream::SetBuffered() {
void raw_ostream::SetBufferAndMode(char *BufferStart, size_t Size,
BufferKind Mode) {
assert(((Mode == Unbuffered && BufferStart == 0 && Size == 0) ||
- (Mode != Unbuffered && BufferStart && Size >= 64)) &&
- "stream must be unbuffered, or have >= 64 bytes of buffer");
+ (Mode != Unbuffered && BufferStart && Size)) &&
+ "stream must be unbuffered or have at least one byte");
// Make sure the current buffer is free of content (we can't flush here; the
// child buffer management logic will be in write_impl).
assert(GetNumBytesInBuffer() == 0 && "Current buffer is non-empty!");
@@ -454,6 +454,10 @@ raw_ostream &raw_fd_ostream::resetColor() {
return *this;
}
+bool raw_fd_ostream::is_displayed() const {
+ return sys::Process::FileDescriptorIsDisplayed(FD);
+}
+
//===----------------------------------------------------------------------===//
// raw_stdout/err_ostream
//===----------------------------------------------------------------------===//
diff --git a/libclamav/c++/llvm/lib/Support/regcomp.c b/libclamav/c++/llvm/lib/Support/regcomp.c
index 2755fd8..cd018d5 100644
--- a/libclamav/c++/llvm/lib/Support/regcomp.c
+++ b/libclamav/c++/llvm/lib/Support/regcomp.c
@@ -142,6 +142,7 @@ static char nuls[10]; /* place to point scanner in event of error */
#else
#define DUPMAX 255
#endif
+#define INFINITY (DUPMAX + 1)
#ifndef NDEBUG
static int never = 0; /* for use in asserts; shuts lint up */
@@ -256,8 +257,8 @@ static void
p_ere(struct parse *p, int stop) /* character this ERE should end at */
{
char c;
- sopno prevback = prevback;
- sopno prevfwd = prevfwd;
+ sopno prevback = 0;
+ sopno prevfwd = 0;
sopno conc;
int first = 1; /* is this the first alternative? */
diff --git a/libclamav/c++/llvm/lib/Support/regengine.inc b/libclamav/c++/llvm/lib/Support/regengine.inc
index ac848bc..0f27cfd 100644
--- a/libclamav/c++/llvm/lib/Support/regengine.inc
+++ b/libclamav/c++/llvm/lib/Support/regengine.inc
@@ -302,7 +302,6 @@ dissect(struct match *m, char *start, char *stop, sopno startst, sopno stopst)
char *ssp; /* start of string matched by subsubRE */
char *sep; /* end of string matched by subsubRE */
char *oldssp; /* previous ssp */
- char *dp;
AT("diss", start, stop, startst, stopst);
sp = start;
@@ -361,7 +360,8 @@ dissect(struct match *m, char *start, char *stop, sopno startst, sopno stopst)
esub = es - 1;
/* did innards match? */
if (slow(m, sp, rest, ssub, esub) != NULL) {
- dp = dissect(m, sp, rest, ssub, esub);
+ char *dp = dissect(m, sp, rest, ssub, esub);
+ (void)dp; /* avoid warning if assertions off */
assert(dp == rest);
} else /* no */
assert(sp == rest);
@@ -399,8 +399,11 @@ dissect(struct match *m, char *start, char *stop, sopno startst, sopno stopst)
}
assert(sep == rest); /* must exhaust substring */
assert(slow(m, ssp, sep, ssub, esub) == rest);
- dp = dissect(m, ssp, sep, ssub, esub);
- assert(dp == sep);
+ {
+ char *dp = dissect(m, ssp, sep, ssub, esub);
+ (void)dp; /* avoid warning if assertions off */
+ assert(dp == sep);
+ }
sp = rest;
break;
case OCH_:
@@ -434,8 +437,11 @@ dissect(struct match *m, char *start, char *stop, sopno startst, sopno stopst)
else
assert(OP(m->g->strip[esub]) == O_CH);
}
- dp = dissect(m, sp, rest, ssub, esub);
- assert(dp == rest);
+ {
+ char *dp = dissect(m, sp, rest, ssub, esub);
+ (void)dp; /* avoid warning if assertions off */
+ assert(dp == rest);
+ }
sp = rest;
break;
case O_PLUS:
diff --git a/libclamav/c++/llvm/lib/Support/regerror.c b/libclamav/c++/llvm/lib/Support/regerror.c
index 88d33b8..1d67c9a 100644
--- a/libclamav/c++/llvm/lib/Support/regerror.c
+++ b/libclamav/c++/llvm/lib/Support/regerror.c
@@ -45,6 +45,10 @@
#include "regutils.h"
+#ifdef _MSC_VER
+#define snprintf _snprintf
+#endif
+
static const char *regatoi(const llvm_regex_t *, char *, int);
static struct rerr {
diff --git a/libclamav/c++/llvm/lib/Support/regutils.h b/libclamav/c++/llvm/lib/Support/regutils.h
index 7150a3f..d0ee100 100644
--- a/libclamav/c++/llvm/lib/Support/regutils.h
+++ b/libclamav/c++/llvm/lib/Support/regutils.h
@@ -36,8 +36,6 @@
*/
/* utility definitions */
-#define DUPMAX _POSIX2_RE_DUP_MAX /* xxx is this right? */
-#define INFINITY (DUPMAX + 1)
#define NC (CHAR_MAX - CHAR_MIN + 1)
typedef unsigned char uch;
diff --git a/libclamav/c++/llvm/lib/System/Memory.cpp b/libclamav/c++/llvm/lib/System/Memory.cpp
index 375c73c..e2d838d 100644
--- a/libclamav/c++/llvm/lib/System/Memory.cpp
+++ b/libclamav/c++/llvm/lib/System/Memory.cpp
@@ -37,13 +37,16 @@ void llvm::sys::Memory::InvalidateInstructionCache(const void *Addr,
// icache invalidation for PPC and ARM.
#if defined(__APPLE__)
-#if (defined(__POWERPC__) || defined (__ppc__) || \
+
+# if (defined(__POWERPC__) || defined (__ppc__) || \
defined(_POWER) || defined(_ARCH_PPC)) || defined(__arm__)
sys_icache_invalidate(Addr, Len);
-#endif
+# endif
+
#else
-#if (defined(__POWERPC__) || defined (__ppc__) || \
- defined(_POWER) || defined(_ARCH_PPC)) && defined(__GNUC__)
+
+# if (defined(__POWERPC__) || defined (__ppc__) || \
+ defined(_POWER) || defined(_ARCH_PPC)) && defined(__GNUC__)
const size_t LineSize = 32;
const intptr_t Mask = ~(LineSize - 1);
@@ -57,6 +60,12 @@ void llvm::sys::Memory::InvalidateInstructionCache(const void *Addr,
for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
asm volatile("icbi 0, %0" : : "r"(Line));
asm volatile("isync");
-#endif
+# elif defined(__arm__) && defined(__GNUC__)
+ // FIXME: Can we safely always call this for __GNUC__ everywhere?
+ char *Start = (char*) Addr;
+ char *End = Start + Len;
+ __clear_cache(Start, End);
+# endif
+
#endif // end apple
}
diff --git a/libclamav/c++/llvm/lib/System/Mutex.cpp b/libclamav/c++/llvm/lib/System/Mutex.cpp
index a5e9920..8ccd6e5 100644
--- a/libclamav/c++/llvm/lib/System/Mutex.cpp
+++ b/libclamav/c++/llvm/lib/System/Mutex.cpp
@@ -115,8 +115,7 @@ MutexImpl::acquire()
int errorcode = pthread_mutex_lock(mutex);
return errorcode == 0;
- }
- return false;
+ } else return false;
}
bool
@@ -129,8 +128,7 @@ MutexImpl::release()
int errorcode = pthread_mutex_unlock(mutex);
return errorcode == 0;
- }
- return false;
+ } else return false;
}
bool
@@ -143,8 +141,7 @@ MutexImpl::tryacquire()
int errorcode = pthread_mutex_trylock(mutex);
return errorcode == 0;
- }
- return false;
+ } else return false;
}
}
diff --git a/libclamav/c++/llvm/lib/System/RWMutex.cpp b/libclamav/c++/llvm/lib/System/RWMutex.cpp
index 15d98cb..5faf220 100644
--- a/libclamav/c++/llvm/lib/System/RWMutex.cpp
+++ b/libclamav/c++/llvm/lib/System/RWMutex.cpp
@@ -117,8 +117,7 @@ RWMutexImpl::reader_acquire()
int errorcode = pthread_rwlock_rdlock(rwlock);
return errorcode == 0;
- }
- return false;
+ } else return false;
}
bool
@@ -131,8 +130,7 @@ RWMutexImpl::reader_release()
int errorcode = pthread_rwlock_unlock(rwlock);
return errorcode == 0;
- }
- return false;
+ } else return false;
}
bool
@@ -145,8 +143,7 @@ RWMutexImpl::writer_acquire()
int errorcode = pthread_rwlock_wrlock(rwlock);
return errorcode == 0;
- }
- return false;
+ } else return false;
}
bool
@@ -159,8 +156,7 @@ RWMutexImpl::writer_release()
int errorcode = pthread_rwlock_unlock(rwlock);
return errorcode == 0;
- }
- return false;
+ } else return false;
}
}
diff --git a/libclamav/c++/llvm/lib/System/Unix/Host.inc b/libclamav/c++/llvm/lib/System/Unix/Host.inc
index fb319fd..c76d6a4 100644
--- a/libclamav/c++/llvm/lib/System/Unix/Host.inc
+++ b/libclamav/c++/llvm/lib/System/Unix/Host.inc
@@ -16,7 +16,8 @@
//=== is guaranteed to work on *all* UNIX variants.
//===----------------------------------------------------------------------===//
-#include <llvm/Config/config.h>
+#include "llvm/Config/config.h"
+#include "llvm/ADT/StringRef.h"
#include "Unix.h"
#include <sys/utsname.h>
#include <string>
@@ -33,10 +34,47 @@ static std::string getOSVersion() {
}
std::string sys::getHostTriple() {
- // FIXME: Derive more directly instead of relying on the autoconf
- // generated variable.
+ // FIXME: Derive directly instead of relying on the autoconf generated
+ // variable.
- std::string Triple = LLVM_HOSTTRIPLE;
+ StringRef HostTripleString(LLVM_HOSTTRIPLE);
+ std::pair<StringRef, StringRef> ArchSplit = HostTripleString.split('-');
+
+ // Normalize the arch, since the host triple may not actually match the host.
+ std::string Arch = ArchSplit.first;
+
+ // It would be nice to do this in terms of llvm::Triple, but that is in
+ // Support which is layered above us.
+#if defined(__x86_64__)
+ Arch = "x86_64";
+#elif defined(__i386__)
+ Arch = "i386";
+#elif defined(__ppc64__)
+ Arch = "powerpc64";
+#elif defined(__ppc__)
+ Arch = "powerpc";
+#elif defined(__arm__)
+
+ // FIXME: We need to pick the right ARM triple (which involves querying the
+ // chip). However, for now this is most important for LLVM arch selection, so
+ // we only need to make sure to distinguish ARM and Thumb.
+# if defined(__thumb__)
+ Arch = "thumb";
+# else
+ Arch = "arm";
+# endif
+
+#else
+
+ // FIXME: When enough auto-detection is in place, this should just
+ // #error. Then at least the arch selection is done, and we only need the OS
+ // etc selection to kill off the use of LLVM_HOSTTRIPLE.
+
+#endif
+
+ std::string Triple(Arch);
+ Triple += '-';
+ Triple += ArchSplit.second;
// Force i<N>86 to i386.
if (Triple[0] == 'i' && isdigit(Triple[1]) &&
diff --git a/libclamav/c++/llvm/lib/System/Unix/Path.inc b/libclamav/c++/llvm/lib/System/Unix/Path.inc
index d7aa711..89285b4 100644
--- a/libclamav/c++/llvm/lib/System/Unix/Path.inc
+++ b/libclamav/c++/llvm/lib/System/Unix/Path.inc
@@ -57,6 +57,10 @@
#include <dlfcn.h>
#endif
+#ifdef __APPLE__
+#include <mach-o/dyld.h>
+#endif
+
// Put in a hack for Cygwin which falsely reports that the mkdtemp function
// is available when it is not.
#ifdef __CYGWIN__
@@ -336,7 +340,17 @@ getprogpath(char ret[PATH_MAX], const char *bin)
/// GetMainExecutable - Return the path to the main executable, given the
/// value of argv[0] from program startup.
Path Path::GetMainExecutable(const char *argv0, void *MainAddr) {
-#if defined(__FreeBSD__)
+#if defined(__APPLE__)
+ // On OS X the executable path is saved to the stack by dyld. Reading it
+ // from there is much faster than calling dladdr, especially for large
+ // binaries with symbols.
+ char exe_path[MAXPATHLEN];
+ uint32_t size = sizeof(exe_path);
+ if (_NSGetExecutablePath(exe_path, &size) == 0) {
+ char link_path[MAXPATHLEN];
+ return Path(std::string(realpath(exe_path, link_path)));
+ }
+#elif defined(__FreeBSD__)
char exe_path[PATH_MAX];
if (getprogpath(exe_path, argv0) != NULL)
diff --git a/libclamav/c++/llvm/lib/System/Unix/Process.inc b/libclamav/c++/llvm/lib/System/Unix/Process.inc
index c4ce35a..d715585 100644
--- a/libclamav/c++/llvm/lib/System/Unix/Process.inc
+++ b/libclamav/c++/llvm/lib/System/Unix/Process.inc
@@ -179,27 +179,24 @@ void Process::PreventCoreFiles() {
}
bool Process::StandardInIsUserInput() {
-#if HAVE_ISATTY
- return isatty(0);
-#endif
- // If we don't have isatty, just return false.
- return false;
+ return FileDescriptorIsDisplayed(STDIN_FILENO);
}
bool Process::StandardOutIsDisplayed() {
-#if HAVE_ISATTY
- return isatty(1);
-#endif
- // If we don't have isatty, just return false.
- return false;
+ return FileDescriptorIsDisplayed(STDOUT_FILENO);
}
bool Process::StandardErrIsDisplayed() {
+ return FileDescriptorIsDisplayed(STDERR_FILENO);
+}
+
+bool Process::FileDescriptorIsDisplayed(int fd) {
#if HAVE_ISATTY
- return isatty(2);
-#endif
+ return isatty(fd);
+#else
// If we don't have isatty, just return false.
return false;
+#endif
}
static unsigned getColumns(int FileID) {
diff --git a/libclamav/c++/llvm/lib/System/Unix/Program.inc b/libclamav/c++/llvm/lib/System/Unix/Program.inc
index 84e025c..56dea25 100644
--- a/libclamav/c++/llvm/lib/System/Unix/Program.inc
+++ b/libclamav/c++/llvm/lib/System/Unix/Program.inc
@@ -34,10 +34,15 @@
namespace llvm {
using namespace sys;
-Program::Program() : Pid_(0) {}
+Program::Program() : Data_(0) {}
Program::~Program() {}
+unsigned Program::GetPid() const {
+ uint64_t pid = reinterpret_cast<uint64_t>(Data_);
+ return static_cast<unsigned>(pid);
+}
+
// This function just uses the PATH environment variable to find the program.
Path
Program::FindProgramByName(const std::string& progName) {
@@ -116,11 +121,6 @@ static bool RedirectIO(const Path *Path, int FD, std::string* ErrMsg) {
return false;
}
-static bool Timeout = false;
-static void TimeOutHandler(int Sig) {
- Timeout = true;
-}
-
static void SetMemoryLimits (unsigned size)
{
#if HAVE_SYS_RESOURCE_H
@@ -214,7 +214,7 @@ Program::Execute(const Path& path,
break;
}
- Pid_ = child;
+ Data_ = reinterpret_cast<void*>(child);
return true;
}
@@ -226,25 +226,24 @@ Program::Wait(unsigned secondsToWait,
#ifdef HAVE_SYS_WAIT_H
struct sigaction Act, Old;
- if (Pid_ == 0) {
+ if (Data_ == 0) {
MakeErrMsg(ErrMsg, "Process not started!");
return -1;
}
// Install a timeout handler.
if (secondsToWait) {
- Timeout = false;
- Act.sa_sigaction = 0;
- Act.sa_handler = TimeOutHandler;
+ memset(&Act, 0, sizeof(Act));
+ Act.sa_handler = SIG_IGN;
sigemptyset(&Act.sa_mask);
- Act.sa_flags = 0;
sigaction(SIGALRM, &Act, &Old);
alarm(secondsToWait);
}
// Parent process: Wait for the child process to terminate.
int status;
- int child = this->Pid_;
+ uint64_t pid = reinterpret_cast<uint64_t>(Data_);
+ pid_t child = static_cast<pid_t>(pid);
while (wait(&status) != child)
if (secondsToWait && errno == EINTR) {
// Kill the child.
@@ -290,6 +289,24 @@ Program::Wait(unsigned secondsToWait,
}
+bool
+Program::Kill(std::string* ErrMsg) {
+ if (Data_ == 0) {
+ MakeErrMsg(ErrMsg, "Process not started!");
+ return true;
+ }
+
+ uint64_t pid64 = reinterpret_cast<uint64_t>(Data_);
+ pid_t pid = static_cast<pid_t>(pid64);
+
+ if (kill(pid, SIGKILL) != 0) {
+ MakeErrMsg(ErrMsg, "The process couldn't be killed!");
+ return true;
+ }
+
+ return false;
+}
+
bool Program::ChangeStdinToBinary(){
// Do nothing, as Unix doesn't differentiate between text and binary.
return false;
diff --git a/libclamav/c++/llvm/lib/System/Win32/Process.inc b/libclamav/c++/llvm/lib/System/Win32/Process.inc
index cfbe33c..feb0806 100644
--- a/libclamav/c++/llvm/lib/System/Win32/Process.inc
+++ b/libclamav/c++/llvm/lib/System/Win32/Process.inc
@@ -120,15 +120,19 @@ void Process::PreventCoreFiles() {
}
bool Process::StandardInIsUserInput() {
- return GetFileType((HANDLE)_get_osfhandle(0)) == FILE_TYPE_CHAR;
+ return FileDescriptorIsDisplayed(0);
}
bool Process::StandardOutIsDisplayed() {
- return GetFileType((HANDLE)_get_osfhandle(1)) == FILE_TYPE_CHAR;
+ return FileDescriptorIsDisplayed(1);
}
bool Process::StandardErrIsDisplayed() {
- return GetFileType((HANDLE)_get_osfhandle(2)) == FILE_TYPE_CHAR;
+ return FileDescriptorIsDisplayed(2);
+}
+
+bool Process::FileDescriptorIsDisplayed(int fd) {
+ return GetFileType((HANDLE)_get_osfhandle(fd)) == FILE_TYPE_CHAR;
}
unsigned Process::StandardOutColumns() {
diff --git a/libclamav/c++/llvm/lib/System/Win32/Program.inc b/libclamav/c++/llvm/lib/System/Win32/Program.inc
index 804273b..a69826f 100644
--- a/libclamav/c++/llvm/lib/System/Win32/Program.inc
+++ b/libclamav/c++/llvm/lib/System/Win32/Program.inc
@@ -22,17 +22,30 @@
//=== and must not be UNIX code
//===----------------------------------------------------------------------===//
+namespace {
+ struct Win32ProcessInfo {
+ HANDLE hProcess;
+ DWORD dwProcessId;
+ };
+}
+
namespace llvm {
using namespace sys;
-Program::Program() : Pid_(0), Data(0) {}
+Program::Program() : Data_(0) {}
Program::~Program() {
- if (Data) {
- HANDLE hProcess = (HANDLE) Data;
- CloseHandle(hProcess);
- Data = 0;
- }
+ if (Data_) {
+ Win32ProcessInfo* wpi = reinterpret_cast<Win32ProcessInfo*>(Data_);
+ CloseHandle(wpi->hProcess);
+ delete wpi;
+ Data_ = 0;
+ }
+}
+
+unsigned Program::GetPid() const {
+ Win32ProcessInfo* wpi = reinterpret_cast<Win32ProcessInfo*>(Data_);
+ return wpi->dwProcessId;
}
// This function just uses the PATH environment variable to find the program.
@@ -121,7 +134,7 @@ static HANDLE RedirectIO(const Path *path, int fd, std::string* ErrMsg) {
/// ArgNeedsQuotes - Check whether argument needs to be quoted when calling
/// CreateProcess.
-static bool ArgNeedsQuotes(const char *Str) {
+static bool ArgNeedsQuotes(const char *Str) {
return Str[0] == '\0' || strchr(Str, ' ') != 0;
}
@@ -132,12 +145,13 @@ Program::Execute(const Path& path,
const Path** redirects,
unsigned memoryLimit,
std::string* ErrMsg) {
- if (Data) {
- HANDLE hProcess = (HANDLE) Data;
- CloseHandle(Data);
- Data = 0;
+ if (Data_) {
+ Win32ProcessInfo* wpi = reinterpret_cast<Win32ProcessInfo*>(Data_);
+ CloseHandle(wpi->hProcess);
+ delete wpi;
+ Data_ = 0;
}
-
+
if (!path.canExecute()) {
if (ErrMsg)
*ErrMsg = "program not executable";
@@ -264,9 +278,11 @@ Program::Execute(const Path& path,
path.str() + "'");
return false;
}
- Pid_ = pi.dwProcessId;
- Data = pi.hProcess;
-
+ Win32ProcessInfo* wpi = new Win32ProcessInfo;
+ wpi->hProcess = pi.hProcess;
+ wpi->dwProcessId = pi.dwProcessId;
+ Data_ = wpi;
+
// Make sure these get closed no matter what.
AutoHandle hThread(pi.hThread);
@@ -301,13 +317,14 @@ Program::Execute(const Path& path,
int
Program::Wait(unsigned secondsToWait,
std::string* ErrMsg) {
- if (Data == 0) {
+ if (Data_ == 0) {
MakeErrMsg(ErrMsg, "Process not started!");
return -1;
}
- HANDLE hProcess = (HANDLE) Data;
-
+ Win32ProcessInfo* wpi = reinterpret_cast<Win32ProcessInfo*>(Data_);
+ HANDLE hProcess = wpi->hProcess;
+
// Wait for the process to terminate.
DWORD millisecondsToWait = INFINITE;
if (secondsToWait > 0)
@@ -335,6 +352,23 @@ Program::Wait(unsigned secondsToWait,
return status;
}
+bool
+Program::Kill(std::string* ErrMsg) {
+ if (Data_ == 0) {
+ MakeErrMsg(ErrMsg, "Process not started!");
+ return true;
+ }
+
+ Win32ProcessInfo* wpi = reinterpret_cast<Win32ProcessInfo*>(Data_);
+ HANDLE hProcess = wpi->hProcess;
+ if (TerminateProcess(hProcess, 1) == 0) {
+ MakeErrMsg(ErrMsg, "The process couldn't be killed!");
+ return true;
+ }
+
+ return false;
+}
+
bool Program::ChangeStdinToBinary(){
int result = _setmode( _fileno(stdin), _O_BINARY );
return result == -1;
diff --git a/libclamav/c++/llvm/lib/System/Win32/Signals.inc b/libclamav/c++/llvm/lib/System/Win32/Signals.inc
index 4a1a4cc..dba2218 100644
--- a/libclamav/c++/llvm/lib/System/Win32/Signals.inc
+++ b/libclamav/c++/llvm/lib/System/Win32/Signals.inc
@@ -43,6 +43,9 @@ static std::vector<llvm::sys::Path> *FilesToRemove = NULL;
static std::vector<std::pair<void(*)(void*), void*> > *CallBacksToRun = 0;
static bool RegisteredUnhandledExceptionFilter = false;
static bool CleanupExecuted = false;
+#ifdef _MSC_VER
+static bool ExitOnUnhandledExceptions = false;
+#endif
static PTOP_LEVEL_EXCEPTION_FILTER OldFilter = NULL;
// Windows creates a new thread to execute the console handler when an event
@@ -57,8 +60,38 @@ namespace llvm {
//=== and must not be UNIX code
//===----------------------------------------------------------------------===//
+#ifdef _MSC_VER
+/// CRTReportHook - Function called on a CRT debugging event.
+static int CRTReportHook(int ReportType, char *Message, int *Return) {
+ // Don't cause a DebugBreak() on return.
+ if (Return)
+ *Return = 0;
+
+ switch (ReportType) {
+ default:
+ case _CRT_ASSERT:
+ fprintf(stderr, "CRT assert: %s\n", Message);
+ // FIXME: Is there a way to just crash? Perhaps throw to the unhandled
+ // exception code? Perhaps SetErrorMode() handles this.
+ _exit(3);
+ break;
+ case _CRT_ERROR:
+ fprintf(stderr, "CRT error: %s\n", Message);
+ // FIXME: Is there a way to just crash? Perhaps throw to the unhandled
+ // exception code? Perhaps SetErrorMode() handles this.
+ _exit(3);
+ break;
+ case _CRT_WARN:
+ fprintf(stderr, "CRT warn: %s\n", Message);
+ break;
+ }
+
+ // Don't call _CrtDbgReport.
+ return TRUE;
+}
+#endif
-static void RegisterHandler() {
+static void RegisterHandler() {
if (RegisteredUnhandledExceptionFilter) {
EnterCriticalSection(&CriticalSection);
return;
@@ -76,6 +109,14 @@ static void RegisterHandler() {
OldFilter = SetUnhandledExceptionFilter(LLVMUnhandledExceptionFilter);
SetConsoleCtrlHandler(LLVMConsoleCtrlHandler, TRUE);
+ // Environment variable to disable any kind of crash dialog.
+#ifdef _MSC_VER
+ if (getenv("LLVM_DISABLE_CRT_DEBUG")) {
+ _CrtSetReportHook(CRTReportHook);
+ ExitOnUnhandledExceptions = true;
+ }
+#endif
+
// IMPORTANT NOTE: Caller must call LeaveCriticalSection(&CriticalSection) or
// else multi-threading problems will ensue.
}
@@ -235,6 +276,11 @@ static LONG WINAPI LLVMUnhandledExceptionFilter(LPEXCEPTION_POINTERS ep) {
assert(0 && "Crashed in LLVMUnhandledExceptionFilter");
}
+#ifdef _MSC_VER
+ if (ExitOnUnhandledExceptions)
+ _exit(-3);
+#endif
+
// Allow dialog box to pop up allowing choice to start debugger.
if (OldFilter)
return (*OldFilter)(ep);
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARM.h b/libclamav/c++/llvm/lib/Target/ARM/ARM.h
index e95dfc0..487ce1d 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARM.h
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARM.h
@@ -92,7 +92,8 @@ inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
}
}
-FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM);
+FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
+ CodeGenOpt::Level OptLevel);
FunctionPass *createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
MachineCodeEmitter &MCE);
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARM.td b/libclamav/c++/llvm/lib/Target/ARM/ARM.td
index eb6304c..8851fbb 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARM.td
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARM.td
@@ -40,9 +40,6 @@ def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
"Enable NEON instructions">;
def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
"Enable Thumb2 instructions">;
-def FeatureNEONFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
- "true",
- "Use NEON for single-precision FP">;
//===----------------------------------------------------------------------===//
// ARM Processors supported.
@@ -92,30 +89,21 @@ def : ProcNoItin<"xscale", [ArchV5TE]>;
def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
// V6 Processors.
-def : Processor<"arm1136j-s", V6Itineraries,
- [ArchV6]>;
-def : Processor<"arm1136jf-s", V6Itineraries,
- [ArchV6, FeatureVFP2]>;
-def : Processor<"arm1176jz-s", V6Itineraries,
- [ArchV6]>;
-def : Processor<"arm1176jzf-s", V6Itineraries,
- [ArchV6, FeatureVFP2]>;
-def : Processor<"mpcorenovfp", V6Itineraries,
- [ArchV6]>;
-def : Processor<"mpcore", V6Itineraries,
- [ArchV6, FeatureVFP2]>;
+def : ProcNoItin<"arm1136j-s", [ArchV6]>;
+def : ProcNoItin<"arm1136jf-s", [ArchV6, FeatureVFP2]>;
+def : ProcNoItin<"arm1176jz-s", [ArchV6]>;
+def : ProcNoItin<"arm1176jzf-s", [ArchV6, FeatureVFP2]>;
+def : ProcNoItin<"mpcorenovfp", [ArchV6]>;
+def : ProcNoItin<"mpcore", [ArchV6, FeatureVFP2]>;
// V6T2 Processors.
-def : Processor<"arm1156t2-s", V6Itineraries,
- [ArchV6T2, FeatureThumb2]>;
-def : Processor<"arm1156t2f-s", V6Itineraries,
- [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
+def : ProcNoItin<"arm1156t2-s", [ArchV6T2, FeatureThumb2]>;
+def : ProcNoItin<"arm1156t2f-s", [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
// V7 Processors.
def : Processor<"cortex-a8", CortexA8Itineraries,
- [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP]>;
-def : Processor<"cortex-a9", CortexA9Itineraries,
[ArchV7A, FeatureThumb2, FeatureNEON]>;
+def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
//===----------------------------------------------------------------------===//
// Register File Description
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/libclamav/c++/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 142c3f1..79950fe 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -423,6 +423,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
default:
llvm_unreachable("Unknown or unset size field for instr!");
case TargetInstrInfo::IMPLICIT_DEF:
+ case TargetInstrInfo::KILL:
case TargetInstrInfo::DBG_LABEL:
case TargetInstrInfo::EH_LABEL:
return 0;
@@ -612,14 +613,29 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
if (I != MBB.end()) DL = I->getDebugLoc();
if (DestRC != SrcRC) {
- if (((DestRC == ARM::DPRRegisterClass) &&
- (SrcRC == ARM::DPR_VFP2RegisterClass)) ||
- ((SrcRC == ARM::DPRRegisterClass) &&
- (DestRC == ARM::DPR_VFP2RegisterClass))) {
- // Allow copy between DPR and DPR_VFP2.
- } else {
+ // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies
+ // Allow QPR / QPR_VFP2 cross-class copies
+ if (DestRC == ARM::DPRRegisterClass) {
+ if (SrcRC == ARM::DPR_VFP2RegisterClass ||
+ SrcRC == ARM::DPR_8RegisterClass) {
+ } else
+ return false;
+ } else if (DestRC == ARM::DPR_VFP2RegisterClass) {
+ if (SrcRC == ARM::DPRRegisterClass ||
+ SrcRC == ARM::DPR_8RegisterClass) {
+ } else
+ return false;
+ } else if (DestRC == ARM::DPR_8RegisterClass) {
+ if (SrcRC == ARM::DPRRegisterClass ||
+ SrcRC == ARM::DPR_VFP2RegisterClass) {
+ } else
+ return false;
+ } else if ((DestRC == ARM::QPRRegisterClass &&
+ SrcRC == ARM::QPR_VFP2RegisterClass) ||
+ (DestRC == ARM::QPR_VFP2RegisterClass &&
+ SrcRC == ARM::QPRRegisterClass)) {
+ } else
return false;
- }
}
if (DestRC == ARM::GPRRegisterClass) {
@@ -629,10 +645,12 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
.addReg(SrcReg));
} else if ((DestRC == ARM::DPRRegisterClass) ||
- (DestRC == ARM::DPR_VFP2RegisterClass)) {
+ (DestRC == ARM::DPR_VFP2RegisterClass) ||
+ (DestRC == ARM::DPR_8RegisterClass)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
.addReg(SrcReg));
- } else if (DestRC == ARM::QPRRegisterClass) {
+ } else if (DestRC == ARM::QPRRegisterClass ||
+ DestRC == ARM::QPR_VFP2RegisterClass) {
BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
} else {
return false;
@@ -652,7 +670,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addReg(0).addImm(0));
- } else if (RC == ARM::DPRRegisterClass || RC == ARM::DPR_VFP2RegisterClass) {
+ } else if (RC == ARM::DPRRegisterClass ||
+ RC == ARM::DPR_VFP2RegisterClass ||
+ RC == ARM::DPR_8RegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0));
@@ -661,7 +681,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0));
} else {
- assert(RC == ARM::QPRRegisterClass && "Unknown regclass!");
+ assert((RC == ARM::QPRRegisterClass ||
+ RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
// FIXME: Neon instructions should support predicates
BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0);
@@ -678,14 +699,17 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
if (RC == ARM::GPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
.addFrameIndex(FI).addReg(0).addImm(0));
- } else if (RC == ARM::DPRRegisterClass || RC == ARM::DPR_VFP2RegisterClass) {
+ } else if (RC == ARM::DPRRegisterClass ||
+ RC == ARM::DPR_VFP2RegisterClass ||
+ RC == ARM::DPR_8RegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
.addFrameIndex(FI).addImm(0));
} else if (RC == ARM::SPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
.addFrameIndex(FI).addImm(0));
} else {
- assert(RC == ARM::QPRRegisterClass && "Unknown regclass!");
+ assert((RC == ARM::QPRRegisterClass ||
+ RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
// FIXME: Neon instructions should support predicates
BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0);
}
@@ -841,7 +865,8 @@ ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
/// getInstrPredicate - If instruction is predicated, returns its predicate
/// condition, otherwise returns AL. It also returns the condition code
/// register by reference.
-ARMCC::CondCodes llvm::getInstrPredicate(MachineInstr *MI, unsigned &PredReg) {
+ARMCC::CondCodes
+llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
int PIdx = MI->findFirstPredOperandIdx();
if (PIdx == -1) {
PredReg = 0;
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/libclamav/c++/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 3632450..a13155b 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -296,7 +296,7 @@ bool isJumpTableBranchOpcode(int Opc) {
/// getInstrPredicate - If instruction is predicated, returns its predicate
/// condition, otherwise returns AL. It also returns the condition code
/// register by reference.
-ARMCC::CondCodes getInstrPredicate(MachineInstr *MI, unsigned &PredReg);
+ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
int getMatchingCondBranchOpcode(int Opc);
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/libclamav/c++/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 1c41073..4db4636 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -245,7 +245,7 @@ bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
const TargetRegisterClass *
ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
- return &ARM::GPRRegClass;
+ return ARM::GPRRegisterClass;
}
/// getAllocationOrder - Returns the register allocation order for a specified
@@ -536,7 +536,8 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
}
}
- if (CSRegClasses[i] == &ARM::GPRRegClass) {
+ if (CSRegClasses[i] == ARM::GPRRegisterClass ||
+ CSRegClasses[i] == ARM::tGPRRegisterClass) {
if (Spilled) {
NumGPRSpills++;
@@ -649,10 +650,18 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// Estimate if we might need to scavenge a register at some point in order
// to materialize a stack offset. If so, either spill one additional
// callee-saved register or reserve a special spill slot to facilitate
- // register scavenging.
- if (RS && !ExtraCSSpill && !AFI->isThumb1OnlyFunction()) {
+ // register scavenging. Thumb1 needs a spill slot for stack pointer
+ // adjustments also, even when the frame itself is small.
+ if (RS && !ExtraCSSpill) {
MachineFrameInfo *MFI = MF.getFrameInfo();
- if (estimateStackSize(MF, MFI) >= estimateRSStackSizeLimit(MF)) {
+ // If any of the stack slot references may be out of range of an
+ // immediate offset, make sure a register (or a spill slot) is
+ // available for the register scavenger. Note that if we're indexing
+ // off the frame pointer, the effective stack size is 4 bytes larger
+ // since the FP points to the stack slot of the previous FP.
+ if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
+ >= estimateRSStackSizeLimit(MF)
+ || AFI->isThumb1OnlyFunction()) {
// If any non-reserved CS register isn't spilled, just spill one or two
// extra. That should take care of it!
unsigned NumExtras = TargetAlign / 4;
@@ -665,12 +674,15 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
NumExtras--;
}
}
- while (NumExtras && !UnspilledCS2GPRs.empty()) {
- unsigned Reg = UnspilledCS2GPRs.back();
- UnspilledCS2GPRs.pop_back();
- if (!isReservedReg(MF, Reg)) {
- Extras.push_back(Reg);
- NumExtras--;
+ // For non-Thumb1 functions, also check for hi-reg CS registers
+ if (!AFI->isThumb1OnlyFunction()) {
+ while (NumExtras && !UnspilledCS2GPRs.empty()) {
+ unsigned Reg = UnspilledCS2GPRs.back();
+ UnspilledCS2GPRs.pop_back();
+ if (!isReservedReg(MF, Reg)) {
+ Extras.push_back(Reg);
+ NumExtras--;
+ }
}
}
if (Extras.size() && NumExtras == 0) {
@@ -680,7 +692,7 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
}
} else {
// Reserve a slot closest to SP or frame pointer.
- const TargetRegisterClass *RC = &ARM::GPRRegClass;
+ const TargetRegisterClass *RC = ARM::GPRRegisterClass;
RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
RC->getAlignment()));
}
@@ -1021,7 +1033,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
const MachineFrameInfo *MFI = MF.getFrameInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
assert(!AFI->isThumb1OnlyFunction() &&
- "This eliminateFrameIndex does not suppor Thumb1!");
+ "This eliminateFrameIndex does not support Thumb1!");
while (!MI.getOperand(i).isFI()) {
++i;
@@ -1068,10 +1080,10 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// If the offset we have is too large to fit into the instruction, we need
// to form it with a series of ADDri's. Do this by taking 8-bit chunks
// out of 'Offset'.
- unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
+ unsigned ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI);
if (ScratchReg == 0)
// No register is "free". Scavenge a register.
- ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
+ ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj);
int PIdx = MI.findFirstPredOperandIdx();
ARMCC::CondCodes Pred = (PIdx == -1)
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
@@ -1149,6 +1161,7 @@ emitPrologue(MachineFunction &MF) const {
unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
int FramePtrSpillFI = 0;
+ // Allocate the vararg register save area. This is not counted in NumBytes.
if (VARegSaveSize)
emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
@@ -1196,8 +1209,11 @@ emitPrologue(MachineFunction &MF) const {
emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
- // Darwin ABI requires FP to point to the stack slot that contains the
- // previous FP.
+ // Set FP to point to the stack slot that contains the previous FP.
+ // For Darwin, FP is R7, which has now been stored in spill area 1.
+ // Otherwise, if this is not Darwin, all the callee-saved registers go
+ // into spill area 1, including the FP in R11. In either case, it is
+ // now safe to emit this assignment.
if (STI.isTargetDarwin() || hasFP(MF)) {
unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
MachineInstrBuilder MIB =
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/libclamav/c++/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
index 37e2cfc..6419b69 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -31,6 +31,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Compiler.h"
@@ -60,12 +61,18 @@ namespace {
ARMJITInfo *JTI;
const ARMInstrInfo *II;
const TargetData *TD;
+ const ARMSubtarget *Subtarget;
TargetMachine &TM;
CodeEmitter &MCE;
const std::vector<MachineConstantPoolEntry> *MCPEs;
const std::vector<MachineJumpTableEntry> *MJTEs;
bool IsPIC;
+ void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<MachineModuleInfo>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
public:
static char ID;
explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
@@ -163,7 +170,7 @@ namespace {
/// Routines that handle operands which add machine relocations which are
/// fixed up by the relocation stage.
void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
- bool NeedStub, intptr_t ACPV = 0);
+ bool NeedStub, bool Indirect, intptr_t ACPV = 0);
void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
@@ -195,13 +202,15 @@ bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
MF.getTarget().getRelocationModel() != Reloc::Static) &&
"JIT relocation model must be set to static or default!");
+ JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
- JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
+ Subtarget = &TM.getSubtarget<ARMSubtarget>();
MCPEs = &MF.getConstantPool()->getConstants();
MJTEs = &MF.getJumpTableInfo()->getJumpTables();
IsPIC = TM.getRelocationModel() == Reloc::PIC_;
JTI->Initialize(MF, IsPIC);
+ MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
do {
DEBUG(errs() << "JITTing function '"
@@ -244,7 +253,7 @@ unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
else if (MO.isImm())
return static_cast<unsigned>(MO.getImm());
else if (MO.isGlobal())
- emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
+ emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
else if (MO.isSymbol())
emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
else if (MO.isCPI()) {
@@ -270,9 +279,14 @@ unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
///
template<class CodeEmitter>
void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
- bool NeedStub, intptr_t ACPV) {
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
- GV, ACPV, NeedStub));
+ bool NeedStub, bool Indirect,
+ intptr_t ACPV) {
+ MachineRelocation MR = Indirect
+ ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
+ GV, ACPV, NeedStub)
+ : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
+ GV, ACPV, NeedStub);
+ MCE.addRelocation(MR);
}
/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
@@ -417,8 +431,11 @@ void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
GlobalValue *GV = ACPV->getGV();
if (GV) {
+ Reloc::Model RelocM = TM.getRelocationModel();
emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
- isa<Function>(GV), (intptr_t)ACPV);
+ isa<Function>(GV),
+ Subtarget->GVIsIndirectSymbol(GV, RelocM),
+ (intptr_t)ACPV);
} else {
emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
}
@@ -437,7 +454,7 @@ void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
});
if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
- emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
+ emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
emitWordLE(0);
} else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
@@ -579,7 +596,8 @@ void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
unsigned Opcode = MI.getDesc().Opcode;
switch (Opcode) {
default:
- llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
+ llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
+ // FIXME: Add support for MOVimm32.
case TargetInstrInfo::INLINEASM: {
// We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT.
@@ -593,6 +611,7 @@ void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
MCE.emitLabel(MI.getOperand(0).getImm());
break;
case TargetInstrInfo::IMPLICIT_DEF:
+ case TargetInstrInfo::KILL:
case ARM::DWARF_LOC:
// Do nothing.
break;
@@ -949,7 +968,7 @@ static unsigned getAddrModeUPBits(unsigned Mode) {
// DB - Decrement before - bit U = 0 and bit P = 1
switch (Mode) {
default: llvm_unreachable("Unknown addressing sub-mode!");
- case ARM_AM::da: break;
+ case ARM_AM::da: break;
case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
@@ -979,7 +998,7 @@ void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
Binary |= 0x1 << ARMII::W_BitShift;
// Set registers
- for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
+ for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || MO.isImplicit())
break;
@@ -1384,11 +1403,11 @@ void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
Binary |= 0x1 << ARMII::W_BitShift;
// First register is encoded in Dd.
- Binary |= encodeVFPRd(MI, 4);
+ Binary |= encodeVFPRd(MI, 5);
// Number of registers are encoded in offset field.
unsigned NumRegs = 1;
- for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
+ for (unsigned i = 6, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || MO.isImplicit())
break;
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/libclamav/c++/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index c44ea2e..43a823d 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -1359,9 +1359,11 @@ bool ARMConstantIslands::UndoLRSpillRestore() {
bool MadeChange = false;
for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
MachineInstr *MI = PushPopMIs[i];
+ // First two operands are predicates, the third is a zero since there
+ // is no writeback.
if (MI->getOpcode() == ARM::tPOP_RET &&
- MI->getOperand(2).getReg() == ARM::PC &&
- MI->getNumExplicitOperands() == 3) {
+ MI->getOperand(3).getReg() == ARM::PC &&
+ MI->getNumExplicitOperands() == 4) {
BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET));
MI->eraseFromParent();
MadeChange = true;
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp b/libclamav/c++/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp
index 6c8c39f..7170089 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp
@@ -20,11 +20,12 @@
using namespace llvm;
ARMConstantPoolValue::ARMConstantPoolValue(GlobalValue *gv, unsigned id,
+ ARMCP::ARMCPKind K,
unsigned char PCAdj,
const char *Modif,
bool AddCA)
: MachineConstantPoolValue((const Type*)gv->getType()),
- GV(gv), S(NULL), LabelId(id), PCAdjust(PCAdj),
+ GV(gv), S(NULL), LabelId(id), Kind(K), PCAdjust(PCAdj),
Modifier(Modif), AddCurrentAddress(AddCA) {}
ARMConstantPoolValue::ARMConstantPoolValue(LLVMContext &C,
@@ -33,12 +34,12 @@ ARMConstantPoolValue::ARMConstantPoolValue(LLVMContext &C,
const char *Modif,
bool AddCA)
: MachineConstantPoolValue((const Type*)Type::getInt32Ty(C)),
- GV(NULL), S(strdup(s)), LabelId(id), PCAdjust(PCAdj),
+ GV(NULL), S(strdup(s)), LabelId(id), Kind(ARMCP::CPValue), PCAdjust(PCAdj),
Modifier(Modif), AddCurrentAddress(AddCA) {}
ARMConstantPoolValue::ARMConstantPoolValue(GlobalValue *gv, const char *Modif)
: MachineConstantPoolValue((const Type*)Type::getInt32Ty(gv->getContext())),
- GV(gv), S(NULL), LabelId(0), PCAdjust(0),
+ GV(gv), S(NULL), LabelId(0), Kind(ARMCP::CPValue), PCAdjust(0),
Modifier(Modif) {}
int ARMConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP,
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMConstantPoolValue.h b/libclamav/c++/llvm/lib/Target/ARM/ARMConstantPoolValue.h
index 8a0348b..00c4808 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMConstantPoolValue.h
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMConstantPoolValue.h
@@ -21,6 +21,13 @@ namespace llvm {
class GlobalValue;
class LLVMContext;
+namespace ARMCP {
+ enum ARMCPKind {
+ CPValue,
+ CPLSDA
+ };
+}
+
/// ARMConstantPoolValue - ARM specific constantpool value. This is used to
/// represent PC relative displacement between the address of the load
/// instruction and the global value being loaded, i.e. (&GV-(LPIC+8)).
@@ -28,6 +35,7 @@ class ARMConstantPoolValue : public MachineConstantPoolValue {
GlobalValue *GV; // GlobalValue being loaded.
const char *S; // ExtSymbol being loaded.
unsigned LabelId; // Label id of the load.
+ ARMCP::ARMCPKind Kind; // Value or LSDA?
unsigned char PCAdjust; // Extra adjustment if constantpool is pc relative.
// 8 for ARM, 4 for Thumb.
const char *Modifier; // GV modifier i.e. (&GV(modifier)-(LPIC+8))
@@ -35,6 +43,7 @@ class ARMConstantPoolValue : public MachineConstantPoolValue {
public:
ARMConstantPoolValue(GlobalValue *gv, unsigned id,
+ ARMCP::ARMCPKind Kind = ARMCP::CPValue,
unsigned char PCAdj = 0, const char *Modifier = NULL,
bool AddCurrentAddress = false);
ARMConstantPoolValue(LLVMContext &C, const char *s, unsigned id,
@@ -52,6 +61,7 @@ public:
bool mustAddCurrentAddress() const { return AddCurrentAddress; }
unsigned getLabelId() const { return LabelId; }
unsigned char getPCAdjustment() const { return PCAdjust; }
+ bool isLSDA() { return Kind == ARMCP::CPLSDA; }
virtual unsigned getRelocationInfo() const {
// FIXME: This is conservatively claiming that these entries require a
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMFrameInfo.h b/libclamav/c++/llvm/lib/Target/ARM/ARMFrameInfo.h
index d304bc8..d5dae24 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMFrameInfo.h
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMFrameInfo.h
@@ -23,7 +23,7 @@ namespace llvm {
class ARMFrameInfo : public TargetFrameInfo {
public:
explicit ARMFrameInfo(const ARMSubtarget &ST)
- : TargetFrameInfo(StackGrowsDown, ST.getStackAlignment(), 0) {
+ : TargetFrameInfo(StackGrowsDown, ST.getStackAlignment(), 0, 4) {
}
};
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/libclamav/c++/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 97edb97..53f2282 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -49,8 +49,9 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
const ARMSubtarget *Subtarget;
public:
- explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm)
- : SelectionDAGISel(tm), TM(tm),
+ explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
+ CodeGenOpt::Level OptLevel)
+ : SelectionDAGISel(tm, OptLevel), TM(tm),
Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
}
@@ -813,8 +814,8 @@ SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain };
- return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
- MVT::Other, Ops, 6);
+ return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
+ MVT::Other, Ops, 6);
}
return NULL;
@@ -861,8 +862,8 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain };
- return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
- MVT::Other, Ops, 5);
+ return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
+ MVT::Other, Ops, 5);
}
return NULL;
@@ -882,7 +883,7 @@ SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
// instruction that can read and write SP. This matches to a pseudo
// instruction that has a chain to ensure the result is written back to
// the stack pointer.
- SP = SDValue(CurDAG->getTargetNode(ARM::tANDsp, dl, VT, SP, Align), 0);
+ SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0);
bool isC = isa<ConstantSDNode>(Size);
uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
@@ -934,19 +935,21 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case ISD::Constant: {
unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
bool UseCP = true;
- if (Subtarget->isThumb()) {
- if (Subtarget->hasThumb2())
- // Thumb2 has the MOVT instruction, so all immediates can
- // be done with MOV + MOVT, at worst.
- UseCP = 0;
- else
+ if (Subtarget->hasThumb2())
+ // Thumb2-aware targets have the MOVT instruction, so all immediates can
+ // be done with MOV + MOVT, at worst.
+ UseCP = 0;
+ else {
+ if (Subtarget->isThumb()) {
UseCP = (Val > 255 && // MOV
~Val > 255 && // MOV + MVN
!ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
- } else
- UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
- ARM_AM::getSOImmVal(~Val) == -1 && // MVN
- !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
+ } else
+ UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
+ ARM_AM::getSOImmVal(~Val) == -1 && // MVN
+ !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
+ }
+
if (UseCP) {
SDValue CPIdx =
CurDAG->getTargetConstantPool(ConstantInt::get(
@@ -958,8 +961,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
- ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
- Ops, 4);
+ ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
+ Ops, 4);
} else {
SDValue Ops[] = {
CPIdx,
@@ -969,8 +972,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
CurDAG->getRegister(0, MVT::i32),
CurDAG->getEntryNode()
};
- ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
- Ops, 6);
+ ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
+ Ops, 6);
}
ReplaceUses(Op, SDValue(ResNode, 0));
return NULL;
@@ -1038,9 +1041,9 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
}
break;
case ARMISD::FMRRD:
- return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
- Op.getOperand(0), getAL(CurDAG),
- CurDAG->getRegister(0, MVT::i32));
+ return CurDAG->getMachineNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
+ Op.getOperand(0), getAL(CurDAG),
+ CurDAG->getRegister(0, MVT::i32));
case ISD::UMUL_LOHI: {
if (Subtarget->isThumb1Only())
break;
@@ -1048,12 +1051,12 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getTargetNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
+ return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
} else {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
+ return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
}
}
case ISD::SMUL_LOHI: {
@@ -1062,12 +1065,12 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
if (Subtarget->isThumb()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getTargetNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
+ return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
} else {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
+ return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
}
}
case ISD::LOAD: {
@@ -1109,8 +1112,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
cast<ConstantSDNode>(N2)->getZExtValue()),
MVT::i32);
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
- SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
- MVT::Flag, Ops, 5);
+ SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
+ MVT::Flag, Ops, 5);
Chain = SDValue(ResNode, 0);
if (Op.getNode()->getNumValues() == 2) {
InFlag = SDValue(ResNode, 1);
@@ -1277,8 +1280,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VZIPq32; break;
}
- return CurDAG->getTargetNode(Opc, dl, VT, VT,
- N->getOperand(0), N->getOperand(1));
+ return CurDAG->getMachineNode(Opc, dl, VT, VT,
+ N->getOperand(0), N->getOperand(1));
}
case ARMISD::VUZP: {
unsigned Opc = 0;
@@ -1294,8 +1297,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VUZPq32; break;
}
- return CurDAG->getTargetNode(Opc, dl, VT, VT,
- N->getOperand(0), N->getOperand(1));
+ return CurDAG->getMachineNode(Opc, dl, VT, VT,
+ N->getOperand(0), N->getOperand(1));
}
case ARMISD::VTRN: {
unsigned Opc = 0;
@@ -1311,8 +1314,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VTRNq32; break;
}
- return CurDAG->getTargetNode(Opc, dl, VT, VT,
- N->getOperand(0), N->getOperand(1));
+ return CurDAG->getMachineNode(Opc, dl, VT, VT,
+ N->getOperand(0), N->getOperand(1));
}
case ISD::INTRINSIC_VOID:
@@ -1338,7 +1341,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
- return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
+ return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
}
case Intrinsic::arm_neon_vld3: {
@@ -1354,7 +1357,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
- return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
+ return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
}
case Intrinsic::arm_neon_vld4: {
@@ -1372,7 +1375,64 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
std::vector<EVT> ResTys(4, VT);
ResTys.push_back(MVT::Other);
- return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 4);
+ return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
+ }
+
+ case Intrinsic::arm_neon_vld2lane: {
+ SDValue MemAddr, MemUpdate, MemOpc;
+ if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
+ return NULL;
+ switch (VT.getSimpleVT().SimpleTy) {
+ default: llvm_unreachable("unhandled vld2lane type");
+ case MVT::v8i8: Opc = ARM::VLD2LNd8; break;
+ case MVT::v4i16: Opc = ARM::VLD2LNd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD2LNd32; break;
+ }
+ SDValue Chain = N->getOperand(0);
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
+ N->getOperand(3), N->getOperand(4),
+ N->getOperand(5), Chain };
+ return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 7);
+ }
+
+ case Intrinsic::arm_neon_vld3lane: {
+ SDValue MemAddr, MemUpdate, MemOpc;
+ if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
+ return NULL;
+ switch (VT.getSimpleVT().SimpleTy) {
+ default: llvm_unreachable("unhandled vld3lane type");
+ case MVT::v8i8: Opc = ARM::VLD3LNd8; break;
+ case MVT::v4i16: Opc = ARM::VLD3LNd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD3LNd32; break;
+ }
+ SDValue Chain = N->getOperand(0);
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
+ N->getOperand(3), N->getOperand(4),
+ N->getOperand(5), N->getOperand(6), Chain };
+ return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8);
+ }
+
+ case Intrinsic::arm_neon_vld4lane: {
+ SDValue MemAddr, MemUpdate, MemOpc;
+ if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
+ return NULL;
+ switch (VT.getSimpleVT().SimpleTy) {
+ default: llvm_unreachable("unhandled vld4lane type");
+ case MVT::v8i8: Opc = ARM::VLD4LNd8; break;
+ case MVT::v4i16: Opc = ARM::VLD4LNd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD4LNd32; break;
+ }
+ SDValue Chain = N->getOperand(0);
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
+ N->getOperand(3), N->getOperand(4),
+ N->getOperand(5), N->getOperand(6),
+ N->getOperand(7), Chain };
+ std::vector<EVT> ResTys(4, VT);
+ ResTys.push_back(MVT::Other);
+ return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 9);
}
case Intrinsic::arm_neon_vst2: {
@@ -1389,7 +1449,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(3), N->getOperand(4), Chain };
- return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
+ return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6);
}
case Intrinsic::arm_neon_vst3: {
@@ -1407,7 +1467,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(3), N->getOperand(4),
N->getOperand(5), Chain };
- return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
+ return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
}
case Intrinsic::arm_neon_vst4: {
@@ -1425,7 +1485,62 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(3), N->getOperand(4),
N->getOperand(5), N->getOperand(6), Chain };
- return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
+ return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
+ }
+
+ case Intrinsic::arm_neon_vst2lane: {
+ SDValue MemAddr, MemUpdate, MemOpc;
+ if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
+ return NULL;
+ switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
+ default: llvm_unreachable("unhandled vst2lane type");
+ case MVT::v8i8: Opc = ARM::VST2LNd8; break;
+ case MVT::v4i16: Opc = ARM::VST2LNd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VST2LNd32; break;
+ }
+ SDValue Chain = N->getOperand(0);
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
+ N->getOperand(3), N->getOperand(4),
+ N->getOperand(5), Chain };
+ return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
+ }
+
+ case Intrinsic::arm_neon_vst3lane: {
+ SDValue MemAddr, MemUpdate, MemOpc;
+ if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
+ return NULL;
+ switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
+ default: llvm_unreachable("unhandled vst3lane type");
+ case MVT::v8i8: Opc = ARM::VST3LNd8; break;
+ case MVT::v4i16: Opc = ARM::VST3LNd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VST3LNd32; break;
+ }
+ SDValue Chain = N->getOperand(0);
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
+ N->getOperand(3), N->getOperand(4),
+ N->getOperand(5), N->getOperand(6), Chain };
+ return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
+ }
+
+ case Intrinsic::arm_neon_vst4lane: {
+ SDValue MemAddr, MemUpdate, MemOpc;
+ if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
+ return NULL;
+ switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
+ default: llvm_unreachable("unhandled vst4lane type");
+ case MVT::v8i8: Opc = ARM::VST4LNd8; break;
+ case MVT::v4i16: Opc = ARM::VST4LNd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VST4LNd32; break;
+ }
+ SDValue Chain = N->getOperand(0);
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
+ N->getOperand(3), N->getOperand(4),
+ N->getOperand(5), N->getOperand(6),
+ N->getOperand(7), Chain };
+ return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 9);
}
}
}
@@ -1452,6 +1567,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
/// createARMISelDag - This pass converts a legalized DAG into a
/// ARM-specific DAG, ready for instruction scheduling.
///
-FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM) {
- return new ARMDAGToDAGISel(TM);
+FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
+ CodeGenOpt::Level OptLevel) {
+ return new ARMDAGToDAGISel(TM, OptLevel);
}
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMISelLowering.cpp b/libclamav/c++/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 0484fd0..4fa24f3 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -40,6 +40,7 @@
#include "llvm/ADT/VectorExtras.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
+#include <sstream>
using namespace llvm;
static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
@@ -76,6 +77,12 @@ void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
+ if (ElemTy != MVT::i32) {
+ setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
+ setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
+ setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
+ setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
+ }
setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
@@ -98,6 +105,14 @@ void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
PromotedBitwiseVT.getSimpleVT());
}
+
+ // Neon does not support vector divide/remainder operations.
+ setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
+ setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
+ setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
+ setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
+ setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
+ setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
}
void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
@@ -236,6 +251,39 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
addQRTypeForNEON(MVT::v4i32);
addQRTypeForNEON(MVT::v2i64);
+ // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
+ // neither Neon nor VFP support any arithmetic operations on it.
+ setOperationAction(ISD::FADD, MVT::v2f64, Expand);
+ setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
+ setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
+ setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
+ setOperationAction(ISD::FREM, MVT::v2f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
+ setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
+ setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
+ setOperationAction(ISD::FABS, MVT::v2f64, Expand);
+ setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
+ setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
+ setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
+ setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
+ setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
+ setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
+ setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
+ setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
+ setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
+ setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
+ setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
+ setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
+ setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
+ setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
+ setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
+
+ // Neon does not support some operations on v1i64 and v2i64 types.
+ setOperationAction(ISD::MUL, MVT::v1i64, Expand);
+ setOperationAction(ISD::MUL, MVT::v2i64, Expand);
+ setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
+ setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
+
setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
setTargetDAGCombine(ISD::SHL);
setTargetDAGCombine(ISD::SRL);
@@ -494,7 +542,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
/// getFunctionAlignment - Return the Log2 alignment of this function.
unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
- return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
+ return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
}
//===----------------------------------------------------------------------===//
@@ -518,12 +566,9 @@ static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
}
}
-/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
-/// returns true if the operands should be inverted to form the proper
-/// comparison.
-static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
+/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
+static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
ARMCC::CondCodes &CondCode2) {
- bool Invert = false;
CondCode2 = ARMCC::AL;
switch (CC) {
default: llvm_unreachable("Unknown FP condition!");
@@ -534,7 +579,7 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
case ISD::SETGE:
case ISD::SETOGE: CondCode = ARMCC::GE; break;
case ISD::SETOLT: CondCode = ARMCC::MI; break;
- case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
+ case ISD::SETOLE: CondCode = ARMCC::LS; break;
case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
case ISD::SETO: CondCode = ARMCC::VC; break;
case ISD::SETUO: CondCode = ARMCC::VS; break;
@@ -548,7 +593,6 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
case ISD::SETNE:
case ISD::SETUNE: CondCode = ARMCC::NE; break;
}
- return Invert;
}
//===----------------------------------------------------------------------===//
@@ -684,7 +728,7 @@ static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
/// given CallingConvention value.
-CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
+CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
bool Return,
bool isVarArg) const {
switch (CC) {
@@ -714,7 +758,7 @@ CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
/// appropriate copies out of appropriate physical registers.
SDValue
ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) {
@@ -845,7 +889,7 @@ void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
/// nodes.
SDValue
ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -969,7 +1013,8 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
// tBX takes a register source operand.
if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
- ARMPCLabelIndex, 4);
+ ARMPCLabelIndex,
+ ARMCP::CPValue, 4);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), dl,
@@ -1048,7 +1093,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
SDValue
ARMTargetLowering::LowerReturn(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) {
@@ -1166,7 +1211,7 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
- PCAdj, "tlsgd", true);
+ ARMCP::CPValue, PCAdj, "tlsgd", true);
SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
@@ -1208,7 +1253,7 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
- PCAdj, "gottpoff", true);
+ ARMCP::CPValue, PCAdj, "gottpoff", true);
Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
@@ -1284,7 +1329,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
else {
unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
ARMConstantPoolValue *CPV =
- new ARMConstantPoolValue(GV, ARMPCLabelIndex, PCAdj);
+ new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
}
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
@@ -1297,7 +1342,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
- if (Subtarget->GVIsIndirectSymbol(GV, RelocM == Reloc::Static))
+ if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
return Result;
@@ -1348,6 +1393,46 @@ static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
return SDValue();
}
+static SDValue LowerNeonVLDLaneIntrinsic(SDValue Op, SelectionDAG &DAG,
+ unsigned NumVecs) {
+ SDNode *Node = Op.getNode();
+ EVT VT = Node->getValueType(0);
+
+ if (!VT.is64BitVector())
+ return SDValue(); // unimplemented
+
+ // Change the lane number operand to be a TargetConstant; otherwise it
+ // will be legalized into a register.
+ ConstantSDNode *Lane = dyn_cast<ConstantSDNode>(Node->getOperand(NumVecs+3));
+ if (!Lane) {
+ assert(false && "vld lane number must be a constant");
+ return SDValue();
+ }
+ SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
+ Ops[NumVecs+3] = DAG.getTargetConstant(Lane->getZExtValue(), MVT::i32);
+ return DAG.UpdateNodeOperands(Op, &Ops[0], Ops.size());
+}
+
+static SDValue LowerNeonVSTLaneIntrinsic(SDValue Op, SelectionDAG &DAG,
+ unsigned NumVecs) {
+ SDNode *Node = Op.getNode();
+ EVT VT = Node->getOperand(3).getValueType();
+
+ if (!VT.is64BitVector())
+ return SDValue(); // unimplemented
+
+ // Change the lane number operand to be a TargetConstant; otherwise it
+ // will be legalized into a register.
+ ConstantSDNode *Lane = dyn_cast<ConstantSDNode>(Node->getOperand(NumVecs+3));
+ if (!Lane) {
+ assert(false && "vst lane number must be a constant");
+ return SDValue();
+ }
+ SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
+ Ops[NumVecs+3] = DAG.getTargetConstant(Lane->getZExtValue(), MVT::i32);
+ return DAG.UpdateNodeOperands(Op, &Ops[0], Ops.size());
+}
+
SDValue
ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
@@ -1356,10 +1441,22 @@ ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
return LowerNeonVLDIntrinsic(Op, DAG, 3);
case Intrinsic::arm_neon_vld4:
return LowerNeonVLDIntrinsic(Op, DAG, 4);
+ case Intrinsic::arm_neon_vld2lane:
+ return LowerNeonVLDLaneIntrinsic(Op, DAG, 2);
+ case Intrinsic::arm_neon_vld3lane:
+ return LowerNeonVLDLaneIntrinsic(Op, DAG, 3);
+ case Intrinsic::arm_neon_vld4lane:
+ return LowerNeonVLDLaneIntrinsic(Op, DAG, 4);
case Intrinsic::arm_neon_vst3:
return LowerNeonVSTIntrinsic(Op, DAG, 3);
case Intrinsic::arm_neon_vst4:
return LowerNeonVSTIntrinsic(Op, DAG, 4);
+ case Intrinsic::arm_neon_vst2lane:
+ return LowerNeonVSTLaneIntrinsic(Op, DAG, 2);
+ case Intrinsic::arm_neon_vst3lane:
+ return LowerNeonVSTLaneIntrinsic(Op, DAG, 3);
+ case Intrinsic::arm_neon_vst4lane:
+ return LowerNeonVSTLaneIntrinsic(Op, DAG, 4);
default: return SDValue(); // Don't custom lower most intrinsics.
}
}
@@ -1375,10 +1472,6 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
}
case Intrinsic::eh_sjlj_lsda: {
- // blah. horrible, horrible hack with the forced magic name.
- // really need to clean this up. It belongs in the target-independent
- // layer somehow that doesn't require the coupling with the asm
- // printer.
MachineFunction &MF = DAG.getMachineFunction();
EVT PtrVT = getPointerTy();
DebugLoc dl = Op.getDebugLoc();
@@ -1386,13 +1479,9 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
SDValue CPAddr;
unsigned PCAdj = (RelocM != Reloc::PIC_)
? 0 : (Subtarget->isThumb() ? 4 : 8);
- // Save off the LSDA name for the AsmPrinter to use when it's time
- // to emit the table
- std::string LSDAName = "L_lsda_";
- LSDAName += MF.getFunction()->getName();
ARMConstantPoolValue *CPV =
- new ARMConstantPoolValue(*DAG.getContext(), LSDAName.c_str(),
- ARMPCLabelIndex, PCAdj);
+ new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
+ ARMCP::CPLSDA, PCAdj);
CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result =
@@ -1504,7 +1593,7 @@ ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
SDValue
ARMTargetLowering::LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg>
&Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -1768,8 +1857,7 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
}
ARMCC::CondCodes CondCode, CondCode2;
- if (FPCCToARMCC(CC, CondCode, CondCode2))
- std::swap(TrueVal, FalseVal);
+ FPCCToARMCC(CC, CondCode, CondCode2);
SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
@@ -1805,9 +1893,7 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
ARMCC::CondCodes CondCode, CondCode2;
- if (FPCCToARMCC(CC, CondCode, CondCode2))
- // Swap the LHS/RHS of the comparison if needed.
- std::swap(LHS, RHS);
+ FPCCToARMCC(CC, CondCode, CondCode2);
SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
@@ -2040,14 +2126,19 @@ static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
// will be implemented with the NEON VNEG instruction. However, VNEG does
// not support i64 elements, so sometimes the zero vectors will need to be
// explicitly constructed. For those cases, and potentially other uses in
- // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
+ // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
// to their dest type. This ensures they get CSE'd.
SDValue Vec;
- SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
- if (VT.getSizeInBits() == 64)
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
- else
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
+ SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
+ SmallVector<SDValue, 8> Ops;
+ MVT TVT;
+
+ if (VT.getSizeInBits() == 64) {
+ Ops.assign(8, Cst); TVT = MVT::v8i8;
+ } else {
+ Ops.assign(16, Cst); TVT = MVT::v16i8;
+ }
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
@@ -2057,14 +2148,19 @@ static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type");
- // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
- // type. This ensures they get CSE'd.
+ // Always build ones vectors as <16 x i32> or <8 x i32> bitcasted to their
+ // dest type. This ensures they get CSE'd.
SDValue Vec;
- SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
- if (VT.getSizeInBits() == 64)
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
- else
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
+ SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
+ SmallVector<SDValue, 8> Ops;
+ MVT TVT;
+
+ if (VT.getSizeInBits() == 64) {
+ Ops.assign(8, Cst); TVT = MVT::v8i8;
+ } else {
+ Ops.assign(16, Cst); TVT = MVT::v16i8;
+ }
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
@@ -2792,7 +2888,8 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
MachineBasicBlock *
ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
- MachineBasicBlock *BB) const {
+ MachineBasicBlock *BB,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
DebugLoc dl = MI->getDebugLoc();
switch (MI->getOpcode()) {
@@ -2823,12 +2920,15 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
F->insert(It, sinkMBB);
// Update machine-CFG edges by first adding all successors of the current
// block to the new block which will contain the Phi node for the select.
- for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
- e = BB->succ_end(); i != e; ++i)
- sinkMBB->addSuccessor(*i);
+ // Also inform sdisel of the edge changes.
+ for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
+ E = BB->succ_end(); I != E; ++I) {
+ EM->insert(std::make_pair(*I, sinkMBB));
+ sinkMBB->addSuccessor(*I);
+ }
// Next, remove all successors of the current block, and add the true
// and fallthrough blocks as its successors.
- while(!BB->succ_empty())
+ while (!BB->succ_empty())
BB->removeSuccessor(BB->succ_begin());
BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);
@@ -3973,3 +4073,9 @@ void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
Ops, DAG);
}
+
+bool
+ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
+ // The ARM target isn't yet aware of offsets.
+ return false;
+}
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMISelLowering.h b/libclamav/c++/llvm/lib/Target/ARM/ARMISelLowering.h
index 80d1f00..7d85f45 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -160,7 +160,8 @@ namespace llvm {
virtual const char *getTargetNodeName(unsigned Opcode) const;
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
- MachineBasicBlock *MBB) const;
+ MachineBasicBlock *MBB,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) const;
/// allowsUnalignedMemoryAccesses - Returns true if the target allows
/// unaligned memory accesses. of the specified type.
@@ -222,6 +223,7 @@ namespace llvm {
virtual unsigned getFunctionAlignment(const Function *F) const;
bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
+ bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
private:
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
/// make the right decision when generating code for different targets.
@@ -246,7 +248,7 @@ namespace llvm {
SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
- CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return, bool isVarArg) const;
+ CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const;
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
DebugLoc dl, SelectionDAG &DAG,
const CCValAssign &VA,
@@ -273,21 +275,21 @@ namespace llvm {
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff);
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
virtual SDValue
LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
virtual SDValue
LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -296,7 +298,7 @@ namespace llvm {
virtual SDValue
LowerReturn(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG);
};
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrFormats.td b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrFormats.td
index 62e64db..b3c0028 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -984,6 +984,11 @@ class T2JTI<dag oops, dag iops, InstrItinClass itin,
string asm, list<dag> pattern>
: Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
+class T2Ix2<dag oops, dag iops, InstrItinClass itin,
+ string opc, string asm, list<dag> pattern>
+ : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
+
+
// T2Iidxldst - Thumb2 indexed load / store instructions.
class T2Iidxldst<dag oops, dag iops, AddrMode am, IndexMode im,
InstrItinClass itin,
@@ -1070,7 +1075,7 @@ class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
}
// Load / store multiple
-class AXSI5<dag oops, dag iops, InstrItinClass itin,
+class AXDI5<dag oops, dag iops, InstrItinClass itin,
string asm, list<dag> pattern>
: VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
VFPLdStMulFrm, itin, asm, "", pattern> {
@@ -1079,7 +1084,7 @@ class AXSI5<dag oops, dag iops, InstrItinClass itin,
let Inst{11-8} = 0b1011;
}
-class AXDI5<dag oops, dag iops, InstrItinClass itin,
+class AXSI5<dag oops, dag iops, InstrItinClass itin,
string asm, list<dag> pattern>
: VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
VFPLdStMulFrm, itin, asm, "", pattern> {
@@ -1088,7 +1093,6 @@ class AXDI5<dag oops, dag iops, InstrItinClass itin,
let Inst{11-8} = 0b1010;
}
-
// Double precision, unary
class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
InstrItinClass itin, string opc, string asm, list<dag> pattern>
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrInfo.td b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrInfo.td
index 233a4ea..9571ecd 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -100,6 +100,7 @@ def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
+def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
@@ -190,6 +191,27 @@ def bf_inv_mask_imm : Operand<i32>,
let PrintMethod = "printBitfieldInvMaskImmOperand";
}
+/// Split a 32-bit immediate into two 16 bit parts.
+def lo16 : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
+ MVT::i32);
+}]>;
+
+def hi16 : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
+}]>;
+
+def lo16AllZero : PatLeaf<(i32 imm), [{
+ // Returns true if all low 16-bits are 0.
+ return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
+ }], hi16>;
+
+/// imm0_65535 predicate - True if the 32-bit immediate is in the range
+/// [0.65535].
+def imm0_65535 : PatLeaf<(i32 imm), [{
+ return (uint32_t)N->getZExtValue() < 65536;
+}]>;
+
class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
@@ -596,7 +618,7 @@ def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
// Control Flow Instructions.
//
-let isReturn = 1, isTerminator = 1 in
+let isReturn = 1, isTerminator = 1, isBarrier = 1 in
def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
"bx", " lr", [(ARMretflag)]> {
let Inst{7-4} = 0b0001;
@@ -605,13 +627,12 @@ let isReturn = 1, isTerminator = 1 in
}
// FIXME: remove when we have a way to marking a MI with these properties.
-// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
-// operand list.
// FIXME: Should pc be an implicit operand like PICADD, etc?
-let isReturn = 1, isTerminator = 1, mayLoad = 1 in
+let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
+ hasExtraDefRegAllocReq = 1 in
def LDM_RET : AXI4ld<(outs),
- (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
- LdStMulFrm, IIC_Br, "ldm${p}${addr:submode} $addr, $dst1",
+ (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
+ LdStMulFrm, IIC_Br, "ldm${p}${addr:submode} $addr, $wb",
[]>;
// On non-Darwin platforms R9 is callee-saved.
@@ -619,7 +640,7 @@ let isCall = 1,
Defs = [R0, R1, R2, R3, R12, LR,
D0, D1, D2, D3, D4, D5, D6, D7,
D16, D17, D18, D19, D20, D21, D22, D23,
- D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
+ D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
IIC_Br, "bl ${func:call}",
[(ARMcall tglobaladdr:$func)]>,
@@ -656,7 +677,7 @@ let isCall = 1,
Defs = [R0, R1, R2, R3, R9, R12, LR,
D0, D1, D2, D3, D4, D5, D6, D7,
D16, D17, D18, D19, D20, D21, D22, D23,
- D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
+ D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
IIC_Br, "bl ${func:call}",
[(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
@@ -763,7 +784,7 @@ def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoadr, "ldr", "sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
-let mayLoad = 1 in {
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
// Load doubleword
def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoadr, "ldr", "d $dst1, $addr",
@@ -826,7 +847,7 @@ def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
// Store doubleword
-let mayStore = 1 in
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
StMiscFrm, IIC_iStorer,
"str", "d $src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
@@ -878,17 +899,16 @@ def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
// Load / store multiple Instructions.
//
-// FIXME: $dst1 should be a def.
-let mayLoad = 1 in
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
def LDM : AXI4ld<(outs),
- (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
- LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode} $addr, $dst1",
+ (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
+ LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode} $addr, $wb",
[]>;
-let mayStore = 1 in
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def STM : AXI4st<(outs),
- (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
- LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode} $addr, $src1",
+ (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
+ LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode} $addr, $wb",
[]>;
//===----------------------------------------------------------------------===//
@@ -897,15 +917,38 @@ def STM : AXI4st<(outs),
let neverHasSideEffects = 1 in
def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
- "mov", " $dst, $src", []>, UnaryDP;
+ "mov", " $dst, $src", []>, UnaryDP;
def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
- DPSoRegFrm, IIC_iMOVsr,
- "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
+ DPSoRegFrm, IIC_iMOVsr,
+ "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
- "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
+ "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
+ let Inst{25} = 1;
+}
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
+ DPFrm, IIC_iMOVi,
+ "movw", " $dst, $src",
+ [(set GPR:$dst, imm0_65535:$src)]>,
+ Requires<[IsARM, HasV6T2]> {
+ let Inst{25} = 1;
+}
+
+let Constraints = "$src = $dst" in
+def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
+ DPFrm, IIC_iMOVi,
+ "movt", " $dst, $imm",
+ [(set GPR:$dst,
+ (or (and GPR:$src, 0xffff),
+ lo16AllZero:$imm))]>, UnaryDP,
+ Requires<[IsARM, HasV6T2]> {
+ let Inst{25} = 1;
+}
+
+let Uses = [CPSR] in
def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
"mov", " $dst, $src, rrx",
[(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
@@ -989,7 +1032,9 @@ defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
// These don't define reg/reg forms, because they are handled above.
def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALUi, "rsb", " $dst, $a, $b",
- [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
+ [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
+ let Inst{25} = 1;
+}
def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALUsr, "rsb", " $dst, $a, $b",
@@ -999,7 +1044,9 @@ def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
let Defs = [CPSR] in {
def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALUi, "rsb", "s $dst, $a, $b",
- [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
+ [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
+ let Inst{25} = 1;
+}
def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALUsr, "rsb", "s $dst, $a, $b",
[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
@@ -1009,7 +1056,9 @@ let Uses = [CPSR] in {
def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
DPFrm, IIC_iALUi, "rsc", " $dst, $a, $b",
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
- Requires<[IsARM, CarryDefIsUnused]>;
+ Requires<[IsARM, CarryDefIsUnused]> {
+ let Inst{25} = 1;
+}
def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALUsr, "rsc", " $dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
@@ -1021,7 +1070,9 @@ let Defs = [CPSR], Uses = [CPSR] in {
def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
DPFrm, IIC_iALUi, "rscs $dst, $a, $b",
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
- Requires<[IsARM, CarryDefIsUnused]>;
+ Requires<[IsARM, CarryDefIsUnused]> {
+ let Inst{25} = 1;
+}
def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALUsr, "rscs $dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
@@ -1075,7 +1126,9 @@ def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
IIC_iMOVi, "mvn", " $dst, $imm",
- [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
+ [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
+ let Inst{25} = 1;
+}
def : ARMPat<(and GPR:$src, so_imm_not:$imm),
(BICri GPR:$src, so_imm_not:$imm)>;
@@ -1393,7 +1446,9 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
(ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
"mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
- RegConstraint<"$false = $dst">, UnaryDP;
+ RegConstraint<"$false = $dst">, UnaryDP {
+ let Inst{25} = 1;
+}
//===----------------------------------------------------------------------===//
@@ -1454,7 +1509,8 @@ let isReMaterializable = 1 in
def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
Pseudo, IIC_iMOVi,
"mov", " $dst, $src",
- [(set GPR:$dst, so_imm2part:$src)]>;
+ [(set GPR:$dst, so_imm2part:$src)]>,
+ Requires<[IsARM, NoV6T2]>;
def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
(ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
@@ -1463,6 +1519,15 @@ def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
(EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
(so_imm2part_2 imm:$RHS))>;
+// 32-bit immediate using movw + movt.
+// This is a single pseudo instruction to make it re-materializable. Remove
+// when we can do generalized remat.
+let isReMaterializable = 1 in
+def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
+ "movw", " $dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
+ [(set GPR:$dst, (i32 imm:$src))]>,
+ Requires<[IsARM, HasV6T2]>;
+
// TODO: add,sub,and, 3-instr forms?
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrNEON.td b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrNEON.td
index c278e8b..57af2c1 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -107,10 +107,10 @@ def addrmode_neonldstm : Operand<i32>,
//===----------------------------------------------------------------------===//
/* TODO: Take advantage of vldm.
-let mayLoad = 1 in {
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
def VLDMD : NI<(outs),
(ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
- NoItinerary,
+ IIC_fpLoadm,
"vldm${addr:submode} ${addr:base}, $dst1",
[]> {
let Inst{27-25} = 0b110;
@@ -120,7 +120,7 @@ def VLDMD : NI<(outs),
def VLDMS : NI<(outs),
(ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
- NoItinerary,
+ IIC_fpLoadm,
"vldm${addr:submode} ${addr:base}, $dst1",
[]> {
let Inst{27-25} = 0b110;
@@ -132,7 +132,7 @@ def VLDMS : NI<(outs),
// Use vldmia to load a Q register as a D register pair.
def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
- NoItinerary,
+ IIC_fpLoadm,
"vldmia $addr, ${dst:dregpair}",
[(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
let Inst{27-25} = 0b110;
@@ -144,7 +144,7 @@ def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
// Use vstmia to store a Q register as a D register pair.
def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
- NoItinerary,
+ IIC_fpStorem,
"vstmia $addr, ${src:dregpair}",
[(store (v2f64 QPR:$src), addrmode4:$addr)]> {
let Inst{27-25} = 0b110;
@@ -156,11 +156,11 @@ def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
// VLD1 : Vector Load (multiple single elements)
class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
- : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr), NoItinerary,
+ : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
!strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "",
[(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
- : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr), NoItinerary,
+ : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD1,
!strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "",
[(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
@@ -176,11 +176,11 @@ def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
-let mayLoad = 1 in {
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
// VLD2 : Vector Load (multiple 2-element structures)
class VLD2D<string OpcodeStr>
- : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr), NoItinerary,
+ : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr), IIC_VLD2,
!strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>;
def VLD2d8 : VLD2D<"vld2.8">;
@@ -190,7 +190,7 @@ def VLD2d32 : VLD2D<"vld2.32">;
// VLD3 : Vector Load (multiple 3-element structures)
class VLD3D<string OpcodeStr>
: NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
- NoItinerary,
+ IIC_VLD3,
!strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>;
def VLD3d8 : VLD3D<"vld3.8">;
@@ -200,25 +200,64 @@ def VLD3d32 : VLD3D<"vld3.32">;
// VLD4 : Vector Load (multiple 4-element structures)
class VLD4D<string OpcodeStr>
: NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
- (ins addrmode6:$addr), NoItinerary,
+ (ins addrmode6:$addr), IIC_VLD4,
!strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
"", []>;
def VLD4d8 : VLD4D<"vld4.8">;
def VLD4d16 : VLD4D<"vld4.16">;
def VLD4d32 : VLD4D<"vld4.32">;
-}
+
+// VLD2LN : Vector Load (single 2-element structure to one lane)
+class VLD2LND<string OpcodeStr>
+ : NLdSt<(outs DPR:$dst1, DPR:$dst2),
+ (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
+ IIC_VLD2,
+ !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"),
+ "$src1 = $dst1, $src2 = $dst2", []>;
+
+def VLD2LNd8 : VLD2LND<"vld2.8">;
+def VLD2LNd16 : VLD2LND<"vld2.16">;
+def VLD2LNd32 : VLD2LND<"vld2.32">;
+
+// VLD3LN : Vector Load (single 3-element structure to one lane)
+class VLD3LND<string OpcodeStr>
+ : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
+ (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
+ nohash_imm:$lane), IIC_VLD3,
+ !strconcat(OpcodeStr,
+ "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
+ "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
+
+def VLD3LNd8 : VLD3LND<"vld3.8">;
+def VLD3LNd16 : VLD3LND<"vld3.16">;
+def VLD3LNd32 : VLD3LND<"vld3.32">;
+
+// VLD4LN : Vector Load (single 4-element structure to one lane)
+class VLD4LND<string OpcodeStr>
+ : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
+ (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
+ nohash_imm:$lane), IIC_VLD4,
+ !strconcat(OpcodeStr,
+ "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"),
+ "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
+
+def VLD4LNd8 : VLD4LND<"vld4.8">;
+def VLD4LNd16 : VLD4LND<"vld4.16">;
+def VLD4LNd32 : VLD4LND<"vld4.32">;
+} // mayLoad = 1, hasExtraDefRegAllocReq = 1
// VST1 : Vector Store (multiple single elements)
class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
- : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src), NoItinerary,
+ : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
!strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "",
[(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
- : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src), NoItinerary,
+ : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src), IIC_VST,
!strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
[(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
+let hasExtraSrcRegAllocReq = 1 in {
def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
@@ -230,12 +269,13 @@ def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1>;
def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
+} // hasExtraSrcRegAllocReq
-let mayStore = 1 in {
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
// VST2 : Vector Store (multiple 2-element structures)
class VST2D<string OpcodeStr>
- : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
+ : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST,
!strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>;
def VST2d8 : VST2D<"vst2.8">;
@@ -245,7 +285,7 @@ def VST2d32 : VST2D<"vst2.32">;
// VST3 : Vector Store (multiple 3-element structures)
class VST3D<string OpcodeStr>
: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
- NoItinerary,
+ IIC_VST,
!strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>;
def VST3d8 : VST3D<"vst3.8">;
@@ -255,14 +295,48 @@ def VST3d32 : VST3D<"vst3.32">;
// VST4 : Vector Store (multiple 4-element structures)
class VST4D<string OpcodeStr>
: NLdSt<(outs), (ins addrmode6:$addr,
- DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
+ DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
!strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
"", []>;
def VST4d8 : VST4D<"vst4.8">;
def VST4d16 : VST4D<"vst4.16">;
def VST4d32 : VST4D<"vst4.32">;
-}
+
+// VST2LN : Vector Store (single 2-element structure from one lane)
+class VST2LND<string OpcodeStr>
+ : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
+ IIC_VST,
+ !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"),
+ "", []>;
+
+def VST2LNd8 : VST2LND<"vst2.8">;
+def VST2LNd16 : VST2LND<"vst2.16">;
+def VST2LNd32 : VST2LND<"vst2.32">;
+
+// VST3LN : Vector Store (single 3-element structure from one lane)
+class VST3LND<string OpcodeStr>
+ : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
+ nohash_imm:$lane), IIC_VST,
+ !strconcat(OpcodeStr,
+ "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>;
+
+def VST3LNd8 : VST3LND<"vst3.8">;
+def VST3LNd16 : VST3LND<"vst3.16">;
+def VST3LNd32 : VST3LND<"vst3.32">;
+
+// VST4LN : Vector Store (single 4-element structure from one lane)
+class VST4LND<string OpcodeStr>
+ : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
+ DPR:$src4, nohash_imm:$lane), IIC_VST,
+ !strconcat(OpcodeStr,
+ "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"),
+ "", []>;
+
+def VST4LNd8 : VST4LND<"vst4.8">;
+def VST4LNd16 : VST4LND<"vst4.16">;
+def VST4LNd32 : VST4LND<"vst4.32">;
+} // mayStore = 1, hasExtraSrcRegAllocReq = 1
//===----------------------------------------------------------------------===//
@@ -283,6 +357,9 @@ def DSubReg_i32_reg : SDNodeXForm<imm, [{
def DSubReg_f64_reg : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
}]>;
+def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
+}]>;
// Extract S sub-registers of Q/D registers.
// (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
@@ -310,13 +387,13 @@ class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
ValueType ResTy, ValueType OpTy, SDNode OpNode>
: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
- (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
+ (ins DPR:$src), IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
ValueType ResTy, ValueType OpTy, SDNode OpNode>
: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
- (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
+ (ins QPR:$src), IIC_VUNAQ, !strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
// Basic 2-register operations, scalar single-precision.
@@ -325,7 +402,7 @@ class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
ValueType ResTy, ValueType OpTy, SDNode OpNode>
: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
(outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
- NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
+ IIC_VUNAD, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
: NEONFPPat<(ResTy (OpNode SPR:$a)),
@@ -335,24 +412,27 @@ class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
// Basic 2-register intrinsics, both double- and quad-register.
class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
- bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
+ bits<2> op17_16, bits<5> op11_7, bit op4,
+ InstrItinClass itin, string OpcodeStr,
ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
- (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
+ (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
- bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
+ bits<2> op17_16, bits<5> op11_7, bit op4,
+ InstrItinClass itin, string OpcodeStr,
ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
- (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
+ (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
// Basic 2-register intrinsics, scalar single-precision
class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
- bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
+ bits<2> op17_16, bits<5> op11_7, bit op4,
+ InstrItinClass itin, string OpcodeStr,
ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
- (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
+ (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), itin,
!strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
class N2VDIntsPat<SDNode OpNode, NeonI Inst>
@@ -364,58 +444,108 @@ class N2VDIntsPat<SDNode OpNode, NeonI Inst>
// Narrow 2-register intrinsics.
class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
- string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
+ InstrItinClass itin, string OpcodeStr,
+ ValueType TyD, ValueType TyQ, Intrinsic IntOp>
: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
- (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
+ (ins QPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
// Long 2-register intrinsics. (This is currently only used for VMOVL and is
// derived from N2VImm instead of N2V because of the way the size is encoded.)
class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
- bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
- Intrinsic IntOp>
+ bit op6, bit op4, InstrItinClass itin, string OpcodeStr,
+ ValueType TyQ, ValueType TyD, Intrinsic IntOp>
: N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
- (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
+ (ins DPR:$src), itin, !strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
// 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
: N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
- (ins DPR:$src1, DPR:$src2), NoItinerary,
+ (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
!strconcat(OpcodeStr, "\t$dst1, $dst2"),
"$src1 = $dst1, $src2 = $dst2", []>;
-class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
+class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
+ InstrItinClass itin, string OpcodeStr>
: N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
- (ins QPR:$src1, QPR:$src2), NoItinerary,
+ (ins QPR:$src1, QPR:$src2), itin,
!strconcat(OpcodeStr, "\t$dst1, $dst2"),
"$src1 = $dst1, $src2 = $dst2", []>;
// Basic 3-register operations, both double- and quad-register.
class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
- string OpcodeStr, ValueType ResTy, ValueType OpTy,
+ InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
SDNode OpNode, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
!strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
[(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
let isCommutable = Commutable;
}
+class N3VDSL<bits<2> op21_20, bits<4> op11_8,
+ InstrItinClass itin, string OpcodeStr, ValueType Ty, SDNode ShOp>
+ : N3V<0, 1, op21_20, op11_8, 1, 0,
+ (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
+ itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
+ [(set (Ty DPR:$dst),
+ (Ty (ShOp (Ty DPR:$src1),
+ (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
+ imm:$lane)))))]> {
+ let isCommutable = 0;
+}
+class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
+ string OpcodeStr, ValueType Ty, SDNode ShOp>
+ : N3V<0, 1, op21_20, op11_8, 1, 0,
+ (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
+ IIC_VMULi16D,
+ !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
+ [(set (Ty DPR:$dst),
+ (Ty (ShOp (Ty DPR:$src1),
+ (Ty (NEONvduplane (Ty DPR_8:$src2),
+ imm:$lane)))))]> {
+ let isCommutable = 0;
+}
+
class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
- string OpcodeStr, ValueType ResTy, ValueType OpTy,
+ InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
SDNode OpNode, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 1, op4,
- (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
+ (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
!strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
[(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
let isCommutable = Commutable;
}
+class N3VQSL<bits<2> op21_20, bits<4> op11_8,
+ InstrItinClass itin, string OpcodeStr,
+ ValueType ResTy, ValueType OpTy, SDNode ShOp>
+ : N3V<1, 1, op21_20, op11_8, 1, 0,
+ (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
+ itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
+ [(set (ResTy QPR:$dst),
+ (ResTy (ShOp (ResTy QPR:$src1),
+ (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
+ imm:$lane)))))]> {
+ let isCommutable = 0;
+}
+class N3VQSL16<bits<2> op21_20, bits<4> op11_8,
+ string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode ShOp>
+ : N3V<1, 1, op21_20, op11_8, 1, 0,
+ (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
+ IIC_VMULi16Q,
+ !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
+ [(set (ResTy QPR:$dst),
+ (ResTy (ShOp (ResTy QPR:$src1),
+ (ResTy (NEONvduplane (OpTy DPR_8:$src2),
+ imm:$lane)))))]> {
+ let isCommutable = 0;
+}
// Basic 3-register operations, scalar single-precision
class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
string OpcodeStr, ValueType ResTy, ValueType OpTy,
SDNode OpNode, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
+ (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), IIC_VBIND,
!strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
let isCommutable = Commutable;
}
@@ -428,46 +558,141 @@ class N3VDsPat<SDNode OpNode, NeonI Inst>
// Basic 3-register intrinsics, both double- and quad-register.
class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
- string OpcodeStr, ValueType ResTy, ValueType OpTy,
+ InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
Intrinsic IntOp, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
!strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
[(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
let isCommutable = Commutable;
}
+class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType Ty, Intrinsic IntOp>
+ : N3V<0, 1, op21_20, op11_8, 1, 0,
+ (outs DPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
+ itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
+ [(set (Ty DPR:$dst),
+ (Ty (IntOp (Ty DPR:$src1),
+ (Ty (NEONvduplane (Ty DPR_VFP2:$src2),
+ imm:$lane)))))]> {
+ let isCommutable = 0;
+}
+class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType Ty, Intrinsic IntOp>
+ : N3V<0, 1, op21_20, op11_8, 1, 0,
+ (outs DPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
+ itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
+ [(set (Ty DPR:$dst),
+ (Ty (IntOp (Ty DPR:$src1),
+ (Ty (NEONvduplane (Ty DPR_8:$src2),
+ imm:$lane)))))]> {
+ let isCommutable = 0;
+}
+
class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
- string OpcodeStr, ValueType ResTy, ValueType OpTy,
+ InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy,
Intrinsic IntOp, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 1, op4,
- (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
+ (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), itin,
!strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
[(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
let isCommutable = Commutable;
}
+class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
+ : N3V<1, 1, op21_20, op11_8, 1, 0,
+ (outs QPR:$dst), (ins QPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
+ itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
+ [(set (ResTy QPR:$dst),
+ (ResTy (IntOp (ResTy QPR:$src1),
+ (ResTy (NEONvduplane (OpTy DPR_VFP2:$src2),
+ imm:$lane)))))]> {
+ let isCommutable = 0;
+}
+class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
+ : N3V<1, 1, op21_20, op11_8, 1, 0,
+ (outs QPR:$dst), (ins QPR:$src1, DPR_8:$src2, nohash_imm:$lane),
+ itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
+ [(set (ResTy QPR:$dst),
+ (ResTy (IntOp (ResTy QPR:$src1),
+ (ResTy (NEONvduplane (OpTy DPR_8:$src2),
+ imm:$lane)))))]> {
+ let isCommutable = 0;
+}
// Multiply-Add/Sub operations, both double- and quad-register.
class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
- string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
+ InstrItinClass itin, string OpcodeStr,
+ ValueType Ty, SDNode MulOp, SDNode OpNode>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
!strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
[(set DPR:$dst, (Ty (OpNode DPR:$src1,
(Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
+class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
+ : N3V<0, 1, op21_20, op11_8, 1, 0,
+ (outs DPR:$dst),
+ (ins DPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
+ !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
+ [(set (Ty DPR:$dst),
+ (Ty (ShOp (Ty DPR:$src1),
+ (Ty (MulOp DPR:$src2,
+ (Ty (NEONvduplane (Ty DPR_VFP2:$src3),
+ imm:$lane)))))))]>;
+class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode ShOp>
+ : N3V<0, 1, op21_20, op11_8, 1, 0,
+ (outs DPR:$dst),
+ (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
+ !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
+ [(set (Ty DPR:$dst),
+ (Ty (ShOp (Ty DPR:$src1),
+ (Ty (MulOp DPR:$src2,
+ (Ty (NEONvduplane (Ty DPR_8:$src3),
+ imm:$lane)))))))]>;
+
class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
- string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
+ InstrItinClass itin, string OpcodeStr, ValueType Ty,
+ SDNode MulOp, SDNode OpNode>
: N3V<op24, op23, op21_20, op11_8, 1, op4,
- (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
+ (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
!strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
[(set QPR:$dst, (Ty (OpNode QPR:$src1,
(Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
+class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType ResTy, ValueType OpTy,
+ SDNode MulOp, SDNode ShOp>
+ : N3V<1, 1, op21_20, op11_8, 1, 0,
+ (outs QPR:$dst),
+ (ins QPR:$src1, QPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
+ !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
+ [(set (ResTy QPR:$dst),
+ (ResTy (ShOp (ResTy QPR:$src1),
+ (ResTy (MulOp QPR:$src2,
+ (ResTy (NEONvduplane (OpTy DPR_VFP2:$src3),
+ imm:$lane)))))))]>;
+class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType ResTy, ValueType OpTy,
+ SDNode MulOp, SDNode ShOp>
+ : N3V<1, 1, op21_20, op11_8, 1, 0,
+ (outs QPR:$dst),
+ (ins QPR:$src1, QPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
+ !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
+ [(set (ResTy QPR:$dst),
+ (ResTy (ShOp (ResTy QPR:$src1),
+ (ResTy (MulOp QPR:$src2,
+ (ResTy (NEONvduplane (OpTy DPR_8:$src3),
+ imm:$lane)))))))]>;
// Multiply-Add/Sub operations, scalar single-precision
class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
- string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
+ InstrItinClass itin, string OpcodeStr,
+ ValueType Ty, SDNode MulOp, SDNode OpNode>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
(outs DPR_VFP2:$dst),
- (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
+ (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), itin,
!strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
@@ -481,18 +706,18 @@ class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
// Neon 3-argument intrinsics, both double- and quad-register.
// The destination register is also used as the first source operand register.
class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
- string OpcodeStr, ValueType ResTy, ValueType OpTy,
- Intrinsic IntOp>
+ InstrItinClass itin, string OpcodeStr,
+ ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), itin,
!strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
[(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
(OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
- string OpcodeStr, ValueType ResTy, ValueType OpTy,
- Intrinsic IntOp>
+ InstrItinClass itin, string OpcodeStr,
+ ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
: N3V<op24, op23, op21_20, op11_8, 1, op4,
- (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
+ (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), itin,
!strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
[(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
(OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
@@ -500,19 +725,44 @@ class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
// Neon Long 3-argument intrinsic. The destination register is
// a quad-register and is also used as the first source operand register.
class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
- string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
+ InstrItinClass itin, string OpcodeStr,
+ ValueType TyQ, ValueType TyD, Intrinsic IntOp>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
+ (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), itin,
!strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
[(set QPR:$dst,
(TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
+class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
+ : N3V<op24, 1, op21_20, op11_8, 1, 0,
+ (outs QPR:$dst),
+ (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), itin,
+ !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
+ [(set (ResTy QPR:$dst),
+ (ResTy (IntOp (ResTy QPR:$src1),
+ (OpTy DPR:$src2),
+ (OpTy (NEONvduplane (OpTy DPR_VFP2:$src3),
+ imm:$lane)))))]>;
+class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType ResTy, ValueType OpTy,
+ Intrinsic IntOp>
+ : N3V<op24, 1, op21_20, op11_8, 1, 0,
+ (outs QPR:$dst),
+ (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), itin,
+ !strconcat(OpcodeStr, "\t$dst, $src2, $src3[$lane]"), "$src1 = $dst",
+ [(set (ResTy QPR:$dst),
+ (ResTy (IntOp (ResTy QPR:$src1),
+ (OpTy DPR:$src2),
+ (OpTy (NEONvduplane (OpTy DPR_8:$src3),
+ imm:$lane)))))]>;
+
// Narrowing 3-register intrinsics.
class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
string OpcodeStr, ValueType TyD, ValueType TyQ,
Intrinsic IntOp, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
+ (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VBINi4D,
!strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
[(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
let isCommutable = Commutable;
@@ -520,21 +770,40 @@ class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
// Long 3-register intrinsics.
class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
- string OpcodeStr, ValueType TyQ, ValueType TyD,
+ InstrItinClass itin, string OpcodeStr, ValueType TyQ, ValueType TyD,
Intrinsic IntOp, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
+ (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), itin,
!strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
[(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
let isCommutable = Commutable;
}
+class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
+ : N3V<op24, 1, op21_20, op11_8, 1, 0,
+ (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, nohash_imm:$lane),
+ itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
+ [(set (ResTy QPR:$dst),
+ (ResTy (IntOp (OpTy DPR:$src1),
+ (OpTy (NEONvduplane (OpTy DPR_VFP2:$src2),
+ imm:$lane)))))]>;
+class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
+ string OpcodeStr, ValueType ResTy, ValueType OpTy,
+ Intrinsic IntOp>
+ : N3V<op24, 1, op21_20, op11_8, 1, 0,
+ (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane),
+ itin, !strconcat(OpcodeStr, "\t$dst, $src1, $src2[$lane]"), "",
+ [(set (ResTy QPR:$dst),
+ (ResTy (IntOp (OpTy DPR:$src1),
+ (OpTy (NEONvduplane (OpTy DPR_8:$src2),
+ imm:$lane)))))]>;
// Wide 3-register intrinsics.
class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
string OpcodeStr, ValueType TyQ, ValueType TyD,
Intrinsic IntOp, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
+ (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), IIC_VSUBiD,
!strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
[(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
let isCommutable = Commutable;
@@ -545,13 +814,13 @@ class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
- (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
+ (ins DPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
- (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
+ (ins QPR:$src), IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
// Pairwise long 2-register accumulate intrinsics,
@@ -561,29 +830,31 @@ class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
- (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
!strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
[(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
: N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
- (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
+ (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
!strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
[(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
// Shift by immediate,
// both double- and quad-register.
class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
- bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
+ bit op4, InstrItinClass itin, string OpcodeStr,
+ ValueType Ty, SDNode OpNode>
: N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
- (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), itin,
!strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
[(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
- bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
+ bit op4, InstrItinClass itin, string OpcodeStr,
+ ValueType Ty, SDNode OpNode>
: N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
- (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
+ (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
!strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
[(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
@@ -592,17 +863,17 @@ class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
bit op6, bit op4, string OpcodeStr, ValueType ResTy,
ValueType OpTy, SDNode OpNode>
: N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
- (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
+ (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VSHLiD,
!strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
[(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
(i32 imm:$SIMM))))]>;
// Narrow shift by immediate.
class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
- bit op6, bit op4, string OpcodeStr, ValueType ResTy,
- ValueType OpTy, SDNode OpNode>
+ bit op6, bit op4, InstrItinClass itin, string OpcodeStr,
+ ValueType ResTy, ValueType OpTy, SDNode OpNode>
: N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
- (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
+ (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), itin,
!strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
[(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
(i32 imm:$SIMM))))]>;
@@ -613,7 +884,7 @@ class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
: N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
(outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
- NoItinerary,
+ IIC_VPALiD,
!strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
[(set DPR:$dst, (Ty (add DPR:$src1,
(Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
@@ -621,7 +892,7 @@ class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
: N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
(outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
- NoItinerary,
+ IIC_VPALiD,
!strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
[(set QPR:$dst, (Ty (add QPR:$src1,
(Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
@@ -632,14 +903,14 @@ class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
: N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
(outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
- NoItinerary,
+ IIC_VSHLiD,
!strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
[(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
: N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
(outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
- NoItinerary,
+ IIC_VSHLiQ,
!strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
[(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
@@ -649,14 +920,14 @@ class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
Intrinsic IntOp>
: N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
- (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), IIC_VUNAD,
!strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
[(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
Intrinsic IntOp>
: N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
- (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
+ (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), IIC_VUNAQ,
!strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
[(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
@@ -668,46 +939,58 @@ class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
// First with only element sizes of 8, 16 and 32 bits:
multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
+ InstrItinClass itinD16, InstrItinClass itinD32,
+ InstrItinClass itinQ16, InstrItinClass itinQ32,
string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
// 64-bit vector types.
- def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
- v8i8, v8i8, OpNode, Commutable>;
- def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
- v4i16, v4i16, OpNode, Commutable>;
- def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
- v2i32, v2i32, OpNode, Commutable>;
+ def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
+ !strconcat(OpcodeStr, "8"), v8i8, v8i8, OpNode, Commutable>;
+ def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
+ !strconcat(OpcodeStr, "16"), v4i16, v4i16, OpNode, Commutable>;
+ def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
+ !strconcat(OpcodeStr, "32"), v2i32, v2i32, OpNode, Commutable>;
// 128-bit vector types.
- def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
- v16i8, v16i8, OpNode, Commutable>;
- def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
- v8i16, v8i16, OpNode, Commutable>;
- def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
- v4i32, v4i32, OpNode, Commutable>;
+ def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
+ !strconcat(OpcodeStr, "8"), v16i8, v16i8, OpNode, Commutable>;
+ def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
+ !strconcat(OpcodeStr, "16"), v8i16, v8i16, OpNode, Commutable>;
+ def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
+ !strconcat(OpcodeStr, "32"), v4i32, v4i32, OpNode, Commutable>;
+}
+
+multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
+ def v4i16 : N3VDSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
+ def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
+ def v8i16 : N3VQSL16<0b01, op11_8, !strconcat(OpcodeStr, "16"), v8i16, v4i16, ShOp>;
+ def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, !strconcat(OpcodeStr, "32"), v4i32, v2i32, ShOp>;
}
// ....then also with element size 64 bits:
multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
+ InstrItinClass itinD, InstrItinClass itinQ,
string OpcodeStr, SDNode OpNode, bit Commutable = 0>
- : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
- def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
- v1i64, v1i64, OpNode, Commutable>;
- def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
- v2i64, v2i64, OpNode, Commutable>;
+ : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
+ OpcodeStr, OpNode, Commutable> {
+ def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
+ !strconcat(OpcodeStr, "64"), v1i64, v1i64, OpNode, Commutable>;
+ def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
+ !strconcat(OpcodeStr, "64"), v2i64, v2i64, OpNode, Commutable>;
}
// Neon Narrowing 2-register vector intrinsics,
// source operand element sizes of 16, 32 and 64 bits:
multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
- bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
+ bits<5> op11_7, bit op6, bit op4,
+ InstrItinClass itin, string OpcodeStr,
Intrinsic IntOp> {
def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
- !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
+ itin, !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
- !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
+ itin, !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
- !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
+ itin, !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
}
@@ -716,11 +999,11 @@ multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
bit op4, string OpcodeStr, Intrinsic IntOp> {
def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
- !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
+ IIC_VQUNAiD, !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
- !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
+ IIC_VQUNAiD, !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
- !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
+ IIC_VQUNAiD, !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
}
@@ -728,38 +1011,56 @@ multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
// First with only element sizes of 16 and 32 bits:
multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
+ InstrItinClass itinD16, InstrItinClass itinD32,
+ InstrItinClass itinQ16, InstrItinClass itinQ32,
string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
// 64-bit vector types.
- def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
+ def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, itinD16, !strconcat(OpcodeStr,"16"),
v4i16, v4i16, IntOp, Commutable>;
- def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
+ def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, itinD32, !strconcat(OpcodeStr,"32"),
v2i32, v2i32, IntOp, Commutable>;
// 128-bit vector types.
- def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
+ def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, itinQ16, !strconcat(OpcodeStr,"16"),
v8i16, v8i16, IntOp, Commutable>;
- def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
+ def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, itinQ32, !strconcat(OpcodeStr,"32"),
v4i32, v4i32, IntOp, Commutable>;
}
+multiclass N3VIntSL_HS<bits<4> op11_8,
+ InstrItinClass itinD16, InstrItinClass itinD32,
+ InstrItinClass itinQ16, InstrItinClass itinQ32,
+ string OpcodeStr, Intrinsic IntOp> {
+ def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, !strconcat(OpcodeStr, "16"), v4i16, IntOp>;
+ def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, !strconcat(OpcodeStr, "32"), v2i32, IntOp>;
+ def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, !strconcat(OpcodeStr, "16"), v8i16, v4i16, IntOp>;
+ def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, !strconcat(OpcodeStr, "32"), v4i32, v2i32, IntOp>;
+}
+
// ....then also with element size of 8 bits:
multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
+ InstrItinClass itinD16, InstrItinClass itinD32,
+ InstrItinClass itinQ16, InstrItinClass itinQ32,
string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
- : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
- def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
- v8i8, v8i8, IntOp, Commutable>;
- def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
- v16i8, v16i8, IntOp, Commutable>;
+ : N3VInt_HS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
+ OpcodeStr, IntOp, Commutable> {
+ def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, itinD16,
+ !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp, Commutable>;
+ def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, itinQ16,
+ !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp, Commutable>;
}
// ....then also with element size of 64 bits:
multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
+ InstrItinClass itinD16, InstrItinClass itinD32,
+ InstrItinClass itinQ16, InstrItinClass itinQ32,
string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
- : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
- def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
- v1i64, v1i64, IntOp, Commutable>;
- def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
- v2i64, v2i64, IntOp, Commutable>;
+ : N3VInt_QHS<op24, op23, op11_8, op4, itinD16, itinD32, itinQ16, itinQ32,
+ OpcodeStr, IntOp, Commutable> {
+ def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, itinD32,
+ !strconcat(OpcodeStr,"64"), v1i64, v1i64, IntOp, Commutable>;
+ def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, itinQ32,
+ !strconcat(OpcodeStr,"64"), v2i64, v2i64, IntOp, Commutable>;
}
@@ -780,19 +1081,29 @@ multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
// First with only element sizes of 16 and 32 bits:
multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
- string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
- def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
- v4i32, v4i16, IntOp, Commutable>;
- def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
- v2i64, v2i32, IntOp, Commutable>;
+ InstrItinClass itin, string OpcodeStr,
+ Intrinsic IntOp, bit Commutable = 0> {
+ def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin,
+ !strconcat(OpcodeStr,"16"), v4i32, v4i16, IntOp, Commutable>;
+ def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin,
+ !strconcat(OpcodeStr,"32"), v2i64, v2i32, IntOp, Commutable>;
+}
+
+multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
+ InstrItinClass itin, string OpcodeStr, Intrinsic IntOp> {
+ def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
+ !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
+ def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
+ !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
}
// ....then also with element size of 8 bits:
multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
- string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
- : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
- def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
- v8i16, v8i8, IntOp, Commutable>;
+ InstrItinClass itin, string OpcodeStr,
+ Intrinsic IntOp, bit Commutable = 0>
+ : N3VLInt_HS<op24, op23, op11_8, op4, itin, OpcodeStr, IntOp, Commutable> {
+ def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin,
+ !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp, Commutable>;
}
@@ -812,43 +1123,58 @@ multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
// Neon Multiply-Op vector operations,
// element sizes of 8, 16 and 32 bits:
multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
+ InstrItinClass itinD16, InstrItinClass itinD32,
+ InstrItinClass itinQ16, InstrItinClass itinQ32,
string OpcodeStr, SDNode OpNode> {
// 64-bit vector types.
- def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
+ def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
!strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
- def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
+ def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
!strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
- def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
+ def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
!strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
// 128-bit vector types.
- def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
+ def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
!strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
- def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
+ def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
!strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
- def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
+ def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
!strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
}
+multiclass N3VMulOpSL_HS<bits<4> op11_8,
+ InstrItinClass itinD16, InstrItinClass itinD32,
+ InstrItinClass itinQ16, InstrItinClass itinQ32,
+ string OpcodeStr, SDNode ShOp> {
+ def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
+ !strconcat(OpcodeStr, "16"), v4i16, mul, ShOp>;
+ def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
+ !strconcat(OpcodeStr, "32"), v2i32, mul, ShOp>;
+ def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
+ !strconcat(OpcodeStr, "16"), v8i16, v4i16, mul, ShOp>;
+ def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
+ !strconcat(OpcodeStr, "32"), v4i32, v2i32, mul, ShOp>;
+}
// Neon 3-argument intrinsics,
// element sizes of 8, 16 and 32 bits:
multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
string OpcodeStr, Intrinsic IntOp> {
// 64-bit vector types.
- def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
+ def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16D,
!strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
- def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
+ def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
!strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
- def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
+ def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32D,
!strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
// 128-bit vector types.
- def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
+ def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, IIC_VMACi16Q,
!strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
- def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
+ def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16Q,
!strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
- def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
+ def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi32Q,
!strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
}
@@ -858,17 +1184,25 @@ multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
// First with only element sizes of 16 and 32 bits:
multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
string OpcodeStr, Intrinsic IntOp> {
- def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
+ def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
!strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
- def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
+ def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, IIC_VMACi16D,
!strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
}
+multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
+ string OpcodeStr, Intrinsic IntOp> {
+ def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
+ !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
+ def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
+ !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
+}
+
// ....then also with element size of 8 bits:
multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
string OpcodeStr, Intrinsic IntOp>
: N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
- def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
+ def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4, IIC_VMACi16D,
!strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
}
@@ -876,23 +1210,24 @@ multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
// Neon 2-register vector intrinsics,
// element sizes of 8, 16 and 32 bits:
multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
- bits<5> op11_7, bit op4, string OpcodeStr,
- Intrinsic IntOp> {
+ bits<5> op11_7, bit op4,
+ InstrItinClass itinD, InstrItinClass itinQ,
+ string OpcodeStr, Intrinsic IntOp> {
// 64-bit vector types.
def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
- !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
+ itinD, !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
- !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
+ itinD, !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
- !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
+ itinD, !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
// 128-bit vector types.
def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
- !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
+ itinQ, !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
- !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
+ itinQ, !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
- !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
+ itinQ, !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
}
@@ -945,25 +1280,25 @@ multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
// Neon 2-register vector shift by immediate,
// element sizes of 8, 16, 32 and 64 bits:
multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
- string OpcodeStr, SDNode OpNode> {
+ InstrItinClass itin, string OpcodeStr, SDNode OpNode> {
// 64-bit vector types.
- def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
+ def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4, itin,
!strconcat(OpcodeStr, "8"), v8i8, OpNode>;
- def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
+ def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4, itin,
!strconcat(OpcodeStr, "16"), v4i16, OpNode>;
- def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
+ def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4, itin,
!strconcat(OpcodeStr, "32"), v2i32, OpNode>;
- def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
+ def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4, itin,
!strconcat(OpcodeStr, "64"), v1i64, OpNode>;
// 128-bit vector types.
- def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
+ def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4, itin,
!strconcat(OpcodeStr, "8"), v16i8, OpNode>;
- def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
+ def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4, itin,
!strconcat(OpcodeStr, "16"), v8i16, OpNode>;
- def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
+ def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4, itin,
!strconcat(OpcodeStr, "32"), v4i32, OpNode>;
- def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
+ def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4, itin,
!strconcat(OpcodeStr, "64"), v2i64, OpNode>;
}
@@ -1026,24 +1361,30 @@ multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
// Vector Add Operations.
// VADD : Vector Add (integer and floating-point)
-defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
-def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
-def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
+defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd.i", add, 1>;
+def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd.f32", v2f32, v2f32, fadd, 1>;
+def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd.f32", v4f32, v4f32, fadd, 1>;
// VADDL : Vector Add Long (Q = D + D)
-defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
-defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
+defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, "vaddl.s", int_arm_neon_vaddls, 1>;
+defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, "vaddl.u", int_arm_neon_vaddlu, 1>;
// VADDW : Vector Add Wide (Q = Q + D)
defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
// VHADD : Vector Halving Add
-defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
-defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
+defm VHADDs : N3VInt_QHS<0,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vhadd.s", int_arm_neon_vhadds, 1>;
+defm VHADDu : N3VInt_QHS<1,0,0b0000,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vhadd.u", int_arm_neon_vhaddu, 1>;
// VRHADD : Vector Rounding Halving Add
-defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
-defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
+defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vrhadd.s", int_arm_neon_vrhadds, 1>;
+defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
// VQADD : Vector Saturating Add
-defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
-defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
+defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vqadd.s", int_arm_neon_vqadds, 1>;
+defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vqadd.u", int_arm_neon_vqaddu, 1>;
// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
@@ -1052,64 +1393,208 @@ defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
// Vector Multiply Operations.
// VMUL : Vector Multiply (integer, polynomial and floating-point)
-defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
-def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
+defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q,
+ IIC_VMULi32Q, "vmul.i", mul, 1>;
+def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16D, "vmul.p8", v8i8, v8i8,
int_arm_neon_vmulp, 1>;
-def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
+def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, IIC_VMULi16Q, "vmul.p8", v16i8, v16i8,
int_arm_neon_vmulp, 1>;
-def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
-def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
+def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VBIND, "vmul.f32", v2f32, v2f32, fmul, 1>;
+def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VBINQ, "vmul.f32", v4f32, v4f32, fmul, 1>;
+defm VMULsl : N3VSL_HS<0b1000, "vmul.i", mul>;
+def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul.f32", v2f32, fmul>;
+def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul.f32", v4f32, v2f32, fmul>;
+def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
+ (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
+ (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
+ (v4i16 (EXTRACT_SUBREG QPR:$src2,
+ (DSubReg_i16_reg imm:$lane))),
+ (SubReg_i16_lane imm:$lane)))>;
+def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
+ (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
+ (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
+ (v2i32 (EXTRACT_SUBREG QPR:$src2,
+ (DSubReg_i32_reg imm:$lane))),
+ (SubReg_i32_lane imm:$lane)))>;
+def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
+ (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
+ (v4f32 (VMULslfq (v4f32 QPR:$src1),
+ (v2f32 (EXTRACT_SUBREG QPR:$src2,
+ (DSubReg_i32_reg imm:$lane))),
+ (SubReg_i32_lane imm:$lane)))>;
+
// VQDMULH : Vector Saturating Doubling Multiply Returning High Half
-defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
+defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
+ IIC_VMULi16Q, IIC_VMULi32Q,
+ "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
+defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
+ IIC_VMULi16Q, IIC_VMULi32Q,
+ "vqdmulh.s", int_arm_neon_vqdmulh>;
+def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
+ (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
+ (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
+ (v4i16 (EXTRACT_SUBREG QPR:$src2,
+ (DSubReg_i16_reg imm:$lane))),
+ (SubReg_i16_lane imm:$lane)))>;
+def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
+ (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
+ (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
+ (v2i32 (EXTRACT_SUBREG QPR:$src2,
+ (DSubReg_i32_reg imm:$lane))),
+ (SubReg_i32_lane imm:$lane)))>;
+
// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
-defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
+defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, IIC_VMULi16D, IIC_VMULi32D,
+ IIC_VMULi16Q, IIC_VMULi32Q,
+ "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
+defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
+ IIC_VMULi16Q, IIC_VMULi32Q,
+ "vqrdmulh.s", int_arm_neon_vqrdmulh>;
+def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
+ (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
+ (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
+ (v4i16 (EXTRACT_SUBREG QPR:$src2,
+ (DSubReg_i16_reg imm:$lane))),
+ (SubReg_i16_lane imm:$lane)))>;
+def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
+ (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
+ (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
+ (v2i32 (EXTRACT_SUBREG QPR:$src2,
+ (DSubReg_i32_reg imm:$lane))),
+ (SubReg_i32_lane imm:$lane)))>;
+
// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
-defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
-defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
-def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
+defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls, 1>;
+defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu, 1>;
+def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull.p8", v8i16, v8i8,
int_arm_neon_vmullp, 1>;
+defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull.s", int_arm_neon_vmulls>;
+defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull.u", int_arm_neon_vmullu>;
+
// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
-defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
+defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull, 1>;
+defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull.s", int_arm_neon_vqdmull>;
// Vector Multiply-Accumulate and Multiply-Subtract Operations.
// VMLA : Vector Multiply Accumulate (integer and floating-point)
-defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
-def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
-def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
+defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
+ IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
+def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
+def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla.f32", v4f32, fmul, fadd>;
+defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
+ IIC_VMACi16Q, IIC_VMACi32Q, "vmla.i", add>;
+def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla.f32", v2f32, fmul, fadd>;
+def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla.f32", v4f32, v2f32, fmul, fadd>;
+
+def : Pat<(v8i16 (add (v8i16 QPR:$src1),
+ (mul (v8i16 QPR:$src2),
+ (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
+ (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1),
+ (v8i16 QPR:$src2),
+ (v4i16 (EXTRACT_SUBREG QPR:$src3,
+ (DSubReg_i16_reg imm:$lane))),
+ (SubReg_i16_lane imm:$lane)))>;
+
+def : Pat<(v4i32 (add (v4i32 QPR:$src1),
+ (mul (v4i32 QPR:$src2),
+ (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
+ (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1),
+ (v4i32 QPR:$src2),
+ (v2i32 (EXTRACT_SUBREG QPR:$src3,
+ (DSubReg_i32_reg imm:$lane))),
+ (SubReg_i32_lane imm:$lane)))>;
+
+def : Pat<(v4f32 (fadd (v4f32 QPR:$src1),
+ (fmul (v4f32 QPR:$src2),
+ (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
+ (v4f32 (VMLAslfq (v4f32 QPR:$src1),
+ (v4f32 QPR:$src2),
+ (v2f32 (EXTRACT_SUBREG QPR:$src3,
+ (DSubReg_i32_reg imm:$lane))),
+ (SubReg_i32_lane imm:$lane)))>;
+
// VMLAL : Vector Multiply Accumulate Long (Q += D * D)
defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
+
+defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal.s", int_arm_neon_vmlals>;
+defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal.u", int_arm_neon_vmlalu>;
+
// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
+defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal.s", int_arm_neon_vqdmlal>;
+
// VMLS : Vector Multiply Subtract (integer and floating-point)
-defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
-def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
-def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
+defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
+ IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
+def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
+def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls.f32", v4f32, fmul, fsub>;
+defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
+ IIC_VMACi16Q, IIC_VMACi32Q, "vmls.i", sub>;
+def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls.f32", v2f32, fmul, fsub>;
+def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls.f32", v4f32, v2f32, fmul, fsub>;
+
+def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
+ (mul (v8i16 QPR:$src2),
+ (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
+ (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1),
+ (v8i16 QPR:$src2),
+ (v4i16 (EXTRACT_SUBREG QPR:$src3,
+ (DSubReg_i16_reg imm:$lane))),
+ (SubReg_i16_lane imm:$lane)))>;
+
+def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
+ (mul (v4i32 QPR:$src2),
+ (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
+ (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1),
+ (v4i32 QPR:$src2),
+ (v2i32 (EXTRACT_SUBREG QPR:$src3,
+ (DSubReg_i32_reg imm:$lane))),
+ (SubReg_i32_lane imm:$lane)))>;
+
+def : Pat<(v4f32 (fsub (v4f32 QPR:$src1),
+ (fmul (v4f32 QPR:$src2),
+ (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
+ (v4f32 (VMLSslfq (v4f32 QPR:$src1),
+ (v4f32 QPR:$src2),
+ (v2f32 (EXTRACT_SUBREG QPR:$src3,
+ (DSubReg_i32_reg imm:$lane))),
+ (SubReg_i32_lane imm:$lane)))>;
+
// VMLSL : Vector Multiply Subtract Long (Q -= D * D)
defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
+
+defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl.s", int_arm_neon_vmlsls>;
+defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl.u", int_arm_neon_vmlslu>;
+
// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
+defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
// Vector Subtract Operations.
// VSUB : Vector Subtract (integer and floating-point)
-defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
-def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
-def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
+defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, "vsub.i", sub, 0>;
+def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub.f32", v2f32, v2f32, fsub, 0>;
+def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub.f32", v4f32, v4f32, fsub, 0>;
// VSUBL : Vector Subtract Long (Q = D - D)
-defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
-defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
+defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, "vsubl.s", int_arm_neon_vsubls, 1>;
+defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, "vsubl.u", int_arm_neon_vsublu, 1>;
// VSUBW : Vector Subtract Wide (Q = Q - D)
defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
// VHSUB : Vector Halving Subtract
-defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
-defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
+defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vhsub.s", int_arm_neon_vhsubs, 0>;
+defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vhsub.u", int_arm_neon_vhsubu, 0>;
// VQSUB : Vector Saturing Subtract
-defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
-defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
+defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vqsub.s", int_arm_neon_vqsubs, 0>;
+defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vqsub.u", int_arm_neon_vqsubu, 0>;
// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
@@ -1118,73 +1603,83 @@ defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
// Vector Comparisons.
// VCEQ : Vector Compare Equal
-defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
-def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
-def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
+defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vceq.i", NEONvceq, 1>;
+def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
+def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
// VCGE : Vector Compare Greater Than or Equal
-defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
-defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
-def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
-def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
+defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vcge.s", NEONvcge, 0>;
+defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vcge.u", NEONvcgeu, 0>;
+def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
+def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
// VCGT : Vector Compare Greater Than
-defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
-defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
-def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
-def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
+defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vcgt.s", NEONvcgt, 0>;
+defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vcgt.u", NEONvcgtu, 0>;
+def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
+def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
-def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
+def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, IIC_VBIND, "vacge.f32", v2i32, v2f32,
int_arm_neon_vacged, 0>;
-def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
+def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, IIC_VBINQ, "vacge.f32", v4i32, v4f32,
int_arm_neon_vacgeq, 0>;
// VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
-def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
+def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, IIC_VBIND, "vacgt.f32", v2i32, v2f32,
int_arm_neon_vacgtd, 0>;
-def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
+def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, IIC_VBINQ, "vacgt.f32", v4i32, v4f32,
int_arm_neon_vacgtq, 0>;
// VTST : Vector Test Bits
-defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
+defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vtst.i", NEONvtst, 1>;
// Vector Bitwise Operations.
// VAND : Vector Bitwise AND
-def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
-def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
+def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", v2i32, v2i32, and, 1>;
+def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", v4i32, v4i32, and, 1>;
// VEOR : Vector Bitwise Exclusive OR
-def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
-def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
+def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", v2i32, v2i32, xor, 1>;
+def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", v4i32, v4i32, xor, 1>;
// VORR : Vector Bitwise OR
-def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
-def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
+def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", v2i32, v2i32, or, 1>;
+def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", v4i32, v4i32, or, 1>;
// VBIC : Vector Bitwise Bit Clear (AND NOT)
def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
- (ins DPR:$src1, DPR:$src2), NoItinerary,
+ (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
"vbic\t$dst, $src1, $src2", "",
- [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
+ [(set DPR:$dst, (v2i32 (and DPR:$src1,
+ (vnot_conv DPR:$src2))))]>;
def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
- (ins QPR:$src1, QPR:$src2), NoItinerary,
+ (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
"vbic\t$dst, $src1, $src2", "",
- [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
+ [(set QPR:$dst, (v4i32 (and QPR:$src1,
+ (vnot_conv QPR:$src2))))]>;
// VORN : Vector Bitwise OR NOT
def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
- (ins DPR:$src1, DPR:$src2), NoItinerary,
+ (ins DPR:$src1, DPR:$src2), IIC_VBINiD,
"vorn\t$dst, $src1, $src2", "",
- [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
+ [(set DPR:$dst, (v2i32 (or DPR:$src1,
+ (vnot_conv DPR:$src2))))]>;
def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
- (ins QPR:$src1, QPR:$src2), NoItinerary,
+ (ins QPR:$src1, QPR:$src2), IIC_VBINiQ,
"vorn\t$dst, $src1, $src2", "",
- [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
+ [(set QPR:$dst, (v4i32 (or QPR:$src1,
+ (vnot_conv QPR:$src2))))]>;
// VMVN : Vector Bitwise NOT
def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
- (outs DPR:$dst), (ins DPR:$src), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD,
"vmvn\t$dst, $src", "",
[(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
- (outs QPR:$dst), (ins QPR:$src), NoItinerary,
+ (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD,
"vmvn\t$dst, $src", "",
[(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
@@ -1192,17 +1687,17 @@ def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
// VBSL : Vector Bitwise Select
def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
- (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
+ (ins DPR:$src1, DPR:$src2, DPR:$src3), IIC_VCNTiD,
"vbsl\t$dst, $src2, $src3", "$src1 = $dst",
[(set DPR:$dst,
(v2i32 (or (and DPR:$src2, DPR:$src1),
- (and DPR:$src3, (vnot DPR:$src1)))))]>;
+ (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
- (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
+ (ins QPR:$src1, QPR:$src2, QPR:$src3), IIC_VCNTiQ,
"vbsl\t$dst, $src2, $src3", "$src1 = $dst",
[(set QPR:$dst,
(v4i32 (or (and QPR:$src2, QPR:$src1),
- (and QPR:$src3, (vnot QPR:$src1)))))]>;
+ (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
// VBIF : Vector Bitwise Insert if False
// like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
@@ -1215,16 +1710,18 @@ def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
// Vector Absolute Differences.
// VABD : Vector Absolute Difference
-defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
-defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
-def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
+defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vabd.s", int_arm_neon_vabds, 0>;
+defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vabd.u", int_arm_neon_vabdu, 0>;
+def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, IIC_VBIND, "vabd.f32", v2f32, v2f32,
int_arm_neon_vabds, 0>;
-def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
+def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vabd.f32", v4f32, v4f32,
int_arm_neon_vabds, 0>;
// VABDL : Vector Absolute Difference Long (Q = | D - D |)
-defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
-defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
+defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q, "vabdl.s", int_arm_neon_vabdls, 0>;
+defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q, "vabdl.u", int_arm_neon_vabdlu, 0>;
// VABA : Vector Absolute Difference and Accumulate
defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
@@ -1237,31 +1734,35 @@ defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
// Vector Maximum and Minimum.
// VMAX : Vector Maximum
-defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
-defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
-def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
+defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vmax.s", int_arm_neon_vmaxs, 1>;
+defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vmax.u", int_arm_neon_vmaxu, 1>;
+def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax.f32", v2f32, v2f32,
int_arm_neon_vmaxs, 1>;
-def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
+def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax.f32", v4f32, v4f32,
int_arm_neon_vmaxs, 1>;
// VMIN : Vector Minimum
-defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
-defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
-def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
+defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vmin.s", int_arm_neon_vmins, 1>;
+defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
+ IIC_VBINi4Q, "vmin.u", int_arm_neon_vminu, 1>;
+def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin.f32", v2f32, v2f32,
int_arm_neon_vmins, 1>;
-def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
+def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin.f32", v4f32, v4f32,
int_arm_neon_vmins, 1>;
// Vector Pairwise Operations.
// VPADD : Vector Pairwise Add
-def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
+def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, IIC_VBINiD, "vpadd.i8", v8i8, v8i8,
int_arm_neon_vpadd, 0>;
-def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
+def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, IIC_VBINiD, "vpadd.i16", v4i16, v4i16,
int_arm_neon_vpadd, 0>;
-def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
+def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, IIC_VBINiD, "vpadd.i32", v2i32, v2i32,
int_arm_neon_vpadd, 0>;
-def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
+def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, IIC_VBIND, "vpadd.f32", v2f32, v2f32,
int_arm_neon_vpadd, 0>;
// VPADDL : Vector Pairwise Add Long
@@ -1277,81 +1778,91 @@ defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
int_arm_neon_vpadalu>;
// VPMAX : Vector Pairwise Maximum
-def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
+def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.s8", v8i8, v8i8,
int_arm_neon_vpmaxs, 0>;
-def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
+def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.s16", v4i16, v4i16,
int_arm_neon_vpmaxs, 0>;
-def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
+def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.s32", v2i32, v2i32,
int_arm_neon_vpmaxs, 0>;
-def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
+def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, IIC_VBINi4D, "vpmax.u8", v8i8, v8i8,
int_arm_neon_vpmaxu, 0>;
-def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
+def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, IIC_VBINi4D, "vpmax.u16", v4i16, v4i16,
int_arm_neon_vpmaxu, 0>;
-def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
+def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, IIC_VBINi4D, "vpmax.u32", v2i32, v2i32,
int_arm_neon_vpmaxu, 0>;
-def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
+def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, IIC_VBINi4D, "vpmax.f32", v2f32, v2f32,
int_arm_neon_vpmaxs, 0>;
// VPMIN : Vector Pairwise Minimum
-def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
+def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.s8", v8i8, v8i8,
int_arm_neon_vpmins, 0>;
-def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
+def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.s16", v4i16, v4i16,
int_arm_neon_vpmins, 0>;
-def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
+def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.s32", v2i32, v2i32,
int_arm_neon_vpmins, 0>;
-def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
+def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, IIC_VBINi4D, "vpmin.u8", v8i8, v8i8,
int_arm_neon_vpminu, 0>;
-def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
+def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, IIC_VBINi4D, "vpmin.u16", v4i16, v4i16,
int_arm_neon_vpminu, 0>;
-def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
+def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, IIC_VBINi4D, "vpmin.u32", v2i32, v2i32,
int_arm_neon_vpminu, 0>;
-def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
+def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, IIC_VBINi4D, "vpmin.f32", v2f32, v2f32,
int_arm_neon_vpmins, 0>;
// Vector Reciprocal and Reciprocal Square Root Estimate and Step.
// VRECPE : Vector Reciprocal Estimate
-def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
+def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
+ IIC_VUNAD, "vrecpe.u32",
v2i32, v2i32, int_arm_neon_vrecpe>;
-def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
+def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
+ IIC_VUNAQ, "vrecpe.u32",
v4i32, v4i32, int_arm_neon_vrecpe>;
-def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
+def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
+ IIC_VUNAD, "vrecpe.f32",
v2f32, v2f32, int_arm_neon_vrecpe>;
-def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
+def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
+ IIC_VUNAQ, "vrecpe.f32",
v4f32, v4f32, int_arm_neon_vrecpe>;
// VRECPS : Vector Reciprocal Step
-def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
+def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSD, "vrecps.f32", v2f32, v2f32,
int_arm_neon_vrecps, 1>;
-def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
+def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, IIC_VRECSQ, "vrecps.f32", v4f32, v4f32,
int_arm_neon_vrecps, 1>;
// VRSQRTE : Vector Reciprocal Square Root Estimate
-def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
- v2i32, v2i32, int_arm_neon_vrsqrte>;
-def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
- v4i32, v4i32, int_arm_neon_vrsqrte>;
-def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
- v2f32, v2f32, int_arm_neon_vrsqrte>;
-def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
- v4f32, v4f32, int_arm_neon_vrsqrte>;
+def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
+ IIC_VUNAD, "vrsqrte.u32",
+ v2i32, v2i32, int_arm_neon_vrsqrte>;
+def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
+ IIC_VUNAQ, "vrsqrte.u32",
+ v4i32, v4i32, int_arm_neon_vrsqrte>;
+def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
+ IIC_VUNAD, "vrsqrte.f32",
+ v2f32, v2f32, int_arm_neon_vrsqrte>;
+def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
+ IIC_VUNAQ, "vrsqrte.f32",
+ v4f32, v4f32, int_arm_neon_vrsqrte>;
// VRSQRTS : Vector Reciprocal Square Root Step
-def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
+def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSD, "vrsqrts.f32", v2f32, v2f32,
int_arm_neon_vrsqrts, 1>;
-def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
+def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, IIC_VRECSQ, "vrsqrts.f32", v4f32, v4f32,
int_arm_neon_vrsqrts, 1>;
// Vector Shifts.
// VSHL : Vector Shift
-defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
-defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
+defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
+ IIC_VSHLiQ, "vshl.s", int_arm_neon_vshifts, 0>;
+defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
+ IIC_VSHLiQ, "vshl.u", int_arm_neon_vshiftu, 0>;
// VSHL : Vector Shift Left (Immediate)
-defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
+defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLiD, "vshl.i", NEONvshl>;
// VSHR : Vector Shift Right (Immediate)
-defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
-defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
+defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr.s", NEONvshrs>;
+defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr.u", NEONvshru>;
// VSHLL : Vector Shift Left Long
def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
@@ -1376,86 +1887,90 @@ def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
v2i64, v2i32, NEONvshlli>;
// VSHRN : Vector Shift Right and Narrow
-def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
- v8i8, v8i16, NEONvshrn>;
-def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
- v4i16, v4i32, NEONvshrn>;
-def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
- v2i32, v2i64, NEONvshrn>;
+def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1,
+ IIC_VSHLiD, "vshrn.i16", v8i8, v8i16, NEONvshrn>;
+def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1,
+ IIC_VSHLiD, "vshrn.i32", v4i16, v4i32, NEONvshrn>;
+def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1,
+ IIC_VSHLiD, "vshrn.i64", v2i32, v2i64, NEONvshrn>;
// VRSHL : Vector Rounding Shift
-defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
-defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
+defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+ IIC_VSHLi4Q, "vrshl.s", int_arm_neon_vrshifts, 0>;
+defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+ IIC_VSHLi4Q, "vrshl.u", int_arm_neon_vrshiftu, 0>;
// VRSHR : Vector Rounding Shift Right
-defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
-defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
+defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.s", NEONvrshrs>;
+defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, IIC_VSHLi4D, "vrshr.u", NEONvrshru>;
// VRSHRN : Vector Rounding Shift Right and Narrow
-def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
- v8i8, v8i16, NEONvrshrn>;
-def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
- v4i16, v4i32, NEONvrshrn>;
-def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
- v2i32, v2i64, NEONvrshrn>;
+def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1,
+ IIC_VSHLi4D, "vrshrn.i16", v8i8, v8i16, NEONvrshrn>;
+def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1,
+ IIC_VSHLi4D, "vrshrn.i32", v4i16, v4i32, NEONvrshrn>;
+def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1,
+ IIC_VSHLi4D, "vrshrn.i64", v2i32, v2i64, NEONvrshrn>;
// VQSHL : Vector Saturating Shift
-defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
-defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
+defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+ IIC_VSHLi4Q, "vqshl.s", int_arm_neon_vqshifts, 0>;
+defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+ IIC_VSHLi4Q, "vqshl.u", int_arm_neon_vqshiftu, 0>;
// VQSHL : Vector Saturating Shift Left (Immediate)
-defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
-defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
+defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.s", NEONvqshls>;
+defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, IIC_VSHLi4D, "vqshl.u", NEONvqshlu>;
// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
-defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
+defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, IIC_VSHLi4D, "vqshlu.s", NEONvqshlsu>;
// VQSHRN : Vector Saturating Shift Right and Narrow
-def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
- v8i8, v8i16, NEONvqshrns>;
-def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
- v4i16, v4i32, NEONvqshrns>;
-def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
- v2i32, v2i64, NEONvqshrns>;
-def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
- v8i8, v8i16, NEONvqshrnu>;
-def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
- v4i16, v4i32, NEONvqshrnu>;
-def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
- v2i32, v2i64, NEONvqshrnu>;
+def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1,
+ IIC_VSHLi4D, "vqshrn.s16", v8i8, v8i16, NEONvqshrns>;
+def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1,
+ IIC_VSHLi4D, "vqshrn.s32", v4i16, v4i32, NEONvqshrns>;
+def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1,
+ IIC_VSHLi4D, "vqshrn.s64", v2i32, v2i64, NEONvqshrns>;
+def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1,
+ IIC_VSHLi4D, "vqshrn.u16", v8i8, v8i16, NEONvqshrnu>;
+def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1,
+ IIC_VSHLi4D, "vqshrn.u32", v4i16, v4i32, NEONvqshrnu>;
+def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1,
+ IIC_VSHLi4D, "vqshrn.u64", v2i32, v2i64, NEONvqshrnu>;
// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
-def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
- v8i8, v8i16, NEONvqshrnsu>;
-def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
- v4i16, v4i32, NEONvqshrnsu>;
-def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
- v2i32, v2i64, NEONvqshrnsu>;
+def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1,
+ IIC_VSHLi4D, "vqshrun.s16", v8i8, v8i16, NEONvqshrnsu>;
+def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1,
+ IIC_VSHLi4D, "vqshrun.s32", v4i16, v4i32, NEONvqshrnsu>;
+def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1,
+ IIC_VSHLi4D, "vqshrun.s64", v2i32, v2i64, NEONvqshrnsu>;
// VQRSHL : Vector Saturating Rounding Shift
-defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
- int_arm_neon_vqrshifts, 0>;
-defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
- int_arm_neon_vqrshiftu, 0>;
+defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+ IIC_VSHLi4Q, "vqrshl.s", int_arm_neon_vqrshifts, 0>;
+defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
+ IIC_VSHLi4Q, "vqrshl.u", int_arm_neon_vqrshiftu, 0>;
// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
-def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
- v8i8, v8i16, NEONvqrshrns>;
-def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
- v4i16, v4i32, NEONvqrshrns>;
-def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
- v2i32, v2i64, NEONvqrshrns>;
-def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
- v8i8, v8i16, NEONvqrshrnu>;
-def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
- v4i16, v4i32, NEONvqrshrnu>;
-def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
- v2i32, v2i64, NEONvqrshrnu>;
+def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1,
+ IIC_VSHLi4D, "vqrshrn.s16", v8i8, v8i16, NEONvqrshrns>;
+def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1,
+ IIC_VSHLi4D, "vqrshrn.s32", v4i16, v4i32, NEONvqrshrns>;
+def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1,
+ IIC_VSHLi4D, "vqrshrn.s64", v2i32, v2i64, NEONvqrshrns>;
+def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1,
+ IIC_VSHLi4D, "vqrshrn.u16", v8i8, v8i16, NEONvqrshrnu>;
+def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1,
+ IIC_VSHLi4D, "vqrshrn.u32", v4i16, v4i32, NEONvqrshrnu>;
+def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1,
+ IIC_VSHLi4D, "vqrshrn.u64", v2i32, v2i64, NEONvqrshrnu>;
// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
-def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
- v8i8, v8i16, NEONvqrshrnsu>;
-def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
- v4i16, v4i32, NEONvqrshrnsu>;
-def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
- v2i32, v2i64, NEONvqrshrnsu>;
+def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1,
+ IIC_VSHLi4D, "vqrshrun.s16", v8i8, v8i16, NEONvqrshrnsu>;
+def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1,
+ IIC_VSHLi4D, "vqrshrun.s32", v4i16, v4i32, NEONvqrshrnsu>;
+def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1,
+ IIC_VSHLi4D, "vqrshrun.s64", v2i32, v2i64, NEONvqrshrnsu>;
// VSRA : Vector Shift Right and Accumulate
defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
@@ -1472,15 +1987,19 @@ defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
// Vector Absolute and Saturating Absolute.
// VABS : Vector Absolute Value
-defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
+defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
+ IIC_VUNAiD, IIC_VUNAiQ, "vabs.s",
int_arm_neon_vabs>;
-def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
+def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
+ IIC_VUNAD, "vabs.f32",
v2f32, v2f32, int_arm_neon_vabs>;
-def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
+def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
+ IIC_VUNAQ, "vabs.f32",
v4f32, v4f32, int_arm_neon_vabs>;
// VQABS : Vector Saturating Absolute Value
-defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
+defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
+ IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs.s",
int_arm_neon_vqabs>;
// Vector Negate.
@@ -1490,13 +2009,11 @@ def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
- NoItinerary,
- !strconcat(OpcodeStr, "\t$dst, $src"), "",
+ IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
- NoItinerary,
- !strconcat(OpcodeStr, "\t$dst, $src"), "",
+ IIC_VSHLiD, !strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
// VNEG : Vector Negate
@@ -1509,11 +2026,11 @@ def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
// VNEG : Vector Negate (floating-point)
def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
- (outs DPR:$dst), (ins DPR:$src), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src), IIC_VUNAD,
"vneg.f32\t$dst, $src", "",
[(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
- (outs QPR:$dst), (ins QPR:$src), NoItinerary,
+ (outs QPR:$dst), (ins QPR:$src), IIC_VUNAQ,
"vneg.f32\t$dst, $src", "",
[(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
@@ -1525,21 +2042,26 @@ def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
// VQNEG : Vector Saturating Negate
-defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
+defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
+ IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg.s",
int_arm_neon_vqneg>;
// Vector Bit Counting Operations.
// VCLS : Vector Count Leading Sign Bits
-defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
+defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
+ IIC_VCNTiD, IIC_VCNTiQ, "vcls.s",
int_arm_neon_vcls>;
// VCLZ : Vector Count Leading Zeros
-defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
+defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
+ IIC_VCNTiD, IIC_VCNTiQ, "vclz.i",
int_arm_neon_vclz>;
// VCNT : Vector Count One Bits
-def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
+def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
+ IIC_VCNTiD, "vcnt.8",
v8i8, v8i8, int_arm_neon_vcnt>;
-def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
+def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
+ IIC_VCNTiQ, "vcnt.8",
v16i8, v16i8, int_arm_neon_vcnt>;
// Vector Move Operations.
@@ -1547,9 +2069,9 @@ def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
// VMOV : Vector Move (Register)
def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
- NoItinerary, "vmov\t$dst, $src", "", []>;
+ IIC_VMOVD, "vmov\t$dst, $src", "", []>;
def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
- NoItinerary, "vmov\t$dst, $src", "", []>;
+ IIC_VMOVD, "vmov\t$dst, $src", "", []>;
// VMOV : Vector Move (Immediate)
@@ -1589,38 +2111,38 @@ def vmovImm64 : PatLeaf<(build_vector), [{
// be encoded based on the immed values.
def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
- (ins i8imm:$SIMM), NoItinerary,
+ (ins i8imm:$SIMM), IIC_VMOVImm,
"vmov.i8\t$dst, $SIMM", "",
[(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
- (ins i8imm:$SIMM), NoItinerary,
+ (ins i8imm:$SIMM), IIC_VMOVImm,
"vmov.i8\t$dst, $SIMM", "",
[(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
- (ins i16imm:$SIMM), NoItinerary,
+ (ins i16imm:$SIMM), IIC_VMOVImm,
"vmov.i16\t$dst, $SIMM", "",
[(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
- (ins i16imm:$SIMM), NoItinerary,
+ (ins i16imm:$SIMM), IIC_VMOVImm,
"vmov.i16\t$dst, $SIMM", "",
[(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
- (ins i32imm:$SIMM), NoItinerary,
+ (ins i32imm:$SIMM), IIC_VMOVImm,
"vmov.i32\t$dst, $SIMM", "",
[(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
- (ins i32imm:$SIMM), NoItinerary,
+ (ins i32imm:$SIMM), IIC_VMOVImm,
"vmov.i32\t$dst, $SIMM", "",
[(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
- (ins i64imm:$SIMM), NoItinerary,
+ (ins i64imm:$SIMM), IIC_VMOVImm,
"vmov.i64\t$dst, $SIMM", "",
[(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
- (ins i64imm:$SIMM), NoItinerary,
+ (ins i64imm:$SIMM), IIC_VMOVImm,
"vmov.i64\t$dst, $SIMM", "",
[(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
@@ -1628,27 +2150,27 @@ def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
- NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
+ IIC_VMOVSI, "vmov", ".s8\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
imm:$lane))]>;
def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
- NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
+ IIC_VMOVSI, "vmov", ".s16\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
imm:$lane))]>;
def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
- NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
+ IIC_VMOVSI, "vmov", ".u8\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
imm:$lane))]>;
def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
- NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
+ IIC_VMOVSI, "vmov", ".u16\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
imm:$lane))]>;
def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
(outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
- NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
+ IIC_VMOVSI, "vmov", ".32\t$dst, $src[$lane]",
[(set GPR:$dst, (extractelt (v2i32 DPR:$src),
imm:$lane))]>;
// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
@@ -1673,9 +2195,11 @@ def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
(DSubReg_i32_reg imm:$lane))),
(SubReg_i32_lane imm:$lane))>;
def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
- (EXTRACT_SUBREG DPR:$src1, (SSubReg_f32_reg imm:$src2))>;
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2),
+ (SSubReg_f32_reg imm:$src2))>;
def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
- (EXTRACT_SUBREG QPR:$src1, (SSubReg_f32_reg imm:$src2))>;
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2),
+ (SSubReg_f32_reg imm:$src2))>;
//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
// (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
@@ -1687,17 +2211,17 @@ def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
let Constraints = "$src1 = $dst" in {
def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
(ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
- NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
+ IIC_VMOVISL, "vmov", ".8\t$dst[$lane], $src2",
[(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
GPR:$src2, imm:$lane))]>;
def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
(ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
- NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
+ IIC_VMOVISL, "vmov", ".16\t$dst[$lane], $src2",
[(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
GPR:$src2, imm:$lane))]>;
def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
(ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
- NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
+ IIC_VMOVISL, "vmov", ".32\t$dst[$lane], $src2",
[(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
GPR:$src2, imm:$lane))]>;
}
@@ -1721,9 +2245,11 @@ def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
(DSubReg_i32_reg imm:$lane)))>;
def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
- (INSERT_SUBREG DPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
+ (INSERT_SUBREG (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2),
+ SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
- (INSERT_SUBREG QPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
+ (INSERT_SUBREG (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2),
+ SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
// (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
@@ -1761,11 +2287,11 @@ def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
: NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
- NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
+ IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
[(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
: NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
- NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
+ IIC_VMOVIS, "vdup", !strconcat(asmSize, "\t$dst, $src"),
[(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
@@ -1776,11 +2302,11 @@ def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
- NoItinerary, "vdup", ".32\t$dst, $src",
+ IIC_VMOVIS, "vdup", ".32\t$dst, $src",
[(set DPR:$dst, (v2f32 (NEONvdup
(f32 (bitconvert GPR:$src)))))]>;
def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
- NoItinerary, "vdup", ".32\t$dst, $src",
+ IIC_VMOVIS, "vdup", ".32\t$dst, $src",
[(set QPR:$dst, (v4f32 (NEONvdup
(f32 (bitconvert GPR:$src)))))]>;
@@ -1788,14 +2314,14 @@ def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
- (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
!strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
[(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
ValueType ResTy, ValueType OpTy>
: N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
- (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
+ (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), IIC_VMOVD,
!strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
[(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
@@ -1827,23 +2353,32 @@ def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
(outs DPR:$dst), (ins SPR:$src),
- NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
+ IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
[(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
(outs QPR:$dst), (ins SPR:$src),
- NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
+ IIC_VMOVD, "vdup.32\t$dst, ${src:lane}", "",
[(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
+def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
+ (INSERT_SUBREG QPR:$src,
+ (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
+ (DSubReg_f64_other_reg imm:$lane))>;
+def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
+ (INSERT_SUBREG QPR:$src,
+ (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
+ (DSubReg_f64_other_reg imm:$lane))>;
+
// VMOVN : Vector Narrowing Move
-defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
+defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD, "vmovn.i",
int_arm_neon_vmovn>;
// VQMOVN : Vector Saturating Narrowing Move
-defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
+defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, "vqmovn.s",
int_arm_neon_vqmovns>;
-defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
+defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD, "vqmovn.u",
int_arm_neon_vqmovnu>;
-defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
+defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD, "vqmovun.s",
int_arm_neon_vqmovnsu>;
// VMOVL : Vector Lengthening Move
defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
@@ -1897,12 +2432,12 @@ def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
- (ins DPR:$src), NoItinerary,
+ (ins DPR:$src), IIC_VMOVD,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
- (ins QPR:$src), NoItinerary,
+ (ins QPR:$src), IIC_VMOVD,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
@@ -1920,12 +2455,12 @@ def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
- (ins DPR:$src), NoItinerary,
+ (ins DPR:$src), IIC_VMOVD,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
- (ins QPR:$src), NoItinerary,
+ (ins QPR:$src), IIC_VMOVD,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
@@ -1939,12 +2474,12 @@ def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
- (ins DPR:$src), NoItinerary,
+ (ins DPR:$src), IIC_VMOVD,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
- (ins QPR:$src), NoItinerary,
+ (ins QPR:$src), IIC_VMOVD,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
[(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
@@ -1957,14 +2492,14 @@ def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
class VEXTd<string OpcodeStr, ValueType Ty>
: N3V<0,1,0b11,0b0000,0,0, (outs DPR:$dst),
- (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NoItinerary,
+ (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
!strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
[(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
(Ty DPR:$rhs), imm:$index)))]>;
class VEXTq<string OpcodeStr, ValueType Ty>
: N3V<0,1,0b11,0b0000,1,0, (outs QPR:$dst),
- (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NoItinerary,
+ (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
!strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
[(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
(Ty QPR:$rhs), imm:$index)))]>;
@@ -1985,9 +2520,9 @@ def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
-def VTRNq8 : N2VQShuffle<0b00, 0b00001, "vtrn.8">;
-def VTRNq16 : N2VQShuffle<0b01, 0b00001, "vtrn.16">;
-def VTRNq32 : N2VQShuffle<0b10, 0b00001, "vtrn.32">;
+def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn.8">;
+def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn.16">;
+def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn.32">;
// VUZP : Vector Unzip (Deinterleave)
@@ -1995,9 +2530,9 @@ def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
-def VUZPq8 : N2VQShuffle<0b00, 0b00010, "vuzp.8">;
-def VUZPq16 : N2VQShuffle<0b01, 0b00010, "vuzp.16">;
-def VUZPq32 : N2VQShuffle<0b10, 0b00010, "vuzp.32">;
+def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp.8">;
+def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp.16">;
+def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp.32">;
// VZIP : Vector Zip (Interleave)
@@ -2005,62 +2540,66 @@ def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
-def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">;
-def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
-def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
+def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip.8">;
+def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip.16">;
+def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip.32">;
// Vector Table Lookup and Table Extension.
// VTBL : Vector Table Lookup
def VTBL1
: N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
- (ins DPR:$tbl1, DPR:$src), NoItinerary,
+ (ins DPR:$tbl1, DPR:$src), IIC_VTB1,
"vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
+let hasExtraSrcRegAllocReq = 1 in {
def VTBL2
: N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
- (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
+ (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
"vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
def VTBL3
: N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
- (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
+ (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTB3,
"vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
def VTBL4
: N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
- (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
+ (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTB4,
"vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
+} // hasExtraSrcRegAllocReq = 1
// VTBX : Vector Table Extension
def VTBX1
: N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
- (ins DPR:$orig, DPR:$tbl1, DPR:$src), NoItinerary,
+ (ins DPR:$orig, DPR:$tbl1, DPR:$src), IIC_VTBX1,
"vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
+let hasExtraSrcRegAllocReq = 1 in {
def VTBX2
: N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
- (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
+ (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
"vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
def VTBX3
: N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
- (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
+ (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), IIC_VTBX3,
"vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
def VTBX4
: N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
- DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
+ DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), IIC_VTBX4,
"vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
+} // hasExtraSrcRegAllocReq = 1
//===----------------------------------------------------------------------===//
// NEON instructions for single-precision FP math
@@ -2086,23 +2625,24 @@ def : N3VDsPat<fmul, VMULfd_sfp>;
// Vector Multiply-Accumulate/Subtract used for single-precision FP
let neverHasSideEffects = 1 in
-def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
+def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32,fmul,fadd>;
def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
let neverHasSideEffects = 1 in
-def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
+def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32,fmul,fsub>;
def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
// Vector Absolute used for single-precision FP
let neverHasSideEffects = 1 in
-def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
+def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
+ IIC_VUNAD, "vabs.f32",
v2f32, v2f32, int_arm_neon_vabs>;
def : N2VDIntsPat<fabs, VABSfd_sfp>;
// Vector Negate used for single-precision FP
let neverHasSideEffects = 1 in
def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
- (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
+ (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), IIC_VUNAD,
"vneg.f32\t$dst, $src", "", []>;
def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrThumb.td b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrThumb.td
index b5159f9..9816add 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -139,7 +139,7 @@ def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALUi,
// ADD rd, sp, #imm8
def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALUi,
- "add $dst, $sp, $rhs * 4 @ addrspi", []>;
+ "add $dst, $sp, $rhs * 4", []>;
// ADD sp, sp, #imm7
def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi,
@@ -174,22 +174,23 @@ def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
// Control Flow Instructions.
//
-let isReturn = 1, isTerminator = 1 in {
+let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
def tBX_RET : TI<(outs), (ins), IIC_Br, "bx lr", [(ARMretflag)]>;
// Alternative return instruction used by vararg functions.
def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx $target", []>;
}
// FIXME: remove when we have a way to marking a MI with these properties.
-let isReturn = 1, isTerminator = 1, mayLoad = 1 in
-def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$dst1, variable_ops), IIC_Br,
- "pop${p} $dst1", []>;
+let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
+ hasExtraDefRegAllocReq = 1 in
+def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
+ "pop${p} $wb", []>;
let isCall = 1,
Defs = [R0, R1, R2, R3, R12, LR,
D0, D1, D2, D3, D4, D5, D6, D7,
D16, D17, D18, D19, D20, D21, D22, D23,
- D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
+ D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
// Also used for Thumb2
def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
"bl ${func:call}",
@@ -220,7 +221,7 @@ let isCall = 1,
Defs = [R0, R1, R2, R3, R9, R12, LR,
D0, D1, D2, D3, D4, D5, D6, D7,
D16, D17, D18, D19, D20, D21, D22, D23,
- D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
+ D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
// Also used for Thumb2
def tBLr9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
"bl ${func:call}",
@@ -250,7 +251,7 @@ let isBranch = 1, isTerminator = 1 in {
let isBarrier = 1 in {
let isPredicable = 1 in
def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
- "b.n $target", [(br bb:$target)]>;
+ "b $target", [(br bb:$target)]>;
// Far jump
let Defs = [LR] in
@@ -268,7 +269,7 @@ let isBranch = 1, isTerminator = 1 in {
// a two-value operand where a dag node expects two operands. :(
let isBranch = 1, isTerminator = 1 in
def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
- "b$cc.n $target",
+ "b$cc $target",
[/*(ARMbrcond bb:$target, imm:$cc)*/]>;
//===----------------------------------------------------------------------===//
@@ -310,10 +311,9 @@ def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
"ldr", " $dst, $addr", []>;
// Load tconstpool
-// FIXME: Added .n suffix to workaround a Darwin assembler bug.
let canFoldAsLoad = 1 in
def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
- "ldr", ".n $dst, $addr",
+ "ldr", " $dst, $addr",
[(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
// Special LDR for loads from non-pc-relative constpools.
@@ -349,25 +349,25 @@ def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
//
// These requires base address to be written back or one of the loaded regs.
-let mayLoad = 1 in
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
def tLDM : T1I<(outs),
- (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
+ (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
IIC_iLoadm,
- "ldm${addr:submode}${p} $addr, $dst1", []>;
+ "ldm${addr:submode}${p} $addr, $wb", []>;
-let mayStore = 1 in
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def tSTM : T1I<(outs),
- (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
+ (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
IIC_iStorem,
- "stm${addr:submode}${p} $addr, $src1", []>;
+ "stm${addr:submode}${p} $addr, $wb", []>;
-let mayLoad = 1, Uses = [SP], Defs = [SP] in
-def tPOP : T1I<(outs), (ins pred:$p, reglist:$dst1, variable_ops), IIC_Br,
- "pop${p} $dst1", []>;
+let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
+def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
+ "pop${p} $wb", []>;
-let mayStore = 1, Uses = [SP], Defs = [SP] in
-def tPUSH : T1I<(outs), (ins pred:$p, reglist:$src1, variable_ops), IIC_Br,
- "push${p} $src1", []>;
+let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
+def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
+ "push${p} $wb", []>;
//===----------------------------------------------------------------------===//
// Arithmetic Instructions.
@@ -396,7 +396,7 @@ def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
let neverHasSideEffects = 1 in
def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
- "add", " $dst, $rhs @ addhirr", []>;
+ "add", " $dst, $rhs", []>;
// And register
let isCommutable = 1 in
@@ -500,11 +500,11 @@ def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
// FIXME: Make these predicable.
def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
- "mov $dst, $src\t@ hir2lor", []>;
+ "mov $dst, $src", []>;
def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
- "mov $dst, $src\t@ lor2hir", []>;
+ "mov $dst, $src", []>;
def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
- "mov $dst, $src\t@ hir2hir", []>;
+ "mov $dst, $src", []>;
} // neverHasSideEffects
// multiply register
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrThumb2.td b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 0108e8f..79d7108 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -88,28 +88,6 @@ def imm0_255_neg : PatLeaf<(i32 imm), [{
return (uint32_t)(-N->getZExtValue()) < 255;
}], imm_neg_XFORM>;
-/// imm0_65535 predicate - True if the 32-bit immediate is in the range
-/// [0.65535].
-def imm0_65535 : PatLeaf<(i32 imm), [{
- return (uint32_t)N->getZExtValue() < 65536;
-}]>;
-
-/// Split a 32-bit immediate into two 16 bit parts.
-def t2_lo16 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
- MVT::i32);
-}]>;
-
-def t2_hi16 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
-}]>;
-
-def t2_lo16AllZero : PatLeaf<(i32 imm), [{
- // Returns true if all low 16-bits are 0.
- return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
- }], t2_hi16>;
-
-
// Define Thumb2 specific addressing modes.
// t2addrmode_imm12 := reg + imm12
@@ -483,12 +461,14 @@ defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
-let mayLoad = 1 in {
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
// Load doubleword
-def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
- IIC_iLoadi, "ldrd", " $dst, $addr", []>;
-def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
- "ldrd", " $dst, $addr", []>;
+def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2),
+ (ins t2addrmode_imm8s4:$addr),
+ IIC_iLoadi, "ldrd", " $dst1, $addr", []>;
+def t2LDRDpci : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2),
+ (ins i32imm:$addr), IIC_iLoadi,
+ "ldrd", " $dst1, $addr", []>;
}
// zextload i1 -> zextload i8
@@ -596,9 +576,10 @@ defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
// Store doubleword
-let mayLoad = 1 in
-def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
- IIC_iStorer, "strd", " $src, $addr", []>;
+let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
+def t2STRDi8 : T2Ii8s4<(outs),
+ (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
+ IIC_iStorer, "strd", " $src1, $addr", []>;
// Indexed stores
def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
@@ -650,15 +631,15 @@ def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
// Load / store multiple Instructions.
//
-let mayLoad = 1 in
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
def t2LDM : T2XI<(outs),
- (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
- IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide} $addr, $dst1", []>;
+ (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
+ IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide} $addr, $wb", []>;
-let mayStore = 1 in
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def t2STM : T2XI<(outs),
- (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
- IIC_iStorem, "stm${addr:submode}${p}${addr:wide} $addr, $src1", []>;
+ (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
+ IIC_iStorem, "stm${addr:submode}${p}${addr:wide} $addr, $wb", []>;
//===----------------------------------------------------------------------===//
// Move Instructions.
@@ -668,7 +649,8 @@ let neverHasSideEffects = 1 in
def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
"mov", ".w $dst, $src", []>;
-let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
+let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
"mov", ".w $dst, $src",
[(set GPR:$dst, t2_so_imm:$src)]>;
@@ -678,12 +660,11 @@ def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
"movw", " $dst, $src",
[(set GPR:$dst, imm0_65535:$src)]>;
-// FIXME: Also available in ARM mode.
let Constraints = "$src = $dst" in
-def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
- "movt", " $dst, $imm",
- [(set GPR:$dst,
- (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
+def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
+ "movt", " $dst, $imm",
+ [(set GPR:$dst,
+ (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]>;
//===----------------------------------------------------------------------===//
// Extend Instructions.
@@ -756,9 +737,11 @@ defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
+let Uses = [CPSR] in {
def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
- "rrx", ".w $dst, $src",
+ "rrx", " $dst, $src",
[(set GPR:$dst, (ARMrrx GPR:$src))]>;
+}
let Defs = [CPSR] in {
def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
@@ -1089,10 +1072,11 @@ let Defs =
// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
// operand list.
// FIXME: Should pc be an implicit operand like PICADD, etc?
-let isReturn = 1, isTerminator = 1, mayLoad = 1 in
+let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
+ hasExtraDefRegAllocReq = 1 in
def t2LDM_RET : T2XI<(outs),
- (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
- IIC_Br, "ldm${addr:submode}${p}${addr:wide} $addr, $dst1",
+ (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
+ IIC_Br, "ldm${addr:submode}${p}${addr:wide} $addr, $wb",
[]>;
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
@@ -1145,7 +1129,10 @@ def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
(t2LEApcrelJT tjumptable:$dst, imm:$id)>;
-// Large immediate handling.
-
-def : T2Pat<(i32 imm:$src),
- (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;
+// 32-bit immediate using movw + movt.
+// This is a single pseudo instruction to make it re-materializable. Remove
+// when we can do generalized remat.
+let isReMaterializable = 1 in
+def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
+ "movw", " $dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
+ [(set GPR:$dst, (i32 imm:$src))]>;
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrVFP.td b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrVFP.td
index f7c16bb..56336d1 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -36,57 +36,57 @@ def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
let canFoldAsLoad = 1 in {
def FLDD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
- IIC_fpLoad, "fldd", " $dst, $addr",
+ IIC_fpLoad64, "fldd", " $dst, $addr",
[(set DPR:$dst, (load addrmode5:$addr))]>;
def FLDS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
- IIC_fpLoad, "flds", " $dst, $addr",
+ IIC_fpLoad32, "flds", " $dst, $addr",
[(set SPR:$dst, (load addrmode5:$addr))]>;
} // canFoldAsLoad
def FSTD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
- IIC_fpStore, "fstd", " $src, $addr",
+ IIC_fpStore64, "fstd", " $src, $addr",
[(store DPR:$src, addrmode5:$addr)]>;
def FSTS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
- IIC_fpStore, "fsts", " $src, $addr",
+ IIC_fpStore32, "fsts", " $src, $addr",
[(store SPR:$src, addrmode5:$addr)]>;
//===----------------------------------------------------------------------===//
// Load / store multiple Instructions.
//
-let mayLoad = 1 in {
-def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
- variable_ops), IIC_fpLoad,
- "fldm${addr:submode}d${p} ${addr:base}, $dst1",
+let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
+def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
+ variable_ops), IIC_fpLoadm,
+ "fldm${addr:submode}d${p} ${addr:base}, $wb",
[]> {
let Inst{20} = 1;
}
-def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
- variable_ops), IIC_fpLoad,
- "fldm${addr:submode}s${p} ${addr:base}, $dst1",
+def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
+ variable_ops), IIC_fpLoadm,
+ "fldm${addr:submode}s${p} ${addr:base}, $wb",
[]> {
let Inst{20} = 1;
}
-}
+} // mayLoad, hasExtraDefRegAllocReq
-let mayStore = 1 in {
-def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
- variable_ops), IIC_fpStore,
- "fstm${addr:submode}d${p} ${addr:base}, $src1",
+let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
+def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
+ variable_ops), IIC_fpStorem,
+ "fstm${addr:submode}d${p} ${addr:base}, $wb",
[]> {
let Inst{20} = 0;
}
-def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
- variable_ops), IIC_fpStore,
- "fstm${addr:submode}s${p} ${addr:base}, $src1",
+def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
+ variable_ops), IIC_fpStorem,
+ "fstm${addr:submode}s${p} ${addr:base}, $wb",
[]> {
let Inst{20} = 0;
}
-} // mayStore
+} // mayStore, hasExtraSrcRegAllocReq
// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
@@ -95,48 +95,48 @@ def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
//
def FADDD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
- IIC_fpALU, "faddd", " $dst, $a, $b",
+ IIC_fpALU64, "faddd", " $dst, $a, $b",
[(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
def FADDS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
- IIC_fpALU, "fadds", " $dst, $a, $b",
+ IIC_fpALU32, "fadds", " $dst, $a, $b",
[(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
// These are encoded as unary instructions.
let Defs = [FPSCR] in {
def FCMPED : ADuI<0b11101011, 0b0100, 0b1100, (outs), (ins DPR:$a, DPR:$b),
- IIC_fpALU, "fcmped", " $a, $b",
+ IIC_fpCMP64, "fcmped", " $a, $b",
[(arm_cmpfp DPR:$a, DPR:$b)]>;
def FCMPES : ASuI<0b11101011, 0b0100, 0b1100, (outs), (ins SPR:$a, SPR:$b),
- IIC_fpALU, "fcmpes", " $a, $b",
+ IIC_fpCMP32, "fcmpes", " $a, $b",
[(arm_cmpfp SPR:$a, SPR:$b)]>;
}
def FDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
- IIC_fpALU, "fdivd", " $dst, $a, $b",
+ IIC_fpDIV64, "fdivd", " $dst, $a, $b",
[(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
def FDIVS : ASbI<0b11101000, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
- IIC_fpALU, "fdivs", " $dst, $a, $b",
+ IIC_fpDIV32, "fdivs", " $dst, $a, $b",
[(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
def FMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
- IIC_fpALU, "fmuld", " $dst, $a, $b",
+ IIC_fpMUL64, "fmuld", " $dst, $a, $b",
[(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
def FMULS : ASbIn<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
- IIC_fpALU, "fmuls", " $dst, $a, $b",
+ IIC_fpMUL32, "fmuls", " $dst, $a, $b",
[(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
def FNMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
- IIC_fpALU, "fnmuld", " $dst, $a, $b",
+ IIC_fpMUL64, "fnmuld", " $dst, $a, $b",
[(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]> {
let Inst{6} = 1;
}
def FNMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
- IIC_fpALU, "fnmuls", " $dst, $a, $b",
+ IIC_fpMUL32, "fnmuls", " $dst, $a, $b",
[(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]> {
let Inst{6} = 1;
}
@@ -149,13 +149,13 @@ def : Pat<(fmul (fneg SPR:$a), SPR:$b),
def FSUBD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
- IIC_fpALU, "fsubd", " $dst, $a, $b",
+ IIC_fpALU64, "fsubd", " $dst, $a, $b",
[(set DPR:$dst, (fsub DPR:$a, DPR:$b))]> {
let Inst{6} = 1;
}
def FSUBS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
- IIC_fpALU, "fsubs", " $dst, $a, $b",
+ IIC_fpALU32, "fsubs", " $dst, $a, $b",
[(set SPR:$dst, (fsub SPR:$a, SPR:$b))]> {
let Inst{6} = 1;
}
@@ -165,30 +165,30 @@ def FSUBS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
//
def FABSD : ADuI<0b11101011, 0b0000, 0b1100, (outs DPR:$dst), (ins DPR:$a),
- IIC_fpALU, "fabsd", " $dst, $a",
+ IIC_fpUNA64, "fabsd", " $dst, $a",
[(set DPR:$dst, (fabs DPR:$a))]>;
def FABSS : ASuIn<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins SPR:$a),
- IIC_fpALU, "fabss", " $dst, $a",
+ IIC_fpUNA32, "fabss", " $dst, $a",
[(set SPR:$dst, (fabs SPR:$a))]>;
let Defs = [FPSCR] in {
def FCMPEZD : ADuI<0b11101011, 0b0101, 0b1100, (outs), (ins DPR:$a),
- IIC_fpALU, "fcmpezd", " $a",
+ IIC_fpCMP64, "fcmpezd", " $a",
[(arm_cmpfp0 DPR:$a)]>;
def FCMPEZS : ASuI<0b11101011, 0b0101, 0b1100, (outs), (ins SPR:$a),
- IIC_fpALU, "fcmpezs", " $a",
+ IIC_fpCMP32, "fcmpezs", " $a",
[(arm_cmpfp0 SPR:$a)]>;
}
def FCVTDS : ASuI<0b11101011, 0b0111, 0b1100, (outs DPR:$dst), (ins SPR:$a),
- IIC_fpALU, "fcvtds", " $dst, $a",
+ IIC_fpCVTDS, "fcvtds", " $dst, $a",
[(set DPR:$dst, (fextend SPR:$a))]>;
// Special case encoding: bits 11-8 is 0b1011.
def FCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
- IIC_fpALU, "fcvtsd", " $dst, $a",
+ IIC_fpCVTSD, "fcvtsd", " $dst, $a",
[(set SPR:$dst, (fround DPR:$a))]> {
let Inst{27-23} = 0b11101;
let Inst{21-16} = 0b110111;
@@ -198,26 +198,26 @@ def FCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
let neverHasSideEffects = 1 in {
def FCPYD : ADuI<0b11101011, 0b0000, 0b0100, (outs DPR:$dst), (ins DPR:$a),
- IIC_fpALU, "fcpyd", " $dst, $a", []>;
+ IIC_fpUNA64, "fcpyd", " $dst, $a", []>;
def FCPYS : ASuI<0b11101011, 0b0000, 0b0100, (outs SPR:$dst), (ins SPR:$a),
- IIC_fpALU, "fcpys", " $dst, $a", []>;
+ IIC_fpUNA32, "fcpys", " $dst, $a", []>;
} // neverHasSideEffects
def FNEGD : ADuI<0b11101011, 0b0001, 0b0100, (outs DPR:$dst), (ins DPR:$a),
- IIC_fpALU, "fnegd", " $dst, $a",
+ IIC_fpUNA64, "fnegd", " $dst, $a",
[(set DPR:$dst, (fneg DPR:$a))]>;
def FNEGS : ASuIn<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins SPR:$a),
- IIC_fpALU, "fnegs", " $dst, $a",
+ IIC_fpUNA32, "fnegs", " $dst, $a",
[(set SPR:$dst, (fneg SPR:$a))]>;
def FSQRTD : ADuI<0b11101011, 0b0001, 0b1100, (outs DPR:$dst), (ins DPR:$a),
- IIC_fpALU, "fsqrtd", " $dst, $a",
+ IIC_fpSQRT64, "fsqrtd", " $dst, $a",
[(set DPR:$dst, (fsqrt DPR:$a))]>;
def FSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins SPR:$a),
- IIC_fpALU, "fsqrts", " $dst, $a",
+ IIC_fpSQRT32, "fsqrts", " $dst, $a",
[(set SPR:$dst, (fsqrt SPR:$a))]>;
//===----------------------------------------------------------------------===//
@@ -225,16 +225,16 @@ def FSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins SPR:$a),
//
def FMRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
- IIC_fpALU, "fmrs", " $dst, $src",
+ IIC_VMOVSI, "fmrs", " $dst, $src",
[(set GPR:$dst, (bitconvert SPR:$src))]>;
def FMSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
- IIC_fpALU, "fmsr", " $dst, $src",
+ IIC_VMOVIS, "fmsr", " $dst, $src",
[(set SPR:$dst, (bitconvert GPR:$src))]>;
def FMRRD : AVConv3I<0b11000101, 0b1011,
- (outs GPR:$dst1, GPR:$dst2), (ins DPR:$src),
- IIC_fpALU, "fmrrd", " $dst1, $dst2, $src",
+ (outs GPR:$wb, GPR:$dst2), (ins DPR:$src),
+ IIC_VMOVDI, "fmrrd", " $wb, $dst2, $src",
[/* FIXME: Can't write pattern for multiple result instr*/]>;
// FMDHR: GPR -> SPR
@@ -242,7 +242,7 @@ def FMRRD : AVConv3I<0b11000101, 0b1011,
def FMDRR : AVConv5I<0b11000100, 0b1011,
(outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
- IIC_fpALU, "fmdrr", " $dst, $src1, $src2",
+ IIC_VMOVID, "fmdrr", " $dst, $src1, $src2",
[(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
// FMRDH: SPR -> GPR
@@ -258,23 +258,23 @@ def FMDRR : AVConv5I<0b11000100, 0b1011,
// Int to FP:
def FSITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
- IIC_fpALU, "fsitod", " $dst, $a",
+ IIC_fpCVTID, "fsitod", " $dst, $a",
[(set DPR:$dst, (arm_sitof SPR:$a))]> {
let Inst{7} = 1;
}
def FSITOS : AVConv1In<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),(ins SPR:$a),
- IIC_fpALU, "fsitos", " $dst, $a",
+ IIC_fpCVTIS, "fsitos", " $dst, $a",
[(set SPR:$dst, (arm_sitof SPR:$a))]> {
let Inst{7} = 1;
}
def FUITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
- IIC_fpALU, "fuitod", " $dst, $a",
+ IIC_fpCVTID, "fuitod", " $dst, $a",
[(set DPR:$dst, (arm_uitof SPR:$a))]>;
def FUITOS : AVConv1In<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),(ins SPR:$a),
- IIC_fpALU, "fuitos", " $dst, $a",
+ IIC_fpCVTIS, "fuitos", " $dst, $a",
[(set SPR:$dst, (arm_uitof SPR:$a))]>;
// FP to Int:
@@ -282,28 +282,28 @@ def FUITOS : AVConv1In<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),(ins SPR:$a),
def FTOSIZD : AVConv1I<0b11101011, 0b1101, 0b1011,
(outs SPR:$dst), (ins DPR:$a),
- IIC_fpALU, "ftosizd", " $dst, $a",
+ IIC_fpCVTDI, "ftosizd", " $dst, $a",
[(set SPR:$dst, (arm_ftosi DPR:$a))]> {
let Inst{7} = 1; // Z bit
}
def FTOSIZS : AVConv1In<0b11101011, 0b1101, 0b1010,
(outs SPR:$dst), (ins SPR:$a),
- IIC_fpALU, "ftosizs", " $dst, $a",
+ IIC_fpCVTSI, "ftosizs", " $dst, $a",
[(set SPR:$dst, (arm_ftosi SPR:$a))]> {
let Inst{7} = 1; // Z bit
}
def FTOUIZD : AVConv1I<0b11101011, 0b1100, 0b1011,
(outs SPR:$dst), (ins DPR:$a),
- IIC_fpALU, "ftouizd", " $dst, $a",
+ IIC_fpCVTDI, "ftouizd", " $dst, $a",
[(set SPR:$dst, (arm_ftoui DPR:$a))]> {
let Inst{7} = 1; // Z bit
}
def FTOUIZS : AVConv1In<0b11101011, 0b1100, 0b1010,
(outs SPR:$dst), (ins SPR:$a),
- IIC_fpALU, "ftouizs", " $dst, $a",
+ IIC_fpCVTSI, "ftouizs", " $dst, $a",
[(set SPR:$dst, (arm_ftoui SPR:$a))]> {
let Inst{7} = 1; // Z bit
}
@@ -313,34 +313,34 @@ def FTOUIZS : AVConv1In<0b11101011, 0b1100, 0b1010,
//
def FMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
- IIC_fpALU, "fmacd", " $dst, $a, $b",
+ IIC_fpMAC64, "fmacd", " $dst, $a, $b",
[(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
def FMACS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
- IIC_fpALU, "fmacs", " $dst, $a, $b",
+ IIC_fpMAC32, "fmacs", " $dst, $a, $b",
[(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
def FMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
- IIC_fpALU, "fmscd", " $dst, $a, $b",
+ IIC_fpMAC64, "fmscd", " $dst, $a, $b",
[(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
def FMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
- IIC_fpALU, "fmscs", " $dst, $a, $b",
+ IIC_fpMAC32, "fmscs", " $dst, $a, $b",
[(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
def FNMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
- IIC_fpALU, "fnmacd", " $dst, $a, $b",
+ IIC_fpMAC64, "fnmacd", " $dst, $a, $b",
[(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
RegConstraint<"$dstin = $dst"> {
let Inst{6} = 1;
}
def FNMACS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
- IIC_fpALU, "fnmacs", " $dst, $a, $b",
+ IIC_fpMAC32, "fnmacs", " $dst, $a, $b",
[(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
RegConstraint<"$dstin = $dst"> {
let Inst{6} = 1;
@@ -352,14 +352,14 @@ def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
(FNMACS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
def FNMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
- IIC_fpALU, "fnmscd", " $dst, $a, $b",
+ IIC_fpMAC64, "fnmscd", " $dst, $a, $b",
[(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
RegConstraint<"$dstin = $dst"> {
let Inst{6} = 1;
}
def FNMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
- IIC_fpALU, "fnmscs", " $dst, $a, $b",
+ IIC_fpMAC32, "fnmscs", " $dst, $a, $b",
[(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
RegConstraint<"$dstin = $dst"> {
let Inst{6} = 1;
@@ -371,25 +371,25 @@ def FNMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
def FCPYDcc : ADuI<0b11101011, 0b0000, 0b0100,
(outs DPR:$dst), (ins DPR:$false, DPR:$true),
- IIC_fpALU, "fcpyd", " $dst, $true",
+ IIC_fpUNA64, "fcpyd", " $dst, $true",
[/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
def FCPYScc : ASuI<0b11101011, 0b0000, 0b0100,
(outs SPR:$dst), (ins SPR:$false, SPR:$true),
- IIC_fpALU, "fcpys", " $dst, $true",
+ IIC_fpUNA32, "fcpys", " $dst, $true",
[/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
def FNEGDcc : ADuI<0b11101011, 0b0001, 0b0100,
(outs DPR:$dst), (ins DPR:$false, DPR:$true),
- IIC_fpALU, "fnegd", " $dst, $true",
+ IIC_fpUNA64, "fnegd", " $dst, $true",
[/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
def FNEGScc : ASuI<0b11101011, 0b0001, 0b0100,
(outs SPR:$dst), (ins SPR:$false, SPR:$true),
- IIC_fpALU, "fnegs", " $dst, $true",
+ IIC_fpUNA32, "fnegs", " $dst, $true",
[/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
@@ -399,7 +399,7 @@ def FNEGScc : ASuI<0b11101011, 0b0001, 0b0100,
//
let Defs = [CPSR], Uses = [FPSCR] in
-def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpALU, "fmstat", "", [(arm_fmstat)]> {
+def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "fmstat", "", [(arm_fmstat)]> {
let Inst{27-20} = 0b11101111;
let Inst{19-16} = 0b0001;
let Inst{15-12} = 0b1111;
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMJITInfo.cpp b/libclamav/c++/llvm/lib/Target/ARM/ARMJITInfo.cpp
index 0456f33..24990e6 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMJITInfo.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMJITInfo.cpp
@@ -140,7 +140,14 @@ ARMJITInfo::getLazyResolverFunction(JITCompilerFn F) {
void *ARMJITInfo::emitGlobalValueIndirectSym(const GlobalValue *GV, void *Ptr,
JITCodeEmitter &JCE) {
JCE.startGVStub(GV, 4, 4);
+ intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
+ if (!sys::Memory::setRangeWritable((void*)Addr, 4)) {
+ llvm_unreachable("ERROR: Unable to mark indirect symbol writable");
+ }
JCE.emitWordLE((intptr_t)Ptr);
+ if (!sys::Memory::setRangeExecutable((void*)Addr, 4)) {
+ llvm_unreachable("ERROR: Unable to mark indirect symbol executable");
+ }
void *PtrAddr = JCE.finishGVStub(GV);
addIndirectSymAddr(Ptr, (intptr_t)PtrAddr);
return PtrAddr;
@@ -167,18 +174,30 @@ void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
}
JCE.startGVStub(F, 16, 4);
intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
+ if (!sys::Memory::setRangeWritable((void*)Addr, 16)) {
+ llvm_unreachable("ERROR: Unable to mark stub writable");
+ }
JCE.emitWordLE(0xe59fc004); // ldr pc, [pc, #+4]
JCE.emitWordLE(0xe08fc00c); // L_func$scv: add ip, pc, ip
JCE.emitWordLE(0xe59cf000); // ldr pc, [ip]
JCE.emitWordLE(LazyPtr - (Addr+4+8)); // func - (L_func$scv+8)
sys::Memory::InvalidateInstructionCache((void*)Addr, 16);
+ if (!sys::Memory::setRangeExecutable((void*)Addr, 16)) {
+ llvm_unreachable("ERROR: Unable to mark stub executable");
+ }
} else {
// The stub is 8-byte size and 4-aligned.
JCE.startGVStub(F, 8, 4);
intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
+ if (!sys::Memory::setRangeWritable((void*)Addr, 8)) {
+ llvm_unreachable("ERROR: Unable to mark stub writable");
+ }
JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
JCE.emitWordLE((intptr_t)Fn); // addr of function
sys::Memory::InvalidateInstructionCache((void*)Addr, 8);
+ if (!sys::Memory::setRangeExecutable((void*)Addr, 8)) {
+ llvm_unreachable("ERROR: Unable to mark stub executable");
+ }
}
} else {
// The compilation callback will overwrite the first two words of this
@@ -190,6 +209,9 @@ void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
// The stub is 16-byte size and 4-byte aligned.
JCE.startGVStub(F, 16, 4);
intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
+ if (!sys::Memory::setRangeWritable((void*)Addr, 16)) {
+ llvm_unreachable("ERROR: Unable to mark stub writable");
+ }
// Save LR so the callback can determine which stub called it.
// The compilation callback is responsible for popping this prior
// to returning.
@@ -201,6 +223,9 @@ void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
// The address of the compilation callback.
JCE.emitWordLE((intptr_t)ARMCompilationCallback);
sys::Memory::InvalidateInstructionCache((void*)Addr, 16);
+ if (!sys::Memory::setRangeExecutable((void*)Addr, 16)) {
+ llvm_unreachable("ERROR: Unable to mark stub executable");
+ }
}
return JCE.finishGVStub(F);
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/libclamav/c++/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index d927dd2..d2ec9ee 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -241,6 +241,7 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
.addReg(Base, getKillRegState(BaseKill))
.addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
.addImm(Pred).addReg(PredReg);
+ MIB.addReg(0); // Add optional writeback (0 for now).
for (unsigned i = 0; i != NumRegs; ++i)
MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
| getKillRegState(Regs[i].second));
@@ -383,7 +384,7 @@ static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
case ARM::STM:
case ARM::t2LDM:
case ARM::t2STM:
- return (MI->getNumOperands() - 4) * 4;
+ return (MI->getNumOperands() - 5) * 4;
case ARM::FLDMS:
case ARM::FSTMS:
case ARM::FLDMD:
@@ -434,11 +435,15 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
if (Mode == ARM_AM::ia &&
isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::db, true));
+ MI->getOperand(4).setReg(Base);
+ MI->getOperand(4).setIsDef();
MBB.erase(PrevMBBI);
return true;
} else if (Mode == ARM_AM::ib &&
isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::da, true));
+ MI->getOperand(4).setReg(Base); // WB to base
+ MI->getOperand(4).setIsDef();
MBB.erase(PrevMBBI);
return true;
}
@@ -449,6 +454,8 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
+ MI->getOperand(4).setReg(Base); // WB to base
+ MI->getOperand(4).setIsDef();
if (NextMBBI == I) {
Advance = true;
++I;
@@ -458,6 +465,8 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
} else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
+ MI->getOperand(4).setReg(Base); // WB to base
+ MI->getOperand(4).setIsDef();
if (NextMBBI == I) {
Advance = true;
++I;
@@ -478,6 +487,8 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
if (Mode == ARM_AM::ia &&
isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::db, true, Offset));
+ MI->getOperand(4).setReg(Base); // WB to base
+ MI->getOperand(4).setIsDef();
MBB.erase(PrevMBBI);
return true;
}
@@ -488,6 +499,8 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
if (Mode == ARM_AM::ia &&
isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset));
+ MI->getOperand(4).setReg(Base); // WB to base
+ MI->getOperand(4).setIsDef();
if (NextMBBI == I) {
Advance = true;
++I;
@@ -630,6 +643,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
.addReg(Base, getKillRegState(BaseKill))
.addImm(Offset).addImm(Pred).addReg(PredReg)
+ .addReg(Base, getDefRegState(true)) // WB base register
.addReg(MI->getOperand(0).getReg(), RegState::Define);
else if (isAM2)
// LDR_PRE, LDR_POST,
@@ -647,6 +661,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
// FSTMS, FSTMD
BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset)
.addImm(Pred).addReg(PredReg)
+ .addReg(Base, getDefRegState(true)) // WB base register
.addReg(MO.getReg(), getKillRegState(MO.isKill()));
else if (isAM2)
// STR_PRE, STR_POST
@@ -683,7 +698,7 @@ static bool isMemoryOp(const MachineInstr *MI) {
case ARM::t2LDRi12:
case ARM::t2STRi8:
case ARM::t2STRi12:
- return true;
+ return MI->getOperand(1).isReg();
}
return false;
}
@@ -737,37 +752,43 @@ static void InsertLDR_STR(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
int OffImm, bool isDef,
DebugLoc dl, unsigned NewOpc,
- unsigned Reg, bool RegDeadKill,
- unsigned BaseReg, bool BaseKill,
- unsigned OffReg, bool OffKill,
+ unsigned Reg, bool RegDeadKill, bool RegUndef,
+ unsigned BaseReg, bool BaseKill, bool BaseUndef,
+ unsigned OffReg, bool OffKill, bool OffUndef,
ARMCC::CondCodes Pred, unsigned PredReg,
- const TargetInstrInfo *TII) {
- unsigned Offset;
- if (OffImm < 0)
- Offset = ARM_AM::getAM2Opc(ARM_AM::sub, -OffImm, ARM_AM::no_shift);
- else
- Offset = ARM_AM::getAM2Opc(ARM_AM::add, OffImm, ARM_AM::no_shift);
- if (isDef)
- BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
+ const TargetInstrInfo *TII, bool isT2) {
+ int Offset = OffImm;
+ if (!isT2) {
+ if (OffImm < 0)
+ Offset = ARM_AM::getAM2Opc(ARM_AM::sub, -OffImm, ARM_AM::no_shift);
+ else
+ Offset = ARM_AM::getAM2Opc(ARM_AM::add, OffImm, ARM_AM::no_shift);
+ }
+ if (isDef) {
+ MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
+ TII->get(NewOpc))
.addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
- .addReg(BaseReg, getKillRegState(BaseKill))
- .addReg(OffReg, getKillRegState(OffKill))
- .addImm(Offset)
- .addImm(Pred).addReg(PredReg);
- else
- BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
- .addReg(Reg, getKillRegState(RegDeadKill))
- .addReg(BaseReg, getKillRegState(BaseKill))
- .addReg(OffReg, getKillRegState(OffKill))
- .addImm(Offset)
- .addImm(Pred).addReg(PredReg);
+ .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
+ if (!isT2)
+ MIB.addReg(OffReg, getKillRegState(OffKill)|getUndefRegState(OffUndef));
+ MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
+ } else {
+ MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
+ TII->get(NewOpc))
+ .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
+ .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
+ if (!isT2)
+ MIB.addReg(OffReg, getKillRegState(OffKill)|getUndefRegState(OffUndef));
+ MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
+ }
}
bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI) {
MachineInstr *MI = &*MBBI;
unsigned Opcode = MI->getOpcode();
- if (Opcode == ARM::LDRD || Opcode == ARM::STRD) {
+ if (Opcode == ARM::LDRD || Opcode == ARM::STRD ||
+ Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) {
unsigned EvenReg = MI->getOperand(0).getReg();
unsigned OddReg = MI->getOperand(1).getReg();
unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);
@@ -775,17 +796,21 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
if ((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum)
return false;
- bool isLd = Opcode == ARM::LDRD;
+ bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;
+ bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
bool EvenDeadKill = isLd ?
MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
+ bool EvenUndef = MI->getOperand(0).isUndef();
bool OddDeadKill = isLd ?
MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
+ bool OddUndef = MI->getOperand(1).isUndef();
const MachineOperand &BaseOp = MI->getOperand(2);
unsigned BaseReg = BaseOp.getReg();
bool BaseKill = BaseOp.isKill();
- const MachineOperand &OffOp = MI->getOperand(3);
- unsigned OffReg = OffOp.getReg();
- bool OffKill = OffOp.isKill();
+ bool BaseUndef = BaseOp.isUndef();
+ unsigned OffReg = isT2 ? 0 : MI->getOperand(3).getReg();
+ bool OffKill = isT2 ? false : MI->getOperand(3).isKill();
+ bool OffUndef = isT2 ? false : MI->getOperand(3).isUndef();
int OffImm = getMemoryOpOffset(MI);
unsigned PredReg = 0;
ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg);
@@ -793,27 +818,37 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
if (OddRegNum > EvenRegNum && OffReg == 0 && OffImm == 0) {
// Ascending register numbers and no offset. It's safe to change it to a
// ldm or stm.
- unsigned NewOpc = (Opcode == ARM::LDRD) ? ARM::LDM : ARM::STM;
+ unsigned NewOpc = (isLd)
+ ? (isT2 ? ARM::t2LDM : ARM::LDM)
+ : (isT2 ? ARM::t2STM : ARM::STM);
if (isLd) {
BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
.addReg(BaseReg, getKillRegState(BaseKill))
.addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
.addImm(Pred).addReg(PredReg)
+ .addReg(0)
.addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
- .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill));
+ .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill));
++NumLDRD2LDM;
} else {
BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
.addReg(BaseReg, getKillRegState(BaseKill))
.addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
.addImm(Pred).addReg(PredReg)
- .addReg(EvenReg, getKillRegState(EvenDeadKill))
- .addReg(OddReg, getKillRegState(OddDeadKill));
+ .addReg(0)
+ .addReg(EvenReg,
+ getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
+ .addReg(OddReg,
+ getKillRegState(OddDeadKill) | getUndefRegState(OddUndef));
++NumSTRD2STM;
}
} else {
// Split into two instructions.
- unsigned NewOpc = (Opcode == ARM::LDRD) ? ARM::LDR : ARM::STR;
+ assert((!isT2 || !OffReg) &&
+ "Thumb2 ldrd / strd does not encode offset register!");
+ unsigned NewOpc = (isLd)
+ ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDR)
+ : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STR);
DebugLoc dl = MBBI->getDebugLoc();
// If this is a load and base register is killed, it may have been
// re-defed by the load, make sure the first load does not clobber it.
@@ -823,17 +858,23 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
(OffReg && TRI->regsOverlap(EvenReg, OffReg)))) {
assert(!TRI->regsOverlap(OddReg, BaseReg) &&
(!OffReg || !TRI->regsOverlap(OddReg, OffReg)));
- InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc, OddReg, OddDeadKill,
- BaseReg, false, OffReg, false, Pred, PredReg, TII);
- InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, EvenReg, EvenDeadKill,
- BaseReg, BaseKill, OffReg, OffKill, Pred, PredReg, TII);
+ InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc,
+ OddReg, OddDeadKill, false,
+ BaseReg, false, BaseUndef, OffReg, false, OffUndef,
+ Pred, PredReg, TII, isT2);
+ InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
+ EvenReg, EvenDeadKill, false,
+ BaseReg, BaseKill, BaseUndef, OffReg, OffKill, OffUndef,
+ Pred, PredReg, TII, isT2);
} else {
InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
- EvenReg, EvenDeadKill, BaseReg, false, OffReg, false,
- Pred, PredReg, TII);
+ EvenReg, EvenDeadKill, EvenUndef,
+ BaseReg, false, BaseUndef, OffReg, false, OffUndef,
+ Pred, PredReg, TII, isT2);
InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc,
- OddReg, OddDeadKill, BaseReg, BaseKill, OffReg, OffKill,
- Pred, PredReg, TII);
+ OddReg, OddDeadKill, OddUndef,
+ BaseReg, BaseKill, BaseUndef, OffReg, OffKill, OffUndef,
+ Pred, PredReg, TII, isT2);
}
if (isLd)
++NumLDRD2LDR;
@@ -942,7 +983,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
// First advance to the instruction just before the start of the chain.
AdvanceRS(MBB, MemOps);
// Find a scratch register.
- unsigned Scratch = RS->FindUnusedReg(&ARM::GPRRegClass);
+ unsigned Scratch = RS->FindUnusedReg(ARM::GPRRegisterClass);
// Process the load / store instructions.
RS->forward(prior(MBBI));
@@ -1071,6 +1112,7 @@ namespace {
const TargetRegisterInfo *TRI;
const ARMSubtarget *STI;
MachineRegisterInfo *MRI;
+ MachineFunction *MF;
virtual bool runOnMachineFunction(MachineFunction &Fn);
@@ -1082,8 +1124,9 @@ namespace {
bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl,
unsigned &NewOpc, unsigned &EvenReg,
unsigned &OddReg, unsigned &BaseReg,
- unsigned &OffReg, unsigned &Offset,
- unsigned &PredReg, ARMCC::CondCodes &Pred);
+ unsigned &OffReg, int &Offset,
+ unsigned &PredReg, ARMCC::CondCodes &Pred,
+ bool &isT2);
bool RescheduleOps(MachineBasicBlock *MBB,
SmallVector<MachineInstr*, 4> &Ops,
unsigned Base, bool isLd,
@@ -1099,6 +1142,7 @@ bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
TRI = Fn.getTarget().getRegisterInfo();
STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
MRI = &Fn.getRegInfo();
+ MF = &Fn;
bool Modified = false;
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
@@ -1160,49 +1204,82 @@ ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
DebugLoc &dl,
unsigned &NewOpc, unsigned &EvenReg,
unsigned &OddReg, unsigned &BaseReg,
- unsigned &OffReg, unsigned &Offset,
+ unsigned &OffReg, int &Offset,
unsigned &PredReg,
- ARMCC::CondCodes &Pred) {
+ ARMCC::CondCodes &Pred,
+ bool &isT2) {
+ // Make sure we're allowed to generate LDRD/STRD.
+ if (!STI->hasV5TEOps())
+ return false;
+
// FIXME: FLDS / FSTS -> FLDD / FSTD
+ unsigned Scale = 1;
unsigned Opcode = Op0->getOpcode();
if (Opcode == ARM::LDR)
NewOpc = ARM::LDRD;
else if (Opcode == ARM::STR)
NewOpc = ARM::STRD;
- else
- return 0;
+ else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {
+ NewOpc = ARM::t2LDRDi8;
+ Scale = 4;
+ isT2 = true;
+ } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) {
+ NewOpc = ARM::t2STRDi8;
+ Scale = 4;
+ isT2 = true;
+ } else
+ return false;
+
+ // Make sure the offset registers match.
+ if (!isT2 &&
+ (Op0->getOperand(2).getReg() != Op1->getOperand(2).getReg()))
+ return false;
// Must sure the base address satisfies i64 ld / st alignment requirement.
if (!Op0->hasOneMemOperand() ||
- !Op0->memoperands_begin()->getValue() ||
- Op0->memoperands_begin()->isVolatile())
+ !(*Op0->memoperands_begin())->getValue() ||
+ (*Op0->memoperands_begin())->isVolatile())
return false;
- unsigned Align = Op0->memoperands_begin()->getAlignment();
+ unsigned Align = (*Op0->memoperands_begin())->getAlignment();
+ Function *Func = MF->getFunction();
unsigned ReqAlign = STI->hasV6Ops()
- ? TD->getPrefTypeAlignment(
- Type::getInt64Ty(Op0->getParent()->getParent()->getFunction()->getContext()))
- : 8; // Pre-v6 need 8-byte align
+ ? TD->getPrefTypeAlignment(Type::getInt64Ty(Func->getContext()))
+ : 8; // Pre-v6 need 8-byte align
if (Align < ReqAlign)
return false;
// Then make sure the immediate offset fits.
int OffImm = getMemoryOpOffset(Op0);
- ARM_AM::AddrOpc AddSub = ARM_AM::add;
- if (OffImm < 0) {
- AddSub = ARM_AM::sub;
- OffImm = - OffImm;
+ if (isT2) {
+ if (OffImm < 0) {
+ if (OffImm < -255)
+ // Can't fall back to t2LDRi8 / t2STRi8.
+ return false;
+ } else {
+ int Limit = (1 << 8) * Scale;
+ if (OffImm >= Limit || (OffImm & (Scale-1)))
+ return false;
+ }
+ Offset = OffImm;
+ } else {
+ ARM_AM::AddrOpc AddSub = ARM_AM::add;
+ if (OffImm < 0) {
+ AddSub = ARM_AM::sub;
+ OffImm = - OffImm;
+ }
+ int Limit = (1 << 8) * Scale;
+ if (OffImm >= Limit || (OffImm & (Scale-1)))
+ return false;
+ Offset = ARM_AM::getAM3Opc(AddSub, OffImm);
}
- if (OffImm >= 256) // 8 bits
- return false;
- Offset = ARM_AM::getAM3Opc(AddSub, OffImm);
-
EvenReg = Op0->getOperand(0).getReg();
OddReg = Op1->getOperand(0).getReg();
if (EvenReg == OddReg)
return false;
BaseReg = Op0->getOperand(1).getReg();
- OffReg = Op0->getOperand(2).getReg();
+ if (!isT2)
+ OffReg = Op0->getOperand(2).getReg();
Pred = llvm::getInstrPredicate(Op0, PredReg);
dl = Op0->getDebugLoc();
return true;
@@ -1255,7 +1332,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
LastOffset = Offset;
LastBytes = Bytes;
LastOpcode = Opcode;
- if (++NumMove == 8) // FIXME: Tune
+ if (++NumMove == 8) // FIXME: Tune this limit.
break;
}
@@ -1291,29 +1368,36 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
unsigned EvenReg = 0, OddReg = 0;
unsigned BaseReg = 0, OffReg = 0, PredReg = 0;
ARMCC::CondCodes Pred = ARMCC::AL;
+ bool isT2 = false;
unsigned NewOpc = 0;
- unsigned Offset = 0;
+ int Offset = 0;
DebugLoc dl;
if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc,
EvenReg, OddReg, BaseReg, OffReg,
- Offset, PredReg, Pred)) {
+ Offset, PredReg, Pred, isT2)) {
Ops.pop_back();
Ops.pop_back();
// Form the pair instruction.
if (isLd) {
- BuildMI(*MBB, InsertPos, dl, TII->get(NewOpc))
+ MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos,
+ dl, TII->get(NewOpc))
.addReg(EvenReg, RegState::Define)
.addReg(OddReg, RegState::Define)
- .addReg(BaseReg).addReg(0).addImm(Offset)
- .addImm(Pred).addReg(PredReg);
+ .addReg(BaseReg);
+ if (!isT2)
+ MIB.addReg(OffReg);
+ MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
++NumLDRDFormed;
} else {
- BuildMI(*MBB, InsertPos, dl, TII->get(NewOpc))
+ MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos,
+ dl, TII->get(NewOpc))
.addReg(EvenReg)
.addReg(OddReg)
- .addReg(BaseReg).addReg(0).addImm(Offset)
- .addImm(Pred).addReg(PredReg);
+ .addReg(BaseReg);
+ if (!isT2)
+ MIB.addReg(OffReg);
+ MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
++NumSTRDFormed;
}
MBB->erase(Op0);
@@ -1369,9 +1453,8 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
if (llvm::getInstrPredicate(MI, PredReg) != ARMCC::AL)
continue;
- int Opcode = MI->getOpcode();
- bool isLd = Opcode == ARM::LDR ||
- Opcode == ARM::FLDS || Opcode == ARM::FLDD;
+ int Opc = MI->getOpcode();
+ bool isLd = isi32Load(Opc) || Opc == ARM::FLDS || Opc == ARM::FLDD;
unsigned Base = MI->getOperand(1).getReg();
int Offset = getMemoryOpOffset(MI);
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMPerfectShuffle.h b/libclamav/c++/llvm/lib/Target/ARM/ARMPerfectShuffle.h
index 51da27a..5ff7c38 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMPerfectShuffle.h
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMPerfectShuffle.h
@@ -14,159 +14,159 @@
// 31 entries have cost 0
// 242 entries have cost 1
-// 1374 entries have cost 2
-// 3515 entries have cost 3
-// 1390 entries have cost 4
-// 9 entries have cost 5
+// 1447 entries have cost 2
+// 3602 entries have cost 3
+// 1237 entries have cost 4
+// 2 entries have cost 5
// This table is 6561*4 = 26244 bytes in size.
static const unsigned PerfectShuffleTable[6561+1] = {
135053414U, // <0,0,0,0>: Cost 1 vdup0 LHS
1543503974U, // <0,0,0,1>: Cost 2 vext2 <0,0,0,0>, LHS
- 2819407872U, // <0,0,0,2>: Cost 3 vuzpr LHS, <0,0,0,0>
+ 2618572962U, // <0,0,0,2>: Cost 3 vext2 <0,2,0,0>, <0,2,0,0>
2568054923U, // <0,0,0,3>: Cost 3 vext1 <3,0,0,0>, <3,0,0,0>
1476398390U, // <0,0,0,4>: Cost 2 vext1 <0,0,0,0>, RHS
2550140624U, // <0,0,0,5>: Cost 3 vext1 <0,0,0,0>, <5,1,7,3>
2550141434U, // <0,0,0,6>: Cost 3 vext1 <0,0,0,0>, <6,2,7,3>
2591945711U, // <0,0,0,7>: Cost 3 vext1 <7,0,0,0>, <7,0,0,0>
135053414U, // <0,0,0,u>: Cost 1 vdup0 LHS
- 2556117094U, // <0,0,1,0>: Cost 3 vext1 <1,0,0,1>, LHS
- 1879883878U, // <0,0,1,1>: Cost 2 vzipr LHS, LHS
+ 2886516736U, // <0,0,1,0>: Cost 3 vzipl LHS, <0,0,0,0>
+ 1812775014U, // <0,0,1,1>: Cost 2 vzipl LHS, LHS
1618133094U, // <0,0,1,2>: Cost 2 vext3 <1,2,3,0>, LHS
- 2568063116U, // <0,0,1,3>: Cost 3 vext1 <3,0,0,1>, <3,0,0,1>
- 2556120374U, // <0,0,1,4>: Cost 3 vext1 <1,0,0,1>, RHS
+ 2625209292U, // <0,0,1,3>: Cost 3 vext2 <1,3,0,0>, <1,3,0,0>
+ 2886558034U, // <0,0,1,4>: Cost 3 vzipl LHS, <0,4,1,5>
2617246864U, // <0,0,1,5>: Cost 3 vext2 <0,0,0,0>, <1,5,3,7>
- 3629863418U, // <0,0,1,6>: Cost 4 vext1 <1,0,0,1>, <6,2,7,3>
+ 3659723031U, // <0,0,1,6>: Cost 4 vext1 <6,0,0,1>, <6,0,0,1>
2591953904U, // <0,0,1,7>: Cost 3 vext1 <7,0,0,1>, <7,0,0,1>
- 1884528742U, // <0,0,1,u>: Cost 2 vzipr LHS, LHS
- 3088351334U, // <0,0,2,0>: Cost 3 vtrnr <0,2,0,2>, LHS
- 2953625764U, // <0,0,2,1>: Cost 3 vzipr LHS, <0,2,0,2>
- 2014101606U, // <0,0,2,2>: Cost 2 vtrnr LHS, LHS
+ 1812775581U, // <0,0,1,u>: Cost 2 vzipl LHS, LHS
+ 3020734464U, // <0,0,2,0>: Cost 3 vtrnl LHS, <0,0,0,0>
+ 3020734474U, // <0,0,2,1>: Cost 3 vtrnl LHS, <0,0,1,1>
+ 1946992742U, // <0,0,2,2>: Cost 2 vtrnl LHS, LHS
2631181989U, // <0,0,2,3>: Cost 3 vext2 <2,3,0,0>, <2,3,0,0>
- 2562100534U, // <0,0,2,4>: Cost 3 vext1 <2,0,0,2>, RHS
- 3635842768U, // <0,0,2,5>: Cost 4 vext1 <2,0,0,2>, <5,1,7,3>
+ 3020734668U, // <0,0,2,4>: Cost 3 vtrnl LHS, <0,2,4,6>
+ 3826550569U, // <0,0,2,5>: Cost 4 vuzpl <0,2,0,2>, <2,4,5,6>
2617247674U, // <0,0,2,6>: Cost 3 vext2 <0,0,0,0>, <2,6,3,7>
2591962097U, // <0,0,2,7>: Cost 3 vext1 <7,0,0,2>, <7,0,0,2>
- 2014543974U, // <0,0,2,u>: Cost 2 vtrnr LHS, LHS
+ 1946992796U, // <0,0,2,u>: Cost 2 vtrnl LHS, LHS
2635163787U, // <0,0,3,0>: Cost 3 vext2 <3,0,0,0>, <3,0,0,0>
- 3704260849U, // <0,0,3,1>: Cost 4 vext2 <2,2,0,0>, <3,1,2,3>
+ 2686419196U, // <0,0,3,1>: Cost 3 vext3 <0,3,1,0>, <0,3,1,0>
2686492933U, // <0,0,3,2>: Cost 3 vext3 <0,3,2,0>, <0,3,2,0>
2617248156U, // <0,0,3,3>: Cost 3 vext2 <0,0,0,0>, <3,3,3,3>
2617248258U, // <0,0,3,4>: Cost 3 vext2 <0,0,0,0>, <3,4,5,6>
- 3913302016U, // <0,0,3,5>: Cost 4 vuzpr <3,4,5,6>, <0,0,0,0>
- 3690990218U, // <0,0,3,6>: Cost 4 vext2 <0,0,0,0>, <3,6,2,7>
- 3690990275U, // <0,0,3,7>: Cost 4 vext2 <0,0,0,0>, <3,7,0,1>
+ 3826551298U, // <0,0,3,5>: Cost 4 vuzpl <0,2,0,2>, <3,4,5,6>
+ 3690990200U, // <0,0,3,6>: Cost 4 vext2 <0,0,0,0>, <3,6,0,7>
+ 3713551042U, // <0,0,3,7>: Cost 4 vext2 <3,7,0,0>, <3,7,0,0>
2635163787U, // <0,0,3,u>: Cost 3 vext2 <3,0,0,0>, <3,0,0,0>
- 2643790738U, // <0,0,4,0>: Cost 3 vext2 <4,4,0,0>, <4,0,5,1>
- 2718712146U, // <0,0,4,1>: Cost 3 vext3 <5,6,7,0>, <0,4,1,5>
- 2718712156U, // <0,0,4,2>: Cost 3 vext3 <5,6,7,0>, <0,4,2,6>
+ 2617248658U, // <0,0,4,0>: Cost 3 vext2 <0,0,0,0>, <4,0,5,1>
+ 2888450150U, // <0,0,4,1>: Cost 3 vzipl <0,4,1,5>, LHS
+ 3021570150U, // <0,0,4,2>: Cost 3 vtrnl <0,2,4,6>, LHS
3641829519U, // <0,0,4,3>: Cost 4 vext1 <3,0,0,4>, <3,0,0,4>
- 2643791016U, // <0,0,4,4>: Cost 3 vext2 <4,4,0,0>, <4,4,0,0>
+ 3021570252U, // <0,0,4,4>: Cost 3 vtrnl <0,2,4,6>, <0,2,4,6>
1543507254U, // <0,0,4,5>: Cost 2 vext2 <0,0,0,0>, RHS
- 2846277632U, // <0,0,4,6>: Cost 3 vuzpr RHS, <0,0,0,0>
- 3665720307U, // <0,0,4,7>: Cost 4 vext1 <7,0,0,4>, <7,0,0,4>
+ 2752810294U, // <0,0,4,6>: Cost 3 vuzpl <0,2,0,2>, RHS
+ 3786998152U, // <0,0,4,7>: Cost 4 vext3 <4,7,5,0>, <0,4,7,5>
1543507497U, // <0,0,4,u>: Cost 2 vext2 <0,0,0,0>, RHS
2684354972U, // <0,0,5,0>: Cost 3 vext3 <0,0,0,0>, <0,5,0,7>
2617249488U, // <0,0,5,1>: Cost 3 vext2 <0,0,0,0>, <5,1,7,3>
- 3696299808U, // <0,0,5,2>: Cost 4 vext2 <0,u,0,0>, <5,2,7,2>
- 3690991471U, // <0,0,5,3>: Cost 4 vext2 <0,0,0,0>, <5,3,7,0>
+ 3765617070U, // <0,0,5,2>: Cost 4 vext3 <1,2,3,0>, <0,5,2,7>
+ 3635865780U, // <0,0,5,3>: Cost 4 vext1 <2,0,0,5>, <3,0,4,5>
2617249734U, // <0,0,5,4>: Cost 3 vext2 <0,0,0,0>, <5,4,7,6>
2617249796U, // <0,0,5,5>: Cost 3 vext2 <0,0,0,0>, <5,5,5,5>
2718712274U, // <0,0,5,6>: Cost 3 vext3 <5,6,7,0>, <0,5,6,7>
- 3923378176U, // <0,0,5,7>: Cost 4 vuzpr <5,1,7,3>, <0,0,0,0>
+ 2617249960U, // <0,0,5,7>: Cost 3 vext2 <0,0,0,0>, <5,7,5,7>
2720039396U, // <0,0,5,u>: Cost 3 vext3 <5,u,7,0>, <0,5,u,7>
2684355053U, // <0,0,6,0>: Cost 3 vext3 <0,0,0,0>, <0,6,0,7>
- 3786113526U, // <0,0,6,1>: Cost 4 vext3 <4,6,2,0>, <0,6,1,7>
+ 3963609190U, // <0,0,6,1>: Cost 4 vzipl <0,6,2,7>, LHS
2617250298U, // <0,0,6,2>: Cost 3 vext2 <0,0,0,0>, <6,2,7,3>
- 3704263240U, // <0,0,6,3>: Cost 4 vext2 <2,2,0,0>, <6,3,7,0>
- 3729478234U, // <0,0,6,4>: Cost 4 vext2 <6,4,0,0>, <6,4,0,0>
- 3717534443U, // <0,0,6,5>: Cost 4 vext2 <4,4,0,0>, <6,5,7,1>
+ 3796435464U, // <0,0,6,3>: Cost 4 vext3 <6,3,7,0>, <0,6,3,7>
+ 3659762998U, // <0,0,6,4>: Cost 4 vext1 <6,0,0,6>, RHS
+ 3659763810U, // <0,0,6,5>: Cost 4 vext1 <6,0,0,6>, <5,6,7,0>
2617250616U, // <0,0,6,6>: Cost 3 vext2 <0,0,0,0>, <6,6,6,6>
2657727309U, // <0,0,6,7>: Cost 3 vext2 <6,7,0,0>, <6,7,0,0>
2658390942U, // <0,0,6,u>: Cost 3 vext2 <6,u,0,0>, <6,u,0,0>
2659054575U, // <0,0,7,0>: Cost 3 vext2 <7,0,0,0>, <7,0,0,0>
- 3934208000U, // <0,0,7,1>: Cost 4 vuzpr <7,0,1,2>, <0,0,0,0>
- 3934265508U, // <0,0,7,2>: Cost 4 vuzpr <7,0,2,0>, <0,2,0,2>
+ 3635880854U, // <0,0,7,1>: Cost 4 vext1 <2,0,0,7>, <1,2,3,0>
+ 3635881401U, // <0,0,7,2>: Cost 4 vext1 <2,0,0,7>, <2,0,0,7>
3734787298U, // <0,0,7,3>: Cost 4 vext2 <7,3,0,0>, <7,3,0,0>
2617251174U, // <0,0,7,4>: Cost 3 vext2 <0,0,0,0>, <7,4,5,6>
- 3665743970U, // <0,0,7,5>: Cost 4 vext1 <7,0,0,7>, <5,6,7,0>
- 3665744562U, // <0,0,7,6>: Cost 4 vext1 <7,0,0,7>, <6,5,0,7>
+ 3659772002U, // <0,0,7,5>: Cost 4 vext1 <6,0,0,7>, <5,6,7,0>
+ 3659772189U, // <0,0,7,6>: Cost 4 vext1 <6,0,0,7>, <6,0,0,7>
2617251436U, // <0,0,7,7>: Cost 3 vext2 <0,0,0,0>, <7,7,7,7>
2659054575U, // <0,0,7,u>: Cost 3 vext2 <7,0,0,0>, <7,0,0,0>
135053414U, // <0,0,u,0>: Cost 1 vdup0 LHS
- 1879884445U, // <0,0,u,1>: Cost 2 vzipr LHS, LHS
- 2014101660U, // <0,0,u,2>: Cost 2 vtrnr LHS, LHS
+ 1817419878U, // <0,0,u,1>: Cost 2 vzipl LHS, LHS
+ 1947435110U, // <0,0,u,2>: Cost 2 vtrnl LHS, LHS
2568120467U, // <0,0,u,3>: Cost 3 vext1 <3,0,0,u>, <3,0,0,u>
1476463926U, // <0,0,u,4>: Cost 2 vext1 <0,0,0,u>, RHS
1543510170U, // <0,0,u,5>: Cost 2 vext2 <0,0,0,0>, RHS
- 2870165504U, // <0,0,u,6>: Cost 3 vuzpr RHS, <0,0,0,0>
+ 2752813210U, // <0,0,u,6>: Cost 3 vuzpl <0,2,0,2>, RHS
2592011255U, // <0,0,u,7>: Cost 3 vext1 <7,0,0,u>, <7,0,0,u>
135053414U, // <0,0,u,u>: Cost 1 vdup0 LHS
- 2631188480U, // <0,1,0,0>: Cost 3 vext2 <2,3,0,1>, <0,0,0,0>
+ 2618581002U, // <0,1,0,0>: Cost 3 vext2 <0,2,0,1>, <0,0,1,1>
1557446758U, // <0,1,0,1>: Cost 2 vext2 <2,3,0,1>, LHS
- 2819448842U, // <0,1,0,2>: Cost 3 vuzpr LHS, <0,0,1,1>
- 3020734464U, // <0,1,0,3>: Cost 3 vtrnl LHS, <0,0,0,0>
- 2568129846U, // <0,1,0,4>: Cost 3 vext1 <3,0,1,0>, RHS
- 3641872080U, // <0,1,0,5>: Cost 4 vext1 <3,0,1,0>, <5,1,7,3>
+ 2618581155U, // <0,1,0,2>: Cost 3 vext2 <0,2,0,1>, <0,2,0,1>
+ 2690548468U, // <0,1,0,3>: Cost 3 vext3 <1,0,3,0>, <1,0,3,0>
+ 2626543954U, // <0,1,0,4>: Cost 3 vext2 <1,5,0,1>, <0,4,1,5>
+ 4094985216U, // <0,1,0,5>: Cost 4 vtrnl <0,2,0,2>, <1,3,5,7>
2592019278U, // <0,1,0,6>: Cost 3 vext1 <7,0,1,0>, <6,7,0,1>
2592019448U, // <0,1,0,7>: Cost 3 vext1 <7,0,1,0>, <7,0,1,0>
1557447325U, // <0,1,0,u>: Cost 2 vext2 <2,3,0,1>, LHS
- 1524252774U, // <0,1,1,0>: Cost 2 vext1 <u,0,1,1>, LHS
- 2556191459U, // <0,1,1,1>: Cost 3 vext1 <1,0,1,1>, <1,0,1,1>
- 2960310374U, // <0,1,1,2>: Cost 3 vzipr <1,2,3,0>, LHS
- 3020734474U, // <0,1,1,3>: Cost 3 vtrnl LHS, <0,0,1,1>
- 1524256054U, // <0,1,1,4>: Cost 2 vext1 <u,0,1,1>, RHS
- 2580082247U, // <0,1,1,5>: Cost 3 vext1 <5,0,1,1>, <5,0,1,1>
- 2597999098U, // <0,1,1,6>: Cost 3 vext1 <u,0,1,1>, <6,2,7,3>
- 2597999610U, // <0,1,1,7>: Cost 3 vext1 <u,0,1,1>, <7,0,1,2>
- 1524258514U, // <0,1,1,u>: Cost 2 vext1 <u,0,1,1>, <u,0,1,1>
+ 1476476938U, // <0,1,1,0>: Cost 2 vext1 <0,0,1,1>, <0,0,1,1>
+ 2886517556U, // <0,1,1,1>: Cost 3 vzipl LHS, <1,1,1,1>
+ 2886517654U, // <0,1,1,2>: Cost 3 vzipl LHS, <1,2,3,0>
+ 2886517720U, // <0,1,1,3>: Cost 3 vzipl LHS, <1,3,1,3>
+ 1476480310U, // <0,1,1,4>: Cost 2 vext1 <0,0,1,1>, RHS
+ 2886558864U, // <0,1,1,5>: Cost 3 vzipl LHS, <1,5,3,7>
+ 2550223354U, // <0,1,1,6>: Cost 3 vext1 <0,0,1,1>, <6,2,7,3>
+ 2550223856U, // <0,1,1,7>: Cost 3 vext1 <0,0,1,1>, <7,0,0,1>
+ 1476482862U, // <0,1,1,u>: Cost 2 vext1 <0,0,1,1>, LHS
1494401126U, // <0,1,2,0>: Cost 2 vext1 <3,0,1,2>, LHS
- 2556199652U, // <0,1,2,1>: Cost 3 vext1 <1,0,1,2>, <1,0,1,2>
+ 3020735284U, // <0,1,2,1>: Cost 3 vtrnl LHS, <1,1,1,1>
2562172349U, // <0,1,2,2>: Cost 3 vext1 <2,0,1,2>, <2,0,1,2>
835584U, // <0,1,2,3>: Cost 0 copy LHS
1494404406U, // <0,1,2,4>: Cost 2 vext1 <3,0,1,2>, RHS
- 2568146640U, // <0,1,2,5>: Cost 3 vext1 <3,0,1,2>, <5,1,7,3>
- 2568147450U, // <0,1,2,6>: Cost 3 vext1 <3,0,1,2>, <6,2,7,3>
+ 3020735488U, // <0,1,2,5>: Cost 3 vtrnl LHS, <1,3,5,7>
+ 2631190458U, // <0,1,2,6>: Cost 3 vext2 <2,3,0,1>, <2,6,3,7>
1518294010U, // <0,1,2,7>: Cost 2 vext1 <7,0,1,2>, <7,0,1,2>
835584U, // <0,1,2,u>: Cost 0 copy LHS
- 2631190676U, // <0,1,3,0>: Cost 3 vext2 <2,3,0,1>, <3,0,1,0>
- 3696969948U, // <0,1,3,1>: Cost 4 vext2 <1,0,0,1>, <3,1,0,0>
- 2631190856U, // <0,1,3,2>: Cost 3 vext2 <2,3,0,1>, <3,2,3,0>
+ 2692318156U, // <0,1,3,0>: Cost 3 vext3 <1,3,0,0>, <1,3,0,0>
+ 2691875800U, // <0,1,3,1>: Cost 3 vext3 <1,2,3,0>, <1,3,1,3>
+ 2691875806U, // <0,1,3,2>: Cost 3 vext3 <1,2,3,0>, <1,3,2,0>
2692539367U, // <0,1,3,3>: Cost 3 vext3 <1,3,3,0>, <1,3,3,0>
- 2631191042U, // <0,1,3,4>: Cost 3 vext2 <2,3,0,1>, <3,4,5,6>
- 3704932898U, // <0,1,3,5>: Cost 4 vext2 <2,3,0,1>, <3,5,0,2>
- 2657733296U, // <0,1,3,6>: Cost 3 vext2 <6,7,0,1>, <3,6,7,0>
+ 2562182454U, // <0,1,3,4>: Cost 3 vext1 <2,0,1,3>, RHS
+ 2691875840U, // <0,1,3,5>: Cost 3 vext3 <1,2,3,0>, <1,3,5,7>
+ 2692760578U, // <0,1,3,6>: Cost 3 vext3 <1,3,6,0>, <1,3,6,0>
2639817411U, // <0,1,3,7>: Cost 3 vext2 <3,7,0,1>, <3,7,0,1>
- 2692908052U, // <0,1,3,u>: Cost 3 vext3 <1,3,u,0>, <1,3,u,0>
- 2631191442U, // <0,1,4,0>: Cost 3 vext2 <2,3,0,1>, <4,0,5,1>
- 3704933322U, // <0,1,4,1>: Cost 4 vext2 <2,3,0,1>, <4,1,2,3>
+ 2691875863U, // <0,1,3,u>: Cost 3 vext3 <1,2,3,0>, <1,3,u,3>
+ 2568159334U, // <0,1,4,0>: Cost 3 vext1 <3,0,1,4>, LHS
+ 4095312692U, // <0,1,4,1>: Cost 4 vtrnl <0,2,4,6>, <1,1,1,1>
2568160934U, // <0,1,4,2>: Cost 3 vext1 <3,0,1,4>, <2,3,0,1>
2568161432U, // <0,1,4,3>: Cost 3 vext1 <3,0,1,4>, <3,0,1,4>
2568162614U, // <0,1,4,4>: Cost 3 vext1 <3,0,1,4>, RHS
1557450038U, // <0,1,4,5>: Cost 2 vext2 <2,3,0,1>, RHS
- 2631191884U, // <0,1,4,6>: Cost 3 vext2 <2,3,0,1>, <4,6,0,2>
+ 2754235702U, // <0,1,4,6>: Cost 3 vuzpl <0,4,1,5>, RHS
2592052220U, // <0,1,4,7>: Cost 3 vext1 <7,0,1,4>, <7,0,1,4>
1557450281U, // <0,1,4,u>: Cost 2 vext2 <2,3,0,1>, RHS
- 3704933959U, // <0,1,5,0>: Cost 4 vext2 <2,3,0,1>, <5,0,1,1>
- 2631192272U, // <0,1,5,1>: Cost 3 vext2 <2,3,0,1>, <5,1,7,3>
- 3696308006U, // <0,1,5,2>: Cost 4 vext2 <0,u,0,1>, <5,2,7,u>
- 2718712976U, // <0,1,5,3>: Cost 3 vext3 <5,6,7,0>, <1,5,3,7>
+ 3765617775U, // <0,1,5,0>: Cost 4 vext3 <1,2,3,0>, <1,5,0,1>
+ 2647781007U, // <0,1,5,1>: Cost 3 vext2 <5,1,0,1>, <5,1,0,1>
+ 3704934138U, // <0,1,5,2>: Cost 4 vext2 <2,3,0,1>, <5,2,3,0>
+ 2691875984U, // <0,1,5,3>: Cost 3 vext3 <1,2,3,0>, <1,5,3,7>
2657734598U, // <0,1,5,4>: Cost 3 vext2 <6,7,0,1>, <5,4,7,6>
- 2657734660U, // <0,1,5,5>: Cost 3 vext2 <6,7,0,1>, <5,5,5,5>
+ 2650435539U, // <0,1,5,5>: Cost 3 vext2 <5,5,0,1>, <5,5,0,1>
2651099172U, // <0,1,5,6>: Cost 3 vext2 <5,6,0,1>, <5,6,0,1>
- 3704934518U, // <0,1,5,7>: Cost 4 vext2 <2,3,0,1>, <5,7,0,2>
- 2631192839U, // <0,1,5,u>: Cost 3 vext2 <2,3,0,1>, <5,u,7,3>
+ 2651762805U, // <0,1,5,7>: Cost 3 vext2 <5,7,0,1>, <5,7,0,1>
+ 2691876029U, // <0,1,5,u>: Cost 3 vext3 <1,2,3,0>, <1,5,u,7>
2592063590U, // <0,1,6,0>: Cost 3 vext1 <7,0,1,6>, LHS
- 3704934780U, // <0,1,6,1>: Cost 4 vext2 <2,3,0,1>, <6,1,2,3>
- 2631193082U, // <0,1,6,2>: Cost 3 vext2 <2,3,0,1>, <6,2,7,3>
- 3704934984U, // <0,1,6,3>: Cost 4 vext2 <2,3,0,1>, <6,3,7,0>
+ 3765617871U, // <0,1,6,1>: Cost 4 vext3 <1,2,3,0>, <1,6,1,7>
+ 2654417337U, // <0,1,6,2>: Cost 3 vext2 <6,2,0,1>, <6,2,0,1>
+ 3765617889U, // <0,1,6,3>: Cost 4 vext3 <1,2,3,0>, <1,6,3,7>
2592066870U, // <0,1,6,4>: Cost 3 vext1 <7,0,1,6>, RHS
- 3721523947U, // <0,1,6,5>: Cost 4 vext2 <5,1,0,1>, <6,5,7,1>
- 2657735480U, // <0,1,6,6>: Cost 3 vext2 <6,7,0,1>, <6,6,6,6>
+ 3765617907U, // <0,1,6,5>: Cost 4 vext3 <1,2,3,0>, <1,6,5,7>
+ 2657071869U, // <0,1,6,6>: Cost 3 vext2 <6,6,0,1>, <6,6,0,1>
1583993678U, // <0,1,6,7>: Cost 2 vext2 <6,7,0,1>, <6,7,0,1>
1584657311U, // <0,1,6,u>: Cost 2 vext2 <6,u,0,1>, <6,u,0,1>
2657735672U, // <0,1,7,0>: Cost 3 vext2 <6,7,0,1>, <7,0,1,0>
- 3731477571U, // <0,1,7,1>: Cost 4 vext2 <6,7,0,1>, <7,1,0,3>
+ 2657735808U, // <0,1,7,1>: Cost 3 vext2 <6,7,0,1>, <7,1,7,1>
2631193772U, // <0,1,7,2>: Cost 3 vext2 <2,3,0,1>, <7,2,3,0>
2661053667U, // <0,1,7,3>: Cost 3 vext2 <7,3,0,1>, <7,3,0,1>
2657736038U, // <0,1,7,4>: Cost 3 vext2 <6,7,0,1>, <7,4,5,6>
@@ -176,403 +176,403 @@ static const unsigned PerfectShuffleTable[6561+1] = {
2657736322U, // <0,1,7,u>: Cost 3 vext2 <6,7,0,1>, <7,u,1,2>
1494450278U, // <0,1,u,0>: Cost 2 vext1 <3,0,1,u>, LHS
1557452590U, // <0,1,u,1>: Cost 2 vext2 <2,3,0,1>, LHS
- 2960310941U, // <0,1,u,2>: Cost 3 vzipr <1,2,3,0>, LHS
+ 2754238254U, // <0,1,u,2>: Cost 3 vuzpl <0,4,1,5>, LHS
835584U, // <0,1,u,3>: Cost 0 copy LHS
1494453558U, // <0,1,u,4>: Cost 2 vext1 <3,0,1,u>, RHS
1557452954U, // <0,1,u,5>: Cost 2 vext2 <2,3,0,1>, RHS
- 2631194800U, // <0,1,u,6>: Cost 3 vext2 <2,3,0,1>, <u,6,0,2>
+ 2754238618U, // <0,1,u,6>: Cost 3 vuzpl <0,4,1,5>, RHS
1518343168U, // <0,1,u,7>: Cost 2 vext1 <7,0,1,u>, <7,0,1,u>
835584U, // <0,1,u,u>: Cost 0 copy LHS
- 2618589184U, // <0,2,0,0>: Cost 3 vext2 <0,2,0,2>, <0,0,0,0>
+ 2752299008U, // <0,2,0,0>: Cost 3 vuzpl LHS, <0,0,0,0>
1544847462U, // <0,2,0,1>: Cost 2 vext2 <0,2,0,2>, LHS
- 1745666150U, // <0,2,0,2>: Cost 2 vuzpr LHS, LHS
- 2886516736U, // <0,2,0,3>: Cost 3 vzipl LHS, <0,0,0,0>
- 2562231606U, // <0,2,0,4>: Cost 3 vext1 <2,0,2,0>, RHS
- 3635973840U, // <0,2,0,5>: Cost 4 vext1 <2,0,2,0>, <5,1,7,3>
- 2586120488U, // <0,2,0,6>: Cost 3 vext1 <6,0,2,0>, <6,0,2,0>
+ 1678557286U, // <0,2,0,2>: Cost 2 vuzpl LHS, LHS
+ 2696521165U, // <0,2,0,3>: Cost 3 vext3 <2,0,3,0>, <2,0,3,0>
+ 2752340172U, // <0,2,0,4>: Cost 3 vuzpl LHS, <0,2,4,6>
+ 2691876326U, // <0,2,0,5>: Cost 3 vext3 <1,2,3,0>, <2,0,5,7>
+ 2618589695U, // <0,2,0,6>: Cost 3 vext2 <0,2,0,2>, <0,6,2,7>
2592093185U, // <0,2,0,7>: Cost 3 vext1 <7,0,2,0>, <7,0,2,0>
- 1746108518U, // <0,2,0,u>: Cost 2 vuzpr LHS, LHS
+ 1678557340U, // <0,2,0,u>: Cost 2 vuzpl LHS, LHS
2618589942U, // <0,2,1,0>: Cost 3 vext2 <0,2,0,2>, <1,0,3,2>
- 2618590004U, // <0,2,1,1>: Cost 3 vext2 <0,2,0,2>, <1,1,1,1>
- 2618590102U, // <0,2,1,2>: Cost 3 vext2 <0,2,0,2>, <1,2,3,0>
- 2886518438U, // <0,2,1,3>: Cost 3 vzipl LHS, <2,3,0,1>
- 2556267830U, // <0,2,1,4>: Cost 3 vext1 <1,0,2,1>, RHS
- 2645132432U, // <0,2,1,5>: Cost 3 vext2 <4,6,0,2>, <1,5,3,7>
- 2586128681U, // <0,2,1,6>: Cost 3 vext1 <6,0,2,1>, <6,0,2,1>
- 3725509931U, // <0,2,1,7>: Cost 4 vext2 <5,7,0,2>, <1,7,3,0>
- 2886559398U, // <0,2,1,u>: Cost 3 vzipl LHS, <2,3,0,1>
- 1524334694U, // <0,2,2,0>: Cost 2 vext1 <u,0,2,2>, LHS
- 2618590744U, // <0,2,2,1>: Cost 3 vext2 <0,2,0,2>, <2,1,2,3>
- 2618590824U, // <0,2,2,2>: Cost 3 vext2 <0,2,0,2>, <2,2,2,2>
- 2886516900U, // <0,2,2,3>: Cost 3 vzipl LHS, <0,2,0,2>
- 1524337974U, // <0,2,2,4>: Cost 2 vext1 <u,0,2,2>, RHS
- 2598080208U, // <0,2,2,5>: Cost 3 vext1 <u,0,2,2>, <5,1,7,3>
- 2645133242U, // <0,2,2,6>: Cost 3 vext2 <4,6,0,2>, <2,6,3,7>
- 2598081530U, // <0,2,2,7>: Cost 3 vext1 <u,0,2,2>, <7,0,1,2>
- 1524340444U, // <0,2,2,u>: Cost 2 vext1 <u,0,2,2>, <u,0,2,2>
+ 2752299828U, // <0,2,1,1>: Cost 3 vuzpl LHS, <1,1,1,1>
+ 2886518376U, // <0,2,1,2>: Cost 3 vzipl LHS, <2,2,2,2>
+ 2752299766U, // <0,2,1,3>: Cost 3 vuzpl LHS, <1,0,3,2>
+ 2550295862U, // <0,2,1,4>: Cost 3 vext1 <0,0,2,1>, RHS
+ 2752340992U, // <0,2,1,5>: Cost 3 vuzpl LHS, <1,3,5,7>
+ 2886559674U, // <0,2,1,6>: Cost 3 vzipl LHS, <2,6,3,7>
+ 3934208106U, // <0,2,1,7>: Cost 4 vuzpr <7,0,1,2>, <0,1,2,7>
+ 2752340771U, // <0,2,1,u>: Cost 3 vuzpl LHS, <1,0,u,2>
+ 1476558868U, // <0,2,2,0>: Cost 2 vext1 <0,0,2,2>, <0,0,2,2>
+ 2226628029U, // <0,2,2,1>: Cost 3 vrev <2,0,1,2>
+ 2752300648U, // <0,2,2,2>: Cost 3 vuzpl LHS, <2,2,2,2>
+ 3020736114U, // <0,2,2,3>: Cost 3 vtrnl LHS, <2,2,3,3>
+ 1476562230U, // <0,2,2,4>: Cost 2 vext1 <0,0,2,2>, RHS
+ 2550304464U, // <0,2,2,5>: Cost 3 vext1 <0,0,2,2>, <5,1,7,3>
+ 2618591162U, // <0,2,2,6>: Cost 3 vext2 <0,2,0,2>, <2,6,3,7>
+ 2550305777U, // <0,2,2,7>: Cost 3 vext1 <0,0,2,2>, <7,0,0,2>
+ 1476564782U, // <0,2,2,u>: Cost 2 vext1 <0,0,2,2>, LHS
2618591382U, // <0,2,3,0>: Cost 3 vext2 <0,2,0,2>, <3,0,1,2>
- 2691876528U, // <0,2,3,1>: Cost 3 vext3 <1,2,3,0>, <2,3,1,2>
- 3692333360U, // <0,2,3,2>: Cost 4 vext2 <0,2,0,2>, <3,2,0,3>
- 2618591644U, // <0,2,3,3>: Cost 3 vext2 <0,2,0,2>, <3,3,3,3>
+ 2752301206U, // <0,2,3,1>: Cost 3 vuzpl LHS, <3,0,1,2>
+ 3826043121U, // <0,2,3,2>: Cost 4 vuzpl LHS, <3,1,2,3>
+ 2752301468U, // <0,2,3,3>: Cost 3 vuzpl LHS, <3,3,3,3>
2618591746U, // <0,2,3,4>: Cost 3 vext2 <0,2,0,2>, <3,4,5,6>
- 2839560294U, // <0,2,3,5>: Cost 3 vuzpr <3,4,5,6>, LHS
- 3692333706U, // <0,2,3,6>: Cost 4 vext2 <0,2,0,2>, <3,6,2,7>
+ 2752301570U, // <0,2,3,5>: Cost 3 vuzpl LHS, <3,4,5,6>
+ 3830688102U, // <0,2,3,6>: Cost 4 vuzpl LHS, <3,2,6,3>
2698807012U, // <0,2,3,7>: Cost 3 vext3 <2,3,7,0>, <2,3,7,0>
- 2618592030U, // <0,2,3,u>: Cost 3 vext2 <0,2,0,2>, <3,u,1,2>
- 2618592146U, // <0,2,4,0>: Cost 3 vext2 <0,2,0,2>, <4,0,5,1>
- 3692334062U, // <0,2,4,1>: Cost 4 vext2 <0,2,0,2>, <4,1,6,3>
+ 2752301269U, // <0,2,3,u>: Cost 3 vuzpl LHS, <3,0,u,2>
+ 2562261094U, // <0,2,4,0>: Cost 3 vext1 <2,0,2,4>, LHS
+ 4095313828U, // <0,2,4,1>: Cost 4 vtrnl <0,2,4,6>, <2,6,1,3>
2226718152U, // <0,2,4,2>: Cost 3 vrev <2,0,2,4>
2568235169U, // <0,2,4,3>: Cost 3 vext1 <3,0,2,4>, <3,0,2,4>
2562264374U, // <0,2,4,4>: Cost 3 vext1 <2,0,2,4>, RHS
1544850742U, // <0,2,4,5>: Cost 2 vext2 <0,2,0,2>, RHS
- 1772535910U, // <0,2,4,6>: Cost 2 vuzpr RHS, LHS
+ 1678560566U, // <0,2,4,6>: Cost 2 vuzpl LHS, RHS
2592125957U, // <0,2,4,7>: Cost 3 vext1 <7,0,2,4>, <7,0,2,4>
- 1544850985U, // <0,2,4,u>: Cost 2 vext2 <0,2,0,2>, RHS
+ 1678560584U, // <0,2,4,u>: Cost 2 vuzpl LHS, RHS
2691876686U, // <0,2,5,0>: Cost 3 vext3 <1,2,3,0>, <2,5,0,7>
2618592976U, // <0,2,5,1>: Cost 3 vext2 <0,2,0,2>, <5,1,7,3>
- 2618593056U, // <0,2,5,2>: Cost 3 vext2 <0,2,0,2>, <5,2,7,2>
- 3964905940U, // <0,2,5,3>: Cost 4 vzipl LHS, <3,4,0,5>
- 2645135302U, // <0,2,5,4>: Cost 3 vext2 <4,6,0,2>, <5,4,7,6>
- 2645135364U, // <0,2,5,5>: Cost 3 vext2 <4,6,0,2>, <5,5,5,5>
- 2645135458U, // <0,2,5,6>: Cost 3 vext2 <4,6,0,2>, <5,6,7,0>
- 2849636454U, // <0,2,5,7>: Cost 3 vuzpr <5,1,7,3>, LHS
- 2645135620U, // <0,2,5,u>: Cost 3 vext2 <4,6,0,2>, <5,u,7,0>
- 2645135656U, // <0,2,6,0>: Cost 3 vext2 <4,6,0,2>, <6,0,2,0>
- 2645135740U, // <0,2,6,1>: Cost 3 vext2 <4,6,0,2>, <6,1,2,3>
+ 3765618528U, // <0,2,5,2>: Cost 4 vext3 <1,2,3,0>, <2,5,2,7>
+ 3765618536U, // <0,2,5,3>: Cost 4 vext3 <1,2,3,0>, <2,5,3,6>
+ 2618593222U, // <0,2,5,4>: Cost 3 vext2 <0,2,0,2>, <5,4,7,6>
+ 2752303108U, // <0,2,5,5>: Cost 3 vuzpl LHS, <5,5,5,5>
+ 2618593378U, // <0,2,5,6>: Cost 3 vext2 <0,2,0,2>, <5,6,7,0>
+ 2824785206U, // <0,2,5,7>: Cost 3 vuzpr <1,0,3,2>, RHS
+ 2824785207U, // <0,2,5,u>: Cost 3 vuzpr <1,0,3,2>, RHS
+ 2752303950U, // <0,2,6,0>: Cost 3 vuzpl LHS, <6,7,0,1>
+ 3830690081U, // <0,2,6,1>: Cost 4 vuzpl LHS, <6,0,1,2>
2618593786U, // <0,2,6,2>: Cost 3 vext2 <0,2,0,2>, <6,2,7,3>
- 2718713786U, // <0,2,6,3>: Cost 3 vext3 <5,6,7,0>, <2,6,3,7>
- 2645135980U, // <0,2,6,4>: Cost 3 vext2 <4,6,0,2>, <6,4,2,0>
- 2645136068U, // <0,2,6,5>: Cost 3 vext2 <4,6,0,2>, <6,5,2,7>
- 2645136184U, // <0,2,6,6>: Cost 3 vext2 <4,6,0,2>, <6,6,6,6>
- 2645136206U, // <0,2,6,7>: Cost 3 vext2 <4,6,0,2>, <6,7,0,1>
- 2618594272U, // <0,2,6,u>: Cost 3 vext2 <0,2,0,2>, <6,u,7,3>
- 2645136378U, // <0,2,7,0>: Cost 3 vext2 <4,6,0,2>, <7,0,1,2>
- 2860466278U, // <0,2,7,1>: Cost 3 vuzpr <7,0,1,2>, LHS
- 3692336303U, // <0,2,7,2>: Cost 4 vext2 <0,2,0,2>, <7,2,3,3>
+ 2691876794U, // <0,2,6,3>: Cost 3 vext3 <1,2,3,0>, <2,6,3,7>
+ 2752303990U, // <0,2,6,4>: Cost 3 vuzpl LHS, <6,7,4,5>
+ 3830690445U, // <0,2,6,5>: Cost 4 vuzpl LHS, <6,4,5,6>
+ 2752303928U, // <0,2,6,6>: Cost 3 vuzpl LHS, <6,6,6,6>
+ 2657743695U, // <0,2,6,7>: Cost 3 vext2 <6,7,0,2>, <6,7,0,2>
+ 2691876839U, // <0,2,6,u>: Cost 3 vext3 <1,2,3,0>, <2,6,u,7>
+ 2659070961U, // <0,2,7,0>: Cost 3 vext2 <7,0,0,2>, <7,0,0,2>
+ 2659734594U, // <0,2,7,1>: Cost 3 vext2 <7,1,0,2>, <7,1,0,2>
+ 3734140051U, // <0,2,7,2>: Cost 4 vext2 <7,2,0,2>, <7,2,0,2>
2701166596U, // <0,2,7,3>: Cost 3 vext3 <2,7,3,0>, <2,7,3,0>
- 2645136742U, // <0,2,7,4>: Cost 3 vext2 <4,6,0,2>, <7,4,5,6>
- 2863448166U, // <0,2,7,5>: Cost 3 vuzpr <7,4,5,6>, LHS
- 3718878688U, // <0,2,7,6>: Cost 4 vext2 <4,6,0,2>, <7,6,1,2>
- 2645137004U, // <0,2,7,7>: Cost 3 vext2 <4,6,0,2>, <7,7,7,7>
- 2645137026U, // <0,2,7,u>: Cost 3 vext2 <4,6,0,2>, <7,u,1,2>
- 1524383846U, // <0,2,u,0>: Cost 2 vext1 <u,0,2,u>, LHS
+ 2662389094U, // <0,2,7,4>: Cost 3 vext2 <7,5,0,2>, <7,4,5,6>
+ 2662389126U, // <0,2,7,5>: Cost 3 vext2 <7,5,0,2>, <7,5,0,2>
+ 3736794583U, // <0,2,7,6>: Cost 4 vext2 <7,6,0,2>, <7,6,0,2>
+ 2752304748U, // <0,2,7,7>: Cost 3 vuzpl LHS, <7,7,7,7>
+ 2659070961U, // <0,2,7,u>: Cost 3 vext2 <7,0,0,2>, <7,0,0,2>
+ 1476608026U, // <0,2,u,0>: Cost 2 vext1 <0,0,2,u>, <0,0,2,u>
1544853294U, // <0,2,u,1>: Cost 2 vext2 <0,2,0,2>, LHS
- 1793441894U, // <0,2,u,2>: Cost 2 vuzpr LHS, LHS
- 2886518445U, // <0,2,u,3>: Cost 3 vzipl LHS, <2,3,0,u>
- 1524387126U, // <0,2,u,4>: Cost 2 vext1 <u,0,2,u>, RHS
+ 1678563118U, // <0,2,u,2>: Cost 2 vuzpl LHS, LHS
+ 3021178482U, // <0,2,u,3>: Cost 3 vtrnl LHS, <2,2,3,3>
+ 1476611382U, // <0,2,u,4>: Cost 2 vext1 <0,0,2,u>, RHS
1544853658U, // <0,2,u,5>: Cost 2 vext2 <0,2,0,2>, RHS
- 1796423782U, // <0,2,u,6>: Cost 2 vuzpr RHS, LHS
- 2645137664U, // <0,2,u,7>: Cost 3 vext2 <4,6,0,2>, <u,7,0,1>
- 1544853861U, // <0,2,u,u>: Cost 2 vext2 <0,2,0,2>, LHS
- 2618597376U, // <0,3,0,0>: Cost 3 vext2 <0,2,0,3>, <0,0,0,0>
- 2618597478U, // <0,3,0,1>: Cost 3 vext2 <0,2,0,3>, LHS
- 2618597541U, // <0,3,0,2>: Cost 3 vext2 <0,2,0,3>, <0,2,0,3>
- 3692339443U, // <0,3,0,3>: Cost 4 vext2 <0,2,0,3>, <0,3,0,0>
- 2691877044U, // <0,3,0,4>: Cost 3 vext3 <1,2,3,0>, <3,0,4,5>
- 3765618873U, // <0,3,0,5>: Cost 4 vext3 <1,2,3,0>, <3,0,5,1>
- 3765618883U, // <0,3,0,6>: Cost 4 vext3 <1,2,3,0>, <3,0,6,2>
- 3665908746U, // <0,3,0,7>: Cost 4 vext1 <7,0,3,0>, <7,0,3,0>
- 2618598045U, // <0,3,0,u>: Cost 3 vext2 <0,2,0,3>, LHS
- 2562310246U, // <0,3,1,0>: Cost 3 vext1 <2,0,3,1>, LHS
- 3692340020U, // <0,3,1,1>: Cost 4 vext2 <0,2,0,3>, <1,1,1,1>
+ 1678563482U, // <0,2,u,6>: Cost 2 vuzpl LHS, RHS
+ 2824785449U, // <0,2,u,7>: Cost 3 vuzpr <1,0,3,2>, RHS
+ 1678563172U, // <0,2,u,u>: Cost 2 vuzpl LHS, LHS
+ 2556329984U, // <0,3,0,0>: Cost 3 vext1 <1,0,3,0>, <0,0,0,0>
+ 2686421142U, // <0,3,0,1>: Cost 3 vext3 <0,3,1,0>, <3,0,1,2>
+ 2562303437U, // <0,3,0,2>: Cost 3 vext1 <2,0,3,0>, <2,0,3,0>
+ 4094986652U, // <0,3,0,3>: Cost 4 vtrnl <0,2,0,2>, <3,3,3,3>
+ 2556333366U, // <0,3,0,4>: Cost 3 vext1 <1,0,3,0>, RHS
+ 4094986754U, // <0,3,0,5>: Cost 4 vtrnl <0,2,0,2>, <3,4,5,6>
+ 3798796488U, // <0,3,0,6>: Cost 4 vext3 <6,7,3,0>, <3,0,6,7>
+ 3776530634U, // <0,3,0,7>: Cost 4 vext3 <3,0,7,0>, <3,0,7,0>
+ 2556335918U, // <0,3,0,u>: Cost 3 vext1 <1,0,3,0>, LHS
+ 2886518934U, // <0,3,1,0>: Cost 3 vzipl LHS, <3,0,1,2>
+ 2556338933U, // <0,3,1,1>: Cost 3 vext1 <1,0,3,1>, <1,0,3,1>
2691877105U, // <0,3,1,2>: Cost 3 vext3 <1,2,3,0>, <3,1,2,3>
- 2568284327U, // <0,3,1,3>: Cost 3 vext1 <3,0,3,1>, <3,0,3,1>
- 2562313526U, // <0,3,1,4>: Cost 3 vext1 <2,0,3,1>, RHS
- 3765618956U, // <0,3,1,5>: Cost 4 vext3 <1,2,3,0>, <3,1,5,3>
- 3636056570U, // <0,3,1,6>: Cost 4 vext1 <2,0,3,1>, <6,2,7,3>
- 3665916939U, // <0,3,1,7>: Cost 4 vext1 <7,0,3,1>, <7,0,3,1>
- 2695858471U, // <0,3,1,u>: Cost 3 vext3 <1,u,3,0>, <3,1,u,3>
+ 2886519196U, // <0,3,1,3>: Cost 3 vzipl LHS, <3,3,3,3>
+ 2886519298U, // <0,3,1,4>: Cost 3 vzipl LHS, <3,4,5,6>
+ 4095740418U, // <0,3,1,5>: Cost 4 vtrnl <0,3,1,4>, <3,4,5,6>
+ 3659944242U, // <0,3,1,6>: Cost 4 vext1 <6,0,3,1>, <6,0,3,1>
+ 3769600286U, // <0,3,1,7>: Cost 4 vext3 <1,u,3,0>, <3,1,7,3>
+ 2886519582U, // <0,3,1,u>: Cost 3 vzipl LHS, <3,u,1,2>
1482604646U, // <0,3,2,0>: Cost 2 vext1 <1,0,3,2>, LHS
1482605302U, // <0,3,2,1>: Cost 2 vext1 <1,0,3,2>, <1,0,3,2>
2556348008U, // <0,3,2,2>: Cost 3 vext1 <1,0,3,2>, <2,2,2,2>
- 2556348566U, // <0,3,2,3>: Cost 3 vext1 <1,0,3,2>, <3,0,1,2>
+ 3020736924U, // <0,3,2,3>: Cost 3 vtrnl LHS, <3,3,3,3>
1482607926U, // <0,3,2,4>: Cost 2 vext1 <1,0,3,2>, RHS
- 2556350160U, // <0,3,2,5>: Cost 3 vext1 <1,0,3,2>, <5,1,7,3>
- 2556350970U, // <0,3,2,6>: Cost 3 vext1 <1,0,3,2>, <6,2,7,3>
+ 3020737026U, // <0,3,2,5>: Cost 3 vtrnl LHS, <3,4,5,6>
+ 2598154746U, // <0,3,2,6>: Cost 3 vext1 <u,0,3,2>, <6,2,7,3>
2598155258U, // <0,3,2,7>: Cost 3 vext1 <u,0,3,2>, <7,0,1,2>
1482610478U, // <0,3,2,u>: Cost 2 vext1 <1,0,3,2>, LHS
- 3692341387U, // <0,3,3,0>: Cost 4 vext2 <0,2,0,3>, <3,0,0,0>
+ 3692341398U, // <0,3,3,0>: Cost 4 vext2 <0,2,0,3>, <3,0,1,2>
2635851999U, // <0,3,3,1>: Cost 3 vext2 <3,1,0,3>, <3,1,0,3>
- 2636515632U, // <0,3,3,2>: Cost 3 vext2 <3,2,0,3>, <3,2,0,3>
+ 3636069840U, // <0,3,3,2>: Cost 4 vext1 <2,0,3,3>, <2,0,3,3>
2691877276U, // <0,3,3,3>: Cost 3 vext3 <1,2,3,0>, <3,3,3,3>
- 3692341762U, // <0,3,3,4>: Cost 4 vext2 <0,2,0,3>, <3,4,5,6>
- 3778374059U, // <0,3,3,5>: Cost 4 vext3 <3,3,5,0>, <3,3,5,0>
- 3692341898U, // <0,3,3,6>: Cost 5 vext2 <0,2,0,3>, <3,6,2,7>
- 3665933325U, // <0,3,3,7>: Cost 4 vext1 <7,0,3,3>, <7,0,3,3>
+ 3961522690U, // <0,3,3,4>: Cost 4 vzipl <0,3,1,4>, <3,4,5,6>
+ 3826797058U, // <0,3,3,5>: Cost 4 vuzpl <0,2,3,5>, <3,4,5,6>
+ 3703622282U, // <0,3,3,6>: Cost 4 vext2 <2,1,0,3>, <3,6,2,7>
+ 3769600452U, // <0,3,3,7>: Cost 4 vext3 <1,u,3,0>, <3,3,7,7>
2640497430U, // <0,3,3,u>: Cost 3 vext2 <3,u,0,3>, <3,u,0,3>
- 3692342162U, // <0,3,4,0>: Cost 4 vext2 <0,2,0,3>, <4,0,5,1>
+ 3962194070U, // <0,3,4,0>: Cost 4 vzipl <0,4,1,5>, <3,0,1,2>
2232617112U, // <0,3,4,1>: Cost 3 vrev <3,0,1,4>
2232690849U, // <0,3,4,2>: Cost 3 vrev <3,0,2,4>
- 3306506410U, // <0,3,4,3>: Cost 4 vrev <3,0,3,4>
- 3765987832U, // <0,3,4,4>: Cost 4 vext3 <1,2,u,0>, <3,4,4,5>
- 2618600758U, // <0,3,4,5>: Cost 3 vext2 <0,2,0,3>, RHS
- 2705369605U, // <0,3,4,6>: Cost 3 vext3 <3,4,6,0>, <3,4,6,0>
+ 4095314332U, // <0,3,4,3>: Cost 4 vtrnl <0,2,4,6>, <3,3,3,3>
+ 3962194434U, // <0,3,4,4>: Cost 4 vzipl <0,4,1,5>, <3,4,5,6>
+ 2691877378U, // <0,3,4,5>: Cost 3 vext3 <1,2,3,0>, <3,4,5,6>
+ 3826765110U, // <0,3,4,6>: Cost 4 vuzpl <0,2,3,1>, RHS
3665941518U, // <0,3,4,7>: Cost 4 vext1 <7,0,3,4>, <7,0,3,4>
- 2618601001U, // <0,3,4,u>: Cost 3 vext2 <0,2,0,3>, RHS
- 3765619234U, // <0,3,5,0>: Cost 4 vext3 <1,2,3,0>, <3,5,0,2>
- 3692342992U, // <0,3,5,1>: Cost 4 vext2 <0,2,0,3>, <5,1,7,3>
- 3708268318U, // <0,3,5,2>: Cost 4 vext2 <2,u,0,3>, <5,2,7,0>
- 3648031234U, // <0,3,5,3>: Cost 4 vext1 <4,0,3,5>, <3,4,5,6>
+ 2691877405U, // <0,3,4,u>: Cost 3 vext3 <1,2,3,0>, <3,4,u,6>
+ 3630112870U, // <0,3,5,0>: Cost 4 vext1 <1,0,3,5>, LHS
+ 3630113526U, // <0,3,5,1>: Cost 4 vext1 <1,0,3,5>, <1,0,3,2>
+ 4035199734U, // <0,3,5,2>: Cost 4 vzipr <1,4,0,5>, <1,0,3,2>
+ 3769600578U, // <0,3,5,3>: Cost 4 vext3 <1,u,3,0>, <3,5,3,7>
2232846516U, // <0,3,5,4>: Cost 3 vrev <3,0,4,5>
- 3779701325U, // <0,3,5,5>: Cost 4 vext3 <3,5,5,0>, <3,5,5,0>
+ 3779037780U, // <0,3,5,5>: Cost 4 vext3 <3,4,5,0>, <3,5,5,7>
2718714461U, // <0,3,5,6>: Cost 3 vext3 <5,6,7,0>, <3,5,6,7>
- 3779848799U, // <0,3,5,7>: Cost 4 vext3 <3,5,7,0>, <3,5,7,0>
+ 2706106975U, // <0,3,5,7>: Cost 3 vext3 <3,5,7,0>, <3,5,7,0>
2233141464U, // <0,3,5,u>: Cost 3 vrev <3,0,u,5>
- 3648036966U, // <0,3,6,0>: Cost 4 vext1 <4,0,3,6>, LHS
- 3306375322U, // <0,3,6,1>: Cost 4 vrev <3,0,1,6>
- 3692343802U, // <0,3,6,2>: Cost 4 vext2 <0,2,0,3>, <6,2,7,3>
- 3703624266U, // <0,3,6,3>: Cost 4 vext2 <2,1,0,3>, <6,3,7,2>
- 3306596533U, // <0,3,6,4>: Cost 4 vrev <3,0,4,6>
+ 2691877496U, // <0,3,6,0>: Cost 3 vext3 <1,2,3,0>, <3,6,0,7>
+ 3727511914U, // <0,3,6,1>: Cost 4 vext2 <6,1,0,3>, <6,1,0,3>
+ 3765619338U, // <0,3,6,2>: Cost 4 vext3 <1,2,3,0>, <3,6,2,7>
+ 3765619347U, // <0,3,6,3>: Cost 4 vext3 <1,2,3,0>, <3,6,3,7>
+ 3765987996U, // <0,3,6,4>: Cost 4 vext3 <1,2,u,0>, <3,6,4,7>
3306670270U, // <0,3,6,5>: Cost 4 vrev <3,0,5,6>
- 3733484344U, // <0,3,6,6>: Cost 4 vext2 <7,1,0,3>, <6,6,6,6>
+ 3792456365U, // <0,3,6,6>: Cost 4 vext3 <5,6,7,0>, <3,6,6,6>
2706770608U, // <0,3,6,7>: Cost 3 vext3 <3,6,7,0>, <3,6,7,0>
2706844345U, // <0,3,6,u>: Cost 3 vext3 <3,6,u,0>, <3,6,u,0>
- 3796437698U, // <0,3,7,0>: Cost 4 vext3 <6,3,7,0>, <3,7,0,0>
+ 3769600707U, // <0,3,7,0>: Cost 4 vext3 <1,u,3,0>, <3,7,0,1>
2659742787U, // <0,3,7,1>: Cost 3 vext2 <7,1,0,3>, <7,1,0,3>
- 3734148244U, // <0,3,7,2>: Cost 4 vext2 <7,2,0,3>, <7,2,0,3>
- 3734811877U, // <0,3,7,3>: Cost 4 vext2 <7,3,0,3>, <7,3,0,3>
- 3733484902U, // <0,3,7,4>: Cost 4 vext2 <7,1,0,3>, <7,4,5,6>
- 3781028591U, // <0,3,7,5>: Cost 4 vext3 <3,7,5,0>, <3,7,5,0>
- 3736802776U, // <0,3,7,6>: Cost 4 vext2 <7,6,0,3>, <7,6,0,3>
- 3733485103U, // <0,3,7,7>: Cost 4 vext2 <7,1,0,3>, <7,7,1,0>
+ 3636102612U, // <0,3,7,2>: Cost 4 vext1 <2,0,3,7>, <2,0,3,7>
+ 3769600740U, // <0,3,7,3>: Cost 4 vext3 <1,u,3,0>, <3,7,3,7>
+ 3769600747U, // <0,3,7,4>: Cost 4 vext3 <1,u,3,0>, <3,7,4,5>
+ 3769600758U, // <0,3,7,5>: Cost 4 vext3 <1,u,3,0>, <3,7,5,7>
+ 3659993400U, // <0,3,7,6>: Cost 4 vext1 <6,0,3,7>, <6,0,3,7>
+ 3781176065U, // <0,3,7,7>: Cost 4 vext3 <3,7,7,0>, <3,7,7,0>
2664388218U, // <0,3,7,u>: Cost 3 vext2 <7,u,0,3>, <7,u,0,3>
1482653798U, // <0,3,u,0>: Cost 2 vext1 <1,0,3,u>, LHS
1482654460U, // <0,3,u,1>: Cost 2 vext1 <1,0,3,u>, <1,0,3,u>
2556397160U, // <0,3,u,2>: Cost 3 vext1 <1,0,3,u>, <2,2,2,2>
- 2556397718U, // <0,3,u,3>: Cost 3 vext1 <1,0,3,u>, <3,0,1,2>
+ 3021179292U, // <0,3,u,3>: Cost 3 vtrnl LHS, <3,3,3,3>
1482657078U, // <0,3,u,4>: Cost 2 vext1 <1,0,3,u>, RHS
- 2618603674U, // <0,3,u,5>: Cost 3 vext2 <0,2,0,3>, RHS
- 2556400122U, // <0,3,u,6>: Cost 3 vext1 <1,0,3,u>, <6,2,7,3>
- 2598204410U, // <0,3,u,7>: Cost 3 vext1 <u,0,3,u>, <7,0,1,2>
+ 3021179394U, // <0,3,u,5>: Cost 3 vtrnl LHS, <3,4,5,6>
+ 2598203898U, // <0,3,u,6>: Cost 3 vext1 <u,0,3,u>, <6,2,7,3>
+ 2708097874U, // <0,3,u,7>: Cost 3 vext3 <3,u,7,0>, <3,u,7,0>
1482659630U, // <0,3,u,u>: Cost 2 vext1 <1,0,3,u>, LHS
2617278468U, // <0,4,0,0>: Cost 3 vext2 <0,0,0,4>, <0,0,0,4>
- 2631213158U, // <0,4,0,1>: Cost 3 vext2 <2,3,0,4>, LHS
- 2819408076U, // <0,4,0,2>: Cost 3 vuzpr LHS, <0,2,4,6>
+ 2618605670U, // <0,4,0,1>: Cost 3 vext2 <0,2,0,4>, LHS
+ 2618605734U, // <0,4,0,2>: Cost 3 vext2 <0,2,0,4>, <0,2,0,4>
3642091695U, // <0,4,0,3>: Cost 4 vext1 <3,0,4,0>, <3,0,4,0>
- 2657755474U, // <0,4,0,4>: Cost 3 vext2 <6,7,0,4>, <0,4,1,5>
- 2691877778U, // <0,4,0,5>: Cost 3 vext3 <1,2,3,0>, <4,0,5,1>
- 2691877788U, // <0,4,0,6>: Cost 3 vext3 <1,2,3,0>, <4,0,6,2>
+ 2753134796U, // <0,4,0,4>: Cost 3 vuzpl <0,2,4,6>, <0,2,4,6>
+ 2718714770U, // <0,4,0,5>: Cost 3 vext3 <5,6,7,0>, <4,0,5,1>
+ 3021245750U, // <0,4,0,6>: Cost 3 vtrnl <0,2,0,2>, RHS
3665982483U, // <0,4,0,7>: Cost 4 vext1 <7,0,4,0>, <7,0,4,0>
- 2691877805U, // <0,4,0,u>: Cost 3 vext3 <1,2,3,0>, <4,0,u,1>
+ 3021245768U, // <0,4,0,u>: Cost 3 vtrnl <0,2,0,2>, RHS
2568355942U, // <0,4,1,0>: Cost 3 vext1 <3,0,4,1>, LHS
- 3704955700U, // <0,4,1,1>: Cost 4 vext2 <2,3,0,4>, <1,1,1,1>
- 2631213974U, // <0,4,1,2>: Cost 3 vext2 <2,3,0,4>, <1,2,3,0>
+ 3692348212U, // <0,4,1,1>: Cost 4 vext2 <0,2,0,4>, <1,1,1,1>
+ 3692348310U, // <0,4,1,2>: Cost 4 vext2 <0,2,0,4>, <1,2,3,0>
2568358064U, // <0,4,1,3>: Cost 3 vext1 <3,0,4,1>, <3,0,4,1>
2568359222U, // <0,4,1,4>: Cost 3 vext1 <3,0,4,1>, RHS
- 1906753638U, // <0,4,1,5>: Cost 2 vzipr RHS, LHS
- 3114713098U, // <0,4,1,6>: Cost 3 vtrnr RHS, <0,0,1,1>
+ 1812778294U, // <0,4,1,5>: Cost 2 vzipl LHS, RHS
+ 3022671158U, // <0,4,1,6>: Cost 3 vtrnl <0,4,1,5>, RHS
2592248852U, // <0,4,1,7>: Cost 3 vext1 <7,0,4,1>, <7,0,4,1>
- 1908744294U, // <0,4,1,u>: Cost 2 vzipr RHS, LHS
- 2562392166U, // <0,4,2,0>: Cost 3 vext1 <2,0,4,2>, LHS
+ 1812778537U, // <0,4,1,u>: Cost 2 vzipl LHS, RHS
+ 2568364134U, // <0,4,2,0>: Cost 3 vext1 <3,0,4,2>, LHS
2238573423U, // <0,4,2,1>: Cost 3 vrev <4,0,1,2>
- 2562393560U, // <0,4,2,2>: Cost 3 vext1 <2,0,4,2>, <2,0,4,2>
+ 3692349032U, // <0,4,2,2>: Cost 4 vext2 <0,2,0,4>, <2,2,2,2>
2631214761U, // <0,4,2,3>: Cost 3 vext2 <2,3,0,4>, <2,3,0,4>
- 2562395446U, // <0,4,2,4>: Cost 3 vext1 <2,0,4,2>, RHS
- 3111272550U, // <0,4,2,5>: Cost 3 vtrnr <4,0,5,1>, LHS
- 2040971366U, // <0,4,2,6>: Cost 2 vtrnr RHS, LHS
+ 2568367414U, // <0,4,2,4>: Cost 3 vext1 <3,0,4,2>, RHS
+ 2887028022U, // <0,4,2,5>: Cost 3 vzipl <0,2,0,2>, RHS
+ 1946996022U, // <0,4,2,6>: Cost 2 vtrnl LHS, RHS
2592257045U, // <0,4,2,7>: Cost 3 vext1 <7,0,4,2>, <7,0,4,2>
- 2041118822U, // <0,4,2,u>: Cost 2 vtrnr RHS, LHS
- 3704957078U, // <0,4,3,0>: Cost 4 vext2 <2,3,0,4>, <3,0,1,2>
- 3704957169U, // <0,4,3,1>: Cost 4 vext2 <2,3,0,4>, <3,1,2,3>
- 3704957232U, // <0,4,3,2>: Cost 4 vext2 <2,3,0,4>, <3,2,0,3>
- 3704957340U, // <0,4,3,3>: Cost 4 vext2 <2,3,0,4>, <3,3,3,3>
- 3704957442U, // <0,4,3,4>: Cost 4 vext2 <2,3,0,4>, <3,4,5,6>
- 3312618388U, // <0,4,3,5>: Cost 4 vrev <4,0,5,3>
- 3312692125U, // <0,4,3,6>: Cost 4 vrev <4,0,6,3>
+ 1946996040U, // <0,4,2,u>: Cost 2 vtrnl LHS, RHS
+ 3692349590U, // <0,4,3,0>: Cost 4 vext2 <0,2,0,4>, <3,0,1,2>
+ 3826878614U, // <0,4,3,1>: Cost 4 vuzpl <0,2,4,6>, <3,0,1,2>
+ 3826878625U, // <0,4,3,2>: Cost 4 vuzpl <0,2,4,6>, <3,0,2,4>
+ 3692349852U, // <0,4,3,3>: Cost 4 vext2 <0,2,0,4>, <3,3,3,3>
+ 3692349954U, // <0,4,3,4>: Cost 4 vext2 <0,2,0,4>, <3,4,5,6>
+ 3826878978U, // <0,4,3,5>: Cost 4 vuzpl <0,2,4,6>, <3,4,5,6>
+ 4095200566U, // <0,4,3,6>: Cost 4 vtrnl <0,2,3,1>, RHS
3713583814U, // <0,4,3,7>: Cost 4 vext2 <3,7,0,4>, <3,7,0,4>
- 3704957726U, // <0,4,3,u>: Cost 4 vext2 <2,3,0,4>, <3,u,1,2>
- 2710899880U, // <0,4,4,0>: Cost 3 vext3 <4,4,0,0>, <4,4,0,0>
- 3704957924U, // <0,4,4,1>: Cost 4 vext2 <2,3,0,4>, <4,1,5,2>
- 3642123945U, // <0,4,4,2>: Cost 4 vext1 <3,0,4,4>, <2,3,0,4>
+ 3692350238U, // <0,4,3,u>: Cost 4 vext2 <0,2,0,4>, <3,u,1,2>
+ 2550464552U, // <0,4,4,0>: Cost 3 vext1 <0,0,4,4>, <0,0,4,4>
+ 3962194914U, // <0,4,4,1>: Cost 4 vzipl <0,4,1,5>, <4,1,5,0>
+ 3693677631U, // <0,4,4,2>: Cost 4 vext2 <0,4,0,4>, <4,2,6,3>
3642124467U, // <0,4,4,3>: Cost 4 vext1 <3,0,4,4>, <3,0,4,4>
2718715088U, // <0,4,4,4>: Cost 3 vext3 <5,6,7,0>, <4,4,4,4>
- 2631216438U, // <0,4,4,5>: Cost 3 vext2 <2,3,0,4>, RHS
- 2846277836U, // <0,4,4,6>: Cost 3 vuzpr RHS, <0,2,4,6>
+ 2618608950U, // <0,4,4,5>: Cost 3 vext2 <0,2,0,4>, RHS
+ 2753137974U, // <0,4,4,6>: Cost 3 vuzpl <0,2,4,6>, RHS
3666015255U, // <0,4,4,7>: Cost 4 vext1 <7,0,4,4>, <7,0,4,4>
- 2631216681U, // <0,4,4,u>: Cost 3 vext2 <2,3,0,4>, RHS
+ 2618609193U, // <0,4,4,u>: Cost 3 vext2 <0,2,0,4>, RHS
2568388710U, // <0,4,5,0>: Cost 3 vext1 <3,0,4,5>, LHS
2568389526U, // <0,4,5,1>: Cost 3 vext1 <3,0,4,5>, <1,2,3,0>
3636159963U, // <0,4,5,2>: Cost 4 vext1 <2,0,4,5>, <2,0,4,5>
2568390836U, // <0,4,5,3>: Cost 3 vext1 <3,0,4,5>, <3,0,4,5>
2568391990U, // <0,4,5,4>: Cost 3 vext1 <3,0,4,5>, RHS
- 2592280674U, // <0,4,5,5>: Cost 3 vext1 <7,0,4,5>, <5,6,7,0>
+ 2718715180U, // <0,4,5,5>: Cost 3 vext3 <5,6,7,0>, <4,5,5,6>
1618136374U, // <0,4,5,6>: Cost 2 vext3 <1,2,3,0>, RHS
2592281624U, // <0,4,5,7>: Cost 3 vext1 <7,0,4,5>, <7,0,4,5>
1618136392U, // <0,4,5,u>: Cost 2 vext3 <1,2,3,0>, RHS
- 2691878220U, // <0,4,6,0>: Cost 3 vext3 <1,2,3,0>, <4,6,0,2>
- 3765620052U, // <0,4,6,1>: Cost 4 vext3 <1,2,3,0>, <4,6,1,1>
- 2712374620U, // <0,4,6,2>: Cost 3 vext3 <4,6,2,0>, <4,6,2,0>
- 3704959560U, // <0,4,6,3>: Cost 4 vext2 <2,3,0,4>, <6,3,7,0>
- 2712522094U, // <0,4,6,4>: Cost 3 vext3 <4,6,4,0>, <4,6,4,0>
- 4054237677U, // <0,4,6,5>: Cost 4 vzipr RHS, <0,6,0,7>
+ 2550480938U, // <0,4,6,0>: Cost 3 vext1 <0,0,4,6>, <0,0,4,6>
+ 3826880801U, // <0,4,6,1>: Cost 4 vuzpl <0,2,4,6>, <6,0,1,2>
+ 2562426332U, // <0,4,6,2>: Cost 3 vext1 <2,0,4,6>, <2,0,4,6>
+ 3786190181U, // <0,4,6,3>: Cost 4 vext3 <4,6,3,0>, <4,6,3,0>
+ 2718715252U, // <0,4,6,4>: Cost 3 vext3 <5,6,7,0>, <4,6,4,6>
+ 3826881165U, // <0,4,6,5>: Cost 4 vuzpl <0,2,4,6>, <6,4,5,6>
2712669568U, // <0,4,6,6>: Cost 3 vext3 <4,6,6,0>, <4,6,6,0>
2657760081U, // <0,4,6,7>: Cost 3 vext2 <6,7,0,4>, <6,7,0,4>
- 2712817042U, // <0,4,6,u>: Cost 3 vext3 <4,6,u,0>, <4,6,u,0>
- 3731502074U, // <0,4,7,0>: Cost 4 vext2 <6,7,0,4>, <7,0,1,2>
- 3934208204U, // <0,4,7,1>: Cost 4 vuzpr <7,0,1,2>, <0,2,4,6>
- 3934298316U, // <0,4,7,2>: Cost 4 vuzpr <7,0,2,4>, <0,2,4,6>
+ 2718715284U, // <0,4,6,u>: Cost 3 vext3 <5,6,7,0>, <4,6,u,2>
+ 3654090854U, // <0,4,7,0>: Cost 4 vext1 <5,0,4,7>, LHS
+ 3934229326U, // <0,4,7,1>: Cost 4 vuzpr <7,0,1,4>, <6,7,0,1>
+ 3734156437U, // <0,4,7,2>: Cost 4 vext2 <7,2,0,4>, <7,2,0,4>
3734820070U, // <0,4,7,3>: Cost 4 vext2 <7,3,0,4>, <7,3,0,4>
- 3731502438U, // <0,4,7,4>: Cost 4 vext2 <6,7,0,4>, <7,4,5,6>
- 3937190092U, // <0,4,7,5>: Cost 4 vuzpr <7,4,5,6>, <0,2,4,6>
+ 3654094134U, // <0,4,7,4>: Cost 4 vext1 <5,0,4,7>, RHS
+ 2713259464U, // <0,4,7,5>: Cost 3 vext3 <4,7,5,0>, <4,7,5,0>
2713333201U, // <0,4,7,6>: Cost 3 vext3 <4,7,6,0>, <4,7,6,0>
- 3731502700U, // <0,4,7,7>: Cost 4 vext2 <6,7,0,4>, <7,7,7,7>
- 2713480675U, // <0,4,7,u>: Cost 3 vext3 <4,7,u,0>, <4,7,u,0>
- 2691878382U, // <0,4,u,0>: Cost 3 vext3 <1,2,3,0>, <4,u,0,2>
- 2631218990U, // <0,4,u,1>: Cost 3 vext2 <2,3,0,4>, LHS
- 2562442718U, // <0,4,u,2>: Cost 3 vext1 <2,0,4,u>, <2,0,4,u>
+ 3654095866U, // <0,4,7,7>: Cost 4 vext1 <5,0,4,7>, <7,0,1,2>
+ 2713259464U, // <0,4,7,u>: Cost 3 vext3 <4,7,5,0>, <4,7,5,0>
+ 2568413286U, // <0,4,u,0>: Cost 3 vext1 <3,0,4,u>, LHS
+ 2618611502U, // <0,4,u,1>: Cost 3 vext2 <0,2,0,4>, LHS
+ 2753140526U, // <0,4,u,2>: Cost 3 vuzpl <0,2,4,6>, LHS
2568415415U, // <0,4,u,3>: Cost 3 vext1 <3,0,4,u>, <3,0,4,u>
- 2562444598U, // <0,4,u,4>: Cost 3 vext1 <2,0,4,u>, RHS
- 1906754205U, // <0,4,u,5>: Cost 2 vzipr RHS, LHS
- 1618136617U, // <0,4,u,6>: Cost 2 vext3 <1,2,3,0>, RHS
+ 2568416566U, // <0,4,u,4>: Cost 3 vext1 <3,0,4,u>, RHS
+ 1817423158U, // <0,4,u,5>: Cost 2 vzipl LHS, RHS
+ 1947438390U, // <0,4,u,6>: Cost 2 vtrnl LHS, RHS
2592306203U, // <0,4,u,7>: Cost 3 vext1 <7,0,4,u>, <7,0,4,u>
- 1618136635U, // <0,4,u,u>: Cost 2 vext3 <1,2,3,0>, RHS
- 3636191334U, // <0,5,0,0>: Cost 4 vext1 <2,0,5,0>, LHS
- 2637856870U, // <0,5,0,1>: Cost 3 vext2 <3,4,0,5>, LHS
- 3636192735U, // <0,5,0,2>: Cost 4 vext1 <2,0,5,0>, <2,0,5,0>
- 3642165432U, // <0,5,0,3>: Cost 4 vext1 <3,0,5,0>, <3,0,5,0>
- 3636194614U, // <0,5,0,4>: Cost 4 vext1 <2,0,5,0>, RHS
- 3711598998U, // <0,5,0,5>: Cost 4 vext2 <3,4,0,5>, <0,5,0,1>
+ 1947438408U, // <0,4,u,u>: Cost 2 vtrnl LHS, RHS
+ 3630219264U, // <0,5,0,0>: Cost 4 vext1 <1,0,5,0>, <0,0,0,0>
+ 2625912934U, // <0,5,0,1>: Cost 3 vext2 <1,4,0,5>, LHS
+ 3692355748U, // <0,5,0,2>: Cost 4 vext2 <0,2,0,5>, <0,2,0,2>
+ 3693019384U, // <0,5,0,3>: Cost 4 vext2 <0,3,0,5>, <0,3,0,5>
+ 3630222646U, // <0,5,0,4>: Cost 4 vext1 <1,0,5,0>, RHS
+ 3699655062U, // <0,5,0,5>: Cost 4 vext2 <1,4,0,5>, <0,5,0,1>
2718715508U, // <0,5,0,6>: Cost 3 vext3 <5,6,7,0>, <5,0,6,1>
- 3047604224U, // <0,5,0,7>: Cost 3 vtrnl RHS, <0,0,0,0>
- 2637857437U, // <0,5,0,u>: Cost 3 vext2 <3,4,0,5>, LHS
+ 3087011126U, // <0,5,0,7>: Cost 3 vtrnr <0,0,0,0>, RHS
+ 2625913501U, // <0,5,0,u>: Cost 3 vext2 <1,4,0,5>, LHS
1500659814U, // <0,5,1,0>: Cost 2 vext1 <4,0,5,1>, LHS
- 2574402294U, // <0,5,1,1>: Cost 3 vext1 <4,0,5,1>, <1,0,3,2>
+ 2886520528U, // <0,5,1,1>: Cost 3 vzipl LHS, <5,1,7,3>
2574403176U, // <0,5,1,2>: Cost 3 vext1 <4,0,5,1>, <2,2,2,2>
2574403734U, // <0,5,1,3>: Cost 3 vext1 <4,0,5,1>, <3,0,1,2>
1500662674U, // <0,5,1,4>: Cost 2 vext1 <4,0,5,1>, <4,0,5,1>
- 2574405328U, // <0,5,1,5>: Cost 3 vext1 <4,0,5,1>, <5,1,7,3>
- 2574406138U, // <0,5,1,6>: Cost 3 vext1 <4,0,5,1>, <6,2,7,3>
- 2691878608U, // <0,5,1,7>: Cost 3 vext3 <1,2,3,0>, <5,1,7,3>
+ 2886520836U, // <0,5,1,5>: Cost 3 vzipl LHS, <5,5,5,5>
+ 2886520930U, // <0,5,1,6>: Cost 3 vzipl LHS, <5,6,7,0>
+ 2718715600U, // <0,5,1,7>: Cost 3 vext3 <5,6,7,0>, <5,1,7,3>
1500665646U, // <0,5,1,u>: Cost 2 vext1 <4,0,5,1>, LHS
- 2568437862U, // <0,5,2,0>: Cost 3 vext1 <3,0,5,2>, LHS
+ 2556493926U, // <0,5,2,0>: Cost 3 vext1 <1,0,5,2>, LHS
2244546120U, // <0,5,2,1>: Cost 3 vrev <5,0,1,2>
- 3636209121U, // <0,5,2,2>: Cost 4 vext1 <2,0,5,2>, <2,0,5,2>
+ 3692357256U, // <0,5,2,2>: Cost 4 vext2 <0,2,0,5>, <2,2,5,7>
2568439994U, // <0,5,2,3>: Cost 3 vext1 <3,0,5,2>, <3,0,5,2>
- 2568441142U, // <0,5,2,4>: Cost 3 vext1 <3,0,5,2>, RHS
- 3120595046U, // <0,5,2,5>: Cost 3 vtrnr <5,5,5,5>, LHS
- 3765620504U, // <0,5,2,6>: Cost 4 vext3 <1,2,3,0>, <5,2,6,3>
- 3047604244U, // <0,5,2,7>: Cost 3 vtrnl RHS, <0,0,2,2>
- 2568443694U, // <0,5,2,u>: Cost 3 vext1 <3,0,5,2>, LHS
- 3710937274U, // <0,5,3,0>: Cost 4 vext2 <3,3,0,5>, <3,0,5,2>
- 3790024505U, // <0,5,3,1>: Cost 4 vext3 <5,3,1,0>, <5,3,1,0>
- 3318369874U, // <0,5,3,2>: Cost 4 vrev <5,0,2,3>
- 3710937475U, // <0,5,3,3>: Cost 4 vext2 <3,3,0,5>, <3,3,0,5>
+ 2556497206U, // <0,5,2,4>: Cost 3 vext1 <1,0,5,2>, RHS
+ 3020738564U, // <0,5,2,5>: Cost 3 vtrnl LHS, <5,5,5,5>
+ 4027877161U, // <0,5,2,6>: Cost 4 vzipr <0,2,0,2>, <2,4,5,6>
+ 3093220662U, // <0,5,2,7>: Cost 3 vtrnr <1,0,3,2>, RHS
+ 3093220663U, // <0,5,2,u>: Cost 3 vtrnr <1,0,3,2>, RHS
+ 3699656854U, // <0,5,3,0>: Cost 4 vext2 <1,4,0,5>, <3,0,1,2>
+ 3699656927U, // <0,5,3,1>: Cost 4 vext2 <1,4,0,5>, <3,1,0,3>
+ 3699657006U, // <0,5,3,2>: Cost 4 vext2 <1,4,0,5>, <3,2,0,1>
+ 3699657116U, // <0,5,3,3>: Cost 4 vext2 <1,4,0,5>, <3,3,3,3>
2637859284U, // <0,5,3,4>: Cost 3 vext2 <3,4,0,5>, <3,4,0,5>
3790319453U, // <0,5,3,5>: Cost 4 vext3 <5,3,5,0>, <5,3,5,0>
- 3790393190U, // <0,5,3,6>: Cost 4 vext3 <5,3,6,0>, <5,3,6,0>
+ 3699657354U, // <0,5,3,6>: Cost 4 vext2 <1,4,0,5>, <3,6,2,7>
2716725103U, // <0,5,3,7>: Cost 3 vext3 <5,3,7,0>, <5,3,7,0>
- 2640513816U, // <0,5,3,u>: Cost 3 vext2 <3,u,0,5>, <3,u,0,5>
- 2637859730U, // <0,5,4,0>: Cost 3 vext2 <3,4,0,5>, <4,0,5,1>
- 3711601637U, // <0,5,4,1>: Cost 4 vext2 <3,4,0,5>, <4,1,5,3>
+ 2716798840U, // <0,5,3,u>: Cost 3 vext3 <5,3,u,0>, <5,3,u,0>
+ 2661747602U, // <0,5,4,0>: Cost 3 vext2 <7,4,0,5>, <4,0,5,1>
+ 3630252810U, // <0,5,4,1>: Cost 4 vext1 <1,0,5,4>, <1,0,5,4>
3636225507U, // <0,5,4,2>: Cost 4 vext1 <2,0,5,4>, <2,0,5,4>
- 3648170452U, // <0,5,4,3>: Cost 4 vext1 <4,0,5,4>, <3,4,0,5>
- 3636227382U, // <0,5,4,4>: Cost 4 vext1 <2,0,5,4>, RHS
- 2637860150U, // <0,5,4,5>: Cost 3 vext2 <3,4,0,5>, RHS
- 2718715836U, // <0,5,4,6>: Cost 3 vext3 <5,6,7,0>, <5,4,6,5>
+ 3716910172U, // <0,5,4,3>: Cost 4 vext2 <4,3,0,5>, <4,3,0,5>
+ 3962195892U, // <0,5,4,4>: Cost 4 vzipl <0,4,1,5>, <5,4,5,6>
+ 2625916214U, // <0,5,4,5>: Cost 3 vext2 <1,4,0,5>, RHS
+ 3718901071U, // <0,5,4,6>: Cost 4 vext2 <4,6,0,5>, <4,6,0,5>
2718715846U, // <0,5,4,7>: Cost 3 vext3 <5,6,7,0>, <5,4,7,6>
- 2637860393U, // <0,5,4,u>: Cost 3 vext2 <3,4,0,5>, RHS
- 3792457683U, // <0,5,5,0>: Cost 4 vext3 <5,6,7,0>, <5,5,0,1>
- 3704966864U, // <0,5,5,1>: Cost 4 vext2 <2,3,0,5>, <5,1,7,3>
- 3711602411U, // <0,5,5,2>: Cost 4 vext2 <3,4,0,5>, <5,2,1,3>
- 3642206397U, // <0,5,5,3>: Cost 4 vext1 <3,0,5,5>, <3,0,5,5>
+ 2625916457U, // <0,5,4,u>: Cost 3 vext2 <1,4,0,5>, RHS
+ 3791278034U, // <0,5,5,0>: Cost 4 vext3 <5,5,0,0>, <5,5,0,0>
+ 3791351771U, // <0,5,5,1>: Cost 4 vext3 <5,5,1,0>, <5,5,1,0>
+ 3318386260U, // <0,5,5,2>: Cost 4 vrev <5,0,2,5>
+ 3791499245U, // <0,5,5,3>: Cost 4 vext3 <5,5,3,0>, <5,5,3,0>
3318533734U, // <0,5,5,4>: Cost 4 vrev <5,0,4,5>
2718715908U, // <0,5,5,5>: Cost 3 vext3 <5,6,7,0>, <5,5,5,5>
2657767522U, // <0,5,5,6>: Cost 3 vext2 <6,7,0,5>, <5,6,7,0>
2718715928U, // <0,5,5,7>: Cost 3 vext3 <5,6,7,0>, <5,5,7,7>
2718715937U, // <0,5,5,u>: Cost 3 vext3 <5,6,7,0>, <5,5,u,7>
2592358502U, // <0,5,6,0>: Cost 3 vext1 <7,0,5,6>, LHS
- 3788918835U, // <0,5,6,1>: Cost 4 vext3 <5,1,4,0>, <5,6,1,7>
- 3711603194U, // <0,5,6,2>: Cost 4 vext2 <3,4,0,5>, <6,2,7,3>
+ 3792015404U, // <0,5,6,1>: Cost 4 vext3 <5,6,1,0>, <5,6,1,0>
+ 3731509754U, // <0,5,6,2>: Cost 4 vext2 <6,7,0,5>, <6,2,7,3>
3785748546U, // <0,5,6,3>: Cost 4 vext3 <4,5,6,0>, <5,6,3,4>
2592361782U, // <0,5,6,4>: Cost 3 vext1 <7,0,5,6>, RHS
2592362594U, // <0,5,6,5>: Cost 3 vext1 <7,0,5,6>, <5,6,7,0>
- 3792384089U, // <0,5,6,6>: Cost 4 vext3 <5,6,6,0>, <5,6,6,0>
+ 3785748576U, // <0,5,6,6>: Cost 4 vext3 <4,5,6,0>, <5,6,6,7>
1644974178U, // <0,5,6,7>: Cost 2 vext3 <5,6,7,0>, <5,6,7,0>
1645047915U, // <0,5,6,u>: Cost 2 vext3 <5,6,u,0>, <5,6,u,0>
- 3765620854U, // <0,5,7,0>: Cost 4 vext3 <1,2,3,0>, <5,7,0,2>
- 3699659876U, // <0,5,7,1>: Cost 4 vext2 <1,4,0,5>, <7,1,4,0>
- 3792752774U, // <0,5,7,2>: Cost 4 vext3 <5,7,2,0>, <5,7,2,0>
- 3734828263U, // <0,5,7,3>: Cost 4 vext2 <7,3,0,5>, <7,3,0,5>
- 2661750072U, // <0,5,7,4>: Cost 3 vext2 <7,4,0,5>, <7,4,0,5>
- 3792457896U, // <0,5,7,5>: Cost 4 vext3 <5,6,7,0>, <5,7,5,7>
- 3660140874U, // <0,5,7,6>: Cost 4 vext1 <6,0,5,7>, <6,0,5,7>
+ 2562506854U, // <0,5,7,0>: Cost 3 vext1 <2,0,5,7>, LHS
+ 2562507670U, // <0,5,7,1>: Cost 3 vext1 <2,0,5,7>, <1,2,3,0>
+ 2562508262U, // <0,5,7,2>: Cost 3 vext1 <2,0,5,7>, <2,0,5,7>
+ 3636250774U, // <0,5,7,3>: Cost 4 vext1 <2,0,5,7>, <3,0,1,2>
+ 2562510134U, // <0,5,7,4>: Cost 3 vext1 <2,0,5,7>, RHS
+ 2718716072U, // <0,5,7,5>: Cost 3 vext3 <5,6,7,0>, <5,7,5,7>
+ 2718716074U, // <0,5,7,6>: Cost 3 vext3 <5,6,7,0>, <5,7,6,0>
2719379635U, // <0,5,7,7>: Cost 3 vext3 <5,7,7,0>, <5,7,7,0>
- 2719453372U, // <0,5,7,u>: Cost 3 vext3 <5,7,u,0>, <5,7,u,0>
+ 2562512686U, // <0,5,7,u>: Cost 3 vext1 <2,0,5,7>, LHS
1500717158U, // <0,5,u,0>: Cost 2 vext1 <4,0,5,u>, LHS
- 2637862702U, // <0,5,u,1>: Cost 3 vext2 <3,4,0,5>, LHS
- 2574460520U, // <0,5,u,2>: Cost 3 vext1 <4,0,5,u>, <2,2,2,2>
+ 2625918766U, // <0,5,u,1>: Cost 3 vext2 <1,4,0,5>, LHS
+ 2719674583U, // <0,5,u,2>: Cost 3 vext3 <5,u,2,0>, <5,u,2,0>
2568489152U, // <0,5,u,3>: Cost 3 vext1 <3,0,5,u>, <3,0,5,u>
1500720025U, // <0,5,u,4>: Cost 2 vext1 <4,0,5,u>, <4,0,5,u>
- 2637863066U, // <0,5,u,5>: Cost 3 vext2 <3,4,0,5>, RHS
- 2574463482U, // <0,5,u,6>: Cost 3 vext1 <4,0,5,u>, <6,2,7,3>
+ 2625919130U, // <0,5,u,5>: Cost 3 vext2 <1,4,0,5>, RHS
+ 2586407243U, // <0,5,u,6>: Cost 3 vext1 <6,0,5,u>, <6,0,5,u>
1646301444U, // <0,5,u,7>: Cost 2 vext3 <5,u,7,0>, <5,u,7,0>
- 1500722990U, // <0,5,u,u>: Cost 2 vext1 <4,0,5,u>, LHS
- 2574467174U, // <0,6,0,0>: Cost 3 vext1 <4,0,6,0>, LHS
- 2637865062U, // <0,6,0,1>: Cost 3 vext2 <3,4,0,6>, LHS
- 2250576168U, // <0,6,0,2>: Cost 3 vrev <6,0,2,0>
- 3779113269U, // <0,6,0,3>: Cost 4 vext3 <3,4,6,0>, <6,0,3,4>
- 2574470042U, // <0,6,0,4>: Cost 3 vext1 <4,0,6,0>, <4,0,6,0>
- 3648212688U, // <0,6,0,5>: Cost 4 vext1 <4,0,6,0>, <5,1,7,3>
+ 1646375181U, // <0,5,u,u>: Cost 2 vext3 <5,u,u,0>, <5,u,u,0>
+ 2586411110U, // <0,6,0,0>: Cost 3 vext1 <6,0,6,0>, LHS
+ 2619949158U, // <0,6,0,1>: Cost 3 vext2 <0,4,0,6>, LHS
+ 2619949220U, // <0,6,0,2>: Cost 3 vext2 <0,4,0,6>, <0,2,0,2>
+ 3785748789U, // <0,6,0,3>: Cost 4 vext3 <4,5,6,0>, <6,0,3,4>
+ 2619949386U, // <0,6,0,4>: Cost 3 vext2 <0,4,0,6>, <0,4,0,6>
+ 2586415202U, // <0,6,0,5>: Cost 3 vext1 <6,0,6,0>, <5,6,7,0>
2586415436U, // <0,6,0,6>: Cost 3 vext1 <6,0,6,0>, <6,0,6,0>
- 2913386496U, // <0,6,0,7>: Cost 3 vzipl RHS, <0,0,0,0>
- 2637865629U, // <0,6,0,u>: Cost 3 vext2 <3,4,0,6>, LHS
- 2574475366U, // <0,6,1,0>: Cost 3 vext1 <4,0,6,1>, LHS
- 3699663668U, // <0,6,1,1>: Cost 4 vext2 <1,4,0,6>, <1,1,1,1>
- 2990489702U, // <0,6,1,2>: Cost 3 vzipr <6,2,7,3>, LHS
- 3642247362U, // <0,6,1,3>: Cost 4 vext1 <3,0,6,1>, <3,0,6,1>
- 2574478235U, // <0,6,1,4>: Cost 3 vext1 <4,0,6,1>, <4,0,6,1>
+ 2952793398U, // <0,6,0,7>: Cost 3 vzipr <0,0,0,0>, RHS
+ 2619949725U, // <0,6,0,u>: Cost 3 vext2 <0,4,0,6>, LHS
+ 2562531430U, // <0,6,1,0>: Cost 3 vext1 <2,0,6,1>, LHS
+ 3693691700U, // <0,6,1,1>: Cost 4 vext2 <0,4,0,6>, <1,1,1,1>
+ 2886521338U, // <0,6,1,2>: Cost 3 vzipl LHS, <6,2,7,3>
+ 3693691864U, // <0,6,1,3>: Cost 4 vext2 <0,4,0,6>, <1,3,1,3>
+ 2562534710U, // <0,6,1,4>: Cost 3 vext1 <2,0,6,1>, RHS
2580450932U, // <0,6,1,5>: Cost 3 vext1 <5,0,6,1>, <5,0,6,1>
- 2993094758U, // <0,6,1,6>: Cost 3 vzipr <6,6,6,6>, LHS
- 2913388198U, // <0,6,1,7>: Cost 3 vzipl RHS, <2,3,0,1>
- 2574481198U, // <0,6,1,u>: Cost 3 vext1 <4,0,6,1>, LHS
+ 2886521656U, // <0,6,1,6>: Cost 3 vzipl LHS, <6,6,6,6>
+ 2966736182U, // <0,6,1,7>: Cost 3 vzipr <2,3,0,1>, RHS
+ 2966736183U, // <0,6,1,u>: Cost 3 vzipr <2,3,0,1>, RHS
1500741734U, // <0,6,2,0>: Cost 2 vext1 <4,0,6,2>, LHS
- 2574484214U, // <0,6,2,1>: Cost 3 vext1 <4,0,6,2>, <1,0,3,2>
+ 2250518817U, // <0,6,2,1>: Cost 3 vrev <6,0,1,2>
2574485096U, // <0,6,2,2>: Cost 3 vext1 <4,0,6,2>, <2,2,2,2>
- 2574485654U, // <0,6,2,3>: Cost 3 vext1 <4,0,6,2>, <3,0,1,2>
+ 2631894694U, // <0,6,2,3>: Cost 3 vext2 <2,4,0,6>, <2,3,0,1>
1500744604U, // <0,6,2,4>: Cost 2 vext1 <4,0,6,2>, <4,0,6,2>
2574487248U, // <0,6,2,5>: Cost 3 vext1 <4,0,6,2>, <5,1,7,3>
- 2574488013U, // <0,6,2,6>: Cost 3 vext1 <4,0,6,2>, <6,2,2,3>
- 2691879418U, // <0,6,2,7>: Cost 3 vext3 <1,2,3,0>, <6,2,7,3>
+ 3020739384U, // <0,6,2,6>: Cost 3 vtrnl LHS, <6,6,6,6>
+ 2954136886U, // <0,6,2,7>: Cost 3 vzipr <0,2,0,2>, RHS
1500747566U, // <0,6,2,u>: Cost 2 vext1 <4,0,6,2>, LHS
- 3711608982U, // <0,6,3,0>: Cost 4 vext2 <3,4,0,6>, <3,0,1,2>
- 3324268834U, // <0,6,3,1>: Cost 4 vrev <6,0,1,3>
- 3324342571U, // <0,6,3,2>: Cost 4 vrev <6,0,2,3>
- 3711609244U, // <0,6,3,3>: Cost 4 vext2 <3,4,0,6>, <3,3,3,3>
+ 3693693078U, // <0,6,3,0>: Cost 4 vext2 <0,4,0,6>, <3,0,1,2>
+ 3705637136U, // <0,6,3,1>: Cost 4 vext2 <2,4,0,6>, <3,1,5,7>
+ 3705637192U, // <0,6,3,2>: Cost 4 vext2 <2,4,0,6>, <3,2,3,0>
+ 3693693340U, // <0,6,3,3>: Cost 4 vext2 <0,4,0,6>, <3,3,3,3>
2637867477U, // <0,6,3,4>: Cost 3 vext2 <3,4,0,6>, <3,4,0,6>
- 3796292150U, // <0,6,3,5>: Cost 4 vext3 <6,3,5,0>, <6,3,5,0>
+ 3705637424U, // <0,6,3,5>: Cost 4 vext2 <2,4,0,6>, <3,5,1,7>
3666154056U, // <0,6,3,6>: Cost 4 vext1 <7,0,6,3>, <6,3,7,0>
2722697800U, // <0,6,3,7>: Cost 3 vext3 <6,3,7,0>, <6,3,7,0>
- 2640522009U, // <0,6,3,u>: Cost 3 vext2 <3,u,0,6>, <3,u,0,6>
- 2637867932U, // <0,6,4,0>: Cost 3 vext2 <3,4,0,6>, <4,0,6,2>
- 3324277027U, // <0,6,4,1>: Cost 4 vrev <6,0,1,4>
- 2250608940U, // <0,6,4,2>: Cost 3 vrev <6,0,2,4>
- 3711609997U, // <0,6,4,3>: Cost 4 vext2 <3,4,0,6>, <4,3,6,0>
- 3648244638U, // <0,6,4,4>: Cost 4 vext1 <4,0,6,4>, <4,0,6,4>
- 2637868342U, // <0,6,4,5>: Cost 3 vext2 <3,4,0,6>, RHS
+ 2722771537U, // <0,6,3,u>: Cost 3 vext3 <6,3,u,0>, <6,3,u,0>
+ 2562556006U, // <0,6,4,0>: Cost 3 vext1 <2,0,6,4>, LHS
+ 4095316257U, // <0,6,4,1>: Cost 4 vtrnl <0,2,4,6>, <6,0,1,2>
+ 2562557420U, // <0,6,4,2>: Cost 3 vext1 <2,0,6,4>, <2,0,6,4>
+ 3636299926U, // <0,6,4,3>: Cost 4 vext1 <2,0,6,4>, <3,0,1,2>
+ 2562559286U, // <0,6,4,4>: Cost 3 vext1 <2,0,6,4>, RHS
+ 2619952438U, // <0,6,4,5>: Cost 3 vext2 <0,4,0,6>, RHS
2723287696U, // <0,6,4,6>: Cost 3 vext3 <6,4,6,0>, <6,4,6,0>
- 3779039902U, // <0,6,4,7>: Cost 4 vext3 <3,4,5,0>, <6,4,7,5>
- 2637868585U, // <0,6,4,u>: Cost 3 vext2 <3,4,0,6>, RHS
+ 4027895094U, // <0,6,4,7>: Cost 4 vzipr <0,2,0,4>, RHS
+ 2619952681U, // <0,6,4,u>: Cost 3 vext2 <0,4,0,6>, RHS
2718716594U, // <0,6,5,0>: Cost 3 vext3 <5,6,7,0>, <6,5,0,7>
- 3711610576U, // <0,6,5,1>: Cost 4 vext2 <3,4,0,6>, <5,1,7,3>
- 3786265284U, // <0,6,5,2>: Cost 4 vext3 <4,6,4,0>, <6,5,2,7>
- 3711610736U, // <0,6,5,3>: Cost 5 vext2 <3,4,0,6>, <5,3,7,1>
- 3723554695U, // <0,6,5,4>: Cost 4 vext2 <5,4,0,6>, <5,4,0,6>
- 3792458460U, // <0,6,5,5>: Cost 4 vext3 <5,6,7,0>, <6,5,5,4>
+ 3648250774U, // <0,6,5,1>: Cost 4 vext1 <4,0,6,5>, <1,2,3,0>
+ 3792458436U, // <0,6,5,2>: Cost 4 vext3 <5,6,7,0>, <6,5,2,7>
+ 3705638767U, // <0,6,5,3>: Cost 5 vext2 <2,4,0,6>, <5,3,7,0>
+ 3648252831U, // <0,6,5,4>: Cost 4 vext1 <4,0,6,5>, <4,0,6,5>
+ 3797619416U, // <0,6,5,5>: Cost 4 vext3 <6,5,5,0>, <6,5,5,0>
3792458472U, // <0,6,5,6>: Cost 4 vext3 <5,6,7,0>, <6,5,6,7>
- 3784643307U, // <0,6,5,7>: Cost 4 vext3 <4,4,0,0>, <6,5,7,1>
+ 4035202358U, // <0,6,5,7>: Cost 4 vzipr <1,4,0,5>, RHS
2718716594U, // <0,6,5,u>: Cost 3 vext3 <5,6,7,0>, <6,5,0,7>
3786412796U, // <0,6,6,0>: Cost 4 vext3 <4,6,6,0>, <6,6,0,0>
- 3765621511U, // <0,6,6,1>: Cost 4 vext3 <1,2,3,0>, <6,6,1,2>
- 3704975866U, // <0,6,6,2>: Cost 4 vext2 <2,3,0,6>, <6,2,7,3>
- 3642288327U, // <0,6,6,3>: Cost 4 vext1 <3,0,6,6>, <3,0,6,6>
+ 3792458504U, // <0,6,6,1>: Cost 4 vext3 <5,6,7,0>, <6,6,1,3>
+ 3728200126U, // <0,6,6,2>: Cost 4 vext2 <6,2,0,6>, <6,2,0,6>
+ 3798135575U, // <0,6,6,3>: Cost 4 vext3 <6,6,3,0>, <6,6,3,0>
3786412836U, // <0,6,6,4>: Cost 4 vext3 <4,6,6,0>, <6,6,4,4>
- 3666178146U, // <0,6,6,5>: Cost 4 vext1 <7,0,6,6>, <5,6,7,0>
+ 3792458543U, // <0,6,6,5>: Cost 4 vext3 <5,6,7,0>, <6,6,5,6>
2718716728U, // <0,6,6,6>: Cost 3 vext3 <5,6,7,0>, <6,6,6,6>
2718716738U, // <0,6,6,7>: Cost 3 vext3 <5,6,7,0>, <6,6,7,7>
2718716747U, // <0,6,6,u>: Cost 3 vext3 <5,6,7,0>, <6,6,u,7>
2718716750U, // <0,6,7,0>: Cost 3 vext3 <5,6,7,0>, <6,7,0,1>
2724909910U, // <0,6,7,1>: Cost 3 vext3 <6,7,1,0>, <6,7,1,0>
- 3786117986U, // <0,6,7,2>: Cost 4 vext3 <4,6,2,0>, <6,7,2,3>
+ 3636323823U, // <0,6,7,2>: Cost 4 vext1 <2,0,6,7>, <2,0,6,7>
2725057384U, // <0,6,7,3>: Cost 3 vext3 <6,7,3,0>, <6,7,3,0>
2718716790U, // <0,6,7,4>: Cost 3 vext3 <5,6,7,0>, <6,7,4,5>
2718716800U, // <0,6,7,5>: Cost 3 vext3 <5,6,7,0>, <6,7,5,6>
@@ -580,241 +580,241 @@ static const unsigned PerfectShuffleTable[6561+1] = {
2725352332U, // <0,6,7,7>: Cost 3 vext3 <6,7,7,0>, <6,7,7,0>
2718716822U, // <0,6,7,u>: Cost 3 vext3 <5,6,7,0>, <6,7,u,1>
1500790886U, // <0,6,u,0>: Cost 2 vext1 <4,0,6,u>, LHS
- 2637870894U, // <0,6,u,1>: Cost 3 vext2 <3,4,0,6>, LHS
- 2574534248U, // <0,6,u,2>: Cost 3 vext1 <4,0,6,u>, <2,2,2,2>
- 2574534806U, // <0,6,u,3>: Cost 3 vext1 <4,0,6,u>, <3,0,1,2>
+ 2619954990U, // <0,6,u,1>: Cost 3 vext2 <0,4,0,6>, LHS
+ 2562590192U, // <0,6,u,2>: Cost 3 vext1 <2,0,6,u>, <2,0,6,u>
+ 2725721017U, // <0,6,u,3>: Cost 3 vext3 <6,u,3,0>, <6,u,3,0>
1500793762U, // <0,6,u,4>: Cost 2 vext1 <4,0,6,u>, <4,0,6,u>
- 2637871258U, // <0,6,u,5>: Cost 3 vext2 <3,4,0,6>, RHS
- 2574537210U, // <0,6,u,6>: Cost 3 vext1 <4,0,6,u>, <6,2,7,3>
- 2691879904U, // <0,6,u,7>: Cost 3 vext3 <1,2,3,0>, <6,u,7,3>
+ 2619955354U, // <0,6,u,5>: Cost 3 vext2 <0,4,0,6>, RHS
+ 2725942228U, // <0,6,u,6>: Cost 3 vext3 <6,u,6,0>, <6,u,6,0>
+ 2954186038U, // <0,6,u,7>: Cost 3 vzipr <0,2,0,u>, RHS
1500796718U, // <0,6,u,u>: Cost 2 vext1 <4,0,6,u>, LHS
2256401391U, // <0,7,0,0>: Cost 3 vrev <7,0,0,0>
- 2718716922U, // <0,7,0,1>: Cost 3 vext3 <5,6,7,0>, <7,0,1,2>
+ 2632564838U, // <0,7,0,1>: Cost 3 vext2 <2,5,0,7>, LHS
2256548865U, // <0,7,0,2>: Cost 3 vrev <7,0,2,0>
- 3990487040U, // <0,7,0,3>: Cost 4 vzipl <5,1,7,3>, <0,0,0,0>
+ 3700998396U, // <0,7,0,3>: Cost 4 vext2 <1,6,0,7>, <0,3,1,0>
2718716952U, // <0,7,0,4>: Cost 3 vext3 <5,6,7,0>, <7,0,4,5>
2718716962U, // <0,7,0,5>: Cost 3 vext3 <5,6,7,0>, <7,0,5,6>
2621284845U, // <0,7,0,6>: Cost 3 vext2 <0,6,0,7>, <0,6,0,7>
- 3993174016U, // <0,7,0,7>: Cost 4 vzipl <5,5,7,7>, <0,0,0,0>
- 2718716984U, // <0,7,0,u>: Cost 3 vext3 <5,6,7,0>, <7,0,u,1>
- 2580521062U, // <0,7,1,0>: Cost 3 vext1 <5,0,7,1>, LHS
- 3654263542U, // <0,7,1,1>: Cost 4 vext1 <5,0,7,1>, <1,0,3,2>
- 2586494630U, // <0,7,1,2>: Cost 3 vext1 <6,0,7,1>, <2,3,0,1>
- 3654264982U, // <0,7,1,3>: Cost 4 vext1 <5,0,7,1>, <3,0,1,2>
- 2580523922U, // <0,7,1,4>: Cost 3 vext1 <5,0,7,1>, <4,0,5,1>
- 2580524669U, // <0,7,1,5>: Cost 3 vext1 <5,0,7,1>, <5,0,7,1>
- 2586497366U, // <0,7,1,6>: Cost 3 vext1 <6,0,7,1>, <6,0,7,1>
- 2999812198U, // <0,7,1,7>: Cost 3 vzipr <7,7,7,7>, LHS
- 2580526894U, // <0,7,1,u>: Cost 3 vext1 <5,0,7,1>, LHS
- 2580529254U, // <0,7,2,0>: Cost 3 vext1 <5,0,7,2>, LHS
+ 3904685542U, // <0,7,0,7>: Cost 4 vuzpr <2,0,5,7>, <2,0,5,7>
+ 2632565405U, // <0,7,0,u>: Cost 3 vext2 <2,5,0,7>, LHS
+ 2256409584U, // <0,7,1,0>: Cost 3 vrev <7,0,0,1>
+ 3706307380U, // <0,7,1,1>: Cost 4 vext2 <2,5,0,7>, <1,1,1,1>
+ 2632565654U, // <0,7,1,2>: Cost 3 vext2 <2,5,0,7>, <1,2,3,0>
+ 3769603168U, // <0,7,1,3>: Cost 4 vext3 <1,u,3,0>, <7,1,3,5>
+ 2256704532U, // <0,7,1,4>: Cost 3 vrev <7,0,4,1>
+ 3769603184U, // <0,7,1,5>: Cost 4 vext3 <1,u,3,0>, <7,1,5,3>
+ 3700999366U, // <0,7,1,6>: Cost 4 vext2 <1,6,0,7>, <1,6,0,7>
+ 2886522476U, // <0,7,1,7>: Cost 3 vzipl LHS, <7,7,7,7>
+ 2256999480U, // <0,7,1,u>: Cost 3 vrev <7,0,u,1>
+ 2586501222U, // <0,7,2,0>: Cost 3 vext1 <6,0,7,2>, LHS
1182749690U, // <0,7,2,1>: Cost 2 vrev <7,0,1,2>
- 3654272616U, // <0,7,2,2>: Cost 4 vext1 <5,0,7,2>, <2,2,2,2>
+ 3636356595U, // <0,7,2,2>: Cost 4 vext1 <2,0,7,2>, <2,0,7,2>
2727711916U, // <0,7,2,3>: Cost 3 vext3 <7,2,3,0>, <7,2,3,0>
- 2580532534U, // <0,7,2,4>: Cost 3 vext1 <5,0,7,2>, RHS
- 2580532862U, // <0,7,2,5>: Cost 3 vext1 <5,0,7,2>, <5,0,7,2>
+ 2586504502U, // <0,7,2,4>: Cost 3 vext1 <6,0,7,2>, RHS
+ 2632566606U, // <0,7,2,5>: Cost 3 vext2 <2,5,0,7>, <2,5,0,7>
2586505559U, // <0,7,2,6>: Cost 3 vext1 <6,0,7,2>, <6,0,7,2>
- 3134029926U, // <0,7,2,7>: Cost 3 vtrnr <7,7,7,7>, LHS
+ 3020740204U, // <0,7,2,7>: Cost 3 vtrnl LHS, <7,7,7,7>
1183265849U, // <0,7,2,u>: Cost 2 vrev <7,0,u,2>
- 3792458979U, // <0,7,3,0>: Cost 4 vext3 <5,6,7,0>, <7,3,0,1>
- 3330241531U, // <0,7,3,1>: Cost 4 vrev <7,0,1,3>
+ 3701000342U, // <0,7,3,0>: Cost 4 vext2 <1,6,0,7>, <3,0,1,2>
+ 3706308849U, // <0,7,3,1>: Cost 4 vext2 <2,5,0,7>, <3,1,2,3>
3330315268U, // <0,7,3,2>: Cost 4 vrev <7,0,2,3>
- 3792459008U, // <0,7,3,3>: Cost 4 vext3 <5,6,7,0>, <7,3,3,3>
- 3787740430U, // <0,7,3,4>: Cost 4 vext3 <4,u,6,0>, <7,3,4,u>
+ 3706309020U, // <0,7,3,3>: Cost 4 vext2 <2,5,0,7>, <3,3,3,3>
+ 3706309122U, // <0,7,3,4>: Cost 4 vext2 <2,5,0,7>, <3,4,5,6>
3712281127U, // <0,7,3,5>: Cost 4 vext2 <3,5,0,7>, <3,5,0,7>
- 3712944760U, // <0,7,3,6>: Cost 4 vext2 <3,6,0,7>, <3,6,0,7>
+ 2639202936U, // <0,7,3,6>: Cost 3 vext2 <3,6,0,7>, <3,6,0,7>
3802412321U, // <0,7,3,7>: Cost 4 vext3 <7,3,7,0>, <7,3,7,0>
- 3714272026U, // <0,7,3,u>: Cost 4 vext2 <3,u,0,7>, <3,u,0,7>
+ 2640530202U, // <0,7,3,u>: Cost 3 vext2 <3,u,0,7>, <3,u,0,7>
3654287462U, // <0,7,4,0>: Cost 4 vext1 <5,0,7,4>, LHS
2256507900U, // <0,7,4,1>: Cost 3 vrev <7,0,1,4>
2256581637U, // <0,7,4,2>: Cost 3 vrev <7,0,2,4>
- 3330397198U, // <0,7,4,3>: Cost 4 vrev <7,0,3,4>
+ 3660262008U, // <0,7,4,3>: Cost 4 vext1 <6,0,7,4>, <3,6,0,7>
3786413405U, // <0,7,4,4>: Cost 4 vext3 <4,6,6,0>, <7,4,4,6>
- 2718717286U, // <0,7,4,5>: Cost 3 vext3 <5,6,7,0>, <7,4,5,6>
- 2729260393U, // <0,7,4,6>: Cost 3 vext3 <7,4,6,0>, <7,4,6,0>
- 3792459127U, // <0,7,4,7>: Cost 4 vext3 <5,6,7,0>, <7,4,7,5>
- 2718717313U, // <0,7,4,u>: Cost 3 vext3 <5,6,7,0>, <7,4,u,6>
- 3712282238U, // <0,7,5,0>: Cost 4 vext2 <3,5,0,7>, <5,0,7,2>
- 3712282320U, // <0,7,5,1>: Cost 4 vext2 <3,5,0,7>, <5,1,7,3>
- 3789804957U, // <0,7,5,2>: Cost 4 vext3 <5,2,7,0>, <7,5,2,7>
- 3654297780U, // <0,7,5,3>: Cost 4 vext1 <5,0,7,5>, <3,0,4,5>
+ 2632568118U, // <0,7,4,5>: Cost 3 vext2 <2,5,0,7>, RHS
+ 3718917457U, // <0,7,4,6>: Cost 4 vext2 <4,6,0,7>, <4,6,0,7>
+ 3787003255U, // <0,7,4,7>: Cost 4 vext3 <4,7,5,0>, <7,4,7,5>
+ 2632568361U, // <0,7,4,u>: Cost 3 vext2 <2,5,0,7>, RHS
+ 3706310268U, // <0,7,5,0>: Cost 4 vext2 <2,5,0,7>, <5,0,7,0>
+ 3792459156U, // <0,7,5,1>: Cost 4 vext3 <5,6,7,0>, <7,5,1,7>
+ 3330331654U, // <0,7,5,2>: Cost 4 vrev <7,0,2,5>
+ 3722899255U, // <0,7,5,3>: Cost 4 vext2 <5,3,0,7>, <5,3,0,7>
2256737304U, // <0,7,5,4>: Cost 3 vrev <7,0,4,5>
- 3654299265U, // <0,7,5,5>: Cost 4 vext1 <5,0,7,5>, <5,0,7,5>
+ 3724226521U, // <0,7,5,5>: Cost 4 vext2 <5,5,0,7>, <5,5,0,7>
2718717377U, // <0,7,5,6>: Cost 3 vext3 <5,6,7,0>, <7,5,6,7>
- 3792459210U, // <0,7,5,7>: Cost 4 vext3 <5,6,7,0>, <7,5,7,7>
- 2257032252U, // <0,7,5,u>: Cost 3 vrev <7,0,u,5>
- 3712946519U, // <0,7,6,0>: Cost 4 vext2 <3,6,0,7>, <6,0,7,2>
+ 2729997763U, // <0,7,5,7>: Cost 3 vext3 <7,5,7,0>, <7,5,7,0>
+ 2720044499U, // <0,7,5,u>: Cost 3 vext3 <5,u,7,0>, <7,5,u,7>
+ 3712946517U, // <0,7,6,0>: Cost 4 vext2 <3,6,0,7>, <6,0,7,0>
2256524286U, // <0,7,6,1>: Cost 3 vrev <7,0,1,6>
- 3712946682U, // <0,7,6,2>: Cost 4 vext2 <3,6,0,7>, <6,2,7,3>
- 3660278229U, // <0,7,6,3>: Cost 4 vext1 <6,0,7,6>, <3,4,0,6>
- 3792459262U, // <0,7,6,4>: Cost 4 vext3 <5,6,7,0>, <7,6,4,5>
+ 3792459246U, // <0,7,6,2>: Cost 4 vext3 <5,6,7,0>, <7,6,2,7>
+ 3796440567U, // <0,7,6,3>: Cost 4 vext3 <6,3,7,0>, <7,6,3,7>
+ 3654307126U, // <0,7,6,4>: Cost 4 vext1 <5,0,7,6>, RHS
2656457394U, // <0,7,6,5>: Cost 3 vext2 <6,5,0,7>, <6,5,0,7>
3792459281U, // <0,7,6,6>: Cost 4 vext3 <5,6,7,0>, <7,6,6,6>
2730661396U, // <0,7,6,7>: Cost 3 vext3 <7,6,7,0>, <7,6,7,0>
2658448293U, // <0,7,6,u>: Cost 3 vext2 <6,u,0,7>, <6,u,0,7>
- 3792459303U, // <0,7,7,0>: Cost 4 vext3 <5,6,7,0>, <7,7,0,1>
- 3934208226U, // <0,7,7,1>: Cost 4 vuzpr <7,0,1,2>, <0,2,7,1>
- 3801454139U, // <0,7,7,2>: Cost 4 vext3 <7,2,3,0>, <7,7,2,3>
+ 3787003431U, // <0,7,7,0>: Cost 4 vext3 <4,7,5,0>, <7,7,0,1>
+ 3654312854U, // <0,7,7,1>: Cost 4 vext1 <5,0,7,7>, <1,2,3,0>
+ 3654313446U, // <0,7,7,2>: Cost 4 vext1 <5,0,7,7>, <2,0,5,7>
3804771905U, // <0,7,7,3>: Cost 4 vext3 <7,7,3,0>, <7,7,3,0>
- 3792459343U, // <0,7,7,4>: Cost 4 vext3 <5,6,7,0>, <7,7,4,5>
- 3792459352U, // <0,7,7,5>: Cost 4 vext3 <5,6,7,0>, <7,7,5,5>
- 3730200066U, // <0,7,7,6>: Cost 4 vext2 <6,5,0,7>, <7,6,5,0>
+ 3654315318U, // <0,7,7,4>: Cost 4 vext1 <5,0,7,7>, RHS
+ 3654315651U, // <0,7,7,5>: Cost 4 vext1 <5,0,7,7>, <5,0,7,7>
+ 3660288348U, // <0,7,7,6>: Cost 4 vext1 <6,0,7,7>, <6,0,7,7>
2718717548U, // <0,7,7,7>: Cost 3 vext3 <5,6,7,0>, <7,7,7,7>
- 2718717548U, // <0,7,7,u>: Cost 3 vext3 <5,6,7,0>, <7,7,7,7>
- 2580578406U, // <0,7,u,0>: Cost 3 vext1 <5,0,7,u>, LHS
+ 2664420990U, // <0,7,7,u>: Cost 3 vext2 <7,u,0,7>, <7,u,0,7>
+ 2256466935U, // <0,7,u,0>: Cost 3 vrev <7,0,0,u>
1182798848U, // <0,7,u,1>: Cost 2 vrev <7,0,1,u>
- 2731619977U, // <0,7,u,2>: Cost 3 vext3 <7,u,2,0>, <7,u,2,0>
+ 2256614409U, // <0,7,u,2>: Cost 3 vrev <7,0,2,u>
2731693714U, // <0,7,u,3>: Cost 3 vext3 <7,u,3,0>, <7,u,3,0>
- 2580581686U, // <0,7,u,4>: Cost 3 vext1 <5,0,7,u>, RHS
- 2580582020U, // <0,7,u,5>: Cost 3 vext1 <5,0,7,u>, <5,0,7,u>
- 2586554717U, // <0,7,u,6>: Cost 3 vext1 <6,0,7,u>, <6,0,7,u>
- 2999812765U, // <0,7,u,7>: Cost 3 vzipr <7,7,7,7>, LHS
+ 2256761883U, // <0,7,u,4>: Cost 3 vrev <7,0,4,u>
+ 2632571034U, // <0,7,u,5>: Cost 3 vext2 <2,5,0,7>, RHS
+ 2669066421U, // <0,7,u,6>: Cost 3 vext2 <u,6,0,7>, <u,6,0,7>
+ 2731988662U, // <0,7,u,7>: Cost 3 vext3 <7,u,7,0>, <7,u,7,0>
1183315007U, // <0,7,u,u>: Cost 2 vrev <7,0,u,u>
135053414U, // <0,u,0,0>: Cost 1 vdup0 LHS
1544896614U, // <0,u,0,1>: Cost 2 vext2 <0,2,0,u>, LHS
- 1745666204U, // <0,u,0,2>: Cost 2 vuzpr LHS, LHS
- 2886959104U, // <0,u,0,3>: Cost 3 vzipl LHS, <0,0,0,0>
+ 1678999654U, // <0,u,0,2>: Cost 2 vuzpl LHS, LHS
+ 2691880677U, // <0,u,0,3>: Cost 3 vext3 <1,2,3,0>, <u,0,3,2>
1476988214U, // <0,u,0,4>: Cost 2 vext1 <0,0,u,0>, RHS
- 2691880694U, // <0,u,0,5>: Cost 3 vext3 <1,2,3,0>, <u,0,5,1>
- 2691880704U, // <0,u,0,6>: Cost 3 vext3 <1,2,3,0>, <u,0,6,2>
- 2913533952U, // <0,u,0,7>: Cost 3 vzipl RHS, <0,0,0,0>
+ 2718791419U, // <0,u,0,5>: Cost 3 vext3 <5,6,u,0>, <u,0,5,6>
+ 3021248666U, // <0,u,0,6>: Cost 3 vtrnl <0,2,0,2>, RHS
+ 2592535607U, // <0,u,0,7>: Cost 3 vext1 <7,0,u,0>, <7,0,u,0>
135053414U, // <0,u,0,u>: Cost 1 vdup0 LHS
- 1500880998U, // <0,u,1,0>: Cost 2 vext1 <4,0,u,1>, LHS
- 1927659622U, // <0,u,1,1>: Cost 2 vzipr LHS, LHS
+ 1476993097U, // <0,u,1,0>: Cost 2 vext1 <0,0,u,1>, <0,0,u,1>
+ 1812780846U, // <0,u,1,1>: Cost 2 vzipl LHS, LHS
1618138926U, // <0,u,1,2>: Cost 2 vext3 <1,2,3,0>, LHS
- 2886960806U, // <0,u,1,3>: Cost 3 vzipl LHS, <2,3,0,1>
- 1500883885U, // <0,u,1,4>: Cost 2 vext1 <4,0,u,1>, <4,0,u,1>
- 1930641510U, // <0,u,1,5>: Cost 2 vzipr RHS, LHS
- 2574627322U, // <0,u,1,6>: Cost 3 vext1 <4,0,u,1>, <6,2,7,3>
- 2691880795U, // <0,u,1,7>: Cost 3 vext3 <1,2,3,0>, <u,1,7,3>
- 1618138980U, // <0,u,1,u>: Cost 2 vext3 <1,2,3,0>, LHS
+ 2752742134U, // <0,u,1,3>: Cost 3 vuzpl LHS, <1,0,3,2>
+ 1476996406U, // <0,u,1,4>: Cost 2 vext1 <0,0,u,1>, RHS
+ 1812781210U, // <0,u,1,5>: Cost 2 vzipl LHS, RHS
+ 2887006416U, // <0,u,1,6>: Cost 3 vzipl LHS, <u,6,3,7>
+ 2966736200U, // <0,u,1,7>: Cost 3 vzipr <2,3,0,1>, RHS
+ 1812781413U, // <0,u,1,u>: Cost 2 vzipl LHS, LHS
1482973286U, // <0,u,2,0>: Cost 2 vext1 <1,0,u,2>, LHS
1482973987U, // <0,u,2,1>: Cost 2 vext1 <1,0,u,2>, <1,0,u,2>
- 2061877350U, // <0,u,2,2>: Cost 2 vtrnr LHS, LHS
+ 1946998574U, // <0,u,2,2>: Cost 2 vtrnl LHS, LHS
835584U, // <0,u,2,3>: Cost 0 copy LHS
1482976566U, // <0,u,2,4>: Cost 2 vext1 <1,0,u,2>, RHS
- 2556718800U, // <0,u,2,5>: Cost 3 vext1 <1,0,u,2>, <5,1,7,3>
- 2064859238U, // <0,u,2,6>: Cost 2 vtrnr RHS, LHS
+ 3020781631U, // <0,u,2,5>: Cost 3 vtrnl LHS, <u,4,5,6>
+ 1946998938U, // <0,u,2,6>: Cost 2 vtrnl LHS, RHS
1518810169U, // <0,u,2,7>: Cost 2 vext1 <7,0,u,2>, <7,0,u,2>
835584U, // <0,u,2,u>: Cost 0 copy LHS
2618640534U, // <0,u,3,0>: Cost 3 vext2 <0,2,0,u>, <3,0,1,2>
- 2691880902U, // <0,u,3,1>: Cost 3 vext3 <1,2,3,0>, <u,3,1,2>
+ 2752743574U, // <0,u,3,1>: Cost 3 vuzpl LHS, <3,0,1,2>
2636556597U, // <0,u,3,2>: Cost 3 vext2 <3,2,0,u>, <3,2,0,u>
- 2618640796U, // <0,u,3,3>: Cost 3 vext2 <0,2,0,u>, <3,3,3,3>
+ 2752743836U, // <0,u,3,3>: Cost 3 vuzpl LHS, <3,3,3,3>
2618640898U, // <0,u,3,4>: Cost 3 vext2 <0,2,0,u>, <3,4,5,6>
- 2839560348U, // <0,u,3,5>: Cost 3 vuzpr <3,4,5,6>, LHS
- 2657733296U, // <0,u,3,6>: Cost 3 vext2 <6,7,0,1>, <3,6,7,0>
- 2734643194U, // <0,u,3,7>: Cost 3 vext3 <u,3,7,0>, <u,3,7,0>
- 2618641182U, // <0,u,3,u>: Cost 3 vext2 <0,2,0,u>, <3,u,1,2>
- 2618641298U, // <0,u,4,0>: Cost 3 vext2 <0,2,0,u>, <4,0,5,1>
- 2718717978U, // <0,u,4,1>: Cost 3 vext3 <5,6,7,0>, <u,4,1,5>
- 2562704894U, // <0,u,4,2>: Cost 3 vext1 <2,0,u,4>, <2,0,u,4>
+ 2752743938U, // <0,u,3,5>: Cost 3 vuzpl LHS, <3,4,5,6>
+ 2639202936U, // <0,u,3,6>: Cost 3 vext2 <3,6,0,7>, <3,6,0,7>
+ 2639874762U, // <0,u,3,7>: Cost 3 vext2 <3,7,0,u>, <3,7,0,u>
+ 2752743637U, // <0,u,3,u>: Cost 3 vuzpl LHS, <3,0,u,2>
+ 2562703462U, // <0,u,4,0>: Cost 3 vext1 <2,0,u,4>, LHS
+ 2888455982U, // <0,u,4,1>: Cost 3 vzipl <0,4,1,5>, LHS
+ 3021575982U, // <0,u,4,2>: Cost 3 vtrnl <0,2,4,6>, LHS
2568677591U, // <0,u,4,3>: Cost 3 vext1 <3,0,u,4>, <3,0,u,4>
2562706742U, // <0,u,4,4>: Cost 3 vext1 <2,0,u,4>, RHS
1544899894U, // <0,u,4,5>: Cost 2 vext2 <0,2,0,u>, RHS
- 1772535964U, // <0,u,4,6>: Cost 2 vuzpr RHS, LHS
+ 1679002934U, // <0,u,4,6>: Cost 2 vuzpl LHS, RHS
2718718033U, // <0,u,4,7>: Cost 3 vext3 <5,6,7,0>, <u,4,7,6>
- 1544900137U, // <0,u,4,u>: Cost 2 vext2 <0,2,0,u>, RHS
+ 1679002952U, // <0,u,4,u>: Cost 2 vuzpl LHS, RHS
2568683622U, // <0,u,5,0>: Cost 3 vext1 <3,0,u,5>, LHS
- 2618642128U, // <0,u,5,1>: Cost 3 vext2 <0,2,0,u>, <5,1,7,3>
- 2618642214U, // <0,u,5,2>: Cost 3 vext2 <0,2,0,u>, <5,2,7,u>
- 2568685784U, // <0,u,5,3>: Cost 3 vext1 <3,0,u,5>, <3,0,u,5>
+ 2568684438U, // <0,u,5,1>: Cost 3 vext1 <3,0,u,5>, <1,2,3,0>
+ 3765622902U, // <0,u,5,2>: Cost 4 vext3 <1,2,3,0>, <u,5,2,7>
+ 2691881087U, // <0,u,5,3>: Cost 3 vext3 <1,2,3,0>, <u,5,3,7>
2568686902U, // <0,u,5,4>: Cost 3 vext1 <3,0,u,5>, RHS
- 2645184516U, // <0,u,5,5>: Cost 3 vext2 <4,6,0,u>, <5,5,5,5>
+ 2650492890U, // <0,u,5,5>: Cost 3 vext2 <5,5,0,u>, <5,5,0,u>
1618139290U, // <0,u,5,6>: Cost 2 vext3 <1,2,3,0>, RHS
- 2849636508U, // <0,u,5,7>: Cost 3 vuzpr <5,1,7,3>, LHS
+ 2824834358U, // <0,u,5,7>: Cost 3 vuzpr <1,0,3,u>, RHS
1618139308U, // <0,u,5,u>: Cost 2 vext3 <1,2,3,0>, RHS
- 2691881136U, // <0,u,6,0>: Cost 3 vext3 <1,2,3,0>, <u,6,0,2>
- 2645184946U, // <0,u,6,1>: Cost 3 vext2 <4,6,0,u>, <6,1,u,3>
- 2618642938U, // <0,u,6,2>: Cost 3 vext2 <0,2,0,u>, <6,2,7,3>
- 2718718160U, // <0,u,6,3>: Cost 3 vext3 <5,6,7,0>, <u,6,3,7>
- 2718718168U, // <0,u,6,4>: Cost 3 vext3 <5,6,7,0>, <u,6,4,6>
+ 2592579686U, // <0,u,6,0>: Cost 3 vext1 <7,0,u,6>, LHS
+ 2262496983U, // <0,u,6,1>: Cost 3 vrev <u,0,1,6>
+ 2654474688U, // <0,u,6,2>: Cost 3 vext2 <6,2,0,u>, <6,2,0,u>
+ 2691881168U, // <0,u,6,3>: Cost 3 vext3 <1,2,3,0>, <u,6,3,7>
+ 2592582966U, // <0,u,6,4>: Cost 3 vext1 <7,0,u,6>, RHS
2656465587U, // <0,u,6,5>: Cost 3 vext2 <6,5,0,u>, <6,5,0,u>
- 2645185336U, // <0,u,6,6>: Cost 3 vext2 <4,6,0,u>, <6,6,6,6>
+ 2657129220U, // <0,u,6,6>: Cost 3 vext2 <6,6,0,u>, <6,6,0,u>
1584051029U, // <0,u,6,7>: Cost 2 vext2 <6,7,0,u>, <6,7,0,u>
1584714662U, // <0,u,6,u>: Cost 2 vext2 <6,u,0,u>, <6,u,0,u>
- 2645185530U, // <0,u,7,0>: Cost 3 vext2 <4,6,0,u>, <7,0,1,2>
- 2860466332U, // <0,u,7,1>: Cost 3 vuzpr <7,0,1,2>, LHS
- 2631193772U, // <0,u,7,2>: Cost 3 vext2 <2,3,0,1>, <7,2,3,0>
+ 2562728038U, // <0,u,7,0>: Cost 3 vext1 <2,0,u,7>, LHS
+ 2562728854U, // <0,u,7,1>: Cost 3 vext1 <2,0,u,7>, <1,2,3,0>
+ 2562729473U, // <0,u,7,2>: Cost 3 vext1 <2,0,u,7>, <2,0,u,7>
2661111018U, // <0,u,7,3>: Cost 3 vext2 <7,3,0,u>, <7,3,0,u>
- 2645185894U, // <0,u,7,4>: Cost 3 vext2 <4,6,0,u>, <7,4,5,6>
+ 2562731318U, // <0,u,7,4>: Cost 3 vext1 <2,0,u,7>, RHS
2718718258U, // <0,u,7,5>: Cost 3 vext3 <5,6,7,0>, <u,7,5,6>
- 2663101917U, // <0,u,7,6>: Cost 3 vext2 <7,6,0,u>, <7,6,0,u>
- 2645186156U, // <0,u,7,7>: Cost 3 vext2 <4,6,0,u>, <7,7,7,7>
- 2645186178U, // <0,u,7,u>: Cost 3 vext2 <4,6,0,u>, <7,u,1,2>
+ 2586620261U, // <0,u,7,6>: Cost 3 vext1 <6,0,u,7>, <6,0,u,7>
+ 2657793644U, // <0,u,7,7>: Cost 3 vext2 <6,7,0,u>, <7,7,7,7>
+ 2562733870U, // <0,u,7,u>: Cost 3 vext1 <2,0,u,7>, LHS
135053414U, // <0,u,u,0>: Cost 1 vdup0 LHS
1544902446U, // <0,u,u,1>: Cost 2 vext2 <0,2,0,u>, LHS
- 1618139493U, // <0,u,u,2>: Cost 2 vext3 <1,2,3,0>, LHS
+ 1679005486U, // <0,u,u,2>: Cost 2 vuzpl LHS, LHS
835584U, // <0,u,u,3>: Cost 0 copy LHS
1483025718U, // <0,u,u,4>: Cost 2 vext1 <1,0,u,u>, RHS
1544902810U, // <0,u,u,5>: Cost 2 vext2 <0,2,0,u>, RHS
- 1618139533U, // <0,u,u,6>: Cost 2 vext3 <1,2,3,0>, RHS
+ 1679005850U, // <0,u,u,6>: Cost 2 vuzpl LHS, RHS
1518859327U, // <0,u,u,7>: Cost 2 vext1 <7,0,u,u>, <7,0,u,u>
835584U, // <0,u,u,u>: Cost 0 copy LHS
- 2691072000U, // <1,0,0,0>: Cost 3 vext3 <1,1,1,1>, <0,0,0,0>
+ 2689744896U, // <1,0,0,0>: Cost 3 vext3 <0,u,1,1>, <0,0,0,0>
1610694666U, // <1,0,0,1>: Cost 2 vext3 <0,0,1,1>, <0,0,1,1>
- 2691072020U, // <1,0,0,2>: Cost 3 vext3 <1,1,1,1>, <0,0,2,2>
- 3704996101U, // <1,0,0,3>: Cost 4 vext2 <2,3,1,0>, <0,3,2,0>
- 2556775734U, // <1,0,0,4>: Cost 3 vext1 <1,1,0,0>, RHS
+ 2689744916U, // <1,0,0,2>: Cost 3 vext3 <0,u,1,1>, <0,0,2,2>
+ 2619310332U, // <1,0,0,3>: Cost 3 vext2 <0,3,1,0>, <0,3,1,0>
+ 2684657701U, // <1,0,0,4>: Cost 3 vext3 <0,0,4,1>, <0,0,4,1>
2620637598U, // <1,0,0,5>: Cost 3 vext2 <0,5,1,0>, <0,5,1,0>
- 3289440391U, // <1,0,0,6>: Cost 4 vrev <0,1,6,0>
+ 3708977654U, // <1,0,0,6>: Cost 4 vext2 <3,0,1,0>, <0,6,1,7>
3666351168U, // <1,0,0,7>: Cost 4 vext1 <7,1,0,0>, <7,1,0,0>
1611210825U, // <1,0,0,u>: Cost 2 vext3 <0,0,u,1>, <0,0,u,1>
- 2698297426U, // <1,0,1,0>: Cost 3 vext3 <2,3,0,1>, <0,1,0,1>
- 2953626420U, // <1,0,1,1>: Cost 3 vzipr LHS, <1,1,1,1>
- 1617330278U, // <1,0,1,2>: Cost 2 vext3 <1,1,1,1>, LHS
- 3898524378U, // <1,0,1,3>: Cost 4 vuzpr <1,0,3,2>, <1,0,0,1>
- 2698297466U, // <1,0,1,4>: Cost 3 vext3 <2,3,0,1>, <0,1,4,5>
+ 2556780646U, // <1,0,1,0>: Cost 3 vext1 <1,1,0,1>, LHS
+ 2556781355U, // <1,0,1,1>: Cost 3 vext1 <1,1,0,1>, <1,1,0,1>
+ 1616003174U, // <1,0,1,2>: Cost 2 vext3 <0,u,1,1>, LHS
+ 3693052888U, // <1,0,1,3>: Cost 4 vext2 <0,3,1,0>, <1,3,1,3>
+ 2556783926U, // <1,0,1,4>: Cost 3 vext1 <1,1,0,1>, RHS
2580672143U, // <1,0,1,5>: Cost 3 vext1 <5,1,0,1>, <5,1,0,1>
2724839566U, // <1,0,1,6>: Cost 3 vext3 <6,7,0,1>, <0,1,6,7>
3654415354U, // <1,0,1,7>: Cost 4 vext1 <5,1,0,1>, <7,0,1,2>
- 1617330332U, // <1,0,1,u>: Cost 2 vext3 <1,1,1,1>, LHS
- 2686279844U, // <1,0,2,0>: Cost 3 vext3 <0,2,u,1>, <0,2,0,2>
- 2953626518U, // <1,0,2,1>: Cost 3 vzipr LHS, <1,2,3,0>
- 4161585900U, // <1,0,2,2>: Cost 4 vtrnr LHS, <1,0,2,1>
- 2631255726U, // <1,0,2,3>: Cost 3 vext2 <2,3,1,0>, <2,3,1,0>
- 2556792118U, // <1,0,2,4>: Cost 3 vext1 <1,1,0,2>, RHS
- 3759800528U, // <1,0,2,5>: Cost 4 vext3 <0,2,5,1>, <0,2,5,1>
- 3630535162U, // <1,0,2,6>: Cost 4 vext1 <1,1,0,2>, <6,2,7,3>
- 2686206178U, // <1,0,2,7>: Cost 3 vext3 <0,2,7,1>, <0,2,7,1>
+ 1616003228U, // <1,0,1,u>: Cost 2 vext3 <0,u,1,1>, LHS
+ 2685690019U, // <1,0,2,0>: Cost 3 vext3 <0,2,0,1>, <0,2,0,1>
+ 2685763756U, // <1,0,2,1>: Cost 3 vext3 <0,2,1,1>, <0,2,1,1>
+ 2698297524U, // <1,0,2,2>: Cost 3 vext3 <2,3,0,1>, <0,2,2,0>
+ 2685911230U, // <1,0,2,3>: Cost 3 vext3 <0,2,3,1>, <0,2,3,1>
+ 2689745100U, // <1,0,2,4>: Cost 3 vext3 <0,u,1,1>, <0,2,4,6>
+ 3764814038U, // <1,0,2,5>: Cost 4 vext3 <1,1,1,1>, <0,2,5,7>
+ 2724839640U, // <1,0,2,6>: Cost 3 vext3 <6,7,0,1>, <0,2,6,0>
+ 2592625658U, // <1,0,2,7>: Cost 3 vext1 <7,1,0,2>, <7,0,1,2>
2686279915U, // <1,0,2,u>: Cost 3 vext3 <0,2,u,1>, <0,2,u,1>
- 2562768998U, // <1,0,3,0>: Cost 3 vext1 <2,1,0,3>, LHS
- 2562769654U, // <1,0,3,1>: Cost 3 vext1 <2,1,0,3>, <1,0,3,2>
+ 3087843328U, // <1,0,3,0>: Cost 3 vtrnr LHS, <0,0,0,0>
+ 3087843338U, // <1,0,3,1>: Cost 3 vtrnr LHS, <0,0,1,1>
67944550U, // <1,0,3,2>: Cost 1 vrev LHS
2568743135U, // <1,0,3,3>: Cost 3 vext1 <3,1,0,3>, <3,1,0,3>
2562772278U, // <1,0,3,4>: Cost 3 vext1 <2,1,0,3>, RHS
- 3636514512U, // <1,0,3,5>: Cost 4 vext1 <2,1,0,3>, <5,1,7,3>
- 3636515322U, // <1,0,3,6>: Cost 4 vext1 <2,1,0,3>, <6,2,7,3>
+ 4099850454U, // <1,0,3,5>: Cost 4 vtrnl <1,0,3,2>, <0,2,5,7>
+ 3704998538U, // <1,0,3,6>: Cost 4 vext2 <2,3,1,0>, <3,6,2,7>
2592633923U, // <1,0,3,7>: Cost 3 vext1 <7,1,0,3>, <7,1,0,3>
68386972U, // <1,0,3,u>: Cost 1 vrev LHS
2620640146U, // <1,0,4,0>: Cost 3 vext2 <0,5,1,0>, <4,0,5,1>
- 2708619602U, // <1,0,4,1>: Cost 3 vext3 <4,0,5,1>, <0,4,1,5>
- 2724839772U, // <1,0,4,2>: Cost 3 vext3 <6,7,0,1>, <0,4,2,6>
- 3642493152U, // <1,0,4,3>: Cost 4 vext1 <3,1,0,4>, <3,1,0,4>
- 3642494262U, // <1,0,4,4>: Cost 4 vext1 <3,1,0,4>, RHS
- 2631257398U, // <1,0,4,5>: Cost 3 vext2 <2,3,1,0>, RHS
- 3704999244U, // <1,0,4,6>: Cost 4 vext2 <2,3,1,0>, <4,6,0,2>
+ 2689745234U, // <1,0,4,1>: Cost 3 vext3 <0,u,1,1>, <0,4,1,5>
+ 2689745244U, // <1,0,4,2>: Cost 3 vext3 <0,u,1,1>, <0,4,2,6>
+ 3760980320U, // <1,0,4,3>: Cost 4 vext3 <0,4,3,1>, <0,4,3,1>
+ 3761054057U, // <1,0,4,4>: Cost 4 vext3 <0,4,4,1>, <0,4,4,1>
+ 2619313462U, // <1,0,4,5>: Cost 3 vext2 <0,3,1,0>, RHS
+ 3761201531U, // <1,0,4,6>: Cost 4 vext3 <0,4,6,1>, <0,4,6,1>
3666383940U, // <1,0,4,7>: Cost 4 vext1 <7,1,0,4>, <7,1,0,4>
- 2631257641U, // <1,0,4,u>: Cost 3 vext2 <2,3,1,0>, RHS
- 3782361494U, // <1,0,5,0>: Cost 4 vext3 <4,0,5,1>, <0,5,0,1>
- 2708619678U, // <1,0,5,1>: Cost 3 vext3 <4,0,5,1>, <0,5,1,0>
- 3987308882U, // <1,0,5,2>: Cost 4 vzipl <4,6,0,2>, <0,4,1,5>
- 3708981104U, // <1,0,5,3>: Cost 4 vext2 <3,0,1,0>, <5,3,7,1>
+ 2619313705U, // <1,0,4,u>: Cost 3 vext2 <0,3,1,0>, RHS
+ 4029300736U, // <1,0,5,0>: Cost 4 vzipr <0,4,1,5>, <0,0,0,0>
+ 2895249510U, // <1,0,5,1>: Cost 3 vzipl <1,5,3,7>, LHS
+ 3028287590U, // <1,0,5,2>: Cost 3 vtrnl <1,3,5,7>, LHS
+ 3642501345U, // <1,0,5,3>: Cost 4 vext1 <3,1,0,5>, <3,1,0,5>
2215592058U, // <1,0,5,4>: Cost 3 vrev <0,1,4,5>
- 3654446739U, // <1,0,5,5>: Cost 4 vext1 <5,1,0,5>, <5,1,0,5>
+ 3724242907U, // <1,0,5,5>: Cost 4 vext2 <5,5,1,0>, <5,5,1,0>
3724906540U, // <1,0,5,6>: Cost 4 vext2 <5,6,1,0>, <5,6,1,0>
- 3782361560U, // <1,0,5,7>: Cost 4 vext3 <4,0,5,1>, <0,5,7,4>
- 2708619678U, // <1,0,5,u>: Cost 3 vext3 <4,0,5,1>, <0,5,1,0>
- 3708981590U, // <1,0,6,0>: Cost 4 vext2 <3,0,1,0>, <6,0,7,1>
+ 3911118134U, // <1,0,5,7>: Cost 4 vuzpr <3,1,3,0>, RHS
+ 3028287644U, // <1,0,5,u>: Cost 3 vtrnl <1,3,5,7>, LHS
+ 3762086375U, // <1,0,6,0>: Cost 4 vext3 <0,6,0,1>, <0,6,0,1>
2698297846U, // <1,0,6,1>: Cost 3 vext3 <2,3,0,1>, <0,6,1,7>
- 3705000442U, // <1,0,6,2>: Cost 4 vext2 <2,3,1,0>, <6,2,7,3>
- 3705000522U, // <1,0,6,3>: Cost 4 vext2 <2,3,1,0>, <6,3,7,2>
- 3666398518U, // <1,0,6,4>: Cost 4 vext1 <7,1,0,6>, RHS
+ 3760022015U, // <1,0,6,2>: Cost 4 vext3 <0,2,u,1>, <0,6,2,7>
+ 3642509538U, // <1,0,6,3>: Cost 4 vext1 <3,1,0,6>, <3,1,0,6>
+ 3762381323U, // <1,0,6,4>: Cost 4 vext3 <0,6,4,1>, <0,6,4,1>
3730215604U, // <1,0,6,5>: Cost 4 vext2 <6,5,1,0>, <6,5,1,0>
- 3731542840U, // <1,0,6,6>: Cost 4 vext2 <6,7,1,0>, <6,6,6,6>
+ 3730879237U, // <1,0,6,6>: Cost 4 vext2 <6,6,1,0>, <6,6,1,0>
2657801046U, // <1,0,6,7>: Cost 3 vext2 <6,7,1,0>, <6,7,1,0>
2658464679U, // <1,0,6,u>: Cost 3 vext2 <6,u,1,0>, <6,u,1,0>
2659128312U, // <1,0,7,0>: Cost 3 vext2 <7,0,1,0>, <7,0,1,0>
- 3788481088U, // <1,0,7,1>: Cost 4 vext3 <5,0,7,1>, <0,7,1,0>
+ 4047898278U, // <1,0,7,1>: Cost 4 vzipr <3,5,1,7>, <2,3,0,1>
2215460970U, // <1,0,7,2>: Cost 3 vrev <0,1,2,7>
3734861035U, // <1,0,7,3>: Cost 4 vext2 <7,3,1,0>, <7,3,1,0>
3731543398U, // <1,0,7,4>: Cost 4 vext2 <6,7,1,0>, <7,4,5,6>
@@ -822,123 +822,123 @@ static const unsigned PerfectShuffleTable[6561+1] = {
2663110110U, // <1,0,7,6>: Cost 3 vext2 <7,6,1,0>, <7,6,1,0>
3731543660U, // <1,0,7,7>: Cost 4 vext2 <6,7,1,0>, <7,7,7,7>
2664437376U, // <1,0,7,u>: Cost 3 vext2 <7,u,1,0>, <7,u,1,0>
- 2689671817U, // <1,0,u,0>: Cost 3 vext3 <0,u,0,1>, <0,u,0,1>
+ 3087884288U, // <1,0,u,0>: Cost 3 vtrnr LHS, <0,0,0,0>
1616003730U, // <1,0,u,1>: Cost 2 vext3 <0,u,1,1>, <0,u,1,1>
67985515U, // <1,0,u,2>: Cost 1 vrev LHS
- 2568784100U, // <1,0,u,3>: Cost 3 vext1 <3,1,0,u>, <3,1,0,u>
- 2556841270U, // <1,0,u,4>: Cost 3 vext1 <1,1,0,u>, RHS
- 2631260314U, // <1,0,u,5>: Cost 3 vext2 <2,3,1,0>, RHS
+ 2689893028U, // <1,0,u,3>: Cost 3 vext3 <0,u,3,1>, <0,u,3,1>
+ 2689745586U, // <1,0,u,4>: Cost 3 vext3 <0,u,1,1>, <0,u,4,6>
+ 2619316378U, // <1,0,u,5>: Cost 3 vext2 <0,3,1,0>, RHS
2669082807U, // <1,0,u,6>: Cost 3 vext2 <u,6,1,0>, <u,6,1,0>
2592674888U, // <1,0,u,7>: Cost 3 vext1 <7,1,0,u>, <7,1,0,u>
68427937U, // <1,0,u,u>: Cost 1 vrev LHS
1543585802U, // <1,1,0,0>: Cost 2 vext2 <0,0,1,1>, <0,0,1,1>
- 1550221414U, // <1,1,0,1>: Cost 2 vext2 <1,1,1,1>, LHS
- 2819408692U, // <1,1,0,2>: Cost 3 vuzpr LHS, <1,1,1,1>
- 2690335478U, // <1,1,0,3>: Cost 3 vext3 <1,0,0,1>, <1,0,3,2>
- 2665103698U, // <1,1,0,4>: Cost 3 vext2 <u,0,1,1>, <0,4,1,5>
- 3782361863U, // <1,1,0,5>: Cost 4 vext3 <4,0,5,1>, <1,0,5,1>
- 3660452208U, // <1,1,0,6>: Cost 4 vext1 <6,1,1,0>, <6,1,1,0>
+ 1548894310U, // <1,1,0,1>: Cost 2 vext2 <0,u,1,1>, LHS
+ 2618654892U, // <1,1,0,2>: Cost 3 vext2 <0,2,1,1>, <0,2,1,1>
+ 2689745654U, // <1,1,0,3>: Cost 3 vext3 <0,u,1,1>, <1,0,3,2>
+ 2622636370U, // <1,1,0,4>: Cost 3 vext2 <0,u,1,1>, <0,4,1,5>
+ 2620645791U, // <1,1,0,5>: Cost 3 vext2 <0,5,1,1>, <0,5,1,1>
+ 3696378367U, // <1,1,0,6>: Cost 4 vext2 <0,u,1,1>, <0,6,2,7>
3666424905U, // <1,1,0,7>: Cost 4 vext1 <7,1,1,0>, <7,1,1,0>
- 1550221981U, // <1,1,0,u>: Cost 2 vext2 <1,1,1,1>, LHS
+ 1548894866U, // <1,1,0,u>: Cost 2 vext2 <0,u,1,1>, <0,u,1,1>
1483112550U, // <1,1,1,0>: Cost 2 vext1 <1,1,1,1>, LHS
202162278U, // <1,1,1,1>: Cost 1 vdup1 LHS
- 2556855912U, // <1,1,1,2>: Cost 3 vext1 <1,1,1,1>, <2,2,2,2>
- 3020735284U, // <1,1,1,3>: Cost 3 vtrnl LHS, <1,1,1,1>
+ 2622636950U, // <1,1,1,2>: Cost 3 vext2 <0,u,1,1>, <1,2,3,0>
+ 2622637016U, // <1,1,1,3>: Cost 3 vext2 <0,u,1,1>, <1,3,1,3>
1483115830U, // <1,1,1,4>: Cost 2 vext1 <1,1,1,1>, RHS
- 2556858064U, // <1,1,1,5>: Cost 3 vext1 <1,1,1,1>, <5,1,7,3>
- 2556858874U, // <1,1,1,6>: Cost 3 vext1 <1,1,1,1>, <6,2,7,3>
+ 2622637200U, // <1,1,1,5>: Cost 3 vext2 <0,u,1,1>, <1,5,3,7>
+ 2622637263U, // <1,1,1,6>: Cost 3 vext2 <0,u,1,1>, <1,6,1,7>
2592691274U, // <1,1,1,7>: Cost 3 vext1 <7,1,1,1>, <7,1,1,1>
202162278U, // <1,1,1,u>: Cost 1 vdup1 LHS
- 2598666342U, // <1,1,2,0>: Cost 3 vext1 <u,1,1,2>, LHS
- 2691072903U, // <1,1,2,1>: Cost 3 vext3 <1,1,1,1>, <1,2,1,3>
- 2623964776U, // <1,1,2,2>: Cost 3 vext2 <1,1,1,1>, <2,2,2,2>
- 2690483094U, // <1,1,2,3>: Cost 3 vext3 <1,0,2,1>, <1,2,3,0>
- 2598669622U, // <1,1,2,4>: Cost 3 vext1 <u,1,1,2>, RHS
- 3654495897U, // <1,1,2,5>: Cost 4 vext1 <5,1,1,2>, <5,1,1,2>
- 2665105338U, // <1,1,2,6>: Cost 3 vext2 <u,0,1,1>, <2,6,3,7>
- 3801088954U, // <1,1,2,7>: Cost 4 vext3 <7,1,7,1>, <1,2,7,0>
- 2623965243U, // <1,1,2,u>: Cost 3 vext2 <1,1,1,1>, <2,u,0,1>
- 2623965334U, // <1,1,3,0>: Cost 3 vext2 <1,1,1,1>, <3,0,1,2>
- 2623965414U, // <1,1,3,1>: Cost 3 vext2 <1,1,1,1>, <3,1,1,1>
- 4166878102U, // <1,1,3,2>: Cost 4 vtrnr <1,0,2,1>, <1,2,3,0>
- 1946992742U, // <1,1,3,3>: Cost 2 vtrnl LHS, LHS
- 2623965698U, // <1,1,3,4>: Cost 3 vext2 <1,1,1,1>, <3,4,5,6>
- 3697707554U, // <1,1,3,5>: Cost 4 vext2 <1,1,1,1>, <3,5,0,2>
- 3697707658U, // <1,1,3,6>: Cost 4 vext2 <1,1,1,1>, <3,6,2,7>
+ 2550890588U, // <1,1,2,0>: Cost 3 vext1 <0,1,1,2>, <0,1,1,2>
+ 2617329183U, // <1,1,2,1>: Cost 3 vext2 <0,0,1,1>, <2,1,3,1>
+ 2622637672U, // <1,1,2,2>: Cost 3 vext2 <0,u,1,1>, <2,2,2,2>
+ 2622637734U, // <1,1,2,3>: Cost 3 vext2 <0,u,1,1>, <2,3,0,1>
+ 2550893878U, // <1,1,2,4>: Cost 3 vext1 <0,1,1,2>, RHS
+ 3696379744U, // <1,1,2,5>: Cost 4 vext2 <0,u,1,1>, <2,5,2,7>
+ 2622638010U, // <1,1,2,6>: Cost 3 vext2 <0,u,1,1>, <2,6,3,7>
+ 3804554170U, // <1,1,2,7>: Cost 4 vext3 <7,7,0,1>, <1,2,7,0>
+ 2622638139U, // <1,1,2,u>: Cost 3 vext2 <0,u,1,1>, <2,u,0,1>
+ 2622638230U, // <1,1,3,0>: Cost 3 vext2 <0,u,1,1>, <3,0,1,2>
+ 3087844148U, // <1,1,3,1>: Cost 3 vtrnr LHS, <1,1,1,1>
+ 4161585244U, // <1,1,3,2>: Cost 4 vtrnr LHS, <0,1,1,2>
+ 2014101606U, // <1,1,3,3>: Cost 2 vtrnr LHS, LHS
+ 2622638594U, // <1,1,3,4>: Cost 3 vext2 <0,u,1,1>, <3,4,5,6>
+ 2689745920U, // <1,1,3,5>: Cost 3 vext3 <0,u,1,1>, <1,3,5,7>
+ 3763487753U, // <1,1,3,6>: Cost 4 vext3 <0,u,1,1>, <1,3,6,7>
2592707660U, // <1,1,3,7>: Cost 3 vext1 <7,1,1,3>, <7,1,1,3>
- 1947033702U, // <1,1,3,u>: Cost 2 vtrnl LHS, LHS
- 2623966098U, // <1,1,4,0>: Cost 3 vext2 <1,1,1,1>, <4,0,5,1>
+ 2014101611U, // <1,1,3,u>: Cost 2 vtrnr LHS, LHS
+ 2556878950U, // <1,1,4,0>: Cost 3 vext1 <1,1,1,4>, LHS
2221335351U, // <1,1,4,1>: Cost 3 vrev <1,1,1,4>
- 3697708086U, // <1,1,4,2>: Cost 4 vext2 <1,1,1,1>, <4,2,5,3>
- 3630622870U, // <1,1,4,3>: Cost 4 vext1 <1,1,1,4>, <3,0,1,2>
+ 3696380988U, // <1,1,4,2>: Cost 4 vext2 <0,u,1,1>, <4,2,6,0>
+ 3763487805U, // <1,1,4,3>: Cost 4 vext3 <0,u,1,1>, <1,4,3,5>
2556882230U, // <1,1,4,4>: Cost 3 vext1 <1,1,1,4>, RHS
- 1550224694U, // <1,1,4,5>: Cost 2 vext2 <1,1,1,1>, RHS
- 2623966540U, // <1,1,4,6>: Cost 3 vext2 <1,1,1,1>, <4,6,0,2>
+ 1548897590U, // <1,1,4,5>: Cost 2 vext2 <0,u,1,1>, RHS
+ 2758184246U, // <1,1,4,6>: Cost 3 vuzpl <1,1,1,1>, RHS
3666457677U, // <1,1,4,7>: Cost 4 vext1 <7,1,1,4>, <7,1,1,4>
- 1550224937U, // <1,1,4,u>: Cost 2 vext2 <1,1,1,1>, RHS
- 2647191111U, // <1,1,5,0>: Cost 3 vext2 <5,0,1,1>, <5,0,1,1>
- 2623966928U, // <1,1,5,1>: Cost 3 vext2 <1,1,1,1>, <5,1,7,3>
- 3697708779U, // <1,1,5,2>: Cost 4 vext2 <1,1,1,1>, <5,2,1,3>
- 2724840592U, // <1,1,5,3>: Cost 3 vext3 <6,7,0,1>, <1,5,3,7>
+ 1548897833U, // <1,1,4,u>: Cost 2 vext2 <0,u,1,1>, RHS
+ 2693653615U, // <1,1,5,0>: Cost 3 vext3 <1,5,0,1>, <1,5,0,1>
+ 2617331408U, // <1,1,5,1>: Cost 3 vext2 <0,0,1,1>, <5,1,7,3>
+ 4029302934U, // <1,1,5,2>: Cost 4 vzipr <0,4,1,5>, <3,0,1,2>
+ 2689746064U, // <1,1,5,3>: Cost 3 vext3 <0,u,1,1>, <1,5,3,7>
2221564755U, // <1,1,5,4>: Cost 3 vrev <1,1,4,5>
- 2650509276U, // <1,1,5,5>: Cost 3 vext2 <5,5,1,1>, <5,5,1,1>
- 2665107554U, // <1,1,5,6>: Cost 3 vext2 <u,0,1,1>, <5,6,7,0>
- 3697709174U, // <1,1,5,7>: Cost 4 vext2 <1,1,1,1>, <5,7,0,2>
- 2623967495U, // <1,1,5,u>: Cost 3 vext2 <1,1,1,1>, <5,u,7,3>
- 3697709353U, // <1,1,6,0>: Cost 4 vext2 <1,1,1,1>, <6,0,2,1>
- 2684437711U, // <1,1,6,1>: Cost 3 vext3 <0,0,1,1>, <1,6,1,7>
- 2623967738U, // <1,1,6,2>: Cost 3 vext2 <1,1,1,1>, <6,2,7,3>
- 3697709642U, // <1,1,6,3>: Cost 4 vext2 <1,1,1,1>, <6,3,7,2>
- 3630640438U, // <1,1,6,4>: Cost 4 vext1 <1,1,1,6>, RHS
- 3724251883U, // <1,1,6,5>: Cost 4 vext2 <5,5,1,1>, <6,5,7,1>
- 2665108280U, // <1,1,6,6>: Cost 3 vext2 <u,0,1,1>, <6,6,6,6>
+ 2955559250U, // <1,1,5,5>: Cost 3 vzipr <0,4,1,5>, <0,4,1,5>
+ 2617331810U, // <1,1,5,6>: Cost 3 vext2 <0,0,1,1>, <5,6,7,0>
+ 2825293110U, // <1,1,5,7>: Cost 3 vuzpr <1,1,1,1>, RHS
+ 2689746109U, // <1,1,5,u>: Cost 3 vext3 <0,u,1,1>, <1,5,u,7>
+ 3696382241U, // <1,1,6,0>: Cost 4 vext2 <0,u,1,1>, <6,0,1,2>
+ 2689746127U, // <1,1,6,1>: Cost 3 vext3 <0,u,1,1>, <1,6,1,7>
+ 2617332218U, // <1,1,6,2>: Cost 3 vext2 <0,0,1,1>, <6,2,7,3>
+ 3763487969U, // <1,1,6,3>: Cost 4 vext3 <0,u,1,1>, <1,6,3,7>
+ 3696382605U, // <1,1,6,4>: Cost 4 vext2 <0,u,1,1>, <6,4,5,6>
+ 4029309266U, // <1,1,6,5>: Cost 4 vzipr <0,4,1,6>, <0,4,1,5>
+ 2617332536U, // <1,1,6,6>: Cost 3 vext2 <0,0,1,1>, <6,6,6,6>
2724840702U, // <1,1,6,7>: Cost 3 vext3 <6,7,0,1>, <1,6,7,0>
- 2623968224U, // <1,1,6,u>: Cost 3 vext2 <1,1,1,1>, <6,u,7,3>
- 2665108474U, // <1,1,7,0>: Cost 3 vext2 <u,0,1,1>, <7,0,1,2>
+ 2725504263U, // <1,1,6,u>: Cost 3 vext3 <6,u,0,1>, <1,6,u,0>
+ 2617332720U, // <1,1,7,0>: Cost 3 vext2 <0,0,1,1>, <7,0,0,1>
2659800138U, // <1,1,7,1>: Cost 3 vext2 <7,1,1,1>, <7,1,1,1>
- 3697710255U, // <1,1,7,2>: Cost 4 vext2 <1,1,1,1>, <7,2,3,3>
- 3798582571U, // <1,1,7,3>: Cost 4 vext3 <6,7,0,1>, <1,7,3,0>
- 2665108838U, // <1,1,7,4>: Cost 3 vext2 <u,0,1,1>, <7,4,5,6>
- 3720934789U, // <1,1,7,5>: Cost 4 vext2 <5,0,1,1>, <7,5,0,1>
+ 3691074717U, // <1,1,7,2>: Cost 4 vext2 <0,0,1,1>, <7,2,1,3>
+ 4167811174U, // <1,1,7,3>: Cost 4 vtrnr <1,1,5,7>, LHS
+ 2617333094U, // <1,1,7,4>: Cost 3 vext2 <0,0,1,1>, <7,4,5,6>
+ 3295396702U, // <1,1,7,5>: Cost 4 vrev <1,1,5,7>
3803891014U, // <1,1,7,6>: Cost 4 vext3 <7,6,0,1>, <1,7,6,0>
- 2665109100U, // <1,1,7,7>: Cost 3 vext2 <u,0,1,1>, <7,7,7,7>
- 2665109112U, // <1,1,7,u>: Cost 3 vext2 <u,0,1,1>, <7,u,0,1>
- 1591367378U, // <1,1,u,0>: Cost 2 vext2 <u,0,1,1>, <u,0,1,1>
+ 2617333356U, // <1,1,7,7>: Cost 3 vext2 <0,0,1,1>, <7,7,7,7>
+ 2659800138U, // <1,1,7,u>: Cost 3 vext2 <7,1,1,1>, <7,1,1,1>
+ 1483112550U, // <1,1,u,0>: Cost 2 vext1 <1,1,1,1>, LHS
202162278U, // <1,1,u,1>: Cost 1 vdup1 LHS
- 2623969132U, // <1,1,u,2>: Cost 3 vext2 <1,1,1,1>, <u,2,0,2>
- 1946992747U, // <1,1,u,3>: Cost 2 vtrnl LHS, LHS
+ 2622642056U, // <1,1,u,2>: Cost 3 vext2 <0,u,1,1>, <u,2,3,3>
+ 2014142566U, // <1,1,u,3>: Cost 2 vtrnr LHS, LHS
1483115830U, // <1,1,u,4>: Cost 2 vext1 <1,1,1,1>, RHS
- 1550227610U, // <1,1,u,5>: Cost 2 vext2 <1,1,1,1>, RHS
- 2623969456U, // <1,1,u,6>: Cost 3 vext2 <1,1,1,1>, <u,6,0,2>
- 2592748625U, // <1,1,u,7>: Cost 3 vext1 <7,1,1,u>, <7,1,1,u>
+ 1548900506U, // <1,1,u,5>: Cost 2 vext2 <0,u,1,1>, RHS
+ 2622642384U, // <1,1,u,6>: Cost 3 vext2 <0,u,1,1>, <u,6,3,7>
+ 2825293353U, // <1,1,u,7>: Cost 3 vuzpr <1,1,1,1>, RHS
202162278U, // <1,1,u,u>: Cost 1 vdup1 LHS
- 2698298804U, // <1,2,0,0>: Cost 3 vext3 <2,3,0,1>, <2,0,0,2>
+ 2635251712U, // <1,2,0,0>: Cost 3 vext2 <3,0,1,2>, <0,0,0,0>
1561509990U, // <1,2,0,1>: Cost 2 vext2 <3,0,1,2>, LHS
- 2629279908U, // <1,2,0,2>: Cost 3 vext2 <2,0,1,2>, <0,2,0,2>
+ 2618663085U, // <1,2,0,2>: Cost 3 vext2 <0,2,1,2>, <0,2,1,2>
2696529358U, // <1,2,0,3>: Cost 3 vext3 <2,0,3,1>, <2,0,3,1>
- 2659139922U, // <1,2,0,4>: Cost 3 vext2 <7,0,1,2>, <0,4,1,5>
- 3775727073U, // <1,2,0,5>: Cost 4 vext3 <2,u,5,1>, <2,0,5,2>
+ 2635252050U, // <1,2,0,4>: Cost 3 vext2 <3,0,1,2>, <0,4,1,5>
+ 3769533926U, // <1,2,0,5>: Cost 4 vext3 <1,u,2,1>, <2,0,5,7>
2621317617U, // <1,2,0,6>: Cost 3 vext2 <0,6,1,2>, <0,6,1,2>
2659140170U, // <1,2,0,7>: Cost 3 vext2 <7,0,1,2>, <0,7,2,1>
1561510557U, // <1,2,0,u>: Cost 2 vext2 <3,0,1,2>, LHS
2623308516U, // <1,2,1,0>: Cost 3 vext2 <1,0,1,2>, <1,0,1,2>
- 2623308596U, // <1,2,1,1>: Cost 3 vext2 <1,0,1,2>, <1,1,1,1>
+ 2635252532U, // <1,2,1,1>: Cost 3 vext2 <3,0,1,2>, <1,1,1,1>
2631271318U, // <1,2,1,2>: Cost 3 vext2 <2,3,1,2>, <1,2,3,0>
- 2886517556U, // <1,2,1,3>: Cost 3 vzipl LHS, <1,1,1,1>
- 3764225580U, // <1,2,1,4>: Cost 4 vext3 <1,0,2,1>, <2,1,4,5>
- 2659140752U, // <1,2,1,5>: Cost 3 vext2 <7,0,1,2>, <1,5,3,7>
- 3794085433U, // <1,2,1,6>: Cost 4 vext3 <6,0,2,1>, <2,1,6,0>
+ 2958180454U, // <1,2,1,3>: Cost 3 vzipr <0,u,1,1>, LHS
+ 2550959414U, // <1,2,1,4>: Cost 3 vext1 <0,1,2,1>, RHS
+ 2635252880U, // <1,2,1,5>: Cost 3 vext2 <3,0,1,2>, <1,5,3,7>
+ 2635252952U, // <1,2,1,6>: Cost 3 vext2 <3,0,1,2>, <1,6,2,7>
3732882731U, // <1,2,1,7>: Cost 4 vext2 <7,0,1,2>, <1,7,3,0>
- 2886557706U, // <1,2,1,u>: Cost 3 vzipl LHS, <0,0,1,1>
+ 2958180459U, // <1,2,1,u>: Cost 3 vzipr <0,u,1,1>, LHS
2629281213U, // <1,2,2,0>: Cost 3 vext2 <2,0,1,2>, <2,0,1,2>
- 3630678846U, // <1,2,2,1>: Cost 4 vext1 <1,1,2,2>, <1,1,2,2>
- 2691073640U, // <1,2,2,2>: Cost 3 vext3 <1,1,1,1>, <2,2,2,2>
- 2886518934U, // <1,2,2,3>: Cost 3 vzipl LHS, <3,0,1,2>
- 3630681398U, // <1,2,2,4>: Cost 4 vext1 <1,1,2,2>, RHS
- 3771745922U, // <1,2,2,5>: Cost 4 vext3 <2,2,5,1>, <2,2,5,1>
- 2659141562U, // <1,2,2,6>: Cost 3 vext2 <7,0,1,2>, <2,6,3,7>
+ 2635253280U, // <1,2,2,1>: Cost 3 vext2 <3,0,1,2>, <2,1,3,2>
+ 2618664552U, // <1,2,2,2>: Cost 3 vext2 <0,2,1,2>, <2,2,2,2>
+ 2689746546U, // <1,2,2,3>: Cost 3 vext3 <0,u,1,1>, <2,2,3,3>
+ 3764815485U, // <1,2,2,4>: Cost 4 vext3 <1,1,1,1>, <2,2,4,5>
+ 3760023176U, // <1,2,2,5>: Cost 4 vext3 <0,2,u,1>, <2,2,5,7>
+ 2635253690U, // <1,2,2,6>: Cost 3 vext2 <3,0,1,2>, <2,6,3,7>
2659141610U, // <1,2,2,7>: Cost 3 vext2 <7,0,1,2>, <2,7,0,1>
- 2886559894U, // <1,2,2,u>: Cost 3 vzipl LHS, <3,0,1,2>
+ 2689746591U, // <1,2,2,u>: Cost 3 vext3 <0,u,1,1>, <2,2,u,3>
403488870U, // <1,2,3,0>: Cost 1 vext1 LHS, LHS
1477231350U, // <1,2,3,1>: Cost 2 vext1 LHS, <1,0,3,2>
1477232232U, // <1,2,3,2>: Cost 2 vext1 LHS, <2,2,2,2>
@@ -948,40 +948,40 @@ static const unsigned PerfectShuffleTable[6561+1] = {
1525010938U, // <1,2,3,6>: Cost 2 vext1 LHS, <6,2,7,3>
1525011450U, // <1,2,3,7>: Cost 2 vext1 LHS, <7,0,1,2>
403494702U, // <1,2,3,u>: Cost 1 vext1 LHS, LHS
- 2635254674U, // <1,2,4,0>: Cost 3 vext2 <3,0,1,2>, <4,0,5,1>
- 3702361059U, // <1,2,4,1>: Cost 4 vext2 <1,u,1,2>, <4,1,5,1>
- 3772630796U, // <1,2,4,2>: Cost 4 vext3 <2,3,u,1>, <2,4,2,4>
+ 2641226607U, // <1,2,4,0>: Cost 3 vext2 <4,0,1,2>, <4,0,1,2>
+ 3624723446U, // <1,2,4,1>: Cost 4 vext1 <0,1,2,4>, <1,3,4,6>
+ 3301123609U, // <1,2,4,2>: Cost 4 vrev <2,1,2,4>
2598759198U, // <1,2,4,3>: Cost 3 vext1 <u,1,2,4>, <3,u,1,2>
2659142864U, // <1,2,4,4>: Cost 3 vext2 <7,0,1,2>, <4,4,4,4>
1561513270U, // <1,2,4,5>: Cost 2 vext2 <3,0,1,2>, RHS
- 2635255116U, // <1,2,4,6>: Cost 3 vext2 <3,0,1,2>, <4,6,0,2>
- 3732884945U, // <1,2,4,7>: Cost 4 vext2 <7,0,1,2>, <4,7,6,0>
+ 2659143028U, // <1,2,4,6>: Cost 3 vext2 <7,0,1,2>, <4,6,4,6>
+ 2659143112U, // <1,2,4,7>: Cost 3 vext2 <7,0,1,2>, <4,7,5,0>
1561513513U, // <1,2,4,u>: Cost 2 vext2 <3,0,1,2>, RHS
- 2647199304U, // <1,2,5,0>: Cost 3 vext2 <5,0,1,2>, <5,0,1,2>
- 2635255504U, // <1,2,5,1>: Cost 3 vext2 <3,0,1,2>, <5,1,7,3>
- 3703025440U, // <1,2,5,2>: Cost 4 vext2 <2,0,1,2>, <5,2,7,2>
- 2934292818U, // <1,2,5,3>: Cost 3 vzipl LHS, <0,4,1,5>
- 2659143622U, // <1,2,5,4>: Cost 3 vext2 <7,0,1,2>, <5,4,7,6>
+ 2550988902U, // <1,2,5,0>: Cost 3 vext1 <0,1,2,5>, LHS
+ 2550989824U, // <1,2,5,1>: Cost 3 vext1 <0,1,2,5>, <1,3,5,7>
+ 3624732264U, // <1,2,5,2>: Cost 4 vext1 <0,1,2,5>, <2,2,2,2>
+ 2955559014U, // <1,2,5,3>: Cost 3 vzipr <0,4,1,5>, LHS
+ 2550992182U, // <1,2,5,4>: Cost 3 vext1 <0,1,2,5>, RHS
2659143684U, // <1,2,5,5>: Cost 3 vext2 <7,0,1,2>, <5,5,5,5>
2659143778U, // <1,2,5,6>: Cost 3 vext2 <7,0,1,2>, <5,6,7,0>
- 3708997750U, // <1,2,5,7>: Cost 4 vext2 <3,0,1,2>, <5,7,0,2>
- 2635256071U, // <1,2,5,u>: Cost 3 vext2 <3,0,1,2>, <5,u,7,3>
- 2653172001U, // <1,2,6,0>: Cost 3 vext2 <6,0,1,2>, <6,0,1,2>
+ 2659143848U, // <1,2,5,7>: Cost 3 vext2 <7,0,1,2>, <5,7,5,7>
+ 2550994734U, // <1,2,5,u>: Cost 3 vext1 <0,1,2,5>, LHS
+ 2700289945U, // <1,2,6,0>: Cost 3 vext3 <2,6,0,1>, <2,6,0,1>
2635256232U, // <1,2,6,1>: Cost 3 vext2 <3,0,1,2>, <6,1,7,2>
- 2635256314U, // <1,2,6,2>: Cost 3 vext2 <3,0,1,2>, <6,2,7,3>
- 2724841402U, // <1,2,6,3>: Cost 3 vext3 <6,7,0,1>, <2,6,3,7>
- 3708998302U, // <1,2,6,4>: Cost 4 vext2 <3,0,1,2>, <6,4,7,5>
- 3714306800U, // <1,2,6,5>: Cost 4 vext2 <3,u,1,2>, <6,5,7,6>
+ 2659144186U, // <1,2,6,2>: Cost 3 vext2 <7,0,1,2>, <6,2,7,3>
+ 2689746874U, // <1,2,6,3>: Cost 3 vext3 <0,u,1,1>, <2,6,3,7>
+ 3763488705U, // <1,2,6,4>: Cost 4 vext3 <0,u,1,1>, <2,6,4,5>
+ 3763488716U, // <1,2,6,5>: Cost 4 vext3 <0,u,1,1>, <2,6,5,7>
2659144504U, // <1,2,6,6>: Cost 3 vext2 <7,0,1,2>, <6,6,6,6>
2657817432U, // <1,2,6,7>: Cost 3 vext2 <6,7,1,2>, <6,7,1,2>
- 2635256800U, // <1,2,6,u>: Cost 3 vext2 <3,0,1,2>, <6,u,7,3>
+ 2689746919U, // <1,2,6,u>: Cost 3 vext3 <0,u,1,1>, <2,6,u,7>
1585402874U, // <1,2,7,0>: Cost 2 vext2 <7,0,1,2>, <7,0,1,2>
- 2659144810U, // <1,2,7,1>: Cost 3 vext2 <7,0,1,2>, <7,1,4,6>
- 3708998831U, // <1,2,7,2>: Cost 4 vext2 <3,0,1,2>, <7,2,3,3>
+ 2659144770U, // <1,2,7,1>: Cost 3 vext2 <7,0,1,2>, <7,1,0,2>
+ 3708998858U, // <1,2,7,2>: Cost 4 vext2 <3,0,1,2>, <7,2,6,3>
2635257059U, // <1,2,7,3>: Cost 3 vext2 <3,0,1,2>, <7,3,0,1>
2659145062U, // <1,2,7,4>: Cost 3 vext2 <7,0,1,2>, <7,4,5,6>
- 3726251469U, // <1,2,7,5>: Cost 4 vext2 <5,u,1,2>, <7,5,u,1>
- 3731559912U, // <1,2,7,6>: Cost 4 vext2 <6,7,1,2>, <7,6,2,1>
+ 3732886916U, // <1,2,7,5>: Cost 4 vext2 <7,0,1,2>, <7,5,0,0>
+ 3732886998U, // <1,2,7,6>: Cost 4 vext2 <7,0,1,2>, <7,6,0,1>
2659145255U, // <1,2,7,7>: Cost 3 vext2 <7,0,1,2>, <7,7,0,1>
1590711938U, // <1,2,7,u>: Cost 2 vext2 <7,u,1,2>, <7,u,1,2>
403529835U, // <1,2,u,0>: Cost 1 vext1 LHS, LHS
@@ -989,483 +989,483 @@ static const unsigned PerfectShuffleTable[6561+1] = {
1477273192U, // <1,2,u,2>: Cost 2 vext1 LHS, <2,2,2,2>
1477273750U, // <1,2,u,3>: Cost 2 vext1 LHS, <3,0,1,2>
403533110U, // <1,2,u,4>: Cost 1 vext1 LHS, RHS
- 1477275344U, // <1,2,u,5>: Cost 2 vext1 LHS, <5,1,7,3>
- 1477276154U, // <1,2,u,6>: Cost 2 vext1 LHS, <6,2,7,3>
+ 1561516186U, // <1,2,u,5>: Cost 2 vext2 <3,0,1,2>, RHS
+ 1525051898U, // <1,2,u,6>: Cost 2 vext1 LHS, <6,2,7,3>
1525052410U, // <1,2,u,7>: Cost 2 vext1 LHS, <7,0,1,2>
403535662U, // <1,2,u,u>: Cost 1 vext1 LHS, LHS
- 2628624394U, // <1,3,0,0>: Cost 3 vext2 <1,u,1,3>, <0,0,1,1>
- 2618671206U, // <1,3,0,1>: Cost 3 vext2 <0,2,1,3>, LHS
+ 2819407872U, // <1,3,0,0>: Cost 3 vuzpr LHS, <0,0,0,0>
+ 1551564902U, // <1,3,0,1>: Cost 2 vext2 <1,3,1,3>, LHS
2819408630U, // <1,3,0,2>: Cost 3 vuzpr LHS, <1,0,3,2>
- 2702502055U, // <1,3,0,3>: Cost 3 vext3 <3,0,3,1>, <3,0,3,1>
- 2702575792U, // <1,3,0,4>: Cost 3 vext3 <3,0,4,1>, <3,0,4,1>
- 3764816058U, // <1,3,0,5>: Cost 4 vext3 <1,1,1,1>, <3,0,5,2>
- 3776465090U, // <1,3,0,6>: Cost 4 vext3 <3,0,6,1>, <3,0,6,1>
- 3666572379U, // <1,3,0,7>: Cost 4 vext1 <7,1,3,0>, <7,1,3,0>
- 2819850998U, // <1,3,0,u>: Cost 3 vuzpr LHS, <1,0,3,2>
- 2625307382U, // <1,3,1,0>: Cost 3 vext2 <1,3,1,3>, <1,0,3,2>
- 2691074278U, // <1,3,1,1>: Cost 3 vext3 <1,1,1,1>, <3,1,1,1>
+ 2619334911U, // <1,3,0,3>: Cost 3 vext2 <0,3,1,3>, <0,3,1,3>
+ 2625306962U, // <1,3,0,4>: Cost 3 vext2 <1,3,1,3>, <0,4,1,5>
+ 3832725879U, // <1,3,0,5>: Cost 4 vuzpl <1,2,3,0>, <0,4,5,6>
+ 3699048959U, // <1,3,0,6>: Cost 4 vext2 <1,3,1,3>, <0,6,2,7>
+ 3776538827U, // <1,3,0,7>: Cost 4 vext3 <3,0,7,1>, <3,0,7,1>
+ 1551565469U, // <1,3,0,u>: Cost 2 vext2 <1,3,1,3>, LHS
+ 2618671862U, // <1,3,1,0>: Cost 3 vext2 <0,2,1,3>, <1,0,3,2>
+ 2819408692U, // <1,3,1,1>: Cost 3 vuzpr LHS, <1,1,1,1>
2624643975U, // <1,3,1,2>: Cost 3 vext2 <1,2,1,3>, <1,2,1,3>
- 2824782582U, // <1,3,1,3>: Cost 3 vuzpr <1,0,3,2>, <1,0,3,2>
- 2562977078U, // <1,3,1,4>: Cost 3 vext1 <2,1,3,1>, RHS
- 3764816140U, // <1,3,1,5>: Cost 4 vext3 <1,1,1,1>, <3,1,5,3>
- 3636720039U, // <1,3,1,6>: Cost 4 vext1 <2,1,3,1>, <6,1,7,1>
- 3666580572U, // <1,3,1,7>: Cost 4 vext1 <7,1,3,1>, <7,1,3,1>
- 2628625773U, // <1,3,1,u>: Cost 3 vext2 <1,u,1,3>, <1,u,1,3>
- 2703608110U, // <1,3,2,0>: Cost 3 vext3 <3,2,0,1>, <3,2,0,1>
- 2698889534U, // <1,3,2,1>: Cost 3 vext3 <2,3,u,1>, <3,2,1,u>
- 3692414568U, // <1,3,2,2>: Cost 4 vext2 <0,2,1,3>, <2,2,2,2>
- 2618672806U, // <1,3,2,3>: Cost 3 vext2 <0,2,1,3>, <2,3,0,1>
- 3764816212U, // <1,3,2,4>: Cost 4 vext3 <1,1,1,1>, <3,2,4,3>
- 3772631390U, // <1,3,2,5>: Cost 4 vext3 <2,3,u,1>, <3,2,5,4>
- 3718956986U, // <1,3,2,6>: Cost 4 vext2 <4,6,1,3>, <2,6,3,7>
- 3666588765U, // <1,3,2,7>: Cost 4 vext1 <7,1,3,2>, <7,1,3,2>
- 2701617525U, // <1,3,2,u>: Cost 3 vext3 <2,u,0,1>, <3,2,u,0>
+ 1745666150U, // <1,3,1,3>: Cost 2 vuzpr LHS, LHS
+ 2557005110U, // <1,3,1,4>: Cost 3 vext1 <1,1,3,1>, RHS
+ 2625307792U, // <1,3,1,5>: Cost 3 vext2 <1,3,1,3>, <1,5,3,7>
+ 3698386127U, // <1,3,1,6>: Cost 4 vext2 <1,2,1,3>, <1,6,1,7>
+ 2592838748U, // <1,3,1,7>: Cost 3 vext1 <7,1,3,1>, <7,1,3,1>
+ 1745666155U, // <1,3,1,u>: Cost 2 vuzpr LHS, LHS
+ 2819408790U, // <1,3,2,0>: Cost 3 vuzpr LHS, <1,2,3,0>
+ 2625308193U, // <1,3,2,1>: Cost 3 vext2 <1,3,1,3>, <2,1,3,3>
+ 2819408036U, // <1,3,2,2>: Cost 3 vuzpr LHS, <0,2,0,2>
+ 2819851890U, // <1,3,2,3>: Cost 3 vuzpr LHS, <2,2,3,3>
+ 2819408794U, // <1,3,2,4>: Cost 3 vuzpr LHS, <1,2,3,4>
+ 3893149890U, // <1,3,2,5>: Cost 4 vuzpr LHS, <0,2,3,5>
+ 2819408076U, // <1,3,2,6>: Cost 3 vuzpr LHS, <0,2,4,6>
+ 3772041583U, // <1,3,2,7>: Cost 4 vext3 <2,3,0,1>, <3,2,7,3>
+ 2819408042U, // <1,3,2,u>: Cost 3 vuzpr LHS, <0,2,0,u>
1483276390U, // <1,3,3,0>: Cost 2 vext1 <1,1,3,3>, LHS
1483277128U, // <1,3,3,1>: Cost 2 vext1 <1,1,3,3>, <1,1,3,3>
2557019752U, // <1,3,3,2>: Cost 3 vext1 <1,1,3,3>, <2,2,2,2>
- 2691074460U, // <1,3,3,3>: Cost 3 vext3 <1,1,1,1>, <3,3,3,3>
+ 2819408856U, // <1,3,3,3>: Cost 3 vuzpr LHS, <1,3,1,3>
1483279670U, // <1,3,3,4>: Cost 2 vext1 <1,1,3,3>, RHS
- 2557021904U, // <1,3,3,5>: Cost 3 vext1 <1,1,3,3>, <5,1,7,3>
- 2557022714U, // <1,3,3,6>: Cost 3 vext1 <1,1,3,3>, <6,2,7,3>
- 2598827002U, // <1,3,3,7>: Cost 3 vext1 <u,1,3,3>, <7,0,1,2>
+ 2819409614U, // <1,3,3,5>: Cost 3 vuzpr LHS, <2,3,4,5>
+ 2598826490U, // <1,3,3,6>: Cost 3 vext1 <u,1,3,3>, <6,2,7,3>
+ 3087844352U, // <1,3,3,7>: Cost 3 vtrnr LHS, <1,3,5,7>
1483282222U, // <1,3,3,u>: Cost 2 vext1 <1,1,3,3>, LHS
- 2704935376U, // <1,3,4,0>: Cost 3 vext3 <3,4,0,1>, <3,4,0,1>
- 3697724387U, // <1,3,4,1>: Cost 4 vext2 <1,1,1,3>, <4,1,5,1>
- 3636741666U, // <1,3,4,2>: Cost 4 vext1 <2,1,3,4>, <2,1,3,4>
- 3630770690U, // <1,3,4,3>: Cost 4 vext1 <1,1,3,4>, <3,4,5,6>
- 3630771510U, // <1,3,4,4>: Cost 4 vext1 <1,1,3,4>, RHS
- 2618674486U, // <1,3,4,5>: Cost 3 vext2 <0,2,1,3>, RHS
- 2846278390U, // <1,3,4,6>: Cost 3 vuzpr RHS, <1,0,3,2>
+ 2568970342U, // <1,3,4,0>: Cost 3 vext1 <3,1,3,4>, LHS
+ 2568971224U, // <1,3,4,1>: Cost 3 vext1 <3,1,3,4>, <1,3,1,3>
+ 3832761290U, // <1,3,4,2>: Cost 4 vuzpl <1,2,3,4>, <4,1,2,3>
+ 2233428219U, // <1,3,4,3>: Cost 3 vrev <3,1,3,4>
+ 2568973622U, // <1,3,4,4>: Cost 3 vext1 <3,1,3,4>, RHS
+ 1551568182U, // <1,3,4,5>: Cost 2 vext2 <1,3,1,3>, RHS
+ 2819410434U, // <1,3,4,6>: Cost 3 vuzpr LHS, <3,4,5,6>
3666605151U, // <1,3,4,7>: Cost 4 vext1 <7,1,3,4>, <7,1,3,4>
- 2618674729U, // <1,3,4,u>: Cost 3 vext2 <0,2,1,3>, RHS
- 3764816418U, // <1,3,5,0>: Cost 4 vext3 <1,1,1,1>, <3,5,0,2>
- 3692416720U, // <1,3,5,1>: Cost 4 vext2 <0,2,1,3>, <5,1,7,3>
- 2648534763U, // <1,3,5,2>: Cost 3 vext2 <5,2,1,3>, <5,2,1,3>
- 3782363712U, // <1,3,5,3>: Cost 4 vext3 <4,0,5,1>, <3,5,3,5>
- 3307251973U, // <1,3,5,4>: Cost 4 vrev <3,1,4,5>
- 3779709518U, // <1,3,5,5>: Cost 4 vext3 <3,5,5,1>, <3,5,5,1>
- 3718959202U, // <1,3,5,6>: Cost 4 vext2 <4,6,1,3>, <5,6,7,0>
- 3923378934U, // <1,3,5,7>: Cost 4 vuzpr <5,1,7,3>, <1,0,3,2>
- 2652516561U, // <1,3,5,u>: Cost 3 vext2 <5,u,1,3>, <5,u,1,3>
- 3780004466U, // <1,3,6,0>: Cost 4 vext3 <3,6,0,1>, <3,6,0,1>
- 3697725863U, // <1,3,6,1>: Cost 4 vext2 <1,1,1,3>, <6,1,7,1>
- 3692417530U, // <1,3,6,2>: Cost 4 vext2 <0,2,1,3>, <6,2,7,3>
- 3699053130U, // <1,3,6,3>: Cost 4 vext2 <1,3,1,3>, <6,3,7,2>
- 3798583964U, // <1,3,6,4>: Cost 4 vext3 <6,7,0,1>, <3,6,4,7>
- 3722277611U, // <1,3,6,5>: Cost 4 vext2 <5,2,1,3>, <6,5,7,1>
- 3718959928U, // <1,3,6,6>: Cost 4 vext2 <4,6,1,3>, <6,6,6,6>
- 2724842160U, // <1,3,6,7>: Cost 3 vext3 <6,7,0,1>, <3,6,7,0>
- 2725505721U, // <1,3,6,u>: Cost 3 vext3 <6,u,0,1>, <3,6,u,0>
+ 1551568425U, // <1,3,4,u>: Cost 2 vext2 <1,3,1,3>, RHS
+ 2563006566U, // <1,3,5,0>: Cost 3 vext1 <2,1,3,5>, LHS
+ 2568979456U, // <1,3,5,1>: Cost 3 vext1 <3,1,3,5>, <1,3,5,7>
+ 2563008035U, // <1,3,5,2>: Cost 3 vext1 <2,1,3,5>, <2,1,3,5>
+ 2233436412U, // <1,3,5,3>: Cost 3 vrev <3,1,3,5>
+ 2563009846U, // <1,3,5,4>: Cost 3 vext1 <2,1,3,5>, RHS
+ 2867187716U, // <1,3,5,5>: Cost 3 vuzpr LHS, <5,5,5,5>
+ 2655834214U, // <1,3,5,6>: Cost 3 vext2 <6,4,1,3>, <5,6,7,4>
+ 1745669430U, // <1,3,5,7>: Cost 2 vuzpr LHS, RHS
+ 1745669431U, // <1,3,5,u>: Cost 2 vuzpr LHS, RHS
+ 2867187810U, // <1,3,6,0>: Cost 3 vuzpr LHS, <5,6,7,0>
+ 3699052931U, // <1,3,6,1>: Cost 4 vext2 <1,3,1,3>, <6,1,3,1>
+ 2654507460U, // <1,3,6,2>: Cost 3 vext2 <6,2,1,3>, <6,2,1,3>
+ 3766291091U, // <1,3,6,3>: Cost 4 vext3 <1,3,3,1>, <3,6,3,7>
+ 2655834726U, // <1,3,6,4>: Cost 3 vext2 <6,4,1,3>, <6,4,1,3>
+ 3923384562U, // <1,3,6,5>: Cost 4 vuzpr <5,1,7,3>, <u,6,7,5>
+ 2657161992U, // <1,3,6,6>: Cost 3 vext2 <6,6,1,3>, <6,6,1,3>
+ 2819852218U, // <1,3,6,7>: Cost 3 vuzpr LHS, <2,6,3,7>
+ 2819852219U, // <1,3,6,u>: Cost 3 vuzpr LHS, <2,6,3,u>
2706926275U, // <1,3,7,0>: Cost 3 vext3 <3,7,0,1>, <3,7,0,1>
2659816524U, // <1,3,7,1>: Cost 3 vext2 <7,1,1,3>, <7,1,1,3>
- 3934954390U, // <1,3,7,2>: Cost 4 vuzpr <7,1,2,3>, <1,2,3,0>
- 3666627120U, // <1,3,7,3>: Cost 4 vext1 <7,1,3,7>, <3,5,1,7>
- 3718960486U, // <1,3,7,4>: Cost 4 vext2 <4,6,1,3>, <7,4,5,6>
- 3722278295U, // <1,3,7,5>: Cost 4 vext2 <5,2,1,3>, <7,5,2,1>
- 3307415833U, // <1,3,7,6>: Cost 4 vrev <3,1,6,7>
- 3718960748U, // <1,3,7,7>: Cost 4 vext2 <4,6,1,3>, <7,7,7,7>
- 2664461955U, // <1,3,7,u>: Cost 3 vext2 <7,u,1,3>, <7,u,1,3>
+ 3636766245U, // <1,3,7,2>: Cost 4 vext1 <2,1,3,7>, <2,1,3,7>
+ 2867187903U, // <1,3,7,3>: Cost 3 vuzpr LHS, <5,7,u,3>
+ 2625312102U, // <1,3,7,4>: Cost 3 vext2 <1,3,1,3>, <7,4,5,6>
+ 2867188598U, // <1,3,7,5>: Cost 3 vuzpr LHS, <6,7,4,5>
+ 3728250344U, // <1,3,7,6>: Cost 4 vext2 <6,2,1,3>, <7,6,2,1>
+ 2867187880U, // <1,3,7,7>: Cost 3 vuzpr LHS, <5,7,5,7>
+ 2707516171U, // <1,3,7,u>: Cost 3 vext3 <3,7,u,1>, <3,7,u,1>
1483317350U, // <1,3,u,0>: Cost 2 vext1 <1,1,3,u>, LHS
1483318093U, // <1,3,u,1>: Cost 2 vext1 <1,1,3,u>, <1,1,3,u>
- 2557060712U, // <1,3,u,2>: Cost 3 vext1 <1,1,3,u>, <2,2,2,2>
- 2557061270U, // <1,3,u,3>: Cost 3 vext1 <1,1,3,u>, <3,0,1,2>
+ 2819410718U, // <1,3,u,2>: Cost 3 vuzpr LHS, <3,u,1,2>
+ 1745666717U, // <1,3,u,3>: Cost 2 vuzpr LHS, LHS
1483320630U, // <1,3,u,4>: Cost 2 vext1 <1,1,3,u>, RHS
- 2618677402U, // <1,3,u,5>: Cost 3 vext2 <0,2,1,3>, RHS
- 2557063674U, // <1,3,u,6>: Cost 3 vext1 <1,1,3,u>, <6,2,7,3>
- 2598867962U, // <1,3,u,7>: Cost 3 vext1 <u,1,3,u>, <7,0,1,2>
- 1483323182U, // <1,3,u,u>: Cost 2 vext1 <1,1,3,u>, LHS
- 2708253541U, // <1,4,0,0>: Cost 3 vext3 <4,0,0,1>, <4,0,0,1>
- 2623987814U, // <1,4,0,1>: Cost 3 vext2 <1,1,1,4>, LHS
- 3697729700U, // <1,4,0,2>: Cost 4 vext2 <1,1,1,4>, <0,2,0,2>
- 3709010200U, // <1,4,0,3>: Cost 4 vext2 <3,0,1,4>, <0,3,4,1>
- 2580958098U, // <1,4,0,4>: Cost 3 vext1 <5,1,4,0>, <4,0,5,1>
+ 1551571098U, // <1,3,u,5>: Cost 2 vext2 <1,3,1,3>, RHS
+ 2819410758U, // <1,3,u,6>: Cost 3 vuzpr LHS, <3,u,5,6>
+ 1745669673U, // <1,3,u,7>: Cost 2 vuzpr LHS, RHS
+ 1745666722U, // <1,3,u,u>: Cost 2 vuzpr LHS, LHS
+ 2617352205U, // <1,4,0,0>: Cost 3 vext2 <0,0,1,4>, <0,0,1,4>
+ 2619342950U, // <1,4,0,1>: Cost 3 vext2 <0,3,1,4>, LHS
+ 3692421295U, // <1,4,0,2>: Cost 4 vext2 <0,2,1,4>, <0,2,1,4>
+ 2619343104U, // <1,4,0,3>: Cost 3 vext2 <0,3,1,4>, <0,3,1,4>
+ 2617352530U, // <1,4,0,4>: Cost 3 vext2 <0,0,1,4>, <0,4,1,5>
1634880402U, // <1,4,0,5>: Cost 2 vext3 <4,0,5,1>, <4,0,5,1>
- 2691074972U, // <1,4,0,6>: Cost 3 vext3 <1,1,1,1>, <4,0,6,2>
- 3654702074U, // <1,4,0,7>: Cost 4 vext1 <5,1,4,0>, <7,0,1,2>
+ 2713930652U, // <1,4,0,6>: Cost 3 vext3 <4,u,5,1>, <4,0,6,2>
+ 3732898396U, // <1,4,0,7>: Cost 4 vext2 <7,0,1,4>, <0,7,4,1>
1635101613U, // <1,4,0,u>: Cost 2 vext3 <4,0,u,1>, <4,0,u,1>
- 3697730275U, // <1,4,1,0>: Cost 4 vext2 <1,1,1,4>, <1,0,1,1>
+ 3693085430U, // <1,4,1,0>: Cost 4 vext2 <0,3,1,4>, <1,0,3,2>
2623988535U, // <1,4,1,1>: Cost 3 vext2 <1,1,1,4>, <1,1,1,4>
- 3697730439U, // <1,4,1,2>: Cost 4 vext2 <1,1,1,4>, <1,2,1,3>
- 3776318416U, // <1,4,1,3>: Cost 4 vext3 <3,0,4,1>, <4,1,3,0>
- 3697730590U, // <1,4,1,4>: Cost 4 vext2 <1,1,1,4>, <1,4,0,1>
- 2709285859U, // <1,4,1,5>: Cost 3 vext3 <4,1,5,1>, <4,1,5,1>
- 2709359596U, // <1,4,1,6>: Cost 3 vext3 <4,1,6,1>, <4,1,6,1>
+ 3693085590U, // <1,4,1,2>: Cost 4 vext2 <0,3,1,4>, <1,2,3,0>
+ 3692422134U, // <1,4,1,3>: Cost 4 vext2 <0,2,1,4>, <1,3,4,6>
+ 3693085726U, // <1,4,1,4>: Cost 4 vext2 <0,3,1,4>, <1,4,0,1>
+ 2892401974U, // <1,4,1,5>: Cost 3 vzipl <1,1,1,1>, RHS
+ 3026619702U, // <1,4,1,6>: Cost 3 vtrnl <1,1,1,1>, RHS
3800206324U, // <1,4,1,7>: Cost 4 vext3 <7,0,4,1>, <4,1,7,0>
- 2709507070U, // <1,4,1,u>: Cost 3 vext3 <4,1,u,1>, <4,1,u,1>
- 3709011380U, // <1,4,2,0>: Cost 4 vext2 <3,0,1,4>, <2,0,0,2>
- 3697731103U, // <1,4,2,1>: Cost 4 vext2 <1,1,1,4>, <2,1,3,1>
- 3697731176U, // <1,4,2,2>: Cost 4 vext2 <1,1,1,4>, <2,2,2,2>
+ 2892402217U, // <1,4,1,u>: Cost 3 vzipl <1,1,1,1>, RHS
+ 3966978927U, // <1,4,2,0>: Cost 4 vzipl <1,2,3,4>, <4,0,1,2>
+ 3966979018U, // <1,4,2,1>: Cost 4 vzipl <1,2,3,4>, <4,1,2,3>
+ 3693086312U, // <1,4,2,2>: Cost 4 vext2 <0,3,1,4>, <2,2,2,2>
2635269798U, // <1,4,2,3>: Cost 3 vext2 <3,0,1,4>, <2,3,0,1>
- 3642772790U, // <1,4,2,4>: Cost 4 vext1 <3,1,4,2>, RHS
- 2980496278U, // <1,4,2,5>: Cost 3 vzipr RHS, <1,2,3,0>
- 3771968574U, // <1,4,2,6>: Cost 4 vext3 <2,2,u,1>, <4,2,6,2>
+ 3966979280U, // <1,4,2,4>: Cost 4 vzipl <1,2,3,4>, <4,4,4,4>
+ 2893204790U, // <1,4,2,5>: Cost 3 vzipl <1,2,3,0>, RHS
+ 3693086650U, // <1,4,2,6>: Cost 4 vext2 <0,3,1,4>, <2,6,3,7>
3666662502U, // <1,4,2,7>: Cost 4 vext1 <7,1,4,2>, <7,1,4,2>
- 2982486934U, // <1,4,2,u>: Cost 3 vzipr RHS, <1,2,3,0>
+ 2893205033U, // <1,4,2,u>: Cost 3 vzipl <1,2,3,0>, RHS
2563063910U, // <1,4,3,0>: Cost 3 vext1 <2,1,4,3>, LHS
2563064730U, // <1,4,3,1>: Cost 3 vext1 <2,1,4,3>, <1,2,3,4>
2563065386U, // <1,4,3,2>: Cost 3 vext1 <2,1,4,3>, <2,1,4,3>
- 3697731996U, // <1,4,3,3>: Cost 4 vext2 <1,1,1,4>, <3,3,3,3>
- 2563067190U, // <1,4,3,4>: Cost 3 vext1 <2,1,4,3>, RHS
- 3070443622U, // <1,4,3,5>: Cost 3 vtrnl <u,4,1,5>, LHS
- 3040886886U, // <1,4,3,6>: Cost 3 vtrnl <3,4,5,6>, LHS
+ 3693087132U, // <1,4,3,3>: Cost 4 vext2 <0,3,1,4>, <3,3,3,3>
+ 2619345410U, // <1,4,3,4>: Cost 3 vext2 <0,3,1,4>, <3,4,5,6>
+ 3087843666U, // <1,4,3,5>: Cost 3 vtrnr LHS, <0,4,1,5>
+ 3087843676U, // <1,4,3,6>: Cost 3 vtrnr LHS, <0,4,2,6>
3666670695U, // <1,4,3,7>: Cost 4 vext1 <7,1,4,3>, <7,1,4,3>
- 2563069742U, // <1,4,3,u>: Cost 3 vext1 <2,1,4,3>, LHS
+ 3087843669U, // <1,4,3,u>: Cost 3 vtrnr LHS, <0,4,1,u>
2620672914U, // <1,4,4,0>: Cost 3 vext2 <0,5,1,4>, <4,0,5,1>
- 3697732579U, // <1,4,4,1>: Cost 4 vext2 <1,1,1,4>, <4,1,5,1>
- 3709013052U, // <1,4,4,2>: Cost 4 vext2 <3,0,1,4>, <4,2,6,0>
- 3313142740U, // <1,4,4,3>: Cost 4 vrev <4,1,3,4>
- 2724842704U, // <1,4,4,4>: Cost 3 vext3 <6,7,0,1>, <4,4,4,4>
- 2623991094U, // <1,4,4,5>: Cost 3 vext2 <1,1,1,4>, RHS
- 2724842724U, // <1,4,4,6>: Cost 3 vext3 <6,7,0,1>, <4,4,6,6>
- 3786640622U, // <1,4,4,7>: Cost 5 vext3 <4,7,0,1>, <4,4,7,7>
- 2623991337U, // <1,4,4,u>: Cost 3 vext2 <1,1,1,4>, RHS
+ 3630842706U, // <1,4,4,1>: Cost 4 vext1 <1,1,4,4>, <1,1,4,4>
+ 3313069003U, // <1,4,4,2>: Cost 4 vrev <4,1,2,4>
+ 3642788100U, // <1,4,4,3>: Cost 4 vext1 <3,1,4,4>, <3,1,4,4>
+ 2713930960U, // <1,4,4,4>: Cost 3 vext3 <4,u,5,1>, <4,4,4,4>
+ 2619346230U, // <1,4,4,5>: Cost 3 vext2 <0,3,1,4>, RHS
+ 2713930980U, // <1,4,4,6>: Cost 3 vext3 <4,u,5,1>, <4,4,6,6>
+ 3736882642U, // <1,4,4,7>: Cost 4 vext2 <7,6,1,4>, <4,7,6,1>
+ 2619346473U, // <1,4,4,u>: Cost 3 vext2 <0,3,1,4>, RHS
2557108326U, // <1,4,5,0>: Cost 3 vext1 <1,1,4,5>, LHS
2557109075U, // <1,4,5,1>: Cost 3 vext1 <1,1,4,5>, <1,1,4,5>
2598913774U, // <1,4,5,2>: Cost 3 vext1 <u,1,4,5>, <2,3,u,1>
3630852246U, // <1,4,5,3>: Cost 4 vext1 <1,1,4,5>, <3,0,1,2>
2557111606U, // <1,4,5,4>: Cost 3 vext1 <1,1,4,5>, RHS
- 2980504720U, // <1,4,5,5>: Cost 3 vzipr RHS, <1,5,3,7>
- 1617333558U, // <1,4,5,6>: Cost 2 vext3 <1,1,1,1>, RHS
- 3654743034U, // <1,4,5,7>: Cost 4 vext1 <5,1,4,5>, <7,0,1,2>
- 1617333576U, // <1,4,5,u>: Cost 2 vext3 <1,1,1,1>, RHS
- 2691075404U, // <1,4,6,0>: Cost 3 vext3 <1,1,1,1>, <4,6,0,2>
- 2712309076U, // <1,4,6,1>: Cost 3 vext3 <4,6,1,1>, <4,6,1,1>
- 2698300764U, // <1,4,6,2>: Cost 3 vext3 <2,3,0,1>, <4,6,2,0>
- 2712456550U, // <1,4,6,3>: Cost 3 vext3 <4,6,3,1>, <4,6,3,1>
- 2712825204U, // <1,4,6,4>: Cost 3 vext3 <4,6,u,1>, <4,6,4,6>
- 4054238415U, // <1,4,6,5>: Cost 4 vzipr RHS, <1,6,1,7>
- 3660722577U, // <1,4,6,6>: Cost 4 vext1 <6,1,4,6>, <6,1,4,6>
- 2659160910U, // <1,4,6,7>: Cost 3 vext2 <7,0,1,4>, <6,7,0,1>
- 2712825235U, // <1,4,6,u>: Cost 3 vext3 <4,6,u,1>, <4,6,u,1>
+ 2895252790U, // <1,4,5,5>: Cost 3 vzipl <1,5,3,7>, RHS
+ 1616006454U, // <1,4,5,6>: Cost 2 vext3 <0,u,1,1>, RHS
+ 3899059510U, // <1,4,5,7>: Cost 4 vuzpr <1,1,1,4>, RHS
+ 1616006472U, // <1,4,5,u>: Cost 2 vext3 <0,u,1,1>, RHS
+ 2557116518U, // <1,4,6,0>: Cost 3 vext1 <1,1,4,6>, LHS
+ 2557117236U, // <1,4,6,1>: Cost 3 vext1 <1,1,4,6>, <1,1,1,1>
+ 3630859880U, // <1,4,6,2>: Cost 4 vext1 <1,1,4,6>, <2,2,2,2>
+ 2569062550U, // <1,4,6,3>: Cost 3 vext1 <3,1,4,6>, <3,0,1,2>
+ 2557119798U, // <1,4,6,4>: Cost 3 vext1 <1,1,4,6>, RHS
+ 3763490174U, // <1,4,6,5>: Cost 4 vext3 <0,u,1,1>, <4,6,5,7>
+ 3763490183U, // <1,4,6,6>: Cost 4 vext3 <0,u,1,1>, <4,6,6,7>
+ 2712751498U, // <1,4,6,7>: Cost 3 vext3 <4,6,7,1>, <4,6,7,1>
+ 2557122350U, // <1,4,6,u>: Cost 3 vext1 <1,1,4,6>, LHS
2659161084U, // <1,4,7,0>: Cost 3 vext2 <7,0,1,4>, <7,0,1,4>
- 3733566541U, // <1,4,7,1>: Cost 4 vext2 <7,1,1,4>, <7,1,1,4>
+ 3732903040U, // <1,4,7,1>: Cost 4 vext2 <7,0,1,4>, <7,1,7,1>
3734230174U, // <1,4,7,2>: Cost 4 vext2 <7,2,1,4>, <7,2,1,4>
3734893807U, // <1,4,7,3>: Cost 4 vext2 <7,3,1,4>, <7,3,1,4>
- 3732903270U, // <1,4,7,4>: Cost 4 vext2 <7,0,1,4>, <7,4,5,6>
- 3736221073U, // <1,4,7,5>: Cost 4 vext2 <7,5,1,4>, <7,5,1,4>
- 3798584785U, // <1,4,7,6>: Cost 4 vext3 <6,7,0,1>, <4,7,6,0>
- 3732903532U, // <1,4,7,7>: Cost 4 vext2 <7,0,1,4>, <7,7,7,7>
+ 3660729654U, // <1,4,7,4>: Cost 4 vext1 <6,1,4,7>, RHS
+ 3786493384U, // <1,4,7,5>: Cost 4 vext3 <4,6,7,1>, <4,7,5,0>
+ 2713341394U, // <1,4,7,6>: Cost 3 vext3 <4,7,6,1>, <4,7,6,1>
+ 3660731386U, // <1,4,7,7>: Cost 4 vext1 <6,1,4,7>, <7,0,1,2>
2664470148U, // <1,4,7,u>: Cost 3 vext2 <7,u,1,4>, <7,u,1,4>
- 2691075566U, // <1,4,u,0>: Cost 3 vext3 <1,1,1,1>, <4,u,0,2>
- 2623993646U, // <1,4,u,1>: Cost 3 vext2 <1,1,1,4>, LHS
+ 2557132902U, // <1,4,u,0>: Cost 3 vext1 <1,1,4,u>, LHS
+ 2619348782U, // <1,4,u,1>: Cost 3 vext2 <0,3,1,4>, LHS
2563106351U, // <1,4,u,2>: Cost 3 vext1 <2,1,4,u>, <2,1,4,u>
2713783816U, // <1,4,u,3>: Cost 3 vext3 <4,u,3,1>, <4,u,3,1>
- 2557136182U, // <1,4,u,4>: Cost 3 vext1 <1,1,4,u>, RHS
- 1634880402U, // <1,4,u,5>: Cost 2 vext3 <4,0,5,1>, <4,0,5,1>
- 1617333801U, // <1,4,u,6>: Cost 2 vext3 <1,1,1,1>, RHS
- 2659160910U, // <1,4,u,7>: Cost 3 vext2 <7,0,1,4>, <6,7,0,1>
- 1617333819U, // <1,4,u,u>: Cost 2 vext3 <1,1,1,1>, RHS
- 2575056998U, // <1,5,0,0>: Cost 3 vext1 <4,1,5,0>, LHS
- 1594048614U, // <1,5,0,1>: Cost 2 vext2 <u,4,1,5>, LHS
- 2667790500U, // <1,5,0,2>: Cost 3 vext2 <u,4,1,5>, <0,2,0,2>
- 3648800918U, // <1,5,0,3>: Cost 4 vext1 <4,1,5,0>, <3,0,1,2>
+ 2622666815U, // <1,4,u,4>: Cost 3 vext2 <0,u,1,4>, <u,4,5,6>
+ 1640189466U, // <1,4,u,5>: Cost 2 vext3 <4,u,5,1>, <4,u,5,1>
+ 1616006697U, // <1,4,u,6>: Cost 2 vext3 <0,u,1,1>, RHS
+ 2712751498U, // <1,4,u,7>: Cost 3 vext3 <4,6,7,1>, <4,6,7,1>
+ 1616006715U, // <1,4,u,u>: Cost 2 vext3 <0,u,1,1>, RHS
+ 2620014592U, // <1,5,0,0>: Cost 3 vext2 <0,4,1,5>, <0,0,0,0>
+ 1546272870U, // <1,5,0,1>: Cost 2 vext2 <0,4,1,5>, LHS
+ 2618687664U, // <1,5,0,2>: Cost 3 vext2 <0,2,1,5>, <0,2,1,5>
+ 3693093120U, // <1,5,0,3>: Cost 4 vext2 <0,3,1,5>, <0,3,1,4>
1546273106U, // <1,5,0,4>: Cost 2 vext2 <0,4,1,5>, <0,4,1,5>
- 2714594923U, // <1,5,0,5>: Cost 3 vext3 <5,0,5,1>, <5,0,5,1>
+ 2620678563U, // <1,5,0,5>: Cost 3 vext2 <0,5,1,5>, <0,5,1,5>
2714668660U, // <1,5,0,6>: Cost 3 vext3 <5,0,6,1>, <5,0,6,1>
- 2714742397U, // <1,5,0,7>: Cost 3 vext3 <5,0,7,1>, <5,0,7,1>
- 1594049181U, // <1,5,0,u>: Cost 2 vext2 <u,4,1,5>, LHS
- 2708622991U, // <1,5,1,0>: Cost 3 vext3 <4,0,5,1>, <5,1,0,1>
- 2575065908U, // <1,5,1,1>: Cost 3 vext1 <4,1,5,1>, <1,1,1,1>
- 2667791254U, // <1,5,1,2>: Cost 3 vext2 <u,4,1,5>, <1,2,3,0>
- 3642837258U, // <1,5,1,3>: Cost 4 vext1 <3,1,5,1>, <3,1,5,1>
- 2708623026U, // <1,5,1,4>: Cost 3 vext3 <4,0,5,1>, <5,1,4,0>
- 2657838224U, // <1,5,1,5>: Cost 3 vext2 <6,7,1,5>, <1,5,3,7>
+ 3772042877U, // <1,5,0,7>: Cost 4 vext3 <2,3,0,1>, <5,0,7,1>
+ 1546273437U, // <1,5,0,u>: Cost 2 vext2 <0,4,1,5>, LHS
+ 2620015350U, // <1,5,1,0>: Cost 3 vext2 <0,4,1,5>, <1,0,3,2>
+ 2620015412U, // <1,5,1,1>: Cost 3 vext2 <0,4,1,5>, <1,1,1,1>
+ 2620015510U, // <1,5,1,2>: Cost 3 vext2 <0,4,1,5>, <1,2,3,0>
+ 2618688512U, // <1,5,1,3>: Cost 3 vext2 <0,2,1,5>, <1,3,5,7>
+ 2620015677U, // <1,5,1,4>: Cost 3 vext2 <0,4,1,5>, <1,4,3,5>
+ 2620015727U, // <1,5,1,5>: Cost 3 vext2 <0,4,1,5>, <1,5,0,1>
2620015859U, // <1,5,1,6>: Cost 3 vext2 <0,4,1,5>, <1,6,5,7>
- 2691075792U, // <1,5,1,7>: Cost 3 vext3 <1,1,1,1>, <5,1,7,3>
- 2691075801U, // <1,5,1,u>: Cost 3 vext3 <1,1,1,1>, <5,1,u,3>
- 2575073382U, // <1,5,2,0>: Cost 3 vext1 <4,1,5,2>, LHS
- 2708623083U, // <1,5,2,1>: Cost 3 vext3 <4,0,5,1>, <5,2,1,3>
- 2667791976U, // <1,5,2,2>: Cost 3 vext2 <u,4,1,5>, <2,2,2,2>
- 2667792038U, // <1,5,2,3>: Cost 3 vext2 <u,4,1,5>, <2,3,0,1>
- 2575076324U, // <1,5,2,4>: Cost 3 vext1 <4,1,5,2>, <4,1,5,2>
- 3648818896U, // <1,5,2,5>: Cost 4 vext1 <4,1,5,2>, <5,1,7,3>
- 2667792314U, // <1,5,2,6>: Cost 3 vext2 <u,4,1,5>, <2,6,3,7>
- 3760025376U, // <1,5,2,7>: Cost 4 vext3 <0,2,u,1>, <5,2,7,2>
- 2575079214U, // <1,5,2,u>: Cost 3 vext1 <4,1,5,2>, LHS
- 2569109606U, // <1,5,3,0>: Cost 3 vext1 <3,1,5,3>, LHS
- 2592998544U, // <1,5,3,1>: Cost 3 vext1 <7,1,5,3>, <1,5,3,7>
- 2569111246U, // <1,5,3,2>: Cost 3 vext1 <3,1,5,3>, <2,3,4,5>
- 2569111820U, // <1,5,3,3>: Cost 3 vext1 <3,1,5,3>, <3,1,5,3>
- 2569112886U, // <1,5,3,4>: Cost 3 vext1 <3,1,5,3>, RHS
- 3053486182U, // <1,5,3,5>: Cost 3 vtrnl <5,5,5,5>, LHS
- 3642855930U, // <1,5,3,6>: Cost 4 vext1 <3,1,5,3>, <6,2,7,3>
- 1973862502U, // <1,5,3,7>: Cost 2 vtrnl RHS, LHS
- 1973870694U, // <1,5,3,u>: Cost 2 vtrnl RHS, LHS
- 2667793298U, // <1,5,4,0>: Cost 3 vext2 <u,4,1,5>, <4,0,5,1>
- 2667793378U, // <1,5,4,1>: Cost 3 vext2 <u,4,1,5>, <4,1,5,0>
- 3741535277U, // <1,5,4,2>: Cost 4 vext2 <u,4,1,5>, <4,2,4,3>
- 3319115437U, // <1,5,4,3>: Cost 4 vrev <5,1,3,4>
- 2667793616U, // <1,5,4,4>: Cost 3 vext2 <u,4,1,5>, <4,4,4,4>
- 1594051894U, // <1,5,4,5>: Cost 2 vext2 <u,4,1,5>, RHS
- 2667793740U, // <1,5,4,6>: Cost 3 vext2 <u,4,1,5>, <4,6,0,2>
- 2724843462U, // <1,5,4,7>: Cost 3 vext3 <6,7,0,1>, <5,4,7,6>
- 1594052137U, // <1,5,4,u>: Cost 2 vext2 <u,4,1,5>, RHS
- 2717544403U, // <1,5,5,0>: Cost 3 vext3 <5,5,0,1>, <5,5,0,1>
- 2649878224U, // <1,5,5,1>: Cost 3 vext2 <5,4,1,5>, <5,1,7,3>
- 3741535979U, // <1,5,5,2>: Cost 4 vext2 <u,4,1,5>, <5,2,1,3>
- 3722956606U, // <1,5,5,3>: Cost 4 vext2 <5,3,1,5>, <5,3,1,5>
- 2245455543U, // <1,5,5,4>: Cost 3 vrev <5,1,4,5>
- 2718134276U, // <1,5,5,5>: Cost 3 vext3 <5,5,u,1>, <5,5,5,5>
+ 3093728566U, // <1,5,1,7>: Cost 3 vtrnr <1,1,1,1>, RHS
+ 2620015981U, // <1,5,1,u>: Cost 3 vext2 <0,4,1,5>, <1,u,1,3>
+ 3692430816U, // <1,5,2,0>: Cost 4 vext2 <0,2,1,5>, <2,0,5,1>
+ 2620016163U, // <1,5,2,1>: Cost 3 vext2 <0,4,1,5>, <2,1,3,5>
+ 2620016232U, // <1,5,2,2>: Cost 3 vext2 <0,4,1,5>, <2,2,2,2>
+ 2620016294U, // <1,5,2,3>: Cost 3 vext2 <0,4,1,5>, <2,3,0,1>
+ 3693758221U, // <1,5,2,4>: Cost 4 vext2 <0,4,1,5>, <2,4,2,5>
+ 3692431209U, // <1,5,2,5>: Cost 4 vext2 <0,2,1,5>, <2,5,3,7>
+ 2620016570U, // <1,5,2,6>: Cost 3 vext2 <0,4,1,5>, <2,6,3,7>
+ 4173598006U, // <1,5,2,7>: Cost 4 vtrnr <2,1,3,2>, RHS
+ 2620016699U, // <1,5,2,u>: Cost 3 vext2 <0,4,1,5>, <2,u,0,1>
+ 2620016790U, // <1,5,3,0>: Cost 3 vext2 <0,4,1,5>, <3,0,1,2>
+ 2569110672U, // <1,5,3,1>: Cost 3 vext1 <3,1,5,3>, <1,5,3,7>
+ 3693758785U, // <1,5,3,2>: Cost 4 vext2 <0,4,1,5>, <3,2,2,2>
+ 2620017052U, // <1,5,3,3>: Cost 3 vext2 <0,4,1,5>, <3,3,3,3>
+ 2620017154U, // <1,5,3,4>: Cost 3 vext2 <0,4,1,5>, <3,4,5,6>
+ 3135623172U, // <1,5,3,5>: Cost 3 vtrnr LHS, <5,5,5,5>
+ 4161587048U, // <1,5,3,6>: Cost 4 vtrnr LHS, <2,5,3,6>
+ 2014104886U, // <1,5,3,7>: Cost 2 vtrnr LHS, RHS
+ 2014104887U, // <1,5,3,u>: Cost 2 vtrnr LHS, RHS
+ 2620017554U, // <1,5,4,0>: Cost 3 vext2 <0,4,1,5>, <4,0,5,1>
+ 2620017634U, // <1,5,4,1>: Cost 3 vext2 <0,4,1,5>, <4,1,5,0>
+ 3693759551U, // <1,5,4,2>: Cost 4 vext2 <0,4,1,5>, <4,2,6,3>
+ 3642861837U, // <1,5,4,3>: Cost 4 vext1 <3,1,5,4>, <3,1,5,4>
+ 2575092710U, // <1,5,4,4>: Cost 3 vext1 <4,1,5,4>, <4,1,5,4>
+ 1546276150U, // <1,5,4,5>: Cost 2 vext2 <0,4,1,5>, RHS
+ 2759855414U, // <1,5,4,6>: Cost 3 vuzpl <1,3,5,7>, RHS
+ 2713931718U, // <1,5,4,7>: Cost 3 vext3 <4,u,5,1>, <5,4,7,6>
+ 1546276393U, // <1,5,4,u>: Cost 2 vext2 <0,4,1,5>, RHS
+ 2557182054U, // <1,5,5,0>: Cost 3 vext1 <1,1,5,5>, LHS
+ 2557182812U, // <1,5,5,1>: Cost 3 vext1 <1,1,5,5>, <1,1,5,5>
+ 3630925347U, // <1,5,5,2>: Cost 4 vext1 <1,1,5,5>, <2,1,3,5>
+ 4029301675U, // <1,5,5,3>: Cost 4 vzipr <0,4,1,5>, <1,2,5,3>
+ 2557185334U, // <1,5,5,4>: Cost 3 vext1 <1,1,5,5>, RHS
+ 2713931780U, // <1,5,5,5>: Cost 3 vext3 <4,u,5,1>, <5,5,5,5>
2667794530U, // <1,5,5,6>: Cost 3 vext2 <u,4,1,5>, <5,6,7,0>
- 2724843544U, // <1,5,5,7>: Cost 3 vext3 <6,7,0,1>, <5,5,7,7>
- 2245750491U, // <1,5,5,u>: Cost 3 vrev <5,1,u,5>
+ 2713931800U, // <1,5,5,7>: Cost 3 vext3 <4,u,5,1>, <5,5,7,7>
+ 2557187886U, // <1,5,5,u>: Cost 3 vext1 <1,1,5,5>, LHS
2718208036U, // <1,5,6,0>: Cost 3 vext3 <5,6,0,1>, <5,6,0,1>
- 2708623411U, // <1,5,6,1>: Cost 3 vext3 <4,0,5,1>, <5,6,1,7>
+ 2620019115U, // <1,5,6,1>: Cost 3 vext2 <0,4,1,5>, <6,1,7,5>
2667794938U, // <1,5,6,2>: Cost 3 vext2 <u,4,1,5>, <6,2,7,3>
- 3782365250U, // <1,5,6,3>: Cost 4 vext3 <4,0,5,1>, <5,6,3,4>
- 3782365255U, // <1,5,6,4>: Cost 4 vext3 <4,0,5,1>, <5,6,4,0>
- 3791876183U, // <1,5,6,5>: Cost 4 vext3 <5,5,u,1>, <5,6,5,7>
+ 3787673666U, // <1,5,6,3>: Cost 4 vext3 <4,u,5,1>, <5,6,3,4>
+ 3693761165U, // <1,5,6,4>: Cost 4 vext2 <0,4,1,5>, <6,4,5,6>
+ 3319279297U, // <1,5,6,5>: Cost 4 vrev <5,1,5,6>
2667795256U, // <1,5,6,6>: Cost 3 vext2 <u,4,1,5>, <6,6,6,6>
- 2718724195U, // <1,5,6,7>: Cost 3 vext3 <5,6,7,1>, <5,6,7,1>
- 2718797932U, // <1,5,6,u>: Cost 3 vext3 <5,6,u,1>, <5,6,u,1>
- 2667795450U, // <1,5,7,0>: Cost 3 vext2 <u,4,1,5>, <7,0,1,2>
- 4057597227U, // <1,5,7,1>: Cost 4 vzipr <5,1,7,3>, <1,7,3,0>
- 3741537445U, // <1,5,7,2>: Cost 4 vext2 <u,4,1,5>, <7,2,2,2>
- 3723621648U, // <1,5,7,3>: Cost 4 vext2 <5,4,1,5>, <7,3,5,1>
- 2667795814U, // <1,5,7,4>: Cost 3 vext2 <u,4,1,5>, <7,4,5,6>
- 3723621780U, // <1,5,7,5>: Cost 4 vext2 <5,4,1,5>, <7,5,1,7>
- 3736892899U, // <1,5,7,6>: Cost 4 vext2 <7,6,1,5>, <7,6,1,5>
- 2667796076U, // <1,5,7,7>: Cost 3 vext2 <u,4,1,5>, <7,7,7,7>
- 2667796098U, // <1,5,7,u>: Cost 3 vext2 <u,4,1,5>, <7,u,1,2>
- 2569150566U, // <1,5,u,0>: Cost 3 vext1 <3,1,5,u>, LHS
- 1594054446U, // <1,5,u,1>: Cost 2 vext2 <u,4,1,5>, LHS
- 2569152206U, // <1,5,u,2>: Cost 3 vext1 <3,1,5,u>, <2,3,4,5>
- 2569152785U, // <1,5,u,3>: Cost 3 vext1 <3,1,5,u>, <3,1,5,u>
+ 2713931874U, // <1,5,6,7>: Cost 3 vext3 <4,u,5,1>, <5,6,7,0>
+ 2713931883U, // <1,5,6,u>: Cost 3 vext3 <4,u,5,1>, <5,6,u,0>
+ 2557198438U, // <1,5,7,0>: Cost 3 vext1 <1,1,5,7>, LHS
+ 2557199156U, // <1,5,7,1>: Cost 3 vext1 <1,1,5,7>, <1,1,1,1>
+ 2569143974U, // <1,5,7,2>: Cost 3 vext1 <3,1,5,7>, <2,3,0,1>
+ 2569144592U, // <1,5,7,3>: Cost 3 vext1 <3,1,5,7>, <3,1,5,7>
+ 2557201718U, // <1,5,7,4>: Cost 3 vext1 <1,1,5,7>, RHS
+ 2713931944U, // <1,5,7,5>: Cost 3 vext3 <4,u,5,1>, <5,7,5,7>
+ 3787673770U, // <1,5,7,6>: Cost 4 vext3 <4,u,5,1>, <5,7,6,0>
+ 2719387828U, // <1,5,7,7>: Cost 3 vext3 <5,7,7,1>, <5,7,7,1>
+ 2557204270U, // <1,5,7,u>: Cost 3 vext1 <1,1,5,7>, LHS
+ 2620020435U, // <1,5,u,0>: Cost 3 vext2 <0,4,1,5>, <u,0,1,2>
+ 1546278702U, // <1,5,u,1>: Cost 2 vext2 <0,4,1,5>, LHS
+ 2620020616U, // <1,5,u,2>: Cost 3 vext2 <0,4,1,5>, <u,2,3,3>
+ 2620020668U, // <1,5,u,3>: Cost 3 vext2 <0,4,1,5>, <u,3,0,1>
1594054682U, // <1,5,u,4>: Cost 2 vext2 <u,4,1,5>, <u,4,1,5>
- 1594054810U, // <1,5,u,5>: Cost 2 vext2 <u,4,1,5>, RHS
- 2667796656U, // <1,5,u,6>: Cost 3 vext2 <u,4,1,5>, <u,6,0,2>
- 1973862507U, // <1,5,u,7>: Cost 2 vtrnl RHS, LHS
- 1973870699U, // <1,5,u,u>: Cost 2 vtrnl RHS, LHS
- 2620022794U, // <1,6,0,0>: Cost 3 vext2 <0,4,1,6>, <0,0,1,1>
- 2659172454U, // <1,6,0,1>: Cost 3 vext2 <7,0,1,6>, LHS
- 2720346409U, // <1,6,0,2>: Cost 3 vext3 <6,0,2,1>, <6,0,2,1>
- 3325055362U, // <1,6,0,3>: Cost 4 vrev <6,1,3,0>
- 2620023123U, // <1,6,0,4>: Cost 3 vext2 <0,4,1,6>, <0,4,1,6>
- 3798585674U, // <1,6,0,5>: Cost 4 vext3 <6,7,0,1>, <6,0,5,7>
+ 1546279066U, // <1,5,u,5>: Cost 2 vext2 <0,4,1,5>, RHS
+ 2620020944U, // <1,5,u,6>: Cost 3 vext2 <0,4,1,5>, <u,6,3,7>
+ 2014145846U, // <1,5,u,7>: Cost 2 vtrnr LHS, RHS
+ 2014145847U, // <1,5,u,u>: Cost 2 vtrnr LHS, RHS
+ 3692437504U, // <1,6,0,0>: Cost 4 vext2 <0,2,1,6>, <0,0,0,0>
+ 2618695782U, // <1,6,0,1>: Cost 3 vext2 <0,2,1,6>, LHS
+ 2618695857U, // <1,6,0,2>: Cost 3 vext2 <0,2,1,6>, <0,2,1,6>
+ 3794161970U, // <1,6,0,3>: Cost 4 vext3 <6,0,3,1>, <6,0,3,1>
+ 2620023122U, // <1,6,0,4>: Cost 3 vext2 <0,4,1,6>, <0,4,1,5>
+ 2620686756U, // <1,6,0,5>: Cost 3 vext2 <0,5,1,6>, <0,5,1,6>
2621350389U, // <1,6,0,6>: Cost 3 vext2 <0,6,1,6>, <0,6,1,6>
- 2720715094U, // <1,6,0,7>: Cost 3 vext3 <6,0,7,1>, <6,0,7,1>
- 2720788831U, // <1,6,0,u>: Cost 3 vext3 <6,0,u,1>, <6,0,u,1>
- 2575138918U, // <1,6,1,0>: Cost 3 vext1 <4,1,6,1>, LHS
- 2575139636U, // <1,6,1,1>: Cost 3 vext1 <4,1,6,1>, <1,1,1,1>
- 3764818300U, // <1,6,1,2>: Cost 4 vext3 <1,1,1,1>, <6,1,2,3>
- 3648882838U, // <1,6,1,3>: Cost 4 vext1 <4,1,6,1>, <3,0,1,2>
- 2575141868U, // <1,6,1,4>: Cost 3 vext1 <4,1,6,1>, <4,1,6,1>
- 3700401277U, // <1,6,1,5>: Cost 4 vext2 <1,5,1,6>, <1,5,1,6>
- 3648885159U, // <1,6,1,6>: Cost 4 vext1 <4,1,6,1>, <6,1,7,1>
- 2913386506U, // <1,6,1,7>: Cost 3 vzipl RHS, <0,0,1,1>
- 2575144750U, // <1,6,1,u>: Cost 3 vext1 <4,1,6,1>, LHS
+ 4028599606U, // <1,6,0,7>: Cost 4 vzipr <0,3,1,0>, RHS
+ 2618696349U, // <1,6,0,u>: Cost 3 vext2 <0,2,1,6>, LHS
+ 3692438262U, // <1,6,1,0>: Cost 4 vext2 <0,2,1,6>, <1,0,3,2>
+ 2625995572U, // <1,6,1,1>: Cost 3 vext2 <1,4,1,6>, <1,1,1,1>
+ 3692438422U, // <1,6,1,2>: Cost 4 vext2 <0,2,1,6>, <1,2,3,0>
+ 3692438488U, // <1,6,1,3>: Cost 4 vext2 <0,2,1,6>, <1,3,1,3>
+ 2625995820U, // <1,6,1,4>: Cost 3 vext2 <1,4,1,6>, <1,4,1,6>
+ 3692438672U, // <1,6,1,5>: Cost 4 vext2 <0,2,1,6>, <1,5,3,7>
+ 3692438720U, // <1,6,1,6>: Cost 4 vext2 <0,2,1,6>, <1,6,0,1>
+ 2958183734U, // <1,6,1,7>: Cost 3 vzipr <0,u,1,1>, RHS
+ 2958183735U, // <1,6,1,u>: Cost 3 vzipr <0,u,1,1>, RHS
2721526201U, // <1,6,2,0>: Cost 3 vext3 <6,2,0,1>, <6,2,0,1>
- 3630973794U, // <1,6,2,1>: Cost 4 vext1 <1,1,6,2>, <1,1,6,2>
- 3764818381U, // <1,6,2,2>: Cost 4 vext3 <1,1,1,1>, <6,2,2,3>
- 3709028006U, // <1,6,2,3>: Cost 4 vext2 <3,0,1,6>, <2,3,0,1>
- 3630976310U, // <1,6,2,4>: Cost 4 vext1 <1,1,6,2>, RHS
- 3654864582U, // <1,6,2,5>: Cost 4 vext1 <5,1,6,2>, <5,1,6,2>
- 3630977530U, // <1,6,2,6>: Cost 4 vext1 <1,1,6,2>, <6,2,7,3>
- 2691076602U, // <1,6,2,7>: Cost 3 vext3 <1,1,1,1>, <6,2,7,3>
- 2691076611U, // <1,6,2,u>: Cost 3 vext3 <1,1,1,1>, <6,2,u,3>
- 2575155302U, // <1,6,3,0>: Cost 3 vext1 <4,1,6,3>, LHS
- 3636954057U, // <1,6,3,1>: Cost 4 vext1 <2,1,6,3>, <1,2,u,6>
- 3047784550U, // <1,6,3,2>: Cost 3 vtrnl <4,6,0,2>, LHS
- 2575157762U, // <1,6,3,3>: Cost 3 vext1 <4,1,6,3>, <3,4,5,6>
- 2575158254U, // <1,6,3,4>: Cost 3 vext1 <4,1,6,3>, <4,1,6,3>
- 3648900816U, // <1,6,3,5>: Cost 4 vext1 <4,1,6,3>, <5,1,7,3>
- 3048112230U, // <1,6,3,6>: Cost 3 vtrnl <4,6,4,6>, LHS
- 3060285542U, // <1,6,3,7>: Cost 3 vtrnl <6,6,7,7>, LHS
- 2575161134U, // <1,6,3,u>: Cost 3 vext1 <4,1,6,3>, LHS
- 3782365791U, // <1,6,4,0>: Cost 4 vext3 <4,0,5,1>, <6,4,0,5>
- 3699739628U, // <1,6,4,1>: Cost 4 vext2 <1,4,1,6>, <4,1,6,1>
- 3794088561U, // <1,6,4,2>: Cost 4 vext3 <6,0,2,1>, <6,4,2,5>
+ 3692439097U, // <1,6,2,1>: Cost 4 vext2 <0,2,1,6>, <2,1,6,0>
+ 3692439144U, // <1,6,2,2>: Cost 4 vext2 <0,2,1,6>, <2,2,2,2>
+ 3692439206U, // <1,6,2,3>: Cost 4 vext2 <0,2,1,6>, <2,3,0,1>
+ 3636948278U, // <1,6,2,4>: Cost 4 vext1 <2,1,6,2>, RHS
+ 3787674092U, // <1,6,2,5>: Cost 4 vext3 <4,u,5,1>, <6,2,5,7>
+ 2618697658U, // <1,6,2,6>: Cost 3 vext2 <0,2,1,6>, <2,6,3,7>
+ 2970799414U, // <1,6,2,7>: Cost 3 vzipr <3,0,1,2>, RHS
+ 2970799415U, // <1,6,2,u>: Cost 3 vzipr <3,0,1,2>, RHS
+ 2563211366U, // <1,6,3,0>: Cost 3 vext1 <2,1,6,3>, LHS
+ 3699738854U, // <1,6,3,1>: Cost 4 vext2 <1,4,1,6>, <3,1,1,1>
+ 2563212860U, // <1,6,3,2>: Cost 3 vext1 <2,1,6,3>, <2,1,6,3>
+ 3692439964U, // <1,6,3,3>: Cost 4 vext2 <0,2,1,6>, <3,3,3,3>
+ 2563214646U, // <1,6,3,4>: Cost 3 vext1 <2,1,6,3>, RHS
+ 4191820018U, // <1,6,3,5>: Cost 4 vtrnr <5,1,7,3>, <u,6,7,5>
+ 2587103648U, // <1,6,3,6>: Cost 3 vext1 <6,1,6,3>, <6,1,6,3>
+ 3087845306U, // <1,6,3,7>: Cost 3 vtrnr LHS, <2,6,3,7>
+ 3087845307U, // <1,6,3,u>: Cost 3 vtrnr LHS, <2,6,3,u>
+ 3693767570U, // <1,6,4,0>: Cost 4 vext2 <0,4,1,6>, <4,0,5,1>
+ 3693767650U, // <1,6,4,1>: Cost 4 vext2 <0,4,1,6>, <4,1,5,0>
+ 3636962877U, // <1,6,4,2>: Cost 4 vext1 <2,1,6,4>, <2,1,6,4>
3325088134U, // <1,6,4,3>: Cost 4 vrev <6,1,3,4>
- 3648908271U, // <1,6,4,4>: Cost 4 vext1 <4,1,6,4>, <4,1,6,4>
- 2659175734U, // <1,6,4,5>: Cost 3 vext2 <7,0,1,6>, RHS
- 3786568336U, // <1,6,4,6>: Cost 4 vext3 <4,6,u,1>, <6,4,6,0>
- 3772633758U, // <1,6,4,7>: Cost 4 vext3 <2,3,u,1>, <6,4,7,5>
- 2659175977U, // <1,6,4,u>: Cost 3 vext2 <7,0,1,6>, RHS
- 3648913510U, // <1,6,5,0>: Cost 4 vext1 <4,1,6,5>, LHS
- 3648914228U, // <1,6,5,1>: Cost 4 vext1 <4,1,6,5>, <1,1,1,1>
- 4064232592U, // <1,6,5,2>: Cost 4 vzipr <6,2,7,3>, <1,5,3,7>
+ 3693767898U, // <1,6,4,4>: Cost 4 vext2 <0,4,1,6>, <4,4,5,5>
+ 2618699062U, // <1,6,4,5>: Cost 3 vext2 <0,2,1,6>, RHS
+ 3833670966U, // <1,6,4,6>: Cost 4 vuzpl <1,3,6,7>, RHS
+ 4028632374U, // <1,6,4,7>: Cost 4 vzipr <0,3,1,4>, RHS
+ 2618699305U, // <1,6,4,u>: Cost 3 vext2 <0,2,1,6>, RHS
+ 3693768264U, // <1,6,5,0>: Cost 4 vext2 <0,4,1,6>, <5,0,1,2>
+ 3630998373U, // <1,6,5,1>: Cost 4 vext1 <1,1,6,5>, <1,1,6,5>
+ 3636971070U, // <1,6,5,2>: Cost 4 vext1 <2,1,6,5>, <2,1,6,5>
3642943767U, // <1,6,5,3>: Cost 4 vext1 <3,1,6,5>, <3,1,6,5>
- 3648916464U, // <1,6,5,4>: Cost 4 vext1 <4,1,6,5>, <4,1,6,5>
- 3724292065U, // <1,6,5,5>: Cost 4 vext2 <5,5,1,6>, <5,5,1,6>
- 2668466274U, // <1,6,5,6>: Cost 3 vext2 <u,5,1,6>, <5,6,7,0>
- 2915377490U, // <1,6,5,7>: Cost 3 vzipl RHS, <0,4,1,5>
- 2913395026U, // <1,6,5,u>: Cost 3 vzipl RHS, <0,4,1,5>
+ 3693768628U, // <1,6,5,4>: Cost 4 vext2 <0,4,1,6>, <5,4,5,6>
+ 3732918276U, // <1,6,5,5>: Cost 4 vext2 <7,0,1,6>, <5,5,5,5>
+ 2620690530U, // <1,6,5,6>: Cost 3 vext2 <0,5,1,6>, <5,6,7,0>
+ 2955562294U, // <1,6,5,7>: Cost 3 vzipr <0,4,1,5>, RHS
+ 2955562295U, // <1,6,5,u>: Cost 3 vzipr <0,4,1,5>, RHS
2724180733U, // <1,6,6,0>: Cost 3 vext3 <6,6,0,1>, <6,6,0,1>
- 3742871965U, // <1,6,6,1>: Cost 4 vext2 <u,6,1,6>, <6,1,6,0>
- 3697750522U, // <1,6,6,2>: Cost 4 vext2 <1,1,1,6>, <6,2,7,3>
- 3782365979U, // <1,6,6,3>: Cost 5 vext3 <4,0,5,1>, <6,6,3,4>
- 3654896530U, // <1,6,6,4>: Cost 4 vext1 <5,1,6,6>, <4,0,5,1>
- 3654897354U, // <1,6,6,5>: Cost 4 vext1 <5,1,6,6>, <5,1,6,6>
- 2724770616U, // <1,6,6,6>: Cost 3 vext3 <6,6,u,1>, <6,6,6,6>
- 2724844354U, // <1,6,6,7>: Cost 3 vext3 <6,7,0,1>, <6,6,7,7>
- 2724770629U, // <1,6,6,u>: Cost 3 vext3 <6,6,u,1>, <6,6,u,1>
+ 3631006566U, // <1,6,6,1>: Cost 4 vext1 <1,1,6,6>, <1,1,6,6>
+ 3631007674U, // <1,6,6,2>: Cost 4 vext1 <1,1,6,6>, <2,6,3,7>
+ 3692442184U, // <1,6,6,3>: Cost 4 vext2 <0,2,1,6>, <6,3,7,0>
+ 3631009078U, // <1,6,6,4>: Cost 4 vext1 <1,1,6,6>, RHS
+ 3787674416U, // <1,6,6,5>: Cost 4 vext3 <4,u,5,1>, <6,6,5,7>
+ 2713932600U, // <1,6,6,6>: Cost 3 vext3 <4,u,5,1>, <6,6,6,6>
+ 2713932610U, // <1,6,6,7>: Cost 3 vext3 <4,u,5,1>, <6,6,7,7>
+ 2713932619U, // <1,6,6,u>: Cost 3 vext3 <4,u,5,1>, <6,6,u,7>
1651102542U, // <1,6,7,0>: Cost 2 vext3 <6,7,0,1>, <6,7,0,1>
2724918103U, // <1,6,7,1>: Cost 3 vext3 <6,7,1,1>, <6,7,1,1>
2698302306U, // <1,6,7,2>: Cost 3 vext3 <2,3,0,1>, <6,7,2,3>
- 3786199912U, // <1,6,7,3>: Cost 4 vext3 <4,6,3,1>, <6,7,3,0>
- 2724844406U, // <1,6,7,4>: Cost 3 vext3 <6,7,0,1>, <6,7,4,5>
+ 3642960153U, // <1,6,7,3>: Cost 4 vext1 <3,1,6,7>, <3,1,6,7>
+ 2713932662U, // <1,6,7,4>: Cost 3 vext3 <4,u,5,1>, <6,7,4,5>
2725213051U, // <1,6,7,5>: Cost 3 vext3 <6,7,5,1>, <6,7,5,1>
2724844426U, // <1,6,7,6>: Cost 3 vext3 <6,7,0,1>, <6,7,6,7>
- 3987129551U, // <1,6,7,7>: Cost 4 vzipl RHS, <1,6,1,7>
+ 4035956022U, // <1,6,7,7>: Cost 4 vzipr <1,5,1,7>, RHS
1651692438U, // <1,6,7,u>: Cost 2 vext3 <6,7,u,1>, <6,7,u,1>
1651766175U, // <1,6,u,0>: Cost 2 vext3 <6,u,0,1>, <6,u,0,1>
- 2725581736U, // <1,6,u,1>: Cost 3 vext3 <6,u,1,1>, <6,u,1,1>
- 3047784555U, // <1,6,u,2>: Cost 3 vtrnl <4,6,0,2>, LHS
- 2575198722U, // <1,6,u,3>: Cost 3 vext1 <4,1,6,u>, <3,4,5,6>
- 2575199219U, // <1,6,u,4>: Cost 3 vext1 <4,1,6,u>, <4,1,6,u>
- 2725876684U, // <1,6,u,5>: Cost 3 vext3 <6,u,5,1>, <6,u,5,1>
- 3048112235U, // <1,6,u,6>: Cost 3 vtrnl <4,6,4,6>, LHS
- 2691077088U, // <1,6,u,7>: Cost 3 vext3 <1,1,1,1>, <6,u,7,3>
+ 2618701614U, // <1,6,u,1>: Cost 3 vext2 <0,2,1,6>, LHS
+ 3135663508U, // <1,6,u,2>: Cost 3 vtrnr LHS, <4,6,u,2>
+ 3692443580U, // <1,6,u,3>: Cost 4 vext2 <0,2,1,6>, <u,3,0,1>
+ 2713932743U, // <1,6,u,4>: Cost 3 vext3 <4,u,5,1>, <6,u,4,5>
+ 2618701978U, // <1,6,u,5>: Cost 3 vext2 <0,2,1,6>, RHS
+ 2622683344U, // <1,6,u,6>: Cost 3 vext2 <0,u,1,6>, <u,6,3,7>
+ 3087886266U, // <1,6,u,7>: Cost 3 vtrnr LHS, <2,6,3,7>
1652356071U, // <1,6,u,u>: Cost 2 vext3 <6,u,u,1>, <6,u,u,1>
2726171632U, // <1,7,0,0>: Cost 3 vext3 <7,0,0,1>, <7,0,0,1>
- 2638610534U, // <1,7,0,1>: Cost 3 vext2 <3,5,1,7>, LHS
- 3706380452U, // <1,7,0,2>: Cost 4 vext2 <2,5,1,7>, <0,2,0,2>
- 3654920752U, // <1,7,0,3>: Cost 4 vext1 <5,1,7,0>, <3,5,1,7>
+ 2626666598U, // <1,7,0,1>: Cost 3 vext2 <1,5,1,7>, LHS
+ 3695100067U, // <1,7,0,2>: Cost 4 vext2 <0,6,1,7>, <0,2,0,1>
+ 3707044102U, // <1,7,0,3>: Cost 4 vext2 <2,6,1,7>, <0,3,2,1>
2726466580U, // <1,7,0,4>: Cost 3 vext3 <7,0,4,1>, <7,0,4,1>
3654921933U, // <1,7,0,5>: Cost 4 vext1 <5,1,7,0>, <5,1,7,0>
2621358582U, // <1,7,0,6>: Cost 3 vext2 <0,6,1,7>, <0,6,1,7>
2622022215U, // <1,7,0,7>: Cost 3 vext2 <0,7,1,7>, <0,7,1,7>
- 2638611101U, // <1,7,0,u>: Cost 3 vext2 <3,5,1,7>, LHS
- 2581184614U, // <1,7,1,0>: Cost 3 vext1 <5,1,7,1>, LHS
- 2581185332U, // <1,7,1,1>: Cost 3 vext1 <5,1,7,1>, <1,1,1,1>
- 3712353174U, // <1,7,1,2>: Cost 4 vext2 <3,5,1,7>, <1,2,3,0>
- 3654928534U, // <1,7,1,3>: Cost 4 vext1 <5,1,7,1>, <3,0,1,2>
- 2581187894U, // <1,7,1,4>: Cost 3 vext1 <5,1,7,1>, RHS
- 2581188302U, // <1,7,1,5>: Cost 3 vext1 <5,1,7,1>, <5,1,7,1>
- 2587160999U, // <1,7,1,6>: Cost 3 vext1 <6,1,7,1>, <6,1,7,1>
- 2593133562U, // <1,7,1,7>: Cost 3 vext1 <7,1,7,1>, <7,0,1,2>
- 2581190446U, // <1,7,1,u>: Cost 3 vext1 <5,1,7,1>, LHS
+ 2626667165U, // <1,7,0,u>: Cost 3 vext2 <1,5,1,7>, LHS
+ 2593128550U, // <1,7,1,0>: Cost 3 vext1 <7,1,7,1>, LHS
+ 2626667316U, // <1,7,1,1>: Cost 3 vext2 <1,5,1,7>, <1,1,1,1>
+ 3700409238U, // <1,7,1,2>: Cost 4 vext2 <1,5,1,7>, <1,2,3,0>
+ 2257294428U, // <1,7,1,3>: Cost 3 vrev <7,1,3,1>
+ 2593131830U, // <1,7,1,4>: Cost 3 vext1 <7,1,7,1>, RHS
+ 2626667646U, // <1,7,1,5>: Cost 3 vext2 <1,5,1,7>, <1,5,1,7>
+ 2627331279U, // <1,7,1,6>: Cost 3 vext2 <1,6,1,7>, <1,6,1,7>
+ 2593133696U, // <1,7,1,7>: Cost 3 vext1 <7,1,7,1>, <7,1,7,1>
+ 2628658545U, // <1,7,1,u>: Cost 3 vext2 <1,u,1,7>, <1,u,1,7>
2587164774U, // <1,7,2,0>: Cost 3 vext1 <6,1,7,2>, LHS
- 3654935340U, // <1,7,2,1>: Cost 4 vext1 <5,1,7,2>, <1,1,0,2>
- 3712353896U, // <1,7,2,2>: Cost 4 vext2 <3,5,1,7>, <2,2,2,2>
- 2587166870U, // <1,7,2,3>: Cost 3 vext1 <6,1,7,2>, <3,0,1,2>
+ 3701073445U, // <1,7,2,1>: Cost 4 vext2 <1,6,1,7>, <2,1,3,7>
+ 3700409960U, // <1,7,2,2>: Cost 4 vext2 <1,5,1,7>, <2,2,2,2>
+ 2638612134U, // <1,7,2,3>: Cost 3 vext2 <3,5,1,7>, <2,3,0,1>
2587168054U, // <1,7,2,4>: Cost 3 vext1 <6,1,7,2>, RHS
3706382167U, // <1,7,2,5>: Cost 4 vext2 <2,5,1,7>, <2,5,1,7>
2587169192U, // <1,7,2,6>: Cost 3 vext1 <6,1,7,2>, <6,1,7,2>
- 3993176214U, // <1,7,2,7>: Cost 4 vzipl <5,5,7,7>, <3,0,1,2>
+ 3660911610U, // <1,7,2,7>: Cost 4 vext1 <6,1,7,2>, <7,0,1,2>
2587170606U, // <1,7,2,u>: Cost 3 vext1 <6,1,7,2>, LHS
1507459174U, // <1,7,3,0>: Cost 2 vext1 <5,1,7,3>, LHS
- 2581201654U, // <1,7,3,1>: Cost 3 vext1 <5,1,7,3>, <1,0,3,2>
+ 2569257984U, // <1,7,3,1>: Cost 3 vext1 <3,1,7,3>, <1,3,5,7>
2581202536U, // <1,7,3,2>: Cost 3 vext1 <5,1,7,3>, <2,2,2,2>
- 2581203094U, // <1,7,3,3>: Cost 3 vext1 <5,1,7,3>, <3,0,1,2>
+ 2569259294U, // <1,7,3,3>: Cost 3 vext1 <3,1,7,3>, <3,1,7,3>
1507462454U, // <1,7,3,4>: Cost 2 vext1 <5,1,7,3>, RHS
1507462864U, // <1,7,3,5>: Cost 2 vext1 <5,1,7,3>, <5,1,7,3>
2581205498U, // <1,7,3,6>: Cost 3 vext1 <5,1,7,3>, <6,2,7,3>
2581206010U, // <1,7,3,7>: Cost 3 vext1 <5,1,7,3>, <7,0,1,2>
1507465006U, // <1,7,3,u>: Cost 2 vext1 <5,1,7,3>, LHS
- 2651220882U, // <1,7,4,0>: Cost 3 vext2 <5,6,1,7>, <4,0,5,1>
- 3330913357U, // <1,7,4,1>: Cost 4 vrev <7,1,1,4>
+ 2728826164U, // <1,7,4,0>: Cost 3 vext3 <7,4,0,1>, <7,4,0,1>
+ 3654951732U, // <1,7,4,1>: Cost 4 vext1 <5,1,7,4>, <1,1,1,1>
3330987094U, // <1,7,4,2>: Cost 4 vrev <7,1,2,4>
- 3654953520U, // <1,7,4,3>: Cost 4 vext1 <5,1,7,4>, <3,5,1,7>
- 3654954294U, // <1,7,4,4>: Cost 4 vext1 <5,1,7,4>, RHS
- 2638613814U, // <1,7,4,5>: Cost 3 vext2 <3,5,1,7>, RHS
- 3712355660U, // <1,7,4,6>: Cost 4 vext2 <3,5,1,7>, <4,6,0,2>
- 3798586743U, // <1,7,4,7>: Cost 4 vext3 <6,7,0,1>, <7,4,7,5>
- 2638614057U, // <1,7,4,u>: Cost 3 vext2 <3,5,1,7>, RHS
- 2599133286U, // <1,7,5,0>: Cost 3 vext1 <u,1,7,5>, LHS
- 2638614224U, // <1,7,5,1>: Cost 3 vext2 <3,5,1,7>, <5,1,7,3>
- 3724963563U, // <1,7,5,2>: Cost 4 vext2 <5,6,1,7>, <5,2,1,3>
- 3990487378U, // <1,7,5,3>: Cost 4 vzipl <5,1,7,3>, <0,4,1,5>
- 2599136566U, // <1,7,5,4>: Cost 3 vext1 <u,1,7,5>, RHS
- 3654962898U, // <1,7,5,5>: Cost 4 vext1 <5,1,7,5>, <5,1,7,5>
+ 3331060831U, // <1,7,4,3>: Cost 4 vrev <7,1,3,4>
+ 3787674971U, // <1,7,4,4>: Cost 4 vext3 <4,u,5,1>, <7,4,4,4>
+ 2626669878U, // <1,7,4,5>: Cost 3 vext2 <1,5,1,7>, RHS
+ 3785979241U, // <1,7,4,6>: Cost 4 vext3 <4,6,0,1>, <7,4,6,0>
+ 3787085176U, // <1,7,4,7>: Cost 4 vext3 <4,7,6,1>, <7,4,7,6>
+ 2626670121U, // <1,7,4,u>: Cost 3 vext2 <1,5,1,7>, RHS
+ 2569273446U, // <1,7,5,0>: Cost 3 vext1 <3,1,7,5>, LHS
+ 2569274368U, // <1,7,5,1>: Cost 3 vext1 <3,1,7,5>, <1,3,5,7>
+ 3643016808U, // <1,7,5,2>: Cost 4 vext1 <3,1,7,5>, <2,2,2,2>
+ 2569275680U, // <1,7,5,3>: Cost 3 vext1 <3,1,7,5>, <3,1,7,5>
+ 2569276726U, // <1,7,5,4>: Cost 3 vext1 <3,1,7,5>, RHS
+ 4102034790U, // <1,7,5,5>: Cost 4 vtrnl <1,3,5,7>, <7,4,5,6>
2651222067U, // <1,7,5,6>: Cost 3 vext2 <5,6,1,7>, <5,6,1,7>
- 3712356470U, // <1,7,5,7>: Cost 4 vext2 <3,5,1,7>, <5,7,0,2>
- 2638614224U, // <1,7,5,u>: Cost 3 vext2 <3,5,1,7>, <5,1,7,3>
+ 3899378998U, // <1,7,5,7>: Cost 4 vuzpr <1,1,5,7>, RHS
+ 2569279278U, // <1,7,5,u>: Cost 3 vext1 <3,1,7,5>, LHS
2730153430U, // <1,7,6,0>: Cost 3 vext3 <7,6,0,1>, <7,6,0,1>
2724845022U, // <1,7,6,1>: Cost 3 vext3 <6,7,0,1>, <7,6,1,0>
- 3712356858U, // <1,7,6,2>: Cost 4 vext2 <3,5,1,7>, <6,2,7,3>
- 3772044786U, // <1,7,6,3>: Cost 4 vext3 <2,3,0,1>, <7,6,3,2>
- 3798586878U, // <1,7,6,4>: Cost 4 vext3 <6,7,0,1>, <7,6,4,5>
- 3724964587U, // <1,7,6,5>: Cost 4 vext2 <5,6,1,7>, <6,5,7,1>
- 3724964664U, // <1,7,6,6>: Cost 4 vext2 <5,6,1,7>, <6,6,6,6>
+ 3643025338U, // <1,7,6,2>: Cost 4 vext1 <3,1,7,6>, <2,6,3,7>
+ 3643025697U, // <1,7,6,3>: Cost 4 vext1 <3,1,7,6>, <3,1,7,6>
+ 3643026742U, // <1,7,6,4>: Cost 4 vext1 <3,1,7,6>, RHS
+ 3654971091U, // <1,7,6,5>: Cost 4 vext1 <5,1,7,6>, <5,1,7,6>
+ 3787675153U, // <1,7,6,6>: Cost 4 vext3 <4,u,5,1>, <7,6,6,6>
2724845076U, // <1,7,6,7>: Cost 3 vext3 <6,7,0,1>, <7,6,7,0>
2725508637U, // <1,7,6,u>: Cost 3 vext3 <6,u,0,1>, <7,6,u,0>
2730817063U, // <1,7,7,0>: Cost 3 vext3 <7,7,0,1>, <7,7,0,1>
- 4134125710U, // <1,7,7,1>: Cost 4 vtrnl <6,7,0,1>, <0,1,6,7>
- 3712357556U, // <1,7,7,2>: Cost 4 vext2 <3,5,1,7>, <7,2,3,u>
- 3990489648U, // <1,7,7,3>: Cost 4 vzipl <5,1,7,3>, <3,5,1,7>
- 3724965176U, // <1,7,7,4>: Cost 4 vext2 <5,6,1,7>, <7,4,0,5>
+ 3631088436U, // <1,7,7,1>: Cost 4 vext1 <1,1,7,7>, <1,1,1,1>
+ 3660949158U, // <1,7,7,2>: Cost 4 vext1 <6,1,7,7>, <2,3,0,1>
+ 3801904705U, // <1,7,7,3>: Cost 4 vext3 <7,3,0,1>, <7,7,3,0>
+ 3631090998U, // <1,7,7,4>: Cost 4 vext1 <1,1,7,7>, RHS
2662503828U, // <1,7,7,5>: Cost 3 vext2 <7,5,1,7>, <7,5,1,7>
3660951981U, // <1,7,7,6>: Cost 4 vext1 <6,1,7,7>, <6,1,7,7>
- 2724845164U, // <1,7,7,7>: Cost 3 vext3 <6,7,0,1>, <7,7,7,7>
+ 2713933420U, // <1,7,7,7>: Cost 3 vext3 <4,u,5,1>, <7,7,7,7>
2731406959U, // <1,7,7,u>: Cost 3 vext3 <7,7,u,1>, <7,7,u,1>
1507500134U, // <1,7,u,0>: Cost 2 vext1 <5,1,7,u>, LHS
- 2638616366U, // <1,7,u,1>: Cost 3 vext2 <3,5,1,7>, LHS
+ 2626672430U, // <1,7,u,1>: Cost 3 vext2 <1,5,1,7>, LHS
2581243496U, // <1,7,u,2>: Cost 3 vext1 <5,1,7,u>, <2,2,2,2>
- 2581244054U, // <1,7,u,3>: Cost 3 vext1 <5,1,7,u>, <3,0,1,2>
+ 2569300259U, // <1,7,u,3>: Cost 3 vext1 <3,1,7,u>, <3,1,7,u>
1507503414U, // <1,7,u,4>: Cost 2 vext1 <5,1,7,u>, RHS
1507503829U, // <1,7,u,5>: Cost 2 vext1 <5,1,7,u>, <5,1,7,u>
2581246458U, // <1,7,u,6>: Cost 3 vext1 <5,1,7,u>, <6,2,7,3>
2581246970U, // <1,7,u,7>: Cost 3 vext1 <5,1,7,u>, <7,0,1,2>
1507505966U, // <1,7,u,u>: Cost 2 vext1 <5,1,7,u>, LHS
1543643153U, // <1,u,0,0>: Cost 2 vext2 <0,0,1,u>, <0,0,1,u>
- 1561559142U, // <1,u,0,1>: Cost 2 vext2 <3,0,1,u>, LHS
- 2819449635U, // <1,u,0,2>: Cost 3 vuzpr LHS, <1,0,u,2>
- 2691077861U, // <1,u,0,3>: Cost 3 vext3 <1,1,1,1>, <u,0,3,2>
+ 1546297446U, // <1,u,0,1>: Cost 2 vext2 <0,4,1,u>, LHS
+ 2819448852U, // <1,u,0,2>: Cost 3 vuzpr LHS, <0,0,2,2>
+ 2619375876U, // <1,u,0,3>: Cost 3 vext2 <0,3,1,u>, <0,3,1,u>
1546297685U, // <1,u,0,4>: Cost 2 vext2 <0,4,1,u>, <0,4,1,u>
1658771190U, // <1,u,0,5>: Cost 2 vext3 <u,0,5,1>, <u,0,5,1>
- 2691077888U, // <1,u,0,6>: Cost 3 vext3 <1,1,1,1>, <u,0,6,2>
+ 2736789248U, // <1,u,0,6>: Cost 3 vext3 <u,7,0,1>, <u,0,6,2>
2659189376U, // <1,u,0,7>: Cost 3 vext2 <7,0,1,u>, <0,7,u,1>
- 1561559709U, // <1,u,0,u>: Cost 2 vext2 <3,0,1,u>, LHS
+ 1546298013U, // <1,u,0,u>: Cost 2 vext2 <0,4,1,u>, LHS
1483112550U, // <1,u,1,0>: Cost 2 vext1 <1,1,1,1>, LHS
202162278U, // <1,u,1,1>: Cost 1 vdup1 LHS
- 1617336110U, // <1,u,1,2>: Cost 2 vext3 <1,1,1,1>, LHS
- 2886959114U, // <1,u,1,3>: Cost 3 vzipl LHS, <0,0,1,1>
+ 1616009006U, // <1,u,1,2>: Cost 2 vext3 <0,u,1,1>, LHS
+ 1745707110U, // <1,u,1,3>: Cost 2 vuzpr LHS, LHS
1483115830U, // <1,u,1,4>: Cost 2 vext1 <1,1,1,1>, RHS
- 2581262039U, // <1,u,1,5>: Cost 3 vext1 <5,1,u,1>, <5,1,u,1>
- 2587234736U, // <1,u,1,6>: Cost 3 vext1 <6,1,u,1>, <6,1,u,1>
- 2691077979U, // <1,u,1,7>: Cost 3 vext3 <1,1,1,1>, <u,1,7,3>
+ 2620040336U, // <1,u,1,5>: Cost 3 vext2 <0,4,1,u>, <1,5,3,7>
+ 3026622618U, // <1,u,1,6>: Cost 3 vtrnl <1,1,1,1>, RHS
+ 2958183752U, // <1,u,1,7>: Cost 3 vzipr <0,u,1,1>, RHS
202162278U, // <1,u,1,u>: Cost 1 vdup1 LHS
- 2691077996U, // <1,u,2,0>: Cost 3 vext3 <1,1,1,1>, <u,2,0,2>
- 2698893174U, // <1,u,2,1>: Cost 3 vext3 <2,3,u,1>, <u,2,1,3>
- 2635302504U, // <1,u,2,2>: Cost 3 vext2 <3,0,1,u>, <2,2,2,2>
- 2886961302U, // <1,u,2,3>: Cost 3 vzipl LHS, <3,0,1,2>
- 2575297535U, // <1,u,2,4>: Cost 3 vext1 <4,1,u,2>, <4,1,u,2>
- 3004384150U, // <1,u,2,5>: Cost 3 vzipr RHS, <1,2,3,0>
- 2587242929U, // <1,u,2,6>: Cost 3 vext1 <6,1,u,2>, <6,1,u,2>
- 2691078060U, // <1,u,2,7>: Cost 3 vext3 <1,1,1,1>, <u,2,7,3>
- 2887002262U, // <1,u,2,u>: Cost 3 vzipl LHS, <3,0,1,2>
+ 2819449750U, // <1,u,2,0>: Cost 3 vuzpr LHS, <1,2,3,0>
+ 2893207342U, // <1,u,2,1>: Cost 3 vzipl <1,2,3,0>, LHS
+ 2819448996U, // <1,u,2,2>: Cost 3 vuzpr LHS, <0,2,0,2>
+ 2819450482U, // <1,u,2,3>: Cost 3 vuzpr LHS, <2,2,3,3>
+ 2819449754U, // <1,u,2,4>: Cost 3 vuzpr LHS, <1,2,3,4>
+ 2893207706U, // <1,u,2,5>: Cost 3 vzipl <1,2,3,0>, RHS
+ 2819449036U, // <1,u,2,6>: Cost 3 vuzpr LHS, <0,2,4,6>
+ 2970799432U, // <1,u,2,7>: Cost 3 vzipr <3,0,1,2>, RHS
+ 2819449002U, // <1,u,2,u>: Cost 3 vuzpr LHS, <0,2,0,u>
403931292U, // <1,u,3,0>: Cost 1 vext1 LHS, LHS
1477673718U, // <1,u,3,1>: Cost 2 vext1 LHS, <1,0,3,2>
115726126U, // <1,u,3,2>: Cost 1 vrev LHS
- 1477675158U, // <1,u,3,3>: Cost 2 vext1 LHS, <3,0,1,2>
+ 2014102173U, // <1,u,3,3>: Cost 2 vtrnr LHS, LHS
403934518U, // <1,u,3,4>: Cost 1 vext1 LHS, RHS
- 1477676752U, // <1,u,3,5>: Cost 2 vext1 LHS, <5,1,7,3>
- 1477677562U, // <1,u,3,6>: Cost 2 vext1 LHS, <6,2,7,3>
- 1975853158U, // <1,u,3,7>: Cost 2 vtrnl RHS, LHS
+ 1507536601U, // <1,u,3,5>: Cost 2 vext1 <5,1,u,3>, <5,1,u,3>
+ 1525453306U, // <1,u,3,6>: Cost 2 vext1 LHS, <6,2,7,3>
+ 2014105129U, // <1,u,3,7>: Cost 2 vtrnr LHS, RHS
403937070U, // <1,u,3,u>: Cost 1 vext1 LHS, LHS
- 2635303826U, // <1,u,4,0>: Cost 3 vext2 <3,0,1,u>, <4,0,5,1>
- 2724845594U, // <1,u,4,1>: Cost 3 vext3 <6,7,0,1>, <u,4,1,5>
- 2724845604U, // <1,u,4,2>: Cost 3 vext3 <6,7,0,1>, <u,4,2,6>
- 2599201572U, // <1,u,4,3>: Cost 3 vext1 <u,1,u,4>, <3,u,1,u>
- 2659192016U, // <1,u,4,4>: Cost 3 vext2 <7,0,1,u>, <4,4,4,4>
- 1561562422U, // <1,u,4,5>: Cost 2 vext2 <3,0,1,u>, RHS
- 2635304268U, // <1,u,4,6>: Cost 3 vext2 <3,0,1,u>, <4,6,0,2>
+ 2620042157U, // <1,u,4,0>: Cost 3 vext2 <0,4,1,u>, <4,0,u,1>
+ 2620042237U, // <1,u,4,1>: Cost 3 vext2 <0,4,1,u>, <4,1,u,0>
+ 2263217967U, // <1,u,4,2>: Cost 3 vrev <u,1,2,4>
+ 2569341224U, // <1,u,4,3>: Cost 3 vext1 <3,1,u,4>, <3,1,u,4>
+ 2569342262U, // <1,u,4,4>: Cost 3 vext1 <3,1,u,4>, RHS
+ 1546300726U, // <1,u,4,5>: Cost 2 vext2 <0,4,1,u>, RHS
+ 2819449180U, // <1,u,4,6>: Cost 3 vuzpr LHS, <0,4,2,6>
2724845649U, // <1,u,4,7>: Cost 3 vext3 <6,7,0,1>, <u,4,7,6>
- 1561562665U, // <1,u,4,u>: Cost 2 vext2 <3,0,1,u>, RHS
- 2557403238U, // <1,u,5,0>: Cost 3 vext1 <1,1,u,5>, LHS
- 2557404023U, // <1,u,5,1>: Cost 3 vext1 <1,1,u,5>, <1,1,u,5>
- 2648575728U, // <1,u,5,2>: Cost 3 vext2 <5,2,1,u>, <5,2,1,u>
- 2724845695U, // <1,u,5,3>: Cost 3 vext3 <6,7,0,1>, <u,5,3,7>
- 2557406518U, // <1,u,5,4>: Cost 3 vext1 <1,1,u,5>, RHS
- 2581294811U, // <1,u,5,5>: Cost 3 vext1 <5,1,u,5>, <5,1,u,5>
- 1617336474U, // <1,u,5,6>: Cost 2 vext3 <1,1,1,1>, RHS
- 2913534290U, // <1,u,5,7>: Cost 3 vzipl RHS, <0,4,1,5>
- 1617336492U, // <1,u,5,u>: Cost 2 vext3 <1,1,1,1>, RHS
- 2691078320U, // <1,u,6,0>: Cost 3 vext3 <1,1,1,1>, <u,6,0,2>
+ 1546300969U, // <1,u,4,u>: Cost 2 vext2 <0,4,1,u>, RHS
+ 2551431270U, // <1,u,5,0>: Cost 3 vext1 <0,1,u,5>, LHS
+ 2551432192U, // <1,u,5,1>: Cost 3 vext1 <0,1,u,5>, <1,3,5,7>
+ 3028293422U, // <1,u,5,2>: Cost 3 vtrnl <1,3,5,7>, LHS
+ 2955559068U, // <1,u,5,3>: Cost 3 vzipr <0,4,1,5>, LHS
+ 2551434550U, // <1,u,5,4>: Cost 3 vext1 <0,1,u,5>, RHS
+ 2895255706U, // <1,u,5,5>: Cost 3 vzipl <1,5,3,7>, RHS
+ 1616009370U, // <1,u,5,6>: Cost 2 vext3 <0,u,1,1>, RHS
+ 1745710390U, // <1,u,5,7>: Cost 2 vuzpr LHS, RHS
+ 1745710391U, // <1,u,5,u>: Cost 2 vuzpr LHS, RHS
+ 2653221159U, // <1,u,6,0>: Cost 3 vext2 <6,0,1,u>, <6,0,1,u>
2725509303U, // <1,u,6,1>: Cost 3 vext3 <6,u,0,1>, <u,6,1,0>
- 2635305466U, // <1,u,6,2>: Cost 3 vext2 <3,0,1,u>, <6,2,7,3>
- 2724845776U, // <1,u,6,3>: Cost 3 vext3 <6,7,0,1>, <u,6,3,7>
- 2724845784U, // <1,u,6,4>: Cost 3 vext3 <6,7,0,1>, <u,6,4,6>
- 3714355952U, // <1,u,6,5>: Cost 4 vext2 <3,u,1,u>, <6,5,7,6>
- 2659193656U, // <1,u,6,6>: Cost 3 vext2 <7,0,1,u>, <6,6,6,6>
- 2724845805U, // <1,u,6,7>: Cost 3 vext3 <6,7,0,1>, <u,6,7,0>
- 2635305952U, // <1,u,6,u>: Cost 3 vext2 <3,0,1,u>, <6,u,7,3>
+ 2659193338U, // <1,u,6,2>: Cost 3 vext2 <7,0,1,u>, <6,2,7,3>
+ 2689751248U, // <1,u,6,3>: Cost 3 vext3 <0,u,1,1>, <u,6,3,7>
+ 2867228774U, // <1,u,6,4>: Cost 3 vuzpr LHS, <5,6,7,4>
+ 3764820194U, // <1,u,6,5>: Cost 4 vext3 <1,1,1,1>, <u,6,5,7>
+ 2657202957U, // <1,u,6,6>: Cost 3 vext2 <6,6,1,u>, <6,6,1,u>
+ 2819450810U, // <1,u,6,7>: Cost 3 vuzpr LHS, <2,6,3,7>
+ 2819450811U, // <1,u,6,u>: Cost 3 vuzpr LHS, <2,6,3,u>
1585452032U, // <1,u,7,0>: Cost 2 vext2 <7,0,1,u>, <7,0,1,u>
- 2659857489U, // <1,u,7,1>: Cost 3 vext2 <7,1,1,u>, <7,1,1,u>
- 2263242546U, // <1,u,7,2>: Cost 3 vrev <u,1,2,7>
- 2635257059U, // <1,u,7,3>: Cost 3 vext2 <3,0,1,2>, <7,3,0,1>
- 2724845864U, // <1,u,7,4>: Cost 3 vext3 <6,7,0,1>, <u,7,4,5>
+ 2557420340U, // <1,u,7,1>: Cost 3 vext1 <1,1,u,7>, <1,1,1,1>
+ 2569365158U, // <1,u,7,2>: Cost 3 vext1 <3,1,u,7>, <2,3,0,1>
+ 2569365803U, // <1,u,7,3>: Cost 3 vext1 <3,1,u,7>, <3,1,u,7>
+ 2557422902U, // <1,u,7,4>: Cost 3 vext1 <1,1,u,7>, RHS
2662512021U, // <1,u,7,5>: Cost 3 vext2 <7,5,1,u>, <7,5,1,u>
2724845884U, // <1,u,7,6>: Cost 3 vext3 <6,7,0,1>, <u,7,6,7>
2659194476U, // <1,u,7,7>: Cost 3 vext2 <7,0,1,u>, <7,7,7,7>
@@ -1473,1102 +1473,1102 @@ static const unsigned PerfectShuffleTable[6561+1] = {
403972257U, // <1,u,u,0>: Cost 1 vext1 LHS, LHS
202162278U, // <1,u,u,1>: Cost 1 vdup1 LHS
115767091U, // <1,u,u,2>: Cost 1 vrev LHS
- 1477716118U, // <1,u,u,3>: Cost 2 vext1 LHS, <3,0,1,2>
+ 1745707677U, // <1,u,u,3>: Cost 2 vuzpr LHS, LHS
403975478U, // <1,u,u,4>: Cost 1 vext1 LHS, RHS
- 1477717712U, // <1,u,u,5>: Cost 2 vext1 LHS, <5,1,7,3>
- 1477718522U, // <1,u,u,6>: Cost 2 vext1 LHS, <6,2,7,3>
- 1975853163U, // <1,u,u,7>: Cost 2 vtrnl RHS, LHS
+ 1546303642U, // <1,u,u,5>: Cost 2 vext2 <0,4,1,u>, RHS
+ 1616009613U, // <1,u,u,6>: Cost 2 vext3 <0,u,1,1>, RHS
+ 1745710633U, // <1,u,u,7>: Cost 2 vuzpr LHS, RHS
403978030U, // <1,u,u,u>: Cost 1 vext1 LHS, LHS
- 2685698048U, // <2,0,0,0>: Cost 3 vext3 <0,2,0,2>, <0,0,0,0>
+ 2551463936U, // <2,0,0,0>: Cost 3 vext1 <0,2,0,0>, <0,0,0,0>
2685698058U, // <2,0,0,1>: Cost 3 vext3 <0,2,0,2>, <0,0,1,1>
1610776596U, // <2,0,0,2>: Cost 2 vext3 <0,0,2,2>, <0,0,2,2>
2619384069U, // <2,0,0,3>: Cost 3 vext2 <0,3,2,0>, <0,3,2,0>
- 2563411254U, // <2,0,0,4>: Cost 3 vext1 <2,2,0,0>, RHS
- 3637153488U, // <2,0,0,5>: Cost 4 vext1 <2,2,0,0>, <5,1,7,3>
+ 2551467318U, // <2,0,0,4>: Cost 3 vext1 <0,2,0,0>, RHS
+ 3899836596U, // <2,0,0,5>: Cost 4 vuzpr <1,2,3,0>, <3,0,4,5>
2621374968U, // <2,0,0,6>: Cost 3 vext2 <0,6,2,0>, <0,6,2,0>
- 3732939321U, // <2,0,0,7>: Cost 4 vext2 <7,0,2,0>, <0,7,0,2>
+ 4168271334U, // <2,0,0,7>: Cost 4 vtrnr <1,2,3,0>, <2,0,5,7>
1611219018U, // <2,0,0,u>: Cost 2 vext3 <0,0,u,2>, <0,0,u,2>
- 2569388134U, // <2,0,1,0>: Cost 3 vext1 <3,2,0,1>, LHS
- 2569388790U, // <2,0,1,1>: Cost 3 vext1 <3,2,0,1>, <1,0,3,2>
+ 2551472138U, // <2,0,1,0>: Cost 3 vext1 <0,2,0,1>, <0,0,1,1>
+ 2690564186U, // <2,0,1,1>: Cost 3 vext3 <1,0,3,2>, <0,1,1,0>
1611956326U, // <2,0,1,2>: Cost 2 vext3 <0,2,0,2>, LHS
- 2569390382U, // <2,0,1,3>: Cost 3 vext1 <3,2,0,1>, <3,2,0,1>
- 2569391414U, // <2,0,1,4>: Cost 3 vext1 <3,2,0,1>, RHS
- 3290038480U, // <2,0,1,5>: Cost 4 vrev <0,2,5,1>
+ 2826092646U, // <2,0,1,3>: Cost 3 vuzpr <1,2,3,0>, LHS
+ 2551475510U, // <2,0,1,4>: Cost 3 vext1 <0,2,0,1>, RHS
+ 3692463248U, // <2,0,1,5>: Cost 4 vext2 <0,2,2,0>, <1,5,3,7>
2587308473U, // <2,0,1,6>: Cost 3 vext1 <6,2,0,1>, <6,2,0,1>
3661050874U, // <2,0,1,7>: Cost 4 vext1 <6,2,0,1>, <7,0,1,2>
1611956380U, // <2,0,1,u>: Cost 2 vext3 <0,2,0,2>, LHS
1477738598U, // <2,0,2,0>: Cost 2 vext1 <0,2,0,2>, LHS
- 2953627240U, // <2,0,2,1>: Cost 3 vzipr LHS, <2,2,2,2>
- 3087844968U, // <2,0,2,2>: Cost 3 vtrnr LHS, <2,2,2,2>
+ 2551481078U, // <2,0,2,1>: Cost 3 vext1 <0,2,0,2>, <1,0,3,2>
+ 2551481796U, // <2,0,2,2>: Cost 3 vext1 <0,2,0,2>, <2,0,2,0>
2551482518U, // <2,0,2,3>: Cost 3 vext1 <0,2,0,2>, <3,0,1,2>
1477741878U, // <2,0,2,4>: Cost 2 vext1 <0,2,0,2>, RHS
2551484112U, // <2,0,2,5>: Cost 3 vext1 <0,2,0,2>, <5,1,7,3>
- 2551484922U, // <2,0,2,6>: Cost 3 vext1 <0,2,0,2>, <6,2,7,3>
- 2599261178U, // <2,0,2,7>: Cost 3 vext1 <u,2,0,2>, <7,0,1,2>
+ 2551484759U, // <2,0,2,6>: Cost 3 vext1 <0,2,0,2>, <6,0,7,2>
+ 2551485434U, // <2,0,2,7>: Cost 3 vext1 <0,2,0,2>, <7,0,1,2>
1477744430U, // <2,0,2,u>: Cost 2 vext1 <0,2,0,2>, LHS
- 2551488512U, // <2,0,3,0>: Cost 3 vext1 <0,2,0,3>, <0,0,0,0>
+ 2953625600U, // <2,0,3,0>: Cost 3 vzipr LHS, <0,0,0,0>
2953627302U, // <2,0,3,1>: Cost 3 vzipr LHS, <2,3,0,1>
- 3087844978U, // <2,0,3,2>: Cost 3 vtrnr LHS, <2,2,3,3>
- 2569406768U, // <2,0,3,3>: Cost 3 vext1 <3,2,0,3>, <3,2,0,3>
- 2551491894U, // <2,0,3,4>: Cost 3 vext1 <0,2,0,3>, RHS
- 3625234128U, // <2,0,3,5>: Cost 4 vext1 <0,2,0,3>, <5,1,7,3>
- 3625234938U, // <2,0,3,6>: Cost 4 vext1 <0,2,0,3>, <6,2,7,3>
- 3998629990U, // <2,0,3,7>: Cost 4 vzipl <6,5,0,7>, LHS
- 3088287346U, // <2,0,3,u>: Cost 3 vtrnr LHS, <2,2,3,3>
- 2687025478U, // <2,0,4,0>: Cost 3 vext3 <0,4,0,2>, <0,4,0,2>
- 2712240466U, // <2,0,4,1>: Cost 3 vext3 <4,6,0,2>, <0,4,1,5>
- 3087845070U, // <2,0,4,2>: Cost 3 vtrnr LHS, <2,3,4,5>
- 3289915585U, // <2,0,4,3>: Cost 4 vrev <0,2,3,4>
- 3637185846U, // <2,0,4,4>: Cost 4 vext1 <2,2,0,4>, RHS
- 2629340470U, // <2,0,4,5>: Cost 3 vext2 <2,0,2,0>, RHS
- 2846279334U, // <2,0,4,6>: Cost 3 vuzpr RHS, <2,3,0,1>
- 3667047573U, // <2,0,4,7>: Cost 4 vext1 <7,2,0,4>, <7,2,0,4>
- 3088287438U, // <2,0,4,u>: Cost 3 vtrnr LHS, <2,3,4,5>
- 4162094889U, // <2,0,5,0>: Cost 4 vtrnr <0,2,0,2>, <2,4,5,6>
- 3703082704U, // <2,0,5,1>: Cost 4 vext2 <2,0,2,0>, <5,1,7,3>
- 2684518830U, // <2,0,5,2>: Cost 3 vext3 <0,0,2,2>, <0,5,2,7>
- 3719008112U, // <2,0,5,3>: Cost 4 vext2 <4,6,2,0>, <5,3,7,1>
+ 2953625764U, // <2,0,3,2>: Cost 3 vzipr LHS, <0,2,0,2>
+ 4027369695U, // <2,0,3,3>: Cost 4 vzipr LHS, <3,1,0,3>
+ 3625233718U, // <2,0,3,4>: Cost 4 vext1 <0,2,0,3>, RHS
+ 3899836110U, // <2,0,3,5>: Cost 4 vuzpr <1,2,3,0>, <2,3,4,5>
+ 4032012618U, // <2,0,3,6>: Cost 4 vzipr LHS, <0,4,0,6>
+ 3899835392U, // <2,0,3,7>: Cost 4 vuzpr <1,2,3,0>, <1,3,5,7>
+ 2953625770U, // <2,0,3,u>: Cost 3 vzipr LHS, <0,2,0,u>
+ 2551496806U, // <2,0,4,0>: Cost 3 vext1 <0,2,0,4>, LHS
+ 2685698386U, // <2,0,4,1>: Cost 3 vext3 <0,2,0,2>, <0,4,1,5>
+ 2685698396U, // <2,0,4,2>: Cost 3 vext3 <0,2,0,2>, <0,4,2,6>
+ 3625240726U, // <2,0,4,3>: Cost 4 vext1 <0,2,0,4>, <3,0,1,2>
+ 2551500086U, // <2,0,4,4>: Cost 3 vext1 <0,2,0,4>, RHS
+ 2618723638U, // <2,0,4,5>: Cost 3 vext2 <0,2,2,0>, RHS
+ 2765409590U, // <2,0,4,6>: Cost 3 vuzpl <2,3,0,1>, RHS
+ 3799990664U, // <2,0,4,7>: Cost 4 vext3 <7,0,1,2>, <0,4,7,5>
+ 2685698450U, // <2,0,4,u>: Cost 3 vext3 <0,2,0,2>, <0,4,u,6>
+ 3625246822U, // <2,0,5,0>: Cost 4 vext1 <0,2,0,5>, LHS
+ 3289776304U, // <2,0,5,1>: Cost 4 vrev <0,2,1,5>
+ 2690564526U, // <2,0,5,2>: Cost 3 vext3 <1,0,3,2>, <0,5,2,7>
+ 3289923778U, // <2,0,5,3>: Cost 4 vrev <0,2,3,5>
2216255691U, // <2,0,5,4>: Cost 3 vrev <0,2,4,5>
- 3719008260U, // <2,0,5,5>: Cost 4 vext2 <4,6,2,0>, <5,5,5,5>
- 3719008354U, // <2,0,5,6>: Cost 4 vext2 <4,6,2,0>, <5,6,7,0>
- 3923379878U, // <2,0,5,7>: Cost 4 vuzpr <5,1,7,3>, <2,3,0,1>
+ 3726307332U, // <2,0,5,5>: Cost 4 vext2 <5,u,2,0>, <5,5,5,5>
+ 3726307426U, // <2,0,5,6>: Cost 4 vext2 <5,u,2,0>, <5,6,7,0>
+ 2826095926U, // <2,0,5,7>: Cost 3 vuzpr <1,2,3,0>, RHS
2216550639U, // <2,0,5,u>: Cost 3 vrev <0,2,u,5>
- 2653229352U, // <2,0,6,0>: Cost 3 vext2 <6,0,2,0>, <6,0,2,0>
- 2953627578U, // <2,0,6,1>: Cost 3 vzipr LHS, <2,6,3,7>
- 2708701688U, // <2,0,6,2>: Cost 3 vext3 <4,0,6,2>, <0,6,2,0>
- 3782443525U, // <2,0,6,3>: Cost 4 vext3 <4,0,6,2>, <0,6,3,4>
- 2655883884U, // <2,0,6,4>: Cost 3 vext2 <6,4,2,0>, <6,4,2,0>
- 3726971588U, // <2,0,6,5>: Cost 4 vext2 <6,0,2,0>, <6,5,2,7>
- 3719009080U, // <2,0,6,6>: Cost 4 vext2 <4,6,2,0>, <6,6,6,6>
- 3719009102U, // <2,0,6,7>: Cost 4 vext2 <4,6,2,0>, <6,7,0,1>
- 2653229352U, // <2,0,6,u>: Cost 3 vext2 <6,0,2,0>, <6,0,2,0>
+ 4162420736U, // <2,0,6,0>: Cost 4 vtrnr <0,2,4,6>, <0,0,0,0>
+ 2901885030U, // <2,0,6,1>: Cost 3 vzipl <2,6,3,7>, LHS
+ 2685698559U, // <2,0,6,2>: Cost 3 vext3 <0,2,0,2>, <0,6,2,7>
+ 3643173171U, // <2,0,6,3>: Cost 4 vext1 <3,2,0,6>, <3,2,0,6>
+ 2216263884U, // <2,0,6,4>: Cost 3 vrev <0,2,4,6>
+ 3730289341U, // <2,0,6,5>: Cost 4 vext2 <6,5,2,0>, <6,5,2,0>
+ 3726308152U, // <2,0,6,6>: Cost 4 vext2 <5,u,2,0>, <6,6,6,6>
+ 3899836346U, // <2,0,6,7>: Cost 4 vuzpr <1,2,3,0>, <2,6,3,7>
+ 2216558832U, // <2,0,6,u>: Cost 3 vrev <0,2,u,6>
2659202049U, // <2,0,7,0>: Cost 3 vext2 <7,0,2,0>, <7,0,2,0>
- 3934209702U, // <2,0,7,1>: Cost 4 vuzpr <7,0,1,2>, <2,3,0,1>
+ 3726308437U, // <2,0,7,1>: Cost 4 vext2 <5,u,2,0>, <7,1,2,3>
2726249034U, // <2,0,7,2>: Cost 3 vext3 <7,0,1,2>, <0,7,2,1>
- 3935667878U, // <2,0,7,3>: Cost 4 vuzpr <7,2,3,0>, <2,3,0,1>
- 3719009638U, // <2,0,7,4>: Cost 4 vext2 <4,6,2,0>, <7,4,5,6>
- 3937191590U, // <2,0,7,5>: Cost 4 vuzpr <7,4,5,6>, <2,3,0,1>
+ 3734934772U, // <2,0,7,3>: Cost 4 vext2 <7,3,2,0>, <7,3,2,0>
+ 3726308710U, // <2,0,7,4>: Cost 4 vext2 <5,u,2,0>, <7,4,5,6>
+ 3726308814U, // <2,0,7,5>: Cost 4 vext2 <5,u,2,0>, <7,5,u,2>
3736925671U, // <2,0,7,6>: Cost 4 vext2 <7,6,2,0>, <7,6,2,0>
- 3719009900U, // <2,0,7,7>: Cost 4 vext2 <4,6,2,0>, <7,7,7,7>
- 2664511113U, // <2,0,7,u>: Cost 3 vext2 <7,u,2,0>, <7,u,2,0>
+ 3726308972U, // <2,0,7,7>: Cost 4 vext2 <5,u,2,0>, <7,7,7,7>
+ 2659202049U, // <2,0,7,u>: Cost 3 vext2 <7,0,2,0>, <7,0,2,0>
1477787750U, // <2,0,u,0>: Cost 2 vext1 <0,2,0,u>, LHS
- 2953668667U, // <2,0,u,1>: Cost 3 vzipr LHS, <2,u,0,1>
+ 2953668262U, // <2,0,u,1>: Cost 3 vzipr LHS, <2,3,0,1>
1611956893U, // <2,0,u,2>: Cost 2 vext3 <0,2,0,2>, LHS
2551531670U, // <2,0,u,3>: Cost 3 vext1 <0,2,0,u>, <3,0,1,2>
1477791030U, // <2,0,u,4>: Cost 2 vext1 <0,2,0,u>, RHS
- 2551533264U, // <2,0,u,5>: Cost 3 vext1 <0,2,0,u>, <5,1,7,3>
- 2551534074U, // <2,0,u,6>: Cost 3 vext1 <0,2,0,u>, <6,2,7,3>
- 2599310330U, // <2,0,u,7>: Cost 3 vext1 <u,2,0,u>, <7,0,1,2>
+ 2618726554U, // <2,0,u,5>: Cost 3 vext2 <0,2,2,0>, RHS
+ 2765412506U, // <2,0,u,6>: Cost 3 vuzpl <2,3,0,1>, RHS
+ 2826096169U, // <2,0,u,7>: Cost 3 vuzpr <1,2,3,0>, RHS
1611956947U, // <2,0,u,u>: Cost 2 vext3 <0,2,0,2>, LHS
- 2690564826U, // <2,1,0,0>: Cost 3 vext3 <1,0,3,2>, <1,0,0,1>
- 2690417380U, // <2,1,0,1>: Cost 3 vext3 <1,0,1,2>, <1,0,1,2>
- 2617401508U, // <2,1,0,2>: Cost 3 vext2 <0,0,2,1>, <0,2,0,2>
+ 2569453670U, // <2,1,0,0>: Cost 3 vext1 <3,2,1,0>, LHS
+ 2619392102U, // <2,1,0,1>: Cost 3 vext2 <0,3,2,1>, LHS
+ 3759440619U, // <2,1,0,2>: Cost 4 vext3 <0,2,0,2>, <1,0,2,0>
1616823030U, // <2,1,0,3>: Cost 2 vext3 <1,0,3,2>, <1,0,3,2>
2569456950U, // <2,1,0,4>: Cost 3 vext1 <3,2,1,0>, RHS
- 3643199184U, // <2,1,0,5>: Cost 4 vext1 <3,2,1,0>, <5,1,7,3>
- 3643199994U, // <2,1,0,6>: Cost 4 vext1 <3,2,1,0>, <6,2,7,3>
+ 2690712328U, // <2,1,0,5>: Cost 3 vext3 <1,0,5,2>, <1,0,5,2>
+ 3661115841U, // <2,1,0,6>: Cost 4 vext1 <6,2,1,0>, <6,2,1,0>
2622046794U, // <2,1,0,7>: Cost 3 vext2 <0,7,2,1>, <0,7,2,1>
1617191715U, // <2,1,0,u>: Cost 2 vext3 <1,0,u,2>, <1,0,u,2>
- 2623374060U, // <2,1,1,0>: Cost 3 vext2 <1,0,2,1>, <1,0,2,1>
+ 2551545958U, // <2,1,1,0>: Cost 3 vext1 <0,2,1,1>, LHS
2685698868U, // <2,1,1,1>: Cost 3 vext3 <0,2,0,2>, <1,1,1,1>
- 2623374230U, // <2,1,1,2>: Cost 3 vext2 <1,0,2,1>, <1,2,3,0>
+ 2628682646U, // <2,1,1,2>: Cost 3 vext2 <1,u,2,1>, <1,2,3,0>
2685698888U, // <2,1,1,3>: Cost 3 vext3 <0,2,0,2>, <1,1,3,3>
- 3625291062U, // <2,1,1,4>: Cost 4 vext1 <0,2,1,1>, RHS
- 3726976144U, // <2,1,1,5>: Cost 4 vext2 <6,0,2,1>, <1,5,3,7>
- 3765191522U, // <2,1,1,6>: Cost 4 vext3 <1,1,6,2>, <1,1,6,2>
- 3296158651U, // <2,1,1,7>: Cost 4 vrev <1,2,7,1>
+ 2551549238U, // <2,1,1,4>: Cost 3 vext1 <0,2,1,1>, RHS
+ 3693134992U, // <2,1,1,5>: Cost 4 vext2 <0,3,2,1>, <1,5,3,7>
+ 3661124034U, // <2,1,1,6>: Cost 4 vext1 <6,2,1,1>, <6,2,1,1>
+ 3625292794U, // <2,1,1,7>: Cost 4 vext1 <0,2,1,1>, <7,0,1,2>
2685698933U, // <2,1,1,u>: Cost 3 vext3 <0,2,0,2>, <1,1,u,3>
- 2629346757U, // <2,1,2,0>: Cost 3 vext2 <2,0,2,1>, <2,0,2,1>
- 3759440775U, // <2,1,2,1>: Cost 4 vext3 <0,2,0,2>, <1,2,1,3>
- 2629346920U, // <2,1,2,2>: Cost 3 vext2 <2,0,2,1>, <2,2,2,2>
- 3020734628U, // <2,1,2,3>: Cost 3 vtrnl LHS, <0,2,0,2>
- 2702361508U, // <2,1,2,4>: Cost 3 vext3 <3,0,1,2>, <1,2,4,5>
- 3776103337U, // <2,1,2,5>: Cost 4 vext3 <3,0,1,2>, <1,2,5,1>
- 3776103347U, // <2,1,2,6>: Cost 4 vext3 <3,0,1,2>, <1,2,6,2>
+ 2551554150U, // <2,1,2,0>: Cost 3 vext1 <0,2,1,2>, LHS
+ 3893649571U, // <2,1,2,1>: Cost 4 vuzpr <0,2,0,1>, <0,2,0,1>
+ 2551555688U, // <2,1,2,2>: Cost 3 vext1 <0,2,1,2>, <2,2,2,2>
+ 2685698966U, // <2,1,2,3>: Cost 3 vext3 <0,2,0,2>, <1,2,3,0>
+ 2551557430U, // <2,1,2,4>: Cost 3 vext1 <0,2,1,2>, RHS
+ 3763422123U, // <2,1,2,5>: Cost 4 vext3 <0,u,0,2>, <1,2,5,3>
+ 3693135802U, // <2,1,2,6>: Cost 4 vext2 <0,3,2,1>, <2,6,3,7>
2726249402U, // <2,1,2,7>: Cost 3 vext3 <7,0,1,2>, <1,2,7,0>
- 3020775588U, // <2,1,2,u>: Cost 3 vtrnl LHS, <0,2,0,2>
+ 2685699011U, // <2,1,2,u>: Cost 3 vext3 <0,2,0,2>, <1,2,u,0>
2551562342U, // <2,1,3,0>: Cost 3 vext1 <0,2,1,3>, LHS
- 2892398694U, // <2,1,3,1>: Cost 3 vzipl <1,1,1,1>, LHS
- 2551563942U, // <2,1,3,2>: Cost 3 vext1 <0,2,1,3>, <2,3,0,1>
- 3020736114U, // <2,1,3,3>: Cost 3 vtrnl LHS, <2,2,3,3>
+ 2953625610U, // <2,1,3,1>: Cost 3 vzipr LHS, <0,0,1,1>
+ 2953627798U, // <2,1,3,2>: Cost 3 vzipr LHS, <3,0,1,2>
+ 2953626584U, // <2,1,3,3>: Cost 3 vzipr LHS, <1,3,1,3>
2551565622U, // <2,1,3,4>: Cost 3 vext1 <0,2,1,3>, RHS
- 2581425899U, // <2,1,3,5>: Cost 3 vext1 <5,2,1,3>, <5,2,1,3>
- 3625308666U, // <2,1,3,6>: Cost 4 vext1 <0,2,1,3>, <6,2,7,3>
- 3980787814U, // <2,1,3,7>: Cost 4 vzipl <3,5,1,7>, LHS
- 3020777074U, // <2,1,3,u>: Cost 3 vtrnl LHS, <2,2,3,3>
- 3697118098U, // <2,1,4,0>: Cost 4 vext2 <1,0,2,1>, <4,0,5,1>
- 4100359066U, // <2,1,4,1>: Cost 4 vtrnl <1,1,1,1>, <1,2,3,4>
- 3977429095U, // <2,1,4,2>: Cost 4 vzipl <3,0,1,2>, <0,1,2,4>
+ 2953625938U, // <2,1,3,5>: Cost 3 vzipr LHS, <0,4,1,5>
+ 2587398596U, // <2,1,3,6>: Cost 3 vext1 <6,2,1,3>, <6,2,1,3>
+ 4032013519U, // <2,1,3,7>: Cost 4 vzipr LHS, <1,6,1,7>
+ 2953625617U, // <2,1,3,u>: Cost 3 vzipr LHS, <0,0,1,u>
+ 2690565154U, // <2,1,4,0>: Cost 3 vext3 <1,0,3,2>, <1,4,0,5>
+ 3625313270U, // <2,1,4,1>: Cost 4 vext1 <0,2,1,4>, <1,3,4,6>
+ 3771532340U, // <2,1,4,2>: Cost 4 vext3 <2,2,2,2>, <1,4,2,5>
1148404634U, // <2,1,4,3>: Cost 2 vrev <1,2,3,4>
- 3643231542U, // <2,1,4,4>: Cost 4 vext1 <3,2,1,4>, RHS
- 2623376694U, // <2,1,4,5>: Cost 3 vext2 <1,0,2,1>, RHS
- 3697118540U, // <2,1,4,6>: Cost 4 vext2 <1,0,2,1>, <4,6,0,2>
- 3667121310U, // <2,1,4,7>: Cost 4 vext1 <7,2,1,4>, <7,2,1,4>
+ 3625315638U, // <2,1,4,4>: Cost 4 vext1 <0,2,1,4>, RHS
+ 2619395382U, // <2,1,4,5>: Cost 3 vext2 <0,3,2,1>, RHS
+ 3837242678U, // <2,1,4,6>: Cost 4 vuzpl <2,0,1,2>, RHS
+ 3799991394U, // <2,1,4,7>: Cost 4 vext3 <7,0,1,2>, <1,4,7,6>
1148773319U, // <2,1,4,u>: Cost 2 vrev <1,2,u,4>
- 3643236454U, // <2,1,5,0>: Cost 4 vext1 <3,2,1,5>, LHS
- 3697118928U, // <2,1,5,1>: Cost 4 vext2 <1,0,2,1>, <5,1,7,3>
- 3643238099U, // <2,1,5,2>: Cost 4 vext1 <3,2,1,5>, <2,3,5,1>
- 2712241296U, // <2,1,5,3>: Cost 3 vext3 <4,6,0,2>, <1,5,3,7>
- 2222228388U, // <2,1,5,4>: Cost 3 vrev <1,2,4,5>
- 3643240144U, // <2,1,5,5>: Cost 4 vext1 <3,2,1,5>, <5,1,7,3>
- 3726979170U, // <2,1,5,6>: Cost 4 vext2 <6,0,2,1>, <5,6,7,0>
- 3631297530U, // <2,1,5,7>: Cost 4 vext1 <1,2,1,5>, <7,0,1,2>
- 2222523336U, // <2,1,5,u>: Cost 3 vrev <1,2,u,5>
- 2653237545U, // <2,1,6,0>: Cost 3 vext2 <6,0,2,1>, <6,0,2,1>
- 3785983183U, // <2,1,6,1>: Cost 4 vext3 <4,6,0,2>, <1,6,1,7>
- 2653237754U, // <2,1,6,2>: Cost 3 vext2 <6,0,2,1>, <6,2,7,3>
- 3068510412U, // <2,1,6,3>: Cost 3 vtrnl LHS, <0,2,4,6>
- 3726979697U, // <2,1,6,4>: Cost 4 vext2 <6,0,2,1>, <6,4,2,5>
- 3785983220U, // <2,1,6,5>: Cost 4 vext3 <4,6,0,2>, <1,6,5,u>
- 3726979896U, // <2,1,6,6>: Cost 4 vext2 <6,0,2,1>, <6,6,6,6>
- 3726979918U, // <2,1,6,7>: Cost 4 vext2 <6,0,2,1>, <6,7,0,1>
- 2222531529U, // <2,1,6,u>: Cost 3 vrev <1,2,u,6>
+ 2551578726U, // <2,1,5,0>: Cost 3 vext1 <0,2,1,5>, LHS
+ 2551579648U, // <2,1,5,1>: Cost 3 vext1 <0,2,1,5>, <1,3,5,7>
+ 3625321952U, // <2,1,5,2>: Cost 4 vext1 <0,2,1,5>, <2,0,5,1>
+ 2685699216U, // <2,1,5,3>: Cost 3 vext3 <0,2,0,2>, <1,5,3,7>
+ 2551582006U, // <2,1,5,4>: Cost 3 vext1 <0,2,1,5>, RHS
+ 3740913668U, // <2,1,5,5>: Cost 4 vext2 <u,3,2,1>, <5,5,5,5>
+ 3661156806U, // <2,1,5,6>: Cost 4 vext1 <6,2,1,5>, <6,2,1,5>
+ 3893652790U, // <2,1,5,7>: Cost 4 vuzpr <0,2,0,1>, RHS
+ 2685699261U, // <2,1,5,u>: Cost 3 vext3 <0,2,0,2>, <1,5,u,7>
+ 2551586918U, // <2,1,6,0>: Cost 3 vext1 <0,2,1,6>, LHS
+ 3625329398U, // <2,1,6,1>: Cost 4 vext1 <0,2,1,6>, <1,0,3,2>
+ 2551588794U, // <2,1,6,2>: Cost 3 vext1 <0,2,1,6>, <2,6,3,7>
+ 3088679014U, // <2,1,6,3>: Cost 3 vtrnr <0,2,4,6>, LHS
+ 2551590198U, // <2,1,6,4>: Cost 3 vext1 <0,2,1,6>, RHS
+ 4029382994U, // <2,1,6,5>: Cost 4 vzipr <0,4,2,6>, <0,4,1,5>
+ 3625333560U, // <2,1,6,6>: Cost 4 vext1 <0,2,1,6>, <6,6,6,6>
+ 3731624800U, // <2,1,6,7>: Cost 4 vext2 <6,7,2,1>, <6,7,2,1>
+ 2551592750U, // <2,1,6,u>: Cost 3 vext1 <0,2,1,6>, LHS
2622051322U, // <2,1,7,0>: Cost 3 vext2 <0,7,2,1>, <7,0,1,2>
3733615699U, // <2,1,7,1>: Cost 4 vext2 <7,1,2,1>, <7,1,2,1>
- 3726980271U, // <2,1,7,2>: Cost 4 vext2 <6,0,2,1>, <7,2,3,3>
+ 3795125538U, // <2,1,7,2>: Cost 4 vext3 <6,1,7,2>, <1,7,2,0>
2222171037U, // <2,1,7,3>: Cost 3 vrev <1,2,3,7>
- 3726980454U, // <2,1,7,4>: Cost 4 vext2 <6,0,2,1>, <7,4,5,6>
- 3736270231U, // <2,1,7,5>: Cost 4 vext2 <7,5,2,1>, <7,5,2,1>
- 3726980567U, // <2,1,7,6>: Cost 4 vext2 <6,0,2,1>, <7,6,0,2>
- 3726980716U, // <2,1,7,7>: Cost 4 vext2 <6,0,2,1>, <7,7,7,7>
+ 3740915046U, // <2,1,7,4>: Cost 4 vext2 <u,3,2,1>, <7,4,5,6>
+ 3296060335U, // <2,1,7,5>: Cost 4 vrev <1,2,5,7>
+ 3736933864U, // <2,1,7,6>: Cost 4 vext2 <7,6,2,1>, <7,6,2,1>
+ 3805300055U, // <2,1,7,7>: Cost 4 vext3 <7,u,1,2>, <1,7,7,u>
2669827714U, // <2,1,7,u>: Cost 3 vext2 <u,7,2,1>, <7,u,1,2>
2551603302U, // <2,1,u,0>: Cost 3 vext1 <0,2,1,u>, LHS
- 2623379246U, // <2,1,u,1>: Cost 3 vext2 <1,0,2,1>, LHS
- 2551604902U, // <2,1,u,2>: Cost 3 vext1 <0,2,1,u>, <2,3,0,1>
+ 2953666570U, // <2,1,u,1>: Cost 3 vzipr LHS, <0,0,1,1>
+ 2953668758U, // <2,1,u,2>: Cost 3 vzipr LHS, <3,0,1,2>
1148437406U, // <2,1,u,3>: Cost 2 vrev <1,2,3,u>
2551606582U, // <2,1,u,4>: Cost 3 vext1 <0,2,1,u>, RHS
- 2623379610U, // <2,1,u,5>: Cost 3 vext2 <1,0,2,1>, RHS
- 3625349626U, // <2,1,u,6>: Cost 4 vext1 <0,2,1,u>, <6,2,7,3>
+ 2953666898U, // <2,1,u,5>: Cost 3 vzipr LHS, <0,4,1,5>
+ 2587398596U, // <2,1,u,6>: Cost 3 vext1 <6,2,1,3>, <6,2,1,3>
2669828370U, // <2,1,u,7>: Cost 3 vext2 <u,7,2,1>, <u,7,2,1>
1148806091U, // <2,1,u,u>: Cost 2 vrev <1,2,u,u>
1543667732U, // <2,2,0,0>: Cost 2 vext2 <0,0,2,2>, <0,0,2,2>
- 1556938854U, // <2,2,0,1>: Cost 2 vext2 <2,2,2,2>, LHS
- 2819409512U, // <2,2,0,2>: Cost 3 vuzpr LHS, <2,2,2,2>
- 2696537551U, // <2,2,0,3>: Cost 3 vext3 <2,0,3,2>, <2,0,3,2>
- 2696611288U, // <2,2,0,4>: Cost 3 vext3 <2,0,4,2>, <2,0,4,2>
- 2617409966U, // <2,2,0,5>: Cost 3 vext2 <0,0,2,2>, <0,5,2,7>
- 3770500586U, // <2,2,0,6>: Cost 4 vext3 <2,0,6,2>, <2,0,6,2>
- 3799991795U, // <2,2,0,7>: Cost 4 vext3 <7,0,1,2>, <2,0,7,2>
- 1556939421U, // <2,2,0,u>: Cost 2 vext2 <2,2,2,2>, LHS
- 2690565638U, // <2,2,1,0>: Cost 3 vext3 <1,0,3,2>, <2,1,0,3>
- 2630681396U, // <2,2,1,1>: Cost 3 vext2 <2,2,2,2>, <1,1,1,1>
- 2685699608U, // <2,2,1,2>: Cost 3 vext3 <0,2,0,2>, <2,1,2,3>
- 3759441441U, // <2,2,1,3>: Cost 4 vext3 <0,2,0,2>, <2,1,3,3>
- 3759441450U, // <2,2,1,4>: Cost 4 vext3 <0,2,0,2>, <2,1,4,3>
- 2665186448U, // <2,2,1,5>: Cost 3 vext2 <u,0,2,2>, <1,5,3,7>
- 3738928335U, // <2,2,1,6>: Cost 4 vext2 <u,0,2,2>, <1,6,1,7>
- 3738928427U, // <2,2,1,7>: Cost 4 vext2 <u,0,2,2>, <1,7,3,0>
- 2630681980U, // <2,2,1,u>: Cost 3 vext2 <2,2,2,2>, <1,u,3,0>
+ 1548976230U, // <2,2,0,1>: Cost 2 vext2 <0,u,2,2>, LHS
+ 2685699524U, // <2,2,0,2>: Cost 3 vext3 <0,2,0,2>, <2,0,2,0>
+ 2685699535U, // <2,2,0,3>: Cost 3 vext3 <0,2,0,2>, <2,0,3,2>
+ 2551614774U, // <2,2,0,4>: Cost 3 vext1 <0,2,2,0>, RHS
+ 3704422830U, // <2,2,0,5>: Cost 4 vext2 <2,2,2,2>, <0,5,2,7>
+ 3893657642U, // <2,2,0,6>: Cost 4 vuzpr <0,2,0,2>, <0,0,4,6>
+ 3770574323U, // <2,2,0,7>: Cost 4 vext3 <2,0,7,2>, <2,0,7,2>
+ 1548976796U, // <2,2,0,u>: Cost 2 vext2 <0,u,2,2>, <0,u,2,2>
+ 2622718710U, // <2,2,1,0>: Cost 3 vext2 <0,u,2,2>, <1,0,3,2>
+ 2622718772U, // <2,2,1,1>: Cost 3 vext2 <0,u,2,2>, <1,1,1,1>
+ 2622718870U, // <2,2,1,2>: Cost 3 vext2 <0,u,2,2>, <1,2,3,0>
+ 2819915878U, // <2,2,1,3>: Cost 3 vuzpr <0,2,0,2>, LHS
+ 3625364790U, // <2,2,1,4>: Cost 4 vext1 <0,2,2,1>, RHS
+ 2622719120U, // <2,2,1,5>: Cost 3 vext2 <0,u,2,2>, <1,5,3,7>
+ 3760031292U, // <2,2,1,6>: Cost 4 vext3 <0,2,u,2>, <2,1,6,3>
+ 3667170468U, // <2,2,1,7>: Cost 4 vext1 <7,2,2,1>, <7,2,2,1>
+ 2819915883U, // <2,2,1,u>: Cost 3 vuzpr <0,2,0,2>, LHS
1489829990U, // <2,2,2,0>: Cost 2 vext1 <2,2,2,2>, LHS
2563572470U, // <2,2,2,1>: Cost 3 vext1 <2,2,2,2>, <1,0,3,2>
269271142U, // <2,2,2,2>: Cost 1 vdup2 LHS
- 2886518376U, // <2,2,2,3>: Cost 3 vzipl LHS, <2,2,2,2>
+ 2685699698U, // <2,2,2,3>: Cost 3 vext3 <0,2,0,2>, <2,2,3,3>
1489833270U, // <2,2,2,4>: Cost 2 vext1 <2,2,2,2>, RHS
- 2563575504U, // <2,2,2,5>: Cost 3 vext1 <2,2,2,2>, <5,1,7,3>
- 2563576314U, // <2,2,2,6>: Cost 3 vext1 <2,2,2,2>, <6,2,7,3>
+ 2685699720U, // <2,2,2,5>: Cost 3 vext3 <0,2,0,2>, <2,2,5,7>
+ 2622719930U, // <2,2,2,6>: Cost 3 vext2 <0,u,2,2>, <2,6,3,7>
2593436837U, // <2,2,2,7>: Cost 3 vext1 <7,2,2,2>, <7,2,2,2>
269271142U, // <2,2,2,u>: Cost 1 vdup2 LHS
2685699750U, // <2,2,3,0>: Cost 3 vext3 <0,2,0,2>, <2,3,0,1>
2690565806U, // <2,2,3,1>: Cost 3 vext3 <1,0,3,2>, <2,3,1,0>
- 2630682945U, // <2,2,3,2>: Cost 3 vext2 <2,2,2,2>, <3,2,2,2>
- 1812775014U, // <2,2,3,3>: Cost 2 vzipl LHS, LHS
+ 2953627240U, // <2,2,3,2>: Cost 3 vzipr LHS, <2,2,2,2>
+ 1879883878U, // <2,2,3,3>: Cost 2 vzipr LHS, LHS
2685699790U, // <2,2,3,4>: Cost 3 vext3 <0,2,0,2>, <2,3,4,5>
- 3625381584U, // <2,2,3,5>: Cost 4 vext1 <0,2,2,3>, <5,1,7,3>
- 2698749661U, // <2,2,3,6>: Cost 3 vext3 <2,3,6,2>, <2,3,6,2>
+ 3893659342U, // <2,2,3,5>: Cost 4 vuzpr <0,2,0,2>, <2,3,4,5>
+ 2958270812U, // <2,2,3,6>: Cost 3 vzipr LHS, <0,4,2,6>
2593445030U, // <2,2,3,7>: Cost 3 vext1 <7,2,2,3>, <7,2,2,3>
- 1812815974U, // <2,2,3,u>: Cost 2 vzipl LHS, LHS
- 2630683538U, // <2,2,4,0>: Cost 3 vext2 <2,2,2,2>, <4,0,5,1>
- 3704425418U, // <2,2,4,1>: Cost 4 vext2 <2,2,2,2>, <4,1,2,3>
- 2228045418U, // <2,2,4,2>: Cost 3 vrev <2,2,2,4>
- 3964904904U, // <2,2,4,3>: Cost 4 vzipl LHS, <2,0,2,4>
- 3027452826U, // <2,2,4,4>: Cost 3 vtrnl <1,2,3,4>, <1,2,3,4>
- 1556942134U, // <2,2,4,5>: Cost 2 vext2 <2,2,2,2>, RHS
- 2630683980U, // <2,2,4,6>: Cost 3 vext2 <2,2,2,2>, <4,6,0,2>
+ 1879883883U, // <2,2,3,u>: Cost 2 vzipr LHS, LHS
+ 2551644262U, // <2,2,4,0>: Cost 3 vext1 <0,2,2,4>, LHS
+ 3625386742U, // <2,2,4,1>: Cost 4 vext1 <0,2,2,4>, <1,0,3,2>
+ 2551645902U, // <2,2,4,2>: Cost 3 vext1 <0,2,2,4>, <2,3,4,5>
+ 3759441686U, // <2,2,4,3>: Cost 4 vext3 <0,2,0,2>, <2,4,3,5>
+ 2551647542U, // <2,2,4,4>: Cost 3 vext1 <0,2,2,4>, RHS
+ 1548979510U, // <2,2,4,5>: Cost 2 vext2 <0,u,2,2>, RHS
+ 2764901686U, // <2,2,4,6>: Cost 3 vuzpl <2,2,2,2>, RHS
3667195047U, // <2,2,4,7>: Cost 4 vext1 <7,2,2,4>, <7,2,2,4>
- 1556942377U, // <2,2,4,u>: Cost 2 vext2 <2,2,2,2>, RHS
- 3704426055U, // <2,2,5,0>: Cost 4 vext2 <2,2,2,2>, <5,0,1,1>
- 2630684368U, // <2,2,5,1>: Cost 3 vext2 <2,2,2,2>, <5,1,7,3>
+ 1548979753U, // <2,2,4,u>: Cost 2 vext2 <0,u,2,2>, RHS
+ 3696463432U, // <2,2,5,0>: Cost 4 vext2 <0,u,2,2>, <5,0,1,2>
+ 2617413328U, // <2,2,5,1>: Cost 3 vext2 <0,0,2,2>, <5,1,7,3>
2685699936U, // <2,2,5,2>: Cost 3 vext3 <0,2,0,2>, <2,5,2,7>
- 3779348328U, // <2,2,5,3>: Cost 4 vext3 <3,5,0,2>, <2,5,3,6>
+ 4027383910U, // <2,2,5,3>: Cost 4 vzipr <0,1,2,5>, LHS
2228201085U, // <2,2,5,4>: Cost 3 vrev <2,2,4,5>
- 2665189380U, // <2,2,5,5>: Cost 3 vext2 <u,0,2,2>, <5,5,5,5>
- 2665189474U, // <2,2,5,6>: Cost 3 vext2 <u,0,2,2>, <5,6,7,0>
- 3704426614U, // <2,2,5,7>: Cost 4 vext2 <2,2,2,2>, <5,7,0,2>
- 2630684935U, // <2,2,5,u>: Cost 3 vext2 <2,2,2,2>, <5,u,7,3>
- 3704426793U, // <2,2,6,0>: Cost 4 vext2 <2,2,2,2>, <6,0,2,1>
- 3704426876U, // <2,2,6,1>: Cost 4 vext2 <2,2,2,2>, <6,1,2,3>
- 2630685178U, // <2,2,6,2>: Cost 3 vext2 <2,2,2,2>, <6,2,7,3>
- 2712242106U, // <2,2,6,3>: Cost 3 vext3 <4,6,0,2>, <2,6,3,7>
- 3637349686U, // <2,2,6,4>: Cost 4 vext1 <2,2,2,6>, RHS
- 3738931890U, // <2,2,6,5>: Cost 4 vext2 <u,0,2,2>, <6,5,0,7>
- 2657227536U, // <2,2,6,6>: Cost 3 vext2 <6,6,2,2>, <6,6,2,2>
+ 2617413636U, // <2,2,5,5>: Cost 3 vext2 <0,0,2,2>, <5,5,5,5>
+ 2617413730U, // <2,2,5,6>: Cost 3 vext2 <0,0,2,2>, <5,6,7,0>
+ 2819919158U, // <2,2,5,7>: Cost 3 vuzpr <0,2,0,2>, RHS
+ 2819919159U, // <2,2,5,u>: Cost 3 vuzpr <0,2,0,2>, RHS
+ 3625402554U, // <2,2,6,0>: Cost 4 vext1 <0,2,2,6>, <0,2,2,6>
+ 3760031652U, // <2,2,6,1>: Cost 4 vext3 <0,2,u,2>, <2,6,1,3>
+ 2617414138U, // <2,2,6,2>: Cost 3 vext2 <0,0,2,2>, <6,2,7,3>
+ 2685700026U, // <2,2,6,3>: Cost 3 vext3 <0,2,0,2>, <2,6,3,7>
+ 3625405750U, // <2,2,6,4>: Cost 4 vext1 <0,2,2,6>, RHS
+ 3760031692U, // <2,2,6,5>: Cost 4 vext3 <0,2,u,2>, <2,6,5,7>
+ 3088679116U, // <2,2,6,6>: Cost 3 vtrnr <0,2,4,6>, <0,2,4,6>
2657891169U, // <2,2,6,7>: Cost 3 vext2 <6,7,2,2>, <6,7,2,2>
- 2630685664U, // <2,2,6,u>: Cost 3 vext2 <2,2,2,2>, <6,u,7,3>
+ 2685700071U, // <2,2,6,u>: Cost 3 vext3 <0,2,0,2>, <2,6,u,7>
2726250474U, // <2,2,7,0>: Cost 3 vext3 <7,0,1,2>, <2,7,0,1>
- 3934209640U, // <2,2,7,1>: Cost 4 vuzpr <7,0,1,2>, <2,2,2,2>
+ 3704427616U, // <2,2,7,1>: Cost 4 vext2 <2,2,2,2>, <7,1,3,5>
2660545701U, // <2,2,7,2>: Cost 3 vext2 <7,2,2,2>, <7,2,2,2>
- 3964906122U, // <2,2,7,3>: Cost 4 vzipl LHS, <3,6,2,7>
- 2665190758U, // <2,2,7,4>: Cost 3 vext2 <u,0,2,2>, <7,4,5,6>
- 3937191528U, // <2,2,7,5>: Cost 4 vuzpr <7,4,5,6>, <2,2,2,2>
- 3730970125U, // <2,2,7,6>: Cost 4 vext2 <6,6,2,2>, <7,6,6,2>
- 2665191020U, // <2,2,7,7>: Cost 3 vext2 <u,0,2,2>, <7,7,7,7>
+ 4030718054U, // <2,2,7,3>: Cost 4 vzipr <0,6,2,7>, LHS
+ 2617415014U, // <2,2,7,4>: Cost 3 vext2 <0,0,2,2>, <7,4,5,6>
+ 3302033032U, // <2,2,7,5>: Cost 4 vrev <2,2,5,7>
+ 3661246929U, // <2,2,7,6>: Cost 4 vext1 <6,2,2,7>, <6,2,2,7>
+ 2617415276U, // <2,2,7,7>: Cost 3 vext2 <0,0,2,2>, <7,7,7,7>
2731558962U, // <2,2,7,u>: Cost 3 vext3 <7,u,1,2>, <2,7,u,1>
- 1591449308U, // <2,2,u,0>: Cost 2 vext2 <u,0,2,2>, <u,0,2,2>
- 1556944686U, // <2,2,u,1>: Cost 2 vext2 <2,2,2,2>, LHS
+ 1489829990U, // <2,2,u,0>: Cost 2 vext1 <2,2,2,2>, LHS
+ 1548982062U, // <2,2,u,1>: Cost 2 vext2 <0,u,2,2>, LHS
269271142U, // <2,2,u,2>: Cost 1 vdup2 LHS
- 1812775019U, // <2,2,u,3>: Cost 2 vzipl LHS, LHS
+ 1879924838U, // <2,2,u,3>: Cost 2 vzipr LHS, LHS
1489833270U, // <2,2,u,4>: Cost 2 vext1 <2,2,2,2>, RHS
- 1556945050U, // <2,2,u,5>: Cost 2 vext2 <2,2,2,2>, RHS
- 2630686896U, // <2,2,u,6>: Cost 3 vext2 <2,2,2,2>, <u,6,0,2>
- 2593485995U, // <2,2,u,7>: Cost 3 vext1 <7,2,2,u>, <7,2,2,u>
+ 1548982426U, // <2,2,u,5>: Cost 2 vext2 <0,u,2,2>, RHS
+ 2953666908U, // <2,2,u,6>: Cost 3 vzipr LHS, <0,4,2,6>
+ 2819919401U, // <2,2,u,7>: Cost 3 vuzpr <0,2,0,2>, RHS
269271142U, // <2,2,u,u>: Cost 1 vdup2 LHS
1544339456U, // <2,3,0,0>: Cost 2 vext2 LHS, <0,0,0,0>
470597734U, // <2,3,0,1>: Cost 1 vext2 LHS, LHS
1548984484U, // <2,3,0,2>: Cost 2 vext2 LHS, <0,2,0,2>
- 2557659286U, // <2,3,0,3>: Cost 3 vext1 <1,2,3,0>, <3,0,1,2>
- 1483918646U, // <2,3,0,4>: Cost 2 vext1 <1,2,3,0>, RHS
- 2557660880U, // <2,3,0,5>: Cost 3 vext1 <1,2,3,0>, <5,1,7,3>
- 2557661690U, // <2,3,0,6>: Cost 3 vext1 <1,2,3,0>, <6,2,7,3>
+ 2619408648U, // <2,3,0,3>: Cost 3 vext2 <0,3,2,3>, <0,3,2,3>
+ 1548984658U, // <2,3,0,4>: Cost 2 vext2 LHS, <0,4,1,5>
+ 2665857454U, // <2,3,0,5>: Cost 3 vext2 LHS, <0,5,2,7>
+ 2622726655U, // <2,3,0,6>: Cost 3 vext2 LHS, <0,6,2,7>
2593494188U, // <2,3,0,7>: Cost 3 vext1 <7,2,3,0>, <7,2,3,0>
470598301U, // <2,3,0,u>: Cost 1 vext2 LHS, LHS
1544340214U, // <2,3,1,0>: Cost 2 vext2 LHS, <1,0,3,2>
1544340276U, // <2,3,1,1>: Cost 2 vext2 LHS, <1,1,1,1>
1544340374U, // <2,3,1,2>: Cost 2 vext2 LHS, <1,2,3,0>
- 2622727118U, // <2,3,1,3>: Cost 3 vext2 LHS, <1,3,0,2>
- 2557668662U, // <2,3,1,4>: Cost 3 vext1 <1,2,3,1>, RHS
- 1592116368U, // <2,3,1,5>: Cost 2 vext2 LHS, <1,5,3,7>
- 2665858255U, // <2,3,1,6>: Cost 3 vext2 LHS, <1,6,1,7>
+ 1548985304U, // <2,3,1,3>: Cost 2 vext2 LHS, <1,3,1,3>
+ 2551696694U, // <2,3,1,4>: Cost 3 vext1 <0,2,3,1>, RHS
+ 1548985488U, // <2,3,1,5>: Cost 2 vext2 LHS, <1,5,3,7>
+ 2622727375U, // <2,3,1,6>: Cost 3 vext2 LHS, <1,6,1,7>
2665858347U, // <2,3,1,7>: Cost 3 vext2 LHS, <1,7,3,0>
- 1548985724U, // <2,3,1,u>: Cost 2 vext2 LHS, <1,u,3,0>
- 2622727604U, // <2,3,2,0>: Cost 3 vext2 LHS, <2,0,0,2>
- 2622727686U, // <2,3,2,1>: Cost 3 vext2 LHS, <2,1,0,3>
+ 1548985709U, // <2,3,1,u>: Cost 2 vext2 LHS, <1,u,1,3>
+ 2622727613U, // <2,3,2,0>: Cost 3 vext2 LHS, <2,0,1,2>
+ 2622727711U, // <2,3,2,1>: Cost 3 vext2 LHS, <2,1,3,1>
1544341096U, // <2,3,2,2>: Cost 2 vext2 LHS, <2,2,2,2>
1544341158U, // <2,3,2,3>: Cost 2 vext2 LHS, <2,3,0,1>
- 2622727928U, // <2,3,2,4>: Cost 3 vext2 LHS, <2,4,0,2>
- 2665858894U, // <2,3,2,5>: Cost 3 vext2 LHS, <2,5,0,7>
- 1592117178U, // <2,3,2,6>: Cost 2 vext2 LHS, <2,6,3,7>
+ 2622727958U, // <2,3,2,4>: Cost 3 vext2 LHS, <2,4,3,5>
+ 2622728032U, // <2,3,2,5>: Cost 3 vext2 LHS, <2,5,2,7>
+ 1548986298U, // <2,3,2,6>: Cost 2 vext2 LHS, <2,6,3,7>
2665859050U, // <2,3,2,7>: Cost 3 vext2 LHS, <2,7,0,1>
1548986427U, // <2,3,2,u>: Cost 2 vext2 LHS, <2,u,0,1>
1548986518U, // <2,3,3,0>: Cost 2 vext2 LHS, <3,0,1,2>
- 2622728414U, // <2,3,3,1>: Cost 3 vext2 LHS, <3,1,0,2>
+ 2622728415U, // <2,3,3,1>: Cost 3 vext2 LHS, <3,1,0,3>
1489913458U, // <2,3,3,2>: Cost 2 vext1 <2,2,3,3>, <2,2,3,3>
1544341916U, // <2,3,3,3>: Cost 2 vext2 LHS, <3,3,3,3>
1548986882U, // <2,3,3,4>: Cost 2 vext2 LHS, <3,4,5,6>
- 2622728738U, // <2,3,3,5>: Cost 3 vext2 LHS, <3,5,0,2>
- 2622728842U, // <2,3,3,6>: Cost 3 vext2 LHS, <3,6,2,7>
- 2593518767U, // <2,3,3,7>: Cost 3 vext1 <7,2,3,3>, <7,2,3,3>
+ 2665859632U, // <2,3,3,5>: Cost 3 vext2 LHS, <3,5,1,7>
+ 2234304870U, // <2,3,3,6>: Cost 3 vrev <3,2,6,3>
+ 2958271632U, // <2,3,3,7>: Cost 3 vzipr LHS, <1,5,3,7>
1548987166U, // <2,3,3,u>: Cost 2 vext2 LHS, <3,u,1,2>
- 1548987282U, // <2,3,4,0>: Cost 2 vext2 LHS, <4,0,5,1>
+ 1483948134U, // <2,3,4,0>: Cost 2 vext1 <1,2,3,4>, LHS
1483948954U, // <2,3,4,1>: Cost 2 vext1 <1,2,3,4>, <1,2,3,4>
- 2622729270U, // <2,3,4,2>: Cost 3 vext2 LHS, <4,2,5,3>
+ 2622729276U, // <2,3,4,2>: Cost 3 vext2 LHS, <4,2,6,0>
2557692054U, // <2,3,4,3>: Cost 3 vext1 <1,2,3,4>, <3,0,1,2>
1483951414U, // <2,3,4,4>: Cost 2 vext1 <1,2,3,4>, RHS
470601014U, // <2,3,4,5>: Cost 1 vext2 LHS, RHS
- 1548987724U, // <2,3,4,6>: Cost 2 vext2 LHS, <4,6,0,2>
+ 1592118644U, // <2,3,4,6>: Cost 2 vext2 LHS, <4,6,4,6>
2593526960U, // <2,3,4,7>: Cost 3 vext1 <7,2,3,4>, <7,2,3,4>
470601257U, // <2,3,4,u>: Cost 1 vext2 LHS, RHS
- 2622729799U, // <2,3,5,0>: Cost 3 vext2 LHS, <5,0,1,1>
- 1548988112U, // <2,3,5,1>: Cost 2 vext2 LHS, <5,1,7,3>
- 2622729968U, // <2,3,5,2>: Cost 3 vext2 LHS, <5,2,1,u>
- 2665860976U, // <2,3,5,3>: Cost 3 vext2 LHS, <5,3,7,1>
+ 2551726182U, // <2,3,5,0>: Cost 3 vext1 <0,2,3,5>, LHS
+ 1592118992U, // <2,3,5,1>: Cost 2 vext2 LHS, <5,1,7,3>
+ 2665860862U, // <2,3,5,2>: Cost 3 vext2 LHS, <5,2,3,4>
+ 2551728642U, // <2,3,5,3>: Cost 3 vext1 <0,2,3,5>, <3,4,5,6>
1592119238U, // <2,3,5,4>: Cost 2 vext2 LHS, <5,4,7,6>
1592119300U, // <2,3,5,5>: Cost 2 vext2 LHS, <5,5,5,5>
1592119394U, // <2,3,5,6>: Cost 2 vext2 LHS, <5,6,7,0>
- 2622730358U, // <2,3,5,7>: Cost 3 vext2 LHS, <5,7,0,2>
- 1592119556U, // <2,3,5,u>: Cost 2 vext2 LHS, <5,u,7,0>
- 2622730537U, // <2,3,6,0>: Cost 3 vext2 LHS, <6,0,2,1>
- 2622730620U, // <2,3,6,1>: Cost 3 vext2 LHS, <6,1,2,3>
- 1548988922U, // <2,3,6,2>: Cost 2 vext2 LHS, <6,2,7,3>
+ 1592119464U, // <2,3,5,7>: Cost 2 vext2 LHS, <5,7,5,7>
+ 1592119545U, // <2,3,5,u>: Cost 2 vext2 LHS, <5,u,5,7>
+ 2622730529U, // <2,3,6,0>: Cost 3 vext2 LHS, <6,0,1,2>
+ 2557707164U, // <2,3,6,1>: Cost 3 vext1 <1,2,3,6>, <1,2,3,6>
+ 1592119802U, // <2,3,6,2>: Cost 2 vext2 LHS, <6,2,7,3>
2665861682U, // <2,3,6,3>: Cost 3 vext2 LHS, <6,3,4,5>
- 2665861740U, // <2,3,6,4>: Cost 3 vext2 LHS, <6,4,2,0>
+ 2622730893U, // <2,3,6,4>: Cost 3 vext2 LHS, <6,4,5,6>
2665861810U, // <2,3,6,5>: Cost 3 vext2 LHS, <6,5,0,7>
1592120120U, // <2,3,6,6>: Cost 2 vext2 LHS, <6,6,6,6>
1592120142U, // <2,3,6,7>: Cost 2 vext2 LHS, <6,7,0,1>
- 1548989408U, // <2,3,6,u>: Cost 2 vext2 LHS, <6,u,7,3>
+ 1592120223U, // <2,3,6,u>: Cost 2 vext2 LHS, <6,u,0,1>
1592120314U, // <2,3,7,0>: Cost 2 vext2 LHS, <7,0,1,2>
2659890261U, // <2,3,7,1>: Cost 3 vext2 <7,1,2,3>, <7,1,2,3>
- 2622731439U, // <2,3,7,2>: Cost 3 vext2 LHS, <7,2,3,3>
+ 2660553894U, // <2,3,7,2>: Cost 3 vext2 <7,2,2,3>, <7,2,2,3>
2665862371U, // <2,3,7,3>: Cost 3 vext2 LHS, <7,3,0,1>
1592120678U, // <2,3,7,4>: Cost 2 vext2 LHS, <7,4,5,6>
- 2665862548U, // <2,3,7,5>: Cost 3 vext2 LHS, <7,5,1,7>
+ 2665862534U, // <2,3,7,5>: Cost 3 vext2 LHS, <7,5,0,2>
2665862614U, // <2,3,7,6>: Cost 3 vext2 LHS, <7,6,0,1>
1592120940U, // <2,3,7,7>: Cost 2 vext2 LHS, <7,7,7,7>
1592120962U, // <2,3,7,u>: Cost 2 vext2 LHS, <7,u,1,2>
- 1548990162U, // <2,3,u,0>: Cost 2 vext2 LHS, <u,0,1,1>
+ 1548990163U, // <2,3,u,0>: Cost 2 vext2 LHS, <u,0,1,2>
470603566U, // <2,3,u,1>: Cost 1 vext2 LHS, LHS
- 1548990316U, // <2,3,u,2>: Cost 2 vext2 LHS, <u,2,0,2>
+ 1548990341U, // <2,3,u,2>: Cost 2 vext2 LHS, <u,2,3,0>
1548990396U, // <2,3,u,3>: Cost 2 vext2 LHS, <u,3,0,1>
1548990527U, // <2,3,u,4>: Cost 2 vext2 LHS, <u,4,5,6>
470603930U, // <2,3,u,5>: Cost 1 vext2 LHS, RHS
- 1548990640U, // <2,3,u,6>: Cost 2 vext2 LHS, <u,6,0,2>
+ 1548990672U, // <2,3,u,6>: Cost 2 vext2 LHS, <u,6,3,7>
1592121600U, // <2,3,u,7>: Cost 2 vext2 LHS, <u,7,0,1>
470604133U, // <2,3,u,u>: Cost 1 vext2 LHS, LHS
- 2708261734U, // <2,4,0,0>: Cost 3 vext3 <4,0,0,2>, <4,0,0,2>
- 2629369958U, // <2,4,0,1>: Cost 3 vext2 <2,0,2,4>, LHS
- 2819409614U, // <2,4,0,2>: Cost 3 vuzpr LHS, <2,3,4,5>
+ 2617425942U, // <2,4,0,0>: Cost 3 vext2 <0,0,2,4>, <0,0,2,4>
+ 2618753126U, // <2,4,0,1>: Cost 3 vext2 <0,2,2,4>, LHS
+ 2618753208U, // <2,4,0,2>: Cost 3 vext2 <0,2,2,4>, <0,2,2,4>
2619416841U, // <2,4,0,3>: Cost 3 vext2 <0,3,2,4>, <0,3,2,4>
- 2712243086U, // <2,4,0,4>: Cost 3 vext3 <4,6,0,2>, <4,0,4,6>
- 2685701010U, // <2,4,0,5>: Cost 3 vext3 <0,2,0,2>, <4,0,5,1>
+ 2587593628U, // <2,4,0,4>: Cost 3 vext1 <6,2,4,0>, <4,0,6,2>
+ 2712832914U, // <2,4,0,5>: Cost 3 vext3 <4,6,u,2>, <4,0,5,1>
1634962332U, // <2,4,0,6>: Cost 2 vext3 <4,0,6,2>, <4,0,6,2>
- 3661337594U, // <2,4,0,7>: Cost 4 vext1 <6,2,4,0>, <7,0,1,2>
- 1635109806U, // <2,4,0,u>: Cost 2 vext3 <4,0,u,2>, <4,0,u,2>
+ 3799993252U, // <2,4,0,7>: Cost 4 vext3 <7,0,1,2>, <4,0,7,1>
+ 1634962332U, // <2,4,0,u>: Cost 2 vext3 <4,0,6,2>, <4,0,6,2>
2619417334U, // <2,4,1,0>: Cost 3 vext2 <0,3,2,4>, <1,0,3,2>
- 3899033294U, // <2,4,1,1>: Cost 4 vuzpr <1,1,1,1>, <2,3,4,5>
- 3703112598U, // <2,4,1,2>: Cost 4 vext2 <2,0,2,4>, <1,2,3,0>
- 3898525390U, // <2,4,1,3>: Cost 4 vuzpr <1,0,3,2>, <2,3,4,5>
- 3643427810U, // <2,4,1,4>: Cost 4 vext1 <3,2,4,1>, <4,1,5,0>
- 2709294052U, // <2,4,1,5>: Cost 3 vext3 <4,1,5,2>, <4,1,5,2>
- 3759442926U, // <2,4,1,6>: Cost 4 vext3 <0,2,0,2>, <4,1,6,3>
- 3701785894U, // <2,4,1,7>: Cost 4 vext2 <1,7,2,4>, <1,7,2,4>
- 2709515263U, // <2,4,1,u>: Cost 3 vext3 <4,1,u,2>, <4,1,u,2>
+ 3692495668U, // <2,4,1,1>: Cost 4 vext2 <0,2,2,4>, <1,1,1,1>
+ 2625389466U, // <2,4,1,2>: Cost 3 vext2 <1,3,2,4>, <1,2,3,4>
+ 2826125414U, // <2,4,1,3>: Cost 3 vuzpr <1,2,3,4>, LHS
+ 3699794995U, // <2,4,1,4>: Cost 4 vext2 <1,4,2,4>, <1,4,2,4>
+ 3692496016U, // <2,4,1,5>: Cost 4 vext2 <0,2,2,4>, <1,5,3,7>
+ 3763424238U, // <2,4,1,6>: Cost 4 vext3 <0,u,0,2>, <4,1,6,3>
+ 3667317942U, // <2,4,1,7>: Cost 4 vext1 <7,2,4,1>, <7,2,4,1>
+ 2826125419U, // <2,4,1,u>: Cost 3 vuzpr <1,2,3,4>, LHS
2629371336U, // <2,4,2,0>: Cost 3 vext2 <2,0,2,4>, <2,0,2,4>
- 3703113240U, // <2,4,2,1>: Cost 4 vext2 <2,0,2,4>, <2,1,2,3>
+ 3699131946U, // <2,4,2,1>: Cost 4 vext2 <1,3,2,4>, <2,1,4,3>
2630698602U, // <2,4,2,2>: Cost 3 vext2 <2,2,2,4>, <2,2,2,4>
- 2632025806U, // <2,4,2,3>: Cost 3 vext2 <2,4,2,4>, <2,3,4,5>
- 2832844494U, // <2,4,2,4>: Cost 3 vuzpr <2,3,4,5>, <2,3,4,5>
- 2709957685U, // <2,4,2,5>: Cost 3 vext3 <4,2,5,2>, <4,2,5,2>
- 2710031422U, // <2,4,2,6>: Cost 3 vext3 <4,2,6,2>, <4,2,6,2>
+ 2618754766U, // <2,4,2,3>: Cost 3 vext2 <0,2,2,4>, <2,3,4,5>
+ 2826126234U, // <2,4,2,4>: Cost 3 vuzpr <1,2,3,4>, <1,2,3,4>
+ 2899119414U, // <2,4,2,5>: Cost 3 vzipl <2,2,2,2>, RHS
+ 3033337142U, // <2,4,2,6>: Cost 3 vtrnl <2,2,2,2>, RHS
3800214597U, // <2,4,2,7>: Cost 4 vext3 <7,0,4,2>, <4,2,7,0>
- 2710178896U, // <2,4,2,u>: Cost 3 vext3 <4,2,u,2>, <4,2,u,2>
- 2569699430U, // <2,4,3,0>: Cost 3 vext1 <3,2,4,3>, LHS
- 2569700250U, // <2,4,3,1>: Cost 3 vext1 <3,2,4,3>, <1,2,3,4>
- 3971678310U, // <2,4,3,2>: Cost 4 vzipl <2,0,4,2>, LHS
- 2569701716U, // <2,4,3,3>: Cost 3 vext1 <3,2,4,3>, <3,2,4,3>
- 2569702710U, // <2,4,3,4>: Cost 3 vext1 <3,2,4,3>, RHS
- 2899951718U, // <2,4,3,5>: Cost 3 vzipl <2,3,4,5>, LHS
- 3114714738U, // <2,4,3,6>: Cost 3 vtrnr RHS, <2,2,3,3>
- 3987644518U, // <2,4,3,7>: Cost 4 vzipl <4,6,4,7>, LHS
- 2899976294U, // <2,4,3,u>: Cost 3 vzipl <2,3,4,u>, LHS
- 2563735654U, // <2,4,4,0>: Cost 3 vext1 <2,2,4,4>, LHS
- 2563736474U, // <2,4,4,1>: Cost 3 vext1 <2,2,4,4>, <1,2,3,4>
- 2563737212U, // <2,4,4,2>: Cost 3 vext1 <2,2,4,4>, <2,2,4,4>
- 3637479574U, // <2,4,4,3>: Cost 4 vext1 <2,2,4,4>, <3,0,1,2>
- 2563738934U, // <2,4,4,4>: Cost 3 vext1 <2,2,4,4>, RHS
- 2629373238U, // <2,4,4,5>: Cost 3 vext2 <2,0,2,4>, RHS
- 2846279374U, // <2,4,4,6>: Cost 3 vuzpr RHS, <2,3,4,5>
- 3667342521U, // <2,4,4,7>: Cost 4 vext1 <7,2,4,4>, <7,2,4,4>
- 2629373481U, // <2,4,4,u>: Cost 3 vext2 <2,0,2,4>, RHS
+ 2899119657U, // <2,4,2,u>: Cost 3 vzipl <2,2,2,2>, RHS
+ 2635344033U, // <2,4,3,0>: Cost 3 vext2 <3,0,2,4>, <3,0,2,4>
+ 4032012325U, // <2,4,3,1>: Cost 4 vzipr LHS, <0,0,4,1>
+ 3692497228U, // <2,4,3,2>: Cost 4 vext2 <0,2,2,4>, <3,2,3,4>
+ 3692497308U, // <2,4,3,3>: Cost 4 vext2 <0,2,2,4>, <3,3,3,3>
+ 3001404624U, // <2,4,3,4>: Cost 3 vzipr LHS, <4,4,4,4>
+ 2953627342U, // <2,4,3,5>: Cost 3 vzipr LHS, <2,3,4,5>
+ 2953625804U, // <2,4,3,6>: Cost 3 vzipr LHS, <0,2,4,6>
+ 3899868160U, // <2,4,3,7>: Cost 4 vuzpr <1,2,3,4>, <1,3,5,7>
+ 2953625806U, // <2,4,3,u>: Cost 3 vzipr LHS, <0,2,4,u>
+ 2710916266U, // <2,4,4,0>: Cost 3 vext3 <4,4,0,2>, <4,4,0,2>
+ 3899869648U, // <2,4,4,1>: Cost 4 vuzpr <1,2,3,4>, <3,4,0,1>
+ 3899869658U, // <2,4,4,2>: Cost 4 vuzpr <1,2,3,4>, <3,4,1,2>
+ 3899868930U, // <2,4,4,3>: Cost 4 vuzpr <1,2,3,4>, <2,4,1,3>
+ 2712833232U, // <2,4,4,4>: Cost 3 vext3 <4,6,u,2>, <4,4,4,4>
+ 2618756406U, // <2,4,4,5>: Cost 3 vext2 <0,2,2,4>, RHS
+ 2765737270U, // <2,4,4,6>: Cost 3 vuzpl <2,3,4,5>, RHS
+ 4168304426U, // <2,4,4,7>: Cost 4 vtrnr <1,2,3,4>, <2,4,5,7>
+ 2618756649U, // <2,4,4,u>: Cost 3 vext2 <0,2,2,4>, RHS
2551800011U, // <2,4,5,0>: Cost 3 vext1 <0,2,4,5>, <0,2,4,5>
2569716470U, // <2,4,5,1>: Cost 3 vext1 <3,2,4,5>, <1,0,3,2>
2563745405U, // <2,4,5,2>: Cost 3 vext1 <2,2,4,5>, <2,2,4,5>
2569718102U, // <2,4,5,3>: Cost 3 vext1 <3,2,4,5>, <3,2,4,5>
2551803190U, // <2,4,5,4>: Cost 3 vext1 <0,2,4,5>, RHS
- 3625545424U, // <2,4,5,5>: Cost 4 vext1 <0,2,4,5>, <5,1,7,3>
+ 3625545732U, // <2,4,5,5>: Cost 4 vext1 <0,2,4,5>, <5,5,5,5>
1611959606U, // <2,4,5,6>: Cost 2 vext3 <0,2,0,2>, RHS
- 3923379918U, // <2,4,5,7>: Cost 4 vuzpr <5,1,7,3>, <2,3,4,5>
+ 2826128694U, // <2,4,5,7>: Cost 3 vuzpr <1,2,3,4>, RHS
1611959624U, // <2,4,5,u>: Cost 2 vext3 <0,2,0,2>, RHS
- 1638501708U, // <2,4,6,0>: Cost 2 vext3 <4,6,0,2>, <4,6,0,2>
- 2599584502U, // <2,4,6,1>: Cost 3 vext1 <u,2,4,6>, <1,0,3,2>
- 2712391006U, // <2,4,6,2>: Cost 3 vext3 <4,6,2,2>, <4,6,2,2>
- 2599585942U, // <2,4,6,3>: Cost 3 vext1 <u,2,4,6>, <3,0,1,2>
- 1525845302U, // <2,4,6,4>: Cost 2 vext1 <u,2,4,6>, RHS
- 2980497338U, // <2,4,6,5>: Cost 3 vzipr RHS, <2,6,3,7>
- 2599588346U, // <2,4,6,6>: Cost 3 vext1 <u,2,4,6>, <6,2,7,3>
- 2599588858U, // <2,4,6,7>: Cost 3 vext1 <u,2,4,6>, <7,0,1,2>
- 1525847854U, // <2,4,6,u>: Cost 2 vext1 <u,2,4,6>, LHS
+ 1478066278U, // <2,4,6,0>: Cost 2 vext1 <0,2,4,6>, LHS
+ 2551808758U, // <2,4,6,1>: Cost 3 vext1 <0,2,4,6>, <1,0,3,2>
+ 2551809516U, // <2,4,6,2>: Cost 3 vext1 <0,2,4,6>, <2,0,6,4>
+ 2551810198U, // <2,4,6,3>: Cost 3 vext1 <0,2,4,6>, <3,0,1,2>
+ 1478069558U, // <2,4,6,4>: Cost 2 vext1 <0,2,4,6>, RHS
+ 2901888310U, // <2,4,6,5>: Cost 3 vzipl <2,6,3,7>, RHS
+ 2551812920U, // <2,4,6,6>: Cost 3 vext1 <0,2,4,6>, <6,6,6,6>
+ 2726251914U, // <2,4,6,7>: Cost 3 vext3 <7,0,1,2>, <4,6,7,1>
+ 1478072110U, // <2,4,6,u>: Cost 2 vext1 <0,2,4,6>, LHS
2659234821U, // <2,4,7,0>: Cost 3 vext2 <7,0,2,4>, <7,0,2,4>
- 3934209742U, // <2,4,7,1>: Cost 4 vuzpr <7,0,1,2>, <2,3,4,5>
- 3719042224U, // <2,4,7,2>: Cost 4 vext2 <4,6,2,4>, <7,2,3,4>
- 3935700686U, // <2,4,7,3>: Cost 4 vuzpr <7,2,3,4>, <2,3,4,5>
- 3719042406U, // <2,4,7,4>: Cost 4 vext2 <4,6,2,4>, <7,4,5,6>
- 3937191630U, // <2,4,7,5>: Cost 4 vuzpr <7,4,5,6>, <2,3,4,5>
- 3799993809U, // <2,4,7,6>: Cost 4 vext3 <7,0,1,2>, <4,7,6,0>
- 3719042668U, // <2,4,7,7>: Cost 4 vext2 <4,6,2,4>, <7,7,7,7>
- 2664543885U, // <2,4,7,u>: Cost 3 vext2 <7,u,2,4>, <7,u,2,4>
- 1639828974U, // <2,4,u,0>: Cost 2 vext3 <4,u,0,2>, <4,u,0,2>
- 2629375790U, // <2,4,u,1>: Cost 3 vext2 <2,0,2,4>, LHS
- 2563769984U, // <2,4,u,2>: Cost 3 vext1 <2,2,4,u>, <2,2,4,u>
- 2569742681U, // <2,4,u,3>: Cost 3 vext1 <3,2,4,u>, <3,2,4,u>
- 1525845302U, // <2,4,u,4>: Cost 2 vext1 <u,2,4,6>, RHS
- 2629376154U, // <2,4,u,5>: Cost 3 vext2 <2,0,2,4>, RHS
+ 3786722726U, // <2,4,7,1>: Cost 4 vext3 <4,7,1,2>, <4,7,1,2>
+ 3734303911U, // <2,4,7,2>: Cost 4 vext2 <7,2,2,4>, <7,2,2,4>
+ 3734967544U, // <2,4,7,3>: Cost 4 vext2 <7,3,2,4>, <7,3,2,4>
+ 3727005030U, // <2,4,7,4>: Cost 4 vext2 <6,0,2,4>, <7,4,5,6>
+ 2726251976U, // <2,4,7,5>: Cost 3 vext3 <7,0,1,2>, <4,7,5,0>
+ 2726251986U, // <2,4,7,6>: Cost 3 vext3 <7,0,1,2>, <4,7,6,1>
+ 3727005292U, // <2,4,7,7>: Cost 4 vext2 <6,0,2,4>, <7,7,7,7>
+ 2659234821U, // <2,4,7,u>: Cost 3 vext2 <7,0,2,4>, <7,0,2,4>
+ 1478082662U, // <2,4,u,0>: Cost 2 vext1 <0,2,4,u>, LHS
+ 2618758958U, // <2,4,u,1>: Cost 3 vext2 <0,2,2,4>, LHS
+ 2551826024U, // <2,4,u,2>: Cost 3 vext1 <0,2,4,u>, <2,2,2,2>
+ 2551826582U, // <2,4,u,3>: Cost 3 vext1 <0,2,4,u>, <3,0,1,2>
+ 1478085942U, // <2,4,u,4>: Cost 2 vext1 <0,2,4,u>, RHS
+ 2953668302U, // <2,4,u,5>: Cost 3 vzipr LHS, <2,3,4,5>
1611959849U, // <2,4,u,6>: Cost 2 vext3 <0,2,0,2>, RHS
- 2599588858U, // <2,4,u,7>: Cost 3 vext1 <u,2,4,6>, <7,0,1,2>
+ 2826128937U, // <2,4,u,7>: Cost 3 vuzpr <1,2,3,4>, RHS
1611959867U, // <2,4,u,u>: Cost 2 vext3 <0,2,0,2>, RHS
- 3893659433U, // <2,5,0,0>: Cost 4 vuzpr <0,2,0,2>, <2,4,5,6>
- 2714308168U, // <2,5,0,1>: Cost 3 vext3 <5,0,1,2>, <5,0,1,2>
- 3893192808U, // <2,5,0,2>: Cost 4 vuzpr LHS, <2,u,5,1>
- 3319746298U, // <2,5,0,3>: Cost 4 vrev <5,2,3,0>
+ 3691839488U, // <2,5,0,0>: Cost 4 vext2 <0,1,2,5>, <0,0,0,0>
+ 2618097766U, // <2,5,0,1>: Cost 3 vext2 <0,1,2,5>, LHS
+ 2620088484U, // <2,5,0,2>: Cost 3 vext2 <0,4,2,5>, <0,2,0,2>
+ 2619425034U, // <2,5,0,3>: Cost 3 vext2 <0,3,2,5>, <0,3,2,5>
2620088667U, // <2,5,0,4>: Cost 3 vext2 <0,4,2,5>, <0,4,2,5>
2620752300U, // <2,5,0,5>: Cost 3 vext2 <0,5,2,5>, <0,5,2,5>
- 3788418677U, // <2,5,0,6>: Cost 4 vext3 <5,0,6,2>, <5,0,6,2>
- 3047605142U, // <2,5,0,7>: Cost 3 vtrnl RHS, <1,2,3,0>
- 3047613334U, // <2,5,0,u>: Cost 3 vtrnl RHS, <1,2,3,0>
- 3625582800U, // <2,5,1,0>: Cost 4 vext1 <0,2,5,1>, <0,2,5,1>
- 3643499254U, // <2,5,1,1>: Cost 4 vext1 <3,2,5,1>, <1,0,3,2>
+ 3693830655U, // <2,5,0,6>: Cost 4 vext2 <0,4,2,5>, <0,6,2,7>
+ 3094531382U, // <2,5,0,7>: Cost 3 vtrnr <1,2,3,0>, RHS
+ 2618098333U, // <2,5,0,u>: Cost 3 vext2 <0,1,2,5>, LHS
+ 3691840246U, // <2,5,1,0>: Cost 4 vext2 <0,1,2,5>, <1,0,3,2>
+ 3691840308U, // <2,5,1,1>: Cost 4 vext2 <0,1,2,5>, <1,1,1,1>
2626061206U, // <2,5,1,2>: Cost 3 vext2 <1,4,2,5>, <1,2,3,0>
- 3643500891U, // <2,5,1,3>: Cost 4 vext1 <3,2,5,1>, <3,2,5,1>
+ 2618098688U, // <2,5,1,3>: Cost 3 vext2 <0,1,2,5>, <1,3,5,7>
2626061364U, // <2,5,1,4>: Cost 3 vext2 <1,4,2,5>, <1,4,2,5>
- 3625586384U, // <2,5,1,5>: Cost 4 vext1 <0,2,5,1>, <5,1,7,3>
+ 3691840656U, // <2,5,1,5>: Cost 4 vext2 <0,1,2,5>, <1,5,3,7>
3789082310U, // <2,5,1,6>: Cost 4 vext3 <5,1,6,2>, <5,1,6,2>
- 2685701840U, // <2,5,1,7>: Cost 3 vext3 <0,2,0,2>, <5,1,7,3>
- 2685701849U, // <2,5,1,u>: Cost 3 vext3 <0,2,0,2>, <5,1,u,3>
- 2575736934U, // <2,5,2,0>: Cost 3 vext1 <4,2,5,2>, LHS
- 3759443696U, // <2,5,2,1>: Cost 4 vext3 <0,2,0,2>, <5,2,1,u>
- 2575738472U, // <2,5,2,2>: Cost 3 vext1 <4,2,5,2>, <2,2,2,2>
- 3772714750U, // <2,5,2,3>: Cost 4 vext3 <2,4,0,2>, <5,2,3,4>
- 2575739957U, // <2,5,2,4>: Cost 3 vext1 <4,2,5,2>, <4,2,5,2>
- 3906627283U, // <2,5,2,5>: Cost 4 vuzpr <2,3,5,1>, <2,3,5,1>
- 3759443736U, // <2,5,2,6>: Cost 4 vext3 <0,2,0,2>, <5,2,6,3>
- 3047604388U, // <2,5,2,7>: Cost 3 vtrnl RHS, <0,2,0,2>
- 2575742766U, // <2,5,2,u>: Cost 3 vext1 <4,2,5,2>, LHS
- 2575745126U, // <2,5,3,0>: Cost 3 vext1 <4,2,5,3>, LHS
- 2909945958U, // <2,5,3,1>: Cost 3 vzipl <4,0,5,1>, LHS
+ 2712833744U, // <2,5,1,7>: Cost 3 vext3 <4,6,u,2>, <5,1,7,3>
+ 2628715896U, // <2,5,1,u>: Cost 3 vext2 <1,u,2,5>, <1,u,2,5>
+ 3693831613U, // <2,5,2,0>: Cost 4 vext2 <0,4,2,5>, <2,0,1,2>
+ 4026698642U, // <2,5,2,1>: Cost 4 vzipr <0,0,2,2>, <4,0,5,1>
+ 2632033896U, // <2,5,2,2>: Cost 3 vext2 <2,4,2,5>, <2,2,2,2>
+ 3691841190U, // <2,5,2,3>: Cost 4 vext2 <0,1,2,5>, <2,3,0,1>
+ 2632034061U, // <2,5,2,4>: Cost 3 vext2 <2,4,2,5>, <2,4,2,5>
+ 3691841352U, // <2,5,2,5>: Cost 4 vext2 <0,1,2,5>, <2,5,0,1>
+ 3691841466U, // <2,5,2,6>: Cost 4 vext2 <0,1,2,5>, <2,6,3,7>
+ 3088354614U, // <2,5,2,7>: Cost 3 vtrnr <0,2,0,2>, RHS
+ 3088354615U, // <2,5,2,u>: Cost 3 vtrnr <0,2,0,2>, RHS
+ 2557829222U, // <2,5,3,0>: Cost 3 vext1 <1,2,5,3>, LHS
+ 2557830059U, // <2,5,3,1>: Cost 3 vext1 <1,2,5,3>, <1,2,5,3>
2575746766U, // <2,5,3,2>: Cost 3 vext1 <4,2,5,3>, <2,3,4,5>
- 3978395750U, // <2,5,3,3>: Cost 4 vzipl <3,1,5,3>, LHS
- 2575748150U, // <2,5,3,4>: Cost 3 vext1 <4,2,5,3>, <4,2,5,3>
- 2919268454U, // <2,5,3,5>: Cost 3 vzipl <5,5,5,5>, LHS
- 2906669158U, // <2,5,3,6>: Cost 3 vzipl <3,4,5,6>, LHS
- 3047605874U, // <2,5,3,7>: Cost 3 vtrnl RHS, <2,2,3,3>
- 2906685542U, // <2,5,3,u>: Cost 3 vzipl <3,4,5,u>, LHS
+ 3691841948U, // <2,5,3,3>: Cost 4 vext2 <0,1,2,5>, <3,3,3,3>
+ 2619427330U, // <2,5,3,4>: Cost 3 vext2 <0,3,2,5>, <3,4,5,6>
+ 2581720847U, // <2,5,3,5>: Cost 3 vext1 <5,2,5,3>, <5,2,5,3>
+ 2953628162U, // <2,5,3,6>: Cost 3 vzipr LHS, <3,4,5,6>
+ 2953626624U, // <2,5,3,7>: Cost 3 vzipr LHS, <1,3,5,7>
+ 2953626625U, // <2,5,3,u>: Cost 3 vzipr LHS, <1,3,5,u>
2569781350U, // <2,5,4,0>: Cost 3 vext1 <3,2,5,4>, LHS
- 3643523830U, // <2,5,4,1>: Cost 4 vext1 <3,2,5,4>, <1,0,3,2>
+ 3631580076U, // <2,5,4,1>: Cost 4 vext1 <1,2,5,4>, <1,2,5,4>
2569782990U, // <2,5,4,2>: Cost 3 vext1 <3,2,5,4>, <2,3,4,5>
2569783646U, // <2,5,4,3>: Cost 3 vext1 <3,2,5,4>, <3,2,5,4>
2569784630U, // <2,5,4,4>: Cost 3 vext1 <3,2,5,4>, RHS
- 2655923510U, // <2,5,4,5>: Cost 3 vext2 <6,4,2,5>, RHS
- 3643527674U, // <2,5,4,6>: Cost 4 vext1 <3,2,5,4>, <6,2,7,3>
- 3047605146U, // <2,5,4,7>: Cost 3 vtrnl RHS, <1,2,3,4>
- 2569787182U, // <2,5,4,u>: Cost 3 vext1 <3,2,5,4>, LHS
- 2599649382U, // <2,5,5,0>: Cost 3 vext1 <u,2,5,5>, LHS
- 3703123664U, // <2,5,5,1>: Cost 4 vext2 <2,0,2,5>, <5,1,7,3>
+ 2618101046U, // <2,5,4,5>: Cost 3 vext2 <0,1,2,5>, RHS
+ 3893905922U, // <2,5,4,6>: Cost 4 vuzpr <0,2,3,5>, <3,4,5,6>
+ 3094564150U, // <2,5,4,7>: Cost 3 vtrnr <1,2,3,4>, RHS
+ 2618101289U, // <2,5,4,u>: Cost 3 vext2 <0,1,2,5>, RHS
+ 2551873638U, // <2,5,5,0>: Cost 3 vext1 <0,2,5,5>, LHS
+ 3637560320U, // <2,5,5,1>: Cost 4 vext1 <2,2,5,5>, <1,3,5,7>
3637560966U, // <2,5,5,2>: Cost 4 vext1 <2,2,5,5>, <2,2,5,5>
3723030343U, // <2,5,5,3>: Cost 4 vext2 <5,3,2,5>, <5,3,2,5>
- 2599652662U, // <2,5,5,4>: Cost 3 vext1 <u,2,5,5>, RHS
- 2712244228U, // <2,5,5,5>: Cost 3 vext3 <4,6,0,2>, <5,5,5,5>
- 3779350542U, // <2,5,5,6>: Cost 4 vext3 <3,5,0,2>, <5,5,6,6>
- 2712244248U, // <2,5,5,7>: Cost 3 vext3 <4,6,0,2>, <5,5,7,7>
- 2712244257U, // <2,5,5,u>: Cost 3 vext3 <4,6,0,2>, <5,5,u,7>
- 3779350564U, // <2,5,6,0>: Cost 4 vext3 <3,5,0,2>, <5,6,0,1>
- 3785986099U, // <2,5,6,1>: Cost 4 vext3 <4,6,0,2>, <5,6,1,7>
+ 2551876918U, // <2,5,5,4>: Cost 3 vext1 <0,2,5,5>, RHS
+ 2712834052U, // <2,5,5,5>: Cost 3 vext3 <4,6,u,2>, <5,5,5,5>
+ 4028713474U, // <2,5,5,6>: Cost 4 vzipr <0,3,2,5>, <3,4,5,6>
+ 2712834072U, // <2,5,5,7>: Cost 3 vext3 <4,6,u,2>, <5,5,7,7>
+ 2712834081U, // <2,5,5,u>: Cost 3 vext3 <4,6,u,2>, <5,5,u,7>
+ 2575769702U, // <2,5,6,0>: Cost 3 vext1 <4,2,5,6>, LHS
+ 3631596462U, // <2,5,6,1>: Cost 4 vext1 <1,2,5,6>, <1,2,5,6>
2655924730U, // <2,5,6,2>: Cost 3 vext2 <6,4,2,5>, <6,2,7,3>
- 3779350594U, // <2,5,6,3>: Cost 4 vext3 <3,5,0,2>, <5,6,3,4>
+ 3643541856U, // <2,5,6,3>: Cost 4 vext1 <3,2,5,6>, <3,2,5,6>
2655924849U, // <2,5,6,4>: Cost 3 vext2 <6,4,2,5>, <6,4,2,5>
- 3785986135U, // <2,5,6,5>: Cost 4 vext3 <4,6,0,2>, <5,6,5,7>
- 3785986144U, // <2,5,6,6>: Cost 4 vext3 <4,6,0,2>, <5,6,6,7>
- 3047604428U, // <2,5,6,7>: Cost 3 vtrnl RHS, <0,2,4,6>
- 3047612620U, // <2,5,6,u>: Cost 3 vtrnl RHS, <0,2,4,6>
- 2718879862U, // <2,5,7,0>: Cost 3 vext3 <5,7,0,2>, <5,7,0,2>
- 4057597959U, // <2,5,7,1>: Cost 4 vzipr <5,1,7,3>, <2,7,3,3>
- 3792769160U, // <2,5,7,2>: Cost 4 vext3 <5,7,2,2>, <5,7,2,2>
- 3729667354U, // <2,5,7,3>: Cost 4 vext2 <6,4,2,5>, <7,3,6,2>
- 2599669046U, // <2,5,7,4>: Cost 3 vext1 <u,2,5,7>, RHS
- 2599669456U, // <2,5,7,5>: Cost 3 vext1 <u,2,5,7>, <5,1,7,3>
- 3729667566U, // <2,5,7,6>: Cost 4 vext2 <6,4,2,5>, <7,6,2,7>
- 3793137845U, // <2,5,7,7>: Cost 4 vext3 <5,7,7,2>, <5,7,7,2>
- 2599671598U, // <2,5,7,u>: Cost 3 vext1 <u,2,5,7>, LHS
- 2569814118U, // <2,5,u,0>: Cost 3 vext1 <3,2,5,u>, LHS
- 2909945963U, // <2,5,u,1>: Cost 3 vzipl <4,0,5,1>, LHS
- 2569815794U, // <2,5,u,2>: Cost 3 vext1 <3,2,5,u>, <2,3,u,5>
+ 3787755607U, // <2,5,6,5>: Cost 4 vext3 <4,u,6,2>, <5,6,5,7>
+ 4029385218U, // <2,5,6,6>: Cost 4 vzipr <0,4,2,6>, <3,4,5,6>
+ 3088682294U, // <2,5,6,7>: Cost 3 vtrnr <0,2,4,6>, RHS
+ 3088682295U, // <2,5,6,u>: Cost 3 vtrnr <0,2,4,6>, RHS
+ 2563833958U, // <2,5,7,0>: Cost 3 vext1 <2,2,5,7>, LHS
+ 2551890678U, // <2,5,7,1>: Cost 3 vext1 <0,2,5,7>, <1,0,3,2>
+ 2563835528U, // <2,5,7,2>: Cost 3 vext1 <2,2,5,7>, <2,2,5,7>
+ 3637577878U, // <2,5,7,3>: Cost 4 vext1 <2,2,5,7>, <3,0,1,2>
+ 2563837238U, // <2,5,7,4>: Cost 3 vext1 <2,2,5,7>, RHS
+ 2712834216U, // <2,5,7,5>: Cost 3 vext3 <4,6,u,2>, <5,7,5,7>
+ 2712834220U, // <2,5,7,6>: Cost 3 vext3 <4,6,u,2>, <5,7,6,2>
+ 4174449974U, // <2,5,7,7>: Cost 4 vtrnr <2,2,5,7>, RHS
+ 2563839790U, // <2,5,7,u>: Cost 3 vext1 <2,2,5,7>, LHS
+ 2563842150U, // <2,5,u,0>: Cost 3 vext1 <2,2,5,u>, LHS
+ 2618103598U, // <2,5,u,1>: Cost 3 vext2 <0,1,2,5>, LHS
+ 2563843721U, // <2,5,u,2>: Cost 3 vext1 <2,2,5,u>, <2,2,5,u>
2569816418U, // <2,5,u,3>: Cost 3 vext1 <3,2,5,u>, <3,2,5,u>
- 2569817398U, // <2,5,u,4>: Cost 3 vext1 <3,2,5,u>, RHS
- 2919268459U, // <2,5,u,5>: Cost 3 vzipl <5,5,5,5>, LHS
- 2906669163U, // <2,5,u,6>: Cost 3 vzipl <3,4,5,6>, LHS
- 2690568455U, // <2,5,u,7>: Cost 3 vext3 <1,0,3,2>, <5,u,7,3>
- 2690568464U, // <2,5,u,u>: Cost 3 vext3 <1,0,3,2>, <5,u,u,3>
- 2575794278U, // <2,6,0,0>: Cost 3 vext1 <4,2,6,0>, LHS
- 1594130534U, // <2,6,0,1>: Cost 2 vext2 <u,4,2,6>, LHS
- 2575795878U, // <2,6,0,2>: Cost 3 vext1 <4,2,6,0>, <2,3,0,1>
- 3649538196U, // <2,6,0,3>: Cost 4 vext1 <4,2,6,0>, <3,0,1,0>
+ 2622748735U, // <2,5,u,4>: Cost 3 vext2 <0,u,2,5>, <u,4,5,6>
+ 2618103962U, // <2,5,u,5>: Cost 3 vext2 <0,1,2,5>, RHS
+ 2953669122U, // <2,5,u,6>: Cost 3 vzipr LHS, <3,4,5,6>
+ 2953667584U, // <2,5,u,7>: Cost 3 vzipr LHS, <1,3,5,7>
+ 2618104165U, // <2,5,u,u>: Cost 3 vext2 <0,1,2,5>, LHS
+ 2620096512U, // <2,6,0,0>: Cost 3 vext2 <0,4,2,6>, <0,0,0,0>
+ 1546354790U, // <2,6,0,1>: Cost 2 vext2 <0,4,2,6>, LHS
+ 2620096676U, // <2,6,0,2>: Cost 3 vext2 <0,4,2,6>, <0,2,0,2>
+ 3693838588U, // <2,6,0,3>: Cost 4 vext2 <0,4,2,6>, <0,3,1,0>
1546355036U, // <2,6,0,4>: Cost 2 vext2 <0,4,2,6>, <0,4,2,6>
- 3649539792U, // <2,6,0,5>: Cost 4 vext1 <4,2,6,0>, <5,1,7,3>
- 2720649550U, // <2,6,0,6>: Cost 3 vext3 <6,0,6,2>, <6,0,6,2>
+ 3694502317U, // <2,6,0,5>: Cost 4 vext2 <0,5,2,6>, <0,5,2,6>
+ 2551911246U, // <2,6,0,6>: Cost 3 vext1 <0,2,6,0>, <6,7,0,1>
2720723287U, // <2,6,0,7>: Cost 3 vext3 <6,0,7,2>, <6,0,7,2>
- 1594131101U, // <2,6,0,u>: Cost 2 vext2 <u,4,2,6>, LHS
- 2251764153U, // <2,6,1,0>: Cost 3 vrev <6,2,0,1>
- 2667873076U, // <2,6,1,1>: Cost 3 vext2 <u,4,2,6>, <1,1,1,1>
- 2712244604U, // <2,6,1,2>: Cost 3 vext3 <4,6,0,2>, <6,1,2,3>
- 3794022791U, // <2,6,1,3>: Cost 4 vext3 <6,0,1,2>, <6,1,3,5>
- 3649547325U, // <2,6,1,4>: Cost 4 vext1 <4,2,6,1>, <4,2,6,1>
- 2667873424U, // <2,6,1,5>: Cost 3 vext2 <u,4,2,6>, <1,5,3,7>
- 3667464616U, // <2,6,1,6>: Cost 4 vext1 <7,2,6,1>, <6,1,7,2>
+ 1546355357U, // <2,6,0,u>: Cost 2 vext2 <0,4,2,6>, LHS
+ 2620097270U, // <2,6,1,0>: Cost 3 vext2 <0,4,2,6>, <1,0,3,2>
+ 2620097332U, // <2,6,1,1>: Cost 3 vext2 <0,4,2,6>, <1,1,1,1>
+ 2620097430U, // <2,6,1,2>: Cost 3 vext2 <0,4,2,6>, <1,2,3,0>
+ 2820243558U, // <2,6,1,3>: Cost 3 vuzpr <0,2,4,6>, LHS
+ 2620097598U, // <2,6,1,4>: Cost 3 vext2 <0,4,2,6>, <1,4,3,6>
+ 2620097680U, // <2,6,1,5>: Cost 3 vext2 <0,4,2,6>, <1,5,3,7>
+ 3693839585U, // <2,6,1,6>: Cost 4 vext2 <0,4,2,6>, <1,6,3,7>
2721386920U, // <2,6,1,7>: Cost 3 vext3 <6,1,7,2>, <6,1,7,2>
- 2721460657U, // <2,6,1,u>: Cost 3 vext3 <6,1,u,2>, <6,1,u,2>
- 2708705721U, // <2,6,2,0>: Cost 3 vext3 <4,0,6,2>, <6,2,0,1>
- 3643581174U, // <2,6,2,1>: Cost 4 vext1 <3,2,6,2>, <1,0,3,2>
- 2708705741U, // <2,6,2,2>: Cost 3 vext3 <4,0,6,2>, <6,2,2,3>
- 2667873958U, // <2,6,2,3>: Cost 3 vext2 <u,4,2,6>, <2,3,0,1>
- 2708705756U, // <2,6,2,4>: Cost 3 vext3 <4,0,6,2>, <6,2,4,0>
- 3782447590U, // <2,6,2,5>: Cost 4 vext3 <4,0,6,2>, <6,2,5,1>
- 2657920954U, // <2,6,2,6>: Cost 3 vext2 <6,7,2,6>, <2,6,3,7>
- 2685702650U, // <2,6,2,7>: Cost 3 vext3 <0,2,0,2>, <6,2,7,3>
- 2685702659U, // <2,6,2,u>: Cost 3 vext3 <0,2,0,2>, <6,2,u,3>
- 2575818854U, // <2,6,3,0>: Cost 3 vext1 <4,2,6,3>, LHS
- 3643590018U, // <2,6,3,1>: Cost 4 vext1 <3,2,6,3>, <1,u,3,6>
- 2910027878U, // <2,6,3,2>: Cost 3 vzipl <4,0,6,2>, LHS
- 2581793282U, // <2,6,3,3>: Cost 3 vext1 <5,2,6,3>, <3,4,5,6>
- 2575821887U, // <2,6,3,4>: Cost 3 vext1 <4,2,6,3>, <4,2,6,3>
- 2581794584U, // <2,6,3,5>: Cost 3 vext1 <5,2,6,3>, <5,2,6,3>
- 2925985894U, // <2,6,3,6>: Cost 3 vzipl <6,6,6,6>, LHS
- 1839644774U, // <2,6,3,7>: Cost 2 vzipl RHS, LHS
- 1839652966U, // <2,6,3,u>: Cost 2 vzipl RHS, LHS
- 2575827046U, // <2,6,4,0>: Cost 3 vext1 <4,2,6,4>, LHS
- 3649569526U, // <2,6,4,1>: Cost 4 vext1 <4,2,6,4>, <1,0,3,2>
- 2575828686U, // <2,6,4,2>: Cost 3 vext1 <4,2,6,4>, <2,3,4,5>
+ 2820243563U, // <2,6,1,u>: Cost 3 vuzpr <0,2,4,6>, LHS
+ 2714014137U, // <2,6,2,0>: Cost 3 vext3 <4,u,6,2>, <6,2,0,1>
+ 2712834500U, // <2,6,2,1>: Cost 3 vext3 <4,6,u,2>, <6,2,1,3>
+ 2620098152U, // <2,6,2,2>: Cost 3 vext2 <0,4,2,6>, <2,2,2,2>
+ 2620098214U, // <2,6,2,3>: Cost 3 vext2 <0,4,2,6>, <2,3,0,1>
+ 2632042254U, // <2,6,2,4>: Cost 3 vext2 <2,4,2,6>, <2,4,2,6>
+ 2712834540U, // <2,6,2,5>: Cost 3 vext3 <4,6,u,2>, <6,2,5,7>
+ 2820243660U, // <2,6,2,6>: Cost 3 vuzpr <0,2,4,6>, <0,2,4,6>
+ 2958265654U, // <2,6,2,7>: Cost 3 vzipr <0,u,2,2>, RHS
+ 2620098619U, // <2,6,2,u>: Cost 3 vext2 <0,4,2,6>, <2,u,0,1>
+ 2620098710U, // <2,6,3,0>: Cost 3 vext2 <0,4,2,6>, <3,0,1,2>
+ 3893986982U, // <2,6,3,1>: Cost 4 vuzpr <0,2,4,6>, <2,3,0,1>
+ 2569848762U, // <2,6,3,2>: Cost 3 vext1 <3,2,6,3>, <2,6,3,7>
+ 2620098972U, // <2,6,3,3>: Cost 3 vext2 <0,4,2,6>, <3,3,3,3>
+ 2620099074U, // <2,6,3,4>: Cost 3 vext2 <0,4,2,6>, <3,4,5,6>
+ 3893987022U, // <2,6,3,5>: Cost 4 vuzpr <0,2,4,6>, <2,3,4,5>
+ 3001404644U, // <2,6,3,6>: Cost 3 vzipr LHS, <4,4,6,6>
+ 1879887158U, // <2,6,3,7>: Cost 2 vzipr LHS, RHS
+ 1879887159U, // <2,6,3,u>: Cost 2 vzipr LHS, RHS
+ 2620099484U, // <2,6,4,0>: Cost 3 vext2 <0,4,2,6>, <4,0,6,2>
+ 2620099566U, // <2,6,4,1>: Cost 3 vext2 <0,4,2,6>, <4,1,6,3>
+ 2620099644U, // <2,6,4,2>: Cost 3 vext2 <0,4,2,6>, <4,2,6,0>
3643599207U, // <2,6,4,3>: Cost 4 vext1 <3,2,6,4>, <3,2,6,4>
2575830080U, // <2,6,4,4>: Cost 3 vext1 <4,2,6,4>, <4,2,6,4>
- 1594133814U, // <2,6,4,5>: Cost 2 vext2 <u,4,2,6>, RHS
- 2667875660U, // <2,6,4,6>: Cost 3 vext2 <u,4,2,6>, <4,6,0,2>
- 3772715678U, // <2,6,4,7>: Cost 4 vext3 <2,4,0,2>, <6,4,7,5>
- 1594134057U, // <2,6,4,u>: Cost 2 vext2 <u,4,2,6>, RHS
- 3649577062U, // <2,6,5,0>: Cost 4 vext1 <4,2,6,5>, LHS
+ 1546358070U, // <2,6,4,5>: Cost 2 vext2 <0,4,2,6>, RHS
+ 2667875700U, // <2,6,4,6>: Cost 3 vext2 <u,4,2,6>, <4,6,4,6>
+ 4028042550U, // <2,6,4,7>: Cost 4 vzipr <0,2,2,4>, RHS
+ 1546358313U, // <2,6,4,u>: Cost 2 vext2 <0,4,2,6>, RHS
+ 3693841992U, // <2,6,5,0>: Cost 4 vext2 <0,4,2,6>, <5,0,1,2>
2667876048U, // <2,6,5,1>: Cost 3 vext2 <u,4,2,6>, <5,1,7,3>
- 2712244932U, // <2,6,5,2>: Cost 3 vext3 <4,6,0,2>, <6,5,2,7>
- 3741618032U, // <2,6,5,3>: Cost 4 vext2 <u,4,2,6>, <5,3,7,1>
+ 2712834756U, // <2,6,5,2>: Cost 3 vext3 <4,6,u,2>, <6,5,2,7>
+ 3643607400U, // <2,6,5,3>: Cost 4 vext1 <3,2,6,5>, <3,2,6,5>
2252091873U, // <2,6,5,4>: Cost 3 vrev <6,2,4,5>
2667876356U, // <2,6,5,5>: Cost 3 vext2 <u,4,2,6>, <5,5,5,5>
2667876450U, // <2,6,5,6>: Cost 3 vext2 <u,4,2,6>, <5,6,7,0>
- 3779351280U, // <2,6,5,7>: Cost 4 vext3 <3,5,0,2>, <6,5,7,6>
- 2252386821U, // <2,6,5,u>: Cost 3 vrev <6,2,u,5>
- 2620100924U, // <2,6,6,0>: Cost 3 vext2 <0,4,2,6>, <6,0,4,2>
- 3637642185U, // <2,6,6,1>: Cost 4 vext1 <2,2,6,6>, <1,2,u,6>
- 2724336400U, // <2,6,6,2>: Cost 3 vext3 <6,6,2,2>, <6,6,2,2>
- 3741618738U, // <2,6,6,3>: Cost 4 vext2 <u,4,2,6>, <6,3,4,5>
- 3637644598U, // <2,6,6,4>: Cost 4 vext1 <2,2,6,6>, RHS
- 3730338499U, // <2,6,6,5>: Cost 4 vext2 <6,5,2,6>, <6,5,2,6>
- 2712245048U, // <2,6,6,6>: Cost 3 vext3 <4,6,0,2>, <6,6,6,6>
- 2712245058U, // <2,6,6,7>: Cost 3 vext3 <4,6,0,2>, <6,6,7,7>
- 2913395036U, // <2,6,6,u>: Cost 3 vzipl RHS, <0,4,2,6>
- 2712245070U, // <2,6,7,0>: Cost 3 vext3 <4,6,0,2>, <6,7,0,1>
+ 2820246838U, // <2,6,5,7>: Cost 3 vuzpr <0,2,4,6>, RHS
+ 2820246839U, // <2,6,5,u>: Cost 3 vuzpr <0,2,4,6>, RHS
+ 2563899494U, // <2,6,6,0>: Cost 3 vext1 <2,2,6,6>, LHS
+ 3893988683U, // <2,6,6,1>: Cost 4 vuzpr <0,2,4,6>, <4,6,0,1>
+ 2563901072U, // <2,6,6,2>: Cost 3 vext1 <2,2,6,6>, <2,2,6,6>
+ 3893987236U, // <2,6,6,3>: Cost 4 vuzpr <0,2,4,6>, <2,6,1,3>
+ 2563902774U, // <2,6,6,4>: Cost 3 vext1 <2,2,6,6>, RHS
+ 3893988723U, // <2,6,6,5>: Cost 4 vuzpr <0,2,4,6>, <4,6,4,5>
+ 2712834872U, // <2,6,6,6>: Cost 3 vext3 <4,6,u,2>, <6,6,6,6>
+ 2955644214U, // <2,6,6,7>: Cost 3 vzipr <0,4,2,6>, RHS
+ 2955644215U, // <2,6,6,u>: Cost 3 vzipr <0,4,2,6>, RHS
+ 2712834894U, // <2,6,7,0>: Cost 3 vext3 <4,6,u,2>, <6,7,0,1>
2724926296U, // <2,6,7,1>: Cost 3 vext3 <6,7,1,2>, <6,7,1,2>
2725000033U, // <2,6,7,2>: Cost 3 vext3 <6,7,2,2>, <6,7,2,2>
2702365544U, // <2,6,7,3>: Cost 3 vext3 <3,0,1,2>, <6,7,3,0>
- 2712245110U, // <2,6,7,4>: Cost 3 vext3 <4,6,0,2>, <6,7,4,5>
- 3785986939U, // <2,6,7,5>: Cost 4 vext3 <4,6,0,2>, <6,7,5,1>
+ 2712834934U, // <2,6,7,4>: Cost 3 vext3 <4,6,u,2>, <6,7,4,5>
+ 3776107393U, // <2,6,7,5>: Cost 4 vext3 <3,0,1,2>, <6,7,5,7>
2725294981U, // <2,6,7,6>: Cost 3 vext3 <6,7,6,2>, <6,7,6,2>
2726253452U, // <2,6,7,7>: Cost 3 vext3 <7,0,1,2>, <6,7,7,0>
- 2712245142U, // <2,6,7,u>: Cost 3 vext3 <4,6,0,2>, <6,7,u,1>
- 2575859814U, // <2,6,u,0>: Cost 3 vext1 <4,2,6,u>, LHS
- 1594136366U, // <2,6,u,1>: Cost 2 vext2 <u,4,2,6>, LHS
- 2708706227U, // <2,6,u,2>: Cost 3 vext3 <4,0,6,2>, <6,u,2,3>
- 2581834242U, // <2,6,u,3>: Cost 3 vext1 <5,2,6,u>, <3,4,5,6>
+ 2712834966U, // <2,6,7,u>: Cost 3 vext3 <4,6,u,2>, <6,7,u,1>
+ 2620102355U, // <2,6,u,0>: Cost 3 vext2 <0,4,2,6>, <u,0,1,2>
+ 1546360622U, // <2,6,u,1>: Cost 2 vext2 <0,4,2,6>, LHS
+ 2620102536U, // <2,6,u,2>: Cost 3 vext2 <0,4,2,6>, <u,2,3,3>
+ 2820244125U, // <2,6,u,3>: Cost 3 vuzpr <0,2,4,6>, LHS
1594136612U, // <2,6,u,4>: Cost 2 vext2 <u,4,2,6>, <u,4,2,6>
- 1594136730U, // <2,6,u,5>: Cost 2 vext2 <u,4,2,6>, RHS
- 2925985899U, // <2,6,u,6>: Cost 3 vzipl <6,6,6,6>, LHS
- 1839644779U, // <2,6,u,7>: Cost 2 vzipl RHS, LHS
- 1839652971U, // <2,6,u,u>: Cost 2 vzipl RHS, LHS
- 2581839974U, // <2,7,0,0>: Cost 3 vext1 <5,2,7,0>, LHS
+ 1546360986U, // <2,6,u,5>: Cost 2 vext2 <0,4,2,6>, RHS
+ 2620102864U, // <2,6,u,6>: Cost 3 vext2 <0,4,2,6>, <u,6,3,7>
+ 1879928118U, // <2,6,u,7>: Cost 2 vzipr LHS, RHS
+ 1879928119U, // <2,6,u,u>: Cost 2 vzipr LHS, RHS
+ 2726179825U, // <2,7,0,0>: Cost 3 vext3 <7,0,0,2>, <7,0,0,2>
1652511738U, // <2,7,0,1>: Cost 2 vext3 <7,0,1,2>, <7,0,1,2>
- 2685703169U, // <2,7,0,2>: Cost 3 vext3 <0,2,0,2>, <7,0,2,0>
+ 2621431972U, // <2,7,0,2>: Cost 3 vext2 <0,6,2,7>, <0,2,0,2>
2257949868U, // <2,7,0,3>: Cost 3 vrev <7,2,3,0>
- 2581843254U, // <2,7,0,4>: Cost 3 vext1 <5,2,7,0>, RHS
- 2581843742U, // <2,7,0,5>: Cost 3 vext1 <5,2,7,0>, <5,2,7,0>
- 3655586298U, // <2,7,0,6>: Cost 4 vext1 <5,2,7,0>, <6,2,7,3>
+ 2726474773U, // <2,7,0,4>: Cost 3 vext3 <7,0,4,2>, <7,0,4,2>
+ 2620768686U, // <2,7,0,5>: Cost 3 vext2 <0,5,2,7>, <0,5,2,7>
+ 2621432319U, // <2,7,0,6>: Cost 3 vext2 <0,6,2,7>, <0,6,2,7>
2599760953U, // <2,7,0,7>: Cost 3 vext1 <u,2,7,0>, <7,0,u,2>
1653027897U, // <2,7,0,u>: Cost 2 vext3 <7,0,u,2>, <7,0,u,2>
- 2599764070U, // <2,7,1,0>: Cost 3 vext1 <u,2,7,1>, LHS
- 3701146420U, // <2,7,1,1>: Cost 4 vext2 <1,6,2,7>, <1,1,1,1>
- 3713090454U, // <2,7,1,2>: Cost 4 vext2 <3,6,2,7>, <1,2,3,0>
- 3997126953U, // <2,7,1,3>: Cost 4 vzipl <6,2,7,3>, <6,0,2,1>
- 2726253674U, // <2,7,1,4>: Cost 3 vext3 <7,0,1,2>, <7,1,4,6>
- 3785987184U, // <2,7,1,5>: Cost 4 vext3 <4,6,0,2>, <7,1,5,3>
- 3701146840U, // <2,7,1,6>: Cost 4 vext2 <1,6,2,7>, <1,6,2,7>
- 2599769082U, // <2,7,1,7>: Cost 3 vext1 <u,2,7,1>, <7,0,1,2>
- 2599769902U, // <2,7,1,u>: Cost 3 vext1 <u,2,7,1>, LHS
- 2581856358U, // <2,7,2,0>: Cost 3 vext1 <5,2,7,2>, LHS
- 3655598838U, // <2,7,2,1>: Cost 4 vext1 <5,2,7,2>, <1,0,3,2>
- 2587829864U, // <2,7,2,2>: Cost 3 vext1 <6,2,7,2>, <2,2,2,2>
- 3759445167U, // <2,7,2,3>: Cost 4 vext3 <0,2,0,2>, <7,2,3,3>
- 2581859638U, // <2,7,2,4>: Cost 3 vext1 <5,2,7,2>, RHS
- 2581860128U, // <2,7,2,5>: Cost 3 vext1 <5,2,7,2>, <5,2,7,2>
- 2587832825U, // <2,7,2,6>: Cost 3 vext1 <6,2,7,2>, <6,2,7,2>
- 3713091562U, // <2,7,2,7>: Cost 4 vext2 <3,6,2,7>, <2,7,0,1>
- 2581862190U, // <2,7,2,u>: Cost 3 vext1 <5,2,7,2>, LHS
+ 2639348470U, // <2,7,1,0>: Cost 3 vext2 <3,6,2,7>, <1,0,3,2>
+ 3695174452U, // <2,7,1,1>: Cost 4 vext2 <0,6,2,7>, <1,1,1,1>
+ 3695174550U, // <2,7,1,2>: Cost 4 vext2 <0,6,2,7>, <1,2,3,0>
+ 3694511104U, // <2,7,1,3>: Cost 4 vext2 <0,5,2,7>, <1,3,5,7>
+ 3713090594U, // <2,7,1,4>: Cost 4 vext2 <3,6,2,7>, <1,4,0,5>
+ 3693184144U, // <2,7,1,5>: Cost 4 vext2 <0,3,2,7>, <1,5,3,7>
+ 2627405016U, // <2,7,1,6>: Cost 3 vext2 <1,6,2,7>, <1,6,2,7>
+ 3799995519U, // <2,7,1,7>: Cost 4 vext3 <7,0,1,2>, <7,1,7,0>
+ 2639348470U, // <2,7,1,u>: Cost 3 vext2 <3,6,2,7>, <1,0,3,2>
+ 3695175101U, // <2,7,2,0>: Cost 4 vext2 <0,6,2,7>, <2,0,1,2>
+ 3643655168U, // <2,7,2,1>: Cost 4 vext1 <3,2,7,2>, <1,3,5,7>
+ 2257892517U, // <2,7,2,2>: Cost 3 vrev <7,2,2,2>
+ 3695175334U, // <2,7,2,3>: Cost 4 vext2 <0,6,2,7>, <2,3,0,1>
+ 3695175465U, // <2,7,2,4>: Cost 4 vext2 <0,6,2,7>, <2,4,5,6>
+ 2632714080U, // <2,7,2,5>: Cost 3 vext2 <2,5,2,7>, <2,5,2,7>
+ 2633377713U, // <2,7,2,6>: Cost 3 vext2 <2,6,2,7>, <2,6,2,7>
+ 3695175658U, // <2,7,2,7>: Cost 4 vext2 <0,6,2,7>, <2,7,0,1>
+ 2634704979U, // <2,7,2,u>: Cost 3 vext2 <2,u,2,7>, <2,u,2,7>
1514094694U, // <2,7,3,0>: Cost 2 vext1 <6,2,7,3>, LHS
- 2587837174U, // <2,7,3,1>: Cost 3 vext1 <6,2,7,3>, <1,0,3,2>
- 2581866098U, // <2,7,3,2>: Cost 3 vext1 <5,2,7,3>, <2,2,3,3>
- 2916745318U, // <2,7,3,3>: Cost 3 vzipl <5,1,7,3>, LHS
+ 2569921680U, // <2,7,3,1>: Cost 3 vext1 <3,2,7,3>, <1,5,3,7>
+ 2587838056U, // <2,7,3,2>: Cost 3 vext1 <6,2,7,3>, <2,2,2,2>
+ 2569922927U, // <2,7,3,3>: Cost 3 vext1 <3,2,7,3>, <3,2,7,3>
1514097974U, // <2,7,3,4>: Cost 2 vext1 <6,2,7,3>, RHS
2581868321U, // <2,7,3,5>: Cost 3 vext1 <5,2,7,3>, <5,2,7,3>
1514099194U, // <2,7,3,6>: Cost 2 vext1 <6,2,7,3>, <6,2,7,3>
- 2919432294U, // <2,7,3,7>: Cost 3 vzipl <5,5,7,7>, LHS
+ 2587841530U, // <2,7,3,7>: Cost 3 vext1 <6,2,7,3>, <7,0,1,2>
1514100526U, // <2,7,3,u>: Cost 2 vext1 <6,2,7,3>, LHS
- 2581872742U, // <2,7,4,0>: Cost 3 vext1 <5,2,7,4>, LHS
- 2581873562U, // <2,7,4,1>: Cost 3 vext1 <5,2,7,4>, <1,2,3,4>
- 3655616042U, // <2,7,4,2>: Cost 4 vext1 <5,2,7,4>, <2,1,4,3>
+ 2708706617U, // <2,7,4,0>: Cost 3 vext3 <4,0,6,2>, <7,4,0,6>
+ 3649643418U, // <2,7,4,1>: Cost 4 vext1 <4,2,7,4>, <1,2,3,4>
+ 3649644330U, // <2,7,4,2>: Cost 4 vext1 <4,2,7,4>, <2,4,5,7>
2257982640U, // <2,7,4,3>: Cost 3 vrev <7,2,3,4>
- 2581876022U, // <2,7,4,4>: Cost 3 vext1 <5,2,7,4>, RHS
- 2639351094U, // <2,7,4,5>: Cost 3 vext2 <3,6,2,7>, RHS
- 2712245609U, // <2,7,4,6>: Cost 3 vext3 <4,6,0,2>, <7,4,6,0>
- 3785987447U, // <2,7,4,7>: Cost 4 vext3 <4,6,0,2>, <7,4,7,5>
- 2639351337U, // <2,7,4,u>: Cost 3 vext2 <3,6,2,7>, RHS
- 2599796838U, // <2,7,5,0>: Cost 3 vext1 <u,2,7,5>, LHS
- 3713093328U, // <2,7,5,1>: Cost 4 vext2 <3,6,2,7>, <5,1,7,3>
- 3712429856U, // <2,7,5,2>: Cost 4 vext2 <3,5,2,7>, <5,2,7,2>
- 3997127281U, // <2,7,5,3>: Cost 4 vzipl <6,2,7,3>, <6,4,2,5>
+ 3649645641U, // <2,7,4,4>: Cost 4 vext1 <4,2,7,4>, <4,2,7,4>
+ 2621435190U, // <2,7,4,5>: Cost 3 vext2 <0,6,2,7>, RHS
+ 2712835441U, // <2,7,4,6>: Cost 3 vext3 <4,6,u,2>, <7,4,6,u>
+ 3799995762U, // <2,7,4,7>: Cost 4 vext3 <7,0,1,2>, <7,4,7,0>
+ 2621435433U, // <2,7,4,u>: Cost 3 vext2 <0,6,2,7>, RHS
+ 2729497990U, // <2,7,5,0>: Cost 3 vext3 <7,5,0,2>, <7,5,0,2>
+ 3643679744U, // <2,7,5,1>: Cost 4 vext1 <3,2,7,5>, <1,3,5,7>
+ 3637708424U, // <2,7,5,2>: Cost 4 vext1 <2,2,7,5>, <2,2,5,7>
+ 3643681137U, // <2,7,5,3>: Cost 4 vext1 <3,2,7,5>, <3,2,7,5>
2599800118U, // <2,7,5,4>: Cost 3 vext1 <u,2,7,5>, RHS
- 3785987510U, // <2,7,5,5>: Cost 4 vext3 <4,6,0,2>, <7,5,5,5>
- 3785987521U, // <2,7,5,6>: Cost 4 vext3 <4,6,0,2>, <7,5,6,7>
+ 3786577334U, // <2,7,5,5>: Cost 4 vext3 <4,6,u,2>, <7,5,5,5>
+ 3786577345U, // <2,7,5,6>: Cost 4 vext3 <4,6,u,2>, <7,5,6,7>
2599802214U, // <2,7,5,7>: Cost 3 vext1 <u,2,7,5>, <7,4,5,6>
2599802670U, // <2,7,5,u>: Cost 3 vext1 <u,2,7,5>, LHS
- 2599805030U, // <2,7,6,0>: Cost 3 vext1 <u,2,7,6>, LHS
- 3713094057U, // <2,7,6,1>: Cost 4 vext2 <3,6,2,7>, <6,1,7,3>
- 2639352314U, // <2,7,6,2>: Cost 3 vext2 <3,6,2,7>, <6,2,7,3>
- 3990487388U, // <2,7,6,3>: Cost 4 vzipl <5,1,7,3>, <0,4,2,6>
- 2599808310U, // <2,7,6,4>: Cost 3 vext1 <u,2,7,6>, RHS
- 2656604868U, // <2,7,6,5>: Cost 3 vext2 <6,5,2,7>, <6,5,2,7>
- 3785987601U, // <2,7,6,6>: Cost 4 vext3 <4,6,0,2>, <7,6,6,6>
- 3713094479U, // <2,7,6,7>: Cost 4 vext2 <3,6,2,7>, <6,7,0,2>
- 2599810862U, // <2,7,6,u>: Cost 3 vext1 <u,2,7,6>, LHS
+ 2581889126U, // <2,7,6,0>: Cost 3 vext1 <5,2,7,6>, LHS
+ 3643687936U, // <2,7,6,1>: Cost 4 vext1 <3,2,7,6>, <1,3,5,7>
+ 2663240186U, // <2,7,6,2>: Cost 3 vext2 <7,6,2,7>, <6,2,7,3>
+ 3643689330U, // <2,7,6,3>: Cost 4 vext1 <3,2,7,6>, <3,2,7,6>
+ 2581892406U, // <2,7,6,4>: Cost 3 vext1 <5,2,7,6>, RHS
+ 2581892900U, // <2,7,6,5>: Cost 3 vext1 <5,2,7,6>, <5,2,7,6>
+ 2587865597U, // <2,7,6,6>: Cost 3 vext1 <6,2,7,6>, <6,2,7,6>
+ 3786577428U, // <2,7,6,7>: Cost 4 vext3 <4,6,u,2>, <7,6,7,0>
+ 2581894958U, // <2,7,6,u>: Cost 3 vext1 <5,2,7,6>, LHS
2726254119U, // <2,7,7,0>: Cost 3 vext3 <7,0,1,2>, <7,7,0,1>
- 3799995955U, // <2,7,7,1>: Cost 4 vext3 <7,0,1,2>, <7,7,1,4>
- 3713094831U, // <2,7,7,2>: Cost 4 vext2 <3,6,2,7>, <7,2,3,3>
- 3997125258U, // <2,7,7,3>: Cost 4 vzipl <6,2,7,3>, <3,6,2,7>
- 3785987663U, // <2,7,7,4>: Cost 4 vext3 <4,6,0,2>, <7,7,4,5>
+ 3804640817U, // <2,7,7,1>: Cost 4 vext3 <7,7,1,2>, <7,7,1,2>
+ 3637724826U, // <2,7,7,2>: Cost 4 vext1 <2,2,7,7>, <2,2,7,7>
+ 3734992123U, // <2,7,7,3>: Cost 4 vext2 <7,3,2,7>, <7,3,2,7>
+ 2552040758U, // <2,7,7,4>: Cost 3 vext1 <0,2,7,7>, RHS
3799995992U, // <2,7,7,5>: Cost 4 vext3 <7,0,1,2>, <7,7,5,5>
2663241198U, // <2,7,7,6>: Cost 3 vext2 <7,6,2,7>, <7,6,2,7>
- 2712245868U, // <2,7,7,7>: Cost 3 vext3 <4,6,0,2>, <7,7,7,7>
+ 2712835692U, // <2,7,7,7>: Cost 3 vext3 <4,6,u,2>, <7,7,7,7>
2731562607U, // <2,7,7,u>: Cost 3 vext3 <7,u,1,2>, <7,7,u,1>
1514135654U, // <2,7,u,0>: Cost 2 vext1 <6,2,7,u>, LHS
1657820802U, // <2,7,u,1>: Cost 2 vext3 <7,u,1,2>, <7,u,1,2>
- 2640680876U, // <2,7,u,2>: Cost 3 vext2 <3,u,2,7>, <u,2,7,3>
- 2916745323U, // <2,7,u,3>: Cost 3 vzipl <5,1,7,3>, LHS
+ 2587879016U, // <2,7,u,2>: Cost 3 vext1 <6,2,7,u>, <2,2,2,2>
+ 2569963892U, // <2,7,u,3>: Cost 3 vext1 <3,2,7,u>, <3,2,7,u>
1514138934U, // <2,7,u,4>: Cost 2 vext1 <6,2,7,u>, RHS
- 2639354010U, // <2,7,u,5>: Cost 3 vext2 <3,6,2,7>, RHS
+ 2621438106U, // <2,7,u,5>: Cost 3 vext2 <0,6,2,7>, RHS
1514140159U, // <2,7,u,6>: Cost 2 vext1 <6,2,7,u>, <6,2,7,u>
- 2919432299U, // <2,7,u,7>: Cost 3 vzipl <5,5,7,7>, LHS
+ 2587882490U, // <2,7,u,7>: Cost 3 vext1 <6,2,7,u>, <7,0,1,2>
1514141486U, // <2,7,u,u>: Cost 2 vext1 <6,2,7,u>, LHS
1544380416U, // <2,u,0,0>: Cost 2 vext2 LHS, <0,0,0,0>
470638699U, // <2,u,0,1>: Cost 1 vext2 LHS, LHS
1544380580U, // <2,u,0,2>: Cost 2 vext2 LHS, <0,2,0,2>
1658631909U, // <2,u,0,3>: Cost 2 vext3 <u,0,3,2>, <u,0,3,2>
- 1484287286U, // <2,u,0,4>: Cost 2 vext1 <1,2,u,0>, RHS
- 2685703926U, // <2,u,0,5>: Cost 3 vext3 <0,2,0,2>, <u,0,5,1>
+ 1544380754U, // <2,u,0,4>: Cost 2 vext2 LHS, <0,4,1,5>
+ 2665898414U, // <2,u,0,5>: Cost 3 vext2 LHS, <0,5,2,7>
1658853120U, // <2,u,0,6>: Cost 2 vext3 <u,0,6,2>, <u,0,6,2>
- 3049595798U, // <2,u,0,7>: Cost 3 vtrnl RHS, <1,2,3,0>
+ 3094531625U, // <2,u,0,7>: Cost 3 vtrnr <1,2,3,0>, RHS
470639261U, // <2,u,0,u>: Cost 1 vext2 LHS, LHS
1544381174U, // <2,u,1,0>: Cost 2 vext2 LHS, <1,0,3,2>
1544381236U, // <2,u,1,1>: Cost 2 vext2 LHS, <1,1,1,1>
1544381334U, // <2,u,1,2>: Cost 2 vext2 LHS, <1,2,3,0>
- 2618123214U, // <2,u,1,3>: Cost 3 vext2 LHS, <1,3,0,2>
- 2552065334U, // <2,u,1,4>: Cost 3 vext1 <0,2,u,1>, RHS
- 1592157328U, // <2,u,1,5>: Cost 2 vext2 LHS, <1,5,3,7>
- 2587898369U, // <2,u,1,6>: Cost 3 vext1 <6,2,u,1>, <6,2,u,1>
- 2685704027U, // <2,u,1,7>: Cost 3 vext3 <0,2,0,2>, <u,1,7,3>
- 1611962212U, // <2,u,1,u>: Cost 2 vext3 <0,2,0,2>, LHS
- 1659737964U, // <2,u,2,0>: Cost 2 vext3 <u,2,0,2>, <u,2,0,2>
- 2618123782U, // <2,u,2,1>: Cost 3 vext2 LHS, <2,1,0,3>
+ 1544381400U, // <2,u,1,3>: Cost 2 vext2 LHS, <1,3,1,3>
+ 2618123325U, // <2,u,1,4>: Cost 3 vext2 LHS, <1,4,3,5>
+ 1544381584U, // <2,u,1,5>: Cost 2 vext2 LHS, <1,5,3,7>
+ 2618123489U, // <2,u,1,6>: Cost 3 vext2 LHS, <1,6,3,7>
+ 2726254427U, // <2,u,1,7>: Cost 3 vext3 <7,0,1,2>, <u,1,7,3>
+ 1544381823U, // <2,u,1,u>: Cost 2 vext2 LHS, <1,u,3,3>
+ 1478328422U, // <2,u,2,0>: Cost 2 vext1 <0,2,u,2>, LHS
+ 2618123807U, // <2,u,2,1>: Cost 3 vext2 LHS, <2,1,3,1>
269271142U, // <2,u,2,2>: Cost 1 vdup2 LHS
1544382118U, // <2,u,2,3>: Cost 2 vext2 LHS, <2,3,0,1>
- 1477741878U, // <2,u,2,4>: Cost 2 vext1 <0,2,0,2>, RHS
- 2581933865U, // <2,u,2,5>: Cost 3 vext1 <5,2,u,2>, <5,2,u,2>
- 1592158138U, // <2,u,2,6>: Cost 2 vext2 LHS, <2,6,3,7>
- 2685704108U, // <2,u,2,7>: Cost 3 vext3 <0,2,0,2>, <u,2,7,3>
+ 1478331702U, // <2,u,2,4>: Cost 2 vext1 <0,2,u,2>, RHS
+ 2618124136U, // <2,u,2,5>: Cost 3 vext2 LHS, <2,5,3,6>
+ 1544382394U, // <2,u,2,6>: Cost 2 vext2 LHS, <2,6,3,7>
+ 3088354857U, // <2,u,2,7>: Cost 3 vtrnr <0,2,0,2>, RHS
269271142U, // <2,u,2,u>: Cost 1 vdup2 LHS
1544382614U, // <2,u,3,0>: Cost 2 vext2 LHS, <3,0,1,2>
- 2618124510U, // <2,u,3,1>: Cost 3 vext2 LHS, <3,1,0,2>
+ 2953627374U, // <2,u,3,1>: Cost 3 vzipr LHS, <2,3,u,1>
1490282143U, // <2,u,3,2>: Cost 2 vext1 <2,2,u,3>, <2,2,u,3>
- 1544382876U, // <2,u,3,3>: Cost 2 vext2 LHS, <3,3,3,3>
+ 1879883932U, // <2,u,3,3>: Cost 2 vzipr LHS, LHS
1544382978U, // <2,u,3,4>: Cost 2 vext2 LHS, <3,4,5,6>
- 2618124834U, // <2,u,3,5>: Cost 3 vext2 LHS, <3,5,0,2>
+ 2953627378U, // <2,u,3,5>: Cost 3 vzipr LHS, <2,3,u,5>
1514172931U, // <2,u,3,6>: Cost 2 vext1 <6,2,u,3>, <6,2,u,3>
- 1839792230U, // <2,u,3,7>: Cost 2 vzipl RHS, LHS
- 1544383262U, // <2,u,3,u>: Cost 2 vext2 LHS, <3,u,1,2>
- 1544383378U, // <2,u,4,0>: Cost 2 vext2 LHS, <4,0,5,1>
+ 1879887176U, // <2,u,3,7>: Cost 2 vzipr LHS, RHS
+ 1879883937U, // <2,u,3,u>: Cost 2 vzipr LHS, LHS
+ 1484316774U, // <2,u,4,0>: Cost 2 vext1 <1,2,u,4>, LHS
1484317639U, // <2,u,4,1>: Cost 2 vext1 <1,2,u,4>, <1,2,u,4>
- 2618125366U, // <2,u,4,2>: Cost 3 vext2 LHS, <4,2,5,3>
+ 2552088270U, // <2,u,4,2>: Cost 3 vext1 <0,2,u,4>, <2,3,4,5>
1190213513U, // <2,u,4,3>: Cost 2 vrev <u,2,3,4>
1484320054U, // <2,u,4,4>: Cost 2 vext1 <1,2,u,4>, RHS
470641974U, // <2,u,4,5>: Cost 1 vext2 LHS, RHS
- 1544383820U, // <2,u,4,6>: Cost 2 vext2 LHS, <4,6,0,2>
- 3049595802U, // <2,u,4,7>: Cost 3 vtrnl RHS, <1,2,3,4>
+ 1592159604U, // <2,u,4,6>: Cost 2 vext2 LHS, <4,6,4,6>
+ 3094564393U, // <2,u,4,7>: Cost 3 vtrnr <1,2,3,4>, RHS
470642217U, // <2,u,4,u>: Cost 1 vext2 LHS, RHS
- 2618125950U, // <2,u,5,0>: Cost 3 vext2 LHS, <5,0,7,2>
- 1544384208U, // <2,u,5,1>: Cost 2 vext2 LHS, <5,1,7,3>
- 2618126104U, // <2,u,5,2>: Cost 3 vext2 LHS, <5,2,6,3>
- 2570013050U, // <2,u,5,3>: Cost 3 vext1 <3,2,u,5>, <3,2,u,5>
+ 2552094959U, // <2,u,5,0>: Cost 3 vext1 <0,2,u,5>, <0,2,u,5>
+ 1592159952U, // <2,u,5,1>: Cost 2 vext2 LHS, <5,1,7,3>
+ 2564040353U, // <2,u,5,2>: Cost 3 vext1 <2,2,u,5>, <2,2,u,5>
+ 2690275455U, // <2,u,5,3>: Cost 3 vext3 <0,u,u,2>, <u,5,3,7>
1592160198U, // <2,u,5,4>: Cost 2 vext2 LHS, <5,4,7,6>
1592160260U, // <2,u,5,5>: Cost 2 vext2 LHS, <5,5,5,5>
1611962522U, // <2,u,5,6>: Cost 2 vext3 <0,2,0,2>, RHS
- 2622771318U, // <2,u,5,7>: Cost 3 vext2 LHS, <5,7,0,2>
+ 1592160424U, // <2,u,5,7>: Cost 2 vext2 LHS, <5,7,5,7>
1611962540U, // <2,u,5,u>: Cost 2 vext3 <0,2,0,2>, RHS
- 1662392496U, // <2,u,6,0>: Cost 2 vext3 <u,6,0,2>, <u,6,0,2>
- 2618126716U, // <2,u,6,1>: Cost 3 vext2 LHS, <6,1,2,3>
- 1544385018U, // <2,u,6,2>: Cost 2 vext2 LHS, <6,2,7,3>
- 2712246480U, // <2,u,6,3>: Cost 3 vext3 <4,6,0,2>, <u,6,3,7>
- 1525845302U, // <2,u,6,4>: Cost 2 vext1 <u,2,4,6>, RHS
- 2656613061U, // <2,u,6,5>: Cost 3 vext2 <6,5,2,u>, <6,5,2,u>
+ 1478361190U, // <2,u,6,0>: Cost 2 vext1 <0,2,u,6>, LHS
+ 2552103670U, // <2,u,6,1>: Cost 3 vext1 <0,2,u,6>, <1,0,3,2>
+ 1592160762U, // <2,u,6,2>: Cost 2 vext2 LHS, <6,2,7,3>
+ 2685704400U, // <2,u,6,3>: Cost 3 vext3 <0,2,0,2>, <u,6,3,7>
+ 1478364470U, // <2,u,6,4>: Cost 2 vext1 <0,2,u,6>, RHS
+ 2901891226U, // <2,u,6,5>: Cost 3 vzipl <2,6,3,7>, RHS
1592161080U, // <2,u,6,6>: Cost 2 vext2 LHS, <6,6,6,6>
1592161102U, // <2,u,6,7>: Cost 2 vext2 LHS, <6,7,0,1>
- 1549030368U, // <2,u,6,u>: Cost 2 vext2 LHS, <6,u,7,3>
+ 1478367022U, // <2,u,6,u>: Cost 2 vext1 <0,2,u,6>, LHS
1592161274U, // <2,u,7,0>: Cost 2 vext2 LHS, <7,0,1,2>
2659931226U, // <2,u,7,1>: Cost 3 vext2 <7,1,2,u>, <7,1,2,u>
- 2618127535U, // <2,u,7,2>: Cost 3 vext2 LHS, <7,2,3,3>
+ 2564056739U, // <2,u,7,2>: Cost 3 vext1 <2,2,u,7>, <2,2,u,7>
2665903331U, // <2,u,7,3>: Cost 3 vext2 LHS, <7,3,0,1>
1592161638U, // <2,u,7,4>: Cost 2 vext2 LHS, <7,4,5,6>
- 2665903508U, // <2,u,7,5>: Cost 3 vext2 LHS, <7,5,1,7>
- 2663249391U, // <2,u,7,6>: Cost 3 vext2 <7,6,2,u>, <7,6,2,u>
+ 2665903494U, // <2,u,7,5>: Cost 3 vext2 LHS, <7,5,0,2>
+ 2587947527U, // <2,u,7,6>: Cost 3 vext1 <6,2,u,7>, <6,2,u,7>
1592161900U, // <2,u,7,7>: Cost 2 vext2 LHS, <7,7,7,7>
1592161922U, // <2,u,7,u>: Cost 2 vext2 LHS, <7,u,1,2>
- 1544386258U, // <2,u,u,0>: Cost 2 vext2 LHS, <u,0,1,1>
+ 1478377574U, // <2,u,u,0>: Cost 2 vext1 <0,2,u,u>, LHS
470644526U, // <2,u,u,1>: Cost 1 vext2 LHS, LHS
269271142U, // <2,u,u,2>: Cost 1 vdup2 LHS
- 1813217387U, // <2,u,u,3>: Cost 2 vzipl LHS, LHS
- 1549031487U, // <2,u,u,4>: Cost 2 vext2 LHS, <u,4,5,6>
+ 1879924892U, // <2,u,u,3>: Cost 2 vzipr LHS, LHS
+ 1478380854U, // <2,u,u,4>: Cost 2 vext1 <0,2,u,u>, RHS
470644890U, // <2,u,u,5>: Cost 1 vext2 LHS, RHS
- 1544386736U, // <2,u,u,6>: Cost 2 vext2 LHS, <u,6,0,2>
- 1839792235U, // <2,u,u,7>: Cost 2 vzipl RHS, LHS
+ 1611962765U, // <2,u,u,6>: Cost 2 vext3 <0,2,0,2>, RHS
+ 1879928136U, // <2,u,u,7>: Cost 2 vzipr LHS, RHS
470645093U, // <2,u,u,u>: Cost 1 vext2 LHS, LHS
1611448320U, // <3,0,0,0>: Cost 2 vext3 LHS, <0,0,0,0>
1611890698U, // <3,0,0,1>: Cost 2 vext3 LHS, <0,0,1,1>
1611890708U, // <3,0,0,2>: Cost 2 vext3 LHS, <0,0,2,2>
- 3763576862U, // <3,0,0,3>: Cost 4 vext3 LHS, <0,0,3,3>
- 2564074806U, // <3,0,0,4>: Cost 3 vext1 <2,3,0,0>, RHS
- 3637817040U, // <3,0,0,5>: Cost 4 vext1 <2,3,0,0>, <5,1,7,3>
- 3637817850U, // <3,0,0,6>: Cost 4 vext1 <2,3,0,0>, <6,2,7,3>
+ 3763576860U, // <3,0,0,3>: Cost 4 vext3 LHS, <0,0,3,1>
+ 2689835045U, // <3,0,0,4>: Cost 3 vext3 LHS, <0,0,4,1>
+ 3698508206U, // <3,0,0,5>: Cost 4 vext2 <1,2,3,0>, <0,5,2,7>
+ 3763576887U, // <3,0,0,6>: Cost 4 vext3 LHS, <0,0,6,1>
3667678434U, // <3,0,0,7>: Cost 4 vext1 <7,3,0,0>, <7,3,0,0>
- 1611890761U, // <3,0,0,u>: Cost 2 vext3 LHS, <0,0,u,1>
+ 1616093258U, // <3,0,0,u>: Cost 2 vext3 LHS, <0,0,u,2>
1490337894U, // <3,0,1,0>: Cost 2 vext1 <2,3,0,1>, LHS
- 2685632605U, // <3,0,1,1>: Cost 3 vext3 LHS, <0,1,1,3>
+ 2685632602U, // <3,0,1,1>: Cost 3 vext3 LHS, <0,1,1,0>
537706598U, // <3,0,1,2>: Cost 1 vext3 LHS, LHS
- 2625430503U, // <3,0,1,3>: Cost 3 vext2 <1,3,3,0>, <1,3,3,0>
+ 2624766936U, // <3,0,1,3>: Cost 3 vext2 <1,2,3,0>, <1,3,1,3>
1490341174U, // <3,0,1,4>: Cost 2 vext1 <2,3,0,1>, RHS
- 2564083408U, // <3,0,1,5>: Cost 3 vext1 <2,3,0,1>, <5,1,7,3>
- 2564084218U, // <3,0,1,6>: Cost 3 vext1 <2,3,0,1>, <6,2,7,3>
+ 2624767120U, // <3,0,1,5>: Cost 3 vext2 <1,2,3,0>, <1,5,3,7>
+ 2732966030U, // <3,0,1,6>: Cost 3 vext3 LHS, <0,1,6,7>
2593944803U, // <3,0,1,7>: Cost 3 vext1 <7,3,0,1>, <7,3,0,1>
537706652U, // <3,0,1,u>: Cost 1 vext3 LHS, LHS
1611890852U, // <3,0,2,0>: Cost 2 vext3 LHS, <0,2,0,2>
- 2685632686U, // <3,0,2,1>: Cost 3 vext3 LHS, <0,2,1,3>
- 2685632695U, // <3,0,2,2>: Cost 3 vext3 LHS, <0,2,2,3>
- 2624767654U, // <3,0,2,3>: Cost 3 vext2 <1,2,3,0>, <2,3,0,1>
- 1659224268U, // <3,0,2,4>: Cost 2 vext3 LHS, <0,2,4,6>
+ 2685632684U, // <3,0,2,1>: Cost 3 vext3 LHS, <0,2,1,1>
+ 2685632692U, // <3,0,2,2>: Cost 3 vext3 LHS, <0,2,2,0>
+ 2685632702U, // <3,0,2,3>: Cost 3 vext3 LHS, <0,2,3,1>
+ 1611890892U, // <3,0,2,4>: Cost 2 vext3 LHS, <0,2,4,6>
2732966102U, // <3,0,2,5>: Cost 3 vext3 LHS, <0,2,5,7>
- 2666571706U, // <3,0,2,6>: Cost 3 vext2 <u,2,3,0>, <2,6,3,7>
- 2732966114U, // <3,0,2,7>: Cost 3 vext3 LHS, <0,2,7,1>
- 1659666668U, // <3,0,2,u>: Cost 2 vext3 LHS, <0,2,u,2>
+ 2624767930U, // <3,0,2,6>: Cost 3 vext2 <1,2,3,0>, <2,6,3,7>
+ 2685632744U, // <3,0,2,7>: Cost 3 vext3 LHS, <0,2,7,7>
+ 1611890924U, // <3,0,2,u>: Cost 2 vext3 LHS, <0,2,u,2>
2624768150U, // <3,0,3,0>: Cost 3 vext2 <1,2,3,0>, <3,0,1,2>
- 2953628060U, // <3,0,3,1>: Cost 3 vzipr LHS, <3,3,3,3>
- 3087845788U, // <3,0,3,2>: Cost 3 vtrnr LHS, <3,3,3,3>
+ 2685632764U, // <3,0,3,1>: Cost 3 vext3 LHS, <0,3,1,0>
+ 2685632774U, // <3,0,3,2>: Cost 3 vext3 LHS, <0,3,2,1>
2624768412U, // <3,0,3,3>: Cost 3 vext2 <1,2,3,0>, <3,3,3,3>
2624768514U, // <3,0,3,4>: Cost 3 vext2 <1,2,3,0>, <3,4,5,6>
- 3698510370U, // <3,0,3,5>: Cost 4 vext2 <1,2,3,0>, <3,5,0,2>
- 3698510474U, // <3,0,3,6>: Cost 4 vext2 <1,2,3,0>, <3,6,2,7>
- 3800588595U, // <3,0,3,7>: Cost 4 vext3 <7,1,0,3>, <0,3,7,1>
- 3088288156U, // <3,0,3,u>: Cost 3 vtrnr LHS, <3,3,3,3>
- 2624768914U, // <3,0,4,0>: Cost 3 vext2 <1,2,3,0>, <4,0,5,1>
- 1659224402U, // <3,0,4,1>: Cost 2 vext3 LHS, <0,4,1,5>
- 1659224412U, // <3,0,4,2>: Cost 2 vext3 LHS, <0,4,2,6>
- 3637848214U, // <3,0,4,3>: Cost 4 vext1 <2,3,0,4>, <3,0,1,2>
- 2564107574U, // <3,0,4,4>: Cost 3 vext1 <2,3,0,4>, RHS
+ 3702491714U, // <3,0,3,5>: Cost 4 vext2 <1,u,3,0>, <3,5,3,7>
+ 2624768632U, // <3,0,3,6>: Cost 3 vext2 <1,2,3,0>, <3,6,0,7>
+ 3702491843U, // <3,0,3,7>: Cost 4 vext2 <1,u,3,0>, <3,7,0,1>
+ 2686959934U, // <3,0,3,u>: Cost 3 vext3 <0,3,u,3>, <0,3,u,3>
+ 2689835336U, // <3,0,4,0>: Cost 3 vext3 LHS, <0,4,0,4>
+ 1611891026U, // <3,0,4,1>: Cost 2 vext3 LHS, <0,4,1,5>
+ 1611891036U, // <3,0,4,2>: Cost 2 vext3 LHS, <0,4,2,6>
+ 3763577184U, // <3,0,4,3>: Cost 4 vext3 LHS, <0,4,3,1>
+ 2689835374U, // <3,0,4,4>: Cost 3 vext3 LHS, <0,4,4,6>
1551027510U, // <3,0,4,5>: Cost 2 vext2 <1,2,3,0>, RHS
- 2624769356U, // <3,0,4,6>: Cost 3 vext2 <1,2,3,0>, <4,6,0,2>
+ 2666573172U, // <3,0,4,6>: Cost 3 vext2 <u,2,3,0>, <4,6,4,6>
3667711206U, // <3,0,4,7>: Cost 4 vext1 <7,3,0,4>, <7,3,0,4>
- 1551027753U, // <3,0,4,u>: Cost 2 vext2 <1,2,3,0>, RHS
- 2732966300U, // <3,0,5,0>: Cost 3 vext3 LHS, <0,5,0,7>
- 2624769744U, // <3,0,5,1>: Cost 3 vext2 <1,2,3,0>, <5,1,7,3>
- 3087845890U, // <3,0,5,2>: Cost 3 vtrnr LHS, <3,4,5,6>
- 3710455664U, // <3,0,5,3>: Cost 4 vext2 <3,2,3,0>, <5,3,7,1>
+ 1616093586U, // <3,0,4,u>: Cost 2 vext3 LHS, <0,4,u,6>
+ 2685190556U, // <3,0,5,0>: Cost 3 vext3 LHS, <0,5,0,7>
+ 2666573520U, // <3,0,5,1>: Cost 3 vext2 <u,2,3,0>, <5,1,7,3>
+ 3040886886U, // <3,0,5,2>: Cost 3 vtrnl <3,4,5,6>, LHS
+ 3625912834U, // <3,0,5,3>: Cost 4 vext1 <0,3,0,5>, <3,4,5,6>
2666573766U, // <3,0,5,4>: Cost 3 vext2 <u,2,3,0>, <5,4,7,6>
2666573828U, // <3,0,5,5>: Cost 3 vext2 <u,2,3,0>, <5,5,5,5>
2732966354U, // <3,0,5,6>: Cost 3 vext3 LHS, <0,5,6,7>
- 3698511990U, // <3,0,5,7>: Cost 4 vext2 <1,2,3,0>, <5,7,0,2>
- 3088288258U, // <3,0,5,u>: Cost 3 vtrnr LHS, <3,4,5,6>
- 2732966381U, // <3,0,6,0>: Cost 3 vext3 LHS, <0,6,0,7>
- 2732966385U, // <3,0,6,1>: Cost 3 vext3 LHS, <0,6,1,2>
- 2624770554U, // <3,0,6,2>: Cost 3 vext2 <1,2,3,0>, <6,2,7,3>
- 3698512458U, // <3,0,6,3>: Cost 4 vext2 <1,2,3,0>, <6,3,7,2>
- 3637865782U, // <3,0,6,4>: Cost 4 vext1 <2,3,0,6>, RHS
+ 2666573992U, // <3,0,5,7>: Cost 3 vext2 <u,2,3,0>, <5,7,5,7>
+ 3040886940U, // <3,0,5,u>: Cost 3 vtrnl <3,4,5,6>, LHS
+ 2685190637U, // <3,0,6,0>: Cost 3 vext3 LHS, <0,6,0,7>
+ 2732966390U, // <3,0,6,1>: Cost 3 vext3 LHS, <0,6,1,7>
+ 2689835519U, // <3,0,6,2>: Cost 3 vext3 LHS, <0,6,2,7>
+ 3667724438U, // <3,0,6,3>: Cost 4 vext1 <7,3,0,6>, <3,0,1,2>
+ 3763577355U, // <3,0,6,4>: Cost 4 vext3 LHS, <0,6,4,1>
3806708243U, // <3,0,6,5>: Cost 4 vext3 LHS, <0,6,5,0>
2666574648U, // <3,0,6,6>: Cost 3 vext2 <u,2,3,0>, <6,6,6,6>
2657948520U, // <3,0,6,7>: Cost 3 vext2 <6,7,3,0>, <6,7,3,0>
- 2624771040U, // <3,0,6,u>: Cost 3 vext2 <1,2,3,0>, <6,u,7,3>
+ 2689835573U, // <3,0,6,u>: Cost 3 vext3 LHS, <0,6,u,7>
2666574842U, // <3,0,7,0>: Cost 3 vext2 <u,2,3,0>, <7,0,1,2>
- 2732966471U, // <3,0,7,1>: Cost 3 vext3 LHS, <0,7,1,7>
+ 2685633095U, // <3,0,7,1>: Cost 3 vext3 LHS, <0,7,1,7>
2660603052U, // <3,0,7,2>: Cost 3 vext2 <7,2,3,0>, <7,2,3,0>
- 3731690723U, // <3,0,7,3>: Cost 4 vext2 <6,7,3,0>, <7,3,0,1>
+ 3643844997U, // <3,0,7,3>: Cost 4 vext1 <3,3,0,7>, <3,3,0,7>
2666575206U, // <3,0,7,4>: Cost 3 vext2 <u,2,3,0>, <7,4,5,6>
- 3806708328U, // <3,0,7,5>: Cost 4 vext3 LHS, <0,7,5,4>
+ 3655790391U, // <3,0,7,5>: Cost 4 vext1 <5,3,0,7>, <5,3,0,7>
3731690968U, // <3,0,7,6>: Cost 4 vext2 <6,7,3,0>, <7,6,0,3>
2666575468U, // <3,0,7,7>: Cost 3 vext2 <u,2,3,0>, <7,7,7,7>
2664584850U, // <3,0,7,u>: Cost 3 vext2 <7,u,3,0>, <7,u,3,0>
- 1611891338U, // <3,0,u,0>: Cost 2 vext3 LHS, <0,u,0,2>
- 1551030062U, // <3,0,u,1>: Cost 2 vext2 <1,2,3,0>, LHS
+ 1616093834U, // <3,0,u,0>: Cost 2 vext3 LHS, <0,u,0,2>
+ 1611891346U, // <3,0,u,1>: Cost 2 vext3 LHS, <0,u,1,1>
537707165U, // <3,0,u,2>: Cost 1 vext3 LHS, LHS
- 2624772028U, // <3,0,u,3>: Cost 3 vext2 <1,2,3,0>, <u,3,0,1>
- 1490398518U, // <3,0,u,4>: Cost 2 vext1 <2,3,0,u>, RHS
+ 2689835684U, // <3,0,u,3>: Cost 3 vext3 LHS, <0,u,3,1>
+ 1616093874U, // <3,0,u,4>: Cost 2 vext3 LHS, <0,u,4,6>
1551030426U, // <3,0,u,5>: Cost 2 vext2 <1,2,3,0>, RHS
- 2624772272U, // <3,0,u,6>: Cost 3 vext2 <1,2,3,0>, <u,6,0,2>
+ 2624772304U, // <3,0,u,6>: Cost 3 vext2 <1,2,3,0>, <u,6,3,7>
2594002154U, // <3,0,u,7>: Cost 3 vext1 <7,3,0,u>, <7,3,0,u>
537707219U, // <3,0,u,u>: Cost 1 vext3 LHS, LHS
- 2685633242U, // <3,1,0,0>: Cost 3 vext3 LHS, <1,0,0,1>
- 2685633251U, // <3,1,0,1>: Cost 3 vext3 LHS, <1,0,1,1>
- 2819410070U, // <3,1,0,2>: Cost 3 vuzpr LHS, <3,0,1,2>
+ 2552201318U, // <3,1,0,0>: Cost 3 vext1 <0,3,1,0>, LHS
+ 2618802278U, // <3,1,0,1>: Cost 3 vext2 <0,2,3,1>, LHS
+ 2618802366U, // <3,1,0,2>: Cost 3 vext2 <0,2,3,1>, <0,2,3,1>
1611449078U, // <3,1,0,3>: Cost 2 vext3 LHS, <1,0,3,2>
- 2564148534U, // <3,1,0,4>: Cost 3 vext1 <2,3,1,0>, RHS
- 3637890768U, // <3,1,0,5>: Cost 4 vext1 <2,3,1,0>, <5,1,7,3>
- 3637891578U, // <3,1,0,6>: Cost 4 vext1 <2,3,1,0>, <6,2,7,3>
+ 2552204598U, // <3,1,0,4>: Cost 3 vext1 <0,3,1,0>, RHS
+ 2732966663U, // <3,1,0,5>: Cost 3 vext3 LHS, <1,0,5,1>
+ 3906258396U, // <3,1,0,6>: Cost 4 vuzpr <2,3,0,1>, <2,0,4,6>
3667752171U, // <3,1,0,7>: Cost 4 vext1 <7,3,1,0>, <7,3,1,0>
1611891491U, // <3,1,0,u>: Cost 2 vext3 LHS, <1,0,u,2>
- 2685633324U, // <3,1,1,0>: Cost 3 vext3 LHS, <1,1,0,2>
+ 2689835819U, // <3,1,1,0>: Cost 3 vext3 LHS, <1,1,0,1>
1611449140U, // <3,1,1,1>: Cost 2 vext3 LHS, <1,1,1,1>
2624775063U, // <3,1,1,2>: Cost 3 vext2 <1,2,3,1>, <1,2,3,1>
1611891528U, // <3,1,1,3>: Cost 2 vext3 LHS, <1,1,3,3>
- 2564156726U, // <3,1,1,4>: Cost 3 vext1 <2,3,1,1>, RHS
- 3637898958U, // <3,1,1,5>: Cost 4 vext1 <2,3,1,1>, <5,1,7,1>
- 3637899687U, // <3,1,1,6>: Cost 4 vext1 <2,3,1,1>, <6,1,7,1>
- 3789161328U, // <3,1,1,7>: Cost 4 vext3 <5,1,7,3>, <1,1,7,7>
+ 2689835859U, // <3,1,1,4>: Cost 3 vext3 LHS, <1,1,4,5>
+ 2689835868U, // <3,1,1,5>: Cost 3 vext3 LHS, <1,1,5,5>
+ 3763577701U, // <3,1,1,6>: Cost 4 vext3 LHS, <1,1,6,5>
+ 3765273452U, // <3,1,1,7>: Cost 4 vext3 <1,1,7,3>, <1,1,7,3>
1611891573U, // <3,1,1,u>: Cost 2 vext3 LHS, <1,1,u,3>
2629420494U, // <3,1,2,0>: Cost 3 vext2 <2,0,3,1>, <2,0,3,1>
- 2685633415U, // <3,1,2,1>: Cost 3 vext3 LHS, <1,2,1,3>
- 2685633424U, // <3,1,2,2>: Cost 3 vext3 LHS, <1,2,2,3>
+ 2689835911U, // <3,1,2,1>: Cost 3 vext3 LHS, <1,2,1,3>
+ 2564163248U, // <3,1,2,2>: Cost 3 vext1 <2,3,1,2>, <2,3,1,2>
1611449238U, // <3,1,2,3>: Cost 2 vext3 LHS, <1,2,3,0>
2564164918U, // <3,1,2,4>: Cost 3 vext1 <2,3,1,2>, RHS
- 2733409195U, // <3,1,2,5>: Cost 3 vext3 LHS, <1,2,5,3>
- 3637907962U, // <3,1,2,6>: Cost 4 vext1 <2,3,1,2>, <6,2,7,3>
+ 2689835947U, // <3,1,2,5>: Cost 3 vext3 LHS, <1,2,5,3>
+ 3692545978U, // <3,1,2,6>: Cost 4 vext2 <0,2,3,1>, <2,6,3,7>
2732966842U, // <3,1,2,7>: Cost 3 vext3 LHS, <1,2,7,0>
1611891651U, // <3,1,2,u>: Cost 2 vext3 LHS, <1,2,u,0>
- 2685633486U, // <3,1,3,0>: Cost 3 vext3 LHS, <1,3,0,2>
- 2558198518U, // <3,1,3,1>: Cost 3 vext1 <1,3,1,3>, <1,0,3,2>
- 3759522785U, // <3,1,3,2>: Cost 4 vext3 <0,2,1,3>, <1,3,2,3>
- 3020736924U, // <3,1,3,3>: Cost 3 vtrnl LHS, <3,3,3,3>
- 2558201142U, // <3,1,3,4>: Cost 3 vext1 <1,3,1,3>, RHS
- 3631943376U, // <3,1,3,5>: Cost 4 vext1 <1,3,1,3>, <5,1,7,3>
- 3631944186U, // <3,1,3,6>: Cost 4 vext1 <1,3,1,3>, <6,2,7,3>
- 3800663052U, // <3,1,3,7>: Cost 4 vext3 <7,1,1,3>, <1,3,7,1>
- 3020777884U, // <3,1,3,u>: Cost 3 vtrnl LHS, <3,3,3,3>
- 2732966946U, // <3,1,4,0>: Cost 3 vext3 LHS, <1,4,0,5>
- 3966141338U, // <3,1,4,1>: Cost 4 vzipl <1,1,1,1>, <1,2,3,4>
+ 1484456038U, // <3,1,3,0>: Cost 2 vext1 <1,3,1,3>, LHS
+ 1611891672U, // <3,1,3,1>: Cost 2 vext3 LHS, <1,3,1,3>
+ 2685633502U, // <3,1,3,2>: Cost 3 vext3 LHS, <1,3,2,0>
+ 2685633512U, // <3,1,3,3>: Cost 3 vext3 LHS, <1,3,3,1>
+ 1484459318U, // <3,1,3,4>: Cost 2 vext1 <1,3,1,3>, RHS
+ 1611891712U, // <3,1,3,5>: Cost 2 vext3 LHS, <1,3,5,7>
+ 2689836041U, // <3,1,3,6>: Cost 3 vext3 LHS, <1,3,6,7>
+ 2733409294U, // <3,1,3,7>: Cost 3 vext3 LHS, <1,3,7,3>
+ 1611891735U, // <3,1,3,u>: Cost 2 vext3 LHS, <1,3,u,3>
+ 2552234086U, // <3,1,4,0>: Cost 3 vext1 <0,3,1,4>, LHS
+ 2732966955U, // <3,1,4,1>: Cost 3 vext3 LHS, <1,4,1,5>
2732966964U, // <3,1,4,2>: Cost 3 vext3 LHS, <1,4,2,5>
- 2222810091U, // <3,1,4,3>: Cost 3 vrev <1,3,3,4>
- 3637923126U, // <3,1,4,4>: Cost 4 vext1 <2,3,1,4>, RHS
- 2624777526U, // <3,1,4,5>: Cost 3 vext2 <1,2,3,1>, RHS
- 2846279830U, // <3,1,4,6>: Cost 3 vuzpr RHS, <3,0,1,2>
+ 2685633597U, // <3,1,4,3>: Cost 3 vext3 LHS, <1,4,3,5>
+ 2552237366U, // <3,1,4,4>: Cost 3 vext1 <0,3,1,4>, RHS
+ 2618805558U, // <3,1,4,5>: Cost 3 vext2 <0,2,3,1>, RHS
+ 2769472822U, // <3,1,4,6>: Cost 3 vuzpl <3,0,1,2>, RHS
3667784943U, // <3,1,4,7>: Cost 4 vext1 <7,3,1,4>, <7,3,1,4>
- 2624777769U, // <3,1,4,u>: Cost 3 vext2 <1,2,3,1>, RHS
- 2600018022U, // <3,1,5,0>: Cost 3 vext1 <u,3,1,5>, LHS
- 2600019088U, // <3,1,5,1>: Cost 3 vext1 <u,3,1,5>, <1,5,3,7>
+ 2685633642U, // <3,1,4,u>: Cost 3 vext3 LHS, <1,4,u,5>
+ 2689836143U, // <3,1,5,0>: Cost 3 vext3 LHS, <1,5,0,1>
+ 2564187280U, // <3,1,5,1>: Cost 3 vext1 <2,3,1,5>, <1,5,3,7>
2564187827U, // <3,1,5,2>: Cost 3 vext1 <2,3,1,5>, <2,3,1,5>
- 1659225232U, // <3,1,5,3>: Cost 2 vext3 LHS, <1,5,3,7>
- 2600021302U, // <3,1,5,4>: Cost 3 vext1 <u,3,1,5>, RHS
- 3719090180U, // <3,1,5,5>: Cost 4 vext2 <4,6,3,1>, <5,5,5,5>
- 3719090274U, // <3,1,5,6>: Cost 4 vext2 <4,6,3,1>, <5,6,7,0>
- 3923380374U, // <3,1,5,7>: Cost 4 vuzpr <5,1,7,3>, <3,0,1,2>
- 1659225277U, // <3,1,5,u>: Cost 2 vext3 LHS, <1,5,u,7>
- 3795797185U, // <3,1,6,0>: Cost 4 vext3 <6,2,7,3>, <1,6,0,2>
- 2732967119U, // <3,1,6,1>: Cost 3 vext3 LHS, <1,6,1,7>
- 3698520570U, // <3,1,6,2>: Cost 4 vext2 <1,2,3,1>, <6,2,7,3>
- 2732967132U, // <3,1,6,3>: Cost 3 vext3 LHS, <1,6,3,2>
- 3933128854U, // <3,1,6,4>: Cost 4 vuzpr <6,7,4,5>, <3,0,1,2>
- 2732967155U, // <3,1,6,5>: Cost 3 vext3 LHS, <1,6,5,7>
- 3719091000U, // <3,1,6,6>: Cost 4 vext2 <4,6,3,1>, <6,6,6,6>
+ 1611891856U, // <3,1,5,3>: Cost 2 vext3 LHS, <1,5,3,7>
+ 2689836183U, // <3,1,5,4>: Cost 3 vext3 LHS, <1,5,4,5>
+ 3759375522U, // <3,1,5,5>: Cost 4 vext3 LHS, <1,5,5,7>
+ 3720417378U, // <3,1,5,6>: Cost 4 vext2 <4,u,3,1>, <5,6,7,0>
+ 2832518454U, // <3,1,5,7>: Cost 3 vuzpr <2,3,0,1>, RHS
+ 1611891901U, // <3,1,5,u>: Cost 2 vext3 LHS, <1,5,u,7>
+ 3763578048U, // <3,1,6,0>: Cost 4 vext3 LHS, <1,6,0,1>
+ 2689836239U, // <3,1,6,1>: Cost 3 vext3 LHS, <1,6,1,7>
+ 2732967128U, // <3,1,6,2>: Cost 3 vext3 LHS, <1,6,2,7>
+ 2685633761U, // <3,1,6,3>: Cost 3 vext3 LHS, <1,6,3,7>
+ 3763578088U, // <3,1,6,4>: Cost 4 vext3 LHS, <1,6,4,5>
+ 2689836275U, // <3,1,6,5>: Cost 3 vext3 LHS, <1,6,5,7>
+ 3763578108U, // <3,1,6,6>: Cost 4 vext3 LHS, <1,6,6,7>
2732967166U, // <3,1,6,7>: Cost 3 vext3 LHS, <1,6,7,0>
- 2732967175U, // <3,1,6,u>: Cost 3 vext3 LHS, <1,6,u,0>
- 3719091194U, // <3,1,7,0>: Cost 4 vext2 <4,6,3,1>, <7,0,1,2>
- 3934210198U, // <3,1,7,1>: Cost 4 vuzpr <7,0,1,2>, <3,0,1,2>
- 4001318032U, // <3,1,7,2>: Cost 4 vzipl <7,0,1,2>, <1,5,3,7>
- 2715419947U, // <3,1,7,3>: Cost 3 vext3 <5,1,7,3>, <1,7,3,0>
- 3719091558U, // <3,1,7,4>: Cost 4 vext2 <4,6,3,1>, <7,4,5,6>
- 3789161790U, // <3,1,7,5>: Cost 4 vext3 <5,1,7,3>, <1,7,5,1>
- 3806709062U, // <3,1,7,6>: Cost 4 vext3 LHS, <1,7,6,0>
- 3719091820U, // <3,1,7,7>: Cost 4 vext2 <4,6,3,1>, <7,7,7,7>
- 2732967256U, // <3,1,7,u>: Cost 3 vext3 LHS, <1,7,u,0>
- 2685633891U, // <3,1,u,0>: Cost 3 vext3 LHS, <1,u,0,2>
- 1611449140U, // <3,1,u,1>: Cost 2 vext3 LHS, <1,1,1,1>
- 2689836406U, // <3,1,u,2>: Cost 3 vext3 LHS, <1,u,2,3>
+ 2685633806U, // <3,1,6,u>: Cost 3 vext3 LHS, <1,6,u,7>
+ 3631972454U, // <3,1,7,0>: Cost 4 vext1 <1,3,1,7>, LHS
+ 2659947612U, // <3,1,7,1>: Cost 3 vext2 <7,1,3,1>, <7,1,3,1>
+ 4036102294U, // <3,1,7,2>: Cost 4 vzipr <1,5,3,7>, <3,0,1,2>
+ 3095396454U, // <3,1,7,3>: Cost 3 vtrnr <1,3,5,7>, LHS
+ 3631975734U, // <3,1,7,4>: Cost 4 vext1 <1,3,1,7>, RHS
+ 2222982144U, // <3,1,7,5>: Cost 3 vrev <1,3,5,7>
+ 3296797705U, // <3,1,7,6>: Cost 4 vrev <1,3,6,7>
+ 3720418924U, // <3,1,7,7>: Cost 4 vext2 <4,u,3,1>, <7,7,7,7>
+ 3095396459U, // <3,1,7,u>: Cost 3 vtrnr <1,3,5,7>, LHS
+ 1484496998U, // <3,1,u,0>: Cost 2 vext1 <1,3,1,u>, LHS
+ 1611892077U, // <3,1,u,1>: Cost 2 vext3 LHS, <1,u,1,3>
+ 2685633907U, // <3,1,u,2>: Cost 3 vext3 LHS, <1,u,2,0>
1611892092U, // <3,1,u,3>: Cost 2 vext3 LHS, <1,u,3,0>
- 2564214070U, // <3,1,u,4>: Cost 3 vext1 <2,3,1,u>, RHS
- 2624780442U, // <3,1,u,5>: Cost 3 vext2 <1,2,3,1>, RHS
- 2870167702U, // <3,1,u,6>: Cost 3 vuzpr RHS, <3,0,1,2>
- 2732967328U, // <3,1,u,7>: Cost 3 vext3 LHS, <1,u,7,0>
- 1616094633U, // <3,1,u,u>: Cost 2 vext3 LHS, <1,u,u,0>
- 2685633972U, // <3,2,0,0>: Cost 3 vext3 LHS, <2,0,0,2>
+ 1484500278U, // <3,1,u,4>: Cost 2 vext1 <1,3,1,u>, RHS
+ 1611892117U, // <3,1,u,5>: Cost 2 vext3 LHS, <1,u,5,7>
+ 2685633950U, // <3,1,u,6>: Cost 3 vext3 LHS, <1,u,6,7>
+ 2832518697U, // <3,1,u,7>: Cost 3 vuzpr <2,3,0,1>, RHS
+ 1611892140U, // <3,1,u,u>: Cost 2 vext3 LHS, <1,u,u,3>
+ 2623455232U, // <3,2,0,0>: Cost 3 vext2 <1,0,3,2>, <0,0,0,0>
1549713510U, // <3,2,0,1>: Cost 2 vext2 <1,0,3,2>, LHS
- 2685633989U, // <3,2,0,2>: Cost 3 vext3 LHS, <2,0,2,1>
- 2886517654U, // <3,2,0,3>: Cost 3 vzipl LHS, <1,2,3,0>
- 2685634008U, // <3,2,0,4>: Cost 3 vext3 LHS, <2,0,4,2>
- 3759375841U, // <3,2,0,5>: Cost 4 vext3 LHS, <2,0,5,2>
- 2685634025U, // <3,2,0,6>: Cost 3 vext3 LHS, <2,0,6,1>
+ 2689836484U, // <3,2,0,2>: Cost 3 vext3 LHS, <2,0,2,0>
+ 2685633997U, // <3,2,0,3>: Cost 3 vext3 LHS, <2,0,3,0>
+ 2623455570U, // <3,2,0,4>: Cost 3 vext2 <1,0,3,2>, <0,4,1,5>
+ 2732967398U, // <3,2,0,5>: Cost 3 vext3 LHS, <2,0,5,7>
+ 2689836524U, // <3,2,0,6>: Cost 3 vext3 LHS, <2,0,6,4>
2229044964U, // <3,2,0,7>: Cost 3 vrev <2,3,7,0>
1549714077U, // <3,2,0,u>: Cost 2 vext2 <1,0,3,2>, LHS
1549714166U, // <3,2,1,0>: Cost 2 vext2 <1,0,3,2>, <1,0,3,2>
2623456052U, // <3,2,1,1>: Cost 3 vext2 <1,0,3,2>, <1,1,1,1>
- 2685634072U, // <3,2,1,2>: Cost 3 vext3 LHS, <2,1,2,3>
- 2685634081U, // <3,2,1,3>: Cost 3 vext3 LHS, <2,1,3,3>
- 2685634090U, // <3,2,1,4>: Cost 3 vext3 LHS, <2,1,4,3>
- 2228905683U, // <3,2,1,5>: Cost 3 vrev <2,3,5,1>
- 2733409852U, // <3,2,1,6>: Cost 3 vext3 LHS, <2,1,6,3>
+ 2623456150U, // <3,2,1,2>: Cost 3 vext2 <1,0,3,2>, <1,2,3,0>
+ 2685634079U, // <3,2,1,3>: Cost 3 vext3 LHS, <2,1,3,1>
+ 2552286518U, // <3,2,1,4>: Cost 3 vext1 <0,3,2,1>, RHS
+ 2623456400U, // <3,2,1,5>: Cost 3 vext2 <1,0,3,2>, <1,5,3,7>
+ 2689836604U, // <3,2,1,6>: Cost 3 vext3 LHS, <2,1,6,3>
3667834101U, // <3,2,1,7>: Cost 4 vext1 <7,3,2,1>, <7,3,2,1>
1155385070U, // <3,2,1,u>: Cost 2 vrev <2,3,u,1>
- 2685634134U, // <3,2,2,0>: Cost 3 vext3 LHS, <2,2,0,2>
- 2228618928U, // <3,2,2,1>: Cost 3 vrev <2,3,1,2>
+ 2689836629U, // <3,2,2,0>: Cost 3 vext3 LHS, <2,2,0,1>
+ 2689836640U, // <3,2,2,1>: Cost 3 vext3 LHS, <2,2,1,3>
1611449960U, // <3,2,2,2>: Cost 2 vext3 LHS, <2,2,2,2>
1611892338U, // <3,2,2,3>: Cost 2 vext3 LHS, <2,2,3,3>
- 2564238646U, // <3,2,2,4>: Cost 3 vext1 <2,3,2,2>, RHS
- 3763578499U, // <3,2,2,5>: Cost 4 vext3 LHS, <2,2,5,2>
- 2228987613U, // <3,2,2,6>: Cost 3 vrev <2,3,6,2>
- 3759376027U, // <3,2,2,7>: Cost 4 vext3 LHS, <2,2,7,u>
+ 2689836669U, // <3,2,2,4>: Cost 3 vext3 LHS, <2,2,4,5>
+ 2689836680U, // <3,2,2,5>: Cost 3 vext3 LHS, <2,2,5,7>
+ 2689836688U, // <3,2,2,6>: Cost 3 vext3 LHS, <2,2,6,6>
+ 3763578518U, // <3,2,2,7>: Cost 4 vext3 LHS, <2,2,7,3>
1611892383U, // <3,2,2,u>: Cost 2 vext3 LHS, <2,2,u,3>
1611450022U, // <3,2,3,0>: Cost 2 vext3 LHS, <2,3,0,1>
2685191854U, // <3,2,3,1>: Cost 3 vext3 LHS, <2,3,1,0>
2685191865U, // <3,2,3,2>: Cost 3 vext3 LHS, <2,3,2,2>
2685191875U, // <3,2,3,3>: Cost 3 vext3 LHS, <2,3,3,3>
1611450062U, // <3,2,3,4>: Cost 2 vext3 LHS, <2,3,4,5>
- 2689836755U, // <3,2,3,5>: Cost 3 vext3 LHS, <2,3,5,1>
- 2689836765U, // <3,2,3,6>: Cost 3 vext3 LHS, <2,3,6,2>
+ 2732967635U, // <3,2,3,5>: Cost 3 vext3 LHS, <2,3,5,1>
+ 2732967645U, // <3,2,3,6>: Cost 3 vext3 LHS, <2,3,6,2>
2732967652U, // <3,2,3,7>: Cost 3 vext3 LHS, <2,3,7,0>
1611450094U, // <3,2,3,u>: Cost 2 vext3 LHS, <2,3,u,1>
- 2685634296U, // <3,2,4,0>: Cost 3 vext3 LHS, <2,4,0,2>
- 2552308470U, // <3,2,4,1>: Cost 3 vext1 <0,3,2,4>, <1,0,3,2>
+ 2558279782U, // <3,2,4,0>: Cost 3 vext1 <1,3,2,4>, LHS
+ 2558280602U, // <3,2,4,1>: Cost 3 vext1 <1,3,2,4>, <1,2,3,4>
2732967692U, // <3,2,4,2>: Cost 3 vext3 LHS, <2,4,2,4>
- 2886517658U, // <3,2,4,3>: Cost 3 vzipl LHS, <1,2,3,4>
- 2228856525U, // <3,2,4,4>: Cost 3 vrev <2,3,4,4>
+ 2685634326U, // <3,2,4,3>: Cost 3 vext3 LHS, <2,4,3,5>
+ 2558283062U, // <3,2,4,4>: Cost 3 vext1 <1,3,2,4>, RHS
1549716790U, // <3,2,4,5>: Cost 2 vext2 <1,0,3,2>, RHS
- 2623458636U, // <3,2,4,6>: Cost 3 vext2 <1,0,3,2>, <4,6,0,2>
+ 2689836844U, // <3,2,4,6>: Cost 3 vext3 LHS, <2,4,6,0>
2229077736U, // <3,2,4,7>: Cost 3 vrev <2,3,7,4>
1549717033U, // <3,2,4,u>: Cost 2 vext2 <1,0,3,2>, RHS
- 2732967758U, // <3,2,5,0>: Cost 3 vext3 LHS, <2,5,0,7>
- 2623459024U, // <3,2,5,1>: Cost 3 vext2 <1,0,3,2>, <5,1,7,3>
- 2732967776U, // <3,2,5,2>: Cost 3 vext3 LHS, <2,5,2,7>
- 2732967779U, // <3,2,5,3>: Cost 3 vext3 LHS, <2,5,3,1>
+ 2552316006U, // <3,2,5,0>: Cost 3 vext1 <0,3,2,5>, LHS
+ 2228643507U, // <3,2,5,1>: Cost 3 vrev <2,3,1,5>
+ 2689836896U, // <3,2,5,2>: Cost 3 vext3 LHS, <2,5,2,7>
+ 2685634408U, // <3,2,5,3>: Cost 3 vext3 LHS, <2,5,3,6>
1155122894U, // <3,2,5,4>: Cost 2 vrev <2,3,4,5>
2665263108U, // <3,2,5,5>: Cost 3 vext2 <u,0,3,2>, <5,5,5,5>
- 2665263202U, // <3,2,5,6>: Cost 3 vext2 <u,0,3,2>, <5,6,7,0>
- 3697201270U, // <3,2,5,7>: Cost 4 vext2 <1,0,3,2>, <5,7,0,2>
+ 2689836932U, // <3,2,5,6>: Cost 3 vext3 LHS, <2,5,6,7>
+ 2665263272U, // <3,2,5,7>: Cost 3 vext2 <u,0,3,2>, <5,7,5,7>
1155417842U, // <3,2,5,u>: Cost 2 vrev <2,3,u,5>
- 2600099942U, // <3,2,6,0>: Cost 3 vext1 <u,3,2,6>, LHS
- 3697201532U, // <3,2,6,1>: Cost 4 vext2 <1,0,3,2>, <6,1,2,3>
- 2623459834U, // <3,2,6,2>: Cost 3 vext2 <1,0,3,2>, <6,2,7,3>
- 1659226042U, // <3,2,6,3>: Cost 2 vext3 LHS, <2,6,3,7>
- 2228872911U, // <3,2,6,4>: Cost 3 vrev <2,3,4,6>
- 2228946648U, // <3,2,6,5>: Cost 3 vrev <2,3,5,6>
- 2665263928U, // <3,2,6,6>: Cost 3 vext2 <u,0,3,2>, <6,6,6,6>
+ 2689836953U, // <3,2,6,0>: Cost 3 vext3 LHS, <2,6,0,1>
+ 2689836964U, // <3,2,6,1>: Cost 3 vext3 LHS, <2,6,1,3>
+ 2689836976U, // <3,2,6,2>: Cost 3 vext3 LHS, <2,6,2,6>
+ 1611892666U, // <3,2,6,3>: Cost 2 vext3 LHS, <2,6,3,7>
+ 2689836993U, // <3,2,6,4>: Cost 3 vext3 LHS, <2,6,4,5>
+ 2689837004U, // <3,2,6,5>: Cost 3 vext3 LHS, <2,6,5,7>
+ 2689837013U, // <3,2,6,6>: Cost 3 vext3 LHS, <2,6,6,7>
2665263950U, // <3,2,6,7>: Cost 3 vext2 <u,0,3,2>, <6,7,0,1>
- 1659226087U, // <3,2,6,u>: Cost 2 vext3 LHS, <2,6,u,7>
+ 1611892711U, // <3,2,6,u>: Cost 2 vext3 LHS, <2,6,u,7>
2665264122U, // <3,2,7,0>: Cost 3 vext2 <u,0,3,2>, <7,0,1,2>
2623460419U, // <3,2,7,1>: Cost 3 vext2 <1,0,3,2>, <7,1,0,3>
- 3697202351U, // <3,2,7,2>: Cost 4 vext2 <1,0,3,2>, <7,2,3,3>
- 2722056196U, // <3,2,7,3>: Cost 3 vext3 <6,2,7,3>, <2,7,3,0>
+ 4169138340U, // <3,2,7,2>: Cost 4 vtrnr <1,3,5,7>, <0,2,0,2>
+ 2962358374U, // <3,2,7,3>: Cost 3 vzipr <1,5,3,7>, LHS
2665264486U, // <3,2,7,4>: Cost 3 vext2 <u,0,3,2>, <7,4,5,6>
- 3302696665U, // <3,2,7,5>: Cost 4 vrev <2,3,5,7>
+ 2228954841U, // <3,2,7,5>: Cost 3 vrev <2,3,5,7>
2229028578U, // <3,2,7,6>: Cost 3 vrev <2,3,6,7>
2665264748U, // <3,2,7,7>: Cost 3 vext2 <u,0,3,2>, <7,7,7,7>
- 2665264762U, // <3,2,7,u>: Cost 3 vext2 <u,0,3,2>, <7,u,0,3>
+ 2962358379U, // <3,2,7,u>: Cost 3 vzipr <1,5,3,7>, LHS
1611892795U, // <3,2,u,0>: Cost 2 vext3 LHS, <2,u,0,1>
1549719342U, // <3,2,u,1>: Cost 2 vext2 <1,0,3,2>, LHS
1611449960U, // <3,2,u,2>: Cost 2 vext3 LHS, <2,2,2,2>
- 1659226204U, // <3,2,u,3>: Cost 2 vext3 LHS, <2,u,3,7>
+ 1611892824U, // <3,2,u,3>: Cost 2 vext3 LHS, <2,u,3,3>
1611892835U, // <3,2,u,4>: Cost 2 vext3 LHS, <2,u,4,5>
1549719706U, // <3,2,u,5>: Cost 2 vext2 <1,0,3,2>, RHS
- 2685634674U, // <3,2,u,6>: Cost 3 vext3 LHS, <2,u,6,2>
+ 2689837168U, // <3,2,u,6>: Cost 3 vext3 LHS, <2,u,6,0>
2665265408U, // <3,2,u,7>: Cost 3 vext2 <u,0,3,2>, <u,7,0,1>
1611892867U, // <3,2,u,u>: Cost 2 vext3 LHS, <2,u,u,1>
2685192331U, // <3,3,0,0>: Cost 3 vext3 LHS, <3,0,0,0>
1611450518U, // <3,3,0,1>: Cost 2 vext3 LHS, <3,0,1,2>
- 2819410332U, // <3,3,0,2>: Cost 3 vuzpr LHS, <3,3,3,3>
- 2685634727U, // <3,3,0,3>: Cost 3 vext3 LHS, <3,0,3,1>
+ 2685634717U, // <3,3,0,2>: Cost 3 vext3 LHS, <3,0,2,0>
+ 2564294806U, // <3,3,0,3>: Cost 3 vext1 <2,3,3,0>, <3,0,1,2>
2685634736U, // <3,3,0,4>: Cost 3 vext3 LHS, <3,0,4,1>
- 2685634746U, // <3,3,0,5>: Cost 3 vext3 LHS, <3,0,5,2>
- 3763579074U, // <3,3,0,6>: Cost 4 vext3 LHS, <3,0,6,1>
- 3667899645U, // <3,3,0,7>: Cost 4 vext1 <7,3,3,0>, <7,3,3,0>
+ 2732968122U, // <3,3,0,5>: Cost 3 vext3 LHS, <3,0,5,2>
+ 3763579075U, // <3,3,0,6>: Cost 4 vext3 LHS, <3,0,6,2>
+ 4034053264U, // <3,3,0,7>: Cost 4 vzipr <1,2,3,0>, <1,5,3,7>
1611450581U, // <3,3,0,u>: Cost 2 vext3 LHS, <3,0,u,2>
2685192415U, // <3,3,1,0>: Cost 3 vext3 LHS, <3,1,0,3>
1550385992U, // <3,3,1,1>: Cost 2 vext2 <1,1,3,3>, <1,1,3,3>
2685192433U, // <3,3,1,2>: Cost 3 vext3 LHS, <3,1,2,3>
- 2685634810U, // <3,3,1,3>: Cost 3 vext3 LHS, <3,1,3,3>
+ 2685634808U, // <3,3,1,3>: Cost 3 vext3 LHS, <3,1,3,1>
2558332214U, // <3,3,1,4>: Cost 3 vext1 <1,3,3,1>, RHS
2685634828U, // <3,3,1,5>: Cost 3 vext3 LHS, <3,1,5,3>
- 3763579157U, // <3,3,1,6>: Cost 4 vext3 LHS, <3,1,6,3>
- 3789162782U, // <3,3,1,7>: Cost 4 vext3 <5,1,7,3>, <3,1,7,3>
- 1550385992U, // <3,3,1,u>: Cost 2 vext2 <1,1,3,3>, <1,1,3,3>
- 2685634864U, // <3,3,2,0>: Cost 3 vext3 LHS, <3,2,0,3>
+ 3759376661U, // <3,3,1,6>: Cost 4 vext3 LHS, <3,1,6,3>
+ 2703477022U, // <3,3,1,7>: Cost 3 vext3 <3,1,7,3>, <3,1,7,3>
+ 1555031423U, // <3,3,1,u>: Cost 2 vext2 <1,u,3,3>, <1,u,3,3>
+ 2564309094U, // <3,3,2,0>: Cost 3 vext1 <2,3,3,2>, LHS
2630100513U, // <3,3,2,1>: Cost 3 vext2 <2,1,3,3>, <2,1,3,3>
1557022322U, // <3,3,2,2>: Cost 2 vext2 <2,2,3,3>, <2,2,3,3>
2685192520U, // <3,3,2,3>: Cost 3 vext3 LHS, <3,2,3,0>
- 2685634900U, // <3,3,2,4>: Cost 3 vext3 LHS, <3,2,4,3>
+ 2564312374U, // <3,3,2,4>: Cost 3 vext1 <2,3,3,2>, RHS
2732968286U, // <3,3,2,5>: Cost 3 vext3 LHS, <3,2,5,4>
- 2732968294U, // <3,3,2,6>: Cost 3 vext3 LHS, <3,2,6,3>
- 2634082311U, // <3,3,2,7>: Cost 3 vext2 <2,7,3,3>, <2,7,3,3>
- 1557022322U, // <3,3,2,u>: Cost 2 vext2 <2,2,3,3>, <2,2,3,3>
+ 2685634918U, // <3,3,2,6>: Cost 3 vext3 LHS, <3,2,6,3>
+ 2704140655U, // <3,3,2,7>: Cost 3 vext3 <3,2,7,3>, <3,2,7,3>
+ 1561004120U, // <3,3,2,u>: Cost 2 vext2 <2,u,3,3>, <2,u,3,3>
1496547430U, // <3,3,3,0>: Cost 2 vext1 <3,3,3,3>, LHS
2624129256U, // <3,3,3,1>: Cost 3 vext2 <1,1,3,3>, <3,1,1,3>
2630764866U, // <3,3,3,2>: Cost 3 vext2 <2,2,3,3>, <3,2,2,3>
336380006U, // <3,3,3,3>: Cost 1 vdup3 LHS
1496550710U, // <3,3,3,4>: Cost 2 vext1 <3,3,3,3>, RHS
- 2570292944U, // <3,3,3,5>: Cost 3 vext1 <3,3,3,3>, <5,1,7,3>
- 2570293754U, // <3,3,3,6>: Cost 3 vext1 <3,3,3,3>, <6,2,7,3>
+ 2732968368U, // <3,3,3,5>: Cost 3 vext3 LHS, <3,3,5,5>
+ 2624129683U, // <3,3,3,6>: Cost 3 vext2 <1,1,3,3>, <3,6,3,7>
2594182400U, // <3,3,3,7>: Cost 3 vext1 <7,3,3,3>, <7,3,3,3>
336380006U, // <3,3,3,u>: Cost 1 vdup3 LHS
- 2689837524U, // <3,3,4,0>: Cost 3 vext3 LHS, <3,4,0,5>
+ 2558353510U, // <3,3,4,0>: Cost 3 vext1 <1,3,3,4>, LHS
2558354411U, // <3,3,4,1>: Cost 3 vext1 <1,3,3,4>, <1,3,3,4>
2564327108U, // <3,3,4,2>: Cost 3 vext1 <2,3,3,4>, <2,3,3,4>
2564327938U, // <3,3,4,3>: Cost 3 vext1 <2,3,3,4>, <3,4,5,6>
- 2893235098U, // <3,3,4,4>: Cost 3 vzipl <1,2,3,4>, <1,2,3,4>
+ 2960343962U, // <3,3,4,4>: Cost 3 vzipr <1,2,3,4>, <1,2,3,4>
1611893250U, // <3,3,4,5>: Cost 2 vext3 LHS, <3,4,5,6>
- 2689837573U, // <3,3,4,6>: Cost 3 vext3 LHS, <3,4,6,0>
- 3667932417U, // <3,3,4,7>: Cost 4 vext1 <7,3,3,4>, <7,3,3,4>
+ 2771619126U, // <3,3,4,6>: Cost 3 vuzpl <3,3,3,3>, RHS
+ 4034086032U, // <3,3,4,7>: Cost 4 vzipr <1,2,3,4>, <1,5,3,7>
1611893277U, // <3,3,4,u>: Cost 2 vext3 LHS, <3,4,u,6>
- 2685635106U, // <3,3,5,0>: Cost 3 vext3 LHS, <3,5,0,2>
- 2689837616U, // <3,3,5,1>: Cost 3 vext3 LHS, <3,5,1,7>
- 2630766369U, // <3,3,5,2>: Cost 3 vext2 <2,2,3,3>, <5,2,7,3>
+ 2558361702U, // <3,3,5,0>: Cost 3 vext1 <1,3,3,5>, LHS
+ 2558362604U, // <3,3,5,1>: Cost 3 vext1 <1,3,3,5>, <1,3,3,5>
+ 2558363342U, // <3,3,5,2>: Cost 3 vext1 <1,3,3,5>, <2,3,4,5>
2732968512U, // <3,3,5,3>: Cost 3 vext3 LHS, <3,5,3,5>
- 2234837415U, // <3,3,5,4>: Cost 3 vrev <3,3,4,5>
- 3034171086U, // <3,3,5,5>: Cost 3 vtrnl <2,3,4,5>, <2,3,4,5>
+ 2558364982U, // <3,3,5,4>: Cost 3 vext1 <1,3,3,5>, RHS
+ 3101279950U, // <3,3,5,5>: Cost 3 vtrnr <2,3,4,5>, <2,3,4,5>
2665934946U, // <3,3,5,6>: Cost 3 vext2 <u,1,3,3>, <5,6,7,0>
- 3763579487U, // <3,3,5,7>: Cost 4 vext3 LHS, <3,5,7,0>
- 2690280048U, // <3,3,5,u>: Cost 3 vext3 LHS, <3,5,u,u>
- 3763579507U, // <3,3,6,0>: Cost 4 vext3 LHS, <3,6,0,2>
- 3763579516U, // <3,3,6,1>: Cost 4 vext3 LHS, <3,6,1,2>
- 2689837706U, // <3,3,6,2>: Cost 3 vext3 LHS, <3,6,2,7>
+ 2826636598U, // <3,3,5,7>: Cost 3 vuzpr <1,3,1,3>, RHS
+ 2826636599U, // <3,3,5,u>: Cost 3 vuzpr <1,3,1,3>, RHS
+ 2732968568U, // <3,3,6,0>: Cost 3 vext3 LHS, <3,6,0,7>
+ 3763579521U, // <3,3,6,1>: Cost 4 vext3 LHS, <3,6,1,7>
+ 2732968586U, // <3,3,6,2>: Cost 3 vext3 LHS, <3,6,2,7>
2732968595U, // <3,3,6,3>: Cost 3 vext3 LHS, <3,6,3,7>
2732968604U, // <3,3,6,4>: Cost 3 vext3 LHS, <3,6,4,7>
- 3806710430U, // <3,3,6,5>: Cost 4 vext3 LHS, <3,6,5,0>
- 2665935672U, // <3,3,6,6>: Cost 3 vext2 <u,1,3,3>, <6,6,6,6>
+ 3763579557U, // <3,3,6,5>: Cost 4 vext3 LHS, <3,6,5,7>
+ 2732968621U, // <3,3,6,6>: Cost 3 vext3 LHS, <3,6,6,6>
2657973099U, // <3,3,6,7>: Cost 3 vext2 <6,7,3,3>, <6,7,3,3>
- 2690280128U, // <3,3,6,u>: Cost 3 vext3 LHS, <3,6,u,7>
- 2665935866U, // <3,3,7,0>: Cost 3 vext2 <u,1,3,3>, <7,0,1,2>
- 2624132172U, // <3,3,7,1>: Cost 3 vext2 <1,1,3,3>, <7,1,1,3>
- 2660627631U, // <3,3,7,2>: Cost 3 vext2 <7,2,3,3>, <7,2,3,3>
+ 2658636732U, // <3,3,6,u>: Cost 3 vext2 <6,u,3,3>, <6,u,3,3>
+ 2558378086U, // <3,3,7,0>: Cost 3 vext1 <1,3,3,7>, LHS
+ 2558378990U, // <3,3,7,1>: Cost 3 vext1 <1,3,3,7>, <1,3,3,7>
+ 2564351687U, // <3,3,7,2>: Cost 3 vext1 <2,3,3,7>, <2,3,3,7>
2661291264U, // <3,3,7,3>: Cost 3 vext2 <7,3,3,3>, <7,3,3,3>
- 2665936230U, // <3,3,7,4>: Cost 3 vext2 <u,1,3,3>, <7,4,5,6>
- 3937192348U, // <3,3,7,5>: Cost 4 vuzpr <7,4,5,6>, <3,3,3,3>
- 3795798778U, // <3,3,7,6>: Cost 4 vext3 <6,2,7,3>, <3,7,6,2>
- 2665936492U, // <3,3,7,7>: Cost 3 vext2 <u,1,3,3>, <7,7,7,7>
- 2664609429U, // <3,3,7,u>: Cost 3 vext2 <7,u,3,3>, <7,u,3,3>
+ 2558381366U, // <3,3,7,4>: Cost 3 vext1 <1,3,3,7>, RHS
+ 2732968694U, // <3,3,7,5>: Cost 3 vext3 LHS, <3,7,5,7>
+ 3781126907U, // <3,3,7,6>: Cost 4 vext3 <3,7,6,3>, <3,7,6,3>
+ 3095397376U, // <3,3,7,7>: Cost 3 vtrnr <1,3,5,7>, <1,3,5,7>
+ 2558383918U, // <3,3,7,u>: Cost 3 vext1 <1,3,3,7>, LHS
1496547430U, // <3,3,u,0>: Cost 2 vext1 <3,3,3,3>, LHS
1611893534U, // <3,3,u,1>: Cost 2 vext3 LHS, <3,u,1,2>
1592858504U, // <3,3,u,2>: Cost 2 vext2 <u,2,3,3>, <u,2,3,3>
336380006U, // <3,3,u,3>: Cost 1 vdup3 LHS
1496550710U, // <3,3,u,4>: Cost 2 vext1 <3,3,3,3>, RHS
1611893574U, // <3,3,u,5>: Cost 2 vext3 LHS, <3,u,5,6>
- 2689837897U, // <3,3,u,6>: Cost 3 vext3 LHS, <3,u,6,0>
- 2732968793U, // <3,3,u,7>: Cost 3 vext3 LHS, <3,u,7,7>
+ 2690280268U, // <3,3,u,6>: Cost 3 vext3 LHS, <3,u,6,3>
+ 2826636841U, // <3,3,u,7>: Cost 3 vuzpr <1,3,1,3>, RHS
336380006U, // <3,3,u,u>: Cost 1 vdup3 LHS
- 2685635429U, // <3,4,0,0>: Cost 3 vext3 LHS, <4,0,0,1>
+ 2624798720U, // <3,4,0,0>: Cost 3 vext2 <1,2,3,4>, <0,0,0,0>
1551056998U, // <3,4,0,1>: Cost 2 vext2 <1,2,3,4>, LHS
2624798884U, // <3,4,0,2>: Cost 3 vext2 <1,2,3,4>, <0,2,0,2>
- 3698540805U, // <3,4,0,3>: Cost 4 vext2 <1,2,3,4>, <0,3,2,0>
- 2564369298U, // <3,4,0,4>: Cost 3 vext1 <2,3,4,0>, <4,0,5,1>
- 1611893650U, // <3,4,0,5>: Cost 2 vext3 LHS, <4,0,5,1>
- 1611893660U, // <3,4,0,6>: Cost 2 vext3 LHS, <4,0,6,2>
+ 3693232384U, // <3,4,0,3>: Cost 4 vext2 <0,3,3,4>, <0,3,1,4>
+ 2624799058U, // <3,4,0,4>: Cost 3 vext2 <1,2,3,4>, <0,4,1,5>
+ 1659227026U, // <3,4,0,5>: Cost 2 vext3 LHS, <4,0,5,1>
+ 1659227036U, // <3,4,0,6>: Cost 2 vext3 LHS, <4,0,6,2>
3667973382U, // <3,4,0,7>: Cost 4 vext1 <7,3,4,0>, <7,3,4,0>
- 1611893677U, // <3,4,0,u>: Cost 2 vext3 LHS, <4,0,u,1>
+ 1551057565U, // <3,4,0,u>: Cost 2 vext2 <1,2,3,4>, LHS
2624799478U, // <3,4,1,0>: Cost 3 vext2 <1,2,3,4>, <1,0,3,2>
2624799540U, // <3,4,1,1>: Cost 3 vext2 <1,2,3,4>, <1,1,1,1>
1551057818U, // <3,4,1,2>: Cost 2 vext2 <1,2,3,4>, <1,2,3,4>
- 2625463275U, // <3,4,1,3>: Cost 3 vext2 <1,3,3,4>, <1,3,3,4>
+ 2624799704U, // <3,4,1,3>: Cost 3 vext2 <1,2,3,4>, <1,3,1,3>
2564377910U, // <3,4,1,4>: Cost 3 vext1 <2,3,4,1>, RHS
- 2732968930U, // <3,4,1,5>: Cost 3 vext3 LHS, <4,1,5,0>
- 2685635566U, // <3,4,1,6>: Cost 3 vext3 LHS, <4,1,6,3>
+ 2689838050U, // <3,4,1,5>: Cost 3 vext3 LHS, <4,1,5,0>
+ 2689838062U, // <3,4,1,6>: Cost 3 vext3 LHS, <4,1,6,3>
2628117807U, // <3,4,1,7>: Cost 3 vext2 <1,7,3,4>, <1,7,3,4>
1555039616U, // <3,4,1,u>: Cost 2 vext2 <1,u,3,4>, <1,u,3,4>
- 3759377422U, // <3,4,2,0>: Cost 4 vext3 LHS, <4,2,0,u>
+ 3626180710U, // <3,4,2,0>: Cost 4 vext1 <0,3,4,2>, LHS
2624800298U, // <3,4,2,1>: Cost 3 vext2 <1,2,3,4>, <2,1,4,3>
2624800360U, // <3,4,2,2>: Cost 3 vext2 <1,2,3,4>, <2,2,2,2>
2624800422U, // <3,4,2,3>: Cost 3 vext2 <1,2,3,4>, <2,3,0,1>
- 2733411373U, // <3,4,2,4>: Cost 3 vext3 LHS, <4,2,4,3>
- 2685635638U, // <3,4,2,5>: Cost 3 vext3 LHS, <4,2,5,3>
- 2710039615U, // <3,4,2,6>: Cost 3 vext3 <4,2,6,3>, <4,2,6,3>
+ 2624800514U, // <3,4,2,4>: Cost 3 vext2 <1,2,3,4>, <2,4,1,3>
+ 2709965878U, // <3,4,2,5>: Cost 3 vext3 <4,2,5,3>, <4,2,5,3>
+ 2689838140U, // <3,4,2,6>: Cost 3 vext3 LHS, <4,2,6,0>
2634090504U, // <3,4,2,7>: Cost 3 vext2 <2,7,3,4>, <2,7,3,4>
- 2685635665U, // <3,4,2,u>: Cost 3 vext3 LHS, <4,2,u,3>
+ 2689838158U, // <3,4,2,u>: Cost 3 vext3 LHS, <4,2,u,0>
2624800918U, // <3,4,3,0>: Cost 3 vext2 <1,2,3,4>, <3,0,1,2>
- 3698542814U, // <3,4,3,1>: Cost 4 vext2 <1,2,3,4>, <3,1,0,2>
- 2624801108U, // <3,4,3,2>: Cost 3 vext2 <1,2,3,4>, <3,2,4,3>
+ 2636081403U, // <3,4,3,1>: Cost 3 vext2 <3,1,3,4>, <3,1,3,4>
+ 2636745036U, // <3,4,3,2>: Cost 3 vext2 <3,2,3,4>, <3,2,3,4>
2624801180U, // <3,4,3,3>: Cost 3 vext2 <1,2,3,4>, <3,3,3,3>
2624801232U, // <3,4,3,4>: Cost 3 vext2 <1,2,3,4>, <3,4,0,1>
- 2710629511U, // <3,4,3,5>: Cost 3 vext3 <4,3,5,3>, <4,3,5,3>
- 2710703248U, // <3,4,3,6>: Cost 3 vext3 <4,3,6,3>, <4,3,6,3>
- 3667997961U, // <3,4,3,7>: Cost 4 vext1 <7,3,4,3>, <7,3,4,3>
+ 2905836854U, // <3,4,3,5>: Cost 3 vzipl <3,3,3,3>, RHS
+ 3040054582U, // <3,4,3,6>: Cost 3 vtrnl <3,3,3,3>, RHS
+ 3702524611U, // <3,4,3,7>: Cost 4 vext2 <1,u,3,4>, <3,7,0,1>
2624801566U, // <3,4,3,u>: Cost 3 vext2 <1,2,3,4>, <3,u,1,2>
- 2624801682U, // <3,4,4,0>: Cost 3 vext2 <1,2,3,4>, <4,0,5,1>
+ 2564399206U, // <3,4,4,0>: Cost 3 vext1 <2,3,4,4>, LHS
2564400026U, // <3,4,4,1>: Cost 3 vext1 <2,3,4,4>, <1,2,3,4>
2564400845U, // <3,4,4,2>: Cost 3 vext1 <2,3,4,4>, <2,3,4,4>
2570373542U, // <3,4,4,3>: Cost 3 vext1 <3,3,4,4>, <3,3,4,4>
@@ -2578,33 +2578,33 @@ static const unsigned PerfectShuffleTable[6561+1] = {
3668006154U, // <3,4,4,7>: Cost 4 vext1 <7,3,4,4>, <7,3,4,4>
1551060521U, // <3,4,4,u>: Cost 2 vext2 <1,2,3,4>, RHS
1490665574U, // <3,4,5,0>: Cost 2 vext1 <2,3,4,5>, LHS
- 2624802512U, // <3,4,5,1>: Cost 3 vext2 <1,2,3,4>, <5,1,7,3>
+ 2689838341U, // <3,4,5,1>: Cost 3 vext3 LHS, <4,5,1,3>
1490667214U, // <3,4,5,2>: Cost 2 vext1 <2,3,4,5>, <2,3,4,5>
2564409494U, // <3,4,5,3>: Cost 3 vext1 <2,3,4,5>, <3,0,1,2>
1490668854U, // <3,4,5,4>: Cost 2 vext1 <2,3,4,5>, RHS
- 2564411088U, // <3,4,5,5>: Cost 3 vext1 <2,3,4,5>, <5,1,7,3>
+ 2689838381U, // <3,4,5,5>: Cost 3 vext3 LHS, <4,5,5,7>
537709878U, // <3,4,5,6>: Cost 1 vext3 LHS, RHS
2594272523U, // <3,4,5,7>: Cost 3 vext1 <7,3,4,5>, <7,3,4,5>
537709896U, // <3,4,5,u>: Cost 1 vext3 LHS, RHS
- 1611894092U, // <3,4,6,0>: Cost 2 vext3 LHS, <4,6,0,2>
- 2712325462U, // <3,4,6,1>: Cost 3 vext3 <4,6,1,3>, <4,6,1,3>
- 2624803322U, // <3,4,6,2>: Cost 3 vext2 <1,2,3,4>, <6,2,7,3>
- 2712472936U, // <3,4,6,3>: Cost 3 vext3 <4,6,3,3>, <4,6,3,3>
+ 2689838411U, // <3,4,6,0>: Cost 3 vext3 LHS, <4,6,0,1>
+ 2558444534U, // <3,4,6,1>: Cost 3 vext1 <1,3,4,6>, <1,3,4,6>
+ 2666607098U, // <3,4,6,2>: Cost 3 vext2 <u,2,3,4>, <6,2,7,3>
+ 2558446082U, // <3,4,6,3>: Cost 3 vext1 <1,3,4,6>, <3,4,5,6>
1659227508U, // <3,4,6,4>: Cost 2 vext3 LHS, <4,6,4,6>
- 2732969337U, // <3,4,6,5>: Cost 3 vext3 LHS, <4,6,5,2>
- 2732969344U, // <3,4,6,6>: Cost 3 vext3 LHS, <4,6,6,0>
+ 2689838462U, // <3,4,6,5>: Cost 3 vext3 LHS, <4,6,5,7>
+ 2689838471U, // <3,4,6,6>: Cost 3 vext3 LHS, <4,6,6,7>
2657981292U, // <3,4,6,7>: Cost 3 vext2 <6,7,3,4>, <6,7,3,4>
- 1659669908U, // <3,4,6,u>: Cost 2 vext3 LHS, <4,6,u,2>
+ 1659227540U, // <3,4,6,u>: Cost 2 vext3 LHS, <4,6,u,2>
2666607610U, // <3,4,7,0>: Cost 3 vext2 <u,2,3,4>, <7,0,1,2>
- 3733714015U, // <3,4,7,1>: Cost 4 vext2 <7,1,3,4>, <7,1,3,4>
+ 3702527072U, // <3,4,7,1>: Cost 4 vext2 <1,u,3,4>, <7,1,3,5>
2660635824U, // <3,4,7,2>: Cost 3 vext2 <7,2,3,4>, <7,2,3,4>
- 3725088011U, // <3,4,7,3>: Cost 4 vext2 <5,6,3,4>, <7,3,4,5>
+ 3644139945U, // <3,4,7,3>: Cost 4 vext1 <3,3,4,7>, <3,3,4,7>
2666607974U, // <3,4,7,4>: Cost 3 vext2 <u,2,3,4>, <7,4,5,6>
- 4054239946U, // <3,4,7,5>: Cost 4 vzipr RHS, <3,7,0,u>
+ 2732969416U, // <3,4,7,5>: Cost 3 vext3 LHS, <4,7,5,0>
2732969425U, // <3,4,7,6>: Cost 3 vext3 LHS, <4,7,6,0>
2666608236U, // <3,4,7,7>: Cost 3 vext2 <u,2,3,4>, <7,7,7,7>
2664617622U, // <3,4,7,u>: Cost 3 vext2 <7,u,3,4>, <7,u,3,4>
- 1611894254U, // <3,4,u,0>: Cost 2 vext3 LHS, <4,u,0,2>
+ 1490690150U, // <3,4,u,0>: Cost 2 vext1 <2,3,4,u>, LHS
1551062830U, // <3,4,u,1>: Cost 2 vext2 <1,2,3,4>, LHS
1490691793U, // <3,4,u,2>: Cost 2 vext1 <2,3,4,u>, <2,3,4,u>
2624804796U, // <3,4,u,3>: Cost 3 vext2 <1,2,3,4>, <u,3,0,1>
@@ -2613,53 +2613,53 @@ static const unsigned PerfectShuffleTable[6561+1] = {
537710121U, // <3,4,u,6>: Cost 1 vext3 LHS, RHS
2594297102U, // <3,4,u,7>: Cost 3 vext1 <7,3,4,u>, <7,3,4,u>
537710139U, // <3,4,u,u>: Cost 1 vext3 LHS, RHS
- 3759377982U, // <3,5,0,0>: Cost 4 vext3 LHS, <5,0,0,1>
- 2685636167U, // <3,5,0,1>: Cost 3 vext3 LHS, <5,0,1,1>
- 2819410434U, // <3,5,0,2>: Cost 3 vuzpr LHS, <3,4,5,6>
- 3644156331U, // <3,5,0,3>: Cost 4 vext1 <3,3,5,0>, <3,3,5,0>
+ 3692576768U, // <3,5,0,0>: Cost 4 vext2 <0,2,3,5>, <0,0,0,0>
+ 2618835046U, // <3,5,0,1>: Cost 3 vext2 <0,2,3,5>, LHS
+ 2618835138U, // <3,5,0,2>: Cost 3 vext2 <0,2,3,5>, <0,2,3,5>
+ 3692577024U, // <3,5,0,3>: Cost 4 vext2 <0,2,3,5>, <0,3,1,4>
2689838690U, // <3,5,0,4>: Cost 3 vext3 LHS, <5,0,4,1>
- 2685636203U, // <3,5,0,5>: Cost 3 vext3 LHS, <5,0,5,1>
- 2685636212U, // <3,5,0,6>: Cost 3 vext3 LHS, <5,0,6,1>
- 2685636222U, // <3,5,0,7>: Cost 3 vext3 LHS, <5,0,7,2>
- 2685636231U, // <3,5,0,u>: Cost 3 vext3 LHS, <5,0,u,2>
- 2564448358U, // <3,5,1,0>: Cost 3 vext1 <2,3,5,1>, LHS
- 3899034114U, // <3,5,1,1>: Cost 4 vuzpr <1,1,1,1>, <3,4,5,6>
- 2564450003U, // <3,5,1,2>: Cost 3 vext1 <2,3,5,1>, <2,3,5,1>
- 3898526210U, // <3,5,1,3>: Cost 4 vuzpr <1,0,3,2>, <3,4,5,6>
- 2564451638U, // <3,5,1,4>: Cost 3 vext1 <2,3,5,1>, RHS
- 2564452048U, // <3,5,1,5>: Cost 3 vext1 <2,3,5,1>, <5,1,7,3>
- 3638194682U, // <3,5,1,6>: Cost 4 vext1 <2,3,5,1>, <6,2,7,3>
- 1611894480U, // <3,5,1,7>: Cost 2 vext3 LHS, <5,1,7,3>
- 1611894489U, // <3,5,1,u>: Cost 2 vext3 LHS, <5,1,u,3>
- 3906259458U, // <3,5,2,0>: Cost 4 vuzpr <2,3,0,1>, <3,4,5,6>
- 2685636336U, // <3,5,2,1>: Cost 3 vext3 LHS, <5,2,1,u>
- 3759378169U, // <3,5,2,2>: Cost 4 vext3 LHS, <5,2,2,u>
- 2632107726U, // <3,5,2,3>: Cost 3 vext2 <2,4,3,5>, <2,3,4,5>
+ 2732969579U, // <3,5,0,5>: Cost 3 vext3 LHS, <5,0,5,1>
+ 2732969588U, // <3,5,0,6>: Cost 3 vext3 LHS, <5,0,6,1>
+ 2246963055U, // <3,5,0,7>: Cost 3 vrev <5,3,7,0>
+ 2618835613U, // <3,5,0,u>: Cost 3 vext2 <0,2,3,5>, LHS
+ 2594308198U, // <3,5,1,0>: Cost 3 vext1 <7,3,5,1>, LHS
+ 3692577588U, // <3,5,1,1>: Cost 4 vext2 <0,2,3,5>, <1,1,1,1>
+ 2624807835U, // <3,5,1,2>: Cost 3 vext2 <1,2,3,5>, <1,2,3,5>
+ 2625471468U, // <3,5,1,3>: Cost 3 vext2 <1,3,3,5>, <1,3,3,5>
+ 2626135101U, // <3,5,1,4>: Cost 3 vext2 <1,4,3,5>, <1,4,3,5>
+ 2594311888U, // <3,5,1,5>: Cost 3 vext1 <7,3,5,1>, <5,1,7,3>
+ 3699877107U, // <3,5,1,6>: Cost 4 vext2 <1,4,3,5>, <1,6,5,7>
+ 1641680592U, // <3,5,1,7>: Cost 2 vext3 <5,1,7,3>, <5,1,7,3>
+ 1641754329U, // <3,5,1,u>: Cost 2 vext3 <5,1,u,3>, <5,1,u,3>
+ 3692578274U, // <3,5,2,0>: Cost 4 vext2 <0,2,3,5>, <2,0,5,3>
+ 2630116899U, // <3,5,2,1>: Cost 3 vext2 <2,1,3,5>, <2,1,3,5>
+ 3692578408U, // <3,5,2,2>: Cost 4 vext2 <0,2,3,5>, <2,2,2,2>
+ 2625472206U, // <3,5,2,3>: Cost 3 vext2 <1,3,3,5>, <2,3,4,5>
2632107798U, // <3,5,2,4>: Cost 3 vext2 <2,4,3,5>, <2,4,3,5>
- 2733412111U, // <3,5,2,5>: Cost 3 vext3 LHS, <5,2,5,3>
- 2685636376U, // <3,5,2,6>: Cost 3 vext3 LHS, <5,2,6,3>
- 2689838880U, // <3,5,2,7>: Cost 3 vext3 LHS, <5,2,7,2>
- 2685636394U, // <3,5,2,u>: Cost 3 vext3 LHS, <5,2,u,3>
- 2576408678U, // <3,5,3,0>: Cost 3 vext1 <4,3,5,3>, LHS
- 3705850124U, // <3,5,3,1>: Cost 4 vext2 <2,4,3,5>, <3,1,5,3>
- 3702532445U, // <3,5,3,2>: Cost 4 vext2 <1,u,3,5>, <3,2,5,3>
- 2576411036U, // <3,5,3,3>: Cost 3 vext1 <4,3,5,3>, <3,3,3,3>
- 2638744066U, // <3,5,3,4>: Cost 3 vext2 <3,5,3,5>, <3,4,5,6>
- 2839562754U, // <3,5,3,5>: Cost 3 vuzpr <3,4,5,6>, <3,4,5,6>
- 3980411720U, // <3,5,3,6>: Cost 4 vzipl <3,4,5,6>, <1,1,3,3>
- 3047606684U, // <3,5,3,7>: Cost 3 vtrnl RHS, <3,3,3,3>
- 2576414510U, // <3,5,3,u>: Cost 3 vext1 <4,3,5,3>, LHS
+ 2715938575U, // <3,5,2,5>: Cost 3 vext3 <5,2,5,3>, <5,2,5,3>
+ 3692578746U, // <3,5,2,6>: Cost 4 vext2 <0,2,3,5>, <2,6,3,7>
+ 2716086049U, // <3,5,2,7>: Cost 3 vext3 <5,2,7,3>, <5,2,7,3>
+ 2634762330U, // <3,5,2,u>: Cost 3 vext2 <2,u,3,5>, <2,u,3,5>
+ 3692578966U, // <3,5,3,0>: Cost 4 vext2 <0,2,3,5>, <3,0,1,2>
+ 2636089596U, // <3,5,3,1>: Cost 3 vext2 <3,1,3,5>, <3,1,3,5>
+ 3699214668U, // <3,5,3,2>: Cost 4 vext2 <1,3,3,5>, <3,2,3,4>
+ 2638080412U, // <3,5,3,3>: Cost 3 vext2 <3,4,3,5>, <3,3,3,3>
+ 2618837506U, // <3,5,3,4>: Cost 3 vext2 <0,2,3,5>, <3,4,5,6>
+ 2832844494U, // <3,5,3,5>: Cost 3 vuzpr <2,3,4,5>, <2,3,4,5>
+ 4033415682U, // <3,5,3,6>: Cost 4 vzipr <1,1,3,3>, <3,4,5,6>
+ 3095072054U, // <3,5,3,7>: Cost 3 vtrnr <1,3,1,3>, RHS
+ 3095072055U, // <3,5,3,u>: Cost 3 vtrnr <1,3,1,3>, RHS
2600304742U, // <3,5,4,0>: Cost 3 vext1 <u,3,5,4>, LHS
- 2715422607U, // <3,5,4,1>: Cost 3 vext3 <5,1,7,3>, <5,4,1,5>
+ 3763580815U, // <3,5,4,1>: Cost 4 vext3 LHS, <5,4,1,5>
2564474582U, // <3,5,4,2>: Cost 3 vext1 <2,3,5,4>, <2,3,5,4>
- 3705851012U, // <3,5,4,3>: Cost 4 vext2 <2,4,3,5>, <4,3,5,0>
+ 3699879044U, // <3,5,4,3>: Cost 4 vext2 <1,4,3,5>, <4,3,5,0>
2600308022U, // <3,5,4,4>: Cost 3 vext1 <u,3,5,4>, RHS
- 2628791606U, // <3,5,4,5>: Cost 3 vext2 <1,u,3,5>, RHS
- 2846280194U, // <3,5,4,6>: Cost 3 vuzpr RHS, <3,4,5,6>
+ 2618838326U, // <3,5,4,5>: Cost 3 vext2 <0,2,3,5>, RHS
+ 2772454710U, // <3,5,4,6>: Cost 3 vuzpl <3,4,5,6>, RHS
1659228102U, // <3,5,4,7>: Cost 2 vext3 LHS, <5,4,7,6>
1659228111U, // <3,5,4,u>: Cost 2 vext3 LHS, <5,4,u,6>
2570453094U, // <3,5,5,0>: Cost 3 vext1 <3,3,5,5>, LHS
- 2628792016U, // <3,5,5,1>: Cost 3 vext2 <1,u,3,5>, <5,1,7,3>
+ 2624810704U, // <3,5,5,1>: Cost 3 vext2 <1,2,3,5>, <5,1,7,3>
2570454734U, // <3,5,5,2>: Cost 3 vext1 <3,3,5,5>, <2,3,4,5>
2570455472U, // <3,5,5,3>: Cost 3 vext1 <3,3,5,5>, <3,3,5,5>
2570456374U, // <3,5,5,4>: Cost 3 vext1 <3,3,5,5>, RHS
@@ -2676,625 +2676,625 @@ static const unsigned PerfectShuffleTable[6561+1] = {
2732970080U, // <3,5,6,6>: Cost 3 vext3 LHS, <5,6,6,7>
1659228258U, // <3,5,6,7>: Cost 2 vext3 LHS, <5,6,7,0>
1659228267U, // <3,5,6,u>: Cost 2 vext3 LHS, <5,6,u,0>
- 2685636726U, // <3,5,7,0>: Cost 3 vext3 LHS, <5,7,0,2>
- 3789164670U, // <3,5,7,1>: Cost 4 vext3 <5,1,7,3>, <5,7,1,1>
- 3702535348U, // <3,5,7,2>: Cost 4 vext2 <1,u,3,5>, <7,2,3,u>
- 3719124235U, // <3,5,7,3>: Cost 4 vext2 <4,6,3,5>, <7,3,4,5>
- 2715422878U, // <3,5,7,4>: Cost 3 vext3 <5,1,7,3>, <5,7,4,6>
- 2732970152U, // <3,5,7,5>: Cost 3 vext3 LHS, <5,7,5,7>
- 3793072301U, // <3,5,7,6>: Cost 4 vext3 <5,7,6,3>, <5,7,6,3>
- 2732970163U, // <3,5,7,7>: Cost 3 vext3 LHS, <5,7,7,0>
- 2732970172U, // <3,5,7,u>: Cost 3 vext3 LHS, <5,7,u,0>
- 2685636807U, // <3,5,u,0>: Cost 3 vext3 LHS, <5,u,0,2>
- 2689839313U, // <3,5,u,1>: Cost 3 vext3 LHS, <5,u,1,3>
- 2867186178U, // <3,5,u,2>: Cost 3 vuzpr LHS, <3,4,5,6>
- 2732970212U, // <3,5,u,3>: Cost 3 vext3 LHS, <5,u,3,4>
- 2594368822U, // <3,5,u,4>: Cost 3 vext1 <7,3,5,u>, RHS
- 1659228164U, // <3,5,u,5>: Cost 2 vext3 LHS, <5,5,5,5>
- 2689839358U, // <3,5,u,6>: Cost 3 vext3 LHS, <5,u,6,3>
- 1616539911U, // <3,5,u,7>: Cost 2 vext3 LHS, <5,u,7,3>
- 1616539920U, // <3,5,u,u>: Cost 2 vext3 LHS, <5,u,u,3>
- 3759378711U, // <3,6,0,0>: Cost 4 vext3 LHS, <6,0,0,1>
- 2628796518U, // <3,6,0,1>: Cost 3 vext2 <1,u,3,6>, LHS
- 2685636905U, // <3,6,0,2>: Cost 3 vext3 LHS, <6,0,2,1>
- 3650202069U, // <3,6,0,3>: Cost 4 vext1 <4,3,6,0>, <3,4,0,6>
+ 1484783718U, // <3,5,7,0>: Cost 2 vext1 <1,3,5,7>, LHS
+ 1484784640U, // <3,5,7,1>: Cost 2 vext1 <1,3,5,7>, <1,3,5,7>
+ 2558527080U, // <3,5,7,2>: Cost 3 vext1 <1,3,5,7>, <2,2,2,2>
+ 2558527638U, // <3,5,7,3>: Cost 3 vext1 <1,3,5,7>, <3,0,1,2>
+ 1484786998U, // <3,5,7,4>: Cost 2 vext1 <1,3,5,7>, RHS
+ 1659228328U, // <3,5,7,5>: Cost 2 vext3 LHS, <5,7,5,7>
+ 2732970154U, // <3,5,7,6>: Cost 3 vext3 LHS, <5,7,6,0>
+ 2558531180U, // <3,5,7,7>: Cost 3 vext1 <1,3,5,7>, <7,7,7,7>
+ 1484789550U, // <3,5,7,u>: Cost 2 vext1 <1,3,5,7>, LHS
+ 1484791910U, // <3,5,u,0>: Cost 2 vext1 <1,3,5,u>, LHS
+ 1484792833U, // <3,5,u,1>: Cost 2 vext1 <1,3,5,u>, <1,3,5,u>
+ 2558535272U, // <3,5,u,2>: Cost 3 vext1 <1,3,5,u>, <2,2,2,2>
+ 2558535830U, // <3,5,u,3>: Cost 3 vext1 <1,3,5,u>, <3,0,1,2>
+ 1484795190U, // <3,5,u,4>: Cost 2 vext1 <1,3,5,u>, RHS
+ 1659228409U, // <3,5,u,5>: Cost 2 vext3 LHS, <5,u,5,7>
+ 2772457626U, // <3,5,u,6>: Cost 3 vuzpl <3,4,5,6>, RHS
+ 1646326023U, // <3,5,u,7>: Cost 2 vext3 <5,u,7,3>, <5,u,7,3>
+ 1484797742U, // <3,5,u,u>: Cost 2 vext1 <1,3,5,u>, LHS
+ 2558541926U, // <3,6,0,0>: Cost 3 vext1 <1,3,6,0>, LHS
+ 2689839393U, // <3,6,0,1>: Cost 3 vext3 LHS, <6,0,1,2>
+ 2689839404U, // <3,6,0,2>: Cost 3 vext3 LHS, <6,0,2,4>
+ 3706519808U, // <3,6,0,3>: Cost 4 vext2 <2,5,3,6>, <0,3,1,4>
2689839420U, // <3,6,0,4>: Cost 3 vext3 LHS, <6,0,4,2>
- 3656175462U, // <3,6,0,5>: Cost 4 vext1 <5,3,6,0>, <5,3,6,0>
+ 2732970314U, // <3,6,0,5>: Cost 3 vext3 LHS, <6,0,5,7>
2732970316U, // <3,6,0,6>: Cost 3 vext3 LHS, <6,0,6,0>
- 2685636951U, // <3,6,0,7>: Cost 3 vext3 LHS, <6,0,7,2>
- 2685636960U, // <3,6,0,u>: Cost 3 vext3 LHS, <6,0,u,2>
- 2576466022U, // <3,6,1,0>: Cost 3 vext1 <4,3,6,1>, LHS
- 3699221320U, // <3,6,1,1>: Cost 4 vext2 <1,3,3,6>, <1,1,3,3>
- 2685636988U, // <3,6,1,2>: Cost 3 vext3 LHS, <6,1,2,3>
- 2576468118U, // <3,6,1,3>: Cost 3 vext1 <4,3,6,1>, <3,0,1,2>
- 2576469134U, // <3,6,1,4>: Cost 3 vext1 <4,3,6,1>, <4,3,6,1>
- 3650211536U, // <3,6,1,5>: Cost 4 vext1 <4,3,6,1>, <5,1,7,3>
- 2733412768U, // <3,6,1,6>: Cost 3 vext3 LHS, <6,1,6,3>
- 2732970407U, // <3,6,1,7>: Cost 3 vext3 LHS, <6,1,7,1>
- 2689839538U, // <3,6,1,u>: Cost 3 vext3 LHS, <6,1,u,3>
- 2564530278U, // <3,6,2,0>: Cost 3 vext1 <2,3,6,2>, LHS
- 3759378889U, // <3,6,2,1>: Cost 4 vext3 LHS, <6,2,1,u>
- 2685637074U, // <3,6,2,2>: Cost 3 vext3 LHS, <6,2,2,u>
- 3759378902U, // <3,6,2,3>: Cost 4 vext3 LHS, <6,2,3,3>
- 2564533558U, // <3,6,2,4>: Cost 3 vext1 <2,3,6,2>, RHS
+ 2960313654U, // <3,6,0,7>: Cost 3 vzipr <1,2,3,0>, RHS
+ 2689839456U, // <3,6,0,u>: Cost 3 vext3 LHS, <6,0,u,2>
+ 3763581290U, // <3,6,1,0>: Cost 4 vext3 LHS, <6,1,0,3>
+ 3763581297U, // <3,6,1,1>: Cost 4 vext3 LHS, <6,1,1,1>
+ 2624816028U, // <3,6,1,2>: Cost 3 vext2 <1,2,3,6>, <1,2,3,6>
+ 3763581315U, // <3,6,1,3>: Cost 4 vext3 LHS, <6,1,3,1>
+ 2626143294U, // <3,6,1,4>: Cost 3 vext2 <1,4,3,6>, <1,4,3,6>
+ 3763581335U, // <3,6,1,5>: Cost 4 vext3 LHS, <6,1,5,3>
+ 2721321376U, // <3,6,1,6>: Cost 3 vext3 <6,1,6,3>, <6,1,6,3>
+ 2721395113U, // <3,6,1,7>: Cost 3 vext3 <6,1,7,3>, <6,1,7,3>
+ 2628797826U, // <3,6,1,u>: Cost 3 vext2 <1,u,3,6>, <1,u,3,6>
+ 2594390118U, // <3,6,2,0>: Cost 3 vext1 <7,3,6,2>, LHS
+ 2721616324U, // <3,6,2,1>: Cost 3 vext3 <6,2,1,3>, <6,2,1,3>
+ 2630788725U, // <3,6,2,2>: Cost 3 vext2 <2,2,3,6>, <2,2,3,6>
+ 3763581395U, // <3,6,2,3>: Cost 4 vext3 LHS, <6,2,3,0>
+ 2632115991U, // <3,6,2,4>: Cost 3 vext2 <2,4,3,6>, <2,4,3,6>
2632779624U, // <3,6,2,5>: Cost 3 vext2 <2,5,3,6>, <2,5,3,6>
- 2564534778U, // <3,6,2,6>: Cost 3 vext1 <2,3,6,2>, <6,2,7,3>
- 1611895290U, // <3,6,2,7>: Cost 2 vext3 LHS, <6,2,7,3>
- 1611895299U, // <3,6,2,u>: Cost 2 vext3 LHS, <6,2,u,3>
- 2576482406U, // <3,6,3,0>: Cost 3 vext1 <4,3,6,3>, LHS
- 3650224886U, // <3,6,3,1>: Cost 4 vext1 <4,3,6,3>, <1,0,3,2>
- 3702540646U, // <3,6,3,2>: Cost 4 vext2 <1,u,3,6>, <3,2,6,3>
- 2576484764U, // <3,6,3,3>: Cost 3 vext1 <4,3,6,3>, <3,3,3,3>
- 2576485520U, // <3,6,3,4>: Cost 3 vext1 <4,3,6,3>, <4,3,6,3>
+ 2594394618U, // <3,6,2,6>: Cost 3 vext1 <7,3,6,2>, <6,2,7,3>
+ 1648316922U, // <3,6,2,7>: Cost 2 vext3 <6,2,7,3>, <6,2,7,3>
+ 1648390659U, // <3,6,2,u>: Cost 2 vext3 <6,2,u,3>, <6,2,u,3>
+ 3693914262U, // <3,6,3,0>: Cost 4 vext2 <0,4,3,6>, <3,0,1,2>
+ 3638281176U, // <3,6,3,1>: Cost 4 vext1 <2,3,6,3>, <1,3,1,3>
+ 3696568678U, // <3,6,3,2>: Cost 4 vext2 <0,u,3,6>, <3,2,6,3>
+ 2638088604U, // <3,6,3,3>: Cost 3 vext2 <3,4,3,6>, <3,3,3,3>
+ 2632780290U, // <3,6,3,4>: Cost 3 vext2 <2,5,3,6>, <3,4,5,6>
3712494145U, // <3,6,3,5>: Cost 4 vext2 <3,5,3,6>, <3,5,3,6>
- 3702540914U, // <3,6,3,6>: Cost 4 vext2 <1,u,3,6>, <3,6,0,1>
- 2913387336U, // <3,6,3,7>: Cost 3 vzipl RHS, <1,1,3,3>
- 2576488238U, // <3,6,3,u>: Cost 3 vext1 <4,3,6,3>, LHS
- 2685637212U, // <3,6,4,0>: Cost 3 vext3 LHS, <6,4,0,2>
- 3783119465U, // <3,6,4,1>: Cost 4 vext3 <4,1,6,3>, <6,4,1,6>
- 2722058865U, // <3,6,4,2>: Cost 3 vext3 <6,2,7,3>, <6,4,2,5>
- 3650234882U, // <3,6,4,3>: Cost 4 vext1 <4,3,6,4>, <3,4,5,6>
+ 3698559612U, // <3,6,3,6>: Cost 4 vext2 <1,2,3,6>, <3,6,1,2>
+ 2959674678U, // <3,6,3,7>: Cost 3 vzipr <1,1,3,3>, RHS
+ 2959674679U, // <3,6,3,u>: Cost 3 vzipr <1,1,3,3>, RHS
+ 3763581536U, // <3,6,4,0>: Cost 4 vext3 LHS, <6,4,0,6>
+ 2722943590U, // <3,6,4,1>: Cost 3 vext3 <6,4,1,3>, <6,4,1,3>
+ 2732970609U, // <3,6,4,2>: Cost 3 vext3 LHS, <6,4,2,5>
+ 3698560147U, // <3,6,4,3>: Cost 4 vext2 <1,2,3,6>, <4,3,6,6>
2732970628U, // <3,6,4,4>: Cost 3 vext3 LHS, <6,4,4,6>
- 2628799798U, // <3,6,4,5>: Cost 3 vext2 <1,u,3,6>, RHS
+ 2689839757U, // <3,6,4,5>: Cost 3 vext3 LHS, <6,4,5,6>
2732970640U, // <3,6,4,6>: Cost 3 vext3 LHS, <6,4,6,0>
- 2913387418U, // <3,6,4,7>: Cost 3 vzipl RHS, <1,2,3,4>
- 2628800041U, // <3,6,4,u>: Cost 3 vext2 <1,u,3,6>, RHS
+ 2960346422U, // <3,6,4,7>: Cost 3 vzipr <1,2,3,4>, RHS
+ 2689839784U, // <3,6,4,u>: Cost 3 vext3 LHS, <6,4,u,6>
2576498790U, // <3,6,5,0>: Cost 3 vext1 <4,3,6,5>, LHS
- 3702542032U, // <3,6,5,1>: Cost 4 vext2 <1,u,3,6>, <5,1,7,3>
+ 3650241270U, // <3,6,5,1>: Cost 4 vext1 <4,3,6,5>, <1,0,3,2>
2732970692U, // <3,6,5,2>: Cost 3 vext3 LHS, <6,5,2,7>
2576501250U, // <3,6,5,3>: Cost 3 vext1 <4,3,6,5>, <3,4,5,6>
2576501906U, // <3,6,5,4>: Cost 3 vext1 <4,3,6,5>, <4,3,6,5>
- 3650244304U, // <3,6,5,5>: Cost 4 vext1 <4,3,6,5>, <5,1,7,3>
- 2732970728U, // <3,6,5,6>: Cost 3 vext3 LHS, <6,5,6,7>
- 2732970731U, // <3,6,5,7>: Cost 3 vext3 LHS, <6,5,7,1>
+ 3650244622U, // <3,6,5,5>: Cost 4 vext1 <4,3,6,5>, <5,5,6,6>
+ 4114633528U, // <3,6,5,6>: Cost 4 vtrnl <3,4,5,6>, <6,6,6,6>
+ 2732970735U, // <3,6,5,7>: Cost 3 vext3 LHS, <6,5,7,5>
2576504622U, // <3,6,5,u>: Cost 3 vext1 <4,3,6,5>, LHS
2732970749U, // <3,6,6,0>: Cost 3 vext3 LHS, <6,6,0,1>
- 3806712581U, // <3,6,6,1>: Cost 4 vext3 LHS, <6,6,1,0>
- 2628801018U, // <3,6,6,2>: Cost 3 vext2 <1,u,3,6>, <6,2,7,3>
- 3650251269U, // <3,6,6,3>: Cost 4 vext1 <4,3,6,6>, <3,4,6,0>
+ 2724270856U, // <3,6,6,1>: Cost 3 vext3 <6,6,1,3>, <6,6,1,3>
+ 2624819706U, // <3,6,6,2>: Cost 3 vext2 <1,2,3,6>, <6,2,7,3>
+ 3656223234U, // <3,6,6,3>: Cost 4 vext1 <5,3,6,6>, <3,4,5,6>
2732970788U, // <3,6,6,4>: Cost 3 vext3 LHS, <6,6,4,4>
- 3668168400U, // <3,6,6,5>: Cost 4 vext1 <7,3,6,6>, <5,1,7,3>
+ 2732970800U, // <3,6,6,5>: Cost 3 vext3 LHS, <6,6,5,7>
1659228984U, // <3,6,6,6>: Cost 2 vext3 LHS, <6,6,6,6>
1659228994U, // <3,6,6,7>: Cost 2 vext3 LHS, <6,6,7,7>
1659229003U, // <3,6,6,u>: Cost 2 vext3 LHS, <6,6,u,7>
1659229006U, // <3,6,7,0>: Cost 2 vext3 LHS, <6,7,0,1>
- 2732970838U, // <3,6,7,1>: Cost 3 vext3 LHS, <6,7,1,0>
- 2725008226U, // <3,6,7,2>: Cost 3 vext3 <6,7,2,3>, <6,7,2,3>
+ 2558600201U, // <3,6,7,1>: Cost 3 vext1 <1,3,6,7>, <1,3,6,7>
+ 2558601146U, // <3,6,7,2>: Cost 3 vext1 <1,3,6,7>, <2,6,3,7>
2725081963U, // <3,6,7,3>: Cost 3 vext3 <6,7,3,3>, <6,7,3,3>
1659229046U, // <3,6,7,4>: Cost 2 vext3 LHS, <6,7,4,5>
2715423611U, // <3,6,7,5>: Cost 3 vext3 <5,1,7,3>, <6,7,5,1>
2722059141U, // <3,6,7,6>: Cost 3 vext3 <6,2,7,3>, <6,7,6,2>
- 2913388474U, // <3,6,7,7>: Cost 3 vzipl RHS, <2,6,3,7>
+ 2962361654U, // <3,6,7,7>: Cost 3 vzipr <1,5,3,7>, RHS
1659229078U, // <3,6,7,u>: Cost 2 vext3 LHS, <6,7,u,1>
1659229087U, // <3,6,u,0>: Cost 2 vext3 LHS, <6,u,0,1>
- 2628802350U, // <3,6,u,1>: Cost 3 vext2 <1,u,3,6>, LHS
- 2689840051U, // <3,6,u,2>: Cost 3 vext3 LHS, <6,u,2,3>
+ 2689840041U, // <3,6,u,1>: Cost 3 vext3 LHS, <6,u,1,2>
+ 2558609339U, // <3,6,u,2>: Cost 3 vext1 <1,3,6,u>, <2,6,3,u>
2576525853U, // <3,6,u,3>: Cost 3 vext1 <4,3,6,u>, <3,4,u,6>
1659229127U, // <3,6,u,4>: Cost 2 vext3 LHS, <6,u,4,5>
- 2628802714U, // <3,6,u,5>: Cost 3 vext2 <1,u,3,6>, RHS
+ 2689840081U, // <3,6,u,5>: Cost 3 vext3 LHS, <6,u,5,6>
1659228984U, // <3,6,u,6>: Cost 2 vext3 LHS, <6,6,6,6>
- 1616098272U, // <3,6,u,7>: Cost 2 vext3 LHS, <6,u,7,3>
- 1616098281U, // <3,6,u,u>: Cost 2 vext3 LHS, <6,u,u,3>
- 2588475494U, // <3,7,0,0>: Cost 3 vext1 <6,3,7,0>, LHS
- 1659229178U, // <3,7,0,1>: Cost 2 vext3 LHS, <7,0,1,2>
- 2732971009U, // <3,7,0,2>: Cost 3 vext3 LHS, <7,0,2,0>
- 3759379468U, // <3,7,0,3>: Cost 4 vext3 LHS, <7,0,3,2>
- 2588478774U, // <3,7,0,4>: Cost 3 vext1 <6,3,7,0>, RHS
- 2732971042U, // <3,7,0,5>: Cost 3 vext3 LHS, <7,0,5,6>
+ 1652298720U, // <3,6,u,7>: Cost 2 vext3 <6,u,7,3>, <6,u,7,3>
+ 1659229159U, // <3,6,u,u>: Cost 2 vext3 LHS, <6,u,u,1>
+ 2626813952U, // <3,7,0,0>: Cost 3 vext2 <1,5,3,7>, <0,0,0,0>
+ 1553072230U, // <3,7,0,1>: Cost 2 vext2 <1,5,3,7>, LHS
+ 2626814116U, // <3,7,0,2>: Cost 3 vext2 <1,5,3,7>, <0,2,0,2>
+ 3700556028U, // <3,7,0,3>: Cost 4 vext2 <1,5,3,7>, <0,3,1,0>
+ 2626814290U, // <3,7,0,4>: Cost 3 vext2 <1,5,3,7>, <0,4,1,5>
+ 2582507375U, // <3,7,0,5>: Cost 3 vext1 <5,3,7,0>, <5,3,7,0>
2588480072U, // <3,7,0,6>: Cost 3 vext1 <6,3,7,0>, <6,3,7,0>
- 2600424442U, // <3,7,0,7>: Cost 3 vext1 <u,3,7,0>, <7,0,1,2>
- 1659229241U, // <3,7,0,u>: Cost 2 vext3 LHS, <7,0,u,2>
- 2582511718U, // <3,7,1,0>: Cost 3 vext1 <5,3,7,1>, LHS
- 2726925388U, // <3,7,1,1>: Cost 3 vext3 <7,1,1,3>, <7,1,1,3>
- 2582513318U, // <3,7,1,2>: Cost 3 vext1 <5,3,7,1>, <2,3,0,1>
- 3789165661U, // <3,7,1,3>: Cost 4 vext3 <5,1,7,3>, <7,1,3,2>
+ 2732971055U, // <3,7,0,7>: Cost 3 vext3 LHS, <7,0,7,1>
+ 1553072797U, // <3,7,0,u>: Cost 2 vext2 <1,5,3,7>, LHS
+ 2626814710U, // <3,7,1,0>: Cost 3 vext2 <1,5,3,7>, <1,0,3,2>
+ 2626814772U, // <3,7,1,1>: Cost 3 vext2 <1,5,3,7>, <1,1,1,1>
+ 2626814870U, // <3,7,1,2>: Cost 3 vext2 <1,5,3,7>, <1,2,3,0>
+ 2625487854U, // <3,7,1,3>: Cost 3 vext2 <1,3,3,7>, <1,3,3,7>
2582514998U, // <3,7,1,4>: Cost 3 vext1 <5,3,7,1>, RHS
1553073296U, // <3,7,1,5>: Cost 2 vext2 <1,5,3,7>, <1,5,3,7>
2627478753U, // <3,7,1,6>: Cost 3 vext2 <1,6,3,7>, <1,6,3,7>
- 2732971136U, // <3,7,1,7>: Cost 3 vext3 LHS, <7,1,7,1>
+ 2727367810U, // <3,7,1,7>: Cost 3 vext3 <7,1,7,3>, <7,1,7,3>
1555064195U, // <3,7,1,u>: Cost 2 vext2 <1,u,3,7>, <1,u,3,7>
2588491878U, // <3,7,2,0>: Cost 3 vext1 <6,3,7,2>, LHS
- 2588492534U, // <3,7,2,1>: Cost 3 vext1 <6,3,7,2>, <1,0,3,2>
- 2727662758U, // <3,7,2,2>: Cost 3 vext3 <7,2,2,3>, <7,2,2,3>
- 2685637807U, // <3,7,2,3>: Cost 3 vext3 LHS, <7,2,3,3>
+ 3700557318U, // <3,7,2,1>: Cost 4 vext2 <1,5,3,7>, <2,1,0,3>
+ 2626815592U, // <3,7,2,2>: Cost 3 vext2 <1,5,3,7>, <2,2,2,2>
+ 2626815654U, // <3,7,2,3>: Cost 3 vext2 <1,5,3,7>, <2,3,0,1>
2588495158U, // <3,7,2,4>: Cost 3 vext1 <6,3,7,2>, RHS
2632787817U, // <3,7,2,5>: Cost 3 vext2 <2,5,3,7>, <2,5,3,7>
1559709626U, // <3,7,2,6>: Cost 2 vext2 <2,6,3,7>, <2,6,3,7>
- 2733413587U, // <3,7,2,7>: Cost 3 vext3 LHS, <7,2,7,3>
+ 2728031443U, // <3,7,2,7>: Cost 3 vext3 <7,2,7,3>, <7,2,7,3>
1561036892U, // <3,7,2,u>: Cost 2 vext2 <2,u,3,7>, <2,u,3,7>
- 2582528102U, // <3,7,3,0>: Cost 3 vext1 <5,3,7,3>, LHS
- 2588500808U, // <3,7,3,1>: Cost 3 vext1 <6,3,7,3>, <1,1,3,3>
+ 2626816150U, // <3,7,3,0>: Cost 3 vext2 <1,5,3,7>, <3,0,1,2>
+ 2626816268U, // <3,7,3,1>: Cost 3 vext2 <1,5,3,7>, <3,1,5,3>
2633451878U, // <3,7,3,2>: Cost 3 vext2 <2,6,3,7>, <3,2,6,3>
- 2582530460U, // <3,7,3,3>: Cost 3 vext1 <5,3,7,3>, <3,3,3,3>
- 2582531382U, // <3,7,3,4>: Cost 3 vext1 <5,3,7,3>, RHS
- 2715424016U, // <3,7,3,5>: Cost 3 vext3 <5,1,7,3>, <7,3,5,1>
- 2722059546U, // <3,7,3,6>: Cost 3 vext3 <6,2,7,3>, <7,3,6,2>
- 2626816720U, // <3,7,3,7>: Cost 3 vext2 <1,5,3,7>, <3,7,1,5>
- 2582533934U, // <3,7,3,u>: Cost 3 vext1 <5,3,7,3>, LHS
- 2588508262U, // <3,7,4,0>: Cost 3 vext1 <6,3,7,4>, LHS
- 2588509082U, // <3,7,4,1>: Cost 3 vext1 <6,3,7,4>, <1,2,3,4>
- 2564622056U, // <3,7,4,2>: Cost 3 vext1 <2,3,7,4>, <2,3,7,4>
- 3990487962U, // <3,7,4,3>: Cost 4 vzipl <5,1,7,3>, <1,2,3,4>
- 2588511542U, // <3,7,4,4>: Cost 3 vext1 <6,3,7,4>, RHS
- 1659229542U, // <3,7,4,5>: Cost 2 vext3 LHS, <7,4,5,6>
+ 2626816412U, // <3,7,3,3>: Cost 3 vext2 <1,5,3,7>, <3,3,3,3>
+ 2626816514U, // <3,7,3,4>: Cost 3 vext2 <1,5,3,7>, <3,4,5,6>
+ 2638760514U, // <3,7,3,5>: Cost 3 vext2 <3,5,3,7>, <3,5,3,7>
+ 2639424147U, // <3,7,3,6>: Cost 3 vext2 <3,6,3,7>, <3,6,3,7>
+ 2826961920U, // <3,7,3,7>: Cost 3 vuzpr <1,3,5,7>, <1,3,5,7>
+ 2626816798U, // <3,7,3,u>: Cost 3 vext2 <1,5,3,7>, <3,u,1,2>
+ 2582536294U, // <3,7,4,0>: Cost 3 vext1 <5,3,7,4>, LHS
+ 2582537360U, // <3,7,4,1>: Cost 3 vext1 <5,3,7,4>, <1,5,3,7>
+ 2588510138U, // <3,7,4,2>: Cost 3 vext1 <6,3,7,4>, <2,6,3,7>
+ 3700558996U, // <3,7,4,3>: Cost 4 vext2 <1,5,3,7>, <4,3,6,7>
+ 2582539574U, // <3,7,4,4>: Cost 3 vext1 <5,3,7,4>, RHS
+ 1553075510U, // <3,7,4,5>: Cost 2 vext2 <1,5,3,7>, RHS
2588512844U, // <3,7,4,6>: Cost 3 vext1 <6,3,7,4>, <6,3,7,4>
- 2732971383U, // <3,7,4,7>: Cost 3 vext3 LHS, <7,4,7,5>
- 1659229569U, // <3,7,4,u>: Cost 2 vext3 LHS, <7,4,u,6>
- 2582544486U, // <3,7,5,0>: Cost 3 vext1 <5,3,7,5>, LHS
- 2715424148U, // <3,7,5,1>: Cost 3 vext3 <5,1,7,3>, <7,5,1,7>
- 2582546126U, // <3,7,5,2>: Cost 3 vext1 <5,3,7,5>, <2,3,4,5>
- 2668621679U, // <3,7,5,3>: Cost 3 vext2 <u,5,3,7>, <5,3,7,0>
- 2582547766U, // <3,7,5,4>: Cost 3 vext1 <5,3,7,5>, RHS
- 2582548340U, // <3,7,5,5>: Cost 3 vext1 <5,3,7,5>, <5,3,7,5>
+ 2564625766U, // <3,7,4,7>: Cost 3 vext1 <2,3,7,4>, <7,4,5,6>
+ 1553075753U, // <3,7,4,u>: Cost 2 vext2 <1,5,3,7>, RHS
+ 2732971398U, // <3,7,5,0>: Cost 3 vext3 LHS, <7,5,0,2>
+ 2626817744U, // <3,7,5,1>: Cost 3 vext2 <1,5,3,7>, <5,1,7,3>
+ 3700559649U, // <3,7,5,2>: Cost 4 vext2 <1,5,3,7>, <5,2,7,3>
+ 2626817903U, // <3,7,5,3>: Cost 3 vext2 <1,5,3,7>, <5,3,7,0>
+ 2258728203U, // <3,7,5,4>: Cost 3 vrev <7,3,4,5>
+ 2732971446U, // <3,7,5,5>: Cost 3 vext3 LHS, <7,5,5,5>
2732971457U, // <3,7,5,6>: Cost 3 vext3 LHS, <7,5,6,7>
- 2732971466U, // <3,7,5,7>: Cost 3 vext3 LHS, <7,5,7,7>
- 2582550318U, // <3,7,5,u>: Cost 3 vext1 <5,3,7,5>, LHS
+ 2826964278U, // <3,7,5,7>: Cost 3 vuzpr <1,3,5,7>, RHS
+ 2826964279U, // <3,7,5,u>: Cost 3 vuzpr <1,3,5,7>, RHS
2732971478U, // <3,7,6,0>: Cost 3 vext3 LHS, <7,6,0,1>
2732971486U, // <3,7,6,1>: Cost 3 vext3 LHS, <7,6,1,0>
- 2722059758U, // <3,7,6,2>: Cost 3 vext3 <6,2,7,3>, <7,6,2,7>
- 2669285960U, // <3,7,6,3>: Cost 3 vext2 <u,6,3,7>, <6,3,7,0>
+ 2633454074U, // <3,7,6,2>: Cost 3 vext2 <2,6,3,7>, <6,2,7,3>
+ 2633454152U, // <3,7,6,3>: Cost 3 vext2 <2,6,3,7>, <6,3,7,0>
2732971518U, // <3,7,6,4>: Cost 3 vext3 LHS, <7,6,4,5>
2732971526U, // <3,7,6,5>: Cost 3 vext3 LHS, <7,6,5,4>
2732971537U, // <3,7,6,6>: Cost 3 vext3 LHS, <7,6,6,6>
2732971540U, // <3,7,6,7>: Cost 3 vext3 LHS, <7,6,7,0>
2726041124U, // <3,7,6,u>: Cost 3 vext3 <6,u,7,3>, <7,6,u,7>
- 2732971559U, // <3,7,7,0>: Cost 3 vext3 LHS, <7,7,0,1>
- 2626819184U, // <3,7,7,1>: Cost 3 vext2 <1,5,3,7>, <7,1,5,3>
+ 2570616934U, // <3,7,7,0>: Cost 3 vext1 <3,3,7,7>, LHS
+ 2570617856U, // <3,7,7,1>: Cost 3 vext1 <3,3,7,7>, <1,3,5,7>
2564646635U, // <3,7,7,2>: Cost 3 vext1 <2,3,7,7>, <2,3,7,7>
- 3990488208U, // <3,7,7,3>: Cost 4 vzipl <5,1,7,3>, <1,5,3,7>
- 2732971599U, // <3,7,7,4>: Cost 3 vext3 LHS, <7,7,4,5>
- 2732971608U, // <3,7,7,5>: Cost 3 vext3 LHS, <7,7,5,5>
- 2732971618U, // <3,7,7,6>: Cost 3 vext3 LHS, <7,7,6,6>
+ 2570619332U, // <3,7,7,3>: Cost 3 vext1 <3,3,7,7>, <3,3,7,7>
+ 2570620214U, // <3,7,7,4>: Cost 3 vext1 <3,3,7,7>, RHS
+ 2582564726U, // <3,7,7,5>: Cost 3 vext1 <5,3,7,7>, <5,3,7,7>
+ 2588537423U, // <3,7,7,6>: Cost 3 vext1 <6,3,7,7>, <6,3,7,7>
1659229804U, // <3,7,7,7>: Cost 2 vext3 LHS, <7,7,7,7>
1659229804U, // <3,7,7,u>: Cost 2 vext3 LHS, <7,7,7,7>
- 2582569062U, // <3,7,u,0>: Cost 3 vext1 <5,3,7,u>, LHS
- 1659229826U, // <3,7,u,1>: Cost 2 vext3 LHS, <7,u,1,2>
- 2582570669U, // <3,7,u,2>: Cost 3 vext1 <5,3,7,u>, <2,3,0,u>
- 2689840789U, // <3,7,u,3>: Cost 3 vext3 LHS, <7,u,3,3>
- 2582572342U, // <3,7,u,4>: Cost 3 vext1 <5,3,7,u>, RHS
- 1659229866U, // <3,7,u,5>: Cost 2 vext3 LHS, <7,u,5,6>
+ 2626819795U, // <3,7,u,0>: Cost 3 vext2 <1,5,3,7>, <u,0,1,2>
+ 1553078062U, // <3,7,u,1>: Cost 2 vext2 <1,5,3,7>, LHS
+ 2626819973U, // <3,7,u,2>: Cost 3 vext2 <1,5,3,7>, <u,2,3,0>
+ 2826961565U, // <3,7,u,3>: Cost 3 vuzpr <1,3,5,7>, LHS
+ 2626820159U, // <3,7,u,4>: Cost 3 vext2 <1,5,3,7>, <u,4,5,6>
+ 1553078426U, // <3,7,u,5>: Cost 2 vext2 <1,5,3,7>, RHS
1595545808U, // <3,7,u,6>: Cost 2 vext2 <u,6,3,7>, <u,6,3,7>
1659229804U, // <3,7,u,7>: Cost 2 vext3 LHS, <7,7,7,7>
- 1659229889U, // <3,7,u,u>: Cost 2 vext3 LHS, <7,u,u,2>
+ 1553078629U, // <3,7,u,u>: Cost 2 vext2 <1,5,3,7>, LHS
1611448320U, // <3,u,0,0>: Cost 2 vext3 LHS, <0,0,0,0>
- 1611896530U, // <3,u,0,1>: Cost 2 vext3 LHS, <u,0,1,1>
- 1611896540U, // <3,u,0,2>: Cost 2 vext3 LHS, <u,0,2,2>
+ 1611896531U, // <3,u,0,1>: Cost 2 vext3 LHS, <u,0,1,2>
+ 1659672284U, // <3,u,0,2>: Cost 2 vext3 LHS, <u,0,2,2>
1616099045U, // <3,u,0,3>: Cost 2 vext3 LHS, <u,0,3,2>
2685638381U, // <3,u,0,4>: Cost 3 vext3 LHS, <u,0,4,1>
- 1611896566U, // <3,u,0,5>: Cost 2 vext3 LHS, <u,0,5,1>
- 1611896576U, // <3,u,0,6>: Cost 2 vext3 LHS, <u,0,6,2>
- 2685638409U, // <3,u,0,7>: Cost 3 vext3 LHS, <u,0,7,2>
- 1611896593U, // <3,u,0,u>: Cost 2 vext3 LHS, <u,0,u,1>
+ 1663874806U, // <3,u,0,5>: Cost 2 vext3 LHS, <u,0,5,1>
+ 1663874816U, // <3,u,0,6>: Cost 2 vext3 LHS, <u,0,6,2>
+ 2960313672U, // <3,u,0,7>: Cost 3 vzipr <1,2,3,0>, RHS
+ 1611896594U, // <3,u,0,u>: Cost 2 vext3 LHS, <u,0,u,2>
1549763324U, // <3,u,1,0>: Cost 2 vext2 <1,0,3,u>, <1,0,3,u>
1550426957U, // <3,u,1,1>: Cost 2 vext2 <1,1,3,u>, <1,1,3,u>
537712430U, // <3,u,1,2>: Cost 1 vext3 LHS, LHS
- 1611896631U, // <3,u,1,3>: Cost 2 vext3 LHS, <u,1,3,3>
+ 1616541495U, // <3,u,1,3>: Cost 2 vext3 LHS, <u,1,3,3>
1490930998U, // <3,u,1,4>: Cost 2 vext1 <2,3,u,1>, RHS
1553081489U, // <3,u,1,5>: Cost 2 vext2 <1,5,3,u>, <1,5,3,u>
- 2685638482U, // <3,u,1,6>: Cost 3 vext3 LHS, <u,1,6,3>
- 1611896667U, // <3,u,1,7>: Cost 2 vext3 LHS, <u,1,7,3>
+ 2627486946U, // <3,u,1,6>: Cost 3 vext2 <1,6,3,u>, <1,6,3,u>
+ 1659230043U, // <3,u,1,7>: Cost 2 vext3 LHS, <u,1,7,3>
537712484U, // <3,u,1,u>: Cost 1 vext3 LHS, LHS
- 1611896684U, // <3,u,2,0>: Cost 2 vext3 LHS, <u,2,0,2>
- 2685638518U, // <3,u,2,1>: Cost 3 vext3 LHS, <u,2,1,3>
+ 1611890852U, // <3,u,2,0>: Cost 2 vext3 LHS, <0,2,0,2>
+ 2624833102U, // <3,u,2,1>: Cost 3 vext2 <1,2,3,u>, <2,1,u,3>
1557063287U, // <3,u,2,2>: Cost 2 vext2 <2,2,3,u>, <2,2,3,u>
- 1611896712U, // <3,u,2,3>: Cost 2 vext3 LHS, <u,2,3,3>
- 1659230100U, // <3,u,2,4>: Cost 2 vext3 LHS, <u,2,4,6>
- 2685638554U, // <3,u,2,5>: Cost 3 vext3 LHS, <u,2,5,3>
+ 1616099205U, // <3,u,2,3>: Cost 2 vext3 LHS, <u,2,3,0>
+ 1611890892U, // <3,u,2,4>: Cost 2 vext3 LHS, <0,2,4,6>
+ 2689841054U, // <3,u,2,5>: Cost 3 vext3 LHS, <u,2,5,7>
1559717819U, // <3,u,2,6>: Cost 2 vext2 <2,6,3,u>, <2,6,3,u>
- 1611896748U, // <3,u,2,7>: Cost 2 vext3 LHS, <u,2,7,3>
- 1611896757U, // <3,u,2,u>: Cost 2 vext3 LHS, <u,2,u,3>
+ 1659230124U, // <3,u,2,7>: Cost 2 vext3 LHS, <u,2,7,3>
+ 1616541618U, // <3,u,2,u>: Cost 2 vext3 LHS, <u,2,u,0>
1611896764U, // <3,u,3,0>: Cost 2 vext3 LHS, <u,3,0,1>
- 2685638596U, // <3,u,3,1>: Cost 3 vext3 LHS, <u,3,1,0>
+ 1484973079U, // <3,u,3,1>: Cost 2 vext1 <1,3,u,3>, <1,3,u,3>
2685638607U, // <3,u,3,2>: Cost 3 vext3 LHS, <u,3,2,2>
336380006U, // <3,u,3,3>: Cost 1 vdup3 LHS
1611896804U, // <3,u,3,4>: Cost 2 vext3 LHS, <u,3,4,5>
- 2685638633U, // <3,u,3,5>: Cost 3 vext3 LHS, <u,3,5,1>
- 2685638643U, // <3,u,3,6>: Cost 3 vext3 LHS, <u,3,6,2>
- 2913534792U, // <3,u,3,7>: Cost 3 vzipl RHS, <1,1,3,3>
+ 1616541679U, // <3,u,3,5>: Cost 2 vext3 LHS, <u,3,5,7>
+ 2690283512U, // <3,u,3,6>: Cost 3 vext3 LHS, <u,3,6,7>
+ 2959674696U, // <3,u,3,7>: Cost 3 vzipr <1,1,3,3>, RHS
336380006U, // <3,u,3,u>: Cost 1 vdup3 LHS
- 2685638673U, // <3,u,4,0>: Cost 3 vext3 LHS, <u,4,0,5>
- 1659230234U, // <3,u,4,1>: Cost 2 vext3 LHS, <u,4,1,5>
- 1659230244U, // <3,u,4,2>: Cost 2 vext3 LHS, <u,4,2,6>
- 2886960026U, // <3,u,4,3>: Cost 3 vzipl LHS, <1,2,3,4>
+ 2558722150U, // <3,u,4,0>: Cost 3 vext1 <1,3,u,4>, LHS
+ 1659672602U, // <3,u,4,1>: Cost 2 vext3 LHS, <u,4,1,5>
+ 1659672612U, // <3,u,4,2>: Cost 2 vext3 LHS, <u,4,2,6>
+ 2689841196U, // <3,u,4,3>: Cost 3 vext3 LHS, <u,4,3,5>
1659227344U, // <3,u,4,4>: Cost 2 vext3 LHS, <4,4,4,4>
1611896895U, // <3,u,4,5>: Cost 2 vext3 LHS, <u,4,5,6>
- 1659230280U, // <3,u,4,6>: Cost 2 vext3 LHS, <u,4,6,6>
+ 1663875144U, // <3,u,4,6>: Cost 2 vext3 LHS, <u,4,6,6>
1659230289U, // <3,u,4,7>: Cost 2 vext3 LHS, <u,4,7,6>
1611896922U, // <3,u,4,u>: Cost 2 vext3 LHS, <u,4,u,6>
1490960486U, // <3,u,5,0>: Cost 2 vext1 <2,3,u,5>, LHS
- 2685638765U, // <3,u,5,1>: Cost 3 vext3 LHS, <u,5,1,7>
+ 2689841261U, // <3,u,5,1>: Cost 3 vext3 LHS, <u,5,1,7>
1490962162U, // <3,u,5,2>: Cost 2 vext1 <2,3,u,5>, <2,3,u,5>
- 1659230335U, // <3,u,5,3>: Cost 2 vext3 LHS, <u,5,3,7>
+ 1616541823U, // <3,u,5,3>: Cost 2 vext3 LHS, <u,5,3,7>
1490963766U, // <3,u,5,4>: Cost 2 vext1 <2,3,u,5>, RHS
1659228164U, // <3,u,5,5>: Cost 2 vext3 LHS, <5,5,5,5>
537712794U, // <3,u,5,6>: Cost 1 vext3 LHS, RHS
1659230371U, // <3,u,5,7>: Cost 2 vext3 LHS, <u,5,7,7>
537712812U, // <3,u,5,u>: Cost 1 vext3 LHS, RHS
- 1611897008U, // <3,u,6,0>: Cost 2 vext3 LHS, <u,6,0,2>
- 2732972215U, // <3,u,6,1>: Cost 3 vext3 LHS, <u,6,1,0>
- 2685638855U, // <3,u,6,2>: Cost 3 vext3 LHS, <u,6,2,7>
- 1659230416U, // <3,u,6,3>: Cost 2 vext3 LHS, <u,6,3,7>
- 1659230424U, // <3,u,6,4>: Cost 2 vext3 LHS, <u,6,4,6>
- 2732972255U, // <3,u,6,5>: Cost 3 vext3 LHS, <u,6,5,4>
+ 2689841327U, // <3,u,6,0>: Cost 3 vext3 LHS, <u,6,0,1>
+ 2558739482U, // <3,u,6,1>: Cost 3 vext1 <1,3,u,6>, <1,3,u,6>
+ 2689841351U, // <3,u,6,2>: Cost 3 vext3 LHS, <u,6,2,7>
+ 1616099536U, // <3,u,6,3>: Cost 2 vext3 LHS, <u,6,3,7>
+ 1659227508U, // <3,u,6,4>: Cost 2 vext3 LHS, <4,6,4,6>
+ 2690283746U, // <3,u,6,5>: Cost 3 vext3 LHS, <u,6,5,7>
1659228984U, // <3,u,6,6>: Cost 2 vext3 LHS, <6,6,6,6>
1659230445U, // <3,u,6,7>: Cost 2 vext3 LHS, <u,6,7,0>
- 1659230454U, // <3,u,6,u>: Cost 2 vext3 LHS, <u,6,u,0>
- 1659230464U, // <3,u,7,0>: Cost 2 vext3 LHS, <u,7,0,1>
- 2732972296U, // <3,u,7,1>: Cost 3 vext3 LHS, <u,7,1,0>
- 2660668596U, // <3,u,7,2>: Cost 3 vext2 <7,2,3,u>, <7,2,3,u>
- 2720069919U, // <3,u,7,3>: Cost 3 vext3 <5,u,7,3>, <u,7,3,5>
- 1659230504U, // <3,u,7,4>: Cost 2 vext3 LHS, <u,7,4,5>
- 2715425069U, // <3,u,7,5>: Cost 3 vext3 <5,1,7,3>, <u,7,5,1>
+ 1616099581U, // <3,u,6,u>: Cost 2 vext3 LHS, <u,6,u,7>
+ 1485004902U, // <3,u,7,0>: Cost 2 vext1 <1,3,u,7>, LHS
+ 1485005851U, // <3,u,7,1>: Cost 2 vext1 <1,3,u,7>, <1,3,u,7>
+ 2558748264U, // <3,u,7,2>: Cost 3 vext1 <1,3,u,7>, <2,2,2,2>
+ 3095397021U, // <3,u,7,3>: Cost 3 vtrnr <1,3,5,7>, LHS
+ 1485008182U, // <3,u,7,4>: Cost 2 vext1 <1,3,u,7>, RHS
+ 1659228328U, // <3,u,7,5>: Cost 2 vext3 LHS, <5,7,5,7>
2722060599U, // <3,u,7,6>: Cost 3 vext3 <6,2,7,3>, <u,7,6,2>
1659229804U, // <3,u,7,7>: Cost 2 vext3 LHS, <7,7,7,7>
- 1659230536U, // <3,u,7,u>: Cost 2 vext3 LHS, <u,7,u,1>
- 1611897170U, // <3,u,u,0>: Cost 2 vext3 LHS, <u,u,0,2>
+ 1485010734U, // <3,u,7,u>: Cost 2 vext1 <1,3,u,7>, LHS
+ 1616099665U, // <3,u,u,0>: Cost 2 vext3 LHS, <u,u,0,1>
1611897179U, // <3,u,u,1>: Cost 2 vext3 LHS, <u,u,1,2>
537712997U, // <3,u,u,2>: Cost 1 vext3 LHS, LHS
336380006U, // <3,u,u,3>: Cost 1 vdup3 LHS
1616099705U, // <3,u,u,4>: Cost 2 vext3 LHS, <u,u,4,5>
1611897219U, // <3,u,u,5>: Cost 2 vext3 LHS, <u,u,5,6>
537713037U, // <3,u,u,6>: Cost 1 vext3 LHS, RHS
- 1616099730U, // <3,u,u,7>: Cost 2 vext3 LHS, <u,u,7,3>
+ 1659230607U, // <3,u,u,7>: Cost 2 vext3 LHS, <u,u,7,0>
537713051U, // <3,u,u,u>: Cost 1 vext3 LHS, LHS
2691907584U, // <4,0,0,0>: Cost 3 vext3 <1,2,3,4>, <0,0,0,0>
- 2953669522U, // <4,0,0,1>: Cost 3 vzipr LHS, <4,0,5,1>
- 2819411276U, // <4,0,0,2>: Cost 3 vuzpr LHS, <4,6,0,2>
- 3644451279U, // <4,0,0,3>: Cost 4 vext1 <3,4,0,0>, <3,4,0,0>
- 2576681874U, // <4,0,0,4>: Cost 3 vext1 <4,4,0,0>, <4,0,5,1>
- 3650424445U, // <4,0,0,5>: Cost 4 vext1 <4,4,0,0>, <5,0,7,1>
- 3650425338U, // <4,0,0,6>: Cost 4 vext1 <4,4,0,0>, <6,2,7,3>
+ 2691907594U, // <4,0,0,1>: Cost 3 vext3 <1,2,3,4>, <0,0,1,1>
+ 2691907604U, // <4,0,0,2>: Cost 3 vext3 <1,2,3,4>, <0,0,2,2>
+ 3709862144U, // <4,0,0,3>: Cost 4 vext2 <3,1,4,0>, <0,3,1,4>
+ 2684682280U, // <4,0,0,4>: Cost 3 vext3 <0,0,4,4>, <0,0,4,4>
+ 3694600633U, // <4,0,0,5>: Cost 4 vext2 <0,5,4,0>, <0,5,4,0>
+ 3291431290U, // <4,0,0,6>: Cost 4 vrev <0,4,6,0>
3668342067U, // <4,0,0,7>: Cost 4 vext1 <7,4,0,0>, <7,4,0,0>
- 2819853644U, // <4,0,0,u>: Cost 3 vuzpr LHS, <4,6,0,2>
+ 2691907657U, // <4,0,0,u>: Cost 3 vext3 <1,2,3,4>, <0,0,u,1>
2570715238U, // <4,0,1,0>: Cost 3 vext1 <3,4,0,1>, LHS
2570716058U, // <4,0,1,1>: Cost 3 vext1 <3,4,0,1>, <1,2,3,4>
1618165862U, // <4,0,1,2>: Cost 2 vext3 <1,2,3,4>, LHS
2570717648U, // <4,0,1,3>: Cost 3 vext1 <3,4,0,1>, <3,4,0,1>
2570718518U, // <4,0,1,4>: Cost 3 vext1 <3,4,0,1>, RHS
2594607206U, // <4,0,1,5>: Cost 3 vext1 <7,4,0,1>, <5,6,7,4>
- 3644461562U, // <4,0,1,6>: Cost 4 vext1 <3,4,0,1>, <6,2,7,3>
+ 3662377563U, // <4,0,1,6>: Cost 4 vext1 <6,4,0,1>, <6,4,0,1>
2594608436U, // <4,0,1,7>: Cost 3 vext1 <7,4,0,1>, <7,4,0,1>
1618165916U, // <4,0,1,u>: Cost 2 vext3 <1,2,3,4>, LHS
- 2691907748U, // <4,0,2,0>: Cost 3 vext3 <1,2,3,4>, <0,2,0,2>
- 4027370550U, // <4,0,2,1>: Cost 4 vzipr LHS, <4,2,5,3>
- 2564753102U, // <4,0,2,2>: Cost 3 vext1 <2,4,0,2>, <2,3,4,5>
+ 2685714598U, // <4,0,2,0>: Cost 3 vext3 <0,2,0,4>, <0,2,0,4>
+ 3759530159U, // <4,0,2,1>: Cost 4 vext3 <0,2,1,4>, <0,2,1,4>
+ 2685862072U, // <4,0,2,2>: Cost 3 vext3 <0,2,2,4>, <0,2,2,4>
2631476937U, // <4,0,2,3>: Cost 3 vext2 <2,3,4,0>, <2,3,4,0>
- 2564754742U, // <4,0,2,4>: Cost 3 vext1 <2,4,0,2>, RHS
- 3638496840U, // <4,0,2,5>: Cost 4 vext1 <2,4,0,2>, <5,0,1,2>
- 2588643932U, // <4,0,2,6>: Cost 3 vext1 <6,4,0,2>, <6,4,0,2>
+ 2685714636U, // <4,0,2,4>: Cost 3 vext3 <0,2,0,4>, <0,2,4,6>
+ 3765649622U, // <4,0,2,5>: Cost 4 vext3 <1,2,3,4>, <0,2,5,7>
+ 2686157020U, // <4,0,2,6>: Cost 3 vext3 <0,2,6,4>, <0,2,6,4>
3668358453U, // <4,0,2,7>: Cost 4 vext1 <7,4,0,2>, <7,4,0,2>
- 2564757294U, // <4,0,2,u>: Cost 3 vext1 <2,4,0,2>, LHS
- 3705219222U, // <4,0,3,0>: Cost 4 vext2 <2,3,4,0>, <3,0,1,2>
- 3910323532U, // <4,0,3,1>: Cost 4 vuzpr <3,0,1,2>, <4,6,0,2>
+ 2686304494U, // <4,0,2,u>: Cost 3 vext3 <0,2,u,4>, <0,2,u,4>
+ 3632529510U, // <4,0,3,0>: Cost 4 vext1 <1,4,0,3>, LHS
+ 2686451968U, // <4,0,3,1>: Cost 3 vext3 <0,3,1,4>, <0,3,1,4>
2686525705U, // <4,0,3,2>: Cost 3 vext3 <0,3,2,4>, <0,3,2,4>
- 3705219484U, // <4,0,3,3>: Cost 4 vext2 <2,3,4,0>, <3,3,3,3>
- 3705219539U, // <4,0,3,4>: Cost 4 vext2 <2,3,4,0>, <3,4,0,4>
- 3913305420U, // <4,0,3,5>: Cost 4 vuzpr <3,4,5,6>, <4,6,0,2>
- 3913329996U, // <4,0,3,6>: Cost 4 vuzpr <3,4,6,0>, <4,6,0,2>
+ 3760341266U, // <4,0,3,3>: Cost 4 vext3 <0,3,3,4>, <0,3,3,4>
+ 3632532790U, // <4,0,3,4>: Cost 4 vext1 <1,4,0,3>, RHS
+ 3913254606U, // <4,0,3,5>: Cost 4 vuzpr <3,4,5,0>, <2,3,4,5>
+ 3705219740U, // <4,0,3,6>: Cost 4 vext2 <2,3,4,0>, <3,6,4,7>
3713845990U, // <4,0,3,7>: Cost 4 vext2 <3,7,4,0>, <3,7,4,0>
- 2686968127U, // <4,0,3,u>: Cost 3 vext3 <0,3,u,4>, <0,3,u,4>
- 2631478162U, // <4,0,4,0>: Cost 3 vext2 <2,3,4,0>, <4,0,5,1>
- 2718744914U, // <4,0,4,1>: Cost 3 vext3 <5,6,7,4>, <0,4,1,5>
- 2718744924U, // <4,0,4,2>: Cost 3 vext3 <5,6,7,4>, <0,4,2,6>
- 3644484051U, // <4,0,4,3>: Cost 4 vext1 <3,4,0,4>, <3,4,0,4>
- 2644085964U, // <4,0,4,4>: Cost 3 vext2 <4,4,4,0>, <4,4,4,0>
+ 2686451968U, // <4,0,3,u>: Cost 3 vext3 <0,3,1,4>, <0,3,1,4>
+ 2552823910U, // <4,0,4,0>: Cost 3 vext1 <0,4,0,4>, LHS
+ 2691907922U, // <4,0,4,1>: Cost 3 vext3 <1,2,3,4>, <0,4,1,5>
+ 2691907932U, // <4,0,4,2>: Cost 3 vext3 <1,2,3,4>, <0,4,2,6>
+ 3626567830U, // <4,0,4,3>: Cost 4 vext1 <0,4,0,4>, <3,0,1,2>
+ 2552827190U, // <4,0,4,4>: Cost 3 vext1 <0,4,0,4>, RHS
2631478582U, // <4,0,4,5>: Cost 3 vext2 <2,3,4,0>, RHS
- 2846281036U, // <4,0,4,6>: Cost 3 vuzpr RHS, <4,6,0,2>
+ 3626570017U, // <4,0,4,6>: Cost 4 vext1 <0,4,0,4>, <6,0,1,2>
3668374839U, // <4,0,4,7>: Cost 4 vext1 <7,4,0,4>, <7,4,0,4>
- 2631478825U, // <4,0,4,u>: Cost 3 vext2 <2,3,4,0>, RHS
- 2570748006U, // <4,0,5,0>: Cost 3 vext1 <3,4,0,5>, LHS
- 1879887158U, // <4,0,5,1>: Cost 2 vzipr LHS, RHS
- 3087846290U, // <4,0,5,2>: Cost 3 vtrnr LHS, <4,0,5,1>
+ 2552829742U, // <4,0,4,u>: Cost 3 vext1 <0,4,0,4>, LHS
+ 2558804070U, // <4,0,5,0>: Cost 3 vext1 <1,4,0,5>, LHS
+ 1839644774U, // <4,0,5,1>: Cost 2 vzipl RHS, LHS
+ 2913386660U, // <4,0,5,2>: Cost 3 vzipl RHS, <0,2,0,2>
2570750420U, // <4,0,5,3>: Cost 3 vext1 <3,4,0,5>, <3,4,0,5>
- 2570750866U, // <4,0,5,4>: Cost 3 vext1 <3,4,0,5>, <4,0,5,1>
- 3644493520U, // <4,0,5,5>: Cost 4 vext1 <3,4,0,5>, <5,1,7,3>
- 3644494330U, // <4,0,5,6>: Cost 4 vext1 <3,4,0,5>, <6,2,7,3>
+ 2558807350U, // <4,0,5,4>: Cost 3 vext1 <1,4,0,5>, RHS
+ 3987128750U, // <4,0,5,5>: Cost 4 vzipl RHS, <0,5,2,7>
+ 3987128822U, // <4,0,5,6>: Cost 4 vzipl RHS, <0,6,1,7>
2594641208U, // <4,0,5,7>: Cost 3 vext1 <7,4,0,5>, <7,4,0,5>
- 1884532022U, // <4,0,5,u>: Cost 2 vzipr LHS, RHS
- 3088354614U, // <4,0,6,0>: Cost 3 vtrnr <0,2,0,2>, RHS
- 2953629004U, // <4,0,6,1>: Cost 3 vzipr LHS, <4,6,0,2>
- 2014104886U, // <4,0,6,2>: Cost 2 vtrnr LHS, RHS
+ 1839645341U, // <4,0,5,u>: Cost 2 vzipl RHS, LHS
+ 2552840294U, // <4,0,6,0>: Cost 3 vext1 <0,4,0,6>, LHS
+ 3047604234U, // <4,0,6,1>: Cost 3 vtrnl RHS, <0,0,1,1>
+ 1973862502U, // <4,0,6,2>: Cost 2 vtrnl RHS, LHS
2570758613U, // <4,0,6,3>: Cost 3 vext1 <3,4,0,6>, <3,4,0,6>
- 2570759068U, // <4,0,6,4>: Cost 3 vext1 <3,4,0,6>, <4,0,6,2>
+ 2552843574U, // <4,0,6,4>: Cost 3 vext1 <0,4,0,6>, RHS
2217664887U, // <4,0,6,5>: Cost 3 vrev <0,4,5,6>
- 3644502477U, // <4,0,6,6>: Cost 4 vext1 <3,4,0,6>, <6,2,2,3>
+ 3662418528U, // <4,0,6,6>: Cost 4 vext1 <6,4,0,6>, <6,4,0,6>
2658022257U, // <4,0,6,7>: Cost 3 vext2 <6,7,4,0>, <6,7,4,0>
- 2014547254U, // <4,0,6,u>: Cost 2 vtrnr LHS, RHS
- 3719156730U, // <4,0,7,0>: Cost 4 vext2 <4,6,4,0>, <7,0,1,2>
- 3934211404U, // <4,0,7,1>: Cost 4 vuzpr <7,0,1,2>, <4,6,0,2>
- 3734418613U, // <4,0,7,2>: Cost 4 vext2 <7,2,4,0>, <7,2,4,0>
+ 1973862556U, // <4,0,6,u>: Cost 2 vtrnl RHS, LHS
+ 3731764218U, // <4,0,7,0>: Cost 4 vext2 <6,7,4,0>, <7,0,1,2>
+ 3988324454U, // <4,0,7,1>: Cost 4 vzipl <4,7,5,0>, LHS
+ 4122034278U, // <4,0,7,2>: Cost 4 vtrnl <4,6,7,1>, LHS
3735082246U, // <4,0,7,3>: Cost 4 vext2 <7,3,4,0>, <7,3,4,0>
- 3719157094U, // <4,0,7,4>: Cost 4 vext2 <4,6,4,0>, <7,4,5,6>
- 3721811345U, // <4,0,7,5>: Cost 4 vext2 <5,1,4,0>, <7,5,1,4>
- 3728446955U, // <4,0,7,6>: Cost 4 vext2 <6,2,4,0>, <7,6,2,4>
- 3719157356U, // <4,0,7,7>: Cost 4 vext2 <4,6,4,0>, <7,7,7,7>
- 3719157378U, // <4,0,7,u>: Cost 4 vext2 <4,6,4,0>, <7,u,1,2>
- 3088354632U, // <4,0,u,0>: Cost 3 vtrnr <0,2,0,2>, RHS
- 1879887401U, // <4,0,u,1>: Cost 2 vzipr LHS, RHS
- 2014104904U, // <4,0,u,2>: Cost 2 vtrnr LHS, RHS
+ 3731764536U, // <4,0,7,4>: Cost 4 vext2 <6,7,4,0>, <7,4,0,5>
+ 3937145718U, // <4,0,7,5>: Cost 4 vuzpr <7,4,5,0>, <6,7,4,5>
+ 3737073145U, // <4,0,7,6>: Cost 4 vext2 <7,6,4,0>, <7,6,4,0>
+ 3731764844U, // <4,0,7,7>: Cost 4 vext2 <6,7,4,0>, <7,7,7,7>
+ 4122034332U, // <4,0,7,u>: Cost 4 vtrnl <4,6,7,1>, LHS
+ 2552856678U, // <4,0,u,0>: Cost 3 vext1 <0,4,0,u>, LHS
+ 1841635430U, // <4,0,u,1>: Cost 2 vzipl RHS, LHS
+ 1618166429U, // <4,0,u,2>: Cost 2 vext3 <1,2,3,4>, LHS
2570774999U, // <4,0,u,3>: Cost 3 vext1 <3,4,0,u>, <3,4,0,u>
- 2564803894U, // <4,0,u,4>: Cost 3 vext1 <2,4,0,u>, RHS
+ 2552859958U, // <4,0,u,4>: Cost 3 vext1 <0,4,0,u>, RHS
2631481498U, // <4,0,u,5>: Cost 3 vext2 <2,3,4,0>, RHS
- 2870168908U, // <4,0,u,6>: Cost 3 vuzpr RHS, <4,6,0,2>
+ 2686157020U, // <4,0,u,6>: Cost 3 vext3 <0,2,6,4>, <0,2,6,4>
2594665787U, // <4,0,u,7>: Cost 3 vext1 <7,4,0,u>, <7,4,0,u>
- 2014547272U, // <4,0,u,u>: Cost 2 vtrnr LHS, RHS
- 4032744338U, // <4,1,0,0>: Cost 4 vzipr <1,0,3,2>, <4,0,5,1>
- 2631483494U, // <4,1,0,1>: Cost 3 vext2 <2,3,4,1>, LHS
- 4034055058U, // <4,1,0,2>: Cost 4 vzipr <1,2,3,0>, <4,0,5,1>
+ 1618166483U, // <4,0,u,u>: Cost 2 vext3 <1,2,3,4>, LHS
+ 2617548837U, // <4,1,0,0>: Cost 3 vext2 <0,0,4,1>, <0,0,4,1>
+ 2622857318U, // <4,1,0,1>: Cost 3 vext2 <0,u,4,1>, LHS
+ 3693281484U, // <4,1,0,2>: Cost 4 vext2 <0,3,4,1>, <0,2,4,6>
2691908342U, // <4,1,0,3>: Cost 3 vext3 <1,2,3,4>, <1,0,3,2>
- 2659352914U, // <4,1,0,4>: Cost 3 vext2 <7,0,4,1>, <0,4,1,5>
- 3297330250U, // <4,1,0,5>: Cost 4 vrev <1,4,5,0>
- 3297403987U, // <4,1,0,6>: Cost 4 vrev <1,4,6,0>
- 3668415804U, // <4,1,0,7>: Cost 4 vext1 <7,4,1,0>, <7,4,1,0>
- 2691908387U, // <4,1,0,u>: Cost 3 vext3 <1,2,3,4>, <1,0,u,2>
- 3764839211U, // <4,1,1,0>: Cost 4 vext3 <1,1,1,4>, <1,1,0,1>
+ 2622857554U, // <4,1,0,4>: Cost 3 vext2 <0,u,4,1>, <0,4,1,5>
+ 3764470538U, // <4,1,0,5>: Cost 4 vext3 <1,0,5,4>, <1,0,5,4>
+ 3695272459U, // <4,1,0,6>: Cost 4 vext2 <0,6,4,1>, <0,6,4,1>
+ 3733094980U, // <4,1,0,7>: Cost 4 vext2 <7,0,4,1>, <0,7,1,4>
+ 2622857885U, // <4,1,0,u>: Cost 3 vext2 <0,u,4,1>, LHS
+ 3696599798U, // <4,1,1,0>: Cost 4 vext2 <0,u,4,1>, <1,0,3,2>
2691097399U, // <4,1,1,1>: Cost 3 vext3 <1,1,1,4>, <1,1,1,4>
2631484314U, // <4,1,1,2>: Cost 3 vext2 <2,3,4,1>, <1,2,3,4>
2691908424U, // <4,1,1,3>: Cost 3 vext3 <1,2,3,4>, <1,1,3,3>
- 3764839247U, // <4,1,1,4>: Cost 4 vext3 <1,1,1,4>, <1,1,4,1>
- 3765134171U, // <4,1,1,5>: Cost 4 vext3 <1,1,5,4>, <1,1,5,4>
- 3733095667U, // <4,1,1,6>: Cost 4 vext2 <7,0,4,1>, <1,6,5,7>
+ 3696600125U, // <4,1,1,4>: Cost 4 vext2 <0,u,4,1>, <1,4,3,5>
+ 3696600175U, // <4,1,1,5>: Cost 4 vext2 <0,u,4,1>, <1,5,0,1>
+ 3696600307U, // <4,1,1,6>: Cost 4 vext2 <0,u,4,1>, <1,6,5,7>
3668423997U, // <4,1,1,7>: Cost 4 vext1 <7,4,1,1>, <7,4,1,1>
2691908469U, // <4,1,1,u>: Cost 3 vext3 <1,2,3,4>, <1,1,u,3>
2570797158U, // <4,1,2,0>: Cost 3 vext1 <3,4,1,2>, LHS
2570797978U, // <4,1,2,1>: Cost 3 vext1 <3,4,1,2>, <1,2,3,4>
- 3765650320U, // <4,1,2,2>: Cost 4 vext3 <1,2,3,4>, <1,2,2,3>
+ 3696600680U, // <4,1,2,2>: Cost 4 vext2 <0,u,4,1>, <2,2,2,2>
1618166682U, // <4,1,2,3>: Cost 2 vext3 <1,2,3,4>, <1,2,3,4>
2570800438U, // <4,1,2,4>: Cost 3 vext1 <3,4,1,2>, RHS
- 3644542672U, // <4,1,2,5>: Cost 4 vext1 <3,4,1,2>, <5,1,7,3>
- 3644543482U, // <4,1,2,6>: Cost 4 vext1 <3,4,1,2>, <6,2,7,3>
+ 3765650347U, // <4,1,2,5>: Cost 4 vext3 <1,2,3,4>, <1,2,5,3>
+ 3696601018U, // <4,1,2,6>: Cost 4 vext2 <0,u,4,1>, <2,6,3,7>
3668432190U, // <4,1,2,7>: Cost 4 vext1 <7,4,1,2>, <7,4,1,2>
1618535367U, // <4,1,2,u>: Cost 2 vext3 <1,2,u,4>, <1,2,u,4>
- 2635466928U, // <4,1,3,0>: Cost 3 vext2 <3,0,4,1>, <3,0,4,1>
- 3765650392U, // <4,1,3,1>: Cost 4 vext3 <1,2,3,4>, <1,3,1,3>
- 3705227604U, // <4,1,3,2>: Cost 4 vext2 <2,3,4,1>, <3,2,4,3>
+ 2564833382U, // <4,1,3,0>: Cost 3 vext1 <2,4,1,3>, LHS
+ 2691908568U, // <4,1,3,1>: Cost 3 vext3 <1,2,3,4>, <1,3,1,3>
+ 2691908578U, // <4,1,3,2>: Cost 3 vext3 <1,2,3,4>, <1,3,2,4>
2692572139U, // <4,1,3,3>: Cost 3 vext3 <1,3,3,4>, <1,3,3,4>
- 2635467266U, // <4,1,3,4>: Cost 3 vext2 <3,0,4,1>, <3,4,5,6>
- 3709209122U, // <4,1,3,5>: Cost 4 vext2 <3,0,4,1>, <3,5,0,2>
- 3297428566U, // <4,1,3,6>: Cost 4 vrev <1,4,6,3>
- 3713854183U, // <4,1,3,7>: Cost 4 vext2 <3,7,4,1>, <3,7,4,1>
- 2692940824U, // <4,1,3,u>: Cost 3 vext3 <1,3,u,4>, <1,3,u,4>
- 3764839454U, // <4,1,4,0>: Cost 4 vext3 <1,1,1,4>, <1,4,0,1>
- 3764839463U, // <4,1,4,1>: Cost 4 vext3 <1,1,1,4>, <1,4,1,1>
- 4034088144U, // <4,1,4,2>: Cost 4 vzipr <1,2,3,4>, <4,4,4,4>
- 3068513488U, // <4,1,4,3>: Cost 3 vtrnl LHS, <4,4,4,4>
- 3764839494U, // <4,1,4,4>: Cost 4 vext3 <1,1,1,4>, <1,4,4,5>
- 2631486774U, // <4,1,4,5>: Cost 3 vext2 <2,3,4,1>, RHS
- 3705228620U, // <4,1,4,6>: Cost 4 vext2 <2,3,4,1>, <4,6,0,2>
+ 2564836662U, // <4,1,3,4>: Cost 3 vext1 <2,4,1,3>, RHS
+ 2691908608U, // <4,1,3,5>: Cost 3 vext3 <1,2,3,4>, <1,3,5,7>
+ 2588725862U, // <4,1,3,6>: Cost 3 vext1 <6,4,1,3>, <6,4,1,3>
+ 3662468090U, // <4,1,3,7>: Cost 4 vext1 <6,4,1,3>, <7,0,1,2>
+ 2691908631U, // <4,1,3,u>: Cost 3 vext3 <1,2,3,4>, <1,3,u,3>
+ 3760194590U, // <4,1,4,0>: Cost 4 vext3 <0,3,1,4>, <1,4,0,1>
+ 3693947874U, // <4,1,4,1>: Cost 4 vext2 <0,4,4,1>, <4,1,5,0>
+ 3765650484U, // <4,1,4,2>: Cost 4 vext3 <1,2,3,4>, <1,4,2,5>
+ 3113877606U, // <4,1,4,3>: Cost 3 vtrnr <4,4,4,4>, LHS
+ 3760194630U, // <4,1,4,4>: Cost 4 vext3 <0,3,1,4>, <1,4,4,5>
+ 2622860598U, // <4,1,4,5>: Cost 3 vext2 <0,u,4,1>, RHS
+ 3297436759U, // <4,1,4,6>: Cost 4 vrev <1,4,6,4>
3800007772U, // <4,1,4,7>: Cost 4 vext3 <7,0,1,4>, <1,4,7,0>
- 2631487017U, // <4,1,4,u>: Cost 3 vext2 <2,3,4,1>, RHS
- 1526939750U, // <4,1,5,0>: Cost 2 vext1 <u,4,1,5>, LHS
- 2959510838U, // <4,1,5,1>: Cost 3 vzipr <1,1,1,1>, RHS
- 2960313654U, // <4,1,5,2>: Cost 3 vzipr <1,2,3,0>, RHS
- 2718745744U, // <4,1,5,3>: Cost 3 vext3 <5,6,7,4>, <1,5,3,7>
- 1526943030U, // <4,1,5,4>: Cost 2 vext1 <u,4,1,5>, RHS
- 2582769360U, // <4,1,5,5>: Cost 3 vext1 <5,4,1,5>, <5,1,7,3>
+ 2622860841U, // <4,1,4,u>: Cost 3 vext2 <0,u,4,1>, RHS
+ 1479164006U, // <4,1,5,0>: Cost 2 vext1 <0,4,1,5>, LHS
+ 2552906486U, // <4,1,5,1>: Cost 3 vext1 <0,4,1,5>, <1,0,3,2>
+ 2552907299U, // <4,1,5,2>: Cost 3 vext1 <0,4,1,5>, <2,1,3,5>
+ 2552907926U, // <4,1,5,3>: Cost 3 vext1 <0,4,1,5>, <3,0,1,2>
+ 1479167286U, // <4,1,5,4>: Cost 2 vext1 <0,4,1,5>, RHS
+ 2913387664U, // <4,1,5,5>: Cost 3 vzipl RHS, <1,5,3,7>
2600686074U, // <4,1,5,6>: Cost 3 vext1 <u,4,1,5>, <6,2,7,3>
2600686586U, // <4,1,5,7>: Cost 3 vext1 <u,4,1,5>, <7,0,1,2>
- 1526945582U, // <4,1,5,u>: Cost 2 vext1 <u,4,1,5>, LHS
- 2552913930U, // <4,1,6,0>: Cost 3 vext1 <0,4,1,6>, <0,0,1,1>
- 3093728566U, // <4,1,6,1>: Cost 3 vtrnr <1,1,1,1>, RHS
- 4166880566U, // <4,1,6,2>: Cost 4 vtrnr <1,0,2,1>, RHS
- 3020737026U, // <4,1,6,3>: Cost 3 vtrnl LHS, <3,4,5,6>
+ 1479169838U, // <4,1,5,u>: Cost 2 vext1 <0,4,1,5>, LHS
+ 2552914022U, // <4,1,6,0>: Cost 3 vext1 <0,4,1,6>, LHS
+ 2558886708U, // <4,1,6,1>: Cost 3 vext1 <1,4,1,6>, <1,1,1,1>
+ 4028205206U, // <4,1,6,2>: Cost 4 vzipr <0,2,4,6>, <3,0,1,2>
+ 3089858662U, // <4,1,6,3>: Cost 3 vtrnr <0,4,2,6>, LHS
2552917302U, // <4,1,6,4>: Cost 3 vext1 <0,4,1,6>, RHS
2223637584U, // <4,1,6,5>: Cost 3 vrev <1,4,5,6>
- 3662492265U, // <4,1,6,6>: Cost 4 vext1 <6,4,1,6>, <6,4,1,6>
- 3731772274U, // <4,1,6,7>: Cost 4 vext2 <6,7,4,1>, <6,7,4,1>
- 3020777986U, // <4,1,6,u>: Cost 3 vtrnl LHS, <3,4,5,6>
+ 4121347081U, // <4,1,6,6>: Cost 4 vtrnl RHS, <1,3,6,7>
+ 3721155406U, // <4,1,6,7>: Cost 4 vext2 <5,0,4,1>, <6,7,0,1>
+ 2552919854U, // <4,1,6,u>: Cost 3 vext1 <0,4,1,6>, LHS
2659357716U, // <4,1,7,0>: Cost 3 vext2 <7,0,4,1>, <7,0,4,1>
- 3768821021U, // <4,1,7,1>: Cost 4 vext3 <1,7,1,4>, <1,7,1,4>
- 3768894758U, // <4,1,7,2>: Cost 4 vext3 <1,7,2,4>, <1,7,2,4>
+ 3733763173U, // <4,1,7,1>: Cost 4 vext2 <7,1,4,1>, <7,1,4,1>
+ 3734426806U, // <4,1,7,2>: Cost 4 vext2 <7,2,4,1>, <7,2,4,1>
2695226671U, // <4,1,7,3>: Cost 3 vext3 <1,7,3,4>, <1,7,3,4>
- 3733099878U, // <4,1,7,4>: Cost 4 vext2 <7,0,4,1>, <7,4,5,6>
- 3736417705U, // <4,1,7,5>: Cost 4 vext2 <7,5,4,1>, <7,5,4,1>
- 3297461338U, // <4,1,7,6>: Cost 4 vrev <1,4,6,7>
- 3733100074U, // <4,1,7,7>: Cost 4 vext2 <7,0,4,1>, <7,7,0,4>
- 2664666780U, // <4,1,7,u>: Cost 3 vext2 <7,u,4,1>, <7,u,4,1>
- 1526939750U, // <4,1,u,0>: Cost 2 vext1 <u,4,1,5>, LHS
- 2959511081U, // <4,1,u,1>: Cost 3 vzipr <1,1,1,1>, RHS
- 2960313897U, // <4,1,u,2>: Cost 3 vzipr <1,2,3,0>, RHS
+ 3721155942U, // <4,1,7,4>: Cost 4 vext2 <5,0,4,1>, <7,4,5,6>
+ 3721155976U, // <4,1,7,5>: Cost 4 vext2 <5,0,4,1>, <7,5,0,4>
+ 3662500458U, // <4,1,7,6>: Cost 4 vext1 <6,4,1,7>, <6,4,1,7>
+ 3721156204U, // <4,1,7,7>: Cost 4 vext2 <5,0,4,1>, <7,7,7,7>
+ 2659357716U, // <4,1,7,u>: Cost 3 vext2 <7,0,4,1>, <7,0,4,1>
+ 1479188582U, // <4,1,u,0>: Cost 2 vext1 <0,4,1,u>, LHS
+ 2552931062U, // <4,1,u,1>: Cost 3 vext1 <0,4,1,u>, <1,0,3,2>
+ 2552931944U, // <4,1,u,2>: Cost 3 vext1 <0,4,1,u>, <2,2,2,2>
1622148480U, // <4,1,u,3>: Cost 2 vext3 <1,u,3,4>, <1,u,3,4>
- 1526943030U, // <4,1,u,4>: Cost 2 vext1 <u,4,1,5>, RHS
- 2223653970U, // <4,1,u,5>: Cost 3 vrev <1,4,5,u>
- 2600686074U, // <4,1,u,6>: Cost 3 vext1 <u,4,1,5>, <6,2,7,3>
+ 1479191862U, // <4,1,u,4>: Cost 2 vext1 <0,4,1,u>, RHS
+ 2622863514U, // <4,1,u,5>: Cost 3 vext2 <0,u,4,1>, RHS
+ 2588725862U, // <4,1,u,6>: Cost 3 vext1 <6,4,1,3>, <6,4,1,3>
2600686586U, // <4,1,u,7>: Cost 3 vext1 <u,4,1,5>, <7,0,1,2>
- 1622517165U, // <4,1,u,u>: Cost 2 vext3 <1,u,u,4>, <1,u,u,4>
- 2588770406U, // <4,2,0,0>: Cost 3 vext1 <6,4,2,0>, LHS
- 2629501030U, // <4,2,0,1>: Cost 3 vext2 <2,0,4,2>, LHS
- 2696480200U, // <4,2,0,2>: Cost 3 vext3 <2,0,2,4>, <2,0,2,4>
- 3964905161U, // <4,2,0,3>: Cost 4 vzipl LHS, <2,3,4,0>
- 2588773686U, // <4,2,0,4>: Cost 3 vext1 <6,4,2,0>, RHS
- 3770443235U, // <4,2,0,5>: Cost 4 vext3 <2,0,5,4>, <2,0,5,4>
- 2588775020U, // <4,2,0,6>: Cost 3 vext1 <6,4,2,0>, <6,4,2,0>
- 3662517242U, // <4,2,0,7>: Cost 4 vext1 <6,4,2,0>, <7,0,1,2>
- 2629501597U, // <4,2,0,u>: Cost 3 vext2 <2,0,4,2>, LHS
- 3765650950U, // <4,2,1,0>: Cost 4 vext3 <1,2,3,4>, <2,1,0,3>
- 3703243572U, // <4,2,1,1>: Cost 4 vext2 <2,0,4,2>, <1,1,1,1>
- 3765650968U, // <4,2,1,2>: Cost 4 vext3 <1,2,3,4>, <2,1,2,3>
- 3964905648U, // <4,2,1,3>: Cost 4 vzipl LHS, <3,0,4,1>
+ 1479194414U, // <4,1,u,u>: Cost 2 vext1 <0,4,1,u>, LHS
+ 2617557030U, // <4,2,0,0>: Cost 3 vext2 <0,0,4,2>, <0,0,4,2>
+ 2622865510U, // <4,2,0,1>: Cost 3 vext2 <0,u,4,2>, LHS
+ 2622865612U, // <4,2,0,2>: Cost 3 vext2 <0,u,4,2>, <0,2,4,6>
+ 3693289753U, // <4,2,0,3>: Cost 4 vext2 <0,3,4,2>, <0,3,4,2>
+ 2635473244U, // <4,2,0,4>: Cost 3 vext2 <3,0,4,2>, <0,4,2,6>
+ 3765650918U, // <4,2,0,5>: Cost 4 vext3 <1,2,3,4>, <2,0,5,7>
+ 2696775148U, // <4,2,0,6>: Cost 3 vext3 <2,0,6,4>, <2,0,6,4>
+ 3695944285U, // <4,2,0,7>: Cost 4 vext2 <0,7,4,2>, <0,7,4,2>
+ 2622866077U, // <4,2,0,u>: Cost 3 vext2 <0,u,4,2>, LHS
+ 3696607990U, // <4,2,1,0>: Cost 4 vext2 <0,u,4,2>, <1,0,3,2>
+ 3696608052U, // <4,2,1,1>: Cost 4 vext2 <0,u,4,2>, <1,1,1,1>
+ 3696608150U, // <4,2,1,2>: Cost 4 vext2 <0,u,4,2>, <1,2,3,0>
+ 3895574630U, // <4,2,1,3>: Cost 4 vuzpr <0,4,u,2>, LHS
2691909162U, // <4,2,1,4>: Cost 3 vext3 <1,2,3,4>, <2,1,4,3>
- 3733103760U, // <4,2,1,5>: Cost 4 vext2 <7,0,4,2>, <1,5,3,7>
- 3807454780U, // <4,2,1,6>: Cost 4 vext3 <u,2,3,4>, <2,1,6,3>
- 3792488005U, // <4,2,1,7>: Cost 5 vext3 <5,6,7,4>, <2,1,7,3>
+ 3696608400U, // <4,2,1,5>: Cost 4 vext2 <0,u,4,2>, <1,5,3,7>
+ 3760784956U, // <4,2,1,6>: Cost 4 vext3 <0,4,0,4>, <2,1,6,3>
+ 3773908549U, // <4,2,1,7>: Cost 5 vext3 <2,5,7,4>, <2,1,7,3>
2691909162U, // <4,2,1,u>: Cost 3 vext3 <1,2,3,4>, <2,1,4,3>
- 2629502424U, // <4,2,2,0>: Cost 3 vext2 <2,0,4,2>, <2,0,4,2>
- 3644613530U, // <4,2,2,1>: Cost 4 vext1 <3,4,2,2>, <1,2,3,4>
+ 3696608748U, // <4,2,2,0>: Cost 4 vext2 <0,u,4,2>, <2,0,6,4>
+ 3696608828U, // <4,2,2,1>: Cost 4 vext2 <0,u,4,2>, <2,1,6,3>
2691909224U, // <4,2,2,2>: Cost 3 vext3 <1,2,3,4>, <2,2,2,2>
2691909234U, // <4,2,2,3>: Cost 3 vext3 <1,2,3,4>, <2,2,3,3>
- 2697954940U, // <4,2,2,4>: Cost 3 vext3 <2,2,4,4>, <2,2,4,4>
- 3771770501U, // <4,2,2,5>: Cost 4 vext3 <2,2,5,4>, <2,2,5,4>
- 3733104570U, // <4,2,2,6>: Cost 4 vext2 <7,0,4,2>, <2,6,3,7>
+ 3759605368U, // <4,2,2,4>: Cost 4 vext3 <0,2,2,4>, <2,2,4,0>
+ 3696609156U, // <4,2,2,5>: Cost 4 vext2 <0,u,4,2>, <2,5,6,7>
+ 3760785040U, // <4,2,2,6>: Cost 4 vext3 <0,4,0,4>, <2,2,6,6>
3668505927U, // <4,2,2,7>: Cost 4 vext1 <7,4,2,2>, <7,4,2,2>
2691909279U, // <4,2,2,u>: Cost 3 vext3 <1,2,3,4>, <2,2,u,3>
2691909286U, // <4,2,3,0>: Cost 3 vext3 <1,2,3,4>, <2,3,0,1>
3764840111U, // <4,2,3,1>: Cost 4 vext3 <1,1,1,4>, <2,3,1,1>
3765651129U, // <4,2,3,2>: Cost 4 vext3 <1,2,3,4>, <2,3,2,2>
2698544836U, // <4,2,3,3>: Cost 3 vext3 <2,3,3,4>, <2,3,3,4>
- 2691909322U, // <4,2,3,4>: Cost 3 vext3 <1,2,3,4>, <2,3,4,1>
+ 2685863630U, // <4,2,3,4>: Cost 3 vext3 <0,2,2,4>, <2,3,4,5>
2698692310U, // <4,2,3,5>: Cost 3 vext3 <2,3,5,4>, <2,3,5,4>
- 3765651165U, // <4,2,3,6>: Cost 4 vext3 <1,2,3,4>, <2,3,6,2>
+ 3772507871U, // <4,2,3,6>: Cost 4 vext3 <2,3,6,4>, <2,3,6,4>
2698839784U, // <4,2,3,7>: Cost 3 vext3 <2,3,7,4>, <2,3,7,4>
2691909358U, // <4,2,3,u>: Cost 3 vext3 <1,2,3,4>, <2,3,u,1>
2564915302U, // <4,2,4,0>: Cost 3 vext1 <2,4,2,4>, LHS
- 3638657782U, // <4,2,4,1>: Cost 4 vext1 <2,4,2,4>, <1,0,3,2>
- 2564916942U, // <4,2,4,2>: Cost 3 vext1 <2,4,2,4>, <2,3,4,5>
- 2934295760U, // <4,2,4,3>: Cost 3 vzipl LHS, <4,4,4,4>
+ 2564916122U, // <4,2,4,1>: Cost 3 vext1 <2,4,2,4>, <1,2,3,4>
+ 2564917004U, // <4,2,4,2>: Cost 3 vext1 <2,4,2,4>, <2,4,2,4>
+ 2699208469U, // <4,2,4,3>: Cost 3 vext3 <2,4,3,4>, <2,4,3,4>
2564918582U, // <4,2,4,4>: Cost 3 vext1 <2,4,2,4>, RHS
- 2629504310U, // <4,2,4,5>: Cost 3 vext2 <2,0,4,2>, RHS
+ 2622868790U, // <4,2,4,5>: Cost 3 vext2 <0,u,4,2>, RHS
2229667632U, // <4,2,4,6>: Cost 3 vrev <2,4,6,4>
3800082229U, // <4,2,4,7>: Cost 4 vext3 <7,0,2,4>, <2,4,7,0>
- 2629504553U, // <4,2,4,u>: Cost 3 vext2 <2,0,4,2>, RHS
- 2588811366U, // <4,2,5,0>: Cost 3 vext1 <6,4,2,5>, LHS
+ 2622869033U, // <4,2,4,u>: Cost 3 vext2 <0,u,4,2>, RHS
+ 2552979558U, // <4,2,5,0>: Cost 3 vext1 <0,4,2,5>, LHS
2558952342U, // <4,2,5,1>: Cost 3 vext1 <1,4,2,5>, <1,2,3,0>
- 2966228278U, // <4,2,5,2>: Cost 3 vzipr <2,2,2,2>, RHS
- 2886518478U, // <4,2,5,3>: Cost 3 vzipl LHS, <2,3,4,5>
- 2588814646U, // <4,2,5,4>: Cost 3 vext1 <6,4,2,5>, RHS
- 3656585112U, // <4,2,5,5>: Cost 4 vext1 <5,4,2,5>, <5,4,2,5>
- 2588815866U, // <4,2,5,6>: Cost 3 vext1 <6,4,2,5>, <6,2,7,3>
- 3662558202U, // <4,2,5,7>: Cost 4 vext1 <6,4,2,5>, <7,0,1,2>
- 2886559438U, // <4,2,5,u>: Cost 3 vzipl LHS, <2,3,4,5>
- 1527021670U, // <4,2,6,0>: Cost 2 vext1 <u,4,2,6>, LHS
- 2600764150U, // <4,2,6,1>: Cost 3 vext1 <u,4,2,6>, <1,0,3,2>
- 3100446006U, // <4,2,6,2>: Cost 3 vtrnr <2,2,2,2>, RHS
- 3100527926U, // <4,2,6,3>: Cost 3 vtrnr <2,2,3,3>, RHS
- 1527024950U, // <4,2,6,4>: Cost 2 vext1 <u,4,2,6>, RHS
+ 2564925032U, // <4,2,5,2>: Cost 3 vext1 <2,4,2,5>, <2,2,2,2>
+ 2967060582U, // <4,2,5,3>: Cost 3 vzipr <2,3,4,5>, LHS
+ 2552982838U, // <4,2,5,4>: Cost 3 vext1 <0,4,2,5>, RHS
+ 3987130190U, // <4,2,5,5>: Cost 4 vzipl RHS, <2,5,0,7>
+ 2913388474U, // <4,2,5,6>: Cost 3 vzipl RHS, <2,6,3,7>
+ 3895577910U, // <4,2,5,7>: Cost 4 vuzpr <0,4,u,2>, RHS
+ 2552985390U, // <4,2,5,u>: Cost 3 vext1 <0,4,2,5>, LHS
+ 1479245926U, // <4,2,6,0>: Cost 2 vext1 <0,4,2,6>, LHS
+ 2552988406U, // <4,2,6,1>: Cost 3 vext1 <0,4,2,6>, <1,0,3,2>
+ 2552989288U, // <4,2,6,2>: Cost 3 vext1 <0,4,2,6>, <2,2,2,2>
+ 2954461286U, // <4,2,6,3>: Cost 3 vzipr <0,2,4,6>, LHS
+ 1479249206U, // <4,2,6,4>: Cost 2 vext1 <0,4,2,6>, RHS
2229610281U, // <4,2,6,5>: Cost 3 vrev <2,4,5,6>
2600767994U, // <4,2,6,6>: Cost 3 vext1 <u,4,2,6>, <6,2,7,3>
2600768506U, // <4,2,6,7>: Cost 3 vext1 <u,4,2,6>, <7,0,1,2>
- 1527027502U, // <4,2,6,u>: Cost 2 vext1 <u,4,2,6>, LHS
+ 1479251758U, // <4,2,6,u>: Cost 2 vext1 <0,4,2,6>, LHS
2659365909U, // <4,2,7,0>: Cost 3 vext2 <7,0,4,2>, <7,0,4,2>
3733771366U, // <4,2,7,1>: Cost 4 vext2 <7,1,4,2>, <7,1,4,2>
3734434999U, // <4,2,7,2>: Cost 4 vext2 <7,2,4,2>, <7,2,4,2>
2701199368U, // <4,2,7,3>: Cost 3 vext3 <2,7,3,4>, <2,7,3,4>
- 3789834253U, // <4,2,7,4>: Cost 4 vext3 <5,2,7,4>, <2,7,4,0>
- 3775088666U, // <4,2,7,5>: Cost 4 vext3 <2,7,5,4>, <2,7,5,4>
- 3737089531U, // <4,2,7,6>: Cost 4 vext2 <7,6,4,2>, <7,6,4,2>
- 3733108332U, // <4,2,7,7>: Cost 4 vext2 <7,0,4,2>, <7,7,7,7>
- 2664674973U, // <4,2,7,u>: Cost 3 vext2 <7,u,4,2>, <7,u,4,2>
- 1527038054U, // <4,2,u,0>: Cost 2 vext1 <u,4,2,u>, LHS
- 2629506862U, // <4,2,u,1>: Cost 3 vext2 <2,0,4,2>, LHS
- 2966228521U, // <4,2,u,2>: Cost 3 vzipr <2,2,2,2>, RHS
- 2886518481U, // <4,2,u,3>: Cost 3 vzipl LHS, <2,3,4,u>
- 1527041334U, // <4,2,u,4>: Cost 2 vext1 <u,4,2,u>, RHS
- 2629507226U, // <4,2,u,5>: Cost 3 vext2 <2,0,4,2>, RHS
- 2588840442U, // <4,2,u,6>: Cost 3 vext1 <6,4,2,u>, <6,2,7,3>
+ 4175774618U, // <4,2,7,4>: Cost 4 vtrnr <2,4,5,7>, <1,2,3,4>
+ 3303360298U, // <4,2,7,5>: Cost 4 vrev <2,4,5,7>
+ 3727136217U, // <4,2,7,6>: Cost 4 vext2 <6,0,4,2>, <7,6,0,4>
+ 3727136364U, // <4,2,7,7>: Cost 4 vext2 <6,0,4,2>, <7,7,7,7>
+ 2659365909U, // <4,2,7,u>: Cost 3 vext2 <7,0,4,2>, <7,0,4,2>
+ 1479262310U, // <4,2,u,0>: Cost 2 vext1 <0,4,2,u>, LHS
+ 2553004790U, // <4,2,u,1>: Cost 3 vext1 <0,4,2,u>, <1,0,3,2>
+ 2553005672U, // <4,2,u,2>: Cost 3 vext1 <0,4,2,u>, <2,2,2,2>
+ 2954477670U, // <4,2,u,3>: Cost 3 vzipr <0,2,4,u>, LHS
+ 1479265590U, // <4,2,u,4>: Cost 2 vext1 <0,4,2,u>, RHS
+ 2622871706U, // <4,2,u,5>: Cost 3 vext2 <0,u,4,2>, RHS
+ 2229700404U, // <4,2,u,6>: Cost 3 vrev <2,4,6,u>
2600784890U, // <4,2,u,7>: Cost 3 vext1 <u,4,2,u>, <7,0,1,2>
- 1527043886U, // <4,2,u,u>: Cost 2 vext1 <u,4,2,u>, LHS
+ 1479268142U, // <4,2,u,u>: Cost 2 vext1 <0,4,2,u>, LHS
3765651595U, // <4,3,0,0>: Cost 4 vext3 <1,2,3,4>, <3,0,0,0>
2691909782U, // <4,3,0,1>: Cost 3 vext3 <1,2,3,4>, <3,0,1,2>
2702452897U, // <4,3,0,2>: Cost 3 vext3 <3,0,2,4>, <3,0,2,4>
- 3765651623U, // <4,3,0,3>: Cost 4 vext3 <1,2,3,4>, <3,0,3,1>
- 3765651632U, // <4,3,0,4>: Cost 4 vext3 <1,2,3,4>, <3,0,4,1>
+ 3693297946U, // <4,3,0,3>: Cost 4 vext2 <0,3,4,3>, <0,3,4,3>
+ 3760711856U, // <4,3,0,4>: Cost 4 vext3 <0,3,u,4>, <3,0,4,1>
2235533820U, // <4,3,0,5>: Cost 3 vrev <3,4,5,0>
- 2235607557U, // <4,3,0,6>: Cost 3 vrev <3,4,6,0>
+ 3309349381U, // <4,3,0,6>: Cost 4 vrev <3,4,6,0>
3668563278U, // <4,3,0,7>: Cost 4 vext1 <7,4,3,0>, <7,4,3,0>
2691909845U, // <4,3,0,u>: Cost 3 vext3 <1,2,3,4>, <3,0,u,2>
2235173328U, // <4,3,1,0>: Cost 3 vrev <3,4,0,1>
3764840678U, // <4,3,1,1>: Cost 4 vext3 <1,1,1,4>, <3,1,1,1>
2630173594U, // <4,3,1,2>: Cost 3 vext2 <2,1,4,3>, <1,2,3,4>
- 3765651706U, // <4,3,1,3>: Cost 4 vext3 <1,2,3,4>, <3,1,3,3>
- 3765651713U, // <4,3,1,4>: Cost 4 vext3 <1,2,3,4>, <3,1,4,1>
+ 2703190267U, // <4,3,1,3>: Cost 3 vext3 <3,1,3,4>, <3,1,3,4>
+ 3760195840U, // <4,3,1,4>: Cost 4 vext3 <0,3,1,4>, <3,1,4,0>
3765651724U, // <4,3,1,5>: Cost 4 vext3 <1,2,3,4>, <3,1,5,3>
3309357574U, // <4,3,1,6>: Cost 4 vrev <3,4,6,1>
- 3792488734U, // <4,3,1,7>: Cost 5 vext3 <5,6,7,4>, <3,1,7,3>
- 2235763224U, // <4,3,1,u>: Cost 3 vrev <3,4,u,1>
- 3696616904U, // <4,3,2,0>: Cost 4 vext2 <0,u,4,3>, <2,0,2,4>
+ 3769633054U, // <4,3,1,7>: Cost 4 vext3 <1,u,3,4>, <3,1,7,3>
+ 2703558952U, // <4,3,1,u>: Cost 3 vext3 <3,1,u,4>, <3,1,u,4>
+ 3626770534U, // <4,3,2,0>: Cost 4 vext1 <0,4,3,2>, LHS
2630174250U, // <4,3,2,1>: Cost 3 vext2 <2,1,4,3>, <2,1,4,3>
3765651777U, // <4,3,2,2>: Cost 4 vext3 <1,2,3,4>, <3,2,2,2>
2703853900U, // <4,3,2,3>: Cost 3 vext3 <3,2,3,4>, <3,2,3,4>
- 2691909972U, // <4,3,2,4>: Cost 3 vext3 <1,2,3,4>, <3,2,4,3>
+ 3626773814U, // <4,3,2,4>: Cost 4 vext1 <0,4,3,2>, RHS
2704001374U, // <4,3,2,5>: Cost 3 vext3 <3,2,5,4>, <3,2,5,4>
- 3777816935U, // <4,3,2,6>: Cost 4 vext3 <3,2,6,4>, <3,2,6,4>
- 3707897872U, // <4,3,2,7>: Cost 4 vext2 <2,7,4,3>, <2,7,4,3>
+ 3765651814U, // <4,3,2,6>: Cost 4 vext3 <1,2,3,4>, <3,2,6,3>
+ 3769633135U, // <4,3,2,7>: Cost 4 vext3 <1,u,3,4>, <3,2,7,3>
2634819681U, // <4,3,2,u>: Cost 3 vext2 <2,u,4,3>, <2,u,4,3>
3765651839U, // <4,3,3,0>: Cost 4 vext3 <1,2,3,4>, <3,3,0,1>
3765651848U, // <4,3,3,1>: Cost 4 vext3 <1,2,3,4>, <3,3,1,1>
- 2636810580U, // <4,3,3,2>: Cost 3 vext2 <3,2,4,3>, <3,2,4,3>
+ 3710552404U, // <4,3,3,2>: Cost 4 vext2 <3,2,4,3>, <3,2,4,3>
2691910044U, // <4,3,3,3>: Cost 3 vext3 <1,2,3,4>, <3,3,3,3>
2704591270U, // <4,3,3,4>: Cost 3 vext3 <3,3,4,4>, <3,3,4,4>
- 3772877232U, // <4,3,3,5>: Cost 4 vext3 <2,4,2,4>, <3,3,5,5>
- 3765651896U, // <4,3,3,6>: Cost 4 vext3 <1,2,3,4>, <3,3,6,4>
- 3668587857U, // <4,3,3,7>: Cost 4 vext1 <7,4,3,3>, <7,4,3,3>
- 2640792378U, // <4,3,3,u>: Cost 3 vext2 <3,u,4,3>, <3,u,4,3>
+ 3769633202U, // <4,3,3,5>: Cost 4 vext3 <1,u,3,4>, <3,3,5,7>
+ 3703917212U, // <4,3,3,6>: Cost 4 vext2 <2,1,4,3>, <3,6,4,7>
+ 3769633220U, // <4,3,3,7>: Cost 4 vext3 <1,u,3,4>, <3,3,7,7>
+ 2691910044U, // <4,3,3,u>: Cost 3 vext3 <1,2,3,4>, <3,3,3,3>
2691910096U, // <4,3,4,0>: Cost 3 vext3 <1,2,3,4>, <3,4,0,1>
2691910106U, // <4,3,4,1>: Cost 3 vext3 <1,2,3,4>, <3,4,1,2>
- 2642783277U, // <4,3,4,2>: Cost 3 vext2 <4,2,4,3>, <4,2,4,3>
+ 2564990741U, // <4,3,4,2>: Cost 3 vext1 <2,4,3,4>, <2,4,3,4>
3765651946U, // <4,3,4,3>: Cost 4 vext3 <1,2,3,4>, <3,4,3,0>
2691910136U, // <4,3,4,4>: Cost 3 vext3 <1,2,3,4>, <3,4,4,5>
- 2691910146U, // <4,3,4,5>: Cost 3 vext3 <1,2,3,4>, <3,4,5,6>
+ 2686454274U, // <4,3,4,5>: Cost 3 vext3 <0,3,1,4>, <3,4,5,6>
2235640329U, // <4,3,4,6>: Cost 3 vrev <3,4,6,4>
3801483792U, // <4,3,4,7>: Cost 4 vext3 <7,2,3,4>, <3,4,7,2>
2691910168U, // <4,3,4,u>: Cost 3 vext3 <1,2,3,4>, <3,4,u,1>
- 2564997222U, // <4,3,5,0>: Cost 3 vext1 <2,4,3,5>, LHS
+ 2559025254U, // <4,3,5,0>: Cost 3 vext1 <1,4,3,5>, LHS
2559026237U, // <4,3,5,1>: Cost 3 vext1 <1,4,3,5>, <1,4,3,5>
2564998862U, // <4,3,5,2>: Cost 3 vext1 <2,4,3,5>, <2,3,4,5>
- 2972945718U, // <4,3,5,3>: Cost 3 vzipr <3,3,3,3>, RHS
- 2565000502U, // <4,3,5,4>: Cost 3 vext1 <2,4,3,5>, RHS
- 4107912982U, // <4,3,5,5>: Cost 4 vtrnl <2,3,4,5>, <2,4,3,5>
- 3638743546U, // <4,3,5,6>: Cost 4 vext1 <2,4,3,5>, <6,2,7,3>
- 3668604243U, // <4,3,5,7>: Cost 4 vext1 <7,4,3,5>, <7,4,3,5>
- 2565003054U, // <4,3,5,u>: Cost 3 vext1 <2,4,3,5>, LHS
- 2235214293U, // <4,3,6,0>: Cost 3 vrev <3,4,0,6>
- 3105017142U, // <4,3,6,1>: Cost 3 vtrnr <3,0,1,2>, RHS
- 2565006962U, // <4,3,6,2>: Cost 3 vext1 <2,4,3,6>, <2,2,3,3>
- 3107163446U, // <4,3,6,3>: Cost 3 vtrnr <3,3,3,3>, RHS
- 2600840502U, // <4,3,6,4>: Cost 3 vext1 <u,4,3,6>, RHS
+ 2570971548U, // <4,3,5,3>: Cost 3 vext1 <3,4,3,5>, <3,3,3,3>
+ 2559028534U, // <4,3,5,4>: Cost 3 vext1 <1,4,3,5>, RHS
+ 4163519477U, // <4,3,5,5>: Cost 4 vtrnr <0,4,1,5>, <1,3,4,5>
+ 3309390346U, // <4,3,5,6>: Cost 4 vrev <3,4,6,5>
+ 2706139747U, // <4,3,5,7>: Cost 3 vext3 <3,5,7,4>, <3,5,7,4>
+ 2559031086U, // <4,3,5,u>: Cost 3 vext1 <1,4,3,5>, LHS
+ 2559033446U, // <4,3,6,0>: Cost 3 vext1 <1,4,3,6>, LHS
+ 2559034430U, // <4,3,6,1>: Cost 3 vext1 <1,4,3,6>, <1,4,3,6>
+ 2565007127U, // <4,3,6,2>: Cost 3 vext1 <2,4,3,6>, <2,4,3,6>
+ 2570979740U, // <4,3,6,3>: Cost 3 vext1 <3,4,3,6>, <3,3,3,3>
+ 2559036726U, // <4,3,6,4>: Cost 3 vext1 <1,4,3,6>, RHS
1161841154U, // <4,3,6,5>: Cost 2 vrev <3,4,5,6>
- 4181765430U, // <4,3,6,6>: Cost 4 vtrnr <3,4,6,0>, RHS
+ 4028203932U, // <4,3,6,6>: Cost 4 vzipr <0,2,4,6>, <1,2,3,6>
2706803380U, // <4,3,6,7>: Cost 3 vext3 <3,6,7,4>, <3,6,7,4>
1162062365U, // <4,3,6,u>: Cost 2 vrev <3,4,u,6>
- 3739751418U, // <4,3,7,0>: Cost 4 vext2 <u,1,4,3>, <7,0,1,2>
- 3733779559U, // <4,3,7,1>: Cost 4 vext2 <7,1,4,3>, <7,1,4,3>
- 3734443192U, // <4,3,7,2>: Cost 4 vext2 <7,2,4,3>, <7,2,4,3>
- 3735106825U, // <4,3,7,3>: Cost 4 vext2 <7,3,4,3>, <7,3,4,3>
- 3796470502U, // <4,3,7,4>: Cost 4 vext3 <6,3,7,4>, <3,7,4,0>
- 3309332995U, // <4,3,7,5>: Cost 4 vrev <3,4,5,7>
- 3737097724U, // <4,3,7,6>: Cost 4 vext2 <7,6,4,3>, <7,6,4,3>
- 3739752044U, // <4,3,7,7>: Cost 4 vext2 <u,1,4,3>, <7,7,7,7>
- 3738424990U, // <4,3,7,u>: Cost 4 vext2 <7,u,4,3>, <7,u,4,3>
- 2565021798U, // <4,3,u,0>: Cost 3 vext1 <2,4,3,u>, LHS
+ 3769633475U, // <4,3,7,0>: Cost 4 vext3 <1,u,3,4>, <3,7,0,1>
+ 3769633488U, // <4,3,7,1>: Cost 4 vext3 <1,u,3,4>, <3,7,1,5>
+ 3638757144U, // <4,3,7,2>: Cost 4 vext1 <2,4,3,7>, <2,4,3,7>
+ 3769633508U, // <4,3,7,3>: Cost 4 vext3 <1,u,3,4>, <3,7,3,7>
+ 3769633515U, // <4,3,7,4>: Cost 4 vext3 <1,u,3,4>, <3,7,4,5>
+ 3769633526U, // <4,3,7,5>: Cost 4 vext3 <1,u,3,4>, <3,7,5,7>
+ 3662647932U, // <4,3,7,6>: Cost 4 vext1 <6,4,3,7>, <6,4,3,7>
+ 3781208837U, // <4,3,7,7>: Cost 4 vext3 <3,7,7,4>, <3,7,7,4>
+ 3769633547U, // <4,3,7,u>: Cost 4 vext3 <1,u,3,4>, <3,7,u,1>
+ 2559049830U, // <4,3,u,0>: Cost 3 vext1 <1,4,3,u>, LHS
2691910430U, // <4,3,u,1>: Cost 3 vext3 <1,2,3,4>, <3,u,1,2>
- 2565023441U, // <4,3,u,2>: Cost 3 vext1 <2,4,3,u>, <2,3,4,u>
- 2972945961U, // <4,3,u,3>: Cost 3 vzipr <3,3,3,3>, RHS
- 2691910458U, // <4,3,u,4>: Cost 3 vext3 <1,2,3,4>, <3,u,4,3>
+ 2565023513U, // <4,3,u,2>: Cost 3 vext1 <2,4,3,u>, <2,4,3,u>
+ 2707835698U, // <4,3,u,3>: Cost 3 vext3 <3,u,3,4>, <3,u,3,4>
+ 2559053110U, // <4,3,u,4>: Cost 3 vext1 <1,4,3,u>, RHS
1161857540U, // <4,3,u,5>: Cost 2 vrev <3,4,5,u>
- 2235607557U, // <4,3,u,6>: Cost 3 vrev <3,4,6,0>
+ 2235673101U, // <4,3,u,6>: Cost 3 vrev <3,4,6,u>
2708130646U, // <4,3,u,7>: Cost 3 vext3 <3,u,7,4>, <3,u,7,4>
1162078751U, // <4,3,u,u>: Cost 2 vrev <3,4,u,u>
- 2977057682U, // <4,4,0,0>: Cost 3 vzipr <4,0,5,1>, <4,0,5,1>
+ 2617573416U, // <4,4,0,0>: Cost 3 vext2 <0,0,4,4>, <0,0,4,4>
1570373734U, // <4,4,0,1>: Cost 2 vext2 <4,4,4,4>, LHS
- 2819411152U, // <4,4,0,2>: Cost 3 vuzpr LHS, <4,4,4,4>
- 3644746227U, // <4,4,0,3>: Cost 4 vext1 <3,4,4,0>, <3,4,4,0>
+ 2779676774U, // <4,4,0,2>: Cost 3 vuzpl <4,6,4,6>, LHS
+ 3760196480U, // <4,4,0,3>: Cost 4 vext3 <0,3,1,4>, <4,0,3,1>
2576977100U, // <4,4,0,4>: Cost 3 vext1 <4,4,4,0>, <4,4,4,0>
- 2691910546U, // <4,4,0,5>: Cost 3 vext3 <1,2,3,4>, <4,0,5,1>
- 2691910556U, // <4,4,0,6>: Cost 3 vext3 <1,2,3,4>, <4,0,6,2>
+ 2718747538U, // <4,4,0,5>: Cost 3 vext3 <5,6,7,4>, <4,0,5,1>
+ 2718747548U, // <4,4,0,6>: Cost 3 vext3 <5,6,7,4>, <4,0,6,2>
3668637015U, // <4,4,0,7>: Cost 4 vext1 <7,4,4,0>, <7,4,4,0>
1570374301U, // <4,4,0,u>: Cost 2 vext2 <4,4,4,4>, LHS
2644116214U, // <4,4,1,0>: Cost 3 vext2 <4,4,4,4>, <1,0,3,2>
2644116276U, // <4,4,1,1>: Cost 3 vext2 <4,4,4,4>, <1,1,1,1>
2691910602U, // <4,4,1,2>: Cost 3 vext3 <1,2,3,4>, <4,1,2,3>
- 3899870416U, // <4,4,1,3>: Cost 4 vuzpr <1,2,3,4>, <4,4,4,4>
+ 2644116440U, // <4,4,1,3>: Cost 3 vext2 <4,4,4,4>, <1,3,1,3>
2711227356U, // <4,4,1,4>: Cost 3 vext3 <4,4,4,4>, <4,1,4,3>
2709310438U, // <4,4,1,5>: Cost 3 vext3 <4,1,5,4>, <4,1,5,4>
- 3764841452U, // <4,4,1,6>: Cost 4 vext3 <1,1,1,4>, <4,1,6,1>
+ 3765652462U, // <4,4,1,6>: Cost 4 vext3 <1,2,3,4>, <4,1,6,3>
3768970231U, // <4,4,1,7>: Cost 4 vext3 <1,7,3,4>, <4,1,7,3>
2695891968U, // <4,4,1,u>: Cost 3 vext3 <1,u,3,4>, <4,1,u,3>
- 3770223624U, // <4,4,2,0>: Cost 4 vext3 <2,0,2,4>, <4,2,0,2>
+ 3703260634U, // <4,4,2,0>: Cost 4 vext2 <2,0,4,4>, <2,0,4,4>
3765652499U, // <4,4,2,1>: Cost 4 vext3 <1,2,3,4>, <4,2,1,4>
- 2630846076U, // <4,4,2,2>: Cost 3 vext2 <2,2,4,4>, <2,2,4,4>
+ 2644117096U, // <4,4,2,2>: Cost 3 vext2 <4,4,4,4>, <2,2,2,2>
2631509709U, // <4,4,2,3>: Cost 3 vext2 <2,3,4,4>, <2,3,4,4>
- 2711227437U, // <4,4,2,4>: Cost 3 vext3 <4,4,4,4>, <4,2,4,3>
- 3765652534U, // <4,4,2,5>: Cost 4 vext3 <1,2,3,4>, <4,2,5,3>
+ 2644117269U, // <4,4,2,4>: Cost 3 vext2 <4,4,4,4>, <2,4,3,4>
+ 3705251698U, // <4,4,2,5>: Cost 4 vext2 <2,3,4,4>, <2,5,4,7>
2710047808U, // <4,4,2,6>: Cost 3 vext3 <4,2,6,4>, <4,2,6,4>
- 3774942280U, // <4,4,2,7>: Cost 4 vext3 <2,7,3,4>, <4,2,7,3>
+ 3783863369U, // <4,4,2,7>: Cost 4 vext3 <4,2,7,4>, <4,2,7,4>
2634827874U, // <4,4,2,u>: Cost 3 vext2 <2,u,4,4>, <2,u,4,4>
2644117654U, // <4,4,3,0>: Cost 3 vext2 <4,4,4,4>, <3,0,1,2>
- 3644769178U, // <4,4,3,1>: Cost 4 vext1 <3,4,4,3>, <1,2,3,4>
- 3765652589U, // <4,4,3,2>: Cost 4 vext3 <1,2,3,4>, <4,3,2,4>
+ 3638797210U, // <4,4,3,1>: Cost 4 vext1 <2,4,4,3>, <1,2,3,4>
+ 3638798082U, // <4,4,3,2>: Cost 4 vext1 <2,4,4,3>, <2,4,1,3>
2637482406U, // <4,4,3,3>: Cost 3 vext2 <3,3,4,4>, <3,3,4,4>
2638146039U, // <4,4,3,4>: Cost 3 vext2 <3,4,4,4>, <3,4,4,4>
- 3778260103U, // <4,4,3,5>: Cost 4 vext3 <3,3,3,4>, <4,3,5,3>
- 3778260112U, // <4,4,3,6>: Cost 4 vext3 <3,3,3,4>, <4,3,6,3>
+ 3913287374U, // <4,4,3,5>: Cost 4 vuzpr <3,4,5,4>, <2,3,4,5>
+ 3765652625U, // <4,4,3,6>: Cost 4 vext3 <1,2,3,4>, <4,3,6,4>
3713878762U, // <4,4,3,7>: Cost 4 vext2 <3,7,4,4>, <3,7,4,4>
2637482406U, // <4,4,3,u>: Cost 3 vext2 <3,3,4,4>, <3,3,4,4>
1503264870U, // <4,4,4,0>: Cost 2 vext1 <4,4,4,4>, LHS
@@ -3303,925 +3303,925 @@ static const unsigned PerfectShuffleTable[6561+1] = {
2571037175U, // <4,4,4,3>: Cost 3 vext1 <3,4,4,4>, <3,4,4,4>
161926454U, // <4,4,4,4>: Cost 1 vdup0 RHS
1570377014U, // <4,4,4,5>: Cost 2 vext2 <4,4,4,4>, RHS
- 2846280912U, // <4,4,4,6>: Cost 3 vuzpr RHS, <4,4,4,4>
+ 2779680054U, // <4,4,4,6>: Cost 3 vuzpl <4,6,4,6>, RHS
2594927963U, // <4,4,4,7>: Cost 3 vext1 <7,4,4,4>, <7,4,4,4>
161926454U, // <4,4,4,u>: Cost 1 vdup0 RHS
2571042918U, // <4,4,5,0>: Cost 3 vext1 <3,4,4,5>, LHS
2571043738U, // <4,4,5,1>: Cost 3 vext1 <3,4,4,5>, <1,2,3,4>
- 3971679950U, // <4,4,5,2>: Cost 4 vzipl <2,0,4,2>, <2,3,4,5>
+ 3638814495U, // <4,4,5,2>: Cost 4 vext1 <2,4,4,5>, <2,4,4,5>
2571045368U, // <4,4,5,3>: Cost 3 vext1 <3,4,4,5>, <3,4,4,5>
2571046198U, // <4,4,5,4>: Cost 3 vext1 <3,4,4,5>, RHS
- 1906756918U, // <4,4,5,5>: Cost 2 vzipr RHS, RHS
+ 1839648054U, // <4,4,5,5>: Cost 2 vzipl RHS, RHS
1618169142U, // <4,4,5,6>: Cost 2 vext3 <1,2,3,4>, RHS
2594936156U, // <4,4,5,7>: Cost 3 vext1 <7,4,4,5>, <7,4,4,5>
1618169160U, // <4,4,5,u>: Cost 2 vext3 <1,2,3,4>, RHS
- 2691910988U, // <4,4,6,0>: Cost 3 vext3 <1,2,3,4>, <4,6,0,2>
- 3764841812U, // <4,4,6,1>: Cost 4 vext3 <1,1,1,4>, <4,6,1,1>
- 2712407392U, // <4,4,6,2>: Cost 3 vext3 <4,6,2,4>, <4,6,2,4>
+ 2553135206U, // <4,4,6,0>: Cost 3 vext1 <0,4,4,6>, LHS
+ 3626877686U, // <4,4,6,1>: Cost 4 vext1 <0,4,4,6>, <1,0,3,2>
+ 2565080782U, // <4,4,6,2>: Cost 3 vext1 <2,4,4,6>, <2,3,4,5>
2571053561U, // <4,4,6,3>: Cost 3 vext1 <3,4,4,6>, <3,4,4,6>
- 3115224374U, // <4,4,6,4>: Cost 3 vtrnr <4,6,4,6>, RHS
- 3111275830U, // <4,4,6,5>: Cost 3 vtrnr <4,0,5,1>, RHS
- 2040974646U, // <4,4,6,6>: Cost 2 vtrnr RHS, RHS
+ 2553138486U, // <4,4,6,4>: Cost 3 vext1 <0,4,4,6>, RHS
+ 2241555675U, // <4,4,6,5>: Cost 3 vrev <4,4,5,6>
+ 1973865782U, // <4,4,6,6>: Cost 2 vtrnl RHS, RHS
2658055029U, // <4,4,6,7>: Cost 3 vext2 <6,7,4,4>, <6,7,4,4>
- 2041122102U, // <4,4,6,u>: Cost 2 vtrnr RHS, RHS
+ 1973865800U, // <4,4,6,u>: Cost 2 vtrnl RHS, RHS
2644120570U, // <4,4,7,0>: Cost 3 vext2 <4,4,4,4>, <7,0,1,2>
- 3934211280U, // <4,4,7,1>: Cost 4 vuzpr <7,0,1,2>, <4,4,4,4>
- 3801484720U, // <4,4,7,2>: Cost 4 vext3 <7,2,3,4>, <4,7,2,3>
+ 3638829978U, // <4,4,7,1>: Cost 4 vext1 <2,4,4,7>, <1,2,3,4>
+ 3638830881U, // <4,4,7,2>: Cost 4 vext1 <2,4,4,7>, <2,4,4,7>
3735115018U, // <4,4,7,3>: Cost 4 vext2 <7,3,4,4>, <7,3,4,4>
2662036827U, // <4,4,7,4>: Cost 3 vext2 <7,4,4,4>, <7,4,4,4>
- 3724498357U, // <4,4,7,5>: Cost 4 vext2 <5,5,4,4>, <7,5,5,4>
+ 2713292236U, // <4,4,7,5>: Cost 3 vext3 <4,7,5,4>, <4,7,5,4>
2713365973U, // <4,4,7,6>: Cost 3 vext3 <4,7,6,4>, <4,7,6,4>
2644121196U, // <4,4,7,7>: Cost 3 vext2 <4,4,4,4>, <7,7,7,7>
2662036827U, // <4,4,7,u>: Cost 3 vext2 <7,4,4,4>, <7,4,4,4>
1503297638U, // <4,4,u,0>: Cost 2 vext1 <4,4,4,u>, LHS
1570379566U, // <4,4,u,1>: Cost 2 vext2 <4,4,4,4>, LHS
- 2867186896U, // <4,4,u,2>: Cost 3 vuzpr LHS, <4,4,4,4>
+ 2779682606U, // <4,4,u,2>: Cost 3 vuzpl <4,6,4,6>, LHS
2571069947U, // <4,4,u,3>: Cost 3 vext1 <3,4,4,u>, <3,4,4,u>
161926454U, // <4,4,u,4>: Cost 1 vdup0 RHS
- 1906757161U, // <4,4,u,5>: Cost 2 vzipr RHS, RHS
+ 1841638710U, // <4,4,u,5>: Cost 2 vzipl RHS, RHS
1618169385U, // <4,4,u,6>: Cost 2 vext3 <1,2,3,4>, RHS
2594960735U, // <4,4,u,7>: Cost 3 vext1 <7,4,4,u>, <7,4,4,u>
161926454U, // <4,4,u,u>: Cost 1 vdup0 RHS
2631516160U, // <4,5,0,0>: Cost 3 vext2 <2,3,4,5>, <0,0,0,0>
1557774438U, // <4,5,0,1>: Cost 2 vext2 <2,3,4,5>, LHS
- 2819451794U, // <4,5,0,2>: Cost 3 vuzpr LHS, <4,0,5,1>
+ 2618908875U, // <4,5,0,2>: Cost 3 vext2 <0,2,4,5>, <0,2,4,5>
2571078140U, // <4,5,0,3>: Cost 3 vext1 <3,4,5,0>, <3,4,5,0>
- 2571078966U, // <4,5,0,4>: Cost 3 vext1 <3,4,5,0>, RHS
- 3644821064U, // <4,5,0,5>: Cost 4 vext1 <3,4,5,0>, <5,0,1,2>
+ 2626871634U, // <4,5,0,4>: Cost 3 vext2 <1,5,4,5>, <0,4,1,5>
+ 3705258414U, // <4,5,0,5>: Cost 4 vext2 <2,3,4,5>, <0,5,2,7>
2594968438U, // <4,5,0,6>: Cost 3 vext1 <7,4,5,0>, <6,7,4,5>
2594968928U, // <4,5,0,7>: Cost 3 vext1 <7,4,5,0>, <7,4,5,0>
1557775005U, // <4,5,0,u>: Cost 2 vext2 <2,3,4,5>, LHS
2631516918U, // <4,5,1,0>: Cost 3 vext2 <2,3,4,5>, <1,0,3,2>
2624217939U, // <4,5,1,1>: Cost 3 vext2 <1,1,4,5>, <1,1,4,5>
2631517078U, // <4,5,1,2>: Cost 3 vext2 <2,3,4,5>, <1,2,3,0>
- 3898526610U, // <4,5,1,3>: Cost 4 vuzpr <1,0,3,2>, <4,0,5,1>
- 3697960010U, // <4,5,1,4>: Cost 4 vext2 <1,1,4,5>, <1,4,5,0>
- 2658059408U, // <4,5,1,5>: Cost 3 vext2 <6,7,4,5>, <1,5,3,7>
- 3980413104U, // <4,5,1,6>: Cost 4 vzipl <3,4,5,6>, <3,0,4,1>
- 2691911376U, // <4,5,1,7>: Cost 3 vext3 <1,2,3,4>, <5,1,7,3>
- 2691911385U, // <4,5,1,u>: Cost 3 vext3 <1,2,3,4>, <5,1,u,3>
- 2631517656U, // <4,5,2,0>: Cost 3 vext2 <2,3,4,5>, <2,0,4,2>
- 3692652056U, // <4,5,2,1>: Cost 4 vext2 <0,2,4,5>, <2,1,2,3>
+ 2821341286U, // <4,5,1,3>: Cost 3 vuzpr <0,4,1,5>, LHS
+ 3895086054U, // <4,5,1,4>: Cost 4 vuzpr <0,4,1,5>, <4,1,5,4>
+ 2626872471U, // <4,5,1,5>: Cost 3 vext2 <1,5,4,5>, <1,5,4,5>
+ 3895083131U, // <4,5,1,6>: Cost 4 vuzpr <0,4,1,5>, <0,1,4,6>
+ 2718748368U, // <4,5,1,7>: Cost 3 vext3 <5,6,7,4>, <5,1,7,3>
+ 2821341291U, // <4,5,1,u>: Cost 3 vuzpr <0,4,1,5>, LHS
+ 2571092070U, // <4,5,2,0>: Cost 3 vext1 <3,4,5,2>, LHS
+ 3699287585U, // <4,5,2,1>: Cost 4 vext2 <1,3,4,5>, <2,1,3,3>
2630854269U, // <4,5,2,2>: Cost 3 vext2 <2,2,4,5>, <2,2,4,5>
1557776078U, // <4,5,2,3>: Cost 2 vext2 <2,3,4,5>, <2,3,4,5>
- 2631517944U, // <4,5,2,4>: Cost 3 vext2 <2,3,4,5>, <2,4,0,2>
- 3644837448U, // <4,5,2,5>: Cost 4 vext1 <3,4,5,2>, <5,0,1,2>
- 2658060218U, // <4,5,2,6>: Cost 3 vext2 <6,7,4,5>, <2,6,3,7>
- 2716094242U, // <4,5,2,7>: Cost 3 vext3 <5,2,7,4>, <5,2,7,4>
+ 2631517974U, // <4,5,2,4>: Cost 3 vext2 <2,3,4,5>, <2,4,3,5>
+ 3692652384U, // <4,5,2,5>: Cost 4 vext2 <0,2,4,5>, <2,5,2,7>
+ 2631518138U, // <4,5,2,6>: Cost 3 vext2 <2,3,4,5>, <2,6,3,7>
+ 4164013366U, // <4,5,2,7>: Cost 4 vtrnr <0,4,u,2>, RHS
1561094243U, // <4,5,2,u>: Cost 2 vext2 <2,u,4,5>, <2,u,4,5>
2631518358U, // <4,5,3,0>: Cost 3 vext2 <2,3,4,5>, <3,0,1,2>
- 2631518476U, // <4,5,3,1>: Cost 3 vext2 <2,3,4,5>, <3,1,5,3>
+ 3895084710U, // <4,5,3,1>: Cost 4 vuzpr <0,4,1,5>, <2,3,0,1>
2631518540U, // <4,5,3,2>: Cost 3 vext2 <2,3,4,5>, <3,2,3,4>
2631518620U, // <4,5,3,3>: Cost 3 vext2 <2,3,4,5>, <3,3,3,3>
2631518716U, // <4,5,3,4>: Cost 3 vext2 <2,3,4,5>, <3,4,5,0>
- 3705260578U, // <4,5,3,5>: Cost 4 vext2 <2,3,4,5>, <3,5,0,2>
+ 2631518784U, // <4,5,3,5>: Cost 3 vext2 <2,3,4,5>, <3,5,3,5>
2658060980U, // <4,5,3,6>: Cost 3 vext2 <6,7,4,5>, <3,6,7,4>
2640145131U, // <4,5,3,7>: Cost 3 vext2 <3,7,4,5>, <3,7,4,5>
2631519006U, // <4,5,3,u>: Cost 3 vext2 <2,3,4,5>, <3,u,1,2>
- 2631519122U, // <4,5,4,0>: Cost 3 vext2 <2,3,4,5>, <4,0,5,1>
- 3697961955U, // <4,5,4,1>: Cost 4 vext2 <1,1,4,5>, <4,1,5,1>
- 2631519286U, // <4,5,4,2>: Cost 3 vext2 <2,3,4,5>, <4,2,5,3>
+ 2571108454U, // <4,5,4,0>: Cost 3 vext1 <3,4,5,4>, LHS
+ 3632907342U, // <4,5,4,1>: Cost 4 vext1 <1,4,5,4>, <1,4,5,4>
+ 2571110094U, // <4,5,4,2>: Cost 3 vext1 <3,4,5,4>, <2,3,4,5>
2571110912U, // <4,5,4,3>: Cost 3 vext1 <3,4,5,4>, <3,4,5,4>
2571111734U, // <4,5,4,4>: Cost 3 vext1 <3,4,5,4>, RHS
1557777718U, // <4,5,4,5>: Cost 2 vext2 <2,3,4,5>, RHS
- 2631519564U, // <4,5,4,6>: Cost 3 vext2 <2,3,4,5>, <4,6,0,2>
- 3047607504U, // <4,5,4,7>: Cost 3 vtrnl RHS, <4,4,4,4>
+ 2645454195U, // <4,5,4,6>: Cost 3 vext2 <4,6,4,5>, <4,6,4,5>
+ 2718748614U, // <4,5,4,7>: Cost 3 vext3 <5,6,7,4>, <5,4,7,6>
1557777961U, // <4,5,4,u>: Cost 2 vext2 <2,3,4,5>, RHS
- 1527234662U, // <4,5,5,0>: Cost 2 vext1 <u,4,5,5>, LHS
- 2631519952U, // <4,5,5,1>: Cost 3 vext2 <2,3,4,5>, <5,1,7,3>
- 2577090254U, // <4,5,5,2>: Cost 3 vext1 <4,4,5,5>, <2,3,4,5>
- 2600978582U, // <4,5,5,3>: Cost 3 vext1 <u,4,5,5>, <3,0,1,2>
- 1527237942U, // <4,5,5,4>: Cost 2 vext1 <u,4,5,5>, RHS
+ 1503346790U, // <4,5,5,0>: Cost 2 vext1 <4,4,5,5>, LHS
+ 2913398480U, // <4,5,5,1>: Cost 3 vzipl RHS, <5,1,7,3>
+ 2631519998U, // <4,5,5,2>: Cost 3 vext2 <2,3,4,5>, <5,2,3,4>
+ 2577090710U, // <4,5,5,3>: Cost 3 vext1 <4,4,5,5>, <3,0,1,2>
+ 1503349978U, // <4,5,5,4>: Cost 2 vext1 <4,4,5,5>, <4,4,5,5>
2631520260U, // <4,5,5,5>: Cost 3 vext2 <2,3,4,5>, <5,5,5,5>
- 2651426892U, // <4,5,5,6>: Cost 3 vext2 <5,6,4,5>, <5,6,4,5>
- 3047604562U, // <4,5,5,7>: Cost 3 vtrnl RHS, <0,4,1,5>
- 1527240494U, // <4,5,5,u>: Cost 2 vext1 <u,4,5,5>, LHS
+ 2913390690U, // <4,5,5,6>: Cost 3 vzipl RHS, <5,6,7,0>
+ 2821344566U, // <4,5,5,7>: Cost 3 vuzpr <0,4,1,5>, RHS
+ 1503352622U, // <4,5,5,u>: Cost 2 vext1 <4,4,5,5>, LHS
1497383014U, // <4,5,6,0>: Cost 2 vext1 <3,4,5,6>, LHS
2559181904U, // <4,5,6,1>: Cost 3 vext1 <1,4,5,6>, <1,4,5,6>
- 2631520762U, // <4,5,6,2>: Cost 3 vext2 <2,3,4,5>, <6,2,7,3>
+ 2565154601U, // <4,5,6,2>: Cost 3 vext1 <2,4,5,6>, <2,4,5,6>
1497385474U, // <4,5,6,3>: Cost 2 vext1 <3,4,5,6>, <3,4,5,6>
1497386294U, // <4,5,6,4>: Cost 2 vext1 <3,4,5,6>, RHS
- 2571128528U, // <4,5,6,5>: Cost 3 vext1 <3,4,5,6>, <5,1,7,3>
- 2571129338U, // <4,5,6,6>: Cost 3 vext1 <3,4,5,6>, <6,2,7,3>
+ 3047608324U, // <4,5,6,5>: Cost 3 vtrnl RHS, <5,5,5,5>
+ 2571129656U, // <4,5,6,6>: Cost 3 vext1 <3,4,5,6>, <6,6,6,6>
27705344U, // <4,5,6,7>: Cost 0 copy RHS
27705344U, // <4,5,6,u>: Cost 0 copy RHS
- 2658063354U, // <4,5,7,0>: Cost 3 vext2 <6,7,4,5>, <7,0,1,2>
- 3731805251U, // <4,5,7,1>: Cost 4 vext2 <6,7,4,5>, <7,1,0,3>
- 2631521456U, // <4,5,7,2>: Cost 3 vext2 <2,3,4,5>, <7,2,3,4>
+ 2565161062U, // <4,5,7,0>: Cost 3 vext1 <2,4,5,7>, LHS
+ 2565161882U, // <4,5,7,1>: Cost 3 vext1 <2,4,5,7>, <1,2,3,4>
+ 2565162794U, // <4,5,7,2>: Cost 3 vext1 <2,4,5,7>, <2,4,5,7>
2661381387U, // <4,5,7,3>: Cost 3 vext2 <7,3,4,5>, <7,3,4,5>
- 2658063712U, // <4,5,7,4>: Cost 3 vext2 <6,7,4,5>, <7,4,5,0>
- 3656822480U, // <4,5,7,5>: Cost 4 vext1 <5,4,5,7>, <5,1,7,3>
- 2658063896U, // <4,5,7,6>: Cost 3 vext2 <6,7,4,5>, <7,6,7,4>
+ 2565164342U, // <4,5,7,4>: Cost 3 vext1 <2,4,5,7>, RHS
+ 2718748840U, // <4,5,7,5>: Cost 3 vext3 <5,6,7,4>, <5,7,5,7>
+ 2718748846U, // <4,5,7,6>: Cost 3 vext3 <5,6,7,4>, <5,7,6,4>
2719412407U, // <4,5,7,7>: Cost 3 vext3 <5,7,7,4>, <5,7,7,4>
- 2719486144U, // <4,5,7,u>: Cost 3 vext3 <5,7,u,4>, <5,7,u,4>
+ 2565166894U, // <4,5,7,u>: Cost 3 vext1 <2,4,5,7>, LHS
1497399398U, // <4,5,u,0>: Cost 2 vext1 <3,4,5,u>, LHS
1557780270U, // <4,5,u,1>: Cost 2 vext2 <2,3,4,5>, LHS
- 2631522156U, // <4,5,u,2>: Cost 3 vext2 <2,3,4,5>, <u,2,0,2>
+ 2631522181U, // <4,5,u,2>: Cost 3 vext2 <2,3,4,5>, <u,2,3,0>
1497401860U, // <4,5,u,3>: Cost 2 vext1 <3,4,5,u>, <3,4,5,u>
1497402678U, // <4,5,u,4>: Cost 2 vext1 <3,4,5,u>, RHS
1557780634U, // <4,5,u,5>: Cost 2 vext2 <2,3,4,5>, RHS
- 2631522480U, // <4,5,u,6>: Cost 3 vext2 <2,3,4,5>, <u,6,0,2>
+ 2631522512U, // <4,5,u,6>: Cost 3 vext2 <2,3,4,5>, <u,6,3,7>
27705344U, // <4,5,u,7>: Cost 0 copy RHS
27705344U, // <4,5,u,u>: Cost 0 copy RHS
- 2819919158U, // <4,6,0,0>: Cost 3 vuzpr <0,2,0,2>, RHS
- 1571717222U, // <4,6,0,1>: Cost 2 vext2 <4,6,4,6>, LHS
- 1745669430U, // <4,6,0,2>: Cost 2 vuzpr LHS, RHS
- 2571151877U, // <4,6,0,3>: Cost 3 vext1 <3,4,6,0>, <3,4,6,0>
- 2571152694U, // <4,6,0,4>: Cost 3 vext1 <3,4,6,0>, RHS
- 3644894928U, // <4,6,0,5>: Cost 4 vext1 <3,4,6,0>, <5,1,7,3>
+ 2618916864U, // <4,6,0,0>: Cost 3 vext2 <0,2,4,6>, <0,0,0,0>
+ 1545175142U, // <4,6,0,1>: Cost 2 vext2 <0,2,4,6>, LHS
+ 1545175244U, // <4,6,0,2>: Cost 2 vext2 <0,2,4,6>, <0,2,4,6>
+ 3692658940U, // <4,6,0,3>: Cost 4 vext2 <0,2,4,6>, <0,3,1,0>
+ 2618917202U, // <4,6,0,4>: Cost 3 vext2 <0,2,4,6>, <0,4,1,5>
+ 3852910806U, // <4,6,0,5>: Cost 4 vuzpl RHS, <0,2,5,7>
2253525648U, // <4,6,0,6>: Cost 3 vrev <6,4,6,0>
- 2595042665U, // <4,6,0,7>: Cost 3 vext1 <7,4,6,0>, <7,4,6,0>
- 1746111798U, // <4,6,0,u>: Cost 2 vuzpr LHS, RHS
- 2645459702U, // <4,6,1,0>: Cost 3 vext2 <4,6,4,6>, <1,0,3,2>
- 2825293110U, // <4,6,1,1>: Cost 3 vuzpr <1,1,1,1>, RHS
- 2645459862U, // <4,6,1,2>: Cost 3 vext2 <4,6,4,6>, <1,2,3,0>
- 2824785206U, // <4,6,1,3>: Cost 3 vuzpr <1,0,3,2>, RHS
- 3899288886U, // <4,6,1,4>: Cost 4 vuzpr <1,1,4,5>, RHS
- 2645460112U, // <4,6,1,5>: Cost 3 vext2 <4,6,4,6>, <1,5,3,7>
- 2645460192U, // <4,6,1,6>: Cost 3 vext2 <4,6,4,6>, <1,6,3,6>
- 3764842919U, // <4,6,1,7>: Cost 4 vext3 <1,1,1,4>, <6,1,7,1>
- 2825153846U, // <4,6,1,u>: Cost 3 vuzpr <1,0,u,2>, RHS
- 2832518454U, // <4,6,2,0>: Cost 3 vuzpr <2,3,0,1>, RHS
+ 4040764726U, // <4,6,0,7>: Cost 4 vzipr <2,3,4,0>, RHS
+ 1545175709U, // <4,6,0,u>: Cost 2 vext2 <0,2,4,6>, LHS
+ 2618917622U, // <4,6,1,0>: Cost 3 vext2 <0,2,4,6>, <1,0,3,2>
+ 2618917684U, // <4,6,1,1>: Cost 3 vext2 <0,2,4,6>, <1,1,1,1>
+ 2618917782U, // <4,6,1,2>: Cost 3 vext2 <0,2,4,6>, <1,2,3,0>
+ 2618917848U, // <4,6,1,3>: Cost 3 vext2 <0,2,4,6>, <1,3,1,3>
+ 3692659773U, // <4,6,1,4>: Cost 4 vext2 <0,2,4,6>, <1,4,3,5>
+ 2618918032U, // <4,6,1,5>: Cost 3 vext2 <0,2,4,6>, <1,5,3,7>
+ 3692659937U, // <4,6,1,6>: Cost 4 vext2 <0,2,4,6>, <1,6,3,7>
+ 4032146742U, // <4,6,1,7>: Cost 4 vzipr <0,u,4,1>, RHS
+ 2618918253U, // <4,6,1,u>: Cost 3 vext2 <0,2,4,6>, <1,u,1,3>
+ 2618918380U, // <4,6,2,0>: Cost 3 vext2 <0,2,4,6>, <2,0,6,4>
2618918460U, // <4,6,2,1>: Cost 3 vext2 <0,2,4,6>, <2,1,6,3>
- 2832010550U, // <4,6,2,2>: Cost 3 vuzpr <2,2,2,2>, RHS
- 2832092470U, // <4,6,2,3>: Cost 3 vuzpr <2,2,3,3>, RHS
- 2832846134U, // <4,6,2,4>: Cost 3 vuzpr <2,3,4,5>, RHS
+ 2618918504U, // <4,6,2,2>: Cost 3 vext2 <0,2,4,6>, <2,2,2,2>
+ 2618918566U, // <4,6,2,3>: Cost 3 vext2 <0,2,4,6>, <2,3,0,1>
+ 2618918679U, // <4,6,2,4>: Cost 3 vext2 <0,2,4,6>, <2,4,3,6>
2618918788U, // <4,6,2,5>: Cost 3 vext2 <0,2,4,6>, <2,5,6,7>
- 2645460922U, // <4,6,2,6>: Cost 3 vext2 <4,6,4,6>, <2,6,3,7>
- 2691912186U, // <4,6,2,7>: Cost 3 vext3 <1,2,3,4>, <6,2,7,3>
- 2691912195U, // <4,6,2,u>: Cost 3 vext3 <1,2,3,4>, <6,2,u,3>
- 2645461142U, // <4,6,3,0>: Cost 3 vext2 <4,6,4,6>, <3,0,1,2>
- 2836581686U, // <4,6,3,1>: Cost 3 vuzpr <3,0,1,2>, RHS
- 3705268583U, // <4,6,3,2>: Cost 4 vext2 <2,3,4,6>, <3,2,6,4>
- 2838727990U, // <4,6,3,3>: Cost 3 vuzpr <3,3,3,3>, RHS
- 2645461506U, // <4,6,3,4>: Cost 3 vext2 <4,6,4,6>, <3,4,5,6>
- 2839563574U, // <4,6,3,5>: Cost 3 vuzpr <3,4,5,6>, RHS
- 3913329974U, // <4,6,3,6>: Cost 4 vuzpr <3,4,6,0>, RHS
+ 2618918842U, // <4,6,2,6>: Cost 3 vext2 <0,2,4,6>, <2,6,3,7>
+ 2718749178U, // <4,6,2,7>: Cost 3 vext3 <5,6,7,4>, <6,2,7,3>
+ 2618918971U, // <4,6,2,u>: Cost 3 vext2 <0,2,4,6>, <2,u,0,1>
+ 2618919062U, // <4,6,3,0>: Cost 3 vext2 <0,2,4,6>, <3,0,1,2>
+ 2636171526U, // <4,6,3,1>: Cost 3 vext2 <3,1,4,6>, <3,1,4,6>
+ 3692661057U, // <4,6,3,2>: Cost 4 vext2 <0,2,4,6>, <3,2,2,2>
+ 2618919324U, // <4,6,3,3>: Cost 3 vext2 <0,2,4,6>, <3,3,3,3>
+ 2618919426U, // <4,6,3,4>: Cost 3 vext2 <0,2,4,6>, <3,4,5,6>
+ 2638826058U, // <4,6,3,5>: Cost 3 vext2 <3,5,4,6>, <3,5,4,6>
+ 3913303030U, // <4,6,3,6>: Cost 4 vuzpr <3,4,5,6>, <1,3,4,6>
2722730572U, // <4,6,3,7>: Cost 3 vext3 <6,3,7,4>, <6,3,7,4>
- 2837097782U, // <4,6,3,u>: Cost 3 vuzpr <3,0,u,2>, RHS
- 2846461238U, // <4,6,4,0>: Cost 3 vuzpr <4,6,0,2>, RHS
- 3916295478U, // <4,6,4,1>: Cost 4 vuzpr <4,0,1,2>, RHS
+ 2618919710U, // <4,6,3,u>: Cost 3 vext2 <0,2,4,6>, <3,u,1,2>
+ 2565210214U, // <4,6,4,0>: Cost 3 vext1 <2,4,6,4>, LHS
+ 2718749286U, // <4,6,4,1>: Cost 3 vext3 <5,6,7,4>, <6,4,1,3>
2565211952U, // <4,6,4,2>: Cost 3 vext1 <2,4,6,4>, <2,4,6,4>
2571184649U, // <4,6,4,3>: Cost 3 vext1 <3,4,6,4>, <3,4,6,4>
- 2645462224U, // <4,6,4,4>: Cost 3 vext2 <4,6,4,6>, <4,4,4,4>
- 1571720502U, // <4,6,4,5>: Cost 2 vext2 <4,6,4,6>, RHS
- 1772539190U, // <4,6,4,6>: Cost 2 vuzpr RHS, RHS
- 2913389776U, // <4,6,4,7>: Cost 3 vzipl RHS, <4,4,4,4>
- 1772686646U, // <4,6,4,u>: Cost 2 vuzpr RHS, RHS
- 2577162342U, // <4,6,5,0>: Cost 3 vext1 <4,4,6,5>, LHS
+ 2565213494U, // <4,6,4,4>: Cost 3 vext1 <2,4,6,4>, RHS
+ 1545178422U, // <4,6,4,5>: Cost 2 vext2 <0,2,4,6>, RHS
+ 1705430326U, // <4,6,4,6>: Cost 2 vuzpl RHS, RHS
+ 2595075437U, // <4,6,4,7>: Cost 3 vext1 <7,4,6,4>, <7,4,6,4>
+ 1545178665U, // <4,6,4,u>: Cost 2 vext2 <0,2,4,6>, RHS
+ 2565218406U, // <4,6,5,0>: Cost 3 vext1 <2,4,6,5>, LHS
2645462736U, // <4,6,5,1>: Cost 3 vext2 <4,6,4,6>, <5,1,7,3>
- 2990492982U, // <4,6,5,2>: Cost 3 vzipr <6,2,7,3>, RHS
- 3650906262U, // <4,6,5,3>: Cost 4 vext1 <4,4,6,5>, <3,0,1,2>
- 2577165202U, // <4,6,5,4>: Cost 3 vext1 <4,4,6,5>, <4,0,5,1>
- 2645463044U, // <4,6,5,5>: Cost 3 vext2 <4,6,4,6>, <5,5,5,5>
- 2645463138U, // <4,6,5,6>: Cost 3 vext2 <4,6,4,6>, <5,6,7,0>
- 2913388238U, // <4,6,5,7>: Cost 3 vzipl RHS, <2,3,4,5>
- 2577168174U, // <4,6,5,u>: Cost 3 vext1 <4,4,6,5>, LHS
- 1527316582U, // <4,6,6,0>: Cost 2 vext1 <u,4,6,6>, LHS
- 2601059062U, // <4,6,6,1>: Cost 3 vext1 <u,4,6,6>, <1,0,3,2>
+ 2913399290U, // <4,6,5,2>: Cost 3 vzipl RHS, <6,2,7,3>
+ 3913305394U, // <4,6,5,3>: Cost 4 vuzpr <3,4,5,6>, <4,5,6,3>
+ 2645462982U, // <4,6,5,4>: Cost 3 vext2 <4,6,4,6>, <5,4,7,6>
+ 2779172868U, // <4,6,5,5>: Cost 3 vuzpl RHS, <5,5,5,5>
+ 2913391416U, // <4,6,5,6>: Cost 3 vzipl RHS, <6,6,6,6>
+ 2821426486U, // <4,6,5,7>: Cost 3 vuzpr <0,4,2,6>, RHS
+ 2821426487U, // <4,6,5,u>: Cost 3 vuzpr <0,4,2,6>, RHS
+ 1503428710U, // <4,6,6,0>: Cost 2 vext1 <4,4,6,6>, LHS
+ 2577171190U, // <4,6,6,1>: Cost 3 vext1 <4,4,6,6>, <1,0,3,2>
2645463546U, // <4,6,6,2>: Cost 3 vext2 <4,6,4,6>, <6,2,7,3>
- 2577172994U, // <4,6,6,3>: Cost 3 vext1 <4,4,6,6>, <3,4,5,6>
- 1527319862U, // <4,6,6,4>: Cost 2 vext1 <u,4,6,6>, RHS
- 2645463784U, // <4,6,6,5>: Cost 3 vext2 <4,6,4,6>, <6,5,6,7>
- 2645463864U, // <4,6,6,6>: Cost 3 vext2 <4,6,4,6>, <6,6,6,6>
- 2913386700U, // <4,6,6,7>: Cost 3 vzipl RHS, <0,2,4,6>
- 1527322414U, // <4,6,6,u>: Cost 2 vext1 <u,4,6,6>, LHS
+ 2577172630U, // <4,6,6,3>: Cost 3 vext1 <4,4,6,6>, <3,0,1,2>
+ 1503431908U, // <4,6,6,4>: Cost 2 vext1 <4,4,6,6>, <4,4,6,6>
+ 2253501069U, // <4,6,6,5>: Cost 3 vrev <6,4,5,6>
+ 2618921784U, // <4,6,6,6>: Cost 3 vext2 <0,2,4,6>, <6,6,6,6>
+ 2954464566U, // <4,6,6,7>: Cost 3 vzipr <0,2,4,6>, RHS
+ 1503434542U, // <4,6,6,u>: Cost 2 vext1 <4,4,6,6>, LHS
2645464058U, // <4,6,7,0>: Cost 3 vext2 <4,6,4,6>, <7,0,1,2>
- 2860469558U, // <4,6,7,1>: Cost 3 vuzpr <7,0,1,2>, RHS
- 3719206053U, // <4,6,7,2>: Cost 4 vext2 <4,6,4,6>, <7,2,2,2>
+ 2779173882U, // <4,6,7,1>: Cost 3 vuzpl RHS, <7,0,1,2>
+ 3638978355U, // <4,6,7,2>: Cost 4 vext1 <2,4,6,7>, <2,4,6,7>
2725090156U, // <4,6,7,3>: Cost 3 vext3 <6,7,3,4>, <6,7,3,4>
2645464422U, // <4,6,7,4>: Cost 3 vext2 <4,6,4,6>, <7,4,5,6>
- 2725237630U, // <4,6,7,5>: Cost 3 vext3 <6,7,5,4>, <6,7,5,4>
- 3719206382U, // <4,6,7,6>: Cost 4 vext2 <4,6,4,6>, <7,6,2,7>
- 2645464684U, // <4,6,7,7>: Cost 3 vext2 <4,6,4,6>, <7,7,7,7>
- 2645464706U, // <4,6,7,u>: Cost 3 vext2 <4,6,4,6>, <7,u,1,2>
- 1527332966U, // <4,6,u,0>: Cost 2 vext1 <u,4,6,u>, LHS
- 1571723054U, // <4,6,u,1>: Cost 2 vext2 <4,6,4,6>, LHS
- 1793445174U, // <4,6,u,2>: Cost 2 vuzpr LHS, RHS
- 2645465020U, // <4,6,u,3>: Cost 3 vext2 <4,6,4,6>, <u,3,0,1>
- 1527336246U, // <4,6,u,4>: Cost 2 vext1 <u,4,6,u>, RHS
- 1571723418U, // <4,6,u,5>: Cost 2 vext2 <4,6,4,6>, RHS
- 1796427062U, // <4,6,u,6>: Cost 2 vuzpr RHS, RHS
- 2691912672U, // <4,6,u,7>: Cost 3 vext3 <1,2,3,4>, <6,u,7,3>
- 1571723621U, // <4,6,u,u>: Cost 2 vext2 <4,6,4,6>, LHS
- 3719208960U, // <4,7,0,0>: Cost 4 vext2 <4,6,4,7>, <0,0,0,0>
- 2645467238U, // <4,7,0,1>: Cost 3 vext2 <4,6,4,7>, LHS
+ 2779174246U, // <4,6,7,5>: Cost 3 vuzpl RHS, <7,4,5,6>
+ 3852915914U, // <4,6,7,6>: Cost 4 vuzpl RHS, <7,2,6,3>
+ 2779174508U, // <4,6,7,7>: Cost 3 vuzpl RHS, <7,7,7,7>
+ 2779173945U, // <4,6,7,u>: Cost 3 vuzpl RHS, <7,0,u,2>
+ 1503445094U, // <4,6,u,0>: Cost 2 vext1 <4,4,6,u>, LHS
+ 1545180974U, // <4,6,u,1>: Cost 2 vext2 <0,2,4,6>, LHS
+ 1705432878U, // <4,6,u,2>: Cost 2 vuzpl RHS, LHS
+ 2618922940U, // <4,6,u,3>: Cost 3 vext2 <0,2,4,6>, <u,3,0,1>
+ 1503448294U, // <4,6,u,4>: Cost 2 vext1 <4,4,6,u>, <4,4,6,u>
+ 1545181338U, // <4,6,u,5>: Cost 2 vext2 <0,2,4,6>, RHS
+ 1705433242U, // <4,6,u,6>: Cost 2 vuzpl RHS, RHS
+ 2954480950U, // <4,6,u,7>: Cost 3 vzipr <0,2,4,u>, RHS
+ 1545181541U, // <4,6,u,u>: Cost 2 vext2 <0,2,4,6>, LHS
+ 3706601472U, // <4,7,0,0>: Cost 4 vext2 <2,5,4,7>, <0,0,0,0>
+ 2632859750U, // <4,7,0,1>: Cost 3 vext2 <2,5,4,7>, LHS
2726343685U, // <4,7,0,2>: Cost 3 vext3 <7,0,2,4>, <7,0,2,4>
- 3656911356U, // <4,7,0,3>: Cost 4 vext1 <5,4,7,0>, <3,4,5,0>
- 3719209298U, // <4,7,0,4>: Cost 4 vext2 <4,6,4,7>, <0,4,1,5>
+ 3701293312U, // <4,7,0,3>: Cost 4 vext2 <1,6,4,7>, <0,3,1,4>
+ 3706601810U, // <4,7,0,4>: Cost 4 vext2 <2,5,4,7>, <0,4,1,5>
2259424608U, // <4,7,0,5>: Cost 3 vrev <7,4,5,0>
- 2259498345U, // <4,7,0,6>: Cost 3 vrev <7,4,6,0>
+ 3695321617U, // <4,7,0,6>: Cost 4 vext2 <0,6,4,7>, <0,6,4,7>
3800454194U, // <4,7,0,7>: Cost 4 vext3 <7,0,7,4>, <7,0,7,4>
- 2645467805U, // <4,7,0,u>: Cost 3 vext2 <4,6,4,7>, LHS
+ 2632860317U, // <4,7,0,u>: Cost 3 vext2 <2,5,4,7>, LHS
2259064116U, // <4,7,1,0>: Cost 3 vrev <7,4,0,1>
- 3719209780U, // <4,7,1,1>: Cost 4 vext2 <4,6,4,7>, <1,1,1,1>
- 2669355975U, // <4,7,1,2>: Cost 3 vext2 <u,6,4,7>, <1,2,u,4>
- 3656919504U, // <4,7,1,3>: Cost 4 vext1 <5,4,7,1>, <3,4,0,1>
+ 3700630324U, // <4,7,1,1>: Cost 4 vext2 <1,5,4,7>, <1,1,1,1>
+ 2632860570U, // <4,7,1,2>: Cost 3 vext2 <2,5,4,7>, <1,2,3,4>
+ 3769635936U, // <4,7,1,3>: Cost 4 vext3 <1,u,3,4>, <7,1,3,5>
3656920374U, // <4,7,1,4>: Cost 4 vext1 <5,4,7,1>, RHS
- 3719210128U, // <4,7,1,5>: Cost 4 vext2 <4,6,4,7>, <1,5,3,7>
- 3662893722U, // <4,7,1,6>: Cost 4 vext1 <6,4,7,1>, <6,4,7,1>
- 3807458432U, // <4,7,1,7>: Cost 4 vext3 <u,2,3,4>, <7,1,7,1>
+ 3700630681U, // <4,7,1,5>: Cost 4 vext2 <1,5,4,7>, <1,5,4,7>
+ 3701294314U, // <4,7,1,6>: Cost 4 vext2 <1,6,4,7>, <1,6,4,7>
+ 3793818754U, // <4,7,1,7>: Cost 4 vext3 <5,u,7,4>, <7,1,7,3>
2259654012U, // <4,7,1,u>: Cost 3 vrev <7,4,u,1>
3656925286U, // <4,7,2,0>: Cost 4 vext1 <5,4,7,2>, LHS
- 3801339038U, // <4,7,2,1>: Cost 4 vext3 <7,2,1,4>, <7,2,1,4>
- 3719210600U, // <4,7,2,2>: Cost 4 vext2 <4,6,4,7>, <2,2,2,2>
+ 3706603050U, // <4,7,2,1>: Cost 4 vext2 <2,5,4,7>, <2,1,4,3>
+ 3706603112U, // <4,7,2,2>: Cost 4 vext2 <2,5,4,7>, <2,2,2,2>
2727744688U, // <4,7,2,3>: Cost 3 vext3 <7,2,3,4>, <7,2,3,4>
- 3656928566U, // <4,7,2,4>: Cost 4 vext1 <5,4,7,2>, RHS
+ 3705939745U, // <4,7,2,4>: Cost 4 vext2 <2,4,4,7>, <2,4,4,7>
2632861554U, // <4,7,2,5>: Cost 3 vext2 <2,5,4,7>, <2,5,4,7>
- 3719210938U, // <4,7,2,6>: Cost 4 vext2 <4,6,4,7>, <2,6,3,7>
- 3807458515U, // <4,7,2,7>: Cost 4 vext3 <u,2,3,4>, <7,2,7,3>
- 2728113373U, // <4,7,2,u>: Cost 3 vext3 <7,2,u,4>, <7,2,u,4>
- 3719211158U, // <4,7,3,0>: Cost 4 vext2 <4,6,4,7>, <3,0,1,2>
+ 3706603450U, // <4,7,2,6>: Cost 4 vext2 <2,5,4,7>, <2,6,3,7>
+ 3792491731U, // <4,7,2,7>: Cost 4 vext3 <5,6,7,4>, <7,2,7,3>
+ 2634852453U, // <4,7,2,u>: Cost 3 vext2 <2,u,4,7>, <2,u,4,7>
+ 3706603670U, // <4,7,3,0>: Cost 4 vext2 <2,5,4,7>, <3,0,1,2>
3662906266U, // <4,7,3,1>: Cost 4 vext1 <6,4,7,3>, <1,2,3,4>
- 3662906922U, // <4,7,3,2>: Cost 4 vext1 <6,4,7,3>, <2,1,4,3>
- 3719211420U, // <4,7,3,3>: Cost 4 vext2 <4,6,4,7>, <3,3,3,3>
- 3719211522U, // <4,7,3,4>: Cost 4 vext2 <4,6,4,7>, <3,4,5,6>
+ 3725183326U, // <4,7,3,2>: Cost 4 vext2 <5,6,4,7>, <3,2,5,4>
+ 3706603932U, // <4,7,3,3>: Cost 4 vext2 <2,5,4,7>, <3,3,3,3>
+ 3701295618U, // <4,7,3,4>: Cost 4 vext2 <1,6,4,7>, <3,4,5,6>
2638834251U, // <4,7,3,5>: Cost 3 vext2 <3,5,4,7>, <3,5,4,7>
2639497884U, // <4,7,3,6>: Cost 3 vext2 <3,6,4,7>, <3,6,4,7>
3802445093U, // <4,7,3,7>: Cost 4 vext3 <7,3,7,4>, <7,3,7,4>
2640825150U, // <4,7,3,u>: Cost 3 vext2 <3,u,4,7>, <3,u,4,7>
2718750004U, // <4,7,4,0>: Cost 3 vext3 <5,6,7,4>, <7,4,0,1>
- 3792491836U, // <4,7,4,1>: Cost 4 vext3 <5,6,7,4>, <7,4,1,0>
- 3656943310U, // <4,7,4,2>: Cost 4 vext1 <5,4,7,4>, <2,3,4,5>
- 3990490320U, // <4,7,4,3>: Cost 4 vzipl <5,1,7,3>, <4,4,4,4>
- 2645470416U, // <4,7,4,4>: Cost 3 vext2 <4,6,4,7>, <4,4,4,4>
- 2645470518U, // <4,7,4,5>: Cost 3 vext2 <4,6,4,7>, RHS
- 2645470581U, // <4,7,4,6>: Cost 3 vext2 <4,6,4,7>, <4,6,4,7>
- 3719212444U, // <4,7,4,7>: Cost 4 vext2 <4,6,4,7>, <4,7,0,1>
- 2645470761U, // <4,7,4,u>: Cost 3 vext2 <4,6,4,7>, RHS
- 2589180006U, // <4,7,5,0>: Cost 3 vext1 <6,4,7,5>, LHS
- 3719212752U, // <4,7,5,1>: Cost 4 vext2 <4,6,4,7>, <5,1,7,3>
+ 3706604490U, // <4,7,4,1>: Cost 4 vext2 <2,5,4,7>, <4,1,2,3>
+ 3656943474U, // <4,7,4,2>: Cost 4 vext1 <5,4,7,4>, <2,5,4,7>
+ 3779884371U, // <4,7,4,3>: Cost 4 vext3 <3,5,7,4>, <7,4,3,5>
+ 2259383643U, // <4,7,4,4>: Cost 3 vrev <7,4,4,4>
+ 2632863030U, // <4,7,4,5>: Cost 3 vext2 <2,5,4,7>, RHS
+ 2259531117U, // <4,7,4,6>: Cost 3 vrev <7,4,6,4>
+ 3907340074U, // <4,7,4,7>: Cost 4 vuzpr <2,4,5,7>, <2,4,5,7>
+ 2632863273U, // <4,7,4,u>: Cost 3 vext2 <2,5,4,7>, RHS
+ 2913391610U, // <4,7,5,0>: Cost 3 vzipl RHS, <7,0,1,2>
+ 3645006848U, // <4,7,5,1>: Cost 4 vext1 <3,4,7,5>, <1,3,5,7>
2589181646U, // <4,7,5,2>: Cost 3 vext1 <6,4,7,5>, <2,3,4,5>
- 3990488782U, // <4,7,5,3>: Cost 4 vzipl <5,1,7,3>, <2,3,4,5>
- 2589183286U, // <4,7,5,4>: Cost 3 vext1 <6,4,7,5>, RHS
- 3719213060U, // <4,7,5,5>: Cost 4 vext2 <4,6,4,7>, <5,5,5,5>
+ 3645008403U, // <4,7,5,3>: Cost 4 vext1 <3,4,7,5>, <3,4,7,5>
+ 2913391974U, // <4,7,5,4>: Cost 3 vzipl RHS, <7,4,5,6>
+ 2583211973U, // <4,7,5,5>: Cost 3 vext1 <5,4,7,5>, <5,4,7,5>
2589184670U, // <4,7,5,6>: Cost 3 vext1 <6,4,7,5>, <6,4,7,5>
- 2595157367U, // <4,7,5,7>: Cost 3 vext1 <7,4,7,5>, <7,4,7,5>
- 2589185838U, // <4,7,5,u>: Cost 3 vext1 <6,4,7,5>, LHS
+ 2913392236U, // <4,7,5,7>: Cost 3 vzipl RHS, <7,7,7,7>
+ 2913392258U, // <4,7,5,u>: Cost 3 vzipl RHS, <7,u,1,2>
1509474406U, // <4,7,6,0>: Cost 2 vext1 <5,4,7,6>, LHS
- 2583216886U, // <4,7,6,1>: Cost 3 vext1 <5,4,7,6>, <1,0,3,2>
+ 3047609338U, // <4,7,6,1>: Cost 3 vtrnl RHS, <7,0,1,2>
2583217768U, // <4,7,6,2>: Cost 3 vext1 <5,4,7,6>, <2,2,2,2>
2583218326U, // <4,7,6,3>: Cost 3 vext1 <5,4,7,6>, <3,0,1,2>
1509477686U, // <4,7,6,4>: Cost 2 vext1 <5,4,7,6>, RHS
1509478342U, // <4,7,6,5>: Cost 2 vext1 <5,4,7,6>, <5,4,7,6>
2583220730U, // <4,7,6,6>: Cost 3 vext1 <5,4,7,6>, <6,2,7,3>
- 2583221242U, // <4,7,6,7>: Cost 3 vext1 <5,4,7,6>, <7,0,1,2>
+ 3047609964U, // <4,7,6,7>: Cost 3 vtrnl RHS, <7,7,7,7>
1509480238U, // <4,7,6,u>: Cost 2 vext1 <5,4,7,6>, LHS
- 3719214074U, // <4,7,7,0>: Cost 4 vext2 <4,6,4,7>, <7,0,1,2>
- 3934211466U, // <4,7,7,1>: Cost 4 vuzpr <7,0,1,2>, <4,6,7,1>
- 3705279664U, // <4,7,7,2>: Cost 4 vext2 <2,3,4,7>, <7,2,3,4>
+ 3650994278U, // <4,7,7,0>: Cost 4 vext1 <4,4,7,7>, LHS
+ 3650995098U, // <4,7,7,1>: Cost 4 vext1 <4,4,7,7>, <1,2,3,4>
+ 3650996010U, // <4,7,7,2>: Cost 4 vext1 <4,4,7,7>, <2,4,5,7>
3804804677U, // <4,7,7,3>: Cost 4 vext3 <7,7,3,4>, <7,7,3,4>
- 3719214427U, // <4,7,7,4>: Cost 4 vext2 <4,6,4,7>, <7,4,4,4>
+ 3650997486U, // <4,7,7,4>: Cost 4 vext1 <4,4,7,7>, <4,4,7,7>
2662725039U, // <4,7,7,5>: Cost 3 vext2 <7,5,4,7>, <7,5,4,7>
- 3992507094U, // <4,7,7,6>: Cost 4 vzipl <5,4,7,6>, <6,5,4,7>
+ 3662942880U, // <4,7,7,6>: Cost 4 vext1 <6,4,7,7>, <6,4,7,7>
2718750316U, // <4,7,7,7>: Cost 3 vext3 <5,6,7,4>, <7,7,7,7>
2664715938U, // <4,7,7,u>: Cost 3 vext2 <7,u,4,7>, <7,u,4,7>
1509490790U, // <4,7,u,0>: Cost 2 vext1 <5,4,7,u>, LHS
- 2645473070U, // <4,7,u,1>: Cost 3 vext2 <4,6,4,7>, LHS
+ 2632865582U, // <4,7,u,1>: Cost 3 vext2 <2,5,4,7>, LHS
2583234152U, // <4,7,u,2>: Cost 3 vext1 <5,4,7,u>, <2,2,2,2>
2583234710U, // <4,7,u,3>: Cost 3 vext1 <5,4,7,u>, <3,0,1,2>
1509494070U, // <4,7,u,4>: Cost 2 vext1 <5,4,7,u>, RHS
1509494728U, // <4,7,u,5>: Cost 2 vext1 <5,4,7,u>, <5,4,7,u>
2583237114U, // <4,7,u,6>: Cost 3 vext1 <5,4,7,u>, <6,2,7,3>
- 2583237626U, // <4,7,u,7>: Cost 3 vext1 <5,4,7,u>, <7,0,1,2>
+ 3047757420U, // <4,7,u,7>: Cost 3 vtrnl RHS, <7,7,7,7>
1509496622U, // <4,7,u,u>: Cost 2 vext1 <5,4,7,u>, LHS
- 2819919176U, // <4,u,0,0>: Cost 3 vuzpr <0,2,0,2>, RHS
- 1557799014U, // <4,u,0,1>: Cost 2 vext2 <2,3,4,u>, LHS
- 1745669448U, // <4,u,0,2>: Cost 2 vuzpr LHS, RHS
+ 2618933248U, // <4,u,0,0>: Cost 3 vext2 <0,2,4,u>, <0,0,0,0>
+ 1545191526U, // <4,u,0,1>: Cost 2 vext2 <0,2,4,u>, LHS
+ 1545191630U, // <4,u,0,2>: Cost 2 vext2 <0,2,4,u>, <0,2,4,u>
2691913445U, // <4,u,0,3>: Cost 3 vext3 <1,2,3,4>, <u,0,3,2>
- 2571300150U, // <4,u,0,4>: Cost 3 vext1 <3,4,u,0>, RHS
- 2691913462U, // <4,u,0,5>: Cost 3 vext3 <1,2,3,4>, <u,0,5,1>
- 2691913472U, // <4,u,0,6>: Cost 3 vext3 <1,2,3,4>, <u,0,6,2>
+ 2618933586U, // <4,u,0,4>: Cost 3 vext2 <0,2,4,u>, <0,4,1,5>
+ 2265397305U, // <4,u,0,5>: Cost 3 vrev <u,4,5,0>
+ 2595189625U, // <4,u,0,6>: Cost 3 vext1 <7,4,u,0>, <6,7,4,u>
2595190139U, // <4,u,0,7>: Cost 3 vext1 <7,4,u,0>, <7,4,u,0>
- 1746111816U, // <4,u,0,u>: Cost 2 vuzpr LHS, RHS
- 2631541494U, // <4,u,1,0>: Cost 3 vext2 <2,3,4,u>, <1,0,3,2>
- 2825293128U, // <4,u,1,1>: Cost 3 vuzpr <1,1,1,1>, RHS
+ 1545192093U, // <4,u,0,u>: Cost 2 vext2 <0,2,4,u>, LHS
+ 2618934006U, // <4,u,1,0>: Cost 3 vext2 <0,2,4,u>, <1,0,3,2>
+ 2618934068U, // <4,u,1,1>: Cost 3 vext2 <0,2,4,u>, <1,1,1,1>
1618171694U, // <4,u,1,2>: Cost 2 vext3 <1,2,3,4>, LHS
- 2824785224U, // <4,u,1,3>: Cost 3 vuzpr <1,0,3,2>, RHS
+ 2618934232U, // <4,u,1,3>: Cost 3 vext2 <0,2,4,u>, <1,3,1,3>
2695894848U, // <4,u,1,4>: Cost 3 vext3 <1,u,3,4>, <u,1,4,3>
- 2645476496U, // <4,u,1,5>: Cost 3 vext2 <4,6,4,u>, <1,5,3,7>
- 2645460192U, // <4,u,1,6>: Cost 3 vext2 <4,6,4,6>, <1,6,3,6>
- 2691913563U, // <4,u,1,7>: Cost 3 vext3 <1,2,3,4>, <u,1,7,3>
+ 2618934416U, // <4,u,1,5>: Cost 3 vext2 <0,2,4,u>, <1,5,3,7>
+ 3692676321U, // <4,u,1,6>: Cost 4 vext2 <0,2,4,u>, <1,6,3,7>
+ 2718750555U, // <4,u,1,7>: Cost 3 vext3 <5,6,7,4>, <u,1,7,3>
1618171748U, // <4,u,1,u>: Cost 2 vext3 <1,2,3,4>, LHS
- 2691913580U, // <4,u,2,0>: Cost 3 vext3 <1,2,3,4>, <u,2,0,2>
+ 2553397350U, // <4,u,2,0>: Cost 3 vext1 <0,4,u,2>, LHS
2630215215U, // <4,u,2,1>: Cost 3 vext2 <2,1,4,u>, <2,1,4,u>
- 2832010568U, // <4,u,2,2>: Cost 3 vuzpr <2,2,2,2>, RHS
+ 2618934888U, // <4,u,2,2>: Cost 3 vext2 <0,2,4,u>, <2,2,2,2>
1557800657U, // <4,u,2,3>: Cost 2 vext2 <2,3,4,u>, <2,3,4,u>
- 2692282257U, // <4,u,2,4>: Cost 3 vext3 <1,2,u,4>, <u,2,4,3>
+ 2618935065U, // <4,u,2,4>: Cost 3 vext2 <0,2,4,u>, <2,4,3,u>
2733864859U, // <4,u,2,5>: Cost 3 vext3 <u,2,5,4>, <u,2,5,4>
- 2645477306U, // <4,u,2,6>: Cost 3 vext2 <4,6,4,u>, <2,6,3,7>
- 2691913644U, // <4,u,2,7>: Cost 3 vext3 <1,2,3,4>, <u,2,7,3>
+ 2618935226U, // <4,u,2,6>: Cost 3 vext2 <0,2,4,u>, <2,6,3,7>
+ 2718750636U, // <4,u,2,7>: Cost 3 vext3 <5,6,7,4>, <u,2,7,3>
1561118822U, // <4,u,2,u>: Cost 2 vext2 <2,u,4,u>, <2,u,4,u>
- 2691913660U, // <4,u,3,0>: Cost 3 vext3 <1,2,3,4>, <u,3,0,1>
- 2836581704U, // <4,u,3,1>: Cost 3 vuzpr <3,0,1,2>, RHS
+ 2618935446U, // <4,u,3,0>: Cost 3 vext2 <0,2,4,u>, <3,0,1,2>
+ 2779318422U, // <4,u,3,1>: Cost 3 vuzpl RHS, <3,0,1,2>
2636851545U, // <4,u,3,2>: Cost 3 vext2 <3,2,4,u>, <3,2,4,u>
- 2631543196U, // <4,u,3,3>: Cost 3 vext2 <2,3,4,u>, <3,3,3,3>
- 2691913700U, // <4,u,3,4>: Cost 3 vext3 <1,2,3,4>, <u,3,4,5>
- 2839563592U, // <4,u,3,5>: Cost 3 vuzpr <3,4,5,6>, RHS
- 2658060980U, // <4,u,3,6>: Cost 3 vext2 <6,7,4,5>, <3,6,7,4>
- 2734675966U, // <4,u,3,7>: Cost 3 vext3 <u,3,7,4>, <u,3,7,4>
- 2691913732U, // <4,u,3,u>: Cost 3 vext3 <1,2,3,4>, <u,3,u,1>
+ 2618935708U, // <4,u,3,3>: Cost 3 vext2 <0,2,4,u>, <3,3,3,3>
+ 2618935810U, // <4,u,3,4>: Cost 3 vext2 <0,2,4,u>, <3,4,5,6>
+ 2691913711U, // <4,u,3,5>: Cost 3 vext3 <1,2,3,4>, <u,3,5,7>
+ 2588725862U, // <4,u,3,6>: Cost 3 vext1 <6,4,1,3>, <6,4,1,3>
+ 2640169710U, // <4,u,3,7>: Cost 3 vext2 <3,7,4,u>, <3,7,4,u>
+ 2618936094U, // <4,u,3,u>: Cost 3 vext2 <0,2,4,u>, <3,u,1,2>
1503559782U, // <4,u,4,0>: Cost 2 vext1 <4,4,u,4>, LHS
2692282391U, // <4,u,4,1>: Cost 3 vext3 <1,2,u,4>, <u,4,1,2>
- 2631543889U, // <4,u,4,2>: Cost 3 vext2 <2,3,4,u>, <4,2,u,3>
+ 2565359426U, // <4,u,4,2>: Cost 3 vext1 <2,4,u,4>, <2,4,u,4>
2571332123U, // <4,u,4,3>: Cost 3 vext1 <3,4,u,4>, <3,4,u,4>
161926454U, // <4,u,4,4>: Cost 1 vdup0 RHS
- 1557802294U, // <4,u,4,5>: Cost 2 vext2 <2,3,4,u>, RHS
- 1772539208U, // <4,u,4,6>: Cost 2 vuzpr RHS, RHS
- 2913537232U, // <4,u,4,7>: Cost 3 vzipl RHS, <4,4,4,4>
+ 1545194806U, // <4,u,4,5>: Cost 2 vext2 <0,2,4,u>, RHS
+ 1705577782U, // <4,u,4,6>: Cost 2 vuzpl RHS, RHS
+ 2718750801U, // <4,u,4,7>: Cost 3 vext3 <5,6,7,4>, <u,4,7,6>
161926454U, // <4,u,4,u>: Cost 1 vdup0 RHS
- 1526939750U, // <4,u,5,0>: Cost 2 vext1 <u,4,1,5>, LHS
- 1927662902U, // <4,u,5,1>: Cost 2 vzipr LHS, RHS
- 2589255374U, // <4,u,5,2>: Cost 3 vext1 <6,4,u,5>, <2,3,4,5>
- 2886960846U, // <4,u,5,3>: Cost 3 vzipl LHS, <2,3,4,5>
- 1526943030U, // <4,u,5,4>: Cost 2 vext1 <u,4,1,5>, RHS
- 1930644790U, // <4,u,5,5>: Cost 2 vzipr RHS, RHS
+ 1479164006U, // <4,u,5,0>: Cost 2 vext1 <0,4,1,5>, LHS
+ 1839650606U, // <4,u,5,1>: Cost 2 vzipl RHS, LHS
+ 2565367502U, // <4,u,5,2>: Cost 3 vext1 <2,4,u,5>, <2,3,4,5>
+ 3089777309U, // <4,u,5,3>: Cost 3 vtrnr <0,4,1,5>, LHS
+ 1479167286U, // <4,u,5,4>: Cost 2 vext1 <0,4,1,5>, RHS
+ 1839650970U, // <4,u,5,5>: Cost 2 vzipl RHS, RHS
1618172058U, // <4,u,5,6>: Cost 2 vext3 <1,2,3,4>, RHS
- 2913535694U, // <4,u,5,7>: Cost 3 vzipl RHS, <2,3,4,5>
+ 3089780265U, // <4,u,5,7>: Cost 3 vtrnr <0,4,1,5>, RHS
1618172076U, // <4,u,5,u>: Cost 2 vext3 <1,2,3,4>, RHS
- 1497604198U, // <4,u,6,0>: Cost 2 vext1 <3,4,u,6>, LHS
- 2559403115U, // <4,u,6,1>: Cost 3 vext1 <1,4,u,6>, <1,4,u,6>
- 2061880630U, // <4,u,6,2>: Cost 2 vtrnr LHS, RHS
+ 1479688294U, // <4,u,6,0>: Cost 2 vext1 <0,4,u,6>, LHS
+ 2553430774U, // <4,u,6,1>: Cost 3 vext1 <0,4,u,6>, <1,0,3,2>
+ 1973868334U, // <4,u,6,2>: Cost 2 vtrnl RHS, LHS
1497606685U, // <4,u,6,3>: Cost 2 vext1 <3,4,u,6>, <3,4,u,6>
- 1497607478U, // <4,u,6,4>: Cost 2 vext1 <3,4,u,6>, RHS
+ 1479691574U, // <4,u,6,4>: Cost 2 vext1 <0,4,u,6>, RHS
1509552079U, // <4,u,6,5>: Cost 2 vext1 <5,4,u,6>, <5,4,u,6>
- 2064862518U, // <4,u,6,6>: Cost 2 vtrnr RHS, RHS
+ 1973868698U, // <4,u,6,6>: Cost 2 vtrnl RHS, RHS
27705344U, // <4,u,6,7>: Cost 0 copy RHS
27705344U, // <4,u,6,u>: Cost 0 copy RHS
- 2645480442U, // <4,u,7,0>: Cost 3 vext2 <4,6,4,u>, <7,0,1,2>
- 2860469576U, // <4,u,7,1>: Cost 3 vuzpr <7,0,1,2>, RHS
- 2631521456U, // <4,u,7,2>: Cost 3 vext2 <2,3,4,5>, <7,2,3,4>
+ 2565382246U, // <4,u,7,0>: Cost 3 vext1 <2,4,u,7>, LHS
+ 2565383066U, // <4,u,7,1>: Cost 3 vext1 <2,4,u,7>, <1,2,3,4>
+ 2565384005U, // <4,u,7,2>: Cost 3 vext1 <2,4,u,7>, <2,4,u,7>
2661405966U, // <4,u,7,3>: Cost 3 vext2 <7,3,4,u>, <7,3,4,u>
- 2645480806U, // <4,u,7,4>: Cost 3 vext2 <4,6,4,u>, <7,4,5,6>
- 2863451464U, // <4,u,7,5>: Cost 3 vuzpr <7,4,5,6>, RHS
- 2663396865U, // <4,u,7,6>: Cost 3 vext2 <7,6,4,u>, <7,6,4,u>
- 2645481068U, // <4,u,7,7>: Cost 3 vext2 <4,6,4,u>, <7,7,7,7>
- 2645481090U, // <4,u,7,u>: Cost 3 vext2 <4,6,4,u>, <7,u,1,2>
- 1497620582U, // <4,u,u,0>: Cost 2 vext1 <3,4,u,u>, LHS
- 1557804846U, // <4,u,u,1>: Cost 2 vext2 <2,3,4,u>, LHS
+ 2565385526U, // <4,u,7,4>: Cost 3 vext1 <2,4,u,7>, RHS
+ 2779321702U, // <4,u,7,5>: Cost 3 vuzpl RHS, <7,4,5,6>
+ 2589274793U, // <4,u,7,6>: Cost 3 vext1 <6,4,u,7>, <6,4,u,7>
+ 2779321964U, // <4,u,7,7>: Cost 3 vuzpl RHS, <7,7,7,7>
+ 2565388078U, // <4,u,7,u>: Cost 3 vext1 <2,4,u,7>, LHS
+ 1479704678U, // <4,u,u,0>: Cost 2 vext1 <0,4,u,u>, LHS
+ 1545197358U, // <4,u,u,1>: Cost 2 vext2 <0,2,4,u>, LHS
1618172261U, // <4,u,u,2>: Cost 2 vext3 <1,2,3,4>, LHS
1497623071U, // <4,u,u,3>: Cost 2 vext1 <3,4,u,u>, <3,4,u,u>
161926454U, // <4,u,u,4>: Cost 1 vdup0 RHS
- 1557805210U, // <4,u,u,5>: Cost 2 vext2 <2,3,4,u>, RHS
+ 1545197722U, // <4,u,u,5>: Cost 2 vext2 <0,2,4,u>, RHS
1618172301U, // <4,u,u,6>: Cost 2 vext3 <1,2,3,4>, RHS
27705344U, // <4,u,u,7>: Cost 0 copy RHS
27705344U, // <4,u,u,u>: Cost 0 copy RHS
- 2698625024U, // <5,0,0,0>: Cost 3 vext3 <2,3,4,5>, <0,0,0,0>
- 2698625034U, // <5,0,0,1>: Cost 3 vext3 <2,3,4,5>, <0,0,1,1>
- 2698625044U, // <5,0,0,2>: Cost 3 vext3 <2,3,4,5>, <0,0,2,2>
- 3715907845U, // <5,0,0,3>: Cost 4 vext2 <4,1,5,0>, <0,3,2,0>
- 2684690473U, // <5,0,0,4>: Cost 3 vext3 <0,0,4,5>, <0,0,4,5>
- 3733160348U, // <5,0,0,5>: Cost 4 vext2 <7,0,5,0>, <0,5,0,7>
+ 2687123456U, // <5,0,0,0>: Cost 3 vext3 <0,4,1,5>, <0,0,0,0>
+ 2687123466U, // <5,0,0,1>: Cost 3 vext3 <0,4,1,5>, <0,0,1,1>
+ 2687123476U, // <5,0,0,2>: Cost 3 vext3 <0,4,1,5>, <0,0,2,2>
+ 3710599434U, // <5,0,0,3>: Cost 4 vext2 <3,2,5,0>, <0,3,2,5>
+ 2642166098U, // <5,0,0,4>: Cost 3 vext2 <4,1,5,0>, <0,4,1,5>
+ 3657060306U, // <5,0,0,5>: Cost 4 vext1 <5,5,0,0>, <5,5,0,0>
3292094923U, // <5,0,0,6>: Cost 4 vrev <0,5,6,0>
- 3998630419U, // <5,0,0,7>: Cost 5 vzipl <6,5,0,7>, <0,6,5,0>
- 2698625097U, // <5,0,0,u>: Cost 3 vext3 <2,3,4,5>, <0,0,u,1>
- 2642166518U, // <5,0,1,0>: Cost 3 vext2 <4,1,5,0>, <1,0,3,2>
- 2953670352U, // <5,0,1,1>: Cost 3 vzipr LHS, <5,1,7,3>
- 1624883302U, // <5,0,1,2>: Cost 2 vext3 <2,3,4,5>, LHS
- 3645123105U, // <5,0,1,3>: Cost 4 vext1 <3,5,0,1>, <3,5,0,1>
- 2577353978U, // <5,0,1,4>: Cost 3 vext1 <4,5,0,1>, <4,5,0,1>
+ 3669005700U, // <5,0,0,7>: Cost 4 vext1 <7,5,0,0>, <7,5,0,0>
+ 2687123530U, // <5,0,0,u>: Cost 3 vext3 <0,4,1,5>, <0,0,u,2>
+ 2559434854U, // <5,0,1,0>: Cost 3 vext1 <1,5,0,1>, LHS
+ 2559435887U, // <5,0,1,1>: Cost 3 vext1 <1,5,0,1>, <1,5,0,1>
+ 1613381734U, // <5,0,1,2>: Cost 2 vext3 <0,4,1,5>, LHS
+ 3698656256U, // <5,0,1,3>: Cost 4 vext2 <1,2,5,0>, <1,3,5,7>
+ 2559438134U, // <5,0,1,4>: Cost 3 vext1 <1,5,0,1>, RHS
2583326675U, // <5,0,1,5>: Cost 3 vext1 <5,5,0,1>, <5,5,0,1>
- 3651097082U, // <5,0,1,6>: Cost 4 vext1 <4,5,0,1>, <6,2,7,3>
- 3669013893U, // <5,0,1,7>: Cost 4 vext1 <7,5,0,1>, <7,5,0,1>
- 1624883356U, // <5,0,1,u>: Cost 2 vext3 <2,3,4,5>, LHS
+ 3715908851U, // <5,0,1,6>: Cost 4 vext2 <4,1,5,0>, <1,6,5,7>
+ 3657069562U, // <5,0,1,7>: Cost 4 vext1 <5,5,0,1>, <7,0,1,2>
+ 1613381788U, // <5,0,1,u>: Cost 2 vext3 <0,4,1,5>, LHS
2686017700U, // <5,0,2,0>: Cost 3 vext3 <0,2,4,5>, <0,2,0,2>
- 4027371288U, // <5,0,2,1>: Cost 4 vzipr LHS, <5,2,6,3>
- 3759759543U, // <5,0,2,2>: Cost 4 vext3 <0,2,4,5>, <0,2,2,3>
- 2638186190U, // <5,0,2,3>: Cost 3 vext2 <3,4,5,0>, <2,3,4,5>
+ 2685796528U, // <5,0,2,1>: Cost 3 vext3 <0,2,1,5>, <0,2,1,5>
+ 2698625208U, // <5,0,2,2>: Cost 3 vext3 <2,3,4,5>, <0,2,2,4>
+ 2685944002U, // <5,0,2,3>: Cost 3 vext3 <0,2,3,5>, <0,2,3,5>
2686017739U, // <5,0,2,4>: Cost 3 vext3 <0,2,4,5>, <0,2,4,5>
- 3639160528U, // <5,0,2,5>: Cost 4 vext1 <2,5,0,2>, <5,1,7,3>
- 3645133089U, // <5,0,2,6>: Cost 4 vext1 <3,5,0,2>, <6,0,1,2>
- 2686238950U, // <5,0,2,7>: Cost 3 vext3 <0,2,7,5>, <0,2,7,5>
+ 2686091476U, // <5,0,2,5>: Cost 3 vext3 <0,2,5,5>, <0,2,5,5>
+ 2725167324U, // <5,0,2,6>: Cost 3 vext3 <6,7,4,5>, <0,2,6,4>
+ 2595280230U, // <5,0,2,7>: Cost 3 vext1 <7,5,0,2>, <7,4,5,6>
2686312687U, // <5,0,2,u>: Cost 3 vext3 <0,2,u,5>, <0,2,u,5>
- 3776348407U, // <5,0,3,0>: Cost 4 vext3 <3,0,4,5>, <0,3,0,4>
- 3711928588U, // <5,0,3,1>: Cost 4 vext2 <3,4,5,0>, <3,1,5,3>
- 3772367109U, // <5,0,3,2>: Cost 4 vext3 <2,3,4,5>, <0,3,2,0>
- 3711265195U, // <5,0,3,3>: Cost 4 vext2 <3,3,5,0>, <3,3,5,0>
+ 3760128248U, // <5,0,3,0>: Cost 4 vext3 <0,3,0,5>, <0,3,0,5>
+ 3759685888U, // <5,0,3,1>: Cost 4 vext3 <0,2,3,5>, <0,3,1,4>
+ 2686533898U, // <5,0,3,2>: Cost 3 vext3 <0,3,2,5>, <0,3,2,5>
+ 3760349459U, // <5,0,3,3>: Cost 4 vext3 <0,3,3,5>, <0,3,3,5>
2638187004U, // <5,0,3,4>: Cost 3 vext2 <3,4,5,0>, <3,4,5,0>
3776348452U, // <5,0,3,5>: Cost 4 vext3 <3,0,4,5>, <0,3,5,4>
3713256094U, // <5,0,3,6>: Cost 4 vext2 <3,6,5,0>, <3,6,5,0>
- 3713919727U, // <5,0,3,7>: Cost 4 vext2 <3,7,5,0>, <3,7,5,0>
- 2640841536U, // <5,0,3,u>: Cost 3 vext2 <3,u,5,0>, <3,u,5,0>
+ 3914064896U, // <5,0,3,7>: Cost 4 vuzpr <3,5,7,0>, <1,3,5,7>
+ 2686976320U, // <5,0,3,u>: Cost 3 vext3 <0,3,u,5>, <0,3,u,5>
2559459430U, // <5,0,4,0>: Cost 3 vext1 <1,5,0,4>, LHS
1613381970U, // <5,0,4,1>: Cost 2 vext3 <0,4,1,5>, <0,4,1,5>
- 2717942108U, // <5,0,4,2>: Cost 3 vext3 <5,5,5,5>, <0,4,2,6>
- 3711929436U, // <5,0,4,3>: Cost 4 vext2 <3,4,5,0>, <4,3,0,5>
+ 2687123804U, // <5,0,4,2>: Cost 3 vext3 <0,4,1,5>, <0,4,2,6>
+ 3761013092U, // <5,0,4,3>: Cost 4 vext3 <0,4,3,5>, <0,4,3,5>
2559462710U, // <5,0,4,4>: Cost 3 vext1 <1,5,0,4>, RHS
2638187830U, // <5,0,4,5>: Cost 3 vext2 <3,4,5,0>, RHS
- 3711929676U, // <5,0,4,6>: Cost 4 vext2 <3,4,5,0>, <4,6,0,2>
- 3735817632U, // <5,0,4,7>: Cost 4 vext2 <7,4,5,0>, <4,7,0,5>
- 1613898129U, // <5,0,4,u>: Cost 2 vext3 <0,4,u,5>, <0,4,u,5>
- 3705294407U, // <5,0,5,0>: Cost 4 vext2 <2,3,5,0>, <5,0,1,1>
- 2953629700U, // <5,0,5,1>: Cost 3 vzipr LHS, <5,5,5,5>
- 3087847428U, // <5,0,5,2>: Cost 3 vtrnr LHS, <5,5,5,5>
- 3778707892U, // <5,0,5,3>: Cost 4 vext3 <3,4,0,5>, <0,5,3,4>
- 3778707897U, // <5,0,5,4>: Cost 4 vext3 <3,4,0,5>, <0,5,4,0>
+ 3761234303U, // <5,0,4,6>: Cost 4 vext3 <0,4,6,5>, <0,4,6,5>
+ 2646150600U, // <5,0,4,7>: Cost 3 vext2 <4,7,5,0>, <4,7,5,0>
+ 1613381970U, // <5,0,4,u>: Cost 2 vext3 <0,4,1,5>, <0,4,1,5>
+ 3766763926U, // <5,0,5,0>: Cost 4 vext3 <1,4,0,5>, <0,5,0,1>
+ 2919268454U, // <5,0,5,1>: Cost 3 vzipl <5,5,5,5>, LHS
+ 3053486182U, // <5,0,5,2>: Cost 3 vtrnl <5,5,5,5>, LHS
+ 3723210589U, // <5,0,5,3>: Cost 4 vext2 <5,3,5,0>, <5,3,5,0>
+ 3766763966U, // <5,0,5,4>: Cost 4 vext3 <1,4,0,5>, <0,5,4,5>
2650796031U, // <5,0,5,5>: Cost 3 vext2 <5,5,5,0>, <5,5,5,0>
- 3729846348U, // <5,0,5,6>: Cost 4 vext2 <6,4,5,0>, <5,6,4,5>
- 3923382390U, // <5,0,5,7>: Cost 4 vuzpr <5,1,7,3>, <5,7,0,2>
- 3088289796U, // <5,0,5,u>: Cost 3 vtrnr LHS, <5,5,5,5>
- 3791684077U, // <5,0,6,0>: Cost 4 vext3 <5,5,5,5>, <0,6,0,7>
- 2953629794U, // <5,0,6,1>: Cost 3 vzipr LHS, <5,6,7,0>
- 4161589016U, // <5,0,6,2>: Cost 4 vtrnr LHS, <5,2,6,3>
- 3715912266U, // <5,0,6,3>: Cost 4 vext2 <4,1,5,0>, <6,3,7,2>
- 3711931038U, // <5,0,6,4>: Cost 4 vext2 <3,4,5,0>, <6,4,7,5>
- 3737146034U, // <5,0,6,5>: Cost 4 vext2 <7,6,5,0>, <6,5,0,7>
- 3735819064U, // <5,0,6,6>: Cost 4 vext2 <7,4,5,0>, <6,6,6,6>
+ 3719893090U, // <5,0,5,6>: Cost 4 vext2 <4,7,5,0>, <5,6,7,0>
+ 3914067254U, // <5,0,5,7>: Cost 4 vuzpr <3,5,7,0>, RHS
+ 2919269021U, // <5,0,5,u>: Cost 3 vzipl <5,5,5,5>, LHS
+ 4047519744U, // <5,0,6,0>: Cost 4 vzipr <3,4,5,6>, <0,0,0,0>
+ 2920038502U, // <5,0,6,1>: Cost 3 vzipl <5,6,7,0>, LHS
+ 3759759871U, // <5,0,6,2>: Cost 4 vext3 <0,2,4,5>, <0,6,2,7>
+ 3645164070U, // <5,0,6,3>: Cost 4 vext1 <3,5,0,6>, <3,5,0,6>
+ 3762414095U, // <5,0,6,4>: Cost 4 vext3 <0,6,4,5>, <0,6,4,5>
+ 3993780690U, // <5,0,6,5>: Cost 4 vzipl <5,6,7,0>, <0,5,6,7>
+ 3719893816U, // <5,0,6,6>: Cost 4 vext2 <4,7,5,0>, <6,6,6,6>
2662077302U, // <5,0,6,7>: Cost 3 vext2 <7,4,5,0>, <6,7,4,5>
- 2662077302U, // <5,0,6,u>: Cost 3 vext2 <7,4,5,0>, <6,7,4,5>
- 2589343846U, // <5,0,7,0>: Cost 3 vext1 <6,5,0,7>, LHS
- 3044166966U, // <5,0,7,1>: Cost 3 vtrnl <4,0,5,1>, RHS
- 3087847120U, // <5,0,7,2>: Cost 3 vtrnr LHS, <5,1,7,3>
- 3645172263U, // <5,0,7,3>: Cost 4 vext1 <3,5,0,7>, <3,5,0,7>
- 2589347126U, // <5,0,7,4>: Cost 3 vext1 <6,5,0,7>, RHS
+ 2920039069U, // <5,0,6,u>: Cost 3 vzipl <5,6,7,0>, LHS
+ 2565455974U, // <5,0,7,0>: Cost 3 vext1 <2,5,0,7>, LHS
+ 2565456790U, // <5,0,7,1>: Cost 3 vext1 <2,5,0,7>, <1,2,3,0>
+ 2565457742U, // <5,0,7,2>: Cost 3 vext1 <2,5,0,7>, <2,5,0,7>
+ 3639199894U, // <5,0,7,3>: Cost 4 vext1 <2,5,0,7>, <3,0,1,2>
+ 2565459254U, // <5,0,7,4>: Cost 3 vext1 <2,5,0,7>, RHS
2589347938U, // <5,0,7,5>: Cost 3 vext1 <6,5,0,7>, <5,6,7,0>
2589348530U, // <5,0,7,6>: Cost 3 vext1 <6,5,0,7>, <6,5,0,7>
- 3663090682U, // <5,0,7,7>: Cost 4 vext1 <6,5,0,7>, <7,0,1,2>
- 3088289488U, // <5,0,7,u>: Cost 3 vtrnr LHS, <5,1,7,3>
- 2698625674U, // <5,0,u,0>: Cost 3 vext3 <2,3,4,5>, <0,u,0,2>
+ 4188456422U, // <5,0,7,7>: Cost 4 vtrnr RHS, <2,0,5,7>
+ 2565461806U, // <5,0,7,u>: Cost 3 vext1 <2,5,0,7>, LHS
+ 2687124106U, // <5,0,u,0>: Cost 3 vext3 <0,4,1,5>, <0,u,0,2>
1616036502U, // <5,0,u,1>: Cost 2 vext3 <0,u,1,5>, <0,u,1,5>
- 1624883869U, // <5,0,u,2>: Cost 2 vext3 <2,3,4,5>, LHS
- 2638186190U, // <5,0,u,3>: Cost 3 vext2 <3,4,5,0>, <2,3,4,5>
- 2689999537U, // <5,0,u,4>: Cost 3 vext3 <0,u,4,5>, <0,u,4,5>
+ 1613382301U, // <5,0,u,2>: Cost 2 vext3 <0,4,1,5>, LHS
+ 2689925800U, // <5,0,u,3>: Cost 3 vext3 <0,u,3,5>, <0,u,3,5>
+ 2687124146U, // <5,0,u,4>: Cost 3 vext3 <0,4,1,5>, <0,u,4,6>
2638190746U, // <5,0,u,5>: Cost 3 vext2 <3,4,5,0>, RHS
2589356723U, // <5,0,u,6>: Cost 3 vext1 <6,5,0,u>, <6,5,0,u>
- 2662077302U, // <5,0,u,7>: Cost 3 vext2 <7,4,5,0>, <6,7,4,5>
- 1624883923U, // <5,0,u,u>: Cost 2 vext3 <2,3,4,5>, LHS
- 2641510400U, // <5,1,0,0>: Cost 3 vext2 <4,0,5,1>, <0,0,0,0>
- 1567768678U, // <5,1,0,1>: Cost 2 vext2 <4,0,5,1>, LHS
- 2641510564U, // <5,1,0,2>: Cost 3 vext2 <4,0,5,1>, <0,2,0,2>
- 2698625782U, // <5,1,0,3>: Cost 3 vext3 <2,3,4,5>, <1,0,3,2>
+ 2595280230U, // <5,0,u,7>: Cost 3 vext1 <7,5,0,2>, <7,4,5,6>
+ 1613382355U, // <5,0,u,u>: Cost 2 vext3 <0,4,1,5>, LHS
+ 2646818816U, // <5,1,0,0>: Cost 3 vext2 <4,u,5,1>, <0,0,0,0>
+ 1573077094U, // <5,1,0,1>: Cost 2 vext2 <4,u,5,1>, LHS
+ 2646818980U, // <5,1,0,2>: Cost 3 vext2 <4,u,5,1>, <0,2,0,2>
+ 2687124214U, // <5,1,0,3>: Cost 3 vext3 <0,4,1,5>, <1,0,3,2>
2641510738U, // <5,1,0,4>: Cost 3 vext2 <4,0,5,1>, <0,4,1,5>
2641510814U, // <5,1,0,5>: Cost 3 vext2 <4,0,5,1>, <0,5,1,0>
- 3663106740U, // <5,1,0,6>: Cost 4 vext1 <6,5,1,0>, <6,5,1,0>
- 3669079437U, // <5,1,0,7>: Cost 4 vext1 <7,5,1,0>, <7,5,1,0>
- 1567769245U, // <5,1,0,u>: Cost 2 vext2 <4,0,5,1>, LHS
- 2641511158U, // <5,1,1,0>: Cost 3 vext2 <4,0,5,1>, <1,0,3,2>
- 2691326772U, // <5,1,1,1>: Cost 3 vext3 <1,1,4,5>, <1,1,1,1>
- 2641511318U, // <5,1,1,2>: Cost 3 vext2 <4,0,5,1>, <1,2,3,0>
- 2698625864U, // <5,1,1,3>: Cost 3 vext3 <2,3,4,5>, <1,1,3,3>
+ 3720561142U, // <5,1,0,6>: Cost 4 vext2 <4,u,5,1>, <0,6,1,7>
+ 3298141357U, // <5,1,0,7>: Cost 4 vrev <1,5,7,0>
+ 1573077661U, // <5,1,0,u>: Cost 2 vext2 <4,u,5,1>, LHS
+ 2223891567U, // <5,1,1,0>: Cost 3 vrev <1,5,0,1>
+ 2687124276U, // <5,1,1,1>: Cost 3 vext3 <0,4,1,5>, <1,1,1,1>
+ 2646819734U, // <5,1,1,2>: Cost 3 vext2 <4,u,5,1>, <1,2,3,0>
+ 2687124296U, // <5,1,1,3>: Cost 3 vext3 <0,4,1,5>, <1,1,3,3>
2691326803U, // <5,1,1,4>: Cost 3 vext3 <1,1,4,5>, <1,1,4,5>
- 2583400412U, // <5,1,1,5>: Cost 3 vext1 <5,5,1,1>, <5,5,1,1>
- 3657142778U, // <5,1,1,6>: Cost 4 vext1 <5,5,1,1>, <6,2,7,3>
- 3657143290U, // <5,1,1,7>: Cost 4 vext1 <5,5,1,1>, <7,0,1,2>
- 2691621751U, // <5,1,1,u>: Cost 3 vext3 <1,1,u,5>, <1,1,u,5>
- 3708618209U, // <5,1,2,0>: Cost 4 vext2 <2,u,5,1>, <2,0,5,2>
- 3765068679U, // <5,1,2,1>: Cost 4 vext3 <1,1,4,5>, <1,2,1,3>
- 2641512040U, // <5,1,2,2>: Cost 3 vext2 <4,0,5,1>, <2,2,2,2>
- 2698625942U, // <5,1,2,3>: Cost 3 vext3 <2,3,4,5>, <1,2,3,0>
+ 2691400540U, // <5,1,1,5>: Cost 3 vext3 <1,1,5,5>, <1,1,5,5>
+ 3765216101U, // <5,1,1,6>: Cost 4 vext3 <1,1,6,5>, <1,1,6,5>
+ 3765289838U, // <5,1,1,7>: Cost 4 vext3 <1,1,7,5>, <1,1,7,5>
+ 2687124341U, // <5,1,1,u>: Cost 3 vext3 <0,4,1,5>, <1,1,u,3>
+ 3297641584U, // <5,1,2,0>: Cost 4 vrev <1,5,0,2>
+ 3763520391U, // <5,1,2,1>: Cost 4 vext3 <0,u,1,5>, <1,2,1,3>
+ 2646820456U, // <5,1,2,2>: Cost 3 vext2 <4,u,5,1>, <2,2,2,2>
+ 2687124374U, // <5,1,2,3>: Cost 3 vext3 <0,4,1,5>, <1,2,3,0>
2691990436U, // <5,1,2,4>: Cost 3 vext3 <1,2,4,5>, <1,2,4,5>
2687124395U, // <5,1,2,5>: Cost 3 vext3 <0,4,1,5>, <1,2,5,3>
- 2665400250U, // <5,1,2,6>: Cost 3 vext2 <u,0,5,1>, <2,6,3,7>
- 3731843079U, // <5,1,2,7>: Cost 4 vext2 <6,7,5,1>, <2,7,3,3>
- 2692285384U, // <5,1,2,u>: Cost 3 vext3 <1,2,u,5>, <1,2,u,5>
- 2641512598U, // <5,1,3,0>: Cost 3 vext2 <4,0,5,1>, <3,0,1,2>
- 3772367832U, // <5,1,3,1>: Cost 4 vext3 <2,3,4,5>, <1,3,1,3>
- 3705301307U, // <5,1,3,2>: Cost 4 vext2 <2,3,5,1>, <3,2,1,5>
- 2641512860U, // <5,1,3,3>: Cost 3 vext2 <4,0,5,1>, <3,3,3,3>
- 2641512916U, // <5,1,3,4>: Cost 3 vext2 <4,0,5,1>, <3,4,0,5>
- 3705301545U, // <5,1,3,5>: Cost 4 vext2 <2,3,5,1>, <3,5,1,0>
- 3715254922U, // <5,1,3,6>: Cost 4 vext2 <4,0,5,1>, <3,6,2,7>
- 3735161570U, // <5,1,3,7>: Cost 4 vext2 <7,3,5,1>, <3,7,3,5>
- 2641513246U, // <5,1,3,u>: Cost 3 vext2 <4,0,5,1>, <3,u,1,2>
+ 2646820794U, // <5,1,2,6>: Cost 3 vext2 <4,u,5,1>, <2,6,3,7>
+ 3808199610U, // <5,1,2,7>: Cost 4 vext3 <u,3,4,5>, <1,2,7,0>
+ 2687124419U, // <5,1,2,u>: Cost 3 vext3 <0,4,1,5>, <1,2,u,0>
+ 2577440870U, // <5,1,3,0>: Cost 3 vext1 <4,5,1,3>, LHS
+ 2687124440U, // <5,1,3,1>: Cost 3 vext3 <0,4,1,5>, <1,3,1,3>
+ 3759686627U, // <5,1,3,2>: Cost 4 vext3 <0,2,3,5>, <1,3,2,5>
+ 2692580332U, // <5,1,3,3>: Cost 3 vext3 <1,3,3,5>, <1,3,3,5>
+ 2687124469U, // <5,1,3,4>: Cost 3 vext3 <0,4,1,5>, <1,3,4,5>
+ 2685207552U, // <5,1,3,5>: Cost 3 vext3 <0,1,2,5>, <1,3,5,7>
+ 3760866313U, // <5,1,3,6>: Cost 4 vext3 <0,4,1,5>, <1,3,6,7>
+ 2692875280U, // <5,1,3,7>: Cost 3 vext3 <1,3,7,5>, <1,3,7,5>
+ 2687124503U, // <5,1,3,u>: Cost 3 vext3 <0,4,1,5>, <1,3,u,3>
1567771538U, // <5,1,4,0>: Cost 2 vext2 <4,0,5,1>, <4,0,5,1>
- 2642176995U, // <5,1,4,1>: Cost 3 vext2 <4,1,5,1>, <4,1,5,1>
+ 2693096491U, // <5,1,4,1>: Cost 3 vext3 <1,4,1,5>, <1,4,1,5>
2693170228U, // <5,1,4,2>: Cost 3 vext3 <1,4,2,5>, <1,4,2,5>
- 2693243965U, // <5,1,4,3>: Cost 3 vext3 <1,4,3,5>, <1,4,3,5>
- 2665401552U, // <5,1,4,4>: Cost 3 vext2 <u,0,5,1>, <4,4,4,4>
- 1567771958U, // <5,1,4,5>: Cost 2 vext2 <4,0,5,1>, RHS
- 2641513804U, // <5,1,4,6>: Cost 3 vext2 <4,0,5,1>, <4,6,0,2>
- 3669112209U, // <5,1,4,7>: Cost 4 vext1 <7,5,1,4>, <7,5,1,4>
- 1567772201U, // <5,1,4,u>: Cost 2 vext2 <4,0,5,1>, RHS
- 2734900335U, // <5,1,5,0>: Cost 3 vext3 <u,4,1,5>, <1,5,0,1>
- 2631560912U, // <5,1,5,1>: Cost 3 vext2 <2,3,5,1>, <5,1,7,3>
- 2641514219U, // <5,1,5,2>: Cost 3 vext2 <4,0,5,1>, <5,2,1,3>
- 2717942928U, // <5,1,5,3>: Cost 3 vext3 <5,5,5,5>, <1,5,3,7>
- 2665402310U, // <5,1,5,4>: Cost 3 vext2 <u,0,5,1>, <5,4,7,6>
- 2665402372U, // <5,1,5,5>: Cost 3 vext2 <u,0,5,1>, <5,5,5,5>
- 2665402466U, // <5,1,5,6>: Cost 3 vext2 <u,0,5,1>, <5,6,7,0>
- 3705303158U, // <5,1,5,7>: Cost 4 vext2 <2,3,5,1>, <5,7,0,2>
- 2641514705U, // <5,1,5,u>: Cost 3 vext2 <4,0,5,1>, <5,u,1,3>
- 2601353318U, // <5,1,6,0>: Cost 3 vext1 <u,5,1,6>, LHS
- 3966141520U, // <5,1,6,1>: Cost 4 vzipl <1,1,1,1>, <1,4,5,6>
- 2641515002U, // <5,1,6,2>: Cost 3 vext2 <4,0,5,1>, <6,2,7,3>
- 3715256882U, // <5,1,6,3>: Cost 4 vext2 <4,0,5,1>, <6,3,4,5>
- 2601356598U, // <5,1,6,4>: Cost 3 vext1 <u,5,1,6>, RHS
- 2601357410U, // <5,1,6,5>: Cost 3 vext1 <u,5,1,6>, <5,6,7,0>
- 2665403192U, // <5,1,6,6>: Cost 3 vext2 <u,0,5,1>, <6,6,6,6>
- 2658104187U, // <5,1,6,7>: Cost 3 vext2 <6,7,5,1>, <6,7,5,1>
- 2641515488U, // <5,1,6,u>: Cost 3 vext2 <4,0,5,1>, <6,u,7,3>
- 2571501670U, // <5,1,7,0>: Cost 3 vext1 <3,5,1,7>, LHS
- 3026619702U, // <5,1,7,1>: Cost 3 vtrnl <1,1,1,1>, RHS
- 4100295990U, // <5,1,7,2>: Cost 4 vtrnl <1,1,0,2>, RHS
- 1946996022U, // <5,1,7,3>: Cost 2 vtrnl LHS, RHS
- 2571504950U, // <5,1,7,4>: Cost 3 vext1 <3,5,1,7>, RHS
- 2571505360U, // <5,1,7,5>: Cost 3 vext1 <3,5,1,7>, <5,1,7,3>
- 3645247994U, // <5,1,7,6>: Cost 4 vext1 <3,5,1,7>, <6,2,7,3>
- 2595394964U, // <5,1,7,7>: Cost 3 vext1 <7,5,1,7>, <7,5,1,7>
- 1947036982U, // <5,1,7,u>: Cost 2 vtrnl LHS, RHS
+ 2687124541U, // <5,1,4,3>: Cost 3 vext3 <0,4,1,5>, <1,4,3,5>
+ 2646822096U, // <5,1,4,4>: Cost 3 vext2 <4,u,5,1>, <4,4,4,4>
+ 1573080374U, // <5,1,4,5>: Cost 2 vext2 <4,u,5,1>, RHS
+ 2646822260U, // <5,1,4,6>: Cost 3 vext2 <4,u,5,1>, <4,6,4,6>
+ 3298174129U, // <5,1,4,7>: Cost 4 vrev <1,5,7,4>
+ 1573080602U, // <5,1,4,u>: Cost 2 vext2 <4,u,5,1>, <4,u,5,1>
+ 2687124591U, // <5,1,5,0>: Cost 3 vext3 <0,4,1,5>, <1,5,0,1>
+ 2646822543U, // <5,1,5,1>: Cost 3 vext2 <4,u,5,1>, <5,1,0,1>
+ 3760866433U, // <5,1,5,2>: Cost 4 vext3 <0,4,1,5>, <1,5,2,1>
+ 2687124624U, // <5,1,5,3>: Cost 3 vext3 <0,4,1,5>, <1,5,3,7>
+ 2687124631U, // <5,1,5,4>: Cost 3 vext3 <0,4,1,5>, <1,5,4,5>
+ 2646822916U, // <5,1,5,5>: Cost 3 vext2 <4,u,5,1>, <5,5,5,5>
+ 2646823010U, // <5,1,5,6>: Cost 3 vext2 <4,u,5,1>, <5,6,7,0>
+ 2646823080U, // <5,1,5,7>: Cost 3 vext2 <4,u,5,1>, <5,7,5,7>
+ 2687124663U, // <5,1,5,u>: Cost 3 vext3 <0,4,1,5>, <1,5,u,1>
+ 2553577574U, // <5,1,6,0>: Cost 3 vext1 <0,5,1,6>, LHS
+ 3763520719U, // <5,1,6,1>: Cost 4 vext3 <0,u,1,5>, <1,6,1,7>
+ 2646823418U, // <5,1,6,2>: Cost 3 vext2 <4,u,5,1>, <6,2,7,3>
+ 3760866529U, // <5,1,6,3>: Cost 4 vext3 <0,4,1,5>, <1,6,3,7>
+ 2553580854U, // <5,1,6,4>: Cost 3 vext1 <0,5,1,6>, RHS
+ 2687124723U, // <5,1,6,5>: Cost 3 vext3 <0,4,1,5>, <1,6,5,7>
+ 2646823736U, // <5,1,6,6>: Cost 3 vext2 <4,u,5,1>, <6,6,6,6>
+ 2646823758U, // <5,1,6,7>: Cost 3 vext2 <4,u,5,1>, <6,7,0,1>
+ 2646823839U, // <5,1,6,u>: Cost 3 vext2 <4,u,5,1>, <6,u,0,1>
+ 2559557734U, // <5,1,7,0>: Cost 3 vext1 <1,5,1,7>, LHS
+ 2559558452U, // <5,1,7,1>: Cost 3 vext1 <1,5,1,7>, <1,1,1,1>
+ 2571503270U, // <5,1,7,2>: Cost 3 vext1 <3,5,1,7>, <2,3,0,1>
+ 2040971366U, // <5,1,7,3>: Cost 2 vtrnr RHS, LHS
+ 2559561014U, // <5,1,7,4>: Cost 3 vext1 <1,5,1,7>, RHS
+ 2595393232U, // <5,1,7,5>: Cost 3 vext1 <7,5,1,7>, <5,1,7,3>
+ 4188455035U, // <5,1,7,6>: Cost 4 vtrnr RHS, <0,1,4,6>
+ 2646824556U, // <5,1,7,7>: Cost 3 vext2 <4,u,5,1>, <7,7,7,7>
+ 2040971371U, // <5,1,7,u>: Cost 2 vtrnr RHS, LHS
1591662326U, // <5,1,u,0>: Cost 2 vext2 <u,0,5,1>, <u,0,5,1>
- 1567774510U, // <5,1,u,1>: Cost 2 vext2 <4,0,5,1>, LHS
- 2641516396U, // <5,1,u,2>: Cost 3 vext2 <4,0,5,1>, <u,2,0,2>
- 1946996023U, // <5,1,u,3>: Cost 2 vtrnl LHS, RHS
- 2571513142U, // <5,1,u,4>: Cost 3 vext1 <3,5,1,u>, RHS
- 1567774874U, // <5,1,u,5>: Cost 2 vext2 <4,0,5,1>, RHS
- 2641516720U, // <5,1,u,6>: Cost 3 vext2 <4,0,5,1>, <u,6,0,2>
- 2595403157U, // <5,1,u,7>: Cost 3 vext1 <7,5,1,u>, <7,5,1,u>
- 1947036983U, // <5,1,u,u>: Cost 2 vtrnl LHS, RHS
- 3772368308U, // <5,2,0,0>: Cost 4 vext3 <2,3,4,5>, <2,0,0,2>
- 2635546726U, // <5,2,0,1>: Cost 3 vext2 <3,0,5,2>, LHS
- 3759760836U, // <5,2,0,2>: Cost 4 vext3 <0,2,4,5>, <2,0,2,0>
- 3772368334U, // <5,2,0,3>: Cost 4 vext3 <2,3,4,5>, <2,0,3,1>
- 2698626520U, // <5,2,0,4>: Cost 3 vext3 <2,3,4,5>, <2,0,4,2>
- 3759760867U, // <5,2,0,5>: Cost 4 vext3 <0,2,4,5>, <2,0,5,4>
- 3791685100U, // <5,2,0,6>: Cost 4 vext3 <5,5,5,5>, <2,0,6,4>
+ 1573082926U, // <5,1,u,1>: Cost 2 vext2 <4,u,5,1>, LHS
+ 2695824760U, // <5,1,u,2>: Cost 3 vext3 <1,u,2,5>, <1,u,2,5>
+ 2040979558U, // <5,1,u,3>: Cost 2 vtrnr RHS, LHS
+ 2687124874U, // <5,1,u,4>: Cost 3 vext3 <0,4,1,5>, <1,u,4,5>
+ 1573083290U, // <5,1,u,5>: Cost 2 vext2 <4,u,5,1>, RHS
+ 2646825168U, // <5,1,u,6>: Cost 3 vext2 <4,u,5,1>, <u,6,3,7>
+ 2646825216U, // <5,1,u,7>: Cost 3 vext2 <4,u,5,1>, <u,7,0,1>
+ 2040979563U, // <5,1,u,u>: Cost 2 vtrnr RHS, LHS
+ 3702652928U, // <5,2,0,0>: Cost 4 vext2 <1,u,5,2>, <0,0,0,0>
+ 2628911206U, // <5,2,0,1>: Cost 3 vext2 <1,u,5,2>, LHS
+ 2641518756U, // <5,2,0,2>: Cost 3 vext2 <4,0,5,2>, <0,2,0,2>
+ 3759760847U, // <5,2,0,3>: Cost 4 vext3 <0,2,4,5>, <2,0,3,2>
+ 3760866775U, // <5,2,0,4>: Cost 4 vext3 <0,4,1,5>, <2,0,4,1>
+ 3759539680U, // <5,2,0,5>: Cost 4 vext3 <0,2,1,5>, <2,0,5,1>
+ 3760866796U, // <5,2,0,6>: Cost 4 vext3 <0,4,1,5>, <2,0,6,4>
3304114054U, // <5,2,0,7>: Cost 4 vrev <2,5,7,0>
- 2635547293U, // <5,2,0,u>: Cost 3 vext2 <3,0,5,2>, LHS
- 3772368390U, // <5,2,1,0>: Cost 4 vext3 <2,3,4,5>, <2,1,0,3>
- 3709289268U, // <5,2,1,1>: Cost 4 vext2 <3,0,5,2>, <1,1,1,1>
- 2642183062U, // <5,2,1,2>: Cost 3 vext2 <4,1,5,2>, <1,2,3,0>
- 2891164562U, // <5,2,1,3>: Cost 3 vzipl LHS, <4,0,5,1>
- 3771041324U, // <5,2,1,4>: Cost 4 vext3 <2,1,4,5>, <2,1,4,5>
- 3766027827U, // <5,2,1,5>: Cost 4 vext3 <1,2,u,5>, <2,1,5,3>
- 3808200252U, // <5,2,1,6>: Cost 4 vext3 <u,3,4,5>, <2,1,6,3>
- 3669161367U, // <5,2,1,7>: Cost 4 vext1 <7,5,2,1>, <7,5,2,1>
- 2886560658U, // <5,2,1,u>: Cost 3 vzipl LHS, <4,0,5,1>
- 3703317985U, // <5,2,2,0>: Cost 4 vext2 <2,0,5,2>, <2,0,5,2>
- 3633333378U, // <5,2,2,1>: Cost 4 vext1 <1,5,2,2>, <1,5,2,2>
- 2697963112U, // <5,2,2,2>: Cost 3 vext3 <2,2,4,5>, <2,2,2,2>
- 2698626674U, // <5,2,2,3>: Cost 3 vext3 <2,3,4,5>, <2,2,3,3>
+ 2628911773U, // <5,2,0,u>: Cost 3 vext2 <1,u,5,2>, LHS
+ 2623603464U, // <5,2,1,0>: Cost 3 vext2 <1,0,5,2>, <1,0,5,2>
+ 3698008921U, // <5,2,1,1>: Cost 4 vext2 <1,1,5,2>, <1,1,5,2>
+ 3633325603U, // <5,2,1,2>: Cost 4 vext1 <1,5,2,1>, <2,1,3,5>
+ 2687125027U, // <5,2,1,3>: Cost 3 vext3 <0,4,1,5>, <2,1,3,5>
+ 3633327414U, // <5,2,1,4>: Cost 4 vext1 <1,5,2,1>, RHS
+ 3759539760U, // <5,2,1,5>: Cost 4 vext3 <0,2,1,5>, <2,1,5,0>
+ 3760866876U, // <5,2,1,6>: Cost 4 vext3 <0,4,1,5>, <2,1,6,3>
+ 3304122247U, // <5,2,1,7>: Cost 4 vrev <2,5,7,1>
+ 2687125072U, // <5,2,1,u>: Cost 3 vext3 <0,4,1,5>, <2,1,u,5>
+ 3633332326U, // <5,2,2,0>: Cost 4 vext1 <1,5,2,2>, LHS
+ 3759760992U, // <5,2,2,1>: Cost 4 vext3 <0,2,4,5>, <2,2,1,3>
+ 2687125096U, // <5,2,2,2>: Cost 3 vext3 <0,4,1,5>, <2,2,2,2>
+ 2687125106U, // <5,2,2,3>: Cost 3 vext3 <0,4,1,5>, <2,2,3,3>
2697963133U, // <5,2,2,4>: Cost 3 vext3 <2,2,4,5>, <2,2,4,5>
- 3759761027U, // <5,2,2,5>: Cost 4 vext3 <0,2,4,5>, <2,2,5,2>
- 3739150266U, // <5,2,2,6>: Cost 4 vext2 <u,0,5,2>, <2,6,3,7>
- 3719243780U, // <5,2,2,7>: Cost 4 vext2 <4,6,5,2>, <2,7,3,0>
- 2698258081U, // <5,2,2,u>: Cost 3 vext3 <2,2,u,5>, <2,2,u,5>
- 2698626726U, // <5,2,3,0>: Cost 3 vext3 <2,3,4,5>, <2,3,0,1>
+ 3759466120U, // <5,2,2,5>: Cost 4 vext3 <0,2,0,5>, <2,2,5,7>
+ 3760866960U, // <5,2,2,6>: Cost 4 vext3 <0,4,1,5>, <2,2,6,6>
+ 3771926168U, // <5,2,2,7>: Cost 4 vext3 <2,2,7,5>, <2,2,7,5>
+ 2687125151U, // <5,2,2,u>: Cost 3 vext3 <0,4,1,5>, <2,2,u,3>
+ 2687125158U, // <5,2,3,0>: Cost 3 vext3 <0,4,1,5>, <2,3,0,1>
2698405555U, // <5,2,3,1>: Cost 3 vext3 <2,3,1,5>, <2,3,1,5>
2577516238U, // <5,2,3,2>: Cost 3 vext1 <4,5,2,3>, <2,3,4,5>
- 3960261686U, // <5,2,3,3>: Cost 4 vzipl LHS, <4,2,5,3>
+ 3759687365U, // <5,2,3,3>: Cost 4 vext3 <0,2,3,5>, <2,3,3,5>
1624884942U, // <5,2,3,4>: Cost 2 vext3 <2,3,4,5>, <2,3,4,5>
2698700503U, // <5,2,3,5>: Cost 3 vext3 <2,3,5,5>, <2,3,5,5>
- 3772368605U, // <5,2,3,6>: Cost 4 vext3 <2,3,4,5>, <2,3,6,2>
- 3669177753U, // <5,2,3,7>: Cost 4 vext1 <7,5,2,3>, <7,5,2,3>
+ 3772368608U, // <5,2,3,6>: Cost 4 vext3 <2,3,4,5>, <2,3,6,5>
+ 3702655716U, // <5,2,3,7>: Cost 4 vext2 <1,u,5,2>, <3,7,3,7>
1625179890U, // <5,2,3,u>: Cost 2 vext3 <2,3,u,5>, <2,3,u,5>
- 2698626808U, // <5,2,4,0>: Cost 3 vext3 <2,3,4,5>, <2,4,0,2>
- 2642185188U, // <5,2,4,1>: Cost 3 vext2 <4,1,5,2>, <4,1,5,2>
- 2642848821U, // <5,2,4,2>: Cost 3 vext2 <4,2,5,2>, <4,2,5,2>
- 2699216662U, // <5,2,4,3>: Cost 3 vext3 <2,4,3,5>, <2,4,3,5>
+ 2641521555U, // <5,2,4,0>: Cost 3 vext2 <4,0,5,2>, <4,0,5,2>
+ 3772368642U, // <5,2,4,1>: Cost 4 vext3 <2,3,4,5>, <2,4,1,3>
+ 2699142925U, // <5,2,4,2>: Cost 3 vext3 <2,4,2,5>, <2,4,2,5>
+ 2698626838U, // <5,2,4,3>: Cost 3 vext3 <2,3,4,5>, <2,4,3,5>
2698626848U, // <5,2,4,4>: Cost 3 vext3 <2,3,4,5>, <2,4,4,6>
- 2635550006U, // <5,2,4,5>: Cost 3 vext2 <3,0,5,2>, RHS
- 2699437873U, // <5,2,4,6>: Cost 3 vext3 <2,4,6,5>, <2,4,6,5>
+ 2628914486U, // <5,2,4,5>: Cost 3 vext2 <1,u,5,2>, RHS
+ 2645503353U, // <5,2,4,6>: Cost 3 vext2 <4,6,5,2>, <4,6,5,2>
3304146826U, // <5,2,4,7>: Cost 4 vrev <2,5,7,4>
- 2635550249U, // <5,2,4,u>: Cost 3 vext2 <3,0,5,2>, RHS
- 2601418854U, // <5,2,5,0>: Cost 3 vext1 <u,5,2,5>, LHS
- 3703320272U, // <5,2,5,1>: Cost 4 vext2 <2,0,5,2>, <5,1,7,3>
- 3705310960U, // <5,2,5,2>: Cost 4 vext2 <2,3,5,2>, <5,2,1,u>
- 2934295770U, // <5,2,5,3>: Cost 3 vzipl LHS, <4,4,5,5>
- 2601422134U, // <5,2,5,4>: Cost 3 vext1 <u,5,2,5>, RHS
- 2601422852U, // <5,2,5,5>: Cost 3 vext1 <u,5,2,5>, <5,5,5,5>
- 3791685508U, // <5,2,5,6>: Cost 4 vext3 <5,5,5,5>, <2,5,6,7>
- 3675165690U, // <5,2,5,7>: Cost 4 vext1 <u,5,2,5>, <7,0,1,2>
- 2934336730U, // <5,2,5,u>: Cost 3 vzipl LHS, <4,4,5,5>
- 3645309030U, // <5,2,6,0>: Cost 4 vext1 <3,5,2,6>, LHS
- 3633366150U, // <5,2,6,1>: Cost 4 vext1 <1,5,2,6>, <1,5,2,6>
+ 2628914729U, // <5,2,4,u>: Cost 3 vext2 <1,u,5,2>, RHS
+ 2553643110U, // <5,2,5,0>: Cost 3 vext1 <0,5,2,5>, LHS
+ 3758950227U, // <5,2,5,1>: Cost 4 vext3 <0,1,2,5>, <2,5,1,3>
+ 3759761248U, // <5,2,5,2>: Cost 4 vext3 <0,2,4,5>, <2,5,2,7>
+ 2982396006U, // <5,2,5,3>: Cost 3 vzipr <4,u,5,5>, LHS
+ 2553646390U, // <5,2,5,4>: Cost 3 vext1 <0,5,2,5>, RHS
+ 2553647108U, // <5,2,5,5>: Cost 3 vext1 <0,5,2,5>, <5,5,5,5>
+ 3760867204U, // <5,2,5,6>: Cost 4 vext3 <0,4,1,5>, <2,5,6,7>
+ 3702657141U, // <5,2,5,7>: Cost 4 vext2 <1,u,5,2>, <5,7,0,1>
+ 2982396011U, // <5,2,5,u>: Cost 3 vzipr <4,u,5,5>, LHS
+ 3627393126U, // <5,2,6,0>: Cost 4 vext1 <0,5,2,6>, LHS
+ 3760867236U, // <5,2,6,1>: Cost 4 vext3 <0,4,1,5>, <2,6,1,3>
2645504506U, // <5,2,6,2>: Cost 3 vext2 <4,6,5,2>, <6,2,7,3>
- 2886519298U, // <5,2,6,3>: Cost 3 vzipl LHS, <3,4,5,6>
+ 2687125434U, // <5,2,6,3>: Cost 3 vext3 <0,4,1,5>, <2,6,3,7>
2700617665U, // <5,2,6,4>: Cost 3 vext3 <2,6,4,5>, <2,6,4,5>
- 3645312792U, // <5,2,6,5>: Cost 4 vext1 <3,5,2,6>, <5,2,6,3>
- 3791685590U, // <5,2,6,6>: Cost 4 vext3 <5,5,5,5>, <2,6,6,u>
- 3798910939U, // <5,2,6,7>: Cost 4 vext3 <6,7,4,5>, <2,6,7,4>
- 2886560258U, // <5,2,6,u>: Cost 3 vzipl LHS, <3,4,5,6>
- 3027422518U, // <5,2,7,0>: Cost 3 vtrnl <1,2,3,0>, RHS
- 4095569206U, // <5,2,7,1>: Cost 4 vtrnl <0,2,u,1>, RHS
- 3021245750U, // <5,2,7,2>: Cost 3 vtrnl <0,2,0,2>, RHS
- 3033419062U, // <5,2,7,3>: Cost 3 vtrnl <2,2,3,3>, RHS
- 3027455286U, // <5,2,7,4>: Cost 3 vtrnl <1,2,3,4>, RHS
- 4095307062U, // <5,2,7,5>: Cost 4 vtrnl <0,2,4,5>, RHS
- 2589496004U, // <5,2,7,6>: Cost 3 vext1 <6,5,2,7>, <6,5,2,7>
- 3663238138U, // <5,2,7,7>: Cost 4 vext1 <6,5,2,7>, <7,0,1,2>
- 3021294902U, // <5,2,7,u>: Cost 3 vtrnl <0,2,0,u>, RHS
- 3027422519U, // <5,2,u,0>: Cost 3 vtrnl <1,2,3,0>, RHS
- 2635552558U, // <5,2,u,1>: Cost 3 vext2 <3,0,5,2>, LHS
- 3021245751U, // <5,2,u,2>: Cost 3 vtrnl <0,2,0,2>, RHS
- 2886519300U, // <5,2,u,3>: Cost 3 vzipl LHS, <3,4,5,u>
+ 3760867276U, // <5,2,6,5>: Cost 4 vext3 <0,4,1,5>, <2,6,5,7>
+ 3763521493U, // <5,2,6,6>: Cost 4 vext3 <0,u,1,5>, <2,6,6,7>
+ 3719246670U, // <5,2,6,7>: Cost 4 vext2 <4,6,5,2>, <6,7,0,1>
+ 2687125479U, // <5,2,6,u>: Cost 3 vext3 <0,4,1,5>, <2,6,u,7>
+ 2565603430U, // <5,2,7,0>: Cost 3 vext1 <2,5,2,7>, LHS
+ 2553660150U, // <5,2,7,1>: Cost 3 vext1 <0,5,2,7>, <1,0,3,2>
+ 2565605216U, // <5,2,7,2>: Cost 3 vext1 <2,5,2,7>, <2,5,2,7>
+ 2961178726U, // <5,2,7,3>: Cost 3 vzipr <1,3,5,7>, LHS
+ 2565606710U, // <5,2,7,4>: Cost 3 vext1 <2,5,2,7>, RHS
+ 4034920552U, // <5,2,7,5>: Cost 4 vzipr <1,3,5,7>, <0,1,2,5>
+ 3114713292U, // <5,2,7,6>: Cost 3 vtrnr RHS, <0,2,4,6>
+ 3702658668U, // <5,2,7,7>: Cost 4 vext2 <1,u,5,2>, <7,7,7,7>
+ 2961178731U, // <5,2,7,u>: Cost 3 vzipr <1,3,5,7>, LHS
+ 2687125563U, // <5,2,u,0>: Cost 3 vext3 <0,4,1,5>, <2,u,0,1>
+ 2628917038U, // <5,2,u,1>: Cost 3 vext2 <1,u,5,2>, LHS
+ 2565613409U, // <5,2,u,2>: Cost 3 vext1 <2,5,2,u>, <2,5,2,u>
+ 2687125592U, // <5,2,u,3>: Cost 3 vext3 <0,4,1,5>, <2,u,3,3>
1628203107U, // <5,2,u,4>: Cost 2 vext3 <2,u,4,5>, <2,u,4,5>
- 2635552922U, // <5,2,u,5>: Cost 3 vext2 <3,0,5,2>, RHS
- 2589504197U, // <5,2,u,6>: Cost 3 vext1 <6,5,2,u>, <6,5,2,u>
- 3663246330U, // <5,2,u,7>: Cost 4 vext1 <6,5,2,u>, <7,0,1,2>
+ 2628917402U, // <5,2,u,5>: Cost 3 vext2 <1,u,5,2>, RHS
+ 2702092405U, // <5,2,u,6>: Cost 3 vext3 <2,u,6,5>, <2,u,6,5>
+ 3304179598U, // <5,2,u,7>: Cost 4 vrev <2,5,7,u>
1628498055U, // <5,2,u,u>: Cost 2 vext3 <2,u,u,5>, <2,u,u,5>
- 3772369035U, // <5,3,0,0>: Cost 4 vext3 <2,3,4,5>, <3,0,0,0>
- 2698627222U, // <5,3,0,1>: Cost 3 vext3 <2,3,4,5>, <3,0,1,2>
+ 3760867467U, // <5,3,0,0>: Cost 4 vext3 <0,4,1,5>, <3,0,0,0>
+ 2687125654U, // <5,3,0,1>: Cost 3 vext3 <0,4,1,5>, <3,0,1,2>
3759761565U, // <5,3,0,2>: Cost 4 vext3 <0,2,4,5>, <3,0,2,0>
- 3772369063U, // <5,3,0,3>: Cost 4 vext3 <2,3,4,5>, <3,0,3,1>
- 2702608564U, // <5,3,0,4>: Cost 3 vext3 <3,0,4,5>, <3,0,4,5>
- 3772369082U, // <5,3,0,5>: Cost 4 vext3 <2,3,4,5>, <3,0,5,2>
+ 3633391766U, // <5,3,0,3>: Cost 4 vext1 <1,5,3,0>, <3,0,1,2>
+ 2687125680U, // <5,3,0,4>: Cost 3 vext3 <0,4,1,5>, <3,0,4,1>
+ 3760277690U, // <5,3,0,5>: Cost 4 vext3 <0,3,2,5>, <3,0,5,2>
3310013014U, // <5,3,0,6>: Cost 4 vrev <3,5,6,0>
- 3310086751U, // <5,3,0,7>: Cost 4 vrev <3,5,7,0>
- 2698627285U, // <5,3,0,u>: Cost 3 vext3 <2,3,4,5>, <3,0,u,2>
- 2601459814U, // <5,3,1,0>: Cost 3 vext1 <u,5,3,1>, LHS
- 3765070054U, // <5,3,1,1>: Cost 4 vext3 <1,1,4,5>, <3,1,1,1>
+ 2236344927U, // <5,3,0,7>: Cost 3 vrev <3,5,7,0>
+ 2687125717U, // <5,3,0,u>: Cost 3 vext3 <0,4,1,5>, <3,0,u,2>
+ 3760867551U, // <5,3,1,0>: Cost 4 vext3 <0,4,1,5>, <3,1,0,3>
+ 3760867558U, // <5,3,1,1>: Cost 4 vext3 <0,4,1,5>, <3,1,1,1>
2624938923U, // <5,3,1,2>: Cost 3 vext2 <1,2,5,3>, <1,2,5,3>
- 3966307218U, // <5,3,1,3>: Cost 4 vzipl <1,1,3,3>, <4,0,5,1>
- 2601462674U, // <5,3,1,4>: Cost 3 vext1 <u,5,3,1>, <4,0,5,1>
- 2698627340U, // <5,3,1,5>: Cost 3 vext3 <2,3,4,5>, <3,1,5,3>
- 3675206138U, // <5,3,1,6>: Cost 4 vext1 <u,5,3,1>, <6,2,7,3>
- 3669235104U, // <5,3,1,7>: Cost 4 vext1 <7,5,3,1>, <7,5,3,1>
- 2601465646U, // <5,3,1,u>: Cost 3 vext1 <u,5,3,1>, LHS
- 3772369198U, // <5,3,2,0>: Cost 4 vext3 <2,3,4,5>, <3,2,0,1>
- 3703989811U, // <5,3,2,1>: Cost 4 vext2 <2,1,5,3>, <2,1,5,3>
- 3771705665U, // <5,3,2,2>: Cost 4 vext3 <2,2,4,5>, <3,2,2,2>
+ 2703198460U, // <5,3,1,3>: Cost 3 vext3 <3,1,3,5>, <3,1,3,5>
+ 3760867587U, // <5,3,1,4>: Cost 4 vext3 <0,4,1,5>, <3,1,4,3>
+ 2636219536U, // <5,3,1,5>: Cost 3 vext2 <3,1,5,3>, <1,5,3,7>
+ 3698681075U, // <5,3,1,6>: Cost 4 vext2 <1,2,5,3>, <1,6,5,7>
+ 2703493408U, // <5,3,1,7>: Cost 3 vext3 <3,1,7,5>, <3,1,7,5>
+ 2628920721U, // <5,3,1,u>: Cost 3 vext2 <1,u,5,3>, <1,u,5,3>
+ 3766765870U, // <5,3,2,0>: Cost 4 vext3 <1,4,0,5>, <3,2,0,1>
+ 3698681379U, // <5,3,2,1>: Cost 4 vext2 <1,2,5,3>, <2,1,3,5>
+ 3760867649U, // <5,3,2,2>: Cost 4 vext3 <0,4,1,5>, <3,2,2,2>
2698627404U, // <5,3,2,3>: Cost 3 vext3 <2,3,4,5>, <3,2,3,4>
2703935830U, // <5,3,2,4>: Cost 3 vext3 <3,2,4,5>, <3,2,4,5>
2698627422U, // <5,3,2,5>: Cost 3 vext3 <2,3,4,5>, <3,2,5,4>
- 3720579002U, // <5,3,2,6>: Cost 4 vext2 <4,u,5,3>, <2,6,3,7>
- 3777898865U, // <5,3,2,7>: Cost 5 vext3 <3,2,7,5>, <3,2,7,5>
+ 3760867686U, // <5,3,2,6>: Cost 4 vext3 <0,4,1,5>, <3,2,6,3>
+ 3769788783U, // <5,3,2,7>: Cost 4 vext3 <1,u,5,5>, <3,2,7,3>
2701945209U, // <5,3,2,u>: Cost 3 vext3 <2,u,4,5>, <3,2,u,4>
- 3772369279U, // <5,3,3,0>: Cost 4 vext3 <2,3,4,5>, <3,3,0,1>
+ 3760867711U, // <5,3,3,0>: Cost 4 vext3 <0,4,1,5>, <3,3,0,1>
2636220684U, // <5,3,3,1>: Cost 3 vext2 <3,1,5,3>, <3,1,5,3>
3772369298U, // <5,3,3,2>: Cost 4 vext3 <2,3,4,5>, <3,3,2,2>
- 2698627484U, // <5,3,3,3>: Cost 3 vext3 <2,3,4,5>, <3,3,3,3>
+ 2687125916U, // <5,3,3,3>: Cost 3 vext3 <0,4,1,5>, <3,3,3,3>
2704599463U, // <5,3,3,4>: Cost 3 vext3 <3,3,4,5>, <3,3,4,5>
2704673200U, // <5,3,3,5>: Cost 3 vext3 <3,3,5,5>, <3,3,5,5>
- 3733850808U, // <5,3,3,6>: Cost 4 vext2 <7,1,5,3>, <3,6,7,u>
- 4010797891U, // <5,3,3,7>: Cost 4 vzipl <u,5,3,7>, <3,u,5,3>
+ 3709962935U, // <5,3,3,6>: Cost 4 vext2 <3,1,5,3>, <3,6,7,7>
+ 3772369346U, // <5,3,3,7>: Cost 4 vext3 <2,3,4,5>, <3,3,7,5>
2704894411U, // <5,3,3,u>: Cost 3 vext3 <3,3,u,5>, <3,3,u,5>
2704968148U, // <5,3,4,0>: Cost 3 vext3 <3,4,0,5>, <3,4,0,5>
- 3772369370U, // <5,3,4,1>: Cost 4 vext3 <2,3,4,5>, <3,4,1,2>
+ 3698682850U, // <5,3,4,1>: Cost 4 vext2 <1,2,5,3>, <4,1,5,0>
2642857014U, // <5,3,4,2>: Cost 3 vext2 <4,2,5,3>, <4,2,5,3>
- 2643520647U, // <5,3,4,3>: Cost 3 vext2 <4,3,5,3>, <4,3,5,3>
+ 2705189359U, // <5,3,4,3>: Cost 3 vext3 <3,4,3,5>, <3,4,3,5>
2705263096U, // <5,3,4,4>: Cost 3 vext3 <3,4,4,5>, <3,4,4,5>
- 2698627580U, // <5,3,4,5>: Cost 3 vext3 <2,3,4,5>, <3,4,5,0>
- 3772369413U, // <5,3,4,6>: Cost 4 vext3 <2,3,4,5>, <3,4,6,0>
- 3808201238U, // <5,3,4,7>: Cost 4 vext3 <u,3,4,5>, <3,4,7,u>
- 2698627613U, // <5,3,4,u>: Cost 3 vext3 <2,3,4,5>, <3,4,u,6>
+ 2685946370U, // <5,3,4,5>: Cost 3 vext3 <0,2,3,5>, <3,4,5,6>
+ 3779152394U, // <5,3,4,6>: Cost 4 vext3 <3,4,6,5>, <3,4,6,5>
+ 2236377699U, // <5,3,4,7>: Cost 3 vrev <3,5,7,4>
+ 2687126045U, // <5,3,4,u>: Cost 3 vext3 <0,4,1,5>, <3,4,u,6>
2571632742U, // <5,3,5,0>: Cost 3 vext1 <3,5,3,5>, LHS
2559689870U, // <5,3,5,1>: Cost 3 vext1 <1,5,3,5>, <1,5,3,5>
- 2565662567U, // <5,3,5,2>: Cost 3 vext1 <2,5,3,5>, <2,5,3,5>
- 2571635202U, // <5,3,5,3>: Cost 3 vext1 <3,5,3,5>, <3,4,5,6>
+ 2571634382U, // <5,3,5,2>: Cost 3 vext1 <3,5,3,5>, <2,3,4,5>
+ 2571635264U, // <5,3,5,3>: Cost 3 vext1 <3,5,3,5>, <3,5,3,5>
2571636022U, // <5,3,5,4>: Cost 3 vext1 <3,5,3,5>, RHS
- 2601496580U, // <5,3,5,5>: Cost 3 vext1 <u,5,3,5>, <5,5,5,5>
- 3645378849U, // <5,3,5,6>: Cost 4 vext1 <3,5,3,5>, <6,0,1,2>
- 3675239418U, // <5,3,5,7>: Cost 4 vext1 <u,5,3,5>, <7,0,1,2>
+ 2559692804U, // <5,3,5,5>: Cost 3 vext1 <1,5,3,5>, <5,5,5,5>
+ 3720581218U, // <5,3,5,6>: Cost 4 vext2 <4,u,5,3>, <5,6,7,0>
+ 2236385892U, // <5,3,5,7>: Cost 3 vrev <3,5,7,5>
2571638574U, // <5,3,5,u>: Cost 3 vext1 <3,5,3,5>, LHS
- 2601500774U, // <5,3,6,0>: Cost 3 vext1 <u,5,3,6>, LHS
- 3639411508U, // <5,3,6,1>: Cost 4 vext1 <2,5,3,6>, <1,1,1,1>
+ 2565668966U, // <5,3,6,0>: Cost 3 vext1 <2,5,3,6>, LHS
+ 3633439887U, // <5,3,6,1>: Cost 4 vext1 <1,5,3,6>, <1,5,3,6>
2565670760U, // <5,3,6,2>: Cost 3 vext1 <2,5,3,6>, <2,5,3,6>
- 2601503234U, // <5,3,6,3>: Cost 3 vext1 <u,5,3,6>, <3,4,5,6>
- 2601504054U, // <5,3,6,4>: Cost 3 vext1 <u,5,3,6>, RHS
- 4181741336U, // <5,3,6,5>: Cost 4 vtrnr <3,4,5,6>, <5,2,6,3>
- 3720581944U, // <5,3,6,6>: Cost 4 vext2 <4,u,5,3>, <6,6,6,6>
+ 2565671426U, // <5,3,6,3>: Cost 3 vext1 <2,5,3,6>, <3,4,5,6>
+ 2565672246U, // <5,3,6,4>: Cost 3 vext1 <2,5,3,6>, RHS
+ 3639414630U, // <5,3,6,5>: Cost 4 vext1 <2,5,3,6>, <5,3,6,0>
+ 4047521640U, // <5,3,6,6>: Cost 4 vzipr <3,4,5,6>, <2,5,3,6>
2725169844U, // <5,3,6,7>: Cost 3 vext3 <6,7,4,5>, <3,6,7,4>
- 2601506606U, // <5,3,6,u>: Cost 3 vext1 <u,5,3,6>, LHS
- 1527767142U, // <5,3,7,0>: Cost 2 vext1 <u,5,3,7>, LHS
+ 2565674798U, // <5,3,6,u>: Cost 3 vext1 <2,5,3,6>, LHS
+ 1485963366U, // <5,3,7,0>: Cost 2 vext1 <1,5,3,7>, LHS
1485964432U, // <5,3,7,1>: Cost 2 vext1 <1,5,3,7>, <1,5,3,7>
- 2601510504U, // <5,3,7,2>: Cost 3 vext1 <u,5,3,7>, <2,2,2,2>
- 3040054582U, // <5,3,7,3>: Cost 3 vtrnl <3,3,3,3>, RHS
- 1527770422U, // <5,3,7,4>: Cost 2 vext1 <u,5,3,7>, RHS
- 3034172726U, // <5,3,7,5>: Cost 3 vtrnl <2,3,4,5>, RHS
+ 2559706728U, // <5,3,7,2>: Cost 3 vext1 <1,5,3,7>, <2,2,2,2>
+ 2559707286U, // <5,3,7,3>: Cost 3 vext1 <1,5,3,7>, <3,0,1,2>
+ 1485966646U, // <5,3,7,4>: Cost 2 vext1 <1,5,3,7>, RHS
+ 2559708880U, // <5,3,7,5>: Cost 3 vext1 <1,5,3,7>, <5,1,7,3>
2601513466U, // <5,3,7,6>: Cost 3 vext1 <u,5,3,7>, <6,2,7,3>
- 2601513978U, // <5,3,7,7>: Cost 3 vext1 <u,5,3,7>, <7,0,1,2>
- 1527772974U, // <5,3,7,u>: Cost 2 vext1 <u,5,3,7>, LHS
- 1527775334U, // <5,3,u,0>: Cost 2 vext1 <u,5,3,u>, LHS
+ 3114714112U, // <5,3,7,7>: Cost 3 vtrnr RHS, <1,3,5,7>
+ 1485969198U, // <5,3,7,u>: Cost 2 vext1 <1,5,3,7>, LHS
+ 1485971558U, // <5,3,u,0>: Cost 2 vext1 <1,5,3,u>, LHS
1485972625U, // <5,3,u,1>: Cost 2 vext1 <1,5,3,u>, <1,5,3,u>
- 2666747802U, // <5,3,u,2>: Cost 3 vext2 <u,2,5,3>, <u,2,5,3>
- 3040054583U, // <5,3,u,3>: Cost 3 vtrnl <3,3,3,3>, RHS
- 1527778614U, // <5,3,u,4>: Cost 2 vext1 <u,5,3,u>, RHS
- 2698627907U, // <5,3,u,5>: Cost 3 vext3 <2,3,4,5>, <3,u,5,3>
+ 2559714920U, // <5,3,u,2>: Cost 3 vext1 <1,5,3,u>, <2,2,2,2>
+ 2559715478U, // <5,3,u,3>: Cost 3 vext1 <1,5,3,u>, <3,0,1,2>
+ 1485974838U, // <5,3,u,4>: Cost 2 vext1 <1,5,3,u>, RHS
+ 2687126342U, // <5,3,u,5>: Cost 3 vext3 <0,4,1,5>, <3,u,5,6>
2601521658U, // <5,3,u,6>: Cost 3 vext1 <u,5,3,u>, <6,2,7,3>
- 2601522170U, // <5,3,u,7>: Cost 3 vext1 <u,5,3,u>, <7,0,1,2>
- 1527781166U, // <5,3,u,u>: Cost 2 vext1 <u,5,3,u>, LHS
- 3772369765U, // <5,4,0,0>: Cost 4 vext3 <2,3,4,5>, <4,0,0,1>
+ 2236410471U, // <5,3,u,7>: Cost 3 vrev <3,5,7,u>
+ 1485977390U, // <5,3,u,u>: Cost 2 vext1 <1,5,3,u>, LHS
+ 3627491430U, // <5,4,0,0>: Cost 4 vext1 <0,5,4,0>, LHS
2636890214U, // <5,4,0,1>: Cost 3 vext2 <3,2,5,4>, LHS
3703333028U, // <5,4,0,2>: Cost 4 vext2 <2,0,5,4>, <0,2,0,2>
3782249348U, // <5,4,0,3>: Cost 4 vext3 <4,0,3,5>, <4,0,3,5>
- 3782323085U, // <5,4,0,4>: Cost 4 vext3 <4,0,4,5>, <4,0,4,5>
- 2698627986U, // <5,4,0,5>: Cost 3 vext3 <2,3,4,5>, <4,0,5,1>
- 2698627996U, // <5,4,0,6>: Cost 3 vext3 <2,3,4,5>, <4,0,6,2>
- 3669300648U, // <5,4,0,7>: Cost 4 vext1 <7,5,4,0>, <7,5,4,0>
- 2698628013U, // <5,4,0,u>: Cost 3 vext3 <2,3,4,5>, <4,0,u,1>
+ 2642198866U, // <5,4,0,4>: Cost 3 vext2 <4,1,5,4>, <0,4,1,5>
+ 2687126418U, // <5,4,0,5>: Cost 3 vext3 <0,4,1,5>, <4,0,5,1>
+ 2242243887U, // <5,4,0,6>: Cost 3 vrev <4,5,6,0>
+ 3316059448U, // <5,4,0,7>: Cost 4 vrev <4,5,7,0>
+ 2636890781U, // <5,4,0,u>: Cost 3 vext2 <3,2,5,4>, LHS
2241809658U, // <5,4,1,0>: Cost 3 vrev <4,5,0,1>
3698025307U, // <5,4,1,1>: Cost 4 vext2 <1,1,5,4>, <1,1,5,4>
- 3772369866U, // <5,4,1,2>: Cost 4 vext3 <2,3,4,5>, <4,1,2,3>
- 3315772693U, // <5,4,1,3>: Cost 4 vrev <4,5,3,1>
+ 3698688940U, // <5,4,1,2>: Cost 4 vext2 <1,2,5,4>, <1,2,5,4>
+ 3698689024U, // <5,4,1,3>: Cost 4 vext2 <1,2,5,4>, <1,3,5,7>
3700016206U, // <5,4,1,4>: Cost 4 vext2 <1,4,5,4>, <1,4,5,4>
- 2980499152U, // <5,4,1,5>: Cost 3 vzipr RHS, <5,1,7,3>
- 3765070828U, // <5,4,1,6>: Cost 4 vext3 <1,1,4,5>, <4,1,6,1>
- 3669308841U, // <5,4,1,7>: Cost 4 vext1 <7,5,4,1>, <7,5,4,1>
+ 2687126498U, // <5,4,1,5>: Cost 3 vext3 <0,4,1,5>, <4,1,5,0>
+ 3760868336U, // <5,4,1,6>: Cost 4 vext3 <0,4,1,5>, <4,1,6,5>
+ 3316067641U, // <5,4,1,7>: Cost 4 vrev <4,5,7,1>
2242399554U, // <5,4,1,u>: Cost 3 vrev <4,5,u,1>
3703334371U, // <5,4,2,0>: Cost 4 vext2 <2,0,5,4>, <2,0,5,4>
- 3315633412U, // <5,4,2,1>: Cost 4 vrev <4,5,1,2>
+ 3703998004U, // <5,4,2,1>: Cost 4 vext2 <2,1,5,4>, <2,1,5,4>
3704661637U, // <5,4,2,2>: Cost 4 vext2 <2,2,5,4>, <2,2,5,4>
2636891854U, // <5,4,2,3>: Cost 3 vext2 <3,2,5,4>, <2,3,4,5>
- 3772369967U, // <5,4,2,4>: Cost 4 vext3 <2,3,4,5>, <4,2,4,5>
+ 3705988903U, // <5,4,2,4>: Cost 4 vext2 <2,4,5,4>, <2,4,5,4>
2698628150U, // <5,4,2,5>: Cost 3 vext3 <2,3,4,5>, <4,2,5,3>
- 3771706430U, // <5,4,2,6>: Cost 4 vext3 <2,2,4,5>, <4,2,6,2>
- 3707979802U, // <5,4,2,7>: Cost 4 vext2 <2,7,5,4>, <2,7,5,4>
+ 3760868415U, // <5,4,2,6>: Cost 4 vext3 <0,4,1,5>, <4,2,6,3>
+ 3783871562U, // <5,4,2,7>: Cost 4 vext3 <4,2,7,5>, <4,2,7,5>
2666752099U, // <5,4,2,u>: Cost 3 vext2 <u,2,5,4>, <2,u,4,5>
- 3710634134U, // <5,4,3,0>: Cost 4 vext2 <3,2,5,4>, <3,0,1,2>
- 3710634252U, // <5,4,3,1>: Cost 4 vext2 <3,2,5,4>, <3,1,5,3>
+ 3639459942U, // <5,4,3,0>: Cost 4 vext1 <2,5,4,3>, LHS
+ 3709970701U, // <5,4,3,1>: Cost 4 vext2 <3,1,5,4>, <3,1,5,4>
2636892510U, // <5,4,3,2>: Cost 3 vext2 <3,2,5,4>, <3,2,5,4>
3710634396U, // <5,4,3,3>: Cost 4 vext2 <3,2,5,4>, <3,3,3,3>
2638219776U, // <5,4,3,4>: Cost 3 vext2 <3,4,5,4>, <3,4,5,4>
- 3772370052U, // <5,4,3,5>: Cost 4 vext3 <2,3,4,5>, <4,3,5,0>
+ 3766987908U, // <5,4,3,5>: Cost 4 vext3 <1,4,3,5>, <4,3,5,0>
2710719634U, // <5,4,3,6>: Cost 3 vext3 <4,3,6,5>, <4,3,6,5>
- 3713952499U, // <5,4,3,7>: Cost 4 vext2 <3,7,5,4>, <3,7,5,4>
+ 3914097664U, // <5,4,3,7>: Cost 4 vuzpr <3,5,7,4>, <1,3,5,7>
2640874308U, // <5,4,3,u>: Cost 3 vext2 <3,u,5,4>, <3,u,5,4>
2583642214U, // <5,4,4,0>: Cost 3 vext1 <5,5,4,4>, LHS
2642201574U, // <5,4,4,1>: Cost 3 vext2 <4,1,5,4>, <4,1,5,4>
3710635062U, // <5,4,4,2>: Cost 4 vext2 <3,2,5,4>, <4,2,5,3>
3717270664U, // <5,4,4,3>: Cost 4 vext2 <4,3,5,4>, <4,3,5,4>
- 2583645402U, // <5,4,4,4>: Cost 3 vext1 <5,5,4,4>, <4,4,5,5>
+ 2713963728U, // <5,4,4,4>: Cost 3 vext3 <4,u,5,5>, <4,4,4,4>
1637567706U, // <5,4,4,5>: Cost 2 vext3 <4,4,5,5>, <4,4,5,5>
- 2711383267U, // <5,4,4,6>: Cost 3 vext3 <4,4,6,5>, <4,4,6,5>
- 3657389050U, // <5,4,4,7>: Cost 4 vext1 <5,5,4,4>, <7,0,1,2>
+ 2242276659U, // <5,4,4,6>: Cost 3 vrev <4,5,6,4>
+ 2646183372U, // <5,4,4,7>: Cost 3 vext2 <4,7,5,4>, <4,7,5,4>
1637788917U, // <5,4,4,u>: Cost 2 vext3 <4,4,u,5>, <4,4,u,5>
- 2698628346U, // <5,4,5,0>: Cost 3 vext3 <2,3,4,5>, <4,5,0,1>
+ 2559762534U, // <5,4,5,0>: Cost 3 vext1 <1,5,4,5>, LHS
2559763607U, // <5,4,5,1>: Cost 3 vext1 <1,5,4,5>, <1,5,4,5>
2698628366U, // <5,4,5,2>: Cost 3 vext3 <2,3,4,5>, <4,5,2,3>
- 3772370196U, // <5,4,5,3>: Cost 4 vext3 <2,3,4,5>, <4,5,3,0>
- 2698628386U, // <5,4,5,4>: Cost 3 vext3 <2,3,4,5>, <4,5,4,5>
- 2980499460U, // <5,4,5,5>: Cost 3 vzipr RHS, <5,5,5,5>
- 1624886582U, // <5,4,5,6>: Cost 2 vext3 <2,3,4,5>, RHS
- 3923382430U, // <5,4,5,7>: Cost 4 vuzpr <5,1,7,3>, <5,7,4,6>
- 1624886600U, // <5,4,5,u>: Cost 2 vext3 <2,3,4,5>, RHS
- 2698628428U, // <5,4,6,0>: Cost 3 vext3 <2,3,4,5>, <4,6,0,2>
- 3765071188U, // <5,4,6,1>: Cost 4 vext3 <1,1,4,5>, <4,6,1,1>
- 2698628448U, // <5,4,6,2>: Cost 3 vext3 <2,3,4,5>, <4,6,2,4>
- 2712489322U, // <5,4,6,3>: Cost 3 vext3 <4,6,3,5>, <4,6,3,5>
- 2712857972U, // <5,4,6,4>: Cost 3 vext3 <4,6,u,5>, <4,6,4,6>
- 2980499554U, // <5,4,6,5>: Cost 3 vzipr RHS, <5,6,7,0>
- 4114630504U, // <5,4,6,6>: Cost 4 vtrnl <3,4,5,6>, <2,5,3,6>
- 2658128766U, // <5,4,6,7>: Cost 3 vext2 <6,7,5,4>, <6,7,5,4>
- 2712858007U, // <5,4,6,u>: Cost 3 vext3 <4,6,u,5>, <4,6,u,5>
- 2589638758U, // <5,4,7,0>: Cost 3 vext1 <6,5,4,7>, LHS
+ 3633506454U, // <5,4,5,3>: Cost 4 vext1 <1,5,4,5>, <3,0,1,2>
+ 2559765814U, // <5,4,5,4>: Cost 3 vext1 <1,5,4,5>, RHS
+ 2583654395U, // <5,4,5,5>: Cost 3 vext1 <5,5,4,5>, <5,5,4,5>
+ 1613385014U, // <5,4,5,6>: Cost 2 vext3 <0,4,1,5>, RHS
+ 3901639990U, // <5,4,5,7>: Cost 4 vuzpr <1,5,0,4>, RHS
+ 1613385032U, // <5,4,5,u>: Cost 2 vext3 <0,4,1,5>, RHS
+ 2559770726U, // <5,4,6,0>: Cost 3 vext1 <1,5,4,6>, LHS
+ 2559771648U, // <5,4,6,1>: Cost 3 vext1 <1,5,4,6>, <1,3,5,7>
+ 3633514088U, // <5,4,6,2>: Cost 4 vext1 <1,5,4,6>, <2,2,2,2>
+ 2571717122U, // <5,4,6,3>: Cost 3 vext1 <3,5,4,6>, <3,4,5,6>
+ 2559774006U, // <5,4,6,4>: Cost 3 vext1 <1,5,4,6>, RHS
+ 2712636796U, // <5,4,6,5>: Cost 3 vext3 <4,6,5,5>, <4,6,5,5>
+ 3760868743U, // <5,4,6,6>: Cost 4 vext3 <0,4,1,5>, <4,6,6,7>
+ 2712784270U, // <5,4,6,7>: Cost 3 vext3 <4,6,7,5>, <4,6,7,5>
+ 2559776558U, // <5,4,6,u>: Cost 3 vext1 <1,5,4,6>, LHS
+ 2565750886U, // <5,4,7,0>: Cost 3 vext1 <2,5,4,7>, LHS
2565751706U, // <5,4,7,1>: Cost 3 vext1 <2,5,4,7>, <1,2,3,4>
2565752690U, // <5,4,7,2>: Cost 3 vext1 <2,5,4,7>, <2,5,4,7>
2571725387U, // <5,4,7,3>: Cost 3 vext1 <3,5,4,7>, <3,5,4,7>
- 2589642038U, // <5,4,7,4>: Cost 3 vext1 <6,5,4,7>, RHS
- 2589642694U, // <5,4,7,5>: Cost 3 vext1 <6,5,4,7>, <5,4,7,6>
+ 2565754166U, // <5,4,7,4>: Cost 3 vext1 <2,5,4,7>, RHS
+ 3114713426U, // <5,4,7,5>: Cost 3 vtrnr RHS, <0,4,1,5>
94817590U, // <5,4,7,6>: Cost 1 vrev RHS
2595616175U, // <5,4,7,7>: Cost 3 vext1 <7,5,4,7>, <7,5,4,7>
94965064U, // <5,4,7,u>: Cost 1 vrev RHS
- 2698628590U, // <5,4,u,0>: Cost 3 vext3 <2,3,4,5>, <4,u,0,2>
- 2636896046U, // <5,4,u,1>: Cost 3 vext2 <3,2,5,4>, LHS
+ 2559787110U, // <5,4,u,0>: Cost 3 vext1 <1,5,4,u>, LHS
+ 2559788186U, // <5,4,u,1>: Cost 3 vext1 <1,5,4,u>, <1,5,4,u>
2242014483U, // <5,4,u,2>: Cost 3 vrev <4,5,2,u>
- 2713816588U, // <5,4,u,3>: Cost 3 vext3 <4,u,3,5>, <4,u,3,5>
- 2242161957U, // <5,4,u,4>: Cost 3 vrev <4,5,4,u>
+ 2667419628U, // <5,4,u,3>: Cost 3 vext2 <u,3,5,4>, <u,3,5,4>
+ 2559790390U, // <5,4,u,4>: Cost 3 vext1 <1,5,4,u>, RHS
1640222238U, // <5,4,u,5>: Cost 2 vext3 <4,u,5,5>, <4,u,5,5>
94825783U, // <5,4,u,6>: Cost 1 vrev RHS
- 2595624368U, // <5,4,u,7>: Cost 3 vext1 <7,5,4,u>, <7,5,4,u>
+ 2714111536U, // <5,4,u,7>: Cost 3 vext3 <4,u,7,5>, <4,u,7,5>
94973257U, // <5,4,u,u>: Cost 1 vrev RHS
- 2650832896U, // <5,5,0,0>: Cost 3 vext2 <5,5,5,5>, <0,0,0,0>
- 1577091174U, // <5,5,0,1>: Cost 2 vext2 <5,5,5,5>, LHS
- 2650833060U, // <5,5,0,2>: Cost 3 vext2 <5,5,5,5>, <0,2,0,2>
- 3645483597U, // <5,5,0,3>: Cost 4 vext1 <3,5,5,0>, <3,5,5,0>
- 2650833234U, // <5,5,0,4>: Cost 3 vext2 <5,5,5,5>, <0,4,1,5>
+ 2646851584U, // <5,5,0,0>: Cost 3 vext2 <4,u,5,5>, <0,0,0,0>
+ 1573109862U, // <5,5,0,1>: Cost 2 vext2 <4,u,5,5>, LHS
+ 2646851748U, // <5,5,0,2>: Cost 3 vext2 <4,u,5,5>, <0,2,0,2>
+ 3760279130U, // <5,5,0,3>: Cost 4 vext3 <0,3,2,5>, <5,0,3,2>
+ 2687127138U, // <5,5,0,4>: Cost 3 vext3 <0,4,1,5>, <5,0,4,1>
2248142847U, // <5,5,0,5>: Cost 3 vrev <5,5,5,0>
- 3724575213U, // <5,5,0,6>: Cost 4 vext2 <5,5,5,5>, <0,6,0,7>
- 3766029950U, // <5,5,0,7>: Cost 4 vext3 <1,2,u,5>, <5,0,7,2>
- 1577091741U, // <5,5,0,u>: Cost 2 vext2 <5,5,5,5>, LHS
- 2650833654U, // <5,5,1,0>: Cost 3 vext2 <5,5,5,5>, <1,0,3,2>
- 2909948818U, // <5,5,1,1>: Cost 3 vzipl <4,0,5,1>, <4,0,5,1>
- 2650833814U, // <5,5,1,2>: Cost 3 vext2 <5,5,5,5>, <1,2,3,0>
- 3645491790U, // <5,5,1,3>: Cost 4 vext1 <3,5,5,1>, <3,5,5,1>
+ 3720593910U, // <5,5,0,6>: Cost 4 vext2 <4,u,5,5>, <0,6,1,7>
+ 4182502710U, // <5,5,0,7>: Cost 4 vtrnr <3,5,7,0>, RHS
+ 1573110429U, // <5,5,0,u>: Cost 2 vext2 <4,u,5,5>, LHS
+ 2646852342U, // <5,5,1,0>: Cost 3 vext2 <4,u,5,5>, <1,0,3,2>
+ 2624291676U, // <5,5,1,1>: Cost 3 vext2 <1,1,5,5>, <1,1,5,5>
+ 2646852502U, // <5,5,1,2>: Cost 3 vext2 <4,u,5,5>, <1,2,3,0>
+ 2646852568U, // <5,5,1,3>: Cost 3 vext2 <4,u,5,5>, <1,3,1,3>
2715217591U, // <5,5,1,4>: Cost 3 vext3 <5,1,4,5>, <5,1,4,5>
- 2650834064U, // <5,5,1,5>: Cost 3 vext2 <5,5,5,5>, <1,5,3,7>
- 3980413842U, // <5,5,1,6>: Cost 4 vzipl <3,4,5,6>, <4,0,5,1>
- 2692288208U, // <5,5,1,7>: Cost 3 vext3 <1,2,u,5>, <5,1,7,3>
- 2698628825U, // <5,5,1,u>: Cost 3 vext3 <2,3,4,5>, <5,1,u,3>
- 3772370659U, // <5,5,2,0>: Cost 4 vext3 <2,3,4,5>, <5,2,0,4>
- 3772370667U, // <5,5,2,1>: Cost 4 vext3 <2,3,4,5>, <5,2,1,3>
- 2650834536U, // <5,5,2,2>: Cost 3 vext2 <5,5,5,5>, <2,2,2,2>
+ 2628936848U, // <5,5,1,5>: Cost 3 vext2 <1,u,5,5>, <1,5,3,7>
+ 3698033907U, // <5,5,1,6>: Cost 4 vext2 <1,1,5,5>, <1,6,5,7>
+ 2713964240U, // <5,5,1,7>: Cost 3 vext3 <4,u,5,5>, <5,1,7,3>
+ 2628937107U, // <5,5,1,u>: Cost 3 vext2 <1,u,5,5>, <1,u,5,5>
+ 3645497446U, // <5,5,2,0>: Cost 4 vext1 <3,5,5,2>, LHS
+ 3760869099U, // <5,5,2,1>: Cost 4 vext3 <0,4,1,5>, <5,2,1,3>
+ 2646853224U, // <5,5,2,2>: Cost 3 vext2 <4,u,5,5>, <2,2,2,2>
2698628862U, // <5,5,2,3>: Cost 3 vext3 <2,3,4,5>, <5,2,3,4>
- 3772370691U, // <5,5,2,4>: Cost 4 vext3 <2,3,4,5>, <5,2,4,0>
- 2711310095U, // <5,5,2,5>: Cost 3 vext3 <4,4,5,5>, <5,2,5,3>
- 2650834874U, // <5,5,2,6>: Cost 3 vext2 <5,5,5,5>, <2,6,3,7>
- 3759763232U, // <5,5,2,7>: Cost 4 vext3 <0,2,4,5>, <5,2,7,2>
+ 3772370694U, // <5,5,2,4>: Cost 4 vext3 <2,3,4,5>, <5,2,4,3>
+ 2713964303U, // <5,5,2,5>: Cost 3 vext3 <4,u,5,5>, <5,2,5,3>
+ 2646853562U, // <5,5,2,6>: Cost 3 vext2 <4,u,5,5>, <2,6,3,7>
+ 4038198272U, // <5,5,2,7>: Cost 4 vzipr <1,u,5,2>, <1,3,5,7>
2701946667U, // <5,5,2,u>: Cost 3 vext3 <2,u,4,5>, <5,2,u,4>
- 2650835094U, // <5,5,3,0>: Cost 3 vext2 <5,5,5,5>, <3,0,1,2>
- 3772370750U, // <5,5,3,1>: Cost 4 vext3 <2,3,4,5>, <5,3,1,5>
- 3772370757U, // <5,5,3,2>: Cost 4 vext3 <2,3,4,5>, <5,3,2,3>
+ 2646853782U, // <5,5,3,0>: Cost 3 vext2 <4,u,5,5>, <3,0,1,2>
+ 3698034922U, // <5,5,3,1>: Cost 4 vext2 <1,1,5,5>, <3,1,1,5>
+ 3702679919U, // <5,5,3,2>: Cost 4 vext2 <1,u,5,5>, <3,2,7,3>
2637564336U, // <5,5,3,3>: Cost 3 vext2 <3,3,5,5>, <3,3,5,5>
- 2650835458U, // <5,5,3,4>: Cost 3 vext2 <5,5,5,5>, <3,4,5,6>
+ 2646854146U, // <5,5,3,4>: Cost 3 vext2 <4,u,5,5>, <3,4,5,6>
2638891602U, // <5,5,3,5>: Cost 3 vext2 <3,5,5,5>, <3,5,5,5>
- 3790434155U, // <5,5,3,6>: Cost 4 vext3 <5,3,6,5>, <5,3,6,5>
- 2716766068U, // <5,5,3,7>: Cost 3 vext3 <5,3,7,5>, <5,3,7,5>
- 2650835742U, // <5,5,3,u>: Cost 3 vext2 <5,5,5,5>, <3,u,1,2>
- 2650835858U, // <5,5,4,0>: Cost 3 vext2 <5,5,5,5>, <4,0,5,1>
- 2716987279U, // <5,5,4,1>: Cost 3 vext3 <5,4,1,5>, <5,4,1,5>
- 3772370840U, // <5,5,4,2>: Cost 4 vext3 <2,3,4,5>, <5,4,2,5>
+ 3702680247U, // <5,5,3,6>: Cost 4 vext2 <1,u,5,5>, <3,6,7,7>
+ 3702680259U, // <5,5,3,7>: Cost 4 vext2 <1,u,5,5>, <3,7,0,1>
+ 2646854430U, // <5,5,3,u>: Cost 3 vext2 <4,u,5,5>, <3,u,1,2>
+ 2646854546U, // <5,5,4,0>: Cost 3 vext2 <4,u,5,5>, <4,0,5,1>
+ 2642209767U, // <5,5,4,1>: Cost 3 vext2 <4,1,5,5>, <4,1,5,5>
+ 3711306806U, // <5,5,4,2>: Cost 4 vext2 <3,3,5,5>, <4,2,5,3>
3645516369U, // <5,5,4,3>: Cost 4 vext1 <3,5,5,4>, <3,5,5,4>
1570458842U, // <5,5,4,4>: Cost 2 vext2 <4,4,5,5>, <4,4,5,5>
- 1577094454U, // <5,5,4,5>: Cost 2 vext2 <5,5,5,5>, RHS
- 2846281732U, // <5,5,4,6>: Cost 3 vuzpr RHS, <5,5,5,5>
- 2717945798U, // <5,5,4,7>: Cost 3 vext3 <5,5,5,5>, <5,4,7,6>
- 1577094697U, // <5,5,4,u>: Cost 2 vext2 <5,5,5,5>, RHS
+ 1573113142U, // <5,5,4,5>: Cost 2 vext2 <4,u,5,5>, RHS
+ 2645527932U, // <5,5,4,6>: Cost 3 vext2 <4,6,5,5>, <4,6,5,5>
+ 2713964486U, // <5,5,4,7>: Cost 3 vext3 <4,u,5,5>, <5,4,7,6>
+ 1573113374U, // <5,5,4,u>: Cost 2 vext2 <4,u,5,5>, <4,u,5,5>
1509982310U, // <5,5,5,0>: Cost 2 vext1 <5,5,5,5>, LHS
- 2583724790U, // <5,5,5,1>: Cost 3 vext1 <5,5,5,5>, <1,0,3,2>
+ 2646855376U, // <5,5,5,1>: Cost 3 vext2 <4,u,5,5>, <5,1,7,3>
2583725672U, // <5,5,5,2>: Cost 3 vext1 <5,5,5,5>, <2,2,2,2>
2583726230U, // <5,5,5,3>: Cost 3 vext1 <5,5,5,5>, <3,0,1,2>
1509985590U, // <5,5,5,4>: Cost 2 vext1 <5,5,5,5>, RHS
229035318U, // <5,5,5,5>: Cost 1 vdup1 RHS
- 2583728634U, // <5,5,5,6>: Cost 3 vext1 <5,5,5,5>, <6,2,7,3>
- 3047608324U, // <5,5,5,7>: Cost 3 vtrnl RHS, <5,5,5,5>
+ 2646855778U, // <5,5,5,6>: Cost 3 vext2 <4,u,5,5>, <5,6,7,0>
+ 2646855848U, // <5,5,5,7>: Cost 3 vext2 <4,u,5,5>, <5,7,5,7>
229035318U, // <5,5,5,u>: Cost 1 vdup1 RHS
- 3779596324U, // <5,5,6,0>: Cost 4 vext3 <3,5,3,5>, <5,6,0,1>
- 3983690242U, // <5,5,6,1>: Cost 4 vzipl <4,0,5,1>, <3,4,5,6>
- 2650837498U, // <5,5,6,2>: Cost 3 vext2 <5,5,5,5>, <6,2,7,3>
- 3779596354U, // <5,5,6,3>: Cost 4 vext3 <3,5,3,5>, <5,6,3,4>
+ 2577760358U, // <5,5,6,0>: Cost 3 vext1 <4,5,5,6>, LHS
+ 3633587361U, // <5,5,6,1>: Cost 4 vext1 <1,5,5,6>, <1,5,5,6>
+ 2646856186U, // <5,5,6,2>: Cost 3 vext2 <4,u,5,5>, <6,2,7,3>
+ 3633588738U, // <5,5,6,3>: Cost 4 vext1 <1,5,5,6>, <3,4,5,6>
2718535756U, // <5,5,6,4>: Cost 3 vext3 <5,6,4,5>, <5,6,4,5>
- 2717945943U, // <5,5,6,5>: Cost 3 vext3 <5,5,5,5>, <5,6,5,7>
- 2906671618U, // <5,5,6,6>: Cost 3 vzipl <3,4,5,6>, <3,4,5,6>
- 2717356130U, // <5,5,6,7>: Cost 3 vext3 <5,4,6,5>, <5,6,7,0>
- 2650837919U, // <5,5,6,u>: Cost 3 vext2 <5,5,5,5>, <6,u,0,1>
- 2650838010U, // <5,5,7,0>: Cost 3 vext2 <5,5,5,5>, <7,0,1,2>
- 4120857910U, // <5,5,7,1>: Cost 4 vtrnl <4,5,0,1>, RHS
- 4114894134U, // <5,5,7,2>: Cost 4 vtrnl <3,5,0,2>, RHS
+ 2644202223U, // <5,5,6,5>: Cost 3 vext2 <4,4,5,5>, <6,5,7,5>
+ 2973780482U, // <5,5,6,6>: Cost 3 vzipr <3,4,5,6>, <3,4,5,6>
+ 2646856526U, // <5,5,6,7>: Cost 3 vext2 <4,u,5,5>, <6,7,0,1>
+ 2646856607U, // <5,5,6,u>: Cost 3 vext2 <4,u,5,5>, <6,u,0,1>
+ 2571796582U, // <5,5,7,0>: Cost 3 vext1 <3,5,5,7>, LHS
+ 3633595392U, // <5,5,7,1>: Cost 4 vext1 <1,5,5,7>, <1,3,5,7>
+ 2571798222U, // <5,5,7,2>: Cost 3 vext1 <3,5,5,7>, <2,3,4,5>
2571799124U, // <5,5,7,3>: Cost 3 vext1 <3,5,5,7>, <3,5,5,7>
- 2650838374U, // <5,5,7,4>: Cost 3 vext2 <5,5,5,5>, <7,4,5,6>
- 2650838454U, // <5,5,7,5>: Cost 3 vext2 <5,5,5,5>, <7,5,5,5>
- 4193751138U, // <5,5,7,6>: Cost 4 vtrnr <5,4,6,5>, <5,6,7,0>
- 1973865782U, // <5,5,7,7>: Cost 2 vtrnl RHS, RHS
- 1973873974U, // <5,5,7,u>: Cost 2 vtrnl RHS, RHS
+ 2571799862U, // <5,5,7,4>: Cost 3 vext1 <3,5,5,7>, RHS
+ 3114717188U, // <5,5,7,5>: Cost 3 vtrnr RHS, <5,5,5,5>
+ 4034923010U, // <5,5,7,6>: Cost 4 vzipr <1,3,5,7>, <3,4,5,6>
+ 2040974646U, // <5,5,7,7>: Cost 2 vtrnr RHS, RHS
+ 2040974647U, // <5,5,7,u>: Cost 2 vtrnr RHS, RHS
1509982310U, // <5,5,u,0>: Cost 2 vext1 <5,5,5,5>, LHS
- 1577097006U, // <5,5,u,1>: Cost 2 vext2 <5,5,5,5>, LHS
- 2650838892U, // <5,5,u,2>: Cost 3 vext2 <5,5,5,5>, <u,2,0,2>
- 2650838972U, // <5,5,u,3>: Cost 3 vext2 <5,5,5,5>, <u,3,0,1>
- 1594349630U, // <5,5,u,4>: Cost 2 vext2 <u,4,5,5>, <u,4,5,5>
+ 1573115694U, // <5,5,u,1>: Cost 2 vext2 <4,u,5,5>, LHS
+ 2571806414U, // <5,5,u,2>: Cost 3 vext1 <3,5,5,u>, <2,3,4,5>
+ 2571807317U, // <5,5,u,3>: Cost 3 vext1 <3,5,5,u>, <3,5,5,u>
+ 1509985590U, // <5,5,u,4>: Cost 2 vext1 <5,5,5,5>, RHS
229035318U, // <5,5,u,5>: Cost 1 vdup1 RHS
- 2650839216U, // <5,5,u,6>: Cost 3 vext2 <5,5,5,5>, <u,6,0,2>
- 1973865783U, // <5,5,u,7>: Cost 2 vtrnl RHS, RHS
+ 2646857936U, // <5,5,u,6>: Cost 3 vext2 <4,u,5,5>, <u,6,3,7>
+ 2040982838U, // <5,5,u,7>: Cost 2 vtrnr RHS, RHS
229035318U, // <5,5,u,u>: Cost 1 vdup1 RHS
2638233600U, // <5,6,0,0>: Cost 3 vext2 <3,4,5,6>, <0,0,0,0>
1564491878U, // <5,6,0,1>: Cost 2 vext2 <3,4,5,6>, LHS
2632261796U, // <5,6,0,2>: Cost 3 vext2 <2,4,5,6>, <0,2,0,2>
- 2577787394U, // <5,6,0,3>: Cost 3 vext1 <4,5,6,0>, <3,4,5,6>
- 2577788207U, // <5,6,0,4>: Cost 3 vext1 <4,5,6,0>, <4,5,6,0>
- 3711975847U, // <5,6,0,5>: Cost 4 vext2 <3,4,5,6>, <0,5,2,0>
- 3651531041U, // <5,6,0,6>: Cost 4 vext1 <4,5,6,0>, <6,0,1,2>
- 3772371286U, // <5,6,0,7>: Cost 4 vext3 <2,3,4,5>, <6,0,7,1>
+ 2638233856U, // <5,6,0,3>: Cost 3 vext2 <3,4,5,6>, <0,3,1,4>
+ 2638233938U, // <5,6,0,4>: Cost 3 vext2 <3,4,5,6>, <0,4,1,5>
+ 3706003885U, // <5,6,0,5>: Cost 4 vext2 <2,4,5,6>, <0,5,2,6>
+ 3706003967U, // <5,6,0,6>: Cost 4 vext2 <2,4,5,6>, <0,6,2,7>
+ 4047473974U, // <5,6,0,7>: Cost 4 vzipr <3,4,5,0>, RHS
1564492445U, // <5,6,0,u>: Cost 2 vext2 <3,4,5,6>, LHS
2638234358U, // <5,6,1,0>: Cost 3 vext2 <3,4,5,6>, <1,0,3,2>
- 2626290484U, // <5,6,1,1>: Cost 3 vext2 <1,4,5,6>, <1,1,1,1>
+ 2638234420U, // <5,6,1,1>: Cost 3 vext2 <3,4,5,6>, <1,1,1,1>
2638234518U, // <5,6,1,2>: Cost 3 vext2 <3,4,5,6>, <1,2,3,0>
- 3711976398U, // <5,6,1,3>: Cost 4 vext2 <3,4,5,6>, <1,3,0,2>
+ 2638234584U, // <5,6,1,3>: Cost 3 vext2 <3,4,5,6>, <1,3,1,3>
2626290768U, // <5,6,1,4>: Cost 3 vext2 <1,4,5,6>, <1,4,5,6>
- 2662122640U, // <5,6,1,5>: Cost 3 vext2 <7,4,5,6>, <1,5,3,7>
- 3999730578U, // <5,6,1,6>: Cost 4 vzipl <6,6,6,6>, <4,0,5,1>
- 2913389458U, // <5,6,1,7>: Cost 3 vzipl RHS, <4,0,5,1>
+ 2638234768U, // <5,6,1,5>: Cost 3 vext2 <3,4,5,6>, <1,5,3,7>
+ 3700032719U, // <5,6,1,6>: Cost 4 vext2 <1,4,5,6>, <1,6,1,7>
+ 2982366518U, // <5,6,1,7>: Cost 3 vzipr <4,u,5,1>, RHS
2628945300U, // <5,6,1,u>: Cost 3 vext2 <1,u,5,6>, <1,u,5,6>
3706004925U, // <5,6,2,0>: Cost 4 vext2 <2,4,5,6>, <2,0,1,2>
- 3700033055U, // <5,6,2,1>: Cost 4 vext2 <1,4,5,6>, <2,1,3,1>
+ 3711976966U, // <5,6,2,1>: Cost 4 vext2 <3,4,5,6>, <2,1,0,3>
2638235240U, // <5,6,2,2>: Cost 3 vext2 <3,4,5,6>, <2,2,2,2>
2638235302U, // <5,6,2,3>: Cost 3 vext2 <3,4,5,6>, <2,3,0,1>
2632263465U, // <5,6,2,4>: Cost 3 vext2 <2,4,5,6>, <2,4,5,6>
2638235496U, // <5,6,2,5>: Cost 3 vext2 <3,4,5,6>, <2,5,3,6>
- 2662123450U, // <5,6,2,6>: Cost 3 vext2 <7,4,5,6>, <2,6,3,7>
- 2698629626U, // <5,6,2,7>: Cost 3 vext3 <2,3,4,5>, <6,2,7,3>
- 2698629635U, // <5,6,2,u>: Cost 3 vext3 <2,3,4,5>, <6,2,u,3>
+ 2638235578U, // <5,6,2,6>: Cost 3 vext2 <3,4,5,6>, <2,6,3,7>
+ 2713965050U, // <5,6,2,7>: Cost 3 vext3 <4,u,5,5>, <6,2,7,3>
+ 2634917997U, // <5,6,2,u>: Cost 3 vext2 <2,u,5,6>, <2,u,5,6>
2638235798U, // <5,6,3,0>: Cost 3 vext2 <3,4,5,6>, <3,0,1,2>
- 3700033766U, // <5,6,3,1>: Cost 4 vext2 <1,4,5,6>, <3,1,1,1>
- 3711977774U, // <5,6,3,2>: Cost 4 vext2 <3,4,5,6>, <3,2,0,1>
+ 3711977695U, // <5,6,3,1>: Cost 4 vext2 <3,4,5,6>, <3,1,0,3>
+ 3710650720U, // <5,6,3,2>: Cost 4 vext2 <3,2,5,6>, <3,2,5,6>
2638236060U, // <5,6,3,3>: Cost 3 vext2 <3,4,5,6>, <3,3,3,3>
1564494338U, // <5,6,3,4>: Cost 2 vext2 <3,4,5,6>, <3,4,5,6>
- 2638236194U, // <5,6,3,5>: Cost 3 vext2 <3,4,5,6>, <3,5,0,2>
- 3711978122U, // <5,6,3,6>: Cost 4 vext2 <3,4,5,6>, <3,6,2,7>
- 2662124267U, // <5,6,3,7>: Cost 3 vext2 <7,4,5,6>, <3,7,4,5>
+ 2638236234U, // <5,6,3,5>: Cost 3 vext2 <3,4,5,6>, <3,5,4,6>
+ 3711978104U, // <5,6,3,6>: Cost 4 vext2 <3,4,5,6>, <3,6,0,7>
+ 4034227510U, // <5,6,3,7>: Cost 4 vzipr <1,2,5,3>, RHS
1567148870U, // <5,6,3,u>: Cost 2 vext2 <3,u,5,6>, <3,u,5,6>
- 2638236562U, // <5,6,4,0>: Cost 3 vext2 <3,4,5,6>, <4,0,5,1>
- 2638236654U, // <5,6,4,1>: Cost 3 vext2 <3,4,5,6>, <4,1,6,3>
+ 2577817702U, // <5,6,4,0>: Cost 3 vext1 <4,5,6,4>, LHS
+ 3700034544U, // <5,6,4,1>: Cost 4 vext2 <1,4,5,6>, <4,1,6,5>
2723033713U, // <5,6,4,2>: Cost 3 vext3 <6,4,2,5>, <6,4,2,5>
2638236818U, // <5,6,4,3>: Cost 3 vext2 <3,4,5,6>, <4,3,6,5>
2644208859U, // <5,6,4,4>: Cost 3 vext2 <4,4,5,6>, <4,4,5,6>
1564495158U, // <5,6,4,5>: Cost 2 vext2 <3,4,5,6>, RHS
- 2638237004U, // <5,6,4,6>: Cost 3 vext2 <3,4,5,6>, <4,6,0,2>
+ 2645536125U, // <5,6,4,6>: Cost 3 vext2 <4,6,5,6>, <4,6,5,6>
2723402398U, // <5,6,4,7>: Cost 3 vext3 <6,4,7,5>, <6,4,7,5>
1564495401U, // <5,6,4,u>: Cost 2 vext2 <3,4,5,6>, RHS
- 3711979079U, // <5,6,5,0>: Cost 4 vext2 <3,4,5,6>, <5,0,1,1>
- 2638237392U, // <5,6,5,1>: Cost 3 vext2 <3,4,5,6>, <5,1,7,3>
- 2638237464U, // <5,6,5,2>: Cost 3 vext2 <3,4,5,6>, <5,2,6,3>
+ 2577825894U, // <5,6,5,0>: Cost 3 vext1 <4,5,6,5>, LHS
+ 2662125264U, // <5,6,5,1>: Cost 3 vext2 <7,4,5,6>, <5,1,7,3>
+ 3775836867U, // <5,6,5,2>: Cost 4 vext3 <2,u,6,5>, <6,5,2,6>
3711979343U, // <5,6,5,3>: Cost 4 vext2 <3,4,5,6>, <5,3,3,4>
2650181556U, // <5,6,5,4>: Cost 3 vext2 <5,4,5,6>, <5,4,5,6>
2662125572U, // <5,6,5,5>: Cost 3 vext2 <7,4,5,6>, <5,5,5,5>
2638237732U, // <5,6,5,6>: Cost 3 vext2 <3,4,5,6>, <5,6,0,1>
- 2913390596U, // <5,6,5,7>: Cost 3 vzipl RHS, <5,5,5,5>
- 2638237950U, // <5,6,5,u>: Cost 3 vext2 <3,4,5,6>, <5,u,6,3>
+ 2982399286U, // <5,6,5,7>: Cost 3 vzipr <4,u,5,5>, RHS
+ 2982399287U, // <5,6,5,u>: Cost 3 vzipr <4,u,5,5>, RHS
2583806054U, // <5,6,6,0>: Cost 3 vext1 <5,5,6,6>, LHS
- 3700036007U, // <5,6,6,1>: Cost 4 vext2 <1,4,5,6>, <6,1,7,1>
- 2638238202U, // <5,6,6,2>: Cost 3 vext2 <3,4,5,6>, <6,2,7,3>
+ 3711979910U, // <5,6,6,1>: Cost 4 vext2 <3,4,5,6>, <6,1,3,4>
+ 2662126074U, // <5,6,6,2>: Cost 3 vext2 <7,4,5,6>, <6,2,7,3>
2583808514U, // <5,6,6,3>: Cost 3 vext1 <5,5,6,6>, <3,4,5,6>
2583809334U, // <5,6,6,4>: Cost 3 vext1 <5,5,6,6>, RHS
2583810062U, // <5,6,6,5>: Cost 3 vext1 <5,5,6,6>, <5,5,6,6>
2638238520U, // <5,6,6,6>: Cost 3 vext2 <3,4,5,6>, <6,6,6,6>
- 2913389058U, // <5,6,6,7>: Cost 3 vzipl RHS, <3,4,5,6>
- 2638238688U, // <5,6,6,u>: Cost 3 vext2 <3,4,5,6>, <6,u,7,3>
+ 2973781302U, // <5,6,6,7>: Cost 3 vzipr <3,4,5,6>, RHS
+ 2973781303U, // <5,6,6,u>: Cost 3 vzipr <3,4,5,6>, RHS
430358630U, // <5,6,7,0>: Cost 1 vext1 RHS, LHS
1504101110U, // <5,6,7,1>: Cost 2 vext1 RHS, <1,0,3,2>
1504101992U, // <5,6,7,2>: Cost 2 vext1 RHS, <2,2,2,2>
1504102550U, // <5,6,7,3>: Cost 2 vext1 RHS, <3,0,1,2>
430361910U, // <5,6,7,4>: Cost 1 vext1 RHS, RHS
- 1504104144U, // <5,6,7,5>: Cost 2 vext1 RHS, <5,1,7,3>
- 1504104954U, // <5,6,7,6>: Cost 2 vext1 RHS, <6,2,7,3>
+ 1504104390U, // <5,6,7,5>: Cost 2 vext1 RHS, <5,4,7,6>
+ 1504105272U, // <5,6,7,6>: Cost 2 vext1 RHS, <6,6,6,6>
1504106092U, // <5,6,7,7>: Cost 2 vext1 RHS, <7,7,7,7>
430364462U, // <5,6,7,u>: Cost 1 vext1 RHS, LHS
430366822U, // <5,6,u,0>: Cost 1 vext1 RHS, LHS
@@ -4233,1443 +4233,1443 @@ static const unsigned PerfectShuffleTable[6561+1] = {
1504113146U, // <5,6,u,6>: Cost 2 vext1 RHS, <6,2,7,3>
1504113658U, // <5,6,u,7>: Cost 2 vext1 RHS, <7,0,1,2>
430372654U, // <5,6,u,u>: Cost 1 vext1 RHS, LHS
- 3893661392U, // <5,7,0,0>: Cost 4 vuzpr <0,2,0,2>, <5,1,7,3>
- 2645540966U, // <5,7,0,1>: Cost 3 vext2 <4,6,5,7>, LHS
- 2819452624U, // <5,7,0,2>: Cost 3 vuzpr LHS, <5,1,7,3>
- 3645631071U, // <5,7,0,3>: Cost 4 vext1 <3,5,7,0>, <3,5,7,0>
- 2726499352U, // <5,7,0,4>: Cost 3 vext3 <7,0,4,5>, <7,0,4,5>
- 3645632208U, // <5,7,0,5>: Cost 4 vext1 <3,5,7,0>, <5,1,7,3>
- 3663549162U, // <5,7,0,6>: Cost 4 vext1 <6,5,7,0>, <6,5,7,0>
- 3657577466U, // <5,7,0,7>: Cost 4 vext1 <5,5,7,0>, <7,0,1,2>
- 2819854032U, // <5,7,0,u>: Cost 3 vuzpr LHS, <5,1,7,3>
- 2589810790U, // <5,7,1,0>: Cost 3 vext1 <6,5,7,1>, LHS
- 3899035344U, // <5,7,1,1>: Cost 4 vuzpr <1,1,1,1>, <5,1,7,3>
- 3719283606U, // <5,7,1,2>: Cost 4 vext2 <4,6,5,7>, <1,2,3,0>
- 3898527440U, // <5,7,1,3>: Cost 4 vuzpr <1,0,3,2>, <5,1,7,3>
- 2589813650U, // <5,7,1,4>: Cost 3 vext1 <6,5,7,1>, <4,0,5,1>
- 3719283856U, // <5,7,1,5>: Cost 4 vext2 <4,6,5,7>, <1,5,3,7>
- 2589815531U, // <5,7,1,6>: Cost 3 vext1 <6,5,7,1>, <6,5,7,1>
- 3993176978U, // <5,7,1,7>: Cost 4 vzipl <5,5,7,7>, <4,0,5,1>
- 2589816622U, // <5,7,1,u>: Cost 3 vext1 <6,5,7,1>, LHS
- 3906260688U, // <5,7,2,0>: Cost 4 vuzpr <2,3,0,1>, <5,1,7,3>
- 3904351952U, // <5,7,2,1>: Cost 5 vuzpr <2,0,1,2>, <5,1,7,3>
- 3905752784U, // <5,7,2,2>: Cost 4 vuzpr <2,2,2,2>, <5,1,7,3>
- 2645542606U, // <5,7,2,3>: Cost 3 vext2 <4,6,5,7>, <2,3,4,5>
- 3906588368U, // <5,7,2,4>: Cost 4 vuzpr <2,3,4,5>, <5,1,7,3>
- 3906629328U, // <5,7,2,5>: Cost 4 vuzpr <2,3,5,1>, <5,1,7,3>
- 3719284666U, // <5,7,2,6>: Cost 4 vext2 <4,6,5,7>, <2,6,3,7>
- 3725920263U, // <5,7,2,7>: Cost 4 vext2 <5,7,5,7>, <2,7,3,3>
- 2645542606U, // <5,7,2,u>: Cost 3 vext2 <4,6,5,7>, <2,3,4,5>
- 3719284886U, // <5,7,3,0>: Cost 4 vext2 <4,6,5,7>, <3,0,1,2>
- 3910323920U, // <5,7,3,1>: Cost 4 vuzpr <3,0,1,2>, <5,1,7,3>
- 3719285068U, // <5,7,3,2>: Cost 4 vext2 <4,6,5,7>, <3,2,3,4>
- 3912470224U, // <5,7,3,3>: Cost 4 vuzpr <3,3,3,3>, <5,1,7,3>
- 2728490251U, // <5,7,3,4>: Cost 3 vext3 <7,3,4,5>, <7,3,4,5>
- 2638907988U, // <5,7,3,5>: Cost 3 vext2 <3,5,5,7>, <3,5,5,7>
- 3796776218U, // <5,7,3,6>: Cost 4 vext3 <6,4,2,5>, <7,3,6,2>
- 3802453286U, // <5,7,3,7>: Cost 4 vext3 <7,3,7,5>, <7,3,7,5>
- 2728785199U, // <5,7,3,u>: Cost 3 vext3 <7,3,u,5>, <7,3,u,5>
- 2728858936U, // <5,7,4,0>: Cost 3 vext3 <7,4,0,5>, <7,4,0,5>
- 3802674497U, // <5,7,4,1>: Cost 4 vext3 <7,4,1,5>, <7,4,1,5>
- 3719285814U, // <5,7,4,2>: Cost 4 vext2 <4,6,5,7>, <4,2,5,3>
- 3802821971U, // <5,7,4,3>: Cost 4 vext3 <7,4,3,5>, <7,4,3,5>
- 2652843226U, // <5,7,4,4>: Cost 3 vext2 <5,u,5,7>, <4,4,5,5>
- 2645544246U, // <5,7,4,5>: Cost 3 vext2 <4,6,5,7>, RHS
- 2846281424U, // <5,7,4,6>: Cost 3 vuzpr RHS, <5,1,7,3>
- 2729375095U, // <5,7,4,7>: Cost 3 vext3 <7,4,7,5>, <7,4,7,5>
- 2846428880U, // <5,7,4,u>: Cost 3 vuzpr RHS, <5,1,7,3>
- 2589843558U, // <5,7,5,0>: Cost 3 vext1 <6,5,7,5>, LHS
+ 2625634304U, // <5,7,0,0>: Cost 3 vext2 <1,3,5,7>, <0,0,0,0>
+ 1551892582U, // <5,7,0,1>: Cost 2 vext2 <1,3,5,7>, LHS
+ 2625634468U, // <5,7,0,2>: Cost 3 vext2 <1,3,5,7>, <0,2,0,2>
+ 2571889247U, // <5,7,0,3>: Cost 3 vext1 <3,5,7,0>, <3,5,7,0>
+ 2625634642U, // <5,7,0,4>: Cost 3 vext2 <1,3,5,7>, <0,4,1,5>
+ 2595778728U, // <5,7,0,5>: Cost 3 vext1 <7,5,7,0>, <5,7,5,7>
+ 3699376639U, // <5,7,0,6>: Cost 4 vext2 <1,3,5,7>, <0,6,2,7>
+ 2260235715U, // <5,7,0,7>: Cost 3 vrev <7,5,7,0>
+ 1551893149U, // <5,7,0,u>: Cost 2 vext2 <1,3,5,7>, LHS
+ 2625635062U, // <5,7,1,0>: Cost 3 vext2 <1,3,5,7>, <1,0,3,2>
+ 2624308020U, // <5,7,1,1>: Cost 3 vext2 <1,1,5,7>, <1,1,1,1>
+ 2625635222U, // <5,7,1,2>: Cost 3 vext2 <1,3,5,7>, <1,2,3,0>
+ 1551893504U, // <5,7,1,3>: Cost 2 vext2 <1,3,5,7>, <1,3,5,7>
+ 2571898166U, // <5,7,1,4>: Cost 3 vext1 <3,5,7,1>, RHS
+ 2625635472U, // <5,7,1,5>: Cost 3 vext2 <1,3,5,7>, <1,5,3,7>
+ 2627626227U, // <5,7,1,6>: Cost 3 vext2 <1,6,5,7>, <1,6,5,7>
+ 3702031684U, // <5,7,1,7>: Cost 4 vext2 <1,7,5,7>, <1,7,5,7>
+ 1555211669U, // <5,7,1,u>: Cost 2 vext2 <1,u,5,7>, <1,u,5,7>
+ 2629617126U, // <5,7,2,0>: Cost 3 vext2 <2,0,5,7>, <2,0,5,7>
+ 3699377670U, // <5,7,2,1>: Cost 4 vext2 <1,3,5,7>, <2,1,0,3>
+ 2625635944U, // <5,7,2,2>: Cost 3 vext2 <1,3,5,7>, <2,2,2,2>
+ 2625636006U, // <5,7,2,3>: Cost 3 vext2 <1,3,5,7>, <2,3,0,1>
+ 2632271658U, // <5,7,2,4>: Cost 3 vext2 <2,4,5,7>, <2,4,5,7>
+ 2625636201U, // <5,7,2,5>: Cost 3 vext2 <1,3,5,7>, <2,5,3,7>
+ 2625636282U, // <5,7,2,6>: Cost 3 vext2 <1,3,5,7>, <2,6,3,7>
+ 3708004381U, // <5,7,2,7>: Cost 4 vext2 <2,7,5,7>, <2,7,5,7>
+ 2625636411U, // <5,7,2,u>: Cost 3 vext2 <1,3,5,7>, <2,u,0,1>
+ 2625636502U, // <5,7,3,0>: Cost 3 vext2 <1,3,5,7>, <3,0,1,2>
+ 2625636604U, // <5,7,3,1>: Cost 3 vext2 <1,3,5,7>, <3,1,3,5>
+ 3699378478U, // <5,7,3,2>: Cost 4 vext2 <1,3,5,7>, <3,2,0,1>
+ 2625636764U, // <5,7,3,3>: Cost 3 vext2 <1,3,5,7>, <3,3,3,3>
+ 2625636866U, // <5,7,3,4>: Cost 3 vext2 <1,3,5,7>, <3,4,5,6>
+ 2625636959U, // <5,7,3,5>: Cost 3 vext2 <1,3,5,7>, <3,5,7,0>
+ 3699378808U, // <5,7,3,6>: Cost 4 vext2 <1,3,5,7>, <3,6,0,7>
+ 2640235254U, // <5,7,3,7>: Cost 3 vext2 <3,7,5,7>, <3,7,5,7>
+ 2625637150U, // <5,7,3,u>: Cost 3 vext2 <1,3,5,7>, <3,u,1,2>
+ 2571919462U, // <5,7,4,0>: Cost 3 vext1 <3,5,7,4>, LHS
+ 2571920384U, // <5,7,4,1>: Cost 3 vext1 <3,5,7,4>, <1,3,5,7>
+ 3699379260U, // <5,7,4,2>: Cost 4 vext2 <1,3,5,7>, <4,2,6,0>
+ 2571922019U, // <5,7,4,3>: Cost 3 vext1 <3,5,7,4>, <3,5,7,4>
+ 2571922742U, // <5,7,4,4>: Cost 3 vext1 <3,5,7,4>, RHS
+ 1551895862U, // <5,7,4,5>: Cost 2 vext2 <1,3,5,7>, RHS
+ 2846277980U, // <5,7,4,6>: Cost 3 vuzpr RHS, <0,4,2,6>
+ 2646207951U, // <5,7,4,7>: Cost 3 vext2 <4,7,5,7>, <4,7,5,7>
+ 1551896105U, // <5,7,4,u>: Cost 2 vext2 <1,3,5,7>, RHS
+ 2583871590U, // <5,7,5,0>: Cost 3 vext1 <5,5,7,5>, LHS
2652180176U, // <5,7,5,1>: Cost 3 vext2 <5,7,5,7>, <5,1,7,3>
- 3719286526U, // <5,7,5,2>: Cost 4 vext2 <4,6,5,7>, <5,2,3,4>
- 3719286644U, // <5,7,5,3>: Cost 4 vext2 <4,6,5,7>, <5,3,7,5>
- 2589846838U, // <5,7,5,4>: Cost 3 vext1 <6,5,7,5>, RHS
- 2717947318U, // <5,7,5,5>: Cost 3 vext3 <5,5,5,5>, <7,5,5,5>
+ 2625638177U, // <5,7,5,2>: Cost 3 vext2 <1,3,5,7>, <5,2,7,3>
+ 2625638262U, // <5,7,5,3>: Cost 3 vext2 <1,3,5,7>, <5,3,7,7>
+ 2583874870U, // <5,7,5,4>: Cost 3 vext1 <5,5,7,5>, RHS
+ 2846281732U, // <5,7,5,5>: Cost 3 vuzpr RHS, <5,5,5,5>
2651517015U, // <5,7,5,6>: Cost 3 vext2 <5,6,5,7>, <5,6,5,7>
- 2849640144U, // <5,7,5,7>: Cost 3 vuzpr <5,1,7,3>, <5,1,7,3>
- 2652844281U, // <5,7,5,u>: Cost 3 vext2 <5,u,5,7>, <5,u,5,7>
- 2589851750U, // <5,7,6,0>: Cost 3 vext1 <6,5,7,6>, LHS
- 3663594230U, // <5,7,6,1>: Cost 4 vext1 <6,5,7,6>, <1,0,3,2>
- 3719287290U, // <5,7,6,2>: Cost 4 vext2 <4,6,5,7>, <6,2,7,3>
+ 1772539190U, // <5,7,5,7>: Cost 2 vuzpr RHS, RHS
+ 1772539191U, // <5,7,5,u>: Cost 2 vuzpr RHS, RHS
+ 2846281826U, // <5,7,6,0>: Cost 3 vuzpr RHS, <5,6,7,0>
+ 3699380615U, // <5,7,6,1>: Cost 4 vext2 <1,3,5,7>, <6,1,3,5>
+ 2846281108U, // <5,7,6,2>: Cost 3 vuzpr RHS, <4,6,u,2>
2589854210U, // <5,7,6,3>: Cost 3 vext1 <6,5,7,6>, <3,4,5,6>
- 2589855030U, // <5,7,6,4>: Cost 3 vext1 <6,5,7,6>, RHS
+ 2846281830U, // <5,7,6,4>: Cost 3 vuzpr RHS, <5,6,7,4>
2725467658U, // <5,7,6,5>: Cost 3 vext3 <6,7,u,5>, <7,6,5,u>
- 2589856496U, // <5,7,6,6>: Cost 3 vext1 <6,5,7,6>, <6,5,7,6>
- 2725172760U, // <5,7,6,7>: Cost 3 vext3 <6,7,4,5>, <7,6,7,4>
- 2589857582U, // <5,7,6,u>: Cost 3 vext1 <6,5,7,6>, LHS
+ 2846281076U, // <5,7,6,6>: Cost 3 vuzpr RHS, <4,6,4,6>
+ 2846279610U, // <5,7,6,7>: Cost 3 vuzpr RHS, <2,6,3,7>
+ 2846279611U, // <5,7,6,u>: Cost 3 vuzpr RHS, <2,6,3,u>
1510146150U, // <5,7,7,0>: Cost 2 vext1 <5,5,7,7>, LHS
- 2583888630U, // <5,7,7,1>: Cost 3 vext1 <5,5,7,7>, <1,0,3,2>
+ 2846282574U, // <5,7,7,1>: Cost 3 vuzpr RHS, <6,7,0,1>
2583889512U, // <5,7,7,2>: Cost 3 vext1 <5,5,7,7>, <2,2,2,2>
- 2583890070U, // <5,7,7,3>: Cost 3 vext1 <5,5,7,7>, <3,0,1,2>
+ 2846281919U, // <5,7,7,3>: Cost 3 vuzpr RHS, <5,7,u,3>
1510149430U, // <5,7,7,4>: Cost 2 vext1 <5,5,7,7>, RHS
1510150168U, // <5,7,7,5>: Cost 2 vext1 <5,5,7,7>, <5,5,7,7>
2583892474U, // <5,7,7,6>: Cost 3 vext1 <5,5,7,7>, <6,2,7,3>
- 2717947500U, // <5,7,7,7>: Cost 3 vext3 <5,5,5,5>, <7,7,7,7>
+ 2625640044U, // <5,7,7,7>: Cost 3 vext2 <1,3,5,7>, <7,7,7,7>
1510151982U, // <5,7,7,u>: Cost 2 vext1 <5,5,7,7>, LHS
1510154342U, // <5,7,u,0>: Cost 2 vext1 <5,5,7,u>, LHS
- 2645546798U, // <5,7,u,1>: Cost 3 vext2 <4,6,5,7>, LHS
- 2583897704U, // <5,7,u,2>: Cost 3 vext1 <5,5,7,u>, <2,2,2,2>
- 2583898262U, // <5,7,u,3>: Cost 3 vext1 <5,5,7,u>, <3,0,1,2>
+ 1551898414U, // <5,7,u,1>: Cost 2 vext2 <1,3,5,7>, LHS
+ 2625640325U, // <5,7,u,2>: Cost 3 vext2 <1,3,5,7>, <u,2,3,0>
+ 1772536477U, // <5,7,u,3>: Cost 2 vuzpr RHS, LHS
1510157622U, // <5,7,u,4>: Cost 2 vext1 <5,5,7,u>, RHS
- 1510158361U, // <5,7,u,5>: Cost 2 vext1 <5,5,7,u>, <5,5,7,u>
- 2583900666U, // <5,7,u,6>: Cost 3 vext1 <5,5,7,u>, <6,2,7,3>
- 2583901178U, // <5,7,u,7>: Cost 3 vext1 <5,5,7,u>, <7,0,1,2>
- 1510160174U, // <5,7,u,u>: Cost 2 vext1 <5,5,7,u>, LHS
- 2638249984U, // <5,u,0,0>: Cost 3 vext2 <3,4,5,u>, <0,0,0,0>
- 1564508262U, // <5,u,0,1>: Cost 2 vext2 <3,4,5,u>, LHS
- 2819452633U, // <5,u,0,2>: Cost 3 vuzpr LHS, <5,1,u,3>
+ 1551898778U, // <5,7,u,5>: Cost 2 vext2 <1,3,5,7>, RHS
+ 2625640656U, // <5,7,u,6>: Cost 3 vext2 <1,3,5,7>, <u,6,3,7>
+ 1772539433U, // <5,7,u,7>: Cost 2 vuzpr RHS, RHS
+ 1551898981U, // <5,7,u,u>: Cost 2 vext2 <1,3,5,7>, LHS
+ 2625642496U, // <5,u,0,0>: Cost 3 vext2 <1,3,5,u>, <0,0,0,0>
+ 1551900774U, // <5,u,0,1>: Cost 2 vext2 <1,3,5,u>, LHS
+ 2625642660U, // <5,u,0,2>: Cost 3 vext2 <1,3,5,u>, <0,2,0,2>
2698630885U, // <5,u,0,3>: Cost 3 vext3 <2,3,4,5>, <u,0,3,2>
- 2577935681U, // <5,u,0,4>: Cost 3 vext1 <4,5,u,0>, <4,5,u,0>
- 2698630902U, // <5,u,0,5>: Cost 3 vext3 <2,3,4,5>, <u,0,5,1>
- 2698630912U, // <5,u,0,6>: Cost 3 vext3 <2,3,4,5>, <u,0,6,2>
- 3772372744U, // <5,u,0,7>: Cost 4 vext3 <2,3,4,5>, <u,0,7,1>
- 1564508829U, // <5,u,0,u>: Cost 2 vext2 <3,4,5,u>, LHS
- 2638250742U, // <5,u,1,0>: Cost 3 vext2 <3,4,5,u>, <1,0,3,2>
- 2626306868U, // <5,u,1,1>: Cost 3 vext2 <1,4,5,u>, <1,1,1,1>
- 1624889134U, // <5,u,1,2>: Cost 2 vext3 <2,3,4,5>, LHS
- 2886962066U, // <5,u,1,3>: Cost 3 vzipl LHS, <4,0,5,1>
+ 2687129325U, // <5,u,0,4>: Cost 3 vext3 <0,4,1,5>, <u,0,4,1>
+ 2689783542U, // <5,u,0,5>: Cost 3 vext3 <0,u,1,5>, <u,0,5,1>
+ 2266134675U, // <5,u,0,6>: Cost 3 vrev <u,5,6,0>
+ 2595853772U, // <5,u,0,7>: Cost 3 vext1 <7,5,u,0>, <7,5,u,0>
+ 1551901341U, // <5,u,0,u>: Cost 2 vext2 <1,3,5,u>, LHS
+ 2625643254U, // <5,u,1,0>: Cost 3 vext2 <1,3,5,u>, <1,0,3,2>
+ 2625643316U, // <5,u,1,1>: Cost 3 vext2 <1,3,5,u>, <1,1,1,1>
+ 1613387566U, // <5,u,1,2>: Cost 2 vext3 <0,4,1,5>, LHS
+ 1551901697U, // <5,u,1,3>: Cost 2 vext2 <1,3,5,u>, <1,3,5,u>
2626307154U, // <5,u,1,4>: Cost 3 vext2 <1,4,5,u>, <1,4,5,u>
- 2701948745U, // <5,u,1,5>: Cost 3 vext3 <2,u,4,5>, <u,1,5,3>
- 2589889268U, // <5,u,1,6>: Cost 3 vext1 <6,5,u,1>, <6,5,u,1>
- 2698631003U, // <5,u,1,7>: Cost 3 vext3 <2,3,4,5>, <u,1,7,3>
- 1624889188U, // <5,u,1,u>: Cost 2 vext3 <2,3,4,5>, LHS
- 2698631020U, // <5,u,2,0>: Cost 3 vext3 <2,3,4,5>, <u,2,0,2>
- 3700049439U, // <5,u,2,1>: Cost 4 vext2 <1,4,5,u>, <2,1,3,1>
- 2638251624U, // <5,u,2,2>: Cost 3 vext2 <3,4,5,u>, <2,2,2,2>
- 2698631045U, // <5,u,2,3>: Cost 3 vext3 <2,3,4,5>, <u,2,3,0>
+ 2689783622U, // <5,u,1,5>: Cost 3 vext3 <0,u,1,5>, <u,1,5,0>
+ 2627634420U, // <5,u,1,6>: Cost 3 vext2 <1,6,5,u>, <1,6,5,u>
+ 2982366536U, // <5,u,1,7>: Cost 3 vzipr <4,u,5,1>, RHS
+ 1613387620U, // <5,u,1,u>: Cost 2 vext3 <0,4,1,5>, LHS
+ 2846286742U, // <5,u,2,0>: Cost 3 vuzpr RHS, <1,2,3,0>
+ 2685796528U, // <5,u,2,1>: Cost 3 vext3 <0,2,1,5>, <0,2,1,5>
+ 2625644136U, // <5,u,2,2>: Cost 3 vext2 <1,3,5,u>, <2,2,2,2>
+ 2687129480U, // <5,u,2,3>: Cost 3 vext3 <0,4,1,5>, <u,2,3,3>
2632279851U, // <5,u,2,4>: Cost 3 vext2 <2,4,5,u>, <2,4,5,u>
- 2698925978U, // <5,u,2,5>: Cost 3 vext3 <2,3,u,5>, <u,2,5,3>
- 2662139834U, // <5,u,2,6>: Cost 3 vext2 <7,4,5,u>, <2,6,3,7>
- 2698631084U, // <5,u,2,7>: Cost 3 vext3 <2,3,4,5>, <u,2,7,3>
- 2698631090U, // <5,u,2,u>: Cost 3 vext3 <2,3,4,5>, <u,2,u,0>
- 2698631100U, // <5,u,3,0>: Cost 3 vext3 <2,3,4,5>, <u,3,0,1>
+ 2625644394U, // <5,u,2,5>: Cost 3 vext2 <1,3,5,u>, <2,5,3,u>
+ 2625644474U, // <5,u,2,6>: Cost 3 vext2 <1,3,5,u>, <2,6,3,7>
+ 2713966508U, // <5,u,2,7>: Cost 3 vext3 <4,u,5,5>, <u,2,7,3>
+ 2625644603U, // <5,u,2,u>: Cost 3 vext2 <1,3,5,u>, <2,u,0,1>
+ 2687129532U, // <5,u,3,0>: Cost 3 vext3 <0,4,1,5>, <u,3,0,1>
2636261649U, // <5,u,3,1>: Cost 3 vext2 <3,1,5,u>, <3,1,5,u>
2636925282U, // <5,u,3,2>: Cost 3 vext2 <3,2,5,u>, <3,2,5,u>
- 2638252444U, // <5,u,3,3>: Cost 3 vext2 <3,4,5,u>, <3,3,3,3>
+ 2625644956U, // <5,u,3,3>: Cost 3 vext2 <1,3,5,u>, <3,3,3,3>
1564510724U, // <5,u,3,4>: Cost 2 vext2 <3,4,5,u>, <3,4,5,u>
- 2734536685U, // <5,u,3,5>: Cost 3 vext3 <u,3,5,5>, <u,3,5,5>
+ 2625645160U, // <5,u,3,5>: Cost 3 vext2 <1,3,5,u>, <3,5,u,0>
2734610422U, // <5,u,3,6>: Cost 3 vext3 <u,3,6,5>, <u,3,6,5>
- 2734684159U, // <5,u,3,7>: Cost 3 vext3 <u,3,7,5>, <u,3,7,5>
+ 2640243447U, // <5,u,3,7>: Cost 3 vext2 <3,7,5,u>, <3,7,5,u>
1567165256U, // <5,u,3,u>: Cost 2 vext2 <3,u,5,u>, <3,u,5,u>
1567828889U, // <5,u,4,0>: Cost 2 vext2 <4,0,5,u>, <4,0,5,u>
1661163546U, // <5,u,4,1>: Cost 2 vext3 <u,4,1,5>, <u,4,1,5>
- 2642897979U, // <5,u,4,2>: Cost 3 vext2 <4,2,5,u>, <4,2,5,u>
- 2638253220U, // <5,u,4,3>: Cost 3 vext2 <3,4,5,u>, <4,3,u,5>
+ 2734463012U, // <5,u,4,2>: Cost 3 vext3 <u,3,4,5>, <u,4,2,6>
+ 2698631212U, // <5,u,4,3>: Cost 3 vext3 <2,3,4,5>, <u,4,3,5>
1570458842U, // <5,u,4,4>: Cost 2 vext2 <4,4,5,5>, <4,4,5,5>
- 1564511542U, // <5,u,4,5>: Cost 2 vext2 <3,4,5,u>, RHS
- 2638253388U, // <5,u,4,6>: Cost 3 vext2 <3,4,5,u>, <4,6,0,2>
- 2717947985U, // <5,u,4,7>: Cost 3 vext3 <5,5,5,5>, <u,4,7,6>
- 1564511785U, // <5,u,4,u>: Cost 2 vext2 <3,4,5,u>, RHS
+ 1551904054U, // <5,u,4,5>: Cost 2 vext2 <1,3,5,u>, RHS
+ 2846286172U, // <5,u,4,6>: Cost 3 vuzpr RHS, <0,4,2,6>
+ 2646216144U, // <5,u,4,7>: Cost 3 vext2 <4,7,5,u>, <4,7,5,u>
+ 1551904297U, // <5,u,4,u>: Cost 2 vext2 <1,3,5,u>, RHS
1509982310U, // <5,u,5,0>: Cost 2 vext1 <5,5,5,5>, LHS
- 2638253776U, // <5,u,5,1>: Cost 3 vext2 <3,4,5,u>, <5,1,7,3>
+ 2560058555U, // <5,u,5,1>: Cost 3 vext1 <1,5,u,5>, <1,5,u,5>
2698926194U, // <5,u,5,2>: Cost 3 vext3 <2,3,u,5>, <u,5,2,3>
- 2717948031U, // <5,u,5,3>: Cost 3 vext3 <5,5,5,5>, <u,5,3,7>
+ 2698631295U, // <5,u,5,3>: Cost 3 vext3 <2,3,4,5>, <u,5,3,7>
1509985590U, // <5,u,5,4>: Cost 2 vext1 <5,5,5,5>, RHS
229035318U, // <5,u,5,5>: Cost 1 vdup1 RHS
- 1624889498U, // <5,u,5,6>: Cost 2 vext3 <2,3,4,5>, RHS
- 2913537242U, // <5,u,5,7>: Cost 3 vzipl RHS, <4,4,5,5>
+ 1613387930U, // <5,u,5,6>: Cost 2 vext3 <0,4,1,5>, RHS
+ 1772547382U, // <5,u,5,7>: Cost 2 vuzpr RHS, RHS
229035318U, // <5,u,5,u>: Cost 1 vdup1 RHS
- 2698631344U, // <5,u,6,0>: Cost 3 vext3 <2,3,4,5>, <u,6,0,2>
- 3001405538U, // <5,u,6,1>: Cost 3 vzipr LHS, <5,6,7,0>
- 2638254586U, // <5,u,6,2>: Cost 3 vext2 <3,4,5,u>, <6,2,7,3>
- 2886961666U, // <5,u,6,3>: Cost 3 vzipl LHS, <3,4,5,6>
- 2717948120U, // <5,u,6,4>: Cost 3 vext3 <5,5,5,5>, <u,6,4,6>
- 2726131939U, // <5,u,6,5>: Cost 3 vext3 <6,u,u,5>, <u,6,5,u>
- 2662142776U, // <5,u,6,6>: Cost 3 vext2 <7,4,5,u>, <6,6,6,6>
- 2913536514U, // <5,u,6,7>: Cost 3 vzipl RHS, <3,4,5,6>
- 2887002626U, // <5,u,6,u>: Cost 3 vzipl LHS, <3,4,5,6>
+ 2566037606U, // <5,u,6,0>: Cost 3 vext1 <2,5,u,6>, LHS
+ 2920044334U, // <5,u,6,1>: Cost 3 vzipl <5,6,7,0>, LHS
+ 2566039445U, // <5,u,6,2>: Cost 3 vext1 <2,5,u,6>, <2,5,u,6>
+ 2687129808U, // <5,u,6,3>: Cost 3 vext3 <0,4,1,5>, <u,6,3,7>
+ 2566040886U, // <5,u,6,4>: Cost 3 vext1 <2,5,u,6>, RHS
+ 2920044698U, // <5,u,6,5>: Cost 3 vzipl <5,6,7,0>, RHS
+ 2846289268U, // <5,u,6,6>: Cost 3 vuzpr RHS, <4,6,4,6>
+ 2973781320U, // <5,u,6,7>: Cost 3 vzipr <3,4,5,6>, RHS
+ 2687129853U, // <5,u,6,u>: Cost 3 vext3 <0,4,1,5>, <u,6,u,7>
430506086U, // <5,u,7,0>: Cost 1 vext1 RHS, LHS
- 1504248566U, // <5,u,7,1>: Cost 2 vext1 RHS, <1,0,3,2>
+ 1486333117U, // <5,u,7,1>: Cost 2 vext1 <1,5,u,7>, <1,5,u,7>
1504249448U, // <5,u,7,2>: Cost 2 vext1 RHS, <2,2,2,2>
- 1951640886U, // <5,u,7,3>: Cost 2 vtrnl LHS, RHS
+ 2040971933U, // <5,u,7,3>: Cost 2 vtrnr RHS, LHS
430509384U, // <5,u,7,4>: Cost 1 vext1 RHS, RHS
1504251600U, // <5,u,7,5>: Cost 2 vext1 RHS, <5,1,7,3>
118708378U, // <5,u,7,6>: Cost 1 vrev RHS
- 1504252922U, // <5,u,7,7>: Cost 2 vext1 RHS, <7,0,1,2>
+ 2040974889U, // <5,u,7,7>: Cost 2 vtrnr RHS, RHS
430511918U, // <5,u,7,u>: Cost 1 vext1 RHS, LHS
430514278U, // <5,u,u,0>: Cost 1 vext1 RHS, LHS
- 1564514094U, // <5,u,u,1>: Cost 2 vext2 <3,4,5,u>, LHS
- 1624889701U, // <5,u,u,2>: Cost 2 vext3 <2,3,4,5>, LHS
- 1951640887U, // <5,u,u,3>: Cost 2 vtrnl LHS, RHS
+ 1551906606U, // <5,u,u,1>: Cost 2 vext2 <1,3,5,u>, LHS
+ 1613388133U, // <5,u,u,2>: Cost 2 vext3 <0,4,1,5>, LHS
+ 1772544669U, // <5,u,u,3>: Cost 2 vuzpr RHS, LHS
430517577U, // <5,u,u,4>: Cost 1 vext1 RHS, RHS
229035318U, // <5,u,u,5>: Cost 1 vdup1 RHS
118716571U, // <5,u,u,6>: Cost 1 vrev RHS
- 1504261114U, // <5,u,u,7>: Cost 2 vext1 RHS, <7,0,1,2>
+ 1772547625U, // <5,u,u,7>: Cost 2 vuzpr RHS, RHS
430520110U, // <5,u,u,u>: Cost 1 vext1 RHS, LHS
- 2705342464U, // <6,0,0,0>: Cost 3 vext3 <3,4,5,6>, <0,0,0,0>
- 2705342474U, // <6,0,0,1>: Cost 3 vext3 <3,4,5,6>, <0,0,1,1>
- 2705342484U, // <6,0,0,2>: Cost 3 vext3 <3,4,5,6>, <0,0,2,2>
- 3651750038U, // <6,0,0,3>: Cost 4 vext1 <4,6,0,0>, <3,0,1,2>
- 2578009398U, // <6,0,0,4>: Cost 3 vext1 <4,6,0,0>, RHS
- 3651751632U, // <6,0,0,5>: Cost 4 vext1 <4,6,0,0>, <5,1,7,3>
- 3715318246U, // <6,0,0,6>: Cost 4 vext2 <4,0,6,0>, <0,6,0,0>
- 3651752954U, // <6,0,0,7>: Cost 4 vext1 <4,6,0,0>, <7,0,1,2>
- 2705342537U, // <6,0,0,u>: Cost 3 vext3 <3,4,5,6>, <0,0,u,1>
- 2583986278U, // <6,0,1,0>: Cost 3 vext1 <5,6,0,1>, LHS
- 4027412860U, // <6,0,1,1>: Cost 4 vzipr LHS, <6,1,2,3>
- 1631600742U, // <6,0,1,2>: Cost 2 vext3 <3,4,5,6>, LHS
+ 2686025728U, // <6,0,0,0>: Cost 3 vext3 <0,2,4,6>, <0,0,0,0>
+ 2686025738U, // <6,0,0,1>: Cost 3 vext3 <0,2,4,6>, <0,0,1,1>
+ 2686025748U, // <6,0,0,2>: Cost 3 vext3 <0,2,4,6>, <0,0,2,2>
+ 3779084320U, // <6,0,0,3>: Cost 4 vext3 <3,4,5,6>, <0,0,3,5>
+ 2642903388U, // <6,0,0,4>: Cost 3 vext2 <4,2,6,0>, <0,4,2,6>
+ 3657723939U, // <6,0,0,5>: Cost 4 vext1 <5,6,0,0>, <5,6,0,0>
+ 3926676514U, // <6,0,0,6>: Cost 4 vuzpr <5,6,7,0>, <7,0,5,6>
+ 3926675786U, // <6,0,0,7>: Cost 4 vuzpr <5,6,7,0>, <6,0,5,7>
+ 2686025802U, // <6,0,0,u>: Cost 3 vext3 <0,2,4,6>, <0,0,u,2>
+ 2566070374U, // <6,0,1,0>: Cost 3 vext1 <2,6,0,1>, LHS
+ 3759767642U, // <6,0,1,1>: Cost 4 vext3 <0,2,4,6>, <0,1,1,0>
+ 1612284006U, // <6,0,1,2>: Cost 2 vext3 <0,2,4,6>, LHS
2583988738U, // <6,0,1,3>: Cost 3 vext1 <5,6,0,1>, <3,4,5,6>
- 2583989558U, // <6,0,1,4>: Cost 3 vext1 <5,6,0,1>, RHS
+ 2566073654U, // <6,0,1,4>: Cost 3 vext1 <2,6,0,1>, RHS
2583990308U, // <6,0,1,5>: Cost 3 vext1 <5,6,0,1>, <5,6,0,1>
2589963005U, // <6,0,1,6>: Cost 3 vext1 <6,6,0,1>, <6,6,0,1>
2595935702U, // <6,0,1,7>: Cost 3 vext1 <7,6,0,1>, <7,6,0,1>
- 1631600796U, // <6,0,1,u>: Cost 2 vext3 <3,4,5,6>, LHS
- 1504280678U, // <6,0,2,0>: Cost 2 vext1 <4,6,0,2>, LHS
- 2953630202U, // <6,0,2,1>: Cost 3 vzipr LHS, <6,2,7,3>
- 2578024040U, // <6,0,2,2>: Cost 3 vext1 <4,6,0,2>, <2,2,2,2>
- 2642904742U, // <6,0,2,3>: Cost 3 vext2 <4,2,6,0>, <2,3,0,1>
- 1504283958U, // <6,0,2,4>: Cost 2 vext1 <4,6,0,2>, RHS
- 2578026192U, // <6,0,2,5>: Cost 3 vext1 <4,6,0,2>, <5,1,7,3>
- 2578026792U, // <6,0,2,6>: Cost 3 vext1 <4,6,0,2>, <6,0,2,0>
- 2578027514U, // <6,0,2,7>: Cost 3 vext1 <4,6,0,2>, <7,0,1,2>
- 1504286510U, // <6,0,2,u>: Cost 2 vext1 <4,6,0,2>, LHS
- 3712002198U, // <6,0,3,0>: Cost 4 vext2 <3,4,6,0>, <3,0,1,2>
- 4027372082U, // <6,0,3,1>: Cost 4 vzipr LHS, <6,3,4,5>
- 4099853654U, // <6,0,3,2>: Cost 4 vtrnl <1,0,3,2>, <4,6,1,3>
- 3712002460U, // <6,0,3,3>: Cost 4 vext2 <3,4,6,0>, <3,3,3,3>
- 2638260741U, // <6,0,3,4>: Cost 3 vext2 <3,4,6,0>, <3,4,6,0>
- 3718638114U, // <6,0,3,5>: Cost 4 vext2 <4,5,6,0>, <3,5,0,2>
- 3669693288U, // <6,0,3,6>: Cost 4 vext1 <7,6,0,3>, <6,7,3,0>
- 3669693912U, // <6,0,3,7>: Cost 4 vext1 <7,6,0,3>, <7,6,0,3>
- 2640915273U, // <6,0,3,u>: Cost 3 vext2 <3,u,6,0>, <3,u,6,0>
- 2641578906U, // <6,0,4,0>: Cost 3 vext2 <4,0,6,0>, <4,0,6,0>
- 2712568146U, // <6,0,4,1>: Cost 3 vext3 <4,6,4,6>, <0,4,1,5>
+ 1612284060U, // <6,0,1,u>: Cost 2 vext3 <0,2,4,6>, LHS
+ 2686025892U, // <6,0,2,0>: Cost 3 vext3 <0,2,4,6>, <0,2,0,2>
+ 2685804721U, // <6,0,2,1>: Cost 3 vext3 <0,2,1,6>, <0,2,1,6>
+ 3759620282U, // <6,0,2,2>: Cost 4 vext3 <0,2,2,6>, <0,2,2,6>
+ 2705342658U, // <6,0,2,3>: Cost 3 vext3 <3,4,5,6>, <0,2,3,5>
+ 1612284108U, // <6,0,2,4>: Cost 2 vext3 <0,2,4,6>, <0,2,4,6>
+ 3706029956U, // <6,0,2,5>: Cost 4 vext2 <2,4,6,0>, <2,5,6,7>
+ 2686173406U, // <6,0,2,6>: Cost 3 vext3 <0,2,6,6>, <0,2,6,6>
+ 3651769338U, // <6,0,2,7>: Cost 4 vext1 <4,6,0,2>, <7,0,1,2>
+ 1612579056U, // <6,0,2,u>: Cost 2 vext3 <0,2,u,6>, <0,2,u,6>
+ 3706030230U, // <6,0,3,0>: Cost 4 vext2 <2,4,6,0>, <3,0,1,2>
+ 2705342720U, // <6,0,3,1>: Cost 3 vext3 <3,4,5,6>, <0,3,1,4>
+ 2705342730U, // <6,0,3,2>: Cost 3 vext3 <3,4,5,6>, <0,3,2,5>
+ 3706030492U, // <6,0,3,3>: Cost 4 vext2 <2,4,6,0>, <3,3,3,3>
+ 2644896258U, // <6,0,3,4>: Cost 3 vext2 <4,5,6,0>, <3,4,5,6>
+ 3718638154U, // <6,0,3,5>: Cost 4 vext2 <4,5,6,0>, <3,5,4,6>
+ 3729918619U, // <6,0,3,6>: Cost 4 vext2 <6,4,6,0>, <3,6,4,6>
+ 3926672384U, // <6,0,3,7>: Cost 4 vuzpr <5,6,7,0>, <1,3,5,7>
+ 2705342784U, // <6,0,3,u>: Cost 3 vext3 <3,4,5,6>, <0,3,u,5>
+ 2687058250U, // <6,0,4,0>: Cost 3 vext3 <0,4,0,6>, <0,4,0,6>
+ 2686026066U, // <6,0,4,1>: Cost 3 vext3 <0,2,4,6>, <0,4,1,5>
1613463900U, // <6,0,4,2>: Cost 2 vext3 <0,4,2,6>, <0,4,2,6>
- 3712003165U, // <6,0,4,3>: Cost 4 vext2 <3,4,6,0>, <4,3,0,6>
- 2645560548U, // <6,0,4,4>: Cost 3 vext2 <4,6,6,0>, <4,4,6,6>
- 2638261558U, // <6,0,4,5>: Cost 3 vext2 <3,4,6,0>, RHS
- 2638261580U, // <6,0,4,6>: Cost 3 vext2 <3,4,6,0>, <4,6,0,2>
+ 3761021285U, // <6,0,4,3>: Cost 4 vext3 <0,4,3,6>, <0,4,3,6>
+ 2687353198U, // <6,0,4,4>: Cost 3 vext3 <0,4,4,6>, <0,4,4,6>
+ 2632289590U, // <6,0,4,5>: Cost 3 vext2 <2,4,6,0>, RHS
+ 2645560704U, // <6,0,4,6>: Cost 3 vext2 <4,6,6,0>, <4,6,6,0>
2646224337U, // <6,0,4,7>: Cost 3 vext2 <4,7,6,0>, <4,7,6,0>
- 1613463900U, // <6,0,4,u>: Cost 2 vext3 <0,4,2,6>, <0,4,2,6>
- 3786310044U, // <6,0,5,0>: Cost 4 vext3 <4,6,4,6>, <0,5,0,7>
- 3712003792U, // <6,0,5,1>: Cost 4 vext2 <3,4,6,0>, <5,1,7,3>
- 3779084711U, // <6,0,5,2>: Cost 4 vext3 <3,4,5,6>, <0,5,2,0>
- 3716648816U, // <6,0,5,3>: Cost 4 vext2 <4,2,6,0>, <5,3,7,1>
+ 1613906322U, // <6,0,4,u>: Cost 2 vext3 <0,4,u,6>, <0,4,u,6>
+ 3651788902U, // <6,0,5,0>: Cost 4 vext1 <4,6,0,5>, LHS
+ 2687795620U, // <6,0,5,1>: Cost 3 vext3 <0,5,1,6>, <0,5,1,6>
+ 3761611181U, // <6,0,5,2>: Cost 4 vext3 <0,5,2,6>, <0,5,2,6>
+ 3723284326U, // <6,0,5,3>: Cost 4 vext2 <5,3,6,0>, <5,3,6,0>
2646224838U, // <6,0,5,4>: Cost 3 vext2 <4,7,6,0>, <5,4,7,6>
3718639630U, // <6,0,5,5>: Cost 4 vext2 <4,5,6,0>, <5,5,6,6>
- 3718639652U, // <6,0,5,6>: Cost 4 vext2 <4,5,6,0>, <5,6,0,1>
- 3923383118U, // <6,0,5,7>: Cost 4 vuzpr <5,1,7,3>, <6,7,0,1>
- 2646224838U, // <6,0,5,u>: Cost 3 vext2 <4,7,6,0>, <5,4,7,6>
- 2859062094U, // <6,0,6,0>: Cost 3 vuzpr <6,7,0,1>, <6,7,0,1>
- 2953630520U, // <6,0,6,1>: Cost 3 vzipr LHS, <6,6,6,6>
- 3087848248U, // <6,0,6,2>: Cost 3 vtrnr LHS, <6,6,6,6>
- 3778716165U, // <6,0,6,3>: Cost 4 vext3 <3,4,0,6>, <0,6,3,4>
+ 2652196962U, // <6,0,5,6>: Cost 3 vext2 <5,7,6,0>, <5,6,7,0>
+ 2852932918U, // <6,0,5,7>: Cost 3 vuzpr <5,6,7,0>, RHS
+ 2852932919U, // <6,0,5,u>: Cost 3 vuzpr <5,6,7,0>, RHS
+ 2852933730U, // <6,0,6,0>: Cost 3 vuzpr <5,6,7,0>, <5,6,7,0>
+ 2925985894U, // <6,0,6,1>: Cost 3 vzipl <6,6,6,6>, LHS
+ 3060203622U, // <6,0,6,2>: Cost 3 vtrnl <6,6,6,6>, LHS
+ 3718640178U, // <6,0,6,3>: Cost 4 vext2 <4,5,6,0>, <6,3,4,5>
2656178832U, // <6,0,6,4>: Cost 3 vext2 <6,4,6,0>, <6,4,6,0>
- 3718640368U, // <6,0,6,5>: Cost 4 vext2 <4,5,6,0>, <6,5,7,6>
+ 3725939378U, // <6,0,6,5>: Cost 4 vext2 <5,7,6,0>, <6,5,0,7>
2657506098U, // <6,0,6,6>: Cost 3 vext2 <6,6,6,0>, <6,6,6,0>
- 2669450062U, // <6,0,6,7>: Cost 3 vext2 <u,6,6,0>, <6,7,0,1>
- 2859062094U, // <6,0,6,u>: Cost 3 vuzpr <6,7,0,1>, <6,7,0,1>
- 2885684534U, // <6,0,7,0>: Cost 3 vzipl <0,0,0,0>, RHS
- 2899627318U, // <6,0,7,1>: Cost 3 vzipl <2,3,0,1>, RHS
- 3087847930U, // <6,0,7,2>: Cost 3 vtrnr LHS, <6,2,7,3>
- 3960778038U, // <6,0,7,3>: Cost 4 vzipl <0,2,0,3>, RHS
- 2662151529U, // <6,0,7,4>: Cost 3 vext2 <7,4,6,0>, <7,4,6,0>
- 3980037430U, // <6,0,7,5>: Cost 4 vzipl <3,4,0,5>, RHS
- 3980045622U, // <6,0,7,6>: Cost 4 vzipl <3,4,0,6>, RHS
- 3719304812U, // <6,0,7,7>: Cost 4 vext2 <4,6,6,0>, <7,7,7,7>
- 3088290298U, // <6,0,7,u>: Cost 3 vtrnr LHS, <6,2,7,3>
- 1504329830U, // <6,0,u,0>: Cost 2 vext1 <4,6,0,u>, LHS
- 2954073056U, // <6,0,u,1>: Cost 3 vzipr LHS, <6,u,7,3>
- 1631601309U, // <6,0,u,2>: Cost 2 vext3 <3,4,5,6>, LHS
- 2578073750U, // <6,0,u,3>: Cost 3 vext1 <4,6,0,u>, <3,0,1,2>
- 1504333110U, // <6,0,u,4>: Cost 2 vext1 <4,6,0,u>, RHS
- 2638264474U, // <6,0,u,5>: Cost 3 vext2 <3,4,6,0>, RHS
- 2640918704U, // <6,0,u,6>: Cost 3 vext2 <3,u,6,0>, <u,6,0,2>
- 2578076666U, // <6,0,u,7>: Cost 3 vext1 <4,6,0,u>, <7,0,1,2>
- 1631601363U, // <6,0,u,u>: Cost 2 vext3 <3,4,5,6>, LHS
+ 2619020110U, // <6,0,6,7>: Cost 3 vext2 <0,2,6,0>, <6,7,0,1>
+ 2925986461U, // <6,0,6,u>: Cost 3 vzipl <6,6,6,6>, LHS
+ 2572091494U, // <6,0,7,0>: Cost 3 vext1 <3,6,0,7>, LHS
+ 2572092310U, // <6,0,7,1>: Cost 3 vext1 <3,6,0,7>, <1,2,3,0>
+ 2980495524U, // <6,0,7,2>: Cost 3 vzipr RHS, <0,2,0,2>
+ 2572094072U, // <6,0,7,3>: Cost 3 vext1 <3,6,0,7>, <3,6,0,7>
+ 2572094774U, // <6,0,7,4>: Cost 3 vext1 <3,6,0,7>, RHS
+ 4054238242U, // <6,0,7,5>: Cost 4 vzipr RHS, <1,4,0,5>
+ 3645837653U, // <6,0,7,6>: Cost 4 vext1 <3,6,0,7>, <6,0,7,0>
+ 4054239054U, // <6,0,7,7>: Cost 4 vzipr RHS, <2,5,0,7>
+ 2572097326U, // <6,0,7,u>: Cost 3 vext1 <3,6,0,7>, LHS
+ 2686026378U, // <6,0,u,0>: Cost 3 vext3 <0,2,4,6>, <0,u,0,2>
+ 2686026386U, // <6,0,u,1>: Cost 3 vext3 <0,2,4,6>, <0,u,1,1>
+ 1612284573U, // <6,0,u,2>: Cost 2 vext3 <0,2,4,6>, LHS
+ 2705343144U, // <6,0,u,3>: Cost 3 vext3 <3,4,5,6>, <0,u,3,5>
+ 1616265906U, // <6,0,u,4>: Cost 2 vext3 <0,u,4,6>, <0,u,4,6>
+ 2632292506U, // <6,0,u,5>: Cost 3 vext2 <2,4,6,0>, RHS
+ 2590020356U, // <6,0,u,6>: Cost 3 vext1 <6,6,0,u>, <6,6,0,u>
+ 2852933161U, // <6,0,u,7>: Cost 3 vuzpr <5,6,7,0>, RHS
+ 1612284627U, // <6,0,u,u>: Cost 2 vext3 <0,2,4,6>, LHS
2595995750U, // <6,1,0,0>: Cost 3 vext1 <7,6,1,0>, LHS
- 2641584230U, // <6,1,0,1>: Cost 3 vext2 <4,0,6,1>, LHS
- 3779085036U, // <6,1,0,2>: Cost 4 vext3 <3,4,5,6>, <1,0,2,1>
- 2705343222U, // <6,1,0,3>: Cost 3 vext3 <3,4,5,6>, <1,0,3,2>
+ 2646229094U, // <6,1,0,1>: Cost 3 vext2 <4,7,6,1>, LHS
+ 3694092492U, // <6,1,0,2>: Cost 4 vext2 <0,4,6,1>, <0,2,4,6>
+ 2686026486U, // <6,1,0,3>: Cost 3 vext3 <0,2,4,6>, <1,0,3,2>
2595999030U, // <6,1,0,4>: Cost 3 vext1 <7,6,1,0>, RHS
- 3657797676U, // <6,1,0,5>: Cost 4 vext1 <5,6,1,0>, <5,6,1,0>
+ 3767730952U, // <6,1,0,5>: Cost 4 vext3 <1,5,4,6>, <1,0,5,2>
2596000590U, // <6,1,0,6>: Cost 3 vext1 <7,6,1,0>, <6,7,0,1>
2596001246U, // <6,1,0,7>: Cost 3 vext1 <7,6,1,0>, <7,6,1,0>
- 2705343267U, // <6,1,0,u>: Cost 3 vext3 <3,4,5,6>, <1,0,u,2>
- 2578088038U, // <6,1,1,0>: Cost 3 vext1 <4,6,1,1>, LHS
- 2693399348U, // <6,1,1,1>: Cost 3 vext3 <1,4,5,6>, <1,1,1,1>
- 3715326870U, // <6,1,1,2>: Cost 4 vext2 <4,0,6,1>, <1,2,3,0>
- 2705343304U, // <6,1,1,3>: Cost 3 vext3 <3,4,5,6>, <1,1,3,3>
- 2578091318U, // <6,1,1,4>: Cost 3 vext1 <4,6,1,1>, RHS
- 3651833550U, // <6,1,1,5>: Cost 4 vext1 <4,6,1,1>, <5,1,7,1>
- 3715990728U, // <6,1,1,6>: Cost 4 vext2 <4,1,6,1>, <1,6,1,0>
- 3651834874U, // <6,1,1,7>: Cost 4 vext1 <4,6,1,1>, <7,0,1,2>
- 2705343349U, // <6,1,1,u>: Cost 3 vext3 <3,4,5,6>, <1,1,u,3>
+ 2686026531U, // <6,1,0,u>: Cost 3 vext3 <0,2,4,6>, <1,0,u,2>
+ 3763602219U, // <6,1,1,0>: Cost 4 vext3 <0,u,2,6>, <1,1,0,1>
+ 2686026548U, // <6,1,1,1>: Cost 3 vext3 <0,2,4,6>, <1,1,1,1>
+ 3764929346U, // <6,1,1,2>: Cost 4 vext3 <1,1,2,6>, <1,1,2,6>
+ 2686026568U, // <6,1,1,3>: Cost 3 vext3 <0,2,4,6>, <1,1,3,3>
+ 2691334996U, // <6,1,1,4>: Cost 3 vext3 <1,1,4,6>, <1,1,4,6>
+ 3760874332U, // <6,1,1,5>: Cost 4 vext3 <0,4,1,6>, <1,1,5,5>
+ 3765224294U, // <6,1,1,6>: Cost 4 vext3 <1,1,6,6>, <1,1,6,6>
+ 3669751263U, // <6,1,1,7>: Cost 4 vext1 <7,6,1,1>, <7,6,1,1>
+ 2686026613U, // <6,1,1,u>: Cost 3 vext3 <0,2,4,6>, <1,1,u,3>
2554208358U, // <6,1,2,0>: Cost 3 vext1 <0,6,1,2>, LHS
- 3966143388U, // <6,1,2,1>: Cost 4 vzipl <1,1,1,1>, <4,0,6,2>
- 4034056698U, // <6,1,2,2>: Cost 4 vzipr <1,2,3,0>, <6,2,7,3>
- 3020737868U, // <6,1,2,3>: Cost 3 vtrnl LHS, <4,6,0,2>
+ 3763602311U, // <6,1,2,1>: Cost 4 vext3 <0,u,2,6>, <1,2,1,3>
+ 3639895971U, // <6,1,2,2>: Cost 4 vext1 <2,6,1,2>, <2,6,1,2>
+ 2686026646U, // <6,1,2,3>: Cost 3 vext3 <0,2,4,6>, <1,2,3,0>
2554211638U, // <6,1,2,4>: Cost 3 vext1 <0,6,1,2>, RHS
- 3657814062U, // <6,1,2,5>: Cost 4 vext1 <5,6,1,2>, <5,6,1,2>
+ 3760874411U, // <6,1,2,5>: Cost 4 vext3 <0,4,1,6>, <1,2,5,3>
2554212858U, // <6,1,2,6>: Cost 3 vext1 <0,6,1,2>, <6,2,7,3>
- 3800908730U, // <6,1,2,7>: Cost 4 vext3 <7,1,4,6>, <1,2,7,0>
- 3020778828U, // <6,1,2,u>: Cost 3 vtrnl LHS, <4,6,0,2>
- 2643576982U, // <6,1,3,0>: Cost 3 vext2 <4,3,6,1>, <3,0,1,2>
- 2578105078U, // <6,1,3,1>: Cost 3 vext1 <4,6,1,3>, <1,0,3,2>
- 4034056776U, // <6,1,3,2>: Cost 4 vzipr <1,2,3,0>, <6,3,7,0>
- 3766330349U, // <6,1,3,3>: Cost 4 vext3 <1,3,3,6>, <1,3,3,6>
- 2578107702U, // <6,1,3,4>: Cost 3 vext1 <4,6,1,3>, RHS
- 3913306401U, // <6,1,3,5>: Cost 4 vuzpr <3,4,5,6>, <6,0,1,2>
- 3709356682U, // <6,1,3,6>: Cost 4 vext2 <3,0,6,1>, <3,6,2,7>
- 3651851258U, // <6,1,3,7>: Cost 4 vext1 <4,6,1,3>, <7,0,1,2>
- 2578110254U, // <6,1,3,u>: Cost 3 vext1 <4,6,1,3>, LHS
+ 3802973114U, // <6,1,2,7>: Cost 4 vext3 <7,4,5,6>, <1,2,7,0>
+ 2686026691U, // <6,1,2,u>: Cost 3 vext3 <0,2,4,6>, <1,2,u,0>
+ 2566160486U, // <6,1,3,0>: Cost 3 vext1 <2,6,1,3>, LHS
+ 2686026712U, // <6,1,3,1>: Cost 3 vext3 <0,2,4,6>, <1,3,1,3>
+ 2686026724U, // <6,1,3,2>: Cost 3 vext3 <0,2,4,6>, <1,3,2,6>
+ 3759768552U, // <6,1,3,3>: Cost 4 vext3 <0,2,4,6>, <1,3,3,1>
+ 2692662262U, // <6,1,3,4>: Cost 3 vext3 <1,3,4,6>, <1,3,4,6>
+ 2686026752U, // <6,1,3,5>: Cost 3 vext3 <0,2,4,6>, <1,3,5,7>
+ 2590053128U, // <6,1,3,6>: Cost 3 vext1 <6,6,1,3>, <6,6,1,3>
+ 3663795194U, // <6,1,3,7>: Cost 4 vext1 <6,6,1,3>, <7,0,1,2>
+ 2686026775U, // <6,1,3,u>: Cost 3 vext3 <0,2,4,6>, <1,3,u,3>
2641587099U, // <6,1,4,0>: Cost 3 vext2 <4,0,6,1>, <4,0,6,1>
- 2642250732U, // <6,1,4,1>: Cost 3 vext2 <4,1,6,1>, <4,1,6,1>
- 3716656189U, // <6,1,4,2>: Cost 4 vext2 <4,2,6,1>, <4,2,6,1>
- 2643577998U, // <6,1,4,3>: Cost 3 vext2 <4,3,6,1>, <4,3,6,1>
- 3651857718U, // <6,1,4,4>: Cost 4 vext1 <4,6,1,4>, RHS
+ 2693104684U, // <6,1,4,1>: Cost 3 vext3 <1,4,1,6>, <1,4,1,6>
+ 3639912357U, // <6,1,4,2>: Cost 4 vext1 <2,6,1,4>, <2,6,1,4>
+ 2687206462U, // <6,1,4,3>: Cost 3 vext3 <0,4,2,6>, <1,4,3,6>
+ 3633941814U, // <6,1,4,4>: Cost 4 vext1 <1,6,1,4>, RHS
2693399632U, // <6,1,4,5>: Cost 3 vext3 <1,4,5,6>, <1,4,5,6>
- 2641587532U, // <6,1,4,6>: Cost 3 vext2 <4,0,6,1>, <4,6,0,2>
- 3298837762U, // <6,1,4,7>: Cost 4 vrev <1,6,7,4>
- 2693620843U, // <6,1,4,u>: Cost 3 vext3 <1,4,u,6>, <1,4,u,6>
+ 3765077075U, // <6,1,4,6>: Cost 4 vext3 <1,1,4,6>, <1,4,6,0>
+ 2646232530U, // <6,1,4,7>: Cost 3 vext2 <4,7,6,1>, <4,7,6,1>
+ 2687206507U, // <6,1,4,u>: Cost 3 vext3 <0,4,2,6>, <1,4,u,6>
2647559796U, // <6,1,5,0>: Cost 3 vext2 <5,0,6,1>, <5,0,6,1>
- 3767141496U, // <6,1,5,1>: Cost 4 vext3 <1,4,5,6>, <1,5,1,1>
+ 3765077118U, // <6,1,5,1>: Cost 4 vext3 <1,1,4,6>, <1,5,1,7>
3767583878U, // <6,1,5,2>: Cost 4 vext3 <1,5,2,6>, <1,5,2,6>
- 2712568976U, // <6,1,5,3>: Cost 3 vext3 <4,6,4,6>, <1,5,3,7>
- 3651865910U, // <6,1,5,4>: Cost 4 vext1 <4,6,1,5>, RHS
- 3724619785U, // <6,1,5,5>: Cost 4 vext2 <5,5,6,1>, <5,5,6,1>
- 2647560290U, // <6,1,5,6>: Cost 3 vext2 <5,0,6,1>, <5,6,7,0>
- 3669784035U, // <6,1,5,7>: Cost 4 vext1 <7,6,1,5>, <7,6,1,5>
- 2712569021U, // <6,1,5,u>: Cost 3 vext3 <4,6,4,6>, <1,5,u,7>
- 2602016870U, // <6,1,6,0>: Cost 3 vext1 <u,6,1,6>, LHS
- 3705377148U, // <6,1,6,1>: Cost 4 vext2 <2,3,6,1>, <6,1,2,3>
- 3709358586U, // <6,1,6,2>: Cost 4 vext2 <3,0,6,1>, <6,2,7,3>
- 3068513652U, // <6,1,6,3>: Cost 3 vtrnl LHS, <4,6,4,6>
- 2602020150U, // <6,1,6,4>: Cost 3 vext1 <u,6,1,6>, RHS
- 3786310900U, // <6,1,6,5>: Cost 4 vext3 <4,6,4,6>, <1,6,5,u>
- 2602021688U, // <6,1,6,6>: Cost 3 vext1 <u,6,1,6>, <6,6,6,6>
- 3731919748U, // <6,1,6,7>: Cost 4 vext2 <6,7,6,1>, <6,7,6,1>
- 3068554612U, // <6,1,6,u>: Cost 3 vtrnl LHS, <4,6,4,6>
- 2584109158U, // <6,1,7,0>: Cost 3 vext1 <5,6,1,7>, LHS
- 2892401974U, // <6,1,7,1>: Cost 3 vzipl <1,1,1,1>, RHS
- 2903690550U, // <6,1,7,2>: Cost 3 vzipl <3,0,1,2>, RHS
- 3068512186U, // <6,1,7,3>: Cost 3 vtrnl LHS, <2,6,3,7>
- 2584112018U, // <6,1,7,4>: Cost 3 vext1 <5,6,1,7>, <4,0,5,1>
- 2584113203U, // <6,1,7,5>: Cost 3 vext1 <5,6,1,7>, <5,6,1,7>
- 3633967527U, // <6,1,7,6>: Cost 4 vext1 <1,6,1,7>, <6,1,7,1>
- 3980791094U, // <6,1,7,7>: Cost 4 vzipl <3,5,1,7>, RHS
- 2903739702U, // <6,1,7,u>: Cost 3 vzipl <3,0,1,u>, RHS
- 2578145382U, // <6,1,u,0>: Cost 3 vext1 <4,6,1,u>, LHS
- 2892401975U, // <6,1,u,1>: Cost 3 vzipl <1,1,1,1>, RHS
- 2903690551U, // <6,1,u,2>: Cost 3 vzipl <3,0,1,2>, RHS
- 3021180242U, // <6,1,u,3>: Cost 3 vtrnl LHS, <4,6,0,u>
- 2578148662U, // <6,1,u,4>: Cost 3 vext1 <4,6,1,u>, RHS
- 2696054164U, // <6,1,u,5>: Cost 3 vext3 <1,u,5,6>, <1,u,5,6>
- 2596066198U, // <6,1,u,6>: Cost 3 vext1 <7,6,1,u>, <6,7,u,1>
+ 2686026896U, // <6,1,5,3>: Cost 3 vext3 <0,2,4,6>, <1,5,3,7>
+ 2693989528U, // <6,1,5,4>: Cost 3 vext3 <1,5,4,6>, <1,5,4,6>
+ 3767805089U, // <6,1,5,5>: Cost 4 vext3 <1,5,5,6>, <1,5,5,6>
+ 2652868706U, // <6,1,5,6>: Cost 3 vext2 <5,u,6,1>, <5,6,7,0>
+ 3908250934U, // <6,1,5,7>: Cost 4 vuzpr <2,6,0,1>, RHS
+ 2686026941U, // <6,1,5,u>: Cost 3 vext3 <0,2,4,6>, <1,5,u,7>
+ 2554241126U, // <6,1,6,0>: Cost 3 vext1 <0,6,1,6>, LHS
+ 3763602639U, // <6,1,6,1>: Cost 4 vext3 <0,u,2,6>, <1,6,1,7>
+ 3759547607U, // <6,1,6,2>: Cost 4 vext3 <0,2,1,6>, <1,6,2,6>
+ 3115221094U, // <6,1,6,3>: Cost 3 vtrnr <4,6,4,6>, LHS
+ 2554244406U, // <6,1,6,4>: Cost 3 vext1 <0,6,1,6>, RHS
+ 3760874739U, // <6,1,6,5>: Cost 4 vext3 <0,4,1,6>, <1,6,5,7>
+ 2554245944U, // <6,1,6,6>: Cost 3 vext1 <0,6,1,6>, <6,6,6,6>
+ 3719975758U, // <6,1,6,7>: Cost 4 vext2 <4,7,6,1>, <6,7,0,1>
+ 3115221099U, // <6,1,6,u>: Cost 3 vtrnr <4,6,4,6>, LHS
+ 2560221286U, // <6,1,7,0>: Cost 3 vext1 <1,6,1,7>, LHS
+ 2560222415U, // <6,1,7,1>: Cost 3 vext1 <1,6,1,7>, <1,6,1,7>
+ 2980497558U, // <6,1,7,2>: Cost 3 vzipr RHS, <3,0,1,2>
+ 3103211622U, // <6,1,7,3>: Cost 3 vtrnr <2,6,3,7>, LHS
+ 2560224566U, // <6,1,7,4>: Cost 3 vext1 <1,6,1,7>, RHS
+ 2980495698U, // <6,1,7,5>: Cost 3 vzipr RHS, <0,4,1,5>
+ 3633967526U, // <6,1,7,6>: Cost 4 vext1 <1,6,1,7>, <6,1,7,0>
+ 4054237686U, // <6,1,7,7>: Cost 4 vzipr RHS, <0,6,1,7>
+ 2560227118U, // <6,1,7,u>: Cost 3 vext1 <1,6,1,7>, LHS
+ 2560229478U, // <6,1,u,0>: Cost 3 vext1 <1,6,1,u>, LHS
+ 2686027117U, // <6,1,u,1>: Cost 3 vext3 <0,2,4,6>, <1,u,1,3>
+ 2686027129U, // <6,1,u,2>: Cost 3 vext3 <0,2,4,6>, <1,u,2,6>
+ 2686027132U, // <6,1,u,3>: Cost 3 vext3 <0,2,4,6>, <1,u,3,0>
+ 2687206795U, // <6,1,u,4>: Cost 3 vext3 <0,4,2,6>, <1,u,4,6>
+ 2686027157U, // <6,1,u,5>: Cost 3 vext3 <0,2,4,6>, <1,u,5,7>
+ 2590094093U, // <6,1,u,6>: Cost 3 vext1 <6,6,1,u>, <6,6,1,u>
2596066790U, // <6,1,u,7>: Cost 3 vext1 <7,6,1,u>, <7,6,1,u>
- 3021221202U, // <6,1,u,u>: Cost 3 vtrnl LHS, <4,6,0,u>
- 2641592320U, // <6,2,0,0>: Cost 3 vext2 <4,0,6,2>, <0,0,0,0>
- 1567850598U, // <6,2,0,1>: Cost 2 vext2 <4,0,6,2>, LHS
- 2641592484U, // <6,2,0,2>: Cost 3 vext2 <4,0,6,2>, <0,2,0,2>
- 3964905989U, // <6,2,0,3>: Cost 4 vzipl LHS, <3,4,6,0>
+ 2686027177U, // <6,1,u,u>: Cost 3 vext3 <0,2,4,6>, <1,u,u,0>
+ 2646900736U, // <6,2,0,0>: Cost 3 vext2 <4,u,6,2>, <0,0,0,0>
+ 1573159014U, // <6,2,0,1>: Cost 2 vext2 <4,u,6,2>, LHS
+ 2646900900U, // <6,2,0,2>: Cost 3 vext2 <4,u,6,2>, <0,2,0,2>
+ 3759769037U, // <6,2,0,3>: Cost 4 vext3 <0,2,4,6>, <2,0,3,0>
2641592668U, // <6,2,0,4>: Cost 3 vext2 <4,0,6,2>, <0,4,2,6>
- 3773113823U, // <6,2,0,5>: Cost 4 vext3 <2,4,5,6>, <2,0,5,0>
- 2641592824U, // <6,2,0,6>: Cost 3 vext2 <4,0,6,2>, <0,6,2,0>
- 3651900410U, // <6,2,0,7>: Cost 4 vext1 <4,6,2,0>, <7,0,1,2>
- 1567851165U, // <6,2,0,u>: Cost 2 vext2 <4,0,6,2>, LHS
- 2641593078U, // <6,2,1,0>: Cost 3 vext2 <4,0,6,2>, <1,0,3,2>
- 2641593140U, // <6,2,1,1>: Cost 3 vext2 <4,0,6,2>, <1,1,1,1>
- 2641593238U, // <6,2,1,2>: Cost 3 vext2 <4,0,6,2>, <1,2,3,0>
- 3964906395U, // <6,2,1,3>: Cost 4 vzipl LHS, <4,0,6,1>
- 3779085866U, // <6,2,1,4>: Cost 4 vext3 <3,4,5,6>, <2,1,4,3>
- 2665481360U, // <6,2,1,5>: Cost 3 vext2 <u,0,6,2>, <1,5,3,7>
+ 3779085794U, // <6,2,0,5>: Cost 4 vext3 <3,4,5,6>, <2,0,5,3>
+ 2686027244U, // <6,2,0,6>: Cost 3 vext3 <0,2,4,6>, <2,0,6,4>
+ 3669816807U, // <6,2,0,7>: Cost 4 vext1 <7,6,2,0>, <7,6,2,0>
+ 1573159581U, // <6,2,0,u>: Cost 2 vext2 <4,u,6,2>, LHS
+ 2230527897U, // <6,2,1,0>: Cost 3 vrev <2,6,0,1>
+ 2646901556U, // <6,2,1,1>: Cost 3 vext2 <4,u,6,2>, <1,1,1,1>
+ 2646901654U, // <6,2,1,2>: Cost 3 vext2 <4,u,6,2>, <1,2,3,0>
+ 2847047782U, // <6,2,1,3>: Cost 3 vuzpr <4,6,u,2>, LHS
+ 3771049517U, // <6,2,1,4>: Cost 4 vext3 <2,1,4,6>, <2,1,4,6>
+ 2646901904U, // <6,2,1,5>: Cost 3 vext2 <4,u,6,2>, <1,5,3,7>
2686027324U, // <6,2,1,6>: Cost 3 vext3 <0,2,4,6>, <2,1,6,3>
3669825000U, // <6,2,1,7>: Cost 4 vext1 <7,6,2,1>, <7,6,2,1>
- 2641593724U, // <6,2,1,u>: Cost 3 vext2 <4,0,6,2>, <1,u,3,0>
- 2578169958U, // <6,2,2,0>: Cost 3 vext1 <4,6,2,2>, LHS
- 3715335686U, // <6,2,2,1>: Cost 4 vext2 <4,0,6,2>, <2,1,0,3>
- 2705344104U, // <6,2,2,2>: Cost 3 vext3 <3,4,5,6>, <2,2,2,2>
- 2891164572U, // <6,2,2,3>: Cost 3 vzipl LHS, <4,0,6,2>
- 2578173238U, // <6,2,2,4>: Cost 3 vext1 <4,6,2,2>, RHS
- 3715336035U, // <6,2,2,5>: Cost 4 vext2 <4,0,6,2>, <2,5,3,1>
- 2590118672U, // <6,2,2,6>: Cost 3 vext1 <6,6,2,2>, <6,6,2,2>
- 3651916794U, // <6,2,2,7>: Cost 4 vext1 <4,6,2,2>, <7,0,1,2>
- 2886560668U, // <6,2,2,u>: Cost 3 vzipl LHS, <4,0,6,2>
- 2705344166U, // <6,2,3,0>: Cost 3 vext3 <3,4,5,6>, <2,3,0,1>
- 3767142063U, // <6,2,3,1>: Cost 4 vext3 <1,4,5,6>, <2,3,1,1>
- 2578179698U, // <6,2,3,2>: Cost 3 vext1 <4,6,2,3>, <2,2,3,3>
+ 2231117793U, // <6,2,1,u>: Cost 3 vrev <2,6,u,1>
+ 3763603029U, // <6,2,2,0>: Cost 4 vext3 <0,u,2,6>, <2,2,0,1>
+ 3759769184U, // <6,2,2,1>: Cost 4 vext3 <0,2,4,6>, <2,2,1,3>
+ 2686027368U, // <6,2,2,2>: Cost 3 vext3 <0,2,4,6>, <2,2,2,2>
+ 2686027378U, // <6,2,2,3>: Cost 3 vext3 <0,2,4,6>, <2,2,3,3>
+ 2697971326U, // <6,2,2,4>: Cost 3 vext3 <2,2,4,6>, <2,2,4,6>
+ 3759769224U, // <6,2,2,5>: Cost 4 vext3 <0,2,4,6>, <2,2,5,7>
+ 2698118800U, // <6,2,2,6>: Cost 3 vext3 <2,2,6,6>, <2,2,6,6>
+ 3920794092U, // <6,2,2,7>: Cost 4 vuzpr <4,6,u,2>, <6,2,5,7>
+ 2686027423U, // <6,2,2,u>: Cost 3 vext3 <0,2,4,6>, <2,2,u,3>
+ 2686027430U, // <6,2,3,0>: Cost 3 vext3 <0,2,4,6>, <2,3,0,1>
+ 3759769262U, // <6,2,3,1>: Cost 4 vext3 <0,2,4,6>, <2,3,1,0>
+ 2698487485U, // <6,2,3,2>: Cost 3 vext3 <2,3,2,6>, <2,3,2,6>
2705344196U, // <6,2,3,3>: Cost 3 vext3 <3,4,5,6>, <2,3,3,4>
- 2698634959U, // <6,2,3,4>: Cost 3 vext3 <2,3,4,6>, <2,3,4,6>
+ 2686027470U, // <6,2,3,4>: Cost 3 vext3 <0,2,4,6>, <2,3,4,5>
2698708696U, // <6,2,3,5>: Cost 3 vext3 <2,3,5,6>, <2,3,5,6>
- 2698782433U, // <6,2,3,6>: Cost 3 vext3 <2,3,6,6>, <2,3,6,6>
+ 2724660961U, // <6,2,3,6>: Cost 3 vext3 <6,6,6,6>, <2,3,6,6>
2729232104U, // <6,2,3,7>: Cost 3 vext3 <7,4,5,6>, <2,3,7,4>
- 2698929907U, // <6,2,3,u>: Cost 3 vext3 <2,3,u,6>, <2,3,u,6>
+ 2686027502U, // <6,2,3,u>: Cost 3 vext3 <0,2,4,6>, <2,3,u,1>
1567853468U, // <6,2,4,0>: Cost 2 vext2 <4,0,6,2>, <4,0,6,2>
- 3715337162U, // <6,2,4,1>: Cost 4 vext2 <4,0,6,2>, <4,1,2,3>
- 2642922558U, // <6,2,4,2>: Cost 3 vext2 <4,2,6,2>, <4,2,6,2>
- 2699224855U, // <6,2,4,3>: Cost 3 vext3 <2,4,3,6>, <2,4,3,6>
- 2578189622U, // <6,2,4,4>: Cost 3 vext1 <4,6,2,4>, RHS
- 1567853878U, // <6,2,4,5>: Cost 2 vext2 <4,0,6,2>, RHS
- 2641595724U, // <6,2,4,6>: Cost 3 vext2 <4,0,6,2>, <4,6,0,2>
- 3651933178U, // <6,2,4,7>: Cost 4 vext1 <4,6,2,4>, <7,0,1,2>
- 1567854121U, // <6,2,4,u>: Cost 2 vext2 <4,0,6,2>, RHS
- 3773114183U, // <6,2,5,0>: Cost 4 vext3 <2,4,5,6>, <2,5,0,0>
- 2641596112U, // <6,2,5,1>: Cost 3 vext2 <4,0,6,2>, <5,1,7,3>
- 3715337963U, // <6,2,5,2>: Cost 4 vext2 <4,0,6,2>, <5,2,1,3>
+ 3759769351U, // <6,2,4,1>: Cost 4 vext3 <0,2,4,6>, <2,4,1,u>
+ 2699151118U, // <6,2,4,2>: Cost 3 vext3 <2,4,2,6>, <2,4,2,6>
+ 2686027543U, // <6,2,4,3>: Cost 3 vext3 <0,2,4,6>, <2,4,3,6>
+ 2699298592U, // <6,2,4,4>: Cost 3 vext3 <2,4,4,6>, <2,4,4,6>
+ 1573162294U, // <6,2,4,5>: Cost 2 vext2 <4,u,6,2>, RHS
+ 2686027564U, // <6,2,4,6>: Cost 3 vext3 <0,2,4,6>, <2,4,6,0>
+ 3719982547U, // <6,2,4,7>: Cost 4 vext2 <4,7,6,2>, <4,7,6,2>
+ 1573162532U, // <6,2,4,u>: Cost 2 vext2 <4,u,6,2>, <4,u,6,2>
+ 3779086154U, // <6,2,5,0>: Cost 4 vext3 <3,4,5,6>, <2,5,0,3>
+ 2646904528U, // <6,2,5,1>: Cost 3 vext2 <4,u,6,2>, <5,1,7,3>
+ 3759769440U, // <6,2,5,2>: Cost 4 vext3 <0,2,4,6>, <2,5,2,7>
2699888488U, // <6,2,5,3>: Cost 3 vext3 <2,5,3,6>, <2,5,3,6>
- 2665484230U, // <6,2,5,4>: Cost 3 vext2 <u,0,6,2>, <5,4,7,6>
- 2665484292U, // <6,2,5,5>: Cost 3 vext2 <u,0,6,2>, <5,5,5,5>
- 2665484386U, // <6,2,5,6>: Cost 3 vext2 <u,0,6,2>, <5,6,7,0>
- 3715338358U, // <6,2,5,7>: Cost 4 vext2 <4,0,6,2>, <5,7,0,2>
- 2641596679U, // <6,2,5,u>: Cost 3 vext2 <4,0,6,2>, <5,u,7,3>
- 2734983065U, // <6,2,6,0>: Cost 3 vext3 <u,4,2,6>, <2,6,0,1>
- 3715338618U, // <6,2,6,1>: Cost 4 vext2 <4,0,6,2>, <6,1,2,1>
- 2631643642U, // <6,2,6,2>: Cost 3 vext2 <2,3,6,2>, <6,2,7,3>
- 2712569786U, // <6,2,6,3>: Cost 3 vext3 <4,6,4,6>, <2,6,3,7>
- 2734983105U, // <6,2,6,4>: Cost 3 vext3 <u,4,2,6>, <2,6,4,5>
- 3715338987U, // <6,2,6,5>: Cost 4 vext2 <4,0,6,2>, <6,5,7,1>
- 2665485112U, // <6,2,6,6>: Cost 3 vext2 <u,0,6,2>, <6,6,6,6>
- 2658186117U, // <6,2,6,7>: Cost 3 vext2 <6,7,6,2>, <6,7,6,2>
- 2641597363U, // <6,2,6,u>: Cost 3 vext2 <4,0,6,2>, <6,u,2,3>
- 2572238950U, // <6,2,7,0>: Cost 3 vext1 <3,6,2,7>, LHS
- 3965553974U, // <6,2,7,1>: Cost 4 vzipl <1,0,2,1>, RHS
- 2899119414U, // <6,2,7,2>: Cost 3 vzipl <2,2,2,2>, RHS
- 1812778294U, // <6,2,7,3>: Cost 2 vzipl LHS, RHS
- 2572242230U, // <6,2,7,4>: Cost 3 vext1 <3,6,2,7>, RHS
- 3645984464U, // <6,2,7,5>: Cost 4 vext1 <3,6,2,7>, <5,1,7,3>
- 2572243450U, // <6,2,7,6>: Cost 3 vext1 <3,6,2,7>, <6,2,7,3>
- 2596132334U, // <6,2,7,7>: Cost 3 vext1 <7,6,2,7>, <7,6,2,7>
- 1812819254U, // <6,2,7,u>: Cost 2 vzipl LHS, RHS
+ 2230855617U, // <6,2,5,4>: Cost 3 vrev <2,6,4,5>
+ 2646904836U, // <6,2,5,5>: Cost 3 vext2 <4,u,6,2>, <5,5,5,5>
+ 2646904930U, // <6,2,5,6>: Cost 3 vext2 <4,u,6,2>, <5,6,7,0>
+ 2847051062U, // <6,2,5,7>: Cost 3 vuzpr <4,6,u,2>, RHS
+ 2700257173U, // <6,2,5,u>: Cost 3 vext3 <2,5,u,6>, <2,5,u,6>
+ 2687207321U, // <6,2,6,0>: Cost 3 vext3 <0,4,2,6>, <2,6,0,1>
+ 2686027684U, // <6,2,6,1>: Cost 3 vext3 <0,2,4,6>, <2,6,1,3>
+ 2566260656U, // <6,2,6,2>: Cost 3 vext1 <2,6,2,6>, <2,6,2,6>
+ 2685806522U, // <6,2,6,3>: Cost 3 vext3 <0,2,1,6>, <2,6,3,7>
+ 2687207361U, // <6,2,6,4>: Cost 3 vext3 <0,4,2,6>, <2,6,4,5>
+ 2686027724U, // <6,2,6,5>: Cost 3 vext3 <0,2,4,6>, <2,6,5,7>
+ 2646905656U, // <6,2,6,6>: Cost 3 vext2 <4,u,6,2>, <6,6,6,6>
+ 2646905678U, // <6,2,6,7>: Cost 3 vext2 <4,u,6,2>, <6,7,0,1>
+ 2686027751U, // <6,2,6,u>: Cost 3 vext3 <0,2,4,6>, <2,6,u,7>
+ 2554323046U, // <6,2,7,0>: Cost 3 vext1 <0,6,2,7>, LHS
+ 2572239606U, // <6,2,7,1>: Cost 3 vext1 <3,6,2,7>, <1,0,3,2>
+ 2566268849U, // <6,2,7,2>: Cost 3 vext1 <2,6,2,7>, <2,6,2,7>
+ 1906753638U, // <6,2,7,3>: Cost 2 vzipr RHS, LHS
+ 2554326326U, // <6,2,7,4>: Cost 3 vext1 <0,6,2,7>, RHS
+ 3304687564U, // <6,2,7,5>: Cost 4 vrev <2,6,5,7>
+ 2980495708U, // <6,2,7,6>: Cost 3 vzipr RHS, <0,4,2,6>
+ 2646906476U, // <6,2,7,7>: Cost 3 vext2 <4,u,6,2>, <7,7,7,7>
+ 1906753643U, // <6,2,7,u>: Cost 2 vzipr RHS, LHS
1591744256U, // <6,2,u,0>: Cost 2 vext2 <u,0,6,2>, <u,0,6,2>
- 1567856430U, // <6,2,u,1>: Cost 2 vext2 <4,0,6,2>, LHS
- 2899119415U, // <6,2,u,2>: Cost 3 vzipl <2,2,2,2>, RHS
- 1812778295U, // <6,2,u,3>: Cost 2 vzipl LHS, RHS
- 2701953124U, // <6,2,u,4>: Cost 3 vext3 <2,u,4,6>, <2,u,4,6>
- 1567856794U, // <6,2,u,5>: Cost 2 vext2 <4,0,6,2>, RHS
- 2572251651U, // <6,2,u,6>: Cost 3 vext1 <3,6,2,u>, <6,2,u,3>
- 2596140527U, // <6,2,u,7>: Cost 3 vext1 <7,6,2,u>, <7,6,2,u>
- 1812819255U, // <6,2,u,u>: Cost 2 vzipl LHS, RHS
- 3779086475U, // <6,3,0,0>: Cost 4 vext3 <3,4,5,6>, <3,0,0,0>
- 2705344662U, // <6,3,0,1>: Cost 3 vext3 <3,4,5,6>, <3,0,1,2>
+ 1573164846U, // <6,2,u,1>: Cost 2 vext2 <4,u,6,2>, LHS
+ 2701805650U, // <6,2,u,2>: Cost 3 vext3 <2,u,2,6>, <2,u,2,6>
+ 1906761830U, // <6,2,u,3>: Cost 2 vzipr RHS, LHS
+ 2686027875U, // <6,2,u,4>: Cost 3 vext3 <0,2,4,6>, <2,u,4,5>
+ 1573165210U, // <6,2,u,5>: Cost 2 vext2 <4,u,6,2>, RHS
+ 2686322800U, // <6,2,u,6>: Cost 3 vext3 <0,2,u,6>, <2,u,6,0>
+ 2847051305U, // <6,2,u,7>: Cost 3 vuzpr <4,6,u,2>, RHS
+ 1906761835U, // <6,2,u,u>: Cost 2 vzipr RHS, LHS
+ 3759769739U, // <6,3,0,0>: Cost 4 vext3 <0,2,4,6>, <3,0,0,0>
+ 2686027926U, // <6,3,0,1>: Cost 3 vext3 <0,2,4,6>, <3,0,1,2>
2686027937U, // <6,3,0,2>: Cost 3 vext3 <0,2,4,6>, <3,0,2,4>
- 3779086503U, // <6,3,0,3>: Cost 4 vext3 <3,4,5,6>, <3,0,3,1>
- 2705344688U, // <6,3,0,4>: Cost 3 vext3 <3,4,5,6>, <3,0,4,1>
+ 3640027286U, // <6,3,0,3>: Cost 4 vext1 <2,6,3,0>, <3,0,1,2>
+ 2687207601U, // <6,3,0,4>: Cost 3 vext3 <0,4,2,6>, <3,0,4,2>
2705344698U, // <6,3,0,5>: Cost 3 vext3 <3,4,5,6>, <3,0,5,2>
- 4143829090U, // <6,3,0,6>: Cost 4 vtrnl <u,3,5,6>, <5,6,7,0>
+ 3663917847U, // <6,3,0,6>: Cost 4 vext1 <6,6,3,0>, <6,6,3,0>
2237008560U, // <6,3,0,7>: Cost 3 vrev <3,6,7,0>
- 2705344725U, // <6,3,0,u>: Cost 3 vext3 <3,4,5,6>, <3,0,u,2>
- 2578235494U, // <6,3,1,0>: Cost 3 vext1 <4,6,3,1>, LHS
- 3767142630U, // <6,3,1,1>: Cost 4 vext3 <1,4,5,6>, <3,1,1,1>
- 3704062921U, // <6,3,1,2>: Cost 4 vext2 <2,1,6,3>, <1,2,u,6>
- 2578237590U, // <6,3,1,3>: Cost 3 vext1 <4,6,3,1>, <3,0,1,2>
- 2578238774U, // <6,3,1,4>: Cost 3 vext1 <4,6,3,1>, RHS
- 3779086604U, // <6,3,1,5>: Cost 4 vext3 <3,4,5,6>, <3,1,5,3>
- 3716007130U, // <6,3,1,6>: Cost 4 vext2 <4,1,6,3>, <1,6,3,0>
- 3651982330U, // <6,3,1,7>: Cost 4 vext1 <4,6,3,1>, <7,0,1,2>
- 2578241326U, // <6,3,1,u>: Cost 3 vext1 <4,6,3,1>, LHS
- 2602131558U, // <6,3,2,0>: Cost 3 vext1 <u,6,3,2>, LHS
- 2560328924U, // <6,3,2,1>: Cost 3 vext1 <1,6,3,2>, <1,6,3,2>
- 2642929266U, // <6,3,2,2>: Cost 3 vext2 <4,2,6,3>, <2,2,3,3>
- 3966307228U, // <6,3,2,3>: Cost 4 vzipl <1,1,3,3>, <4,0,6,2>
- 2602134428U, // <6,3,2,4>: Cost 3 vext1 <u,6,3,2>, <4,0,6,2>
- 4107914572U, // <6,3,2,5>: Cost 4 vtrnl <2,3,4,5>, <4,6,0,2>
- 2660845498U, // <6,3,2,6>: Cost 3 vext2 <7,2,6,3>, <2,6,3,7>
- 3669906930U, // <6,3,2,7>: Cost 4 vext1 <7,6,3,2>, <7,6,3,2>
- 2602137390U, // <6,3,2,u>: Cost 3 vext1 <u,6,3,2>, LHS
- 2578251878U, // <6,3,3,0>: Cost 3 vext1 <4,6,3,3>, LHS
+ 2686027989U, // <6,3,0,u>: Cost 3 vext3 <0,2,4,6>, <3,0,u,2>
+ 3759769823U, // <6,3,1,0>: Cost 4 vext3 <0,2,4,6>, <3,1,0,3>
+ 3759769830U, // <6,3,1,1>: Cost 4 vext3 <0,2,4,6>, <3,1,1,1>
+ 3759769841U, // <6,3,1,2>: Cost 4 vext3 <0,2,4,6>, <3,1,2,3>
+ 3759769848U, // <6,3,1,3>: Cost 4 vext3 <0,2,4,6>, <3,1,3,1>
+ 2703280390U, // <6,3,1,4>: Cost 3 vext3 <3,1,4,6>, <3,1,4,6>
+ 3759769868U, // <6,3,1,5>: Cost 4 vext3 <0,2,4,6>, <3,1,5,3>
+ 3704063194U, // <6,3,1,6>: Cost 4 vext2 <2,1,6,3>, <1,6,3,0>
+ 3767732510U, // <6,3,1,7>: Cost 4 vext3 <1,5,4,6>, <3,1,7,3>
+ 2703280390U, // <6,3,1,u>: Cost 3 vext3 <3,1,4,6>, <3,1,4,6>
+ 3704063468U, // <6,3,2,0>: Cost 4 vext2 <2,1,6,3>, <2,0,6,4>
+ 2630321724U, // <6,3,2,1>: Cost 3 vext2 <2,1,6,3>, <2,1,6,3>
+ 3759769921U, // <6,3,2,2>: Cost 4 vext3 <0,2,4,6>, <3,2,2,2>
+ 3759769928U, // <6,3,2,3>: Cost 4 vext3 <0,2,4,6>, <3,2,3,0>
+ 3704063767U, // <6,3,2,4>: Cost 4 vext2 <2,1,6,3>, <2,4,3,6>
+ 3704063876U, // <6,3,2,5>: Cost 4 vext2 <2,1,6,3>, <2,5,6,7>
+ 2636957626U, // <6,3,2,6>: Cost 3 vext2 <3,2,6,3>, <2,6,3,7>
+ 3777907058U, // <6,3,2,7>: Cost 4 vext3 <3,2,7,6>, <3,2,7,6>
+ 2630321724U, // <6,3,2,u>: Cost 3 vext2 <2,1,6,3>, <2,1,6,3>
+ 3759769983U, // <6,3,3,0>: Cost 4 vext3 <0,2,4,6>, <3,3,0,1>
3710036245U, // <6,3,3,1>: Cost 4 vext2 <3,1,6,3>, <3,1,6,3>
2636958054U, // <6,3,3,2>: Cost 3 vext2 <3,2,6,3>, <3,2,6,3>
- 2705344924U, // <6,3,3,3>: Cost 3 vext3 <3,4,5,6>, <3,3,3,3>
- 2705344935U, // <6,3,3,4>: Cost 3 vext3 <3,4,5,6>, <3,3,4,5>
- 3779086763U, // <6,3,3,5>: Cost 4 vext3 <3,4,5,6>, <3,3,5,0>
- 3717335692U, // <6,3,3,6>: Cost 4 vext2 <4,3,6,3>, <3,6,3,0>
- 3651998714U, // <6,3,3,7>: Cost 4 vext1 <4,6,3,3>, <7,0,1,2>
+ 2686028188U, // <6,3,3,3>: Cost 3 vext3 <0,2,4,6>, <3,3,3,3>
+ 2704607656U, // <6,3,3,4>: Cost 3 vext3 <3,3,4,6>, <3,3,4,6>
+ 3773041072U, // <6,3,3,5>: Cost 4 vext3 <2,4,4,6>, <3,3,5,5>
+ 3711363731U, // <6,3,3,6>: Cost 4 vext2 <3,3,6,3>, <3,6,3,7>
+ 3767732676U, // <6,3,3,7>: Cost 4 vext3 <1,5,4,6>, <3,3,7,7>
2707999179U, // <6,3,3,u>: Cost 3 vext3 <3,u,5,6>, <3,3,u,5>
- 2704976341U, // <6,3,4,0>: Cost 3 vext3 <3,4,0,6>, <3,4,0,6>
+ 2584232038U, // <6,3,4,0>: Cost 3 vext1 <5,6,3,4>, LHS
2642267118U, // <6,3,4,1>: Cost 3 vext2 <4,1,6,3>, <4,1,6,3>
2642930751U, // <6,3,4,2>: Cost 3 vext2 <4,2,6,3>, <4,2,6,3>
- 2643594384U, // <6,3,4,3>: Cost 3 vext2 <4,3,6,3>, <4,3,6,3>
+ 2705197552U, // <6,3,4,3>: Cost 3 vext3 <3,4,3,6>, <3,4,3,6>
2584235318U, // <6,3,4,4>: Cost 3 vext1 <5,6,3,4>, RHS
1631603202U, // <6,3,4,5>: Cost 2 vext3 <3,4,5,6>, <3,4,5,6>
- 2712570377U, // <6,3,4,6>: Cost 3 vext3 <4,6,4,6>, <3,4,6,4>
+ 2654211444U, // <6,3,4,6>: Cost 3 vext2 <6,1,6,3>, <4,6,4,6>
2237041332U, // <6,3,4,7>: Cost 3 vrev <3,6,7,4>
1631824413U, // <6,3,4,u>: Cost 2 vext3 <3,4,u,6>, <3,4,u,6>
- 2705345058U, // <6,3,5,0>: Cost 3 vext3 <3,4,5,6>, <3,5,0,2>
- 3779086890U, // <6,3,5,1>: Cost 4 vext3 <3,4,5,6>, <3,5,1,1>
- 2648903448U, // <6,3,5,2>: Cost 3 vext2 <5,2,6,3>, <5,2,6,3>
- 2578270722U, // <6,3,5,3>: Cost 3 vext1 <4,6,3,5>, <3,4,5,6>
- 2578271542U, // <6,3,5,4>: Cost 3 vext1 <4,6,3,5>, RHS
- 4181742221U, // <6,3,5,5>: Cost 4 vtrnr <3,4,5,6>, <6,4,5,6>
- 3779824220U, // <6,3,5,6>: Cost 4 vext3 <3,5,6,6>, <3,5,6,6>
- 3652015098U, // <6,3,5,7>: Cost 4 vext1 <4,6,3,5>, <7,0,1,2>
- 2578274094U, // <6,3,5,u>: Cost 3 vext1 <4,6,3,5>, LHS
+ 3640066150U, // <6,3,5,0>: Cost 4 vext1 <2,6,3,5>, LHS
+ 3772746288U, // <6,3,5,1>: Cost 4 vext3 <2,4,0,6>, <3,5,1,7>
+ 3640067790U, // <6,3,5,2>: Cost 4 vext1 <2,6,3,5>, <2,3,4,5>
+ 3773041216U, // <6,3,5,3>: Cost 4 vext3 <2,4,4,6>, <3,5,3,5>
+ 2705934922U, // <6,3,5,4>: Cost 3 vext3 <3,5,4,6>, <3,5,4,6>
+ 3773041236U, // <6,3,5,5>: Cost 4 vext3 <2,4,4,6>, <3,5,5,7>
+ 3779086940U, // <6,3,5,6>: Cost 4 vext3 <3,4,5,6>, <3,5,6,6>
+ 3767732831U, // <6,3,5,7>: Cost 4 vext3 <1,5,4,6>, <3,5,7,0>
+ 2706229870U, // <6,3,5,u>: Cost 3 vext3 <3,5,u,6>, <3,5,u,6>
2602164326U, // <6,3,6,0>: Cost 3 vext1 <u,6,3,6>, LHS
- 2560361696U, // <6,3,6,1>: Cost 3 vext1 <1,6,3,6>, <1,6,3,6>
+ 2654212512U, // <6,3,6,1>: Cost 3 vext2 <6,1,6,3>, <6,1,6,3>
2566334393U, // <6,3,6,2>: Cost 3 vext1 <2,6,3,6>, <2,6,3,6>
- 3716010542U, // <6,3,6,3>: Cost 4 vext2 <4,1,6,3>, <6,3,4,1>
- 2602167606U, // <6,3,6,4>: Cost 3 vext1 <u,6,3,6>, RHS
- 4181742392U, // <6,3,6,5>: Cost 4 vtrnr <3,4,5,6>, <6,6,6,6>
- 2566337336U, // <6,3,6,6>: Cost 3 vext1 <2,6,3,6>, <6,6,6,6>
- 3786312375U, // <6,3,6,7>: Cost 4 vext3 <4,6,4,6>, <3,6,7,7>
+ 3704066588U, // <6,3,6,3>: Cost 4 vext2 <2,1,6,3>, <6,3,2,1>
+ 2602167524U, // <6,3,6,4>: Cost 3 vext1 <u,6,3,6>, <4,4,6,6>
+ 3710702321U, // <6,3,6,5>: Cost 4 vext2 <3,2,6,3>, <6,5,7,7>
+ 2724661933U, // <6,3,6,6>: Cost 3 vext3 <6,6,6,6>, <3,6,6,6>
+ 3710702465U, // <6,3,6,7>: Cost 4 vext2 <3,2,6,3>, <6,7,5,7>
2602170158U, // <6,3,6,u>: Cost 3 vext1 <u,6,3,6>, LHS
- 1528430694U, // <6,3,7,0>: Cost 2 vext1 <u,6,3,7>, LHS
- 2602173174U, // <6,3,7,1>: Cost 3 vext1 <u,6,3,7>, <1,0,3,2>
+ 1492598886U, // <6,3,7,0>: Cost 2 vext1 <2,6,3,7>, LHS
+ 2560369889U, // <6,3,7,1>: Cost 3 vext1 <1,6,3,7>, <1,6,3,7>
1492600762U, // <6,3,7,2>: Cost 2 vext1 <2,6,3,7>, <2,6,3,7>
- 2892565814U, // <6,3,7,3>: Cost 3 vzipl <1,1,3,3>, RHS
- 1528433974U, // <6,3,7,4>: Cost 2 vext1 <u,6,3,7>, RHS
+ 2566342806U, // <6,3,7,3>: Cost 3 vext1 <2,6,3,7>, <3,0,1,2>
+ 1492602166U, // <6,3,7,4>: Cost 2 vext1 <2,6,3,7>, RHS
2602176208U, // <6,3,7,5>: Cost 3 vext1 <u,6,3,7>, <5,1,7,3>
- 2602177018U, // <6,3,7,6>: Cost 3 vext1 <u,6,3,7>, <6,2,7,3>
- 2937056566U, // <6,3,7,7>: Cost 3 vzipl <u,5,3,7>, RHS
- 1528436526U, // <6,3,7,u>: Cost 2 vext1 <u,6,3,7>, LHS
- 1528430694U, // <6,3,u,0>: Cost 2 vext1 <u,6,3,7>, LHS
- 2705345310U, // <6,3,u,1>: Cost 3 vext3 <3,4,5,6>, <3,u,1,2>
+ 2566345210U, // <6,3,7,6>: Cost 3 vext1 <2,6,3,7>, <6,2,7,3>
+ 2980496528U, // <6,3,7,7>: Cost 3 vzipr RHS, <1,5,3,7>
+ 1492604718U, // <6,3,7,u>: Cost 2 vext1 <2,6,3,7>, LHS
+ 1492607078U, // <6,3,u,0>: Cost 2 vext1 <2,6,3,u>, LHS
+ 2686028574U, // <6,3,u,1>: Cost 3 vext3 <0,2,4,6>, <3,u,1,2>
1492608955U, // <6,3,u,2>: Cost 2 vext1 <2,6,3,u>, <2,6,3,u>
- 2892565815U, // <6,3,u,3>: Cost 3 vzipl <1,1,3,3>, RHS
- 1528433974U, // <6,3,u,4>: Cost 2 vext1 <u,6,3,7>, RHS
+ 2566350998U, // <6,3,u,3>: Cost 3 vext1 <2,6,3,u>, <3,0,1,2>
+ 1492610358U, // <6,3,u,4>: Cost 2 vext1 <2,6,3,u>, RHS
1634257734U, // <6,3,u,5>: Cost 2 vext3 <3,u,5,6>, <3,u,5,6>
- 2664831184U, // <6,3,u,6>: Cost 3 vext2 <7,u,6,3>, <u,6,3,7>
- 2937056567U, // <6,3,u,7>: Cost 3 vzipl <u,5,3,7>, RHS
- 1634478945U, // <6,3,u,u>: Cost 2 vext3 <3,u,u,6>, <3,u,u,6>
- 2578301030U, // <6,4,0,0>: Cost 3 vext1 <4,6,4,0>, LHS
- 2642935910U, // <6,4,0,1>: Cost 3 vext2 <4,2,6,4>, LHS
- 2819412854U, // <6,4,0,2>: Cost 3 vuzpr LHS, <6,7,4,5>
- 3782257541U, // <6,4,0,3>: Cost 4 vext3 <4,0,3,6>, <4,0,3,6>
- 2578304310U, // <6,4,0,4>: Cost 3 vext1 <4,6,4,0>, RHS
- 2705345426U, // <6,4,0,5>: Cost 3 vext3 <3,4,5,6>, <4,0,5,1>
- 2704976796U, // <6,4,0,6>: Cost 3 vext3 <3,4,0,6>, <4,0,6,2>
- 3652047866U, // <6,4,0,7>: Cost 4 vext1 <4,6,4,0>, <7,0,1,2>
- 2705345453U, // <6,4,0,u>: Cost 3 vext3 <3,4,5,6>, <4,0,u,1>
+ 2566353489U, // <6,3,u,6>: Cost 3 vext1 <2,6,3,u>, <6,3,u,0>
+ 2980504720U, // <6,3,u,7>: Cost 3 vzipr RHS, <1,5,3,7>
+ 1492612910U, // <6,3,u,u>: Cost 2 vext1 <2,6,3,u>, LHS
+ 3703406592U, // <6,4,0,0>: Cost 4 vext2 <2,0,6,4>, <0,0,0,0>
+ 2629664870U, // <6,4,0,1>: Cost 3 vext2 <2,0,6,4>, LHS
+ 2629664972U, // <6,4,0,2>: Cost 3 vext2 <2,0,6,4>, <0,2,4,6>
+ 3779087232U, // <6,4,0,3>: Cost 4 vext3 <3,4,5,6>, <4,0,3,1>
+ 2642936156U, // <6,4,0,4>: Cost 3 vext2 <4,2,6,4>, <0,4,2,6>
+ 2712570770U, // <6,4,0,5>: Cost 3 vext3 <4,6,4,6>, <4,0,5,1>
+ 2687208348U, // <6,4,0,6>: Cost 3 vext3 <0,4,2,6>, <4,0,6,2>
+ 3316723081U, // <6,4,0,7>: Cost 4 vrev <4,6,7,0>
+ 2629665437U, // <6,4,0,u>: Cost 3 vext2 <2,0,6,4>, LHS
2242473291U, // <6,4,1,0>: Cost 3 vrev <4,6,0,1>
- 3716014900U, // <6,4,1,1>: Cost 4 vext2 <4,1,6,4>, <1,1,1,1>
- 3708715977U, // <6,4,1,2>: Cost 4 vext2 <2,u,6,4>, <1,2,u,6>
- 3779087312U, // <6,4,1,3>: Cost 4 vext3 <3,4,5,6>, <4,1,3,0>
- 3718669374U, // <6,4,1,4>: Cost 4 vext2 <4,5,6,4>, <1,4,3,6>
- 3767143395U, // <6,4,1,5>: Cost 4 vext3 <1,4,5,6>, <4,1,5,1>
- 2705345518U, // <6,4,1,6>: Cost 3 vext3 <3,4,5,6>, <4,1,6,3>
+ 3700089652U, // <6,4,1,1>: Cost 4 vext2 <1,4,6,4>, <1,1,1,1>
+ 3703407510U, // <6,4,1,2>: Cost 4 vext2 <2,0,6,4>, <1,2,3,0>
+ 2852962406U, // <6,4,1,3>: Cost 3 vuzpr <5,6,7,4>, LHS
+ 3628166454U, // <6,4,1,4>: Cost 4 vext1 <0,6,4,1>, RHS
+ 3760876514U, // <6,4,1,5>: Cost 4 vext3 <0,4,1,6>, <4,1,5,0>
+ 2687208430U, // <6,4,1,6>: Cost 3 vext3 <0,4,2,6>, <4,1,6,3>
3316731274U, // <6,4,1,7>: Cost 4 vrev <4,6,7,1>
2243063187U, // <6,4,1,u>: Cost 3 vrev <4,6,u,1>
- 2242481484U, // <6,4,2,0>: Cost 3 vrev <4,6,0,2>
- 3779087378U, // <6,4,2,1>: Cost 4 vext3 <3,4,5,6>, <4,2,1,3>
- 3716679272U, // <6,4,2,2>: Cost 4 vext2 <4,2,6,4>, <2,2,2,2>
- 2642937550U, // <6,4,2,3>: Cost 3 vext2 <4,2,6,4>, <2,3,4,5>
+ 2629666284U, // <6,4,2,0>: Cost 3 vext2 <2,0,6,4>, <2,0,6,4>
+ 3703408188U, // <6,4,2,1>: Cost 4 vext2 <2,0,6,4>, <2,1,6,3>
+ 3703408232U, // <6,4,2,2>: Cost 4 vext2 <2,0,6,4>, <2,2,2,2>
+ 3703408294U, // <6,4,2,3>: Cost 4 vext2 <2,0,6,4>, <2,3,0,1>
2632320816U, // <6,4,2,4>: Cost 3 vext2 <2,4,6,4>, <2,4,6,4>
- 2980499962U, // <6,4,2,5>: Cost 3 vzipr RHS, <6,2,7,3>
- 2734984252U, // <6,4,2,6>: Cost 3 vext3 <u,4,2,6>, <4,2,6,0>
- 3669980667U, // <6,4,2,7>: Cost 4 vext1 <7,6,4,2>, <7,6,4,2>
- 2982490618U, // <6,4,2,u>: Cost 3 vzipr RHS, <6,2,7,3>
- 3716679830U, // <6,4,3,0>: Cost 4 vext2 <4,2,6,4>, <3,0,1,2>
- 3716679948U, // <6,4,3,1>: Cost 4 vext2 <4,2,6,4>, <3,1,5,3>
- 3710708071U, // <6,4,3,2>: Cost 4 vext2 <3,2,6,4>, <3,2,6,4>
- 3716680092U, // <6,4,3,3>: Cost 4 vext2 <4,2,6,4>, <3,3,3,3>
+ 2923384118U, // <6,4,2,5>: Cost 3 vzipl <6,2,7,3>, RHS
+ 2687208508U, // <6,4,2,6>: Cost 3 vext3 <0,4,2,6>, <4,2,6,0>
+ 3760950341U, // <6,4,2,7>: Cost 4 vext3 <0,4,2,6>, <4,2,7,0>
+ 2634975348U, // <6,4,2,u>: Cost 3 vext2 <2,u,6,4>, <2,u,6,4>
+ 3703408790U, // <6,4,3,0>: Cost 4 vext2 <2,0,6,4>, <3,0,1,2>
+ 3316305238U, // <6,4,3,1>: Cost 4 vrev <4,6,1,3>
+ 3703408947U, // <6,4,3,2>: Cost 4 vext2 <2,0,6,4>, <3,2,0,6>
+ 3703409052U, // <6,4,3,3>: Cost 4 vext2 <2,0,6,4>, <3,3,3,3>
2644929026U, // <6,4,3,4>: Cost 3 vext2 <4,5,6,4>, <3,4,5,6>
- 3779087495U, // <6,4,3,5>: Cost 4 vext3 <3,4,5,6>, <4,3,5,3>
+ 3718670922U, // <6,4,3,5>: Cost 4 vext2 <4,5,6,4>, <3,5,4,6>
2705345682U, // <6,4,3,6>: Cost 3 vext3 <3,4,5,6>, <4,3,6,5>
- 3669988860U, // <6,4,3,7>: Cost 4 vext1 <7,6,4,3>, <7,6,4,3>
+ 3926705152U, // <6,4,3,7>: Cost 4 vuzpr <5,6,7,4>, <1,3,5,7>
2668817222U, // <6,4,3,u>: Cost 3 vext2 <u,5,6,4>, <3,u,5,6>
2590277734U, // <6,4,4,0>: Cost 3 vext1 <6,6,4,4>, LHS
3716017135U, // <6,4,4,1>: Cost 4 vext2 <4,1,6,4>, <4,1,6,4>
2642938944U, // <6,4,4,2>: Cost 3 vext2 <4,2,6,4>, <4,2,6,4>
3717344401U, // <6,4,4,3>: Cost 4 vext2 <4,3,6,4>, <4,3,6,4>
2712571088U, // <6,4,4,4>: Cost 3 vext3 <4,6,4,6>, <4,4,4,4>
- 2642939190U, // <6,4,4,5>: Cost 3 vext2 <4,2,6,4>, RHS
+ 2629668150U, // <6,4,4,5>: Cost 3 vext2 <2,0,6,4>, RHS
1637649636U, // <6,4,4,6>: Cost 2 vext3 <4,4,6,6>, <4,4,6,6>
2646257109U, // <6,4,4,7>: Cost 3 vext2 <4,7,6,4>, <4,7,6,4>
1637649636U, // <6,4,4,u>: Cost 2 vext3 <4,4,6,6>, <4,4,6,6>
- 2584313958U, // <6,4,5,0>: Cost 3 vext1 <5,6,4,5>, LHS
- 3646113154U, // <6,4,5,1>: Cost 4 vext1 <3,6,4,5>, <1,u,3,6>
+ 2566398054U, // <6,4,5,0>: Cost 3 vext1 <2,6,4,5>, LHS
+ 3760876805U, // <6,4,5,1>: Cost 4 vext3 <0,4,1,6>, <4,5,1,3>
2566399937U, // <6,4,5,2>: Cost 3 vext1 <2,6,4,5>, <2,6,4,5>
2584316418U, // <6,4,5,3>: Cost 3 vext1 <5,6,4,5>, <3,4,5,6>
- 2584317238U, // <6,4,5,4>: Cost 3 vext1 <5,6,4,5>, RHS
+ 2566401334U, // <6,4,5,4>: Cost 3 vext1 <2,6,4,5>, RHS
2584318028U, // <6,4,5,5>: Cost 3 vext1 <5,6,4,5>, <5,6,4,5>
- 1631604022U, // <6,4,5,6>: Cost 2 vext3 <3,4,5,6>, RHS
- 2596263422U, // <6,4,5,7>: Cost 3 vext1 <7,6,4,5>, <7,6,4,5>
- 1631604040U, // <6,4,5,u>: Cost 2 vext3 <3,4,5,6>, RHS
+ 1612287286U, // <6,4,5,6>: Cost 2 vext3 <0,2,4,6>, RHS
+ 2852965686U, // <6,4,5,7>: Cost 3 vuzpr <5,6,7,4>, RHS
+ 1612287304U, // <6,4,5,u>: Cost 2 vext3 <0,2,4,6>, RHS
1504608358U, // <6,4,6,0>: Cost 2 vext1 <4,6,4,6>, LHS
2578350838U, // <6,4,6,1>: Cost 3 vext1 <4,6,4,6>, <1,0,3,2>
2578351720U, // <6,4,6,2>: Cost 3 vext1 <4,6,4,6>, <2,2,2,2>
2578352278U, // <6,4,6,3>: Cost 3 vext1 <4,6,4,6>, <3,0,1,2>
1504611638U, // <6,4,6,4>: Cost 2 vext1 <4,6,4,6>, RHS
- 2980500280U, // <6,4,6,5>: Cost 3 vzipr RHS, <6,6,6,6>
- 3114718008U, // <6,4,6,6>: Cost 3 vtrnr RHS, <6,6,6,6>
+ 2578353872U, // <6,4,6,5>: Cost 3 vext1 <4,6,4,6>, <5,1,7,3>
+ 2578354682U, // <6,4,6,6>: Cost 3 vext1 <4,6,4,6>, <6,2,7,3>
2578355194U, // <6,4,6,7>: Cost 3 vext1 <4,6,4,6>, <7,0,1,2>
1504614190U, // <6,4,6,u>: Cost 2 vext1 <4,6,4,6>, LHS
- 2578358374U, // <6,4,7,0>: Cost 3 vext1 <4,6,4,7>, LHS
- 2602247111U, // <6,4,7,1>: Cost 3 vext1 <u,6,4,7>, <1,2,u,4>
- 3971681590U, // <6,4,7,2>: Cost 4 vzipl <2,0,4,2>, RHS
+ 2572386406U, // <6,4,7,0>: Cost 3 vext1 <3,6,4,7>, LHS
+ 2572387226U, // <6,4,7,1>: Cost 3 vext1 <3,6,4,7>, <1,2,3,4>
+ 3640157902U, // <6,4,7,2>: Cost 4 vext1 <2,6,4,7>, <2,3,4,5>
2572389020U, // <6,4,7,3>: Cost 3 vext1 <3,6,4,7>, <3,6,4,7>
- 2578361552U, // <6,4,7,4>: Cost 3 vext1 <4,6,4,7>, <4,4,4,4>
- 2899954998U, // <6,4,7,5>: Cost 3 vzipl <2,3,4,5>, RHS
- 3114717690U, // <6,4,7,6>: Cost 3 vtrnr RHS, <6,2,7,3>
- 3652105210U, // <6,4,7,7>: Cost 4 vext1 <4,6,4,7>, <7,0,1,2>
- 2899979574U, // <6,4,7,u>: Cost 3 vzipl <2,3,4,u>, RHS
- 1504624742U, // <6,4,u,0>: Cost 2 vext1 <4,6,4,u>, LHS
- 2642941742U, // <6,4,u,1>: Cost 3 vext2 <4,2,6,4>, LHS
- 2578368104U, // <6,4,u,2>: Cost 3 vext1 <4,6,4,u>, <2,2,2,2>
- 2578368662U, // <6,4,u,3>: Cost 3 vext1 <4,6,4,u>, <3,0,1,2>
- 1504628022U, // <6,4,u,4>: Cost 2 vext1 <4,6,4,u>, RHS
- 2899954999U, // <6,4,u,5>: Cost 3 vzipl <2,3,4,5>, RHS
- 1631604265U, // <6,4,u,6>: Cost 2 vext3 <3,4,5,6>, RHS
- 2578371578U, // <6,4,u,7>: Cost 3 vext1 <4,6,4,u>, <7,0,1,2>
- 1631604283U, // <6,4,u,u>: Cost 2 vext3 <3,4,5,6>, RHS
- 3717349376U, // <6,5,0,0>: Cost 4 vext2 <4,3,6,5>, <0,0,0,0>
- 2643607654U, // <6,5,0,1>: Cost 3 vext2 <4,3,6,5>, LHS
- 3779087952U, // <6,5,0,2>: Cost 4 vext3 <3,4,5,6>, <5,0,2,1>
- 3322400830U, // <6,5,0,3>: Cost 4 vrev <5,6,3,0>
- 3718013266U, // <6,5,0,4>: Cost 4 vext2 <4,4,6,5>, <0,4,1,5>
- 3718013342U, // <6,5,0,5>: Cost 4 vext2 <4,4,6,5>, <0,5,1,0>
- 3779087988U, // <6,5,0,6>: Cost 4 vext3 <3,4,5,6>, <5,0,6,1>
+ 2572389686U, // <6,4,7,4>: Cost 3 vext1 <3,6,4,7>, RHS
+ 2980497102U, // <6,4,7,5>: Cost 3 vzipr RHS, <2,3,4,5>
+ 2980495564U, // <6,4,7,6>: Cost 3 vzipr RHS, <0,2,4,6>
+ 4054239090U, // <6,4,7,7>: Cost 4 vzipr RHS, <2,5,4,7>
+ 2572392238U, // <6,4,7,u>: Cost 3 vext1 <3,6,4,7>, LHS
+ 1504608358U, // <6,4,u,0>: Cost 2 vext1 <4,6,4,6>, LHS
+ 2629670702U, // <6,4,u,1>: Cost 3 vext2 <2,0,6,4>, LHS
+ 2566424516U, // <6,4,u,2>: Cost 3 vext1 <2,6,4,u>, <2,6,4,u>
+ 2584340994U, // <6,4,u,3>: Cost 3 vext1 <5,6,4,u>, <3,4,5,6>
+ 1640156694U, // <6,4,u,4>: Cost 2 vext3 <4,u,4,6>, <4,u,4,6>
+ 2629671066U, // <6,4,u,5>: Cost 3 vext2 <2,0,6,4>, RHS
+ 1612287529U, // <6,4,u,6>: Cost 2 vext3 <0,2,4,6>, RHS
+ 2852965929U, // <6,4,u,7>: Cost 3 vuzpr <5,6,7,4>, RHS
+ 1612287547U, // <6,4,u,u>: Cost 2 vext3 <0,2,4,6>, RHS
+ 3708723200U, // <6,5,0,0>: Cost 4 vext2 <2,u,6,5>, <0,0,0,0>
+ 2634981478U, // <6,5,0,1>: Cost 3 vext2 <2,u,6,5>, LHS
+ 3694125260U, // <6,5,0,2>: Cost 4 vext2 <0,4,6,5>, <0,2,4,6>
+ 3779087962U, // <6,5,0,3>: Cost 4 vext3 <3,4,5,6>, <5,0,3,2>
+ 3760877154U, // <6,5,0,4>: Cost 4 vext3 <0,4,1,6>, <5,0,4,1>
+ 4195110916U, // <6,5,0,5>: Cost 4 vtrnr <5,6,7,0>, <5,5,5,5>
+ 3696779775U, // <6,5,0,6>: Cost 4 vext2 <0,u,6,5>, <0,6,2,7>
1175212130U, // <6,5,0,7>: Cost 2 vrev <5,6,7,0>
1175285867U, // <6,5,0,u>: Cost 2 vrev <5,6,u,0>
2248445988U, // <6,5,1,0>: Cost 3 vrev <5,6,0,1>
- 3716023092U, // <6,5,1,1>: Cost 4 vext2 <4,1,6,5>, <1,1,1,1>
- 3717350294U, // <6,5,1,2>: Cost 4 vext2 <4,3,6,5>, <1,2,3,0>
- 3658099202U, // <6,5,1,3>: Cost 4 vext1 <5,6,5,1>, <3,4,5,6>
+ 3698107237U, // <6,5,1,1>: Cost 4 vext2 <1,1,6,5>, <1,1,6,5>
+ 3708724118U, // <6,5,1,2>: Cost 4 vext2 <2,u,6,5>, <1,2,3,0>
+ 3908575334U, // <6,5,1,3>: Cost 4 vuzpr <2,6,4,5>, LHS
3716023376U, // <6,5,1,4>: Cost 4 vext2 <4,1,6,5>, <1,4,5,6>
- 3652128464U, // <6,5,1,5>: Cost 4 vext1 <4,6,5,1>, <5,1,7,3>
- 3767144133U, // <6,5,1,6>: Cost 4 vext3 <1,4,5,6>, <5,1,6,1>
- 2705346256U, // <6,5,1,7>: Cost 3 vext3 <3,4,5,6>, <5,1,7,3>
- 2705346265U, // <6,5,1,u>: Cost 3 vext3 <3,4,5,6>, <5,1,u,3>
+ 3708724368U, // <6,5,1,5>: Cost 4 vext2 <2,u,6,5>, <1,5,3,7>
+ 3767733960U, // <6,5,1,6>: Cost 4 vext3 <1,5,4,6>, <5,1,6,4>
+ 2712571600U, // <6,5,1,7>: Cost 3 vext3 <4,6,4,6>, <5,1,7,3>
+ 2712571609U, // <6,5,1,u>: Cost 3 vext3 <4,6,4,6>, <5,1,u,3>
2578391142U, // <6,5,2,0>: Cost 3 vext1 <4,6,5,2>, LHS
- 3779088107U, // <6,5,2,1>: Cost 4 vext3 <3,4,5,6>, <5,2,1,3>
- 3717351016U, // <6,5,2,2>: Cost 4 vext2 <4,3,6,5>, <2,2,2,2>
- 3779088126U, // <6,5,2,3>: Cost 4 vext3 <3,4,5,6>, <5,2,3,4>
- 2632329009U, // <6,5,2,4>: Cost 3 vext2 <2,4,6,5>, <2,4,6,5>
+ 3704079934U, // <6,5,2,1>: Cost 4 vext2 <2,1,6,5>, <2,1,6,5>
+ 3708724840U, // <6,5,2,2>: Cost 4 vext2 <2,u,6,5>, <2,2,2,2>
+ 3705407182U, // <6,5,2,3>: Cost 4 vext2 <2,3,6,5>, <2,3,4,5>
+ 2578394422U, // <6,5,2,4>: Cost 3 vext1 <4,6,5,2>, RHS
3717351272U, // <6,5,2,5>: Cost 4 vext2 <4,3,6,5>, <2,5,3,6>
- 2705346328U, // <6,5,2,6>: Cost 3 vext3 <3,4,5,6>, <5,2,6,3>
- 3047607628U, // <6,5,2,7>: Cost 3 vtrnl RHS, <4,6,0,2>
- 3047615820U, // <6,5,2,u>: Cost 3 vtrnl RHS, <4,6,0,2>
- 3717351574U, // <6,5,3,0>: Cost 4 vext2 <4,3,6,5>, <3,0,1,2>
+ 2634983354U, // <6,5,2,6>: Cost 3 vext2 <2,u,6,5>, <2,6,3,7>
+ 3115486518U, // <6,5,2,7>: Cost 3 vtrnr <4,6,u,2>, RHS
+ 2634983541U, // <6,5,2,u>: Cost 3 vext2 <2,u,6,5>, <2,u,6,5>
+ 3708725398U, // <6,5,3,0>: Cost 4 vext2 <2,u,6,5>, <3,0,1,2>
3710052631U, // <6,5,3,1>: Cost 4 vext2 <3,1,6,5>, <3,1,6,5>
- 3322351672U, // <6,5,3,2>: Cost 4 vrev <5,6,2,3>
- 3779088207U, // <6,5,3,3>: Cost 4 vext3 <3,4,5,6>, <5,3,3,4>
+ 3708725606U, // <6,5,3,2>: Cost 4 vext2 <2,u,6,5>, <3,2,6,3>
+ 3708725660U, // <6,5,3,3>: Cost 4 vext2 <2,u,6,5>, <3,3,3,3>
2643610114U, // <6,5,3,4>: Cost 3 vext2 <4,3,6,5>, <3,4,5,6>
- 3913306765U, // <6,5,3,5>: Cost 4 vuzpr <3,4,5,6>, <6,4,5,6>
- 3779088232U, // <6,5,3,6>: Cost 4 vext3 <3,4,5,6>, <5,3,6,2>
+ 3717352010U, // <6,5,3,5>: Cost 4 vext2 <4,3,6,5>, <3,5,4,6>
+ 3773632358U, // <6,5,3,6>: Cost 4 vext3 <2,5,3,6>, <5,3,6,0>
2248978533U, // <6,5,3,7>: Cost 3 vrev <5,6,7,3>
2249052270U, // <6,5,3,u>: Cost 3 vrev <5,6,u,3>
- 2644274066U, // <6,5,4,0>: Cost 3 vext2 <4,4,6,5>, <4,0,5,1>
+ 2596323430U, // <6,5,4,0>: Cost 3 vext1 <7,6,5,4>, LHS
3716025328U, // <6,5,4,1>: Cost 4 vext2 <4,1,6,5>, <4,1,6,5>
3716688961U, // <6,5,4,2>: Cost 4 vext2 <4,2,6,5>, <4,2,6,5>
2643610770U, // <6,5,4,3>: Cost 3 vext2 <4,3,6,5>, <4,3,6,5>
- 2644274403U, // <6,5,4,4>: Cost 3 vext2 <4,4,6,5>, <4,4,6,5>
- 2643610934U, // <6,5,4,5>: Cost 3 vext2 <4,3,6,5>, RHS
- 3779088316U, // <6,5,4,6>: Cost 4 vext3 <3,4,5,6>, <5,4,6,5>
+ 2596326710U, // <6,5,4,4>: Cost 3 vext1 <7,6,5,4>, RHS
+ 2634984758U, // <6,5,4,5>: Cost 3 vext2 <2,u,6,5>, RHS
+ 3767734199U, // <6,5,4,6>: Cost 4 vext3 <1,5,4,6>, <5,4,6,0>
1643696070U, // <6,5,4,7>: Cost 2 vext3 <5,4,7,6>, <5,4,7,6>
1643769807U, // <6,5,4,u>: Cost 2 vext3 <5,4,u,6>, <5,4,u,6>
- 3718016637U, // <6,5,5,0>: Cost 4 vext2 <4,4,6,5>, <5,0,7,1>
- 3717353168U, // <6,5,5,1>: Cost 4 vext2 <4,3,6,5>, <5,1,7,3>
- 3717353240U, // <6,5,5,2>: Cost 4 vext2 <4,3,6,5>, <5,2,6,3>
- 3723325291U, // <6,5,5,3>: Cost 4 vext2 <5,3,6,5>, <5,3,6,5>
- 2650247100U, // <6,5,5,4>: Cost 3 vext2 <5,4,6,5>, <5,4,6,5>
+ 2578415718U, // <6,5,5,0>: Cost 3 vext1 <4,6,5,5>, LHS
+ 3652158198U, // <6,5,5,1>: Cost 4 vext1 <4,6,5,5>, <1,0,3,2>
+ 3652159080U, // <6,5,5,2>: Cost 4 vext1 <4,6,5,5>, <2,2,2,2>
+ 3652159638U, // <6,5,5,3>: Cost 4 vext1 <4,6,5,5>, <3,0,1,2>
+ 2578418998U, // <6,5,5,4>: Cost 3 vext1 <4,6,5,5>, RHS
2712571908U, // <6,5,5,5>: Cost 3 vext3 <4,6,4,6>, <5,5,5,5>
- 2650247266U, // <6,5,5,6>: Cost 3 vext2 <5,4,6,5>, <5,6,7,0>
+ 2718027790U, // <6,5,5,6>: Cost 3 vext3 <5,5,6,6>, <5,5,6,6>
2712571928U, // <6,5,5,7>: Cost 3 vext3 <4,6,4,6>, <5,5,7,7>
2712571937U, // <6,5,5,u>: Cost 3 vext3 <4,6,4,6>, <5,5,u,7>
2705346596U, // <6,5,6,0>: Cost 3 vext3 <3,4,5,6>, <5,6,0,1>
- 3767144493U, // <6,5,6,1>: Cost 4 vext3 <1,4,5,6>, <5,6,1,1>
+ 3767144496U, // <6,5,6,1>: Cost 4 vext3 <1,4,5,6>, <5,6,1,4>
3773116473U, // <6,5,6,2>: Cost 4 vext3 <2,4,5,6>, <5,6,2,4>
2705346626U, // <6,5,6,3>: Cost 3 vext3 <3,4,5,6>, <5,6,3,4>
2705346636U, // <6,5,6,4>: Cost 3 vext3 <3,4,5,6>, <5,6,4,5>
- 3779088465U, // <6,5,6,5>: Cost 4 vext3 <3,4,5,6>, <5,6,5,1>
- 2656219960U, // <6,5,6,6>: Cost 3 vext2 <6,4,6,5>, <6,6,6,6>
- 3047607668U, // <6,5,6,7>: Cost 3 vtrnl RHS, <4,6,4,6>
+ 3908577217U, // <6,5,6,5>: Cost 4 vuzpr <2,6,4,5>, <2,6,4,5>
+ 2578428728U, // <6,5,6,6>: Cost 3 vext1 <4,6,5,6>, <6,6,6,6>
+ 2712572002U, // <6,5,6,7>: Cost 3 vext3 <4,6,4,6>, <5,6,7,0>
2705346668U, // <6,5,6,u>: Cost 3 vext3 <3,4,5,6>, <5,6,u,1>
- 2578432102U, // <6,5,7,0>: Cost 3 vext1 <4,6,5,7>, LHS
- 2909949238U, // <6,5,7,1>: Cost 3 vzipl <4,0,5,1>, RHS
- 2578433742U, // <6,5,7,2>: Cost 3 vext1 <4,6,5,7>, <2,3,4,5>
- 3978399030U, // <6,5,7,3>: Cost 4 vzipl <3,1,5,3>, RHS
- 2578435382U, // <6,5,7,4>: Cost 3 vext1 <4,6,5,7>, RHS
- 2919271734U, // <6,5,7,5>: Cost 3 vzipl <5,5,5,5>, RHS
- 2906672438U, // <6,5,7,6>: Cost 3 vzipl <3,4,5,6>, RHS
- 3047606202U, // <6,5,7,7>: Cost 3 vtrnl RHS, <2,6,3,7>
- 2906688822U, // <6,5,7,u>: Cost 3 vzipl <3,4,5,u>, RHS
- 2248503339U, // <6,5,u,0>: Cost 3 vrev <5,6,0,u>
- 2909949239U, // <6,5,u,1>: Cost 3 vzipl <4,0,5,1>, RHS
- 2578433742U, // <6,5,u,2>: Cost 3 vext1 <4,6,5,7>, <2,3,4,5>
- 2248724550U, // <6,5,u,3>: Cost 3 vrev <5,6,3,u>
- 2248798287U, // <6,5,u,4>: Cost 3 vrev <5,6,4,u>
- 2643613850U, // <6,5,u,5>: Cost 3 vext2 <4,3,6,5>, RHS
- 2705346814U, // <6,5,u,6>: Cost 3 vext3 <3,4,5,6>, <5,u,6,3>
+ 2560516198U, // <6,5,7,0>: Cost 3 vext1 <1,6,5,7>, LHS
+ 2560517363U, // <6,5,7,1>: Cost 3 vext1 <1,6,5,7>, <1,6,5,7>
+ 2566490060U, // <6,5,7,2>: Cost 3 vext1 <2,6,5,7>, <2,6,5,7>
+ 3634260118U, // <6,5,7,3>: Cost 4 vext1 <1,6,5,7>, <3,0,1,2>
+ 2560519478U, // <6,5,7,4>: Cost 3 vext1 <1,6,5,7>, RHS
+ 2980498650U, // <6,5,7,5>: Cost 3 vzipr RHS, <4,4,5,5>
+ 2980497922U, // <6,5,7,6>: Cost 3 vzipr RHS, <3,4,5,6>
+ 3103214902U, // <6,5,7,7>: Cost 3 vtrnr <2,6,3,7>, RHS
+ 2560522030U, // <6,5,7,u>: Cost 3 vext1 <1,6,5,7>, LHS
+ 2560524390U, // <6,5,u,0>: Cost 3 vext1 <1,6,5,u>, LHS
+ 2560525556U, // <6,5,u,1>: Cost 3 vext1 <1,6,5,u>, <1,6,5,u>
+ 2566498253U, // <6,5,u,2>: Cost 3 vext1 <2,6,5,u>, <2,6,5,u>
+ 2646931439U, // <6,5,u,3>: Cost 3 vext2 <4,u,6,5>, <u,3,5,7>
+ 2560527670U, // <6,5,u,4>: Cost 3 vext1 <1,6,5,u>, RHS
+ 2634987674U, // <6,5,u,5>: Cost 3 vext2 <2,u,6,5>, RHS
+ 2980506114U, // <6,5,u,6>: Cost 3 vzipr RHS, <3,4,5,6>
1175277674U, // <6,5,u,7>: Cost 2 vrev <5,6,7,u>
1175351411U, // <6,5,u,u>: Cost 2 vrev <5,6,u,u>
2578448486U, // <6,6,0,0>: Cost 3 vext1 <4,6,6,0>, LHS
- 1583808614U, // <6,6,0,1>: Cost 2 vext2 <6,6,6,6>, LHS
- 2657550500U, // <6,6,0,2>: Cost 3 vext2 <6,6,6,6>, <0,2,0,2>
- 3652192406U, // <6,6,0,3>: Cost 4 vext1 <4,6,6,0>, <3,0,1,2>
- 2578451684U, // <6,6,0,4>: Cost 3 vext1 <4,6,6,0>, <4,4,6,6>
+ 1573191782U, // <6,6,0,1>: Cost 2 vext2 <4,u,6,6>, LHS
+ 2686030124U, // <6,6,0,2>: Cost 3 vext3 <0,2,4,6>, <6,0,2,4>
+ 3779088690U, // <6,6,0,3>: Cost 4 vext3 <3,4,5,6>, <6,0,3,1>
+ 2687209788U, // <6,6,0,4>: Cost 3 vext3 <0,4,2,6>, <6,0,4,2>
3652194000U, // <6,6,0,5>: Cost 4 vext1 <4,6,6,0>, <5,1,7,3>
- 2602341198U, // <6,6,0,6>: Cost 3 vext1 <u,6,6,0>, <6,7,0,1>
- 3766038871U, // <6,6,0,7>: Cost 4 vext3 <1,2,u,6>, <6,0,7,2>
- 1583809181U, // <6,6,0,u>: Cost 2 vext2 <6,6,6,6>, LHS
- 2657551094U, // <6,6,1,0>: Cost 3 vext2 <6,6,6,6>, <1,0,3,2>
- 2657551156U, // <6,6,1,1>: Cost 3 vext2 <6,6,6,6>, <1,1,1,1>
- 2657551254U, // <6,6,1,2>: Cost 3 vext2 <6,6,6,6>, <1,2,3,0>
- 3731293134U, // <6,6,1,3>: Cost 4 vext2 <6,6,6,6>, <1,3,0,2>
- 3767144848U, // <6,6,1,4>: Cost 4 vext3 <1,4,5,6>, <6,1,4,5>
- 2657551504U, // <6,6,1,5>: Cost 3 vext2 <6,6,6,6>, <1,5,3,7>
+ 2254852914U, // <6,6,0,6>: Cost 3 vrev <6,6,6,0>
+ 4041575734U, // <6,6,0,7>: Cost 4 vzipr <2,4,6,0>, RHS
+ 1573192349U, // <6,6,0,u>: Cost 2 vext2 <4,u,6,6>, LHS
+ 2646934262U, // <6,6,1,0>: Cost 3 vext2 <4,u,6,6>, <1,0,3,2>
+ 2646934324U, // <6,6,1,1>: Cost 3 vext2 <4,u,6,6>, <1,1,1,1>
+ 2646934422U, // <6,6,1,2>: Cost 3 vext2 <4,u,6,6>, <1,2,3,0>
+ 2846785638U, // <6,6,1,3>: Cost 3 vuzpr <4,6,4,6>, LHS
+ 3760951694U, // <6,6,1,4>: Cost 4 vext3 <0,4,2,6>, <6,1,4,3>
+ 2646934672U, // <6,6,1,5>: Cost 3 vext2 <4,u,6,6>, <1,5,3,7>
2712572320U, // <6,6,1,6>: Cost 3 vext3 <4,6,4,6>, <6,1,6,3>
- 3767144871U, // <6,6,1,7>: Cost 4 vext3 <1,4,5,6>, <6,1,7,1>
- 2657551740U, // <6,6,1,u>: Cost 3 vext2 <6,6,6,6>, <1,u,3,0>
- 3646234726U, // <6,6,2,0>: Cost 4 vext1 <3,6,6,2>, LHS
- 3646236034U, // <6,6,2,1>: Cost 4 vext1 <3,6,6,2>, <1,u,3,6>
- 2910030748U, // <6,6,2,2>: Cost 3 vzipl <4,0,6,2>, <4,0,6,2>
- 2657552038U, // <6,6,2,3>: Cost 3 vext2 <6,6,6,6>, <2,3,0,1>
- 3646238006U, // <6,6,2,4>: Cost 4 vext1 <3,6,6,2>, RHS
- 3712714600U, // <6,6,2,5>: Cost 4 vext2 <3,5,6,6>, <2,5,3,6>
- 2657552314U, // <6,6,2,6>: Cost 3 vext2 <6,6,6,6>, <2,6,3,7>
- 2692297210U, // <6,6,2,7>: Cost 3 vext3 <1,2,u,6>, <6,2,7,3>
- 2705347075U, // <6,6,2,u>: Cost 3 vext3 <3,4,5,6>, <6,2,u,3>
- 2657552534U, // <6,6,3,0>: Cost 3 vext2 <6,6,6,6>, <3,0,1,2>
- 3731294430U, // <6,6,3,1>: Cost 4 vext2 <6,6,6,6>, <3,1,0,2>
- 3731294510U, // <6,6,3,2>: Cost 4 vext2 <6,6,6,6>, <3,2,0,1>
- 2657552796U, // <6,6,3,3>: Cost 3 vext2 <6,6,6,6>, <3,3,3,3>
+ 3775549865U, // <6,6,1,7>: Cost 4 vext3 <2,u,2,6>, <6,1,7,3>
+ 2846785643U, // <6,6,1,u>: Cost 3 vuzpr <4,6,4,6>, LHS
+ 3759772094U, // <6,6,2,0>: Cost 4 vext3 <0,2,4,6>, <6,2,0,6>
+ 3704751676U, // <6,6,2,1>: Cost 4 vext2 <2,2,6,6>, <2,1,6,3>
+ 2631009936U, // <6,6,2,2>: Cost 3 vext2 <2,2,6,6>, <2,2,6,6>
+ 2646935206U, // <6,6,2,3>: Cost 3 vext2 <4,u,6,6>, <2,3,0,1>
+ 3759772127U, // <6,6,2,4>: Cost 4 vext3 <0,2,4,6>, <6,2,4,3>
+ 3704752004U, // <6,6,2,5>: Cost 4 vext2 <2,2,6,6>, <2,5,6,7>
+ 2646935482U, // <6,6,2,6>: Cost 3 vext2 <4,u,6,6>, <2,6,3,7>
+ 2712572410U, // <6,6,2,7>: Cost 3 vext3 <4,6,4,6>, <6,2,7,3>
+ 2712572419U, // <6,6,2,u>: Cost 3 vext3 <4,6,4,6>, <6,2,u,3>
+ 2646935702U, // <6,6,3,0>: Cost 3 vext2 <4,u,6,6>, <3,0,1,2>
+ 3777024534U, // <6,6,3,1>: Cost 4 vext3 <3,1,4,6>, <6,3,1,4>
+ 3704752453U, // <6,6,3,2>: Cost 4 vext2 <2,2,6,6>, <3,2,2,6>
+ 2646935964U, // <6,6,3,3>: Cost 3 vext2 <4,u,6,6>, <3,3,3,3>
2705347122U, // <6,6,3,4>: Cost 3 vext3 <3,4,5,6>, <6,3,4,5>
- 3779088950U, // <6,6,3,5>: Cost 4 vext3 <3,4,5,6>, <6,3,5,0>
- 2639637165U, // <6,6,3,6>: Cost 3 vext2 <3,6,6,6>, <3,6,6,6>
- 3779088968U, // <6,6,3,7>: Cost 4 vext3 <3,4,5,6>, <6,3,7,0>
+ 3779678778U, // <6,6,3,5>: Cost 4 vext3 <3,5,4,6>, <6,3,5,4>
+ 2657553069U, // <6,6,3,6>: Cost 3 vext2 <6,6,6,6>, <3,6,6,6>
+ 4039609654U, // <6,6,3,7>: Cost 4 vzipr <2,1,6,3>, RHS
2708001366U, // <6,6,3,u>: Cost 3 vext3 <3,u,5,6>, <6,3,u,5>
2578481254U, // <6,6,4,0>: Cost 3 vext1 <4,6,6,4>, LHS
- 3779089001U, // <6,6,4,1>: Cost 4 vext3 <3,4,5,6>, <6,4,1,6>
- 3716697154U, // <6,6,4,2>: Cost 4 vext2 <4,2,6,6>, <4,2,6,6>
+ 3652223734U, // <6,6,4,1>: Cost 4 vext1 <4,6,6,4>, <1,0,3,2>
+ 3760951922U, // <6,6,4,2>: Cost 4 vext3 <0,4,2,6>, <6,4,2,6>
3779089019U, // <6,6,4,3>: Cost 4 vext3 <3,4,5,6>, <6,4,3,6>
1570540772U, // <6,6,4,4>: Cost 2 vext2 <4,4,6,6>, <4,4,6,6>
- 1583811894U, // <6,6,4,5>: Cost 2 vext2 <6,6,6,6>, RHS
- 2846282552U, // <6,6,4,6>: Cost 3 vuzpr RHS, <6,6,6,6>
+ 1573195062U, // <6,6,4,5>: Cost 2 vext2 <4,u,6,6>, RHS
+ 2712572560U, // <6,6,4,6>: Cost 3 vext3 <4,6,4,6>, <6,4,6,0>
2723410591U, // <6,6,4,7>: Cost 3 vext3 <6,4,7,6>, <6,4,7,6>
- 1583812137U, // <6,6,4,u>: Cost 2 vext2 <6,6,6,6>, RHS
- 3786314418U, // <6,6,5,0>: Cost 4 vext3 <4,6,4,6>, <6,5,0,7>
- 2657554128U, // <6,6,5,1>: Cost 3 vext2 <6,6,6,6>, <5,1,7,3>
- 3779089091U, // <6,6,5,2>: Cost 4 vext3 <3,4,5,6>, <6,5,2,6>
- 3658205698U, // <6,6,5,3>: Cost 4 vext1 <5,6,6,5>, <3,4,5,6>
- 2717438678U, // <6,6,5,4>: Cost 3 vext3 <5,4,7,6>, <6,5,4,7>
- 2650918926U, // <6,6,5,5>: Cost 3 vext2 <5,5,6,6>, <5,5,6,6>
- 2712572648U, // <6,6,5,6>: Cost 3 vext3 <4,6,4,6>, <6,5,6,7>
- 2724074224U, // <6,6,5,7>: Cost 3 vext3 <6,5,7,6>, <6,5,7,6>
- 2657554692U, // <6,6,5,u>: Cost 3 vext2 <6,6,6,6>, <5,u,7,0>
+ 1573195304U, // <6,6,4,u>: Cost 2 vext2 <4,u,6,6>, <4,u,6,6>
+ 3640287334U, // <6,6,5,0>: Cost 4 vext1 <2,6,6,5>, LHS
+ 2646937296U, // <6,6,5,1>: Cost 3 vext2 <4,u,6,6>, <5,1,7,3>
+ 3640289235U, // <6,6,5,2>: Cost 4 vext1 <2,6,6,5>, <2,6,6,5>
+ 3720679279U, // <6,6,5,3>: Cost 4 vext2 <4,u,6,6>, <5,3,7,0>
+ 2646937542U, // <6,6,5,4>: Cost 3 vext2 <4,u,6,6>, <5,4,7,6>
+ 2646937604U, // <6,6,5,5>: Cost 3 vext2 <4,u,6,6>, <5,5,5,5>
+ 2646937698U, // <6,6,5,6>: Cost 3 vext2 <4,u,6,6>, <5,6,7,0>
+ 2846788918U, // <6,6,5,7>: Cost 3 vuzpr <4,6,4,6>, RHS
+ 2846788919U, // <6,6,5,u>: Cost 3 vuzpr <4,6,4,6>, RHS
1516699750U, // <6,6,6,0>: Cost 2 vext1 <6,6,6,6>, LHS
2590442230U, // <6,6,6,1>: Cost 3 vext1 <6,6,6,6>, <1,0,3,2>
- 2590443112U, // <6,6,6,2>: Cost 3 vext1 <6,6,6,6>, <2,2,2,2>
+ 2646938106U, // <6,6,6,2>: Cost 3 vext2 <4,u,6,6>, <6,2,7,3>
2590443670U, // <6,6,6,3>: Cost 3 vext1 <6,6,6,6>, <3,0,1,2>
1516703030U, // <6,6,6,4>: Cost 2 vext1 <6,6,6,6>, RHS
2590445264U, // <6,6,6,5>: Cost 3 vext1 <6,6,6,6>, <5,1,7,3>
296144182U, // <6,6,6,6>: Cost 1 vdup2 RHS
- 2913391416U, // <6,6,6,7>: Cost 3 vzipl RHS, <6,6,6,6>
+ 2712572738U, // <6,6,6,7>: Cost 3 vext3 <4,6,4,6>, <6,6,7,7>
296144182U, // <6,6,6,u>: Cost 1 vdup2 RHS
- 2712572750U, // <6,6,7,0>: Cost 3 vext3 <4,6,4,6>, <6,7,0,1>
- 3983764790U, // <6,6,7,1>: Cost 4 vzipl <4,0,6,1>, RHS
- 2910031158U, // <6,6,7,2>: Cost 3 vzipl <4,0,6,2>, RHS
+ 2566561894U, // <6,6,7,0>: Cost 3 vext1 <2,6,6,7>, LHS
+ 3634332924U, // <6,6,7,1>: Cost 4 vext1 <1,6,6,7>, <1,6,6,7>
+ 2566563797U, // <6,6,7,2>: Cost 3 vext1 <2,6,6,7>, <2,6,6,7>
2584480258U, // <6,6,7,3>: Cost 3 vext1 <5,6,6,7>, <3,4,5,6>
- 2712572790U, // <6,6,7,4>: Cost 3 vext3 <4,6,4,6>, <6,7,4,5>
+ 2566565174U, // <6,6,7,4>: Cost 3 vext1 <2,6,6,7>, RHS
2717438846U, // <6,6,7,5>: Cost 3 vext3 <5,4,7,6>, <6,7,5,4>
- 2657555985U, // <6,6,7,6>: Cost 3 vext2 <6,6,6,6>, <7,6,6,6>
- 1839648054U, // <6,6,7,7>: Cost 2 vzipl RHS, RHS
- 1839656246U, // <6,6,7,u>: Cost 2 vzipl RHS, RHS
+ 2980500280U, // <6,6,7,6>: Cost 3 vzipr RHS, <6,6,6,6>
+ 1906756918U, // <6,6,7,7>: Cost 2 vzipr RHS, RHS
+ 1906756919U, // <6,6,7,u>: Cost 2 vzipr RHS, RHS
1516699750U, // <6,6,u,0>: Cost 2 vext1 <6,6,6,6>, LHS
- 1583814446U, // <6,6,u,1>: Cost 2 vext2 <6,6,6,6>, LHS
- 2910031159U, // <6,6,u,2>: Cost 3 vzipl <4,0,6,2>, RHS
- 2657556412U, // <6,6,u,3>: Cost 3 vext2 <6,6,6,6>, <u,3,0,1>
- 1594431560U, // <6,6,u,4>: Cost 2 vext2 <u,4,6,6>, <u,4,6,6>
- 1583814810U, // <6,6,u,5>: Cost 2 vext2 <6,6,6,6>, RHS
+ 1573197614U, // <6,6,u,1>: Cost 2 vext2 <4,u,6,6>, LHS
+ 2566571990U, // <6,6,u,2>: Cost 3 vext1 <2,6,6,u>, <2,6,6,u>
+ 2846786205U, // <6,6,u,3>: Cost 3 vuzpr <4,6,4,6>, LHS
+ 1516703030U, // <6,6,u,4>: Cost 2 vext1 <6,6,6,6>, RHS
+ 1573197978U, // <6,6,u,5>: Cost 2 vext2 <4,u,6,6>, RHS
296144182U, // <6,6,u,6>: Cost 1 vdup2 RHS
- 1839648055U, // <6,6,u,7>: Cost 2 vzipl RHS, RHS
+ 1906765110U, // <6,6,u,7>: Cost 2 vzipr RHS, RHS
296144182U, // <6,6,u,u>: Cost 1 vdup2 RHS
1571209216U, // <6,7,0,0>: Cost 2 vext2 RHS, <0,0,0,0>
497467494U, // <6,7,0,1>: Cost 1 vext2 RHS, LHS
1571209380U, // <6,7,0,2>: Cost 2 vext2 RHS, <0,2,0,2>
- 2644951301U, // <6,7,0,3>: Cost 3 vext2 RHS, <0,3,2,0>
- 1573200210U, // <6,7,0,4>: Cost 2 vext2 RHS, <0,4,1,5>
+ 2644951292U, // <6,7,0,3>: Cost 3 vext2 RHS, <0,3,1,0>
+ 1571209554U, // <6,7,0,4>: Cost 2 vext2 RHS, <0,4,1,5>
1510756450U, // <6,7,0,5>: Cost 2 vext1 <5,6,7,0>, <5,6,7,0>
- 2644951544U, // <6,7,0,6>: Cost 3 vext2 RHS, <0,6,2,0>
+ 2644951542U, // <6,7,0,6>: Cost 3 vext2 RHS, <0,6,1,7>
2584499194U, // <6,7,0,7>: Cost 3 vext1 <5,6,7,0>, <7,0,1,2>
497468061U, // <6,7,0,u>: Cost 1 vext2 RHS, LHS
1571209974U, // <6,7,1,0>: Cost 2 vext2 RHS, <1,0,3,2>
1571210036U, // <6,7,1,1>: Cost 2 vext2 RHS, <1,1,1,1>
1571210134U, // <6,7,1,2>: Cost 2 vext2 RHS, <1,2,3,0>
- 2644952014U, // <6,7,1,3>: Cost 3 vext2 RHS, <1,3,0,2>
+ 1571210200U, // <6,7,1,3>: Cost 2 vext2 RHS, <1,3,1,3>
2644952098U, // <6,7,1,4>: Cost 3 vext2 RHS, <1,4,0,5>
- 1573201040U, // <6,7,1,5>: Cost 2 vext2 RHS, <1,5,3,7>
- 2646942927U, // <6,7,1,6>: Cost 3 vext2 RHS, <1,6,1,7>
- 2668840235U, // <6,7,1,7>: Cost 3 vext2 RHS, <1,7,3,0>
- 1571210620U, // <6,7,1,u>: Cost 2 vext2 RHS, <1,u,3,0>
- 2644952500U, // <6,7,2,0>: Cost 3 vext2 RHS, <2,0,0,2>
+ 1571210384U, // <6,7,1,5>: Cost 2 vext2 RHS, <1,5,3,7>
+ 2644952271U, // <6,7,1,6>: Cost 3 vext2 RHS, <1,6,1,7>
+ 2578535418U, // <6,7,1,7>: Cost 3 vext1 <4,6,7,1>, <7,0,1,2>
+ 1571210605U, // <6,7,1,u>: Cost 2 vext2 RHS, <1,u,1,3>
+ 2644952509U, // <6,7,2,0>: Cost 3 vext2 RHS, <2,0,1,2>
2644952582U, // <6,7,2,1>: Cost 3 vext2 RHS, <2,1,0,3>
1571210856U, // <6,7,2,2>: Cost 2 vext2 RHS, <2,2,2,2>
1571210918U, // <6,7,2,3>: Cost 2 vext2 RHS, <2,3,0,1>
- 2644952824U, // <6,7,2,4>: Cost 3 vext2 RHS, <2,4,0,2>
- 2644952931U, // <6,7,2,5>: Cost 3 vext2 RHS, <2,5,3,1>
- 1573201850U, // <6,7,2,6>: Cost 2 vext2 RHS, <2,6,3,7>
+ 2644952828U, // <6,7,2,4>: Cost 3 vext2 RHS, <2,4,0,6>
+ 2633009028U, // <6,7,2,5>: Cost 3 vext2 <2,5,6,7>, <2,5,6,7>
+ 1571211194U, // <6,7,2,6>: Cost 2 vext2 RHS, <2,6,3,7>
2668840938U, // <6,7,2,7>: Cost 3 vext2 RHS, <2,7,0,1>
1571211323U, // <6,7,2,u>: Cost 2 vext2 RHS, <2,u,0,1>
1571211414U, // <6,7,3,0>: Cost 2 vext2 RHS, <3,0,1,2>
- 2644953310U, // <6,7,3,1>: Cost 3 vext2 RHS, <3,1,0,2>
+ 2644953311U, // <6,7,3,1>: Cost 3 vext2 RHS, <3,1,0,3>
2644953390U, // <6,7,3,2>: Cost 3 vext2 RHS, <3,2,0,1>
1571211676U, // <6,7,3,3>: Cost 2 vext2 RHS, <3,3,3,3>
1571211778U, // <6,7,3,4>: Cost 2 vext2 RHS, <3,4,5,6>
- 2644953634U, // <6,7,3,5>: Cost 3 vext2 RHS, <3,5,0,2>
- 2644953738U, // <6,7,3,6>: Cost 3 vext2 RHS, <3,6,2,7>
- 2668841667U, // <6,7,3,7>: Cost 3 vext2 RHS, <3,7,0,1>
+ 2644953648U, // <6,7,3,5>: Cost 3 vext2 RHS, <3,5,1,7>
+ 2644953720U, // <6,7,3,6>: Cost 3 vext2 RHS, <3,6,0,7>
+ 2644953795U, // <6,7,3,7>: Cost 3 vext2 RHS, <3,7,0,1>
1571212062U, // <6,7,3,u>: Cost 2 vext2 RHS, <3,u,1,2>
- 1571212178U, // <6,7,4,0>: Cost 2 vext2 RHS, <4,0,5,1>
+ 1573202834U, // <6,7,4,0>: Cost 2 vext2 RHS, <4,0,5,1>
2644954058U, // <6,7,4,1>: Cost 3 vext2 RHS, <4,1,2,3>
- 2644954165U, // <6,7,4,2>: Cost 3 vext2 RHS, <4,2,5,2>
- 2644954247U, // <6,7,4,3>: Cost 3 vext2 RHS, <4,3,5,3>
+ 2644954166U, // <6,7,4,2>: Cost 3 vext2 RHS, <4,2,5,3>
+ 2644954258U, // <6,7,4,3>: Cost 3 vext2 RHS, <4,3,6,5>
1571212496U, // <6,7,4,4>: Cost 2 vext2 RHS, <4,4,4,4>
497470774U, // <6,7,4,5>: Cost 1 vext2 RHS, RHS
- 1571212620U, // <6,7,4,6>: Cost 2 vext2 RHS, <4,6,0,2>
- 2584531962U, // <6,7,4,7>: Cost 3 vext1 <5,6,7,4>, <7,0,1,2>
+ 1573203316U, // <6,7,4,6>: Cost 2 vext2 RHS, <4,6,4,6>
+ 2646281688U, // <6,7,4,7>: Cost 3 vext2 <4,7,6,7>, <4,7,6,7>
497471017U, // <6,7,4,u>: Cost 1 vext2 RHS, RHS
- 2644954695U, // <6,7,5,0>: Cost 3 vext2 RHS, <5,0,1,1>
- 1571213008U, // <6,7,5,1>: Cost 2 vext2 RHS, <5,1,7,3>
- 2644954859U, // <6,7,5,2>: Cost 3 vext2 RHS, <5,2,1,3>
- 2644954992U, // <6,7,5,3>: Cost 3 vext2 RHS, <5,3,7,1>
+ 2644954696U, // <6,7,5,0>: Cost 3 vext2 RHS, <5,0,1,2>
+ 1573203664U, // <6,7,5,1>: Cost 2 vext2 RHS, <5,1,7,3>
+ 2644954878U, // <6,7,5,2>: Cost 3 vext2 RHS, <5,2,3,4>
+ 2644954991U, // <6,7,5,3>: Cost 3 vext2 RHS, <5,3,7,0>
1571213254U, // <6,7,5,4>: Cost 2 vext2 RHS, <5,4,7,6>
1571213316U, // <6,7,5,5>: Cost 2 vext2 RHS, <5,5,5,5>
1571213410U, // <6,7,5,6>: Cost 2 vext2 RHS, <5,6,7,0>
- 2644955254U, // <6,7,5,7>: Cost 3 vext2 RHS, <5,7,0,2>
- 1571213575U, // <6,7,5,u>: Cost 2 vext2 RHS, <5,u,7,3>
+ 1573204136U, // <6,7,5,7>: Cost 2 vext2 RHS, <5,7,5,7>
+ 1573204217U, // <6,7,5,u>: Cost 2 vext2 RHS, <5,u,5,7>
2644955425U, // <6,7,6,0>: Cost 3 vext2 RHS, <6,0,1,2>
- 2644955516U, // <6,7,6,1>: Cost 3 vext2 RHS, <6,1,2,3>
- 1571213818U, // <6,7,6,2>: Cost 2 vext2 RHS, <6,2,7,3>
+ 2644955561U, // <6,7,6,1>: Cost 3 vext2 RHS, <6,1,7,3>
+ 1573204474U, // <6,7,6,2>: Cost 2 vext2 RHS, <6,2,7,3>
2644955698U, // <6,7,6,3>: Cost 3 vext2 RHS, <6,3,4,5>
2644955789U, // <6,7,6,4>: Cost 3 vext2 RHS, <6,4,5,6>
- 2644955883U, // <6,7,6,5>: Cost 3 vext2 RHS, <6,5,7,1>
+ 2644955889U, // <6,7,6,5>: Cost 3 vext2 RHS, <6,5,7,7>
1571214136U, // <6,7,6,6>: Cost 2 vext2 RHS, <6,6,6,6>
1571214158U, // <6,7,6,7>: Cost 2 vext2 RHS, <6,7,0,1>
- 1571214304U, // <6,7,6,u>: Cost 2 vext2 RHS, <6,u,7,3>
+ 1573204895U, // <6,7,6,u>: Cost 2 vext2 RHS, <6,u,0,1>
1573204986U, // <6,7,7,0>: Cost 2 vext2 RHS, <7,0,1,2>
- 2646946883U, // <6,7,7,1>: Cost 3 vext2 RHS, <7,1,0,3>
- 2644956335U, // <6,7,7,2>: Cost 3 vext2 RHS, <7,2,3,3>
- 2646947043U, // <6,7,7,3>: Cost 3 vext2 RHS, <7,3,0,1>
+ 2572608656U, // <6,7,7,1>: Cost 3 vext1 <3,6,7,7>, <1,5,3,7>
+ 2644956362U, // <6,7,7,2>: Cost 3 vext2 RHS, <7,2,6,3>
+ 2572610231U, // <6,7,7,3>: Cost 3 vext1 <3,6,7,7>, <3,6,7,7>
1573205350U, // <6,7,7,4>: Cost 2 vext2 RHS, <7,4,5,6>
2646947220U, // <6,7,7,5>: Cost 3 vext2 RHS, <7,5,1,7>
1516786498U, // <6,7,7,6>: Cost 2 vext1 <6,6,7,7>, <6,6,7,7>
1571214956U, // <6,7,7,7>: Cost 2 vext2 RHS, <7,7,7,7>
1573205634U, // <6,7,7,u>: Cost 2 vext2 RHS, <7,u,1,2>
- 1571215058U, // <6,7,u,0>: Cost 2 vext2 RHS, <u,0,1,1>
+ 1571215059U, // <6,7,u,0>: Cost 2 vext2 RHS, <u,0,1,2>
497473326U, // <6,7,u,1>: Cost 1 vext2 RHS, LHS
- 1571215212U, // <6,7,u,2>: Cost 2 vext2 RHS, <u,2,0,2>
+ 1571215237U, // <6,7,u,2>: Cost 2 vext2 RHS, <u,2,3,0>
1571215292U, // <6,7,u,3>: Cost 2 vext2 RHS, <u,3,0,1>
1571215423U, // <6,7,u,4>: Cost 2 vext2 RHS, <u,4,5,6>
497473690U, // <6,7,u,5>: Cost 1 vext2 RHS, RHS
- 1571215536U, // <6,7,u,6>: Cost 2 vext2 RHS, <u,6,0,2>
+ 1571215568U, // <6,7,u,6>: Cost 2 vext2 RHS, <u,6,3,7>
1573206272U, // <6,7,u,7>: Cost 2 vext2 RHS, <u,7,0,1>
497473893U, // <6,7,u,u>: Cost 1 vext2 RHS, LHS
1571217408U, // <6,u,0,0>: Cost 2 vext2 RHS, <0,0,0,0>
497475686U, // <6,u,0,1>: Cost 1 vext2 RHS, LHS
1571217572U, // <6,u,0,2>: Cost 2 vext2 RHS, <0,2,0,2>
- 2705348325U, // <6,u,0,3>: Cost 3 vext3 <3,4,5,6>, <u,0,3,2>
+ 2689865445U, // <6,u,0,3>: Cost 3 vext3 <0,u,2,6>, <u,0,3,2>
1571217746U, // <6,u,0,4>: Cost 2 vext2 RHS, <0,4,1,5>
1510830187U, // <6,u,0,5>: Cost 2 vext1 <5,6,u,0>, <5,6,u,0>
- 2705348352U, // <6,u,0,6>: Cost 3 vext3 <3,4,5,6>, <u,0,6,2>
+ 2644959734U, // <6,u,0,6>: Cost 3 vext2 RHS, <0,6,1,7>
1193130221U, // <6,u,0,7>: Cost 2 vrev <u,6,7,0>
497476253U, // <6,u,0,u>: Cost 1 vext2 RHS, LHS
1571218166U, // <6,u,1,0>: Cost 2 vext2 RHS, <1,0,3,2>
1571218228U, // <6,u,1,1>: Cost 2 vext2 RHS, <1,1,1,1>
- 1631606574U, // <6,u,1,2>: Cost 2 vext3 <3,4,5,6>, LHS
- 2705348407U, // <6,u,1,3>: Cost 3 vext3 <3,4,5,6>, <u,1,3,3>
- 2644960290U, // <6,u,1,4>: Cost 3 vext2 RHS, <1,4,0,5>
+ 1612289838U, // <6,u,1,2>: Cost 2 vext3 <0,2,4,6>, LHS
+ 1571218392U, // <6,u,1,3>: Cost 2 vext2 RHS, <1,3,1,3>
+ 2566663478U, // <6,u,1,4>: Cost 3 vext1 <2,6,u,1>, RHS
1571218576U, // <6,u,1,5>: Cost 2 vext2 RHS, <1,5,3,7>
- 2708002642U, // <6,u,1,6>: Cost 3 vext3 <3,u,5,6>, <u,1,6,3>
- 2705348443U, // <6,u,1,7>: Cost 3 vext3 <3,4,5,6>, <u,1,7,3>
- 1631606628U, // <6,u,1,u>: Cost 2 vext3 <3,4,5,6>, LHS
- 1504280678U, // <6,u,2,0>: Cost 2 vext1 <4,6,0,2>, LHS
+ 2644960463U, // <6,u,1,6>: Cost 3 vext2 RHS, <1,6,1,7>
+ 2717439835U, // <6,u,1,7>: Cost 3 vext3 <5,4,7,6>, <u,1,7,3>
+ 1612289892U, // <6,u,1,u>: Cost 2 vext3 <0,2,4,6>, LHS
+ 1504870502U, // <6,u,2,0>: Cost 2 vext1 <4,6,u,2>, LHS
2644960774U, // <6,u,2,1>: Cost 3 vext2 RHS, <2,1,0,3>
1571219048U, // <6,u,2,2>: Cost 2 vext2 RHS, <2,2,2,2>
1571219110U, // <6,u,2,3>: Cost 2 vext2 RHS, <2,3,0,1>
- 1660065684U, // <6,u,2,4>: Cost 2 vext3 <u,2,4,6>, <u,2,4,6>
- 2644961102U, // <6,u,2,5>: Cost 3 vext2 RHS, <2,5,0,7>
+ 1504873782U, // <6,u,2,4>: Cost 2 vext1 <4,6,u,2>, RHS
+ 2633017221U, // <6,u,2,5>: Cost 3 vext2 <2,5,6,u>, <2,5,6,u>
1571219386U, // <6,u,2,6>: Cost 2 vext2 RHS, <2,6,3,7>
- 2705348524U, // <6,u,2,7>: Cost 3 vext3 <3,4,5,6>, <u,2,7,3>
+ 2712573868U, // <6,u,2,7>: Cost 3 vext3 <4,6,4,6>, <u,2,7,3>
1571219515U, // <6,u,2,u>: Cost 2 vext2 RHS, <2,u,0,1>
1571219606U, // <6,u,3,0>: Cost 2 vext2 RHS, <3,0,1,2>
- 2644961502U, // <6,u,3,1>: Cost 3 vext2 RHS, <3,1,0,2>
- 2644961582U, // <6,u,3,2>: Cost 3 vext2 RHS, <3,2,0,1>
+ 2644961503U, // <6,u,3,1>: Cost 3 vext2 RHS, <3,1,0,3>
+ 2566678499U, // <6,u,3,2>: Cost 3 vext1 <2,6,u,3>, <2,6,u,3>
1571219868U, // <6,u,3,3>: Cost 2 vext2 RHS, <3,3,3,3>
1571219970U, // <6,u,3,4>: Cost 2 vext2 RHS, <3,4,5,6>
- 2644961826U, // <6,u,3,5>: Cost 3 vext2 RHS, <3,5,0,2>
+ 2689865711U, // <6,u,3,5>: Cost 3 vext3 <0,u,2,6>, <u,3,5,7>
2708002806U, // <6,u,3,6>: Cost 3 vext3 <3,u,5,6>, <u,3,6,5>
- 2668849859U, // <6,u,3,7>: Cost 3 vext2 RHS, <3,7,0,1>
+ 2644961987U, // <6,u,3,7>: Cost 3 vext2 RHS, <3,7,0,1>
1571220254U, // <6,u,3,u>: Cost 2 vext2 RHS, <3,u,1,2>
- 1567902626U, // <6,u,4,0>: Cost 2 vext2 <4,0,6,u>, <4,0,6,u>
- 2642308083U, // <6,u,4,1>: Cost 3 vext2 <4,1,6,u>, <4,1,6,u>
+ 1571220370U, // <6,u,4,0>: Cost 2 vext2 RHS, <4,0,5,1>
+ 2644962250U, // <6,u,4,1>: Cost 3 vext2 RHS, <4,1,2,3>
1661245476U, // <6,u,4,2>: Cost 2 vext3 <u,4,2,6>, <u,4,2,6>
- 2643635349U, // <6,u,4,3>: Cost 3 vext2 <4,3,6,u>, <4,3,6,u>
+ 2686031917U, // <6,u,4,3>: Cost 3 vext3 <0,2,4,6>, <u,4,3,6>
1571220688U, // <6,u,4,4>: Cost 2 vext2 RHS, <4,4,4,4>
497478967U, // <6,u,4,5>: Cost 1 vext2 RHS, RHS
- 1571220812U, // <6,u,4,6>: Cost 2 vext2 RHS, <4,6,0,2>
+ 1571220852U, // <6,u,4,6>: Cost 2 vext2 RHS, <4,6,4,6>
1661614161U, // <6,u,4,7>: Cost 2 vext3 <u,4,7,6>, <u,4,7,6>
497479209U, // <6,u,4,u>: Cost 1 vext2 RHS, RHS
- 2644962887U, // <6,u,5,0>: Cost 3 vext2 RHS, <5,0,1,1>
+ 2566692966U, // <6,u,5,0>: Cost 3 vext1 <2,6,u,5>, LHS
1571221200U, // <6,u,5,1>: Cost 2 vext2 RHS, <5,1,7,3>
- 2644963051U, // <6,u,5,2>: Cost 3 vext2 RHS, <5,2,1,3>
- 2644963184U, // <6,u,5,3>: Cost 3 vext2 RHS, <5,3,7,1>
+ 2566694885U, // <6,u,5,2>: Cost 3 vext1 <2,6,u,5>, <2,6,u,5>
+ 2689865855U, // <6,u,5,3>: Cost 3 vext3 <0,u,2,6>, <u,5,3,7>
1571221446U, // <6,u,5,4>: Cost 2 vext2 RHS, <5,4,7,6>
1571221508U, // <6,u,5,5>: Cost 2 vext2 RHS, <5,5,5,5>
- 1631606938U, // <6,u,5,6>: Cost 2 vext3 <3,4,5,6>, RHS
- 2644963446U, // <6,u,5,7>: Cost 3 vext2 RHS, <5,7,0,2>
- 1631606956U, // <6,u,5,u>: Cost 2 vext3 <3,4,5,6>, RHS
- 1504608358U, // <6,u,6,0>: Cost 2 vext1 <4,6,4,6>, LHS
- 2644963708U, // <6,u,6,1>: Cost 3 vext2 RHS, <6,1,2,3>
+ 1612290202U, // <6,u,5,6>: Cost 2 vext3 <0,2,4,6>, RHS
+ 1571221672U, // <6,u,5,7>: Cost 2 vext2 RHS, <5,7,5,7>
+ 1612290220U, // <6,u,5,u>: Cost 2 vext3 <0,2,4,6>, RHS
+ 1504903270U, // <6,u,6,0>: Cost 2 vext1 <4,6,u,6>, LHS
+ 2644963752U, // <6,u,6,1>: Cost 3 vext2 RHS, <6,1,7,2>
1571222010U, // <6,u,6,2>: Cost 2 vext2 RHS, <6,2,7,3>
- 2705569997U, // <6,u,6,3>: Cost 3 vext3 <3,4,u,6>, <u,6,3,4>
- 1662720216U, // <6,u,6,4>: Cost 2 vext3 <u,6,4,6>, <u,6,4,6>
- 2644964018U, // <6,u,6,5>: Cost 3 vext2 RHS, <6,5,0,7>
+ 2686032080U, // <6,u,6,3>: Cost 3 vext3 <0,2,4,6>, <u,6,3,7>
+ 1504906550U, // <6,u,6,4>: Cost 2 vext1 <4,6,u,6>, RHS
+ 2644964079U, // <6,u,6,5>: Cost 3 vext2 RHS, <6,5,7,5>
296144182U, // <6,u,6,6>: Cost 1 vdup2 RHS
1571222350U, // <6,u,6,7>: Cost 2 vext2 RHS, <6,7,0,1>
296144182U, // <6,u,6,u>: Cost 1 vdup2 RHS
- 1571222522U, // <6,u,7,0>: Cost 2 vext2 RHS, <7,0,1,2>
- 2900217142U, // <6,u,7,1>: Cost 3 vzipl <2,3,u,1>, RHS
+ 1492967526U, // <6,u,7,0>: Cost 2 vext1 <2,6,u,7>, LHS
+ 2560738574U, // <6,u,7,1>: Cost 3 vext1 <1,6,u,7>, <1,6,u,7>
1492969447U, // <6,u,7,2>: Cost 2 vext1 <2,6,u,7>, <2,6,u,7>
- 1813220662U, // <6,u,7,3>: Cost 2 vzipl LHS, RHS
- 1571222886U, // <6,u,7,4>: Cost 2 vext2 RHS, <7,4,5,6>
- 2900249910U, // <6,u,7,5>: Cost 3 vzipl <2,3,u,5>, RHS
+ 1906753692U, // <6,u,7,3>: Cost 2 vzipr RHS, LHS
+ 1492970806U, // <6,u,7,4>: Cost 2 vext1 <2,6,u,7>, RHS
+ 2980495761U, // <6,u,7,5>: Cost 3 vzipr RHS, <0,4,u,5>
1516860235U, // <6,u,7,6>: Cost 2 vext1 <6,6,u,7>, <6,6,u,7>
- 1571223148U, // <6,u,7,7>: Cost 2 vext2 RHS, <7,7,7,7>
- 1813261622U, // <6,u,7,u>: Cost 2 vzipl LHS, RHS
- 1571223250U, // <6,u,u,0>: Cost 2 vext2 RHS, <u,0,1,1>
+ 1906756936U, // <6,u,7,7>: Cost 2 vzipr RHS, RHS
+ 1492973358U, // <6,u,7,u>: Cost 2 vext1 <2,6,u,7>, LHS
+ 1492975718U, // <6,u,u,0>: Cost 2 vext1 <2,6,u,u>, LHS
497481518U, // <6,u,u,1>: Cost 1 vext2 RHS, LHS
- 1631607141U, // <6,u,u,2>: Cost 2 vext3 <3,4,5,6>, LHS
- 1813220663U, // <6,u,u,3>: Cost 2 vzipl LHS, RHS
- 1571223578U, // <6,u,u,4>: Cost 2 vext2 RHS, <u,4,1,5>
+ 1612290405U, // <6,u,u,2>: Cost 2 vext3 <0,2,4,6>, LHS
+ 1571223484U, // <6,u,u,3>: Cost 2 vext2 RHS, <u,3,0,1>
+ 1492978998U, // <6,u,u,4>: Cost 2 vext1 <2,6,u,u>, RHS
497481882U, // <6,u,u,5>: Cost 1 vext2 RHS, RHS
296144182U, // <6,u,u,6>: Cost 1 vdup2 RHS
- 1839795511U, // <6,u,u,7>: Cost 2 vzipl RHS, RHS
+ 1906765128U, // <6,u,u,7>: Cost 2 vzipr RHS, RHS
497482085U, // <6,u,u,u>: Cost 1 vext2 RHS, LHS
1638318080U, // <7,0,0,0>: Cost 2 vext3 RHS, <0,0,0,0>
1638318090U, // <7,0,0,1>: Cost 2 vext3 RHS, <0,0,1,1>
1638318100U, // <7,0,0,2>: Cost 2 vext3 RHS, <0,0,2,2>
- 3785801755U, // <7,0,0,3>: Cost 4 vext3 RHS, <0,0,3,0>
- 2712207402U, // <7,0,0,4>: Cost 3 vext3 RHS, <0,0,4,6>
- 2651603410U, // <7,0,0,5>: Cost 3 vext2 <5,6,7,0>, <0,5,6,7>
+ 3646442178U, // <7,0,0,3>: Cost 4 vext1 <3,7,0,0>, <3,7,0,0>
+ 2712059941U, // <7,0,0,4>: Cost 3 vext3 RHS, <0,0,4,1>
+ 2651603364U, // <7,0,0,5>: Cost 3 vext2 <5,6,7,0>, <0,5,1,6>
2590618445U, // <7,0,0,6>: Cost 3 vext1 <6,7,0,0>, <6,7,0,0>
- 3998634082U, // <7,0,0,7>: Cost 4 vzipl <6,5,0,7>, <5,6,7,0>
+ 3785801798U, // <7,0,0,7>: Cost 4 vext3 RHS, <0,0,7,7>
1638318153U, // <7,0,0,u>: Cost 2 vext3 RHS, <0,0,u,1>
1516879974U, // <7,0,1,0>: Cost 2 vext1 <6,7,0,1>, LHS
- 2712059996U, // <7,0,1,1>: Cost 3 vext3 RHS, <0,1,1,2>
+ 2693922911U, // <7,0,1,1>: Cost 3 vext3 <1,5,3,7>, <0,1,1,5>
564576358U, // <7,0,1,2>: Cost 1 vext3 RHS, LHS
- 2590623894U, // <7,0,1,3>: Cost 3 vext1 <6,7,0,1>, <3,0,1,2>
+ 2638996480U, // <7,0,1,3>: Cost 3 vext2 <3,5,7,0>, <1,3,5,7>
1516883254U, // <7,0,1,4>: Cost 2 vext1 <6,7,0,1>, RHS
- 2651604112U, // <7,0,1,5>: Cost 3 vext2 <5,6,7,0>, <1,5,3,7>
+ 2649613456U, // <7,0,1,5>: Cost 3 vext2 <5,3,7,0>, <1,5,3,7>
1516884814U, // <7,0,1,6>: Cost 2 vext1 <6,7,0,1>, <6,7,0,1>
2590626808U, // <7,0,1,7>: Cost 3 vext1 <6,7,0,1>, <7,0,1,0>
564576412U, // <7,0,1,u>: Cost 1 vext3 RHS, LHS
1638318244U, // <7,0,2,0>: Cost 2 vext3 RHS, <0,2,0,2>
- 2712060078U, // <7,0,2,1>: Cost 3 vext3 RHS, <0,2,1,3>
- 2712060087U, // <7,0,2,2>: Cost 3 vext3 RHS, <0,2,2,3>
- 2712060098U, // <7,0,2,3>: Cost 3 vext3 RHS, <0,2,3,5>
- 1638465740U, // <7,0,2,4>: Cost 2 vext3 RHS, <0,2,4,6>
- 2584661712U, // <7,0,2,5>: Cost 3 vext1 <5,7,0,2>, <5,1,7,3>
+ 2692743344U, // <7,0,2,1>: Cost 3 vext3 <1,3,5,7>, <0,2,1,5>
+ 2712060084U, // <7,0,2,2>: Cost 3 vext3 RHS, <0,2,2,0>
+ 2712060094U, // <7,0,2,3>: Cost 3 vext3 RHS, <0,2,3,1>
+ 1638318284U, // <7,0,2,4>: Cost 2 vext3 RHS, <0,2,4,6>
+ 2712060118U, // <7,0,2,5>: Cost 3 vext3 RHS, <0,2,5,7>
2651604922U, // <7,0,2,6>: Cost 3 vext2 <5,6,7,0>, <2,6,3,7>
- 2735948002U, // <7,0,2,7>: Cost 3 vext3 RHS, <0,2,7,1>
- 1662206188U, // <7,0,2,u>: Cost 2 vext3 RHS, <0,2,u,2>
+ 2686255336U, // <7,0,2,7>: Cost 3 vext3 <0,2,7,7>, <0,2,7,7>
+ 1638318316U, // <7,0,2,u>: Cost 2 vext3 RHS, <0,2,u,2>
2651605142U, // <7,0,3,0>: Cost 3 vext2 <5,6,7,0>, <3,0,1,2>
- 3973369552U, // <7,0,3,1>: Cost 4 vzipl <2,3,0,1>, <5,1,7,3>
+ 2712060156U, // <7,0,3,1>: Cost 3 vext3 RHS, <0,3,1,0>
2712060165U, // <7,0,3,2>: Cost 3 vext3 RHS, <0,3,2,0>
2651605404U, // <7,0,3,3>: Cost 3 vext2 <5,6,7,0>, <3,3,3,3>
2651605506U, // <7,0,3,4>: Cost 3 vext2 <5,6,7,0>, <3,4,5,6>
- 2651605597U, // <7,0,3,5>: Cost 3 vext2 <5,6,7,0>, <3,5,6,7>
+ 2638998111U, // <7,0,3,5>: Cost 3 vext2 <3,5,7,0>, <3,5,7,0>
2639661744U, // <7,0,3,6>: Cost 3 vext2 <3,6,7,0>, <3,6,7,0>
- 3729328834U, // <7,0,3,7>: Cost 4 vext2 <6,3,7,0>, <3,7,0,0>
- 2712060219U, // <7,0,3,u>: Cost 3 vext3 RHS, <0,3,u,0>
- 2651605906U, // <7,0,4,0>: Cost 3 vext2 <5,6,7,0>, <4,0,5,1>
- 1638465874U, // <7,0,4,1>: Cost 2 vext3 RHS, <0,4,1,5>
- 1638465884U, // <7,0,4,2>: Cost 2 vext3 RHS, <0,4,2,6>
- 3725347975U, // <7,0,4,3>: Cost 4 vext2 <5,6,7,0>, <4,3,5,3>
- 2712207726U, // <7,0,4,4>: Cost 3 vext3 RHS, <0,4,4,6>
+ 3712740068U, // <7,0,3,7>: Cost 4 vext2 <3,5,7,0>, <3,7,3,7>
+ 2640989010U, // <7,0,3,u>: Cost 3 vext2 <3,u,7,0>, <3,u,7,0>
+ 2712060232U, // <7,0,4,0>: Cost 3 vext3 RHS, <0,4,0,4>
+ 1638318418U, // <7,0,4,1>: Cost 2 vext3 RHS, <0,4,1,5>
+ 1638318428U, // <7,0,4,2>: Cost 2 vext3 RHS, <0,4,2,6>
+ 3646474950U, // <7,0,4,3>: Cost 4 vext1 <3,7,0,4>, <3,7,0,4>
+ 2712060270U, // <7,0,4,4>: Cost 3 vext3 RHS, <0,4,4,6>
1577864502U, // <7,0,4,5>: Cost 2 vext2 <5,6,7,0>, RHS
- 2651606348U, // <7,0,4,6>: Cost 3 vext2 <5,6,7,0>, <4,6,0,2>
- 3725348305U, // <7,0,4,7>: Cost 4 vext2 <5,6,7,0>, <4,7,6,0>
- 1638465937U, // <7,0,4,u>: Cost 2 vext3 RHS, <0,4,u,5>
- 2712207772U, // <7,0,5,0>: Cost 3 vext3 RHS, <0,5,0,7>
- 2712060318U, // <7,0,5,1>: Cost 3 vext3 RHS, <0,5,1,0>
- 2712207790U, // <7,0,5,2>: Cost 3 vext3 RHS, <0,5,2,7>
+ 2651606388U, // <7,0,4,6>: Cost 3 vext2 <5,6,7,0>, <4,6,4,6>
+ 3787792776U, // <7,0,4,7>: Cost 4 vext3 RHS, <0,4,7,5>
+ 1638318481U, // <7,0,4,u>: Cost 2 vext3 RHS, <0,4,u,5>
+ 2590654566U, // <7,0,5,0>: Cost 3 vext1 <6,7,0,5>, LHS
+ 2651606736U, // <7,0,5,1>: Cost 3 vext2 <5,6,7,0>, <5,1,7,3>
+ 2712060334U, // <7,0,5,2>: Cost 3 vext3 RHS, <0,5,2,7>
2649616239U, // <7,0,5,3>: Cost 3 vext2 <5,3,7,0>, <5,3,7,0>
- 2651606972U, // <7,0,5,4>: Cost 3 vext2 <5,6,7,0>, <5,4,6,5>
+ 2651606982U, // <7,0,5,4>: Cost 3 vext2 <5,6,7,0>, <5,4,7,6>
2651607044U, // <7,0,5,5>: Cost 3 vext2 <5,6,7,0>, <5,5,5,5>
1577865314U, // <7,0,5,6>: Cost 2 vext2 <5,6,7,0>, <5,6,7,0>
- 2652270771U, // <7,0,5,7>: Cost 3 vext2 <5,7,7,0>, <5,7,7,0>
+ 2651607208U, // <7,0,5,7>: Cost 3 vext2 <5,6,7,0>, <5,7,5,7>
1579192580U, // <7,0,5,u>: Cost 2 vext2 <5,u,7,0>, <5,u,7,0>
- 2712207853U, // <7,0,6,0>: Cost 3 vext3 RHS, <0,6,0,7>
- 2712207862U, // <7,0,6,1>: Cost 3 vext3 RHS, <0,6,1,7>
- 2712060408U, // <7,0,6,2>: Cost 3 vext3 RHS, <0,6,2,0>
+ 2688393709U, // <7,0,6,0>: Cost 3 vext3 <0,6,0,7>, <0,6,0,7>
+ 2712060406U, // <7,0,6,1>: Cost 3 vext3 RHS, <0,6,1,7>
+ 2688541183U, // <7,0,6,2>: Cost 3 vext3 <0,6,2,7>, <0,6,2,7>
2655588936U, // <7,0,6,3>: Cost 3 vext2 <6,3,7,0>, <6,3,7,0>
- 3785802250U, // <7,0,6,4>: Cost 4 vext3 RHS, <0,6,4,0>
+ 3762430481U, // <7,0,6,4>: Cost 4 vext3 <0,6,4,7>, <0,6,4,7>
2651607730U, // <7,0,6,5>: Cost 3 vext2 <5,6,7,0>, <6,5,0,7>
2651607864U, // <7,0,6,6>: Cost 3 vext2 <5,6,7,0>, <6,6,6,6>
2651607886U, // <7,0,6,7>: Cost 3 vext2 <5,6,7,0>, <6,7,0,1>
- 2712060462U, // <7,0,6,u>: Cost 3 vext3 RHS, <0,6,u,0>
+ 2688983605U, // <7,0,6,u>: Cost 3 vext3 <0,6,u,7>, <0,6,u,7>
2651608058U, // <7,0,7,0>: Cost 3 vext2 <5,6,7,0>, <7,0,1,2>
- 2735948359U, // <7,0,7,1>: Cost 3 vext3 RHS, <0,7,1,7>
- 2735948362U, // <7,0,7,2>: Cost 3 vext3 RHS, <0,7,2,1>
- 3725350115U, // <7,0,7,3>: Cost 4 vext2 <5,6,7,0>, <7,3,0,1>
+ 2932703334U, // <7,0,7,1>: Cost 3 vzipl <7,7,7,7>, LHS
+ 3066921062U, // <7,0,7,2>: Cost 3 vtrnl <7,7,7,7>, LHS
+ 3712742678U, // <7,0,7,3>: Cost 4 vext2 <3,5,7,0>, <7,3,5,7>
2651608422U, // <7,0,7,4>: Cost 3 vext2 <5,6,7,0>, <7,4,5,6>
2651608513U, // <7,0,7,5>: Cost 3 vext2 <5,6,7,0>, <7,5,6,7>
2663552532U, // <7,0,7,6>: Cost 3 vext2 <7,6,7,0>, <7,6,7,0>
2651608684U, // <7,0,7,7>: Cost 3 vext2 <5,6,7,0>, <7,7,7,7>
2651608706U, // <7,0,7,u>: Cost 3 vext2 <5,6,7,0>, <7,u,1,2>
1638318730U, // <7,0,u,0>: Cost 2 vext3 RHS, <0,u,0,2>
- 1577867054U, // <7,0,u,1>: Cost 2 vext2 <5,6,7,0>, LHS
+ 1638318738U, // <7,0,u,1>: Cost 2 vext3 RHS, <0,u,1,1>
564576925U, // <7,0,u,2>: Cost 1 vext3 RHS, LHS
- 2712060584U, // <7,0,u,3>: Cost 3 vext3 RHS, <0,u,3,5>
- 1638466226U, // <7,0,u,4>: Cost 2 vext3 RHS, <0,u,4,6>
+ 2572765898U, // <7,0,u,3>: Cost 3 vext1 <3,7,0,u>, <3,7,0,u>
+ 1638318770U, // <7,0,u,4>: Cost 2 vext3 RHS, <0,u,4,6>
1577867418U, // <7,0,u,5>: Cost 2 vext2 <5,6,7,0>, RHS
1516942165U, // <7,0,u,6>: Cost 2 vext1 <6,7,0,u>, <6,7,0,u>
2651609344U, // <7,0,u,7>: Cost 3 vext2 <5,6,7,0>, <u,7,0,1>
564576979U, // <7,0,u,u>: Cost 1 vext3 RHS, LHS
- 2712060634U, // <7,1,0,0>: Cost 3 vext3 RHS, <1,0,0,1>
- 2712060643U, // <7,1,0,1>: Cost 3 vext3 RHS, <1,0,1,1>
- 2712060652U, // <7,1,0,2>: Cost 3 vext3 RHS, <1,0,2,1>
+ 2590687334U, // <7,1,0,0>: Cost 3 vext1 <6,7,1,0>, LHS
+ 2639003750U, // <7,1,0,1>: Cost 3 vext2 <3,5,7,1>, LHS
+ 2793357414U, // <7,1,0,2>: Cost 3 vuzpl <7,0,1,2>, LHS
1638318838U, // <7,1,0,3>: Cost 2 vext3 RHS, <1,0,3,2>
2590690614U, // <7,1,0,4>: Cost 3 vext1 <6,7,1,0>, RHS
- 3785802503U, // <7,1,0,5>: Cost 4 vext3 RHS, <1,0,5,1>
+ 2712060679U, // <7,1,0,5>: Cost 3 vext3 RHS, <1,0,5,1>
2590692182U, // <7,1,0,6>: Cost 3 vext1 <6,7,1,0>, <6,7,1,0>
- 3721372224U, // <7,1,0,7>: Cost 4 vext2 <5,0,7,1>, <0,7,1,0>
+ 3785802521U, // <7,1,0,7>: Cost 4 vext3 RHS, <1,0,7,1>
1638318883U, // <7,1,0,u>: Cost 2 vext3 RHS, <1,0,u,2>
2712060715U, // <7,1,1,0>: Cost 3 vext3 RHS, <1,1,0,1>
1638318900U, // <7,1,1,1>: Cost 2 vext3 RHS, <1,1,1,1>
- 3785802557U, // <7,1,1,2>: Cost 4 vext3 RHS, <1,1,2,1>
+ 3774300994U, // <7,1,1,2>: Cost 4 vext3 <2,6,3,7>, <1,1,2,6>
1638318920U, // <7,1,1,3>: Cost 2 vext3 RHS, <1,1,3,3>
2712060755U, // <7,1,1,4>: Cost 3 vext3 RHS, <1,1,4,5>
- 2649621648U, // <7,1,1,5>: Cost 3 vext2 <5,3,7,1>, <1,5,3,7>
+ 2691416926U, // <7,1,1,5>: Cost 3 vext3 <1,1,5,7>, <1,1,5,7>
2590700375U, // <7,1,1,6>: Cost 3 vext1 <6,7,1,1>, <6,7,1,1>
- 3785802608U, // <7,1,1,7>: Cost 4 vext3 RHS, <1,1,7,7>
+ 3765158766U, // <7,1,1,7>: Cost 4 vext3 <1,1,5,7>, <1,1,7,5>
1638318965U, // <7,1,1,u>: Cost 2 vext3 RHS, <1,1,u,3>
2712060796U, // <7,1,2,0>: Cost 3 vext3 RHS, <1,2,0,1>
2712060807U, // <7,1,2,1>: Cost 3 vext3 RHS, <1,2,1,3>
- 2712060816U, // <7,1,2,2>: Cost 3 vext3 RHS, <1,2,2,3>
+ 3712747112U, // <7,1,2,2>: Cost 4 vext2 <3,5,7,1>, <2,2,2,2>
1638318998U, // <7,1,2,3>: Cost 2 vext3 RHS, <1,2,3,0>
2712060836U, // <7,1,2,4>: Cost 3 vext3 RHS, <1,2,4,5>
- 2735948715U, // <7,1,2,5>: Cost 3 vext3 RHS, <1,2,5,3>
+ 2712060843U, // <7,1,2,5>: Cost 3 vext3 RHS, <1,2,5,3>
2590708568U, // <7,1,2,6>: Cost 3 vext1 <6,7,1,2>, <6,7,1,2>
2735948730U, // <7,1,2,7>: Cost 3 vext3 RHS, <1,2,7,0>
1638319043U, // <7,1,2,u>: Cost 2 vext3 RHS, <1,2,u,0>
- 2712060878U, // <7,1,3,0>: Cost 3 vext3 RHS, <1,3,0,2>
- 2712060888U, // <7,1,3,1>: Cost 3 vext3 RHS, <1,3,1,3>
- 3977432784U, // <7,1,3,2>: Cost 4 vzipl <3,0,1,2>, <5,1,7,3>
- 2712060903U, // <7,1,3,3>: Cost 3 vext3 RHS, <1,3,3,0>
- 2712208374U, // <7,1,3,4>: Cost 3 vext3 RHS, <1,3,4,6>
- 3992055504U, // <7,1,3,5>: Cost 4 vzipl <5,4,1,5>, <5,1,7,3>
- 3664458585U, // <7,1,3,6>: Cost 4 vext1 <6,7,1,3>, <6,7,1,3>
- 3980791504U, // <7,1,3,7>: Cost 4 vzipl <3,5,1,7>, <5,1,7,3>
- 2712060948U, // <7,1,3,u>: Cost 3 vext3 RHS, <1,3,u,0>
+ 2712060876U, // <7,1,3,0>: Cost 3 vext3 RHS, <1,3,0,0>
+ 1638319064U, // <7,1,3,1>: Cost 2 vext3 RHS, <1,3,1,3>
+ 2712060894U, // <7,1,3,2>: Cost 3 vext3 RHS, <1,3,2,0>
+ 2692596718U, // <7,1,3,3>: Cost 3 vext3 <1,3,3,7>, <1,3,3,7>
+ 2712060917U, // <7,1,3,4>: Cost 3 vext3 RHS, <1,3,4,5>
+ 1619002368U, // <7,1,3,5>: Cost 2 vext3 <1,3,5,7>, <1,3,5,7>
+ 2692817929U, // <7,1,3,6>: Cost 3 vext3 <1,3,6,7>, <1,3,6,7>
+ 2735948814U, // <7,1,3,7>: Cost 3 vext3 RHS, <1,3,7,3>
+ 1619223579U, // <7,1,3,u>: Cost 2 vext3 <1,3,u,7>, <1,3,u,7>
2712060962U, // <7,1,4,0>: Cost 3 vext3 RHS, <1,4,0,5>
- 3785802791U, // <7,1,4,1>: Cost 4 vext3 RHS, <1,4,1,1>
- 2712208436U, // <7,1,4,2>: Cost 3 vext3 RHS, <1,4,2,5>
- 2712060990U, // <7,1,4,3>: Cost 3 vext3 RHS, <1,4,3,6>
+ 2712060971U, // <7,1,4,1>: Cost 3 vext3 RHS, <1,4,1,5>
+ 2712060980U, // <7,1,4,2>: Cost 3 vext3 RHS, <1,4,2,5>
+ 2712060989U, // <7,1,4,3>: Cost 3 vext3 RHS, <1,4,3,5>
3785802822U, // <7,1,4,4>: Cost 4 vext3 RHS, <1,4,4,5>
- 2712061008U, // <7,1,4,5>: Cost 3 vext3 RHS, <1,4,5,6>
- 2846282746U, // <7,1,4,6>: Cost 3 vuzpr RHS, <7,0,1,2>
- 3670439475U, // <7,1,4,7>: Cost 4 vext1 <7,7,1,4>, <7,7,1,4>
- 2712061035U, // <7,1,4,u>: Cost 3 vext3 RHS, <1,4,u,6>
- 2647633533U, // <7,1,5,0>: Cost 3 vext2 <5,0,7,1>, <5,0,7,1>
- 2648297166U, // <7,1,5,1>: Cost 3 vext2 <5,1,7,1>, <5,1,7,1>
- 3785802880U, // <7,1,5,2>: Cost 4 vext3 RHS, <1,5,2,0>
- 1638466704U, // <7,1,5,3>: Cost 2 vext3 RHS, <1,5,3,7>
- 2590731574U, // <7,1,5,4>: Cost 3 vext1 <6,7,1,5>, RHS
- 3785802912U, // <7,1,5,5>: Cost 4 vext3 RHS, <1,5,5,5>
+ 2639007030U, // <7,1,4,5>: Cost 3 vext2 <3,5,7,1>, RHS
+ 2645642634U, // <7,1,4,6>: Cost 3 vext2 <4,6,7,1>, <4,6,7,1>
+ 3719384520U, // <7,1,4,7>: Cost 4 vext2 <4,6,7,1>, <4,7,5,0>
+ 2639007273U, // <7,1,4,u>: Cost 3 vext2 <3,5,7,1>, RHS
+ 2572812390U, // <7,1,5,0>: Cost 3 vext1 <3,7,1,5>, LHS
+ 2693776510U, // <7,1,5,1>: Cost 3 vext3 <1,5,1,7>, <1,5,1,7>
+ 3774301318U, // <7,1,5,2>: Cost 4 vext3 <2,6,3,7>, <1,5,2,6>
+ 1620182160U, // <7,1,5,3>: Cost 2 vext3 <1,5,3,7>, <1,5,3,7>
+ 2572815670U, // <7,1,5,4>: Cost 3 vext1 <3,7,1,5>, RHS
+ 3766486178U, // <7,1,5,5>: Cost 4 vext3 <1,3,5,7>, <1,5,5,7>
2651615331U, // <7,1,5,6>: Cost 3 vext2 <5,6,7,1>, <5,6,7,1>
- 3923383290U, // <7,1,5,7>: Cost 4 vuzpr <5,1,7,3>, <7,0,1,2>
- 1638466749U, // <7,1,5,u>: Cost 2 vext3 RHS, <1,5,u,7>
- 2653606230U, // <7,1,6,0>: Cost 3 vext2 <6,0,7,1>, <6,0,7,1>
- 2712208591U, // <7,1,6,1>: Cost 3 vext3 RHS, <1,6,1,7>
- 3768255704U, // <7,1,6,2>: Cost 4 vext3 <1,6,2,7>, <1,6,2,7>
- 2714051804U, // <7,1,6,3>: Cost 3 vext3 RHS, <1,6,3,2>
- 3658509202U, // <7,1,6,4>: Cost 4 vext1 <5,7,1,6>, <4,0,5,1>
- 2712208628U, // <7,1,6,5>: Cost 3 vext3 RHS, <1,6,5,u>
- 3785803003U, // <7,1,6,6>: Cost 4 vext3 RHS, <1,6,6,6>
- 2735949054U, // <7,1,6,7>: Cost 3 vext3 RHS, <1,6,7,0>
- 2714051849U, // <7,1,6,u>: Cost 3 vext3 RHS, <1,6,u,2>
- 2660242426U, // <7,1,7,0>: Cost 3 vext2 <7,1,7,1>, <7,0,1,2>
- 2860471290U, // <7,1,7,1>: Cost 3 vuzpr <7,0,1,2>, <7,0,1,2>
- 3723367596U, // <7,1,7,2>: Cost 4 vext2 <5,3,7,1>, <7,2,3,0>
- 3068515948U, // <7,1,7,3>: Cost 3 vtrnl LHS, <7,7,7,7>
- 2602691894U, // <7,1,7,4>: Cost 3 vext1 <u,7,1,7>, RHS
- 3779462462U, // <7,1,7,5>: Cost 4 vext3 <3,5,1,7>, <1,7,5,1>
- 3727349212U, // <7,1,7,6>: Cost 4 vext2 <6,0,7,1>, <7,6,0,7>
- 2602694252U, // <7,1,7,7>: Cost 3 vext1 <u,7,1,7>, <7,7,7,7>
- 3068556908U, // <7,1,7,u>: Cost 3 vtrnl LHS, <7,7,7,7>
- 2712061282U, // <7,1,u,0>: Cost 3 vext3 RHS, <1,u,0,1>
- 1638318900U, // <7,1,u,1>: Cost 2 vext3 RHS, <1,1,1,1>
- 2712061302U, // <7,1,u,2>: Cost 3 vext3 RHS, <1,u,2,3>
- 1638319484U, // <7,1,u,3>: Cost 2 vext3 RHS, <1,u,3,0>
- 2712061322U, // <7,1,u,4>: Cost 3 vext3 RHS, <1,u,4,5>
- 2712061332U, // <7,1,u,5>: Cost 3 vext3 RHS, <1,u,5,6>
- 2590757726U, // <7,1,u,6>: Cost 3 vext1 <6,7,1,u>, <6,7,1,u>
- 2735949216U, // <7,1,u,7>: Cost 3 vext3 RHS, <1,u,7,0>
- 1638319529U, // <7,1,u,u>: Cost 2 vext3 RHS, <1,u,u,0>
+ 2652278964U, // <7,1,5,7>: Cost 3 vext2 <5,7,7,1>, <5,7,7,1>
+ 1620550845U, // <7,1,5,u>: Cost 2 vext3 <1,5,u,7>, <1,5,u,7>
+ 3768108230U, // <7,1,6,0>: Cost 4 vext3 <1,6,0,7>, <1,6,0,7>
+ 2694440143U, // <7,1,6,1>: Cost 3 vext3 <1,6,1,7>, <1,6,1,7>
+ 2712061144U, // <7,1,6,2>: Cost 3 vext3 RHS, <1,6,2,7>
+ 2694587617U, // <7,1,6,3>: Cost 3 vext3 <1,6,3,7>, <1,6,3,7>
+ 3768403178U, // <7,1,6,4>: Cost 4 vext3 <1,6,4,7>, <1,6,4,7>
+ 2694735091U, // <7,1,6,5>: Cost 3 vext3 <1,6,5,7>, <1,6,5,7>
+ 3768550652U, // <7,1,6,6>: Cost 4 vext3 <1,6,6,7>, <1,6,6,7>
+ 2652279630U, // <7,1,6,7>: Cost 3 vext2 <5,7,7,1>, <6,7,0,1>
+ 2694956302U, // <7,1,6,u>: Cost 3 vext3 <1,6,u,7>, <1,6,u,7>
+ 2645644282U, // <7,1,7,0>: Cost 3 vext2 <4,6,7,1>, <7,0,1,2>
+ 2859062094U, // <7,1,7,1>: Cost 3 vuzpr <6,7,0,1>, <6,7,0,1>
+ 3779462437U, // <7,1,7,2>: Cost 4 vext3 <3,5,1,7>, <1,7,2,3>
+ 3121938534U, // <7,1,7,3>: Cost 3 vtrnr <5,7,5,7>, LHS
+ 2554916150U, // <7,1,7,4>: Cost 3 vext1 <0,7,1,7>, RHS
+ 3769140548U, // <7,1,7,5>: Cost 4 vext3 <1,7,5,7>, <1,7,5,7>
+ 3726022164U, // <7,1,7,6>: Cost 4 vext2 <5,7,7,1>, <7,6,7,0>
+ 2554918508U, // <7,1,7,7>: Cost 3 vext1 <0,7,1,7>, <7,7,7,7>
+ 3121938539U, // <7,1,7,u>: Cost 3 vtrnr <5,7,5,7>, LHS
+ 2572836966U, // <7,1,u,0>: Cost 3 vext1 <3,7,1,u>, LHS
+ 1638319469U, // <7,1,u,1>: Cost 2 vext3 RHS, <1,u,1,3>
+ 2712061299U, // <7,1,u,2>: Cost 3 vext3 RHS, <1,u,2,0>
+ 1622173059U, // <7,1,u,3>: Cost 2 vext3 <1,u,3,7>, <1,u,3,7>
+ 2572840246U, // <7,1,u,4>: Cost 3 vext1 <3,7,1,u>, RHS
+ 1622320533U, // <7,1,u,5>: Cost 2 vext3 <1,u,5,7>, <1,u,5,7>
+ 2696136094U, // <7,1,u,6>: Cost 3 vext3 <1,u,6,7>, <1,u,6,7>
+ 2859060777U, // <7,1,u,7>: Cost 3 vuzpr <6,7,0,1>, RHS
+ 1622541744U, // <7,1,u,u>: Cost 2 vext3 <1,u,u,7>, <1,u,u,7>
2712061364U, // <7,2,0,0>: Cost 3 vext3 RHS, <2,0,0,2>
2712061373U, // <7,2,0,1>: Cost 3 vext3 RHS, <2,0,1,2>
2712061380U, // <7,2,0,2>: Cost 3 vext3 RHS, <2,0,2,0>
- 2712061390U, // <7,2,0,3>: Cost 3 vext3 RHS, <2,0,3,1>
- 2712061400U, // <7,2,0,4>: Cost 3 vext3 RHS, <2,0,4,2>
- 3785803231U, // <7,2,0,5>: Cost 4 vext3 RHS, <2,0,5,0>
- 2700559849U, // <7,2,0,6>: Cost 3 vext3 <2,6,3,7>, <2,0,6,1>
- 3787793907U, // <7,2,0,7>: Cost 4 vext3 RHS, <2,0,7,2>
- 2712061434U, // <7,2,0,u>: Cost 3 vext3 RHS, <2,0,u,0>
+ 2712061389U, // <7,2,0,3>: Cost 3 vext3 RHS, <2,0,3,0>
+ 2712061404U, // <7,2,0,4>: Cost 3 vext3 RHS, <2,0,4,6>
+ 2696725990U, // <7,2,0,5>: Cost 3 vext3 <2,0,5,7>, <2,0,5,7>
+ 2712061417U, // <7,2,0,6>: Cost 3 vext3 RHS, <2,0,6,1>
+ 3785803251U, // <7,2,0,7>: Cost 4 vext3 RHS, <2,0,7,2>
+ 2696947201U, // <7,2,0,u>: Cost 3 vext3 <2,0,u,7>, <2,0,u,7>
2712061446U, // <7,2,1,0>: Cost 3 vext3 RHS, <2,1,0,3>
3785803276U, // <7,2,1,1>: Cost 4 vext3 RHS, <2,1,1,0>
- 2712061464U, // <7,2,1,2>: Cost 3 vext3 RHS, <2,1,2,3>
+ 3785803285U, // <7,2,1,2>: Cost 4 vext3 RHS, <2,1,2,0>
2712061471U, // <7,2,1,3>: Cost 3 vext3 RHS, <2,1,3,1>
2712061482U, // <7,2,1,4>: Cost 3 vext3 RHS, <2,1,4,3>
- 3785803315U, // <7,2,1,5>: Cost 4 vext3 RHS, <2,1,5,3>
- 2735949372U, // <7,2,1,6>: Cost 3 vext3 RHS, <2,1,6,3>
+ 3766486576U, // <7,2,1,5>: Cost 4 vext3 <1,3,5,7>, <2,1,5,0>
+ 2712061500U, // <7,2,1,6>: Cost 3 vext3 RHS, <2,1,6,3>
2602718850U, // <7,2,1,7>: Cost 3 vext1 <u,7,2,1>, <7,u,1,2>
- 2712061518U, // <7,2,1,u>: Cost 3 vext3 RHS, <2,1,u,3>
- 2712061524U, // <7,2,2,0>: Cost 3 vext3 RHS, <2,2,0,0>
- 3785803357U, // <7,2,2,1>: Cost 4 vext3 RHS, <2,2,1,0>
+ 2712061516U, // <7,2,1,u>: Cost 3 vext3 RHS, <2,1,u,1>
+ 2712061525U, // <7,2,2,0>: Cost 3 vext3 RHS, <2,2,0,1>
+ 2712061536U, // <7,2,2,1>: Cost 3 vext3 RHS, <2,2,1,3>
1638319720U, // <7,2,2,2>: Cost 2 vext3 RHS, <2,2,2,2>
1638319730U, // <7,2,2,3>: Cost 2 vext3 RHS, <2,2,3,3>
- 2712061564U, // <7,2,2,4>: Cost 3 vext3 RHS, <2,2,4,4>
- 3785803394U, // <7,2,2,5>: Cost 4 vext3 RHS, <2,2,5,1>
- 2590782305U, // <7,2,2,6>: Cost 3 vext1 <6,7,2,2>, <6,7,2,2>
- 3780200086U, // <7,2,2,7>: Cost 4 vext3 <3,6,2,7>, <2,2,7,3>
+ 2712061565U, // <7,2,2,4>: Cost 3 vext3 RHS, <2,2,4,5>
+ 2698053256U, // <7,2,2,5>: Cost 3 vext3 <2,2,5,7>, <2,2,5,7>
+ 2712061584U, // <7,2,2,6>: Cost 3 vext3 RHS, <2,2,6,6>
+ 3771795096U, // <7,2,2,7>: Cost 4 vext3 <2,2,5,7>, <2,2,7,5>
1638319775U, // <7,2,2,u>: Cost 2 vext3 RHS, <2,2,u,3>
1638319782U, // <7,2,3,0>: Cost 2 vext3 RHS, <2,3,0,1>
- 2712061614U, // <7,2,3,1>: Cost 3 vext3 RHS, <2,3,1,0>
- 2712061625U, // <7,2,3,2>: Cost 3 vext3 RHS, <2,3,2,2>
- 2886521338U, // <7,2,3,3>: Cost 3 vzipl LHS, <6,2,7,3>
+ 2693924531U, // <7,2,3,1>: Cost 3 vext3 <1,5,3,7>, <2,3,1,5>
+ 2700560061U, // <7,2,3,2>: Cost 3 vext3 <2,6,3,7>, <2,3,2,6>
+ 2693924551U, // <7,2,3,3>: Cost 3 vext3 <1,5,3,7>, <2,3,3,7>
1638319822U, // <7,2,3,4>: Cost 2 vext3 RHS, <2,3,4,5>
- 2712061651U, // <7,2,3,5>: Cost 3 vext3 RHS, <2,3,5,1>
- 2712061661U, // <7,2,3,6>: Cost 3 vext3 RHS, <2,3,6,2>
+ 2698716889U, // <7,2,3,5>: Cost 3 vext3 <2,3,5,7>, <2,3,5,7>
+ 2712061665U, // <7,2,3,6>: Cost 3 vext3 RHS, <2,3,6,6>
2735949540U, // <7,2,3,7>: Cost 3 vext3 RHS, <2,3,7,0>
1638319854U, // <7,2,3,u>: Cost 2 vext3 RHS, <2,3,u,1>
- 2712061688U, // <7,2,4,0>: Cost 3 vext3 RHS, <2,4,0,2>
- 3785803520U, // <7,2,4,1>: Cost 4 vext3 RHS, <2,4,1,1>
+ 2712061692U, // <7,2,4,0>: Cost 3 vext3 RHS, <2,4,0,6>
+ 2712061698U, // <7,2,4,1>: Cost 3 vext3 RHS, <2,4,1,3>
2712061708U, // <7,2,4,2>: Cost 3 vext3 RHS, <2,4,2,4>
2712061718U, // <7,2,4,3>: Cost 3 vext3 RHS, <2,4,3,5>
- 2712209184U, // <7,2,4,4>: Cost 3 vext3 RHS, <2,4,4,6>
- 2712061737U, // <7,2,4,5>: Cost 3 vext3 RHS, <2,4,5,6>
- 2712209201U, // <7,2,4,6>: Cost 3 vext3 RHS, <2,4,6,5>
+ 2712061728U, // <7,2,4,4>: Cost 3 vext3 RHS, <2,4,4,6>
+ 2699380522U, // <7,2,4,5>: Cost 3 vext3 <2,4,5,7>, <2,4,5,7>
+ 2712061740U, // <7,2,4,6>: Cost 3 vext3 RHS, <2,4,6,0>
3809691445U, // <7,2,4,7>: Cost 4 vext3 RHS, <2,4,7,0>
- 2712061764U, // <7,2,4,u>: Cost 3 vext3 RHS, <2,4,u,6>
- 2712209230U, // <7,2,5,0>: Cost 3 vext3 RHS, <2,5,0,7>
- 2647641808U, // <7,2,5,1>: Cost 3 vext2 <5,0,7,2>, <5,1,7,3>
- 2712209248U, // <7,2,5,2>: Cost 3 vext3 RHS, <2,5,2,7>
- 2712061795U, // <7,2,5,3>: Cost 3 vext3 RHS, <2,5,3,1>
- 2712209266U, // <7,2,5,4>: Cost 3 vext3 RHS, <2,5,4,7>
- 3785951099U, // <7,2,5,5>: Cost 4 vext3 RHS, <2,5,5,7>
- 2712209284U, // <7,2,5,6>: Cost 3 vext3 RHS, <2,5,6,7>
- 3721384054U, // <7,2,5,7>: Cost 4 vext2 <5,0,7,2>, <5,7,0,2>
- 2712061840U, // <7,2,5,u>: Cost 3 vext3 RHS, <2,5,u,1>
- 2653614423U, // <7,2,6,0>: Cost 3 vext2 <6,0,7,2>, <6,0,7,2>
- 2654278056U, // <7,2,6,1>: Cost 3 vext2 <6,1,7,2>, <6,1,7,2>
- 2653614586U, // <7,2,6,2>: Cost 3 vext2 <6,0,7,2>, <6,2,7,3>
- 1638467514U, // <7,2,6,3>: Cost 2 vext3 RHS, <2,6,3,7>
- 2590813494U, // <7,2,6,4>: Cost 3 vext1 <6,7,2,6>, RHS
- 3787794375U, // <7,2,6,5>: Cost 4 vext3 RHS, <2,6,5,2>
- 2712209366U, // <7,2,6,6>: Cost 3 vext3 RHS, <2,6,6,u>
- 3785803735U, // <7,2,6,7>: Cost 4 vext3 RHS, <2,6,7,0>
- 1638467559U, // <7,2,6,u>: Cost 2 vext3 RHS, <2,6,u,7>
+ 2699601733U, // <7,2,4,u>: Cost 3 vext3 <2,4,u,7>, <2,4,u,7>
+ 2699675470U, // <7,2,5,0>: Cost 3 vext3 <2,5,0,7>, <2,5,0,7>
+ 3766486867U, // <7,2,5,1>: Cost 4 vext3 <1,3,5,7>, <2,5,1,3>
+ 2699822944U, // <7,2,5,2>: Cost 3 vext3 <2,5,2,7>, <2,5,2,7>
+ 2692745065U, // <7,2,5,3>: Cost 3 vext3 <1,3,5,7>, <2,5,3,7>
+ 2699970418U, // <7,2,5,4>: Cost 3 vext3 <2,5,4,7>, <2,5,4,7>
+ 3766486907U, // <7,2,5,5>: Cost 4 vext3 <1,3,5,7>, <2,5,5,7>
+ 2700117892U, // <7,2,5,6>: Cost 3 vext3 <2,5,6,7>, <2,5,6,7>
+ 3771795334U, // <7,2,5,7>: Cost 4 vext3 <2,2,5,7>, <2,5,7,0>
+ 2692745110U, // <7,2,5,u>: Cost 3 vext3 <1,3,5,7>, <2,5,u,7>
+ 2572894310U, // <7,2,6,0>: Cost 3 vext1 <3,7,2,6>, LHS
+ 2712061860U, // <7,2,6,1>: Cost 3 vext3 RHS, <2,6,1,3>
+ 2700486577U, // <7,2,6,2>: Cost 3 vext3 <2,6,2,7>, <2,6,2,7>
+ 1626818490U, // <7,2,6,3>: Cost 2 vext3 <2,6,3,7>, <2,6,3,7>
+ 2572897590U, // <7,2,6,4>: Cost 3 vext1 <3,7,2,6>, RHS
+ 2700707788U, // <7,2,6,5>: Cost 3 vext3 <2,6,5,7>, <2,6,5,7>
+ 2700781525U, // <7,2,6,6>: Cost 3 vext3 <2,6,6,7>, <2,6,6,7>
+ 3774597086U, // <7,2,6,7>: Cost 4 vext3 <2,6,7,7>, <2,6,7,7>
+ 1627187175U, // <7,2,6,u>: Cost 2 vext3 <2,6,u,7>, <2,6,u,7>
2735949802U, // <7,2,7,0>: Cost 3 vext3 RHS, <2,7,0,1>
- 3729347651U, // <7,2,7,1>: Cost 4 vext2 <6,3,7,2>, <7,1,0,3>
- 3705459887U, // <7,2,7,2>: Cost 4 vext2 <2,3,7,2>, <7,2,3,3>
- 2934296600U, // <7,2,7,3>: Cost 3 vzipl LHS, <5,5,7,7>
- 2602765622U, // <7,2,7,4>: Cost 3 vext1 <u,7,2,7>, RHS
- 3721385364U, // <7,2,7,5>: Cost 4 vext2 <5,0,7,2>, <7,5,1,7>
- 3780200481U, // <7,2,7,6>: Cost 4 vext3 <3,6,2,7>, <2,7,6,2>
- 2602767980U, // <7,2,7,7>: Cost 3 vext1 <u,7,2,7>, <7,7,7,7>
- 2934337560U, // <7,2,7,u>: Cost 3 vzipl LHS, <5,5,7,7>
+ 3780200434U, // <7,2,7,1>: Cost 4 vext3 <3,6,2,7>, <2,7,1,0>
+ 3773564928U, // <7,2,7,2>: Cost 4 vext3 <2,5,2,7>, <2,7,2,5>
+ 2986541158U, // <7,2,7,3>: Cost 3 vzipr <5,5,7,7>, LHS
+ 2554989878U, // <7,2,7,4>: Cost 3 vext1 <0,7,2,7>, RHS
+ 3775113245U, // <7,2,7,5>: Cost 4 vext3 <2,7,5,7>, <2,7,5,7>
+ 4060283228U, // <7,2,7,6>: Cost 4 vzipr <5,5,7,7>, <0,4,2,6>
+ 2554992236U, // <7,2,7,7>: Cost 3 vext1 <0,7,2,7>, <7,7,7,7>
+ 2986541163U, // <7,2,7,u>: Cost 3 vzipr <5,5,7,7>, LHS
1638320187U, // <7,2,u,0>: Cost 2 vext3 RHS, <2,u,0,1>
- 2712062019U, // <7,2,u,1>: Cost 3 vext3 RHS, <2,u,1,0>
+ 2693924936U, // <7,2,u,1>: Cost 3 vext3 <1,5,3,7>, <2,u,1,5>
1638319720U, // <7,2,u,2>: Cost 2 vext3 RHS, <2,2,2,2>
- 1640310876U, // <7,2,u,3>: Cost 2 vext3 RHS, <2,u,3,7>
+ 1628145756U, // <7,2,u,3>: Cost 2 vext3 <2,u,3,7>, <2,u,3,7>
1638320227U, // <7,2,u,4>: Cost 2 vext3 RHS, <2,u,4,5>
- 2712062056U, // <7,2,u,5>: Cost 3 vext3 RHS, <2,u,5,1>
- 2712062066U, // <7,2,u,6>: Cost 3 vext3 RHS, <2,u,6,2>
+ 2702035054U, // <7,2,u,5>: Cost 3 vext3 <2,u,5,7>, <2,u,5,7>
+ 2702108791U, // <7,2,u,6>: Cost 3 vext3 <2,u,6,7>, <2,u,6,7>
2735949945U, // <7,2,u,7>: Cost 3 vext3 RHS, <2,u,7,0>
- 1638320259U, // <7,2,u,u>: Cost 2 vext3 RHS, <2,u,u,1>
+ 1628514441U, // <7,2,u,u>: Cost 2 vext3 <2,u,u,7>, <2,u,u,7>
2712062091U, // <7,3,0,0>: Cost 3 vext3 RHS, <3,0,0,0>
1638320278U, // <7,3,0,1>: Cost 2 vext3 RHS, <3,0,1,2>
2712062109U, // <7,3,0,2>: Cost 3 vext3 RHS, <3,0,2,0>
- 2712062119U, // <7,3,0,3>: Cost 3 vext3 RHS, <3,0,3,1>
+ 2590836886U, // <7,3,0,3>: Cost 3 vext1 <6,7,3,0>, <3,0,1,2>
2712062128U, // <7,3,0,4>: Cost 3 vext3 RHS, <3,0,4,1>
2712062138U, // <7,3,0,5>: Cost 3 vext3 RHS, <3,0,5,2>
2590839656U, // <7,3,0,6>: Cost 3 vext1 <6,7,3,0>, <6,7,3,0>
- 3722052169U, // <7,3,0,7>: Cost 4 vext2 <5,1,7,3>, <0,7,2,0>
+ 3311414017U, // <7,3,0,7>: Cost 4 vrev <3,7,7,0>
1638320341U, // <7,3,0,u>: Cost 2 vext3 RHS, <3,0,u,2>
- 2712062174U, // <7,3,1,0>: Cost 3 vext3 RHS, <3,1,0,2>
+ 2237164227U, // <7,3,1,0>: Cost 3 vrev <3,7,0,1>
2712062182U, // <7,3,1,1>: Cost 3 vext3 RHS, <3,1,1,1>
2712062193U, // <7,3,1,2>: Cost 3 vext3 RHS, <3,1,2,3>
- 2712062202U, // <7,3,1,3>: Cost 3 vext3 RHS, <3,1,3,3>
- 2712209670U, // <7,3,1,4>: Cost 3 vext3 RHS, <3,1,4,6>
- 2712062220U, // <7,3,1,5>: Cost 3 vext3 RHS, <3,1,5,3>
- 3785804053U, // <7,3,1,6>: Cost 4 vext3 RHS, <3,1,6,3>
- 2648311083U, // <7,3,1,7>: Cost 3 vext2 <5,1,7,3>, <1,7,3,0>
- 2712062247U, // <7,3,1,u>: Cost 3 vext3 RHS, <3,1,u,3>
+ 2692745468U, // <7,3,1,3>: Cost 3 vext3 <1,3,5,7>, <3,1,3,5>
+ 2712062214U, // <7,3,1,4>: Cost 3 vext3 RHS, <3,1,4,6>
+ 2693925132U, // <7,3,1,5>: Cost 3 vext3 <1,5,3,7>, <3,1,5,3>
+ 3768183059U, // <7,3,1,6>: Cost 4 vext3 <1,6,1,7>, <3,1,6,1>
+ 2692745504U, // <7,3,1,7>: Cost 3 vext3 <1,3,5,7>, <3,1,7,5>
+ 2696063273U, // <7,3,1,u>: Cost 3 vext3 <1,u,5,7>, <3,1,u,5>
2712062254U, // <7,3,2,0>: Cost 3 vext3 RHS, <3,2,0,1>
2712062262U, // <7,3,2,1>: Cost 3 vext3 RHS, <3,2,1,0>
2712062273U, // <7,3,2,2>: Cost 3 vext3 RHS, <3,2,2,2>
2712062280U, // <7,3,2,3>: Cost 3 vext3 RHS, <3,2,3,0>
- 2712062292U, // <7,3,2,4>: Cost 3 vext3 RHS, <3,2,4,3>
+ 2712062294U, // <7,3,2,4>: Cost 3 vext3 RHS, <3,2,4,5>
2712062302U, // <7,3,2,5>: Cost 3 vext3 RHS, <3,2,5,4>
- 2648311738U, // <7,3,2,6>: Cost 3 vext2 <5,1,7,3>, <2,6,3,7>
- 2654947332U, // <7,3,2,7>: Cost 3 vext2 <6,2,7,3>, <2,7,3,0>
+ 2700560742U, // <7,3,2,6>: Cost 3 vext3 <2,6,3,7>, <3,2,6,3>
+ 2712062319U, // <7,3,2,7>: Cost 3 vext3 RHS, <3,2,7,3>
2712062325U, // <7,3,2,u>: Cost 3 vext3 RHS, <3,2,u,0>
2712062335U, // <7,3,3,0>: Cost 3 vext3 RHS, <3,3,0,1>
- 2712062344U, // <7,3,3,1>: Cost 3 vext3 RHS, <3,3,1,1>
- 2712062354U, // <7,3,3,2>: Cost 3 vext3 RHS, <3,3,2,2>
+ 2636368158U, // <7,3,3,1>: Cost 3 vext2 <3,1,7,3>, <3,1,7,3>
+ 2637031791U, // <7,3,3,2>: Cost 3 vext2 <3,2,7,3>, <3,2,7,3>
1638320540U, // <7,3,3,3>: Cost 2 vext3 RHS, <3,3,3,3>
2712062374U, // <7,3,3,4>: Cost 3 vext3 RHS, <3,3,4,4>
- 2712062384U, // <7,3,3,5>: Cost 3 vext3 RHS, <3,3,5,5>
- 2654947978U, // <7,3,3,6>: Cost 3 vext2 <6,2,7,3>, <3,6,2,7>
- 3722054339U, // <7,3,3,7>: Cost 4 vext2 <5,1,7,3>, <3,7,0,1>
+ 2704689586U, // <7,3,3,5>: Cost 3 vext3 <3,3,5,7>, <3,3,5,7>
+ 2590864235U, // <7,3,3,6>: Cost 3 vext1 <6,7,3,3>, <6,7,3,3>
+ 2704837060U, // <7,3,3,7>: Cost 3 vext3 <3,3,7,7>, <3,3,7,7>
1638320540U, // <7,3,3,u>: Cost 2 vext3 RHS, <3,3,3,3>
2712062416U, // <7,3,4,0>: Cost 3 vext3 RHS, <3,4,0,1>
2712062426U, // <7,3,4,1>: Cost 3 vext3 RHS, <3,4,1,2>
2566981640U, // <7,3,4,2>: Cost 3 vext1 <2,7,3,4>, <2,7,3,4>
- 2590870018U, // <7,3,4,3>: Cost 3 vext1 <6,7,3,4>, <3,4,5,6>
+ 2712062447U, // <7,3,4,3>: Cost 3 vext3 RHS, <3,4,3,5>
2712062456U, // <7,3,4,4>: Cost 3 vext3 RHS, <3,4,4,5>
1638320642U, // <7,3,4,5>: Cost 2 vext3 RHS, <3,4,5,6>
- 2712062469U, // <7,3,4,6>: Cost 3 vext3 RHS, <3,4,6,0>
- 3785951763U, // <7,3,4,7>: Cost 4 vext3 RHS, <3,4,7,5>
+ 2648313204U, // <7,3,4,6>: Cost 3 vext2 <5,1,7,3>, <4,6,4,6>
+ 3311446789U, // <7,3,4,7>: Cost 4 vrev <3,7,7,4>
1638320669U, // <7,3,4,u>: Cost 2 vext3 RHS, <3,4,u,6>
- 2712062498U, // <7,3,5,0>: Cost 3 vext3 RHS, <3,5,0,2>
+ 2602819686U, // <7,3,5,0>: Cost 3 vext1 <u,7,3,5>, LHS
1574571728U, // <7,3,5,1>: Cost 2 vext2 <5,1,7,3>, <5,1,7,3>
2648977185U, // <7,3,5,2>: Cost 3 vext2 <5,2,7,3>, <5,2,7,3>
- 2712062528U, // <7,3,5,3>: Cost 3 vext3 RHS, <3,5,3,5>
- 2712209994U, // <7,3,5,4>: Cost 3 vext3 RHS, <3,5,4,6>
- 2712210004U, // <7,3,5,5>: Cost 3 vext3 RHS, <3,5,5,7>
+ 2705869378U, // <7,3,5,3>: Cost 3 vext3 <3,5,3,7>, <3,5,3,7>
+ 2237491947U, // <7,3,5,4>: Cost 3 vrev <3,7,4,5>
+ 2706016852U, // <7,3,5,5>: Cost 3 vext3 <3,5,5,7>, <3,5,5,7>
2648313954U, // <7,3,5,6>: Cost 3 vext2 <5,1,7,3>, <5,6,7,0>
- 2648313974U, // <7,3,5,7>: Cost 3 vext2 <5,1,7,3>, <5,7,0,2>
+ 2692745823U, // <7,3,5,7>: Cost 3 vext3 <1,3,5,7>, <3,5,7,0>
1579217159U, // <7,3,5,u>: Cost 2 vext2 <5,u,7,3>, <5,u,7,3>
- 2654949673U, // <7,3,6,0>: Cost 3 vext2 <6,2,7,3>, <6,0,2,1>
+ 2706311800U, // <7,3,6,0>: Cost 3 vext3 <3,6,0,7>, <3,6,0,7>
2654286249U, // <7,3,6,1>: Cost 3 vext2 <6,1,7,3>, <6,1,7,3>
1581208058U, // <7,3,6,2>: Cost 2 vext2 <6,2,7,3>, <6,2,7,3>
- 2712210067U, // <7,3,6,3>: Cost 3 vext3 RHS, <3,6,3,7>
- 2712210076U, // <7,3,6,4>: Cost 3 vext3 RHS, <3,6,4,7>
- 3785804446U, // <7,3,6,5>: Cost 4 vext3 RHS, <3,6,5,0>
- 2648314680U, // <7,3,6,6>: Cost 3 vext2 <5,1,7,3>, <6,6,6,6>
- 2712210103U, // <7,3,6,7>: Cost 3 vext3 RHS, <3,6,7,7>
+ 2706533011U, // <7,3,6,3>: Cost 3 vext3 <3,6,3,7>, <3,6,3,7>
+ 2706606748U, // <7,3,6,4>: Cost 3 vext3 <3,6,4,7>, <3,6,4,7>
+ 3780422309U, // <7,3,6,5>: Cost 4 vext3 <3,6,5,7>, <3,6,5,7>
+ 2712062637U, // <7,3,6,6>: Cost 3 vext3 RHS, <3,6,6,6>
+ 2706827959U, // <7,3,6,7>: Cost 3 vext3 <3,6,7,7>, <3,6,7,7>
1585189856U, // <7,3,6,u>: Cost 2 vext2 <6,u,7,3>, <6,u,7,3>
- 2712062666U, // <7,3,7,0>: Cost 3 vext3 RHS, <3,7,0,u>
+ 2693925571U, // <7,3,7,0>: Cost 3 vext3 <1,5,3,7>, <3,7,0,1>
2693925584U, // <7,3,7,1>: Cost 3 vext3 <1,5,3,7>, <3,7,1,5>
- 2654950575U, // <7,3,7,2>: Cost 3 vext2 <6,2,7,3>, <7,2,3,3>
- 2648315152U, // <7,3,7,3>: Cost 3 vext2 <5,1,7,3>, <7,3,5,1>
- 2648315238U, // <7,3,7,4>: Cost 3 vext2 <5,1,7,3>, <7,4,5,6>
- 2648315284U, // <7,3,7,5>: Cost 3 vext2 <5,1,7,3>, <7,5,1,7>
+ 2700561114U, // <7,3,7,2>: Cost 3 vext3 <2,6,3,7>, <3,7,2,6>
+ 2572978916U, // <7,3,7,3>: Cost 3 vext1 <3,7,3,7>, <3,7,3,7>
+ 2693925611U, // <7,3,7,4>: Cost 3 vext3 <1,5,3,7>, <3,7,4,5>
+ 2707344118U, // <7,3,7,5>: Cost 3 vext3 <3,7,5,7>, <3,7,5,7>
2654950894U, // <7,3,7,6>: Cost 3 vext2 <6,2,7,3>, <7,6,2,7>
2648315500U, // <7,3,7,7>: Cost 3 vext2 <5,1,7,3>, <7,7,7,7>
- 2648315522U, // <7,3,7,u>: Cost 3 vext2 <5,1,7,3>, <7,u,1,2>
- 2712062740U, // <7,3,u,0>: Cost 3 vext3 RHS, <3,u,0,1>
+ 2693925643U, // <7,3,7,u>: Cost 3 vext3 <1,5,3,7>, <3,7,u,1>
+ 2237221578U, // <7,3,u,0>: Cost 3 vrev <3,7,0,u>
1638320926U, // <7,3,u,1>: Cost 2 vext3 RHS, <3,u,1,2>
1593153452U, // <7,3,u,2>: Cost 2 vext2 <u,2,7,3>, <u,2,7,3>
1638320540U, // <7,3,u,3>: Cost 2 vext3 RHS, <3,3,3,3>
- 2712062778U, // <7,3,u,4>: Cost 3 vext3 RHS, <3,u,4,3>
+ 2237516526U, // <7,3,u,4>: Cost 3 vrev <3,7,4,u>
1638320966U, // <7,3,u,5>: Cost 2 vext3 RHS, <3,u,5,6>
- 2712062793U, // <7,3,u,6>: Cost 3 vext3 RHS, <3,u,6,0>
- 2714053465U, // <7,3,u,7>: Cost 3 vext3 RHS, <3,u,7,7>
+ 2712062796U, // <7,3,u,6>: Cost 3 vext3 RHS, <3,u,6,3>
+ 2692967250U, // <7,3,u,7>: Cost 3 vext3 <1,3,u,7>, <3,u,7,0>
1638320989U, // <7,3,u,u>: Cost 2 vext3 RHS, <3,u,u,2>
- 2712062821U, // <7,4,0,0>: Cost 3 vext3 RHS, <4,0,0,1>
+ 2651635712U, // <7,4,0,0>: Cost 3 vext2 <5,6,7,4>, <0,0,0,0>
1577893990U, // <7,4,0,1>: Cost 2 vext2 <5,6,7,4>, LHS
2651635876U, // <7,4,0,2>: Cost 3 vext2 <5,6,7,4>, <0,2,0,2>
3785804672U, // <7,4,0,3>: Cost 4 vext3 RHS, <4,0,3,1>
- 2712210318U, // <7,4,0,4>: Cost 3 vext3 RHS, <4,0,4,6>
- 1638321042U, // <7,4,0,5>: Cost 2 vext3 RHS, <4,0,5,1>
- 1638321052U, // <7,4,0,6>: Cost 2 vext3 RHS, <4,0,6,2>
- 3664655354U, // <7,4,0,7>: Cost 4 vext1 <6,7,4,0>, <7,0,1,2>
- 1638321069U, // <7,4,0,u>: Cost 2 vext3 RHS, <4,0,u,1>
+ 2651636050U, // <7,4,0,4>: Cost 3 vext2 <5,6,7,4>, <0,4,1,5>
+ 1638468498U, // <7,4,0,5>: Cost 2 vext3 RHS, <4,0,5,1>
+ 1638468508U, // <7,4,0,6>: Cost 2 vext3 RHS, <4,0,6,2>
+ 3787795364U, // <7,4,0,7>: Cost 4 vext3 RHS, <4,0,7,1>
+ 1640459181U, // <7,4,0,u>: Cost 2 vext3 RHS, <4,0,u,1>
2651636470U, // <7,4,1,0>: Cost 3 vext2 <5,6,7,4>, <1,0,3,2>
2651636532U, // <7,4,1,1>: Cost 3 vext2 <5,6,7,4>, <1,1,1,1>
2712062922U, // <7,4,1,2>: Cost 3 vext3 RHS, <4,1,2,3>
- 3785804752U, // <7,4,1,3>: Cost 4 vext3 RHS, <4,1,3,0>
- 2735950812U, // <7,4,1,4>: Cost 3 vext3 RHS, <4,1,4,3>
+ 2639029248U, // <7,4,1,3>: Cost 3 vext2 <3,5,7,4>, <1,3,5,7>
+ 2712062940U, // <7,4,1,4>: Cost 3 vext3 RHS, <4,1,4,3>
2712062946U, // <7,4,1,5>: Cost 3 vext3 RHS, <4,1,5,0>
- 2712062956U, // <7,4,1,6>: Cost 3 vext3 RHS, <4,1,6,1>
- 3725378859U, // <7,4,1,7>: Cost 4 vext2 <5,6,7,4>, <1,7,3,0>
+ 2712062958U, // <7,4,1,6>: Cost 3 vext3 RHS, <4,1,6,3>
+ 3785804791U, // <7,4,1,7>: Cost 4 vext3 RHS, <4,1,7,3>
2712062973U, // <7,4,1,u>: Cost 3 vext3 RHS, <4,1,u,0>
3785804807U, // <7,4,2,0>: Cost 4 vext3 RHS, <4,2,0,1>
3785804818U, // <7,4,2,1>: Cost 4 vext3 RHS, <4,2,1,3>
2651637352U, // <7,4,2,2>: Cost 3 vext2 <5,6,7,4>, <2,2,2,2>
2651637414U, // <7,4,2,3>: Cost 3 vext2 <5,6,7,4>, <2,3,0,1>
- 2735950893U, // <7,4,2,4>: Cost 3 vext3 RHS, <4,2,4,3>
- 2712063029U, // <7,4,2,5>: Cost 3 vext3 RHS, <4,2,5,2>
+ 3716753194U, // <7,4,2,4>: Cost 4 vext2 <4,2,7,4>, <2,4,5,7>
+ 2712063030U, // <7,4,2,5>: Cost 3 vext3 RHS, <4,2,5,3>
2712063036U, // <7,4,2,6>: Cost 3 vext3 RHS, <4,2,6,0>
- 3722725389U, // <7,4,2,7>: Cost 4 vext2 <5,2,7,4>, <2,7,4,0>
- 2712063056U, // <7,4,2,u>: Cost 3 vext3 RHS, <4,2,u,2>
+ 3773123658U, // <7,4,2,7>: Cost 4 vext3 <2,4,5,7>, <4,2,7,5>
+ 2712063054U, // <7,4,2,u>: Cost 3 vext3 RHS, <4,2,u,0>
2651637910U, // <7,4,3,0>: Cost 3 vext2 <5,6,7,4>, <3,0,1,2>
- 3785804896U, // <7,4,3,1>: Cost 4 vext3 RHS, <4,3,1,0>
+ 3712772348U, // <7,4,3,1>: Cost 4 vext2 <3,5,7,4>, <3,1,3,5>
3785804906U, // <7,4,3,2>: Cost 4 vext3 RHS, <4,3,2,1>
2651638172U, // <7,4,3,3>: Cost 3 vext2 <5,6,7,4>, <3,3,3,3>
2651638274U, // <7,4,3,4>: Cost 3 vext2 <5,6,7,4>, <3,4,5,6>
- 2712063111U, // <7,4,3,5>: Cost 3 vext3 RHS, <4,3,5,3>
- 2712063118U, // <7,4,3,6>: Cost 3 vext3 RHS, <4,3,6,1>
- 3729361638U, // <7,4,3,7>: Cost 4 vext2 <6,3,7,4>, <3,7,4,0>
- 2712063138U, // <7,4,3,u>: Cost 3 vext3 RHS, <4,3,u,3>
- 2712063144U, // <7,4,4,0>: Cost 3 vext3 RHS, <4,4,0,0>
- 3785804979U, // <7,4,4,1>: Cost 4 vext3 RHS, <4,4,1,2>
- 3785804988U, // <7,4,4,2>: Cost 4 vext3 RHS, <4,4,2,2>
+ 2639030883U, // <7,4,3,5>: Cost 3 vext2 <3,5,7,4>, <3,5,7,4>
+ 2712063122U, // <7,4,3,6>: Cost 3 vext3 RHS, <4,3,6,5>
+ 3712772836U, // <7,4,3,7>: Cost 4 vext2 <3,5,7,4>, <3,7,3,7>
+ 2641021782U, // <7,4,3,u>: Cost 3 vext2 <3,u,7,4>, <3,u,7,4>
+ 2714053802U, // <7,4,4,0>: Cost 3 vext3 RHS, <4,4,0,2>
+ 3785804978U, // <7,4,4,1>: Cost 4 vext3 RHS, <4,4,1,1>
+ 3716754505U, // <7,4,4,2>: Cost 4 vext2 <4,2,7,4>, <4,2,7,4>
3785804998U, // <7,4,4,3>: Cost 4 vext3 RHS, <4,4,3,3>
1638321360U, // <7,4,4,4>: Cost 2 vext3 RHS, <4,4,4,4>
1638468826U, // <7,4,4,5>: Cost 2 vext3 RHS, <4,4,5,5>
1638468836U, // <7,4,4,6>: Cost 2 vext3 RHS, <4,4,6,6>
- 3787795694U, // <7,4,4,7>: Cost 4 vext3 RHS, <4,4,7,7>
- 1638468853U, // <7,4,4,u>: Cost 2 vext3 RHS, <4,4,u,5>
+ 3785215214U, // <7,4,4,7>: Cost 4 vext3 <4,4,7,7>, <4,4,7,7>
+ 1640459509U, // <7,4,4,u>: Cost 2 vext3 RHS, <4,4,u,5>
1517207654U, // <7,4,5,0>: Cost 2 vext1 <6,7,4,5>, LHS
- 2651639504U, // <7,4,5,1>: Cost 3 vext2 <5,6,7,4>, <5,1,7,3>
+ 2573034640U, // <7,4,5,1>: Cost 3 vext1 <3,7,4,5>, <1,5,3,7>
2712063246U, // <7,4,5,2>: Cost 3 vext3 RHS, <4,5,2,3>
- 2590951574U, // <7,4,5,3>: Cost 3 vext1 <6,7,4,5>, <3,0,1,2>
+ 2573036267U, // <7,4,5,3>: Cost 3 vext1 <3,7,4,5>, <3,7,4,5>
1517210934U, // <7,4,5,4>: Cost 2 vext1 <6,7,4,5>, RHS
- 2712210726U, // <7,4,5,5>: Cost 3 vext3 RHS, <4,5,5,0>
+ 2711989549U, // <7,4,5,5>: Cost 3 vext3 <4,5,5,7>, <4,5,5,7>
564579638U, // <7,4,5,6>: Cost 1 vext3 RHS, RHS
- 2652303543U, // <7,4,5,7>: Cost 3 vext2 <5,7,7,4>, <5,7,7,4>
+ 2651639976U, // <7,4,5,7>: Cost 3 vext2 <5,6,7,4>, <5,7,5,7>
564579656U, // <7,4,5,u>: Cost 1 vext3 RHS, RHS
- 1638321484U, // <7,4,6,0>: Cost 2 vext3 RHS, <4,6,0,2>
- 2712063316U, // <7,4,6,1>: Cost 3 vext3 RHS, <4,6,1,1>
- 2712063324U, // <7,4,6,2>: Cost 3 vext3 RHS, <4,6,2,0>
- 2712063334U, // <7,4,6,3>: Cost 3 vext3 RHS, <4,6,3,1>
+ 2712063307U, // <7,4,6,0>: Cost 3 vext3 RHS, <4,6,0,1>
+ 3767668056U, // <7,4,6,1>: Cost 4 vext3 <1,5,3,7>, <4,6,1,5>
+ 2651640314U, // <7,4,6,2>: Cost 3 vext2 <5,6,7,4>, <6,2,7,3>
+ 2655621708U, // <7,4,6,3>: Cost 3 vext2 <6,3,7,4>, <6,3,7,4>
1638468980U, // <7,4,6,4>: Cost 2 vext3 RHS, <4,6,4,6>
- 2712210814U, // <7,4,6,5>: Cost 3 vext3 RHS, <4,6,5,7>
- 2712210816U, // <7,4,6,6>: Cost 3 vext3 RHS, <4,6,6,0>
- 2651640654U, // <7,4,6,7>: Cost 3 vext2 <5,6,7,4>, <6,7,0,1>
- 1662209428U, // <7,4,6,u>: Cost 2 vext3 RHS, <4,6,u,2>
+ 2712063358U, // <7,4,6,5>: Cost 3 vext3 RHS, <4,6,5,7>
+ 2712063367U, // <7,4,6,6>: Cost 3 vext3 RHS, <4,6,6,7>
+ 2712210826U, // <7,4,6,7>: Cost 3 vext3 RHS, <4,6,7,1>
+ 1638469012U, // <7,4,6,u>: Cost 2 vext3 RHS, <4,6,u,2>
2651640826U, // <7,4,7,0>: Cost 3 vext2 <5,6,7,4>, <7,0,1,2>
- 3725382723U, // <7,4,7,1>: Cost 4 vext2 <5,6,7,4>, <7,1,0,3>
- 3725382821U, // <7,4,7,2>: Cost 4 vext2 <5,6,7,4>, <7,2,2,2>
- 3785952700U, // <7,4,7,3>: Cost 4 vext3 RHS, <4,7,3,6>
+ 3773713830U, // <7,4,7,1>: Cost 4 vext3 <2,5,4,7>, <4,7,1,2>
+ 3773713842U, // <7,4,7,2>: Cost 4 vext3 <2,5,4,7>, <4,7,2,5>
+ 3780349372U, // <7,4,7,3>: Cost 4 vext3 <3,6,4,7>, <4,7,3,6>
2651641140U, // <7,4,7,4>: Cost 3 vext2 <5,6,7,4>, <7,4,0,1>
- 2980501100U, // <7,4,7,5>: Cost 3 vzipr RHS, <7,7,7,7>
- 3114718828U, // <7,4,7,6>: Cost 3 vtrnr RHS, <7,7,7,7>
+ 2712210888U, // <7,4,7,5>: Cost 3 vext3 RHS, <4,7,5,0>
+ 2712210898U, // <7,4,7,6>: Cost 3 vext3 RHS, <4,7,6,1>
2651641452U, // <7,4,7,7>: Cost 3 vext2 <5,6,7,4>, <7,7,7,7>
- 3114866284U, // <7,4,7,u>: Cost 3 vtrnr RHS, <7,7,7,7>
- 1638321646U, // <7,4,u,0>: Cost 2 vext3 RHS, <4,u,0,2>
+ 2713538026U, // <7,4,7,u>: Cost 3 vext3 <4,7,u,7>, <4,7,u,7>
+ 1517232230U, // <7,4,u,0>: Cost 2 vext1 <6,7,4,u>, LHS
1577899822U, // <7,4,u,1>: Cost 2 vext2 <5,6,7,4>, LHS
- 2712063488U, // <7,4,u,2>: Cost 3 vext3 RHS, <4,u,2,2>
- 2712063496U, // <7,4,u,3>: Cost 3 vext3 RHS, <4,u,3,1>
- 1638469142U, // <7,4,u,4>: Cost 2 vext3 RHS, <4,u,4,6>
- 1577900186U, // <7,4,u,5>: Cost 2 vext2 <5,6,7,4>, RHS
+ 2712063489U, // <7,4,u,2>: Cost 3 vext3 RHS, <4,u,2,3>
+ 2573060846U, // <7,4,u,3>: Cost 3 vext1 <3,7,4,u>, <3,7,4,u>
+ 1640312342U, // <7,4,u,4>: Cost 2 vext3 RHS, <4,u,4,6>
+ 1638469146U, // <7,4,u,5>: Cost 2 vext3 RHS, <4,u,5,1>
564579881U, // <7,4,u,6>: Cost 1 vext3 RHS, RHS
- 2651642112U, // <7,4,u,7>: Cost 3 vext2 <5,6,7,4>, <u,7,0,1>
+ 2714054192U, // <7,4,u,7>: Cost 3 vext3 RHS, <4,u,7,5>
564579899U, // <7,4,u,u>: Cost 1 vext3 RHS, RHS
- 3785805373U, // <7,5,0,0>: Cost 4 vext3 RHS, <5,0,0,0>
- 2712063559U, // <7,5,0,1>: Cost 3 vext3 RHS, <5,0,1,1>
- 2819413350U, // <7,5,0,2>: Cost 3 vuzpr LHS, <7,4,5,6>
- 3785805404U, // <7,5,0,3>: Cost 4 vext3 RHS, <5,0,3,4>
+ 2579038310U, // <7,5,0,0>: Cost 3 vext1 <4,7,5,0>, LHS
+ 2636382310U, // <7,5,0,1>: Cost 3 vext2 <3,1,7,5>, LHS
+ 2796339302U, // <7,5,0,2>: Cost 3 vuzpl <7,4,5,6>, LHS
+ 3646810719U, // <7,5,0,3>: Cost 4 vext1 <3,7,5,0>, <3,5,7,0>
2712063586U, // <7,5,0,4>: Cost 3 vext3 RHS, <5,0,4,1>
- 2712063595U, // <7,5,0,5>: Cost 3 vext3 RHS, <5,0,5,1>
- 2712063604U, // <7,5,0,6>: Cost 3 vext3 RHS, <5,0,6,1>
- 2712063613U, // <7,5,0,7>: Cost 3 vext3 RHS, <5,0,7,1>
- 2712063623U, // <7,5,0,u>: Cost 3 vext3 RHS, <5,0,u,2>
- 2712063631U, // <7,5,1,0>: Cost 3 vext3 RHS, <5,1,0,1>
- 3983692523U, // <7,5,1,1>: Cost 4 vzipl <4,0,5,1>, <6,5,7,1>
- 3785805474U, // <7,5,1,2>: Cost 4 vext3 RHS, <5,1,2,2>
- 3785805481U, // <7,5,1,3>: Cost 4 vext3 RHS, <5,1,3,0>
- 2712063666U, // <7,5,1,4>: Cost 3 vext3 RHS, <5,1,4,0>
+ 2735951467U, // <7,5,0,5>: Cost 3 vext3 RHS, <5,0,5,1>
+ 2735951476U, // <7,5,0,6>: Cost 3 vext3 RHS, <5,0,6,1>
+ 2579043322U, // <7,5,0,7>: Cost 3 vext1 <4,7,5,0>, <7,0,1,2>
+ 2636382877U, // <7,5,0,u>: Cost 3 vext2 <3,1,7,5>, LHS
+ 2712211087U, // <7,5,1,0>: Cost 3 vext3 RHS, <5,1,0,1>
+ 3698180916U, // <7,5,1,1>: Cost 4 vext2 <1,1,7,5>, <1,1,1,1>
+ 3710124950U, // <7,5,1,2>: Cost 4 vext2 <3,1,7,5>, <1,2,3,0>
+ 2636383232U, // <7,5,1,3>: Cost 3 vext2 <3,1,7,5>, <1,3,5,7>
+ 2712211127U, // <7,5,1,4>: Cost 3 vext3 RHS, <5,1,4,5>
2590994128U, // <7,5,1,5>: Cost 3 vext1 <6,7,5,1>, <5,1,7,3>
2590995323U, // <7,5,1,6>: Cost 3 vext1 <6,7,5,1>, <6,7,5,1>
- 1638321872U, // <7,5,1,7>: Cost 2 vext3 RHS, <5,1,7,3>
- 1638321881U, // <7,5,1,u>: Cost 2 vext3 RHS, <5,1,u,3>
+ 1638469328U, // <7,5,1,7>: Cost 2 vext3 RHS, <5,1,7,3>
+ 1638469337U, // <7,5,1,u>: Cost 2 vext3 RHS, <5,1,u,3>
3785805536U, // <7,5,2,0>: Cost 4 vext3 RHS, <5,2,0,1>
- 2712063723U, // <7,5,2,1>: Cost 3 vext3 RHS, <5,2,1,3>
- 3785805555U, // <7,5,2,2>: Cost 4 vext3 RHS, <5,2,2,2>
+ 3785805544U, // <7,5,2,1>: Cost 4 vext3 RHS, <5,2,1,0>
+ 3704817288U, // <7,5,2,2>: Cost 4 vext2 <2,2,7,5>, <2,2,5,7>
2712063742U, // <7,5,2,3>: Cost 3 vext3 RHS, <5,2,3,4>
- 3785805571U, // <7,5,2,4>: Cost 4 vext3 RHS, <5,2,4,0>
- 2735951631U, // <7,5,2,5>: Cost 3 vext3 RHS, <5,2,5,3>
- 2712063768U, // <7,5,2,6>: Cost 3 vext3 RHS, <5,2,6,3>
- 2712063774U, // <7,5,2,7>: Cost 3 vext3 RHS, <5,2,7,0>
- 2712063783U, // <7,5,2,u>: Cost 3 vext3 RHS, <5,2,u,0>
- 3785805617U, // <7,5,3,0>: Cost 4 vext3 RHS, <5,3,0,1>
- 3973738192U, // <7,5,3,1>: Cost 4 vzipl <2,3,5,1>, <5,1,7,3>
- 3785805637U, // <7,5,3,2>: Cost 4 vext3 RHS, <5,3,2,3>
- 3785805644U, // <7,5,3,3>: Cost 4 vext3 RHS, <5,3,3,1>
- 3785805652U, // <7,5,3,4>: Cost 4 vext3 RHS, <5,3,4,0>
- 3785805661U, // <7,5,3,5>: Cost 4 vext3 RHS, <5,3,5,0>
- 3980414672U, // <7,5,3,6>: Cost 4 vzipl <3,4,5,6>, <5,1,7,3>
- 2712063856U, // <7,5,3,7>: Cost 3 vext3 RHS, <5,3,7,1>
- 2712063865U, // <7,5,3,u>: Cost 3 vext3 RHS, <5,3,u,1>
- 2591015014U, // <7,5,4,0>: Cost 3 vext1 <6,7,5,4>, LHS
- 2712211343U, // <7,5,4,1>: Cost 3 vext3 RHS, <5,4,1,5>
- 3785805718U, // <7,5,4,2>: Cost 4 vext3 RHS, <5,4,2,3>
- 3785805726U, // <7,5,4,3>: Cost 4 vext3 RHS, <5,4,3,2>
- 2591018294U, // <7,5,4,4>: Cost 3 vext1 <6,7,5,4>, RHS
- 2712063924U, // <7,5,4,5>: Cost 3 vext3 RHS, <5,4,5,6>
- 2846283110U, // <7,5,4,6>: Cost 3 vuzpr RHS, <7,4,5,6>
+ 3716761386U, // <7,5,2,4>: Cost 4 vext2 <4,2,7,5>, <2,4,5,7>
+ 2714054415U, // <7,5,2,5>: Cost 3 vext3 RHS, <5,2,5,3>
+ 3774304024U, // <7,5,2,6>: Cost 4 vext3 <2,6,3,7>, <5,2,6,3>
+ 2712063777U, // <7,5,2,7>: Cost 3 vext3 RHS, <5,2,7,3>
+ 2712063787U, // <7,5,2,u>: Cost 3 vext3 RHS, <5,2,u,4>
+ 3634888806U, // <7,5,3,0>: Cost 4 vext1 <1,7,5,3>, LHS
+ 2636384544U, // <7,5,3,1>: Cost 3 vext2 <3,1,7,5>, <3,1,7,5>
+ 3710790001U, // <7,5,3,2>: Cost 4 vext2 <3,2,7,5>, <3,2,7,5>
+ 3710126492U, // <7,5,3,3>: Cost 4 vext2 <3,1,7,5>, <3,3,3,3>
+ 3634892086U, // <7,5,3,4>: Cost 4 vext1 <1,7,5,3>, RHS
+ 2639039076U, // <7,5,3,5>: Cost 3 vext2 <3,5,7,5>, <3,5,7,5>
+ 3713444533U, // <7,5,3,6>: Cost 4 vext2 <3,6,7,5>, <3,6,7,5>
+ 2693926767U, // <7,5,3,7>: Cost 3 vext3 <1,5,3,7>, <5,3,7,0>
+ 2712063864U, // <7,5,3,u>: Cost 3 vext3 RHS, <5,3,u,0>
+ 2579071078U, // <7,5,4,0>: Cost 3 vext1 <4,7,5,4>, LHS
+ 3646841856U, // <7,5,4,1>: Cost 4 vext1 <3,7,5,4>, <1,3,5,7>
+ 3716762698U, // <7,5,4,2>: Cost 4 vext2 <4,2,7,5>, <4,2,7,5>
+ 3646843491U, // <7,5,4,3>: Cost 4 vext1 <3,7,5,4>, <3,5,7,4>
+ 2579074358U, // <7,5,4,4>: Cost 3 vext1 <4,7,5,4>, RHS
+ 2636385590U, // <7,5,4,5>: Cost 3 vext2 <3,1,7,5>, RHS
+ 2645675406U, // <7,5,4,6>: Cost 3 vext2 <4,6,7,5>, <4,6,7,5>
1638322118U, // <7,5,4,7>: Cost 2 vext3 RHS, <5,4,7,6>
1638469583U, // <7,5,4,u>: Cost 2 vext3 RHS, <5,4,u,6>
- 2591023206U, // <7,5,5,0>: Cost 3 vext1 <6,7,5,5>, LHS
- 2712063964U, // <7,5,5,1>: Cost 3 vext3 RHS, <5,5,1,1>
- 3785805799U, // <7,5,5,2>: Cost 4 vext3 RHS, <5,5,2,3>
- 2649657204U, // <7,5,5,3>: Cost 3 vext2 <5,3,7,5>, <5,3,7,5>
+ 2714054611U, // <7,5,5,0>: Cost 3 vext3 RHS, <5,5,0,1>
+ 2652974800U, // <7,5,5,1>: Cost 3 vext2 <5,u,7,5>, <5,1,7,3>
+ 3710127905U, // <7,5,5,2>: Cost 4 vext2 <3,1,7,5>, <5,2,7,3>
+ 3785805808U, // <7,5,5,3>: Cost 4 vext3 RHS, <5,5,3,3>
2712211450U, // <7,5,5,4>: Cost 3 vext3 RHS, <5,5,4,4>
1638322180U, // <7,5,5,5>: Cost 2 vext3 RHS, <5,5,5,5>
2712064014U, // <7,5,5,6>: Cost 3 vext3 RHS, <5,5,6,6>
1638469656U, // <7,5,5,7>: Cost 2 vext3 RHS, <5,5,7,7>
1638469665U, // <7,5,5,u>: Cost 2 vext3 RHS, <5,5,u,7>
2712064036U, // <7,5,6,0>: Cost 3 vext3 RHS, <5,6,0,1>
- 2712211507U, // <7,5,6,1>: Cost 3 vext3 RHS, <5,6,1,7>
+ 2714054707U, // <7,5,6,1>: Cost 3 vext3 RHS, <5,6,1,7>
3785805879U, // <7,5,6,2>: Cost 4 vext3 RHS, <5,6,2,2>
2712064066U, // <7,5,6,3>: Cost 3 vext3 RHS, <5,6,3,4>
2712064076U, // <7,5,6,4>: Cost 3 vext3 RHS, <5,6,4,5>
- 2712211543U, // <7,5,6,5>: Cost 3 vext3 RHS, <5,6,5,7>
- 2712211552U, // <7,5,6,6>: Cost 3 vext3 RHS, <5,6,6,7>
+ 2714054743U, // <7,5,6,5>: Cost 3 vext3 RHS, <5,6,5,7>
+ 2712064096U, // <7,5,6,6>: Cost 3 vext3 RHS, <5,6,6,7>
1638322274U, // <7,5,6,7>: Cost 2 vext3 RHS, <5,6,7,0>
1638469739U, // <7,5,6,u>: Cost 2 vext3 RHS, <5,6,u,0>
- 2712064118U, // <7,5,7,0>: Cost 3 vext3 RHS, <5,7,0,2>
- 3785805950U, // <7,5,7,1>: Cost 4 vext3 RHS, <5,7,1,1>
- 3785805958U, // <7,5,7,2>: Cost 4 vext3 RHS, <5,7,2,0>
- 3785805968U, // <7,5,7,3>: Cost 4 vext3 RHS, <5,7,3,1>
- 2712211614U, // <7,5,7,4>: Cost 3 vext3 RHS, <5,7,4,6>
- 2585071312U, // <7,5,7,5>: Cost 3 vext1 <5,7,5,7>, <5,1,7,3>
- 4060894828U, // <7,5,7,6>: Cost 4 vzipr <5,6,7,0>, <7,7,7,7>
- 3047609964U, // <7,5,7,7>: Cost 3 vtrnl RHS, <7,7,7,7>
- 3047618156U, // <7,5,7,u>: Cost 3 vtrnl RHS, <7,7,7,7>
- 2712064198U, // <7,5,u,0>: Cost 3 vext3 RHS, <5,u,0,1>
- 2712064208U, // <7,5,u,1>: Cost 3 vext3 RHS, <5,u,1,2>
- 2867189094U, // <7,5,u,2>: Cost 3 vuzpr LHS, <7,4,5,6>
- 2712064228U, // <7,5,u,3>: Cost 3 vext3 RHS, <5,u,3,4>
- 2712064233U, // <7,5,u,4>: Cost 3 vext3 RHS, <5,u,4,0>
- 1638322180U, // <7,5,u,5>: Cost 2 vext3 RHS, <5,5,5,5>
- 2712064254U, // <7,5,u,6>: Cost 3 vext3 RHS, <5,u,6,3>
- 1638322439U, // <7,5,u,7>: Cost 2 vext3 RHS, <5,u,7,3>
- 1638322448U, // <7,5,u,u>: Cost 2 vext3 RHS, <5,u,u,3>
+ 1511325798U, // <7,5,7,0>: Cost 2 vext1 <5,7,5,7>, LHS
+ 2692747392U, // <7,5,7,1>: Cost 3 vext3 <1,3,5,7>, <5,7,1,3>
+ 2585069160U, // <7,5,7,2>: Cost 3 vext1 <5,7,5,7>, <2,2,2,2>
+ 2573126390U, // <7,5,7,3>: Cost 3 vext1 <3,7,5,7>, <3,7,5,7>
+ 1511329078U, // <7,5,7,4>: Cost 2 vext1 <5,7,5,7>, RHS
+ 1638469800U, // <7,5,7,5>: Cost 2 vext3 RHS, <5,7,5,7>
+ 2712211626U, // <7,5,7,6>: Cost 3 vext3 RHS, <5,7,6,0>
+ 2712211636U, // <7,5,7,7>: Cost 3 vext3 RHS, <5,7,7,1>
+ 1638469823U, // <7,5,7,u>: Cost 2 vext3 RHS, <5,7,u,3>
+ 1511333990U, // <7,5,u,0>: Cost 2 vext1 <5,7,5,u>, LHS
+ 2636388142U, // <7,5,u,1>: Cost 3 vext2 <3,1,7,5>, LHS
+ 2712211671U, // <7,5,u,2>: Cost 3 vext3 RHS, <5,u,2,0>
+ 2573134583U, // <7,5,u,3>: Cost 3 vext1 <3,7,5,u>, <3,7,5,u>
+ 1511337270U, // <7,5,u,4>: Cost 2 vext1 <5,7,5,u>, RHS
+ 1638469881U, // <7,5,u,5>: Cost 2 vext3 RHS, <5,u,5,7>
+ 2712064258U, // <7,5,u,6>: Cost 3 vext3 RHS, <5,u,6,7>
+ 1638469892U, // <7,5,u,7>: Cost 2 vext3 RHS, <5,u,7,0>
+ 1638469904U, // <7,5,u,u>: Cost 2 vext3 RHS, <5,u,u,3>
2650324992U, // <7,6,0,0>: Cost 3 vext2 <5,4,7,6>, <0,0,0,0>
1576583270U, // <7,6,0,1>: Cost 2 vext2 <5,4,7,6>, LHS
- 2712064297U, // <7,6,0,2>: Cost 3 vext3 RHS, <6,0,2,1>
+ 2712064300U, // <7,6,0,2>: Cost 3 vext3 RHS, <6,0,2,4>
2255295336U, // <7,6,0,3>: Cost 3 vrev <6,7,3,0>
- 2650325330U, // <7,6,0,4>: Cost 3 vext2 <5,4,7,6>, <0,4,1,5>
- 2579115974U, // <7,6,0,5>: Cost 3 vext1 <4,7,6,0>, <5,4,7,6>
+ 2712064316U, // <7,6,0,4>: Cost 3 vext3 RHS, <6,0,4,2>
+ 2585088098U, // <7,6,0,5>: Cost 3 vext1 <5,7,6,0>, <5,6,7,0>
2735952204U, // <7,6,0,6>: Cost 3 vext3 RHS, <6,0,6,0>
- 2712064342U, // <7,6,0,7>: Cost 3 vext3 RHS, <6,0,7,1>
+ 2712211799U, // <7,6,0,7>: Cost 3 vext3 RHS, <6,0,7,2>
1576583837U, // <7,6,0,u>: Cost 2 vext2 <5,4,7,6>, LHS
1181340494U, // <7,6,1,0>: Cost 2 vrev <6,7,0,1>
2650325812U, // <7,6,1,1>: Cost 3 vext2 <5,4,7,6>, <1,1,1,1>
- 2712064380U, // <7,6,1,2>: Cost 3 vext3 RHS, <6,1,2,3>
- 3785806210U, // <7,6,1,3>: Cost 4 vext3 RHS, <6,1,3,0>
- 3785806219U, // <7,6,1,4>: Cost 4 vext3 RHS, <6,1,4,0>
+ 2650325910U, // <7,6,1,2>: Cost 3 vext2 <5,4,7,6>, <1,2,3,0>
+ 2650325976U, // <7,6,1,3>: Cost 3 vext2 <5,4,7,6>, <1,3,1,3>
+ 2579123510U, // <7,6,1,4>: Cost 3 vext1 <4,7,6,1>, RHS
2650326160U, // <7,6,1,5>: Cost 3 vext2 <5,4,7,6>, <1,5,3,7>
- 2735952288U, // <7,6,1,6>: Cost 3 vext3 RHS, <6,1,6,3>
- 2712064423U, // <7,6,1,7>: Cost 3 vext3 RHS, <6,1,7,1>
+ 2714055072U, // <7,6,1,6>: Cost 3 vext3 RHS, <6,1,6,3>
+ 2712064425U, // <7,6,1,7>: Cost 3 vext3 RHS, <6,1,7,3>
1181930390U, // <7,6,1,u>: Cost 2 vrev <6,7,u,1>
- 2712064441U, // <7,6,2,0>: Cost 3 vext3 RHS, <6,2,0,1>
- 2255164248U, // <7,6,2,1>: Cost 3 vrev <6,7,1,2>
- 2712064461U, // <7,6,2,2>: Cost 3 vext3 RHS, <6,2,2,3>
+ 2712211897U, // <7,6,2,0>: Cost 3 vext3 RHS, <6,2,0,1>
+ 2714055108U, // <7,6,2,1>: Cost 3 vext3 RHS, <6,2,1,3>
+ 2650326632U, // <7,6,2,2>: Cost 3 vext2 <5,4,7,6>, <2,2,2,2>
2650326694U, // <7,6,2,3>: Cost 3 vext2 <5,4,7,6>, <2,3,0,1>
- 2712064476U, // <7,6,2,4>: Cost 3 vext3 RHS, <6,2,4,0>
- 3785806310U, // <7,6,2,5>: Cost 4 vext3 RHS, <6,2,5,1>
+ 2714055137U, // <7,6,2,4>: Cost 3 vext3 RHS, <6,2,4,5>
+ 2714055148U, // <7,6,2,5>: Cost 3 vext3 RHS, <6,2,5,7>
2650326970U, // <7,6,2,6>: Cost 3 vext2 <5,4,7,6>, <2,6,3,7>
- 1638322682U, // <7,6,2,7>: Cost 2 vext3 RHS, <6,2,7,3>
- 1638322691U, // <7,6,2,u>: Cost 2 vext3 RHS, <6,2,u,3>
+ 1638470138U, // <7,6,2,7>: Cost 2 vext3 RHS, <6,2,7,3>
+ 1638470147U, // <7,6,2,u>: Cost 2 vext3 RHS, <6,2,u,3>
2650327190U, // <7,6,3,0>: Cost 3 vext2 <5,4,7,6>, <3,0,1,2>
- 3785806354U, // <7,6,3,1>: Cost 4 vext3 RHS, <6,3,1,0>
+ 2255172441U, // <7,6,3,1>: Cost 3 vrev <6,7,1,3>
2255246178U, // <7,6,3,2>: Cost 3 vrev <6,7,2,3>
2650327452U, // <7,6,3,3>: Cost 3 vext2 <5,4,7,6>, <3,3,3,3>
2712064562U, // <7,6,3,4>: Cost 3 vext3 RHS, <6,3,4,5>
2650327627U, // <7,6,3,5>: Cost 3 vext2 <5,4,7,6>, <3,5,4,7>
- 3785806404U, // <7,6,3,6>: Cost 4 vext3 RHS, <6,3,6,5>
- 2712064584U, // <7,6,3,7>: Cost 3 vext3 RHS, <6,3,7,0>
+ 3713452726U, // <7,6,3,6>: Cost 4 vext2 <3,6,7,6>, <3,6,7,6>
+ 2700563016U, // <7,6,3,7>: Cost 3 vext3 <2,6,3,7>, <6,3,7,0>
2712064593U, // <7,6,3,u>: Cost 3 vext3 RHS, <6,3,u,0>
2650327954U, // <7,6,4,0>: Cost 3 vext2 <5,4,7,6>, <4,0,5,1>
- 3785806441U, // <7,6,4,1>: Cost 4 vext3 RHS, <6,4,1,6>
- 2712212081U, // <7,6,4,2>: Cost 3 vext3 RHS, <6,4,2,5>
+ 2735952486U, // <7,6,4,1>: Cost 3 vext3 RHS, <6,4,1,3>
+ 2735952497U, // <7,6,4,2>: Cost 3 vext3 RHS, <6,4,2,5>
2255328108U, // <7,6,4,3>: Cost 3 vrev <6,7,3,4>
2712212100U, // <7,6,4,4>: Cost 3 vext3 RHS, <6,4,4,6>
1576586550U, // <7,6,4,5>: Cost 2 vext2 <5,4,7,6>, RHS
- 2712212117U, // <7,6,4,6>: Cost 3 vext3 RHS, <6,4,6,5>
- 2712064670U, // <7,6,4,7>: Cost 3 vext3 RHS, <6,4,7,5>
+ 2714055312U, // <7,6,4,6>: Cost 3 vext3 RHS, <6,4,6,0>
+ 2712212126U, // <7,6,4,7>: Cost 3 vext3 RHS, <6,4,7,5>
1576586793U, // <7,6,4,u>: Cost 2 vext2 <5,4,7,6>, RHS
- 2712212146U, // <7,6,5,0>: Cost 3 vext3 RHS, <6,5,0,7>
+ 2579152998U, // <7,6,5,0>: Cost 3 vext1 <4,7,6,5>, LHS
2650328784U, // <7,6,5,1>: Cost 3 vext2 <5,4,7,6>, <5,1,7,3>
- 2712212164U, // <7,6,5,2>: Cost 3 vext3 RHS, <6,5,2,7>
+ 2714055364U, // <7,6,5,2>: Cost 3 vext3 RHS, <6,5,2,7>
3785806538U, // <7,6,5,3>: Cost 4 vext3 RHS, <6,5,3,4>
1576587206U, // <7,6,5,4>: Cost 2 vext2 <5,4,7,6>, <5,4,7,6>
2650329092U, // <7,6,5,5>: Cost 3 vext2 <5,4,7,6>, <5,5,5,5>
- 2712212200U, // <7,6,5,6>: Cost 3 vext3 RHS, <6,5,6,7>
- 2712064747U, // <7,6,5,7>: Cost 3 vext3 RHS, <6,5,7,1>
+ 2650329186U, // <7,6,5,6>: Cost 3 vext2 <5,4,7,6>, <5,6,7,0>
+ 2712064753U, // <7,6,5,7>: Cost 3 vext3 RHS, <6,5,7,7>
1181963162U, // <7,6,5,u>: Cost 2 vrev <6,7,u,5>
- 2591105126U, // <7,6,6,0>: Cost 3 vext1 <6,7,6,6>, LHS
- 3787797259U, // <7,6,6,1>: Cost 4 vext3 RHS, <6,6,1,6>
- 2712064784U, // <7,6,6,2>: Cost 3 vext3 RHS, <6,6,2,2>
+ 2714055421U, // <7,6,6,0>: Cost 3 vext3 RHS, <6,6,0,1>
+ 2714055432U, // <7,6,6,1>: Cost 3 vext3 RHS, <6,6,1,3>
+ 2650329594U, // <7,6,6,2>: Cost 3 vext2 <5,4,7,6>, <6,2,7,3>
3785806619U, // <7,6,6,3>: Cost 4 vext3 RHS, <6,6,3,4>
2712212260U, // <7,6,6,4>: Cost 3 vext3 RHS, <6,6,4,4>
- 2656965360U, // <7,6,6,5>: Cost 3 vext2 <6,5,7,6>, <6,5,7,6>
+ 2714055472U, // <7,6,6,5>: Cost 3 vext3 RHS, <6,6,5,7>
1638323000U, // <7,6,6,6>: Cost 2 vext3 RHS, <6,6,6,6>
1638470466U, // <7,6,6,7>: Cost 2 vext3 RHS, <6,6,7,7>
1638470475U, // <7,6,6,u>: Cost 2 vext3 RHS, <6,6,u,7>
@@ -5678,24 +5678,24 @@ static const unsigned PerfectShuffleTable[6561+1] = {
2712064865U, // <7,6,7,2>: Cost 3 vext3 RHS, <6,7,2,2>
2712064872U, // <7,6,7,3>: Cost 3 vext3 RHS, <6,7,3,0>
1638323062U, // <7,6,7,4>: Cost 2 vext3 RHS, <6,7,4,5>
- 2712064891U, // <7,6,7,5>: Cost 3 vext3 RHS, <6,7,5,1>
- 2712064901U, // <7,6,7,6>: Cost 3 vext3 RHS, <6,7,6,2>
+ 2712064894U, // <7,6,7,5>: Cost 3 vext3 RHS, <6,7,5,4>
+ 2712064905U, // <7,6,7,6>: Cost 3 vext3 RHS, <6,7,6,6>
2712064915U, // <7,6,7,7>: Cost 3 vext3 RHS, <6,7,7,7>
1638323094U, // <7,6,7,u>: Cost 2 vext3 RHS, <6,7,u,1>
1638470559U, // <7,6,u,0>: Cost 2 vext3 RHS, <6,u,0,1>
1576589102U, // <7,6,u,1>: Cost 2 vext2 <5,4,7,6>, LHS
- 2712064947U, // <7,6,u,2>: Cost 3 vext3 RHS, <6,u,2,3>
+ 2712212402U, // <7,6,u,2>: Cost 3 vext3 RHS, <6,u,2,2>
2712212409U, // <7,6,u,3>: Cost 3 vext3 RHS, <6,u,3,0>
1638470599U, // <7,6,u,4>: Cost 2 vext3 RHS, <6,u,4,5>
1576589466U, // <7,6,u,5>: Cost 2 vext2 <5,4,7,6>, RHS
1638323000U, // <7,6,u,6>: Cost 2 vext3 RHS, <6,6,6,6>
- 1638323168U, // <7,6,u,7>: Cost 2 vext3 RHS, <6,u,7,3>
- 1638323177U, // <7,6,u,u>: Cost 2 vext3 RHS, <6,u,u,3>
+ 1638470624U, // <7,6,u,7>: Cost 2 vext3 RHS, <6,u,7,3>
+ 1638470631U, // <7,6,u,u>: Cost 2 vext3 RHS, <6,u,u,1>
2712065007U, // <7,7,0,0>: Cost 3 vext3 RHS, <7,0,0,0>
1638323194U, // <7,7,0,1>: Cost 2 vext3 RHS, <7,0,1,2>
2712065025U, // <7,7,0,2>: Cost 3 vext3 RHS, <7,0,2,0>
- 3785806859U, // <7,7,0,3>: Cost 4 vext3 RHS, <7,0,3,1>
- 2712212500U, // <7,7,0,4>: Cost 3 vext3 RHS, <7,0,4,1>
+ 3646958337U, // <7,7,0,3>: Cost 4 vext1 <3,7,7,0>, <3,7,7,0>
+ 2712065044U, // <7,7,0,4>: Cost 3 vext3 RHS, <7,0,4,1>
2585161907U, // <7,7,0,5>: Cost 3 vext1 <5,7,7,0>, <5,7,7,0>
2591134604U, // <7,7,0,6>: Cost 3 vext1 <6,7,7,0>, <6,7,7,0>
2591134714U, // <7,7,0,7>: Cost 3 vext1 <6,7,7,0>, <7,0,1,2>
@@ -5703,57 +5703,57 @@ static const unsigned PerfectShuffleTable[6561+1] = {
2712065091U, // <7,7,1,0>: Cost 3 vext3 RHS, <7,1,0,3>
2712065098U, // <7,7,1,1>: Cost 3 vext3 RHS, <7,1,1,1>
2712065109U, // <7,7,1,2>: Cost 3 vext3 RHS, <7,1,2,3>
- 3785806939U, // <7,7,1,3>: Cost 4 vext3 RHS, <7,1,3,0>
- 2712212586U, // <7,7,1,4>: Cost 3 vext3 RHS, <7,1,4,6>
- 2712212592U, // <7,7,1,5>: Cost 3 vext3 RHS, <7,1,5,3>
- 2657633505U, // <7,7,1,6>: Cost 3 vext2 <6,6,7,7>, <1,6,3,7>
+ 2692748384U, // <7,7,1,3>: Cost 3 vext3 <1,3,5,7>, <7,1,3,5>
+ 2585169206U, // <7,7,1,4>: Cost 3 vext1 <5,7,7,1>, RHS
+ 2693928048U, // <7,7,1,5>: Cost 3 vext3 <1,5,3,7>, <7,1,5,3>
+ 2585170766U, // <7,7,1,6>: Cost 3 vext1 <5,7,7,1>, <6,7,0,1>
2735953024U, // <7,7,1,7>: Cost 3 vext3 RHS, <7,1,7,1>
- 2712065163U, // <7,7,1,u>: Cost 3 vext3 RHS, <7,1,u,3>
- 3785806993U, // <7,7,2,0>: Cost 4 vext3 RHS, <7,2,0,0>
+ 2695918731U, // <7,7,1,u>: Cost 3 vext3 <1,u,3,7>, <7,1,u,3>
+ 3770471574U, // <7,7,2,0>: Cost 4 vext3 <2,0,5,7>, <7,2,0,5>
3785807002U, // <7,7,2,1>: Cost 4 vext3 RHS, <7,2,1,0>
2712065189U, // <7,7,2,2>: Cost 3 vext3 RHS, <7,2,2,2>
2712065196U, // <7,7,2,3>: Cost 3 vext3 RHS, <7,2,3,0>
- 3785807029U, // <7,7,2,4>: Cost 4 vext3 RHS, <7,2,4,0>
- 3785807041U, // <7,7,2,5>: Cost 4 vext3 RHS, <7,2,5,3>
- 2712212682U, // <7,7,2,6>: Cost 3 vext3 RHS, <7,2,6,3>
+ 3773125818U, // <7,7,2,4>: Cost 4 vext3 <2,4,5,7>, <7,2,4,5>
+ 3766490305U, // <7,7,2,5>: Cost 4 vext3 <1,3,5,7>, <7,2,5,3>
+ 2700563658U, // <7,7,2,6>: Cost 3 vext3 <2,6,3,7>, <7,2,6,3>
2735953107U, // <7,7,2,7>: Cost 3 vext3 RHS, <7,2,7,3>
- 2712065241U, // <7,7,2,u>: Cost 3 vext3 RHS, <7,2,u,0>
+ 2701890780U, // <7,7,2,u>: Cost 3 vext3 <2,u,3,7>, <7,2,u,3>
2712065251U, // <7,7,3,0>: Cost 3 vext3 RHS, <7,3,0,1>
- 3785807083U, // <7,7,3,1>: Cost 4 vext3 RHS, <7,3,1,0>
- 3785807092U, // <7,7,3,2>: Cost 4 vext3 RHS, <7,3,2,0>
- 2712065280U, // <7,7,3,3>: Cost 3 vext3 RHS, <7,3,3,3>
+ 3766490350U, // <7,7,3,1>: Cost 4 vext3 <1,3,5,7>, <7,3,1,3>
+ 3774305530U, // <7,7,3,2>: Cost 4 vext3 <2,6,3,7>, <7,3,2,6>
+ 2637728196U, // <7,7,3,3>: Cost 3 vext2 <3,3,7,7>, <3,3,7,7>
2712065291U, // <7,7,3,4>: Cost 3 vext3 RHS, <7,3,4,5>
- 2735953168U, // <7,7,3,5>: Cost 3 vext3 RHS, <7,3,5,1>
- 2735953178U, // <7,7,3,6>: Cost 3 vext3 RHS, <7,3,6,2>
+ 2585186486U, // <7,7,3,5>: Cost 3 vext1 <5,7,7,3>, <5,7,7,3>
+ 2639719095U, // <7,7,3,6>: Cost 3 vext2 <3,6,7,7>, <3,6,7,7>
2640382728U, // <7,7,3,7>: Cost 3 vext2 <3,7,7,7>, <3,7,7,7>
- 2712065323U, // <7,7,3,u>: Cost 3 vext3 RHS, <7,3,u,1>
- 2712065336U, // <7,7,4,0>: Cost 3 vext3 RHS, <7,4,0,5>
- 3785807166U, // <7,7,4,1>: Cost 4 vext3 RHS, <7,4,1,2>
- 3785807178U, // <7,7,4,2>: Cost 4 vext3 RHS, <7,4,2,5>
- 3785807187U, // <7,7,4,3>: Cost 4 vext3 RHS, <7,4,3,5>
+ 2641046361U, // <7,7,3,u>: Cost 3 vext2 <3,u,7,7>, <3,u,7,7>
+ 2712212792U, // <7,7,4,0>: Cost 3 vext3 RHS, <7,4,0,5>
+ 3646989312U, // <7,7,4,1>: Cost 4 vext1 <3,7,7,4>, <1,3,5,7>
+ 3785807176U, // <7,7,4,2>: Cost 4 vext3 RHS, <7,4,2,3>
+ 3646991109U, // <7,7,4,3>: Cost 4 vext1 <3,7,7,4>, <3,7,7,4>
2712065371U, // <7,7,4,4>: Cost 3 vext3 RHS, <7,4,4,4>
1638323558U, // <7,7,4,5>: Cost 2 vext3 RHS, <7,4,5,6>
- 2712065385U, // <7,7,4,6>: Cost 3 vext3 RHS, <7,4,6,0>
- 2712212855U, // <7,7,4,7>: Cost 3 vext3 RHS, <7,4,7,5>
+ 2712212845U, // <7,7,4,6>: Cost 3 vext3 RHS, <7,4,6,4>
+ 2591167846U, // <7,7,4,7>: Cost 3 vext1 <6,7,7,4>, <7,4,5,6>
1638323585U, // <7,7,4,u>: Cost 2 vext3 RHS, <7,4,u,6>
2585198694U, // <7,7,5,0>: Cost 3 vext1 <5,7,7,5>, LHS
- 2712065428U, // <7,7,5,1>: Cost 3 vext3 RHS, <7,5,1,7>
- 3785807255U, // <7,7,5,2>: Cost 4 vext3 RHS, <7,5,2,1>
- 3785807264U, // <7,7,5,3>: Cost 4 vext3 RHS, <7,5,3,1>
+ 2712212884U, // <7,7,5,1>: Cost 3 vext3 RHS, <7,5,1,7>
+ 3711471393U, // <7,7,5,2>: Cost 4 vext2 <3,3,7,7>, <5,2,7,3>
+ 2649673590U, // <7,7,5,3>: Cost 3 vext2 <5,3,7,7>, <5,3,7,7>
2712065455U, // <7,7,5,4>: Cost 3 vext3 RHS, <7,5,4,7>
1577259032U, // <7,7,5,5>: Cost 2 vext2 <5,5,7,7>, <5,5,7,7>
2712065473U, // <7,7,5,6>: Cost 3 vext3 RHS, <7,5,6,7>
- 2712212938U, // <7,7,5,7>: Cost 3 vext3 RHS, <7,5,7,7>
- 1577259032U, // <7,7,5,u>: Cost 2 vext2 <5,5,7,7>, <5,5,7,7>
+ 2712212936U, // <7,7,5,7>: Cost 3 vext3 RHS, <7,5,7,5>
+ 1579249931U, // <7,7,5,u>: Cost 2 vext2 <5,u,7,7>, <5,u,7,7>
2591178854U, // <7,7,6,0>: Cost 3 vext1 <6,7,7,6>, LHS
2735953374U, // <7,7,6,1>: Cost 3 vext3 RHS, <7,6,1,0>
- 2712065518U, // <7,7,6,2>: Cost 3 vext3 RHS, <7,6,2,7>
+ 2712212974U, // <7,7,6,2>: Cost 3 vext3 RHS, <7,6,2,7>
2655646287U, // <7,7,6,3>: Cost 3 vext2 <6,3,7,7>, <6,3,7,7>
2591182134U, // <7,7,6,4>: Cost 3 vext1 <6,7,7,6>, RHS
2656973553U, // <7,7,6,5>: Cost 3 vext2 <6,5,7,7>, <6,5,7,7>
1583895362U, // <7,7,6,6>: Cost 2 vext2 <6,6,7,7>, <6,6,7,7>
2712065556U, // <7,7,6,7>: Cost 3 vext3 RHS, <7,6,7,0>
- 1583895362U, // <7,7,6,u>: Cost 2 vext2 <6,6,7,7>, <6,6,7,7>
+ 1585222628U, // <7,7,6,u>: Cost 2 vext2 <6,u,7,7>, <6,u,7,7>
1523417190U, // <7,7,7,0>: Cost 2 vext1 <7,7,7,7>, LHS
2597159670U, // <7,7,7,1>: Cost 3 vext1 <7,7,7,7>, <1,0,3,2>
2597160552U, // <7,7,7,2>: Cost 3 vext1 <7,7,7,7>, <2,2,2,2>
@@ -5765,82 +5765,82 @@ static const unsigned PerfectShuffleTable[6561+1] = {
363253046U, // <7,7,7,u>: Cost 1 vdup3 RHS
1523417190U, // <7,7,u,0>: Cost 2 vext1 <7,7,7,7>, LHS
1638471298U, // <7,7,u,1>: Cost 2 vext3 RHS, <7,u,1,2>
- 2712213129U, // <7,7,u,2>: Cost 3 vext3 RHS, <7,u,2,0>
- 2712065685U, // <7,7,u,3>: Cost 3 vext3 RHS, <7,u,3,3>
+ 2712213132U, // <7,7,u,2>: Cost 3 vext3 RHS, <7,u,2,3>
+ 2712213138U, // <7,7,u,3>: Cost 3 vext3 RHS, <7,u,3,0>
1523420470U, // <7,7,u,4>: Cost 2 vext1 <7,7,7,7>, RHS
1638471338U, // <7,7,u,5>: Cost 2 vext3 RHS, <7,u,5,6>
1595840756U, // <7,7,u,6>: Cost 2 vext2 <u,6,7,7>, <u,6,7,7>
363253046U, // <7,7,u,7>: Cost 1 vdup3 RHS
363253046U, // <7,7,u,u>: Cost 1 vdup3 RHS
1638318080U, // <7,u,0,0>: Cost 2 vext3 RHS, <0,0,0,0>
- 1638323922U, // <7,u,0,1>: Cost 2 vext3 RHS, <u,0,1,1>
- 1638323932U, // <7,u,0,2>: Cost 2 vext3 RHS, <u,0,2,2>
+ 1638323923U, // <7,u,0,1>: Cost 2 vext3 RHS, <u,0,1,2>
+ 1662211804U, // <7,u,0,2>: Cost 2 vext3 RHS, <u,0,2,2>
1638323941U, // <7,u,0,3>: Cost 2 vext3 RHS, <u,0,3,2>
2712065773U, // <7,u,0,4>: Cost 3 vext3 RHS, <u,0,4,1>
- 1638323958U, // <7,u,0,5>: Cost 2 vext3 RHS, <u,0,5,1>
- 1638323968U, // <7,u,0,6>: Cost 2 vext3 RHS, <u,0,6,2>
- 2712065800U, // <7,u,0,7>: Cost 3 vext3 RHS, <u,0,7,1>
- 1638323985U, // <7,u,0,u>: Cost 2 vext3 RHS, <u,0,u,1>
+ 1662359286U, // <7,u,0,5>: Cost 2 vext3 RHS, <u,0,5,1>
+ 1662359296U, // <7,u,0,6>: Cost 2 vext3 RHS, <u,0,6,2>
+ 2987150664U, // <7,u,0,7>: Cost 3 vzipr <5,6,7,0>, RHS
+ 1638323986U, // <7,u,0,u>: Cost 2 vext3 RHS, <u,0,u,2>
1517469798U, // <7,u,1,0>: Cost 2 vext1 <6,7,u,1>, LHS
1638318900U, // <7,u,1,1>: Cost 2 vext3 RHS, <1,1,1,1>
564582190U, // <7,u,1,2>: Cost 1 vext3 RHS, LHS
1638324023U, // <7,u,1,3>: Cost 2 vext3 RHS, <u,1,3,3>
1517473078U, // <7,u,1,4>: Cost 2 vext1 <6,7,u,1>, RHS
- 2712065862U, // <7,u,1,5>: Cost 3 vext3 RHS, <u,1,5,0>
+ 2693928777U, // <7,u,1,5>: Cost 3 vext3 <1,5,3,7>, <u,1,5,3>
1517474710U, // <7,u,1,6>: Cost 2 vext1 <6,7,u,1>, <6,7,u,1>
- 1638324059U, // <7,u,1,7>: Cost 2 vext3 RHS, <u,1,7,3>
+ 1640462171U, // <7,u,1,7>: Cost 2 vext3 RHS, <u,1,7,3>
564582244U, // <7,u,1,u>: Cost 1 vext3 RHS, LHS
- 1638324076U, // <7,u,2,0>: Cost 2 vext3 RHS, <u,2,0,2>
+ 1638318244U, // <7,u,2,0>: Cost 2 vext3 RHS, <0,2,0,2>
2712065907U, // <7,u,2,1>: Cost 3 vext3 RHS, <u,2,1,0>
1638319720U, // <7,u,2,2>: Cost 2 vext3 RHS, <2,2,2,2>
1638324101U, // <7,u,2,3>: Cost 2 vext3 RHS, <u,2,3,0>
- 1638471572U, // <7,u,2,4>: Cost 2 vext3 RHS, <u,2,4,6>
- 2712065945U, // <7,u,2,5>: Cost 3 vext3 RHS, <u,2,5,2>
- 2712065952U, // <7,u,2,6>: Cost 3 vext3 RHS, <u,2,6,0>
- 1638324140U, // <7,u,2,7>: Cost 2 vext3 RHS, <u,2,7,3>
+ 1638318284U, // <7,u,2,4>: Cost 2 vext3 RHS, <0,2,4,6>
+ 2712065947U, // <7,u,2,5>: Cost 3 vext3 RHS, <u,2,5,4>
+ 2700564387U, // <7,u,2,6>: Cost 3 vext3 <2,6,3,7>, <u,2,6,3>
+ 1640314796U, // <7,u,2,7>: Cost 2 vext3 RHS, <u,2,7,3>
1638324146U, // <7,u,2,u>: Cost 2 vext3 RHS, <u,2,u,0>
1638324156U, // <7,u,3,0>: Cost 2 vext3 RHS, <u,3,0,1>
- 2712065988U, // <7,u,3,1>: Cost 3 vext3 RHS, <u,3,1,0>
- 2712065998U, // <7,u,3,2>: Cost 3 vext3 RHS, <u,3,2,1>
+ 1638319064U, // <7,u,3,1>: Cost 2 vext3 RHS, <1,3,1,3>
+ 2700564435U, // <7,u,3,2>: Cost 3 vext3 <2,6,3,7>, <u,3,2,6>
1638320540U, // <7,u,3,3>: Cost 2 vext3 RHS, <3,3,3,3>
1638324196U, // <7,u,3,4>: Cost 2 vext3 RHS, <u,3,4,5>
- 2712066025U, // <7,u,3,5>: Cost 3 vext3 RHS, <u,3,5,1>
- 2712066035U, // <7,u,3,6>: Cost 3 vext3 RHS, <u,3,6,2>
- 2712066042U, // <7,u,3,7>: Cost 3 vext3 RHS, <u,3,7,0>
+ 1638324207U, // <7,u,3,5>: Cost 2 vext3 RHS, <u,3,5,7>
+ 2700564472U, // <7,u,3,6>: Cost 3 vext3 <2,6,3,7>, <u,3,6,7>
+ 2695919610U, // <7,u,3,7>: Cost 3 vext3 <1,u,3,7>, <u,3,7,0>
1638324228U, // <7,u,3,u>: Cost 2 vext3 RHS, <u,3,u,1>
2712066061U, // <7,u,4,0>: Cost 3 vext3 RHS, <u,4,0,1>
- 1638471706U, // <7,u,4,1>: Cost 2 vext3 RHS, <u,4,1,5>
- 1638471716U, // <7,u,4,2>: Cost 2 vext3 RHS, <u,4,2,6>
+ 1662212122U, // <7,u,4,1>: Cost 2 vext3 RHS, <u,4,1,5>
+ 1662212132U, // <7,u,4,2>: Cost 2 vext3 RHS, <u,4,2,6>
2712066092U, // <7,u,4,3>: Cost 3 vext3 RHS, <u,4,3,5>
1638321360U, // <7,u,4,4>: Cost 2 vext3 RHS, <4,4,4,4>
1638324287U, // <7,u,4,5>: Cost 2 vext3 RHS, <u,4,5,6>
- 1638471752U, // <7,u,4,6>: Cost 2 vext3 RHS, <u,4,6,6>
+ 1662359624U, // <7,u,4,6>: Cost 2 vext3 RHS, <u,4,6,6>
1640314961U, // <7,u,4,7>: Cost 2 vext3 RHS, <u,4,7,6>
1638324314U, // <7,u,4,u>: Cost 2 vext3 RHS, <u,4,u,6>
1517502566U, // <7,u,5,0>: Cost 2 vext1 <6,7,u,5>, LHS
1574612693U, // <7,u,5,1>: Cost 2 vext2 <5,1,7,u>, <5,1,7,u>
2712066162U, // <7,u,5,2>: Cost 3 vext3 RHS, <u,5,2,3>
- 1638471807U, // <7,u,5,3>: Cost 2 vext3 RHS, <u,5,3,7>
+ 1638324351U, // <7,u,5,3>: Cost 2 vext3 RHS, <u,5,3,7>
1576603592U, // <7,u,5,4>: Cost 2 vext2 <5,4,7,u>, <5,4,7,u>
1577267225U, // <7,u,5,5>: Cost 2 vext2 <5,5,7,u>, <5,5,7,u>
564582554U, // <7,u,5,6>: Cost 1 vext3 RHS, RHS
- 1638471843U, // <7,u,5,7>: Cost 2 vext3 RHS, <u,5,7,7>
+ 1640462499U, // <7,u,5,7>: Cost 2 vext3 RHS, <u,5,7,7>
564582572U, // <7,u,5,u>: Cost 1 vext3 RHS, RHS
- 1638324400U, // <7,u,6,0>: Cost 2 vext3 RHS, <u,6,0,2>
- 2712066232U, // <7,u,6,1>: Cost 3 vext3 RHS, <u,6,1,1>
+ 2712066223U, // <7,u,6,0>: Cost 3 vext3 RHS, <u,6,0,1>
+ 2712066238U, // <7,u,6,1>: Cost 3 vext3 RHS, <u,6,1,7>
1581249023U, // <7,u,6,2>: Cost 2 vext2 <6,2,7,u>, <6,2,7,u>
- 1638471888U, // <7,u,6,3>: Cost 2 vext3 RHS, <u,6,3,7>
- 1638471896U, // <7,u,6,4>: Cost 2 vext3 RHS, <u,6,4,6>
- 2712213730U, // <7,u,6,5>: Cost 3 vext3 RHS, <u,6,5,7>
+ 1638324432U, // <7,u,6,3>: Cost 2 vext3 RHS, <u,6,3,7>
+ 1638468980U, // <7,u,6,4>: Cost 2 vext3 RHS, <4,6,4,6>
+ 2712066274U, // <7,u,6,5>: Cost 3 vext3 RHS, <u,6,5,7>
1583903555U, // <7,u,6,6>: Cost 2 vext2 <6,6,7,u>, <6,6,7,u>
- 1638471924U, // <7,u,6,7>: Cost 2 vext3 RHS, <u,6,7,7>
- 1640462582U, // <7,u,6,u>: Cost 2 vext3 RHS, <u,6,u,0>
+ 1640315117U, // <7,u,6,7>: Cost 2 vext3 RHS, <u,6,7,0>
+ 1638324477U, // <7,u,6,u>: Cost 2 vext3 RHS, <u,6,u,7>
1638471936U, // <7,u,7,0>: Cost 2 vext3 RHS, <u,7,0,1>
- 2712213768U, // <7,u,7,1>: Cost 3 vext3 RHS, <u,7,1,0>
- 2712213779U, // <7,u,7,2>: Cost 3 vext3 RHS, <u,7,2,2>
- 2712213786U, // <7,u,7,3>: Cost 3 vext3 RHS, <u,7,3,0>
+ 2692970763U, // <7,u,7,1>: Cost 3 vext3 <1,3,u,7>, <u,7,1,3>
+ 2700933399U, // <7,u,7,2>: Cost 3 vext3 <2,6,u,7>, <u,7,2,6>
+ 2573347601U, // <7,u,7,3>: Cost 3 vext1 <3,7,u,7>, <3,7,u,7>
1638471976U, // <7,u,7,4>: Cost 2 vext3 RHS, <u,7,4,5>
- 2712213805U, // <7,u,7,5>: Cost 3 vext3 RHS, <u,7,5,1>
+ 1511551171U, // <7,u,7,5>: Cost 2 vext1 <5,7,u,7>, <5,7,u,7>
2712213815U, // <7,u,7,6>: Cost 3 vext3 RHS, <u,7,6,2>
363253046U, // <7,u,7,7>: Cost 1 vdup3 RHS
363253046U, // <7,u,7,u>: Cost 1 vdup3 RHS
@@ -5858,361 +5858,361 @@ static const unsigned PerfectShuffleTable[6561+1] = {
1611489300U, // <u,0,0,2>: Cost 2 vext3 LHS, <0,0,2,2>
2568054923U, // <u,0,0,3>: Cost 3 vext1 <3,0,0,0>, <3,0,0,0>
1481706806U, // <u,0,0,4>: Cost 2 vext1 <0,u,0,0>, RHS
- 2621153757U, // <u,0,0,5>: Cost 3 vext2 <0,5,u,0>, <0,5,u,0>
+ 2555449040U, // <u,0,0,5>: Cost 3 vext1 <0,u,0,0>, <5,1,7,3>
2591282078U, // <u,0,0,6>: Cost 3 vext1 <6,u,0,0>, <6,u,0,0>
2591945711U, // <u,0,0,7>: Cost 3 vext1 <7,0,0,0>, <7,0,0,0>
135053414U, // <u,0,0,u>: Cost 1 vdup0 LHS
1493655654U, // <u,0,1,0>: Cost 2 vext1 <2,u,0,1>, LHS
- 1879889710U, // <u,0,1,1>: Cost 2 vzipr LHS, LHS
+ 1860550758U, // <u,0,1,1>: Cost 2 vzipl LHS, LHS
537747563U, // <u,0,1,2>: Cost 1 vext3 LHS, LHS
- 2625799188U, // <u,0,1,3>: Cost 3 vext2 <1,3,u,0>, <1,3,u,0>
+ 2625135576U, // <u,0,1,3>: Cost 3 vext2 <1,2,u,0>, <1,3,1,3>
1493658934U, // <u,0,1,4>: Cost 2 vext1 <2,u,0,1>, RHS
- 2567401168U, // <u,0,1,5>: Cost 3 vext1 <2,u,0,1>, <5,1,7,3>
+ 2625135760U, // <u,0,1,5>: Cost 3 vext2 <1,2,u,0>, <1,5,3,7>
1517548447U, // <u,0,1,6>: Cost 2 vext1 <6,u,0,1>, <6,u,0,1>
2591290362U, // <u,0,1,7>: Cost 3 vext1 <6,u,0,1>, <7,0,1,2>
537747612U, // <u,0,1,u>: Cost 1 vext3 LHS, LHS
1611489444U, // <u,0,2,0>: Cost 2 vext3 LHS, <0,2,0,2>
- 2953631596U, // <u,0,2,1>: Cost 3 vzipr LHS, <u,2,0,2>
- 2014107438U, // <u,0,2,2>: Cost 2 vtrnr LHS, LHS
- 2555463830U, // <u,0,2,3>: Cost 3 vext1 <0,u,0,2>, <3,0,1,2>
- 1481723190U, // <u,0,2,4>: Cost 2 vext1 <0,u,0,2>, RHS
- 2555465424U, // <u,0,2,5>: Cost 3 vext1 <0,u,0,2>, <5,1,7,3>
- 2555466234U, // <u,0,2,6>: Cost 3 vext1 <0,u,0,2>, <6,2,7,3>
- 2579354618U, // <u,0,2,7>: Cost 3 vext1 <4,u,0,2>, <7,0,1,2>
- 2014549806U, // <u,0,2,u>: Cost 2 vtrnr LHS, LHS
- 2555469824U, // <u,0,3,0>: Cost 3 vext1 <0,u,0,3>, <0,0,0,0>
- 2954074044U, // <u,0,3,1>: Cost 3 vzipr LHS, <u,3,0,1>
+ 2685231276U, // <u,0,2,1>: Cost 3 vext3 LHS, <0,2,1,1>
+ 1994768486U, // <u,0,2,2>: Cost 2 vtrnl LHS, LHS
+ 2685231294U, // <u,0,2,3>: Cost 3 vext3 LHS, <0,2,3,1>
+ 1611489484U, // <u,0,2,4>: Cost 2 vext3 LHS, <0,2,4,6>
+ 2712068310U, // <u,0,2,5>: Cost 3 vext3 RHS, <0,2,5,7>
+ 2625136570U, // <u,0,2,6>: Cost 3 vext2 <1,2,u,0>, <2,6,3,7>
+ 2591962097U, // <u,0,2,7>: Cost 3 vext1 <7,0,0,2>, <7,0,0,2>
+ 1611489516U, // <u,0,2,u>: Cost 2 vext3 LHS, <0,2,u,2>
+ 2954067968U, // <u,0,3,0>: Cost 3 vzipr LHS, <0,0,0,0>
+ 2685231356U, // <u,0,3,1>: Cost 3 vext3 LHS, <0,3,1,0>
72589981U, // <u,0,3,2>: Cost 1 vrev LHS
2625137052U, // <u,0,3,3>: Cost 3 vext2 <1,2,u,0>, <3,3,3,3>
- 2555473206U, // <u,0,3,4>: Cost 3 vext1 <0,u,0,3>, RHS
- 2651679326U, // <u,0,3,5>: Cost 3 vext2 <5,6,u,0>, <3,5,6,u>
+ 2625137154U, // <u,0,3,4>: Cost 3 vext2 <1,2,u,0>, <3,4,5,6>
+ 2639071848U, // <u,0,3,5>: Cost 3 vext2 <3,5,u,0>, <3,5,u,0>
2639735481U, // <u,0,3,6>: Cost 3 vext2 <3,6,u,0>, <3,6,u,0>
2597279354U, // <u,0,3,7>: Cost 3 vext1 <7,u,0,3>, <7,u,0,3>
73032403U, // <u,0,3,u>: Cost 1 vrev LHS
- 2625137554U, // <u,0,4,0>: Cost 3 vext2 <1,2,u,0>, <4,0,5,1>
- 1638326610U, // <u,0,4,1>: Cost 2 vext3 RHS, <0,4,1,5>
- 1638326620U, // <u,0,4,2>: Cost 2 vext3 RHS, <0,4,2,6>
- 3293897383U, // <u,0,4,3>: Cost 4 vrev <0,u,3,4>
- 2567425334U, // <u,0,4,4>: Cost 3 vext1 <2,u,0,4>, RHS
+ 2687074636U, // <u,0,4,0>: Cost 3 vext3 <0,4,0,u>, <0,4,0,u>
+ 1611489618U, // <u,0,4,1>: Cost 2 vext3 LHS, <0,4,1,5>
+ 1611489628U, // <u,0,4,2>: Cost 2 vext3 LHS, <0,4,2,6>
+ 3629222038U, // <u,0,4,3>: Cost 4 vext1 <0,u,0,4>, <3,0,1,2>
+ 2555481398U, // <u,0,4,4>: Cost 3 vext1 <0,u,0,4>, RHS
1551396150U, // <u,0,4,5>: Cost 2 vext2 <1,2,u,0>, RHS
- 2625137996U, // <u,0,4,6>: Cost 3 vext2 <1,2,u,0>, <4,6,0,2>
- 2646371811U, // <u,0,4,7>: Cost 3 vext2 <4,7,u,0>, <4,7,u,0>
- 1551396393U, // <u,0,4,u>: Cost 2 vext2 <1,2,u,0>, RHS
- 2573402214U, // <u,0,5,0>: Cost 3 vext1 <3,u,0,5>, LHS
- 1879890074U, // <u,0,5,1>: Cost 2 vzipr LHS, RHS
- 3087849206U, // <u,0,5,2>: Cost 3 vtrnr LHS, <u,0,5,1>
- 2573404952U, // <u,0,5,3>: Cost 3 vext1 <3,u,0,5>, <3,u,0,5>
+ 2651680116U, // <u,0,4,6>: Cost 3 vext2 <5,6,u,0>, <4,6,4,6>
+ 2646150600U, // <u,0,4,7>: Cost 3 vext2 <4,7,5,0>, <4,7,5,0>
+ 1611932050U, // <u,0,4,u>: Cost 2 vext3 LHS, <0,4,u,6>
+ 2561458278U, // <u,0,5,0>: Cost 3 vext1 <1,u,0,5>, LHS
+ 1863532646U, // <u,0,5,1>: Cost 2 vzipl RHS, LHS
+ 2712068526U, // <u,0,5,2>: Cost 3 vext3 RHS, <0,5,2,7>
+ 2649689976U, // <u,0,5,3>: Cost 3 vext2 <5,3,u,0>, <5,3,u,0>
2220237489U, // <u,0,5,4>: Cost 3 vrev <0,u,4,5>
2651680772U, // <u,0,5,5>: Cost 3 vext2 <5,6,u,0>, <5,5,5,5>
1577939051U, // <u,0,5,6>: Cost 2 vext2 <5,6,u,0>, <5,6,u,0>
- 2652344508U, // <u,0,5,7>: Cost 3 vext2 <5,7,u,0>, <5,7,u,0>
- 1884534938U, // <u,0,5,u>: Cost 2 vzipr LHS, RHS
- 3088357530U, // <u,0,6,0>: Cost 3 vtrnr <0,2,0,2>, RHS
- 2953631920U, // <u,0,6,1>: Cost 3 vzipr LHS, <u,6,0,2>
- 2014107802U, // <u,0,6,2>: Cost 2 vtrnr LHS, RHS
- 2573413145U, // <u,0,6,3>: Cost 3 vext1 <3,u,0,6>, <3,u,0,6>
- 2573413686U, // <u,0,6,4>: Cost 3 vext1 <3,u,0,6>, RHS
+ 2830077238U, // <u,0,5,7>: Cost 3 vuzpr <1,u,3,0>, RHS
+ 1579266317U, // <u,0,5,u>: Cost 2 vext2 <5,u,u,0>, <5,u,u,0>
+ 2555494502U, // <u,0,6,0>: Cost 3 vext1 <0,u,0,6>, LHS
+ 2712068598U, // <u,0,6,1>: Cost 3 vext3 RHS, <0,6,1,7>
+ 1997750374U, // <u,0,6,2>: Cost 2 vtrnl RHS, LHS
+ 2655662673U, // <u,0,6,3>: Cost 3 vext2 <6,3,u,0>, <6,3,u,0>
+ 2555497782U, // <u,0,6,4>: Cost 3 vext1 <0,u,0,6>, RHS
2651681459U, // <u,0,6,5>: Cost 3 vext2 <5,6,u,0>, <6,5,0,u>
2651681592U, // <u,0,6,6>: Cost 3 vext2 <5,6,u,0>, <6,6,6,6>
2651681614U, // <u,0,6,7>: Cost 3 vext2 <5,6,u,0>, <6,7,0,1>
- 2014550170U, // <u,0,6,u>: Cost 2 vtrnr LHS, RHS
- 2651681786U, // <u,0,7,0>: Cost 3 vext2 <5,6,u,0>, <7,0,1,2>
- 2899627336U, // <u,0,7,1>: Cost 3 vzipl <2,3,0,1>, RHS
- 3087849307U, // <u,0,7,2>: Cost 3 vtrnr LHS, <u,1,7,3>
- 3960778056U, // <u,0,7,3>: Cost 4 vzipl <0,2,0,3>, RHS
- 2651682150U, // <u,0,7,4>: Cost 3 vext2 <5,6,u,0>, <7,4,5,6>
+ 1997750428U, // <u,0,6,u>: Cost 2 vtrnl RHS, LHS
+ 2567446630U, // <u,0,7,0>: Cost 3 vext1 <2,u,0,7>, LHS
+ 2567447446U, // <u,0,7,1>: Cost 3 vext1 <2,u,0,7>, <1,2,3,0>
+ 2567448641U, // <u,0,7,2>: Cost 3 vext1 <2,u,0,7>, <2,u,0,7>
+ 2573421338U, // <u,0,7,3>: Cost 3 vext1 <3,u,0,7>, <3,u,0,7>
+ 2567449910U, // <u,0,7,4>: Cost 3 vext1 <2,u,0,7>, RHS
2651682242U, // <u,0,7,5>: Cost 3 vext2 <5,6,u,0>, <7,5,6,u>
2591339429U, // <u,0,7,6>: Cost 3 vext1 <6,u,0,7>, <6,u,0,7>
2651682412U, // <u,0,7,7>: Cost 3 vext2 <5,6,u,0>, <7,7,7,7>
- 3088291675U, // <u,0,7,u>: Cost 3 vtrnr LHS, <u,1,7,3>
+ 2567452462U, // <u,0,7,u>: Cost 3 vext1 <2,u,0,7>, LHS
135053414U, // <u,0,u,0>: Cost 1 vdup0 LHS
- 1879890277U, // <u,0,u,1>: Cost 2 vzipr LHS, LHS
+ 1611489938U, // <u,0,u,1>: Cost 2 vext3 LHS, <0,u,1,1>
537748125U, // <u,0,u,2>: Cost 1 vext3 LHS, LHS
- 2555512982U, // <u,0,u,3>: Cost 3 vext1 <0,u,0,u>, <3,0,1,2>
- 1481772342U, // <u,0,u,4>: Cost 2 vext1 <0,u,0,u>, RHS
+ 2685674148U, // <u,0,u,3>: Cost 3 vext3 LHS, <0,u,3,1>
+ 1611932338U, // <u,0,u,4>: Cost 2 vext3 LHS, <0,u,4,6>
1551399066U, // <u,0,u,5>: Cost 2 vext2 <1,2,u,0>, RHS
1517605798U, // <u,0,u,6>: Cost 2 vext1 <6,u,0,u>, <6,u,0,u>
- 2579403770U, // <u,0,u,7>: Cost 3 vext1 <4,u,0,u>, <7,0,1,2>
+ 2830077481U, // <u,0,u,7>: Cost 3 vuzpr <1,u,3,0>, RHS
537748179U, // <u,0,u,u>: Cost 1 vext3 LHS, LHS
1544101961U, // <u,1,0,0>: Cost 2 vext2 <0,0,u,1>, <0,0,u,1>
1558036582U, // <u,1,0,1>: Cost 2 vext2 <2,3,u,1>, LHS
- 2685231852U, // <u,1,0,2>: Cost 3 vext3 LHS, <1,0,2,1>
+ 2619171051U, // <u,1,0,2>: Cost 3 vext2 <0,2,u,1>, <0,2,u,1>
1611490038U, // <u,1,0,3>: Cost 2 vext3 LHS, <1,0,3,2>
- 2567466294U, // <u,1,0,4>: Cost 3 vext1 <2,u,1,0>, RHS
- 2641510814U, // <u,1,0,5>: Cost 3 vext2 <4,0,5,1>, <0,5,1,0>
+ 2555522358U, // <u,1,0,4>: Cost 3 vext1 <0,u,1,0>, RHS
+ 2712068871U, // <u,1,0,5>: Cost 3 vext3 RHS, <1,0,5,1>
2591355815U, // <u,1,0,6>: Cost 3 vext1 <6,u,1,0>, <6,u,1,0>
2597328512U, // <u,1,0,7>: Cost 3 vext1 <7,u,1,0>, <7,u,1,0>
1611490083U, // <u,1,0,u>: Cost 2 vext3 LHS, <1,0,u,2>
- 1524252774U, // <u,1,1,0>: Cost 2 vext1 <u,0,1,1>, LHS
+ 1481785446U, // <u,1,1,0>: Cost 2 vext1 <0,u,1,1>, LHS
202162278U, // <u,1,1,1>: Cost 1 vdup1 LHS
- 2960316206U, // <u,1,1,2>: Cost 3 vzipr <1,2,3,0>, LHS
+ 2555528808U, // <u,1,1,2>: Cost 3 vext1 <0,u,1,1>, <2,2,2,2>
1611490120U, // <u,1,1,3>: Cost 2 vext3 LHS, <1,1,3,3>
- 1524256054U, // <u,1,1,4>: Cost 2 vext1 <u,0,1,1>, RHS
- 2658321552U, // <u,1,1,5>: Cost 3 vext2 <6,7,u,1>, <1,5,3,7>
+ 1481788726U, // <u,1,1,4>: Cost 2 vext1 <0,u,1,1>, RHS
+ 2689876828U, // <u,1,1,5>: Cost 3 vext3 LHS, <1,1,5,5>
2591364008U, // <u,1,1,6>: Cost 3 vext1 <6,u,1,1>, <6,u,1,1>
- 2597999610U, // <u,1,1,7>: Cost 3 vext1 <u,0,1,1>, <7,0,1,2>
+ 2592691274U, // <u,1,1,7>: Cost 3 vext1 <7,1,1,1>, <7,1,1,1>
202162278U, // <u,1,1,u>: Cost 1 vdup1 LHS
1499709542U, // <u,1,2,0>: Cost 2 vext1 <3,u,1,2>, LHS
- 2685232007U, // <u,1,2,1>: Cost 3 vext3 LHS, <1,2,1,3>
- 2685232016U, // <u,1,2,2>: Cost 3 vext3 LHS, <1,2,2,3>
+ 2689876871U, // <u,1,2,1>: Cost 3 vext3 LHS, <1,2,1,3>
+ 2631116445U, // <u,1,2,2>: Cost 3 vext2 <2,2,u,1>, <2,2,u,1>
835584U, // <u,1,2,3>: Cost 0 copy LHS
1499712822U, // <u,1,2,4>: Cost 2 vext1 <3,u,1,2>, RHS
- 2573455056U, // <u,1,2,5>: Cost 3 vext1 <3,u,1,2>, <5,1,7,3>
- 2573455866U, // <u,1,2,6>: Cost 3 vext1 <3,u,1,2>, <6,2,7,3>
+ 2689876907U, // <u,1,2,5>: Cost 3 vext3 LHS, <1,2,5,3>
+ 2631780282U, // <u,1,2,6>: Cost 3 vext2 <2,3,u,1>, <2,6,3,7>
1523603074U, // <u,1,2,7>: Cost 2 vext1 <7,u,1,2>, <7,u,1,2>
835584U, // <u,1,2,u>: Cost 0 copy LHS
- 2685232078U, // <u,1,3,0>: Cost 3 vext3 LHS, <1,3,0,2>
- 2892398748U, // <u,1,3,1>: Cost 3 vzipl <1,1,1,1>, LHS
- 2555545254U, // <u,1,3,2>: Cost 3 vext1 <0,u,1,3>, <2,3,0,1>
- 1946993309U, // <u,1,3,3>: Cost 2 vtrnl LHS, LHS
- 2555546934U, // <u,1,3,4>: Cost 3 vext1 <0,u,1,3>, RHS
- 2585407697U, // <u,1,3,5>: Cost 3 vext1 <5,u,1,3>, <5,u,1,3>
- 2658323128U, // <u,1,3,6>: Cost 3 vext2 <6,7,u,1>, <3,6,7,u>
- 2597353091U, // <u,1,3,7>: Cost 3 vext1 <7,u,1,3>, <7,u,1,3>
- 1947034269U, // <u,1,3,u>: Cost 2 vtrnl LHS, LHS
+ 1487773798U, // <u,1,3,0>: Cost 2 vext1 <1,u,1,3>, LHS
+ 1611490264U, // <u,1,3,1>: Cost 2 vext3 LHS, <1,3,1,3>
+ 2685232094U, // <u,1,3,2>: Cost 3 vext3 LHS, <1,3,2,0>
+ 2018746470U, // <u,1,3,3>: Cost 2 vtrnr LHS, LHS
+ 1487777078U, // <u,1,3,4>: Cost 2 vext1 <1,u,1,3>, RHS
+ 1611490304U, // <u,1,3,5>: Cost 2 vext3 LHS, <1,3,5,7>
+ 2685674505U, // <u,1,3,6>: Cost 3 vext3 LHS, <1,3,6,7>
+ 2640407307U, // <u,1,3,7>: Cost 3 vext2 <3,7,u,1>, <3,7,u,1>
+ 1611490327U, // <u,1,3,u>: Cost 2 vext3 LHS, <1,3,u,3>
1567992749U, // <u,1,4,0>: Cost 2 vext2 <4,0,u,1>, <4,0,u,1>
- 2642398206U, // <u,1,4,1>: Cost 3 vext2 <4,1,u,1>, <4,1,u,1>
- 2573469422U, // <u,1,4,2>: Cost 3 vext1 <3,u,1,4>, <2,3,u,1>
+ 2693121070U, // <u,1,4,1>: Cost 3 vext3 <1,4,1,u>, <1,4,1,u>
+ 2693194807U, // <u,1,4,2>: Cost 3 vext3 <1,4,2,u>, <1,4,2,u>
1152386432U, // <u,1,4,3>: Cost 2 vrev <1,u,3,4>
- 2573471030U, // <u,1,4,4>: Cost 3 vext1 <3,u,1,4>, RHS
+ 2555555126U, // <u,1,4,4>: Cost 3 vext1 <0,u,1,4>, RHS
1558039862U, // <u,1,4,5>: Cost 2 vext2 <2,3,u,1>, RHS
- 2631781708U, // <u,1,4,6>: Cost 3 vext2 <2,3,u,1>, <4,6,0,2>
+ 2645716371U, // <u,1,4,6>: Cost 3 vext2 <4,6,u,1>, <4,6,u,1>
2597361284U, // <u,1,4,7>: Cost 3 vext1 <7,u,1,4>, <7,u,1,4>
1152755117U, // <u,1,4,u>: Cost 2 vrev <1,u,u,4>
- 1526939750U, // <u,1,5,0>: Cost 2 vext1 <u,4,1,5>, LHS
- 2959513754U, // <u,1,5,1>: Cost 3 vzipr <1,1,1,1>, RHS
- 2960316570U, // <u,1,5,2>: Cost 3 vzipr <1,2,3,0>, RHS
- 1638327440U, // <u,1,5,3>: Cost 2 vext3 RHS, <1,5,3,7>
- 1526943030U, // <u,1,5,4>: Cost 2 vext1 <u,4,1,5>, RHS
+ 1481818214U, // <u,1,5,0>: Cost 2 vext1 <0,u,1,5>, LHS
+ 2555560694U, // <u,1,5,1>: Cost 3 vext1 <0,u,1,5>, <1,0,3,2>
+ 2555561576U, // <u,1,5,2>: Cost 3 vext1 <0,u,1,5>, <2,2,2,2>
+ 1611490448U, // <u,1,5,3>: Cost 2 vext3 LHS, <1,5,3,7>
+ 1481821494U, // <u,1,5,4>: Cost 2 vext1 <0,u,1,5>, RHS
2651025435U, // <u,1,5,5>: Cost 3 vext2 <5,5,u,1>, <5,5,u,1>
2651689068U, // <u,1,5,6>: Cost 3 vext2 <5,6,u,1>, <5,6,u,1>
- 2600686586U, // <u,1,5,7>: Cost 3 vext1 <u,4,1,5>, <7,0,1,2>
- 1638327485U, // <u,1,5,u>: Cost 2 vext3 RHS, <1,5,u,7>
- 2653679967U, // <u,1,6,0>: Cost 3 vext2 <6,0,u,1>, <6,0,u,1>
- 3093731482U, // <u,1,6,1>: Cost 3 vtrnr <1,1,1,1>, RHS
- 2631782906U, // <u,1,6,2>: Cost 3 vext2 <2,3,u,1>, <6,2,7,3>
- 3020737350U, // <u,1,6,3>: Cost 3 vtrnl LHS, <3,u,5,6>
- 2597375286U, // <u,1,6,4>: Cost 3 vext1 <7,u,1,6>, RHS
- 2226292116U, // <u,1,6,5>: Cost 3 vrev <1,u,5,6>
+ 2823966006U, // <u,1,5,7>: Cost 3 vuzpr <0,u,1,1>, RHS
+ 1611932861U, // <u,1,5,u>: Cost 2 vext3 LHS, <1,5,u,7>
+ 2555568230U, // <u,1,6,0>: Cost 3 vext1 <0,u,1,6>, LHS
+ 2689877199U, // <u,1,6,1>: Cost 3 vext3 LHS, <1,6,1,7>
+ 2712069336U, // <u,1,6,2>: Cost 3 vext3 RHS, <1,6,2,7>
+ 2685232353U, // <u,1,6,3>: Cost 3 vext3 LHS, <1,6,3,7>
+ 2555571510U, // <u,1,6,4>: Cost 3 vext1 <0,u,1,6>, RHS
+ 2689877235U, // <u,1,6,5>: Cost 3 vext3 LHS, <1,6,5,7>
2657661765U, // <u,1,6,6>: Cost 3 vext2 <6,6,u,1>, <6,6,u,1>
1584583574U, // <u,1,6,7>: Cost 2 vext2 <6,7,u,1>, <6,7,u,1>
1585247207U, // <u,1,6,u>: Cost 2 vext2 <6,u,u,1>, <6,u,u,1>
- 2573492326U, // <u,1,7,0>: Cost 3 vext1 <3,u,1,7>, LHS
- 2892401992U, // <u,1,7,1>: Cost 3 vzipl <1,1,1,1>, RHS
- 2903690568U, // <u,1,7,2>: Cost 3 vzipl <3,0,1,2>, RHS
- 1946996265U, // <u,1,7,3>: Cost 2 vtrnl LHS, RHS
- 2573495606U, // <u,1,7,4>: Cost 3 vext1 <3,u,1,7>, RHS
- 2936229192U, // <u,1,7,5>: Cost 3 vzipl <u,4,1,5>, RHS
+ 2561548390U, // <u,1,7,0>: Cost 3 vext1 <1,u,1,7>, LHS
+ 2561549681U, // <u,1,7,1>: Cost 3 vext1 <1,u,1,7>, <1,u,1,7>
+ 2573493926U, // <u,1,7,2>: Cost 3 vext1 <3,u,1,7>, <2,3,0,1>
+ 2042962022U, // <u,1,7,3>: Cost 2 vtrnr RHS, LHS
+ 2561551670U, // <u,1,7,4>: Cost 3 vext1 <1,u,1,7>, RHS
+ 2226300309U, // <u,1,7,5>: Cost 3 vrev <1,u,5,7>
2658325990U, // <u,1,7,6>: Cost 3 vext2 <6,7,u,1>, <7,6,1,u>
2658326124U, // <u,1,7,7>: Cost 3 vext2 <6,7,u,1>, <7,7,7,7>
- 1947037225U, // <u,1,7,u>: Cost 2 vtrnl LHS, RHS
- 1499758694U, // <u,1,u,0>: Cost 2 vext1 <3,u,1,u>, LHS
+ 2042962027U, // <u,1,7,u>: Cost 2 vtrnr RHS, LHS
+ 1481842790U, // <u,1,u,0>: Cost 2 vext1 <0,u,1,u>, LHS
202162278U, // <u,1,u,1>: Cost 1 vdup1 LHS
- 2685674870U, // <u,1,u,2>: Cost 3 vext3 LHS, <1,u,2,3>
+ 2685674867U, // <u,1,u,2>: Cost 3 vext3 LHS, <1,u,2,0>
835584U, // <u,1,u,3>: Cost 0 copy LHS
- 1499761974U, // <u,1,u,4>: Cost 2 vext1 <3,u,1,u>, RHS
- 1558042778U, // <u,1,u,5>: Cost 2 vext2 <2,3,u,1>, RHS
- 2631784624U, // <u,1,u,6>: Cost 3 vext2 <2,3,u,1>, <u,6,0,2>
+ 1481846070U, // <u,1,u,4>: Cost 2 vext1 <0,u,1,u>, RHS
+ 1611933077U, // <u,1,u,5>: Cost 2 vext3 LHS, <1,u,5,7>
+ 2685674910U, // <u,1,u,6>: Cost 3 vext3 LHS, <1,u,6,7>
1523652232U, // <u,1,u,7>: Cost 2 vext1 <7,u,1,u>, <7,u,1,u>
835584U, // <u,1,u,u>: Cost 0 copy LHS
1544110154U, // <u,2,0,0>: Cost 2 vext2 <0,0,u,2>, <0,0,u,2>
- 1550082150U, // <u,2,0,1>: Cost 2 vext2 <1,0,u,2>, LHS
- 1745671982U, // <u,2,0,2>: Cost 2 vuzpr LHS, LHS
- 2685232590U, // <u,2,0,3>: Cost 3 vext3 LHS, <2,0,3,1>
- 2685232600U, // <u,2,0,4>: Cost 3 vext3 LHS, <2,0,4,2>
- 2617409966U, // <u,2,0,5>: Cost 3 vext2 <0,0,2,2>, <0,5,2,7>
- 2586120488U, // <u,2,0,6>: Cost 3 vext1 <6,0,2,0>, <6,0,2,0>
+ 1545437286U, // <u,2,0,1>: Cost 2 vext2 <0,2,u,2>, LHS
+ 1545437420U, // <u,2,0,2>: Cost 2 vext2 <0,2,u,2>, <0,2,u,2>
+ 2685232589U, // <u,2,0,3>: Cost 3 vext3 LHS, <2,0,3,0>
+ 2619179346U, // <u,2,0,4>: Cost 3 vext2 <0,2,u,2>, <0,4,1,5>
+ 2712069606U, // <u,2,0,5>: Cost 3 vext3 RHS, <2,0,5,7>
+ 2689877484U, // <u,2,0,6>: Cost 3 vext3 LHS, <2,0,6,4>
2659656273U, // <u,2,0,7>: Cost 3 vext2 <7,0,u,2>, <0,7,2,u>
- 1746114350U, // <u,2,0,u>: Cost 2 vuzpr LHS, LHS
+ 1545437853U, // <u,2,0,u>: Cost 2 vext2 <0,2,u,2>, LHS
1550082851U, // <u,2,1,0>: Cost 2 vext2 <1,0,u,2>, <1,0,u,2>
- 2623824692U, // <u,2,1,1>: Cost 3 vext2 <1,0,u,2>, <1,1,1,1>
- 2685232664U, // <u,2,1,2>: Cost 3 vext3 LHS, <2,1,2,3>
- 2886518510U, // <u,2,1,3>: Cost 3 vzipl LHS, <2,3,u,1>
- 2685232682U, // <u,2,1,4>: Cost 3 vext3 LHS, <2,1,4,3>
- 2232223848U, // <u,2,1,5>: Cost 3 vrev <2,u,5,1>
- 2733008444U, // <u,2,1,6>: Cost 3 vext3 LHS, <2,1,6,3>
+ 2619179828U, // <u,2,1,1>: Cost 3 vext2 <0,2,u,2>, <1,1,1,1>
+ 2619179926U, // <u,2,1,2>: Cost 3 vext2 <0,2,u,2>, <1,2,3,0>
+ 2685232671U, // <u,2,1,3>: Cost 3 vext3 LHS, <2,1,3,1>
+ 2555604278U, // <u,2,1,4>: Cost 3 vext1 <0,u,2,1>, RHS
+ 2619180176U, // <u,2,1,5>: Cost 3 vext2 <0,2,u,2>, <1,5,3,7>
+ 2689877564U, // <u,2,1,6>: Cost 3 vext3 LHS, <2,1,6,3>
2602718850U, // <u,2,1,7>: Cost 3 vext1 <u,7,2,1>, <7,u,1,2>
1158703235U, // <u,2,1,u>: Cost 2 vrev <2,u,u,1>
- 1524334694U, // <u,2,2,0>: Cost 2 vext1 <u,0,2,2>, LHS
- 2231937093U, // <u,2,2,1>: Cost 3 vrev <2,u,1,2>
+ 1481867366U, // <u,2,2,0>: Cost 2 vext1 <0,u,2,2>, LHS
+ 2555609846U, // <u,2,2,1>: Cost 3 vext1 <0,u,2,2>, <1,0,3,2>
269271142U, // <u,2,2,2>: Cost 1 vdup2 LHS
1611490930U, // <u,2,2,3>: Cost 2 vext3 LHS, <2,2,3,3>
- 1524337974U, // <u,2,2,4>: Cost 2 vext1 <u,0,2,2>, RHS
- 2598080208U, // <u,2,2,5>: Cost 3 vext1 <u,0,2,2>, <5,1,7,3>
- 2232305778U, // <u,2,2,6>: Cost 3 vrev <2,u,6,2>
- 2598081530U, // <u,2,2,7>: Cost 3 vext1 <u,0,2,2>, <7,0,1,2>
+ 1481870646U, // <u,2,2,4>: Cost 2 vext1 <0,u,2,2>, RHS
+ 2689877640U, // <u,2,2,5>: Cost 3 vext3 LHS, <2,2,5,7>
+ 2619180986U, // <u,2,2,6>: Cost 3 vext2 <0,2,u,2>, <2,6,3,7>
+ 2593436837U, // <u,2,2,7>: Cost 3 vext1 <7,2,2,2>, <7,2,2,2>
269271142U, // <u,2,2,u>: Cost 1 vdup2 LHS
408134301U, // <u,2,3,0>: Cost 1 vext1 LHS, LHS
1481876214U, // <u,2,3,1>: Cost 2 vext1 LHS, <1,0,3,2>
1481877096U, // <u,2,3,2>: Cost 2 vext1 LHS, <2,2,2,2>
- 1812775068U, // <u,2,3,3>: Cost 2 vzipl LHS, LHS
+ 1880326246U, // <u,2,3,3>: Cost 2 vzipr LHS, LHS
408137014U, // <u,2,3,4>: Cost 1 vext1 LHS, RHS
- 1481879248U, // <u,2,3,5>: Cost 2 vext1 LHS, <5,1,7,3>
- 1481880058U, // <u,2,3,6>: Cost 2 vext1 LHS, <6,2,7,3>
+ 1529654992U, // <u,2,3,5>: Cost 2 vext1 LHS, <5,1,7,3>
+ 1529655802U, // <u,2,3,6>: Cost 2 vext1 LHS, <6,2,7,3>
1529656314U, // <u,2,3,7>: Cost 2 vext1 LHS, <7,0,1,2>
408139566U, // <u,2,3,u>: Cost 1 vext1 LHS, LHS
- 1568000942U, // <u,2,4,0>: Cost 2 vext2 <4,0,u,2>, <4,0,u,2>
- 2642406399U, // <u,2,4,1>: Cost 3 vext2 <4,1,u,2>, <4,1,u,2>
- 2643070032U, // <u,2,4,2>: Cost 3 vext2 <4,2,u,2>, <4,2,u,2>
- 2891162567U, // <u,2,4,3>: Cost 3 vzipl LHS, <1,2,u,4>
- 2232174690U, // <u,2,4,4>: Cost 3 vrev <2,u,4,4>
- 1550085430U, // <u,2,4,5>: Cost 2 vext2 <1,0,u,2>, RHS
- 1772541742U, // <u,2,4,6>: Cost 2 vuzpr RHS, LHS
- 2597435021U, // <u,2,4,7>: Cost 3 vext1 <7,u,2,4>, <7,u,2,4>
- 1550085673U, // <u,2,4,u>: Cost 2 vext2 <1,0,u,2>, RHS
- 2712069966U, // <u,2,5,0>: Cost 3 vext3 RHS, <2,5,0,7>
- 2623827664U, // <u,2,5,1>: Cost 3 vext2 <1,0,u,2>, <5,1,7,3>
- 2966231194U, // <u,2,5,2>: Cost 3 vzipr <2,2,2,2>, RHS
- 2886518514U, // <u,2,5,3>: Cost 3 vzipl LHS, <2,3,u,5>
+ 1567853468U, // <u,2,4,0>: Cost 2 vext2 <4,0,6,2>, <4,0,6,2>
+ 2561598362U, // <u,2,4,1>: Cost 3 vext1 <1,u,2,4>, <1,2,3,4>
+ 2555627214U, // <u,2,4,2>: Cost 3 vext1 <0,u,2,4>, <2,3,4,5>
+ 2685232918U, // <u,2,4,3>: Cost 3 vext3 LHS, <2,4,3,5>
+ 2555628854U, // <u,2,4,4>: Cost 3 vext1 <0,u,2,4>, RHS
+ 1545440566U, // <u,2,4,5>: Cost 2 vext2 <0,2,u,2>, RHS
+ 1571982740U, // <u,2,4,6>: Cost 2 vext2 <4,6,u,2>, <4,6,u,2>
+ 2592125957U, // <u,2,4,7>: Cost 3 vext1 <7,0,2,4>, <7,0,2,4>
+ 1545440809U, // <u,2,4,u>: Cost 2 vext2 <0,2,u,2>, RHS
+ 2555633766U, // <u,2,5,0>: Cost 3 vext1 <0,u,2,5>, LHS
+ 2561606550U, // <u,2,5,1>: Cost 3 vext1 <1,u,2,5>, <1,2,3,0>
+ 2689877856U, // <u,2,5,2>: Cost 3 vext3 LHS, <2,5,2,7>
+ 2685233000U, // <u,2,5,3>: Cost 3 vext3 LHS, <2,5,3,6>
1158441059U, // <u,2,5,4>: Cost 2 vrev <2,u,4,5>
- 2852165422U, // <u,2,5,5>: Cost 3 vuzpr <5,5,5,5>, LHS
- 2712070020U, // <u,2,5,6>: Cost 3 vext3 RHS, <2,5,6,7>
- 2849642286U, // <u,2,5,7>: Cost 3 vuzpr <5,1,7,3>, LHS
+ 2645725188U, // <u,2,5,5>: Cost 3 vext2 <4,6,u,2>, <5,5,5,5>
+ 2689877892U, // <u,2,5,6>: Cost 3 vext3 LHS, <2,5,6,7>
+ 2823900470U, // <u,2,5,7>: Cost 3 vuzpr <0,u,0,2>, RHS
1158736007U, // <u,2,5,u>: Cost 2 vrev <2,u,u,5>
- 1527021670U, // <u,2,6,0>: Cost 2 vext1 <u,4,2,6>, LHS
- 2654351793U, // <u,2,6,1>: Cost 3 vext2 <6,1,u,2>, <6,1,u,2>
- 2623828474U, // <u,2,6,2>: Cost 3 vext2 <1,0,u,2>, <6,2,7,3>
- 1638328250U, // <u,2,6,3>: Cost 2 vext3 RHS, <2,6,3,7>
- 1527024950U, // <u,2,6,4>: Cost 2 vext1 <u,4,2,6>, RHS
- 2232264813U, // <u,2,6,5>: Cost 3 vrev <2,u,5,6>
- 2712217558U, // <u,2,6,6>: Cost 3 vext3 RHS, <2,6,6,u>
- 2856277806U, // <u,2,6,7>: Cost 3 vuzpr <6,2,7,3>, LHS
- 1638328295U, // <u,2,6,u>: Cost 2 vext3 RHS, <2,6,u,7>
+ 1481900134U, // <u,2,6,0>: Cost 2 vext1 <0,u,2,6>, LHS
+ 2555642614U, // <u,2,6,1>: Cost 3 vext1 <0,u,2,6>, <1,0,3,2>
+ 2555643496U, // <u,2,6,2>: Cost 3 vext1 <0,u,2,6>, <2,2,2,2>
+ 1611491258U, // <u,2,6,3>: Cost 2 vext3 LHS, <2,6,3,7>
+ 1481903414U, // <u,2,6,4>: Cost 2 vext1 <0,u,2,6>, RHS
+ 2689877964U, // <u,2,6,5>: Cost 3 vext3 LHS, <2,6,5,7>
+ 2689877973U, // <u,2,6,6>: Cost 3 vext3 LHS, <2,6,6,7>
+ 2645726030U, // <u,2,6,7>: Cost 3 vext2 <4,6,u,2>, <6,7,0,1>
+ 1611933671U, // <u,2,6,u>: Cost 2 vext3 LHS, <2,6,u,7>
1585919033U, // <u,2,7,0>: Cost 2 vext2 <7,0,u,2>, <7,0,u,2>
- 2860472110U, // <u,2,7,1>: Cost 3 vuzpr <7,0,1,2>, LHS
- 3021245993U, // <u,2,7,2>: Cost 3 vtrnl <0,2,0,2>, RHS
- 1812778312U, // <u,2,7,3>: Cost 2 vzipl LHS, RHS
- 3027455529U, // <u,2,7,4>: Cost 3 vtrnl <1,2,3,4>, RHS
- 2863453998U, // <u,2,7,5>: Cost 3 vuzpr <7,4,5,6>, LHS
- 3069349417U, // <u,2,7,6>: Cost 3 vtrnl <u,2,4,6>, RHS
- 2659661358U, // <u,2,7,7>: Cost 3 vext2 <7,0,u,2>, <7,7,0,u>
- 1812819272U, // <u,2,7,u>: Cost 2 vzipl LHS, RHS
+ 2573566710U, // <u,2,7,1>: Cost 3 vext1 <3,u,2,7>, <1,0,3,2>
+ 2567596115U, // <u,2,7,2>: Cost 3 vext1 <2,u,2,7>, <2,u,2,7>
+ 1906901094U, // <u,2,7,3>: Cost 2 vzipr RHS, LHS
+ 2555653430U, // <u,2,7,4>: Cost 3 vext1 <0,u,2,7>, RHS
+ 2800080230U, // <u,2,7,5>: Cost 3 vuzpl LHS, <7,4,5,6>
+ 2980643164U, // <u,2,7,6>: Cost 3 vzipr RHS, <0,4,2,6>
+ 2645726828U, // <u,2,7,7>: Cost 3 vext2 <4,6,u,2>, <7,7,7,7>
+ 1906901099U, // <u,2,7,u>: Cost 2 vzipr RHS, LHS
408175266U, // <u,2,u,0>: Cost 1 vext1 LHS, LHS
- 1481917174U, // <u,2,u,1>: Cost 2 vext1 LHS, <1,0,3,2>
+ 1545443118U, // <u,2,u,1>: Cost 2 vext2 <0,2,u,2>, LHS
269271142U, // <u,2,u,2>: Cost 1 vdup2 LHS
- 1812775073U, // <u,2,u,3>: Cost 2 vzipl LHS, LHS
+ 1611491416U, // <u,2,u,3>: Cost 2 vext3 LHS, <2,u,3,3>
408177974U, // <u,2,u,4>: Cost 1 vext1 LHS, RHS
- 1481920208U, // <u,2,u,5>: Cost 2 vext1 LHS, <5,1,7,3>
- 1481921018U, // <u,2,u,6>: Cost 2 vext1 LHS, <6,2,7,3>
+ 1545443482U, // <u,2,u,5>: Cost 2 vext2 <0,2,u,2>, RHS
+ 1726339226U, // <u,2,u,6>: Cost 2 vuzpl LHS, RHS
1529697274U, // <u,2,u,7>: Cost 2 vext1 LHS, <7,0,1,2>
408180526U, // <u,2,u,u>: Cost 1 vext1 LHS, LHS
1544781824U, // <u,3,0,0>: Cost 2 vext2 LHS, <0,0,0,0>
471040156U, // <u,3,0,1>: Cost 1 vext2 LHS, LHS
1544781988U, // <u,3,0,2>: Cost 2 vext2 LHS, <0,2,0,2>
- 2685233319U, // <u,3,0,3>: Cost 3 vext3 LHS, <3,0,3,1>
- 1487899958U, // <u,3,0,4>: Cost 2 vext1 <1,u,3,0>, RHS
- 2685233338U, // <u,3,0,5>: Cost 3 vext3 LHS, <3,0,5,2>
- 2561643002U, // <u,3,0,6>: Cost 3 vext1 <1,u,3,0>, <6,2,7,3>
- 2597475986U, // <u,3,0,7>: Cost 3 vext1 <7,u,3,0>, <7,u,3,0>
+ 2618523900U, // <u,3,0,3>: Cost 3 vext2 LHS, <0,3,1,0>
+ 1544782162U, // <u,3,0,4>: Cost 2 vext2 LHS, <0,4,1,5>
+ 2238188352U, // <u,3,0,5>: Cost 3 vrev <3,u,5,0>
+ 2623169023U, // <u,3,0,6>: Cost 3 vext2 LHS, <0,6,2,7>
+ 2238335826U, // <u,3,0,7>: Cost 3 vrev <3,u,7,0>
471040669U, // <u,3,0,u>: Cost 1 vext2 LHS, LHS
1544782582U, // <u,3,1,0>: Cost 2 vext2 LHS, <1,0,3,2>
1544782644U, // <u,3,1,1>: Cost 2 vext2 LHS, <1,1,1,1>
1544782742U, // <u,3,1,2>: Cost 2 vext2 LHS, <1,2,3,0>
- 2685233402U, // <u,3,1,3>: Cost 3 vext3 LHS, <3,1,3,3>
- 2561649974U, // <u,3,1,4>: Cost 3 vext1 <1,u,3,1>, RHS
- 1592558736U, // <u,3,1,5>: Cost 2 vext2 LHS, <1,5,3,7>
- 2666300623U, // <u,3,1,6>: Cost 3 vext2 LHS, <1,6,1,7>
- 2666300715U, // <u,3,1,7>: Cost 3 vext2 LHS, <1,7,3,0>
- 1544783228U, // <u,3,1,u>: Cost 2 vext2 LHS, <1,u,3,0>
+ 1544782808U, // <u,3,1,3>: Cost 2 vext2 LHS, <1,3,1,3>
+ 2618524733U, // <u,3,1,4>: Cost 3 vext2 LHS, <1,4,3,5>
+ 1544782992U, // <u,3,1,5>: Cost 2 vext2 LHS, <1,5,3,7>
+ 2618524897U, // <u,3,1,6>: Cost 3 vext2 LHS, <1,6,3,7>
+ 2703517987U, // <u,3,1,7>: Cost 3 vext3 <3,1,7,u>, <3,1,7,u>
+ 1544783213U, // <u,3,1,u>: Cost 2 vext2 LHS, <1,u,1,3>
1529716838U, // <u,3,2,0>: Cost 2 vext1 <u,u,3,2>, LHS
1164167966U, // <u,3,2,1>: Cost 2 vrev <3,u,1,2>
1544783464U, // <u,3,2,2>: Cost 2 vext2 LHS, <2,2,2,2>
1544783526U, // <u,3,2,3>: Cost 2 vext2 LHS, <2,3,0,1>
1529720118U, // <u,3,2,4>: Cost 2 vext1 <u,u,3,2>, RHS
- 2704034146U, // <u,3,2,5>: Cost 3 vext3 <3,2,5,u>, <3,2,5,u>
- 1592559546U, // <u,3,2,6>: Cost 2 vext2 LHS, <2,6,3,7>
- 2666301418U, // <u,3,2,7>: Cost 3 vext2 LHS, <2,7,0,1>
+ 2618525544U, // <u,3,2,5>: Cost 3 vext2 LHS, <2,5,3,6>
+ 1544783802U, // <u,3,2,6>: Cost 2 vext2 LHS, <2,6,3,7>
+ 2704181620U, // <u,3,2,7>: Cost 3 vext3 <3,2,7,u>, <3,2,7,u>
1544783931U, // <u,3,2,u>: Cost 2 vext2 LHS, <2,u,0,1>
1544784022U, // <u,3,3,0>: Cost 2 vext2 LHS, <3,0,1,2>
- 1483277128U, // <u,3,3,1>: Cost 2 vext1 <1,1,3,3>, <1,1,3,3>
- 1489913458U, // <u,3,3,2>: Cost 2 vext1 <2,2,3,3>, <2,2,3,3>
+ 1487922559U, // <u,3,3,1>: Cost 2 vext1 <1,u,3,3>, <1,u,3,3>
+ 1493895256U, // <u,3,3,2>: Cost 2 vext1 <2,u,3,3>, <2,u,3,3>
336380006U, // <u,3,3,3>: Cost 1 vdup3 LHS
1544784386U, // <u,3,3,4>: Cost 2 vext2 LHS, <3,4,5,6>
- 2618526242U, // <u,3,3,5>: Cost 3 vext2 LHS, <3,5,0,2>
- 2623171210U, // <u,3,3,6>: Cost 3 vext2 LHS, <3,6,2,7>
- 2597500565U, // <u,3,3,7>: Cost 3 vext1 <7,u,3,3>, <7,u,3,3>
+ 2824054478U, // <u,3,3,5>: Cost 3 vuzpr LHS, <2,3,4,5>
+ 2238286668U, // <u,3,3,6>: Cost 3 vrev <3,u,6,3>
+ 2954069136U, // <u,3,3,7>: Cost 3 vzipr LHS, <1,5,3,7>
336380006U, // <u,3,3,u>: Cost 1 vdup3 LHS
- 1544784786U, // <u,3,4,0>: Cost 2 vext2 LHS, <4,0,5,1>
+ 1487929446U, // <u,3,4,0>: Cost 2 vext1 <1,u,3,4>, LHS
1487930752U, // <u,3,4,1>: Cost 2 vext1 <1,u,3,4>, <1,u,3,4>
- 2618526774U, // <u,3,4,2>: Cost 3 vext2 LHS, <4,2,5,3>
+ 2623171644U, // <u,3,4,2>: Cost 3 vext2 LHS, <4,2,6,0>
2561673366U, // <u,3,4,3>: Cost 3 vext1 <1,u,3,4>, <3,0,1,2>
1487932726U, // <u,3,4,4>: Cost 2 vext1 <1,u,3,4>, RHS
471043382U, // <u,3,4,5>: Cost 1 vext2 LHS, RHS
- 1544785228U, // <u,3,4,6>: Cost 2 vext2 LHS, <4,6,0,2>
- 2597508758U, // <u,3,4,7>: Cost 3 vext1 <7,u,3,4>, <7,u,3,4>
+ 1592561012U, // <u,3,4,6>: Cost 2 vext2 LHS, <4,6,4,6>
+ 2238368598U, // <u,3,4,7>: Cost 3 vrev <3,u,7,4>
471043625U, // <u,3,4,u>: Cost 1 vext2 LHS, RHS
- 2685233698U, // <u,3,5,0>: Cost 3 vext3 LHS, <3,5,0,2>
- 1544785616U, // <u,3,5,1>: Cost 2 vext2 LHS, <5,1,7,3>
- 2618527472U, // <u,3,5,2>: Cost 3 vext2 LHS, <5,2,1,u>
- 2972948634U, // <u,3,5,3>: Cost 3 vzipr <3,3,3,3>, RHS
+ 2555707494U, // <u,3,5,0>: Cost 3 vext1 <0,u,3,5>, LHS
+ 1574645465U, // <u,3,5,1>: Cost 2 vext2 <5,1,u,3>, <5,1,u,3>
+ 2567653106U, // <u,3,5,2>: Cost 3 vext1 <2,u,3,5>, <2,3,u,5>
+ 2555709954U, // <u,3,5,3>: Cost 3 vext1 <0,u,3,5>, <3,4,5,6>
1592561606U, // <u,3,5,4>: Cost 2 vext2 LHS, <5,4,7,6>
1592561668U, // <u,3,5,5>: Cost 2 vext2 LHS, <5,5,5,5>
1592561762U, // <u,3,5,6>: Cost 2 vext2 LHS, <5,6,7,0>
- 2618527862U, // <u,3,5,7>: Cost 3 vext2 LHS, <5,7,0,2>
- 1549431047U, // <u,3,5,u>: Cost 2 vext2 LHS, <5,u,7,3>
- 2618528041U, // <u,3,6,0>: Cost 3 vext2 LHS, <6,0,2,1>
- 2618528124U, // <u,3,6,1>: Cost 3 vext2 LHS, <6,1,2,3>
- 1544786426U, // <u,3,6,2>: Cost 2 vext2 LHS, <6,2,7,3>
- 3107166362U, // <u,3,6,3>: Cost 3 vtrnr <3,3,3,3>, RHS
- 2561690934U, // <u,3,6,4>: Cost 3 vext1 <1,u,3,6>, RHS
+ 1750314294U, // <u,3,5,7>: Cost 2 vuzpr LHS, RHS
+ 1750314295U, // <u,3,5,u>: Cost 2 vuzpr LHS, RHS
+ 2623172897U, // <u,3,6,0>: Cost 3 vext2 LHS, <6,0,1,2>
+ 2561688962U, // <u,3,6,1>: Cost 3 vext1 <1,u,3,6>, <1,u,3,6>
+ 1581281795U, // <u,3,6,2>: Cost 2 vext2 <6,2,u,3>, <6,2,u,3>
+ 2706541204U, // <u,3,6,3>: Cost 3 vext3 <3,6,3,u>, <3,6,3,u>
+ 2623173261U, // <u,3,6,4>: Cost 3 vext2 LHS, <6,4,5,6>
1164495686U, // <u,3,6,5>: Cost 2 vrev <3,u,5,6>
1592562488U, // <u,3,6,6>: Cost 2 vext2 LHS, <6,6,6,6>
1592562510U, // <u,3,6,7>: Cost 2 vext2 LHS, <6,7,0,1>
- 1549431776U, // <u,3,6,u>: Cost 2 vext2 LHS, <6,u,7,3>
- 1592562682U, // <u,3,7,0>: Cost 2 vext2 LHS, <7,0,1,2>
+ 1164716897U, // <u,3,6,u>: Cost 2 vrev <3,u,u,6>
+ 1487954022U, // <u,3,7,0>: Cost 2 vext1 <1,u,3,7>, LHS
1487955331U, // <u,3,7,1>: Cost 2 vext1 <1,u,3,7>, <1,u,3,7>
1493928028U, // <u,3,7,2>: Cost 2 vext1 <2,u,3,7>, <2,u,3,7>
- 2892565832U, // <u,3,7,3>: Cost 3 vzipl <1,1,3,3>, RHS
- 1592563046U, // <u,3,7,4>: Cost 2 vext2 LHS, <7,4,5,6>
- 3034172969U, // <u,3,7,5>: Cost 3 vtrnl <2,3,4,5>, RHS
+ 2561697942U, // <u,3,7,3>: Cost 3 vext1 <1,u,3,7>, <3,0,1,2>
+ 1487957302U, // <u,3,7,4>: Cost 2 vext1 <1,u,3,7>, RHS
+ 2707352311U, // <u,3,7,5>: Cost 3 vext3 <3,7,5,u>, <3,7,5,u>
2655024623U, // <u,3,7,6>: Cost 3 vext2 <6,2,u,3>, <7,6,2,u>
1592563308U, // <u,3,7,7>: Cost 2 vext2 LHS, <7,7,7,7>
- 1592563330U, // <u,3,7,u>: Cost 2 vext2 LHS, <7,u,1,2>
- 1544787666U, // <u,3,u,0>: Cost 2 vext2 LHS, <u,0,1,1>
+ 1487959854U, // <u,3,7,u>: Cost 2 vext1 <1,u,3,7>, LHS
+ 1544787667U, // <u,3,u,0>: Cost 2 vext2 LHS, <u,0,1,2>
471045934U, // <u,3,u,1>: Cost 1 vext2 LHS, LHS
- 1544787820U, // <u,3,u,2>: Cost 2 vext2 LHS, <u,2,0,2>
+ 1549432709U, // <u,3,u,2>: Cost 2 vext2 LHS, <u,2,3,0>
336380006U, // <u,3,u,3>: Cost 1 vdup3 LHS
1544788031U, // <u,3,u,4>: Cost 2 vext2 LHS, <u,4,5,6>
471046298U, // <u,3,u,5>: Cost 1 vext2 LHS, RHS
- 1544788144U, // <u,3,u,6>: Cost 2 vext2 LHS, <u,6,0,2>
- 1592563968U, // <u,3,u,7>: Cost 2 vext2 LHS, <u,7,0,1>
+ 1549433040U, // <u,3,u,6>: Cost 2 vext2 LHS, <u,6,3,7>
+ 1750314537U, // <u,3,u,7>: Cost 2 vuzpr LHS, RHS
471046501U, // <u,3,u,u>: Cost 1 vext2 LHS, LHS
- 2685234022U, // <u,4,0,0>: Cost 3 vext3 LHS, <4,0,0,2>
+ 2625167360U, // <u,4,0,0>: Cost 3 vext2 <1,2,u,4>, <0,0,0,0>
1551425638U, // <u,4,0,1>: Cost 2 vext2 <1,2,u,4>, LHS
- 2824058852U, // <u,4,0,2>: Cost 3 vuzpr LHS, <u,3,4,5>
- 2619859263U, // <u,4,0,3>: Cost 3 vext2 <0,3,u,4>, <0,3,u,4>
- 2567687058U, // <u,4,0,4>: Cost 3 vext1 <2,u,4,0>, <4,0,5,1>
- 1611492242U, // <u,4,0,5>: Cost 2 vext3 LHS, <4,0,5,1>
- 1611492252U, // <u,4,0,6>: Cost 2 vext3 LHS, <4,0,6,2>
- 3318050347U, // <u,4,0,7>: Cost 4 vrev <4,u,7,0>
- 1611492269U, // <u,4,0,u>: Cost 2 vext3 LHS, <4,0,u,1>
- 2625168118U, // <u,4,1,0>: Cost 3 vext2 <1,2,u,4>, <1,0,3,2>
+ 2619195630U, // <u,4,0,2>: Cost 3 vext2 <0,2,u,4>, <0,2,u,4>
+ 2619343104U, // <u,4,0,3>: Cost 3 vext2 <0,3,1,4>, <0,3,1,4>
+ 2625167698U, // <u,4,0,4>: Cost 3 vext2 <1,2,u,4>, <0,4,1,5>
+ 1638329234U, // <u,4,0,5>: Cost 2 vext3 RHS, <4,0,5,1>
+ 1638329244U, // <u,4,0,6>: Cost 2 vext3 RHS, <4,0,6,2>
+ 3787803556U, // <u,4,0,7>: Cost 4 vext3 RHS, <4,0,7,1>
+ 1551426205U, // <u,4,0,u>: Cost 2 vext2 <1,2,u,4>, LHS
+ 2555748454U, // <u,4,1,0>: Cost 3 vext1 <0,u,4,1>, LHS
2625168180U, // <u,4,1,1>: Cost 3 vext2 <1,2,u,4>, <1,1,1,1>
1551426503U, // <u,4,1,2>: Cost 2 vext2 <1,2,u,4>, <1,2,u,4>
- 2625831960U, // <u,4,1,3>: Cost 3 vext2 <1,3,u,4>, <1,3,u,4>
- 2567695670U, // <u,4,1,4>: Cost 3 vext1 <2,u,4,1>, RHS
- 1906759470U, // <u,4,1,5>: Cost 2 vzipr RHS, LHS
- 2685234158U, // <u,4,1,6>: Cost 3 vext3 LHS, <4,1,6,3>
- 2597557916U, // <u,4,1,7>: Cost 3 vext1 <7,u,4,1>, <7,u,4,1>
+ 2625168344U, // <u,4,1,3>: Cost 3 vext2 <1,2,u,4>, <1,3,1,3>
+ 2555751734U, // <u,4,1,4>: Cost 3 vext1 <0,u,4,1>, RHS
+ 1860554038U, // <u,4,1,5>: Cost 2 vzipl LHS, RHS
+ 2689879022U, // <u,4,1,6>: Cost 3 vext3 LHS, <4,1,6,3>
+ 2592248852U, // <u,4,1,7>: Cost 3 vext1 <7,0,4,1>, <7,0,4,1>
1555408301U, // <u,4,1,u>: Cost 2 vext2 <1,u,u,4>, <1,u,u,4>
- 2629813758U, // <u,4,2,0>: Cost 3 vext2 <2,0,u,4>, <2,0,u,4>
+ 2555756646U, // <u,4,2,0>: Cost 3 vext1 <0,u,4,2>, LHS
2625168943U, // <u,4,2,1>: Cost 3 vext2 <1,2,u,4>, <2,1,4,u>
2625169000U, // <u,4,2,2>: Cost 3 vext2 <1,2,u,4>, <2,2,2,2>
- 2625169062U, // <u,4,2,3>: Cost 3 vext2 <1,2,u,4>, <2,3,0,1>
- 3115226926U, // <u,4,2,4>: Cost 3 vtrnr <4,6,4,6>, LHS
- 2685234230U, // <u,4,2,5>: Cost 3 vext3 LHS, <4,2,5,3>
- 2040977198U, // <u,4,2,6>: Cost 2 vtrnr RHS, LHS
- 2597566109U, // <u,4,2,7>: Cost 3 vext1 <7,u,4,2>, <7,u,4,2>
- 2041124654U, // <u,4,2,u>: Cost 2 vtrnr RHS, LHS
+ 2619197134U, // <u,4,2,3>: Cost 3 vext2 <0,2,u,4>, <2,3,4,5>
+ 2555759926U, // <u,4,2,4>: Cost 3 vext1 <0,u,4,2>, RHS
+ 2712071222U, // <u,4,2,5>: Cost 3 vext3 RHS, <4,2,5,3>
+ 1994771766U, // <u,4,2,6>: Cost 2 vtrnl LHS, RHS
+ 2592257045U, // <u,4,2,7>: Cost 3 vext1 <7,0,4,2>, <7,0,4,2>
+ 1994771784U, // <u,4,2,u>: Cost 2 vtrnl LHS, RHS
2625169558U, // <u,4,3,0>: Cost 3 vext2 <1,2,u,4>, <3,0,1,2>
2567709594U, // <u,4,3,1>: Cost 3 vext1 <2,u,4,3>, <1,2,3,4>
2567710817U, // <u,4,3,2>: Cost 3 vext1 <2,u,4,3>, <2,u,4,3>
2625169820U, // <u,4,3,3>: Cost 3 vext2 <1,2,u,4>, <3,3,3,3>
2625169922U, // <u,4,3,4>: Cost 3 vext2 <1,2,u,4>, <3,4,5,6>
- 2899951772U, // <u,4,3,5>: Cost 3 vzipl <2,3,4,5>, LHS
- 3040887453U, // <u,4,3,6>: Cost 3 vtrnl <3,4,5,6>, LHS
- 3987644572U, // <u,4,3,7>: Cost 4 vzipl <4,6,4,7>, LHS
- 2625170206U, // <u,4,3,u>: Cost 3 vext2 <1,2,u,4>, <3,u,1,2>
+ 2954069710U, // <u,4,3,5>: Cost 3 vzipr LHS, <2,3,4,5>
+ 2954068172U, // <u,4,3,6>: Cost 3 vzipr LHS, <0,2,4,6>
+ 3903849472U, // <u,4,3,7>: Cost 4 vuzpr <1,u,3,4>, <1,3,5,7>
+ 2954068174U, // <u,4,3,u>: Cost 3 vzipr LHS, <0,2,4,u>
1505919078U, // <u,4,4,0>: Cost 2 vext1 <4,u,4,4>, LHS
2567717831U, // <u,4,4,1>: Cost 3 vext1 <2,u,4,4>, <1,2,u,4>
2567719010U, // <u,4,4,2>: Cost 3 vext1 <2,u,4,4>, <2,u,4,4>
@@ -6223,182 +6223,182 @@ static const unsigned PerfectShuffleTable[6561+1] = {
2594927963U, // <u,4,4,7>: Cost 3 vext1 <7,4,4,4>, <7,4,4,4>
161926454U, // <u,4,4,u>: Cost 1 vdup0 RHS
1493983334U, // <u,4,5,0>: Cost 2 vext1 <2,u,4,5>, LHS
- 2625171152U, // <u,4,5,1>: Cost 3 vext2 <1,2,u,4>, <5,1,7,3>
+ 2689879301U, // <u,4,5,1>: Cost 3 vext3 LHS, <4,5,1,3>
1493985379U, // <u,4,5,2>: Cost 2 vext1 <2,u,4,5>, <2,u,4,5>
2567727254U, // <u,4,5,3>: Cost 3 vext1 <2,u,4,5>, <3,0,1,2>
1493986614U, // <u,4,5,4>: Cost 2 vext1 <2,u,4,5>, RHS
- 1906759834U, // <u,4,5,5>: Cost 2 vzipr RHS, RHS
+ 1863535926U, // <u,4,5,5>: Cost 2 vzipl RHS, RHS
537750838U, // <u,4,5,6>: Cost 1 vext3 LHS, RHS
- 2652377280U, // <u,4,5,7>: Cost 3 vext2 <5,7,u,4>, <5,7,u,4>
+ 2830110006U, // <u,4,5,7>: Cost 3 vuzpr <1,u,3,4>, RHS
537750856U, // <u,4,5,u>: Cost 1 vext3 LHS, RHS
- 1611492684U, // <u,4,6,0>: Cost 2 vext3 LHS, <4,6,0,2>
- 2712071508U, // <u,4,6,1>: Cost 3 vext3 RHS, <4,6,1,1>
- 2625171962U, // <u,4,6,2>: Cost 3 vext2 <1,2,u,4>, <6,2,7,3>
- 2712071526U, // <u,4,6,3>: Cost 3 vext3 RHS, <4,6,3,1>
- 1638329716U, // <u,4,6,4>: Cost 2 vext3 RHS, <4,6,4,6>
- 3111278746U, // <u,4,6,5>: Cost 3 vtrnr <4,0,5,1>, RHS
- 2040977562U, // <u,4,6,6>: Cost 2 vtrnr RHS, RHS
- 2579682298U, // <u,4,6,7>: Cost 3 vext1 <4,u,4,6>, <7,0,1,2>
- 2041125018U, // <u,4,6,u>: Cost 2 vtrnr RHS, RHS
- 2579685478U, // <u,4,7,0>: Cost 3 vext1 <4,u,4,7>, LHS
- 2602247111U, // <u,4,7,1>: Cost 3 vext1 <u,6,4,7>, <1,2,u,4>
- 2661004509U, // <u,4,7,2>: Cost 3 vext2 <7,2,u,4>, <7,2,u,4>
+ 1482047590U, // <u,4,6,0>: Cost 2 vext1 <0,u,4,6>, LHS
+ 2555790070U, // <u,4,6,1>: Cost 3 vext1 <0,u,4,6>, <1,0,3,2>
+ 2555790952U, // <u,4,6,2>: Cost 3 vext1 <0,u,4,6>, <2,2,2,2>
+ 2555791510U, // <u,4,6,3>: Cost 3 vext1 <0,u,4,6>, <3,0,1,2>
+ 1482050870U, // <u,4,6,4>: Cost 2 vext1 <0,u,4,6>, RHS
+ 2689879422U, // <u,4,6,5>: Cost 3 vext3 LHS, <4,6,5,7>
+ 1997753654U, // <u,4,6,6>: Cost 2 vtrnl RHS, RHS
+ 2712071562U, // <u,4,6,7>: Cost 3 vext3 RHS, <4,6,7,1>
+ 1482053422U, // <u,4,6,u>: Cost 2 vext1 <0,u,4,6>, LHS
+ 2567741542U, // <u,4,7,0>: Cost 3 vext1 <2,u,4,7>, LHS
+ 2567742362U, // <u,4,7,1>: Cost 3 vext1 <2,u,4,7>, <1,2,3,4>
+ 2567743589U, // <u,4,7,2>: Cost 3 vext1 <2,u,4,7>, <2,u,4,7>
2573716286U, // <u,4,7,3>: Cost 3 vext1 <3,u,4,7>, <3,u,4,7>
- 2579688656U, // <u,4,7,4>: Cost 3 vext1 <4,u,4,7>, <4,4,4,4>
- 2899955016U, // <u,4,7,5>: Cost 3 vzipl <2,3,4,5>, RHS
+ 2567744822U, // <u,4,7,4>: Cost 3 vext1 <2,u,4,7>, RHS
+ 2712071624U, // <u,4,7,5>: Cost 3 vext3 RHS, <4,7,5,0>
96808489U, // <u,4,7,6>: Cost 1 vrev RHS
2651715180U, // <u,4,7,7>: Cost 3 vext2 <5,6,u,4>, <7,7,7,7>
96955963U, // <u,4,7,u>: Cost 1 vrev RHS
- 1611492846U, // <u,4,u,0>: Cost 2 vext3 LHS, <4,u,0,2>
+ 1482063974U, // <u,4,u,0>: Cost 2 vext1 <0,u,4,u>, LHS
1551431470U, // <u,4,u,1>: Cost 2 vext2 <1,2,u,4>, LHS
1494009958U, // <u,4,u,2>: Cost 2 vext1 <2,u,4,u>, <2,u,4,u>
- 2625173436U, // <u,4,u,3>: Cost 3 vext2 <1,2,u,4>, <u,3,0,1>
+ 2555807894U, // <u,4,u,3>: Cost 3 vext1 <0,u,4,u>, <3,0,1,2>
161926454U, // <u,4,u,4>: Cost 1 vdup0 RHS
1551431834U, // <u,4,u,5>: Cost 2 vext2 <1,2,u,4>, RHS
537751081U, // <u,4,u,6>: Cost 1 vext3 LHS, RHS
- 2651715840U, // <u,4,u,7>: Cost 3 vext2 <5,6,u,4>, <u,7,0,1>
+ 2830110249U, // <u,4,u,7>: Cost 3 vuzpr <1,u,3,4>, RHS
537751099U, // <u,4,u,u>: Cost 1 vext3 LHS, RHS
2631811072U, // <u,5,0,0>: Cost 3 vext2 <2,3,u,5>, <0,0,0,0>
1558069350U, // <u,5,0,1>: Cost 2 vext2 <2,3,u,5>, LHS
- 2819454710U, // <u,5,0,2>: Cost 3 vuzpr LHS, <u,0,5,1>
- 2573732672U, // <u,5,0,3>: Cost 3 vext1 <3,u,5,0>, <3,u,5,0>
- 1546789265U, // <u,5,0,4>: Cost 2 vext2 <0,4,u,5>, <0,4,u,5>
- 2685234795U, // <u,5,0,5>: Cost 3 vext3 LHS, <5,0,5,1>
+ 2619203823U, // <u,5,0,2>: Cost 3 vext2 <0,2,u,5>, <0,2,u,5>
+ 2619867456U, // <u,5,0,3>: Cost 3 vext2 <0,3,u,5>, <0,3,u,5>
+ 1546273106U, // <u,5,0,4>: Cost 2 vext2 <0,4,1,5>, <0,4,1,5>
+ 2733010539U, // <u,5,0,5>: Cost 3 vext3 LHS, <5,0,5,1>
2597622682U, // <u,5,0,6>: Cost 3 vext1 <7,u,5,0>, <6,7,u,5>
1176539396U, // <u,5,0,7>: Cost 2 vrev <5,u,7,0>
1558069917U, // <u,5,0,u>: Cost 2 vext2 <2,3,u,5>, LHS
- 1500659814U, // <u,5,1,0>: Cost 2 vext1 <4,0,5,1>, LHS
+ 1505968230U, // <u,5,1,0>: Cost 2 vext1 <4,u,5,1>, LHS
2624512887U, // <u,5,1,1>: Cost 3 vext2 <1,1,u,5>, <1,1,u,5>
- 2625176520U, // <u,5,1,2>: Cost 3 vext2 <1,2,u,5>, <1,2,u,5>
- 2574403734U, // <u,5,1,3>: Cost 3 vext1 <4,0,5,1>, <3,0,1,2>
- 1500662674U, // <u,5,1,4>: Cost 2 vext1 <4,0,5,1>, <4,0,5,1>
- 2567769808U, // <u,5,1,5>: Cost 3 vext1 <2,u,5,1>, <5,1,7,3>
- 2987153198U, // <u,5,1,6>: Cost 3 vzipr <5,6,7,0>, LHS
- 1611493072U, // <u,5,1,7>: Cost 2 vext3 LHS, <5,1,7,3>
- 1611493081U, // <u,5,1,u>: Cost 2 vext3 LHS, <5,1,u,3>
- 2573746278U, // <u,5,2,0>: Cost 3 vext1 <3,u,5,2>, LHS
- 2685677296U, // <u,5,2,1>: Cost 3 vext3 LHS, <5,2,1,u>
+ 2631811990U, // <u,5,1,2>: Cost 3 vext2 <2,3,u,5>, <1,2,3,0>
+ 2618541056U, // <u,5,1,3>: Cost 3 vext2 <0,1,u,5>, <1,3,5,7>
+ 1505971510U, // <u,5,1,4>: Cost 2 vext1 <4,u,5,1>, RHS
+ 2627167419U, // <u,5,1,5>: Cost 3 vext2 <1,5,u,5>, <1,5,u,5>
+ 2579714554U, // <u,5,1,6>: Cost 3 vext1 <4,u,5,1>, <6,2,7,3>
+ 1638330064U, // <u,5,1,7>: Cost 2 vext3 RHS, <5,1,7,3>
+ 1638477529U, // <u,5,1,u>: Cost 2 vext3 RHS, <5,1,u,3>
+ 2561802342U, // <u,5,2,0>: Cost 3 vext1 <1,u,5,2>, LHS
+ 2561803264U, // <u,5,2,1>: Cost 3 vext1 <1,u,5,2>, <1,3,5,7>
2631149217U, // <u,5,2,2>: Cost 3 vext2 <2,2,u,5>, <2,2,u,5>
1558071026U, // <u,5,2,3>: Cost 2 vext2 <2,3,u,5>, <2,3,u,5>
- 2573749558U, // <u,5,2,4>: Cost 3 vext1 <3,u,5,2>, RHS
- 3120600878U, // <u,5,2,5>: Cost 3 vtrnr <5,5,5,5>, LHS
- 2685234968U, // <u,5,2,6>: Cost 3 vext3 LHS, <5,2,6,3>
- 2689879840U, // <u,5,2,7>: Cost 3 vext3 LHS, <5,2,7,2>
+ 2561805622U, // <u,5,2,4>: Cost 3 vext1 <1,u,5,2>, RHS
+ 2714062607U, // <u,5,2,5>: Cost 3 vext3 RHS, <5,2,5,3>
+ 2631813050U, // <u,5,2,6>: Cost 3 vext2 <2,3,u,5>, <2,6,3,7>
+ 3092335926U, // <u,5,2,7>: Cost 3 vtrnr <0,u,0,2>, RHS
1561389191U, // <u,5,2,u>: Cost 2 vext2 <2,u,u,5>, <2,u,u,5>
- 2631813270U, // <u,5,3,0>: Cost 3 vext2 <2,3,u,5>, <3,0,1,2>
- 2909946012U, // <u,5,3,1>: Cost 3 vzipl <4,0,5,1>, LHS
+ 2561810534U, // <u,5,3,0>: Cost 3 vext1 <1,u,5,3>, LHS
+ 2561811857U, // <u,5,3,1>: Cost 3 vext1 <1,u,5,3>, <1,u,5,3>
2631813474U, // <u,5,3,2>: Cost 3 vext2 <2,3,u,5>, <3,2,5,u>
2631813532U, // <u,5,3,3>: Cost 3 vext2 <2,3,u,5>, <3,3,3,3>
- 2631813634U, // <u,5,3,4>: Cost 3 vext2 <2,3,u,5>, <3,4,5,6>
- 2919268508U, // <u,5,3,5>: Cost 3 vzipl <5,5,5,5>, LHS
- 2906669212U, // <u,5,3,6>: Cost 3 vzipl <3,4,5,6>, LHS
- 1973863069U, // <u,5,3,7>: Cost 2 vtrnl RHS, LHS
- 1973871261U, // <u,5,3,u>: Cost 2 vtrnl RHS, LHS
- 2631814034U, // <u,5,4,0>: Cost 3 vext2 <2,3,u,5>, <4,0,5,1>
- 2712072079U, // <u,5,4,1>: Cost 3 vext3 RHS, <5,4,1,5>
+ 2619869698U, // <u,5,3,4>: Cost 3 vext2 <0,3,u,5>, <3,4,5,6>
+ 3001847002U, // <u,5,3,5>: Cost 3 vzipr LHS, <4,4,5,5>
+ 2954070530U, // <u,5,3,6>: Cost 3 vzipr LHS, <3,4,5,6>
+ 2018749750U, // <u,5,3,7>: Cost 2 vtrnr LHS, RHS
+ 2018749751U, // <u,5,3,u>: Cost 2 vtrnr LHS, RHS
+ 2573762662U, // <u,5,4,0>: Cost 3 vext1 <3,u,5,4>, LHS
+ 2620017634U, // <u,5,4,1>: Cost 3 vext2 <0,4,1,5>, <4,1,5,0>
2573764338U, // <u,5,4,2>: Cost 3 vext1 <3,u,5,4>, <2,3,u,5>
2573765444U, // <u,5,4,3>: Cost 3 vext1 <3,u,5,4>, <3,u,5,4>
1570680053U, // <u,5,4,4>: Cost 2 vext2 <4,4,u,5>, <4,4,u,5>
1558072630U, // <u,5,4,5>: Cost 2 vext2 <2,3,u,5>, RHS
- 2631814476U, // <u,5,4,6>: Cost 3 vext2 <2,3,u,5>, <4,6,0,2>
+ 2645749143U, // <u,5,4,6>: Cost 3 vext2 <4,6,u,5>, <4,6,u,5>
1638330310U, // <u,5,4,7>: Cost 2 vext3 RHS, <5,4,7,6>
1558072873U, // <u,5,4,u>: Cost 2 vext2 <2,3,u,5>, RHS
- 1527234662U, // <u,5,5,0>: Cost 2 vext1 <u,4,5,5>, LHS
- 2625179344U, // <u,5,5,1>: Cost 3 vext2 <1,2,u,5>, <5,1,7,3>
- 2570454734U, // <u,5,5,2>: Cost 3 vext1 <3,3,5,5>, <2,3,4,5>
- 2570455472U, // <u,5,5,3>: Cost 3 vext1 <3,3,5,5>, <3,3,5,5>
- 1527237942U, // <u,5,5,4>: Cost 2 vext1 <u,4,5,5>, RHS
+ 1506000998U, // <u,5,5,0>: Cost 2 vext1 <4,u,5,5>, LHS
+ 2561827984U, // <u,5,5,1>: Cost 3 vext1 <1,u,5,5>, <1,5,3,7>
+ 2579744360U, // <u,5,5,2>: Cost 3 vext1 <4,u,5,5>, <2,2,2,2>
+ 2579744918U, // <u,5,5,3>: Cost 3 vext1 <4,u,5,5>, <3,0,1,2>
+ 1506004278U, // <u,5,5,4>: Cost 2 vext1 <4,u,5,5>, RHS
229035318U, // <u,5,5,5>: Cost 1 vdup1 RHS
2712072206U, // <u,5,5,6>: Cost 3 vext3 RHS, <5,5,6,6>
1638330392U, // <u,5,5,7>: Cost 2 vext3 RHS, <5,5,7,7>
229035318U, // <u,5,5,u>: Cost 1 vdup1 RHS
1500037222U, // <u,5,6,0>: Cost 2 vext1 <3,u,5,6>, LHS
2561836436U, // <u,5,6,1>: Cost 3 vext1 <1,u,5,6>, <1,u,5,6>
- 2631815674U, // <u,5,6,2>: Cost 3 vext2 <2,3,u,5>, <6,2,7,3>
+ 2567809133U, // <u,5,6,2>: Cost 3 vext1 <2,u,5,6>, <2,u,5,6>
1500040006U, // <u,5,6,3>: Cost 2 vext1 <3,u,5,6>, <3,u,5,6>
1500040502U, // <u,5,6,4>: Cost 2 vext1 <3,u,5,6>, RHS
- 2573782736U, // <u,5,6,5>: Cost 3 vext1 <3,u,5,6>, <5,1,7,3>
- 2573783546U, // <u,5,6,6>: Cost 3 vext1 <3,u,5,6>, <6,2,7,3>
+ 2714062935U, // <u,5,6,5>: Cost 3 vext3 RHS, <5,6,5,7>
+ 2712072288U, // <u,5,6,6>: Cost 3 vext3 RHS, <5,6,6,7>
27705344U, // <u,5,6,7>: Cost 0 copy RHS
27705344U, // <u,5,6,u>: Cost 0 copy RHS
- 2685677686U, // <u,5,7,0>: Cost 3 vext3 LHS, <5,7,0,2>
- 2909949256U, // <u,5,7,1>: Cost 3 vzipl <4,0,5,1>, RHS
- 2579760846U, // <u,5,7,2>: Cost 3 vext1 <4,u,5,7>, <2,3,4,5>
- 2661676335U, // <u,5,7,3>: Cost 3 vext2 <7,3,u,5>, <7,3,u,5>
- 2712072350U, // <u,5,7,4>: Cost 3 vext3 RHS, <5,7,4,6>
- 2919271752U, // <u,5,7,5>: Cost 3 vzipl <5,5,5,5>, RHS
- 2906672456U, // <u,5,7,6>: Cost 3 vzipl <3,4,5,6>, RHS
- 1973866025U, // <u,5,7,7>: Cost 2 vtrnl RHS, RHS
- 1973874217U, // <u,5,7,u>: Cost 2 vtrnl RHS, RHS
- 1500053606U, // <u,5,u,0>: Cost 2 vext1 <3,u,5,u>, LHS
- 1558075182U, // <u,5,u,1>: Cost 2 vext2 <2,3,u,5>, LHS
- 2631817068U, // <u,5,u,2>: Cost 3 vext2 <2,3,u,5>, <u,2,0,2>
+ 1488101478U, // <u,5,7,0>: Cost 2 vext1 <1,u,5,7>, LHS
+ 1488102805U, // <u,5,7,1>: Cost 2 vext1 <1,u,5,7>, <1,u,5,7>
+ 2561844840U, // <u,5,7,2>: Cost 3 vext1 <1,u,5,7>, <2,2,2,2>
+ 2561845398U, // <u,5,7,3>: Cost 3 vext1 <1,u,5,7>, <3,0,1,2>
+ 1488104758U, // <u,5,7,4>: Cost 2 vext1 <1,u,5,7>, RHS
+ 1638330536U, // <u,5,7,5>: Cost 2 vext3 RHS, <5,7,5,7>
+ 2712072362U, // <u,5,7,6>: Cost 3 vext3 RHS, <5,7,6,0>
+ 2042965302U, // <u,5,7,7>: Cost 2 vtrnr RHS, RHS
+ 1488107310U, // <u,5,7,u>: Cost 2 vext1 <1,u,5,7>, LHS
+ 1488109670U, // <u,5,u,0>: Cost 2 vext1 <1,u,5,u>, LHS
+ 1488110998U, // <u,5,u,1>: Cost 2 vext1 <1,u,5,u>, <1,u,5,u>
+ 2561853032U, // <u,5,u,2>: Cost 3 vext1 <1,u,5,u>, <2,2,2,2>
1500056392U, // <u,5,u,3>: Cost 2 vext1 <3,u,5,u>, <3,u,5,u>
- 1500056886U, // <u,5,u,4>: Cost 2 vext1 <3,u,5,u>, RHS
+ 1488112950U, // <u,5,u,4>: Cost 2 vext1 <1,u,5,u>, RHS
229035318U, // <u,5,u,5>: Cost 1 vdup1 RHS
- 2685677822U, // <u,5,u,6>: Cost 3 vext3 LHS, <5,u,6,3>
+ 2954111490U, // <u,5,u,6>: Cost 3 vzipr LHS, <3,4,5,6>
27705344U, // <u,5,u,7>: Cost 0 copy RHS
27705344U, // <u,5,u,u>: Cost 0 copy RHS
- 2819922074U, // <u,6,0,0>: Cost 3 vuzpr <0,2,0,2>, RHS
- 1564713062U, // <u,6,0,1>: Cost 2 vext2 <3,4,u,6>, LHS
- 1745672346U, // <u,6,0,2>: Cost 2 vuzpr LHS, RHS
- 2573806409U, // <u,6,0,3>: Cost 3 vext1 <3,u,6,0>, <3,u,6,0>
- 1546355036U, // <u,6,0,4>: Cost 2 vext2 <0,4,2,6>, <0,4,2,6>
- 2579115974U, // <u,6,0,5>: Cost 3 vext1 <4,7,6,0>, <5,4,7,6>
- 2733011276U, // <u,6,0,6>: Cost 3 vext3 LHS, <6,0,6,0>
- 2685235543U, // <u,6,0,7>: Cost 3 vext3 LHS, <6,0,7,2>
- 1746114714U, // <u,6,0,u>: Cost 2 vuzpr LHS, RHS
+ 2619211776U, // <u,6,0,0>: Cost 3 vext2 <0,2,u,6>, <0,0,0,0>
+ 1545470054U, // <u,6,0,1>: Cost 2 vext2 <0,2,u,6>, LHS
+ 1545470192U, // <u,6,0,2>: Cost 2 vext2 <0,2,u,6>, <0,2,u,6>
+ 2255958969U, // <u,6,0,3>: Cost 3 vrev <6,u,3,0>
+ 1546797458U, // <u,6,0,4>: Cost 2 vext2 <0,4,u,6>, <0,4,u,6>
+ 2720624971U, // <u,6,0,5>: Cost 3 vext3 <6,0,5,u>, <6,0,5,u>
+ 2256180180U, // <u,6,0,6>: Cost 3 vrev <6,u,6,0>
+ 2960682294U, // <u,6,0,7>: Cost 3 vzipr <1,2,u,0>, RHS
+ 1545470621U, // <u,6,0,u>: Cost 2 vext2 <0,2,u,6>, LHS
1182004127U, // <u,6,1,0>: Cost 2 vrev <6,u,0,1>
- 2825296026U, // <u,6,1,1>: Cost 3 vuzpr <1,1,1,1>, RHS
- 2685235580U, // <u,6,1,2>: Cost 3 vext3 LHS, <6,1,2,3>
- 2824788122U, // <u,6,1,3>: Cost 3 vuzpr <1,0,3,2>, RHS
+ 2619212596U, // <u,6,1,1>: Cost 3 vext2 <0,2,u,6>, <1,1,1,1>
+ 2619212694U, // <u,6,1,2>: Cost 3 vext2 <0,2,u,6>, <1,2,3,0>
+ 2619212760U, // <u,6,1,3>: Cost 3 vext2 <0,2,u,6>, <1,3,1,3>
2626511979U, // <u,6,1,4>: Cost 3 vext2 <1,4,u,6>, <1,4,u,6>
- 2650399888U, // <u,6,1,5>: Cost 3 vext2 <5,4,u,6>, <1,5,3,7>
- 2993100590U, // <u,6,1,6>: Cost 3 vzipr <6,6,6,6>, LHS
- 2913386569U, // <u,6,1,7>: Cost 3 vzipl RHS, <0,0,u,1>
+ 2619212944U, // <u,6,1,5>: Cost 3 vext2 <0,2,u,6>, <1,5,3,7>
+ 2714063264U, // <u,6,1,6>: Cost 3 vext3 RHS, <6,1,6,3>
+ 2967326006U, // <u,6,1,7>: Cost 3 vzipr <2,3,u,1>, RHS
1182594023U, // <u,6,1,u>: Cost 2 vrev <6,u,u,1>
- 1500741734U, // <u,6,2,0>: Cost 2 vext1 <4,0,6,2>, LHS
- 2255827881U, // <u,6,2,1>: Cost 3 vrev <6,u,1,2>
- 2685678034U, // <u,6,2,2>: Cost 3 vext3 LHS, <6,2,2,u>
- 2832095386U, // <u,6,2,3>: Cost 3 vuzpr <2,2,3,3>, RHS
- 1500744604U, // <u,6,2,4>: Cost 2 vext1 <4,0,6,2>, <4,0,6,2>
- 2574487248U, // <u,6,2,5>: Cost 3 vext1 <4,0,6,2>, <5,1,7,3>
- 2567852538U, // <u,6,2,6>: Cost 3 vext1 <2,u,6,2>, <6,2,7,3>
- 1611493882U, // <u,6,2,7>: Cost 2 vext3 LHS, <6,2,7,3>
- 1611493891U, // <u,6,2,u>: Cost 2 vext3 LHS, <6,2,u,3>
- 2638456982U, // <u,6,3,0>: Cost 3 vext2 <3,4,u,6>, <3,0,1,2>
- 2836584602U, // <u,6,3,1>: Cost 3 vuzpr <3,0,1,2>, RHS
- 2910027932U, // <u,6,3,2>: Cost 3 vzipl <4,0,6,2>, LHS
- 2838730906U, // <u,6,3,3>: Cost 3 vuzpr <3,3,3,3>, RHS
+ 1506050150U, // <u,6,2,0>: Cost 2 vext1 <4,u,6,2>, LHS
+ 2579792630U, // <u,6,2,1>: Cost 3 vext1 <4,u,6,2>, <1,0,3,2>
+ 2619213416U, // <u,6,2,2>: Cost 3 vext2 <0,2,u,6>, <2,2,2,2>
+ 2619213478U, // <u,6,2,3>: Cost 3 vext2 <0,2,u,6>, <2,3,0,1>
+ 1506053430U, // <u,6,2,4>: Cost 2 vext1 <4,u,6,2>, RHS
+ 2633148309U, // <u,6,2,5>: Cost 3 vext2 <2,5,u,6>, <2,5,u,6>
+ 2619213754U, // <u,6,2,6>: Cost 3 vext2 <0,2,u,6>, <2,6,3,7>
+ 1638330874U, // <u,6,2,7>: Cost 2 vext3 RHS, <6,2,7,3>
+ 1638478339U, // <u,6,2,u>: Cost 2 vext3 RHS, <6,2,u,3>
+ 2619213974U, // <u,6,3,0>: Cost 3 vext2 <0,2,u,6>, <3,0,1,2>
+ 2255836074U, // <u,6,3,1>: Cost 3 vrev <6,u,1,3>
+ 2255909811U, // <u,6,3,2>: Cost 3 vrev <6,u,2,3>
+ 2619214236U, // <u,6,3,3>: Cost 3 vext2 <0,2,u,6>, <3,3,3,3>
1564715549U, // <u,6,3,4>: Cost 2 vext2 <3,4,u,6>, <3,4,u,6>
- 2839566490U, // <u,6,3,5>: Cost 3 vuzpr <3,4,5,6>, RHS
- 3048112797U, // <u,6,3,6>: Cost 3 vtrnl <4,6,4,6>, LHS
- 1839644828U, // <u,6,3,7>: Cost 2 vzipl RHS, LHS
- 1567370081U, // <u,6,3,u>: Cost 2 vext2 <3,u,u,6>, <3,u,u,6>
- 2638457746U, // <u,6,4,0>: Cost 3 vext2 <3,4,u,6>, <4,0,5,1>
- 2638236654U, // <u,6,4,1>: Cost 3 vext2 <3,4,5,6>, <4,1,6,3>
- 2712072817U, // <u,6,4,2>: Cost 3 vext3 RHS, <6,4,2,5>
+ 2639121006U, // <u,6,3,5>: Cost 3 vext2 <3,5,u,6>, <3,5,u,6>
+ 3001847012U, // <u,6,3,6>: Cost 3 vzipr LHS, <4,4,6,6>
+ 1880329526U, // <u,6,3,7>: Cost 2 vzipr LHS, RHS
+ 1880329527U, // <u,6,3,u>: Cost 2 vzipr LHS, RHS
+ 2567864422U, // <u,6,4,0>: Cost 3 vext1 <2,u,6,4>, LHS
+ 2733011558U, // <u,6,4,1>: Cost 3 vext3 LHS, <6,4,1,3>
+ 2567866484U, // <u,6,4,2>: Cost 3 vext1 <2,u,6,4>, <2,u,6,4>
2638458005U, // <u,6,4,3>: Cost 3 vext2 <3,4,u,6>, <4,3,6,u>
1570540772U, // <u,6,4,4>: Cost 2 vext2 <4,4,6,6>, <4,4,6,6>
- 1564716342U, // <u,6,4,5>: Cost 2 vext2 <3,4,u,6>, RHS
- 1772542106U, // <u,6,4,6>: Cost 2 vuzpr RHS, RHS
- 2913387463U, // <u,6,4,7>: Cost 3 vzipl RHS, <1,2,u,4>
- 1564716585U, // <u,6,4,u>: Cost 2 vext2 <3,4,u,6>, RHS
- 2712072882U, // <u,6,5,0>: Cost 3 vext3 RHS, <6,5,0,7>
- 2638458576U, // <u,6,5,1>: Cost 3 vext2 <3,4,u,6>, <5,1,7,3>
- 2712072900U, // <u,6,5,2>: Cost 3 vext3 RHS, <6,5,2,7>
+ 1545473334U, // <u,6,4,5>: Cost 2 vext2 <0,2,u,6>, RHS
+ 1572015512U, // <u,6,4,6>: Cost 2 vext2 <4,6,u,6>, <4,6,u,6>
+ 2960715062U, // <u,6,4,7>: Cost 3 vzipr <1,2,u,4>, RHS
+ 1545473577U, // <u,6,4,u>: Cost 2 vext2 <0,2,u,6>, RHS
+ 2567872614U, // <u,6,5,0>: Cost 3 vext1 <2,u,6,5>, LHS
+ 2645757648U, // <u,6,5,1>: Cost 3 vext2 <4,6,u,6>, <5,1,7,3>
+ 2567874490U, // <u,6,5,2>: Cost 3 vext1 <2,u,6,5>, <2,6,3,7>
2576501250U, // <u,6,5,3>: Cost 3 vext1 <4,3,6,5>, <3,4,5,6>
1576660943U, // <u,6,5,4>: Cost 2 vext2 <5,4,u,6>, <5,4,u,6>
- 2650402820U, // <u,6,5,5>: Cost 3 vext2 <5,4,u,6>, <5,5,5,5>
- 2712072936U, // <u,6,5,6>: Cost 3 vext3 RHS, <6,5,6,7>
- 2913388274U, // <u,6,5,7>: Cost 3 vzipl RHS, <2,3,u,5>
+ 2645757956U, // <u,6,5,5>: Cost 3 vext2 <4,6,u,6>, <5,5,5,5>
+ 2645758050U, // <u,6,5,6>: Cost 3 vext2 <4,6,u,6>, <5,6,7,0>
+ 2824080694U, // <u,6,5,7>: Cost 3 vuzpr <0,u,2,6>, RHS
1182626795U, // <u,6,5,u>: Cost 2 vrev <6,u,u,5>
- 1527316582U, // <u,6,6,0>: Cost 2 vext1 <u,4,6,6>, LHS
- 2601059062U, // <u,6,6,1>: Cost 3 vext1 <u,4,6,6>, <1,0,3,2>
- 2625188346U, // <u,6,6,2>: Cost 3 vext2 <1,2,u,6>, <6,2,7,3>
- 2577172994U, // <u,6,6,3>: Cost 3 vext1 <4,4,6,6>, <3,4,5,6>
- 1527319862U, // <u,6,6,4>: Cost 2 vext1 <u,4,6,6>, RHS
- 2256155601U, // <u,6,6,5>: Cost 3 vrev <6,u,5,6>
+ 1506082918U, // <u,6,6,0>: Cost 2 vext1 <4,u,6,6>, LHS
+ 2579825398U, // <u,6,6,1>: Cost 3 vext1 <4,u,6,6>, <1,0,3,2>
+ 2645758458U, // <u,6,6,2>: Cost 3 vext2 <4,6,u,6>, <6,2,7,3>
+ 2579826838U, // <u,6,6,3>: Cost 3 vext1 <4,u,6,6>, <3,0,1,2>
+ 1506086198U, // <u,6,6,4>: Cost 2 vext1 <4,u,6,6>, RHS
+ 2579828432U, // <u,6,6,5>: Cost 3 vext1 <4,u,6,6>, <5,1,7,3>
296144182U, // <u,6,6,6>: Cost 1 vdup2 RHS
1638331202U, // <u,6,6,7>: Cost 2 vext3 RHS, <6,6,7,7>
296144182U, // <u,6,6,u>: Cost 1 vdup2 RHS
@@ -6409,73 +6409,73 @@ static const unsigned PerfectShuffleTable[6561+1] = {
432352809U, // <u,6,7,4>: Cost 1 vext1 RHS, RHS
1506094800U, // <u,6,7,5>: Cost 2 vext1 RHS, <5,1,7,3>
1506095610U, // <u,6,7,6>: Cost 2 vext1 RHS, <6,2,7,3>
- 1839648072U, // <u,6,7,7>: Cost 2 vzipl RHS, RHS
+ 1906904374U, // <u,6,7,7>: Cost 2 vzipr RHS, RHS
432355118U, // <u,6,7,u>: Cost 1 vext1 RHS, LHS
432357478U, // <u,6,u,0>: Cost 1 vext1 RHS, LHS
- 1564718894U, // <u,6,u,1>: Cost 2 vext2 <3,4,u,6>, LHS
+ 1545475886U, // <u,6,u,1>: Cost 2 vext2 <0,2,u,6>, LHS
1506100840U, // <u,6,u,2>: Cost 2 vext1 RHS, <2,2,2,2>
1506101398U, // <u,6,u,3>: Cost 2 vext1 RHS, <3,0,1,2>
432361002U, // <u,6,u,4>: Cost 1 vext1 RHS, RHS
- 1564719258U, // <u,6,u,5>: Cost 2 vext2 <3,4,u,6>, RHS
+ 1545476250U, // <u,6,u,5>: Cost 2 vext2 <0,2,u,6>, RHS
296144182U, // <u,6,u,6>: Cost 1 vdup2 RHS
- 1611936736U, // <u,6,u,7>: Cost 2 vext3 LHS, <6,u,7,3>
+ 1880370486U, // <u,6,u,7>: Cost 2 vzipr LHS, RHS
432363310U, // <u,6,u,u>: Cost 1 vext1 RHS, LHS
1571356672U, // <u,7,0,0>: Cost 2 vext2 RHS, <0,0,0,0>
497614950U, // <u,7,0,1>: Cost 1 vext2 RHS, LHS
1571356836U, // <u,7,0,2>: Cost 2 vext2 RHS, <0,2,0,2>
- 2645098757U, // <u,7,0,3>: Cost 3 vext2 RHS, <0,3,2,0>
+ 2573880146U, // <u,7,0,3>: Cost 3 vext1 <3,u,7,0>, <3,u,7,0>
1571357010U, // <u,7,0,4>: Cost 2 vext2 RHS, <0,4,1,5>
1512083716U, // <u,7,0,5>: Cost 2 vext1 <5,u,7,0>, <5,u,7,0>
- 2645098989U, // <u,7,0,6>: Cost 3 vext2 RHS, <0,6,0,7>
+ 2621874741U, // <u,7,0,6>: Cost 3 vext2 <0,6,u,7>, <0,6,u,7>
2585826298U, // <u,7,0,7>: Cost 3 vext1 <5,u,7,0>, <7,0,1,2>
497615517U, // <u,7,0,u>: Cost 1 vext2 RHS, LHS
1571357430U, // <u,7,1,0>: Cost 2 vext2 RHS, <1,0,3,2>
1571357492U, // <u,7,1,1>: Cost 2 vext2 RHS, <1,1,1,1>
1571357590U, // <u,7,1,2>: Cost 2 vext2 RHS, <1,2,3,0>
- 2645099470U, // <u,7,1,3>: Cost 3 vext2 RHS, <1,3,0,2>
- 2712073322U, // <u,7,1,4>: Cost 3 vext3 RHS, <7,1,4,6>
- 1571357840U, // <u,7,1,5>: Cost 2 vext2 RHS, <1,5,3,7>
- 2645099727U, // <u,7,1,6>: Cost 3 vext2 RHS, <1,6,1,7>
- 2999818030U, // <u,7,1,7>: Cost 3 vzipr <7,7,7,7>, LHS
- 1571358076U, // <u,7,1,u>: Cost 2 vext2 RHS, <1,u,3,0>
- 2645099956U, // <u,7,2,0>: Cost 3 vext2 RHS, <2,0,0,2>
+ 1552114715U, // <u,7,1,3>: Cost 2 vext2 <1,3,u,7>, <1,3,u,7>
+ 2573888822U, // <u,7,1,4>: Cost 3 vext1 <3,u,7,1>, RHS
+ 1553441981U, // <u,7,1,5>: Cost 2 vext2 <1,5,u,7>, <1,5,u,7>
+ 2627847438U, // <u,7,1,6>: Cost 3 vext2 <1,6,u,7>, <1,6,u,7>
+ 2727408775U, // <u,7,1,7>: Cost 3 vext3 <7,1,7,u>, <7,1,7,u>
+ 1555432880U, // <u,7,1,u>: Cost 2 vext2 <1,u,u,7>, <1,u,u,7>
+ 2629838337U, // <u,7,2,0>: Cost 3 vext2 <2,0,u,7>, <2,0,u,7>
1188058754U, // <u,7,2,1>: Cost 2 vrev <7,u,1,2>
1571358312U, // <u,7,2,2>: Cost 2 vext2 RHS, <2,2,2,2>
1571358374U, // <u,7,2,3>: Cost 2 vext2 RHS, <2,3,0,1>
- 2645100280U, // <u,7,2,4>: Cost 3 vext2 RHS, <2,4,0,2>
- 2645100366U, // <u,7,2,5>: Cost 3 vext2 RHS, <2,5,0,7>
- 1571358650U, // <u,7,2,6>: Cost 2 vext2 RHS, <2,6,3,7>
- 3134035758U, // <u,7,2,7>: Cost 3 vtrnr <7,7,7,7>, LHS
- 1571358779U, // <u,7,2,u>: Cost 2 vext2 RHS, <2,u,0,1>
+ 2632492869U, // <u,7,2,4>: Cost 3 vext2 <2,4,u,7>, <2,4,u,7>
+ 2633156502U, // <u,7,2,5>: Cost 3 vext2 <2,5,u,7>, <2,5,u,7>
+ 1560078311U, // <u,7,2,6>: Cost 2 vext2 <2,6,u,7>, <2,6,u,7>
+ 2728072408U, // <u,7,2,7>: Cost 3 vext3 <7,2,7,u>, <7,2,7,u>
+ 1561405577U, // <u,7,2,u>: Cost 2 vext2 <2,u,u,7>, <2,u,u,7>
1571358870U, // <u,7,3,0>: Cost 2 vext2 RHS, <3,0,1,2>
- 2645100766U, // <u,7,3,1>: Cost 3 vext2 RHS, <3,1,0,2>
- 2645100846U, // <u,7,3,2>: Cost 3 vext2 RHS, <3,2,0,1>
+ 2627184913U, // <u,7,3,1>: Cost 3 vext2 <1,5,u,7>, <3,1,5,u>
+ 2633820523U, // <u,7,3,2>: Cost 3 vext2 <2,6,u,7>, <3,2,6,u>
1571359132U, // <u,7,3,3>: Cost 2 vext2 RHS, <3,3,3,3>
1571359234U, // <u,7,3,4>: Cost 2 vext2 RHS, <3,4,5,6>
1512108295U, // <u,7,3,5>: Cost 2 vext1 <5,u,7,3>, <5,u,7,3>
1518080992U, // <u,7,3,6>: Cost 2 vext1 <6,u,7,3>, <6,u,7,3>
- 2919432348U, // <u,7,3,7>: Cost 3 vzipl <5,5,7,7>, LHS
+ 2640456465U, // <u,7,3,7>: Cost 3 vext2 <3,7,u,7>, <3,7,u,7>
1571359518U, // <u,7,3,u>: Cost 2 vext2 RHS, <3,u,1,2>
1571359634U, // <u,7,4,0>: Cost 2 vext2 RHS, <4,0,5,1>
- 2645101514U, // <u,7,4,1>: Cost 3 vext2 RHS, <4,1,2,3>
- 2645101621U, // <u,7,4,2>: Cost 3 vext2 RHS, <4,2,5,2>
- 2645101703U, // <u,7,4,3>: Cost 3 vext2 RHS, <4,3,5,3>
+ 2573911067U, // <u,7,4,1>: Cost 3 vext1 <3,u,7,4>, <1,3,u,7>
+ 2645101622U, // <u,7,4,2>: Cost 3 vext2 RHS, <4,2,5,3>
+ 2573912918U, // <u,7,4,3>: Cost 3 vext1 <3,u,7,4>, <3,u,7,4>
1571359952U, // <u,7,4,4>: Cost 2 vext2 RHS, <4,4,4,4>
497618248U, // <u,7,4,5>: Cost 1 vext2 RHS, RHS
- 1571360076U, // <u,7,4,6>: Cost 2 vext2 RHS, <4,6,0,2>
- 2712073591U, // <u,7,4,7>: Cost 3 vext3 RHS, <7,4,7,5>
+ 1571360116U, // <u,7,4,6>: Cost 2 vext2 RHS, <4,6,4,6>
+ 2645102024U, // <u,7,4,7>: Cost 3 vext2 RHS, <4,7,5,0>
497618473U, // <u,7,4,u>: Cost 1 vext2 RHS, RHS
- 2645102151U, // <u,7,5,0>: Cost 3 vext2 RHS, <5,0,1,1>
+ 2645102152U, // <u,7,5,0>: Cost 3 vext2 RHS, <5,0,1,2>
1571360464U, // <u,7,5,1>: Cost 2 vext2 RHS, <5,1,7,3>
- 2645102315U, // <u,7,5,2>: Cost 3 vext2 RHS, <5,2,1,3>
- 2645102448U, // <u,7,5,3>: Cost 3 vext2 RHS, <5,3,7,1>
+ 2645102334U, // <u,7,5,2>: Cost 3 vext2 RHS, <5,2,3,4>
+ 2645102447U, // <u,7,5,3>: Cost 3 vext2 RHS, <5,3,7,0>
1571360710U, // <u,7,5,4>: Cost 2 vext2 RHS, <5,4,7,6>
1571360772U, // <u,7,5,5>: Cost 2 vext2 RHS, <5,5,5,5>
1571360866U, // <u,7,5,6>: Cost 2 vext2 RHS, <5,6,7,0>
- 2712073674U, // <u,7,5,7>: Cost 3 vext3 RHS, <7,5,7,7>
- 1571361028U, // <u,7,5,u>: Cost 2 vext2 RHS, <5,u,7,0>
+ 1571360936U, // <u,7,5,7>: Cost 2 vext2 RHS, <5,7,5,7>
+ 1571361017U, // <u,7,5,u>: Cost 2 vext2 RHS, <5,u,5,7>
1530044518U, // <u,7,6,0>: Cost 2 vext1 <u,u,7,6>, LHS
- 2645102972U, // <u,7,6,1>: Cost 3 vext2 RHS, <6,1,2,3>
+ 2645103016U, // <u,7,6,1>: Cost 3 vext2 RHS, <6,1,7,2>
1571361274U, // <u,7,6,2>: Cost 2 vext2 RHS, <6,2,7,3>
2645103154U, // <u,7,6,3>: Cost 3 vext2 RHS, <6,3,4,5>
1530047798U, // <u,7,6,4>: Cost 2 vext1 <u,u,7,6>, RHS
@@ -6484,90 +6484,90 @@ static const unsigned PerfectShuffleTable[6561+1] = {
1571361614U, // <u,7,6,7>: Cost 2 vext2 RHS, <6,7,0,1>
1571361695U, // <u,7,6,u>: Cost 2 vext2 RHS, <6,u,0,1>
1571361786U, // <u,7,7,0>: Cost 2 vext2 RHS, <7,0,1,2>
- 2645103683U, // <u,7,7,1>: Cost 3 vext2 RHS, <7,1,0,3>
+ 2573935616U, // <u,7,7,1>: Cost 3 vext1 <3,u,7,7>, <1,3,5,7>
2645103781U, // <u,7,7,2>: Cost 3 vext2 RHS, <7,2,2,2>
- 2645103843U, // <u,7,7,3>: Cost 3 vext2 RHS, <7,3,0,1>
+ 2573937497U, // <u,7,7,3>: Cost 3 vext1 <3,u,7,7>, <3,u,7,7>
1571362150U, // <u,7,7,4>: Cost 2 vext2 RHS, <7,4,5,6>
- 1510150168U, // <u,7,7,5>: Cost 2 vext1 <5,5,7,7>, <5,5,7,7>
- 1516786498U, // <u,7,7,6>: Cost 2 vext1 <6,6,7,7>, <6,6,7,7>
+ 1512141067U, // <u,7,7,5>: Cost 2 vext1 <5,u,7,7>, <5,u,7,7>
+ 1518113764U, // <u,7,7,6>: Cost 2 vext1 <6,u,7,7>, <6,u,7,7>
363253046U, // <u,7,7,7>: Cost 1 vdup3 RHS
363253046U, // <u,7,7,u>: Cost 1 vdup3 RHS
- 1571362514U, // <u,7,u,0>: Cost 2 vext2 RHS, <u,0,1,1>
+ 1571362515U, // <u,7,u,0>: Cost 2 vext2 RHS, <u,0,1,2>
497620782U, // <u,7,u,1>: Cost 1 vext2 RHS, LHS
- 1571362668U, // <u,7,u,2>: Cost 2 vext2 RHS, <u,2,0,2>
+ 1571362693U, // <u,7,u,2>: Cost 2 vext2 RHS, <u,2,3,0>
1571362748U, // <u,7,u,3>: Cost 2 vext2 RHS, <u,3,0,1>
- 1571362842U, // <u,7,u,4>: Cost 2 vext2 RHS, <u,4,1,5>
+ 1571362879U, // <u,7,u,4>: Cost 2 vext2 RHS, <u,4,5,6>
497621146U, // <u,7,u,5>: Cost 1 vext2 RHS, RHS
- 1571362992U, // <u,7,u,6>: Cost 2 vext2 RHS, <u,6,0,2>
+ 1571363024U, // <u,7,u,6>: Cost 2 vext2 RHS, <u,6,3,7>
363253046U, // <u,7,u,7>: Cost 1 vdup3 RHS
497621349U, // <u,7,u,u>: Cost 1 vext2 RHS, LHS
135053414U, // <u,u,0,0>: Cost 1 vdup0 LHS
471081121U, // <u,u,0,1>: Cost 1 vext2 LHS, LHS
- 1745672036U, // <u,u,0,2>: Cost 2 vuzpr LHS, LHS
+ 1544822948U, // <u,u,0,2>: Cost 2 vext2 LHS, <0,2,0,2>
1616140005U, // <u,u,0,3>: Cost 2 vext3 LHS, <u,0,3,2>
- 1488268598U, // <u,u,0,4>: Cost 2 vext1 <1,u,u,0>, RHS
- 1611495158U, // <u,u,0,5>: Cost 2 vext3 LHS, <u,0,5,1>
- 1611495168U, // <u,u,0,6>: Cost 2 vext3 LHS, <u,0,6,2>
+ 1544823122U, // <u,u,0,4>: Cost 2 vext2 LHS, <0,4,1,5>
+ 1512157453U, // <u,u,0,5>: Cost 2 vext1 <5,u,u,0>, <5,u,u,0>
+ 1662220032U, // <u,u,0,6>: Cost 2 vext3 RHS, <u,0,6,2>
1194457487U, // <u,u,0,7>: Cost 2 vrev <u,u,7,0>
471081629U, // <u,u,0,u>: Cost 1 vext2 LHS, LHS
1544823542U, // <u,u,1,0>: Cost 2 vext2 LHS, <1,0,3,2>
202162278U, // <u,u,1,1>: Cost 1 vdup1 LHS
537753390U, // <u,u,1,2>: Cost 1 vext3 LHS, LHS
- 1611495223U, // <u,u,1,3>: Cost 2 vext3 LHS, <u,1,3,3>
+ 1544823768U, // <u,u,1,3>: Cost 2 vext2 LHS, <1,3,1,3>
1494248758U, // <u,u,1,4>: Cost 2 vext1 <2,u,u,1>, RHS
- 1571366032U, // <u,u,1,5>: Cost 2 vext2 RHS, <1,5,3,7>
+ 1544823952U, // <u,u,1,5>: Cost 2 vext2 LHS, <1,5,3,7>
1518138343U, // <u,u,1,6>: Cost 2 vext1 <6,u,u,1>, <6,u,u,1>
- 1611495259U, // <u,u,1,7>: Cost 2 vext3 LHS, <u,1,7,3>
+ 1640322907U, // <u,u,1,7>: Cost 2 vext3 RHS, <u,1,7,3>
537753444U, // <u,u,1,u>: Cost 1 vext3 LHS, LHS
- 1611495276U, // <u,u,2,0>: Cost 2 vext3 LHS, <u,2,0,2>
+ 1482309734U, // <u,u,2,0>: Cost 2 vext1 <0,u,u,2>, LHS
1194031451U, // <u,u,2,1>: Cost 2 vrev <u,u,1,2>
269271142U, // <u,u,2,2>: Cost 1 vdup2 LHS
835584U, // <u,u,2,3>: Cost 0 copy LHS
- 1500228918U, // <u,u,2,4>: Cost 2 vext1 <3,u,u,2>, RHS
- 2685237146U, // <u,u,2,5>: Cost 3 vext3 LHS, <u,2,5,3>
- 1571366842U, // <u,u,2,6>: Cost 2 vext2 RHS, <2,6,3,7>
- 1611495340U, // <u,u,2,7>: Cost 2 vext3 LHS, <u,2,7,3>
+ 1482313014U, // <u,u,2,4>: Cost 2 vext1 <0,u,u,2>, RHS
+ 2618566504U, // <u,u,2,5>: Cost 3 vext2 LHS, <2,5,3,6>
+ 1544824762U, // <u,u,2,6>: Cost 2 vext2 LHS, <2,6,3,7>
+ 1638479788U, // <u,u,2,7>: Cost 2 vext3 RHS, <u,2,7,3>
835584U, // <u,u,2,u>: Cost 0 copy LHS
408576723U, // <u,u,3,0>: Cost 1 vext1 LHS, LHS
1482318582U, // <u,u,3,1>: Cost 2 vext1 LHS, <1,0,3,2>
120371557U, // <u,u,3,2>: Cost 1 vrev LHS
336380006U, // <u,u,3,3>: Cost 1 vdup3 LHS
408579382U, // <u,u,3,4>: Cost 1 vext1 LHS, RHS
- 1482321616U, // <u,u,3,5>: Cost 2 vext1 LHS, <5,1,7,3>
- 1482322426U, // <u,u,3,6>: Cost 2 vext1 LHS, <6,2,7,3>
- 1839792284U, // <u,u,3,7>: Cost 2 vzipl RHS, LHS
+ 1616140271U, // <u,u,3,5>: Cost 2 vext3 LHS, <u,3,5,7>
+ 1530098170U, // <u,u,3,6>: Cost 2 vext1 LHS, <6,2,7,3>
+ 1880329544U, // <u,u,3,7>: Cost 2 vzipr LHS, RHS
408581934U, // <u,u,3,u>: Cost 1 vext1 LHS, LHS
- 1544825746U, // <u,u,4,0>: Cost 2 vext2 LHS, <4,0,5,1>
+ 1488298086U, // <u,u,4,0>: Cost 2 vext1 <1,u,u,4>, LHS
1488299437U, // <u,u,4,1>: Cost 2 vext1 <1,u,u,4>, <1,u,u,4>
- 1638332452U, // <u,u,4,2>: Cost 2 vext3 RHS, <u,4,2,6>
+ 1659271204U, // <u,u,4,2>: Cost 2 vext3 LHS, <u,4,2,6>
1194195311U, // <u,u,4,3>: Cost 2 vrev <u,u,3,4>
161926454U, // <u,u,4,4>: Cost 1 vdup0 RHS
471084342U, // <u,u,4,5>: Cost 1 vext2 LHS, RHS
- 1544826188U, // <u,u,4,6>: Cost 2 vext2 LHS, <4,6,0,2>
+ 1571368308U, // <u,u,4,6>: Cost 2 vext2 RHS, <4,6,4,6>
1640323153U, // <u,u,4,7>: Cost 2 vext3 RHS, <u,4,7,6>
471084585U, // <u,u,4,u>: Cost 1 vext2 LHS, RHS
1494278246U, // <u,u,5,0>: Cost 2 vext1 <2,u,u,5>, LHS
- 1544826576U, // <u,u,5,1>: Cost 2 vext2 LHS, <5,1,7,3>
+ 1571368656U, // <u,u,5,1>: Cost 2 vext2 RHS, <5,1,7,3>
1494280327U, // <u,u,5,2>: Cost 2 vext1 <2,u,u,5>, <2,u,u,5>
- 1638332543U, // <u,u,5,3>: Cost 2 vext3 RHS, <u,5,3,7>
+ 1616140415U, // <u,u,5,3>: Cost 2 vext3 LHS, <u,5,3,7>
1494281526U, // <u,u,5,4>: Cost 2 vext1 <2,u,u,5>, RHS
229035318U, // <u,u,5,5>: Cost 1 vdup1 RHS
537753754U, // <u,u,5,6>: Cost 1 vext3 LHS, RHS
- 1638332579U, // <u,u,5,7>: Cost 2 vext3 RHS, <u,5,7,7>
+ 1750355254U, // <u,u,5,7>: Cost 2 vuzpr LHS, RHS
537753772U, // <u,u,5,u>: Cost 1 vext3 LHS, RHS
- 1611495600U, // <u,u,6,0>: Cost 2 vext3 LHS, <u,6,0,2>
- 2618569084U, // <u,u,6,1>: Cost 3 vext2 LHS, <6,1,2,3>
- 1544827386U, // <u,u,6,2>: Cost 2 vext2 LHS, <6,2,7,3>
- 1500261217U, // <u,u,6,3>: Cost 2 vext1 <3,u,u,6>, <3,u,u,6>
- 1500261686U, // <u,u,6,4>: Cost 2 vext1 <3,u,u,6>, RHS
+ 1482342502U, // <u,u,6,0>: Cost 2 vext1 <0,u,u,6>, LHS
+ 2556084982U, // <u,u,6,1>: Cost 3 vext1 <0,u,u,6>, <1,0,3,2>
+ 1571369466U, // <u,u,6,2>: Cost 2 vext2 RHS, <6,2,7,3>
+ 1611938000U, // <u,u,6,3>: Cost 2 vext3 LHS, <u,6,3,7>
+ 1482345782U, // <u,u,6,4>: Cost 2 vext1 <0,u,u,6>, RHS
1194359171U, // <u,u,6,5>: Cost 2 vrev <u,u,5,6>
296144182U, // <u,u,6,6>: Cost 1 vdup2 RHS
27705344U, // <u,u,6,7>: Cost 0 copy RHS
27705344U, // <u,u,6,u>: Cost 0 copy RHS
432496742U, // <u,u,7,0>: Cost 1 vext1 RHS, LHS
- 1506239222U, // <u,u,7,1>: Cost 2 vext1 RHS, <1,0,3,2>
- 1506240104U, // <u,u,7,2>: Cost 2 vext1 RHS, <2,2,2,2>
- 1813220680U, // <u,u,7,3>: Cost 2 vzipl LHS, RHS
+ 1488324016U, // <u,u,7,1>: Cost 2 vext1 <1,u,u,7>, <1,u,u,7>
+ 1494296713U, // <u,u,7,2>: Cost 2 vext1 <2,u,u,7>, <2,u,u,7>
+ 1906901148U, // <u,u,7,3>: Cost 2 vzipr RHS, LHS
432500283U, // <u,u,7,4>: Cost 1 vext1 RHS, RHS
1506242256U, // <u,u,7,5>: Cost 2 vext1 RHS, <5,1,7,3>
120699277U, // <u,u,7,6>: Cost 1 vrev RHS
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMRegisterInfo.td b/libclamav/c++/llvm/lib/Target/ARM/ARMRegisterInfo.td
index 651eae5..20a7355 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMRegisterInfo.td
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMRegisterInfo.td
@@ -18,8 +18,8 @@ class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
let SubRegs = subregs;
}
-class ARMFReg<bits<5> num, string n> : Register<n> {
- field bits<5> Num;
+class ARMFReg<bits<6> num, string n> : Register<n> {
+ field bits<6> Num;
let Namespace = "ARM";
}
@@ -58,10 +58,11 @@ def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
+def SDummy : ARMFReg<63, "sINVALID">;
// Aliases of the F* registers used to hold 64-bit fp values (doubles)
def D0 : ARMReg< 0, "d0", [S0, S1]>;
-def D1 : ARMReg< 1, "d1", [S2, S3]>;
+def D1 : ARMReg< 1, "d1", [S2, S3]>;
def D2 : ARMReg< 2, "d2", [S4, S5]>;
def D3 : ARMReg< 3, "d3", [S6, S7]>;
def D4 : ARMReg< 4, "d4", [S8, S9]>;
@@ -89,7 +90,7 @@ def D30 : ARMFReg<30, "d30">; def D31 : ARMFReg<31, "d31">;
// Advanced SIMD (NEON) defines 16 quad-word aliases
def Q0 : ARMReg< 0, "q0", [D0, D1]>;
-def Q1 : ARMReg< 1, "q1", [D2, D3]>;
+def Q1 : ARMReg< 1, "q1", [D2, D3]>;
def Q2 : ARMReg< 2, "q2", [D4, D5]>;
def Q3 : ARMReg< 3, "q3", [D6, D7]>;
def Q4 : ARMReg< 4, "q4", [D8, D9]>;
@@ -253,6 +254,17 @@ def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22,
S23, S24, S25, S26, S27, S28, S29, S30, S31]>;
+// Subset of SPR which can be used as a source of NEON scalars for 16-bit
+// operations
+def SPR_8 : RegisterClass<"ARM", [f32], 32,
+ [S0, S1, S2, S3, S4, S5, S6, S7,
+ S8, S9, S10, S11, S12, S13, S14, S15]>;
+
+// Dummy f32 regclass to represent impossible subreg indices.
+def SPR_INVALID : RegisterClass<"ARM", [f32], 32, [SDummy]> {
+ let CopyCost = -1;
+}
+
// Scalar double precision floating point / generic 64-bit vector register
// class.
// ARM requires only word alignment for double. It's more performant if it
@@ -262,23 +274,23 @@ def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
D8, D9, D10, D11, D12, D13, D14, D15,
D16, D17, D18, D19, D20, D21, D22, D23,
D24, D25, D26, D27, D28, D29, D30, D31]> {
- let SubRegClassList = [SPR, SPR];
+ let SubRegClassList = [SPR_INVALID, SPR_INVALID];
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
// VFP2
- static const unsigned ARM_DPR_VFP2[] = {
- ARM::D0, ARM::D1, ARM::D2, ARM::D3,
- ARM::D4, ARM::D5, ARM::D6, ARM::D7,
- ARM::D8, ARM::D9, ARM::D10, ARM::D11,
+ static const unsigned ARM_DPR_VFP2[] = {
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3,
+ ARM::D4, ARM::D5, ARM::D6, ARM::D7,
+ ARM::D8, ARM::D9, ARM::D10, ARM::D11,
ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
// VFP3
static const unsigned ARM_DPR_VFP3[] = {
- ARM::D0, ARM::D1, ARM::D2, ARM::D3,
- ARM::D4, ARM::D5, ARM::D6, ARM::D7,
- ARM::D8, ARM::D9, ARM::D10, ARM::D11,
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3,
+ ARM::D4, ARM::D5, ARM::D6, ARM::D7,
+ ARM::D8, ARM::D9, ARM::D10, ARM::D11,
ARM::D12, ARM::D13, ARM::D14, ARM::D15,
ARM::D16, ARM::D17, ARM::D18, ARM::D19,
ARM::D20, ARM::D21, ARM::D22, ARM::D23,
@@ -307,17 +319,32 @@ def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
// Subset of DPR that are accessible with VFP2 (and so that also have
// 32-bit SPR subregs).
-def DPR_VFP2 : RegisterClass<"ARM", [f64, v2f32], 64,
+def DPR_VFP2 : RegisterClass<"ARM", [f64, v2i32, v2f32], 64,
[D0, D1, D2, D3, D4, D5, D6, D7,
D8, D9, D10, D11, D12, D13, D14, D15]> {
let SubRegClassList = [SPR, SPR];
}
+// Subset of DPR which can be used as a source of NEON scalars for 16-bit
+// operations
+def DPR_8 : RegisterClass<"ARM", [f64, v4i16, v2f32], 64,
+ [D0, D1, D2, D3, D4, D5, D6, D7]> {
+ let SubRegClassList = [SPR_8, SPR_8];
+}
+
// Generic 128-bit vector register class.
def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15]> {
- let SubRegClassList = [SPR, SPR, SPR, SPR, DPR, DPR];
+ let SubRegClassList = [SPR_INVALID, SPR_INVALID, SPR_INVALID, SPR_INVALID,
+ DPR, DPR];
+}
+
+// Subset of QPR that have 32-bit SPR subregs.
+def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+ 128,
+ [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]> {
+ let SubRegClassList = [SPR, SPR, SPR, SPR, DPR_VFP2, DPR_VFP2];
}
// Condition code registers.
@@ -364,4 +391,3 @@ def : SubRegSet<6, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
[D1, D3, D5, D7, D9, D11, D13, D15,
D17, D19, D21, D23, D25, D27, D29, D31]>;
-
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMSchedule.td b/libclamav/c++/llvm/lib/Target/ARM/ARMSchedule.td
index c73c5b6..fc4c5f5 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMSchedule.td
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMSchedule.td
@@ -15,6 +15,8 @@ def FU_Pipe0 : FuncUnit; // pipeline 0
def FU_Pipe1 : FuncUnit; // pipeline 1
def FU_LdSt0 : FuncUnit; // pipeline 0 load/store
def FU_LdSt1 : FuncUnit; // pipeline 1 load/store
+def FU_NPipe : FuncUnit; // NEON ALU/MUL pipe
+def FU_NLSPipe : FuncUnit; // NEON LS pipe
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for ARM
@@ -59,70 +61,99 @@ def IIC_iStoreiu : InstrItinClass;
def IIC_iStoreru : InstrItinClass;
def IIC_iStoresiu : InstrItinClass;
def IIC_iStorem : InstrItinClass;
-def IIC_fpALU : InstrItinClass;
-def IIC_fpMPY : InstrItinClass;
-def IIC_fpLoad : InstrItinClass;
-def IIC_fpStore : InstrItinClass;
def IIC_Br : InstrItinClass;
+def IIC_fpSTAT : InstrItinClass;
+def IIC_fpUNA32 : InstrItinClass;
+def IIC_fpUNA64 : InstrItinClass;
+def IIC_fpCMP32 : InstrItinClass;
+def IIC_fpCMP64 : InstrItinClass;
+def IIC_fpCVTSD : InstrItinClass;
+def IIC_fpCVTDS : InstrItinClass;
+def IIC_fpCVTIS : InstrItinClass;
+def IIC_fpCVTID : InstrItinClass;
+def IIC_fpCVTSI : InstrItinClass;
+def IIC_fpCVTDI : InstrItinClass;
+def IIC_fpALU32 : InstrItinClass;
+def IIC_fpALU64 : InstrItinClass;
+def IIC_fpMUL32 : InstrItinClass;
+def IIC_fpMUL64 : InstrItinClass;
+def IIC_fpMAC32 : InstrItinClass;
+def IIC_fpMAC64 : InstrItinClass;
+def IIC_fpDIV32 : InstrItinClass;
+def IIC_fpDIV64 : InstrItinClass;
+def IIC_fpSQRT32 : InstrItinClass;
+def IIC_fpSQRT64 : InstrItinClass;
+def IIC_fpLoad32 : InstrItinClass;
+def IIC_fpLoad64 : InstrItinClass;
+def IIC_fpLoadm : InstrItinClass;
+def IIC_fpStore32 : InstrItinClass;
+def IIC_fpStore64 : InstrItinClass;
+def IIC_fpStorem : InstrItinClass;
+def IIC_VLD1 : InstrItinClass;
+def IIC_VLD2 : InstrItinClass;
+def IIC_VLD3 : InstrItinClass;
+def IIC_VLD4 : InstrItinClass;
+def IIC_VST : InstrItinClass;
+def IIC_VUNAD : InstrItinClass;
+def IIC_VUNAQ : InstrItinClass;
+def IIC_VBIND : InstrItinClass;
+def IIC_VBINQ : InstrItinClass;
+def IIC_VMOVImm : InstrItinClass;
+def IIC_VMOVD : InstrItinClass;
+def IIC_VMOVQ : InstrItinClass;
+def IIC_VMOVIS : InstrItinClass;
+def IIC_VMOVID : InstrItinClass;
+def IIC_VMOVISL : InstrItinClass;
+def IIC_VMOVSI : InstrItinClass;
+def IIC_VMOVDI : InstrItinClass;
+def IIC_VPERMD : InstrItinClass;
+def IIC_VPERMQ : InstrItinClass;
+def IIC_VPERMQ3 : InstrItinClass;
+def IIC_VMACD : InstrItinClass;
+def IIC_VMACQ : InstrItinClass;
+def IIC_VRECSD : InstrItinClass;
+def IIC_VRECSQ : InstrItinClass;
+def IIC_VCNTiD : InstrItinClass;
+def IIC_VCNTiQ : InstrItinClass;
+def IIC_VUNAiD : InstrItinClass;
+def IIC_VUNAiQ : InstrItinClass;
+def IIC_VQUNAiD : InstrItinClass;
+def IIC_VQUNAiQ : InstrItinClass;
+def IIC_VBINiD : InstrItinClass;
+def IIC_VBINiQ : InstrItinClass;
+def IIC_VSUBiD : InstrItinClass;
+def IIC_VSUBiQ : InstrItinClass;
+def IIC_VBINi4D : InstrItinClass;
+def IIC_VBINi4Q : InstrItinClass;
+def IIC_VSHLiD : InstrItinClass;
+def IIC_VSHLiQ : InstrItinClass;
+def IIC_VSHLi4D : InstrItinClass;
+def IIC_VSHLi4Q : InstrItinClass;
+def IIC_VPALiD : InstrItinClass;
+def IIC_VPALiQ : InstrItinClass;
+def IIC_VMULi16D : InstrItinClass;
+def IIC_VMULi32D : InstrItinClass;
+def IIC_VMULi16Q : InstrItinClass;
+def IIC_VMULi32Q : InstrItinClass;
+def IIC_VMACi16D : InstrItinClass;
+def IIC_VMACi32D : InstrItinClass;
+def IIC_VMACi16Q : InstrItinClass;
+def IIC_VMACi32Q : InstrItinClass;
+def IIC_VEXTD : InstrItinClass;
+def IIC_VEXTQ : InstrItinClass;
+def IIC_VTB1 : InstrItinClass;
+def IIC_VTB2 : InstrItinClass;
+def IIC_VTB3 : InstrItinClass;
+def IIC_VTB4 : InstrItinClass;
+def IIC_VTBX1 : InstrItinClass;
+def IIC_VTBX2 : InstrItinClass;
+def IIC_VTBX3 : InstrItinClass;
+def IIC_VTBX4 : InstrItinClass;
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
-def GenericItineraries : ProcessorItineraries<[
- InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
- InstrStage<2, [FU_LdSt0]>]>,
- InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
- InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>
-]>;
+def GenericItineraries : ProcessorItineraries<[]>;
include "ARMScheduleV6.td"
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMScheduleV6.td b/libclamav/c++/llvm/lib/Target/ARM/ARMScheduleV6.td
index 1cac918..1ace718 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMScheduleV6.td
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMScheduleV6.td
@@ -11,60 +11,4 @@
//
//===----------------------------------------------------------------------===//
-// TODO: this should model an ARM11
-// Single issue pipeline so every itinerary starts with FU_pipe0
-def V6Itineraries : ProcessorItineraries<[
- InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
- InstrStage<2, [FU_LdSt0]>]>,
- InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
- InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>
-]>;
+// TODO: Add model for an ARM11
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMScheduleV7.td b/libclamav/c++/llvm/lib/Target/ARM/ARMScheduleV7.td
index bf58581..e565813 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMScheduleV7.td
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMScheduleV7.td
@@ -14,7 +14,7 @@
//
// Scheduling information derived from "Cortex-A8 Technical Reference Manual".
//
-// Dual issue pipeline so every itinerary starts with FU_Pipe0 | FU_Pipe1
+// Dual issue pipeline represented by FU_Pipe0 | FU_Pipe1
//
def CortexA8Itineraries : ProcessorItineraries<[
@@ -86,7 +86,7 @@ def CortexA8Itineraries : ProcessorItineraries<[
// Scaled register offset, issues over 2 cycles
InstrItinData<IIC_iLoadsi , [InstrStage<2, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0], 0>,
- InstrStage<1, [FU_Pipe1], 0>,
+ InstrStage<1, [FU_Pipe1]>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [4, 1, 1]>,
//
@@ -103,14 +103,14 @@ def CortexA8Itineraries : ProcessorItineraries<[
// Scaled register offset with update, issues over 2 cycles
InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0], 0>,
- InstrStage<1, [FU_Pipe1], 0>,
+ InstrStage<1, [FU_Pipe1]>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [4, 3, 1, 1]>,
//
// Load multiple
InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Issue], 0>,
InstrStage<2, [FU_Pipe0], 0>,
- InstrStage<2, [FU_Pipe1], 0>,
+ InstrStage<2, [FU_Pipe1]>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>]>,
@@ -120,16 +120,18 @@ def CortexA8Itineraries : ProcessorItineraries<[
//
// Immediate offset
InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Issue], 0>,
- InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [3, 1]>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0]>], [3, 1]>,
//
// Register offset
InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Issue], 0>,
- InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [3, 1, 1]>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
//
// Scaled register offset, issues over 2 cycles
InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0], 0>,
- InstrStage<1, [FU_Pipe1], 0>,
+ InstrStage<1, [FU_Pipe1]>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
//
@@ -146,14 +148,14 @@ def CortexA8Itineraries : ProcessorItineraries<[
// Scaled register offset with update, issues over 2 cycles
InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0], 0>,
- InstrStage<1, [FU_Pipe1], 0>,
+ InstrStage<1, [FU_Pipe1]>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [3, 3, 1, 1]>,
//
// Store multiple
InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Issue], 0>,
InstrStage<2, [FU_Pipe0], 0>,
- InstrStage<2, [FU_Pipe1], 0>,
+ InstrStage<2, [FU_Pipe1]>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>]>,
@@ -162,75 +164,424 @@ def CortexA8Itineraries : ProcessorItineraries<[
// no delay slots, so the latency of a branch is unimportant
InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
- // NFP ALU is not pipelined so stall all issues
- InstrItinData<IIC_fpALU , [InstrStage<7, [FU_Pipe0], 0>,
- InstrStage<7, [FU_Pipe1], 0>]>,
- // VFP MPY is not pipelined so stall all issues
- InstrItinData<IIC_fpMPY , [InstrStage<7, [FU_Pipe0], 0>,
- InstrStage<7, [FU_Pipe1], 0>]>,
- // loads have an extra cycle of latency, but are fully pipelined
+ // VFP
+ // Issue through integer pipeline, and execute in NEON unit. We assume
+ // RunFast mode so that NFP pipeline is used for single-precision when
+ // possible.
+ //
+ // FP Special Register to Integer Register File Move
+ InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>]>,
+ //
+ // Single-precision FP Unary
+ InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [7, 1]>,
+ //
+ // Double-precision FP Unary
+ InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<4, [FU_NPipe], 0>,
+ InstrStage<4, [FU_NLSPipe]>]>,
+ //
+ // Single-precision FP Compare
+ InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [7, 1]>,
+ //
+ // Double-precision FP Compare
+ InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<4, [FU_NPipe], 0>,
+ InstrStage<4, [FU_NLSPipe]>]>,
+ //
+ // Single to Double FP Convert
+ InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<7, [FU_NPipe], 0>,
+ InstrStage<7, [FU_NLSPipe]>]>,
+ //
+ // Double to Single FP Convert
+ InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<5, [FU_NPipe], 0>,
+ InstrStage<5, [FU_NLSPipe]>]>,
+ //
+ // Single-Precision FP to Integer Convert
+ InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [7, 1]>,
+ //
+ // Double-Precision FP to Integer Convert
+ InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<8, [FU_NPipe], 0>,
+ InstrStage<8, [FU_NLSPipe]>]>,
+ //
+ // Integer to Single-Precision FP Convert
+ InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [7, 1]>,
+ //
+ // Integer to Double-Precision FP Convert
+ InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<8, [FU_NPipe], 0>,
+ InstrStage<8, [FU_NLSPipe]>]>,
+ //
+ // Single-precision FP ALU
+ InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [7, 1]>,
+ //
+ // Double-precision FP ALU
+ InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<9, [FU_NPipe], 0>,
+ InstrStage<9, [FU_NLSPipe]>]>,
+ //
+ // Single-precision FP Multiply
+ InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [7, 1]>,
+ //
+ // Double-precision FP Multiply
+ InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<11, [FU_NPipe], 0>,
+ InstrStage<11, [FU_NLSPipe]>]>,
+ //
+ // Single-precision FP MAC
+ InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [7, 1]>,
+ //
+ // Double-precision FP MAC
+ InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<19, [FU_NPipe], 0>,
+ InstrStage<19, [FU_NLSPipe]>]>,
+ //
+ // Single-precision FP DIV
+ InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<20, [FU_NPipe], 0>,
+ InstrStage<20, [FU_NLSPipe]>]>,
+ //
+ // Double-precision FP DIV
+ InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<29, [FU_NPipe], 0>,
+ InstrStage<29, [FU_NLSPipe]>]>,
+ //
+ // Single-precision FP SQRT
+ InstrItinData<IIC_fpSQRT32, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<19, [FU_NPipe], 0>,
+ InstrStage<19, [FU_NLSPipe]>]>,
+ //
+ // Double-precision FP SQRT
+ InstrItinData<IIC_fpSQRT64, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<29, [FU_NPipe], 0>,
+ InstrStage<29, [FU_NLSPipe]>]>,
+ //
+ // Single-precision FP Load
// use FU_Issue to enforce the 1 load/store per cycle limit
- InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Issue], 0>,
+ InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
- InstrStage<1, [FU_LdSt0]>]>,
+ InstrStage<1, [FU_LdSt0], 0>,
+ InstrStage<1, [FU_NLSPipe]>]>,
+ //
+ // Double-precision FP Load
// use FU_Issue to enforce the 1 load/store per cycle limit
- InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Issue], 0>,
- InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>
-]>;
+ InstrItinData<IIC_fpLoad64, [InstrStage<2, [FU_Issue], 0>,
+ InstrStage<1, [FU_Pipe0], 0>,
+ InstrStage<1, [FU_Pipe1]>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0], 0>,
+ InstrStage<1, [FU_NLSPipe]>]>,
+ //
+ // FP Load Multiple
+ // use FU_Issue to enforce the 1 load/store per cycle limit
+ InstrItinData<IIC_fpLoadm, [InstrStage<3, [FU_Issue], 0>,
+ InstrStage<2, [FU_Pipe0], 0>,
+ InstrStage<2, [FU_Pipe1]>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0], 0>,
+ InstrStage<1, [FU_NLSPipe]>]>,
+ //
+ // Single-precision FP Store
+ // use FU_Issue to enforce the 1 load/store per cycle limit
+ InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_Issue], 0>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0], 0>,
+ InstrStage<1, [FU_NLSPipe]>]>,
+ //
+ // Double-precision FP Store
+ // use FU_Issue to enforce the 1 load/store per cycle limit
+ InstrItinData<IIC_fpStore64,[InstrStage<2, [FU_Issue], 0>,
+ InstrStage<1, [FU_Pipe0], 0>,
+ InstrStage<1, [FU_Pipe1]>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0], 0>,
+ InstrStage<1, [FU_NLSPipe]>]>,
+ //
+ // FP Store Multiple
+ // use FU_Issue to enforce the 1 load/store per cycle limit
+ InstrItinData<IIC_fpStorem, [InstrStage<3, [FU_Issue], 0>,
+ InstrStage<2, [FU_Pipe0], 0>,
+ InstrStage<2, [FU_Pipe1]>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0], 0>,
+ InstrStage<1, [FU_NLSPipe]>]>,
-// FIXME
-def CortexA9Itineraries : ProcessorItineraries<[
- InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
- InstrStage<2, [FU_LdSt0]>]>,
- InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
- InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>
+ // NEON
+ // Issue through integer pipeline, and execute in NEON unit.
+ //
+ // VLD1
+ InstrItinData<IIC_VLD1, [InstrStage<1, [FU_Issue], 0>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0], 0>,
+ InstrStage<1, [FU_NLSPipe]>]>,
+ //
+ // VLD2
+ InstrItinData<IIC_VLD2, [InstrStage<1, [FU_Issue], 0>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0], 0>,
+ InstrStage<1, [FU_NLSPipe]>], [2, 2, 1]>,
+ //
+ // VLD3
+ InstrItinData<IIC_VLD3, [InstrStage<1, [FU_Issue], 0>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0], 0>,
+ InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 1]>,
+ //
+ // VLD4
+ InstrItinData<IIC_VLD4, [InstrStage<1, [FU_Issue], 0>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0], 0>,
+ InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 2, 1]>,
+ //
+ // VST
+ InstrItinData<IIC_VST, [InstrStage<1, [FU_Issue], 0>,
+ InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_LdSt0], 0>,
+ InstrStage<1, [FU_NLSPipe]>]>,
+ //
+ // Double-register FP Unary
+ InstrItinData<IIC_VUNAD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [5, 2]>,
+ //
+ // Quad-register FP Unary
+ // Result written in N5, but that is relative to the last cycle of multicycle,
+ // so we use 6 for those cases
+ InstrItinData<IIC_VUNAQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [6, 2]>,
+ //
+ // Double-register FP Binary
+ InstrItinData<IIC_VBIND, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [5, 2, 2]>,
+ //
+ // Quad-register FP Binary
+ // Result written in N5, but that is relative to the last cycle of multicycle,
+ // so we use 6 for those cases
+ InstrItinData<IIC_VBINQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [6, 2, 2]>,
+ //
+ // Move Immediate
+ InstrItinData<IIC_VMOVImm, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3]>,
+ //
+ // Double-register Permute Move
+ InstrItinData<IIC_VMOVD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
+ //
+ // Quad-register Permute Move
+ // Result written in N2, but that is relative to the last cycle of multicycle,
+ // so we use 3 for those cases
+ InstrItinData<IIC_VMOVQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NLSPipe]>], [3, 1]>,
+ //
+ // Integer to Single-precision Move
+ InstrItinData<IIC_VMOVIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
+ //
+ // Integer to Double-precision Move
+ InstrItinData<IIC_VMOVID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
+ //
+ // Single-precision to Integer Move
+ InstrItinData<IIC_VMOVSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>], [20, 1]>,
+ //
+ // Double-precision to Integer Move
+ InstrItinData<IIC_VMOVDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>], [20, 20, 1]>,
+ //
+ // Integer to Lane Move
+ InstrItinData<IIC_VMOVISL , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
+ //
+ // Double-register Permute
+ InstrItinData<IIC_VPERMD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>], [2, 2, 1, 1]>,
+ //
+ // Quad-register Permute
+ // Result written in N2, but that is relative to the last cycle of multicycle,
+ // so we use 3 for those cases
+ InstrItinData<IIC_VPERMQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NLSPipe]>], [3, 3, 1, 1]>,
+ //
+ // Quad-register Permute (3 cycle issue)
+ // Result written in N2, but that is relative to the last cycle of multicycle,
+ // so we use 4 for those cases
+ InstrItinData<IIC_VPERMQ3, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>,
+ InstrStage<1, [FU_NPipe], 0>,
+ InstrStage<2, [FU_NLSPipe]>], [4, 4, 1, 1]>,
+ //
+ // Double-register FP Multiple-Accumulate
+ InstrItinData<IIC_VMACD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [9, 2, 2, 3]>,
+ //
+ // Quad-register FP Multiple-Accumulate
+ // Result written in N9, but that is relative to the last cycle of multicycle,
+ // so we use 10 for those cases
+ InstrItinData<IIC_VMACQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [10, 2, 2, 3]>,
+ //
+ // Double-register Reciprical Step
+ InstrItinData<IIC_VRECSD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [9, 2, 2]>,
+ //
+ // Quad-register Reciprical Step
+ InstrItinData<IIC_VRECSQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [10, 2, 2]>,
+ //
+ // Double-register Integer Count
+ InstrItinData<IIC_VCNTiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
+ //
+ // Quad-register Integer Count
+ // Result written in N3, but that is relative to the last cycle of multicycle,
+ // so we use 4 for those cases
+ InstrItinData<IIC_VCNTiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [4, 2, 2]>,
+ //
+ // Double-register Integer Unary
+ InstrItinData<IIC_VUNAiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [4, 2]>,
+ //
+ // Quad-register Integer Unary
+ InstrItinData<IIC_VUNAiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [4, 2]>,
+ //
+ // Double-register Integer Q-Unary
+ InstrItinData<IIC_VQUNAiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [4, 1]>,
+ //
+ // Quad-register Integer CountQ-Unary
+ InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [4, 1]>,
+ //
+ // Double-register Integer Binary
+ InstrItinData<IIC_VBINiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
+ //
+ // Quad-register Integer Binary
+ InstrItinData<IIC_VBINiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
+ //
+ // Double-register Integer Binary (4 cycle)
+ InstrItinData<IIC_VBINi4D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
+ //
+ // Quad-register Integer Binary (4 cycle)
+ InstrItinData<IIC_VBINi4Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
+ //
+ // Double-register Integer Subtract
+ InstrItinData<IIC_VSUBiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
+ //
+ // Quad-register Integer Subtract
+ InstrItinData<IIC_VSUBiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
+ //
+ // Double-register Integer Shift
+ InstrItinData<IIC_VSHLiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
+ //
+ // Quad-register Integer Shift
+ InstrItinData<IIC_VSHLiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [4, 1, 1]>,
+ //
+ // Double-register Integer Shift (4 cycle)
+ InstrItinData<IIC_VSHLi4D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
+ //
+ // Quad-register Integer Shift (4 cycle)
+ InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [5, 1, 1]>,
+ //
+ // Double-register Integer Pair Add Long
+ InstrItinData<IIC_VPALiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [6, 3, 2, 1]>,
+ //
+ // Quad-register Integer Pair Add Long
+ InstrItinData<IIC_VPALiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>,
+ //
+ // Double-register Integer Multiply (.8, .16)
+ InstrItinData<IIC_VMULi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [6, 2, 2]>,
+ //
+ // Double-register Integer Multiply (.32)
+ InstrItinData<IIC_VMULi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [7, 2, 1]>,
+ //
+ // Quad-register Integer Multiply (.8, .16)
+ InstrItinData<IIC_VMULi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [7, 2, 2]>,
+ //
+ // Quad-register Integer Multiply (.32)
+ InstrItinData<IIC_VMULi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>,
+ InstrStage<2, [FU_NLSPipe], 0>,
+ InstrStage<3, [FU_NPipe]>], [9, 2, 1]>,
+ //
+ // Double-register Integer Multiply-Accumulate (.8, .16)
+ InstrItinData<IIC_VMACi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>], [6, 2, 2, 3]>,
+ //
+ // Double-register Integer Multiply-Accumulate (.32)
+ InstrItinData<IIC_VMACi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [7, 2, 1, 3]>,
+ //
+ // Quad-register Integer Multiply-Accumulate (.8, .16)
+ InstrItinData<IIC_VMACi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NPipe]>], [7, 2, 2, 3]>,
+ //
+ // Quad-register Integer Multiply-Accumulate (.32)
+ InstrItinData<IIC_VMACi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NPipe]>,
+ InstrStage<2, [FU_NLSPipe], 0>,
+ InstrStage<3, [FU_NPipe]>], [9, 2, 1, 3]>,
+ //
+ // Double-register VEXT
+ InstrItinData<IIC_VEXTD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
+ //
+ // Quad-register VEXT
+ InstrItinData<IIC_VEXTQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
+ //
+ // VTB
+ InstrItinData<IIC_VTB1, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NLSPipe]>], [3, 2, 1]>,
+ InstrItinData<IIC_VTB2, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NLSPipe]>], [3, 2, 2, 1]>,
+ InstrItinData<IIC_VTB3, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>,
+ InstrStage<1, [FU_NPipe], 0>,
+ InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 1]>,
+ InstrItinData<IIC_VTB4, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>,
+ InstrStage<1, [FU_NPipe], 0>,
+ InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 3, 1]>,
+ //
+ // VTBX
+ InstrItinData<IIC_VTBX1, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 1]>,
+ InstrItinData<IIC_VTBX2, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 2, 1]>,
+ InstrItinData<IIC_VTBX3, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>,
+ InstrStage<1, [FU_NPipe], 0>,
+ InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 1]>,
+ InstrItinData<IIC_VTBX4, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
+ InstrStage<1, [FU_NLSPipe]>,
+ InstrStage<1, [FU_NPipe], 0>,
+ InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
]>;
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMSubtarget.cpp b/libclamav/c++/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 67669cc..cf1ee3f 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -21,14 +21,19 @@ using namespace llvm;
static cl::opt<bool>
ReserveR9("arm-reserve-r9", cl::Hidden,
cl::desc("Reserve R9, making it unavailable as GPR"));
+static cl::opt<bool>
+UseNEONFP("arm-use-neon-fp",
+ cl::desc("Use NEON for single-precision FP"),
+ cl::init(false), cl::Hidden);
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
bool isThumb)
: ARMArchVersion(V4T)
, ARMFPUType(None)
- , UseNEONForSinglePrecisionFP(false)
+ , UseNEONForSinglePrecisionFP(UseNEONFP)
, IsThumb(isThumb)
, ThumbMode(Thumb1)
+ , PostRAScheduler(false)
, IsR9Reserved(ReserveR9)
, stackAlignment(4)
, CPUString("generic")
@@ -92,14 +97,61 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
if (isTargetDarwin())
IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
+
+ // Set CPU specific features.
+ if (CPUString == "cortex-a8") {
+ PostRAScheduler = true;
+ if (UseNEONFP.getPosition() == 0)
+ UseNEONForSinglePrecisionFP = true;
+ }
}
/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
-bool ARMSubtarget::GVIsIndirectSymbol(GlobalValue *GV, bool isStatic) const {
- // If symbol visibility is hidden, the extra load is not needed if
- // the symbol is definitely defined in the current translation unit.
- bool isDecl = GV->isDeclaration() || GV->hasAvailableExternallyLinkage();
- if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
+bool
+ARMSubtarget::GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) const {
+ if (RelocM == Reloc::Static)
return false;
- return !isStatic && (isDecl || GV->isWeakForLinker());
+
+ // GV with ghost linkage (in JIT lazy compilation mode) do not require an
+ // extra load from stub.
+ bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
+
+ if (!isTargetDarwin()) {
+ // Extra load is needed for all externally visible.
+ if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
+ return false;
+ return true;
+ } else {
+ if (RelocM == Reloc::PIC_) {
+ // If this is a strong reference to a definition, it is definitely not
+ // through a stub.
+ if (!isDecl && !GV->isWeakForLinker())
+ return false;
+
+ // Unless we have a symbol with hidden visibility, we have to go through a
+ // normal $non_lazy_ptr stub because this symbol might be resolved late.
+ if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
+ return true;
+
+ // If symbol visibility is hidden, we have a stub for common symbol
+ // references and external declarations.
+ if (isDecl || GV->hasCommonLinkage())
+ // Hidden $non_lazy_ptr reference.
+ return true;
+
+ return false;
+ } else {
+ // If this is a strong reference to a definition, it is definitely not
+ // through a stub.
+ if (!isDecl && !GV->isWeakForLinker())
+ return false;
+
+ // Unless we have a symbol with hidden visibility, we have to go through a
+ // normal $non_lazy_ptr stub because this symbol might be resolved late.
+ if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
+ return true;
+ }
+ }
+
+ return false;
}
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMSubtarget.h b/libclamav/c++/llvm/lib/Target/ARM/ARMSubtarget.h
index 73f9736..7098fd4 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -15,6 +15,7 @@
#define ARMSUBTARGET_H
#include "llvm/Target/TargetInstrItineraries.h"
+#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtarget.h"
#include <string>
@@ -54,6 +55,9 @@ protected:
/// ThumbMode - Indicates supported Thumb version.
ThumbTypeEnum ThumbMode;
+ /// PostRAScheduler - True if using post-register-allocation scheduler.
+ bool PostRAScheduler;
+
/// IsR9Reserved - True if R9 is a not available as general purpose register.
bool IsR9Reserved;
@@ -121,6 +125,10 @@ protected:
bool isR9Reserved() const { return IsR9Reserved; }
const std::string & getCPUString() const { return CPUString; }
+
+ /// enablePostRAScheduler - From TargetSubtarget, return true to
+ /// enable post-RA scheduler.
+ bool enablePostRAScheduler() const { return PostRAScheduler; }
/// getInstrItins - Return the instruction itineraies based on subtarget
/// selection.
@@ -133,7 +141,7 @@ protected:
/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
/// symbol.
- bool GVIsIndirectSymbol(GlobalValue *GV, bool isStatic) const;
+ bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) const;
};
} // End llvm namespace
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/libclamav/c++/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 6a8519a..32ddc20 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -22,13 +22,8 @@
#include "llvm/Target/TargetRegistry.h"
using namespace llvm;
-static cl::opt<bool> DisableLdStOpti("disable-arm-loadstore-opti", cl::Hidden,
- cl::desc("Disable load store optimization pass"));
-static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden,
- cl::desc("Disable if-conversion pass"));
-
static const MCAsmInfo *createMCAsmInfo(const Target &T,
- const StringRef &TT) {
+ const StringRef &TT) {
Triple TheTriple(TT);
switch (TheTriple.getOS()) {
case Triple::Darwin:
@@ -43,7 +38,7 @@ extern "C" void LLVMInitializeARMTarget() {
// Register the target.
RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
-
+
// Register the target asm info.
RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
@@ -91,7 +86,7 @@ ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
// Pass Pipeline Configuration
bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
- PM.add(createARMISelDag(*this));
+ PM.add(createARMISelDag(*this, OptLevel));
return false;
}
@@ -100,21 +95,25 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
if (Subtarget.hasNEON())
PM.add(createNEONPreAllocPass());
- // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
- if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
+ // FIXME: temporarily disabling load / store optimization pass for Thumb1.
+ if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createARMLoadStoreOptimizationPass(true));
return true;
}
-bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
- // FIXME: temporarily disabling load / store optimization pass for Thumb1 mode.
- if (OptLevel != CodeGenOpt::None && !DisableLdStOpti &&
- !Subtarget.isThumb1Only())
+bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
+ // FIXME: temporarily disabling load / store optimization pass for Thumb1.
+ if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createARMLoadStoreOptimizationPass());
- if (OptLevel != CodeGenOpt::None &&
- !DisableIfConversion && !Subtarget.isThumb1Only())
+ return true;
+}
+
+bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
+ // FIXME: temporarily disabling load / store optimization pass for Thumb1.
+ if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createIfConverterPass());
if (Subtarget.isThumb2()) {
diff --git a/libclamav/c++/llvm/lib/Target/ARM/ARMTargetMachine.h b/libclamav/c++/llvm/lib/Target/ARM/ARMTargetMachine.h
index 4203055..71a5348 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/libclamav/c++/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -50,6 +50,7 @@ public:
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
MachineCodeEmitter &MCE);
diff --git a/libclamav/c++/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/libclamav/c++/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
new file mode 100644
index 0000000..c0ca149
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -0,0 +1,93 @@
+//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "ARM.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/MC/MCAsmLexer.h"
+#include "llvm/MC/MCAsmParser.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/Support/SourceMgr.h"
+#include "llvm/Target/TargetRegistry.h"
+#include "llvm/Target/TargetAsmParser.h"
+using namespace llvm;
+
+namespace {
+struct ARMOperand;
+
+class ARMAsmParser : public TargetAsmParser {
+ MCAsmParser &Parser;
+
+private:
+ MCAsmParser &getParser() const { return Parser; }
+
+ MCAsmLexer &getLexer() const { return Parser.getLexer(); }
+
+ void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
+
+ bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
+
+ bool ParseDirectiveWord(unsigned Size, SMLoc L);
+
+public:
+ ARMAsmParser(const Target &T, MCAsmParser &_Parser)
+ : TargetAsmParser(T), Parser(_Parser) {}
+
+ virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst);
+
+ virtual bool ParseDirective(AsmToken DirectiveID);
+};
+
+} // end anonymous namespace
+
+bool ARMAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
+ SMLoc Loc = getLexer().getTok().getLoc();
+ Error(Loc, "ARMAsmParser::ParseInstruction currently unimplemented");
+ return true;
+}
+
+bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
+ StringRef IDVal = DirectiveID.getIdentifier();
+ if (IDVal == ".word")
+ return ParseDirectiveWord(4, DirectiveID.getLoc());
+ return true;
+}
+
+/// ParseDirectiveWord
+/// ::= .word [ expression (, expression)* ]
+bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
+ if (getLexer().isNot(AsmToken::EndOfStatement)) {
+ for (;;) {
+ const MCExpr *Value;
+ if (getParser().ParseExpression(Value))
+ return true;
+
+ getParser().getStreamer().EmitValue(Value, Size);
+
+ if (getLexer().is(AsmToken::EndOfStatement))
+ break;
+
+ // FIXME: Improve diagnostic.
+ if (getLexer().isNot(AsmToken::Comma))
+ return Error(L, "unexpected token in directive");
+ getLexer().Lex();
+ }
+ }
+
+ getLexer().Lex();
+ return false;
+}
+
+// Force static initialization.
+extern "C" void LLVMInitializeARMAsmParser() {
+ RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
+ RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
+}
diff --git a/libclamav/c++/llvm/lib/Target/ARM/AsmParser/CMakeLists.txt b/libclamav/c++/llvm/lib/Target/ARM/AsmParser/CMakeLists.txt
new file mode 100644
index 0000000..308c6cf
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/ARM/AsmParser/CMakeLists.txt
@@ -0,0 +1,6 @@
+include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
+
+add_llvm_library(LLVMARMAsmParser
+ ARMAsmParser.cpp
+ )
+
diff --git a/libclamav/c++/llvm/lib/Target/ARM/AsmParser/Makefile b/libclamav/c++/llvm/lib/Target/ARM/AsmParser/Makefile
new file mode 100644
index 0000000..97e5612
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/ARM/AsmParser/Makefile
@@ -0,0 +1,15 @@
+##===- lib/Target/ARM/AsmParser/Makefile -------------------*- Makefile -*-===##
+#
+# The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+LEVEL = ../../../..
+LIBRARYNAME = LLVMARMAsmParser
+
+# Hack: we need to include 'main' ARM target directory to grab private headers
+CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
+
+include $(LEVEL)/Makefile.common
diff --git a/libclamav/c++/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/libclamav/c++/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
index d782cde..a441993 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
@@ -1,5 +1,3 @@
-//===-- ARMAsmPrinter.cpp - ARM LLVM assembly writer ----------------------===//
-//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
@@ -30,12 +28,14 @@
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/Support/Compiler.h"
@@ -50,7 +50,6 @@ STATISTIC(EmittedInsts, "Number of machine instrs printed");
namespace {
class VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
- DwarfWriter *DW;
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
/// make the right decision when printing asm code for different targets.
@@ -84,7 +83,7 @@ namespace {
public:
explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
const MCAsmInfo *T, bool V)
- : AsmPrinter(O, TM, T, V), DW(0), AFI(NULL), MCP(NULL),
+ : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL),
InCPMode(false) {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
}
@@ -146,10 +145,12 @@ namespace {
void PrintGlobalVariable(const GlobalVariable* GVar);
void printInstruction(const MachineInstr *MI); // autogenerated.
+ static const char *getRegisterName(unsigned RegNo);
+
void printMachineInstruction(const MachineInstr *MI);
bool runOnMachineFunction(MachineFunction &F);
- bool doInitialization(Module &M);
bool doFinalization(Module &M);
+ void EmitStartOfAsmFile(Module &M);
/// EmitMachineConstantPoolValue - Print a machine constantpool value to
/// the .s file.
@@ -159,11 +160,15 @@ namespace {
ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
GlobalValue *GV = ACPV->getGV();
std::string Name;
-
- if (GV) {
+
+ if (ACPV->isLSDA()) {
+ SmallString<16> LSDAName;
+ raw_svector_ostream(LSDAName) << MAI->getPrivateGlobalPrefix() <<
+ "_LSDA_" << getFunctionNumber();
+ Name = LSDAName.str();
+ } else if (GV) {
bool isIndirect = Subtarget->isTargetDarwin() &&
- Subtarget->GVIsIndirectSymbol(GV,
- TM.getRelocationModel() == Reloc::Static);
+ Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
if (!isIndirect)
Name = Mang->getMangledName(GV);
else {
@@ -175,12 +180,10 @@ namespace {
else
GVNonLazyPtrs[SymName] = Name;
}
- } else if (!strncmp(ACPV->getSymbol(), "L_lsda_", 7))
- Name = ACPV->getSymbol();
- else
+ } else
Name = Mang->makeNameProper(ACPV->getSymbol());
- O << Name;
-
+ O << Name;
+
if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
if (ACPV->getPCAdjustment() != 0) {
O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
@@ -192,7 +195,7 @@ namespace {
}
O << "\n";
}
-
+
void getAnalysisUsage(AnalysisUsage &AU) const {
AsmPrinter::getAnalysisUsage(AU);
AU.setPreservesAll();
@@ -220,7 +223,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
// instructions.
O << '\n';
-
+
// Print out labels for the function.
const Function *F = MF.getFunction();
OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
@@ -249,8 +252,9 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
printVisibility(CurrentFnName, F->getVisibility());
+ unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
if (AFI->isThumbFunction()) {
- EmitAlignment(MF.getAlignment(), F, AFI->getAlign());
+ EmitAlignment(FnAlign, F, AFI->getAlign());
O << "\t.code\t16\n";
O << "\t.thumb_func";
if (Subtarget->isTargetDarwin())
@@ -258,7 +262,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
O << "\n";
InCPMode = false;
} else {
- EmitAlignment(MF.getAlignment(), F);
+ EmitAlignment(FnAlign, F);
}
O << CurrentFnName << ":\n";
@@ -280,7 +284,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
I != E; ++I) {
// Print a label for the basic block.
if (I != MF.begin()) {
- printBasicBlockLabel(I, true, true, VerboseAsm);
+ EmitBasicBlockStart(I);
O << '\n';
}
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
@@ -310,26 +314,33 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
O << '{'
- << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
+ << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
<< '}';
} else if (Modifier && strcmp(Modifier, "lane") == 0) {
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
- unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 0 : 1,
- &ARM::DPRRegClass);
- O << TRI->getAsmName(DReg) << '[' << (RegNum & 1) << ']';
+ unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
+ &ARM::DPR_VFP2RegClass);
+ O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
} else {
- O << TRI->getAsmName(Reg);
+ O << getRegisterName(Reg);
}
} else
llvm_unreachable("not implemented");
break;
}
case MachineOperand::MO_Immediate: {
- O << '#' << MO.getImm();
+ int64_t Imm = MO.getImm();
+ if (Modifier) {
+ if (strcmp(Modifier, "lo16") == 0)
+ Imm = Imm & 0xffffLL;
+ else if (strcmp(Modifier, "hi16") == 0)
+ Imm = (Imm & 0xffff0000LL) >> 16;
+ }
+ O << '#' << Imm;
break;
}
case MachineOperand::MO_MachineBasicBlock:
- printBasicBlockLabel(MO.getMBB());
+ GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
return;
case MachineOperand::MO_GlobalAddress: {
bool isCallOp = Modifier && !strcmp(Modifier, "call");
@@ -346,7 +357,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
case MachineOperand::MO_ExternalSymbol: {
bool isCallOp = Modifier && !strcmp(Modifier, "call");
std::string Name = Mang->makeNameProper(MO.getSymbolName());
-
+
O << Name;
if (isCallOp && Subtarget->isTargetELF() &&
TM.getRelocationModel() == Reloc::PIC_)
@@ -407,9 +418,9 @@ void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
O << "\n\torr";
printPredicateOperand(MI, 2);
O << " ";
- printOperand(MI, 0);
+ printOperand(MI, 0);
O << ", ";
- printOperand(MI, 0);
+ printOperand(MI, 0);
O << ", ";
printSOImm(O, V2, VerboseAsm, MAI);
}
@@ -424,8 +435,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
const MachineOperand &MO2 = MI->getOperand(Op+1);
const MachineOperand &MO3 = MI->getOperand(Op+2);
- assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << TRI->getAsmName(MO1.getReg());
+ O << getRegisterName(MO1.getReg());
// Print the shift opc.
O << ", "
@@ -433,8 +443,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
<< " ";
if (MO2.getReg()) {
- assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
- O << TRI->getAsmName(MO2.getReg());
+ O << getRegisterName(MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
} else {
O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
@@ -451,7 +460,7 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
return;
}
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
if (!MO2.getReg()) {
if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
@@ -464,8 +473,8 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
O << ", "
<< (char)ARM_AM::getAM2Op(MO3.getImm())
- << TRI->getAsmName(MO2.getReg());
-
+ << getRegisterName(MO2.getReg());
+
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
O << ", "
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
@@ -487,8 +496,8 @@ void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
}
O << (char)ARM_AM::getAM2Op(MO2.getImm())
- << TRI->getAsmName(MO1.getReg());
-
+ << getRegisterName(MO1.getReg());
+
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
O << ", "
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
@@ -499,18 +508,18 @@ void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
const MachineOperand &MO3 = MI->getOperand(Op+2);
-
+
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
if (MO2.getReg()) {
O << ", "
<< (char)ARM_AM::getAM3Op(MO3.getImm())
- << TRI->getAsmName(MO2.getReg())
+ << getRegisterName(MO2.getReg())
<< "]";
return;
}
-
+
if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
O << ", #"
<< (char)ARM_AM::getAM3Op(MO3.getImm())
@@ -524,7 +533,7 @@ void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
if (MO1.getReg()) {
O << (char)ARM_AM::getAM3Op(MO2.getImm())
- << TRI->getAsmName(MO1.getReg());
+ << getRegisterName(MO1.getReg());
return;
}
@@ -534,7 +543,7 @@ void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
<< (char)ARM_AM::getAM3Op(MO2.getImm())
<< ImmOffs;
}
-
+
void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
const char *Modifier) {
const MachineOperand &MO1 = MI->getOperand(Op);
@@ -570,7 +579,7 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
printOperand(MI, Op);
return;
}
-
+
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
if (Modifier && strcmp(Modifier, "submode") == 0) {
@@ -584,14 +593,14 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
return;
} else if (Modifier && strcmp(Modifier, "base") == 0) {
// Used for FSTM{D|S} and LSTM{D|S} operations.
- O << TRI->getAsmName(MO1.getReg());
+ O << getRegisterName(MO1.getReg());
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
O << "!";
return;
}
-
- O << "[" << TRI->getAsmName(MO1.getReg());
-
+
+ O << "[" << getRegisterName(MO1.getReg());
+
if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
O << ", #"
<< (char)ARM_AM::getAM5Op(MO2.getImm())
@@ -606,13 +615,13 @@ void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
const MachineOperand &MO3 = MI->getOperand(Op+2);
// FIXME: No support yet for specifying alignment.
- O << "[" << TRI->getAsmName(MO1.getReg()) << "]";
+ O << "[" << getRegisterName(MO1.getReg()) << "]";
if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
if (MO2.getReg() == 0)
O << "!";
else
- O << ", " << TRI->getAsmName(MO2.getReg());
+ O << ", " << getRegisterName(MO2.getReg());
}
}
@@ -625,7 +634,7 @@ void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
const MachineOperand &MO1 = MI->getOperand(Op);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << "[pc, +" << TRI->getAsmName(MO1.getReg()) << "]";
+ O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
}
void
@@ -659,8 +668,8 @@ void
ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
- O << "[" << TRI->getAsmName(MO1.getReg());
- O << ", " << TRI->getAsmName(MO2.getReg()) << "]";
+ O << "[" << getRegisterName(MO1.getReg());
+ O << ", " << getRegisterName(MO2.getReg()) << "]";
}
void
@@ -675,9 +684,9 @@ ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
return;
}
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
if (MO3.getReg())
- O << ", " << TRI->getAsmName(MO3.getReg());
+ O << ", " << getRegisterName(MO3.getReg());
else if (unsigned ImmOffs = MO2.getImm()) {
O << ", #" << ImmOffs;
if (Scale > 1)
@@ -702,7 +711,7 @@ ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
if (unsigned ImmOffs = MO2.getImm())
O << ", #" << ImmOffs << " * 4";
O << "]";
@@ -720,7 +729,7 @@ void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
unsigned Reg = MO1.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
- O << TRI->getAsmName(Reg);
+ O << getRegisterName(Reg);
// Print the shift opc.
O << ", "
@@ -736,7 +745,7 @@ void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
unsigned OffImm = MO2.getImm();
if (OffImm) // Don't print +0.
@@ -749,7 +758,7 @@ void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
int32_t OffImm = (int32_t)MO2.getImm();
// Don't print +0.
@@ -765,7 +774,7 @@ void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
int32_t OffImm = (int32_t)MO2.getImm() / 4;
// Don't print +0.
@@ -793,10 +802,10 @@ void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
const MachineOperand &MO3 = MI->getOperand(OpNum+2);
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
assert(MO2.getReg() && "Invalid so_reg load / store address!");
- O << ", " << TRI->getAsmName(MO2.getReg());
+ O << ", " << getRegisterName(MO2.getReg());
unsigned ShAmt = MO3.getImm();
if (ShAmt) {
@@ -830,10 +839,11 @@ void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
O << "{";
- for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
+ // Always skip the first operand, it's the optional (and implicit writeback).
+ for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
if (MI->getOperand(i).isImplicit())
continue;
- if ((int)i != OpNum) O << ", ";
+ if ((int)i != OpNum+1) O << ", ";
printOperand(MI, i);
}
O << "}";
@@ -853,7 +863,7 @@ void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
unsigned CPI = MI->getOperand(OpNum).getIndex();
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
-
+
if (MCPE.isMachineConstantPoolEntry()) {
EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
} else {
@@ -892,11 +902,11 @@ void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
<< '_' << JTI << '_' << MO2.getImm()
<< "_set_" << MBB->getNumber();
else if (TM.getRelocationModel() == Reloc::PIC_) {
- printBasicBlockLabel(MBB, false, false, false);
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
<< getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
} else {
- printBasicBlockLabel(MBB, false, false, false);
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
}
if (i != e-1)
O << '\n';
@@ -928,12 +938,12 @@ void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
O << MAI->getData16bitsDirective();
if (ByteOffset || HalfWordOffset) {
O << '(';
- printBasicBlockLabel(MBB, false, false, false);
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< '_' << JTI << '_' << MO2.getImm() << ")/2";
} else {
O << "\tb.w ";
- printBasicBlockLabel(MBB, false, false, false);
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
}
if (i != e-1)
O << '\n';
@@ -948,7 +958,7 @@ void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
}
void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
- O << "[pc, " << TRI->getAsmName(MI->getOperand(OpNum).getReg());
+ O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
if (MI->getOpcode() == ARM::t2TBH)
O << ", lsl #1";
O << ']';
@@ -968,7 +978,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
default: return true; // Unknown modifier.
case 'a': // Print as a memory address.
if (MI->getOperand(OpNum).isReg()) {
- O << "[" << TRI->getAsmName(MI->getOperand(OpNum).getReg()) << "]";
+ O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
return false;
}
// Fallthrough
@@ -988,7 +998,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
if (TM.getTargetData()->isBigEndian())
break;
// Fallthrough
- case 'H': // Write second word of DI / DF reference.
+ case 'H': // Write second word of DI / DF reference.
// Verify that this operand has two consecutive registers.
if (!MI->getOperand(OpNum).isReg() ||
OpNum+1 == MI->getNumOperands() ||
@@ -997,7 +1007,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
++OpNum; // Return the high-part.
}
}
-
+
printOperand(MI, OpNum);
return false;
}
@@ -1028,13 +1038,43 @@ void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
}}
// Call the autogenerated instruction printer routines.
+ processDebugLoc(MI);
printInstruction(MI);
+ if (VerboseAsm && !MI->getDebugLoc().isUnknown())
+ EmitComments(*MI);
+ O << '\n';
}
-bool ARMAsmPrinter::doInitialization(Module &M) {
-
- bool Result = AsmPrinter::doInitialization(M);
- DW = getAnalysisIfAvailable<DwarfWriter>();
+void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
+ if (Subtarget->isTargetDarwin()) {
+ Reloc::Model RelocM = TM.getRelocationModel();
+ if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
+ // Declare all the text sections up front (before the DWARF sections
+ // emitted by AsmPrinter::doInitialization) so the assembler will keep
+ // them together at the beginning of the object file. This helps
+ // avoid out-of-range branches that are due a fundamental limitation of
+ // the way symbol offsets are encoded with the current Darwin ARM
+ // relocations.
+ TargetLoweringObjectFileMachO &TLOFMacho =
+ static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
+ OutStreamer.SwitchSection(TLOFMacho.getTextSection());
+ OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
+ OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
+ if (RelocM == Reloc::DynamicNoPIC) {
+ const MCSection *sect =
+ TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
+ MCSectionMachO::S_SYMBOL_STUBS,
+ 12, SectionKind::getText());
+ OutStreamer.SwitchSection(sect);
+ } else {
+ const MCSection *sect =
+ TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
+ MCSectionMachO::S_SYMBOL_STUBS,
+ 16, SectionKind::getText());
+ OutStreamer.SwitchSection(sect);
+ }
+ }
+ }
// Use unified assembler syntax mode for Thumb.
if (Subtarget->isThumb())
@@ -1072,8 +1112,6 @@ bool ARMAsmPrinter::doInitialization(Module &M) {
// FIXME: Should we signal R9 usage?
}
-
- return Result;
}
void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
@@ -1106,7 +1144,7 @@ void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
if (Subtarget->isTargetELF())
O << "\t.type " << name << ",%object\n";
-
+
const MCSection *TheSection =
getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
OutStreamer.SwitchSection(TheSection);
@@ -1171,7 +1209,7 @@ void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
return;
}
}
-
+
switch (GVar->getLinkage()) {
case GlobalValue::CommonLinkage:
case GlobalValue::LinkOnceAnyLinkage:
@@ -1217,9 +1255,9 @@ void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
bool ARMAsmPrinter::doFinalization(Module &M) {
if (Subtarget->isTargetDarwin()) {
// All darwin targets use mach-o.
- TargetLoweringObjectFileMachO &TLOFMacho =
+ TargetLoweringObjectFileMachO &TLOFMacho =
static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
-
+
O << '\n';
// Output non-lazy-pointers for external and common global variables.
@@ -1257,7 +1295,7 @@ bool ARMAsmPrinter::doFinalization(Module &M) {
}
// Force static initialization.
-extern "C" void LLVMInitializeARMAsmPrinter() {
+extern "C" void LLVMInitializeARMAsmPrinter() {
RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
}
diff --git a/libclamav/c++/llvm/lib/Target/ARM/Makefile b/libclamav/c++/llvm/lib/Target/ARM/Makefile
index d879521..a8dd38c 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/Makefile
+++ b/libclamav/c++/llvm/lib/Target/ARM/Makefile
@@ -18,6 +18,6 @@ BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
ARMGenDAGISel.inc ARMGenSubtarget.inc \
ARMGenCodeEmitter.inc ARMGenCallingConv.inc
-DIRS = AsmPrinter TargetInfo
+DIRS = AsmPrinter AsmParser TargetInfo
include $(LEVEL)/Makefile.common
diff --git a/libclamav/c++/llvm/lib/Target/ARM/NEONPreAllocPass.cpp b/libclamav/c++/llvm/lib/Target/ARM/NEONPreAllocPass.cpp
index f1f3b31..985cc86 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/NEONPreAllocPass.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/NEONPreAllocPass.cpp
@@ -45,6 +45,9 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
case ARM::VLD2d8:
case ARM::VLD2d16:
case ARM::VLD2d32:
+ case ARM::VLD2LNd8:
+ case ARM::VLD2LNd16:
+ case ARM::VLD2LNd32:
FirstOpnd = 0;
NumRegs = 2;
return true;
@@ -52,6 +55,9 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
case ARM::VLD3d8:
case ARM::VLD3d16:
case ARM::VLD3d32:
+ case ARM::VLD3LNd8:
+ case ARM::VLD3LNd16:
+ case ARM::VLD3LNd32:
FirstOpnd = 0;
NumRegs = 3;
return true;
@@ -59,6 +65,9 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
case ARM::VLD4d8:
case ARM::VLD4d16:
case ARM::VLD4d32:
+ case ARM::VLD4LNd8:
+ case ARM::VLD4LNd16:
+ case ARM::VLD4LNd32:
FirstOpnd = 0;
NumRegs = 4;
return true;
@@ -66,6 +75,9 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
case ARM::VST2d8:
case ARM::VST2d16:
case ARM::VST2d32:
+ case ARM::VST2LNd8:
+ case ARM::VST2LNd16:
+ case ARM::VST2LNd32:
FirstOpnd = 3;
NumRegs = 2;
return true;
@@ -73,6 +85,9 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
case ARM::VST3d8:
case ARM::VST3d16:
case ARM::VST3d32:
+ case ARM::VST3LNd8:
+ case ARM::VST3LNd16:
+ case ARM::VST3LNd32:
FirstOpnd = 3;
NumRegs = 3;
return true;
@@ -80,6 +95,9 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
case ARM::VST4d8:
case ARM::VST4d16:
case ARM::VST4d32:
+ case ARM::VST4LNd8:
+ case ARM::VST4LNd16:
+ case ARM::VST4LNd32:
FirstOpnd = 3;
NumRegs = 4;
return true;
diff --git a/libclamav/c++/llvm/lib/Target/ARM/README.txt b/libclamav/c++/llvm/lib/Target/ARM/README.txt
index 08435c5..8fb1da3 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/README.txt
+++ b/libclamav/c++/llvm/lib/Target/ARM/README.txt
@@ -592,3 +592,11 @@ conditional move:
it saves an instruction and a register.
//===---------------------------------------------------------------------===//
+
+add/sub/and/or + i32 imm can be simplified by folding part of the immediate
+into the operation.
+
+//===---------------------------------------------------------------------===//
+
+It might be profitable to cse MOVi16 if there are lots of 32-bit immediates
+with the same bottom half.
diff --git a/libclamav/c++/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/libclamav/c++/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index dc4ce64..7eed30e 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -156,6 +156,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
AddDefaultPred(MIB);
+ MIB.addReg(0); // No write back.
for (unsigned i = CSI.size(); i != 0; --i) {
unsigned Reg = CSI[i-1].getReg();
// Add the callee-saved register as live-in. It's killed at the spill.
@@ -178,6 +179,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
DebugLoc DL = MI->getDebugLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
AddDefaultPred(MIB);
+ MIB.addReg(0); // No write back.
bool NumRegs = 0;
for (unsigned i = CSI.size(); i != 0; --i) {
diff --git a/libclamav/c++/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp b/libclamav/c++/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
index 796057f..0cea27f 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
@@ -37,10 +37,10 @@
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
-static cl::opt<bool>
-ThumbRegScavenging("enable-thumb-reg-scavenging",
- cl::Hidden,
- cl::desc("Enable register scavenging on Thumb"));
+// FIXME: This cmd line option conditionalizes the new register scavenging
+// implemenation in PEI. Remove the option when scavenging works well enough
+// to be the default.
+extern cl::opt<bool> FrameIndexVirtualScavenging;
Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
const ARMSubtarget &sti)
@@ -84,7 +84,7 @@ Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
bool
Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
- return ThumbRegScavenging;
+ return FrameIndexVirtualScavenging;
}
bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
@@ -113,6 +113,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
const TargetInstrInfo &TII,
const Thumb1RegisterInfo& MRI,
DebugLoc dl) {
+ MachineFunction &MF = *MBB.getParent();
bool isHigh = !isARMLowRegister(DestReg) ||
(BaseReg != 0 && !isARMLowRegister(BaseReg));
bool isSub = false;
@@ -127,9 +128,13 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
unsigned LdReg = DestReg;
if (DestReg == ARM::SP) {
assert(BaseReg == ARM::SP && "Unexpected!");
- LdReg = ARM::R3;
- BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
- .addReg(ARM::R3, RegState::Kill);
+ if (FrameIndexVirtualScavenging) {
+ LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
+ } else {
+ LdReg = ARM::R3;
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
+ .addReg(ARM::R3, RegState::Kill);
+ }
}
if (NumBytes <= 255 && NumBytes >= 0)
@@ -155,7 +160,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
AddDefaultPred(MIB);
- if (DestReg == ARM::SP)
+ if (!FrameIndexVirtualScavenging && DestReg == ARM::SP)
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3)
.addReg(ARM::R12, RegState::Kill);
}
@@ -602,50 +607,73 @@ void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
else // tLDR has an extra register operand.
MI.addOperand(MachineOperand::CreateReg(0, false));
} else if (Desc.mayStore()) {
- // FIXME! This is horrific!!! We need register scavenging.
- // Our temporary workaround has marked r3 unavailable. Of course, r3 is
- // also a ABI register so it's possible that is is the register that is
- // being storing here. If that's the case, we do the following:
- // r12 = r2
- // Use r2 to materialize sp + offset
- // str r3, r2
- // r2 = r12
- unsigned ValReg = MI.getOperand(0).getReg();
- unsigned TmpReg = ARM::R3;
- bool UseRR = false;
- if (ValReg == ARM::R3) {
- BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
- .addReg(ARM::R2, RegState::Kill);
- TmpReg = ARM::R2;
- }
- if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
- BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
- .addReg(ARM::R3, RegState::Kill);
- if (Opcode == ARM::tSpill) {
- if (FrameReg == ARM::SP)
- emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
- Offset, false, TII, *this, dl);
- else {
- emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
- UseRR = true;
+ if (FrameIndexVirtualScavenging) {
+ unsigned TmpReg =
+ MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
+ bool UseRR = false;
+ if (Opcode == ARM::tSpill) {
+ if (FrameReg == ARM::SP)
+ emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
+ Offset, false, TII, *this, dl);
+ else {
+ emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
+ UseRR = true;
+ }
+ } else
+ emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
+ *this, dl);
+ MI.setDesc(TII.get(ARM::tSTR));
+ MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
+ if (UseRR) // Use [reg, reg] addrmode.
+ MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
+ else // tSTR has an extra register operand.
+ MI.addOperand(MachineOperand::CreateReg(0, false));
+ } else {
+ // FIXME! This is horrific!!! We need register scavenging.
+ // Our temporary workaround has marked r3 unavailable. Of course, r3 is
+ // also a ABI register so it's possible that is is the register that is
+ // being storing here. If that's the case, we do the following:
+ // r12 = r2
+ // Use r2 to materialize sp + offset
+ // str r3, r2
+ // r2 = r12
+ unsigned ValReg = MI.getOperand(0).getReg();
+ unsigned TmpReg = ARM::R3;
+ bool UseRR = false;
+ if (ValReg == ARM::R3) {
+ BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
+ .addReg(ARM::R2, RegState::Kill);
+ TmpReg = ARM::R2;
}
- } else
- emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
- *this, dl);
- MI.setDesc(TII.get(ARM::tSTR));
- MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
- if (UseRR) // Use [reg, reg] addrmode.
- MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
- else // tSTR has an extra register operand.
- MI.addOperand(MachineOperand::CreateReg(0, false));
+ if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
+ BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12)
+ .addReg(ARM::R3, RegState::Kill);
+ if (Opcode == ARM::tSpill) {
+ if (FrameReg == ARM::SP)
+ emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
+ Offset, false, TII, *this, dl);
+ else {
+ emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
+ UseRR = true;
+ }
+ } else
+ emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
+ *this, dl);
+ MI.setDesc(TII.get(ARM::tSTR));
+ MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
+ if (UseRR) // Use [reg, reg] addrmode.
+ MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
+ else // tSTR has an extra register operand.
+ MI.addOperand(MachineOperand::CreateReg(0, false));
- MachineBasicBlock::iterator NII = next(II);
- if (ValReg == ARM::R3)
- BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R2)
- .addReg(ARM::R12, RegState::Kill);
- if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
- BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3)
- .addReg(ARM::R12, RegState::Kill);
+ MachineBasicBlock::iterator NII = next(II);
+ if (ValReg == ARM::R3)
+ BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R2)
+ .addReg(ARM::R12, RegState::Kill);
+ if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
+ BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3)
+ .addReg(ARM::R12, RegState::Kill);
+ }
} else
assert(false && "Unexpected opcode!");
@@ -737,8 +765,7 @@ void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
// Darwin ABI requires FP to point to the stack slot that contains the
// previous FP.
if (STI.isTargetDarwin() || hasFP(MF)) {
- MachineInstrBuilder MIB =
- BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
.addFrameIndex(FramePtrSpillFI).addImm(0);
}
@@ -835,11 +862,14 @@ void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
if (VARegSaveSize) {
// Epilogue for vararg functions: pop LR to R3 and branch off it.
// FIXME: Verify this is still ok when R3 is no longer being reserved.
- AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))).addReg(ARM::R3);
+ AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
+ .addReg(0) // No write back.
+ .addReg(ARM::R3, RegState::Define);
emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
- BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
+ .addReg(ARM::R3, RegState::Kill);
MBB.erase(MBBI);
}
}
diff --git a/libclamav/c++/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp b/libclamav/c++/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
index e74a526..98b5cbd 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
@@ -35,17 +35,48 @@ namespace {
}
private:
+ MachineBasicBlock::iterator
+ SplitT2MOV32imm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineInstr *MI, DebugLoc dl,
+ unsigned PredReg, ARMCC::CondCodes CC);
bool InsertITBlocks(MachineBasicBlock &MBB);
};
char Thumb2ITBlockPass::ID = 0;
}
-static ARMCC::CondCodes getPredicate(const MachineInstr *MI,
- const Thumb2InstrInfo *TII) {
+static ARMCC::CondCodes getPredicate(const MachineInstr *MI, unsigned &PredReg){
unsigned Opc = MI->getOpcode();
if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
return ARMCC::AL;
- return TII->getPredicate(MI);
+ return llvm::getInstrPredicate(MI, PredReg);
+}
+
+MachineBasicBlock::iterator
+Thumb2ITBlockPass::SplitT2MOV32imm(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineInstr *MI,
+ DebugLoc dl, unsigned PredReg,
+ ARMCC::CondCodes CC) {
+ // Splitting t2MOVi32imm into a pair of t2MOVi16 + t2MOVTi16 here.
+ // The only reason it was a single instruction was so it could be
+ // re-materialized. We want to split it before this and the thumb2
+ // size reduction pass to make sure the IT mask is correct and expose
+ // width reduction opportunities. It doesn't make sense to do this in a
+ // separate pass so here it is.
+ unsigned DstReg = MI->getOperand(0).getReg();
+ bool DstDead = MI->getOperand(0).isDead(); // Is this possible?
+ unsigned Imm = MI->getOperand(1).getImm();
+ unsigned Lo16 = Imm & 0xffff;
+ unsigned Hi16 = (Imm >> 16) & 0xffff;
+ BuildMI(MBB, MBBI, dl, TII->get(ARM::t2MOVi16), DstReg)
+ .addImm(Lo16).addImm(CC).addReg(PredReg);
+ BuildMI(MBB, MBBI, dl, TII->get(ARM::t2MOVTi16))
+ .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead))
+ .addReg(DstReg).addImm(Hi16).addImm(CC).addReg(PredReg);
+ --MBBI;
+ --MBBI;
+ MI->eraseFromParent();
+ return MBBI;
}
bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
@@ -54,14 +85,21 @@ bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
while (MBBI != E) {
MachineInstr *MI = &*MBBI;
- ARMCC::CondCodes CC = getPredicate(MI, TII);
+ DebugLoc dl = MI->getDebugLoc();
+ unsigned PredReg = 0;
+ ARMCC::CondCodes CC = getPredicate(MI, PredReg);
+
+ if (MI->getOpcode() == ARM::t2MOVi32imm) {
+ MBBI = SplitT2MOV32imm(MBB, MBBI, MI, dl, PredReg, CC);
+ continue;
+ }
+
if (CC == ARMCC::AL) {
++MBBI;
continue;
}
// Insert an IT instruction.
- DebugLoc dl = MI->getDebugLoc();
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
.addImm(CC);
++MBBI;
@@ -70,7 +108,15 @@ bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
unsigned Mask = 0, Pos = 3;
while (MBBI != E && Pos) {
- ARMCC::CondCodes NCC = getPredicate(&*MBBI, TII);
+ MachineInstr *NMI = &*MBBI;
+ DebugLoc ndl = NMI->getDebugLoc();
+ unsigned NPredReg = 0;
+ ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
+ if (NMI->getOpcode() == ARM::t2MOVi32imm) {
+ MBBI = SplitT2MOV32imm(MBB, MBBI, NMI, ndl, NPredReg, NCC);
+ continue;
+ }
+
if (NCC == OCC) {
Mask |= (1 << Pos);
} else if (NCC != CC)
diff --git a/libclamav/c++/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/libclamav/c++/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 8c09ebd..264601b 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -383,6 +383,11 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
"Bit extraction didn't work?");
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
} else {
+
+ // AddrMode4 cannot handle any offset.
+ if (AddrMode == ARMII::AddrMode4)
+ return false;
+
// AddrModeT2_so cannot handle any offset. If there is no offset
// register then we change to an immediate version.
unsigned NewOpc = Opcode;
diff --git a/libclamav/c++/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/libclamav/c++/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
index c95b4c0..b8879d2 100644
--- a/libclamav/c++/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/libclamav/c++/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -79,6 +79,7 @@ namespace {
{ ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 0 },
{ ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 0 },
{ ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0 },
+ { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0 },
// FIXME: Do we need the 16-bit 'S' variant?
{ ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0 },
{ ARM::t2MOVCCr,0, ARM::tMOVCCr, 0, 0, 0, 0, 0,1, 0 },
@@ -262,7 +263,6 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
bool HasImmOffset = false;
bool HasShift = false;
bool isLdStMul = false;
- bool isPopPush = false;
unsigned Opc = Entry.NarrowOpc1;
unsigned OpNum = 3; // First 'rest' of operands.
switch (Entry.WideOpc) {
@@ -301,7 +301,6 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned Mode = MI->getOperand(1).getImm();
if (BaseReg == ARM::SP && ARM_AM::getAM4WBFlag(Mode)) {
Opc = Entry.NarrowOpc2;
- isPopPush = true;
OpNum = 2;
} else if (Entry.WideOpc == ARM::t2LDM_RET ||
!isARMLowRegister(BaseReg) ||
@@ -506,7 +505,7 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
return false;
} else if (MO.isImm() &&
!TID.OpInfo[i].isPredicate()) {
- if (MO.getImm() > Limit || (MO.getImm() & (Scale-1)) != 0)
+ if (((unsigned)MO.getImm()) > Limit || (MO.getImm() & (Scale-1)) != 0)
return false;
}
}
diff --git a/libclamav/c++/llvm/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/libclamav/c++/llvm/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
index 704a439..750cec9 100644
--- a/libclamav/c++/llvm/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
+++ b/libclamav/c++/llvm/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
@@ -31,9 +31,10 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
@@ -119,6 +120,8 @@ namespace {
/// machine instruction was sufficiently described to print it, otherwise it
/// returns false.
void printInstruction(const MachineInstr *MI);
+ static const char *getRegisterName(unsigned RegNo);
+
void printMachineInstruction(const MachineInstr *MI);
void printOp(const MachineOperand &MO);
@@ -148,7 +151,7 @@ namespace {
return;
}
- const char *RegName = TM.getRegisterInfo()->get(RegNo).AsmName;
+ const char *RegName = getRegisterName(RegNo);
// Linux assembler (Others?) does not take register mnemonics.
// FIXME - What about special registers used in mfspr/mtspr?
if (!Subtarget.isDarwin()) RegName = stripRegisterPrefix(RegName);
@@ -338,8 +341,6 @@ namespace {
const char *Modifier);
virtual bool runOnMachineFunction(MachineFunction &F) = 0;
-
- virtual void EmitExternalGlobal(const GlobalVariable *GV);
};
/// PPCLinuxAsmPrinter - PowerPC assembly printer, customized for Linux
@@ -380,8 +381,8 @@ namespace {
}
bool runOnMachineFunction(MachineFunction &F);
- bool doInitialization(Module &M);
bool doFinalization(Module &M);
+ void EmitStartOfAsmFile(Module &M);
void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
@@ -403,7 +404,7 @@ void PPCAsmPrinter::printOp(const MachineOperand &MO) {
llvm_unreachable("printOp() does not handle immediate values");
case MachineOperand::MO_MachineBasicBlock:
- printBasicBlockLabel(MO.getMBB());
+ GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
return;
case MachineOperand::MO_JumpTableIndex:
O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
@@ -459,19 +460,6 @@ void PPCAsmPrinter::printOp(const MachineOperand &MO) {
}
}
-/// EmitExternalGlobal - In this case we need to use the indirect symbol.
-///
-void PPCAsmPrinter::EmitExternalGlobal(const GlobalVariable *GV) {
- std::string Name;
-
- if (TM.getRelocationModel() != Reloc::Static) {
- Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
- } else {
- Name = Mang->getMangledName(GV);
- }
- O << Name;
-}
-
/// PrintAsmOperand - Print out an operand for an inline asm expression.
///
bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
@@ -556,6 +544,8 @@ void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
///
void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
++EmittedInsts;
+
+ processDebugLoc(MI);
// Check for slwi/srwi mnemonics.
if (MI->getOpcode() == PPC::RLWINM) {
@@ -601,6 +591,10 @@ void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
}
printInstruction(MI);
+
+ if (VerboseAsm && !MI->getDebugLoc().isUnknown())
+ EmitComments(*MI);
+ O << '\n';
}
/// runOnMachineFunction - This uses the printMachineInstruction()
@@ -663,7 +657,7 @@ bool PPCLinuxAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
I != E; ++I) {
// Print a label for the basic block.
if (I != MF.begin()) {
- printBasicBlockLabel(I, true, true);
+ EmitBasicBlockStart(I);
O << '\n';
}
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
@@ -847,7 +841,7 @@ bool PPCDarwinAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
I != E; ++I) {
// Print a label for the basic block.
if (I != MF.begin()) {
- printBasicBlockLabel(I, true, true, VerboseAsm);
+ EmitBasicBlockStart(I);
O << '\n';
}
for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
@@ -868,7 +862,7 @@ bool PPCDarwinAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
}
-bool PPCDarwinAsmPrinter::doInitialization(Module &M) {
+void PPCDarwinAsmPrinter::EmitStartOfAsmFile(Module &M) {
static const char *const CPUDirectives[] = {
"",
"ppc",
@@ -891,9 +885,6 @@ bool PPCDarwinAsmPrinter::doInitialization(Module &M) {
assert(Directive <= PPC::DIR_64 && "Directive out of range.");
O << "\t.machine " << CPUDirectives[Directive] << '\n';
- bool Result = AsmPrinter::doInitialization(M);
- assert(MMI);
-
// Prime text sections so they are adjacent. This reduces the likelihood a
// large data or debug section causes a branch to exceed 16M limit.
TargetLoweringObjectFileMachO &TLOFMacho =
@@ -913,8 +904,6 @@ bool PPCDarwinAsmPrinter::doInitialization(Module &M) {
16, SectionKind::getText()));
}
OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
-
- return Result;
}
void PPCDarwinAsmPrinter::PrintGlobalVariable(const GlobalVariable *GVar) {
diff --git a/libclamav/c++/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp b/libclamav/c++/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
index 16535b2..16d55a3 100644
--- a/libclamav/c++/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/libclamav/c++/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -90,7 +90,7 @@ namespace {
template <class CodeEmitter>
char Emitter<CodeEmitter>::ID = 0;
}
-
+
/// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
/// to the specified MCE object.
@@ -129,7 +129,7 @@ bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
template <class CodeEmitter>
void Emitter<CodeEmitter>::emitBasicBlock(MachineBasicBlock &MBB) {
MCE.StartMachineBasicBlock(&MBB);
-
+
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
const MachineInstr &MI = *I;
MCE.processDebugLoc(MI.getDebugLoc());
@@ -142,6 +142,7 @@ void Emitter<CodeEmitter>::emitBasicBlock(MachineBasicBlock &MBB) {
MCE.emitLabel(MI.getOperand(0).getImm());
break;
case TargetInstrInfo::IMPLICIT_DEF:
+ case TargetInstrInfo::KILL:
break; // pseudo opcode, no side effects
case PPC::MovePCtoLR:
case PPC::MovePCtoLR8:
@@ -202,7 +203,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
case PPC::LWZ8:
case PPC::LFS:
case PPC::LFD:
-
+
// Stores.
case PPC::STB:
case PPC::STB8:
@@ -223,7 +224,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
break;
}
}
-
+
MachineRelocation R;
if (MO.isGlobal()) {
R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
@@ -240,7 +241,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
Reloc, MO.getIndex(), 0);
}
-
+
// If in PIC mode, we need to encode the negated address of the
// 'movepctolr' into the unrelocated field. After relocation, we'll have
// &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
@@ -251,7 +252,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
R.setConstantVal(-(intptr_t)MovePCtoLROffset - 4);
}
MCE.addRelocation(R);
-
+
} else if (MO.isMBB()) {
unsigned Reloc = 0;
unsigned Opcode = MI.getOpcode();
diff --git a/libclamav/c++/llvm/lib/Target/PowerPC/PPCFrameInfo.h b/libclamav/c++/llvm/lib/Target/PowerPC/PPCFrameInfo.h
index c563637..65f113e 100644
--- a/libclamav/c++/llvm/lib/Target/PowerPC/PPCFrameInfo.h
+++ b/libclamav/c++/llvm/lib/Target/PowerPC/PPCFrameInfo.h
@@ -88,189 +88,189 @@ public:
}
// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
- const std::pair<unsigned, int> *
+ const SpillSlot *
getCalleeSavedSpillSlots(unsigned &NumEntries) const {
// Early exit if not using the SVR4 ABI.
if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()) {
NumEntries = 0;
return 0;
}
-
- static const std::pair<unsigned, int> Offsets[] = {
+
+ static const SpillSlot Offsets[] = {
// Floating-point register save area offsets.
- std::pair<unsigned, int>(PPC::F31, -8),
- std::pair<unsigned, int>(PPC::F30, -16),
- std::pair<unsigned, int>(PPC::F29, -24),
- std::pair<unsigned, int>(PPC::F28, -32),
- std::pair<unsigned, int>(PPC::F27, -40),
- std::pair<unsigned, int>(PPC::F26, -48),
- std::pair<unsigned, int>(PPC::F25, -56),
- std::pair<unsigned, int>(PPC::F24, -64),
- std::pair<unsigned, int>(PPC::F23, -72),
- std::pair<unsigned, int>(PPC::F22, -80),
- std::pair<unsigned, int>(PPC::F21, -88),
- std::pair<unsigned, int>(PPC::F20, -96),
- std::pair<unsigned, int>(PPC::F19, -104),
- std::pair<unsigned, int>(PPC::F18, -112),
- std::pair<unsigned, int>(PPC::F17, -120),
- std::pair<unsigned, int>(PPC::F16, -128),
- std::pair<unsigned, int>(PPC::F15, -136),
- std::pair<unsigned, int>(PPC::F14, -144),
-
+ {PPC::F31, -8},
+ {PPC::F30, -16},
+ {PPC::F29, -24},
+ {PPC::F28, -32},
+ {PPC::F27, -40},
+ {PPC::F26, -48},
+ {PPC::F25, -56},
+ {PPC::F24, -64},
+ {PPC::F23, -72},
+ {PPC::F22, -80},
+ {PPC::F21, -88},
+ {PPC::F20, -96},
+ {PPC::F19, -104},
+ {PPC::F18, -112},
+ {PPC::F17, -120},
+ {PPC::F16, -128},
+ {PPC::F15, -136},
+ {PPC::F14, -144},
+
// General register save area offsets.
- std::pair<unsigned, int>(PPC::R31, -4),
- std::pair<unsigned, int>(PPC::R30, -8),
- std::pair<unsigned, int>(PPC::R29, -12),
- std::pair<unsigned, int>(PPC::R28, -16),
- std::pair<unsigned, int>(PPC::R27, -20),
- std::pair<unsigned, int>(PPC::R26, -24),
- std::pair<unsigned, int>(PPC::R25, -28),
- std::pair<unsigned, int>(PPC::R24, -32),
- std::pair<unsigned, int>(PPC::R23, -36),
- std::pair<unsigned, int>(PPC::R22, -40),
- std::pair<unsigned, int>(PPC::R21, -44),
- std::pair<unsigned, int>(PPC::R20, -48),
- std::pair<unsigned, int>(PPC::R19, -52),
- std::pair<unsigned, int>(PPC::R18, -56),
- std::pair<unsigned, int>(PPC::R17, -60),
- std::pair<unsigned, int>(PPC::R16, -64),
- std::pair<unsigned, int>(PPC::R15, -68),
- std::pair<unsigned, int>(PPC::R14, -72),
+ {PPC::R31, -4},
+ {PPC::R30, -8},
+ {PPC::R29, -12},
+ {PPC::R28, -16},
+ {PPC::R27, -20},
+ {PPC::R26, -24},
+ {PPC::R25, -28},
+ {PPC::R24, -32},
+ {PPC::R23, -36},
+ {PPC::R22, -40},
+ {PPC::R21, -44},
+ {PPC::R20, -48},
+ {PPC::R19, -52},
+ {PPC::R18, -56},
+ {PPC::R17, -60},
+ {PPC::R16, -64},
+ {PPC::R15, -68},
+ {PPC::R14, -72},
// CR save area offset.
// FIXME SVR4: Disable CR save area for now.
-// std::pair<unsigned, int>(PPC::CR2, -4),
-// std::pair<unsigned, int>(PPC::CR3, -4),
-// std::pair<unsigned, int>(PPC::CR4, -4),
-// std::pair<unsigned, int>(PPC::CR2LT, -4),
-// std::pair<unsigned, int>(PPC::CR2GT, -4),
-// std::pair<unsigned, int>(PPC::CR2EQ, -4),
-// std::pair<unsigned, int>(PPC::CR2UN, -4),
-// std::pair<unsigned, int>(PPC::CR3LT, -4),
-// std::pair<unsigned, int>(PPC::CR3GT, -4),
-// std::pair<unsigned, int>(PPC::CR3EQ, -4),
-// std::pair<unsigned, int>(PPC::CR3UN, -4),
-// std::pair<unsigned, int>(PPC::CR4LT, -4),
-// std::pair<unsigned, int>(PPC::CR4GT, -4),
-// std::pair<unsigned, int>(PPC::CR4EQ, -4),
-// std::pair<unsigned, int>(PPC::CR4UN, -4),
+// {PPC::CR2, -4},
+// {PPC::CR3, -4},
+// {PPC::CR4, -4},
+// {PPC::CR2LT, -4},
+// {PPC::CR2GT, -4},
+// {PPC::CR2EQ, -4},
+// {PPC::CR2UN, -4},
+// {PPC::CR3LT, -4},
+// {PPC::CR3GT, -4},
+// {PPC::CR3EQ, -4},
+// {PPC::CR3UN, -4},
+// {PPC::CR4LT, -4},
+// {PPC::CR4GT, -4},
+// {PPC::CR4EQ, -4},
+// {PPC::CR4UN, -4},
// VRSAVE save area offset.
- std::pair<unsigned, int>(PPC::VRSAVE, -4),
-
+ {PPC::VRSAVE, -4},
+
// Vector register save area
- std::pair<unsigned, int>(PPC::V31, -16),
- std::pair<unsigned, int>(PPC::V30, -32),
- std::pair<unsigned, int>(PPC::V29, -48),
- std::pair<unsigned, int>(PPC::V28, -64),
- std::pair<unsigned, int>(PPC::V27, -80),
- std::pair<unsigned, int>(PPC::V26, -96),
- std::pair<unsigned, int>(PPC::V25, -112),
- std::pair<unsigned, int>(PPC::V24, -128),
- std::pair<unsigned, int>(PPC::V23, -144),
- std::pair<unsigned, int>(PPC::V22, -160),
- std::pair<unsigned, int>(PPC::V21, -176),
- std::pair<unsigned, int>(PPC::V20, -192)
+ {PPC::V31, -16},
+ {PPC::V30, -32},
+ {PPC::V29, -48},
+ {PPC::V28, -64},
+ {PPC::V27, -80},
+ {PPC::V26, -96},
+ {PPC::V25, -112},
+ {PPC::V24, -128},
+ {PPC::V23, -144},
+ {PPC::V22, -160},
+ {PPC::V21, -176},
+ {PPC::V20, -192}
};
-
- static const std::pair<unsigned, int> Offsets64[] = {
+
+ static const SpillSlot Offsets64[] = {
// Floating-point register save area offsets.
- std::pair<unsigned, int>(PPC::F31, -8),
- std::pair<unsigned, int>(PPC::F30, -16),
- std::pair<unsigned, int>(PPC::F29, -24),
- std::pair<unsigned, int>(PPC::F28, -32),
- std::pair<unsigned, int>(PPC::F27, -40),
- std::pair<unsigned, int>(PPC::F26, -48),
- std::pair<unsigned, int>(PPC::F25, -56),
- std::pair<unsigned, int>(PPC::F24, -64),
- std::pair<unsigned, int>(PPC::F23, -72),
- std::pair<unsigned, int>(PPC::F22, -80),
- std::pair<unsigned, int>(PPC::F21, -88),
- std::pair<unsigned, int>(PPC::F20, -96),
- std::pair<unsigned, int>(PPC::F19, -104),
- std::pair<unsigned, int>(PPC::F18, -112),
- std::pair<unsigned, int>(PPC::F17, -120),
- std::pair<unsigned, int>(PPC::F16, -128),
- std::pair<unsigned, int>(PPC::F15, -136),
- std::pair<unsigned, int>(PPC::F14, -144),
+ {PPC::F31, -8},
+ {PPC::F30, -16},
+ {PPC::F29, -24},
+ {PPC::F28, -32},
+ {PPC::F27, -40},
+ {PPC::F26, -48},
+ {PPC::F25, -56},
+ {PPC::F24, -64},
+ {PPC::F23, -72},
+ {PPC::F22, -80},
+ {PPC::F21, -88},
+ {PPC::F20, -96},
+ {PPC::F19, -104},
+ {PPC::F18, -112},
+ {PPC::F17, -120},
+ {PPC::F16, -128},
+ {PPC::F15, -136},
+ {PPC::F14, -144},
// General register save area offsets.
// FIXME 64-bit SVR4: Are 32-bit registers actually allocated in 64-bit
// mode?
- std::pair<unsigned, int>(PPC::R31, -4),
- std::pair<unsigned, int>(PPC::R30, -12),
- std::pair<unsigned, int>(PPC::R29, -20),
- std::pair<unsigned, int>(PPC::R28, -28),
- std::pair<unsigned, int>(PPC::R27, -36),
- std::pair<unsigned, int>(PPC::R26, -44),
- std::pair<unsigned, int>(PPC::R25, -52),
- std::pair<unsigned, int>(PPC::R24, -60),
- std::pair<unsigned, int>(PPC::R23, -68),
- std::pair<unsigned, int>(PPC::R22, -76),
- std::pair<unsigned, int>(PPC::R21, -84),
- std::pair<unsigned, int>(PPC::R20, -92),
- std::pair<unsigned, int>(PPC::R19, -100),
- std::pair<unsigned, int>(PPC::R18, -108),
- std::pair<unsigned, int>(PPC::R17, -116),
- std::pair<unsigned, int>(PPC::R16, -124),
- std::pair<unsigned, int>(PPC::R15, -132),
- std::pair<unsigned, int>(PPC::R14, -140),
+ {PPC::R31, -4},
+ {PPC::R30, -12},
+ {PPC::R29, -20},
+ {PPC::R28, -28},
+ {PPC::R27, -36},
+ {PPC::R26, -44},
+ {PPC::R25, -52},
+ {PPC::R24, -60},
+ {PPC::R23, -68},
+ {PPC::R22, -76},
+ {PPC::R21, -84},
+ {PPC::R20, -92},
+ {PPC::R19, -100},
+ {PPC::R18, -108},
+ {PPC::R17, -116},
+ {PPC::R16, -124},
+ {PPC::R15, -132},
+ {PPC::R14, -140},
- std::pair<unsigned, int>(PPC::X31, -8),
- std::pair<unsigned, int>(PPC::X30, -16),
- std::pair<unsigned, int>(PPC::X29, -24),
- std::pair<unsigned, int>(PPC::X28, -32),
- std::pair<unsigned, int>(PPC::X27, -40),
- std::pair<unsigned, int>(PPC::X26, -48),
- std::pair<unsigned, int>(PPC::X25, -56),
- std::pair<unsigned, int>(PPC::X24, -64),
- std::pair<unsigned, int>(PPC::X23, -72),
- std::pair<unsigned, int>(PPC::X22, -80),
- std::pair<unsigned, int>(PPC::X21, -88),
- std::pair<unsigned, int>(PPC::X20, -96),
- std::pair<unsigned, int>(PPC::X19, -104),
- std::pair<unsigned, int>(PPC::X18, -112),
- std::pair<unsigned, int>(PPC::X17, -120),
- std::pair<unsigned, int>(PPC::X16, -128),
- std::pair<unsigned, int>(PPC::X15, -136),
- std::pair<unsigned, int>(PPC::X14, -144),
+ {PPC::X31, -8},
+ {PPC::X30, -16},
+ {PPC::X29, -24},
+ {PPC::X28, -32},
+ {PPC::X27, -40},
+ {PPC::X26, -48},
+ {PPC::X25, -56},
+ {PPC::X24, -64},
+ {PPC::X23, -72},
+ {PPC::X22, -80},
+ {PPC::X21, -88},
+ {PPC::X20, -96},
+ {PPC::X19, -104},
+ {PPC::X18, -112},
+ {PPC::X17, -120},
+ {PPC::X16, -128},
+ {PPC::X15, -136},
+ {PPC::X14, -144},
// CR save area offset.
// FIXME SVR4: Disable CR save area for now.
-// std::pair<unsigned, int>(PPC::CR2, -4),
-// std::pair<unsigned, int>(PPC::CR3, -4),
-// std::pair<unsigned, int>(PPC::CR4, -4),
-// std::pair<unsigned, int>(PPC::CR2LT, -4),
-// std::pair<unsigned, int>(PPC::CR2GT, -4),
-// std::pair<unsigned, int>(PPC::CR2EQ, -4),
-// std::pair<unsigned, int>(PPC::CR2UN, -4),
-// std::pair<unsigned, int>(PPC::CR3LT, -4),
-// std::pair<unsigned, int>(PPC::CR3GT, -4),
-// std::pair<unsigned, int>(PPC::CR3EQ, -4),
-// std::pair<unsigned, int>(PPC::CR3UN, -4),
-// std::pair<unsigned, int>(PPC::CR4LT, -4),
-// std::pair<unsigned, int>(PPC::CR4GT, -4),
-// std::pair<unsigned, int>(PPC::CR4EQ, -4),
-// std::pair<unsigned, int>(PPC::CR4UN, -4),
+// {PPC::CR2, -4},
+// {PPC::CR3, -4},
+// {PPC::CR4, -4},
+// {PPC::CR2LT, -4},
+// {PPC::CR2GT, -4},
+// {PPC::CR2EQ, -4},
+// {PPC::CR2UN, -4},
+// {PPC::CR3LT, -4},
+// {PPC::CR3GT, -4},
+// {PPC::CR3EQ, -4},
+// {PPC::CR3UN, -4},
+// {PPC::CR4LT, -4},
+// {PPC::CR4GT, -4},
+// {PPC::CR4EQ, -4},
+// {PPC::CR4UN, -4},
// VRSAVE save area offset.
- std::pair<unsigned, int>(PPC::VRSAVE, -4),
+ {PPC::VRSAVE, -4},
// Vector register save area
- std::pair<unsigned, int>(PPC::V31, -16),
- std::pair<unsigned, int>(PPC::V30, -32),
- std::pair<unsigned, int>(PPC::V29, -48),
- std::pair<unsigned, int>(PPC::V28, -64),
- std::pair<unsigned, int>(PPC::V27, -80),
- std::pair<unsigned, int>(PPC::V26, -96),
- std::pair<unsigned, int>(PPC::V25, -112),
- std::pair<unsigned, int>(PPC::V24, -128),
- std::pair<unsigned, int>(PPC::V23, -144),
- std::pair<unsigned, int>(PPC::V22, -160),
- std::pair<unsigned, int>(PPC::V21, -176),
- std::pair<unsigned, int>(PPC::V20, -192)
+ {PPC::V31, -16},
+ {PPC::V30, -32},
+ {PPC::V29, -48},
+ {PPC::V28, -64},
+ {PPC::V27, -80},
+ {PPC::V26, -96},
+ {PPC::V25, -112},
+ {PPC::V24, -128},
+ {PPC::V23, -144},
+ {PPC::V22, -160},
+ {PPC::V21, -176},
+ {PPC::V20, -192}
};
-
+
if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
NumEntries = array_lengthof(Offsets64);
diff --git a/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 356ca32..8fa6a66 100644
--- a/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -469,7 +469,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
SH &= 31;
SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
getI32Imm(ME) };
- return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
+ return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
}
}
return 0;
@@ -488,12 +488,12 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
if (isInt32Immediate(RHS, Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
- getI32Imm(Imm & 0xFFFF)), 0);
+ return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
+ getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16((int)Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
- getI32Imm(Imm & 0xFFFF)), 0);
+ return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
+ getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
// constant, then compare against it, like this:
@@ -504,22 +504,22 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
// xoris r0,r3,0x1234
// cmplwi cr0,r0,0x5678
// beq cr0,L6
- SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, MVT::i32, LHS,
- getI32Imm(Imm >> 16)), 0);
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, Xor,
- getI32Imm(Imm & 0xFFFF)), 0);
+ SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
+ getI32Imm(Imm >> 16)), 0);
+ return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
+ getI32Imm(Imm & 0xFFFF)), 0);
}
Opc = PPC::CMPLW;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
- getI32Imm(Imm & 0xFFFF)), 0);
+ return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
+ getI32Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLW;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
- getI32Imm((int)SImm & 0xFFFF)),
+ return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
+ getI32Imm((int)SImm & 0xFFFF)),
0);
Opc = PPC::CMPW;
}
@@ -529,12 +529,12 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
if (isInt64Immediate(RHS.getNode(), Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
- getI32Imm(Imm & 0xFFFF)), 0);
+ return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
+ getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
- getI32Imm(Imm & 0xFFFF)), 0);
+ return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
+ getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
// constant, then compare against it, like this:
@@ -546,23 +546,23 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
// cmpldi cr0,r0,0x5678
// beq cr0,L6
if (isUInt32(Imm)) {
- SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, MVT::i64, LHS,
- getI64Imm(Imm >> 16)), 0);
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, Xor,
- getI64Imm(Imm & 0xFFFF)), 0);
+ SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
+ getI64Imm(Imm >> 16)), 0);
+ return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
+ getI64Imm(Imm & 0xFFFF)), 0);
}
}
Opc = PPC::CMPLD;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
- getI64Imm(Imm & 0xFFFF)), 0);
+ return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
+ getI64Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLD;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
- getI64Imm(SImm & 0xFFFF)),
+ return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
+ getI64Imm(SImm & 0xFFFF)),
0);
Opc = PPC::CMPD;
}
@@ -572,7 +572,7 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
Opc = PPC::FCMPUD;
}
- return SDValue(CurDAG->getTargetNode(Opc, dl, MVT::i32, LHS, RHS), 0);
+ return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
}
static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
@@ -654,14 +654,14 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
switch (CC) {
default: break;
case ISD::SETEQ: {
- Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
+ Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETNE: {
SDValue AD =
- SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
- Op, getI32Imm(~0U)), 0);
+ SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
+ Op, getI32Imm(~0U)), 0);
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
AD.getValue(1));
}
@@ -671,8 +671,8 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
}
case ISD::SETGT: {
SDValue T =
- SDValue(CurDAG->getTargetNode(PPC::NEG, dl, MVT::i32, Op), 0);
- T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
+ SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
+ T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
@@ -682,31 +682,31 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
switch (CC) {
default: break;
case ISD::SETEQ:
- Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
- Op, getI32Imm(1)), 0);
+ Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
+ Op, getI32Imm(1)), 0);
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
- SDValue(CurDAG->getTargetNode(PPC::LI, dl,
- MVT::i32,
- getI32Imm(0)), 0),
+ SDValue(CurDAG->getMachineNode(PPC::LI, dl,
+ MVT::i32,
+ getI32Imm(0)), 0),
Op.getValue(1));
case ISD::SETNE: {
- Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
- SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
- Op, getI32Imm(~0U));
+ Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
+ SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
+ Op, getI32Imm(~0U));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
Op, SDValue(AD, 1));
}
case ISD::SETLT: {
- SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, MVT::i32, Op,
- getI32Imm(1)), 0);
- SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, MVT::i32, AD,
- Op), 0);
+ SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
+ getI32Imm(1)), 0);
+ SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
+ Op), 0);
SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETGT: {
SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
- Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
+ Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
0);
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
getI32Imm(1));
@@ -729,10 +729,10 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
InFlag).getValue(1);
if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
- IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
- CCReg), 0);
+ IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
+ CCReg), 0);
else
- IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, CCReg), 0);
+ IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCR, dl, MVT::i32, CCReg), 0);
SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
getI32Imm(31), getI32Imm(31) };
@@ -741,7 +741,7 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
// Get the specified bit.
SDValue Tmp =
- SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
+ SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
if (Inv) {
assert(OtherCondIdx == -1 && "Can't have split plus negation");
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
@@ -753,7 +753,7 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
// Get the other bit of the comparison.
Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
SDValue OtherCond =
- SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
+ SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
}
@@ -806,17 +806,17 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
// Simple value.
if (isInt16(Imm)) {
// Just the Lo bits.
- Result = CurDAG->getTargetNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
+ Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
} else if (Lo) {
// Handle the Hi bits.
unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
- Result = CurDAG->getTargetNode(OpC, dl, MVT::i64, getI32Imm(Hi));
+ Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
// And Lo bits.
- Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
- SDValue(Result, 0), getI32Imm(Lo));
+ Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
+ SDValue(Result, 0), getI32Imm(Lo));
} else {
// Just the Hi bits.
- Result = CurDAG->getTargetNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
+ Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
}
// If no shift, we're done.
@@ -824,19 +824,20 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
// Shift for next step if the upper 32-bits were not zero.
if (Imm) {
- Result = CurDAG->getTargetNode(PPC::RLDICR, dl, MVT::i64,
- SDValue(Result, 0),
- getI32Imm(Shift), getI32Imm(63 - Shift));
+ Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
+ SDValue(Result, 0),
+ getI32Imm(Shift),
+ getI32Imm(63 - Shift));
}
// Add in the last bits as required.
if ((Hi = (Remainder >> 16) & 0xFFFF)) {
- Result = CurDAG->getTargetNode(PPC::ORIS8, dl, MVT::i64,
- SDValue(Result, 0), getI32Imm(Hi));
+ Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
+ SDValue(Result, 0), getI32Imm(Hi));
}
if ((Lo = Remainder & 0xFFFF)) {
- Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
- SDValue(Result, 0), getI32Imm(Lo));
+ Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
+ SDValue(Result, 0), getI32Imm(Lo));
}
return Result;
@@ -856,18 +857,18 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
getSmallIPtrImm(0));
- return CurDAG->getTargetNode(Opc, dl, Op.getValueType(), TFI,
- getSmallIPtrImm(0));
+ return CurDAG->getMachineNode(Opc, dl, Op.getValueType(), TFI,
+ getSmallIPtrImm(0));
}
case PPCISD::MFCR: {
SDValue InFlag = N->getOperand(1);
// Use MFOCRF if supported.
if (PPCSubTarget.isGigaProcessor())
- return CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32,
- N->getOperand(0), InFlag);
+ return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
+ N->getOperand(0), InFlag);
else
- return CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, InFlag);
+ return CurDAG->getMachineNode(PPC::MFCR, dl, MVT::i32, InFlag);
}
case ISD::SDIV: {
@@ -881,17 +882,17 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
SDValue N0 = N->getOperand(0);
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
SDNode *Op =
- CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
- N0, getI32Imm(Log2_32(Imm)));
+ CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
+ N0, getI32Imm(Log2_32(Imm)));
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
SDValue(Op, 0), SDValue(Op, 1));
} else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
SDNode *Op =
- CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
- N0, getI32Imm(Log2_32(-Imm)));
+ CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
+ N0, getI32Imm(Log2_32(-Imm)));
SDValue PT =
- SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, MVT::i32,
- SDValue(Op, 0), SDValue(Op, 1)),
+ SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
+ SDValue(Op, 0), SDValue(Op, 1)),
0);
return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
}
@@ -945,9 +946,9 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
SDValue Base = LD->getBasePtr();
SDValue Ops[] = { Offset, Base, Chain };
// FIXME: PPC64
- return CurDAG->getTargetNode(Opcode, dl, LD->getValueType(0),
- PPCLowering.getPointerTy(),
- MVT::Other, Ops, 3);
+ return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
+ PPCLowering.getPointerTy(),
+ MVT::Other, Ops, 3);
} else {
llvm_unreachable("R+R preindex loads not supported yet!");
}
@@ -989,7 +990,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
SDValue Ops[] = { N->getOperand(0).getOperand(0),
N->getOperand(0).getOperand(1),
getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
- return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
+ return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
}
}
@@ -1039,8 +1040,8 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
// FIXME: Implement this optzn for PPC64.
N->getValueType(0) == MVT::i32) {
SDNode *Tmp =
- CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
- N->getOperand(0), getI32Imm(~0U));
+ CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
+ N->getOperand(0), getI32Imm(~0U));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
SDValue(Tmp, 0), N->getOperand(0),
SDValue(Tmp, 1));
@@ -1090,8 +1091,8 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
SDValue Chain = N->getOperand(0);
SDValue Target = N->getOperand(1);
unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
- Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Target,
- Chain), 0);
+ Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
+ Chain), 0);
return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
}
}
diff --git a/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index ad9bbe1..3920b38 100644
--- a/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -909,7 +909,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
- Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0);
+ Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
return true;
}
}
@@ -1021,7 +1021,7 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
- Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0);
+ Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
return true;
}
}
@@ -1484,7 +1484,7 @@ static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
SDValue
PPCTargetLowering::LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg>
&Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -1501,7 +1501,7 @@ PPCTargetLowering::LowerFormalArguments(SDValue Chain,
SDValue
PPCTargetLowering::LowerFormalArguments_SVR4(
SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg>
&Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -1728,7 +1728,7 @@ PPCTargetLowering::LowerFormalArguments_SVR4(
SDValue
PPCTargetLowering::LowerFormalArguments_Darwin(
SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg>
&Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -2164,7 +2164,7 @@ static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
/// optimization should implement this function.
bool
PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
- unsigned CalleeCC,
+ CallingConv::ID CalleeCC,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const {
@@ -2173,7 +2173,7 @@ PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
return false;
MachineFunction &MF = DAG.getMachineFunction();
- unsigned CallerCC = MF.getFunction()->getCallingConv();
+ CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
// Functions containing by val parameters are not supported.
for (unsigned i = 0; i != Ins.size(); i++) {
@@ -2453,7 +2453,7 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
SDValue
PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) {
@@ -2478,8 +2478,8 @@ PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
}
SDValue
-PPCTargetLowering::FinishCall(unsigned CallConv, DebugLoc dl, bool isTailCall,
- bool isVarArg,
+PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
+ bool isTailCall, bool isVarArg,
SelectionDAG &DAG,
SmallVector<std::pair<unsigned, SDValue>, 8>
&RegsToPass,
@@ -2554,7 +2554,7 @@ PPCTargetLowering::FinishCall(unsigned CallConv, DebugLoc dl, bool isTailCall,
SDValue
PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -2573,7 +2573,7 @@ PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
SDValue
PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -2765,7 +2765,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
// Set CR6 to true if this is a vararg call.
if (isVarArg) {
- SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
+ SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0);
Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
InFlag = Chain.getValue(1);
}
@@ -2782,7 +2782,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
SDValue
PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -2876,7 +2876,6 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
SmallVector<SDValue, 8> MemOpChains;
for (unsigned i = 0; i != NumOps; ++i) {
- bool inMem = false;
SDValue Arg = Outs[i].Val;
ISD::ArgFlagsTy Flags = Outs[i].Flags;
@@ -2963,7 +2962,6 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
isPPC64, isTailCall, false, MemOpChains,
TailCallArguments, dl);
- inMem = true;
}
ArgOffset += PtrByteSize;
break;
@@ -3003,7 +3001,6 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
isPPC64, isTailCall, false, MemOpChains,
TailCallArguments, dl);
- inMem = true;
}
if (isPPC64)
ArgOffset += 8;
@@ -3116,7 +3113,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
SDValue
PPCTargetLowering::LowerReturn(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) {
@@ -3380,7 +3377,8 @@ SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
// 64-bit registers. In particular, sign extend the input value into the
// 64-bit register with extsw, store the WHOLE 64-bit value into the stack
// then lfd it and fcfid it.
- MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo *FrameInfo = MF.getFrameInfo();
int FrameIdx = FrameInfo->CreateStackObject(8, 8);
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
@@ -3389,11 +3387,13 @@ SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
Op.getOperand(0));
// STD the extended value into the stack slot.
- MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
- MachineMemOperand::MOStore, 0, 8, 8);
- SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other,
- DAG.getEntryNode(), Ext64, FIdx,
- DAG.getMemOperand(MO));
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
+ MachineMemOperand::MOStore, 0, 8, 8);
+ SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
+ SDValue Store =
+ DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
+ Ops, 4, MVT::i64, MMO);
// Load the value as a double.
SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
@@ -4491,7 +4491,8 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
MachineBasicBlock *
PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
- MachineBasicBlock *BB) const {
+ MachineBasicBlock *BB,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
// To "insert" these instructions we actually have to insert their
@@ -4527,9 +4528,18 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
- // Update machine-CFG edges by transferring all successors of the current
+ // Update machine-CFG edges by first adding all successors of the current
// block to the new block which will contain the Phi node for the select.
- sinkMBB->transferSuccessors(BB);
+ // Also inform sdisel of the edge changes.
+ for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
+ E = BB->succ_end(); I != E; ++I) {
+ EM->insert(std::make_pair(*I, sinkMBB));
+ sinkMBB->addSuccessor(*I);
+ }
+ // Next, remove all successors of the current block, and add the true
+ // and fallthrough blocks as its successors.
+ while (!BB->succ_empty())
+ BB->removeSuccessor(BB->succ_begin());
// Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);
@@ -4914,7 +4924,8 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
}
// Turn STORE (BSWAP) -> sthbrx/stwbrx.
- if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
+ if (cast<StoreSDNode>(N)->isUnindexed() &&
+ N->getOperand(1).getOpcode() == ISD::BSWAP &&
N->getOperand(1).getNode()->hasOneUse() &&
(N->getOperand(1).getValueType() == MVT::i32 ||
N->getOperand(1).getValueType() == MVT::i16)) {
@@ -4923,9 +4934,15 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
if (BSwapOp.getValueType() == MVT::i16)
BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
- return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0),
- BSwapOp, N->getOperand(2), N->getOperand(3),
- DAG.getValueType(N->getOperand(1).getValueType()));
+ SDValue Ops[] = {
+ N->getOperand(0), BSwapOp, N->getOperand(2),
+ DAG.getValueType(N->getOperand(1).getValueType())
+ };
+ return
+ DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
+ Ops, array_lengthof(Ops),
+ cast<StoreSDNode>(N)->getMemoryVT(),
+ cast<StoreSDNode>(N)->getMemOperand());
}
break;
case ISD::BSWAP:
@@ -4936,17 +4953,15 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
SDValue Load = N->getOperand(0);
LoadSDNode *LD = cast<LoadSDNode>(Load);
// Create the byte-swapping load.
- std::vector<EVT> VTs;
- VTs.push_back(MVT::i32);
- VTs.push_back(MVT::Other);
- SDValue MO = DAG.getMemOperand(LD->getMemOperand());
SDValue Ops[] = {
LD->getChain(), // Chain
LD->getBasePtr(), // Ptr
- MO, // MemOperand
DAG.getValueType(N->getValueType(0)) // VT
};
- SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4);
+ SDValue BSLoad =
+ DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
+ DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
+ LD->getMemoryVT(), LD->getMemOperand());
// If this is an i16 load, insert the truncate.
SDValue ResVal = BSLoad;
@@ -5101,7 +5116,7 @@ void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
default: break;
case PPCISD::LBRX: {
// lhbrx is known to have the top bits cleared out.
- if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
+ if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
KnownZero = 0xFFFF0000;
break;
}
diff --git a/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelLowering.h b/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 19fef4d..ac72d87 100644
--- a/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/libclamav/c++/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -41,8 +41,7 @@ namespace llvm {
FCTIDZ, FCTIWZ,
/// STFIWX - The STFIWX instruction. The first operand is an input token
- /// chain, then an f64 value to store, then an address to store it to,
- /// then a SRCVALUE for the address.
+ /// chain, then an f64 value to store, then an address to store it to.
STFIWX,
// VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
@@ -80,9 +79,6 @@ namespace llvm {
/// registers.
EXTSW_32,
- /// STD_32 - This is the STD instruction for use with "32-bit" registers.
- STD_32,
-
/// CALL - A direct function call.
CALL_Darwin, CALL_SVR4,
@@ -124,18 +120,6 @@ namespace llvm {
/// an optional input flag argument.
COND_BRANCH,
- /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a
- /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
- /// the GPRC input, then stores it through Ptr. Type can be either i16 or
- /// i32.
- STBRX,
-
- /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a
- /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
- /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
- /// or i32.
- LBRX,
-
// The following 5 instructions are used only as part of the
// long double-to-int conversion sequence.
@@ -170,7 +154,22 @@ namespace llvm {
/// operand #1 callee (register or absolute)
/// operand #2 stack adjustment
/// operand #3 optional in flag
- TC_RETURN
+ TC_RETURN,
+
+ /// STD_32 - This is the STD instruction for use with "32-bit" registers.
+ STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
+
+ /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
+ /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
+ /// the GPRC input, then stores it through Ptr. Type can be either i16 or
+ /// i32.
+ STBRX,
+
+ /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
+ /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
+ /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
+ /// or i32.
+ LBRX
};
}
@@ -289,7 +288,8 @@ namespace llvm {
unsigned Depth = 0) const;
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
- MachineBasicBlock *MBB) const;
+ MachineBasicBlock *MBB,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
MachineBasicBlock *MBB, bool is64Bit,
unsigned BinOpcode) const;
@@ -332,7 +332,7 @@ namespace llvm {
virtual bool
IsEligibleForTailCallOptimization(SDValue Callee,
- unsigned CalleeCC,
+ CallingConv::ID CalleeCC,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const;
@@ -391,11 +391,11 @@ namespace llvm {
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
- SDValue FinishCall(unsigned CallConv, DebugLoc dl, bool isTailCall,
+ SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
bool isVarArg,
SelectionDAG &DAG,
SmallVector<std::pair<unsigned, SDValue>, 8>
@@ -408,14 +408,14 @@ namespace llvm {
virtual SDValue
LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
virtual SDValue
LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg, bool isTailCall,
+ CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -423,33 +423,33 @@ namespace llvm {
virtual SDValue
LowerReturn(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG);
SDValue
LowerFormalArguments_Darwin(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
SDValue
LowerFormalArguments_SVR4(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
SDValue
LowerCall_Darwin(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg, bool isTailCall,
+ CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
SDValue
LowerCall_SVR4(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg, bool isTailCall,
+ CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
diff --git a/libclamav/c++/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/libclamav/c++/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 85524ce..0f68fb9 100644
--- a/libclamav/c++/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/libclamav/c++/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -68,7 +68,7 @@ let isCall = 1, PPC970_Unit = 7,
F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
LR8,CTR8,
- CR0,CR1,CR5,CR6,CR7] in {
+ CR0,CR1,CR5,CR6,CR7,CARRY] in {
// Convenient aliases for call instructions
let Uses = [RM] in {
def BL8_Darwin : IForm<18, 0, 1,
@@ -94,7 +94,7 @@ let isCall = 1, PPC970_Unit = 7,
F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
LR8,CTR8,
- CR0,CR1,CR5,CR6,CR7] in {
+ CR0,CR1,CR5,CR6,CR7,CARRY] in {
// Convenient aliases for call instructions
let Uses = [RM] in {
def BL8_ELF : IForm<18, 0, 1,
@@ -329,14 +329,15 @@ def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
"add $rT, $rA, $rB", IntGeneral,
[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
+let Defs = [CARRY] in {
def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
"addc $rT, $rA, $rB", IntGeneral,
[(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
PPC970_DGroup_Cracked;
-def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
- "adde $rT, $rA, $rB", IntGeneral,
- [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
-
+def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
+ "addic $rD, $rA, $imm", IntGeneral,
+ [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>;
+}
def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
"addi $rD, $rA, $imm", IntGeneral,
[(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
@@ -344,36 +345,41 @@ def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
"addis $rD, $rA, $imm", IntGeneral,
[(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
+let Defs = [CARRY] in {
def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
"subfic $rD, $rA, $imm", IntGeneral,
[(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
-def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
- "subf $rT, $rA, $rB", IntGeneral,
- [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
"subfc $rT, $rA, $rB", IntGeneral,
[(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
PPC970_DGroup_Cracked;
-
-def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
- "subfe $rT, $rA, $rB", IntGeneral,
- [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
+}
+def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
+ "subf $rT, $rA, $rB", IntGeneral,
+ [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
+def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
+ "neg $rT, $rA", IntGeneral,
+ [(set G8RC:$rT, (ineg G8RC:$rA))]>;
+let Uses = [CARRY], Defs = [CARRY] in {
+def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
+ "adde $rT, $rA, $rB", IntGeneral,
+ [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
"addme $rT, $rA", IntGeneral,
[(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]>;
def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
"addze $rT, $rA", IntGeneral,
[(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
-def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
- "neg $rT, $rA", IntGeneral,
- [(set G8RC:$rT, (ineg G8RC:$rA))]>;
+def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
+ "subfe $rT, $rA, $rB", IntGeneral,
+ [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
"subfme $rT, $rA", IntGeneral,
[(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]>;
def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
"subfze $rT, $rA", IntGeneral,
[(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
-
+}
def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
@@ -398,9 +404,11 @@ def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
"srd $rA, $rS, $rB", IntRotateD,
[(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
+let Defs = [CARRY] in {
def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
"srad $rA, $rS, $rB", IntRotateD,
[(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
+}
def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
"extsb $rA, $rS", IntGeneral,
@@ -420,9 +428,11 @@ def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
"extsw $rA, $rS", IntGeneral,
[(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
+let Defs = [CARRY] in {
def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
"sradi $rA, $rS, $SH", IntRotateD,
[(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
+}
def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
"cntlzd $rA, $rS", IntGeneral,
[(set G8RC:$rA, (ctlz G8RC:$rS))]>;
diff --git a/libclamav/c++/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/libclamav/c++/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 3c32c4a..dc5db6f 100644
--- a/libclamav/c++/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/libclamav/c++/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -35,11 +35,11 @@ def SDT_PPCcondbr : SDTypeProfile<0, 3, [
SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
]>;
-def SDT_PPClbrx : SDTypeProfile<1, 3, [
- SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
+def SDT_PPClbrx : SDTypeProfile<1, 2, [
+ SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
]>;
-def SDT_PPCstbrx : SDTypeProfile<0, 4, [
- SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
+def SDT_PPCstbrx : SDTypeProfile<0, 3, [
+ SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
]>;
def SDT_PPClarx : SDTypeProfile<1, 1, [
@@ -426,7 +426,7 @@ let isCall = 1, PPC970_Unit = 7,
LR,CTR,
CR0,CR1,CR5,CR6,CR7,
CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
- CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
+ CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN,CARRY] in {
// Convenient aliases for call instructions
let Uses = [RM] in {
def BL_Darwin : IForm<18, 0, 1,
@@ -453,7 +453,7 @@ let isCall = 1, PPC970_Unit = 7,
LR,CTR,
CR0,CR1,CR5,CR6,CR7,
CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
- CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
+ CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN,CARRY] in {
// Convenient aliases for call instructions
let Uses = [RM] in {
def BL_SVR4 : IForm<18, 0, 1,
@@ -741,10 +741,10 @@ def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
"lhbrx $rD, $src", LdStGeneral,
- [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
+ [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
"lwbrx $rD, $src", LdStGeneral,
- [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
+ [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
"lfsx $frD, $src", LdStLFDU,
@@ -837,11 +837,11 @@ def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
}
def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
"sthbrx $rS, $dst", LdStGeneral,
- [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
+ [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
PPC970_DGroup_Cracked;
def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
"stwbrx $rS, $dst", LdStGeneral,
- [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
+ [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
PPC970_DGroup_Cracked;
def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
@@ -869,6 +869,7 @@ let PPC970_Unit = 1 in { // FXU Operations.
def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
"addi $rD, $rA, $imm", IntGeneral,
[(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
+let Defs = [CARRY] in {
def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
"addic $rD, $rA, $imm", IntGeneral,
[(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
@@ -876,6 +877,7 @@ def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
"addic. $rD, $rA, $imm", IntGeneral,
[]>;
+}
def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
"addis $rD, $rA, $imm", IntGeneral,
[(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
@@ -886,9 +888,11 @@ def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
"mulli $rD, $rA, $imm", IntMulLI,
[(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
+let Defs = [CARRY] in {
def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
"subfic $rD, $rA, $imm", IntGeneral,
[(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
+}
let isReMaterializable = 1 in {
def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
@@ -961,15 +965,19 @@ def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
"srw $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
+let Defs = [CARRY] in {
def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
"sraw $rA, $rS, $rB", IntShift,
[(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
}
+}
let PPC970_Unit = 1 in { // FXU Operations.
+let Defs = [CARRY] in {
def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
"srawi $rA, $rS, $SH", IntShift,
[(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
+}
def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
"cntlzw $rA, $rS", IntGeneral,
[(set GPRC:$rA, (ctlz GPRC:$rS))]>;
@@ -1164,13 +1172,12 @@ let PPC970_Unit = 1 in { // FXU Operations.
def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
"add $rT, $rA, $rB", IntGeneral,
[(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
+let Defs = [CARRY] in {
def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
"addc $rT, $rA, $rB", IntGeneral,
[(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
PPC970_DGroup_Cracked;
-def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
- "adde $rT, $rA, $rB", IntGeneral,
- [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
+}
def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
"divw $rT, $rA, $rB", IntDivW,
[(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
@@ -1191,22 +1198,28 @@ def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
"subf $rT, $rA, $rB", IntGeneral,
[(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
+let Defs = [CARRY] in {
def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
"subfc $rT, $rA, $rB", IntGeneral,
[(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
PPC970_DGroup_Cracked;
-def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
- "subfe $rT, $rA, $rB", IntGeneral,
- [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
+}
+def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
+ "neg $rT, $rA", IntGeneral,
+ [(set GPRC:$rT, (ineg GPRC:$rA))]>;
+let Uses = [CARRY], Defs = [CARRY] in {
+def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
+ "adde $rT, $rA, $rB", IntGeneral,
+ [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
"addme $rT, $rA", IntGeneral,
[(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
"addze $rT, $rA", IntGeneral,
[(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
-def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
- "neg $rT, $rA", IntGeneral,
- [(set GPRC:$rT, (ineg GPRC:$rA))]>;
+def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
+ "subfe $rT, $rA, $rB", IntGeneral,
+ [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
"subfme $rT, $rA", IntGeneral,
[(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
@@ -1214,6 +1227,7 @@ def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
"subfze $rT, $rA", IntGeneral,
[(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
}
+}
// A-Form instructions. Most of the instructions executed in the FPU are of
// this type.
diff --git a/libclamav/c++/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/libclamav/c++/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 140f5df..049e893 100644
--- a/libclamav/c++/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/libclamav/c++/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -255,6 +255,11 @@ def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>;
// VRsave register
def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[107]>;
+// Carry bit. In the architecture this is really bit 0 of the XER register
+// (which really is SPR register 1); this is the only bit interesting to a
+// compiler.
+def CARRY: SPR<1, "ca">, DwarfRegNum<[0]>;
+
// FP rounding mode: bits 30 and 31 of the FP status and control register
// This is not allocated as a normal register; it appears only in
// Uses and Defs. The ABI says it needs to be preserved by a function,
@@ -377,3 +382,6 @@ def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,
def CTRRC : RegisterClass<"PPC", [i32], 32, [CTR]>;
def CTRRC8 : RegisterClass<"PPC", [i64], 64, [CTR8]>;
def VRSAVERC : RegisterClass<"PPC", [i32], 32, [VRSAVE]>;
+def CARRYRC : RegisterClass<"PPC", [i32], 32, [CARRY]> {
+ let CopyCost = -1;
+}
diff --git a/libclamav/c++/llvm/lib/Target/README.txt b/libclamav/c++/llvm/lib/Target/README.txt
index 97546c4..89ea9d0 100644
--- a/libclamav/c++/llvm/lib/Target/README.txt
+++ b/libclamav/c++/llvm/lib/Target/README.txt
@@ -220,7 +220,20 @@ so cool to turn it into something like:
... which would only do one 32-bit XOR per loop iteration instead of two.
It would also be nice to recognize the reg->size doesn't alias reg->node[i], but
-alas...
+alas.
+
+//===---------------------------------------------------------------------===//
+
+This should be optimized to one 'and' and one 'or', from PR4216:
+
+define i32 @test_bitfield(i32 %bf.prev.low) nounwind ssp {
+entry:
+ %bf.prev.lo.cleared10 = or i32 %bf.prev.low, 32962 ; <i32> [#uses=1]
+ %0 = and i32 %bf.prev.low, -65536 ; <i32> [#uses=1]
+ %1 = and i32 %bf.prev.lo.cleared10, 40186 ; <i32> [#uses=1]
+ %2 = or i32 %1, %0 ; <i32> [#uses=1]
+ ret i32 %2
+}
//===---------------------------------------------------------------------===//
@@ -337,24 +350,22 @@ void foo(int N) {
for (i = 0; i < N; i++) { X = i; Y = i*4; }
}
-produces two identical IV's (after promotion) on PPC/ARM:
+produces two near identical IV's (after promotion) on PPC/ARM:
+
+LBB1_2:
+ ldr r3, LCPI1_0
+ ldr r3, [r3]
+ strh r2, [r3]
+ ldr r3, LCPI1_1
+ ldr r3, [r3]
+ strh r1, [r3]
+ add r1, r1, #4
+ add r2, r2, #1 <- [0,+,1]
+ sub r0, r0, #1 <- [0,-,1]
+ cmp r0, #0
+ bne LBB1_2
-LBB1_1: @bb.preheader
- mov r3, #0
- mov r2, r3
- mov r1, r3
-LBB1_2: @bb
- ldr r12, LCPI1_0
- ldr r12, [r12]
- strh r2, [r12]
- ldr r12, LCPI1_1
- ldr r12, [r12]
- strh r3, [r12]
- add r1, r1, #1 <- [0,+,1]
- add r3, r3, #4
- add r2, r2, #1 <- [0,+,1]
- cmp r1, r0
- bne LBB1_2 @bb
+LSR should reuse the "+" IV for the exit test.
//===---------------------------------------------------------------------===//
@@ -588,25 +599,6 @@ implementations of ceil/floor/rint.
//===---------------------------------------------------------------------===//
-This GCC bug: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34043
-contains a testcase that compiles down to:
-
- %struct.XMM128 = type { <4 x float> }
-..
- %src = alloca %struct.XMM128
-..
- %tmp6263 = bitcast %struct.XMM128* %src to <2 x i64>*
- %tmp65 = getelementptr %struct.XMM128* %src, i32 0, i32 0
- store <2 x i64> %tmp5899, <2 x i64>* %tmp6263, align 16
- %tmp66 = load <4 x float>* %tmp65, align 16
- %tmp71 = add <4 x float> %tmp66, %tmp66
-
-If the mid-level optimizer turned the bitcast of pointer + store of tmp5899
-into a bitcast of the vector value and a store to the pointer, then the
-store->load could be easily removed.
-
-//===---------------------------------------------------------------------===//
-
Consider:
int test() {
@@ -1289,6 +1281,8 @@ http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35287 [LPRE crit edge splitting]
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34677 (licm does this, LPRE crit edge)
llvm-gcc t2.c -S -o - -O0 -emit-llvm | llvm-as | opt -mem2reg -simplifycfg -gvn | llvm-dis
+http://gcc.gnu.org/bugzilla/show_bug.cgi?id=16799 [BITCAST PHI TRANS]
+
//===---------------------------------------------------------------------===//
Type based alias analysis:
@@ -1296,31 +1290,25 @@ http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14705
//===---------------------------------------------------------------------===//
-When GVN/PRE finds a store of float* to a must aliases pointer when expecting
-an int*, it should turn it into a bitcast. This is a nice generalization of
-the SROA hack that would apply to other cases, e.g.:
-
-int foo(int C, int *P, float X) {
- if (C) {
- bar();
- *P = 42;
- } else
- *(float*)P = X;
-
- return *P;
-}
-
-
-One example (that requires crazy phi translation) is:
-http://gcc.gnu.org/bugzilla/show_bug.cgi?id=16799 [BITCAST PHI TRANS]
-
-//===---------------------------------------------------------------------===//
-
A/B get pinned to the stack because we turn an if/then into a select instead
of PRE'ing the load/store. This may be fixable in instcombine:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37892
+struct X { int i; };
+int foo (int x) {
+ struct X a;
+ struct X b;
+ struct X *p;
+ a.i = 1;
+ b.i = 2;
+ if (x)
+ p = &a;
+ else
+ p = &b;
+ return p->i;
+}
+//===---------------------------------------------------------------------===//
Interesting missed case because of control flow flattening (should be 2 loads):
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=26629
@@ -1653,27 +1641,6 @@ entry:
Instcombine should be able to optimize away the loads (and thus the globals).
-
-//===---------------------------------------------------------------------===//
-
-I saw this constant expression in real code after llvm-g++ -O2:
-
-declare extern_weak i32 @0(i64)
-
-define void @foo() {
- br i1 icmp eq (i32 zext (i1 icmp ne (i32 (i64)* @0, i32 (i64)* null) to i32),
-i32 0), label %cond_true, label %cond_false
-cond_true:
- ret void
-cond_false:
- ret void
-}
-
-That branch expression should be reduced to:
-
- i1 icmp eq (i32 (i64)* @0, i32 (i64)* null)
-
-It's probably not a perf issue, I just happened to see it while examining
-something else and didn't want to forget about it.
+See also PR4973
//===---------------------------------------------------------------------===//
diff --git a/libclamav/c++/llvm/lib/Target/TargetLoweringObjectFile.cpp b/libclamav/c++/llvm/lib/Target/TargetLoweringObjectFile.cpp
index b2ee955..c1aab99 100644
--- a/libclamav/c++/llvm/lib/Target/TargetLoweringObjectFile.cpp
+++ b/libclamav/c++/llvm/lib/Target/TargetLoweringObjectFile.cpp
@@ -18,6 +18,7 @@
#include "llvm/Function.h"
#include "llvm/GlobalVariable.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/Target/TargetData.h"
@@ -61,23 +62,23 @@ TargetLoweringObjectFile::~TargetLoweringObjectFile() {
static bool isSuitableForBSS(const GlobalVariable *GV) {
Constant *C = GV->getInitializer();
-
+
// Must have zero initializer.
if (!C->isNullValue())
return false;
-
+
// Leave constant zeros in readonly constant sections, so they can be shared.
if (GV->isConstant())
return false;
-
+
// If the global has an explicit section specified, don't put it in BSS.
if (!GV->getSection().empty())
return false;
-
+
// If -nozero-initialized-in-bss is specified, don't ever use BSS.
if (NoZerosInBSS)
return false;
-
+
// Otherwise, put it in BSS!
return true;
}
@@ -87,7 +88,7 @@ static bool isSuitableForBSS(const GlobalVariable *GV) {
/// nul value and contains no other nuls in it.
static bool IsNullTerminatedString(const Constant *C) {
const ArrayType *ATy = cast<ArrayType>(C->getType());
-
+
// First check: is we have constant array of i8 terminated with zero
if (const ConstantArray *CVA = dyn_cast<ConstantArray>(C)) {
if (ATy->getNumElements() == 0) return false;
@@ -96,7 +97,7 @@ static bool IsNullTerminatedString(const Constant *C) {
dyn_cast<ConstantInt>(CVA->getOperand(ATy->getNumElements()-1));
if (Null == 0 || Null->getZExtValue() != 0)
return false; // Not null terminated.
-
+
// Verify that the null doesn't occur anywhere else in the string.
for (unsigned i = 0, e = ATy->getNumElements()-1; i != e; ++i)
// Reject constantexpr elements etc.
@@ -122,14 +123,14 @@ SectionKind TargetLoweringObjectFile::getKindForGlobal(const GlobalValue *GV,
const TargetMachine &TM){
assert(!GV->isDeclaration() && !GV->hasAvailableExternallyLinkage() &&
"Can only be used for global definitions");
-
+
Reloc::Model ReloModel = TM.getRelocationModel();
-
+
// Early exit - functions should be always in text sections.
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
if (GVar == 0)
return SectionKind::getText();
-
+
// Handle thread-local data first.
if (GVar->isThreadLocal()) {
if (isSuitableForBSS(GVar))
@@ -142,7 +143,7 @@ SectionKind TargetLoweringObjectFile::getKindForGlobal(const GlobalValue *GV,
return SectionKind::getBSS();
Constant *C = GVar->getInitializer();
-
+
// If the global is marked constant, we can put it into a mergable section,
// a mergable string section, or general .data if it contains relocations.
if (GVar->isConstant()) {
@@ -155,7 +156,7 @@ SectionKind TargetLoweringObjectFile::getKindForGlobal(const GlobalValue *GV,
// If initializer is a null-terminated string, put it in a "cstring"
// section of the right width.
if (const ArrayType *ATy = dyn_cast<ArrayType>(C->getType())) {
- if (const IntegerType *ITy =
+ if (const IntegerType *ITy =
dyn_cast<IntegerType>(ATy->getElementType())) {
if ((ITy->getBitWidth() == 8 || ITy->getBitWidth() == 16 ||
ITy->getBitWidth() == 32) &&
@@ -164,13 +165,13 @@ SectionKind TargetLoweringObjectFile::getKindForGlobal(const GlobalValue *GV,
return SectionKind::getMergeable1ByteCString();
if (ITy->getBitWidth() == 16)
return SectionKind::getMergeable2ByteCString();
-
+
assert(ITy->getBitWidth() == 32 && "Unknown width");
return SectionKind::getMergeable4ByteCString();
}
}
}
-
+
// Otherwise, just drop it into a mergable constant section. If we have
// a section for this size, use it, otherwise use the arbitrary sized
// mergable section.
@@ -180,7 +181,7 @@ SectionKind TargetLoweringObjectFile::getKindForGlobal(const GlobalValue *GV,
case 16: return SectionKind::getMergeableConst16();
default: return SectionKind::getMergeableConst();
}
-
+
case Constant::LocalRelocation:
// In static relocation model, the linker will resolve all addresses, so
// the relocation entries will actually be constants by the time the app
@@ -189,11 +190,11 @@ SectionKind TargetLoweringObjectFile::getKindForGlobal(const GlobalValue *GV,
// merge entries in the section.
if (ReloModel == Reloc::Static)
return SectionKind::getReadOnly();
-
+
// Otherwise, the dynamic linker needs to fix it up, put it in the
// writable data.rel.local section.
return SectionKind::getReadOnlyWithRelLocal();
-
+
case Constant::GlobalRelocations:
// In static relocation model, the linker will resolve all addresses, so
// the relocation entries will actually be constants by the time the app
@@ -202,7 +203,7 @@ SectionKind TargetLoweringObjectFile::getKindForGlobal(const GlobalValue *GV,
// merge entries in the section.
if (ReloModel == Reloc::Static)
return SectionKind::getReadOnly();
-
+
// Otherwise, the dynamic linker needs to fix it up, put it in the
// writable data.rel section.
return SectionKind::getReadOnlyWithRel();
@@ -237,8 +238,8 @@ SectionForGlobal(const GlobalValue *GV, SectionKind Kind, Mangler *Mang,
// Select section name.
if (GV->hasSection())
return getExplicitSectionGlobal(GV, Kind, Mang, TM);
-
-
+
+
// Use default section depending on the 'type' of global
return SelectSectionForGlobal(GV, Kind, Mang, TM);
}
@@ -251,13 +252,13 @@ TargetLoweringObjectFile::SelectSectionForGlobal(const GlobalValue *GV,
Mangler *Mang,
const TargetMachine &TM) const{
assert(!Kind.isThreadLocal() && "Doesn't support TLS");
-
+
if (Kind.isText())
return getTextSection();
-
+
if (Kind.isBSS() && BSSSection != 0)
return BSSSection;
-
+
if (Kind.isReadOnly() && ReadOnlySection != 0)
return ReadOnlySection;
@@ -271,10 +272,35 @@ const MCSection *
TargetLoweringObjectFile::getSectionForConstant(SectionKind Kind) const {
if (Kind.isReadOnly() && ReadOnlySection != 0)
return ReadOnlySection;
-
+
return DataSection;
}
+/// getSymbolForDwarfGlobalReference - Return an MCExpr to use for a
+/// pc-relative reference to the specified global variable from exception
+/// handling information. In addition to the symbol, this returns
+/// by-reference:
+///
+/// IsIndirect - True if the returned symbol is actually a stub that contains
+/// the address of the symbol, false if the symbol is the global itself.
+///
+/// IsPCRel - True if the symbol reference is already pc-relative, false if
+/// the caller needs to subtract off the address of the reference from the
+/// symbol.
+///
+const MCExpr *TargetLoweringObjectFile::
+getSymbolForDwarfGlobalReference(const GlobalValue *GV, Mangler *Mang,
+ MachineModuleInfo *MMI,
+ bool &IsIndirect, bool &IsPCRel) const {
+ // The generic implementation of this just returns a direct reference to the
+ // symbol.
+ IsIndirect = false;
+ IsPCRel = false;
+
+ SmallString<128> Name;
+ Mang->getNameWithPrefix(Name, GV, false);
+ return MCSymbolRefExpr::Create(Name.str(), getContext());
+}
//===----------------------------------------------------------------------===//
@@ -293,11 +319,11 @@ getELFSection(StringRef Section, unsigned Type, unsigned Flags,
if (UniquingMap == 0)
UniquingMap = new ELFUniqueMapTy();
ELFUniqueMapTy &Map = *(ELFUniqueMapTy*)UniquingMap;
-
+
// Do the lookup, if we have a hit, return it.
const MCSectionELF *&Entry = Map[Section];
if (Entry) return Entry;
-
+
return Entry = MCSectionELF::Create(Section, Type, Flags, Kind, IsExplicit,
getContext());
}
@@ -308,73 +334,73 @@ void TargetLoweringObjectFileELF::Initialize(MCContext &Ctx,
((ELFUniqueMapTy*)UniquingMap)->clear();
TargetLoweringObjectFile::Initialize(Ctx, TM);
- BSSSection =
+ BSSSection =
getELFSection(".bss", MCSectionELF::SHT_NOBITS,
MCSectionELF::SHF_WRITE | MCSectionELF::SHF_ALLOC,
SectionKind::getBSS());
-
- TextSection =
+
+ TextSection =
getELFSection(".text", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_EXECINSTR | MCSectionELF::SHF_ALLOC,
SectionKind::getText());
- DataSection =
+ DataSection =
getELFSection(".data", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_WRITE | MCSectionELF::SHF_ALLOC,
SectionKind::getDataRel());
- ReadOnlySection =
- getELFSection(".rodata", MCSectionELF::SHT_PROGBITS,
- MCSectionELF::SHF_ALLOC,
+ ReadOnlySection =
+ getELFSection(".rodata", MCSectionELF::SHT_PROGBITS,
+ MCSectionELF::SHF_ALLOC,
SectionKind::getReadOnly());
- TLSDataSection =
+ TLSDataSection =
getELFSection(".tdata", MCSectionELF::SHT_PROGBITS,
- MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_TLS |
+ MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_TLS |
MCSectionELF::SHF_WRITE, SectionKind::getThreadData());
-
- TLSBSSSection =
+
+ TLSBSSSection =
getELFSection(".tbss", MCSectionELF::SHT_NOBITS,
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_TLS |
MCSectionELF::SHF_WRITE, SectionKind::getThreadBSS());
- DataRelSection =
+ DataRelSection =
getELFSection(".data.rel", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_WRITE,
SectionKind::getDataRel());
- DataRelLocalSection =
+ DataRelLocalSection =
getELFSection(".data.rel.local", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_WRITE,
SectionKind::getDataRelLocal());
- DataRelROSection =
+ DataRelROSection =
getELFSection(".data.rel.ro", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_WRITE,
SectionKind::getReadOnlyWithRel());
- DataRelROLocalSection =
+ DataRelROLocalSection =
getELFSection(".data.rel.ro.local", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_WRITE,
SectionKind::getReadOnlyWithRelLocal());
-
- MergeableConst4Section =
+
+ MergeableConst4Section =
getELFSection(".rodata.cst4", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_MERGE,
SectionKind::getMergeableConst4());
- MergeableConst8Section =
+ MergeableConst8Section =
getELFSection(".rodata.cst8", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_MERGE,
SectionKind::getMergeableConst8());
- MergeableConst16Section =
+ MergeableConst16Section =
getELFSection(".rodata.cst16", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_MERGE,
SectionKind::getMergeableConst16());
StaticCtorSection =
- getELFSection(".ctors", MCSectionELF::SHT_PROGBITS,
+ getELFSection(".ctors", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_WRITE,
SectionKind::getDataRel());
@@ -382,9 +408,9 @@ void TargetLoweringObjectFileELF::Initialize(MCContext &Ctx,
getELFSection(".dtors", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_WRITE,
SectionKind::getDataRel());
-
+
// Exception Handling Sections.
-
+
// FIXME: We're emitting LSDA info into a readonly section on ELF, even though
// it contains relocatable pointers. In PIC mode, this is probably a big
// runtime hit for C++ apps. Either the contents of the LSDA need to be
@@ -393,70 +419,74 @@ void TargetLoweringObjectFileELF::Initialize(MCContext &Ctx,
getELFSection(".gcc_except_table", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC, SectionKind::getReadOnly());
EHFrameSection =
- getELFSection(".eh_frame", MCSectionELF::SHT_PROGBITS,
+ getELFSection(".eh_frame", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_WRITE,
SectionKind::getDataRel());
-
+
// Debug Info Sections.
- DwarfAbbrevSection =
- getELFSection(".debug_abbrev", MCSectionELF::SHT_PROGBITS, 0,
+ DwarfAbbrevSection =
+ getELFSection(".debug_abbrev", MCSectionELF::SHT_PROGBITS, 0,
SectionKind::getMetadata());
- DwarfInfoSection =
- getELFSection(".debug_info", MCSectionELF::SHT_PROGBITS, 0,
+ DwarfInfoSection =
+ getELFSection(".debug_info", MCSectionELF::SHT_PROGBITS, 0,
SectionKind::getMetadata());
- DwarfLineSection =
- getELFSection(".debug_line", MCSectionELF::SHT_PROGBITS, 0,
+ DwarfLineSection =
+ getELFSection(".debug_line", MCSectionELF::SHT_PROGBITS, 0,
SectionKind::getMetadata());
- DwarfFrameSection =
- getELFSection(".debug_frame", MCSectionELF::SHT_PROGBITS, 0,
+ DwarfFrameSection =
+ getELFSection(".debug_frame", MCSectionELF::SHT_PROGBITS, 0,
SectionKind::getMetadata());
- DwarfPubNamesSection =
- getELFSection(".debug_pubnames", MCSectionELF::SHT_PROGBITS, 0,
+ DwarfPubNamesSection =
+ getELFSection(".debug_pubnames", MCSectionELF::SHT_PROGBITS, 0,
SectionKind::getMetadata());
- DwarfPubTypesSection =
- getELFSection(".debug_pubtypes", MCSectionELF::SHT_PROGBITS, 0,
+ DwarfPubTypesSection =
+ getELFSection(".debug_pubtypes", MCSectionELF::SHT_PROGBITS, 0,
SectionKind::getMetadata());
- DwarfStrSection =
+ DwarfStrSection =
getELFSection(".debug_str", MCSectionELF::SHT_PROGBITS, 0,
SectionKind::getMetadata());
- DwarfLocSection =
- getELFSection(".debug_loc", MCSectionELF::SHT_PROGBITS, 0,
+ DwarfLocSection =
+ getELFSection(".debug_loc", MCSectionELF::SHT_PROGBITS, 0,
SectionKind::getMetadata());
- DwarfARangesSection =
- getELFSection(".debug_aranges", MCSectionELF::SHT_PROGBITS, 0,
+ DwarfARangesSection =
+ getELFSection(".debug_aranges", MCSectionELF::SHT_PROGBITS, 0,
SectionKind::getMetadata());
- DwarfRangesSection =
- getELFSection(".debug_ranges", MCSectionELF::SHT_PROGBITS, 0,
+ DwarfRangesSection =
+ getELFSection(".debug_ranges", MCSectionELF::SHT_PROGBITS, 0,
SectionKind::getMetadata());
- DwarfMacroInfoSection =
- getELFSection(".debug_macinfo", MCSectionELF::SHT_PROGBITS, 0,
+ DwarfMacroInfoSection =
+ getELFSection(".debug_macinfo", MCSectionELF::SHT_PROGBITS, 0,
SectionKind::getMetadata());
}
-static SectionKind
+static SectionKind
getELFKindForNamedSection(const char *Name, SectionKind K) {
if (Name[0] != '.') return K;
-
+
// Some lame default implementation based on some magic section names.
- if (strncmp(Name, ".gnu.linkonce.b.", 16) == 0 ||
+ if (strcmp(Name, ".bss") == 0 ||
+ strncmp(Name, ".bss.", 5) == 0 ||
+ strncmp(Name, ".gnu.linkonce.b.", 16) == 0 ||
strncmp(Name, ".llvm.linkonce.b.", 17) == 0 ||
+ strcmp(Name, ".sbss") == 0 ||
+ strncmp(Name, ".sbss.", 6) == 0 ||
strncmp(Name, ".gnu.linkonce.sb.", 17) == 0 ||
strncmp(Name, ".llvm.linkonce.sb.", 18) == 0)
return SectionKind::getBSS();
-
+
if (strcmp(Name, ".tdata") == 0 ||
strncmp(Name, ".tdata.", 7) == 0 ||
strncmp(Name, ".gnu.linkonce.td.", 17) == 0 ||
strncmp(Name, ".llvm.linkonce.td.", 18) == 0)
return SectionKind::getThreadData();
-
+
if (strcmp(Name, ".tbss") == 0 ||
strncmp(Name, ".tbss.", 6) == 0 ||
strncmp(Name, ".gnu.linkonce.tb.", 17) == 0 ||
strncmp(Name, ".llvm.linkonce.tb.", 18) == 0)
return SectionKind::getThreadBSS();
-
+
return K;
}
@@ -486,16 +516,16 @@ getELFSectionFlags(SectionKind K) {
if (!K.isMetadata())
Flags |= MCSectionELF::SHF_ALLOC;
-
+
if (K.isText())
Flags |= MCSectionELF::SHF_EXECINSTR;
-
+
if (K.isWriteable())
Flags |= MCSectionELF::SHF_WRITE;
-
+
if (K.isThreadLocal())
Flags |= MCSectionELF::SHF_TLS;
-
+
// K.isMergeableConst() is left out to honour PR4650
if (K.isMergeableCString() || K.isMergeableConst4() ||
K.isMergeableConst8() || K.isMergeableConst16())
@@ -509,31 +539,31 @@ getELFSectionFlags(SectionKind K) {
const MCSection *TargetLoweringObjectFileELF::
-getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,
+getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,
Mangler *Mang, const TargetMachine &TM) const {
const char *SectionName = GV->getSection().c_str();
// Infer section flags from the section name if we can.
Kind = getELFKindForNamedSection(SectionName, Kind);
-
- return getELFSection(SectionName,
- getELFSectionType(SectionName, Kind),
+
+ return getELFSection(SectionName,
+ getELFSectionType(SectionName, Kind),
getELFSectionFlags(Kind), Kind, true);
}
static const char *getSectionPrefixForUniqueGlobal(SectionKind Kind) {
if (Kind.isText()) return ".gnu.linkonce.t.";
if (Kind.isReadOnly()) return ".gnu.linkonce.r.";
-
+
if (Kind.isThreadData()) return ".gnu.linkonce.td.";
if (Kind.isThreadBSS()) return ".gnu.linkonce.tb.";
-
+
if (Kind.isBSS()) return ".gnu.linkonce.b.";
if (Kind.isDataNoRel()) return ".gnu.linkonce.d.";
if (Kind.isDataRelLocal()) return ".gnu.linkonce.d.rel.local.";
if (Kind.isDataRel()) return ".gnu.linkonce.d.rel.";
if (Kind.isReadOnlyWithRelLocal()) return ".gnu.linkonce.d.rel.ro.local.";
-
+
assert(Kind.isReadOnlyWithRel() && "Unknown section kind");
return ".gnu.linkonce.d.rel.ro.";
}
@@ -541,31 +571,31 @@ static const char *getSectionPrefixForUniqueGlobal(SectionKind Kind) {
const MCSection *TargetLoweringObjectFileELF::
SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
Mangler *Mang, const TargetMachine &TM) const {
-
+
// If this global is linkonce/weak and the target handles this by emitting it
// into a 'uniqued' section name, create and return the section now.
if (GV->isWeakForLinker()) {
const char *Prefix = getSectionPrefixForUniqueGlobal(Kind);
std::string Name = Mang->makeNameProper(GV->getNameStr());
- return getELFSection((Prefix+Name).c_str(),
- getELFSectionType((Prefix+Name).c_str(), Kind),
- getELFSectionFlags(Kind),
+ return getELFSection((Prefix+Name).c_str(),
+ getELFSectionType((Prefix+Name).c_str(), Kind),
+ getELFSectionFlags(Kind),
Kind);
}
-
+
if (Kind.isText()) return TextSection;
-
+
if (Kind.isMergeable1ByteCString() ||
Kind.isMergeable2ByteCString() ||
Kind.isMergeable4ByteCString()) {
-
+
// We also need alignment here.
// FIXME: this is getting the alignment of the character, not the
// alignment of the global!
- unsigned Align =
+ unsigned Align =
TM.getTargetData()->getPreferredAlignment(cast<GlobalVariable>(GV));
-
+
const char *SizeSpec = ".rodata.str1.";
if (Kind.isMergeable2ByteCString())
SizeSpec = ".rodata.str2.";
@@ -573,16 +603,16 @@ SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
SizeSpec = ".rodata.str4.";
else
assert(Kind.isMergeable1ByteCString() && "unknown string width");
-
-
+
+
std::string Name = SizeSpec + utostr(Align);
- return getELFSection(Name.c_str(), MCSectionELF::SHT_PROGBITS,
- MCSectionELF::SHF_ALLOC |
- MCSectionELF::SHF_MERGE |
- MCSectionELF::SHF_STRINGS,
+ return getELFSection(Name.c_str(), MCSectionELF::SHT_PROGBITS,
+ MCSectionELF::SHF_ALLOC |
+ MCSectionELF::SHF_MERGE |
+ MCSectionELF::SHF_STRINGS,
Kind);
}
-
+
if (Kind.isMergeableConst()) {
if (Kind.isMergeableConst4() && MergeableConst4Section)
return MergeableConst4Section;
@@ -592,19 +622,19 @@ SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
return MergeableConst16Section;
return ReadOnlySection; // .const
}
-
+
if (Kind.isReadOnly()) return ReadOnlySection;
-
+
if (Kind.isThreadData()) return TLSDataSection;
if (Kind.isThreadBSS()) return TLSBSSSection;
-
+
if (Kind.isBSS()) return BSSSection;
-
+
if (Kind.isDataNoRel()) return DataSection;
if (Kind.isDataRelLocal()) return DataRelLocalSection;
if (Kind.isDataRel()) return DataRelSection;
if (Kind.isReadOnlyWithRelLocal()) return DataRelROLocalSection;
-
+
assert(Kind.isReadOnlyWithRel() && "Unknown section kind");
return DataRelROSection;
}
@@ -622,7 +652,7 @@ getSectionForConstant(SectionKind Kind) const {
return MergeableConst16Section;
if (Kind.isReadOnly())
return ReadOnlySection;
-
+
if (Kind.isReadOnlyWithRelLocal()) return DataRelROLocalSection;
assert(Kind.isReadOnlyWithRel() && "Unknown section kind");
return DataRelROSection;
@@ -647,18 +677,18 @@ getMachOSection(const StringRef &Segment, const StringRef &Section,
// We unique sections by their segment/section pair. The returned section
// may not have the same flags as the requested section, if so this should be
// diagnosed by the client as an error.
-
+
// Create the map if it doesn't already exist.
if (UniquingMap == 0)
UniquingMap = new MachOUniqueMapTy();
MachOUniqueMapTy &Map = *(MachOUniqueMapTy*)UniquingMap;
-
+
// Form the name to look up.
SmallString<64> Name;
Name += Segment;
Name.push_back(',');
Name += Section;
-
+
// Do the lookup, if we have a hit, return it.
const MCSectionMachO *&Entry = Map[Name.str()];
if (Entry) return Entry;
@@ -674,14 +704,14 @@ void TargetLoweringObjectFileMachO::Initialize(MCContext &Ctx,
if (UniquingMap != 0)
((MachOUniqueMapTy*)UniquingMap)->clear();
TargetLoweringObjectFile::Initialize(Ctx, TM);
-
+
TextSection // .text
= getMachOSection("__TEXT", "__text",
MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
SectionKind::getText());
DataSection // .data
= getMachOSection("__DATA", "__data", 0, SectionKind::getDataRel());
-
+
CStringSection // .cstring
= getMachOSection("__TEXT", "__cstring", MCSectionMachO::S_CSTRING_LITERALS,
SectionKind::getMergeable1ByteCString());
@@ -694,7 +724,7 @@ void TargetLoweringObjectFileMachO::Initialize(MCContext &Ctx,
EightByteConstantSection // .literal8
= getMachOSection("__TEXT", "__literal8", MCSectionMachO::S_8BYTE_LITERALS,
SectionKind::getMergeableConst8());
-
+
// ld_classic doesn't support .literal16 in 32-bit mode, and ld64 falls back
// to using it in -static mode.
SixteenByteConstantSection = 0;
@@ -703,10 +733,10 @@ void TargetLoweringObjectFileMachO::Initialize(MCContext &Ctx,
SixteenByteConstantSection = // .literal16
getMachOSection("__TEXT", "__literal16",MCSectionMachO::S_16BYTE_LITERALS,
SectionKind::getMergeableConst16());
-
+
ReadOnlySection // .const
= getMachOSection("__TEXT", "__const", 0, SectionKind::getReadOnly());
-
+
TextCoalSection
= getMachOSection("__TEXT", "__textcoal_nt",
MCSectionMachO::S_COALESCED |
@@ -725,7 +755,7 @@ void TargetLoweringObjectFileMachO::Initialize(MCContext &Ctx,
= getMachOSection("__DATA","__datacoal_nt", MCSectionMachO::S_COALESCED,
SectionKind::getDataRel());
-
+
LazySymbolPointerSection
= getMachOSection("__DATA", "__la_symbol_ptr",
MCSectionMachO::S_LAZY_SYMBOL_POINTERS,
@@ -734,7 +764,7 @@ void TargetLoweringObjectFileMachO::Initialize(MCContext &Ctx,
= getMachOSection("__DATA", "__nl_symbol_ptr",
MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS,
SectionKind::getMetadata());
-
+
if (TM.getRelocationModel() == Reloc::Static) {
StaticCtorSection
= getMachOSection("__TEXT", "__constructor", 0,SectionKind::getDataRel());
@@ -746,11 +776,11 @@ void TargetLoweringObjectFileMachO::Initialize(MCContext &Ctx,
MCSectionMachO::S_MOD_INIT_FUNC_POINTERS,
SectionKind::getDataRel());
StaticDtorSection
- = getMachOSection("__DATA", "__mod_term_func",
+ = getMachOSection("__DATA", "__mod_term_func",
MCSectionMachO::S_MOD_TERM_FUNC_POINTERS,
SectionKind::getDataRel());
}
-
+
// Exception Handling.
LSDASection = getMachOSection("__DATA", "__gcc_except_tab", 0,
SectionKind::getDataRel());
@@ -763,46 +793,46 @@ void TargetLoweringObjectFileMachO::Initialize(MCContext &Ctx,
SectionKind::getReadOnly());
// Debug Information.
- DwarfAbbrevSection =
+ DwarfAbbrevSection =
getMachOSection("__DWARF", "__debug_abbrev", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
- DwarfInfoSection =
+ DwarfInfoSection =
getMachOSection("__DWARF", "__debug_info", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
- DwarfLineSection =
+ DwarfLineSection =
getMachOSection("__DWARF", "__debug_line", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
- DwarfFrameSection =
+ DwarfFrameSection =
getMachOSection("__DWARF", "__debug_frame", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
- DwarfPubNamesSection =
+ DwarfPubNamesSection =
getMachOSection("__DWARF", "__debug_pubnames", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
- DwarfPubTypesSection =
+ DwarfPubTypesSection =
getMachOSection("__DWARF", "__debug_pubtypes", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
- DwarfStrSection =
+ DwarfStrSection =
getMachOSection("__DWARF", "__debug_str", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
- DwarfLocSection =
+ DwarfLocSection =
getMachOSection("__DWARF", "__debug_loc", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
- DwarfARangesSection =
+ DwarfARangesSection =
getMachOSection("__DWARF", "__debug_aranges", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
- DwarfRangesSection =
+ DwarfRangesSection =
getMachOSection("__DWARF", "__debug_ranges", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
- DwarfMacroInfoSection =
+ DwarfMacroInfoSection =
getMachOSection("__DWARF", "__debug_macinfo", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
- DwarfDebugInlineSection =
+ DwarfDebugInlineSection =
getMachOSection("__DWARF", "__debug_inlined", MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
}
const MCSection *TargetLoweringObjectFileMachO::
-getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,
+getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,
Mangler *Mang, const TargetMachine &TM) const {
// Parse the section specifier and create it if valid.
StringRef Segment, Section;
@@ -818,11 +848,11 @@ getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,
// Fall back to dropping it into the data section.
return DataSection;
}
-
+
// Get the section.
const MCSectionMachO *S =
getMachOSection(Segment, Section, TAA, StubSize, Kind);
-
+
// Okay, now that we got the section, verify that the TAA & StubSize agree.
// If the user declared multiple globals with different section flags, we need
// to reject it here.
@@ -832,7 +862,7 @@ getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,
"' section type or attributes does not match previous"
" section specifier");
}
-
+
return S;
}
@@ -840,10 +870,10 @@ const MCSection *TargetLoweringObjectFileMachO::
SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
Mangler *Mang, const TargetMachine &TM) const {
assert(!Kind.isThreadLocal() && "Darwin doesn't support TLS");
-
+
if (Kind.isText())
return GV->isWeakForLinker() ? TextCoalSection : TextSection;
-
+
// If this is weak/linkonce, put this in a coalescable section, either in text
// or data depending on if it is writable.
if (GV->isWeakForLinker()) {
@@ -851,7 +881,7 @@ SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
return ConstTextCoalSection;
return DataCoalSection;
}
-
+
// FIXME: Alignment check should be handled by section classifier.
if (Kind.isMergeable1ByteCString() ||
Kind.isMergeable2ByteCString()) {
@@ -863,7 +893,7 @@ SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
return UStringSection;
}
}
-
+
if (Kind.isMergeableConst()) {
if (Kind.isMergeableConst4())
return FourByteConstantSection;
@@ -882,7 +912,7 @@ SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
// linker needs to write to it, put it in the data segment.
if (Kind.isReadOnlyWithRel())
return ConstDataSection;
-
+
// Otherwise, just drop the variable in the normal data section.
return DataSection;
}
@@ -893,7 +923,7 @@ TargetLoweringObjectFileMachO::getSectionForConstant(SectionKind Kind) const {
// segment, not in the text segment.
if (Kind.isDataRel())
return ConstDataSection;
-
+
if (Kind.isMergeableConst4())
return FourByteConstantSection;
if (Kind.isMergeableConst8())
@@ -911,7 +941,7 @@ shouldEmitUsedDirectiveFor(const GlobalValue *GV, Mangler *Mang) const {
/// On Darwin, internally linked data beginning with "L" or "l" does not have
/// the directive emitted (this occurs in ObjC metadata).
if (!GV) return false;
-
+
// Check whether the mangled name has the "Private" or "LinkerPrivate" prefix.
if (GV->hasLocalLinkage() && !isa<Function>(GV)) {
// FIXME: ObjC metadata is currently emitted as internal symbols that have
@@ -921,10 +951,24 @@ shouldEmitUsedDirectiveFor(const GlobalValue *GV, Mangler *Mang) const {
if (Name[0] == 'L' || Name[0] == 'l')
return false;
}
-
+
return true;
}
+const MCExpr *TargetLoweringObjectFileMachO::
+getSymbolForDwarfGlobalReference(const GlobalValue *GV, Mangler *Mang,
+ MachineModuleInfo *MMI,
+ bool &IsIndirect, bool &IsPCRel) const {
+ // The mach-o version of this method defaults to returning a stub reference.
+ IsIndirect = true;
+ IsPCRel = false;
+
+ SmallString<128> Name;
+ Mang->getNameWithPrefix(Name, GV, true);
+ Name += "$non_lazy_ptr";
+ return MCSymbolRefExpr::Create(Name.str(), getContext());
+}
+
//===----------------------------------------------------------------------===//
// COFF
@@ -943,11 +987,11 @@ getCOFFSection(const char *Name, bool isDirective, SectionKind Kind) const {
if (UniquingMap == 0)
UniquingMap = new MachOUniqueMapTy();
COFFUniqueMapTy &Map = *(COFFUniqueMapTy*)UniquingMap;
-
+
// Do the lookup, if we have a hit, return it.
const MCSectionCOFF *&Entry = Map[Name];
if (Entry) return Entry;
-
+
return Entry = MCSectionCOFF::Create(Name, isDirective, Kind, getContext());
}
@@ -962,7 +1006,7 @@ void TargetLoweringObjectFileCOFF::Initialize(MCContext &Ctx,
getCOFFSection(".ctors", false, SectionKind::getDataRel());
StaticDtorSection =
getCOFFSection(".dtors", false, SectionKind::getDataRel());
-
+
// FIXME: We're emitting LSDA info into a readonly section on COFF, even
// though it contains relocatable pointers. In PIC mode, this is probably a
// big runtime hit for C++ apps. Either the contents of the LSDA need to be
@@ -971,19 +1015,19 @@ void TargetLoweringObjectFileCOFF::Initialize(MCContext &Ctx,
getCOFFSection(".gcc_except_table", false, SectionKind::getReadOnly());
EHFrameSection =
getCOFFSection(".eh_frame", false, SectionKind::getDataRel());
-
+
// Debug info.
// FIXME: Don't use 'directive' mode here.
- DwarfAbbrevSection =
+ DwarfAbbrevSection =
getCOFFSection("\t.section\t.debug_abbrev,\"dr\"",
true, SectionKind::getMetadata());
- DwarfInfoSection =
+ DwarfInfoSection =
getCOFFSection("\t.section\t.debug_info,\"dr\"",
true, SectionKind::getMetadata());
- DwarfLineSection =
+ DwarfLineSection =
getCOFFSection("\t.section\t.debug_line,\"dr\"",
true, SectionKind::getMetadata());
- DwarfFrameSection =
+ DwarfFrameSection =
getCOFFSection("\t.section\t.debug_frame,\"dr\"",
true, SectionKind::getMetadata());
DwarfPubNamesSection =
@@ -992,25 +1036,25 @@ void TargetLoweringObjectFileCOFF::Initialize(MCContext &Ctx,
DwarfPubTypesSection =
getCOFFSection("\t.section\t.debug_pubtypes,\"dr\"",
true, SectionKind::getMetadata());
- DwarfStrSection =
+ DwarfStrSection =
getCOFFSection("\t.section\t.debug_str,\"dr\"",
true, SectionKind::getMetadata());
- DwarfLocSection =
+ DwarfLocSection =
getCOFFSection("\t.section\t.debug_loc,\"dr\"",
true, SectionKind::getMetadata());
- DwarfARangesSection =
+ DwarfARangesSection =
getCOFFSection("\t.section\t.debug_aranges,\"dr\"",
true, SectionKind::getMetadata());
- DwarfRangesSection =
+ DwarfRangesSection =
getCOFFSection("\t.section\t.debug_ranges,\"dr\"",
true, SectionKind::getMetadata());
- DwarfMacroInfoSection =
+ DwarfMacroInfoSection =
getCOFFSection("\t.section\t.debug_macinfo,\"dr\"",
true, SectionKind::getMetadata());
}
const MCSection *TargetLoweringObjectFileCOFF::
-getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,
+getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,
Mangler *Mang, const TargetMachine &TM) const {
return getCOFFSection(GV->getSection().c_str(), false, Kind);
}
@@ -1028,7 +1072,7 @@ const MCSection *TargetLoweringObjectFileCOFF::
SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
Mangler *Mang, const TargetMachine &TM) const {
assert(!Kind.isThreadLocal() && "Doesn't support TLS");
-
+
// If this global is linkonce/weak and the target handles this by emitting it
// into a 'uniqued' section name, create and return the section now.
if (GV->isWeakForLinker()) {
@@ -1036,10 +1080,10 @@ SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
std::string Name = Mang->makeNameProper(GV->getNameStr());
return getCOFFSection((Prefix+Name).c_str(), false, Kind);
}
-
+
if (Kind.isText())
return getTextSection();
-
+
return getDataSection();
}
diff --git a/libclamav/c++/llvm/lib/Target/TargetMachine.cpp b/libclamav/c++/llvm/lib/Target/TargetMachine.cpp
index fdf157a..fec59b5 100644
--- a/libclamav/c++/llvm/lib/Target/TargetMachine.cpp
+++ b/libclamav/c++/llvm/lib/Target/TargetMachine.cpp
@@ -35,6 +35,8 @@ namespace llvm {
bool NoZerosInBSS;
bool DwarfExceptionHandling;
bool SjLjExceptionHandling;
+ bool JITEmitDebugInfo;
+ bool JITEmitDebugInfoToDisk;
bool UnwindTablesMandatory;
Reloc::Model RelocationModel;
CodeModel::Model CMModel;
@@ -114,6 +116,24 @@ EnableSjLjExceptionHandling("enable-sjlj-eh",
cl::desc("Emit SJLJ exception handling (default if target supports)"),
cl::location(SjLjExceptionHandling),
cl::init(false));
+// In debug builds, make this default to true.
+#ifdef NDEBUG
+#define EMIT_DEBUG false
+#else
+#define EMIT_DEBUG true
+#endif
+static cl::opt<bool, true>
+EmitJitDebugInfo("jit-emit-debug",
+ cl::desc("Emit debug information to debugger"),
+ cl::location(JITEmitDebugInfo),
+ cl::init(EMIT_DEBUG));
+#undef EMIT_DEBUG
+static cl::opt<bool, true>
+EmitJitDebugInfoToDisk("jit-emit-debug-to-disk",
+ cl::Hidden,
+ cl::desc("Emit debug info objfiles to disk"),
+ cl::location(JITEmitDebugInfoToDisk),
+ cl::init(false));
static cl::opt<bool, true>
EnableUnwindTables("unwind-tables",
cl::desc("Generate unwinding tables for all functions"),
@@ -243,4 +263,3 @@ namespace llvm {
return !UnsafeFPMath && HonorSignDependentRoundingFPMathOption;
}
}
-
diff --git a/libclamav/c++/llvm/lib/Target/TargetRegisterInfo.cpp b/libclamav/c++/llvm/lib/Target/TargetRegisterInfo.cpp
index 902ee0c..4312399 100644
--- a/libclamav/c++/llvm/lib/Target/TargetRegisterInfo.cpp
+++ b/libclamav/c++/llvm/lib/Target/TargetRegisterInfo.cpp
@@ -85,7 +85,7 @@ BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF,
/// getFrameIndexOffset - Returns the displacement from the frame register to
/// the stack frame of the specified index. This is the default implementation
-/// which is likely incorrect for the target.
+/// which is overridden for some targets.
int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
MachineFrameInfo *MFI = MF.getFrameInfo();
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/libclamav/c++/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index d06350b..c357b4d 100644
--- a/libclamav/c++/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -12,6 +12,7 @@
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAsmLexer.h"
#include "llvm/MC/MCAsmParser.h"
+#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/SourceMgr.h"
@@ -39,7 +40,9 @@ private:
bool ParseOperand(X86Operand &Op);
bool ParseMemOperand(X86Operand &Op);
-
+
+ bool ParseDirectiveWord(unsigned Size, SMLoc L);
+
/// @name Auto-generated Match Functions
/// {
@@ -57,6 +60,8 @@ public:
: TargetAsmParser(T), Parser(_Parser) {}
virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst);
+
+ virtual bool ParseDirective(AsmToken DirectiveID);
};
} // end anonymous namespace
@@ -230,20 +235,25 @@ struct X86Operand {
bool X86ATTAsmParser::ParseRegister(X86Operand &Op) {
+ const AsmToken &TokPercent = getLexer().getTok();
+ (void)TokPercent; // Avoid warning when assertions are disabled.
+ assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
+ getLexer().Lex(); // Eat percent token.
+
const AsmToken &Tok = getLexer().getTok();
- assert(Tok.is(AsmToken::Register) && "Invalid token kind!");
+ if (Tok.isNot(AsmToken::Identifier))
+ return Error(Tok.getLoc(), "invalid register name");
// FIXME: Validate register for the current architecture; we have to do
// validation later, so maybe there is no need for this here.
unsigned RegNo;
- assert(Tok.getString().startswith("%") && "Invalid register name!");
- RegNo = MatchRegisterName(Tok.getString().substr(1));
+ RegNo = MatchRegisterName(Tok.getString());
if (RegNo == 0)
return Error(Tok.getLoc(), "invalid register name");
Op = X86Operand::CreateReg(RegNo);
- getLexer().Lex(); // Eat register token.
+ getLexer().Lex(); // Eat identifier token.
return false;
}
@@ -252,7 +262,7 @@ bool X86ATTAsmParser::ParseOperand(X86Operand &Op) {
switch (getLexer().getKind()) {
default:
return ParseMemOperand(Op);
- case AsmToken::Register:
+ case AsmToken::Percent:
// FIXME: if a segment register, this could either be just the seg reg, or
// the start of a memory operand.
return ParseRegister(Op);
@@ -299,7 +309,7 @@ bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
// so we have to eat the ( to see beyond it.
getLexer().Lex(); // Eat the '('.
- if (getLexer().is(AsmToken::Register) || getLexer().is(AsmToken::Comma)) {
+ if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
// Nothing to do here, fall into the code below with the '(' part of the
// memory operand consumed.
} else {
@@ -327,7 +337,7 @@ bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
// the rest of the memory operand.
unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
- if (getLexer().is(AsmToken::Register)) {
+ if (getLexer().is(AsmToken::Percent)) {
if (ParseRegister(Op))
return true;
BaseReg = Op.getReg();
@@ -342,7 +352,7 @@ bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
//
// Not that even though it would be completely consistent to support syntax
// like "1(%eax,,1)", the assembler doesn't.
- if (getLexer().is(AsmToken::Register)) {
+ if (getLexer().is(AsmToken::Percent)) {
if (ParseRegister(Op))
return true;
IndexReg = Op.getReg();
@@ -428,6 +438,38 @@ bool X86ATTAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
return true;
}
+bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
+ StringRef IDVal = DirectiveID.getIdentifier();
+ if (IDVal == ".word")
+ return ParseDirectiveWord(2, DirectiveID.getLoc());
+ return true;
+}
+
+/// ParseDirectiveWord
+/// ::= .word [ expression (, expression)* ]
+bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
+ if (getLexer().isNot(AsmToken::EndOfStatement)) {
+ for (;;) {
+ const MCExpr *Value;
+ if (getParser().ParseExpression(Value))
+ return true;
+
+ getParser().getStreamer().EmitValue(Value, Size);
+
+ if (getLexer().is(AsmToken::EndOfStatement))
+ break;
+
+ // FIXME: Improve diagnostic.
+ if (getLexer().isNot(AsmToken::Comma))
+ return Error(L, "unexpected token in directive");
+ getLexer().Lex();
+ }
+ }
+
+ getLexer().Lex();
+ return false;
+}
+
// Force static initialization.
extern "C" void LLVMInitializeX86AsmParser() {
RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/CMakeLists.txt b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/CMakeLists.txt
index a28c826..8aec1e8 100644
--- a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/CMakeLists.txt
+++ b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/CMakeLists.txt
@@ -1,9 +1,9 @@
include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
add_llvm_library(LLVMX86AsmPrinter
- X86ATTAsmPrinter.cpp
- X86ATTInstPrinter.cpp
X86AsmPrinter.cpp
- X86IntelAsmPrinter.cpp
+ X86ATTInstPrinter.cpp
+ X86IntelInstPrinter.cpp
+ X86MCInstLower.cpp
)
-add_dependencies(LLVMX86AsmPrinter X86CodeGenTable_gen)
\ No newline at end of file
+add_dependencies(LLVMX86AsmPrinter X86CodeGenTable_gen)
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
deleted file mode 100644
index 2058d7d..0000000
--- a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
+++ /dev/null
@@ -1,1182 +0,0 @@
-//===-- X86ATTAsmPrinter.cpp - Convert X86 LLVM code to AT&T assembly -----===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains a printer that converts from our internal representation
-// of machine-dependent LLVM code to AT&T format assembly
-// language. This printer is the output mechanism used by `llc'.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "asm-printer"
-#include "X86ATTAsmPrinter.h"
-#include "X86.h"
-#include "X86COFF.h"
-#include "X86MachineFunctionInfo.h"
-#include "X86TargetMachine.h"
-#include "X86MCAsmInfo.h"
-#include "llvm/CallingConv.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/Module.h"
-#include "llvm/Type.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/ADT/StringExtras.h"
-#include "llvm/Assembly/Writer.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCSectionMachO.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/CodeGen/DwarfWriter.h"
-#include "llvm/CodeGen/MachineJumpTableInfo.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/FormattedStream.h"
-#include "llvm/Support/Mangler.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/Target/TargetOptions.h"
-using namespace llvm;
-
-STATISTIC(EmittedInsts, "Number of machine instrs printed");
-
-static cl::opt<bool> NewAsmPrinter("experimental-asm-printer",
- cl::Hidden);
-
-//===----------------------------------------------------------------------===//
-// Primitive Helper Functions.
-//===----------------------------------------------------------------------===//
-
-void X86ATTAsmPrinter::PrintPICBaseSymbol() const {
- // FIXME: the actual label generated doesn't matter here! Just mangle in
- // something unique (the function number) with Private prefix.
- if (Subtarget->isTargetDarwin())
- O << "\"L" << getFunctionNumber() << "$pb\"";
- else {
- assert(Subtarget->isTargetELF() && "Don't know how to print PIC label!");
- O << ".Lllvm$" << getFunctionNumber() << ".$piclabel";
- }
-}
-
-MCSymbol *X86ATTAsmPrinter::GetPICBaseSymbol() {
- // FIXME: the actual label generated doesn't matter here! Just mangle in
- // something unique (the function number) with Private prefix.
- std::string Name;
-
- if (Subtarget->isTargetDarwin()) {
- Name = "L" + utostr(getFunctionNumber())+"$pb";
- } else {
- assert(Subtarget->isTargetELF() && "Don't know how to print PIC label!");
- Name = ".Lllvm$" + utostr(getFunctionNumber())+".$piclabel";
- }
- return OutContext.GetOrCreateSymbol(Name);
-}
-
-static X86MachineFunctionInfo calculateFunctionInfo(const Function *F,
- const TargetData *TD) {
- X86MachineFunctionInfo Info;
- uint64_t Size = 0;
-
- switch (F->getCallingConv()) {
- case CallingConv::X86_StdCall:
- Info.setDecorationStyle(StdCall);
- break;
- case CallingConv::X86_FastCall:
- Info.setDecorationStyle(FastCall);
- break;
- default:
- return Info;
- }
-
- unsigned argNum = 1;
- for (Function::const_arg_iterator AI = F->arg_begin(), AE = F->arg_end();
- AI != AE; ++AI, ++argNum) {
- const Type* Ty = AI->getType();
-
- // 'Dereference' type in case of byval parameter attribute
- if (F->paramHasAttr(argNum, Attribute::ByVal))
- Ty = cast<PointerType>(Ty)->getElementType();
-
- // Size should be aligned to DWORD boundary
- Size += ((TD->getTypeAllocSize(Ty) + 3)/4)*4;
- }
-
- // We're not supporting tooooo huge arguments :)
- Info.setBytesToPopOnReturn((unsigned int)Size);
- return Info;
-}
-
-/// DecorateCygMingName - Query FunctionInfoMap and use this information for
-/// various name decorations for Cygwin and MingW.
-void X86ATTAsmPrinter::DecorateCygMingName(std::string &Name,
- const GlobalValue *GV) {
- assert(Subtarget->isTargetCygMing() && "This is only for cygwin and mingw");
-
- const Function *F = dyn_cast<Function>(GV);
- if (!F) return;
-
- // Save function name for later type emission.
- if (F->isDeclaration())
- CygMingStubs.insert(Name);
-
- // We don't want to decorate non-stdcall or non-fastcall functions right now
- unsigned CC = F->getCallingConv();
- if (CC != CallingConv::X86_StdCall && CC != CallingConv::X86_FastCall)
- return;
-
-
- const X86MachineFunctionInfo *Info;
-
- FMFInfoMap::const_iterator info_item = FunctionInfoMap.find(F);
- if (info_item == FunctionInfoMap.end()) {
- // Calculate apropriate function info and populate map
- FunctionInfoMap[F] = calculateFunctionInfo(F, TM.getTargetData());
- Info = &FunctionInfoMap[F];
- } else {
- Info = &info_item->second;
- }
-
- const FunctionType *FT = F->getFunctionType();
- switch (Info->getDecorationStyle()) {
- case None:
- break;
- case StdCall:
- // "Pure" variadic functions do not receive @0 suffix.
- if (!FT->isVarArg() || (FT->getNumParams() == 0) ||
- (FT->getNumParams() == 1 && F->hasStructRetAttr()))
- Name += '@' + utostr_32(Info->getBytesToPopOnReturn());
- break;
- case FastCall:
- // "Pure" variadic functions do not receive @0 suffix.
- if (!FT->isVarArg() || (FT->getNumParams() == 0) ||
- (FT->getNumParams() == 1 && F->hasStructRetAttr()))
- Name += '@' + utostr_32(Info->getBytesToPopOnReturn());
-
- if (Name[0] == '_') {
- Name[0] = '@';
- } else {
- Name = '@' + Name;
- }
- break;
- default:
- llvm_unreachable("Unsupported DecorationStyle");
- }
-}
-
-void X86ATTAsmPrinter::emitFunctionHeader(const MachineFunction &MF) {
- unsigned FnAlign = MF.getAlignment();
- const Function *F = MF.getFunction();
-
- if (Subtarget->isTargetCygMing())
- DecorateCygMingName(CurrentFnName, F);
-
- OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
- EmitAlignment(FnAlign, F);
-
- switch (F->getLinkage()) {
- default: llvm_unreachable("Unknown linkage type!");
- case Function::InternalLinkage: // Symbols default to internal.
- case Function::PrivateLinkage:
- break;
- case Function::DLLExportLinkage:
- case Function::ExternalLinkage:
- O << "\t.globl\t" << CurrentFnName << '\n';
- break;
- case Function::LinkerPrivateLinkage:
- case Function::LinkOnceAnyLinkage:
- case Function::LinkOnceODRLinkage:
- case Function::WeakAnyLinkage:
- case Function::WeakODRLinkage:
- if (Subtarget->isTargetDarwin()) {
- O << "\t.globl\t" << CurrentFnName << '\n';
- O << MAI->getWeakDefDirective() << CurrentFnName << '\n';
- } else if (Subtarget->isTargetCygMing()) {
- O << "\t.globl\t" << CurrentFnName << "\n"
- "\t.linkonce discard\n";
- } else {
- O << "\t.weak\t" << CurrentFnName << '\n';
- }
- break;
- }
-
- printVisibility(CurrentFnName, F->getVisibility());
-
- if (Subtarget->isTargetELF())
- O << "\t.type\t" << CurrentFnName << ", at function\n";
- else if (Subtarget->isTargetCygMing()) {
- O << "\t.def\t " << CurrentFnName
- << ";\t.scl\t" <<
- (F->hasInternalLinkage() ? COFF::C_STAT : COFF::C_EXT)
- << ";\t.type\t" << (COFF::DT_FCN << COFF::N_BTSHFT)
- << ";\t.endef\n";
- }
-
- O << CurrentFnName << ':';
- if (VerboseAsm) {
- O.PadToColumn(MAI->getCommentColumn());
- O << MAI->getCommentString() << ' ';
- WriteAsOperand(O, F, /*PrintType=*/false, F->getParent());
- }
- O << '\n';
-
- // Add some workaround for linkonce linkage on Cygwin\MinGW
- if (Subtarget->isTargetCygMing() &&
- (F->hasLinkOnceLinkage() || F->hasWeakLinkage()))
- O << "Lllvm$workaround$fake$stub$" << CurrentFnName << ":\n";
-}
-
-/// runOnMachineFunction - This uses the printMachineInstruction()
-/// method to print assembly for each instruction.
-///
-bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
- const Function *F = MF.getFunction();
- this->MF = &MF;
- unsigned CC = F->getCallingConv();
-
- SetupMachineFunction(MF);
- O << "\n\n";
-
- // Populate function information map. Actually, We don't want to populate
- // non-stdcall or non-fastcall functions' information right now.
- if (CC == CallingConv::X86_StdCall || CC == CallingConv::X86_FastCall)
- FunctionInfoMap[F] = *MF.getInfo<X86MachineFunctionInfo>();
-
- // Print out constants referenced by the function
- EmitConstantPool(MF.getConstantPool());
-
- if (F->hasDLLExportLinkage())
- DLLExportedFns.insert(Mang->getMangledName(F));
-
- // Print the 'header' of function
- emitFunctionHeader(MF);
-
- // Emit pre-function debug and/or EH information.
- if (MAI->doesSupportDebugInformation() || MAI->doesSupportExceptionHandling())
- DW->BeginFunction(&MF);
-
- // Print out code for the function.
- bool hasAnyRealCode = false;
- for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
- I != E; ++I) {
- // Print a label for the basic block.
- if (!VerboseAsm && (I->pred_empty() || I->isOnlyReachableByFallthrough())) {
- // This is an entry block or a block that's only reachable via a
- // fallthrough edge. In non-VerboseAsm mode, don't print the label.
- } else {
- printBasicBlockLabel(I, true, true, VerboseAsm);
- O << '\n';
- }
- for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
- II != IE; ++II) {
- // Print the assembly for the instruction.
- if (!II->isLabel())
- hasAnyRealCode = true;
- printMachineInstruction(II);
- }
- }
-
- if (Subtarget->isTargetDarwin() && !hasAnyRealCode) {
- // If the function is empty, then we need to emit *something*. Otherwise,
- // the function's label might be associated with something that it wasn't
- // meant to be associated with. We emit a noop in this situation.
- // We are assuming inline asms are code.
- O << "\tnop\n";
- }
-
- if (MAI->hasDotTypeDotSizeDirective())
- O << "\t.size\t" << CurrentFnName << ", .-" << CurrentFnName << '\n';
-
- // Emit post-function debug information.
- if (MAI->doesSupportDebugInformation() || MAI->doesSupportExceptionHandling())
- DW->EndFunction(&MF);
-
- // Print out jump tables referenced by the function.
- EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
-
- // We didn't modify anything.
- return false;
-}
-
-/// printSymbolOperand - Print a raw symbol reference operand. This handles
-/// jump tables, constant pools, global address and external symbols, all of
-/// which print to a label with various suffixes for relocation types etc.
-void X86ATTAsmPrinter::printSymbolOperand(const MachineOperand &MO) {
- switch (MO.getType()) {
- default: llvm_unreachable("unknown symbol type!");
- case MachineOperand::MO_JumpTableIndex:
- O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_'
- << MO.getIndex();
- break;
- case MachineOperand::MO_ConstantPoolIndex:
- O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_'
- << MO.getIndex();
- printOffset(MO.getOffset());
- break;
- case MachineOperand::MO_GlobalAddress: {
- const GlobalValue *GV = MO.getGlobal();
-
- const char *Suffix = "";
- if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB)
- Suffix = "$stub";
- else if (MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
- MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
- MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY ||
- MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
- Suffix = "$non_lazy_ptr";
-
- std::string Name = Mang->getMangledName(GV, Suffix, Suffix[0] != '\0');
- if (Subtarget->isTargetCygMing())
- DecorateCygMingName(Name, GV);
-
- // Handle dllimport linkage.
- if (MO.getTargetFlags() == X86II::MO_DLLIMPORT)
- Name = "__imp_" + Name;
-
- if (MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
- MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE)
- GVStubs[Name] = Mang->getMangledName(GV);
- else if (MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY ||
- MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
- HiddenGVStubs[Name] = Mang->getMangledName(GV);
- else if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB)
- FnStubs[Name] = Mang->getMangledName(GV);
-
- // If the name begins with a dollar-sign, enclose it in parens. We do this
- // to avoid having it look like an integer immediate to the assembler.
- if (Name[0] == '$')
- O << '(' << Name << ')';
- else
- O << Name;
-
- printOffset(MO.getOffset());
- break;
- }
- case MachineOperand::MO_ExternalSymbol: {
- std::string Name = Mang->makeNameProper(MO.getSymbolName());
- if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB) {
- FnStubs[Name+"$stub"] = Name;
- Name += "$stub";
- }
-
- // If the name begins with a dollar-sign, enclose it in parens. We do this
- // to avoid having it look like an integer immediate to the assembler.
- if (Name[0] == '$')
- O << '(' << Name << ')';
- else
- O << Name;
- break;
- }
- }
-
- switch (MO.getTargetFlags()) {
- default:
- llvm_unreachable("Unknown target flag on GV operand");
- case X86II::MO_NO_FLAG: // No flag.
- break;
- case X86II::MO_DARWIN_NONLAZY:
- case X86II::MO_DARWIN_HIDDEN_NONLAZY:
- case X86II::MO_DLLIMPORT:
- case X86II::MO_DARWIN_STUB:
- // These affect the name of the symbol, not any suffix.
- break;
- case X86II::MO_GOT_ABSOLUTE_ADDRESS:
- O << " + [.-";
- PrintPICBaseSymbol();
- O << ']';
- break;
- case X86II::MO_PIC_BASE_OFFSET:
- case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
- case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
- O << '-';
- PrintPICBaseSymbol();
- break;
- case X86II::MO_TLSGD: O << "@TLSGD"; break;
- case X86II::MO_GOTTPOFF: O << "@GOTTPOFF"; break;
- case X86II::MO_INDNTPOFF: O << "@INDNTPOFF"; break;
- case X86II::MO_TPOFF: O << "@TPOFF"; break;
- case X86II::MO_NTPOFF: O << "@NTPOFF"; break;
- case X86II::MO_GOTPCREL: O << "@GOTPCREL"; break;
- case X86II::MO_GOT: O << "@GOT"; break;
- case X86II::MO_GOTOFF: O << "@GOTOFF"; break;
- case X86II::MO_PLT: O << "@PLT"; break;
- }
-}
-
-/// print_pcrel_imm - This is used to print an immediate value that ends up
-/// being encoded as a pc-relative value. These print slightly differently, for
-/// example, a $ is not emitted.
-void X86ATTAsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo) {
- const MachineOperand &MO = MI->getOperand(OpNo);
- switch (MO.getType()) {
- default: llvm_unreachable("Unknown pcrel immediate operand");
- case MachineOperand::MO_Immediate:
- O << MO.getImm();
- return;
- case MachineOperand::MO_MachineBasicBlock:
- printBasicBlockLabel(MO.getMBB(), false, false, false);
- return;
- case MachineOperand::MO_GlobalAddress:
- case MachineOperand::MO_ExternalSymbol:
- printSymbolOperand(MO);
- return;
- }
-}
-
-
-
-void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
- const char *Modifier) {
- const MachineOperand &MO = MI->getOperand(OpNo);
- switch (MO.getType()) {
- default: llvm_unreachable("unknown operand type!");
- case MachineOperand::MO_Register: {
- assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- "Virtual registers should not make it this far!");
- O << '%';
- unsigned Reg = MO.getReg();
- if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
- EVT VT = (strcmp(Modifier+6,"64") == 0) ?
- MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
- ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
- Reg = getX86SubSuperRegister(Reg, VT);
- }
- O << TRI->getAsmName(Reg);
- return;
- }
-
- case MachineOperand::MO_Immediate:
- O << '$' << MO.getImm();
- return;
-
- case MachineOperand::MO_JumpTableIndex:
- case MachineOperand::MO_ConstantPoolIndex:
- case MachineOperand::MO_GlobalAddress:
- case MachineOperand::MO_ExternalSymbol: {
- O << '$';
- printSymbolOperand(MO);
- break;
- }
- }
-}
-
-void X86ATTAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
- unsigned char value = MI->getOperand(Op).getImm();
- assert(value <= 7 && "Invalid ssecc argument!");
- switch (value) {
- case 0: O << "eq"; break;
- case 1: O << "lt"; break;
- case 2: O << "le"; break;
- case 3: O << "unord"; break;
- case 4: O << "neq"; break;
- case 5: O << "nlt"; break;
- case 6: O << "nle"; break;
- case 7: O << "ord"; break;
- }
-}
-
-void X86ATTAsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
- const char *Modifier) {
- const MachineOperand &BaseReg = MI->getOperand(Op);
- const MachineOperand &IndexReg = MI->getOperand(Op+2);
- const MachineOperand &DispSpec = MI->getOperand(Op+3);
-
- // If we really don't want to print out (rip), don't.
- bool HasBaseReg = BaseReg.getReg() != 0;
- if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") &&
- BaseReg.getReg() == X86::RIP)
- HasBaseReg = false;
-
- // HasParenPart - True if we will print out the () part of the mem ref.
- bool HasParenPart = IndexReg.getReg() || HasBaseReg;
-
- if (DispSpec.isImm()) {
- int DispVal = DispSpec.getImm();
- if (DispVal || !HasParenPart)
- O << DispVal;
- } else {
- assert(DispSpec.isGlobal() || DispSpec.isCPI() ||
- DispSpec.isJTI() || DispSpec.isSymbol());
- printSymbolOperand(MI->getOperand(Op+3));
- }
-
- if (HasParenPart) {
- assert(IndexReg.getReg() != X86::ESP &&
- "X86 doesn't allow scaling by ESP");
-
- O << '(';
- if (HasBaseReg)
- printOperand(MI, Op, Modifier);
-
- if (IndexReg.getReg()) {
- O << ',';
- printOperand(MI, Op+2, Modifier);
- unsigned ScaleVal = MI->getOperand(Op+1).getImm();
- if (ScaleVal != 1)
- O << ',' << ScaleVal;
- }
- O << ')';
- }
-}
-
-void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
- const char *Modifier) {
- assert(isMem(MI, Op) && "Invalid memory reference!");
- const MachineOperand &Segment = MI->getOperand(Op+4);
- if (Segment.getReg()) {
- printOperand(MI, Op+4, Modifier);
- O << ':';
- }
- printLeaMemReference(MI, Op, Modifier);
-}
-
-void X86ATTAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
- const MachineBasicBlock *MBB) const {
- if (!MAI->getSetDirective())
- return;
-
- // We don't need .set machinery if we have GOT-style relocations
- if (Subtarget->isPICStyleGOT())
- return;
-
- O << MAI->getSetDirective() << ' ' << MAI->getPrivateGlobalPrefix()
- << getFunctionNumber() << '_' << uid << "_set_" << MBB->getNumber() << ',';
- printBasicBlockLabel(MBB, false, false, false);
- if (Subtarget->isPICStyleRIPRel())
- O << '-' << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
- << '_' << uid << '\n';
- else {
- O << '-';
- PrintPICBaseSymbol();
- O << '\n';
- }
-}
-
-
-void X86ATTAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
- PrintPICBaseSymbol();
- O << '\n';
- PrintPICBaseSymbol();
- O << ':';
-}
-
-
-void X86ATTAsmPrinter::printPICJumpTableEntry(const MachineJumpTableInfo *MJTI,
- const MachineBasicBlock *MBB,
- unsigned uid) const {
- const char *JTEntryDirective = MJTI->getEntrySize() == 4 ?
- MAI->getData32bitsDirective() : MAI->getData64bitsDirective();
-
- O << JTEntryDirective << ' ';
-
- if (Subtarget->isPICStyleRIPRel() || Subtarget->isPICStyleStubPIC()) {
- O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
- << '_' << uid << "_set_" << MBB->getNumber();
- } else if (Subtarget->isPICStyleGOT()) {
- printBasicBlockLabel(MBB, false, false, false);
- O << "@GOTOFF";
- } else
- printBasicBlockLabel(MBB, false, false, false);
-}
-
-bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode) {
- unsigned Reg = MO.getReg();
- switch (Mode) {
- default: return true; // Unknown mode.
- case 'b': // Print QImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i8);
- break;
- case 'h': // Print QImode high register
- Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
- break;
- case 'w': // Print HImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i16);
- break;
- case 'k': // Print SImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i32);
- break;
- case 'q': // Print DImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i64);
- break;
- }
-
- O << '%'<< TRI->getAsmName(Reg);
- return false;
-}
-
-/// PrintAsmOperand - Print out an operand for an inline asm expression.
-///
-bool X86ATTAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant,
- const char *ExtraCode) {
- // Does this asm operand have a single letter operand modifier?
- if (ExtraCode && ExtraCode[0]) {
- if (ExtraCode[1] != 0) return true; // Unknown modifier.
-
- const MachineOperand &MO = MI->getOperand(OpNo);
-
- switch (ExtraCode[0]) {
- default: return true; // Unknown modifier.
- case 'a': // This is an address. Currently only 'i' and 'r' are expected.
- if (MO.isImm()) {
- O << MO.getImm();
- return false;
- }
- if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol()) {
- printSymbolOperand(MO);
- return false;
- }
- if (MO.isReg()) {
- O << '(';
- printOperand(MI, OpNo);
- O << ')';
- return false;
- }
- return true;
-
- case 'c': // Don't print "$" before a global var name or constant.
- if (MO.isImm())
- O << MO.getImm();
- else if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol())
- printSymbolOperand(MO);
- else
- printOperand(MI, OpNo);
- return false;
-
- case 'A': // Print '*' before a register (it must be a register)
- if (MO.isReg()) {
- O << '*';
- printOperand(MI, OpNo);
- return false;
- }
- return true;
-
- case 'b': // Print QImode register
- case 'h': // Print QImode high register
- case 'w': // Print HImode register
- case 'k': // Print SImode register
- case 'q': // Print DImode register
- if (MO.isReg())
- return printAsmMRegister(MO, ExtraCode[0]);
- printOperand(MI, OpNo);
- return false;
-
- case 'P': // This is the operand of a call, treat specially.
- print_pcrel_imm(MI, OpNo);
- return false;
-
- case 'n': // Negate the immediate or print a '-' before the operand.
- // Note: this is a temporary solution. It should be handled target
- // independently as part of the 'MC' work.
- if (MO.isImm()) {
- O << -MO.getImm();
- return false;
- }
- O << '-';
- }
- }
-
- printOperand(MI, OpNo);
- return false;
-}
-
-bool X86ATTAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
- unsigned OpNo,
- unsigned AsmVariant,
- const char *ExtraCode) {
- if (ExtraCode && ExtraCode[0]) {
- if (ExtraCode[1] != 0) return true; // Unknown modifier.
-
- switch (ExtraCode[0]) {
- default: return true; // Unknown modifier.
- case 'b': // Print QImode register
- case 'h': // Print QImode high register
- case 'w': // Print HImode register
- case 'k': // Print SImode register
- case 'q': // Print SImode register
- // These only apply to registers, ignore on mem.
- break;
- case 'P': // Don't print @PLT, but do print as memory.
- printMemReference(MI, OpNo, "no-rip");
- return false;
- }
- }
- printMemReference(MI, OpNo);
- return false;
-}
-
-static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
- // Convert registers in the addr mode according to subreg64.
- for (unsigned i = 0; i != 4; ++i) {
- if (!MI->getOperand(i).isReg()) continue;
-
- unsigned Reg = MI->getOperand(i).getReg();
- if (Reg == 0) continue;
-
- MI->getOperand(i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
- }
-}
-
-/// LowerGlobalAddressOperand - Lower an MO_GlobalAddress operand to an
-/// MCOperand.
-MCOperand X86ATTAsmPrinter::LowerGlobalAddressOperand(const MachineOperand &MO){
- const GlobalValue *GV = MO.getGlobal();
-
- const char *Suffix = "";
- if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB)
- Suffix = "$stub";
- else if (MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
- MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
- MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY ||
- MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
- Suffix = "$non_lazy_ptr";
-
- std::string Name = Mang->getMangledName(GV, Suffix, Suffix[0] != '\0');
- if (Subtarget->isTargetCygMing())
- DecorateCygMingName(Name, GV);
-
- // Handle dllimport linkage.
- if (MO.getTargetFlags() == X86II::MO_DLLIMPORT)
- Name = "__imp_" + Name;
-
- if (MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
- MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE)
- GVStubs[Name] = Mang->getMangledName(GV);
- else if (MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY ||
- MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
- HiddenGVStubs[Name] = Mang->getMangledName(GV);
- else if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB)
- FnStubs[Name] = Mang->getMangledName(GV);
-
-
- // Handle target operand flags.
- // FIXME: This should be common between external symbols, constant pool etc.
- MCSymbol *NegatedSymbol = 0;
-
- switch (MO.getTargetFlags()) {
- default:
- llvm_unreachable("Unknown target flag on GV operand");
- case X86II::MO_NO_FLAG: // No flag.
- break;
- case X86II::MO_DARWIN_NONLAZY:
- case X86II::MO_DARWIN_HIDDEN_NONLAZY:
- case X86II::MO_DLLIMPORT:
- case X86II::MO_DARWIN_STUB:
- // These affect the name of the symbol, not any suffix.
- break;
- case X86II::MO_GOT_ABSOLUTE_ADDRESS:
- assert(0 && "Reloc mode unimp!");
- //O << " + [.-";
- //PrintPICBaseSymbol();
- //O << ']';
- break;
- case X86II::MO_PIC_BASE_OFFSET:
- case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
- case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
- // Subtract the pic base.
- NegatedSymbol = GetPICBaseSymbol();
- break;
-
- // FIXME: These probably should be a modifier on the symbol or something??
- case X86II::MO_TLSGD: Name += "@TLSGD"; break;
- case X86II::MO_GOTTPOFF: Name += "@GOTTPOFF"; break;
- case X86II::MO_INDNTPOFF: Name += "@INDNTPOFF"; break;
- case X86II::MO_TPOFF: Name += "@TPOFF"; break;
- case X86II::MO_NTPOFF: Name += "@NTPOFF"; break;
- case X86II::MO_GOTPCREL: Name += "@GOTPCREL"; break;
- case X86II::MO_GOT: Name += "@GOT"; break;
- case X86II::MO_GOTOFF: Name += "@GOTOFF"; break;
- case X86II::MO_PLT: Name += "@PLT"; break;
- }
-
- // Create a symbol for the name.
- MCSymbol *Sym = OutContext.GetOrCreateSymbol(Name);
- // FIXME: We would like an efficient form for this, so we don't have to do a
- // lot of extra uniquing.
- const MCExpr *Expr = MCSymbolRefExpr::Create(Sym, OutContext);
- if (NegatedSymbol)
- Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(NegatedSymbol,
- OutContext),
- OutContext);
- Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(MO.getOffset(),
- OutContext),
- OutContext);
- return MCOperand::CreateExpr(Expr);
-}
-
-MCOperand X86ATTAsmPrinter::
-LowerExternalSymbolOperand(const MachineOperand &MO){
- std::string Name = Mang->makeNameProper(MO.getSymbolName());
- if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB) {
- FnStubs[Name+"$stub"] = Name;
- Name += "$stub";
- }
-
- MCSymbol *Sym = OutContext.GetOrCreateSymbol(Name);
- // FIXME: We would like an efficient form for this, so we don't have to do a
- // lot of extra uniquing.
- const MCExpr *Expr =
- MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(Sym, OutContext),
- MCConstantExpr::Create(MO.getOffset(),OutContext),
- OutContext);
- return MCOperand::CreateExpr(Expr);
-}
-
-
-/// printMachineInstruction -- Print out a single X86 LLVM instruction MI in
-/// AT&T syntax to the current output stream.
-///
-void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
- ++EmittedInsts;
-
- if (!NewAsmPrinter) {
- // Call the autogenerated instruction printer routines.
- printInstruction(MI);
- return;
- }
-
- MCInst TmpInst;
-
- switch (MI->getOpcode()) {
- case TargetInstrInfo::DBG_LABEL:
- case TargetInstrInfo::EH_LABEL:
- case TargetInstrInfo::GC_LABEL:
- printLabel(MI);
- return;
- case TargetInstrInfo::INLINEASM:
- O << '\t';
- printInlineAsm(MI);
- return;
- case TargetInstrInfo::IMPLICIT_DEF:
- printImplicitDef(MI);
- return;
- case X86::MOVPC32r: {
- // This is a pseudo op for a two instruction sequence with a label, which
- // looks like:
- // call "L1$pb"
- // "L1$pb":
- // popl %esi
-
- // Emit the call.
- MCSymbol *PICBase = GetPICBaseSymbol();
- TmpInst.setOpcode(X86::CALLpcrel32);
- // FIXME: We would like an efficient form for this, so we don't have to do a
- // lot of extra uniquing.
- TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
- OutContext)));
- printInstruction(&TmpInst);
-
- // Emit the label.
- OutStreamer.EmitLabel(PICBase);
-
- // popl $reg
- TmpInst.setOpcode(X86::POP32r);
- TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
- printInstruction(&TmpInst);
- O << "OLD: ";
- // Call the autogenerated instruction printer routines.
- printInstruction(MI);
- return;
- }
- }
-
- O << "NEW: ";
-
- TmpInst.setOpcode(MI->getOpcode());
-
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
-
- MCOperand MCOp;
- switch (MO.getType()) {
- default:
- O.flush();
- errs() << "Cannot lower operand #" << i << " of :" << *MI;
- llvm_unreachable("Unimp");
- case MachineOperand::MO_Register:
- MCOp = MCOperand::CreateReg(MO.getReg());
- break;
- case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
- break;
- case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateMBBLabel(getFunctionNumber(),
- MO.getMBB()->getNumber());
- break;
- case MachineOperand::MO_GlobalAddress:
- MCOp = LowerGlobalAddressOperand(MO);
- break;
- case MachineOperand::MO_ExternalSymbol:
- MCOp = LowerExternalSymbolOperand(MO);
- break;
- }
-
- TmpInst.addOperand(MCOp);
- }
-
- switch (TmpInst.getOpcode()) {
- case X86::LEA64_32r:
- // Handle the 'subreg rewriting' for the lea64_32mem operand.
- lower_lea64_32mem(&TmpInst, 1);
- break;
- }
-
- // FIXME: Convert TmpInst.
- printInstruction(&TmpInst);
- O << "OLD: ";
-
- // Call the autogenerated instruction printer routines.
- printInstruction(MI);
-}
-
-void X86ATTAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
- const TargetData *TD = TM.getTargetData();
-
- if (!GVar->hasInitializer())
- return; // External global require no code
-
- // Check to see if this is a special global used by LLVM, if so, emit it.
- if (EmitSpecialLLVMGlobal(GVar)) {
- if (Subtarget->isTargetDarwin() &&
- TM.getRelocationModel() == Reloc::Static) {
- if (GVar->getName() == "llvm.global_ctors")
- O << ".reference .constructors_used\n";
- else if (GVar->getName() == "llvm.global_dtors")
- O << ".reference .destructors_used\n";
- }
- return;
- }
-
- std::string name = Mang->getMangledName(GVar);
- Constant *C = GVar->getInitializer();
- const Type *Type = C->getType();
- unsigned Size = TD->getTypeAllocSize(Type);
- unsigned Align = TD->getPreferredAlignmentLog(GVar);
-
- printVisibility(name, GVar->getVisibility());
-
- if (Subtarget->isTargetELF())
- O << "\t.type\t" << name << ", at object\n";
-
-
- SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GVar, TM);
- const MCSection *TheSection =
- getObjFileLowering().SectionForGlobal(GVar, GVKind, Mang, TM);
- OutStreamer.SwitchSection(TheSection);
-
- // FIXME: get this stuff from section kind flags.
- if (C->isNullValue() && !GVar->hasSection() &&
- // Don't put things that should go in the cstring section into "comm".
- !TheSection->getKind().isMergeableCString()) {
- if (GVar->hasExternalLinkage()) {
- if (const char *Directive = MAI->getZeroFillDirective()) {
- O << "\t.globl " << name << '\n';
- O << Directive << "__DATA, __common, " << name << ", "
- << Size << ", " << Align << '\n';
- return;
- }
- }
-
- if (!GVar->isThreadLocal() &&
- (GVar->hasLocalLinkage() || GVar->isWeakForLinker())) {
- if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
-
- if (MAI->getLCOMMDirective() != NULL) {
- if (GVar->hasLocalLinkage()) {
- O << MAI->getLCOMMDirective() << name << ',' << Size;
- if (Subtarget->isTargetDarwin())
- O << ',' << Align;
- } else if (Subtarget->isTargetDarwin() && !GVar->hasCommonLinkage()) {
- O << "\t.globl " << name << '\n'
- << MAI->getWeakDefDirective() << name << '\n';
- EmitAlignment(Align, GVar);
- O << name << ":";
- if (VerboseAsm) {
- O.PadToColumn(MAI->getCommentColumn());
- O << MAI->getCommentString() << ' ';
- WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
- }
- O << '\n';
- EmitGlobalConstant(C);
- return;
- } else {
- O << MAI->getCOMMDirective() << name << ',' << Size;
- if (MAI->getCOMMDirectiveTakesAlignment())
- O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
- }
- } else {
- if (!Subtarget->isTargetCygMing()) {
- if (GVar->hasLocalLinkage())
- O << "\t.local\t" << name << '\n';
- }
- O << MAI->getCOMMDirective() << name << ',' << Size;
- if (MAI->getCOMMDirectiveTakesAlignment())
- O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
- }
- if (VerboseAsm) {
- O.PadToColumn(MAI->getCommentColumn());
- O << MAI->getCommentString() << ' ';
- WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
- }
- O << '\n';
- return;
- }
- }
-
- switch (GVar->getLinkage()) {
- case GlobalValue::CommonLinkage:
- case GlobalValue::LinkOnceAnyLinkage:
- case GlobalValue::LinkOnceODRLinkage:
- case GlobalValue::WeakAnyLinkage:
- case GlobalValue::WeakODRLinkage:
- case GlobalValue::LinkerPrivateLinkage:
- if (Subtarget->isTargetDarwin()) {
- O << "\t.globl " << name << '\n'
- << MAI->getWeakDefDirective() << name << '\n';
- } else if (Subtarget->isTargetCygMing()) {
- O << "\t.globl\t" << name << "\n"
- "\t.linkonce same_size\n";
- } else {
- O << "\t.weak\t" << name << '\n';
- }
- break;
- case GlobalValue::DLLExportLinkage:
- case GlobalValue::AppendingLinkage:
- // FIXME: appending linkage variables should go into a section of
- // their name or something. For now, just emit them as external.
- case GlobalValue::ExternalLinkage:
- // If external or appending, declare as a global symbol
- O << "\t.globl " << name << '\n';
- // FALL THROUGH
- case GlobalValue::PrivateLinkage:
- case GlobalValue::InternalLinkage:
- break;
- default:
- llvm_unreachable("Unknown linkage type!");
- }
-
- EmitAlignment(Align, GVar);
- O << name << ":";
- if (VerboseAsm){
- O.PadToColumn(MAI->getCommentColumn());
- O << MAI->getCommentString() << ' ';
- WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
- }
- O << '\n';
-
- EmitGlobalConstant(C);
-
- if (MAI->hasDotTypeDotSizeDirective())
- O << "\t.size\t" << name << ", " << Size << '\n';
-}
-
-bool X86ATTAsmPrinter::doFinalization(Module &M) {
- // Print out module-level global variables here.
- for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();
- I != E; ++I) {
- if (I->hasDLLExportLinkage())
- DLLExportedGVs.insert(Mang->getMangledName(I));
- }
-
- if (Subtarget->isTargetDarwin()) {
- // All darwin targets use mach-o.
- TargetLoweringObjectFileMachO &TLOFMacho =
- static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
-
- // Add the (possibly multiple) personalities to the set of global value
- // stubs. Only referenced functions get into the Personalities list.
- if (MAI->doesSupportExceptionHandling() && MMI && !Subtarget->is64Bit()) {
- const std::vector<Function*> &Personalities = MMI->getPersonalities();
- for (unsigned i = 0, e = Personalities.size(); i != e; ++i) {
- if (Personalities[i])
- GVStubs[Mang->getMangledName(Personalities[i], "$non_lazy_ptr",
- true /*private label*/)] =
- Mang->getMangledName(Personalities[i]);
- }
- }
-
- // Output stubs for dynamically-linked functions
- if (!FnStubs.empty()) {
- const MCSection *TheSection =
- TLOFMacho.getMachOSection("__IMPORT", "__jump_table",
- MCSectionMachO::S_SYMBOL_STUBS |
- MCSectionMachO::S_ATTR_SELF_MODIFYING_CODE |
- MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
- 5, SectionKind::getMetadata());
- OutStreamer.SwitchSection(TheSection);
- for (StringMap<std::string>::iterator I = FnStubs.begin(),
- E = FnStubs.end(); I != E; ++I)
- O << I->getKeyData() << ":\n" << "\t.indirect_symbol " << I->second
- << "\n\thlt ; hlt ; hlt ; hlt ; hlt\n";
- O << '\n';
- }
-
- // Output stubs for external and common global variables.
- if (!GVStubs.empty()) {
- const MCSection *TheSection =
- TLOFMacho.getMachOSection("__IMPORT", "__pointers",
- MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS,
- SectionKind::getMetadata());
- OutStreamer.SwitchSection(TheSection);
- for (StringMap<std::string>::iterator I = GVStubs.begin(),
- E = GVStubs.end(); I != E; ++I)
- O << I->getKeyData() << ":\n\t.indirect_symbol "
- << I->second << "\n\t.long\t0\n";
- }
-
- if (!HiddenGVStubs.empty()) {
- OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
- EmitAlignment(2);
- for (StringMap<std::string>::iterator I = HiddenGVStubs.begin(),
- E = HiddenGVStubs.end(); I != E; ++I)
- O << I->getKeyData() << ":\n" << MAI->getData32bitsDirective()
- << I->second << '\n';
- }
-
- // Funny Darwin hack: This flag tells the linker that no global symbols
- // contain code that falls through to other global symbols (e.g. the obvious
- // implementation of multiple entry points). If this doesn't occur, the
- // linker can safely perform dead code stripping. Since LLVM never
- // generates code that does this, it is always safe to set.
- O << "\t.subsections_via_symbols\n";
- } else if (Subtarget->isTargetCygMing()) {
- // Emit type information for external functions
- for (StringSet<>::iterator i = CygMingStubs.begin(), e = CygMingStubs.end();
- i != e; ++i) {
- O << "\t.def\t " << i->getKeyData()
- << ";\t.scl\t" << COFF::C_EXT
- << ";\t.type\t" << (COFF::DT_FCN << COFF::N_BTSHFT)
- << ";\t.endef\n";
- }
- }
-
-
- // Output linker support code for dllexported globals on windows.
- if (!DLLExportedGVs.empty() || !DLLExportedFns.empty()) {
- // dllexport symbols only exist on coff targets.
- TargetLoweringObjectFileCOFF &TLOFMacho =
- static_cast<TargetLoweringObjectFileCOFF&>(getObjFileLowering());
-
- OutStreamer.SwitchSection(TLOFMacho.getCOFFSection(".section .drectve",true,
- SectionKind::getMetadata()));
-
- for (StringSet<>::iterator i = DLLExportedGVs.begin(),
- e = DLLExportedGVs.end(); i != e; ++i)
- O << "\t.ascii \" -export:" << i->getKeyData() << ",data\"\n";
-
- for (StringSet<>::iterator i = DLLExportedFns.begin(),
- e = DLLExportedFns.end();
- i != e; ++i)
- O << "\t.ascii \" -export:" << i->getKeyData() << "\"\n";
- }
-
- // Do common shutdown.
- return AsmPrinter::doFinalization(M);
-}
-
-// Include the auto-generated portion of the assembly writer.
-#include "X86GenAsmWriter.inc"
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
deleted file mode 100644
index ef8ba6c..0000000
--- a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
+++ /dev/null
@@ -1,228 +0,0 @@
-//===-- X86ATTAsmPrinter.h - Convert X86 LLVM code to AT&T assembly -------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// AT&T assembly code printer class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef X86ATTASMPRINTER_H
-#define X86ATTASMPRINTER_H
-
-#include "../X86.h"
-#include "../X86MachineFunctionInfo.h"
-#include "../X86TargetMachine.h"
-#include "llvm/ADT/StringSet.h"
-#include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/CodeGen/DwarfWriter.h"
-#include "llvm/CodeGen/MachineModuleInfo.h"
-#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/Support/Compiler.h"
-
-namespace llvm {
-
-class MachineJumpTableInfo;
-class MCContext;
-class MCInst;
-class MCOperand;
-class MCStreamer;
-class MCSymbol;
-
-class VISIBILITY_HIDDEN X86ATTAsmPrinter : public AsmPrinter {
- const X86Subtarget *Subtarget;
- public:
- explicit X86ATTAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
- const MCAsmInfo *T, bool V)
- : AsmPrinter(O, TM, T, V) {
- Subtarget = &TM.getSubtarget<X86Subtarget>();
- }
-
- virtual const char *getPassName() const {
- return "X86 AT&T-Style Assembly Printer";
- }
-
- void getAnalysisUsage(AnalysisUsage &AU) const {
- AU.setPreservesAll();
- if (Subtarget->isTargetDarwin() ||
- Subtarget->isTargetELF() ||
- Subtarget->isTargetCygMing()) {
- AU.addRequired<MachineModuleInfo>();
- }
- AU.addRequired<DwarfWriter>();
- AsmPrinter::getAnalysisUsage(AU);
- }
-
- bool doFinalization(Module &M);
-
- /// printInstruction - This method is automatically generated by tablegen
- /// from the instruction set description. This method returns true if the
- /// machine instruction was sufficiently described to print it, otherwise it
- /// returns false.
- void printInstruction(const MachineInstr *MI);
-
-
- // New MCInst printing stuff.
- void printInstruction(const MCInst *MI);
- MCSymbol *GetPICBaseSymbol();
- MCOperand LowerGlobalAddressOperand(const MachineOperand &MO);
- MCOperand LowerExternalSymbolOperand(const MachineOperand &MO);
-
- virtual void printMCInst(const MCInst *MI) { printInstruction(MI); }
-
- void printSymbolOperand(const MachineOperand &MO);
- void printOperand(const MCInst *MI, unsigned OpNo,
- const char *Modifier = 0);
- void printMemReference(const MCInst *MI, unsigned Op);
- void printLeaMemReference(const MCInst *MI, unsigned Op);
- void printSSECC(const MCInst *MI, unsigned Op);
- void printPICLabel(const MCInst *MI, unsigned Op);
- void print_pcrel_imm(const MCInst *MI, unsigned OpNo);
-
- void printi8mem(const MCInst *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printi16mem(const MCInst *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printi32mem(const MCInst *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printi64mem(const MCInst *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printi128mem(const MCInst *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printf32mem(const MCInst *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printf64mem(const MCInst *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printf80mem(const MCInst *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printf128mem(const MCInst *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printlea32mem(const MCInst *MI, unsigned OpNo) {
- printLeaMemReference(MI, OpNo);
- }
- void printlea64mem(const MCInst *MI, unsigned OpNo) {
- printLeaMemReference(MI, OpNo);
- }
- void printlea64_32mem(const MCInst *MI, unsigned OpNo) {
- printLeaMemReference(MI, OpNo);
- }
-
-
-
- // These methods are used by the tablegen'erated instruction printer.
- void printOperand(const MachineInstr *MI, unsigned OpNo,
- const char *Modifier = 0);
- void print_pcrel_imm(const MachineInstr *MI, unsigned OpNo);
- void printi8mem(const MachineInstr *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printi16mem(const MachineInstr *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printi32mem(const MachineInstr *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printi64mem(const MachineInstr *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printi128mem(const MachineInstr *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printi256mem(const MachineInstr *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printf32mem(const MachineInstr *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printf64mem(const MachineInstr *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printf80mem(const MachineInstr *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printf128mem(const MachineInstr *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printf256mem(const MachineInstr *MI, unsigned OpNo) {
- printMemReference(MI, OpNo);
- }
- void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
- printLeaMemReference(MI, OpNo);
- }
- void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
- printLeaMemReference(MI, OpNo);
- }
- void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
- printLeaMemReference(MI, OpNo, "subreg64");
- }
-
- bool printAsmMRegister(const MachineOperand &MO, char Mode);
- bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant, const char *ExtraCode);
- bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant, const char *ExtraCode);
-
- void printMachineInstruction(const MachineInstr *MI);
- void printSSECC(const MachineInstr *MI, unsigned Op);
- void printMemReference(const MachineInstr *MI, unsigned Op,
- const char *Modifier=NULL);
- void printLeaMemReference(const MachineInstr *MI, unsigned Op,
- const char *Modifier=NULL);
- void printPICJumpTableSetLabel(unsigned uid,
- const MachineBasicBlock *MBB) const;
- void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,
- const MachineBasicBlock *MBB) const {
- AsmPrinter::printPICJumpTableSetLabel(uid, uid2, MBB);
- }
- void printPICJumpTableEntry(const MachineJumpTableInfo *MJTI,
- const MachineBasicBlock *MBB,
- unsigned uid) const;
-
- void printPICLabel(const MachineInstr *MI, unsigned Op);
- void PrintGlobalVariable(const GlobalVariable* GVar);
-
- void PrintPICBaseSymbol() const;
-
- bool runOnMachineFunction(MachineFunction &F);
-
- void emitFunctionHeader(const MachineFunction &MF);
-
- // Necessary for Darwin to print out the apprioriate types of linker stubs
- StringMap<std::string> FnStubs, GVStubs, HiddenGVStubs;
-
- // Necessary for dllexport support
- StringSet<> CygMingStubs, DLLExportedFns, DLLExportedGVs;
-
- // We have to propagate some information about MachineFunction to
- // AsmPrinter. It's ok, when we're printing the function, since we have
- // access to MachineFunction and can get the appropriate MachineFunctionInfo.
- // Unfortunately, this is not possible when we're printing reference to
- // Function (e.g. calling it and so on). Even more, there is no way to get the
- // corresponding MachineFunctions: it can even be not created at all. That's
- // why we should use additional structure, when we're collecting all necessary
- // information.
- //
- // This structure is using e.g. for name decoration for stdcall & fastcall'ed
- // function, since we have to use arguments' size for decoration.
- typedef std::map<const Function*, X86MachineFunctionInfo> FMFInfoMap;
- FMFInfoMap FunctionInfoMap;
-
- void DecorateCygMingName(std::string &Name, const GlobalValue *GV);
-};
-
-} // end namespace llvm
-
-#endif
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
index ee79791..bc70ffe 100644
--- a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
@@ -13,12 +13,13 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "asm-printer"
+#include "X86ATTInstPrinter.h"
#include "llvm/MC/MCInst.h"
-#include "X86ATTAsmPrinter.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormattedStream.h"
+#include "X86GenInstrNames.inc"
using namespace llvm;
// Include the auto-generated portion of the assembly writer.
@@ -27,7 +28,9 @@ using namespace llvm;
#include "X86GenAsmWriter.inc"
#undef MachineInstr
-void X86ATTAsmPrinter::printSSECC(const MCInst *MI, unsigned Op) {
+void X86ATTInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
+
+void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
switch (MI->getOperand(Op).getImm()) {
default: llvm_unreachable("Invalid ssecc argument!");
case 0: O << "eq"; break;
@@ -41,67 +44,36 @@ void X86ATTAsmPrinter::printSSECC(const MCInst *MI, unsigned Op) {
}
}
-
-void X86ATTAsmPrinter::printPICLabel(const MCInst *MI, unsigned Op) {
- llvm_unreachable("This is only used for MOVPC32r,"
- "should lower before asm printing!");
-}
-
-
/// print_pcrel_imm - This is used to print an immediate value that ends up
/// being encoded as a pc-relative value. These print slightly differently, for
/// example, a $ is not emitted.
-void X86ATTAsmPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) {
+void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) {
const MCOperand &Op = MI->getOperand(OpNo);
-
if (Op.isImm())
O << Op.getImm();
- else if (Op.isExpr())
- Op.getExpr()->print(O);
- else if (Op.isMBBLabel())
- // FIXME: Keep in sync with printBasicBlockLabel. printBasicBlockLabel
- // should eventually call into this code, not the other way around.
- O << MAI->getPrivateGlobalPrefix() << "BB" << Op.getMBBLabelFunction()
- << '_' << Op.getMBBLabelBlock();
- else
- llvm_unreachable("Unknown pcrel immediate operand");
+ else {
+ assert(Op.isExpr() && "unknown pcrel immediate operand");
+ Op.getExpr()->print(O, &MAI);
+ }
}
-
-void X86ATTAsmPrinter::printOperand(const MCInst *MI, unsigned OpNo,
- const char *Modifier) {
+void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
+ const char *Modifier) {
assert(Modifier == 0 && "Modifiers should not be used");
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
- O << '%';
- unsigned Reg = Op.getReg();
-#if 0
- if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
- EVT VT = (strcmp(Modifier+6,"64") == 0) ?
- EVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? EVT::i32 :
- ((strcmp(Modifier+6,"16") == 0) ? EVT::i16 : EVT::i8));
- Reg = getX86SubSuperRegister(Reg, VT);
- }
-#endif
- O << TRI->getAsmName(Reg);
- return;
+ O << '%' << getRegisterName(Op.getReg());
} else if (Op.isImm()) {
- //if (!Modifier || (strcmp(Modifier, "debug") && strcmp(Modifier, "mem")))
- O << '$';
- O << Op.getImm();
- return;
- } else if (Op.isExpr()) {
+ O << '$' << Op.getImm();
+ } else {
+ assert(Op.isExpr() && "unknown operand kind in printOperand");
O << '$';
- Op.getExpr()->print(O);
- return;
+ Op.getExpr()->print(O, &MAI);
}
-
- O << "<<UNKNOWN OPERAND KIND>>";
}
-void X86ATTAsmPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
-
+void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
const MCOperand &BaseReg = MI->getOperand(Op);
const MCOperand &IndexReg = MI->getOperand(Op+2);
const MCOperand &DispSpec = MI->getOperand(Op+3);
@@ -110,22 +82,12 @@ void X86ATTAsmPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
int64_t DispVal = DispSpec.getImm();
if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
O << DispVal;
- } else if (DispSpec.isExpr()) {
- DispSpec.getExpr()->print(O);
} else {
- llvm_unreachable("non-immediate displacement for LEA?");
- //assert(DispSpec.isGlobal() || DispSpec.isCPI() ||
- // DispSpec.isJTI() || DispSpec.isSymbol());
- //printOperand(MI, Op+3, "mem");
+ assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
+ DispSpec.getExpr()->print(O, &MAI);
}
if (IndexReg.getReg() || BaseReg.getReg()) {
- // There are cases where we can end up with ESP/RSP in the indexreg slot.
- // If this happens, swap the base/index register to support assemblers that
- // don't work when the index is *SP.
- // FIXME: REMOVE THIS.
- assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP);
-
O << '(';
if (BaseReg.getReg())
printOperand(MI, Op);
@@ -141,9 +103,9 @@ void X86ATTAsmPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
}
}
-void X86ATTAsmPrinter::printMemReference(const MCInst *MI, unsigned Op) {
- const MCOperand &Segment = MI->getOperand(Op+4);
- if (Segment.getReg()) {
+void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op) {
+ // If this has a segment register, print it.
+ if (MI->getOperand(Op+4).getReg()) {
printOperand(MI, Op+4);
O << ':';
}
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h
new file mode 100644
index 0000000..5f28fa4
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h
@@ -0,0 +1,86 @@
+//===-- X86ATTInstPrinter.h - Convert X86 MCInst to assembly syntax -------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an X86 MCInst to AT&T style .s file syntax.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef X86_ATT_INST_PRINTER_H
+#define X86_ATT_INST_PRINTER_H
+
+#include "llvm/MC/MCInstPrinter.h"
+
+namespace llvm {
+ class MCOperand;
+
+class X86ATTInstPrinter : public MCInstPrinter {
+public:
+ X86ATTInstPrinter(raw_ostream &O, const MCAsmInfo &MAI)
+ : MCInstPrinter(O, MAI) {}
+
+
+ virtual void printInst(const MCInst *MI);
+
+ // Autogenerated by tblgen.
+ void printInstruction(const MCInst *MI);
+ static const char *getRegisterName(unsigned RegNo);
+
+
+ void printOperand(const MCInst *MI, unsigned OpNo,
+ const char *Modifier = 0);
+ void printMemReference(const MCInst *MI, unsigned Op);
+ void printLeaMemReference(const MCInst *MI, unsigned Op);
+ void printSSECC(const MCInst *MI, unsigned Op);
+ void print_pcrel_imm(const MCInst *MI, unsigned OpNo);
+
+ void printopaquemem(const MCInst *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+
+ void printi8mem(const MCInst *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printi16mem(const MCInst *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printi32mem(const MCInst *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printi64mem(const MCInst *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printi128mem(const MCInst *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printf32mem(const MCInst *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printf64mem(const MCInst *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printf80mem(const MCInst *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printf128mem(const MCInst *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printlea32mem(const MCInst *MI, unsigned OpNo) {
+ printLeaMemReference(MI, OpNo);
+ }
+ void printlea64mem(const MCInst *MI, unsigned OpNo) {
+ printLeaMemReference(MI, OpNo);
+ }
+ void printlea64_32mem(const MCInst *MI, unsigned OpNo) {
+ printLeaMemReference(MI, OpNo);
+ }
+};
+
+}
+
+#endif
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
index 3ca35c5..4f89b71 100644
--- a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
@@ -1,4 +1,4 @@
-//===-- X86AsmPrinter.cpp - Convert X86 LLVM IR to X86 assembly -----------===//
+//===-- X86AsmPrinter.cpp - Convert X86 LLVM code to AT&T assembly --------===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,35 +7,941 @@
//
//===----------------------------------------------------------------------===//
//
-// This file the shared super class printer that converts from our internal
-// representation of machine-dependent LLVM code to Intel and AT&T format
-// assembly language.
-// This printer is the output mechanism used by `llc'.
+// This file contains a printer that converts from our internal representation
+// of machine-dependent LLVM code to AT&T format assembly
+// language. This printer is the output mechanism used by `llc'.
//
//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "asm-printer"
+#include "X86AsmPrinter.h"
+#include "X86ATTInstPrinter.h"
+#include "X86IntelInstPrinter.h"
+#include "X86MCInstLower.h"
#include "X86.h"
-#include "X86ATTAsmPrinter.h"
-#include "X86IntelAsmPrinter.h"
+#include "X86COFF.h"
+#include "X86COFFMachineModuleInfo.h"
+#include "X86MachineFunctionInfo.h"
+#include "X86TargetMachine.h"
+#include "llvm/CallingConv.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/Module.h"
+#include "llvm/Type.h"
+#include "llvm/Assembly/Writer.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCSectionMachO.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSymbol.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineModuleInfoImpls.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/Mangler.h"
#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/Target/TargetLoweringObjectFile.h"
+#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegistry.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/Statistic.h"
using namespace llvm;
-/// createX86CodePrinterPass - Returns a pass that prints the X86 assembly code
-/// for a MachineFunction to the given output stream, using the given target
-/// machine description.
+STATISTIC(EmittedInsts, "Number of machine instrs printed");
+
+//===----------------------------------------------------------------------===//
+// Primitive Helper Functions.
+//===----------------------------------------------------------------------===//
+
+void X86AsmPrinter::printMCInst(const MCInst *MI) {
+ if (MAI->getAssemblerDialect() == 0)
+ X86ATTInstPrinter(O, *MAI).printInstruction(MI);
+ else
+ X86IntelInstPrinter(O, *MAI).printInstruction(MI);
+}
+
+void X86AsmPrinter::PrintPICBaseSymbol() const {
+ // FIXME: Gross const cast hack.
+ X86AsmPrinter *AP = const_cast<X86AsmPrinter*>(this);
+ X86MCInstLower(OutContext, 0, *AP).GetPICBaseSymbol()->print(O, MAI);
+}
+
+void X86AsmPrinter::emitFunctionHeader(const MachineFunction &MF) {
+ unsigned FnAlign = MF.getAlignment();
+ const Function *F = MF.getFunction();
+
+ if (Subtarget->isTargetCygMing()) {
+ X86COFFMachineModuleInfo &COFFMMI =
+ MMI->getObjFileInfo<X86COFFMachineModuleInfo>();
+ COFFMMI.DecorateCygMingName(CurrentFnName, F, *TM.getTargetData());
+ }
+
+ OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
+ EmitAlignment(FnAlign, F);
+
+ switch (F->getLinkage()) {
+ default: llvm_unreachable("Unknown linkage type!");
+ case Function::InternalLinkage: // Symbols default to internal.
+ case Function::PrivateLinkage:
+ break;
+ case Function::DLLExportLinkage:
+ case Function::ExternalLinkage:
+ O << "\t.globl\t" << CurrentFnName << '\n';
+ break;
+ case Function::LinkerPrivateLinkage:
+ case Function::LinkOnceAnyLinkage:
+ case Function::LinkOnceODRLinkage:
+ case Function::WeakAnyLinkage:
+ case Function::WeakODRLinkage:
+ if (Subtarget->isTargetDarwin()) {
+ O << "\t.globl\t" << CurrentFnName << '\n';
+ O << MAI->getWeakDefDirective() << CurrentFnName << '\n';
+ } else if (Subtarget->isTargetCygMing()) {
+ O << "\t.globl\t" << CurrentFnName << "\n"
+ "\t.linkonce discard\n";
+ } else {
+ O << "\t.weak\t" << CurrentFnName << '\n';
+ }
+ break;
+ }
+
+ printVisibility(CurrentFnName, F->getVisibility());
+
+ if (Subtarget->isTargetELF())
+ O << "\t.type\t" << CurrentFnName << ", at function\n";
+ else if (Subtarget->isTargetCygMing()) {
+ O << "\t.def\t " << CurrentFnName
+ << ";\t.scl\t" <<
+ (F->hasInternalLinkage() ? COFF::C_STAT : COFF::C_EXT)
+ << ";\t.type\t" << (COFF::DT_FCN << COFF::N_BTSHFT)
+ << ";\t.endef\n";
+ }
+
+ O << CurrentFnName << ':';
+ if (VerboseAsm) {
+ O.PadToColumn(MAI->getCommentColumn());
+ O << MAI->getCommentString() << ' ';
+ WriteAsOperand(O, F, /*PrintType=*/false, F->getParent());
+ }
+ O << '\n';
+
+ // Add some workaround for linkonce linkage on Cygwin\MinGW
+ if (Subtarget->isTargetCygMing() &&
+ (F->hasLinkOnceLinkage() || F->hasWeakLinkage()))
+ O << "Lllvm$workaround$fake$stub$" << CurrentFnName << ":\n";
+}
+
+/// runOnMachineFunction - This uses the printMachineInstruction()
+/// method to print assembly for each instruction.
///
-static AsmPrinter *createX86CodePrinterPass(formatted_raw_ostream &o,
- TargetMachine &tm,
- const MCAsmInfo *tai,
- bool verbose) {
- if (tm.getMCAsmInfo()->getAssemblerDialect() == 1)
- return new X86IntelAsmPrinter(o, tm, tai, verbose);
- return new X86ATTAsmPrinter(o, tm, tai, verbose);
+bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
+ const Function *F = MF.getFunction();
+ this->MF = &MF;
+ CallingConv::ID CC = F->getCallingConv();
+
+ SetupMachineFunction(MF);
+ O << "\n\n";
+
+ if (Subtarget->isTargetCOFF()) {
+ X86COFFMachineModuleInfo &COFFMMI =
+ MMI->getObjFileInfo<X86COFFMachineModuleInfo>();
+
+ // Populate function information map. Don't want to populate
+ // non-stdcall or non-fastcall functions' information right now.
+ if (CC == CallingConv::X86_StdCall || CC == CallingConv::X86_FastCall)
+ COFFMMI.AddFunctionInfo(F, *MF.getInfo<X86MachineFunctionInfo>());
+ }
+
+ // Print out constants referenced by the function
+ EmitConstantPool(MF.getConstantPool());
+
+ // Print the 'header' of function
+ emitFunctionHeader(MF);
+
+ // Emit pre-function debug and/or EH information.
+ if (MAI->doesSupportDebugInformation() || MAI->doesSupportExceptionHandling())
+ DW->BeginFunction(&MF);
+
+ // Print out code for the function.
+ bool hasAnyRealCode = false;
+ for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
+ I != E; ++I) {
+ // Print a label for the basic block.
+ if (!VerboseAsm && (I->pred_empty() || I->isOnlyReachableByFallthrough())) {
+ // This is an entry block or a block that's only reachable via a
+ // fallthrough edge. In non-VerboseAsm mode, don't print the label.
+ } else {
+ EmitBasicBlockStart(I);
+ O << '\n';
+ }
+ for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
+ II != IE; ++II) {
+ // Print the assembly for the instruction.
+ if (!II->isLabel())
+ hasAnyRealCode = true;
+ printMachineInstruction(II);
+ }
+ }
+
+ if (Subtarget->isTargetDarwin() && !hasAnyRealCode) {
+ // If the function is empty, then we need to emit *something*. Otherwise,
+ // the function's label might be associated with something that it wasn't
+ // meant to be associated with. We emit a noop in this situation.
+ // We are assuming inline asms are code.
+ O << "\tnop\n";
+ }
+
+ if (MAI->hasDotTypeDotSizeDirective())
+ O << "\t.size\t" << CurrentFnName << ", .-" << CurrentFnName << '\n';
+
+ // Emit post-function debug information.
+ if (MAI->doesSupportDebugInformation() || MAI->doesSupportExceptionHandling())
+ DW->EndFunction(&MF);
+
+ // Print out jump tables referenced by the function.
+ EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
+
+ // We didn't modify anything.
+ return false;
+}
+
+/// printSymbolOperand - Print a raw symbol reference operand. This handles
+/// jump tables, constant pools, global address and external symbols, all of
+/// which print to a label with various suffixes for relocation types etc.
+void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO) {
+ switch (MO.getType()) {
+ default: llvm_unreachable("unknown symbol type!");
+ case MachineOperand::MO_JumpTableIndex:
+ O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_'
+ << MO.getIndex();
+ break;
+ case MachineOperand::MO_ConstantPoolIndex:
+ O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_'
+ << MO.getIndex();
+ printOffset(MO.getOffset());
+ break;
+ case MachineOperand::MO_GlobalAddress: {
+ const GlobalValue *GV = MO.getGlobal();
+
+ const char *Suffix = "";
+ if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB)
+ Suffix = "$stub";
+ else if (MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
+ MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
+ MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
+ Suffix = "$non_lazy_ptr";
+
+ std::string Name = Mang->getMangledName(GV, Suffix, Suffix[0] != '\0');
+ if (Subtarget->isTargetCygMing()) {
+ X86COFFMachineModuleInfo &COFFMMI =
+ MMI->getObjFileInfo<X86COFFMachineModuleInfo>();
+ COFFMMI.DecorateCygMingName(Name, GV, *TM.getTargetData());
+ }
+
+ // Handle dllimport linkage.
+ if (MO.getTargetFlags() == X86II::MO_DLLIMPORT)
+ Name = "__imp_" + Name;
+
+ if (MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
+ MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE) {
+ SmallString<128> NameStr;
+ Mang->getNameWithPrefix(NameStr, GV, true);
+ NameStr += "$non_lazy_ptr";
+ MCSymbol *Sym = OutContext.GetOrCreateSymbol(NameStr.str());
+
+ const MCSymbol *&StubSym =
+ MMI->getObjFileInfo<MachineModuleInfoMachO>().getGVStubEntry(Sym);
+ if (StubSym == 0) {
+ NameStr.clear();
+ Mang->getNameWithPrefix(NameStr, GV, false);
+ StubSym = OutContext.GetOrCreateSymbol(NameStr.str());
+ }
+ } else if (MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE){
+ SmallString<128> NameStr;
+ Mang->getNameWithPrefix(NameStr, GV, true);
+ NameStr += "$non_lazy_ptr";
+ MCSymbol *Sym = OutContext.GetOrCreateSymbol(NameStr.str());
+ const MCSymbol *&StubSym =
+ MMI->getObjFileInfo<MachineModuleInfoMachO>().getHiddenGVStubEntry(Sym);
+ if (StubSym == 0) {
+ NameStr.clear();
+ Mang->getNameWithPrefix(NameStr, GV, false);
+ StubSym = OutContext.GetOrCreateSymbol(NameStr.str());
+ }
+ } else if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB) {
+ SmallString<128> NameStr;
+ Mang->getNameWithPrefix(NameStr, GV, true);
+ NameStr += "$stub";
+ MCSymbol *Sym = OutContext.GetOrCreateSymbol(NameStr.str());
+ const MCSymbol *&StubSym =
+ MMI->getObjFileInfo<MachineModuleInfoMachO>().getFnStubEntry(Sym);
+ if (StubSym == 0) {
+ NameStr.clear();
+ Mang->getNameWithPrefix(NameStr, GV, false);
+ StubSym = OutContext.GetOrCreateSymbol(NameStr.str());
+ }
+ }
+
+ // If the name begins with a dollar-sign, enclose it in parens. We do this
+ // to avoid having it look like an integer immediate to the assembler.
+ if (Name[0] == '$')
+ O << '(' << Name << ')';
+ else
+ O << Name;
+
+ printOffset(MO.getOffset());
+ break;
+ }
+ case MachineOperand::MO_ExternalSymbol: {
+ std::string Name = Mang->makeNameProper(MO.getSymbolName());
+ if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB) {
+ Name += "$stub";
+ MCSymbol *Sym = OutContext.GetOrCreateSymbol(Name);
+ const MCSymbol *&StubSym =
+ MMI->getObjFileInfo<MachineModuleInfoMachO>().getFnStubEntry(Sym);
+ if (StubSym == 0) {
+ Name.erase(Name.end()-5, Name.end());
+ StubSym = OutContext.GetOrCreateSymbol(Name);
+ }
+ }
+
+ // If the name begins with a dollar-sign, enclose it in parens. We do this
+ // to avoid having it look like an integer immediate to the assembler.
+ if (Name[0] == '$')
+ O << '(' << Name << ')';
+ else
+ O << Name;
+ break;
+ }
+ }
+
+ switch (MO.getTargetFlags()) {
+ default:
+ llvm_unreachable("Unknown target flag on GV operand");
+ case X86II::MO_NO_FLAG: // No flag.
+ break;
+ case X86II::MO_DARWIN_NONLAZY:
+ case X86II::MO_DLLIMPORT:
+ case X86II::MO_DARWIN_STUB:
+ // These affect the name of the symbol, not any suffix.
+ break;
+ case X86II::MO_GOT_ABSOLUTE_ADDRESS:
+ O << " + [.-";
+ PrintPICBaseSymbol();
+ O << ']';
+ break;
+ case X86II::MO_PIC_BASE_OFFSET:
+ case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
+ case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
+ O << '-';
+ PrintPICBaseSymbol();
+ break;
+ case X86II::MO_TLSGD: O << "@TLSGD"; break;
+ case X86II::MO_GOTTPOFF: O << "@GOTTPOFF"; break;
+ case X86II::MO_INDNTPOFF: O << "@INDNTPOFF"; break;
+ case X86II::MO_TPOFF: O << "@TPOFF"; break;
+ case X86II::MO_NTPOFF: O << "@NTPOFF"; break;
+ case X86II::MO_GOTPCREL: O << "@GOTPCREL"; break;
+ case X86II::MO_GOT: O << "@GOT"; break;
+ case X86II::MO_GOTOFF: O << "@GOTOFF"; break;
+ case X86II::MO_PLT: O << "@PLT"; break;
+ }
+}
+
+/// print_pcrel_imm - This is used to print an immediate value that ends up
+/// being encoded as a pc-relative value. These print slightly differently, for
+/// example, a $ is not emitted.
+void X86AsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo) {
+ const MachineOperand &MO = MI->getOperand(OpNo);
+ switch (MO.getType()) {
+ default: llvm_unreachable("Unknown pcrel immediate operand");
+ case MachineOperand::MO_Immediate:
+ O << MO.getImm();
+ return;
+ case MachineOperand::MO_MachineBasicBlock:
+ GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
+ return;
+ case MachineOperand::MO_GlobalAddress:
+ case MachineOperand::MO_ExternalSymbol:
+ printSymbolOperand(MO);
+ return;
+ }
+}
+
+
+void X86AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
+ const char *Modifier) {
+ const MachineOperand &MO = MI->getOperand(OpNo);
+ switch (MO.getType()) {
+ default: llvm_unreachable("unknown operand type!");
+ case MachineOperand::MO_Register: {
+ O << '%';
+ unsigned Reg = MO.getReg();
+ if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
+ EVT VT = (strcmp(Modifier+6,"64") == 0) ?
+ MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
+ ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
+ Reg = getX86SubSuperRegister(Reg, VT);
+ }
+ O << X86ATTInstPrinter::getRegisterName(Reg);
+ return;
+ }
+
+ case MachineOperand::MO_Immediate:
+ O << '$' << MO.getImm();
+ return;
+
+ case MachineOperand::MO_JumpTableIndex:
+ case MachineOperand::MO_ConstantPoolIndex:
+ case MachineOperand::MO_GlobalAddress:
+ case MachineOperand::MO_ExternalSymbol: {
+ O << '$';
+ printSymbolOperand(MO);
+ break;
+ }
+ }
+}
+
+void X86AsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
+ unsigned char value = MI->getOperand(Op).getImm();
+ assert(value <= 7 && "Invalid ssecc argument!");
+ switch (value) {
+ case 0: O << "eq"; break;
+ case 1: O << "lt"; break;
+ case 2: O << "le"; break;
+ case 3: O << "unord"; break;
+ case 4: O << "neq"; break;
+ case 5: O << "nlt"; break;
+ case 6: O << "nle"; break;
+ case 7: O << "ord"; break;
+ }
+}
+
+void X86AsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
+ const char *Modifier) {
+ const MachineOperand &BaseReg = MI->getOperand(Op);
+ const MachineOperand &IndexReg = MI->getOperand(Op+2);
+ const MachineOperand &DispSpec = MI->getOperand(Op+3);
+
+ // If we really don't want to print out (rip), don't.
+ bool HasBaseReg = BaseReg.getReg() != 0;
+ if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") &&
+ BaseReg.getReg() == X86::RIP)
+ HasBaseReg = false;
+
+ // HasParenPart - True if we will print out the () part of the mem ref.
+ bool HasParenPart = IndexReg.getReg() || HasBaseReg;
+
+ if (DispSpec.isImm()) {
+ int DispVal = DispSpec.getImm();
+ if (DispVal || !HasParenPart)
+ O << DispVal;
+ } else {
+ assert(DispSpec.isGlobal() || DispSpec.isCPI() ||
+ DispSpec.isJTI() || DispSpec.isSymbol());
+ printSymbolOperand(MI->getOperand(Op+3));
+ }
+
+ if (HasParenPart) {
+ assert(IndexReg.getReg() != X86::ESP &&
+ "X86 doesn't allow scaling by ESP");
+
+ O << '(';
+ if (HasBaseReg)
+ printOperand(MI, Op, Modifier);
+
+ if (IndexReg.getReg()) {
+ O << ',';
+ printOperand(MI, Op+2, Modifier);
+ unsigned ScaleVal = MI->getOperand(Op+1).getImm();
+ if (ScaleVal != 1)
+ O << ',' << ScaleVal;
+ }
+ O << ')';
+ }
+}
+
+void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
+ const char *Modifier) {
+ assert(isMem(MI, Op) && "Invalid memory reference!");
+ const MachineOperand &Segment = MI->getOperand(Op+4);
+ if (Segment.getReg()) {
+ printOperand(MI, Op+4, Modifier);
+ O << ':';
+ }
+ printLeaMemReference(MI, Op, Modifier);
+}
+
+void X86AsmPrinter::printPICJumpTableSetLabel(unsigned uid,
+ const MachineBasicBlock *MBB) const {
+ if (!MAI->getSetDirective())
+ return;
+
+ // We don't need .set machinery if we have GOT-style relocations
+ if (Subtarget->isPICStyleGOT())
+ return;
+
+ O << MAI->getSetDirective() << ' ' << MAI->getPrivateGlobalPrefix()
+ << getFunctionNumber() << '_' << uid << "_set_" << MBB->getNumber() << ',';
+
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
+
+ if (Subtarget->isPICStyleRIPRel())
+ O << '-' << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
+ << '_' << uid << '\n';
+ else {
+ O << '-';
+ PrintPICBaseSymbol();
+ O << '\n';
+ }
+}
+
+
+void X86AsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
+ PrintPICBaseSymbol();
+ O << '\n';
+ PrintPICBaseSymbol();
+ O << ':';
+}
+
+void X86AsmPrinter::printPICJumpTableEntry(const MachineJumpTableInfo *MJTI,
+ const MachineBasicBlock *MBB,
+ unsigned uid) const {
+ const char *JTEntryDirective = MJTI->getEntrySize() == 4 ?
+ MAI->getData32bitsDirective() : MAI->getData64bitsDirective();
+
+ O << JTEntryDirective << ' ';
+
+ if (Subtarget->isPICStyleRIPRel() || Subtarget->isPICStyleStubPIC()) {
+ O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
+ << '_' << uid << "_set_" << MBB->getNumber();
+ } else if (Subtarget->isPICStyleGOT()) {
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
+ O << "@GOTOFF";
+ } else
+ GetMBBSymbol(MBB->getNumber())->print(O, MAI);
+}
+
+bool X86AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode) {
+ unsigned Reg = MO.getReg();
+ switch (Mode) {
+ default: return true; // Unknown mode.
+ case 'b': // Print QImode register
+ Reg = getX86SubSuperRegister(Reg, MVT::i8);
+ break;
+ case 'h': // Print QImode high register
+ Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
+ break;
+ case 'w': // Print HImode register
+ Reg = getX86SubSuperRegister(Reg, MVT::i16);
+ break;
+ case 'k': // Print SImode register
+ Reg = getX86SubSuperRegister(Reg, MVT::i32);
+ break;
+ case 'q': // Print DImode register
+ Reg = getX86SubSuperRegister(Reg, MVT::i64);
+ break;
+ }
+
+ O << '%' << X86ATTInstPrinter::getRegisterName(Reg);
+ return false;
+}
+
+/// PrintAsmOperand - Print out an operand for an inline asm expression.
+///
+bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
+ unsigned AsmVariant,
+ const char *ExtraCode) {
+ // Does this asm operand have a single letter operand modifier?
+ if (ExtraCode && ExtraCode[0]) {
+ if (ExtraCode[1] != 0) return true; // Unknown modifier.
+
+ const MachineOperand &MO = MI->getOperand(OpNo);
+
+ switch (ExtraCode[0]) {
+ default: return true; // Unknown modifier.
+ case 'a': // This is an address. Currently only 'i' and 'r' are expected.
+ if (MO.isImm()) {
+ O << MO.getImm();
+ return false;
+ }
+ if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol()) {
+ printSymbolOperand(MO);
+ return false;
+ }
+ if (MO.isReg()) {
+ O << '(';
+ printOperand(MI, OpNo);
+ O << ')';
+ return false;
+ }
+ return true;
+
+ case 'c': // Don't print "$" before a global var name or constant.
+ if (MO.isImm())
+ O << MO.getImm();
+ else if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol())
+ printSymbolOperand(MO);
+ else
+ printOperand(MI, OpNo);
+ return false;
+
+ case 'A': // Print '*' before a register (it must be a register)
+ if (MO.isReg()) {
+ O << '*';
+ printOperand(MI, OpNo);
+ return false;
+ }
+ return true;
+
+ case 'b': // Print QImode register
+ case 'h': // Print QImode high register
+ case 'w': // Print HImode register
+ case 'k': // Print SImode register
+ case 'q': // Print DImode register
+ if (MO.isReg())
+ return printAsmMRegister(MO, ExtraCode[0]);
+ printOperand(MI, OpNo);
+ return false;
+
+ case 'P': // This is the operand of a call, treat specially.
+ print_pcrel_imm(MI, OpNo);
+ return false;
+
+ case 'n': // Negate the immediate or print a '-' before the operand.
+ // Note: this is a temporary solution. It should be handled target
+ // independently as part of the 'MC' work.
+ if (MO.isImm()) {
+ O << -MO.getImm();
+ return false;
+ }
+ O << '-';
+ }
+ }
+
+ printOperand(MI, OpNo);
+ return false;
+}
+
+bool X86AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
+ unsigned OpNo, unsigned AsmVariant,
+ const char *ExtraCode) {
+ if (ExtraCode && ExtraCode[0]) {
+ if (ExtraCode[1] != 0) return true; // Unknown modifier.
+
+ switch (ExtraCode[0]) {
+ default: return true; // Unknown modifier.
+ case 'b': // Print QImode register
+ case 'h': // Print QImode high register
+ case 'w': // Print HImode register
+ case 'k': // Print SImode register
+ case 'q': // Print SImode register
+ // These only apply to registers, ignore on mem.
+ break;
+ case 'P': // Don't print @PLT, but do print as memory.
+ printMemReference(MI, OpNo, "no-rip");
+ return false;
+ }
+ }
+ printMemReference(MI, OpNo);
+ return false;
+}
+
+
+
+/// printMachineInstruction -- Print out a single X86 LLVM instruction MI in
+/// AT&T syntax to the current output stream.
+///
+void X86AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
+ ++EmittedInsts;
+
+ processDebugLoc(MI);
+
+ printInstructionThroughMCStreamer(MI);
+
+ if (VerboseAsm && !MI->getDebugLoc().isUnknown())
+ EmitComments(*MI);
+ O << '\n';
+}
+
+void X86AsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
+ if (!GVar->hasInitializer())
+ return; // External global require no code
+
+ // Check to see if this is a special global used by LLVM, if so, emit it.
+ if (EmitSpecialLLVMGlobal(GVar)) {
+ if (Subtarget->isTargetDarwin() &&
+ TM.getRelocationModel() == Reloc::Static) {
+ if (GVar->getName() == "llvm.global_ctors")
+ O << ".reference .constructors_used\n";
+ else if (GVar->getName() == "llvm.global_dtors")
+ O << ".reference .destructors_used\n";
+ }
+ return;
+ }
+
+ const TargetData *TD = TM.getTargetData();
+
+ std::string name = Mang->getMangledName(GVar);
+ Constant *C = GVar->getInitializer();
+ const Type *Type = C->getType();
+ unsigned Size = TD->getTypeAllocSize(Type);
+ unsigned Align = TD->getPreferredAlignmentLog(GVar);
+
+ printVisibility(name, GVar->getVisibility());
+
+ if (Subtarget->isTargetELF())
+ O << "\t.type\t" << name << ", at object\n";
+
+
+ SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GVar, TM);
+ const MCSection *TheSection =
+ getObjFileLowering().SectionForGlobal(GVar, GVKind, Mang, TM);
+ OutStreamer.SwitchSection(TheSection);
+
+ // FIXME: get this stuff from section kind flags.
+ if (C->isNullValue() && !GVar->hasSection() &&
+ // Don't put things that should go in the cstring section into "comm".
+ !TheSection->getKind().isMergeableCString()) {
+ if (GVar->hasExternalLinkage()) {
+ if (const char *Directive = MAI->getZeroFillDirective()) {
+ O << "\t.globl " << name << '\n';
+ O << Directive << "__DATA, __common, " << name << ", "
+ << Size << ", " << Align << '\n';
+ return;
+ }
+ }
+
+ if (!GVar->isThreadLocal() &&
+ (GVar->hasLocalLinkage() || GVar->isWeakForLinker())) {
+ if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
+
+ if (MAI->getLCOMMDirective() != NULL) {
+ if (GVar->hasLocalLinkage()) {
+ O << MAI->getLCOMMDirective() << name << ',' << Size;
+ if (Subtarget->isTargetDarwin())
+ O << ',' << Align;
+ } else if (Subtarget->isTargetDarwin() && !GVar->hasCommonLinkage()) {
+ O << "\t.globl " << name << '\n'
+ << MAI->getWeakDefDirective() << name << '\n';
+ EmitAlignment(Align, GVar);
+ O << name << ":";
+ if (VerboseAsm) {
+ O.PadToColumn(MAI->getCommentColumn());
+ O << MAI->getCommentString() << ' ';
+ WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
+ }
+ O << '\n';
+ EmitGlobalConstant(C);
+ return;
+ } else {
+ O << MAI->getCOMMDirective() << name << ',' << Size;
+ if (MAI->getCOMMDirectiveTakesAlignment())
+ O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
+ }
+ } else {
+ if (!Subtarget->isTargetCygMing()) {
+ if (GVar->hasLocalLinkage())
+ O << "\t.local\t" << name << '\n';
+ }
+ O << MAI->getCOMMDirective() << name << ',' << Size;
+ if (MAI->getCOMMDirectiveTakesAlignment())
+ O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
+ }
+ if (VerboseAsm) {
+ O.PadToColumn(MAI->getCommentColumn());
+ O << MAI->getCommentString() << ' ';
+ WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
+ }
+ O << '\n';
+ return;
+ }
+ }
+
+ switch (GVar->getLinkage()) {
+ case GlobalValue::CommonLinkage:
+ case GlobalValue::LinkOnceAnyLinkage:
+ case GlobalValue::LinkOnceODRLinkage:
+ case GlobalValue::WeakAnyLinkage:
+ case GlobalValue::WeakODRLinkage:
+ case GlobalValue::LinkerPrivateLinkage:
+ if (Subtarget->isTargetDarwin()) {
+ O << "\t.globl " << name << '\n'
+ << MAI->getWeakDefDirective() << name << '\n';
+ } else if (Subtarget->isTargetCygMing()) {
+ O << "\t.globl\t" << name << "\n"
+ "\t.linkonce same_size\n";
+ } else {
+ O << "\t.weak\t" << name << '\n';
+ }
+ break;
+ case GlobalValue::DLLExportLinkage:
+ case GlobalValue::AppendingLinkage:
+ // FIXME: appending linkage variables should go into a section of
+ // their name or something. For now, just emit them as external.
+ case GlobalValue::ExternalLinkage:
+ // If external or appending, declare as a global symbol
+ O << "\t.globl " << name << '\n';
+ // FALL THROUGH
+ case GlobalValue::PrivateLinkage:
+ case GlobalValue::InternalLinkage:
+ break;
+ default:
+ llvm_unreachable("Unknown linkage type!");
+ }
+
+ EmitAlignment(Align, GVar);
+ O << name << ":";
+ if (VerboseAsm){
+ O.PadToColumn(MAI->getCommentColumn());
+ O << MAI->getCommentString() << ' ';
+ WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
+ }
+ O << '\n';
+
+ EmitGlobalConstant(C);
+
+ if (MAI->hasDotTypeDotSizeDirective())
+ O << "\t.size\t" << name << ", " << Size << '\n';
+}
+
+void X86AsmPrinter::EmitEndOfAsmFile(Module &M) {
+ if (Subtarget->isTargetDarwin()) {
+ // All darwin targets use mach-o.
+ TargetLoweringObjectFileMachO &TLOFMacho =
+ static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
+
+ MachineModuleInfoMachO &MMIMacho =
+ MMI->getObjFileInfo<MachineModuleInfoMachO>();
+
+ // Output stubs for dynamically-linked functions.
+ MachineModuleInfoMachO::SymbolListTy Stubs;
+
+ Stubs = MMIMacho.GetFnStubList();
+ if (!Stubs.empty()) {
+ const MCSection *TheSection =
+ TLOFMacho.getMachOSection("__IMPORT", "__jump_table",
+ MCSectionMachO::S_SYMBOL_STUBS |
+ MCSectionMachO::S_ATTR_SELF_MODIFYING_CODE |
+ MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
+ 5, SectionKind::getMetadata());
+ OutStreamer.SwitchSection(TheSection);
+
+ for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
+ Stubs[i].first->print(O, MAI);
+ O << ":\n" << "\t.indirect_symbol ";
+ // Get the MCSymbol without the $stub suffix.
+ Stubs[i].second->print(O, MAI);
+ O << "\n\thlt ; hlt ; hlt ; hlt ; hlt\n";
+ }
+ O << '\n';
+
+ Stubs.clear();
+ }
+
+ // Output stubs for external and common global variables.
+ Stubs = MMIMacho.GetGVStubList();
+ if (!Stubs.empty()) {
+ const MCSection *TheSection =
+ TLOFMacho.getMachOSection("__IMPORT", "__pointers",
+ MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS,
+ SectionKind::getMetadata());
+ OutStreamer.SwitchSection(TheSection);
+
+ for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
+ Stubs[i].first->print(O, MAI);
+ O << ":\n\t.indirect_symbol ";
+ Stubs[i].second->print(O, MAI);
+ O << "\n\t.long\t0\n";
+ }
+ Stubs.clear();
+ }
+
+ Stubs = MMIMacho.GetHiddenGVStubList();
+ if (!Stubs.empty()) {
+ OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
+ EmitAlignment(2);
+
+ for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
+ Stubs[i].first->print(O, MAI);
+ O << ":\n" << MAI->getData32bitsDirective();
+ Stubs[i].second->print(O, MAI);
+ O << '\n';
+ }
+ Stubs.clear();
+ }
+
+ // Funny Darwin hack: This flag tells the linker that no global symbols
+ // contain code that falls through to other global symbols (e.g. the obvious
+ // implementation of multiple entry points). If this doesn't occur, the
+ // linker can safely perform dead code stripping. Since LLVM never
+ // generates code that does this, it is always safe to set.
+ O << "\t.subsections_via_symbols\n";
+ }
+
+ if (Subtarget->isTargetCOFF()) {
+ // Necessary for dllexport support
+ std::vector<std::string> DLLExportedFns, DLLExportedGlobals;
+
+ X86COFFMachineModuleInfo &COFFMMI =
+ MMI->getObjFileInfo<X86COFFMachineModuleInfo>();
+ TargetLoweringObjectFileCOFF &TLOFCOFF =
+ static_cast<TargetLoweringObjectFileCOFF&>(getObjFileLowering());
+
+ for (Module::const_iterator I = M.begin(), E = M.end(); I != E; ++I)
+ if (I->hasDLLExportLinkage())
+ DLLExportedFns.push_back(Mang->getMangledName(I));
+
+ for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();
+ I != E; ++I)
+ if (I->hasDLLExportLinkage())
+ DLLExportedGlobals.push_back(Mang->getMangledName(I));
+
+ if (Subtarget->isTargetCygMing()) {
+ // Emit type information for external functions
+ for (X86COFFMachineModuleInfo::stub_iterator I = COFFMMI.stub_begin(),
+ E = COFFMMI.stub_end(); I != E; ++I) {
+ O << "\t.def\t " << I->getKeyData()
+ << ";\t.scl\t" << COFF::C_EXT
+ << ";\t.type\t" << (COFF::DT_FCN << COFF::N_BTSHFT)
+ << ";\t.endef\n";
+ }
+ }
+
+ // Output linker support code for dllexported globals on windows.
+ if (!DLLExportedGlobals.empty() || !DLLExportedFns.empty()) {
+ OutStreamer.SwitchSection(TLOFCOFF.getCOFFSection(".section .drectve",
+ true,
+ SectionKind::getMetadata()));
+
+ for (unsigned i = 0, e = DLLExportedGlobals.size(); i != e; ++i)
+ O << "\t.ascii \" -export:" << DLLExportedGlobals[i] << ",data\"\n";
+
+ for (unsigned i = 0, e = DLLExportedFns.size(); i != e; ++i)
+ O << "\t.ascii \" -export:" << DLLExportedFns[i] << "\"\n";
+ }
+ }
+}
+
+
+//===----------------------------------------------------------------------===//
+// Target Registry Stuff
+//===----------------------------------------------------------------------===//
+
+static MCInstPrinter *createX86MCInstPrinter(const Target &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI,
+ raw_ostream &O) {
+ if (SyntaxVariant == 0)
+ return new X86ATTInstPrinter(O, MAI);
+ if (SyntaxVariant == 1)
+ return new X86IntelInstPrinter(O, MAI);
+ return 0;
}
// Force static initialization.
extern "C" void LLVMInitializeX86AsmPrinter() {
- TargetRegistry::RegisterAsmPrinter(TheX86_32Target, createX86CodePrinterPass);
- TargetRegistry::RegisterAsmPrinter(TheX86_64Target, createX86CodePrinterPass);
+ RegisterAsmPrinter<X86AsmPrinter> X(TheX86_32Target);
+ RegisterAsmPrinter<X86AsmPrinter> Y(TheX86_64Target);
+
+ TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,createX86MCInstPrinter);
+ TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,createX86MCInstPrinter);
}
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86AsmPrinter.h b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86AsmPrinter.h
new file mode 100644
index 0000000..0351829
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86AsmPrinter.h
@@ -0,0 +1,150 @@
+//===-- X86AsmPrinter.h - Convert X86 LLVM code to assembly -----*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// AT&T assembly code printer class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef X86ASMPRINTER_H
+#define X86ASMPRINTER_H
+
+#include "../X86.h"
+#include "../X86MachineFunctionInfo.h"
+#include "../X86TargetMachine.h"
+#include "llvm/ADT/StringSet.h"
+#include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/CodeGen/DwarfWriter.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/Support/Compiler.h"
+
+namespace llvm {
+
+class MachineJumpTableInfo;
+class MCContext;
+class MCInst;
+class MCStreamer;
+class MCSymbol;
+
+class VISIBILITY_HIDDEN X86AsmPrinter : public AsmPrinter {
+ const X86Subtarget *Subtarget;
+ public:
+ explicit X86AsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
+ const MCAsmInfo *T, bool V)
+ : AsmPrinter(O, TM, T, V) {
+ Subtarget = &TM.getSubtarget<X86Subtarget>();
+ }
+
+ virtual const char *getPassName() const {
+ return "X86 AT&T-Style Assembly Printer";
+ }
+
+ const X86Subtarget &getSubtarget() const { return *Subtarget; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesAll();
+ AU.addRequired<MachineModuleInfo>();
+ AU.addRequired<DwarfWriter>();
+ AsmPrinter::getAnalysisUsage(AU);
+ }
+
+
+ virtual void EmitEndOfAsmFile(Module &M);
+
+ void printInstructionThroughMCStreamer(const MachineInstr *MI);
+
+
+ void printMCInst(const MCInst *MI);
+
+ void printSymbolOperand(const MachineOperand &MO);
+
+
+
+ // These methods are used by the tablegen'erated instruction printer.
+ void printOperand(const MachineInstr *MI, unsigned OpNo,
+ const char *Modifier = 0);
+ void print_pcrel_imm(const MachineInstr *MI, unsigned OpNo);
+
+ void printopaquemem(const MachineInstr *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+
+ void printi8mem(const MachineInstr *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printi16mem(const MachineInstr *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printi32mem(const MachineInstr *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printi64mem(const MachineInstr *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printi128mem(const MachineInstr *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printf32mem(const MachineInstr *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printf64mem(const MachineInstr *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printf80mem(const MachineInstr *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printf128mem(const MachineInstr *MI, unsigned OpNo) {
+ printMemReference(MI, OpNo);
+ }
+ void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
+ printLeaMemReference(MI, OpNo);
+ }
+ void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
+ printLeaMemReference(MI, OpNo);
+ }
+ void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
+ printLeaMemReference(MI, OpNo, "subreg64");
+ }
+
+ bool printAsmMRegister(const MachineOperand &MO, char Mode);
+ bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
+ unsigned AsmVariant, const char *ExtraCode);
+ bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
+ unsigned AsmVariant, const char *ExtraCode);
+
+ void printMachineInstruction(const MachineInstr *MI);
+ void printSSECC(const MachineInstr *MI, unsigned Op);
+ void printMemReference(const MachineInstr *MI, unsigned Op,
+ const char *Modifier=NULL);
+ void printLeaMemReference(const MachineInstr *MI, unsigned Op,
+ const char *Modifier=NULL);
+ void printPICJumpTableSetLabel(unsigned uid,
+ const MachineBasicBlock *MBB) const;
+ void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,
+ const MachineBasicBlock *MBB) const {
+ AsmPrinter::printPICJumpTableSetLabel(uid, uid2, MBB);
+ }
+ void printPICJumpTableEntry(const MachineJumpTableInfo *MJTI,
+ const MachineBasicBlock *MBB,
+ unsigned uid) const;
+
+ void printPICLabel(const MachineInstr *MI, unsigned Op);
+ void PrintGlobalVariable(const GlobalVariable* GVar);
+
+ void PrintPICBaseSymbol() const;
+
+ bool runOnMachineFunction(MachineFunction &F);
+
+ void emitFunctionHeader(const MachineFunction &MF);
+
+};
+
+} // end namespace llvm
+
+#endif
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
deleted file mode 100644
index 4b70573..0000000
--- a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
+++ /dev/null
@@ -1,632 +0,0 @@
-//===-- X86IntelAsmPrinter.cpp - Convert X86 LLVM code to Intel assembly --===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains a printer that converts from our internal representation
-// of machine-dependent LLVM code to Intel format assembly language.
-// This printer is the output mechanism used by `llc'.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "asm-printer"
-#include "X86IntelAsmPrinter.h"
-#include "X86InstrInfo.h"
-#include "X86MCAsmInfo.h"
-#include "X86.h"
-#include "llvm/CallingConv.h"
-#include "llvm/Constants.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/Module.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/ADT/StringExtras.h"
-#include "llvm/Assembly/Writer.h"
-#include "llvm/CodeGen/DwarfWriter.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/Target/TargetOptions.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/Mangler.h"
-using namespace llvm;
-
-STATISTIC(EmittedInsts, "Number of machine instrs printed");
-
-static X86MachineFunctionInfo calculateFunctionInfo(const Function *F,
- const TargetData *TD) {
- X86MachineFunctionInfo Info;
- uint64_t Size = 0;
-
- switch (F->getCallingConv()) {
- case CallingConv::X86_StdCall:
- Info.setDecorationStyle(StdCall);
- break;
- case CallingConv::X86_FastCall:
- Info.setDecorationStyle(FastCall);
- break;
- default:
- return Info;
- }
-
- unsigned argNum = 1;
- for (Function::const_arg_iterator AI = F->arg_begin(), AE = F->arg_end();
- AI != AE; ++AI, ++argNum) {
- const Type* Ty = AI->getType();
-
- // 'Dereference' type in case of byval parameter attribute
- if (F->paramHasAttr(argNum, Attribute::ByVal))
- Ty = cast<PointerType>(Ty)->getElementType();
-
- // Size should be aligned to DWORD boundary
- Size += ((TD->getTypeAllocSize(Ty) + 3)/4)*4;
- }
-
- // We're not supporting tooooo huge arguments :)
- Info.setBytesToPopOnReturn((unsigned int)Size);
- return Info;
-}
-
-
-/// decorateName - Query FunctionInfoMap and use this information for various
-/// name decoration.
-void X86IntelAsmPrinter::decorateName(std::string &Name,
- const GlobalValue *GV) {
- const Function *F = dyn_cast<Function>(GV);
- if (!F) return;
-
- // We don't want to decorate non-stdcall or non-fastcall functions right now
- unsigned CC = F->getCallingConv();
- if (CC != CallingConv::X86_StdCall && CC != CallingConv::X86_FastCall)
- return;
-
- FMFInfoMap::const_iterator info_item = FunctionInfoMap.find(F);
-
- const X86MachineFunctionInfo *Info;
- if (info_item == FunctionInfoMap.end()) {
- // Calculate apropriate function info and populate map
- FunctionInfoMap[F] = calculateFunctionInfo(F, TM.getTargetData());
- Info = &FunctionInfoMap[F];
- } else {
- Info = &info_item->second;
- }
-
- const FunctionType *FT = F->getFunctionType();
- switch (Info->getDecorationStyle()) {
- case None:
- break;
- case StdCall:
- // "Pure" variadic functions do not receive @0 suffix.
- if (!FT->isVarArg() || (FT->getNumParams() == 0) ||
- (FT->getNumParams() == 1 && F->hasStructRetAttr()))
- Name += '@' + utostr_32(Info->getBytesToPopOnReturn());
- break;
- case FastCall:
- // "Pure" variadic functions do not receive @0 suffix.
- if (!FT->isVarArg() || (FT->getNumParams() == 0) ||
- (FT->getNumParams() == 1 && F->hasStructRetAttr()))
- Name += '@' + utostr_32(Info->getBytesToPopOnReturn());
-
- if (Name[0] == '_')
- Name[0] = '@';
- else
- Name = '@' + Name;
-
- break;
- default:
- llvm_unreachable("Unsupported DecorationStyle");
- }
-}
-
-/// runOnMachineFunction - This uses the printMachineInstruction()
-/// method to print assembly for each instruction.
-///
-bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
- this->MF = &MF;
- SetupMachineFunction(MF);
- O << "\n\n";
-
- // Print out constants referenced by the function
- EmitConstantPool(MF.getConstantPool());
-
- // Print out labels for the function.
- const Function *F = MF.getFunction();
- unsigned CC = F->getCallingConv();
- unsigned FnAlign = MF.getAlignment();
-
- // Populate function information map. Actually, We don't want to populate
- // non-stdcall or non-fastcall functions' information right now.
- if (CC == CallingConv::X86_StdCall || CC == CallingConv::X86_FastCall)
- FunctionInfoMap[F] = *MF.getInfo<X86MachineFunctionInfo>();
-
- decorateName(CurrentFnName, F);
-
- OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
-
- switch (F->getLinkage()) {
- default: llvm_unreachable("Unsupported linkage type!");
- case Function::PrivateLinkage:
- case Function::LinkerPrivateLinkage:
- case Function::InternalLinkage:
- EmitAlignment(FnAlign);
- break;
- case Function::DLLExportLinkage:
- DLLExportedFns.insert(CurrentFnName);
- //FALLS THROUGH
- case Function::ExternalLinkage:
- O << "\tpublic " << CurrentFnName << "\n";
- EmitAlignment(FnAlign);
- break;
- }
-
- O << CurrentFnName << "\tproc near\n";
-
- // Print out code for the function.
- for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
- I != E; ++I) {
- // Print a label for the basic block if there are any predecessors.
- if (!I->pred_empty()) {
- printBasicBlockLabel(I, true, true);
- O << '\n';
- }
- for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
- II != E; ++II) {
- // Print the assembly for the instruction.
- printMachineInstruction(II);
- }
- }
-
- // Print out jump tables referenced by the function.
- EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
-
- O << CurrentFnName << "\tendp\n";
-
- // We didn't modify anything.
- return false;
-}
-
-void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
- unsigned char value = MI->getOperand(Op).getImm();
- assert(value <= 7 && "Invalid ssecc argument!");
- switch (value) {
- case 0: O << "eq"; break;
- case 1: O << "lt"; break;
- case 2: O << "le"; break;
- case 3: O << "unord"; break;
- case 4: O << "neq"; break;
- case 5: O << "nlt"; break;
- case 6: O << "nle"; break;
- case 7: O << "ord"; break;
- }
-}
-
-void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
- const char *Modifier) {
- switch (MO.getType()) {
- case MachineOperand::MO_Register: {
- if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
- unsigned Reg = MO.getReg();
- if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
- EVT VT = (strcmp(Modifier,"subreg64") == 0) ?
- MVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? MVT::i32 :
- ((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
- Reg = getX86SubSuperRegister(Reg, VT);
- }
- O << TRI->getName(Reg);
- } else
- O << "reg" << MO.getReg();
- return;
- }
- case MachineOperand::MO_Immediate:
- O << MO.getImm();
- return;
- case MachineOperand::MO_JumpTableIndex: {
- bool isMemOp = Modifier && !strcmp(Modifier, "mem");
- if (!isMemOp) O << "OFFSET ";
- O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
- << "_" << MO.getIndex();
- return;
- }
- case MachineOperand::MO_ConstantPoolIndex: {
- bool isMemOp = Modifier && !strcmp(Modifier, "mem");
- if (!isMemOp) O << "OFFSET ";
- O << "[" << MAI->getPrivateGlobalPrefix() << "CPI"
- << getFunctionNumber() << "_" << MO.getIndex();
- printOffset(MO.getOffset());
- O << "]";
- return;
- }
- case MachineOperand::MO_GlobalAddress: {
- bool isMemOp = Modifier && !strcmp(Modifier, "mem");
- GlobalValue *GV = MO.getGlobal();
- std::string Name = Mang->getMangledName(GV);
- decorateName(Name, GV);
-
- if (!isMemOp) O << "OFFSET ";
-
- // Handle dllimport linkage.
- // FIXME: This should be fixed with full support of stdcall & fastcall
- // CC's
- if (MO.getTargetFlags() == X86II::MO_DLLIMPORT)
- O << "__imp_";
-
- O << Name;
- printOffset(MO.getOffset());
- return;
- }
- case MachineOperand::MO_ExternalSymbol: {
- O << MAI->getGlobalPrefix() << MO.getSymbolName();
- return;
- }
- default:
- O << "<unknown operand type>"; return;
- }
-}
-
-void X86IntelAsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo){
- const MachineOperand &MO = MI->getOperand(OpNo);
- switch (MO.getType()) {
- default: llvm_unreachable("Unknown pcrel immediate operand");
- case MachineOperand::MO_Immediate:
- O << MO.getImm();
- return;
- case MachineOperand::MO_MachineBasicBlock:
- printBasicBlockLabel(MO.getMBB(), false, false, false);
- return;
-
- case MachineOperand::MO_GlobalAddress: {
- GlobalValue *GV = MO.getGlobal();
- std::string Name = Mang->getMangledName(GV);
- decorateName(Name, GV);
-
- // Handle dllimport linkage.
- // FIXME: This should be fixed with full support of stdcall & fastcall
- // CC's
- if (MO.getTargetFlags() == X86II::MO_DLLIMPORT)
- O << "__imp_";
- O << Name;
- printOffset(MO.getOffset());
- return;
- }
-
- case MachineOperand::MO_ExternalSymbol:
- O << MAI->getGlobalPrefix() << MO.getSymbolName();
- return;
- }
-}
-
-
-void X86IntelAsmPrinter::printLeaMemReference(const MachineInstr *MI,
- unsigned Op,
- const char *Modifier) {
- const MachineOperand &BaseReg = MI->getOperand(Op);
- int ScaleVal = MI->getOperand(Op+1).getImm();
- const MachineOperand &IndexReg = MI->getOperand(Op+2);
- const MachineOperand &DispSpec = MI->getOperand(Op+3);
-
- O << "[";
- bool NeedPlus = false;
- if (BaseReg.getReg()) {
- printOp(BaseReg, Modifier);
- NeedPlus = true;
- }
-
- if (IndexReg.getReg()) {
- if (NeedPlus) O << " + ";
- if (ScaleVal != 1)
- O << ScaleVal << "*";
- printOp(IndexReg, Modifier);
- NeedPlus = true;
- }
-
- if (DispSpec.isGlobal() || DispSpec.isCPI() ||
- DispSpec.isJTI()) {
- if (NeedPlus)
- O << " + ";
- printOp(DispSpec, "mem");
- } else {
- int DispVal = DispSpec.getImm();
- if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
- if (NeedPlus) {
- if (DispVal > 0)
- O << " + ";
- else {
- O << " - ";
- DispVal = -DispVal;
- }
- }
- O << DispVal;
- }
- }
- O << "]";
-}
-
-void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
- const char *Modifier) {
- assert(isMem(MI, Op) && "Invalid memory reference!");
- MachineOperand Segment = MI->getOperand(Op+4);
- if (Segment.getReg()) {
- printOperand(MI, Op+4, Modifier);
- O << ':';
- }
- printLeaMemReference(MI, Op, Modifier);
-}
-
-void X86IntelAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
- const MachineBasicBlock *MBB) const {
- if (!MAI->getSetDirective())
- return;
-
- O << MAI->getSetDirective() << ' ' << MAI->getPrivateGlobalPrefix()
- << getFunctionNumber() << '_' << uid << "_set_" << MBB->getNumber() << ',';
- printBasicBlockLabel(MBB, false, false, false);
- O << '-' << "\"L" << getFunctionNumber() << "$pb\"'\n";
-}
-
-void X86IntelAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
- O << "L" << getFunctionNumber() << "$pb\n";
- O << "L" << getFunctionNumber() << "$pb:";
-}
-
-bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
- const char Mode) {
- unsigned Reg = MO.getReg();
- switch (Mode) {
- default: return true; // Unknown mode.
- case 'b': // Print QImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i8);
- break;
- case 'h': // Print QImode high register
- Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
- break;
- case 'w': // Print HImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i16);
- break;
- case 'k': // Print SImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i32);
- break;
- }
-
- O << TRI->getName(Reg);
- return false;
-}
-
-/// PrintAsmOperand - Print out an operand for an inline asm expression.
-///
-bool X86IntelAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant,
- const char *ExtraCode) {
- // Does this asm operand have a single letter operand modifier?
- if (ExtraCode && ExtraCode[0]) {
- if (ExtraCode[1] != 0) return true; // Unknown modifier.
-
- switch (ExtraCode[0]) {
- default: return true; // Unknown modifier.
- case 'b': // Print QImode register
- case 'h': // Print QImode high register
- case 'w': // Print HImode register
- case 'k': // Print SImode register
- return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]);
- }
- }
-
- printOperand(MI, OpNo);
- return false;
-}
-
-bool X86IntelAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
- unsigned OpNo,
- unsigned AsmVariant,
- const char *ExtraCode) {
- if (ExtraCode && ExtraCode[0])
- return true; // Unknown modifier.
- printMemReference(MI, OpNo);
- return false;
-}
-
-/// printMachineInstruction -- Print out a single X86 LLVM instruction
-/// MI in Intel syntax to the current output stream.
-///
-void X86IntelAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
- ++EmittedInsts;
-
- // Call the autogenerated instruction printer routines.
- printInstruction(MI);
-}
-
-bool X86IntelAsmPrinter::doInitialization(Module &M) {
- bool Result = AsmPrinter::doInitialization(M);
-
- Mang->markCharUnacceptable('.');
-
- O << "\t.686\n\t.MMX\n\t.XMM\n\t.model flat\n\n";
-
- // Emit declarations for external functions.
- for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
- if (I->isDeclaration()) {
- std::string Name = Mang->getMangledName(I);
- decorateName(Name, I);
-
- O << "\tEXTERN " ;
- if (I->hasDLLImportLinkage()) {
- O << "__imp_";
- }
- O << Name << ":near\n";
- }
-
- // Emit declarations for external globals. Note that VC++ always declares
- // external globals to have type byte, and if that's good enough for VC++...
- for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();
- I != E; ++I) {
- if (I->isDeclaration()) {
- std::string Name = Mang->getMangledName(I);
-
- O << "\tEXTERN " ;
- if (I->hasDLLImportLinkage()) {
- O << "__imp_";
- }
- O << Name << ":byte\n";
- }
- }
-
- return Result;
-}
-
-void X86IntelAsmPrinter::PrintGlobalVariable(const GlobalVariable *GV) {
- // Check to see if this is a special global used by LLVM, if so, emit it.
- if (GV->isDeclaration() ||
- EmitSpecialLLVMGlobal(GV))
- return;
-
- const TargetData *TD = TM.getTargetData();
-
- std::string name = Mang->getMangledName(GV);
- Constant *C = GV->getInitializer();
- unsigned Align = TD->getPreferredAlignmentLog(GV);
- bool bCustomSegment = false;
-
- switch (GV->getLinkage()) {
- case GlobalValue::CommonLinkage:
- case GlobalValue::LinkOnceAnyLinkage:
- case GlobalValue::LinkOnceODRLinkage:
- case GlobalValue::WeakAnyLinkage:
- case GlobalValue::WeakODRLinkage:
- // FIXME: make a MCSection.
- O << name << "?\tSEGEMNT PARA common 'COMMON'\n";
- bCustomSegment = true;
- // FIXME: the default alignment is 16 bytes, but 1, 2, 4, and 256
- // are also available.
- break;
- case GlobalValue::AppendingLinkage:
- // FIXME: make a MCSection.
- O << name << "?\tSEGMENT PARA public 'DATA'\n";
- bCustomSegment = true;
- // FIXME: the default alignment is 16 bytes, but 1, 2, 4, and 256
- // are also available.
- break;
- case GlobalValue::DLLExportLinkage:
- DLLExportedGVs.insert(name);
- // FALL THROUGH
- case GlobalValue::ExternalLinkage:
- O << "\tpublic " << name << "\n";
- // FALL THROUGH
- case GlobalValue::InternalLinkage:
- OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
- break;
- default:
- llvm_unreachable("Unknown linkage type!");
- }
-
- if (!bCustomSegment)
- EmitAlignment(Align, GV);
-
- O << name << ":";
- if (VerboseAsm)
- O.PadToColumn(MAI->getCommentColumn());
- O << MAI->getCommentString()
- << " " << GV->getName();
- O << '\n';
-
- EmitGlobalConstant(C);
-
- if (bCustomSegment)
- O << name << "?\tends\n";
-}
-
-bool X86IntelAsmPrinter::doFinalization(Module &M) {
- // Output linker support code for dllexported globals
- if (!DLLExportedGVs.empty() || !DLLExportedFns.empty()) {
- O << "; WARNING: The following code is valid only with MASM v8.x"
- << "and (possible) higher\n"
- << "; This version of MASM is usually shipped with Microsoft "
- << "Visual Studio 2005\n"
- << "; or (possible) further versions. Unfortunately, there is no "
- << "way to support\n"
- << "; dllexported symbols in the earlier versions of MASM in fully "
- << "automatic way\n\n";
- O << "_drectve\t segment info alias('.drectve')\n";
-
- for (StringSet<>::iterator i = DLLExportedGVs.begin(),
- e = DLLExportedGVs.end();
- i != e; ++i)
- O << "\t db ' /EXPORT:" << i->getKeyData() << ",data'\n";
-
- for (StringSet<>::iterator i = DLLExportedFns.begin(),
- e = DLLExportedFns.end();
- i != e; ++i)
- O << "\t db ' /EXPORT:" << i->getKeyData() << "'\n";
-
- O << "_drectve\t ends\n";
- }
-
- // Bypass X86SharedAsmPrinter::doFinalization().
- bool Result = AsmPrinter::doFinalization(M);
- O << "\tend\n";
- return Result;
-}
-
-void X86IntelAsmPrinter::EmitString(const ConstantArray *CVA) const {
- unsigned NumElts = CVA->getNumOperands();
- if (NumElts) {
- // ML does not have escape sequences except '' for '. It also has a maximum
- // string length of 255.
- unsigned len = 0;
- bool inString = false;
- for (unsigned i = 0; i < NumElts; i++) {
- int n = cast<ConstantInt>(CVA->getOperand(i))->getZExtValue() & 255;
- if (len == 0)
- O << "\tdb ";
-
- if (n >= 32 && n <= 127) {
- if (!inString) {
- if (len > 0) {
- O << ",'";
- len += 2;
- } else {
- O << "'";
- len++;
- }
- inString = true;
- }
- if (n == '\'') {
- O << "'";
- len++;
- }
- O << char(n);
- } else {
- if (inString) {
- O << "'";
- len++;
- inString = false;
- }
- if (len > 0) {
- O << ",";
- len++;
- }
- O << n;
- len += 1 + (n > 9) + (n > 99);
- }
-
- if (len > 60) {
- if (inString) {
- O << "'";
- inString = false;
- }
- O << "\n";
- len = 0;
- }
- }
-
- if (len > 0) {
- if (inString)
- O << "'";
- O << "\n";
- }
- }
-}
-
-// Include the auto-generated portion of the assembly writer.
-#include "X86GenAsmWriter1.inc"
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
deleted file mode 100644
index 379e4e7..0000000
--- a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
+++ /dev/null
@@ -1,164 +0,0 @@
-//===-- X86IntelAsmPrinter.h - Convert X86 LLVM code to Intel assembly ----===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Intel assembly code printer class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef X86INTELASMPRINTER_H
-#define X86INTELASMPRINTER_H
-
-#include "../X86.h"
-#include "../X86MachineFunctionInfo.h"
-#include "../X86TargetMachine.h"
-#include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/ADT/StringSet.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/Support/FormattedStream.h"
-
-namespace llvm {
-
-struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
- explicit X86IntelAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
- const MCAsmInfo *T, bool V)
- : AsmPrinter(O, TM, T, V) {}
-
- virtual const char *getPassName() const {
- return "X86 Intel-Style Assembly Printer";
- }
-
- /// printInstruction - This method is automatically generated by tablegen
- /// from the instruction set description. This method returns true if the
- /// machine instruction was sufficiently described to print it, otherwise it
- /// returns false.
- void printInstruction(const MachineInstr *MI);
-
- // This method is used by the tablegen'erated instruction printer.
- void printOperand(const MachineInstr *MI, unsigned OpNo,
- const char *Modifier = 0) {
- const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.isReg()) {
- assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- "Not physreg??");
- O << TM.getRegisterInfo()->get(MO.getReg()).Name; // Capitalized names
- } else {
- printOp(MO, Modifier);
- }
- }
-
- void print_pcrel_imm(const MachineInstr *MI, unsigned OpNo);
-
-
- void printi8mem(const MachineInstr *MI, unsigned OpNo) {
- O << "BYTE PTR ";
- printMemReference(MI, OpNo);
- }
- void printi16mem(const MachineInstr *MI, unsigned OpNo) {
- O << "WORD PTR ";
- printMemReference(MI, OpNo);
- }
- void printi32mem(const MachineInstr *MI, unsigned OpNo) {
- O << "DWORD PTR ";
- printMemReference(MI, OpNo);
- }
- void printi64mem(const MachineInstr *MI, unsigned OpNo) {
- O << "QWORD PTR ";
- printMemReference(MI, OpNo);
- }
- void printi128mem(const MachineInstr *MI, unsigned OpNo) {
- O << "XMMWORD PTR ";
- printMemReference(MI, OpNo);
- }
- void printi256mem(const MachineInstr *MI, unsigned OpNo) {
- O << "YMMWORD PTR ";
- printMemReference(MI, OpNo);
- }
- void printf32mem(const MachineInstr *MI, unsigned OpNo) {
- O << "DWORD PTR ";
- printMemReference(MI, OpNo);
- }
- void printf64mem(const MachineInstr *MI, unsigned OpNo) {
- O << "QWORD PTR ";
- printMemReference(MI, OpNo);
- }
- void printf80mem(const MachineInstr *MI, unsigned OpNo) {
- O << "XWORD PTR ";
- printMemReference(MI, OpNo);
- }
- void printf128mem(const MachineInstr *MI, unsigned OpNo) {
- O << "XMMWORD PTR ";
- printMemReference(MI, OpNo);
- }
- void printf256mem(const MachineInstr *MI, unsigned OpNo) {
- O << "YMMWORD PTR ";
- printMemReference(MI, OpNo);
- }
- void printlea32mem(const MachineInstr *MI, unsigned OpNo) {
- O << "DWORD PTR ";
- printLeaMemReference(MI, OpNo);
- }
- void printlea64mem(const MachineInstr *MI, unsigned OpNo) {
- O << "QWORD PTR ";
- printLeaMemReference(MI, OpNo);
- }
- void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
- O << "QWORD PTR ";
- printLeaMemReference(MI, OpNo, "subreg64");
- }
-
- bool printAsmMRegister(const MachineOperand &MO, const char Mode);
- bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant, const char *ExtraCode);
- bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant, const char *ExtraCode);
- void printMachineInstruction(const MachineInstr *MI);
- void printOp(const MachineOperand &MO, const char *Modifier = 0);
- void printSSECC(const MachineInstr *MI, unsigned Op);
- void printMemReference(const MachineInstr *MI, unsigned Op,
- const char *Modifier=NULL);
- void printLeaMemReference(const MachineInstr *MI, unsigned Op,
- const char *Modifier=NULL);
- void printPICJumpTableSetLabel(unsigned uid,
- const MachineBasicBlock *MBB) const;
- void printPICJumpTableSetLabel(unsigned uid, unsigned uid2,
- const MachineBasicBlock *MBB) const {
- AsmPrinter::printPICJumpTableSetLabel(uid, uid2, MBB);
- }
- void printPICLabel(const MachineInstr *MI, unsigned Op);
- bool runOnMachineFunction(MachineFunction &F);
- bool doInitialization(Module &M);
- bool doFinalization(Module &M);
-
- void PrintGlobalVariable(const GlobalVariable *GV);
-
- // We have to propagate some information about MachineFunction to
- // AsmPrinter. It's ok, when we're printing the function, since we have
- // access to MachineFunction and can get the appropriate MachineFunctionInfo.
- // Unfortunately, this is not possible when we're printing reference to
- // Function (e.g. calling it and so on). Even more, there is no way to get the
- // corresponding MachineFunctions: it can even be not created at all. That's
- // why we should use additional structure, when we're collecting all necessary
- // information.
- //
- // This structure is using e.g. for name decoration for stdcall & fastcall'ed
- // function, since we have to use arguments' size for decoration.
- typedef std::map<const Function*, X86MachineFunctionInfo> FMFInfoMap;
- FMFInfoMap FunctionInfoMap;
-
- void decorateName(std::string& Name, const GlobalValue* GV);
-
- virtual void EmitString(const ConstantArray *CVA) const;
-
- // Necessary for dllexport support
- StringSet<> DLLExportedFns, DLLExportedGVs;
-};
-
-} // end namespace llvm
-
-#endif
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp
new file mode 100644
index 0000000..fde5902
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp
@@ -0,0 +1,131 @@
+//===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file includes code for rendering MCInst instances as AT&T-style
+// assembly.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "asm-printer"
+#include "X86IntelInstPrinter.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/FormattedStream.h"
+#include "X86GenInstrNames.inc"
+using namespace llvm;
+
+// Include the auto-generated portion of the assembly writer.
+#define MachineInstr MCInst
+#define NO_ASM_WRITER_BOILERPLATE
+#include "X86GenAsmWriter1.inc"
+#undef MachineInstr
+
+void X86IntelInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
+
+void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
+ switch (MI->getOperand(Op).getImm()) {
+ default: llvm_unreachable("Invalid ssecc argument!");
+ case 0: O << "eq"; break;
+ case 1: O << "lt"; break;
+ case 2: O << "le"; break;
+ case 3: O << "unord"; break;
+ case 4: O << "neq"; break;
+ case 5: O << "nlt"; break;
+ case 6: O << "nle"; break;
+ case 7: O << "ord"; break;
+ }
+}
+
+/// print_pcrel_imm - This is used to print an immediate value that ends up
+/// being encoded as a pc-relative value.
+void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) {
+ const MCOperand &Op = MI->getOperand(OpNo);
+ if (Op.isImm())
+ O << Op.getImm();
+ else {
+ assert(Op.isExpr() && "unknown pcrel immediate operand");
+ Op.getExpr()->print(O, &MAI);
+ }
+}
+
+static void PrintRegName(raw_ostream &O, StringRef RegName) {
+ for (unsigned i = 0, e = RegName.size(); i != e; ++i)
+ O << (char)toupper(RegName[i]);
+}
+
+void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
+ const char *Modifier) {
+ assert(Modifier == 0 && "Modifiers should not be used");
+
+ const MCOperand &Op = MI->getOperand(OpNo);
+ if (Op.isReg()) {
+ PrintRegName(O, getRegisterName(Op.getReg()));
+ } else if (Op.isImm()) {
+ O << Op.getImm();
+ } else {
+ assert(Op.isExpr() && "unknown operand kind in printOperand");
+ Op.getExpr()->print(O, &MAI);
+ }
+}
+
+void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
+ const MCOperand &BaseReg = MI->getOperand(Op);
+ unsigned ScaleVal = MI->getOperand(Op+1).getImm();
+ const MCOperand &IndexReg = MI->getOperand(Op+2);
+ const MCOperand &DispSpec = MI->getOperand(Op+3);
+
+ O << '[';
+
+ bool NeedPlus = false;
+ if (BaseReg.getReg()) {
+ printOperand(MI, Op);
+ NeedPlus = true;
+ }
+
+ if (IndexReg.getReg()) {
+ if (NeedPlus) O << " + ";
+ if (ScaleVal != 1)
+ O << ScaleVal << '*';
+ printOperand(MI, Op+2);
+ NeedPlus = true;
+ }
+
+
+ if (!DispSpec.isImm()) {
+ if (NeedPlus) O << " + ";
+ assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
+ DispSpec.getExpr()->print(O, &MAI);
+ } else {
+ int64_t DispVal = DispSpec.getImm();
+ if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
+ if (NeedPlus) {
+ if (DispVal > 0)
+ O << " + ";
+ else {
+ O << " - ";
+ DispVal = -DispVal;
+ }
+ }
+ O << DispVal;
+ }
+ }
+
+ O << ']';
+}
+
+void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op) {
+ // If this has a segment register, print it.
+ if (MI->getOperand(Op+4).getReg()) {
+ printOperand(MI, Op+4);
+ O << ':';
+ }
+ printLeaMemReference(MI, Op);
+}
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h
new file mode 100644
index 0000000..1976177
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h
@@ -0,0 +1,99 @@
+//===-- X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -----===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an X86 MCInst to intel style .s file syntax.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef X86_INTEL_INST_PRINTER_H
+#define X86_INTEL_INST_PRINTER_H
+
+#include "llvm/MC/MCInstPrinter.h"
+#include "llvm/Support/raw_ostream.h"
+
+namespace llvm {
+ class MCOperand;
+
+class X86IntelInstPrinter : public MCInstPrinter {
+public:
+ X86IntelInstPrinter(raw_ostream &O, const MCAsmInfo &MAI)
+ : MCInstPrinter(O, MAI) {}
+
+ virtual void printInst(const MCInst *MI);
+
+ // Autogenerated by tblgen.
+ void printInstruction(const MCInst *MI);
+ static const char *getRegisterName(unsigned RegNo);
+
+
+ void printOperand(const MCInst *MI, unsigned OpNo,
+ const char *Modifier = 0);
+ void printMemReference(const MCInst *MI, unsigned Op);
+ void printLeaMemReference(const MCInst *MI, unsigned Op);
+ void printSSECC(const MCInst *MI, unsigned Op);
+ void print_pcrel_imm(const MCInst *MI, unsigned OpNo);
+
+ void printopaquemem(const MCInst *MI, unsigned OpNo) {
+ O << "OPAQUE PTR ";
+ printMemReference(MI, OpNo);
+ }
+
+ void printi8mem(const MCInst *MI, unsigned OpNo) {
+ O << "BYTE PTR ";
+ printMemReference(MI, OpNo);
+ }
+ void printi16mem(const MCInst *MI, unsigned OpNo) {
+ O << "WORD PTR ";
+ printMemReference(MI, OpNo);
+ }
+ void printi32mem(const MCInst *MI, unsigned OpNo) {
+ O << "DWORD PTR ";
+ printMemReference(MI, OpNo);
+ }
+ void printi64mem(const MCInst *MI, unsigned OpNo) {
+ O << "QWORD PTR ";
+ printMemReference(MI, OpNo);
+ }
+ void printi128mem(const MCInst *MI, unsigned OpNo) {
+ O << "XMMWORD PTR ";
+ printMemReference(MI, OpNo);
+ }
+ void printf32mem(const MCInst *MI, unsigned OpNo) {
+ O << "DWORD PTR ";
+ printMemReference(MI, OpNo);
+ }
+ void printf64mem(const MCInst *MI, unsigned OpNo) {
+ O << "QWORD PTR ";
+ printMemReference(MI, OpNo);
+ }
+ void printf80mem(const MCInst *MI, unsigned OpNo) {
+ O << "XWORD PTR ";
+ printMemReference(MI, OpNo);
+ }
+ void printf128mem(const MCInst *MI, unsigned OpNo) {
+ O << "XMMWORD PTR ";
+ printMemReference(MI, OpNo);
+ }
+ void printlea32mem(const MCInst *MI, unsigned OpNo) {
+ O << "DWORD PTR ";
+ printLeaMemReference(MI, OpNo);
+ }
+ void printlea64mem(const MCInst *MI, unsigned OpNo) {
+ O << "QWORD PTR ";
+ printLeaMemReference(MI, OpNo);
+ }
+ void printlea64_32mem(const MCInst *MI, unsigned OpNo) {
+ O << "QWORD PTR ";
+ printLeaMemReference(MI, OpNo);
+ }
+};
+
+}
+
+#endif
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
new file mode 100644
index 0000000..5ccddf5
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
@@ -0,0 +1,485 @@
+//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains code to lower X86 MachineInstrs to their corresponding
+// MCInst records.
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86MCInstLower.h"
+#include "X86AsmPrinter.h"
+#include "X86MCAsmInfo.h"
+#include "X86COFFMachineModuleInfo.h"
+#include "llvm/CodeGen/MachineModuleInfoImpls.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/Mangler.h"
+#include "llvm/ADT/SmallString.h"
+using namespace llvm;
+
+
+const X86Subtarget &X86MCInstLower::getSubtarget() const {
+ return AsmPrinter.getSubtarget();
+}
+
+MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
+ assert(getSubtarget().isTargetDarwin() &&"Can only get MachO info on darwin");
+ return AsmPrinter.MMI->getObjFileInfo<MachineModuleInfoMachO>();
+}
+
+
+MCSymbol *X86MCInstLower::GetPICBaseSymbol() const {
+ SmallString<60> Name;
+ raw_svector_ostream(Name) << AsmPrinter.MAI->getPrivateGlobalPrefix()
+ << AsmPrinter.getFunctionNumber() << "$pb";
+ return Ctx.GetOrCreateSymbol(Name.str());
+}
+
+
+/// LowerGlobalAddressOperand - Lower an MO_GlobalAddress operand to an
+/// MCOperand.
+MCSymbol *X86MCInstLower::
+GetGlobalAddressSymbol(const MachineOperand &MO) const {
+ const GlobalValue *GV = MO.getGlobal();
+
+ bool isImplicitlyPrivate = false;
+ if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
+ MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
+ MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
+ MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
+ isImplicitlyPrivate = true;
+
+ SmallString<128> Name;
+ Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
+
+ if (getSubtarget().isTargetCygMing()) {
+ X86COFFMachineModuleInfo &COFFMMI =
+ AsmPrinter.MMI->getObjFileInfo<X86COFFMachineModuleInfo>();
+ COFFMMI.DecorateCygMingName(Name, GV, *AsmPrinter.TM.getTargetData());
+ }
+
+ switch (MO.getTargetFlags()) {
+ default: llvm_unreachable("Unknown target flag on GV operand");
+ case X86II::MO_NO_FLAG: // No flag.
+ case X86II::MO_PIC_BASE_OFFSET: // Doesn't modify symbol name.
+ break;
+ case X86II::MO_DLLIMPORT: {
+ // Handle dllimport linkage.
+ const char *Prefix = "__imp_";
+ Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
+ break;
+ }
+ case X86II::MO_DARWIN_NONLAZY:
+ case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
+ Name += "$non_lazy_ptr";
+ MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
+
+ const MCSymbol *&StubSym = getMachOMMI().getGVStubEntry(Sym);
+ if (StubSym == 0) {
+ Name.clear();
+ Mang->getNameWithPrefix(Name, GV, false);
+ StubSym = Ctx.GetOrCreateSymbol(Name.str());
+ }
+ return Sym;
+ }
+ case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
+ Name += "$non_lazy_ptr";
+ MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
+ const MCSymbol *&StubSym = getMachOMMI().getHiddenGVStubEntry(Sym);
+ if (StubSym == 0) {
+ Name.clear();
+ Mang->getNameWithPrefix(Name, GV, false);
+ StubSym = Ctx.GetOrCreateSymbol(Name.str());
+ }
+ return Sym;
+ }
+ case X86II::MO_DARWIN_STUB: {
+ Name += "$stub";
+ MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
+ const MCSymbol *&StubSym = getMachOMMI().getFnStubEntry(Sym);
+ if (StubSym == 0) {
+ Name.clear();
+ Mang->getNameWithPrefix(Name, GV, false);
+ StubSym = Ctx.GetOrCreateSymbol(Name.str());
+ }
+ return Sym;
+ }
+ // FIXME: These probably should be a modifier on the symbol or something??
+ case X86II::MO_TLSGD: Name += "@TLSGD"; break;
+ case X86II::MO_GOTTPOFF: Name += "@GOTTPOFF"; break;
+ case X86II::MO_INDNTPOFF: Name += "@INDNTPOFF"; break;
+ case X86II::MO_TPOFF: Name += "@TPOFF"; break;
+ case X86II::MO_NTPOFF: Name += "@NTPOFF"; break;
+ case X86II::MO_GOTPCREL: Name += "@GOTPCREL"; break;
+ case X86II::MO_GOT: Name += "@GOT"; break;
+ case X86II::MO_GOTOFF: Name += "@GOTOFF"; break;
+ case X86II::MO_PLT: Name += "@PLT"; break;
+ }
+
+ return Ctx.GetOrCreateSymbol(Name.str());
+}
+
+MCSymbol *X86MCInstLower::
+GetExternalSymbolSymbol(const MachineOperand &MO) const {
+ SmallString<128> Name;
+ Name += AsmPrinter.MAI->getGlobalPrefix();
+ Name += MO.getSymbolName();
+
+ switch (MO.getTargetFlags()) {
+ default: llvm_unreachable("Unknown target flag on GV operand");
+ case X86II::MO_NO_FLAG: // No flag.
+ case X86II::MO_GOT_ABSOLUTE_ADDRESS: // Doesn't modify symbol name.
+ case X86II::MO_PIC_BASE_OFFSET: // Doesn't modify symbol name.
+ break;
+ case X86II::MO_DLLIMPORT: {
+ // Handle dllimport linkage.
+ const char *Prefix = "__imp_";
+ Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
+ break;
+ }
+ case X86II::MO_DARWIN_STUB: {
+ Name += "$stub";
+ MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
+ const MCSymbol *&StubSym = getMachOMMI().getFnStubEntry(Sym);
+
+ if (StubSym == 0) {
+ Name.erase(Name.end()-5, Name.end());
+ StubSym = Ctx.GetOrCreateSymbol(Name.str());
+ }
+ return Sym;
+ }
+ // FIXME: These probably should be a modifier on the symbol or something??
+ case X86II::MO_TLSGD: Name += "@TLSGD"; break;
+ case X86II::MO_GOTTPOFF: Name += "@GOTTPOFF"; break;
+ case X86II::MO_INDNTPOFF: Name += "@INDNTPOFF"; break;
+ case X86II::MO_TPOFF: Name += "@TPOFF"; break;
+ case X86II::MO_NTPOFF: Name += "@NTPOFF"; break;
+ case X86II::MO_GOTPCREL: Name += "@GOTPCREL"; break;
+ case X86II::MO_GOT: Name += "@GOT"; break;
+ case X86II::MO_GOTOFF: Name += "@GOTOFF"; break;
+ case X86II::MO_PLT: Name += "@PLT"; break;
+ }
+
+ return Ctx.GetOrCreateSymbol(Name.str());
+}
+
+MCSymbol *X86MCInstLower::GetJumpTableSymbol(const MachineOperand &MO) const {
+ SmallString<256> Name;
+ raw_svector_ostream(Name) << AsmPrinter.MAI->getPrivateGlobalPrefix() << "JTI"
+ << AsmPrinter.getFunctionNumber() << '_' << MO.getIndex();
+
+ switch (MO.getTargetFlags()) {
+ default:
+ llvm_unreachable("Unknown target flag on GV operand");
+ case X86II::MO_NO_FLAG: // No flag.
+ case X86II::MO_PIC_BASE_OFFSET:
+ case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
+ case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
+ break;
+ // FIXME: These probably should be a modifier on the symbol or something??
+ case X86II::MO_TLSGD: Name += "@TLSGD"; break;
+ case X86II::MO_GOTTPOFF: Name += "@GOTTPOFF"; break;
+ case X86II::MO_INDNTPOFF: Name += "@INDNTPOFF"; break;
+ case X86II::MO_TPOFF: Name += "@TPOFF"; break;
+ case X86II::MO_NTPOFF: Name += "@NTPOFF"; break;
+ case X86II::MO_GOTPCREL: Name += "@GOTPCREL"; break;
+ case X86II::MO_GOT: Name += "@GOT"; break;
+ case X86II::MO_GOTOFF: Name += "@GOTOFF"; break;
+ case X86II::MO_PLT: Name += "@PLT"; break;
+ }
+
+ // Create a symbol for the name.
+ return Ctx.GetOrCreateSymbol(Name.str());
+}
+
+
+MCSymbol *X86MCInstLower::
+GetConstantPoolIndexSymbol(const MachineOperand &MO) const {
+ SmallString<256> Name;
+ raw_svector_ostream(Name) << AsmPrinter.MAI->getPrivateGlobalPrefix() << "CPI"
+ << AsmPrinter.getFunctionNumber() << '_' << MO.getIndex();
+
+ switch (MO.getTargetFlags()) {
+ default:
+ llvm_unreachable("Unknown target flag on GV operand");
+ case X86II::MO_NO_FLAG: // No flag.
+ case X86II::MO_PIC_BASE_OFFSET:
+ case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
+ case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
+ break;
+ // FIXME: These probably should be a modifier on the symbol or something??
+ case X86II::MO_TLSGD: Name += "@TLSGD"; break;
+ case X86II::MO_GOTTPOFF: Name += "@GOTTPOFF"; break;
+ case X86II::MO_INDNTPOFF: Name += "@INDNTPOFF"; break;
+ case X86II::MO_TPOFF: Name += "@TPOFF"; break;
+ case X86II::MO_NTPOFF: Name += "@NTPOFF"; break;
+ case X86II::MO_GOTPCREL: Name += "@GOTPCREL"; break;
+ case X86II::MO_GOT: Name += "@GOT"; break;
+ case X86II::MO_GOTOFF: Name += "@GOTOFF"; break;
+ case X86II::MO_PLT: Name += "@PLT"; break;
+ }
+
+ // Create a symbol for the name.
+ return Ctx.GetOrCreateSymbol(Name.str());
+}
+
+MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
+ MCSymbol *Sym) const {
+ // FIXME: We would like an efficient form for this, so we don't have to do a
+ // lot of extra uniquing.
+ const MCExpr *Expr = MCSymbolRefExpr::Create(Sym, Ctx);
+
+ switch (MO.getTargetFlags()) {
+ default: llvm_unreachable("Unknown target flag on GV operand");
+ case X86II::MO_NO_FLAG: // No flag.
+
+ // These affect the name of the symbol, not any suffix.
+ case X86II::MO_DARWIN_NONLAZY:
+ case X86II::MO_DLLIMPORT:
+ case X86II::MO_DARWIN_STUB:
+ case X86II::MO_TLSGD:
+ case X86II::MO_GOTTPOFF:
+ case X86II::MO_INDNTPOFF:
+ case X86II::MO_TPOFF:
+ case X86II::MO_NTPOFF:
+ case X86II::MO_GOTPCREL:
+ case X86II::MO_GOT:
+ case X86II::MO_GOTOFF:
+ case X86II::MO_PLT:
+ break;
+ case X86II::MO_PIC_BASE_OFFSET:
+ case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
+ case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
+ // Subtract the pic base.
+ Expr = MCBinaryExpr::CreateSub(Expr,
+ MCSymbolRefExpr::Create(GetPICBaseSymbol(), Ctx),
+ Ctx);
+ break;
+ }
+
+ if (!MO.isJTI() && MO.getOffset())
+ Expr = MCBinaryExpr::CreateAdd(Expr,
+ MCConstantExpr::Create(MO.getOffset(), Ctx),
+ Ctx);
+ return MCOperand::CreateExpr(Expr);
+}
+
+
+
+static void lower_subreg32(MCInst *MI, unsigned OpNo) {
+ // Convert registers in the addr mode according to subreg32.
+ unsigned Reg = MI->getOperand(OpNo).getReg();
+ if (Reg != 0)
+ MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
+}
+
+static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
+ // Convert registers in the addr mode according to subreg64.
+ for (unsigned i = 0; i != 4; ++i) {
+ if (!MI->getOperand(OpNo+i).isReg()) continue;
+
+ unsigned Reg = MI->getOperand(OpNo+i).getReg();
+ if (Reg == 0) continue;
+
+ MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
+ }
+}
+
+
+
+void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
+ OutMI.setOpcode(MI->getOpcode());
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+
+ MCOperand MCOp;
+ switch (MO.getType()) {
+ default:
+ MI->dump();
+ llvm_unreachable("unknown operand type");
+ case MachineOperand::MO_Register:
+ MCOp = MCOperand::CreateReg(MO.getReg());
+ break;
+ case MachineOperand::MO_Immediate:
+ MCOp = MCOperand::CreateImm(MO.getImm());
+ break;
+ case MachineOperand::MO_MachineBasicBlock:
+ MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+ AsmPrinter.GetMBBSymbol(MO.getMBB()->getNumber()), Ctx));
+ break;
+ case MachineOperand::MO_GlobalAddress:
+ MCOp = LowerSymbolOperand(MO, GetGlobalAddressSymbol(MO));
+ break;
+ case MachineOperand::MO_ExternalSymbol:
+ MCOp = LowerSymbolOperand(MO, GetExternalSymbolSymbol(MO));
+ break;
+ case MachineOperand::MO_JumpTableIndex:
+ MCOp = LowerSymbolOperand(MO, GetJumpTableSymbol(MO));
+ break;
+ case MachineOperand::MO_ConstantPoolIndex:
+ MCOp = LowerSymbolOperand(MO, GetConstantPoolIndexSymbol(MO));
+ break;
+ }
+
+ OutMI.addOperand(MCOp);
+ }
+
+ // Handle a few special cases to eliminate operand modifiers.
+ switch (OutMI.getOpcode()) {
+ case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
+ lower_lea64_32mem(&OutMI, 1);
+ break;
+ case X86::MOV16r0:
+ OutMI.setOpcode(X86::MOV32r0);
+ lower_subreg32(&OutMI, 0);
+ break;
+ case X86::MOVZX16rr8:
+ OutMI.setOpcode(X86::MOVZX32rr8);
+ lower_subreg32(&OutMI, 0);
+ break;
+ case X86::MOVZX16rm8:
+ OutMI.setOpcode(X86::MOVZX32rm8);
+ lower_subreg32(&OutMI, 0);
+ break;
+ case X86::MOVSX16rr8:
+ OutMI.setOpcode(X86::MOVSX32rr8);
+ lower_subreg32(&OutMI, 0);
+ break;
+ case X86::MOVSX16rm8:
+ OutMI.setOpcode(X86::MOVSX32rm8);
+ lower_subreg32(&OutMI, 0);
+ break;
+ case X86::MOVZX64rr32:
+ OutMI.setOpcode(X86::MOV32rr);
+ lower_subreg32(&OutMI, 0);
+ break;
+ case X86::MOVZX64rm32:
+ OutMI.setOpcode(X86::MOV32rm);
+ lower_subreg32(&OutMI, 0);
+ break;
+ case X86::MOV64ri64i32:
+ OutMI.setOpcode(X86::MOV32ri);
+ lower_subreg32(&OutMI, 0);
+ break;
+ case X86::MOVZX64rr8:
+ OutMI.setOpcode(X86::MOVZX32rr8);
+ lower_subreg32(&OutMI, 0);
+ break;
+ case X86::MOVZX64rm8:
+ OutMI.setOpcode(X86::MOVZX32rm8);
+ lower_subreg32(&OutMI, 0);
+ break;
+ case X86::MOVZX64rr16:
+ OutMI.setOpcode(X86::MOVZX32rr16);
+ lower_subreg32(&OutMI, 0);
+ break;
+ case X86::MOVZX64rm16:
+ OutMI.setOpcode(X86::MOVZX32rm16);
+ lower_subreg32(&OutMI, 0);
+ break;
+ }
+}
+
+
+
+void X86AsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
+ X86MCInstLower MCInstLowering(OutContext, Mang, *this);
+ switch (MI->getOpcode()) {
+ case TargetInstrInfo::DBG_LABEL:
+ case TargetInstrInfo::EH_LABEL:
+ case TargetInstrInfo::GC_LABEL:
+ printLabel(MI);
+ return;
+ case TargetInstrInfo::INLINEASM:
+ O << '\t';
+ printInlineAsm(MI);
+ return;
+ case TargetInstrInfo::IMPLICIT_DEF:
+ printImplicitDef(MI);
+ return;
+ case TargetInstrInfo::KILL:
+ return;
+ case X86::MOVPC32r: {
+ MCInst TmpInst;
+ // This is a pseudo op for a two instruction sequence with a label, which
+ // looks like:
+ // call "L1$pb"
+ // "L1$pb":
+ // popl %esi
+
+ // Emit the call.
+ MCSymbol *PICBase = MCInstLowering.GetPICBaseSymbol();
+ TmpInst.setOpcode(X86::CALLpcrel32);
+ // FIXME: We would like an efficient form for this, so we don't have to do a
+ // lot of extra uniquing.
+ TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
+ OutContext)));
+ printMCInst(&TmpInst);
+ O << '\n';
+
+ // Emit the label.
+ OutStreamer.EmitLabel(PICBase);
+
+ // popl $reg
+ TmpInst.setOpcode(X86::POP32r);
+ TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
+ printMCInst(&TmpInst);
+ return;
+ }
+
+ case X86::ADD32ri: {
+ // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
+ if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
+ break;
+
+ // Okay, we have something like:
+ // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
+
+ // For this, we want to print something like:
+ // MYGLOBAL + (. - PICBASE)
+ // However, we can't generate a ".", so just emit a new label here and refer
+ // to it. We know that this operand flag occurs at most once per function.
+ SmallString<64> Name;
+ raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
+ << "picbaseref" << getFunctionNumber();
+ MCSymbol *DotSym = OutContext.GetOrCreateSymbol(Name.str());
+ OutStreamer.EmitLabel(DotSym);
+
+ // Now that we have emitted the label, lower the complex operand expression.
+ MCSymbol *OpSym = MCInstLowering.GetExternalSymbolSymbol(MI->getOperand(2));
+
+ const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
+ const MCExpr *PICBase =
+ MCSymbolRefExpr::Create(MCInstLowering.GetPICBaseSymbol(), OutContext);
+ DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
+
+ DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
+ DotExpr, OutContext);
+
+ MCInst TmpInst;
+ TmpInst.setOpcode(X86::ADD32ri);
+ TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
+ TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
+ printMCInst(&TmpInst);
+ return;
+ }
+ }
+
+ MCInst TmpInst;
+ MCInstLowering.Lower(MI, TmpInst);
+
+
+ printMCInst(&TmpInst);
+}
+
diff --git a/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86MCInstLower.h b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86MCInstLower.h
new file mode 100644
index 0000000..fa25b90
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/X86/AsmPrinter/X86MCInstLower.h
@@ -0,0 +1,54 @@
+//===-- X86MCInstLower.h - Lower MachineInstr to MCInst -------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef X86_MCINSTLOWER_H
+#define X86_MCINSTLOWER_H
+
+#include "llvm/Support/Compiler.h"
+
+namespace llvm {
+ class MCContext;
+ class MCInst;
+ class MCOperand;
+ class MCSymbol;
+ class MachineInstr;
+ class MachineModuleInfoMachO;
+ class MachineOperand;
+ class Mangler;
+ class X86AsmPrinter;
+ class X86Subtarget;
+
+/// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
+class VISIBILITY_HIDDEN X86MCInstLower {
+ MCContext &Ctx;
+ Mangler *Mang;
+ X86AsmPrinter &AsmPrinter;
+
+ const X86Subtarget &getSubtarget() const;
+public:
+ X86MCInstLower(MCContext &ctx, Mangler *mang, X86AsmPrinter &asmprinter)
+ : Ctx(ctx), Mang(mang), AsmPrinter(asmprinter) {}
+
+ void Lower(const MachineInstr *MI, MCInst &OutMI) const;
+
+ MCSymbol *GetPICBaseSymbol() const;
+
+ MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const;
+ MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const;
+ MCSymbol *GetJumpTableSymbol(const MachineOperand &MO) const;
+ MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const;
+ MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
+
+private:
+ MachineModuleInfoMachO &getMachOMMI() const;
+};
+
+}
+
+#endif
diff --git a/libclamav/c++/llvm/lib/Target/X86/CMakeLists.txt b/libclamav/c++/llvm/lib/Target/X86/CMakeLists.txt
index 346d6c8..3ad65fb 100644
--- a/libclamav/c++/llvm/lib/Target/X86/CMakeLists.txt
+++ b/libclamav/c++/llvm/lib/Target/X86/CMakeLists.txt
@@ -15,6 +15,7 @@ tablegen(X86GenSubtarget.inc -gen-subtarget)
set(sources
X86CodeEmitter.cpp
+ X86COFFMachineModuleInfo.cpp
X86ELFWriterInfo.cpp
X86FloatingPoint.cpp
X86FloatingPointRegKill.cpp
@@ -26,6 +27,7 @@ set(sources
X86RegisterInfo.cpp
X86Subtarget.cpp
X86TargetMachine.cpp
+ X86TargetObjectFile.cpp
X86FastISel.cpp
)
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86.td b/libclamav/c++/llvm/lib/Target/X86/X86.td
index e7aa1f2..da467fe 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86.td
+++ b/libclamav/c++/llvm/lib/Target/X86/X86.td
@@ -19,12 +19,17 @@ include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// X86 Subtarget features.
//===----------------------------------------------------------------------===//
-
+
+def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
+ "Enable conditional move instructions">;
+
def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
"Enable MMX instructions">;
def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
"Enable SSE instructions",
- [FeatureMMX]>;
+ // SSE codegen depends on cmovs, and all
+ // SSE1+ processors support them.
+ [FeatureMMX, FeatureCMOV]>;
def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
"Enable SSE2 instructions",
[FeatureSSE1]>;
@@ -76,8 +81,8 @@ def : Proc<"i586", []>;
def : Proc<"pentium", []>;
def : Proc<"pentium-mmx", [FeatureMMX]>;
def : Proc<"i686", []>;
-def : Proc<"pentiumpro", []>;
-def : Proc<"pentium2", [FeatureMMX]>;
+def : Proc<"pentiumpro", [FeatureCMOV]>;
+def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
def : Proc<"pentium3", [FeatureSSE1]>;
def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
def : Proc<"pentium4", [FeatureSSE2]>;
@@ -193,11 +198,11 @@ def ATTAsmParser : AsmParser {
// The X86 target supports two different syntaxes for emitting machine code.
// This is controlled by the -x86-asm-syntax={att|intel}
def ATTAsmWriter : AsmWriter {
- string AsmWriterClassName = "ATTAsmPrinter";
+ string AsmWriterClassName = "ATTInstPrinter";
int Variant = 0;
}
def IntelAsmWriter : AsmWriter {
- string AsmWriterClassName = "IntelAsmPrinter";
+ string AsmWriterClassName = "IntelInstPrinter";
int Variant = 1;
}
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp b/libclamav/c++/llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp
new file mode 100644
index 0000000..01c4fcf
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp
@@ -0,0 +1,123 @@
+//===-- llvm/CodeGen/X86COFFMachineModuleInfo.cpp -------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This is an MMI implementation for X86 COFF (windows) targets.
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86COFFMachineModuleInfo.h"
+#include "X86MachineFunctionInfo.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/Function.h"
+#include "llvm/Target/TargetData.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/Support/raw_ostream.h"
+using namespace llvm;
+
+X86COFFMachineModuleInfo::X86COFFMachineModuleInfo(const MachineModuleInfo &) {
+}
+X86COFFMachineModuleInfo::~X86COFFMachineModuleInfo() {
+
+}
+
+void X86COFFMachineModuleInfo::AddFunctionInfo(const Function *F,
+ const X86MachineFunctionInfo &Val) {
+ FunctionInfoMap[F] = Val;
+}
+
+
+
+static X86MachineFunctionInfo calculateFunctionInfo(const Function *F,
+ const TargetData &TD) {
+ X86MachineFunctionInfo Info;
+ uint64_t Size = 0;
+
+ switch (F->getCallingConv()) {
+ case CallingConv::X86_StdCall:
+ Info.setDecorationStyle(StdCall);
+ break;
+ case CallingConv::X86_FastCall:
+ Info.setDecorationStyle(FastCall);
+ break;
+ default:
+ return Info;
+ }
+
+ unsigned argNum = 1;
+ for (Function::const_arg_iterator AI = F->arg_begin(), AE = F->arg_end();
+ AI != AE; ++AI, ++argNum) {
+ const Type* Ty = AI->getType();
+
+ // 'Dereference' type in case of byval parameter attribute
+ if (F->paramHasAttr(argNum, Attribute::ByVal))
+ Ty = cast<PointerType>(Ty)->getElementType();
+
+ // Size should be aligned to DWORD boundary
+ Size += ((TD.getTypeAllocSize(Ty) + 3)/4)*4;
+ }
+
+ // We're not supporting tooooo huge arguments :)
+ Info.setBytesToPopOnReturn((unsigned int)Size);
+ return Info;
+}
+
+
+/// DecorateCygMingName - Query FunctionInfoMap and use this information for
+/// various name decorations for Cygwin and MingW.
+void X86COFFMachineModuleInfo::DecorateCygMingName(SmallVectorImpl<char> &Name,
+ const GlobalValue *GV,
+ const TargetData &TD) {
+ const Function *F = dyn_cast<Function>(GV);
+ if (!F) return;
+
+ // Save function name for later type emission.
+ if (F->isDeclaration())
+ CygMingStubs.insert(StringRef(Name.data(), Name.size()));
+
+ // We don't want to decorate non-stdcall or non-fastcall functions right now
+ CallingConv::ID CC = F->getCallingConv();
+ if (CC != CallingConv::X86_StdCall && CC != CallingConv::X86_FastCall)
+ return;
+
+ const X86MachineFunctionInfo *Info;
+
+ FMFInfoMap::const_iterator info_item = FunctionInfoMap.find(F);
+ if (info_item == FunctionInfoMap.end()) {
+ // Calculate apropriate function info and populate map
+ FunctionInfoMap[F] = calculateFunctionInfo(F, TD);
+ Info = &FunctionInfoMap[F];
+ } else {
+ Info = &info_item->second;
+ }
+
+ if (Info->getDecorationStyle() == None) return;
+ const FunctionType *FT = F->getFunctionType();
+
+ // "Pure" variadic functions do not receive @0 suffix.
+ if (!FT->isVarArg() || FT->getNumParams() == 0 ||
+ (FT->getNumParams() == 1 && F->hasStructRetAttr()))
+ raw_svector_ostream(Name) << '@' << Info->getBytesToPopOnReturn();
+
+ if (Info->getDecorationStyle() == FastCall) {
+ if (Name[0] == '_')
+ Name[0] = '@';
+ else
+ Name.insert(Name.begin(), '@');
+ }
+}
+
+/// DecorateCygMingName - Query FunctionInfoMap and use this information for
+/// various name decorations for Cygwin and MingW.
+void X86COFFMachineModuleInfo::DecorateCygMingName(std::string &Name,
+ const GlobalValue *GV,
+ const TargetData &TD) {
+ SmallString<128> NameStr(Name.begin(), Name.end());
+ DecorateCygMingName(NameStr, GV, TD);
+ Name.assign(NameStr.begin(), NameStr.end());
+}
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86COFFMachineModuleInfo.h b/libclamav/c++/llvm/lib/Target/X86/X86COFFMachineModuleInfo.h
new file mode 100644
index 0000000..afd5525
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/X86/X86COFFMachineModuleInfo.h
@@ -0,0 +1,67 @@
+//===-- llvm/CodeGen/X86COFFMachineModuleInfo.h -----------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This is an MMI implementation for X86 COFF (windows) targets.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef X86COFF_MACHINEMODULEINFO_H
+#define X86COFF_MACHINEMODULEINFO_H
+
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/ADT/StringSet.h"
+
+namespace llvm {
+ class X86MachineFunctionInfo;
+ class TargetData;
+
+/// X86COFFMachineModuleInfo - This is a MachineModuleInfoImpl implementation
+/// for X86 COFF targets.
+class X86COFFMachineModuleInfo : public MachineModuleInfoImpl {
+ StringSet<> CygMingStubs;
+
+ // We have to propagate some information about MachineFunction to
+ // AsmPrinter. It's ok, when we're printing the function, since we have
+ // access to MachineFunction and can get the appropriate MachineFunctionInfo.
+ // Unfortunately, this is not possible when we're printing reference to
+ // Function (e.g. calling it and so on). Even more, there is no way to get the
+ // corresponding MachineFunctions: it can even be not created at all. That's
+ // why we should use additional structure, when we're collecting all necessary
+ // information.
+ //
+ // This structure is using e.g. for name decoration for stdcall & fastcall'ed
+ // function, since we have to use arguments' size for decoration.
+ typedef std::map<const Function*, X86MachineFunctionInfo> FMFInfoMap;
+ FMFInfoMap FunctionInfoMap;
+
+public:
+ X86COFFMachineModuleInfo(const MachineModuleInfo &);
+ ~X86COFFMachineModuleInfo();
+
+
+ void DecorateCygMingName(std::string &Name, const GlobalValue *GV,
+ const TargetData &TD);
+ void DecorateCygMingName(SmallVectorImpl<char> &Name, const GlobalValue *GV,
+ const TargetData &TD);
+
+ void AddFunctionInfo(const Function *F, const X86MachineFunctionInfo &Val);
+
+
+ typedef StringSet<>::const_iterator stub_iterator;
+ stub_iterator stub_begin() const { return CygMingStubs.begin(); }
+ stub_iterator stub_end() const { return CygMingStubs.end(); }
+
+
+};
+
+
+
+} // end namespace llvm
+
+#endif
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86CodeEmitter.cpp b/libclamav/c++/llvm/lib/Target/X86/X86CodeEmitter.cpp
index 7e2fd97..4c12edd 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86CodeEmitter.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/X86CodeEmitter.cpp
@@ -324,32 +324,27 @@ void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
// Otherwise, this is something that requires a relocation. Emit it as such
// now.
+ unsigned RelocType = Is64BitMode ?
+ (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
+ : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
if (RelocOp->isGlobal()) {
// In 64-bit static small code model, we could potentially emit absolute.
// But it's probably not beneficial. If the MCE supports using RIP directly
// do it, otherwise fallback to absolute (this is determined by IsPCRel).
// 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
// 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
- unsigned rt = Is64BitMode ?
- (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
- : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
bool NeedStub = isa<Function>(RelocOp->getGlobal());
bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
- emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
+ emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
Adj, NeedStub, Indirect);
+ } else if (RelocOp->isSymbol()) {
+ emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
} else if (RelocOp->isCPI()) {
- unsigned rt = Is64BitMode ?
- (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
- : (IsPCRel ? X86::reloc_picrel_word : X86::reloc_absolute_word);
- emitConstPoolAddress(RelocOp->getIndex(), rt,
+ emitConstPoolAddress(RelocOp->getIndex(), RelocType,
RelocOp->getOffset(), Adj);
- } else if (RelocOp->isJTI()) {
- unsigned rt = Is64BitMode ?
- (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
- : (IsPCRel ? X86::reloc_picrel_word : X86::reloc_absolute_word);
- emitJumpTableAddress(RelocOp->getIndex(), rt, Adj);
} else {
- llvm_unreachable("Unknown value to relocate!");
+ assert(RelocOp->isJTI() && "Unexpected machine operand!");
+ emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
}
}
@@ -364,6 +359,8 @@ void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
// Figure out what sort of displacement we have to handle here.
if (Op3.isGlobal()) {
DispForReloc = &Op3;
+ } else if (Op3.isSymbol()) {
+ DispForReloc = &Op3;
} else if (Op3.isCPI()) {
if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
DispForReloc = &Op3;
@@ -595,9 +592,11 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
break;
case TargetInstrInfo::DBG_LABEL:
case TargetInstrInfo::EH_LABEL:
+ case TargetInstrInfo::GC_LABEL:
MCE.emitLabel(MI.getOperand(0).getImm());
break;
case TargetInstrInfo::IMPLICIT_DEF:
+ case TargetInstrInfo::KILL:
case X86::DWARF_LOC:
case X86::FP_REG_KILL:
break;
@@ -1094,7 +1093,7 @@ public:
if (!OK) {
errs() << "couldn't convert inst '";
- MI.print(errs());
+ MI.dump();
errs() << "' to machine instr:\n";
Instr->dump();
}
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86FastISel.cpp b/libclamav/c++/llvm/lib/Target/X86/X86FastISel.cpp
index a184c39..ef931bd 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/X86FastISel.cpp
@@ -118,7 +118,7 @@ private:
bool X86VisitIntrinsicCall(IntrinsicInst &I);
bool X86SelectCall(Instruction *I);
- CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
+ CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false);
const X86InstrInfo *getInstrInfo() const {
return getTargetMachine()->getInstrInfo();
@@ -169,7 +169,8 @@ bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) {
/// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
/// convention.
-CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
+CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC,
+ bool isTaillCall) {
if (Subtarget->is64Bit()) {
if (Subtarget->isTargetWin64())
return CC_X86_Win64_C;
@@ -1223,7 +1224,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
// Handle only C and fastcc calling conventions for now.
CallSite CS(CI);
- unsigned CC = CS.getCallingConv();
+ CallingConv::ID CC = CS.getCallingConv();
if (CC != CallingConv::C &&
CC != CallingConv::Fast &&
CC != CallingConv::X86_FastCall)
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86FloatingPoint.cpp b/libclamav/c++/llvm/lib/Target/X86/X86FloatingPoint.cpp
index af0da6f..d9a05a8 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -213,6 +213,14 @@ bool FPS::runOnMachineFunction(MachineFunction &MF) {
I != E; ++I)
Changed |= processBasicBlock(MF, **I);
+ // Process any unreachable blocks in arbitrary order now.
+ if (MF.size() == Processed.size())
+ return Changed;
+
+ for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
+ if (Processed.insert(BB))
+ Changed |= processBasicBlock(MF, *BB);
+
return Changed;
}
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/libclamav/c++/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 22d676e..71b4062 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -364,7 +364,9 @@ static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
Store.getOperand(2), Store.getOperand(3));
}
-/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
+/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG. The
+/// chain produced by the load must only be used by the store's chain operand,
+/// otherwise this may produce a cycle in the DAG.
///
static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
SDValue &Load) {
@@ -382,8 +384,9 @@ static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
return false;
if (N.hasOneUse() &&
+ LD->hasNUsesOfValue(1, 1) &&
N.getOperand(1) == Address &&
- N.getNode()->isOperandOf(Chain.getNode())) {
+ LD->isOperandOf(Chain.getNode())) {
Load = N;
return true;
}
@@ -447,7 +450,8 @@ static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
if (Chain.getOperand(0).getNode() == Callee.getNode())
return true;
if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
- Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()))
+ Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
+ Callee.getValue(1).hasOneUse())
return true;
return false;
}
@@ -1461,11 +1465,14 @@ SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
return NULL;
- SDValue LSI = Node->getOperand(4); // MemOperand
- const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain};
- return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
- MVT::i32, MVT::i32, MVT::Other, Ops,
- array_lengthof(Ops));
+ MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
+ MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
+ const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
+ SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
+ MVT::i32, MVT::i32, MVT::Other, Ops,
+ array_lengthof(Ops));
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
+ return ResNode;
}
SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
@@ -1599,17 +1606,20 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
}
DebugLoc dl = Node->getDebugLoc();
- SDValue Undef = SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
- dl, NVT), 0);
- SDValue MemOp = CurDAG->getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
+ SDValue Undef = SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF,
+ dl, NVT), 0);
+ MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
+ MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
if (isInc || isDec) {
- SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, MemOp, Chain };
- SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7), 0);
+ SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
+ SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0);
+ cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
SDValue RetVals[] = { Undef, Ret };
return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
} else {
- SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, MemOp, Chain };
- SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8), 0);
+ SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
+ SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
+ cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
SDValue RetVals[] = { Undef, Ret };
return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
}
@@ -1719,14 +1729,14 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
- array_lengthof(Ops));
+ CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
+ array_lengthof(Ops));
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
}
// Copy the low half of the result, if it is needed.
@@ -1752,8 +1762,8 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
- Result,
+ Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
+ Result,
CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8.
Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
@@ -1842,14 +1852,14 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16,
- MVT::Other, Ops,
- array_lengthof(Ops)), 0);
+ SDValue(CurDAG->getMachineNode(X86::MOVZX16rm8, dl, MVT::i16,
+ MVT::Other, Ops,
+ array_lengthof(Ops)), 0);
Chain = Move.getValue(1);
ReplaceUses(N0.getValue(1), Chain);
} else {
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
+ SDValue(CurDAG->getMachineNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
Chain = CurDAG->getEntryNode();
}
Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
@@ -1861,27 +1871,27 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
if (isSigned && !signBitIsZero) {
// Sign extend the low part into the high part.
InFlag =
- SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
+ SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
} else {
// Zero out the high part, effectively zero extending the input.
SDValue ClrNode;
if (NVT.getSimpleVT() == MVT::i64) {
- ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, MVT::i32),
+ ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, MVT::i32),
0);
// We just did a 32-bit clear, insert it into a 64-bit register to
// clear the whole 64-bit reg.
SDValue Undef =
- SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
- dl, MVT::i64), 0);
+ SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF,
+ dl, MVT::i64), 0);
SDValue SubRegNo =
CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
ClrNode =
- SDValue(CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl,
- MVT::i64, Undef, ClrNode, SubRegNo),
+ SDValue(CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
+ MVT::i64, Undef, ClrNode, SubRegNo),
0);
} else {
- ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT), 0);
+ ClrNode = SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
}
InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, HiReg,
@@ -1893,14 +1903,14 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
- array_lengthof(Ops));
+ CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
+ array_lengthof(Ops));
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
}
// Copy the division (low) result, if it is needed.
@@ -1926,7 +1936,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
+ Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
Result,
CurDAG->getTargetConstant(8, MVT::i8)),
0);
@@ -1981,8 +1991,8 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
default: llvm_unreachable("Unsupported TEST operand type!");
}
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
- Reg = SDValue(CurDAG->getTargetNode(X86::COPY_TO_REGCLASS, dl,
- Reg.getValueType(), Reg, RC), 0);
+ Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
+ Reg.getValueType(), Reg, RC), 0);
}
// Extract the l-register.
@@ -1990,7 +2000,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
MVT::i8, Reg);
// Emit a testb.
- return CurDAG->getTargetNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
+ return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
}
// For example, "testl %eax, $2048" to "testb %ah, $8".
@@ -2009,8 +2019,8 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
default: llvm_unreachable("Unsupported TEST operand type!");
}
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
- Reg = SDValue(CurDAG->getTargetNode(X86::COPY_TO_REGCLASS, dl,
- Reg.getValueType(), Reg, RC), 0);
+ Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
+ Reg.getValueType(), Reg, RC), 0);
// Extract the h-register.
SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT_HI, dl,
@@ -2018,8 +2028,8 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
// Emit a testb. No special NOREX tricks are needed since there's
// only one GPR operand!
- return CurDAG->getTargetNode(X86::TEST8ri, dl, MVT::i32,
- Subreg, ShiftedImm);
+ return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
+ Subreg, ShiftedImm);
}
// For example, "testl %eax, $32776" to "testw %ax, $32776".
@@ -2033,7 +2043,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
MVT::i16, Reg);
// Emit a testw.
- return CurDAG->getTargetNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
+ return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
}
// For example, "testq %rax, $268468232" to "testl %eax, $268468232".
@@ -2047,7 +2057,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
MVT::i32, Reg);
// Emit a testl.
- return CurDAG->getTargetNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
+ return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
}
}
break;
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86ISelLowering.cpp b/libclamav/c++/llvm/lib/Target/X86/X86ISelLowering.cpp
index 15af42e..de44adf 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -16,6 +16,7 @@
#include "X86InstrBuilder.h"
#include "X86ISelLowering.h"
#include "X86TargetMachine.h"
+#include "X86TargetObjectFile.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
@@ -36,7 +37,6 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
@@ -47,6 +47,14 @@ using namespace llvm;
static cl::opt<bool>
DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
+// Disable16Bit - 16-bit operations typically have a larger encoding than
+// corresponding 32-bit instructions, and 16-bit code is slow on some
+// processors. This is an experimental flag to disable 16-bit operations
+// (which forces them to be Legalized to 32-bit operations).
+static cl::opt<bool>
+Disable16Bit("disable-16bit", cl::Hidden,
+ cl::desc("Disable use of 16-bit instructions"));
+
// Forward declarations.
static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
SDValue V2);
@@ -55,7 +63,9 @@ static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
switch (TM.getSubtarget<X86Subtarget>().TargetType) {
default: llvm_unreachable("unknown subtarget type");
case X86Subtarget::isDarwin:
- return new TargetLoweringObjectFileMachO();
+ if (TM.getSubtarget<X86Subtarget>().is64Bit())
+ return new X8664_MachoTargetObjectFile();
+ return new X8632_MachoTargetObjectFile();
case X86Subtarget::isELF:
return new TargetLoweringObjectFileELF();
case X86Subtarget::isMingw:
@@ -99,7 +109,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// Set up the register classes.
addRegisterClass(MVT::i8, X86::GR8RegisterClass);
- addRegisterClass(MVT::i16, X86::GR16RegisterClass);
+ if (!Disable16Bit)
+ addRegisterClass(MVT::i16, X86::GR16RegisterClass);
addRegisterClass(MVT::i32, X86::GR32RegisterClass);
if (Subtarget->is64Bit())
addRegisterClass(MVT::i64, X86::GR64RegisterClass);
@@ -108,9 +119,11 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// We don't accept any truncstore of integer registers.
setTruncStoreAction(MVT::i64, MVT::i32, Expand);
- setTruncStoreAction(MVT::i64, MVT::i16, Expand);
+ if (!Disable16Bit)
+ setTruncStoreAction(MVT::i64, MVT::i16, Expand);
setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
- setTruncStoreAction(MVT::i32, MVT::i16, Expand);
+ if (!Disable16Bit)
+ setTruncStoreAction(MVT::i32, MVT::i16, Expand);
setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
setTruncStoreAction(MVT::i16, MVT::i8, Expand);
@@ -261,8 +274,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
- setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
- setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
+ if (Disable16Bit) {
+ setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
+ setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
+ } else {
+ setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
+ setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
+ }
setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
@@ -279,13 +297,19 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::SELECT , MVT::i1 , Promote);
// X86 wants to expand cmov itself.
setOperationAction(ISD::SELECT , MVT::i8 , Custom);
- setOperationAction(ISD::SELECT , MVT::i16 , Custom);
+ if (Disable16Bit)
+ setOperationAction(ISD::SELECT , MVT::i16 , Expand);
+ else
+ setOperationAction(ISD::SELECT , MVT::i16 , Custom);
setOperationAction(ISD::SELECT , MVT::i32 , Custom);
setOperationAction(ISD::SELECT , MVT::f32 , Custom);
setOperationAction(ISD::SELECT , MVT::f64 , Custom);
setOperationAction(ISD::SELECT , MVT::f80 , Custom);
setOperationAction(ISD::SETCC , MVT::i8 , Custom);
- setOperationAction(ISD::SETCC , MVT::i16 , Custom);
+ if (Disable16Bit)
+ setOperationAction(ISD::SETCC , MVT::i16 , Expand);
+ else
+ setOperationAction(ISD::SETCC , MVT::i16 , Custom);
setOperationAction(ISD::SETCC , MVT::i32 , Custom);
setOperationAction(ISD::SETCC , MVT::f32 , Custom);
setOperationAction(ISD::SETCC , MVT::f64 , Custom);
@@ -1063,7 +1087,7 @@ unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
SDValue
X86TargetLowering::LowerReturn(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) {
@@ -1085,7 +1109,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
SmallVector<SDValue, 6> RetOps;
RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
// Operand #1 = Bytes To Pop
- RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
+ RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
@@ -1155,7 +1179,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
///
SDValue
X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) {
@@ -1255,7 +1279,7 @@ ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
/// IsCalleePop - Determines whether the callee is required to pop its
/// own arguments. Callee pop is necessary to support tail calls.
-bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
+bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
if (IsVarArg)
return false;
@@ -1273,7 +1297,7 @@ bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
/// given CallingConvention value.
-CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
+CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
if (Subtarget->is64Bit()) {
if (Subtarget->isTargetWin64())
return CC_X86_Win64_C;
@@ -1292,7 +1316,7 @@ CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
/// NameDecorationForCallConv - Selects the appropriate decoration to
/// apply to a MachineFunction containing a given calling convention.
NameDecorationStyle
-X86TargetLowering::NameDecorationForCallConv(unsigned CallConv) {
+X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
if (CallConv == CallingConv::X86_FastCall)
return FastCall;
else if (CallConv == CallingConv::X86_StdCall)
@@ -1316,7 +1340,7 @@ CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
SDValue
X86TargetLowering::LowerMemArgument(SDValue Chain,
- unsigned CallConv,
+ CallingConv::ID CallConv,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
const CCValAssign &VA,
@@ -1351,7 +1375,7 @@ X86TargetLowering::LowerMemArgument(SDValue Chain,
SDValue
X86TargetLowering::LowerFormalArguments(SDValue Chain,
- unsigned CallConv,
+ CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl,
@@ -1652,7 +1676,8 @@ EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
SDValue
X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg, bool isTailCall,
+ CallingConv::ID CallConv, bool isVarArg,
+ bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -2097,12 +2122,12 @@ unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
/// optimization should implement this function.
bool
X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
- unsigned CalleeCC,
+ CallingConv::ID CalleeCC,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
- unsigned CallerCC = MF.getFunction()->getCallingConv();
+ CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
}
@@ -4139,8 +4164,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
if (isShift && ShVal.hasOneUse()) {
// If the shifted value has multiple uses, it may be cheaper to use
// v_set0 + movlhps or movhlps, etc.
- EVT EVT = VT.getVectorElementType();
- ShAmt *= EVT.getSizeInBits();
+ EVT EltVT = VT.getVectorElementType();
+ ShAmt *= EltVT.getSizeInBits();
return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
}
@@ -4167,8 +4192,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
if (isShift) {
// No better options. Use a vshl / vsrl.
- EVT EVT = VT.getVectorElementType();
- ShAmt *= EVT.getSizeInBits();
+ EVT EltVT = VT.getVectorElementType();
+ ShAmt *= EltVT.getSizeInBits();
return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
}
@@ -4343,10 +4368,10 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
MVT::v4i32, Vec),
Op.getOperand(1)));
// Transform it so it match pextrw which produces a 32-bit result.
- EVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
- SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
+ EVT EltVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
+ SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
Op.getOperand(0), Op.getOperand(1));
- SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
+ SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
} else if (VT.getSizeInBits() == 32) {
@@ -4386,17 +4411,17 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
SDValue
X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
EVT VT = Op.getValueType();
- EVT EVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
DebugLoc dl = Op.getDebugLoc();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
- if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
+ if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
isa<ConstantSDNode>(N2)) {
- unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
- : X86ISD::PINSRW;
+ unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
+ : X86ISD::PINSRW;
// Transform it so it match pinsr{b,w} which expects a GR32 as its second
// argument.
if (N1.getValueType() != MVT::i32)
@@ -4404,7 +4429,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
if (N2.getValueType() != MVT::i32)
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
return DAG.getNode(Opc, dl, VT, N0, N1, N2);
- } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
+ } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
// Bits [7:6] of the constant are the source select. This will always be
// zero here. The DAG Combiner may combine an extract_elt index into these
// bits. For example (insert (extract, 3), 2) could be matched by putting
@@ -4417,7 +4442,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
// Create this as a scalar to vector..
N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
- } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
+ } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
// PINSR* works with constant index.
return Op;
}
@@ -4427,12 +4452,12 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
SDValue
X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
EVT VT = Op.getValueType();
- EVT EVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
if (Subtarget->hasSSE41())
return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
- if (EVT == MVT::i8)
+ if (EltVT == MVT::i8)
return SDValue();
DebugLoc dl = Op.getDebugLoc();
@@ -4440,7 +4465,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
- if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
+ if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
// Transform it so it match pinsrw which expects a 16-bit value in a GR32
// as its second argument.
if (N1.getValueType() != MVT::i32)
@@ -5175,11 +5200,8 @@ SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
EVT VT = Op.getValueType();
EVT EltVT = VT;
- unsigned EltNum = 1;
- if (VT.isVector()) {
+ if (VT.isVector())
EltVT = VT.getVectorElementType();
- EltNum = VT.getVectorNumElements();
- }
std::vector<Constant*> CV;
if (EltVT == MVT::f64) {
Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
@@ -5341,21 +5363,48 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
Opcode = X86ISD::ADD;
NumOperands = 2;
break;
+ case ISD::AND: {
+ // If the primary and result isn't used, don't bother using X86ISD::AND,
+ // because a TEST instruction will be better.
+ bool NonFlagUse = false;
+ for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
+ UE = Op.getNode()->use_end(); UI != UE; ++UI)
+ if (UI->getOpcode() != ISD::BRCOND &&
+ UI->getOpcode() != ISD::SELECT &&
+ UI->getOpcode() != ISD::SETCC) {
+ NonFlagUse = true;
+ break;
+ }
+ if (!NonFlagUse)
+ break;
+ }
+ // FALL THROUGH
case ISD::SUB:
- // Due to the ISEL shortcoming noted above, be conservative if this sub is
+ case ISD::OR:
+ case ISD::XOR:
+ // Due to the ISEL shortcoming noted above, be conservative if this op is
// likely to be selected as part of a load-modify-store instruction.
for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
UE = Op.getNode()->use_end(); UI != UE; ++UI)
if (UI->getOpcode() == ISD::STORE)
goto default_case;
- // Otherwise use a regular EFLAGS-setting sub.
- Opcode = X86ISD::SUB;
+ // Otherwise use a regular EFLAGS-setting instruction.
+ switch (Op.getNode()->getOpcode()) {
+ case ISD::SUB: Opcode = X86ISD::SUB; break;
+ case ISD::OR: Opcode = X86ISD::OR; break;
+ case ISD::XOR: Opcode = X86ISD::XOR; break;
+ case ISD::AND: Opcode = X86ISD::AND; break;
+ default: llvm_unreachable("unexpected operator!");
+ }
NumOperands = 2;
break;
case X86ISD::ADD:
case X86ISD::SUB:
case X86ISD::INC:
case X86ISD::DEC:
+ case X86ISD::OR:
+ case X86ISD::XOR:
+ case X86ISD::AND:
return SDValue(Op.getNode(), 1);
default:
default_case:
@@ -5583,7 +5632,10 @@ static bool isX86LogicalCmp(SDValue Op) {
Opc == X86ISD::SMUL ||
Opc == X86ISD::UMUL ||
Opc == X86ISD::INC ||
- Opc == X86ISD::DEC))
+ Opc == X86ISD::DEC ||
+ Opc == X86ISD::OR ||
+ Opc == X86ISD::XOR ||
+ Opc == X86ISD::AND))
return true;
return false;
@@ -6336,9 +6388,23 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
break;
}
}
+
+ // The vector shift intrinsics with scalars uses 32b shift amounts but
+ // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
+ // to be zero.
+ SDValue ShOps[4];
+ ShOps[0] = ShAmt;
+ ShOps[1] = DAG.getConstant(0, MVT::i32);
+ if (ShAmtVT == MVT::v4i32) {
+ ShOps[2] = DAG.getUNDEF(MVT::i32);
+ ShOps[3] = DAG.getUNDEF(MVT::i32);
+ ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
+ } else {
+ ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
+ }
+
EVT VT = Op.getValueType();
- ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
- DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
+ ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(NewIntNo, MVT::i32),
Op.getOperand(1), ShAmt);
@@ -6476,7 +6542,7 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
} else {
const Function *Func =
cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
- unsigned CC = Func->getCallingConv();
+ CallingConv::ID CC = Func->getCallingConv();
unsigned NestReg;
switch (CC) {
@@ -6917,12 +6983,11 @@ ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
Node->getOperand(2), DAG.getIntPtrConstant(0));
SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Node->getOperand(2), DAG.getIntPtrConstant(1));
- // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
- // have a MemOperand. Pass the info through as a normal operand.
- SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
- SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
+ SDValue Ops[] = { Chain, In1, In2L, In2H };
SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
- SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
+ SDValue Result =
+ DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
+ cast<MemSDNode>(Node)->getMemOperand());
SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
Results.push_back(Result.getValue(2));
@@ -7097,6 +7162,9 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
case X86ISD::UMUL: return "X86ISD::UMUL";
case X86ISD::INC: return "X86ISD::INC";
case X86ISD::DEC: return "X86ISD::DEC";
+ case X86ISD::OR: return "X86ISD::OR";
+ case X86ISD::XOR: return "X86ISD::XOR";
+ case X86ISD::AND: return "X86ISD::AND";
case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
case X86ISD::PTEST: return "X86ISD::PTEST";
case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
@@ -7327,7 +7395,8 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
(*MIB).addOperand(*argOpers[i]);
MIB.addReg(t2);
assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
- (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
+ (*MIB).setMemRefs(bInstr->memoperands_begin(),
+ bInstr->memoperands_end());
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
MIB.addReg(EAXreg);
@@ -7479,7 +7548,8 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
(*MIB).addOperand(*argOpers[i]);
assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
- (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
+ (*MIB).setMemRefs(bInstr->memoperands_begin(),
+ bInstr->memoperands_end());
MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
MIB.addReg(X86::EAX);
@@ -7583,7 +7653,8 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
(*MIB).addOperand(*argOpers[i]);
MIB.addReg(t3);
assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
- (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
+ (*MIB).setMemRefs(mInstr->memoperands_begin(),
+ mInstr->memoperands_end());
MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
MIB.addReg(X86::EAX);
@@ -7599,23 +7670,17 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
// all of this code can be replaced with that in the .td file.
MachineBasicBlock *
X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
- unsigned numArgs, bool memArg) const {
+ unsigned numArgs, bool memArg) const {
MachineFunction *F = BB->getParent();
DebugLoc dl = MI->getDebugLoc();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
unsigned Opc;
-
- if (memArg) {
- Opc = numArgs == 3 ?
- X86::PCMPISTRM128rm :
- X86::PCMPESTRM128rm;
- } else {
- Opc = numArgs == 3 ?
- X86::PCMPISTRM128rr :
- X86::PCMPESTRM128rr;
- }
+ if (memArg)
+ Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
+ else
+ Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
@@ -7684,6 +7749,11 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
// In the XMM save block, save all the XMM argument registers.
for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
+ MachineMemOperand *MMO =
+ F->getMachineMemOperand(
+ PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
+ MachineMemOperand::MOStore, Offset,
+ /*Size=*/16, /*Align=*/16);
BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
.addFrameIndex(RegSaveFrameIndex)
.addImm(/*Scale=*/1)
@@ -7691,10 +7761,7 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
.addImm(/*Disp=*/Offset)
.addReg(/*Segment=*/0)
.addReg(MI->getOperand(i).getReg())
- .addMemOperand(MachineMemOperand(
- PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
- MachineMemOperand::MOStore, Offset,
- /*Size=*/16, /*Align=*/16));
+ .addMemOperand(MMO);
}
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
@@ -7703,10 +7770,76 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
}
MachineBasicBlock *
-X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
- MachineBasicBlock *BB) const {
- DebugLoc dl = MI->getDebugLoc();
+X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
+ MachineBasicBlock *BB,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+ DebugLoc DL = MI->getDebugLoc();
+
+ // To "insert" a SELECT_CC instruction, we actually have to insert the
+ // diamond control-flow pattern. The incoming instruction knows the
+ // destination vreg to set, the condition code register to branch on, the
+ // true/false values to select between, and a branch opcode to use.
+ const BasicBlock *LLVM_BB = BB->getBasicBlock();
+ MachineFunction::iterator It = BB;
+ ++It;
+
+ // thisMBB:
+ // ...
+ // TrueVal = ...
+ // cmpTY ccX, r1, r2
+ // bCC copy1MBB
+ // fallthrough --> copy0MBB
+ MachineBasicBlock *thisMBB = BB;
+ MachineFunction *F = BB->getParent();
+ MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
+ MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+ unsigned Opc =
+ X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
+ BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
+ F->insert(It, copy0MBB);
+ F->insert(It, sinkMBB);
+ // Update machine-CFG edges by first adding all successors of the current
+ // block to the new block which will contain the Phi node for the select.
+ // Also inform sdisel of the edge changes.
+ for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
+ E = BB->succ_end(); I != E; ++I) {
+ EM->insert(std::make_pair(*I, sinkMBB));
+ sinkMBB->addSuccessor(*I);
+ }
+ // Next, remove all successors of the current block, and add the true
+ // and fallthrough blocks as its successors.
+ while (!BB->succ_empty())
+ BB->removeSuccessor(BB->succ_begin());
+ // Add the true and fallthrough blocks as its successors.
+ BB->addSuccessor(copy0MBB);
+ BB->addSuccessor(sinkMBB);
+
+ // copy0MBB:
+ // %FalseValue = ...
+ // # fallthrough to sinkMBB
+ BB = copy0MBB;
+
+ // Update machine-CFG edges
+ BB->addSuccessor(sinkMBB);
+
+ // sinkMBB:
+ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
+ // ...
+ BB = sinkMBB;
+ BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
+ .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
+ .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
+
+ F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ return BB;
+}
+
+
+MachineBasicBlock *
+X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
+ MachineBasicBlock *BB,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
switch (MI->getOpcode()) {
default: assert(false && "Unexpected instr type to insert");
case X86::CMOV_GR8:
@@ -7715,57 +7848,8 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case X86::CMOV_FR64:
case X86::CMOV_V4F32:
case X86::CMOV_V2F64:
- case X86::CMOV_V2I64: {
- // To "insert" a SELECT_CC instruction, we actually have to insert the
- // diamond control-flow pattern. The incoming instruction knows the
- // destination vreg to set, the condition code register to branch on, the
- // true/false values to select between, and a branch opcode to use.
- const BasicBlock *LLVM_BB = BB->getBasicBlock();
- MachineFunction::iterator It = BB;
- ++It;
-
- // thisMBB:
- // ...
- // TrueVal = ...
- // cmpTY ccX, r1, r2
- // bCC copy1MBB
- // fallthrough --> copy0MBB
- MachineBasicBlock *thisMBB = BB;
- MachineFunction *F = BB->getParent();
- MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
- MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- unsigned Opc =
- X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
- BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
- F->insert(It, copy0MBB);
- F->insert(It, sinkMBB);
- // Update machine-CFG edges by transferring all successors of the current
- // block to the new block which will contain the Phi node for the select.
- sinkMBB->transferSuccessors(BB);
-
- // Add the true and fallthrough blocks as its successors.
- BB->addSuccessor(copy0MBB);
- BB->addSuccessor(sinkMBB);
-
- // copy0MBB:
- // %FalseValue = ...
- // # fallthrough to sinkMBB
- BB = copy0MBB;
-
- // Update machine-CFG edges
- BB->addSuccessor(sinkMBB);
-
- // sinkMBB:
- // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
- // ...
- BB = sinkMBB;
- BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
- .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
- .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
-
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
- return BB;
- }
+ case X86::CMOV_V2I64:
+ return EmitLoweredSelect(MI, BB, EM);
case X86::FP32_TO_INT16_IN_MEM:
case X86::FP32_TO_INT32_IN_MEM:
@@ -7776,27 +7860,30 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case X86::FP80_TO_INT16_IN_MEM:
case X86::FP80_TO_INT32_IN_MEM:
case X86::FP80_TO_INT64_IN_MEM: {
+ const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+ DebugLoc DL = MI->getDebugLoc();
+
// Change the floating point control register to use "round towards zero"
// mode when truncating to an integer value.
MachineFunction *F = BB->getParent();
int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
- addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
+ addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
// Load the old value of the high byte of the control word...
unsigned OldCW =
F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
- addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
+ addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
CWFrameIdx);
// Set the high part to be round to zero...
- addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
+ addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
.addImm(0xC7F);
// Reload the modified control word now...
- addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
+ addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
// Restore the memory image of control word to original value
- addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
+ addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
.addReg(OldCW);
// Get the X86 opcode to use.
@@ -7835,11 +7922,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
} else {
AM.Disp = Op.getImm();
}
- addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
+ addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
.addReg(MI->getOperand(X86AddrNumOperands).getReg());
// Reload the original control word now.
- addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
+ addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
return BB;
@@ -8048,6 +8135,9 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
case X86ISD::UMUL:
case X86ISD::INC:
case X86ISD::DEC:
+ case X86ISD::OR:
+ case X86ISD::XOR:
+ case X86ISD::AND:
// These nodes' second result is a boolean.
if (Op.getResNo() == 0)
break;
@@ -8084,7 +8174,7 @@ static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
}
static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
- EVT EVT, LoadSDNode *&LDBase,
+ EVT EltVT, LoadSDNode *&LDBase,
unsigned &LastLoadedElt,
SelectionDAG &DAG, MachineFrameInfo *MFI,
const TargetLowering &TLI) {
@@ -8112,7 +8202,7 @@ static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
continue;
LoadSDNode *LD = cast<LoadSDNode>(Elt);
- if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI))
+ if (!TLI.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i, MFI))
return false;
LastLoadedElt = i;
}
@@ -8129,7 +8219,7 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
const TargetLowering &TLI) {
DebugLoc dl = N->getDebugLoc();
EVT VT = N->getValueType(0);
- EVT EVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
unsigned NumElems = VT.getVectorNumElements();
@@ -8140,7 +8230,7 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
LoadSDNode *LD = NULL;
unsigned LastLoadedElt;
- if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG,
+ if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
MFI, TLI))
return SDValue();
@@ -8170,56 +8260,158 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
SDValue LHS = N->getOperand(1);
SDValue RHS = N->getOperand(2);
- // If we have SSE[12] support, try to form min/max nodes.
+ // If we have SSE[12] support, try to form min/max nodes. SSE min/max
+ // instructions have the peculiarity that if either operand is a NaN,
+ // they chose what we call the RHS operand (and as such are not symmetric).
+ // It happens that this matches the semantics of the common C idiom
+ // x<y?x:y and related forms, so we can recognize these cases.
if (Subtarget->hasSSE2() &&
(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
Cond.getOpcode() == ISD::SETCC) {
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
unsigned Opcode = 0;
+ // Check for x CC y ? x : y.
if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
switch (CC) {
default: break;
- case ISD::SETOLE: // (X <= Y) ? X : Y -> min
+ case ISD::SETULT:
+ // This can be a min if we can prove that at least one of the operands
+ // is not a nan.
+ if (!FiniteOnlyFPMath()) {
+ if (DAG.isKnownNeverNaN(RHS)) {
+ // Put the potential NaN in the RHS so that SSE will preserve it.
+ std::swap(LHS, RHS);
+ } else if (!DAG.isKnownNeverNaN(LHS))
+ break;
+ }
+ Opcode = X86ISD::FMIN;
+ break;
+ case ISD::SETOLE:
+ // This can be a min if we can prove that at least one of the operands
+ // is not a nan.
+ if (!FiniteOnlyFPMath()) {
+ if (DAG.isKnownNeverNaN(LHS)) {
+ // Put the potential NaN in the RHS so that SSE will preserve it.
+ std::swap(LHS, RHS);
+ } else if (!DAG.isKnownNeverNaN(RHS))
+ break;
+ }
+ Opcode = X86ISD::FMIN;
+ break;
case ISD::SETULE:
- case ISD::SETLE:
- if (!UnsafeFPMath) break;
- // FALL THROUGH.
- case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
+ // This can be a min, but if either operand is a NaN we need it to
+ // preserve the original LHS.
+ std::swap(LHS, RHS);
+ case ISD::SETOLT:
case ISD::SETLT:
+ case ISD::SETLE:
Opcode = X86ISD::FMIN;
break;
- case ISD::SETOGT: // (X > Y) ? X : Y -> max
+ case ISD::SETOGE:
+ // This can be a max if we can prove that at least one of the operands
+ // is not a nan.
+ if (!FiniteOnlyFPMath()) {
+ if (DAG.isKnownNeverNaN(LHS)) {
+ // Put the potential NaN in the RHS so that SSE will preserve it.
+ std::swap(LHS, RHS);
+ } else if (!DAG.isKnownNeverNaN(RHS))
+ break;
+ }
+ Opcode = X86ISD::FMAX;
+ break;
case ISD::SETUGT:
+ // This can be a max if we can prove that at least one of the operands
+ // is not a nan.
+ if (!FiniteOnlyFPMath()) {
+ if (DAG.isKnownNeverNaN(RHS)) {
+ // Put the potential NaN in the RHS so that SSE will preserve it.
+ std::swap(LHS, RHS);
+ } else if (!DAG.isKnownNeverNaN(LHS))
+ break;
+ }
+ Opcode = X86ISD::FMAX;
+ break;
+ case ISD::SETUGE:
+ // This can be a max, but if either operand is a NaN we need it to
+ // preserve the original LHS.
+ std::swap(LHS, RHS);
+ case ISD::SETOGT:
case ISD::SETGT:
- if (!UnsafeFPMath) break;
- // FALL THROUGH.
- case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
case ISD::SETGE:
Opcode = X86ISD::FMAX;
break;
}
+ // Check for x CC y ? y : x -- a min/max with reversed arms.
} else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
switch (CC) {
default: break;
- case ISD::SETOGT: // (X > Y) ? Y : X -> min
+ case ISD::SETOGE:
+ // This can be a min if we can prove that at least one of the operands
+ // is not a nan.
+ if (!FiniteOnlyFPMath()) {
+ if (DAG.isKnownNeverNaN(RHS)) {
+ // Put the potential NaN in the RHS so that SSE will preserve it.
+ std::swap(LHS, RHS);
+ } else if (!DAG.isKnownNeverNaN(LHS))
+ break;
+ }
+ Opcode = X86ISD::FMIN;
+ break;
case ISD::SETUGT:
+ // This can be a min if we can prove that at least one of the operands
+ // is not a nan.
+ if (!FiniteOnlyFPMath()) {
+ if (DAG.isKnownNeverNaN(LHS)) {
+ // Put the potential NaN in the RHS so that SSE will preserve it.
+ std::swap(LHS, RHS);
+ } else if (!DAG.isKnownNeverNaN(RHS))
+ break;
+ }
+ Opcode = X86ISD::FMIN;
+ break;
+ case ISD::SETUGE:
+ // This can be a min, but if either operand is a NaN we need it to
+ // preserve the original LHS.
+ std::swap(LHS, RHS);
+ case ISD::SETOGT:
case ISD::SETGT:
- if (!UnsafeFPMath) break;
- // FALL THROUGH.
- case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
case ISD::SETGE:
Opcode = X86ISD::FMIN;
break;
- case ISD::SETOLE: // (X <= Y) ? Y : X -> max
+ case ISD::SETULT:
+ // This can be a max if we can prove that at least one of the operands
+ // is not a nan.
+ if (!FiniteOnlyFPMath()) {
+ if (DAG.isKnownNeverNaN(LHS)) {
+ // Put the potential NaN in the RHS so that SSE will preserve it.
+ std::swap(LHS, RHS);
+ } else if (!DAG.isKnownNeverNaN(RHS))
+ break;
+ }
+ Opcode = X86ISD::FMAX;
+ break;
+ case ISD::SETOLE:
+ // This can be a max if we can prove that at least one of the operands
+ // is not a nan.
+ if (!FiniteOnlyFPMath()) {
+ if (DAG.isKnownNeverNaN(RHS)) {
+ // Put the potential NaN in the RHS so that SSE will preserve it.
+ std::swap(LHS, RHS);
+ } else if (!DAG.isKnownNeverNaN(LHS))
+ break;
+ }
+ Opcode = X86ISD::FMAX;
+ break;
case ISD::SETULE:
- case ISD::SETLE:
- if (!UnsafeFPMath) break;
- // FALL THROUGH.
- case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
+ // This can be a max, but if either operand is a NaN we need it to
+ // preserve the original LHS.
+ std::swap(LHS, RHS);
+ case ISD::SETOLT:
case ISD::SETLT:
+ case ISD::SETLE:
Opcode = X86ISD::FMAX;
break;
}
@@ -8521,7 +8713,7 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
SDValue ShAmtOp = N->getOperand(1);
EVT EltVT = VT.getVectorElementType();
DebugLoc DL = N->getDebugLoc();
- SDValue BaseShAmt;
+ SDValue BaseShAmt = SDValue();
if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
unsigned NumElts = VT.getVectorNumElements();
unsigned i = 0;
@@ -8540,15 +8732,34 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
}
} else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
- BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
- DAG.getIntPtrConstant(0));
+ SDValue InVec = ShAmtOp.getOperand(0);
+ if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
+ unsigned NumElts = InVec.getValueType().getVectorNumElements();
+ unsigned i = 0;
+ for (; i != NumElts; ++i) {
+ SDValue Arg = InVec.getOperand(i);
+ if (Arg.getOpcode() == ISD::UNDEF) continue;
+ BaseShAmt = Arg;
+ break;
+ }
+ } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
+ unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
+ if (C->getZExtValue() == SplatIdx)
+ BaseShAmt = InVec.getOperand(1);
+ }
+ }
+ if (BaseShAmt.getNode() == 0)
+ BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
+ DAG.getIntPtrConstant(0));
} else
return SDValue();
+ // The shift amount is an i32.
if (EltVT.bitsGT(MVT::i32))
BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
else if (EltVT.bitsLT(MVT::i32))
- BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
+ BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
// The shift amount is identical so we can do a vector shift.
SDValue ValOp = N->getOperand(0);
@@ -9241,15 +9452,39 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
// Not found as a standard register?
if (Res.second == 0) {
- // GCC calls "st(0)" just plain "st".
+ // Map st(0) -> st(7) -> ST0
+ if (Constraint.size() == 7 && Constraint[0] == '{' &&
+ tolower(Constraint[1]) == 's' &&
+ tolower(Constraint[2]) == 't' &&
+ Constraint[3] == '(' &&
+ (Constraint[4] >= '0' && Constraint[4] <= '7') &&
+ Constraint[5] == ')' &&
+ Constraint[6] == '}') {
+
+ Res.first = X86::ST0+Constraint[4]-'0';
+ Res.second = X86::RFP80RegisterClass;
+ return Res;
+ }
+
+ // GCC allows "st(0)" to be called just plain "st".
if (StringsEqualNoCase("{st}", Constraint)) {
Res.first = X86::ST0;
Res.second = X86::RFP80RegisterClass;
+ return Res;
+ }
+
+ // flags -> EFLAGS
+ if (StringsEqualNoCase("{flags}", Constraint)) {
+ Res.first = X86::EFLAGS;
+ Res.second = X86::CCRRegisterClass;
+ return Res;
}
+
// 'A' means EAX + EDX.
if (Constraint == "A") {
Res.first = X86::EAX;
Res.second = X86::GR32_ADRegisterClass;
+ return Res;
}
return Res;
}
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86ISelLowering.h b/libclamav/c++/llvm/lib/Target/X86/X86ISelLowering.h
index 1c612a1..2f7b8ba 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/libclamav/c++/llvm/lib/Target/X86/X86ISelLowering.h
@@ -204,17 +204,6 @@ namespace llvm {
LCMPXCHG_DAG,
LCMPXCHG8_DAG,
- // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
- // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
- // Atomic 64-bit binary operations.
- ATOMADD64_DAG,
- ATOMSUB64_DAG,
- ATOMOR64_DAG,
- ATOMXOR64_DAG,
- ATOMAND64_DAG,
- ATOMNAND64_DAG,
- ATOMSWAP64_DAG,
-
// FNSTCW16m - Store FP control world into i16 memory.
FNSTCW16m,
@@ -237,7 +226,7 @@ namespace llvm {
// ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
ADD, SUB, SMUL, UMUL,
- INC, DEC,
+ INC, DEC, OR, XOR, AND,
// MUL_IMM - X86 specific multiply by immediate.
MUL_IMM,
@@ -248,7 +237,18 @@ namespace llvm {
// VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
// according to %al. An operator is needed so that this can be expanded
// with control flow.
- VASTART_SAVE_XMM_REGS
+ VASTART_SAVE_XMM_REGS,
+
+ // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
+ // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
+ // Atomic 64-bit binary operations.
+ ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ ATOMSUB64_DAG,
+ ATOMOR64_DAG,
+ ATOMXOR64_DAG,
+ ATOMAND64_DAG,
+ ATOMNAND64_DAG,
+ ATOMSWAP64_DAG
};
}
@@ -413,7 +413,8 @@ namespace llvm {
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
- MachineBasicBlock *MBB) const;
+ MachineBasicBlock *MBB,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
/// getTargetNodeName - This method returns the name of a target specific
@@ -521,7 +522,7 @@ namespace llvm {
/// optimization should implement this function.
virtual bool
IsEligibleForTailCallOptimization(SDValue Callee,
- unsigned CalleeCC,
+ CallingConv::ID CalleeCC,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const;
@@ -578,12 +579,12 @@ namespace llvm {
bool X86ScalarSSEf64;
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
SDValue LowerMemArgument(SDValue Chain,
- unsigned CallConv,
+ CallingConv::ID CallConv,
const SmallVectorImpl<ISD::InputArg> &ArgInfo,
DebugLoc dl, SelectionDAG &DAG,
const CCValAssign &VA, MachineFrameInfo *MFI,
@@ -594,13 +595,13 @@ namespace llvm {
ISD::ArgFlagsTy Flags);
// Call lowering helpers.
- bool IsCalleePop(bool isVarArg, unsigned CallConv);
+ bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv);
SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
SDValue Chain, bool IsTailCall, bool Is64Bit,
int FPDiff, DebugLoc dl);
- CCAssignFn *CCAssignFnForNode(unsigned CallConv) const;
- NameDecorationStyle NameDecorationForCallConv(unsigned CallConv);
+ CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const;
+ NameDecorationStyle NameDecorationForCallConv(CallingConv::ID CallConv);
unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
@@ -659,13 +660,13 @@ namespace llvm {
virtual SDValue
LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
virtual SDValue
LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg, bool isTailCall,
+ CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -673,7 +674,7 @@ namespace llvm {
virtual SDValue
LowerReturn(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG);
@@ -695,15 +696,15 @@ namespace llvm {
/// Utility function to emit string processing sse4.2 instructions
/// that return in xmm0.
- // This takes the instruction to expand, the associated machine basic
- // block, the number of args, and whether or not the second arg is
- // in memory or not.
+ /// This takes the instruction to expand, the associated machine basic
+ /// block, the number of args, and whether or not the second arg is
+ /// in memory or not.
MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
unsigned argNum, bool inMem) const;
/// Utility function to emit atomic bitwise operations (and, or, xor).
- // It takes the bitwise instruction to expand, the associated machine basic
- // block, and the associated X86 opcodes for reg/reg and reg/imm.
+ /// It takes the bitwise instruction to expand, the associated machine basic
+ /// block, and the associated X86 opcodes for reg/reg and reg/imm.
MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
MachineInstr *BInstr,
MachineBasicBlock *BB,
@@ -738,6 +739,10 @@ namespace llvm {
MachineInstr *BInstr,
MachineBasicBlock *BB) const;
+ MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
+ MachineBasicBlock *BB,
+ DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
+
/// Emit nodes that will be selected as "test Op0,Op0", or something
/// equivalent, for use with the given x86 condition code.
SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG);
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86Instr64bit.td b/libclamav/c++/llvm/lib/Target/X86/X86Instr64bit.td
index 00dfc04..ef19823 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86Instr64bit.td
+++ b/libclamav/c++/llvm/lib/Target/X86/X86Instr64bit.td
@@ -139,6 +139,9 @@ let isCall = 1 in
def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
"call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
Requires<[NotWin64]>;
+
+ def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
+ "lcall{q}\t{*}$dst", []>;
}
// FIXME: We need to teach codegen about single list of call-clobbered registers.
@@ -189,6 +192,8 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
[(brind GR64:$dst)]>;
def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
[(brind (loadi64 addr:$dst))]>;
+ def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
+ "ljmp{q}\t{*}$dst", []>;
}
//===----------------------------------------------------------------------===//
@@ -209,12 +214,18 @@ let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
def LEAVE64 : I<0xC9, RawFrm,
(outs), (ins), "leave", []>;
let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
-let mayLoad = 1 in
+let mayLoad = 1 in {
def POP64r : I<0x58, AddRegFrm,
(outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
-let mayStore = 1 in
+def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
+def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
+}
+let mayStore = 1 in {
def PUSH64r : I<0x50, AddRegFrm,
(outs), (ins GR64:$reg), "push{q}\t$reg", []>;
+def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
+def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
+}
}
let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
@@ -273,6 +284,10 @@ let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
[(X86rep_stos i64)]>, REP;
+def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
+
+def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
+
// Fast system-call instructions
def SYSEXIT64 : RI<0x35, RawFrm,
(outs), (ins), "sysexit", []>, TB;
@@ -306,6 +321,25 @@ def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
"mov{q}\t{$src, $dst|$dst, $src}",
[(store i64immSExt32:$src, addr:$dst)]>;
+def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins i8imm:$src),
+ "mov{q}\t{$src, %rax|%rax, $src}", []>;
+def MOV64o32a : RIi32<0xA1, RawFrm, (outs), (ins i32imm:$src),
+ "mov{q}\t{$src, %rax|%rax, $src}", []>;
+def MOV64ao8 : RIi8<0xA2, RawFrm, (outs i8imm:$dst), (ins),
+ "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
+def MOV64ao32 : RIi32<0xA3, RawFrm, (outs i32imm:$dst), (ins),
+ "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
+
+// Moves to and from segment registers
+def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>;
+def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>;
+def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>;
+def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>;
+
// Sign/Zero extenders
// MOVSX64rr8 always has a REX prefix and it has an 8-bit register
@@ -363,13 +397,15 @@ def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
[(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
// Any instruction that defines a 32-bit result leaves the high half of the
-// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
-// be copying from a truncate, but any other 32-bit operation will zero-extend
+// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
+// be copying from a truncate. And x86's cmov doesn't do anything if the
+// condition is false. But any other 32-bit operation will zero-extend
// up to 64 bits.
def def32 : PatLeaf<(i32 GR32:$src), [{
return N->getOpcode() != ISD::TRUNCATE &&
N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
- N->getOpcode() != ISD::CopyFromReg;
+ N->getOpcode() != ISD::CopyFromReg &&
+ N->getOpcode() != X86ISD::CMOV;
}]>;
// In the case of a 32-bit def that is known to implicitly zero-extend,
@@ -392,6 +428,10 @@ let neverHasSideEffects = 1 in {
//
let Defs = [EFLAGS] in {
+
+def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
+ "add{q}\t{$src, %rax|%rax, $src}", []>;
+
let isTwoAddress = 1 in {
let isConvertibleToThreeAddress = 1 in {
let isCommutable = 1 in
@@ -417,6 +457,12 @@ def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:
"add{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
(implicit EFLAGS)]>;
+
+// Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
+// differently encoded.
+def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
+ "add{l}\t{$src2, $dst|$dst, $src2}", []>;
+
} // isTwoAddress
// Memory-Register Addition
@@ -434,6 +480,10 @@ def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
(implicit EFLAGS)]>;
let Uses = [EFLAGS] in {
+
+def ADC64i32 : RI<0x15, RawFrm, (outs), (ins i32imm:$src),
+ "adc{q}\t{$src, %rax|%rax, $src}", []>;
+
let isTwoAddress = 1 in {
let isCommutable = 1 in
def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
@@ -489,6 +539,9 @@ def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
(implicit EFLAGS)]>;
} // isTwoAddress
+def SUB64i32 : RI<0x2D, RawFrm, (outs), (ins i32imm:$src),
+ "sub{q}\t{$src, %rax|%rax, $src}", []>;
+
// Memory-Register Subtraction
def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
"sub{q}\t{$src2, $dst|$dst, $src2}",
@@ -525,6 +578,9 @@ def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:
[(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
} // isTwoAddress
+def SBB64i32 : RI<0x1D, RawFrm, (outs), (ins i32imm:$src),
+ "sbb{q}\t{$src, %rax|%rax, $src}", []>;
+
def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
"sbb{q}\t{$src2, $dst|$dst, $src2}",
[(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
@@ -696,8 +752,10 @@ let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
"shl{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
-// NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
-// cheaper.
+// NOTE: We don't include patterns for shifts of a register by one, because
+// 'add reg,reg' is cheaper.
+def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
+ "shr{q}\t$dst", []>;
} // isTwoAddress
let Uses = [CL] in
@@ -760,6 +818,39 @@ def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
[(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
// Rotate instructions
+
+let isTwoAddress = 1 in {
+def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
+ "rcl{q}\t{1, $dst|$dst, 1}", []>;
+def RCL64m1 : RI<0xD1, MRM2m, (outs i64mem:$dst), (ins i64mem:$src),
+ "rcl{q}\t{1, $dst|$dst, 1}", []>;
+let Uses = [CL] in {
+def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
+ "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
+def RCL64mCL : RI<0xD3, MRM2m, (outs i64mem:$dst), (ins i64mem:$src),
+ "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
+}
+def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
+ "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
+def RCL64mi : RIi8<0xC1, MRM2m, (outs i64mem:$dst), (ins i64mem:$src, i8imm:$cnt),
+ "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
+
+def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
+ "rcr{q}\t{1, $dst|$dst, 1}", []>;
+def RCR64m1 : RI<0xD1, MRM3m, (outs i64mem:$dst), (ins i64mem:$src),
+ "rcr{q}\t{1, $dst|$dst, 1}", []>;
+let Uses = [CL] in {
+def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
+ "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
+def RCR64mCL : RI<0xD3, MRM3m, (outs i64mem:$dst), (ins i64mem:$src),
+ "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
+}
+def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
+ "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
+def RCR64mi : RIi8<0xC1, MRM3m, (outs i64mem:$dst), (ins i64mem:$src, i8imm:$cnt),
+ "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
+}
+
let isTwoAddress = 1 in {
let Uses = [CL] in
def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
@@ -870,6 +961,9 @@ def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
[(store (not (loadi64 addr:$dst)), addr:$dst)]>;
let Defs = [EFLAGS] in {
+def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
+ "and{q}\t{$src, %rax|%rax, $src}", []>;
+
let isTwoAddress = 1 in {
let isCommutable = 1 in
def AND64rr : RI<0x21, MRMDestReg,
@@ -943,6 +1037,9 @@ def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
[(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
(implicit EFLAGS)]>;
+def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
+ "or{q}\t{$src, %rax|%rax, $src}", []>;
+
let isTwoAddress = 1 in {
let isCommutable = 1 in
def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
@@ -976,6 +1073,10 @@ def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
"xor{q}\t{$src, $dst|$dst, $src}",
[(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
(implicit EFLAGS)]>;
+
+def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
+ "xor{q}\t{$src, %rax|%rax, $src}", []>;
+
} // Defs = [EFLAGS]
//===----------------------------------------------------------------------===//
@@ -984,6 +1085,8 @@ def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
// Integer comparison
let Defs = [EFLAGS] in {
+def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
+ "test{q}\t{$src, %rax|%rax, $src}", []>;
let isCommutable = 1 in
def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
"test{q}\t{$src2, $src1|$src1, $src2}",
@@ -1004,10 +1107,15 @@ def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
[(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
(implicit EFLAGS)]>;
+
+def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
+ "cmp{q}\t{$src, %rax|%rax, $src}", []>;
def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
"cmp{q}\t{$src2, $src1|$src1, $src2}",
[(X86cmp GR64:$src1, GR64:$src2),
(implicit EFLAGS)]>;
+def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
+ "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
"cmp{q}\t{$src2, $src1|$src1, $src2}",
[(X86cmp (loadi64 addr:$src1), GR64:$src2),
@@ -1466,6 +1574,18 @@ def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
[(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
}
+// Segmentation support instructions
+
+// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
+def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
+ "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
+def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
+ "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
+
+// String manipulation instructions
+
+def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
+
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
@@ -1962,6 +2082,102 @@ def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
(implicit EFLAGS)),
(DEC64m addr:$dst)>;
+// Register-Register Logical Or with EFLAGS result
+def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
+ (implicit EFLAGS)),
+ (OR64rr GR64:$src1, GR64:$src2)>;
+
+// Register-Integer Logical Or with EFLAGS result
+def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
+ (implicit EFLAGS)),
+ (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
+def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
+ (implicit EFLAGS)),
+ (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
+
+// Register-Memory Logical Or with EFLAGS result
+def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
+ (implicit EFLAGS)),
+ (OR64rm GR64:$src1, addr:$src2)>;
+
+// Memory-Register Logical Or with EFLAGS result
+def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (OR64mr addr:$dst, GR64:$src2)>;
+def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (OR64mi8 addr:$dst, i64immSExt8:$src2)>;
+def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (OR64mi32 addr:$dst, i64immSExt32:$src2)>;
+
+// Register-Register Logical XOr with EFLAGS result
+def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
+ (implicit EFLAGS)),
+ (XOR64rr GR64:$src1, GR64:$src2)>;
+
+// Register-Integer Logical XOr with EFLAGS result
+def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
+ (implicit EFLAGS)),
+ (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
+def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
+ (implicit EFLAGS)),
+ (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
+
+// Register-Memory Logical XOr with EFLAGS result
+def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
+ (implicit EFLAGS)),
+ (XOR64rm GR64:$src1, addr:$src2)>;
+
+// Memory-Register Logical XOr with EFLAGS result
+def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (XOR64mr addr:$dst, GR64:$src2)>;
+def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
+def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt32:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
+
+// Register-Register Logical And with EFLAGS result
+def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
+ (implicit EFLAGS)),
+ (AND64rr GR64:$src1, GR64:$src2)>;
+
+// Register-Integer Logical And with EFLAGS result
+def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
+ (implicit EFLAGS)),
+ (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
+def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
+ (implicit EFLAGS)),
+ (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
+
+// Register-Memory Logical And with EFLAGS result
+def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
+ (implicit EFLAGS)),
+ (AND64rm GR64:$src1, addr:$src2)>;
+
+// Memory-Register Logical And with EFLAGS result
+def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (AND64mr addr:$dst, GR64:$src2)>;
+def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (AND64mi8 addr:$dst, i64immSExt8:$src2)>;
+def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt32:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (AND64mi32 addr:$dst, i64immSExt32:$src2)>;
+
//===----------------------------------------------------------------------===//
// X86-64 SSE Instructions
//===----------------------------------------------------------------------===//
@@ -2033,3 +2249,15 @@ let isTwoAddress = 1 in {
}
defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
+
+// -disable-16bit support.
+def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
+ (MOV16mi addr:$dst, imm:$src)>;
+def : Pat<(truncstorei16 GR64:$src, addr:$dst),
+ (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
+def : Pat<(i64 (sextloadi16 addr:$dst)),
+ (MOVSX64rm16 addr:$dst)>;
+def : Pat<(i64 (zextloadi16 addr:$dst)),
+ (MOVZX64rm16 addr:$dst)>;
+def : Pat<(i64 (extloadi16 addr:$dst)),
+ (MOVZX64rm16 addr:$dst)>;
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86InstrBuilder.h b/libclamav/c++/llvm/lib/Target/X86/X86InstrBuilder.h
index bbcc32c..c475b56 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86InstrBuilder.h
+++ b/libclamav/c++/llvm/lib/Target/X86/X86InstrBuilder.h
@@ -26,6 +26,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
namespace llvm {
@@ -47,7 +48,7 @@ struct X86AddressMode {
unsigned Scale;
unsigned IndexReg;
- unsigned Disp;
+ int Disp;
GlobalValue *GV;
unsigned GVOpFlags;
@@ -142,11 +143,11 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
Flags |= MachineMemOperand::MOLoad;
if (TID.mayStore())
Flags |= MachineMemOperand::MOStore;
- MachineMemOperand MMO(PseudoSourceValue::getFixedStack(FI),
- Flags,
- MFI.getObjectOffset(FI) + Offset,
- MFI.getObjectSize(FI),
- MFI.getObjectAlignment(FI));
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
+ Flags, Offset,
+ MFI.getObjectSize(FI),
+ MFI.getObjectAlignment(FI));
return addOffset(MIB.addFrameIndex(FI), Offset)
.addMemOperand(MMO);
}
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86InstrFPStack.td b/libclamav/c++/llvm/lib/Target/X86/X86InstrFPStack.td
index bc7def4..7e37373 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86InstrFPStack.td
+++ b/libclamav/c++/llvm/lib/Target/X86/X86InstrFPStack.td
@@ -303,6 +303,31 @@ def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
}
def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
+// Versions of FP instructions that take a single memory operand. Added for the
+// disassembler; remove as they are included with patterns elsewhere.
+def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom\t$src">;
+def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp\t$src">;
+
+def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
+def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fstenv\t$dst">;
+
+def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;
+def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
+
+def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom\t$src">;
+def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp\t$src">;
+
+def FISTTP32m: FPI<0xDD, MRM1m, (outs i32mem:$dst), (ins), "fisttp{l}\t$dst">;
+def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">;
+def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fsave\t$dst">;
+def FSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fstsw\t$dst">;
+
+def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{w}\t$src">;
+def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{w}\t$src">;
+
+def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">;
+def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">;
+
// Floating point cmovs.
multiclass FPCMov<PatLeaf cc> {
def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86InstrFormats.td b/libclamav/c++/llvm/lib/Target/X86/X86InstrFormats.td
index ddc8654..abdb313 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86InstrFormats.td
+++ b/libclamav/c++/llvm/lib/Target/X86/X86InstrFormats.td
@@ -143,6 +143,24 @@ class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
let Pattern = pattern;
}
+// Templates for instructions that use a 16- or 32-bit segmented address as
+// their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
+//
+// Iseg16 - 16-bit segment selector, 16-bit offset
+// Iseg32 - 16-bit segment selector, 32-bit offset
+
+class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
+ list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
+ let Pattern = pattern;
+ let CodeSize = 3;
+}
+
+class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
+ list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
+ let Pattern = pattern;
+ let CodeSize = 3;
+}
+
// SSE1 Instruction Templates:
//
// SSI - SSE1 instructions with XS prefix.
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.cpp b/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.cpp
index c52a909..363674b 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -2162,7 +2162,7 @@ MachineInstr*
X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI, unsigned i,
const SmallVectorImpl<MachineOperand> &MOs,
- unsigned Align) const {
+ unsigned Size, unsigned Align) const {
const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
bool isTwoAddrFold = false;
unsigned NumOps = MI->getDesc().getNumOperands();
@@ -2202,13 +2202,44 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
OpcodeTablePtr->find((unsigned*)MI->getOpcode());
if (I != OpcodeTablePtr->end()) {
+ unsigned Opcode = I->second.first;
unsigned MinAlign = I->second.second;
if (Align < MinAlign)
return NULL;
+ bool NarrowToMOV32rm = false;
+ if (Size) {
+ unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
+ if (Size < RCSize) {
+ // Check if it's safe to fold the load. If the size of the object is
+ // narrower than the load width, then it's not.
+ if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
+ return NULL;
+ // If this is a 64-bit load, but the spill slot is 32, then we can do
+ // a 32-bit load which is implicitly zero-extended. This likely is due
+ // to liveintervalanalysis remat'ing a load from stack slot.
+ if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
+ return NULL;
+ Opcode = X86::MOV32rm;
+ NarrowToMOV32rm = true;
+ }
+ }
+
if (isTwoAddrFold)
- NewMI = FuseTwoAddrInst(MF, I->second.first, MOs, MI, *this);
+ NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
else
- NewMI = FuseInst(MF, I->second.first, i, MOs, MI, *this);
+ NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
+
+ if (NarrowToMOV32rm) {
+ // If this is the special case where we use a MOV32rm to load a 32-bit
+ // value and zero-extend the top bits. Change the destination register
+ // to a 32-bit one.
+ unsigned DstReg = NewMI->getOperand(0).getReg();
+ if (TargetRegisterInfo::isPhysicalRegister(DstReg))
+ NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
+ 4/*x86_subreg_32bit*/));
+ else
+ NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
+ }
return NewMI;
}
}
@@ -2228,16 +2259,22 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
if (NoFusing) return NULL;
const MachineFrameInfo *MFI = MF.getFrameInfo();
+ unsigned Size = MFI->getObjectSize(FrameIndex);
unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
unsigned NewOpc = 0;
+ unsigned RCSize = 0;
switch (MI->getOpcode()) {
default: return NULL;
- case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
- case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
- case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
- case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
+ case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
+ case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
+ case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
+ case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
}
+ // Check if it's safe to fold the load. If the size of the object is
+ // narrower than the load width, then it's not.
+ if (Size < RCSize)
+ return NULL;
// Change to CMPXXri r, 0 first.
MI->setDesc(get(NewOpc));
MI->getOperand(1).ChangeToImmediate(0);
@@ -2246,7 +2283,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
SmallVector<MachineOperand,4> MOs;
MOs.push_back(MachineOperand::CreateFI(FrameIndex));
- return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Alignment);
+ return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
}
MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
@@ -2259,10 +2296,22 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
// Determine the alignment of the load.
unsigned Alignment = 0;
if (LoadMI->hasOneMemOperand())
- Alignment = LoadMI->memoperands_begin()->getAlignment();
- else if (LoadMI->getOpcode() == X86::V_SET0 ||
- LoadMI->getOpcode() == X86::V_SETALLONES)
- Alignment = 16;
+ Alignment = (*LoadMI->memoperands_begin())->getAlignment();
+ else
+ switch (LoadMI->getOpcode()) {
+ case X86::V_SET0:
+ case X86::V_SETALLONES:
+ Alignment = 16;
+ break;
+ case X86::FsFLD0SD:
+ Alignment = 8;
+ break;
+ case X86::FsFLD0SS:
+ Alignment = 4;
+ break;
+ default:
+ llvm_unreachable("Don't know how to fold this instruction!");
+ }
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
unsigned NewOpc = 0;
switch (MI->getOpcode()) {
@@ -2279,8 +2328,11 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
return NULL;
SmallVector<MachineOperand,X86AddrNumOperands> MOs;
- if (LoadMI->getOpcode() == X86::V_SET0 ||
- LoadMI->getOpcode() == X86::V_SETALLONES) {
+ switch (LoadMI->getOpcode()) {
+ case X86::V_SET0:
+ case X86::V_SETALLONES:
+ case X86::FsFLD0SD:
+ case X86::FsFLD0SS: {
// Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
// Create a constant-pool entry and operands to load from it.
@@ -2294,17 +2346,22 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
// This doesn't work for several reasons.
// 1. GlobalBaseReg may have been spilled.
// 2. It may not be live at MI.
- return false;
+ return NULL;
}
- // Create a v4i32 constant-pool entry.
+ // Create a constant-pool entry.
MachineConstantPool &MCP = *MF.getConstantPool();
- const VectorType *Ty =
- VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
- Constant *C = LoadMI->getOpcode() == X86::V_SET0 ?
- Constant::getNullValue(Ty) :
- Constant::getAllOnesValue(Ty);
- unsigned CPI = MCP.getConstantPoolIndex(C, 16);
+ const Type *Ty;
+ if (LoadMI->getOpcode() == X86::FsFLD0SS)
+ Ty = Type::getFloatTy(MF.getFunction()->getContext());
+ else if (LoadMI->getOpcode() == X86::FsFLD0SD)
+ Ty = Type::getDoubleTy(MF.getFunction()->getContext());
+ else
+ Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
+ Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
+ Constant::getAllOnesValue(Ty) :
+ Constant::getNullValue(Ty);
+ unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
// Create operands to load from the constant pool entry.
MOs.push_back(MachineOperand::CreateReg(PICBase, false));
@@ -2312,13 +2369,17 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MOs.push_back(MachineOperand::CreateReg(0, false));
MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
MOs.push_back(MachineOperand::CreateReg(0, false));
- } else {
+ break;
+ }
+ default: {
// Folding a normal load. Just copy the load's address operands.
unsigned NumOps = LoadMI->getDesc().getNumOperands();
for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
MOs.push_back(LoadMI->getOperand(i));
+ break;
+ }
}
- return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Alignment);
+ return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
}
@@ -2525,8 +2586,8 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
EVT VT = *RC->vt_begin();
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
- Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
- VT, MVT::Other, &AddrOps[0], AddrOps.size());
+ Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
+ VT, MVT::Other, &AddrOps[0], AddrOps.size());
NewNodes.push_back(Load);
}
@@ -2545,8 +2606,8 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
if (Load)
BeforeOps.push_back(SDValue(Load, 0));
std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
- SDNode *NewNode= DAG.getTargetNode(Opc, dl, VTs, &BeforeOps[0],
- BeforeOps.size());
+ SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
+ BeforeOps.size());
NewNodes.push_back(NewNode);
// Emit the store instruction.
@@ -2556,10 +2617,10 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
AddrOps.push_back(Chain);
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
- SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC,
- isAligned, TM),
- dl, MVT::Other,
- &AddrOps[0], AddrOps.size());
+ SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
+ isAligned, TM),
+ dl, MVT::Other,
+ &AddrOps[0], AddrOps.size());
NewNodes.push_back(Store);
}
@@ -3000,6 +3061,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
case TargetInstrInfo::EH_LABEL:
break;
case TargetInstrInfo::IMPLICIT_DEF:
+ case TargetInstrInfo::KILL:
case X86::DWARF_LOC:
case X86::FP_REG_KILL:
break;
@@ -3237,7 +3299,7 @@ unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
// Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
- .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 0,
+ .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
X86II::MO_GOT_ABSOLUTE_ADDRESS);
} else {
GlobalBaseReg = PC;
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.h b/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.h
index 2e0235a..aff3603 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.h
@@ -170,16 +170,11 @@ namespace X86II {
/// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
MO_DARWIN_NONLAZY_PIC_BASE = 15,
- /// MO_DARWIN_HIDDEN_NONLAZY - On a symbol operand "FOO", this indicates
- /// that the reference is actually to the "FOO$non_lazy_ptr" symbol, which
- /// is a non-PIC-base-relative reference to a hidden dyld lazy pointer stub.
- MO_DARWIN_HIDDEN_NONLAZY = 16,
-
/// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
/// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
/// which is a PIC-base-relative reference to a hidden dyld lazy pointer
/// stub.
- MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE = 17
+ MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE = 16
};
}
@@ -193,7 +188,6 @@ inline static bool isGlobalStubReference(unsigned char TargetFlag) {
case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
- case X86II::MO_DARWIN_HIDDEN_NONLAZY: // Hidden $non_lazy_ptr ref.
return true;
default:
return false;
@@ -609,7 +603,7 @@ private:
MachineInstr* MI,
unsigned OpNum,
const SmallVectorImpl<MachineOperand> &MOs,
- unsigned Alignment) const;
+ unsigned Size, unsigned Alignment) const;
};
} // End llvm namespace
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.td b/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.td
index 056335f..30b57d8 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.td
@@ -162,6 +162,9 @@ def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
+def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags>;
+def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags>;
+def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags>;
def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
@@ -189,17 +192,21 @@ class X86MemOperand<string printMethod> : Operand<iPTR> {
let ParserMatchClass = X86MemAsmOperand;
}
+def opaque32mem : X86MemOperand<"printopaquemem">;
+def opaque48mem : X86MemOperand<"printopaquemem">;
+def opaque80mem : X86MemOperand<"printopaquemem">;
+
def i8mem : X86MemOperand<"printi8mem">;
def i16mem : X86MemOperand<"printi16mem">;
def i32mem : X86MemOperand<"printi32mem">;
def i64mem : X86MemOperand<"printi64mem">;
def i128mem : X86MemOperand<"printi128mem">;
-def i256mem : X86MemOperand<"printi256mem">;
+//def i256mem : X86MemOperand<"printi256mem">;
def f32mem : X86MemOperand<"printf32mem">;
def f64mem : X86MemOperand<"printf64mem">;
def f80mem : X86MemOperand<"printf80mem">;
def f128mem : X86MemOperand<"printf128mem">;
-def f256mem : X86MemOperand<"printf256mem">;
+//def f256mem : X86MemOperand<"printf256mem">;
// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
// plain GR64, so that it doesn't potentially require a REX prefix.
@@ -219,10 +226,6 @@ def SSECC : Operand<i8> {
let PrintMethod = "printSSECC";
}
-def piclabel: Operand<i32> {
- let PrintMethod = "printPICLabel";
-}
-
def ImmSExt8AsmOperand : AsmOperandClass {
let Name = "ImmSExt8";
let SuperClass = ImmAsmOperand;
@@ -543,11 +546,12 @@ let neverHasSideEffects = 1 in {
def INT3 : I<0xcc, RawFrm, (outs), (ins), "int 3", []>;
def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
-// PIC base
+// PIC base construction. This expands to code that looks like this:
+// call $next_inst
+// popl %destreg"
let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
- def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
- "call\t$label\n\t"
- "pop{l}\t$reg", []>;
+ def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
+ "", []>;
//===----------------------------------------------------------------------===//
// Control Flow Instructions...
@@ -561,7 +565,11 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
[(X86retflag 0)]>;
def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
"ret\t$amt",
- [(X86retflag imm:$amt)]>;
+ [(X86retflag timm:$amt)]>;
+ def LRET : I <0xCB, RawFrm, (outs), (ins),
+ "lret", []>;
+ def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
+ "lret\t$amt", []>;
}
// All branches are RawFrm, Void, Branch, and Terminators
@@ -580,6 +588,18 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
[(brind GR32:$dst)]>;
def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
[(brind (loadi32 addr:$dst))]>;
+
+ def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
+ (ins i16imm:$seg, i16imm:$off),
+ "ljmp{w}\t$seg, $off", []>, OpSize;
+ def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
+ (ins i16imm:$seg, i32imm:$off),
+ "ljmp{l}\t$seg, $off", []>;
+
+ def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
+ "ljmp{w}\t{*}$dst", []>, OpSize;
+ def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
+ "ljmp{l}\t{*}$dst", []>;
}
// Conditional branches
@@ -640,6 +660,12 @@ def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
[(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
} // Uses = [EFLAGS]
+// Loop instructions
+
+def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>;
+def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>;
+def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>;
+
//===----------------------------------------------------------------------===//
// Call Instructions...
//
@@ -660,8 +686,25 @@ let isCall = 1 in
"call\t{*}$dst", [(X86call GR32:$dst)]>;
def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
"call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
+
+ def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
+ (ins i16imm:$seg, i16imm:$off),
+ "lcall{w}\t$seg, $off", []>, OpSize;
+ def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
+ (ins i16imm:$seg, i32imm:$off),
+ "lcall{l}\t$seg, $off", []>;
+
+ def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
+ "lcall{w}\t{*}$dst", []>, OpSize;
+ def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
+ "lcall{l}\t{*}$dst", []>;
}
+// Constructing a stack frame.
+
+def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
+ "enter\t$len, $lvl", []>;
+
// Tail call stuff.
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
@@ -693,11 +736,29 @@ def LEAVE : I<0xC9, RawFrm,
(outs), (ins), "leave", []>;
let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
-let mayLoad = 1 in
-def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
+let mayLoad = 1 in {
+def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
+ OpSize;
+def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
+def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
+ OpSize;
+def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
+ OpSize;
+def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
+def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
+}
-let mayStore = 1 in
+let mayStore = 1 in {
+def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
+ OpSize;
def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
+def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
+ OpSize;
+def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
+ OpSize;
+def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
+def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
+}
}
let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
@@ -783,6 +844,14 @@ let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
[(X86rep_stos i32)]>, REP;
+def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
+def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
+def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
+
+def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
+def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
+def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
+
let Defs = [RAX, RDX] in
def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
TB;
@@ -800,6 +869,7 @@ def SYSENTER : I<0x34, RawFrm,
def SYSEXIT : I<0x35, RawFrm,
(outs), (ins), "sysexit", []>, TB;
+def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
//===----------------------------------------------------------------------===//
@@ -877,6 +947,30 @@ def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
"mov{l}\t{$src, $dst|$dst, $src}",
[(store (i32 imm:$src), addr:$dst)]>;
+def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins i8imm:$src),
+ "mov{b}\t{$src, %al|%al, $src}", []>;
+def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins i16imm:$src),
+ "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins i32imm:$src),
+ "mov{l}\t{$src, %eax|%eax, $src}", []>;
+
+def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs i8imm:$dst), (ins),
+ "mov{b}\t{%al, $dst|$dst, %al}", []>;
+def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs i16imm:$dst), (ins),
+ "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
+def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs i32imm:$dst), (ins),
+ "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
+
+// Moves to and from segment registers
+def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>;
+def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>;
+def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>;
+def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>;
+
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
"mov{b}\t{$src, $dst|$dst, $src}",
@@ -1647,6 +1741,14 @@ let isTwoAddress = 0 in {
"and{l}\t{$src, $dst|$dst, $src}",
[(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
(implicit EFLAGS)]>;
+
+ def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
+ "and{b}\t{$src, %al|%al, $src}", []>;
+ def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
+ "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+ def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
+ "and{l}\t{$src, %eax|%eax, $src}", []>;
+
}
@@ -1733,6 +1835,13 @@ let isTwoAddress = 0 in {
"or{l}\t{$src, $dst|$dst, $src}",
[(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
(implicit EFLAGS)]>;
+
+ def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
+ "or{b}\t{$src, %al|%al, $src}", []>;
+ def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
+ "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+ def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
+ "or{l}\t{$src, %eax|%eax, $src}", []>;
} // isTwoAddress = 0
@@ -1842,6 +1951,13 @@ let isTwoAddress = 0 in {
"xor{l}\t{$src, $dst|$dst, $src}",
[(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
(implicit EFLAGS)]>;
+
+ def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
+ "xor{b}\t{$src, %al|%al, $src}", []>;
+ def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
+ "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+ def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
+ "xor{l}\t{$src, %eax|%eax, $src}", []>;
} // isTwoAddress = 0
} // Defs = [EFLAGS]
@@ -1869,8 +1985,17 @@ def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
"shl{l}\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
-// NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
-// cheaper.
+
+// NOTE: We don't include patterns for shifts of a register by one, because
+// 'add reg,reg' is cheaper.
+
+def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
+ "shl{b}\t$dst", []>;
+def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
+ "shl{w}\t$dst", []>, OpSize;
+def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
+ "shl{l}\t$dst", []>;
+
} // isConvertibleToThreeAddress = 1
let isTwoAddress = 0 in {
@@ -2049,6 +2174,97 @@ let isTwoAddress = 0 in {
}
// Rotate instructions
+
+def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
+ "rcl{b}\t{1, $dst|$dst, 1}", []>;
+def RCL8m1 : I<0xD0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
+ "rcl{b}\t{1, $dst|$dst, 1}", []>;
+let Uses = [CL] in {
+def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
+ "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
+def RCL8mCL : I<0xD2, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
+ "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
+}
+def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
+ "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
+def RCL8mi : Ii8<0xC0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
+ "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
+
+def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
+ "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
+def RCL16m1 : I<0xD1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
+ "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
+let Uses = [CL] in {
+def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
+ "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
+def RCL16mCL : I<0xD3, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
+ "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
+}
+def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
+ "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
+def RCL16mi : Ii8<0xC1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src, i8imm:$cnt),
+ "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
+
+def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
+ "rcl{l}\t{1, $dst|$dst, 1}", []>;
+def RCL32m1 : I<0xD1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
+ "rcl{l}\t{1, $dst|$dst, 1}", []>;
+let Uses = [CL] in {
+def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
+ "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
+def RCL32mCL : I<0xD3, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
+ "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
+}
+def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
+ "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
+def RCL32mi : Ii8<0xC1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src, i8imm:$cnt),
+ "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
+
+def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
+ "rcr{b}\t{1, $dst|$dst, 1}", []>;
+def RCR8m1 : I<0xD0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
+ "rcr{b}\t{1, $dst|$dst, 1}", []>;
+let Uses = [CL] in {
+def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
+ "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
+def RCR8mCL : I<0xD2, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
+ "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
+}
+def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
+ "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
+def RCR8mi : Ii8<0xC0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
+ "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
+
+def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
+ "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
+def RCR16m1 : I<0xD1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
+ "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
+let Uses = [CL] in {
+def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
+ "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
+def RCR16mCL : I<0xD3, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
+ "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
+}
+def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
+ "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
+def RCR16mi : Ii8<0xC1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src, i8imm:$cnt),
+ "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
+
+def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
+ "rcr{l}\t{1, $dst|$dst, 1}", []>;
+def RCR32m1 : I<0xD1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
+ "rcr{l}\t{1, $dst|$dst, 1}", []>;
+let Uses = [CL] in {
+def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
+ "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
+def RCR32mCL : I<0xD3, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
+ "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
+}
+def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
+ "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
+def RCR32mi : Ii8<0xC1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src, i8imm:$cnt),
+ "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
+
// FIXME: provide shorter instructions when imm8 == 1
let Uses = [CL] in {
def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
@@ -2326,6 +2542,15 @@ def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
"add{l}\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
(implicit EFLAGS)]>;
+
+// Register-Register Addition - Equivalent to the normal rr forms (ADD8rr,
+// ADD16rr, and ADD32rr), but differently encoded.
+def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
+ "add{b}\t{$src2, $dst|$dst, $src2}", []>;
+def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
+ "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
+def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
+ "add{l}\t{$src2, $dst|$dst, $src2}", []>;
// Register-Integer Addition
def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
@@ -2396,11 +2621,11 @@ let isTwoAddress = 0 in {
// addition to rAX
def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
- "add\t{$src, %al|%al, $src}", []>;
+ "add{b}\t{$src, %al|%al, $src}", []>;
def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
- "add\t{$src, %ax|%ax, $src}", []>, OpSize;
+ "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
- "add\t{$src, %eax|%eax, $src}", []>;
+ "add{l}\t{$src, %eax|%eax, $src}", []>;
}
let Uses = [EFLAGS] in {
@@ -2479,6 +2704,13 @@ let isTwoAddress = 0 in {
def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
"adc{l}\t{$src2, $dst|$dst, $src2}",
[(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
+
+ def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
+ "adc{b}\t{$src, %al|%al, $src}", []>;
+ def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
+ "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+ def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
+ "adc{l}\t{$src, %eax|%eax, $src}", []>;
}
} // Uses = [EFLAGS]
@@ -2578,6 +2810,13 @@ let isTwoAddress = 0 in {
[(store (sub (load addr:$dst), i32immSExt8:$src2),
addr:$dst),
(implicit EFLAGS)]>;
+
+ def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
+ "sub{b}\t{$src, %al|%al, $src}", []>;
+ def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
+ "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+ def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
+ "sub{l}\t{$src, %eax|%eax, $src}", []>;
}
let Uses = [EFLAGS] in {
@@ -2622,6 +2861,13 @@ let isTwoAddress = 0 in {
def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
"sbb{l}\t{$src2, $dst|$dst, $src2}",
[(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
+
+ def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
+ "sbb{b}\t{$src, %al|%al, $src}", []>;
+ def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
+ "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+ def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
+ "sbb{l}\t{$src, %eax|%eax, $src}", []>;
}
def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
"sbb{b}\t{$src2, $dst|$dst, $src2}",
@@ -2753,6 +2999,13 @@ def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
(implicit EFLAGS)]>;
}
+def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
+ "test{b}\t{$src, %al|%al, $src}", []>;
+def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
+ "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
+ "test{l}\t{$src, %eax|%eax, $src}", []>;
+
def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
"test{b}\t{$src2, $src1|$src1, $src2}",
[(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
@@ -2984,6 +3237,13 @@ def SETNOm : I<0x91, MRM0m,
// Integer comparisons
let Defs = [EFLAGS] in {
+def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
+ "cmp{b}\t{$src, %al|%al, $src}", []>;
+def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
+ "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
+ "cmp{l}\t{$src, %eax|%eax, $src}", []>;
+
def CMP8rr : I<0x38, MRMDestReg,
(outs), (ins GR8 :$src1, GR8 :$src2),
"cmp{b}\t{$src2, $src1|$src1, $src2}",
@@ -3026,6 +3286,12 @@ def CMP32rm : I<0x3B, MRMSrcMem,
"cmp{l}\t{$src2, $src1|$src1, $src2}",
[(X86cmp GR32:$src1, (loadi32 addr:$src2)),
(implicit EFLAGS)]>;
+def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
+ "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
+def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
+ "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
+def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
+ "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
def CMP8ri : Ii8<0x80, MRM7r,
(outs), (ins GR8:$src1, i8imm:$src2),
"cmp{b}\t{$src2, $src1|$src1, $src2}",
@@ -3497,6 +3763,25 @@ def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
"#ATOMSWAP6432 PSEUDO!", []>;
}
+// Segmentation support instructions.
+
+def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
+ "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
+def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
+ "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
+
+// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
+def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
+ "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
+def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
+ "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
+
+// String manipulation instructions
+
+def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
+def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
+def LODSD : I<0xAD, RawFrm, (outs), (ins), "lodsd", []>;
+
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
@@ -4133,6 +4418,243 @@ def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
(implicit EFLAGS)),
(DEC32m addr:$dst)>, Requires<[In32BitMode]>;
+// Register-Register Or with EFLAGS result
+def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
+ (implicit EFLAGS)),
+ (OR8rr GR8:$src1, GR8:$src2)>;
+def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
+ (implicit EFLAGS)),
+ (OR16rr GR16:$src1, GR16:$src2)>;
+def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
+ (implicit EFLAGS)),
+ (OR32rr GR32:$src1, GR32:$src2)>;
+
+// Register-Memory Or with EFLAGS result
+def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
+ (implicit EFLAGS)),
+ (OR8rm GR8:$src1, addr:$src2)>;
+def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
+ (implicit EFLAGS)),
+ (OR16rm GR16:$src1, addr:$src2)>;
+def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
+ (implicit EFLAGS)),
+ (OR32rm GR32:$src1, addr:$src2)>;
+
+// Register-Integer Or with EFLAGS result
+def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
+ (implicit EFLAGS)),
+ (OR8ri GR8:$src1, imm:$src2)>;
+def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
+ (implicit EFLAGS)),
+ (OR16ri GR16:$src1, imm:$src2)>;
+def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
+ (implicit EFLAGS)),
+ (OR32ri GR32:$src1, imm:$src2)>;
+def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
+ (implicit EFLAGS)),
+ (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
+def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
+ (implicit EFLAGS)),
+ (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
+
+// Memory-Register Or with EFLAGS result
+def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (OR8mr addr:$dst, GR8:$src2)>;
+def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (OR16mr addr:$dst, GR16:$src2)>;
+def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (OR32mr addr:$dst, GR32:$src2)>;
+
+// Memory-Integer Or with EFLAGS result
+def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (OR8mi addr:$dst, imm:$src2)>;
+def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (OR16mi addr:$dst, imm:$src2)>;
+def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (OR32mi addr:$dst, imm:$src2)>;
+def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
+def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
+
+// Register-Register XOr with EFLAGS result
+def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
+ (implicit EFLAGS)),
+ (XOR8rr GR8:$src1, GR8:$src2)>;
+def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
+ (implicit EFLAGS)),
+ (XOR16rr GR16:$src1, GR16:$src2)>;
+def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
+ (implicit EFLAGS)),
+ (XOR32rr GR32:$src1, GR32:$src2)>;
+
+// Register-Memory XOr with EFLAGS result
+def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
+ (implicit EFLAGS)),
+ (XOR8rm GR8:$src1, addr:$src2)>;
+def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
+ (implicit EFLAGS)),
+ (XOR16rm GR16:$src1, addr:$src2)>;
+def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
+ (implicit EFLAGS)),
+ (XOR32rm GR32:$src1, addr:$src2)>;
+
+// Register-Integer XOr with EFLAGS result
+def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
+ (implicit EFLAGS)),
+ (XOR8ri GR8:$src1, imm:$src2)>;
+def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
+ (implicit EFLAGS)),
+ (XOR16ri GR16:$src1, imm:$src2)>;
+def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
+ (implicit EFLAGS)),
+ (XOR32ri GR32:$src1, imm:$src2)>;
+def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
+ (implicit EFLAGS)),
+ (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
+def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
+ (implicit EFLAGS)),
+ (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
+
+// Memory-Register XOr with EFLAGS result
+def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (XOR8mr addr:$dst, GR8:$src2)>;
+def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (XOR16mr addr:$dst, GR16:$src2)>;
+def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (XOR32mr addr:$dst, GR32:$src2)>;
+
+// Memory-Integer XOr with EFLAGS result
+def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (XOR8mi addr:$dst, imm:$src2)>;
+def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (XOR16mi addr:$dst, imm:$src2)>;
+def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (XOR32mi addr:$dst, imm:$src2)>;
+def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
+def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
+
+// Register-Register And with EFLAGS result
+def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
+ (implicit EFLAGS)),
+ (AND8rr GR8:$src1, GR8:$src2)>;
+def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
+ (implicit EFLAGS)),
+ (AND16rr GR16:$src1, GR16:$src2)>;
+def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
+ (implicit EFLAGS)),
+ (AND32rr GR32:$src1, GR32:$src2)>;
+
+// Register-Memory And with EFLAGS result
+def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
+ (implicit EFLAGS)),
+ (AND8rm GR8:$src1, addr:$src2)>;
+def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
+ (implicit EFLAGS)),
+ (AND16rm GR16:$src1, addr:$src2)>;
+def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
+ (implicit EFLAGS)),
+ (AND32rm GR32:$src1, addr:$src2)>;
+
+// Register-Integer And with EFLAGS result
+def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
+ (implicit EFLAGS)),
+ (AND8ri GR8:$src1, imm:$src2)>;
+def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
+ (implicit EFLAGS)),
+ (AND16ri GR16:$src1, imm:$src2)>;
+def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
+ (implicit EFLAGS)),
+ (AND32ri GR32:$src1, imm:$src2)>;
+def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
+ (implicit EFLAGS)),
+ (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
+def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
+ (implicit EFLAGS)),
+ (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
+
+// Memory-Register And with EFLAGS result
+def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (AND8mr addr:$dst, GR8:$src2)>;
+def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (AND16mr addr:$dst, GR16:$src2)>;
+def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (AND32mr addr:$dst, GR32:$src2)>;
+
+// Memory-Integer And with EFLAGS result
+def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (AND8mi addr:$dst, imm:$src2)>;
+def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (AND16mi addr:$dst, imm:$src2)>;
+def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (AND32mi addr:$dst, imm:$src2)>;
+def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
+def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
+ addr:$dst),
+ (implicit EFLAGS)),
+ (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
+
+// -disable-16bit support.
+def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
+ (MOV16mi addr:$dst, imm:$src)>;
+def : Pat<(truncstorei16 GR32:$src, addr:$dst),
+ (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
+def : Pat<(i32 (sextloadi16 addr:$dst)),
+ (MOVSX32rm16 addr:$dst)>;
+def : Pat<(i32 (zextloadi16 addr:$dst)),
+ (MOVZX32rm16 addr:$dst)>;
+def : Pat<(i32 (extloadi16 addr:$dst)),
+ (MOVZX32rm16 addr:$dst)>;
+
//===----------------------------------------------------------------------===//
// Floating Point Stack Support
//===----------------------------------------------------------------------===//
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86InstrSSE.td b/libclamav/c++/llvm/lib/Target/X86/X86InstrSSE.td
index 7957767..96fc932 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/libclamav/c++/llvm/lib/Target/X86/X86InstrSSE.td
@@ -472,7 +472,8 @@ def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
// that start with 'Fs'.
// Alias instructions that map fld0 to pxor for sse.
-let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
+ canFoldAsLoad = 1 in
def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
"pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
Requires<[HasSSE1]>, TB, OpSize;
@@ -1096,6 +1097,27 @@ def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
"cvtsi2sd\t{$src, $dst|$dst, $src}",
[(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
+def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+ "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
+def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+ "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
+def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+ "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
+def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+ "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
+def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+ "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
+def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+ "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
+def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+ "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
+def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+ "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
+def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
+ "comisd\t{$src2, $src1|$src1, $src2}", []>;
+def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
+ "comisd\t{$src2, $src1|$src1, $src2}", []>;
+
// SSE2 instructions with XS prefix
def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
"cvtss2sd\t{$src, $dst|$dst, $src}",
@@ -1209,7 +1231,8 @@ def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
// that start with 'Fs'.
// Alias instructions that map fld0 to pxor for sse.
-let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
+ canFoldAsLoad = 1 in
def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
"pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
Requires<[HasSSE2]>, TB, OpSize;
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86JITInfo.cpp b/libclamav/c++/llvm/lib/Target/X86/X86JITInfo.cpp
index d36f87a..62ca47f 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86JITInfo.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/X86JITInfo.cpp
@@ -15,6 +15,7 @@
#include "X86JITInfo.h"
#include "X86Relocations.h"
#include "X86Subtarget.h"
+#include "X86TargetMachine.h"
#include "llvm/Function.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
@@ -51,13 +52,6 @@ static TargetJITInfo::JITCompilerFn JITCompilerFunction;
#define GETASMPREFIX(X) GETASMPREFIX2(X)
#define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__)
-// Check if building with -fPIC
-#if defined(__PIC__) && __PIC__ && defined(__linux__)
-#define ASMCALLSUFFIX "@PLT"
-#else
-#define ASMCALLSUFFIX
-#endif
-
// For ELF targets, use a .size and .type directive, to let tools
// know the extent of functions defined in assembler.
#if defined(__ELF__)
@@ -130,7 +124,7 @@ extern "C" {
// JIT callee
"movq %rbp, %rdi\n" // Pass prev frame and return address
"movq 8(%rbp), %rsi\n"
- "call " ASMPREFIX "X86CompilationCallback2" ASMCALLSUFFIX "\n"
+ "call " ASMPREFIX "X86CompilationCallback2\n"
// Restore all XMM arg registers
"movaps 112(%rsp), %xmm7\n"
"movaps 96(%rsp), %xmm6\n"
@@ -206,7 +200,7 @@ extern "C" {
"movl 4(%ebp), %eax\n" // Pass prev frame and return address
"movl %eax, 4(%esp)\n"
"movl %ebp, (%esp)\n"
- "call " ASMPREFIX "X86CompilationCallback2" ASMCALLSUFFIX "\n"
+ "call " ASMPREFIX "X86CompilationCallback2\n"
"movl %ebp, %esp\n" // Restore ESP
CFI(".cfi_def_cfa_register %esp\n")
"subl $12, %esp\n"
@@ -262,7 +256,7 @@ extern "C" {
"movl 4(%ebp), %eax\n" // Pass prev frame and return address
"movl %eax, 4(%esp)\n"
"movl %ebp, (%esp)\n"
- "call " ASMPREFIX "X86CompilationCallback2" ASMCALLSUFFIX "\n"
+ "call " ASMPREFIX "X86CompilationCallback2\n"
"addl $16, %esp\n"
"movaps 48(%esp), %xmm3\n"
CFI(".cfi_restore %xmm3\n")
@@ -330,14 +324,21 @@ extern "C" {
/// function stub when we did not know the real target of a call. This function
/// must locate the start of the stub or call site and pass it into the JIT
/// compiler function.
-extern "C" void ATTRIBUTE_USED
+extern "C" {
+#if !(defined (X86_64_JIT) && defined(_MSC_VER))
+ // the following function is called only from this translation unit,
+ // unless we are under 64bit Windows with MSC, where there is
+ // no support for inline assembly
+static
+#endif
+void ATTRIBUTE_USED
X86CompilationCallback2(intptr_t *StackPtr, intptr_t RetAddr) {
intptr_t *RetAddrLoc = &StackPtr[1];
assert(*RetAddrLoc == RetAddr &&
"Could not find return address on the stack!");
// It's a stub if there is an interrupt marker after the call.
- bool isStub = ((unsigned char*)RetAddr)[0] == 0xCD;
+ bool isStub = ((unsigned char*)RetAddr)[0] == 0xCE;
// The call instruction should have pushed the return value onto the stack...
#if defined (X86_64_JIT)
@@ -376,7 +377,7 @@ X86CompilationCallback2(intptr_t *StackPtr, intptr_t RetAddr) {
// If this is a stub, rewrite the call into an unconditional branch
// instruction so that two return addresses are not pushed onto the stack
// when the requested function finally gets called. This also makes the
- // 0xCD byte (interrupt) dead, so the marker doesn't effect anything.
+ // 0xCE byte (interrupt) dead, so the marker doesn't effect anything.
#if defined (X86_64_JIT)
// If the target address is within 32-bit range of the stub, use a
// PC-relative branch instead of loading the actual address. (This is
@@ -402,31 +403,26 @@ X86CompilationCallback2(intptr_t *StackPtr, intptr_t RetAddr) {
*RetAddrLoc -= 5;
#endif
}
+}
TargetJITInfo::LazyResolverFn
X86JITInfo::getLazyResolverFunction(JITCompilerFn F) {
JITCompilerFunction = F;
#if defined (X86_32_JIT) && !defined (_MSC_VER)
- unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
- union {
- unsigned u[3];
- char c[12];
- } text;
-
- if (!X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) {
- // FIXME: support for AMD family of processors.
- if (memcmp(text.c, "GenuineIntel", 12) == 0) {
- X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
- if ((EDX >> 25) & 0x1)
- return X86CompilationCallback_SSE;
- }
- }
+ if (Subtarget->hasSSE1())
+ return X86CompilationCallback_SSE;
#endif
return X86CompilationCallback;
}
+X86JITInfo::X86JITInfo(X86TargetMachine &tm) : TM(tm) {
+ Subtarget = &TM.getSubtarget<X86Subtarget>();
+ useGOT = 0;
+ TLSOffset = 0;
+}
+
void *X86JITInfo::emitGlobalValueIndirectSym(const GlobalValue* GV, void *ptr,
JITCodeEmitter &JCE) {
#if defined (X86_64_JIT)
@@ -484,7 +480,10 @@ void *X86JITInfo::emitFunctionStub(const Function* F, void *Fn,
JCE.emitWordLE((intptr_t)Fn-JCE.getCurrentPCValue()-4);
#endif
- JCE.emitByte(0xCD); // Interrupt - Just a marker identifying the stub!
+ // This used to use 0xCD, but that value is used by JITMemoryManager to
+ // initialize the buffer with garbage, which means it may follow a
+ // noreturn function call, confusing X86CompilationCallback2. PR 4929.
+ JCE.emitByte(0xCE); // Interrupt - Just a marker identifying the stub!
return JCE.finishGVStub(F);
}
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86JITInfo.h b/libclamav/c++/llvm/lib/Target/X86/X86JITInfo.h
index 6a4e214..c381433 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86JITInfo.h
+++ b/libclamav/c++/llvm/lib/Target/X86/X86JITInfo.h
@@ -20,16 +20,15 @@
namespace llvm {
class X86TargetMachine;
+ class X86Subtarget;
class X86JITInfo : public TargetJITInfo {
X86TargetMachine &TM;
+ const X86Subtarget *Subtarget;
uintptr_t PICBase;
char* TLSOffset;
public:
- explicit X86JITInfo(X86TargetMachine &tm) : TM(tm) {
- useGOT = 0;
- TLSOffset = 0;
- }
+ explicit X86JITInfo(X86TargetMachine &tm);
/// replaceMachineCodeForFunction - Make it so that calling the function
/// whose machine code is at OLD turns into a call to NEW, perhaps by
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86MCAsmInfo.cpp b/libclamav/c++/llvm/lib/Target/X86/X86MCAsmInfo.cpp
index eaa73e1..9d7e66d 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86MCAsmInfo.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/X86MCAsmInfo.cpp
@@ -57,14 +57,6 @@ X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &Triple) {
// Leopard and above support aligned common symbols.
COMMDirectiveTakesAlignment = Triple.getDarwinMajorNumber() >= 9;
- if (is64Bit) {
- PersonalityPrefix = "";
- PersonalitySuffix = "+4 at GOTPCREL";
- } else {
- PersonalityPrefix = "L";
- PersonalitySuffix = "$non_lazy_ptr";
- }
-
CommentString = "##";
PCSymbol = ".";
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86RegisterInfo.cpp b/libclamav/c++/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 5d1ee17..64bd97e 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -645,7 +645,7 @@ X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// }
// [EBP]
MFI->CreateFixedObject(-TailCallReturnAddrDelta,
- (-1*SlotSize)+TailCallReturnAddrDelta);
+ (-1U*SlotSize)+TailCallReturnAddrDelta);
}
if (hasFP(MF)) {
@@ -1086,12 +1086,12 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
}
- if (NumBytes && needsFrameMoves) {
+ if ((NumBytes || PushedRegs) && needsFrameMoves) {
// Mark end of stack pointer adjustment.
unsigned LabelId = MMI->NextLabelID();
BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
- if (!HasFP) {
+ if (!HasFP && NumBytes) {
// Define the current CFA rule to use the provided offset.
if (StackSize) {
MachineLocation SPDst(MachineLocation::VirtualFP);
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86RegisterInfo.td b/libclamav/c++/llvm/lib/Target/X86/X86RegisterInfo.td
index c6d58e9..469a3d8 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/libclamav/c++/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -440,6 +440,11 @@ def GR64 : RegisterClass<"X86", [i64], 64,
}];
}
+// Segment registers for use by MOV instructions (and others) that have a
+// segment register as one operand. Always contain a 16-bit segment
+// descriptor.
+def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]> {
+}
// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86Subtarget.cpp b/libclamav/c++/llvm/lib/Target/X86/X86Subtarget.cpp
index 7308728..fb76aeb 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86Subtarget.cpp
+++ b/libclamav/c++/llvm/lib/Target/X86/X86Subtarget.cpp
@@ -108,14 +108,7 @@ ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
// normal $non_lazy_ptr stub because this symbol might be resolved late.
if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
return X86II::MO_DARWIN_NONLAZY;
-
- // If symbol visibility is hidden, we have a stub for common symbol
- // references and external declarations.
- if (isDecl || GV->hasCommonLinkage()) {
- // Hidden $non_lazy_ptr reference.
- return X86II::MO_DARWIN_HIDDEN_NONLAZY;
- }
-
+
// Otherwise, no stub.
return X86II::MO_NO_FLAG;
}
@@ -158,8 +151,8 @@ unsigned X86Subtarget::getSpecialAddressLatency() const {
/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
/// specified arguments. If we can't run cpuid on the host, return true.
-bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
- unsigned *rECX, unsigned *rEDX) {
+static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
+ unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
#if defined(__GNUC__)
// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
@@ -230,18 +223,19 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
char c[12];
} text;
- if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
+ if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
return;
- X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
+ GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
- if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
- if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
- if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
- if (ECX & 0x1) X86SSELevel = SSE3;
- if ((ECX >> 9) & 0x1) X86SSELevel = SSSE3;
- if ((ECX >> 19) & 0x1) X86SSELevel = SSE41;
- if ((ECX >> 20) & 0x1) X86SSELevel = SSE42;
+ if ((EDX >> 15) & 1) HasCMov = true;
+ if ((EDX >> 23) & 1) X86SSELevel = MMX;
+ if ((EDX >> 25) & 1) X86SSELevel = SSE1;
+ if ((EDX >> 26) & 1) X86SSELevel = SSE2;
+ if (ECX & 0x1) X86SSELevel = SSE3;
+ if ((ECX >> 9) & 1) X86SSELevel = SSSE3;
+ if ((ECX >> 19) & 1) X86SSELevel = SSE41;
+ if ((ECX >> 20) & 1) X86SSELevel = SSE42;
bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
@@ -256,7 +250,7 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
DetectFamilyModel(EAX, Family, Model);
IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
- X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
+ GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
HasX86_64 = (EDX >> 29) & 0x1;
HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
@@ -265,13 +259,13 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
static const char *GetCurrentX86CPU() {
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
- if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
+ if (GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
return "generic";
unsigned Family = 0;
unsigned Model = 0;
DetectFamilyModel(EAX, Family, Model);
- X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
+ GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
bool Em64T = (EDX >> 29) & 0x1;
bool HasSSE3 = (ECX & 0x1);
@@ -280,7 +274,7 @@ static const char *GetCurrentX86CPU() {
char c[12];
} text;
- X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
+ GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
if (memcmp(text.c, "GenuineIntel", 12) == 0) {
switch (Family) {
case 3:
@@ -380,6 +374,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
: PICStyle(PICStyles::None)
, X86SSELevel(NoMMXSSE)
, X863DNowLevel(NoThreeDNow)
+ , HasCMov(false)
, HasX86_64(false)
, HasSSE4A(false)
, HasAVX(false)
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86Subtarget.h b/libclamav/c++/llvm/lib/Target/X86/X86Subtarget.h
index f5ca10a..a2e368d 100644
--- a/libclamav/c++/llvm/lib/Target/X86/X86Subtarget.h
+++ b/libclamav/c++/llvm/lib/Target/X86/X86Subtarget.h
@@ -55,6 +55,10 @@ protected:
///
X863DNowEnum X863DNowLevel;
+ /// HasCMov - True if this processor has conditional move instructions
+ /// (generally pentium pro+).
+ bool HasCMov;
+
/// HasX86_64 - True if the processor supports X86-64 instructions.
///
bool HasX86_64;
@@ -144,12 +148,20 @@ public:
bool isTargetDarwin() const { return TargetType == isDarwin; }
bool isTargetELF() const { return TargetType == isELF; }
+
bool isTargetWindows() const { return TargetType == isWindows; }
bool isTargetMingw() const { return TargetType == isMingw; }
+ bool isTargetCygwin() const { return TargetType == isCygwin; }
bool isTargetCygMing() const {
return TargetType == isMingw || TargetType == isCygwin;
}
- bool isTargetCygwin() const { return TargetType == isCygwin; }
+
+ /// isTargetCOFF - Return true if this is any COFF/Windows target variant.
+ bool isTargetCOFF() const {
+ return TargetType == isMingw || TargetType == isCygwin ||
+ TargetType == isWindows;
+ }
+
bool isTargetWin64() const {
return Is64Bit && (TargetType == isMingw || TargetType == isWindows);
}
@@ -212,13 +224,6 @@ public:
unsigned getSpecialAddressLatency() const;
};
-namespace X86 {
- /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in
- /// the specified arguments. If we can't run cpuid on the host, return true.
- bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
- unsigned *rECX, unsigned *rEDX);
-}
-
} // End llvm namespace
#endif
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86TargetObjectFile.cpp b/libclamav/c++/llvm/lib/Target/X86/X86TargetObjectFile.cpp
new file mode 100644
index 0000000..d39b3c4
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/X86/X86TargetObjectFile.cpp
@@ -0,0 +1,65 @@
+//===-- llvm/Target/X86/X86TargetObjectFile.cpp - X86 Object Info ---------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86TargetObjectFile.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/Support/Mangler.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/CodeGen/MachineModuleInfoImpls.h"
+using namespace llvm;
+
+const MCExpr *X8632_MachoTargetObjectFile::
+getSymbolForDwarfGlobalReference(const GlobalValue *GV, Mangler *Mang,
+ MachineModuleInfo *MMI,
+ bool &IsIndirect, bool &IsPCRel) const {
+ // The mach-o version of this method defaults to returning a stub reference.
+ IsIndirect = true;
+ IsPCRel = false;
+
+
+ MachineModuleInfoMachO &MachOMMI =
+ MMI->getObjFileInfo<MachineModuleInfoMachO>();
+
+ SmallString<128> Name;
+ Mang->getNameWithPrefix(Name, GV, true);
+ Name += "$non_lazy_ptr";
+
+ // Add information about the stub reference to MachOMMI so that the stub gets
+ // emitted by the asmprinter.
+ MCSymbol *Sym = getContext().GetOrCreateSymbol(Name.str());
+ const MCSymbol *&StubSym = MachOMMI.getGVStubEntry(Sym);
+ if (StubSym == 0) {
+ Name.clear();
+ Mang->getNameWithPrefix(Name, GV, false);
+ StubSym = getContext().GetOrCreateSymbol(Name.str());
+ }
+
+ return MCSymbolRefExpr::Create(Sym, getContext());
+}
+
+const MCExpr *X8664_MachoTargetObjectFile::
+getSymbolForDwarfGlobalReference(const GlobalValue *GV, Mangler *Mang,
+ MachineModuleInfo *MMI,
+ bool &IsIndirect, bool &IsPCRel) const {
+
+ // On Darwin/X86-64, we can reference dwarf symbols with foo at GOTPCREL+4, which
+ // is an indirect pc-relative reference.
+ IsIndirect = true;
+ IsPCRel = true;
+
+ SmallString<128> Name;
+ Mang->getNameWithPrefix(Name, GV, false);
+ Name += "@GOTPCREL";
+ const MCExpr *Res =
+ MCSymbolRefExpr::Create(Name.str(), getContext());
+ const MCExpr *Four = MCConstantExpr::Create(4, getContext());
+ return MCBinaryExpr::CreateAdd(Res, Four, getContext());
+}
+
diff --git a/libclamav/c++/llvm/lib/Target/X86/X86TargetObjectFile.h b/libclamav/c++/llvm/lib/Target/X86/X86TargetObjectFile.h
new file mode 100644
index 0000000..377a93b
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Target/X86/X86TargetObjectFile.h
@@ -0,0 +1,40 @@
+//===-- llvm/Target/X86/X86TargetObjectFile.h - X86 Object Info -*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TARGET_X86_TARGETOBJECTFILE_H
+#define LLVM_TARGET_X86_TARGETOBJECTFILE_H
+
+#include "llvm/Target/TargetLoweringObjectFile.h"
+
+namespace llvm {
+
+ /// X8632_MachoTargetObjectFile - This TLOF implementation is used for
+ /// Darwin/x86-32.
+ class X8632_MachoTargetObjectFile : public TargetLoweringObjectFileMachO {
+ public:
+
+ virtual const MCExpr *
+ getSymbolForDwarfGlobalReference(const GlobalValue *GV, Mangler *Mang,
+ MachineModuleInfo *MMI,
+ bool &IsIndirect, bool &IsPCRel) const;
+ };
+
+ /// X8664_MachoTargetObjectFile - This TLOF implementation is used for
+ /// Darwin/x86-64.
+ class X8664_MachoTargetObjectFile : public TargetLoweringObjectFileMachO {
+ public:
+
+ virtual const MCExpr *
+ getSymbolForDwarfGlobalReference(const GlobalValue *GV, Mangler *Mang,
+ MachineModuleInfo *MMI,
+ bool &IsIndirect, bool &IsPCRel) const;
+ };
+} // end namespace llvm
+
+#endif
diff --git a/libclamav/c++/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp b/libclamav/c++/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
index b1f7f04..5b91f3d 100644
--- a/libclamav/c++/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
@@ -589,7 +589,7 @@ CallGraphNode *ArgPromotion::DoPromotion(Function *F,
// Construct the new function type using the new arguments.
FunctionType *NFTy = FunctionType::get(RetTy, Params, FTy->isVarArg());
- // Create the new function body and insert it into the module...
+ // Create the new function body and insert it into the module.
Function *NF = Function::Create(NFTy, F->getLinkage(), F->getName());
NF->copyAttributesFrom(F);
@@ -599,7 +599,8 @@ CallGraphNode *ArgPromotion::DoPromotion(Function *F,
// Recompute the parameter attributes list based on the new arguments for
// the function.
- NF->setAttributes(AttrListPtr::get(AttributesVec.begin(), AttributesVec.end()));
+ NF->setAttributes(AttrListPtr::get(AttributesVec.begin(),
+ AttributesVec.end()));
AttributesVec.clear();
F->getParent()->getFunctionList().insert(F, NF);
@@ -728,7 +729,8 @@ CallGraphNode *ArgPromotion::DoPromotion(Function *F,
AA.replaceWithNewValue(Call, New);
// Update the callgraph to know that the callsite has been transformed.
- CG[Call->getParent()->getParent()]->replaceCallSite(Call, New, NF_CGN);
+ CallGraphNode *CalleeNode = CG[Call->getParent()->getParent()];
+ CalleeNode->replaceCallEdge(Call, New, NF_CGN);
if (!Call->use_empty()) {
Call->replaceAllUsesWith(New);
diff --git a/libclamav/c++/llvm/lib/Transforms/IPO/FunctionAttrs.cpp b/libclamav/c++/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
index 26b4152..7edaa7f 100644
--- a/libclamav/c++/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
@@ -26,6 +26,7 @@
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/CallGraph.h"
#include "llvm/Analysis/CaptureTracking.h"
+#include "llvm/Analysis/MallocHelper.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/UniqueVector.h"
@@ -153,7 +154,7 @@ bool FunctionAttrs::AddReadAttrs(const std::vector<CallGraphNode *> &SCC) {
return false;
if (isa<MallocInst>(I))
- // MallocInst claims not to write memory! PR3754.
+ // malloc claims not to write memory! PR3754.
return false;
// If this instruction may read memory, remember that.
@@ -247,26 +248,30 @@ bool FunctionAttrs::IsFunctionMallocLike(Function *F,
if (Instruction *RVI = dyn_cast<Instruction>(RetVal))
switch (RVI->getOpcode()) {
// Extend the analysis by looking upwards.
- case Instruction::GetElementPtr:
case Instruction::BitCast:
+ case Instruction::GetElementPtr:
FlowsToReturn.insert(RVI->getOperand(0));
continue;
case Instruction::Select: {
SelectInst *SI = cast<SelectInst>(RVI);
FlowsToReturn.insert(SI->getTrueValue());
FlowsToReturn.insert(SI->getFalseValue());
- } continue;
+ continue;
+ }
case Instruction::PHI: {
PHINode *PN = cast<PHINode>(RVI);
for (int i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
FlowsToReturn.insert(PN->getIncomingValue(i));
- } continue;
+ continue;
+ }
// Check whether the pointer came from an allocation.
case Instruction::Alloca:
case Instruction::Malloc:
break;
case Instruction::Call:
+ if (isMalloc(RVI))
+ break;
case Instruction::Invoke: {
CallSite CS(RVI);
if (CS.paramHasAttr(0, Attribute::NoAlias))
diff --git a/libclamav/c++/llvm/lib/Transforms/IPO/GlobalOpt.cpp b/libclamav/c++/llvm/lib/Transforms/IPO/GlobalOpt.cpp
index 4deb3f4..8edd79c 100644
--- a/libclamav/c++/llvm/lib/Transforms/IPO/GlobalOpt.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/IPO/GlobalOpt.cpp
@@ -24,6 +24,7 @@
#include "llvm/Module.h"
#include "llvm/Pass.h"
#include "llvm/Analysis/ConstantFolding.h"
+#include "llvm/Analysis/MallocHelper.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Support/CallSite.h"
#include "llvm/Support/Compiler.h"
@@ -939,6 +940,138 @@ static GlobalVariable *OptimizeGlobalAddressOfMalloc(GlobalVariable *GV,
return NewGV;
}
+/// OptimizeGlobalAddressOfMalloc - This function takes the specified global
+/// variable, and transforms the program as if it always contained the result of
+/// the specified malloc. Because it is always the result of the specified
+/// malloc, there is no reason to actually DO the malloc. Instead, turn the
+/// malloc into a global, and any loads of GV as uses of the new global.
+static GlobalVariable *OptimizeGlobalAddressOfMalloc(GlobalVariable *GV,
+ CallInst *CI,
+ BitCastInst *BCI,
+ LLVMContext &Context,
+ TargetData* TD) {
+ const Type *IntPtrTy = TD->getIntPtrType(Context);
+
+ DEBUG(errs() << "PROMOTING MALLOC GLOBAL: " << *GV << " MALLOC = " << *CI);
+
+ ConstantInt *NElements = cast<ConstantInt>(getMallocArraySize(CI,
+ Context, TD));
+ if (NElements->getZExtValue() != 1) {
+ // If we have an array allocation, transform it to a single element
+ // allocation to make the code below simpler.
+ Type *NewTy = ArrayType::get(getMallocAllocatedType(CI),
+ NElements->getZExtValue());
+ Value* NewM = CallInst::CreateMalloc(CI, IntPtrTy, NewTy);
+ Instruction* NewMI = cast<Instruction>(NewM);
+ Value* Indices[2];
+ Indices[0] = Indices[1] = Constant::getNullValue(IntPtrTy);
+ Value *NewGEP = GetElementPtrInst::Create(NewMI, Indices, Indices + 2,
+ NewMI->getName()+".el0", CI);
+ BCI->replaceAllUsesWith(NewGEP);
+ BCI->eraseFromParent();
+ CI->eraseFromParent();
+ BCI = cast<BitCastInst>(NewMI);
+ CI = extractMallocCallFromBitCast(NewMI);
+ }
+
+ // Create the new global variable. The contents of the malloc'd memory is
+ // undefined, so initialize with an undef value.
+ // FIXME: This new global should have the alignment returned by malloc. Code
+ // could depend on malloc returning large alignment (on the mac, 16 bytes) but
+ // this would only guarantee some lower alignment.
+ const Type *MAT = getMallocAllocatedType(CI);
+ Constant *Init = UndefValue::get(MAT);
+ GlobalVariable *NewGV = new GlobalVariable(*GV->getParent(),
+ MAT, false,
+ GlobalValue::InternalLinkage, Init,
+ GV->getName()+".body",
+ GV,
+ GV->isThreadLocal());
+
+ // Anything that used the malloc now uses the global directly.
+ BCI->replaceAllUsesWith(NewGV);
+
+ Constant *RepValue = NewGV;
+ if (NewGV->getType() != GV->getType()->getElementType())
+ RepValue = ConstantExpr::getBitCast(RepValue,
+ GV->getType()->getElementType());
+
+ // If there is a comparison against null, we will insert a global bool to
+ // keep track of whether the global was initialized yet or not.
+ GlobalVariable *InitBool =
+ new GlobalVariable(Context, Type::getInt1Ty(Context), false,
+ GlobalValue::InternalLinkage,
+ ConstantInt::getFalse(Context), GV->getName()+".init",
+ GV->isThreadLocal());
+ bool InitBoolUsed = false;
+
+ // Loop over all uses of GV, processing them in turn.
+ std::vector<StoreInst*> Stores;
+ while (!GV->use_empty())
+ if (LoadInst *LI = dyn_cast<LoadInst>(GV->use_back())) {
+ while (!LI->use_empty()) {
+ Use &LoadUse = LI->use_begin().getUse();
+ if (!isa<ICmpInst>(LoadUse.getUser()))
+ LoadUse = RepValue;
+ else {
+ ICmpInst *ICI = cast<ICmpInst>(LoadUse.getUser());
+ // Replace the cmp X, 0 with a use of the bool value.
+ Value *LV = new LoadInst(InitBool, InitBool->getName()+".val", ICI);
+ InitBoolUsed = true;
+ switch (ICI->getPredicate()) {
+ default: llvm_unreachable("Unknown ICmp Predicate!");
+ case ICmpInst::ICMP_ULT:
+ case ICmpInst::ICMP_SLT:
+ LV = ConstantInt::getFalse(Context); // X < null -> always false
+ break;
+ case ICmpInst::ICMP_ULE:
+ case ICmpInst::ICMP_SLE:
+ case ICmpInst::ICMP_EQ:
+ LV = BinaryOperator::CreateNot(LV, "notinit", ICI);
+ break;
+ case ICmpInst::ICMP_NE:
+ case ICmpInst::ICMP_UGE:
+ case ICmpInst::ICMP_SGE:
+ case ICmpInst::ICMP_UGT:
+ case ICmpInst::ICMP_SGT:
+ break; // no change.
+ }
+ ICI->replaceAllUsesWith(LV);
+ ICI->eraseFromParent();
+ }
+ }
+ LI->eraseFromParent();
+ } else {
+ StoreInst *SI = cast<StoreInst>(GV->use_back());
+ // The global is initialized when the store to it occurs.
+ new StoreInst(ConstantInt::getTrue(Context), InitBool, SI);
+ SI->eraseFromParent();
+ }
+
+ // If the initialization boolean was used, insert it, otherwise delete it.
+ if (!InitBoolUsed) {
+ while (!InitBool->use_empty()) // Delete initializations
+ cast<Instruction>(InitBool->use_back())->eraseFromParent();
+ delete InitBool;
+ } else
+ GV->getParent()->getGlobalList().insert(GV, InitBool);
+
+
+ // Now the GV is dead, nuke it and the malloc.
+ GV->eraseFromParent();
+ BCI->eraseFromParent();
+ CI->eraseFromParent();
+
+ // To further other optimizations, loop over all users of NewGV and try to
+ // constant prop them. This will promote GEP instructions with constant
+ // indices into GEP constant-exprs, which will allow global-opt to hack on it.
+ ConstantPropUsersOf(NewGV, Context);
+ if (RepValue != NewGV)
+ ConstantPropUsersOf(RepValue, Context);
+
+ return NewGV;
+}
+
/// ValueIsOnlyUsedLocallyOrStoredToOneGlobal - Scan the use-list of V checking
/// to make sure that there are no complex uses of V. We permit simple things
/// like dereferencing the pointer, but not storing through the address, unless
@@ -1086,7 +1219,7 @@ static bool LoadUsesSimpleEnoughForHeapSRA(Value *V,
/// AllGlobalLoadUsesSimpleEnoughForHeapSRA - If all users of values loaded from
/// GV are simple enough to perform HeapSRA, return true.
static bool AllGlobalLoadUsesSimpleEnoughForHeapSRA(GlobalVariable *GV,
- MallocInst *MI) {
+ Instruction *StoredVal) {
SmallPtrSet<PHINode*, 32> LoadUsingPHIs;
SmallPtrSet<PHINode*, 32> LoadUsingPHIsPerLoad;
for (Value::use_iterator UI = GV->use_begin(), E = GV->use_end(); UI != E;
@@ -1110,7 +1243,7 @@ static bool AllGlobalLoadUsesSimpleEnoughForHeapSRA(GlobalVariable *GV,
Value *InVal = PN->getIncomingValue(op);
// PHI of the stored value itself is ok.
- if (InVal == MI) continue;
+ if (InVal == StoredVal) continue;
if (PHINode *InPN = dyn_cast<PHINode>(InVal)) {
// One of the PHIs in our set is (optimistically) ok.
@@ -1444,6 +1577,191 @@ static GlobalVariable *PerformHeapAllocSRoA(GlobalVariable *GV, MallocInst *MI,
return cast<GlobalVariable>(FieldGlobals[0]);
}
+/// PerformHeapAllocSRoA - CI is an allocation of an array of structures. Break
+/// it up into multiple allocations of arrays of the fields.
+static GlobalVariable *PerformHeapAllocSRoA(GlobalVariable *GV,
+ CallInst *CI, BitCastInst* BCI,
+ LLVMContext &Context,
+ TargetData *TD){
+ DEBUG(errs() << "SROA HEAP ALLOC: " << *GV << " MALLOC CALL = " << *CI
+ << " BITCAST = " << *BCI << '\n');
+ const Type* MAT = getMallocAllocatedType(CI);
+ const StructType *STy = cast<StructType>(MAT);
+
+ // There is guaranteed to be at least one use of the malloc (storing
+ // it into GV). If there are other uses, change them to be uses of
+ // the global to simplify later code. This also deletes the store
+ // into GV.
+ ReplaceUsesOfMallocWithGlobal(BCI, GV);
+
+ // Okay, at this point, there are no users of the malloc. Insert N
+ // new mallocs at the same place as CI, and N globals.
+ std::vector<Value*> FieldGlobals;
+ std::vector<Value*> FieldMallocs;
+
+ for (unsigned FieldNo = 0, e = STy->getNumElements(); FieldNo != e;++FieldNo){
+ const Type *FieldTy = STy->getElementType(FieldNo);
+ const PointerType *PFieldTy = PointerType::getUnqual(FieldTy);
+
+ GlobalVariable *NGV =
+ new GlobalVariable(*GV->getParent(),
+ PFieldTy, false, GlobalValue::InternalLinkage,
+ Constant::getNullValue(PFieldTy),
+ GV->getName() + ".f" + Twine(FieldNo), GV,
+ GV->isThreadLocal());
+ FieldGlobals.push_back(NGV);
+
+ Value *NMI = CallInst::CreateMalloc(CI, TD->getIntPtrType(Context), FieldTy,
+ getMallocArraySize(CI, Context, TD),
+ BCI->getName() + ".f" + Twine(FieldNo));
+ FieldMallocs.push_back(NMI);
+ new StoreInst(NMI, NGV, BCI);
+ }
+
+ // The tricky aspect of this transformation is handling the case when malloc
+ // fails. In the original code, malloc failing would set the result pointer
+ // of malloc to null. In this case, some mallocs could succeed and others
+ // could fail. As such, we emit code that looks like this:
+ // F0 = malloc(field0)
+ // F1 = malloc(field1)
+ // F2 = malloc(field2)
+ // if (F0 == 0 || F1 == 0 || F2 == 0) {
+ // if (F0) { free(F0); F0 = 0; }
+ // if (F1) { free(F1); F1 = 0; }
+ // if (F2) { free(F2); F2 = 0; }
+ // }
+ Value *RunningOr = 0;
+ for (unsigned i = 0, e = FieldMallocs.size(); i != e; ++i) {
+ Value *Cond = new ICmpInst(BCI, ICmpInst::ICMP_EQ, FieldMallocs[i],
+ Constant::getNullValue(FieldMallocs[i]->getType()),
+ "isnull");
+ if (!RunningOr)
+ RunningOr = Cond; // First seteq
+ else
+ RunningOr = BinaryOperator::CreateOr(RunningOr, Cond, "tmp", BCI);
+ }
+
+ // Split the basic block at the old malloc.
+ BasicBlock *OrigBB = BCI->getParent();
+ BasicBlock *ContBB = OrigBB->splitBasicBlock(BCI, "malloc_cont");
+
+ // Create the block to check the first condition. Put all these blocks at the
+ // end of the function as they are unlikely to be executed.
+ BasicBlock *NullPtrBlock = BasicBlock::Create(Context, "malloc_ret_null",
+ OrigBB->getParent());
+
+ // Remove the uncond branch from OrigBB to ContBB, turning it into a cond
+ // branch on RunningOr.
+ OrigBB->getTerminator()->eraseFromParent();
+ BranchInst::Create(NullPtrBlock, ContBB, RunningOr, OrigBB);
+
+ // Within the NullPtrBlock, we need to emit a comparison and branch for each
+ // pointer, because some may be null while others are not.
+ for (unsigned i = 0, e = FieldGlobals.size(); i != e; ++i) {
+ Value *GVVal = new LoadInst(FieldGlobals[i], "tmp", NullPtrBlock);
+ Value *Cmp = new ICmpInst(*NullPtrBlock, ICmpInst::ICMP_NE, GVVal,
+ Constant::getNullValue(GVVal->getType()),
+ "tmp");
+ BasicBlock *FreeBlock = BasicBlock::Create(Context, "free_it",
+ OrigBB->getParent());
+ BasicBlock *NextBlock = BasicBlock::Create(Context, "next",
+ OrigBB->getParent());
+ BranchInst::Create(FreeBlock, NextBlock, Cmp, NullPtrBlock);
+
+ // Fill in FreeBlock.
+ new FreeInst(GVVal, FreeBlock);
+ new StoreInst(Constant::getNullValue(GVVal->getType()), FieldGlobals[i],
+ FreeBlock);
+ BranchInst::Create(NextBlock, FreeBlock);
+
+ NullPtrBlock = NextBlock;
+ }
+
+ BranchInst::Create(ContBB, NullPtrBlock);
+
+ // CI and BCI are no longer needed, remove them.
+ BCI->eraseFromParent();
+ CI->eraseFromParent();
+
+ /// InsertedScalarizedLoads - As we process loads, if we can't immediately
+ /// update all uses of the load, keep track of what scalarized loads are
+ /// inserted for a given load.
+ DenseMap<Value*, std::vector<Value*> > InsertedScalarizedValues;
+ InsertedScalarizedValues[GV] = FieldGlobals;
+
+ std::vector<std::pair<PHINode*, unsigned> > PHIsToRewrite;
+
+ // Okay, the malloc site is completely handled. All of the uses of GV are now
+ // loads, and all uses of those loads are simple. Rewrite them to use loads
+ // of the per-field globals instead.
+ for (Value::use_iterator UI = GV->use_begin(), E = GV->use_end(); UI != E;) {
+ Instruction *User = cast<Instruction>(*UI++);
+
+ if (LoadInst *LI = dyn_cast<LoadInst>(User)) {
+ RewriteUsesOfLoadForHeapSRoA(LI, InsertedScalarizedValues, PHIsToRewrite,
+ Context);
+ continue;
+ }
+
+ // Must be a store of null.
+ StoreInst *SI = cast<StoreInst>(User);
+ assert(isa<ConstantPointerNull>(SI->getOperand(0)) &&
+ "Unexpected heap-sra user!");
+
+ // Insert a store of null into each global.
+ for (unsigned i = 0, e = FieldGlobals.size(); i != e; ++i) {
+ const PointerType *PT = cast<PointerType>(FieldGlobals[i]->getType());
+ Constant *Null = Constant::getNullValue(PT->getElementType());
+ new StoreInst(Null, FieldGlobals[i], SI);
+ }
+ // Erase the original store.
+ SI->eraseFromParent();
+ }
+
+ // While we have PHIs that are interesting to rewrite, do it.
+ while (!PHIsToRewrite.empty()) {
+ PHINode *PN = PHIsToRewrite.back().first;
+ unsigned FieldNo = PHIsToRewrite.back().second;
+ PHIsToRewrite.pop_back();
+ PHINode *FieldPN = cast<PHINode>(InsertedScalarizedValues[PN][FieldNo]);
+ assert(FieldPN->getNumIncomingValues() == 0 &&"Already processed this phi");
+
+ // Add all the incoming values. This can materialize more phis.
+ for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
+ Value *InVal = PN->getIncomingValue(i);
+ InVal = GetHeapSROAValue(InVal, FieldNo, InsertedScalarizedValues,
+ PHIsToRewrite, Context);
+ FieldPN->addIncoming(InVal, PN->getIncomingBlock(i));
+ }
+ }
+
+ // Drop all inter-phi links and any loads that made it this far.
+ for (DenseMap<Value*, std::vector<Value*> >::iterator
+ I = InsertedScalarizedValues.begin(), E = InsertedScalarizedValues.end();
+ I != E; ++I) {
+ if (PHINode *PN = dyn_cast<PHINode>(I->first))
+ PN->dropAllReferences();
+ else if (LoadInst *LI = dyn_cast<LoadInst>(I->first))
+ LI->dropAllReferences();
+ }
+
+ // Delete all the phis and loads now that inter-references are dead.
+ for (DenseMap<Value*, std::vector<Value*> >::iterator
+ I = InsertedScalarizedValues.begin(), E = InsertedScalarizedValues.end();
+ I != E; ++I) {
+ if (PHINode *PN = dyn_cast<PHINode>(I->first))
+ PN->eraseFromParent();
+ else if (LoadInst *LI = dyn_cast<LoadInst>(I->first))
+ LI->eraseFromParent();
+ }
+
+ // The old global is now dead, remove it.
+ GV->eraseFromParent();
+
+ ++NumHeapSRA;
+ return cast<GlobalVariable>(FieldGlobals[0]);
+}
+
/// TryToOptimizeStoreOfMallocToGlobal - This function is called when we see a
/// pointer global variable with a single value stored it that is a malloc or
/// cast of malloc.
@@ -1533,6 +1851,99 @@ static bool TryToOptimizeStoreOfMallocToGlobal(GlobalVariable *GV,
return false;
}
+/// TryToOptimizeStoreOfMallocToGlobal - This function is called when we see a
+/// pointer global variable with a single value stored it that is a malloc or
+/// cast of malloc.
+static bool TryToOptimizeStoreOfMallocToGlobal(GlobalVariable *GV,
+ CallInst *CI,
+ BitCastInst *BCI,
+ Module::global_iterator &GVI,
+ TargetData *TD,
+ LLVMContext &Context) {
+ // If we can't figure out the type being malloced, then we can't optimize.
+ const Type *AllocTy = getMallocAllocatedType(CI);
+ assert(AllocTy);
+
+ // If this is a malloc of an abstract type, don't touch it.
+ if (!AllocTy->isSized())
+ return false;
+
+ // We can't optimize this global unless all uses of it are *known* to be
+ // of the malloc value, not of the null initializer value (consider a use
+ // that compares the global's value against zero to see if the malloc has
+ // been reached). To do this, we check to see if all uses of the global
+ // would trap if the global were null: this proves that they must all
+ // happen after the malloc.
+ if (!AllUsesOfLoadedValueWillTrapIfNull(GV))
+ return false;
+
+ // We can't optimize this if the malloc itself is used in a complex way,
+ // for example, being stored into multiple globals. This allows the
+ // malloc to be stored into the specified global, loaded setcc'd, and
+ // GEP'd. These are all things we could transform to using the global
+ // for.
+ {
+ SmallPtrSet<PHINode*, 8> PHIs;
+ if (!ValueIsOnlyUsedLocallyOrStoredToOneGlobal(BCI, GV, PHIs))
+ return false;
+ }
+
+ // If we have a global that is only initialized with a fixed size malloc,
+ // transform the program to use global memory instead of malloc'd memory.
+ // This eliminates dynamic allocation, avoids an indirection accessing the
+ // data, and exposes the resultant global to further GlobalOpt.
+ if (ConstantInt *NElements =
+ dyn_cast<ConstantInt>(getMallocArraySize(CI, Context, TD))) {
+ // Restrict this transformation to only working on small allocations
+ // (2048 bytes currently), as we don't want to introduce a 16M global or
+ // something.
+ if (TD &&
+ NElements->getZExtValue() * TD->getTypeAllocSize(AllocTy) < 2048) {
+ GVI = OptimizeGlobalAddressOfMalloc(GV, CI, BCI, Context, TD);
+ return true;
+ }
+ }
+
+ // If the allocation is an array of structures, consider transforming this
+ // into multiple malloc'd arrays, one for each field. This is basically
+ // SRoA for malloc'd memory.
+
+ // If this is an allocation of a fixed size array of structs, analyze as a
+ // variable size array. malloc [100 x struct],1 -> malloc struct, 100
+ if (!isArrayMalloc(CI, Context, TD))
+ if (const ArrayType *AT = dyn_cast<ArrayType>(AllocTy))
+ AllocTy = AT->getElementType();
+
+ if (const StructType *AllocSTy = dyn_cast<StructType>(AllocTy)) {
+ // This the structure has an unreasonable number of fields, leave it
+ // alone.
+ if (AllocSTy->getNumElements() <= 16 && AllocSTy->getNumElements() != 0 &&
+ AllGlobalLoadUsesSimpleEnoughForHeapSRA(GV, BCI)) {
+
+ // If this is a fixed size array, transform the Malloc to be an alloc of
+ // structs. malloc [100 x struct],1 -> malloc struct, 100
+ if (const ArrayType *AT = dyn_cast<ArrayType>(getMallocAllocatedType(CI))) {
+ Value* NumElements = ConstantInt::get(Type::getInt32Ty(Context),
+ AT->getNumElements());
+ Value* NewMI = CallInst::CreateMalloc(CI, TD->getIntPtrType(Context),
+ AllocSTy, NumElements,
+ BCI->getName());
+ Value *Cast = new BitCastInst(NewMI, getMallocType(CI), "tmp", CI);
+ BCI->replaceAllUsesWith(Cast);
+ BCI->eraseFromParent();
+ CI->eraseFromParent();
+ BCI = cast<BitCastInst>(NewMI);
+ CI = extractMallocCallFromBitCast(NewMI);
+ }
+
+ GVI = PerformHeapAllocSRoA(GV, CI, BCI, Context, TD);
+ return true;
+ }
+ }
+
+ return false;
+}
+
// OptimizeOnceStoredGlobal - Try to optimize globals based on the knowledge
// that only one value (besides its initializer) is ever stored to the global.
static bool OptimizeOnceStoredGlobal(GlobalVariable *GV, Value *StoredOnceVal,
@@ -1558,6 +1969,16 @@ static bool OptimizeOnceStoredGlobal(GlobalVariable *GV, Value *StoredOnceVal,
} else if (MallocInst *MI = dyn_cast<MallocInst>(StoredOnceVal)) {
if (TryToOptimizeStoreOfMallocToGlobal(GV, MI, GVI, TD, Context))
return true;
+ } else if (CallInst *CI = extractMallocCall(StoredOnceVal)) {
+ if (getMallocAllocatedType(CI)) {
+ BitCastInst* BCI = NULL;
+ for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
+ UI != E; )
+ BCI = dyn_cast<BitCastInst>(cast<Instruction>(*UI++));
+ if (BCI &&
+ TryToOptimizeStoreOfMallocToGlobal(GV, CI, BCI, GVI, TD, Context))
+ return true;
+ }
}
}
@@ -1972,14 +2393,14 @@ static GlobalVariable *InstallGlobalCtors(GlobalVariable *GCL,
CSVals[1] = Constant::getNullValue(PFTy);
CSVals[0] = ConstantInt::get(Type::getInt32Ty(Context), 2147483647);
}
- CAList.push_back(ConstantStruct::get(Context, CSVals));
+ CAList.push_back(ConstantStruct::get(Context, CSVals, false));
}
// Create the array initializer.
const Type *StructTy =
- cast<ArrayType>(GCL->getType()->getElementType())->getElementType();
+ cast<ArrayType>(GCL->getType()->getElementType())->getElementType();
Constant *CA = ConstantArray::get(ArrayType::get(StructTy,
- CAList.size()), CAList);
+ CAList.size()), CAList);
// If we didn't change the number of elements, don't create a new GV.
if (CA->getType() == GCL->getInitializer()->getType()) {
@@ -2024,20 +2445,37 @@ static Constant *getVal(DenseMap<Value*, Constant*> &ComputedValues,
/// we punt. We basically just support direct accesses to globals and GEP's of
/// globals. This should be kept up to date with CommitValueTo.
static bool isSimpleEnoughPointerToCommit(Constant *C, LLVMContext &Context) {
- if (GlobalVariable *GV = dyn_cast<GlobalVariable>(C)) {
- if (!GV->hasExternalLinkage() && !GV->hasLocalLinkage())
- return false; // do not allow weak/linkonce/dllimport/dllexport linkage.
- return !GV->isDeclaration(); // reject external globals.
- }
+ // Conservatively, avoid aggregate types. This is because we don't
+ // want to worry about them partially overlapping other stores.
+ if (!cast<PointerType>(C->getType())->getElementType()->isSingleValueType())
+ return false;
+
+ if (GlobalVariable *GV = dyn_cast<GlobalVariable>(C))
+ // Do not allow weak/linkonce/dllimport/dllexport linkage or
+ // external globals.
+ return GV->hasDefinitiveInitializer();
+
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C))
// Handle a constantexpr gep.
if (CE->getOpcode() == Instruction::GetElementPtr &&
- isa<GlobalVariable>(CE->getOperand(0))) {
+ isa<GlobalVariable>(CE->getOperand(0)) &&
+ cast<GEPOperator>(CE)->isInBounds()) {
GlobalVariable *GV = cast<GlobalVariable>(CE->getOperand(0));
- if (!GV->hasExternalLinkage() && !GV->hasLocalLinkage())
- return false; // do not allow weak/linkonce/dllimport/dllexport linkage.
- return GV->hasInitializer() &&
- ConstantFoldLoadThroughGEPConstantExpr(GV->getInitializer(), CE,
+ // Do not allow weak/linkonce/dllimport/dllexport linkage or
+ // external globals.
+ if (!GV->hasDefinitiveInitializer())
+ return false;
+
+ // The first index must be zero.
+ ConstantInt *CI = dyn_cast<ConstantInt>(*next(CE->op_begin()));
+ if (!CI || !CI->isZero()) return false;
+
+ // The remaining indices must be compile-time known integers within the
+ // notional bounds of the corresponding static array types.
+ if (!CE->isGEPWithNoNotionalOverIndexing())
+ return false;
+
+ return ConstantFoldLoadThroughGEPConstantExpr(GV->getInitializer(), CE,
Context);
}
return false;
@@ -2226,8 +2664,9 @@ static bool EvaluateFunction(Function *F, Constant *&RetVal,
for (User::op_iterator i = GEP->op_begin() + 1, e = GEP->op_end();
i != e; ++i)
GEPOps.push_back(getVal(Values, *i));
- InstResult =
- ConstantExpr::getGetElementPtr(P, &GEPOps[0], GEPOps.size());
+ InstResult = cast<GEPOperator>(GEP)->isInBounds() ?
+ ConstantExpr::getInBoundsGetElementPtr(P, &GEPOps[0], GEPOps.size()) :
+ ConstantExpr::getGetElementPtr(P, &GEPOps[0], GEPOps.size());
} else if (LoadInst *LI = dyn_cast<LoadInst>(CurInst)) {
if (LI->isVolatile()) return false; // no volatile accesses.
InstResult = ComputeLoadResult(getVal(Values, LI->getOperand(0)),
diff --git a/libclamav/c++/llvm/lib/Transforms/IPO/IPConstantPropagation.cpp b/libclamav/c++/llvm/lib/Transforms/IPO/IPConstantPropagation.cpp
index bb24486..7b0e9c7 100644
--- a/libclamav/c++/llvm/lib/Transforms/IPO/IPConstantPropagation.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/IPO/IPConstantPropagation.cpp
@@ -130,7 +130,8 @@ bool IPCP::PropagateConstantsIntoArguments(Function &F) {
Function::arg_iterator AI = F.arg_begin();
for (unsigned i = 0, e = ArgumentConstants.size(); i != e; ++i, ++AI) {
// Do we have a constant argument?
- if (ArgumentConstants[i].second || AI->use_empty())
+ if (ArgumentConstants[i].second || AI->use_empty() ||
+ (AI->hasByValAttr() && !F.onlyReadsMemory()))
continue;
Value *V = ArgumentConstants[i].first;
diff --git a/libclamav/c++/llvm/lib/Transforms/IPO/LoopExtractor.cpp b/libclamav/c++/llvm/lib/Transforms/IPO/LoopExtractor.cpp
index 4b09884..02ac3bb 100644
--- a/libclamav/c++/llvm/lib/Transforms/IPO/LoopExtractor.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/IPO/LoopExtractor.cpp
@@ -20,7 +20,7 @@
#include "llvm/Module.h"
#include "llvm/Pass.h"
#include "llvm/Analysis/Dominators.h"
-#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/LoopPass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Transforms/Scalar.h"
@@ -33,23 +33,19 @@ using namespace llvm;
STATISTIC(NumExtracted, "Number of loops extracted");
namespace {
- // FIXME: This is not a function pass, but the PassManager doesn't allow
- // Module passes to require FunctionPasses, so we can't get loop info if we're
- // not a function pass.
- struct VISIBILITY_HIDDEN LoopExtractor : public FunctionPass {
+ struct VISIBILITY_HIDDEN LoopExtractor : public LoopPass {
static char ID; // Pass identification, replacement for typeid
unsigned NumLoops;
explicit LoopExtractor(unsigned numLoops = ~0)
- : FunctionPass(&ID), NumLoops(numLoops) {}
+ : LoopPass(&ID), NumLoops(numLoops) {}
- virtual bool runOnFunction(Function &F);
+ virtual bool runOnLoop(Loop *L, LPPassManager &LPM);
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequiredID(BreakCriticalEdgesID);
AU.addRequiredID(LoopSimplifyID);
AU.addRequired<DominatorTree>();
- AU.addRequired<LoopInfo>();
}
};
}
@@ -73,68 +69,50 @@ Y("loop-extract-single", "Extract at most one loop into a new function");
// createLoopExtractorPass - This pass extracts all natural loops from the
// program into a function if it can.
//
-FunctionPass *llvm::createLoopExtractorPass() { return new LoopExtractor(); }
+Pass *llvm::createLoopExtractorPass() { return new LoopExtractor(); }
-bool LoopExtractor::runOnFunction(Function &F) {
- LoopInfo &LI = getAnalysis<LoopInfo>();
-
- // If this function has no loops, there is nothing to do.
- if (LI.empty())
+bool LoopExtractor::runOnLoop(Loop *L, LPPassManager &LPM) {
+ // Only visit top-level loops.
+ if (L->getParentLoop())
return false;
DominatorTree &DT = getAnalysis<DominatorTree>();
-
- // If there is more than one top-level loop in this function, extract all of
- // the loops.
bool Changed = false;
- if (LI.end()-LI.begin() > 1) {
- for (LoopInfo::iterator i = LI.begin(), e = LI.end(); i != e; ++i) {
- if (NumLoops == 0) return Changed;
- --NumLoops;
- Changed |= ExtractLoop(DT, *i) != 0;
- ++NumExtracted;
- }
- } else {
- // Otherwise there is exactly one top-level loop. If this function is more
- // than a minimal wrapper around the loop, extract the loop.
- Loop *TLL = *LI.begin();
- bool ShouldExtractLoop = false;
-
- // Extract the loop if the entry block doesn't branch to the loop header.
- TerminatorInst *EntryTI = F.getEntryBlock().getTerminator();
- if (!isa<BranchInst>(EntryTI) ||
- !cast<BranchInst>(EntryTI)->isUnconditional() ||
- EntryTI->getSuccessor(0) != TLL->getHeader())
- ShouldExtractLoop = true;
- else {
- // Check to see if any exits from the loop are more than just return
- // blocks.
- SmallVector<BasicBlock*, 8> ExitBlocks;
- TLL->getExitBlocks(ExitBlocks);
- for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i)
- if (!isa<ReturnInst>(ExitBlocks[i]->getTerminator())) {
- ShouldExtractLoop = true;
- break;
- }
- }
- if (ShouldExtractLoop) {
- if (NumLoops == 0) return Changed;
- --NumLoops;
- Changed |= ExtractLoop(DT, TLL) != 0;
- ++NumExtracted;
- } else {
- // Okay, this function is a minimal container around the specified loop.
- // If we extract the loop, we will continue to just keep extracting it
- // infinitely... so don't extract it. However, if the loop contains any
- // subloops, extract them.
- for (Loop::iterator i = TLL->begin(), e = TLL->end(); i != e; ++i) {
- if (NumLoops == 0) return Changed;
- --NumLoops;
- Changed |= ExtractLoop(DT, *i) != 0;
- ++NumExtracted;
+ // If there is more than one top-level loop in this function, extract all of
+ // the loops. Otherwise there is exactly one top-level loop; in this case if
+ // this function is more than a minimal wrapper around the loop, extract
+ // the loop.
+ bool ShouldExtractLoop = false;
+
+ // Extract the loop if the entry block doesn't branch to the loop header.
+ TerminatorInst *EntryTI =
+ L->getHeader()->getParent()->getEntryBlock().getTerminator();
+ if (!isa<BranchInst>(EntryTI) ||
+ !cast<BranchInst>(EntryTI)->isUnconditional() ||
+ EntryTI->getSuccessor(0) != L->getHeader())
+ ShouldExtractLoop = true;
+ else {
+ // Check to see if any exits from the loop are more than just return
+ // blocks.
+ SmallVector<BasicBlock*, 8> ExitBlocks;
+ L->getExitBlocks(ExitBlocks);
+ for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i)
+ if (!isa<ReturnInst>(ExitBlocks[i]->getTerminator())) {
+ ShouldExtractLoop = true;
+ break;
}
+ }
+ if (ShouldExtractLoop) {
+ if (NumLoops == 0) return Changed;
+ --NumLoops;
+ if (ExtractLoop(DT, L) != 0) {
+ Changed = true;
+ // After extraction, the loop is replaced by a function call, so
+ // we shouldn't try to run any more loop passes on it.
+ LPM.deleteLoopFromQueue(L);
}
+ ++NumExtracted;
}
return Changed;
@@ -143,7 +121,7 @@ bool LoopExtractor::runOnFunction(Function &F) {
// createSingleLoopExtractorPass - This pass extracts one natural loop from the
// program into a function if it can. This is used by bugpoint.
//
-FunctionPass *llvm::createSingleLoopExtractorPass() {
+Pass *llvm::createSingleLoopExtractorPass() {
return new SingleLoopExtractor();
}
diff --git a/libclamav/c++/llvm/lib/Transforms/IPO/MergeFunctions.cpp b/libclamav/c++/llvm/lib/Transforms/IPO/MergeFunctions.cpp
index 9c8592e..13bbf9c 100644
--- a/libclamav/c++/llvm/lib/Transforms/IPO/MergeFunctions.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/IPO/MergeFunctions.cpp
@@ -582,19 +582,19 @@ static bool fold(std::vector<Function *> &FnVec, unsigned i, unsigned j) {
llvm_unreachable(0);
// fall-through
case ExternalWeak:
- if (F->hasAddressTaken())
+ if (F->hasAddressTaken())
ThunkGToF(F, G);
else
AliasGToF(F, G);
- break;
+ break;
case Internal: {
bool addrTakenF = F->hasAddressTaken();
bool addrTakenG = G->hasAddressTaken();
if (!addrTakenF && addrTakenG) {
std::swap(FnVec[i], FnVec[j]);
std::swap(F, G);
- std::swap(addrTakenF, addrTakenG);
- }
+ std::swap(addrTakenF, addrTakenG);
+ }
if (addrTakenF && addrTakenG) {
ThunkGToF(F, G);
@@ -602,7 +602,7 @@ static bool fold(std::vector<Function *> &FnVec, unsigned i, unsigned j) {
assert(!addrTakenG);
AliasGToF(F, G);
}
- } break;
+ } break;
}
break;
}
diff --git a/libclamav/c++/llvm/lib/Transforms/IPO/PartialInlining.cpp b/libclamav/c++/llvm/lib/Transforms/IPO/PartialInlining.cpp
index 73ec9c1..8f858d3 100644
--- a/libclamav/c++/llvm/lib/Transforms/IPO/PartialInlining.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/IPO/PartialInlining.cpp
@@ -48,7 +48,8 @@ ModulePass* llvm::createPartialInliningPass() { return new PartialInliner(); }
Function* PartialInliner::unswitchFunction(Function* F) {
// First, verify that this function is an unswitching candidate...
BasicBlock* entryBlock = F->begin();
- if (!isa<BranchInst>(entryBlock->getTerminator()))
+ BranchInst *BR = dyn_cast<BranchInst>(entryBlock->getTerminator());
+ if (!BR || BR->isUnconditional())
return 0;
BasicBlock* returnBlock = 0;
diff --git a/libclamav/c++/llvm/lib/Transforms/IPO/PruneEH.cpp b/libclamav/c++/llvm/lib/Transforms/IPO/PruneEH.cpp
index d9b867e..daf81e9 100644
--- a/libclamav/c++/llvm/lib/Transforms/IPO/PruneEH.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/IPO/PruneEH.cpp
@@ -165,9 +165,6 @@ bool PruneEH::runOnSCC(std::vector<CallGraphNode *> &SCC) {
// function if we have invokes to non-unwinding functions or code after calls to
// no-return functions.
bool PruneEH::SimplifyFunction(Function *F) {
- CallGraph &CG = getAnalysis<CallGraph>();
- CallGraphNode *CGN = CG[F];
-
bool MadeChange = false;
for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
if (InvokeInst *II = dyn_cast<InvokeInst>(BB->getTerminator()))
@@ -181,14 +178,13 @@ bool PruneEH::SimplifyFunction(Function *F) {
Call->setAttributes(II->getAttributes());
// Anything that used the value produced by the invoke instruction
- // now uses the value produced by the call instruction.
+ // now uses the value produced by the call instruction. Note that we
+ // do this even for void functions and calls with no uses so that the
+ // callgraph edge is updated.
II->replaceAllUsesWith(Call);
BasicBlock *UnwindBlock = II->getUnwindDest();
UnwindBlock->removePredecessor(II->getParent());
- // Fix up the call graph.
- CGN->replaceCallSite(II, Call, 0/*keep callee*/);
-
// Insert a branch to the normal destination right before the
// invoke.
BranchInst::Create(II->getNormalDest(), II);
diff --git a/libclamav/c++/llvm/lib/Transforms/IPO/StripSymbols.cpp b/libclamav/c++/llvm/lib/Transforms/IPO/StripSymbols.cpp
index 0bd1696..77d44b2 100644
--- a/libclamav/c++/llvm/lib/Transforms/IPO/StripSymbols.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/IPO/StripSymbols.cpp
@@ -31,12 +31,11 @@
#include "llvm/ValueSymbolTable.h"
#include "llvm/TypeSymbolTable.h"
#include "llvm/Transforms/Utils/Local.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/ADT/SmallPtrSet.h"
using namespace llvm;
namespace {
- class VISIBILITY_HIDDEN StripSymbols : public ModulePass {
+ class StripSymbols : public ModulePass {
bool OnlyDebugInfo;
public:
static char ID; // Pass identification, replacement for typeid
@@ -50,7 +49,7 @@ namespace {
}
};
- class VISIBILITY_HIDDEN StripNonDebugSymbols : public ModulePass {
+ class StripNonDebugSymbols : public ModulePass {
public:
static char ID; // Pass identification, replacement for typeid
explicit StripNonDebugSymbols()
@@ -63,7 +62,7 @@ namespace {
}
};
- class VISIBILITY_HIDDEN StripDebugDeclare : public ModulePass {
+ class StripDebugDeclare : public ModulePass {
public:
static char ID; // Pass identification, replacement for typeid
explicit StripDebugDeclare()
diff --git a/libclamav/c++/llvm/lib/Transforms/IPO/StructRetPromotion.cpp b/libclamav/c++/llvm/lib/Transforms/IPO/StructRetPromotion.cpp
index 4c4c6d6..4442820 100644
--- a/libclamav/c++/llvm/lib/Transforms/IPO/StructRetPromotion.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/IPO/StructRetPromotion.cpp
@@ -321,8 +321,10 @@ CallGraphNode *SRETPromotion::updateCallSites(Function *F, Function *NF) {
New->takeName(Call);
// Update the callgraph to know that the callsite has been transformed.
- CG[Call->getParent()->getParent()]->replaceCallSite(Call, New, NF_CGN);
-
+ CallGraphNode *CalleeNode = CG[Call->getParent()->getParent()];
+ CalleeNode->removeCallEdgeFor(Call);
+ CalleeNode->addCalledFunction(New, NF_CGN);
+
// Update all users of sret parameter to extract value using extractvalue.
for (Value::use_iterator UI = FirstCArg->use_begin(),
UE = FirstCArg->use_end(); UI != UE; ) {
@@ -331,23 +333,19 @@ CallGraphNode *SRETPromotion::updateCallSites(Function *F, Function *NF) {
if (C2 && (C2 == Call))
continue;
- if (GetElementPtrInst *UGEP = dyn_cast<GetElementPtrInst>(U2)) {
- ConstantInt *Idx = dyn_cast<ConstantInt>(UGEP->getOperand(2));
- assert (Idx && "Unexpected getelementptr index!");
- Value *GR = ExtractValueInst::Create(New, Idx->getZExtValue(),
- "evi", UGEP);
- while(!UGEP->use_empty()) {
- // isSafeToUpdateAllCallers has checked that all GEP uses are
- // LoadInsts
- LoadInst *L = cast<LoadInst>(*UGEP->use_begin());
- L->replaceAllUsesWith(GR);
- L->eraseFromParent();
- }
- UGEP->eraseFromParent();
- continue;
+ GetElementPtrInst *UGEP = cast<GetElementPtrInst>(U2);
+ ConstantInt *Idx = cast<ConstantInt>(UGEP->getOperand(2));
+ Value *GR = ExtractValueInst::Create(New, Idx->getZExtValue(),
+ "evi", UGEP);
+ while(!UGEP->use_empty()) {
+ // isSafeToUpdateAllCallers has checked that all GEP uses are
+ // LoadInsts
+ LoadInst *L = cast<LoadInst>(*UGEP->use_begin());
+ L->replaceAllUsesWith(GR);
+ L->eraseFromParent();
}
-
- assert(0 && "Unexpected sret parameter use");
+ UGEP->eraseFromParent();
+ continue;
}
Call->eraseFromParent();
}
diff --git a/libclamav/c++/llvm/lib/Transforms/Instrumentation/CMakeLists.txt b/libclamav/c++/llvm/lib/Transforms/Instrumentation/CMakeLists.txt
index d7c518d..494928e 100644
--- a/libclamav/c++/llvm/lib/Transforms/Instrumentation/CMakeLists.txt
+++ b/libclamav/c++/llvm/lib/Transforms/Instrumentation/CMakeLists.txt
@@ -1,6 +1,7 @@
add_llvm_library(LLVMInstrumentation
BlockProfiling.cpp
EdgeProfiling.cpp
+ OptimalEdgeProfiling.cpp
ProfilingUtils.cpp
RSProfiling.cpp
)
diff --git a/libclamav/c++/llvm/lib/Transforms/Instrumentation/EdgeProfiling.cpp b/libclamav/c++/llvm/lib/Transforms/Instrumentation/EdgeProfiling.cpp
index ed9ff50..b9cb275 100644
--- a/libclamav/c++/llvm/lib/Transforms/Instrumentation/EdgeProfiling.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Instrumentation/EdgeProfiling.cpp
@@ -16,7 +16,7 @@
// number of counters inserted.
//
//===----------------------------------------------------------------------===//
-
+#define DEBUG_TYPE "insert-edge-profiling"
#include "ProfilingUtils.h"
#include "llvm/Module.h"
#include "llvm/Pass.h"
@@ -24,15 +24,22 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Instrumentation.h"
+#include "llvm/ADT/Statistic.h"
#include <set>
using namespace llvm;
+STATISTIC(NumEdgesInserted, "The # of edges inserted.");
+
namespace {
class VISIBILITY_HIDDEN EdgeProfiler : public ModulePass {
bool runOnModule(Module &M);
public:
static char ID; // Pass identification, replacement for typeid
EdgeProfiler() : ModulePass(&ID) {}
+
+ virtual const char *getPassName() const {
+ return "Edge Profiler";
+ }
};
}
@@ -69,6 +76,7 @@ bool EdgeProfiler::runOnModule(Module &M) {
GlobalVariable *Counters =
new GlobalVariable(M, ATy, false, GlobalValue::InternalLinkage,
Constant::getNullValue(ATy), "EdgeProfCounters");
+ NumEdgesInserted = NumEdges;
// Instrument all of the edges...
unsigned i = 0;
diff --git a/libclamav/c++/llvm/lib/Transforms/Instrumentation/MaximumSpanningTree.cpp b/libclamav/c++/llvm/lib/Transforms/Instrumentation/MaximumSpanningTree.cpp
deleted file mode 100644
index 80f1a15..0000000
--- a/libclamav/c++/llvm/lib/Transforms/Instrumentation/MaximumSpanningTree.cpp
+++ /dev/null
@@ -1,121 +0,0 @@
-//===- MaximumSpanningTree.cpp - LLVM Pass to estimate profile info -------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This module privides means for calculating a maximum spanning tree for the
-// CFG of a function according to a given profile. The tree does not contain
-// leaf edges, since they are needed for optimal edge profiling.
-//
-//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "maximum-spanning-tree"
-#include "MaximumSpanningTree.h"
-#include "llvm/Pass.h"
-#include "llvm/Analysis/Passes.h"
-#include "llvm/ADT/EquivalenceClasses.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/Support/CFG.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/Format.h"
-using namespace llvm;
-
-namespace {
- // compare two weighted edges
- struct VISIBILITY_HIDDEN EdgeWeightCompare {
- bool operator()(const ProfileInfo::EdgeWeight X,
- const ProfileInfo::EdgeWeight Y) const {
- if (X.second > Y.second) return true;
- if (X.second < Y.second) return false;
-#ifndef NDEBUG
- if (X.first.first != 0 && Y.first.first == 0) return true;
- if (X.first.first == 0 && Y.first.first != 0) return false;
- if (X.first.first == 0 && Y.first.first == 0) return false;
-
- if (X.first.first->size() > Y.first.first->size()) return true;
- if (X.first.first->size() < Y.first.first->size()) return false;
-
- if (X.first.second != 0 && Y.first.second == 0) return true;
- if (X.first.second == 0 && Y.first.second != 0) return false;
- if (X.first.second == 0 && Y.first.second == 0) return false;
-
- if (X.first.second->size() > Y.first.second->size()) return true;
- if (X.first.second->size() < Y.first.second->size()) return false;
-#endif
- return false;
- }
- };
-}
-
-static void inline printMSTEdge(ProfileInfo::EdgeWeight E,
- const char *M) {
- DEBUG(errs() << "--Edge " << E.first
- <<" (Weight "<< format("%g",E.second) << ") "
- << (M) << "\n");
-}
-
-// MaximumSpanningTree() - Takes a function and returns a spanning tree
-// according to the currently active profiling information, the leaf edges are
-// NOT in the MST. MaximumSpanningTree uses the algorithm of Kruskal.
-MaximumSpanningTree::MaximumSpanningTree(Function *F, ProfileInfo *PI,
- bool inverted = false) {
-
- // Copy edges to vector, sort them biggest first.
- ProfileInfo::EdgeWeights ECs = PI->getEdgeWeights(F);
- std::vector<ProfileInfo::EdgeWeight> EdgeVector(ECs.begin(), ECs.end());
- std::sort(EdgeVector.begin(), EdgeVector.end(), EdgeWeightCompare());
-
- // Create spanning tree, Forest contains a special data structure
- // that makes checking if two nodes are already in a common (sub-)tree
- // fast and cheap.
- EquivalenceClasses<const BasicBlock*> Forest;
- for (std::vector<ProfileInfo::EdgeWeight>::iterator bbi = EdgeVector.begin(),
- bbe = EdgeVector.end(); bbi != bbe; ++bbi) {
- Forest.insert(bbi->first.first);
- Forest.insert(bbi->first.second);
- }
- Forest.insert(0);
-
- // Iterate over the sorted edges, biggest first.
- for (std::vector<ProfileInfo::EdgeWeight>::iterator bbi = EdgeVector.begin(),
- bbe = EdgeVector.end(); bbi != bbe; ++bbi) {
- ProfileInfo::Edge e = (*bbi).first;
-
- if (Forest.findLeader(e.first) != Forest.findLeader(e.second)) {
- Forest.unionSets(e.first, e.second);
- // So we know now that the edge is not already in a subtree (and not
- // (0,entry)), so we push the edge to the MST if it has some successors.
- if (!inverted) { MST.push_back(e); }
- printMSTEdge(*bbi,"in MST");
- } else {
- // This edge is either (0,entry) or (BB,0) or would create a circle in a
- // subtree.
- if (inverted) { MST.push_back(e); }
- printMSTEdge(*bbi,"*not* in MST");
- }
- }
-
- // Sort the MST edges.
- std::stable_sort(MST.begin(),MST.end());
-}
-
-MaximumSpanningTree::MaxSpanTree::iterator MaximumSpanningTree::begin() {
- return MST.begin();
-}
-
-MaximumSpanningTree::MaxSpanTree::iterator MaximumSpanningTree::end() {
- return MST.end();
-}
-
-void MaximumSpanningTree::dump() {
- errs()<<"{";
- for ( MaxSpanTree::iterator ei = MST.begin(), ee = MST.end();
- ei!=ee; ++ei ) {
- errs()<<"("<<((*ei).first?(*ei).first->getNameStr():"0")<<",";
- errs()<<(*ei).second->getNameStr()<<")";
- }
- errs()<<"}\n";
-}
diff --git a/libclamav/c++/llvm/lib/Transforms/Instrumentation/MaximumSpanningTree.h b/libclamav/c++/llvm/lib/Transforms/Instrumentation/MaximumSpanningTree.h
index 5ef8659..2951dbc 100644
--- a/libclamav/c++/llvm/lib/Transforms/Instrumentation/MaximumSpanningTree.h
+++ b/libclamav/c++/llvm/lib/Transforms/Instrumentation/MaximumSpanningTree.h
@@ -7,43 +7,87 @@
//
//===----------------------------------------------------------------------===//
//
-// This module privides means for calculating a maximum spanning tree for the
-// CFG of a function according to a given profile.
+// This module privides means for calculating a maximum spanning tree for a
+// given set of weighted edges. The type parameter T is the type of a node.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_ANALYSIS_MAXIMUMSPANNINGTREE_H
#define LLVM_ANALYSIS_MAXIMUMSPANNINGTREE_H
-#include "llvm/Analysis/ProfileInfo.h"
-#include "llvm/Support/raw_ostream.h"
+#include "llvm/ADT/EquivalenceClasses.h"
#include <vector>
+#include <algorithm>
namespace llvm {
- class Function;
+ /// MaximumSpanningTree - A MST implementation.
+ /// The type parameter T determines the type of the nodes of the graph.
+ template <typename T>
class MaximumSpanningTree {
- public:
- typedef std::vector<ProfileInfo::Edge> MaxSpanTree;
+ // A comparing class for comparing weighted edges.
+ template <typename CT>
+ struct EdgeWeightCompare {
+ bool operator()(typename MaximumSpanningTree<CT>::EdgeWeight X,
+ typename MaximumSpanningTree<CT>::EdgeWeight Y) const {
+ if (X.second > Y.second) return true;
+ if (X.second < Y.second) return false;
+ return false;
+ }
+ };
+
+ public:
+ typedef std::pair<const T*, const T*> Edge;
+ typedef std::pair<Edge, double> EdgeWeight;
+ typedef std::vector<EdgeWeight> EdgeWeights;
protected:
+ typedef std::vector<Edge> MaxSpanTree;
+
MaxSpanTree MST;
public:
static char ID; // Class identification, replacement for typeinfo
- // MaxSpanTree() - Calculates a MST for a function according to a profile.
- // If inverted is true, all the edges *not* in the MST are returned. As a
- // special also all leaf edges of the MST are not included, this makes it
- // easier for the OptimalEdgeProfileInstrumentation to use this MST to do
- // an optimal profiling.
- MaximumSpanningTree(Function *F, ProfileInfo *PI, bool invert);
- virtual ~MaximumSpanningTree() {}
+ /// MaximumSpanningTree() - Takes a vector of weighted edges and returns a
+ /// spanning tree.
+ MaximumSpanningTree(EdgeWeights &EdgeVector) {
+
+ std::stable_sort(EdgeVector.begin(), EdgeVector.end(), EdgeWeightCompare<T>());
+
+ // Create spanning tree, Forest contains a special data structure
+ // that makes checking if two nodes are already in a common (sub-)tree
+ // fast and cheap.
+ EquivalenceClasses<const T*> Forest;
+ for (typename EdgeWeights::iterator EWi = EdgeVector.begin(),
+ EWe = EdgeVector.end(); EWi != EWe; ++EWi) {
+ Edge e = (*EWi).first;
+
+ Forest.insert(e.first);
+ Forest.insert(e.second);
+ }
+
+ // Iterate over the sorted edges, biggest first.
+ for (typename EdgeWeights::iterator EWi = EdgeVector.begin(),
+ EWe = EdgeVector.end(); EWi != EWe; ++EWi) {
+ Edge e = (*EWi).first;
+
+ if (Forest.findLeader(e.first) != Forest.findLeader(e.second)) {
+ Forest.unionSets(e.first, e.second);
+ // So we know now that the edge is not already in a subtree, so we push
+ // the edge to the MST.
+ MST.push_back(e);
+ }
+ }
+ }
- virtual MaxSpanTree::iterator begin();
- virtual MaxSpanTree::iterator end();
+ typename MaxSpanTree::iterator begin() {
+ return MST.begin();
+ }
- virtual void dump();
+ typename MaxSpanTree::iterator end() {
+ return MST.end();
+ }
};
} // End llvm namespace
diff --git a/libclamav/c++/llvm/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp b/libclamav/c++/llvm/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp
new file mode 100644
index 0000000..b2e6747
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp
@@ -0,0 +1,219 @@
+//===- OptimalEdgeProfiling.cpp - Insert counters for opt. edge profiling -===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass instruments the specified program with counters for edge profiling.
+// Edge profiling can give a reasonable approximation of the hot paths through a
+// program, and is used for a wide variety of program transformations.
+//
+//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "insert-optimal-edge-profiling"
+#include "ProfilingUtils.h"
+#include "llvm/Module.h"
+#include "llvm/Pass.h"
+#include "llvm/Analysis/Passes.h"
+#include "llvm/Analysis/ProfileInfo.h"
+#include "llvm/Analysis/ProfileInfoLoader.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Transforms/Utils/BasicBlockUtils.h"
+#include "llvm/Transforms/Instrumentation.h"
+#include "llvm/ADT/DenseSet.h"
+#include "llvm/ADT/Statistic.h"
+#include "MaximumSpanningTree.h"
+#include <set>
+using namespace llvm;
+
+STATISTIC(NumEdgesInserted, "The # of edges inserted.");
+
+namespace {
+ class VISIBILITY_HIDDEN OptimalEdgeProfiler : public ModulePass {
+ bool runOnModule(Module &M);
+ public:
+ static char ID; // Pass identification, replacement for typeid
+ OptimalEdgeProfiler() : ModulePass(&ID) {}
+
+ void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequiredID(ProfileEstimatorPassID);
+ AU.addRequired<ProfileInfo>();
+ }
+
+ virtual const char *getPassName() const {
+ return "Optimal Edge Profiler";
+ }
+ };
+}
+
+char OptimalEdgeProfiler::ID = 0;
+static RegisterPass<OptimalEdgeProfiler>
+X("insert-optimal-edge-profiling",
+ "Insert optimal instrumentation for edge profiling");
+
+ModulePass *llvm::createOptimalEdgeProfilerPass() {
+ return new OptimalEdgeProfiler();
+}
+
+inline static void printEdgeCounter(ProfileInfo::Edge e,
+ BasicBlock* b,
+ unsigned i) {
+ DEBUG(errs() << "--Edge Counter for " << (e) << " in " \
+ << ((b)?(b)->getNameStr():"0") << " (# " << (i) << ")\n");
+}
+
+bool OptimalEdgeProfiler::runOnModule(Module &M) {
+ Function *Main = M.getFunction("main");
+ if (Main == 0) {
+ errs() << "WARNING: cannot insert edge profiling into a module"
+ << " with no main function!\n";
+ return false; // No main, no instrumentation!
+ }
+
+ // NumEdges counts all the edges that may be instrumented. Later on its
+ // decided which edges to actually instrument, to achieve optimal profiling.
+ // For the entry block a virtual edge (0,entry) is reserved, for each block
+ // with no successors an edge (BB,0) is reserved. These edges are necessary
+ // to calculate a truly optimal maximum spanning tree and thus an optimal
+ // instrumentation.
+ unsigned NumEdges = 0;
+
+ for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
+ if (F->isDeclaration()) continue;
+ // Reserve space for (0,entry) edge.
+ ++NumEdges;
+ for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
+ // Keep track of which blocks need to be instrumented. We don't want to
+ // instrument blocks that are added as the result of breaking critical
+ // edges!
+ if (BB->getTerminator()->getNumSuccessors() == 0) {
+ // Reserve space for (BB,0) edge.
+ ++NumEdges;
+ } else {
+ NumEdges += BB->getTerminator()->getNumSuccessors();
+ }
+ }
+ }
+
+ // In the profiling output a counter for each edge is reserved, but only few
+ // are used. This is done to be able to read back in the profile without
+ // calulating the maximum spanning tree again, instead each edge counter that
+ // is not used is initialised with -1 to signal that this edge counter has to
+ // be calculated from other edge counters on reading the profile info back
+ // in.
+
+ const Type *Int32 = Type::getInt32Ty(M.getContext());
+ const ArrayType *ATy = ArrayType::get(Int32, NumEdges);
+ GlobalVariable *Counters =
+ new GlobalVariable(M, ATy, false, GlobalValue::InternalLinkage,
+ Constant::getNullValue(ATy), "OptEdgeProfCounters");
+ NumEdgesInserted = 0;
+
+ std::vector<Constant*> Initializer(NumEdges);
+ Constant* Zero = ConstantInt::get(Int32, 0);
+ Constant* Uncounted = ConstantInt::get(Int32, ProfileInfoLoader::Uncounted);
+
+ // Instrument all of the edges not in MST...
+ unsigned i = 0;
+ for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
+ if (F->isDeclaration()) continue;
+ DEBUG(errs()<<"Working on "<<F->getNameStr()<<"\n");
+
+ // Calculate a Maximum Spanning Tree with the edge weights determined by
+ // ProfileEstimator. ProfileEstimator also assign weights to the virtual
+ // edges (0,entry) and (BB,0) (for blocks with no successors) and this
+ // edges also participate in the maximum spanning tree calculation.
+ // The third parameter of MaximumSpanningTree() has the effect that not the
+ // actual MST is returned but the edges _not_ in the MST.
+
+ ProfileInfo::EdgeWeights ECs =
+ getAnalysisID<ProfileInfo>(ProfileEstimatorPassID, *F).getEdgeWeights(F);
+ std::vector<ProfileInfo::EdgeWeight> EdgeVector(ECs.begin(), ECs.end());
+ MaximumSpanningTree<BasicBlock> MST (EdgeVector);
+ std::stable_sort(MST.begin(),MST.end());
+
+ // Check if (0,entry) not in the MST. If not, instrument edge
+ // (IncrementCounterInBlock()) and set the counter initially to zero, if
+ // the edge is in the MST the counter is initialised to -1.
+
+ BasicBlock *entry = &(F->getEntryBlock());
+ ProfileInfo::Edge edge = ProfileInfo::getEdge(0,entry);
+ if (!std::binary_search(MST.begin(), MST.end(), edge)) {
+ printEdgeCounter(edge,entry,i);
+ IncrementCounterInBlock(entry, i, Counters); NumEdgesInserted++;
+ Initializer[i++] = (Zero);
+ } else{
+ Initializer[i++] = (Uncounted);
+ }
+
+ // InsertedBlocks contains all blocks that were inserted for splitting an
+ // edge, this blocks do not have to be instrumented.
+ DenseSet<BasicBlock*> InsertedBlocks;
+ for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
+ // Check if block was not inserted and thus does not have to be
+ // instrumented.
+ if (InsertedBlocks.count(BB)) continue;
+
+ // Okay, we have to add a counter of each outgoing edge not in MST. If
+ // the outgoing edge is not critical don't split it, just insert the
+ // counter in the source or destination of the edge. Also, if the block
+ // has no successors, the virtual edge (BB,0) is processed.
+ TerminatorInst *TI = BB->getTerminator();
+ if (TI->getNumSuccessors() == 0) {
+ ProfileInfo::Edge edge = ProfileInfo::getEdge(BB,0);
+ if (!std::binary_search(MST.begin(), MST.end(), edge)) {
+ printEdgeCounter(edge,BB,i);
+ IncrementCounterInBlock(BB, i, Counters); NumEdgesInserted++;
+ Initializer[i++] = (Zero);
+ } else{
+ Initializer[i++] = (Uncounted);
+ }
+ }
+ for (unsigned s = 0, e = TI->getNumSuccessors(); s != e; ++s) {
+ BasicBlock *Succ = TI->getSuccessor(s);
+ ProfileInfo::Edge edge = ProfileInfo::getEdge(BB,Succ);
+ if (!std::binary_search(MST.begin(), MST.end(), edge)) {
+
+ // If the edge is critical, split it.
+ bool wasInserted = SplitCriticalEdge(TI, s, this);
+ Succ = TI->getSuccessor(s);
+ if (wasInserted)
+ InsertedBlocks.insert(Succ);
+
+ // Okay, we are guaranteed that the edge is no longer critical. If
+ // we only have a single successor, insert the counter in this block,
+ // otherwise insert it in the successor block.
+ if (TI->getNumSuccessors() == 1) {
+ // Insert counter at the start of the block
+ printEdgeCounter(edge,BB,i);
+ IncrementCounterInBlock(BB, i, Counters); NumEdgesInserted++;
+ } else {
+ // Insert counter at the start of the block
+ printEdgeCounter(edge,Succ,i);
+ IncrementCounterInBlock(Succ, i, Counters); NumEdgesInserted++;
+ }
+ Initializer[i++] = (Zero);
+ } else {
+ Initializer[i++] = (Uncounted);
+ }
+ }
+ }
+ }
+
+ // Check if the number of edges counted at first was the number of edges we
+ // considered for instrumentation.
+ assert(i==NumEdges && "the number of edges in counting array is wrong");
+
+ // Assing the now completely defined initialiser to the array.
+ Constant *init = ConstantArray::get(ATy, Initializer);
+ Counters->setInitializer(init);
+
+ // Add the initialization call to main.
+ InsertProfilingInitCall(Main, "llvm_start_opt_edge_profiling", Counters);
+ return true;
+}
+
diff --git a/libclamav/c++/llvm/lib/Transforms/Instrumentation/RSProfiling.cpp b/libclamav/c++/llvm/lib/Transforms/Instrumentation/RSProfiling.cpp
index 9997d9d..3b72260 100644
--- a/libclamav/c++/llvm/lib/Transforms/Instrumentation/RSProfiling.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Instrumentation/RSProfiling.cpp
@@ -397,7 +397,7 @@ Value* ProfilerRS::Translate(Value* v) {
return i;
} else {
//translate this
- Instruction* i2 = i->clone(v->getContext());
+ Instruction* i2 = i->clone();
if (i->hasName())
i2->setName("dup_" + i->getName());
TransCache[i] = i2;
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/ADCE.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/ADCE.cpp
index 9c55f66..37f383f 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/ADCE.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/ADCE.cpp
@@ -21,19 +21,17 @@
#include "llvm/IntrinsicInst.h"
#include "llvm/Pass.h"
#include "llvm/Support/CFG.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/InstIterator.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
-
using namespace llvm;
STATISTIC(NumRemoved, "Number of instructions removed");
namespace {
- struct VISIBILITY_HIDDEN ADCE : public FunctionPass {
+ struct ADCE : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
ADCE() : FunctionPass(&ID) {}
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/BasicBlockPlacement.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/BasicBlockPlacement.cpp
index 95fd67b..54533f5 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/BasicBlockPlacement.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/BasicBlockPlacement.cpp
@@ -31,7 +31,6 @@
#include "llvm/Function.h"
#include "llvm/Pass.h"
#include "llvm/Support/CFG.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Transforms/Scalar.h"
#include <set>
@@ -40,7 +39,7 @@ using namespace llvm;
STATISTIC(NumMoved, "Number of basic blocks moved");
namespace {
- struct VISIBILITY_HIDDEN BlockPlacement : public FunctionPass {
+ struct BlockPlacement : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
BlockPlacement() : FunctionPass(&ID) {}
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/CMakeLists.txt b/libclamav/c++/llvm/lib/Transforms/Scalar/CMakeLists.txt
index 8a8f83f..7f516b7 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/CMakeLists.txt
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/CMakeLists.txt
@@ -1,13 +1,13 @@
add_llvm_library(LLVMScalarOpts
ADCE.cpp
BasicBlockPlacement.cpp
+ CodeGenLICM.cpp
CodeGenPrepare.cpp
CondPropagate.cpp
ConstantProp.cpp
DCE.cpp
DeadStoreElimination.cpp
GVN.cpp
- GVNPRE.cpp
IndVarSimplify.cpp
InstructionCombining.cpp
JumpThreading.cpp
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/CodeGenLICM.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/CodeGenLICM.cpp
new file mode 100644
index 0000000..9f1d148
--- /dev/null
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/CodeGenLICM.cpp
@@ -0,0 +1,112 @@
+//===- CodeGenLICM.cpp - LICM a function for code generation --------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This function performs late LICM, hoisting constants out of loops that
+// are not valid immediates. It should not be followed by instcombine,
+// because instcombine would quickly stuff the constants back into the loop.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "codegen-licm"
+#include "llvm/Transforms/Scalar.h"
+#include "llvm/Constants.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/Instructions.h"
+#include "llvm/IntrinsicInst.h"
+#include "llvm/LLVMContext.h"
+#include "llvm/Analysis/LoopPass.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/ScalarEvolution.h"
+#include "llvm/Analysis/IVUsers.h"
+#include "llvm/ADT/DenseMap.h"
+using namespace llvm;
+
+namespace {
+ class CodeGenLICM : public LoopPass {
+ virtual bool runOnLoop(Loop *L, LPPassManager &LPM);
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const;
+ public:
+ static char ID; // Pass identification, replacement for typeid
+ explicit CodeGenLICM() : LoopPass(&ID) {}
+ };
+}
+
+char CodeGenLICM::ID = 0;
+static RegisterPass<CodeGenLICM> X("codegen-licm",
+ "hoist constants out of loops");
+
+Pass *llvm::createCodeGenLICMPass() {
+ return new CodeGenLICM();
+}
+
+bool CodeGenLICM::runOnLoop(Loop *L, LPPassManager &) {
+ bool Changed = false;
+
+ // Only visit outermost loops.
+ if (L->getParentLoop()) return Changed;
+
+ Instruction *PreheaderTerm = L->getLoopPreheader()->getTerminator();
+ DenseMap<Constant *, BitCastInst *> HoistedConstants;
+
+ for (Loop::block_iterator I = L->block_begin(), E = L->block_end();
+ I != E; ++I) {
+ BasicBlock *BB = *I;
+ for (BasicBlock::iterator BBI = BB->begin(), BBE = BB->end();
+ BBI != BBE; ++BBI) {
+ Instruction *I = BBI;
+ // TODO: For now, skip all intrinsic instructions, because some of them
+ // can require their operands to be constants, and we don't want to
+ // break that.
+ if (isa<IntrinsicInst>(I))
+ continue;
+ // LLVM represents fneg as -0.0-x; don't hoist the -0.0 out.
+ if (BinaryOperator::isFNeg(I) ||
+ BinaryOperator::isNeg(I) ||
+ BinaryOperator::isNot(I))
+ continue;
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
+ // Don't hoist out switch case constants.
+ if (isa<SwitchInst>(I) && i == 1)
+ break;
+ // Don't hoist out shuffle masks.
+ if (isa<ShuffleVectorInst>(I) && i == 2)
+ break;
+ Value *Op = I->getOperand(i);
+ Constant *C = dyn_cast<Constant>(Op);
+ if (!C) continue;
+ // TODO: Ask the target which constants are legal. This would allow
+ // us to add support for hoisting ConstantInts and GlobalValues too.
+ if (isa<ConstantFP>(C) ||
+ isa<ConstantVector>(C) ||
+ isa<ConstantAggregateZero>(C)) {
+ BitCastInst *&BC = HoistedConstants[C];
+ if (!BC)
+ BC = new BitCastInst(C, C->getType(), "hoist", PreheaderTerm);
+ I->setOperand(i, BC);
+ Changed = true;
+ }
+ }
+ }
+ }
+
+ return Changed;
+}
+
+void CodeGenLICM::getAnalysisUsage(AnalysisUsage &AU) const {
+ // This pass preserves just about everything. List some popular things here.
+ AU.setPreservesCFG();
+ AU.addPreservedID(LoopSimplifyID);
+ AU.addPreserved<LoopInfo>();
+ AU.addPreserved<AliasAnalysis>();
+ AU.addPreserved<ScalarEvolution>();
+ AU.addPreserved<IVUsers>();
+
+ // Hoisting requires a loop preheader.
+ AU.addRequiredID(LoopSimplifyID);
+}
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/CodeGenPrepare.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/CodeGenPrepare.cpp
index 566abd8..a3e3fea 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/CodeGenPrepare.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/CodeGenPrepare.cpp
@@ -23,6 +23,7 @@
#include "llvm/IntrinsicInst.h"
#include "llvm/LLVMContext.h"
#include "llvm/Pass.h"
+#include "llvm/Analysis/ProfileInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Transforms/Utils/AddrModeMatcher.h"
@@ -33,7 +34,6 @@
#include "llvm/Assembly/Writer.h"
#include "llvm/Support/CallSite.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/Support/PatternMatch.h"
@@ -45,10 +45,11 @@ static cl::opt<bool> FactorCommonPreds("split-critical-paths-tweak",
cl::init(false), cl::Hidden);
namespace {
- class VISIBILITY_HIDDEN CodeGenPrepare : public FunctionPass {
+ class CodeGenPrepare : public FunctionPass {
/// TLI - Keep a pointer of a TargetLowering to consult for determining
/// transformation profitability.
const TargetLowering *TLI;
+ ProfileInfo *PI;
/// BackEdges - Keep a set of all the loop back edges.
///
@@ -59,6 +60,10 @@ namespace {
: FunctionPass(&ID), TLI(tli) {}
bool runOnFunction(Function &F);
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addPreserved<ProfileInfo>();
+ }
+
private:
bool EliminateMostlyEmptyBlocks(Function &F);
bool CanMergeBlocks(const BasicBlock *BB, const BasicBlock *DestBB) const;
@@ -94,6 +99,7 @@ void CodeGenPrepare::findLoopBackEdges(const Function &F) {
bool CodeGenPrepare::runOnFunction(Function &F) {
bool EverMadeChange = false;
+ PI = getAnalysisIfAvailable<ProfileInfo>();
// First pass, eliminate blocks that contain only PHI nodes and an
// unconditional branch.
EverMadeChange |= EliminateMostlyEmptyBlocks(F);
@@ -240,7 +246,7 @@ void CodeGenPrepare::EliminateMostlyEmptyBlock(BasicBlock *BB) {
// Remember if SinglePred was the entry block of the function. If so, we
// will need to move BB back to the entry position.
bool isEntry = SinglePred == &SinglePred->getParent()->getEntryBlock();
- MergeBasicBlockIntoOnlyPred(DestBB);
+ MergeBasicBlockIntoOnlyPred(DestBB, this);
if (isEntry && BB != &BB->getParent()->getEntryBlock())
BB->moveBefore(&BB->getParent()->getEntryBlock());
@@ -282,6 +288,10 @@ void CodeGenPrepare::EliminateMostlyEmptyBlock(BasicBlock *BB) {
// The PHIs are now updated, change everything that refers to BB to use
// DestBB and remove BB.
BB->replaceAllUsesWith(DestBB);
+ if (PI) {
+ PI->replaceAllUses(BB, DestBB);
+ PI->removeEdge(ProfileInfo::getEdge(BB, DestBB));
+ }
BB->eraseFromParent();
DEBUG(errs() << "AFTER:\n" << *DestBB << "\n\n\n");
@@ -357,6 +367,9 @@ static void SplitEdgeNicely(TerminatorInst *TI, unsigned SuccNum,
// If we found a workable predecessor, change TI to branch to Succ.
if (FoundMatch) {
+ ProfileInfo *PI = P->getAnalysisIfAvailable<ProfileInfo>();
+ if (PI)
+ PI->splitEdge(TIBB, Dest, Pred);
Dest->removePredecessor(TIBB);
TI->setSuccessor(SuccNum, Pred);
return;
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/CondPropagate.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/CondPropagate.cpp
index 562fc60..5b573f4 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/CondPropagate.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/CondPropagate.cpp
@@ -22,14 +22,13 @@
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/Support/Compiler.h"
using namespace llvm;
STATISTIC(NumBrThread, "Number of CFG edges threaded through branches");
STATISTIC(NumSwThread, "Number of CFG edges threaded through switches");
namespace {
- struct VISIBILITY_HIDDEN CondProp : public FunctionPass {
+ struct CondProp : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
CondProp() : FunctionPass(&ID) {}
@@ -192,8 +191,6 @@ void CondProp::SimplifyPredecessors(SwitchInst *SI) {
if (&*BBI != SI)
return;
- bool RemovedPreds = false;
-
// Ok, we have this really simple case, walk the PHI operands, looking for
// constants. Walk from the end to remove operands from the end when
// possible, and to avoid invalidating "i".
@@ -205,7 +202,6 @@ void CondProp::SimplifyPredecessors(SwitchInst *SI) {
RevectorBlockTo(PN->getIncomingBlock(i-1),
SI->getSuccessor(DestCase));
++NumSwThread;
- RemovedPreds = true;
// If there were two predecessors before this simplification, or if the
// PHI node contained all the same value except for the one we just
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/ConstantProp.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/ConstantProp.cpp
index 2d9d2de..4fee327 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/ConstantProp.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/ConstantProp.cpp
@@ -24,7 +24,6 @@
#include "llvm/Constant.h"
#include "llvm/Instruction.h"
#include "llvm/Pass.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/InstIterator.h"
#include "llvm/ADT/Statistic.h"
#include <set>
@@ -33,7 +32,7 @@ using namespace llvm;
STATISTIC(NumInstKilled, "Number of instructions killed");
namespace {
- struct VISIBILITY_HIDDEN ConstantPropagation : public FunctionPass {
+ struct ConstantPropagation : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
ConstantPropagation() : FunctionPass(&ID) {}
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/DCE.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/DCE.cpp
index 8bb504c..39940c3 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/DCE.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/DCE.cpp
@@ -21,7 +21,6 @@
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Instruction.h"
#include "llvm/Pass.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/InstIterator.h"
#include "llvm/ADT/Statistic.h"
#include <set>
@@ -34,7 +33,7 @@ namespace {
//===--------------------------------------------------------------------===//
// DeadInstElimination pass implementation
//
- struct VISIBILITY_HIDDEN DeadInstElimination : public BasicBlockPass {
+ struct DeadInstElimination : public BasicBlockPass {
static char ID; // Pass identification, replacement for typeid
DeadInstElimination() : BasicBlockPass(&ID) {}
virtual bool runOnBasicBlock(BasicBlock &BB) {
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
index e28ed38..a7b3e75 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
@@ -29,14 +29,13 @@
#include "llvm/Analysis/MemoryDependenceAnalysis.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Transforms/Utils/Local.h"
-#include "llvm/Support/Compiler.h"
using namespace llvm;
STATISTIC(NumFastStores, "Number of stores deleted");
STATISTIC(NumFastOther , "Number of other instrs removed");
namespace {
- struct VISIBILITY_HIDDEN DSE : public FunctionPass {
+ struct DSE : public FunctionPass {
TargetData *TD;
static char ID; // Pass identification, replacement for typeid
@@ -84,7 +83,7 @@ bool DSE::runOnBasicBlock(BasicBlock &BB) {
bool MadeChange = false;
- // Do a top-down walk on the BB
+ // Do a top-down walk on the BB.
for (BasicBlock::iterator BBI = BB.begin(), BBE = BB.end(); BBI != BBE; ) {
Instruction *Inst = BBI++;
@@ -125,7 +124,10 @@ bool DSE::runOnBasicBlock(BasicBlock &BB) {
DeleteDeadInstruction(DepStore);
NumFastStores++;
MadeChange = true;
-
+
+ // DeleteDeadInstruction can delete the current instruction in loop
+ // cases, reset BBI.
+ BBI = Inst;
if (BBI != BB.begin())
--BBI;
continue;
@@ -136,8 +138,15 @@ bool DSE::runOnBasicBlock(BasicBlock &BB) {
if (LoadInst *DepLoad = dyn_cast<LoadInst>(InstDep.getInst())) {
if (SI->getPointerOperand() == DepLoad->getPointerOperand() &&
SI->getOperand(0) == DepLoad) {
+ // DeleteDeadInstruction can delete the current instruction. Save BBI
+ // in case we need it.
+ WeakVH NextInst(BBI);
+
DeleteDeadInstruction(SI);
- if (BBI != BB.begin())
+
+ if (NextInst == 0) // Next instruction deleted.
+ BBI = BB.begin();
+ else if (BBI != BB.begin()) // Revisit this instruction if possible.
--BBI;
NumFastStores++;
MadeChange = true;
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/GVN.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/GVN.cpp
index a667a98..86bbc60 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/GVN.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/GVN.cpp
@@ -23,6 +23,7 @@
#include "llvm/Function.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/LLVMContext.h"
+#include "llvm/Operator.h"
#include "llvm/Value.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DepthFirstIterator.h"
@@ -32,13 +33,15 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/Dominators.h"
#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/MallocHelper.h"
#include "llvm/Analysis/MemoryDependenceAnalysis.h"
#include "llvm/Support/CFG.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetData.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Local.h"
#include <cstdio>
@@ -62,17 +65,17 @@ static cl::opt<bool> EnableLoadPRE("enable-load-pre", cl::init(true));
/// as an efficient mechanism to determine the expression-wise equivalence of
/// two values.
namespace {
- struct VISIBILITY_HIDDEN Expression {
+ struct Expression {
enum ExpressionOpcode { ADD, FADD, SUB, FSUB, MUL, FMUL,
UDIV, SDIV, FDIV, UREM, SREM,
- FREM, SHL, LSHR, ASHR, AND, OR, XOR, ICMPEQ,
- ICMPNE, ICMPUGT, ICMPUGE, ICMPULT, ICMPULE,
- ICMPSGT, ICMPSGE, ICMPSLT, ICMPSLE, FCMPOEQ,
- FCMPOGT, FCMPOGE, FCMPOLT, FCMPOLE, FCMPONE,
- FCMPORD, FCMPUNO, FCMPUEQ, FCMPUGT, FCMPUGE,
+ FREM, SHL, LSHR, ASHR, AND, OR, XOR, ICMPEQ,
+ ICMPNE, ICMPUGT, ICMPUGE, ICMPULT, ICMPULE,
+ ICMPSGT, ICMPSGE, ICMPSLT, ICMPSLE, FCMPOEQ,
+ FCMPOGT, FCMPOGE, FCMPOLT, FCMPOLE, FCMPONE,
+ FCMPORD, FCMPUNO, FCMPUEQ, FCMPUGT, FCMPUGE,
FCMPULT, FCMPULE, FCMPUNE, EXTRACT, INSERT,
SHUFFLE, SELECT, TRUNC, ZEXT, SEXT, FPTOUI,
- FPTOSI, UITOFP, SITOFP, FPTRUNC, FPEXT,
+ FPTOSI, UITOFP, SITOFP, FPTRUNC, FPEXT,
PTRTOINT, INTTOPTR, BITCAST, GEP, CALL, CONSTANT,
EMPTY, TOMBSTONE };
@@ -82,11 +85,11 @@ namespace {
uint32_t secondVN;
uint32_t thirdVN;
SmallVector<uint32_t, 4> varargs;
- Value* function;
-
+ Value *function;
+
Expression() { }
Expression(ExpressionOpcode o) : opcode(o) { }
-
+
bool operator==(const Expression &other) const {
if (opcode != other.opcode)
return false;
@@ -105,30 +108,30 @@ namespace {
else {
if (varargs.size() != other.varargs.size())
return false;
-
+
for (size_t i = 0; i < varargs.size(); ++i)
if (varargs[i] != other.varargs[i])
return false;
-
+
return true;
}
}
-
+
bool operator!=(const Expression &other) const {
return !(*this == other);
}
};
-
- class VISIBILITY_HIDDEN ValueTable {
+
+ class ValueTable {
private:
DenseMap<Value*, uint32_t> valueNumbering;
DenseMap<Expression, uint32_t> expressionNumbering;
AliasAnalysis* AA;
MemoryDependenceAnalysis* MD;
DominatorTree* DT;
-
+
uint32_t nextValueNumber;
-
+
Expression::ExpressionOpcode getOpcode(BinaryOperator* BO);
Expression::ExpressionOpcode getOpcode(CmpInst* C);
Expression::ExpressionOpcode getOpcode(CastInst* C);
@@ -144,11 +147,11 @@ namespace {
Expression create_expression(Constant* C);
public:
ValueTable() : nextValueNumber(1) { }
- uint32_t lookup_or_add(Value* V);
- uint32_t lookup(Value* V) const;
- void add(Value* V, uint32_t num);
+ uint32_t lookup_or_add(Value *V);
+ uint32_t lookup(Value *V) const;
+ void add(Value *V, uint32_t num);
void clear();
- void erase(Value* v);
+ void erase(Value *v);
unsigned size();
void setAliasAnalysis(AliasAnalysis* A) { AA = A; }
AliasAnalysis *getAliasAnalysis() const { return AA; }
@@ -164,30 +167,30 @@ template <> struct DenseMapInfo<Expression> {
static inline Expression getEmptyKey() {
return Expression(Expression::EMPTY);
}
-
+
static inline Expression getTombstoneKey() {
return Expression(Expression::TOMBSTONE);
}
-
+
static unsigned getHashValue(const Expression e) {
unsigned hash = e.opcode;
-
+
hash = e.firstVN + hash * 37;
hash = e.secondVN + hash * 37;
hash = e.thirdVN + hash * 37;
-
+
hash = ((unsigned)((uintptr_t)e.type >> 4) ^
(unsigned)((uintptr_t)e.type >> 9)) +
hash * 37;
-
+
for (SmallVector<uint32_t, 4>::const_iterator I = e.varargs.begin(),
E = e.varargs.end(); I != E; ++I)
hash = *I + hash * 37;
-
+
hash = ((unsigned)((uintptr_t)e.function >> 4) ^
(unsigned)((uintptr_t)e.function >> 9)) +
hash * 37;
-
+
return hash;
}
static bool isEqual(const Expression &LHS, const Expression &RHS) {
@@ -284,126 +287,126 @@ Expression::ExpressionOpcode ValueTable::getOpcode(CastInst* C) {
Expression ValueTable::create_expression(CallInst* C) {
Expression e;
-
+
e.type = C->getType();
e.firstVN = 0;
e.secondVN = 0;
e.thirdVN = 0;
e.function = C->getCalledFunction();
e.opcode = Expression::CALL;
-
+
for (CallInst::op_iterator I = C->op_begin()+1, E = C->op_end();
I != E; ++I)
e.varargs.push_back(lookup_or_add(*I));
-
+
return e;
}
Expression ValueTable::create_expression(BinaryOperator* BO) {
Expression e;
-
+
e.firstVN = lookup_or_add(BO->getOperand(0));
e.secondVN = lookup_or_add(BO->getOperand(1));
e.thirdVN = 0;
e.function = 0;
e.type = BO->getType();
e.opcode = getOpcode(BO);
-
+
return e;
}
Expression ValueTable::create_expression(CmpInst* C) {
Expression e;
-
+
e.firstVN = lookup_or_add(C->getOperand(0));
e.secondVN = lookup_or_add(C->getOperand(1));
e.thirdVN = 0;
e.function = 0;
e.type = C->getType();
e.opcode = getOpcode(C);
-
+
return e;
}
Expression ValueTable::create_expression(CastInst* C) {
Expression e;
-
+
e.firstVN = lookup_or_add(C->getOperand(0));
e.secondVN = 0;
e.thirdVN = 0;
e.function = 0;
e.type = C->getType();
e.opcode = getOpcode(C);
-
+
return e;
}
Expression ValueTable::create_expression(ShuffleVectorInst* S) {
Expression e;
-
+
e.firstVN = lookup_or_add(S->getOperand(0));
e.secondVN = lookup_or_add(S->getOperand(1));
e.thirdVN = lookup_or_add(S->getOperand(2));
e.function = 0;
e.type = S->getType();
e.opcode = Expression::SHUFFLE;
-
+
return e;
}
Expression ValueTable::create_expression(ExtractElementInst* E) {
Expression e;
-
+
e.firstVN = lookup_or_add(E->getOperand(0));
e.secondVN = lookup_or_add(E->getOperand(1));
e.thirdVN = 0;
e.function = 0;
e.type = E->getType();
e.opcode = Expression::EXTRACT;
-
+
return e;
}
Expression ValueTable::create_expression(InsertElementInst* I) {
Expression e;
-
+
e.firstVN = lookup_or_add(I->getOperand(0));
e.secondVN = lookup_or_add(I->getOperand(1));
e.thirdVN = lookup_or_add(I->getOperand(2));
e.function = 0;
e.type = I->getType();
e.opcode = Expression::INSERT;
-
+
return e;
}
Expression ValueTable::create_expression(SelectInst* I) {
Expression e;
-
+
e.firstVN = lookup_or_add(I->getCondition());
e.secondVN = lookup_or_add(I->getTrueValue());
e.thirdVN = lookup_or_add(I->getFalseValue());
e.function = 0;
e.type = I->getType();
e.opcode = Expression::SELECT;
-
+
return e;
}
Expression ValueTable::create_expression(GetElementPtrInst* G) {
Expression e;
-
+
e.firstVN = lookup_or_add(G->getPointerOperand());
e.secondVN = 0;
e.thirdVN = 0;
e.function = 0;
e.type = G->getType();
e.opcode = Expression::GEP;
-
+
for (GetElementPtrInst::op_iterator I = G->idx_begin(), E = G->idx_end();
I != E; ++I)
e.varargs.push_back(lookup_or_add(*I));
-
+
return e;
}
@@ -412,21 +415,21 @@ Expression ValueTable::create_expression(GetElementPtrInst* G) {
//===----------------------------------------------------------------------===//
/// add - Insert a value into the table with a specified value number.
-void ValueTable::add(Value* V, uint32_t num) {
+void ValueTable::add(Value *V, uint32_t num) {
valueNumbering.insert(std::make_pair(V, num));
}
/// lookup_or_add - Returns the value number for the specified value, assigning
/// it a new number if it did not have one before.
-uint32_t ValueTable::lookup_or_add(Value* V) {
+uint32_t ValueTable::lookup_or_add(Value *V) {
DenseMap<Value*, uint32_t>::iterator VI = valueNumbering.find(V);
if (VI != valueNumbering.end())
return VI->second;
-
+
if (CallInst* C = dyn_cast<CallInst>(V)) {
if (AA->doesNotAccessMemory(C)) {
Expression e = create_expression(C);
-
+
DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
if (EI != expressionNumbering.end()) {
valueNumbering.insert(std::make_pair(V, EI->second));
@@ -434,20 +437,20 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
} else {
expressionNumbering.insert(std::make_pair(e, nextValueNumber));
valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
+
return nextValueNumber++;
}
} else if (AA->onlyReadsMemory(C)) {
Expression e = create_expression(C);
-
+
if (expressionNumbering.find(e) == expressionNumbering.end()) {
expressionNumbering.insert(std::make_pair(e, nextValueNumber));
valueNumbering.insert(std::make_pair(V, nextValueNumber));
return nextValueNumber++;
}
-
+
MemDepResult local_dep = MD->getDependency(C);
-
+
if (!local_dep.isDef() && !local_dep.isNonLocal()) {
valueNumbering.insert(std::make_pair(V, nextValueNumber));
return nextValueNumber++;
@@ -455,12 +458,12 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
if (local_dep.isDef()) {
CallInst* local_cdep = cast<CallInst>(local_dep.getInst());
-
+
if (local_cdep->getNumOperands() != C->getNumOperands()) {
valueNumbering.insert(std::make_pair(V, nextValueNumber));
return nextValueNumber++;
}
-
+
for (unsigned i = 1; i < C->getNumOperands(); ++i) {
uint32_t c_vn = lookup_or_add(C->getOperand(i));
uint32_t cd_vn = lookup_or_add(local_cdep->getOperand(i));
@@ -469,19 +472,19 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
return nextValueNumber++;
}
}
-
+
uint32_t v = lookup_or_add(local_cdep);
valueNumbering.insert(std::make_pair(V, v));
return v;
}
// Non-local case.
- const MemoryDependenceAnalysis::NonLocalDepInfo &deps =
+ const MemoryDependenceAnalysis::NonLocalDepInfo &deps =
MD->getNonLocalCallDependency(CallSite(C));
// FIXME: call/call dependencies for readonly calls should return def, not
// clobber! Move the checking logic to MemDep!
CallInst* cdep = 0;
-
+
// Check to see if we have a single dominating call instruction that is
// identical to C.
for (unsigned i = 0, e = deps.size(); i != e; ++i) {
@@ -496,23 +499,23 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
cdep = 0;
break;
}
-
+
CallInst *NonLocalDepCall = dyn_cast<CallInst>(I->second.getInst());
// FIXME: All duplicated with non-local case.
if (NonLocalDepCall && DT->properlyDominates(I->first, C->getParent())){
cdep = NonLocalDepCall;
continue;
}
-
+
cdep = 0;
break;
}
-
+
if (!cdep) {
valueNumbering.insert(std::make_pair(V, nextValueNumber));
return nextValueNumber++;
}
-
+
if (cdep->getNumOperands() != C->getNumOperands()) {
valueNumbering.insert(std::make_pair(V, nextValueNumber));
return nextValueNumber++;
@@ -525,18 +528,18 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
return nextValueNumber++;
}
}
-
+
uint32_t v = lookup_or_add(cdep);
valueNumbering.insert(std::make_pair(V, v));
return v;
-
+
} else {
valueNumbering.insert(std::make_pair(V, nextValueNumber));
return nextValueNumber++;
}
} else if (BinaryOperator* BO = dyn_cast<BinaryOperator>(V)) {
Expression e = create_expression(BO);
-
+
DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
if (EI != expressionNumbering.end()) {
valueNumbering.insert(std::make_pair(V, EI->second));
@@ -544,12 +547,12 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
} else {
expressionNumbering.insert(std::make_pair(e, nextValueNumber));
valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
+
return nextValueNumber++;
}
} else if (CmpInst* C = dyn_cast<CmpInst>(V)) {
Expression e = create_expression(C);
-
+
DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
if (EI != expressionNumbering.end()) {
valueNumbering.insert(std::make_pair(V, EI->second));
@@ -557,12 +560,12 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
} else {
expressionNumbering.insert(std::make_pair(e, nextValueNumber));
valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
+
return nextValueNumber++;
}
} else if (ShuffleVectorInst* U = dyn_cast<ShuffleVectorInst>(V)) {
Expression e = create_expression(U);
-
+
DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
if (EI != expressionNumbering.end()) {
valueNumbering.insert(std::make_pair(V, EI->second));
@@ -570,12 +573,12 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
} else {
expressionNumbering.insert(std::make_pair(e, nextValueNumber));
valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
+
return nextValueNumber++;
}
} else if (ExtractElementInst* U = dyn_cast<ExtractElementInst>(V)) {
Expression e = create_expression(U);
-
+
DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
if (EI != expressionNumbering.end()) {
valueNumbering.insert(std::make_pair(V, EI->second));
@@ -583,12 +586,12 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
} else {
expressionNumbering.insert(std::make_pair(e, nextValueNumber));
valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
+
return nextValueNumber++;
}
} else if (InsertElementInst* U = dyn_cast<InsertElementInst>(V)) {
Expression e = create_expression(U);
-
+
DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
if (EI != expressionNumbering.end()) {
valueNumbering.insert(std::make_pair(V, EI->second));
@@ -596,12 +599,12 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
} else {
expressionNumbering.insert(std::make_pair(e, nextValueNumber));
valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
+
return nextValueNumber++;
}
} else if (SelectInst* U = dyn_cast<SelectInst>(V)) {
Expression e = create_expression(U);
-
+
DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
if (EI != expressionNumbering.end()) {
valueNumbering.insert(std::make_pair(V, EI->second));
@@ -609,12 +612,12 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
} else {
expressionNumbering.insert(std::make_pair(e, nextValueNumber));
valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
+
return nextValueNumber++;
}
} else if (CastInst* U = dyn_cast<CastInst>(V)) {
Expression e = create_expression(U);
-
+
DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
if (EI != expressionNumbering.end()) {
valueNumbering.insert(std::make_pair(V, EI->second));
@@ -622,12 +625,12 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
} else {
expressionNumbering.insert(std::make_pair(e, nextValueNumber));
valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
+
return nextValueNumber++;
}
} else if (GetElementPtrInst* U = dyn_cast<GetElementPtrInst>(V)) {
Expression e = create_expression(U);
-
+
DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
if (EI != expressionNumbering.end()) {
valueNumbering.insert(std::make_pair(V, EI->second));
@@ -635,7 +638,7 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
} else {
expressionNumbering.insert(std::make_pair(e, nextValueNumber));
valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
+
return nextValueNumber++;
}
} else {
@@ -646,7 +649,7 @@ uint32_t ValueTable::lookup_or_add(Value* V) {
/// lookup - Returns the value number of the specified value. Fails if
/// the value has not yet been numbered.
-uint32_t ValueTable::lookup(Value* V) const {
+uint32_t ValueTable::lookup(Value *V) const {
DenseMap<Value*, uint32_t>::iterator VI = valueNumbering.find(V);
assert(VI != valueNumbering.end() && "Value not numbered?");
return VI->second;
@@ -660,7 +663,7 @@ void ValueTable::clear() {
}
/// erase - Remove a value from the value numbering
-void ValueTable::erase(Value* V) {
+void ValueTable::erase(Value *V) {
valueNumbering.erase(V);
}
@@ -678,17 +681,17 @@ void ValueTable::verifyRemoved(const Value *V) const {
//===----------------------------------------------------------------------===//
namespace {
- struct VISIBILITY_HIDDEN ValueNumberScope {
+ struct ValueNumberScope {
ValueNumberScope* parent;
DenseMap<uint32_t, Value*> table;
-
+
ValueNumberScope(ValueNumberScope* p) : parent(p) { }
};
}
namespace {
- class VISIBILITY_HIDDEN GVN : public FunctionPass {
+ class GVN : public FunctionPass {
bool runOnFunction(Function &F);
public:
static char ID; // Pass identification, replacement for typeid
@@ -700,43 +703,43 @@ namespace {
ValueTable VN;
DenseMap<BasicBlock*, ValueNumberScope*> localAvail;
-
+
typedef DenseMap<Value*, SmallPtrSet<Instruction*, 4> > PhiMapType;
PhiMapType phiMap;
-
-
+
+
// This transformation requires dominator postdominator info
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<DominatorTree>();
AU.addRequired<MemoryDependenceAnalysis>();
AU.addRequired<AliasAnalysis>();
-
+
AU.addPreserved<DominatorTree>();
AU.addPreserved<AliasAnalysis>();
}
-
+
// Helper fuctions
// FIXME: eliminate or document these better
bool processLoad(LoadInst* L,
SmallVectorImpl<Instruction*> &toErase);
- bool processInstruction(Instruction* I,
+ bool processInstruction(Instruction *I,
SmallVectorImpl<Instruction*> &toErase);
bool processNonLocalLoad(LoadInst* L,
SmallVectorImpl<Instruction*> &toErase);
- bool processBlock(BasicBlock* BB);
- Value *GetValueForBlock(BasicBlock *BB, Instruction* orig,
+ bool processBlock(BasicBlock *BB);
+ Value *GetValueForBlock(BasicBlock *BB, Instruction *orig,
DenseMap<BasicBlock*, Value*> &Phis,
bool top_level = false);
void dump(DenseMap<uint32_t, Value*>& d);
bool iterateOnFunction(Function &F);
- Value* CollapsePhi(PHINode* p);
+ Value *CollapsePhi(PHINode* p);
bool performPRE(Function& F);
- Value* lookupNumber(BasicBlock* BB, uint32_t num);
- Value* AttemptRedundancyElimination(Instruction* orig, unsigned valno);
+ Value *lookupNumber(BasicBlock *BB, uint32_t num);
+ Value *AttemptRedundancyElimination(Instruction *orig, unsigned valno);
void cleanupGlobalSets();
void verifyRemoved(const Instruction *I) const;
};
-
+
char GVN::ID = 0;
}
@@ -756,50 +759,50 @@ void GVN::dump(DenseMap<uint32_t, Value*>& d) {
printf("}\n");
}
-static bool isSafeReplacement(PHINode* p, Instruction* inst) {
+static bool isSafeReplacement(PHINode* p, Instruction *inst) {
if (!isa<PHINode>(inst))
return true;
-
+
for (Instruction::use_iterator UI = p->use_begin(), E = p->use_end();
UI != E; ++UI)
if (PHINode* use_phi = dyn_cast<PHINode>(UI))
if (use_phi->getParent() == inst->getParent())
return false;
-
+
return true;
}
-Value* GVN::CollapsePhi(PHINode* p) {
- Value* constVal = p->hasConstantValue();
- if (!constVal) return 0;
-
- Instruction* inst = dyn_cast<Instruction>(constVal);
- if (!inst)
- return constVal;
-
- if (DT->dominates(inst, p))
- if (isSafeReplacement(p, inst))
- return inst;
+Value *GVN::CollapsePhi(PHINode *PN) {
+ Value *ConstVal = PN->hasConstantValue(DT);
+ if (!ConstVal) return 0;
+
+ Instruction *Inst = dyn_cast<Instruction>(ConstVal);
+ if (!Inst)
+ return ConstVal;
+
+ if (DT->dominates(Inst, PN))
+ if (isSafeReplacement(PN, Inst))
+ return Inst;
return 0;
}
/// GetValueForBlock - Get the value to use within the specified basic block.
/// available values are in Phis.
-Value *GVN::GetValueForBlock(BasicBlock *BB, Instruction* orig,
+Value *GVN::GetValueForBlock(BasicBlock *BB, Instruction *Orig,
DenseMap<BasicBlock*, Value*> &Phis,
- bool top_level) {
-
+ bool TopLevel) {
+
// If we have already computed this value, return the previously computed val.
DenseMap<BasicBlock*, Value*>::iterator V = Phis.find(BB);
- if (V != Phis.end() && !top_level) return V->second;
-
+ if (V != Phis.end() && !TopLevel) return V->second;
+
// If the block is unreachable, just return undef, since this path
// can't actually occur at runtime.
if (!DT->isReachableFromEntry(BB))
- return Phis[BB] = UndefValue::get(orig->getType());
-
+ return Phis[BB] = UndefValue::get(Orig->getType());
+
if (BasicBlock *Pred = BB->getSinglePredecessor()) {
- Value *ret = GetValueForBlock(Pred, orig, Phis);
+ Value *ret = GetValueForBlock(Pred, Orig, Phis);
Phis[BB] = ret;
return ret;
}
@@ -812,35 +815,35 @@ Value *GVN::GetValueForBlock(BasicBlock *BB, Instruction* orig,
NumPreds = ExistingPN->getNumIncomingValues();
else
NumPreds = std::distance(pred_begin(BB), pred_end(BB));
-
+
// Otherwise, the idom is the loop, so we need to insert a PHI node. Do so
// now, then get values to fill in the incoming values for the PHI.
- PHINode *PN = PHINode::Create(orig->getType(), orig->getName()+".rle",
+ PHINode *PN = PHINode::Create(Orig->getType(), Orig->getName()+".rle",
BB->begin());
PN->reserveOperandSpace(NumPreds);
-
+
Phis.insert(std::make_pair(BB, PN));
-
+
// Fill in the incoming values for the block.
for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) {
- Value* val = GetValueForBlock(*PI, orig, Phis);
+ Value *val = GetValueForBlock(*PI, Orig, Phis);
PN->addIncoming(val, *PI);
}
-
- VN.getAliasAnalysis()->copyValue(orig, PN);
-
+
+ VN.getAliasAnalysis()->copyValue(Orig, PN);
+
// Attempt to collapse PHI nodes that are trivially redundant
- Value* v = CollapsePhi(PN);
+ Value *v = CollapsePhi(PN);
if (!v) {
// Cache our phi construction results
- if (LoadInst* L = dyn_cast<LoadInst>(orig))
+ if (LoadInst* L = dyn_cast<LoadInst>(Orig))
phiMap[L->getPointerOperand()].insert(PN);
else
- phiMap[orig].insert(PN);
-
+ phiMap[Orig].insert(PN);
+
return PN;
}
-
+
PN->replaceAllUsesWith(v);
if (isa<PointerType>(v->getType()))
MD->invalidateCachedPointerInfo(v);
@@ -869,11 +872,11 @@ Value *GVN::GetValueForBlock(BasicBlock *BB, Instruction* orig,
/// currently speculating that it will be.
/// 3) we are speculating for this block and have used that to speculate for
/// other blocks.
-static bool IsValueFullyAvailableInBlock(BasicBlock *BB,
+static bool IsValueFullyAvailableInBlock(BasicBlock *BB,
DenseMap<BasicBlock*, char> &FullyAvailableBlocks) {
// Optimistically assume that the block is fully available and check to see
// if we already know about this block in one lookup.
- std::pair<DenseMap<BasicBlock*, char>::iterator, char> IV =
+ std::pair<DenseMap<BasicBlock*, char>::iterator, char> IV =
FullyAvailableBlocks.insert(std::make_pair(BB, 2));
// If the entry already existed for this block, return the precomputed value.
@@ -884,29 +887,29 @@ static bool IsValueFullyAvailableInBlock(BasicBlock *BB,
IV.first->second = 3;
return IV.first->second != 0;
}
-
+
// Otherwise, see if it is fully available in all predecessors.
pred_iterator PI = pred_begin(BB), PE = pred_end(BB);
-
+
// If this block has no predecessors, it isn't live-in here.
if (PI == PE)
goto SpeculationFailure;
-
+
for (; PI != PE; ++PI)
// If the value isn't fully available in one of our predecessors, then it
// isn't fully available in this block either. Undo our previous
// optimistic assumption and bail out.
if (!IsValueFullyAvailableInBlock(*PI, FullyAvailableBlocks))
goto SpeculationFailure;
-
+
return true;
-
+
// SpeculationFailure - If we get here, we found out that this is not, after
// all, a fully-available block. We have a problem if we speculated on this and
// used the speculation to mark other blocks as available.
SpeculationFailure:
char &BBVal = FullyAvailableBlocks[BB];
-
+
// If we didn't speculate on this, just return with it set to false.
if (BBVal == 2) {
BBVal = 0;
@@ -918,7 +921,7 @@ SpeculationFailure:
// 0 if set to one.
SmallVector<BasicBlock*, 32> BBWorklist;
BBWorklist.push_back(BB);
-
+
while (!BBWorklist.empty()) {
BasicBlock *Entry = BBWorklist.pop_back_val();
// Note that this sets blocks to 0 (unavailable) if they happen to not
@@ -928,25 +931,357 @@ SpeculationFailure:
// Mark as unavailable.
EntryVal = 0;
-
+
for (succ_iterator I = succ_begin(Entry), E = succ_end(Entry); I != E; ++I)
BBWorklist.push_back(*I);
}
-
+
return false;
}
+
+/// CanCoerceMustAliasedValueToLoad - Return true if
+/// CoerceAvailableValueToLoadType will succeed.
+static bool CanCoerceMustAliasedValueToLoad(Value *StoredVal,
+ const Type *LoadTy,
+ const TargetData &TD) {
+ // If the loaded or stored value is an first class array or struct, don't try
+ // to transform them. We need to be able to bitcast to integer.
+ if (isa<StructType>(LoadTy) || isa<ArrayType>(LoadTy) ||
+ isa<StructType>(StoredVal->getType()) ||
+ isa<ArrayType>(StoredVal->getType()))
+ return false;
+
+ // The store has to be at least as big as the load.
+ if (TD.getTypeSizeInBits(StoredVal->getType()) <
+ TD.getTypeSizeInBits(LoadTy))
+ return false;
+
+ return true;
+}
+
+
+/// CoerceAvailableValueToLoadType - If we saw a store of a value to memory, and
+/// then a load from a must-aliased pointer of a different type, try to coerce
+/// the stored value. LoadedTy is the type of the load we want to replace and
+/// InsertPt is the place to insert new instructions.
+///
+/// If we can't do it, return null.
+static Value *CoerceAvailableValueToLoadType(Value *StoredVal,
+ const Type *LoadedTy,
+ Instruction *InsertPt,
+ const TargetData &TD) {
+ if (!CanCoerceMustAliasedValueToLoad(StoredVal, LoadedTy, TD))
+ return 0;
+
+ const Type *StoredValTy = StoredVal->getType();
+
+ uint64_t StoreSize = TD.getTypeSizeInBits(StoredValTy);
+ uint64_t LoadSize = TD.getTypeSizeInBits(LoadedTy);
+
+ // If the store and reload are the same size, we can always reuse it.
+ if (StoreSize == LoadSize) {
+ if (isa<PointerType>(StoredValTy) && isa<PointerType>(LoadedTy)) {
+ // Pointer to Pointer -> use bitcast.
+ return new BitCastInst(StoredVal, LoadedTy, "", InsertPt);
+ }
+
+ // Convert source pointers to integers, which can be bitcast.
+ if (isa<PointerType>(StoredValTy)) {
+ StoredValTy = TD.getIntPtrType(StoredValTy->getContext());
+ StoredVal = new PtrToIntInst(StoredVal, StoredValTy, "", InsertPt);
+ }
+
+ const Type *TypeToCastTo = LoadedTy;
+ if (isa<PointerType>(TypeToCastTo))
+ TypeToCastTo = TD.getIntPtrType(StoredValTy->getContext());
+
+ if (StoredValTy != TypeToCastTo)
+ StoredVal = new BitCastInst(StoredVal, TypeToCastTo, "", InsertPt);
+
+ // Cast to pointer if the load needs a pointer type.
+ if (isa<PointerType>(LoadedTy))
+ StoredVal = new IntToPtrInst(StoredVal, LoadedTy, "", InsertPt);
+
+ return StoredVal;
+ }
+
+ // If the loaded value is smaller than the available value, then we can
+ // extract out a piece from it. If the available value is too small, then we
+ // can't do anything.
+ assert(StoreSize >= LoadSize && "CanCoerceMustAliasedValueToLoad fail");
+
+ // Convert source pointers to integers, which can be manipulated.
+ if (isa<PointerType>(StoredValTy)) {
+ StoredValTy = TD.getIntPtrType(StoredValTy->getContext());
+ StoredVal = new PtrToIntInst(StoredVal, StoredValTy, "", InsertPt);
+ }
+
+ // Convert vectors and fp to integer, which can be manipulated.
+ if (!isa<IntegerType>(StoredValTy)) {
+ StoredValTy = IntegerType::get(StoredValTy->getContext(), StoreSize);
+ StoredVal = new BitCastInst(StoredVal, StoredValTy, "", InsertPt);
+ }
+
+ // If this is a big-endian system, we need to shift the value down to the low
+ // bits so that a truncate will work.
+ if (TD.isBigEndian()) {
+ Constant *Val = ConstantInt::get(StoredVal->getType(), StoreSize-LoadSize);
+ StoredVal = BinaryOperator::CreateLShr(StoredVal, Val, "tmp", InsertPt);
+ }
+
+ // Truncate the integer to the right size now.
+ const Type *NewIntTy = IntegerType::get(StoredValTy->getContext(), LoadSize);
+ StoredVal = new TruncInst(StoredVal, NewIntTy, "trunc", InsertPt);
+
+ if (LoadedTy == NewIntTy)
+ return StoredVal;
+
+ // If the result is a pointer, inttoptr.
+ if (isa<PointerType>(LoadedTy))
+ return new IntToPtrInst(StoredVal, LoadedTy, "inttoptr", InsertPt);
+
+ // Otherwise, bitcast.
+ return new BitCastInst(StoredVal, LoadedTy, "bitcast", InsertPt);
+}
+
+/// GetBaseWithConstantOffset - Analyze the specified pointer to see if it can
+/// be expressed as a base pointer plus a constant offset. Return the base and
+/// offset to the caller.
+static Value *GetBaseWithConstantOffset(Value *Ptr, int64_t &Offset,
+ const TargetData &TD) {
+ Operator *PtrOp = dyn_cast<Operator>(Ptr);
+ if (PtrOp == 0) return Ptr;
+
+ // Just look through bitcasts.
+ if (PtrOp->getOpcode() == Instruction::BitCast)
+ return GetBaseWithConstantOffset(PtrOp->getOperand(0), Offset, TD);
+
+ // If this is a GEP with constant indices, we can look through it.
+ GEPOperator *GEP = dyn_cast<GEPOperator>(PtrOp);
+ if (GEP == 0 || !GEP->hasAllConstantIndices()) return Ptr;
+
+ gep_type_iterator GTI = gep_type_begin(GEP);
+ for (User::op_iterator I = GEP->idx_begin(), E = GEP->idx_end(); I != E;
+ ++I, ++GTI) {
+ ConstantInt *OpC = cast<ConstantInt>(*I);
+ if (OpC->isZero()) continue;
+
+ // Handle a struct and array indices which add their offset to the pointer.
+ if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
+ Offset += TD.getStructLayout(STy)->getElementOffset(OpC->getZExtValue());
+ } else {
+ uint64_t Size = TD.getTypeAllocSize(GTI.getIndexedType());
+ Offset += OpC->getSExtValue()*Size;
+ }
+ }
+
+ // Re-sign extend from the pointer size if needed to get overflow edge cases
+ // right.
+ unsigned PtrSize = TD.getPointerSizeInBits();
+ if (PtrSize < 64)
+ Offset = (Offset << (64-PtrSize)) >> (64-PtrSize);
+
+ return GetBaseWithConstantOffset(GEP->getPointerOperand(), Offset, TD);
+}
+
+
+/// AnalyzeLoadFromClobberingStore - This function is called when we have a
+/// memdep query of a load that ends up being a clobbering store. This means
+/// that the store *may* provide bits used by the load but we can't be sure
+/// because the pointers don't mustalias. Check this case to see if there is
+/// anything more we can do before we give up. This returns -1 if we have to
+/// give up, or a byte number in the stored value of the piece that feeds the
+/// load.
+static int AnalyzeLoadFromClobberingStore(LoadInst *L, StoreInst *DepSI,
+ const TargetData &TD) {
+ // If the loaded or stored value is an first class array or struct, don't try
+ // to transform them. We need to be able to bitcast to integer.
+ if (isa<StructType>(L->getType()) || isa<ArrayType>(L->getType()) ||
+ isa<StructType>(DepSI->getOperand(0)->getType()) ||
+ isa<ArrayType>(DepSI->getOperand(0)->getType()))
+ return -1;
+
+ int64_t StoreOffset = 0, LoadOffset = 0;
+ Value *StoreBase =
+ GetBaseWithConstantOffset(DepSI->getPointerOperand(), StoreOffset, TD);
+ Value *LoadBase =
+ GetBaseWithConstantOffset(L->getPointerOperand(), LoadOffset, TD);
+ if (StoreBase != LoadBase)
+ return -1;
+
+ // If the load and store are to the exact same address, they should have been
+ // a must alias. AA must have gotten confused.
+ // FIXME: Study to see if/when this happens.
+ if (LoadOffset == StoreOffset) {
+#if 0
+ errs() << "STORE/LOAD DEP WITH COMMON POINTER MISSED:\n"
+ << "Base = " << *StoreBase << "\n"
+ << "Store Ptr = " << *DepSI->getPointerOperand() << "\n"
+ << "Store Offs = " << StoreOffset << " - " << *DepSI << "\n"
+ << "Load Ptr = " << *L->getPointerOperand() << "\n"
+ << "Load Offs = " << LoadOffset << " - " << *L << "\n\n";
+ errs() << "'" << L->getParent()->getParent()->getName() << "'"
+ << *L->getParent();
+#endif
+ return -1;
+ }
+
+ // If the load and store don't overlap at all, the store doesn't provide
+ // anything to the load. In this case, they really don't alias at all, AA
+ // must have gotten confused.
+ // FIXME: Investigate cases where this bails out, e.g. rdar://7238614. Then
+ // remove this check, as it is duplicated with what we have below.
+ uint64_t StoreSize = TD.getTypeSizeInBits(DepSI->getOperand(0)->getType());
+ uint64_t LoadSize = TD.getTypeSizeInBits(L->getType());
+
+ if ((StoreSize & 7) | (LoadSize & 7))
+ return -1;
+ StoreSize >>= 3; // Convert to bytes.
+ LoadSize >>= 3;
+
+
+ bool isAAFailure = false;
+ if (StoreOffset < LoadOffset) {
+ isAAFailure = StoreOffset+int64_t(StoreSize) <= LoadOffset;
+ } else {
+ isAAFailure = LoadOffset+int64_t(LoadSize) <= StoreOffset;
+ }
+ if (isAAFailure) {
+#if 0
+ errs() << "STORE LOAD DEP WITH COMMON BASE:\n"
+ << "Base = " << *StoreBase << "\n"
+ << "Store Ptr = " << *DepSI->getPointerOperand() << "\n"
+ << "Store Offs = " << StoreOffset << " - " << *DepSI << "\n"
+ << "Load Ptr = " << *L->getPointerOperand() << "\n"
+ << "Load Offs = " << LoadOffset << " - " << *L << "\n\n";
+ errs() << "'" << L->getParent()->getParent()->getName() << "'"
+ << *L->getParent();
+#endif
+ return -1;
+ }
+
+ // If the Load isn't completely contained within the stored bits, we don't
+ // have all the bits to feed it. We could do something crazy in the future
+ // (issue a smaller load then merge the bits in) but this seems unlikely to be
+ // valuable.
+ if (StoreOffset > LoadOffset ||
+ StoreOffset+StoreSize < LoadOffset+LoadSize)
+ return -1;
+
+ // Okay, we can do this transformation. Return the number of bytes into the
+ // store that the load is.
+ return LoadOffset-StoreOffset;
+}
+
+
+/// GetStoreValueForLoad - This function is called when we have a
+/// memdep query of a load that ends up being a clobbering store. This means
+/// that the store *may* provide bits used by the load but we can't be sure
+/// because the pointers don't mustalias. Check this case to see if there is
+/// anything more we can do before we give up.
+static Value *GetStoreValueForLoad(Value *SrcVal, unsigned Offset,
+ const Type *LoadTy,
+ Instruction *InsertPt, const TargetData &TD){
+ LLVMContext &Ctx = SrcVal->getType()->getContext();
+
+ uint64_t StoreSize = TD.getTypeSizeInBits(SrcVal->getType())/8;
+ uint64_t LoadSize = TD.getTypeSizeInBits(LoadTy)/8;
+
+
+ // Compute which bits of the stored value are being used by the load. Convert
+ // to an integer type to start with.
+ if (isa<PointerType>(SrcVal->getType()))
+ SrcVal = new PtrToIntInst(SrcVal, TD.getIntPtrType(Ctx), "tmp", InsertPt);
+ if (!isa<IntegerType>(SrcVal->getType()))
+ SrcVal = new BitCastInst(SrcVal, IntegerType::get(Ctx, StoreSize*8),
+ "tmp", InsertPt);
+
+ // Shift the bits to the least significant depending on endianness.
+ unsigned ShiftAmt;
+ if (TD.isLittleEndian()) {
+ ShiftAmt = Offset*8;
+ } else {
+ ShiftAmt = (StoreSize-LoadSize-Offset)*8;
+ }
+
+ if (ShiftAmt)
+ SrcVal = BinaryOperator::CreateLShr(SrcVal,
+ ConstantInt::get(SrcVal->getType(), ShiftAmt), "tmp", InsertPt);
+
+ if (LoadSize != StoreSize)
+ SrcVal = new TruncInst(SrcVal, IntegerType::get(Ctx, LoadSize*8),
+ "tmp", InsertPt);
+
+ return CoerceAvailableValueToLoadType(SrcVal, LoadTy, InsertPt, TD);
+}
+
+struct AvailableValueInBlock {
+ /// BB - The basic block in question.
+ BasicBlock *BB;
+ /// V - The value that is live out of the block.
+ Value *V;
+ /// Offset - The byte offset in V that is interesting for the load query.
+ unsigned Offset;
+
+ static AvailableValueInBlock get(BasicBlock *BB, Value *V,
+ unsigned Offset = 0) {
+ AvailableValueInBlock Res;
+ Res.BB = BB;
+ Res.V = V;
+ Res.Offset = Offset;
+ return Res;
+ }
+};
+
+/// GetAvailableBlockValues - Given the ValuesPerBlock list, convert all of the
+/// available values to values of the expected LoadTy in their blocks and insert
+/// the new values into BlockReplValues.
+static void
+GetAvailableBlockValues(DenseMap<BasicBlock*, Value*> &BlockReplValues,
+ const SmallVector<AvailableValueInBlock, 16> &ValuesPerBlock,
+ const Type *LoadTy,
+ const TargetData *TD) {
+
+ for (unsigned i = 0, e = ValuesPerBlock.size(); i != e; ++i) {
+ BasicBlock *BB = ValuesPerBlock[i].BB;
+ Value *AvailableVal = ValuesPerBlock[i].V;
+ unsigned Offset = ValuesPerBlock[i].Offset;
+
+ Value *&BlockEntry = BlockReplValues[BB];
+ if (BlockEntry) continue;
+
+ if (AvailableVal->getType() != LoadTy) {
+ assert(TD && "Need target data to handle type mismatch case");
+ AvailableVal = GetStoreValueForLoad(AvailableVal, Offset, LoadTy,
+ BB->getTerminator(), *TD);
+
+ if (Offset) {
+ DEBUG(errs() << "GVN COERCED NONLOCAL VAL:\n"
+ << *ValuesPerBlock[i].V << '\n'
+ << *AvailableVal << '\n' << "\n\n\n");
+ }
+
+
+ DEBUG(errs() << "GVN COERCED NONLOCAL VAL:\n"
+ << *ValuesPerBlock[i].V << '\n'
+ << *AvailableVal << '\n' << "\n\n\n");
+ }
+ BlockEntry = AvailableVal;
+ }
+}
+
/// processNonLocalLoad - Attempt to eliminate a load whose dependencies are
/// non-local by performing PHI construction.
bool GVN::processNonLocalLoad(LoadInst *LI,
SmallVectorImpl<Instruction*> &toErase) {
// Find the non-local dependencies of the load.
- SmallVector<MemoryDependenceAnalysis::NonLocalDepEntry, 64> Deps;
+ SmallVector<MemoryDependenceAnalysis::NonLocalDepEntry, 64> Deps;
MD->getNonLocalPointerDependency(LI->getOperand(0), true, LI->getParent(),
Deps);
//DEBUG(errs() << "INVESTIGATING NONLOCAL LOAD: "
// << Deps.size() << *LI << '\n');
-
+
// If we had to process more than one hundred blocks to find the
// dependencies, this load isn't worth worrying about. Optimizing
// it will be too expensive.
@@ -963,61 +1298,98 @@ bool GVN::processNonLocalLoad(LoadInst *LI,
);
return false;
}
-
+
// Filter out useless results (non-locals, etc). Keep track of the blocks
// where we have a value available in repl, also keep track of whether we see
// dependencies that produce an unknown value for the load (such as a call
// that could potentially clobber the load).
- SmallVector<std::pair<BasicBlock*, Value*>, 16> ValuesPerBlock;
+ SmallVector<AvailableValueInBlock, 16> ValuesPerBlock;
SmallVector<BasicBlock*, 16> UnavailableBlocks;
+
+ const TargetData *TD = 0;
for (unsigned i = 0, e = Deps.size(); i != e; ++i) {
BasicBlock *DepBB = Deps[i].first;
MemDepResult DepInfo = Deps[i].second;
-
+
if (DepInfo.isClobber()) {
+ // If the dependence is to a store that writes to a superset of the bits
+ // read by the load, we can extract the bits we need for the load from the
+ // stored value.
+ if (StoreInst *DepSI = dyn_cast<StoreInst>(DepInfo.getInst())) {
+ if (TD == 0)
+ TD = getAnalysisIfAvailable<TargetData>();
+ if (TD) {
+ int Offset = AnalyzeLoadFromClobberingStore(LI, DepSI, *TD);
+ if (Offset != -1) {
+ ValuesPerBlock.push_back(AvailableValueInBlock::get(DepBB,
+ DepSI->getOperand(0),
+ Offset));
+ continue;
+ }
+ }
+ }
+
+ // FIXME: Handle memset/memcpy.
UnavailableBlocks.push_back(DepBB);
continue;
}
-
+
Instruction *DepInst = DepInfo.getInst();
-
+
// Loading the allocation -> undef.
- if (isa<AllocationInst>(DepInst)) {
- ValuesPerBlock.push_back(std::make_pair(DepBB,
- UndefValue::get(LI->getType())));
+ if (isa<AllocationInst>(DepInst) || isMalloc(DepInst)) {
+ ValuesPerBlock.push_back(AvailableValueInBlock::get(DepBB,
+ UndefValue::get(LI->getType())));
continue;
}
-
- if (StoreInst* S = dyn_cast<StoreInst>(DepInst)) {
- // Reject loads and stores that are to the same address but are of
- // different types.
- // NOTE: 403.gcc does have this case (e.g. in readonly_fields_p) because
- // of bitfield access, it would be interesting to optimize for it at some
- // point.
+
+ if (StoreInst *S = dyn_cast<StoreInst>(DepInst)) {
+ // Reject loads and stores that are to the same address but are of
+ // different types if we have to.
if (S->getOperand(0)->getType() != LI->getType()) {
- UnavailableBlocks.push_back(DepBB);
- continue;
+ if (TD == 0)
+ TD = getAnalysisIfAvailable<TargetData>();
+
+ // If the stored value is larger or equal to the loaded value, we can
+ // reuse it.
+ if (TD == 0 || !CanCoerceMustAliasedValueToLoad(S->getOperand(0),
+ LI->getType(), *TD)) {
+ UnavailableBlocks.push_back(DepBB);
+ continue;
+ }
}
-
- ValuesPerBlock.push_back(std::make_pair(DepBB, S->getOperand(0)));
-
- } else if (LoadInst* LD = dyn_cast<LoadInst>(DepInst)) {
+
+ ValuesPerBlock.push_back(AvailableValueInBlock::get(DepBB,
+ S->getOperand(0)));
+ continue;
+ }
+
+ if (LoadInst *LD = dyn_cast<LoadInst>(DepInst)) {
+ // If the types mismatch and we can't handle it, reject reuse of the load.
if (LD->getType() != LI->getType()) {
- UnavailableBlocks.push_back(DepBB);
- continue;
+ if (TD == 0)
+ TD = getAnalysisIfAvailable<TargetData>();
+
+ // If the stored value is larger or equal to the loaded value, we can
+ // reuse it.
+ if (TD == 0 || !CanCoerceMustAliasedValueToLoad(LD, LI->getType(),*TD)){
+ UnavailableBlocks.push_back(DepBB);
+ continue;
+ }
}
- ValuesPerBlock.push_back(std::make_pair(DepBB, LD));
- } else {
- UnavailableBlocks.push_back(DepBB);
+ ValuesPerBlock.push_back(AvailableValueInBlock::get(DepBB, LD));
continue;
}
+
+ UnavailableBlocks.push_back(DepBB);
+ continue;
}
-
+
// If we have no predecessors that produce a known value for this load, exit
// early.
if (ValuesPerBlock.empty()) return false;
-
+
// If all of the instructions we depend on produce a known value for this
// load, then it is fully redundant and we can use PHI insertion to compute
// its value. Insert PHIs and remove the fully redundant value now.
@@ -1036,27 +1408,30 @@ bool GVN::processNonLocalLoad(LoadInst *LI,
NumGVNLoad++;
return true;
}
-
- ValuesPerBlock.push_back(std::make_pair((*I)->getParent(), *I));
+
+ ValuesPerBlock.push_back(AvailableValueInBlock::get((*I)->getParent(),
+ *I));
}
-
+
DEBUG(errs() << "GVN REMOVING NONLOCAL LOAD: " << *LI << '\n');
-
+
+ // Convert the block information to a map, and insert coersions as needed.
DenseMap<BasicBlock*, Value*> BlockReplValues;
- BlockReplValues.insert(ValuesPerBlock.begin(), ValuesPerBlock.end());
- // Perform PHI construction.
- Value* v = GetValueForBlock(LI->getParent(), LI, BlockReplValues, true);
- LI->replaceAllUsesWith(v);
+ GetAvailableBlockValues(BlockReplValues, ValuesPerBlock, LI->getType(), TD);
- if (isa<PHINode>(v))
- v->takeName(LI);
- if (isa<PointerType>(v->getType()))
- MD->invalidateCachedPointerInfo(v);
+ // Perform PHI construction.
+ Value *V = GetValueForBlock(LI->getParent(), LI, BlockReplValues, true);
+ LI->replaceAllUsesWith(V);
+
+ if (isa<PHINode>(V))
+ V->takeName(LI);
+ if (isa<PointerType>(V->getType()))
+ MD->invalidateCachedPointerInfo(V);
toErase.push_back(LI);
NumGVNLoad++;
return true;
}
-
+
if (!EnablePRE || !EnableLoadPRE)
return false;
@@ -1067,7 +1442,7 @@ bool GVN::processNonLocalLoad(LoadInst *LI,
// prefer to not increase code size. As such, we only do this when we know
// that we only have to insert *one* load (which means we're basically moving
// the load, not inserting a new one).
-
+
SmallPtrSet<BasicBlock *, 4> Blockers;
for (unsigned i = 0, e = UnavailableBlocks.size(); i != e; ++i)
Blockers.insert(UnavailableBlocks[i]);
@@ -1091,28 +1466,28 @@ bool GVN::processNonLocalLoad(LoadInst *LI,
if (TmpBB->getTerminator()->getNumSuccessors() != 1)
allSingleSucc = false;
}
-
+
assert(TmpBB);
LoadBB = TmpBB;
-
+
// If we have a repl set with LI itself in it, this means we have a loop where
// at least one of the values is LI. Since this means that we won't be able
// to eliminate LI even if we insert uses in the other predecessors, we will
// end up increasing code size. Reject this by scanning for LI.
for (unsigned i = 0, e = ValuesPerBlock.size(); i != e; ++i)
- if (ValuesPerBlock[i].second == LI)
+ if (ValuesPerBlock[i].V == LI)
return false;
-
+
if (isSinglePred) {
bool isHot = false;
for (unsigned i = 0, e = ValuesPerBlock.size(); i != e; ++i)
- if (Instruction *I = dyn_cast<Instruction>(ValuesPerBlock[i].second))
- // "Hot" Instruction is in some loop (because it dominates its dep.
- // instruction).
- if (DT->dominates(LI, I)) {
- isHot = true;
- break;
- }
+ if (Instruction *I = dyn_cast<Instruction>(ValuesPerBlock[i].V))
+ // "Hot" Instruction is in some loop (because it dominates its dep.
+ // instruction).
+ if (DT->dominates(LI, I)) {
+ isHot = true;
+ break;
+ }
// We are interested only in "hot" instructions. We don't want to do any
// mis-optimizations here.
@@ -1129,7 +1504,7 @@ bool GVN::processNonLocalLoad(LoadInst *LI,
DenseMap<BasicBlock*, char> FullyAvailableBlocks;
for (unsigned i = 0, e = ValuesPerBlock.size(); i != e; ++i)
- FullyAvailableBlocks[ValuesPerBlock[i].first] = true;
+ FullyAvailableBlocks[ValuesPerBlock[i].BB] = true;
for (unsigned i = 0, e = UnavailableBlocks.size(); i != e; ++i)
FullyAvailableBlocks[UnavailableBlocks[i]] = false;
@@ -1137,20 +1512,20 @@ bool GVN::processNonLocalLoad(LoadInst *LI,
PI != E; ++PI) {
if (IsValueFullyAvailableInBlock(*PI, FullyAvailableBlocks))
continue;
-
+
// If this load is not available in multiple predecessors, reject it.
if (UnavailablePred && UnavailablePred != *PI)
return false;
UnavailablePred = *PI;
}
-
+
assert(UnavailablePred != 0 &&
"Fully available value should be eliminated above!");
-
+
// If the loaded pointer is PHI node defined in this block, do PHI translation
// to get its value in the predecessor.
Value *LoadPtr = LI->getOperand(0)->DoPHITranslation(LoadBB, UnavailablePred);
-
+
// Make sure the value is live in the predecessor. If it was defined by a
// non-PHI instruction in this block, we don't know how to recompute it above.
if (Instruction *LPInst = dyn_cast<Instruction>(LoadPtr))
@@ -1159,7 +1534,7 @@ bool GVN::processNonLocalLoad(LoadInst *LI,
<< *LPInst << '\n' << *LI << "\n");
return false;
}
-
+
// We don't currently handle critical edges :(
if (UnavailablePred->getTerminator()->getNumSuccessors() != 1) {
DEBUG(errs() << "COULD NOT PRE LOAD BECAUSE OF CRITICAL EDGE '"
@@ -1184,27 +1559,27 @@ bool GVN::processNonLocalLoad(LoadInst *LI,
// and using PHI construction to get the value in the other predecessors, do
// it.
DEBUG(errs() << "GVN REMOVING PRE LOAD: " << *LI << '\n');
-
+
Value *NewLoad = new LoadInst(LoadPtr, LI->getName()+".pre", false,
LI->getAlignment(),
UnavailablePred->getTerminator());
-
+
SmallPtrSet<Instruction*, 4> &p = phiMap[LI->getPointerOperand()];
for (SmallPtrSet<Instruction*, 4>::iterator I = p.begin(), E = p.end();
I != E; ++I)
- ValuesPerBlock.push_back(std::make_pair((*I)->getParent(), *I));
-
+ ValuesPerBlock.push_back(AvailableValueInBlock::get((*I)->getParent(), *I));
+
DenseMap<BasicBlock*, Value*> BlockReplValues;
- BlockReplValues.insert(ValuesPerBlock.begin(), ValuesPerBlock.end());
+ GetAvailableBlockValues(BlockReplValues, ValuesPerBlock, LI->getType(), TD);
BlockReplValues[UnavailablePred] = NewLoad;
-
+
// Perform PHI construction.
- Value* v = GetValueForBlock(LI->getParent(), LI, BlockReplValues, true);
- LI->replaceAllUsesWith(v);
- if (isa<PHINode>(v))
- v->takeName(LI);
- if (isa<PointerType>(v->getType()))
- MD->invalidateCachedPointerInfo(v);
+ Value *V = GetValueForBlock(LI->getParent(), LI, BlockReplValues, true);
+ LI->replaceAllUsesWith(V);
+ if (isa<PHINode>(V))
+ V->takeName(LI);
+ if (isa<PointerType>(V->getType()))
+ MD->invalidateCachedPointerInfo(V);
toErase.push_back(LI);
NumPRELoad++;
return true;
@@ -1215,63 +1590,118 @@ bool GVN::processNonLocalLoad(LoadInst *LI,
bool GVN::processLoad(LoadInst *L, SmallVectorImpl<Instruction*> &toErase) {
if (L->isVolatile())
return false;
-
- Value* pointer = L->getPointerOperand();
// ... to a pointer that has been loaded from before...
- MemDepResult dep = MD->getDependency(L);
-
+ MemDepResult Dep = MD->getDependency(L);
+
// If the value isn't available, don't do anything!
- if (dep.isClobber()) {
+ if (Dep.isClobber()) {
+ // FIXME: We should handle memset/memcpy/memmove as dependent instructions
+ // to forward the value if available.
+ //if (isa<MemIntrinsic>(Dep.getInst()))
+ //errs() << "LOAD DEPENDS ON MEM: " << *L << "\n" << *Dep.getInst()<<"\n\n";
+
+ // Check to see if we have something like this:
+ // store i32 123, i32* %P
+ // %A = bitcast i32* %P to i8*
+ // %B = gep i8* %A, i32 1
+ // %C = load i8* %B
+ //
+ // We could do that by recognizing if the clobber instructions are obviously
+ // a common base + constant offset, and if the previous store (or memset)
+ // completely covers this load. This sort of thing can happen in bitfield
+ // access code.
+ if (StoreInst *DepSI = dyn_cast<StoreInst>(Dep.getInst()))
+ if (const TargetData *TD = getAnalysisIfAvailable<TargetData>()) {
+ int Offset = AnalyzeLoadFromClobberingStore(L, DepSI, *TD);
+ if (Offset != -1) {
+ Value *AvailVal = GetStoreValueForLoad(DepSI->getOperand(0), Offset,
+ L->getType(), L, *TD);
+ DEBUG(errs() << "GVN COERCED STORE BITS:\n" << *DepSI << '\n'
+ << *AvailVal << '\n' << *L << "\n\n\n");
+
+ // Replace the load!
+ L->replaceAllUsesWith(AvailVal);
+ if (isa<PointerType>(AvailVal->getType()))
+ MD->invalidateCachedPointerInfo(AvailVal);
+ toErase.push_back(L);
+ NumGVNLoad++;
+ return true;
+ }
+ }
+
DEBUG(
// fast print dep, using operator<< on instruction would be too slow
errs() << "GVN: load ";
WriteAsOperand(errs(), L);
- Instruction *I = dep.getInst();
+ Instruction *I = Dep.getInst();
errs() << " is clobbered by " << *I << '\n';
);
return false;
}
// If it is defined in another block, try harder.
- if (dep.isNonLocal())
+ if (Dep.isNonLocal())
return processNonLocalLoad(L, toErase);
- Instruction *DepInst = dep.getInst();
+ Instruction *DepInst = Dep.getInst();
if (StoreInst *DepSI = dyn_cast<StoreInst>(DepInst)) {
- // Only forward substitute stores to loads of the same type.
- // FIXME: Could do better!
- if (DepSI->getPointerOperand()->getType() != pointer->getType())
- return false;
+ Value *StoredVal = DepSI->getOperand(0);
+ // The store and load are to a must-aliased pointer, but they may not
+ // actually have the same type. See if we know how to reuse the stored
+ // value (depending on its type).
+ const TargetData *TD = 0;
+ if (StoredVal->getType() != L->getType() &&
+ (TD = getAnalysisIfAvailable<TargetData>())) {
+ StoredVal = CoerceAvailableValueToLoadType(StoredVal, L->getType(),
+ L, *TD);
+ if (StoredVal == 0)
+ return false;
+
+ DEBUG(errs() << "GVN COERCED STORE:\n" << *DepSI << '\n' << *StoredVal
+ << '\n' << *L << "\n\n\n");
+ }
+
// Remove it!
- L->replaceAllUsesWith(DepSI->getOperand(0));
- if (isa<PointerType>(DepSI->getOperand(0)->getType()))
- MD->invalidateCachedPointerInfo(DepSI->getOperand(0));
+ L->replaceAllUsesWith(StoredVal);
+ if (isa<PointerType>(StoredVal->getType()))
+ MD->invalidateCachedPointerInfo(StoredVal);
toErase.push_back(L);
NumGVNLoad++;
return true;
}
if (LoadInst *DepLI = dyn_cast<LoadInst>(DepInst)) {
- // Only forward substitute stores to loads of the same type.
- // FIXME: Could do better! load i32 -> load i8 -> truncate on little endian.
- if (DepLI->getType() != L->getType())
- return false;
+ Value *AvailableVal = DepLI;
+
+ // The loads are of a must-aliased pointer, but they may not actually have
+ // the same type. See if we know how to reuse the previously loaded value
+ // (depending on its type).
+ const TargetData *TD = 0;
+ if (DepLI->getType() != L->getType() &&
+ (TD = getAnalysisIfAvailable<TargetData>())) {
+ AvailableVal = CoerceAvailableValueToLoadType(DepLI, L->getType(), L,*TD);
+ if (AvailableVal == 0)
+ return false;
+
+ DEBUG(errs() << "GVN COERCED LOAD:\n" << *DepLI << "\n" << *AvailableVal
+ << "\n" << *L << "\n\n\n");
+ }
// Remove it!
- L->replaceAllUsesWith(DepLI);
+ L->replaceAllUsesWith(AvailableVal);
if (isa<PointerType>(DepLI->getType()))
MD->invalidateCachedPointerInfo(DepLI);
toErase.push_back(L);
NumGVNLoad++;
return true;
}
-
+
// If this load really doesn't depend on anything, then we must be loading an
// undef value. This can happen when loading for a fresh allocation with no
// intervening stores, for example.
- if (isa<AllocationInst>(DepInst)) {
+ if (isa<AllocationInst>(DepInst) || isMalloc(DepInst)) {
L->replaceAllUsesWith(UndefValue::get(L->getType()));
toErase.push_back(L);
NumGVNLoad++;
@@ -1281,71 +1711,69 @@ bool GVN::processLoad(LoadInst *L, SmallVectorImpl<Instruction*> &toErase) {
return false;
}
-Value* GVN::lookupNumber(BasicBlock* BB, uint32_t num) {
+Value *GVN::lookupNumber(BasicBlock *BB, uint32_t num) {
DenseMap<BasicBlock*, ValueNumberScope*>::iterator I = localAvail.find(BB);
if (I == localAvail.end())
return 0;
-
- ValueNumberScope* locals = I->second;
-
- while (locals) {
- DenseMap<uint32_t, Value*>::iterator I = locals->table.find(num);
- if (I != locals->table.end())
+
+ ValueNumberScope *Locals = I->second;
+ while (Locals) {
+ DenseMap<uint32_t, Value*>::iterator I = Locals->table.find(num);
+ if (I != Locals->table.end())
return I->second;
- else
- locals = locals->parent;
+ Locals = Locals->parent;
}
-
+
return 0;
}
/// AttemptRedundancyElimination - If the "fast path" of redundancy elimination
-/// by inheritance from the dominator fails, see if we can perform phi
+/// by inheritance from the dominator fails, see if we can perform phi
/// construction to eliminate the redundancy.
-Value* GVN::AttemptRedundancyElimination(Instruction* orig, unsigned valno) {
- BasicBlock* BaseBlock = orig->getParent();
-
+Value *GVN::AttemptRedundancyElimination(Instruction *orig, unsigned valno) {
+ BasicBlock *BaseBlock = orig->getParent();
+
SmallPtrSet<BasicBlock*, 4> Visited;
SmallVector<BasicBlock*, 8> Stack;
Stack.push_back(BaseBlock);
-
+
DenseMap<BasicBlock*, Value*> Results;
-
+
// Walk backwards through our predecessors, looking for instances of the
// value number we're looking for. Instances are recorded in the Results
// map, which is then used to perform phi construction.
while (!Stack.empty()) {
- BasicBlock* Current = Stack.back();
+ BasicBlock *Current = Stack.back();
Stack.pop_back();
-
+
// If we've walked all the way to a proper dominator, then give up. Cases
// where the instance is in the dominator will have been caught by the fast
// path, and any cases that require phi construction further than this are
// probably not worth it anyways. Note that this is a SIGNIFICANT compile
// time improvement.
if (DT->properlyDominates(Current, orig->getParent())) return 0;
-
+
DenseMap<BasicBlock*, ValueNumberScope*>::iterator LA =
localAvail.find(Current);
if (LA == localAvail.end()) return 0;
DenseMap<uint32_t, Value*>::iterator V = LA->second->table.find(valno);
-
+
if (V != LA->second->table.end()) {
// Found an instance, record it.
Results.insert(std::make_pair(Current, V->second));
continue;
}
-
+
// If we reach the beginning of the function, then give up.
if (pred_begin(Current) == pred_end(Current))
return 0;
-
+
for (pred_iterator PI = pred_begin(Current), PE = pred_end(Current);
PI != PE; ++PI)
if (Visited.insert(*PI))
Stack.push_back(*PI);
}
-
+
// If we didn't find instances, give up. Otherwise, perform phi construction.
if (Results.size() == 0)
return 0;
@@ -1357,76 +1785,76 @@ Value* GVN::AttemptRedundancyElimination(Instruction* orig, unsigned valno) {
/// by inserting it into the appropriate sets
bool GVN::processInstruction(Instruction *I,
SmallVectorImpl<Instruction*> &toErase) {
- if (LoadInst* L = dyn_cast<LoadInst>(I)) {
- bool changed = processLoad(L, toErase);
-
- if (!changed) {
- unsigned num = VN.lookup_or_add(L);
- localAvail[I->getParent()]->table.insert(std::make_pair(num, L));
+ if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
+ bool Changed = processLoad(LI, toErase);
+
+ if (!Changed) {
+ unsigned Num = VN.lookup_or_add(LI);
+ localAvail[I->getParent()]->table.insert(std::make_pair(Num, LI));
}
-
- return changed;
+
+ return Changed;
}
-
- uint32_t nextNum = VN.getNextUnusedValueNumber();
- unsigned num = VN.lookup_or_add(I);
-
- if (BranchInst* BI = dyn_cast<BranchInst>(I)) {
- localAvail[I->getParent()]->table.insert(std::make_pair(num, I));
-
+
+ uint32_t NextNum = VN.getNextUnusedValueNumber();
+ unsigned Num = VN.lookup_or_add(I);
+
+ if (BranchInst *BI = dyn_cast<BranchInst>(I)) {
+ localAvail[I->getParent()]->table.insert(std::make_pair(Num, I));
+
if (!BI->isConditional() || isa<Constant>(BI->getCondition()))
return false;
-
- Value* branchCond = BI->getCondition();
- uint32_t condVN = VN.lookup_or_add(branchCond);
-
- BasicBlock* trueSucc = BI->getSuccessor(0);
- BasicBlock* falseSucc = BI->getSuccessor(1);
-
- if (trueSucc->getSinglePredecessor())
- localAvail[trueSucc]->table[condVN] =
- ConstantInt::getTrue(trueSucc->getContext());
- if (falseSucc->getSinglePredecessor())
- localAvail[falseSucc]->table[condVN] =
- ConstantInt::getFalse(trueSucc->getContext());
+
+ Value *BranchCond = BI->getCondition();
+ uint32_t CondVN = VN.lookup_or_add(BranchCond);
+
+ BasicBlock *TrueSucc = BI->getSuccessor(0);
+ BasicBlock *FalseSucc = BI->getSuccessor(1);
+
+ if (TrueSucc->getSinglePredecessor())
+ localAvail[TrueSucc]->table[CondVN] =
+ ConstantInt::getTrue(TrueSucc->getContext());
+ if (FalseSucc->getSinglePredecessor())
+ localAvail[FalseSucc]->table[CondVN] =
+ ConstantInt::getFalse(TrueSucc->getContext());
return false;
-
+
// Allocations are always uniquely numbered, so we can save time and memory
- // by fast failing them.
+ // by fast failing them.
} else if (isa<AllocationInst>(I) || isa<TerminatorInst>(I)) {
- localAvail[I->getParent()]->table.insert(std::make_pair(num, I));
+ localAvail[I->getParent()]->table.insert(std::make_pair(Num, I));
return false;
}
-
+
// Collapse PHI nodes
if (PHINode* p = dyn_cast<PHINode>(I)) {
- Value* constVal = CollapsePhi(p);
-
+ Value *constVal = CollapsePhi(p);
+
if (constVal) {
for (PhiMapType::iterator PI = phiMap.begin(), PE = phiMap.end();
PI != PE; ++PI)
PI->second.erase(p);
-
+
p->replaceAllUsesWith(constVal);
if (isa<PointerType>(constVal->getType()))
MD->invalidateCachedPointerInfo(constVal);
VN.erase(p);
-
+
toErase.push_back(p);
} else {
- localAvail[I->getParent()]->table.insert(std::make_pair(num, I));
+ localAvail[I->getParent()]->table.insert(std::make_pair(Num, I));
}
-
+
// If the number we were assigned was a brand new VN, then we don't
// need to do a lookup to see if the number already exists
// somewhere in the domtree: it can't!
- } else if (num == nextNum) {
- localAvail[I->getParent()]->table.insert(std::make_pair(num, I));
-
+ } else if (Num == NextNum) {
+ localAvail[I->getParent()]->table.insert(std::make_pair(Num, I));
+
// Perform fast-path value-number based elimination of values inherited from
// dominators.
- } else if (Value* repl = lookupNumber(I->getParent(), num)) {
+ } else if (Value *repl = lookupNumber(I->getParent(), Num)) {
// Remove it!
VN.erase(I);
I->replaceAllUsesWith(repl);
@@ -1437,7 +1865,7 @@ bool GVN::processInstruction(Instruction *I,
#if 0
// Perform slow-pathvalue-number based elimination with phi construction.
- } else if (Value* repl = AttemptRedundancyElimination(I, num)) {
+ } else if (Value *repl = AttemptRedundancyElimination(I, Num)) {
// Remove it!
VN.erase(I);
I->replaceAllUsesWith(repl);
@@ -1447,9 +1875,9 @@ bool GVN::processInstruction(Instruction *I,
return true;
#endif
} else {
- localAvail[I->getParent()]->table.insert(std::make_pair(num, I));
+ localAvail[I->getParent()]->table.insert(std::make_pair(Num, I));
}
-
+
return false;
}
@@ -1460,35 +1888,35 @@ bool GVN::runOnFunction(Function& F) {
VN.setAliasAnalysis(&getAnalysis<AliasAnalysis>());
VN.setMemDep(MD);
VN.setDomTree(DT);
-
- bool changed = false;
- bool shouldContinue = true;
-
+
+ bool Changed = false;
+ bool ShouldContinue = true;
+
// Merge unconditional branches, allowing PRE to catch more
// optimization opportunities.
for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ) {
- BasicBlock* BB = FI;
+ BasicBlock *BB = FI;
++FI;
bool removedBlock = MergeBlockIntoPredecessor(BB, this);
if (removedBlock) NumGVNBlocks++;
-
- changed |= removedBlock;
+
+ Changed |= removedBlock;
}
-
+
unsigned Iteration = 0;
-
- while (shouldContinue) {
+
+ while (ShouldContinue) {
DEBUG(errs() << "GVN iteration: " << Iteration << "\n");
- shouldContinue = iterateOnFunction(F);
- changed |= shouldContinue;
+ ShouldContinue = iterateOnFunction(F);
+ Changed |= ShouldContinue;
++Iteration;
}
-
+
if (EnablePRE) {
bool PREChanged = true;
while (PREChanged) {
PREChanged = performPRE(F);
- changed |= PREChanged;
+ Changed |= PREChanged;
}
}
// FIXME: Should perform GVN again after PRE does something. PRE can move
@@ -1498,27 +1926,27 @@ bool GVN::runOnFunction(Function& F) {
cleanupGlobalSets();
- return changed;
+ return Changed;
}
-bool GVN::processBlock(BasicBlock* BB) {
+bool GVN::processBlock(BasicBlock *BB) {
// FIXME: Kill off toErase by doing erasing eagerly in a helper function (and
// incrementing BI before processing an instruction).
SmallVector<Instruction*, 8> toErase;
- bool changed_function = false;
-
+ bool ChangedFunction = false;
+
for (BasicBlock::iterator BI = BB->begin(), BE = BB->end();
BI != BE;) {
- changed_function |= processInstruction(BI, toErase);
+ ChangedFunction |= processInstruction(BI, toErase);
if (toErase.empty()) {
++BI;
continue;
}
-
+
// If we need some instructions deleted, do it now.
NumGVNInstr += toErase.size();
-
+
// Avoid iterator invalidation.
bool AtStart = BI == BB->begin();
if (!AtStart)
@@ -1538,8 +1966,8 @@ bool GVN::processBlock(BasicBlock* BB) {
else
++BI;
}
-
- return changed_function;
+
+ return ChangedFunction;
}
/// performPRE - Perform a purely local form of PRE that looks for diamond
@@ -1550,33 +1978,33 @@ bool GVN::performPRE(Function& F) {
DenseMap<BasicBlock*, Value*> predMap;
for (df_iterator<BasicBlock*> DI = df_begin(&F.getEntryBlock()),
DE = df_end(&F.getEntryBlock()); DI != DE; ++DI) {
- BasicBlock* CurrentBlock = *DI;
-
+ BasicBlock *CurrentBlock = *DI;
+
// Nothing to PRE in the entry block.
if (CurrentBlock == &F.getEntryBlock()) continue;
-
+
for (BasicBlock::iterator BI = CurrentBlock->begin(),
BE = CurrentBlock->end(); BI != BE; ) {
Instruction *CurInst = BI++;
- if (isa<AllocationInst>(CurInst) || isa<TerminatorInst>(CurInst) ||
- isa<PHINode>(CurInst) ||
+ if (isa<AllocationInst>(CurInst) ||
+ isa<TerminatorInst>(CurInst) || isa<PHINode>(CurInst) ||
(CurInst->getType() == Type::getVoidTy(F.getContext())) ||
CurInst->mayReadFromMemory() || CurInst->mayHaveSideEffects() ||
isa<DbgInfoIntrinsic>(CurInst))
continue;
- uint32_t valno = VN.lookup(CurInst);
-
+ uint32_t ValNo = VN.lookup(CurInst);
+
// Look for the predecessors for PRE opportunities. We're
// only trying to solve the basic diamond case, where
// a value is computed in the successor and one predecessor,
// but not the other. We also explicitly disallow cases
// where the successor is its own predecessor, because they're
// more complicated to get right.
- unsigned numWith = 0;
- unsigned numWithout = 0;
- BasicBlock* PREPred = 0;
+ unsigned NumWith = 0;
+ unsigned NumWithout = 0;
+ BasicBlock *PREPred = 0;
predMap.clear();
for (pred_iterator PI = pred_begin(CurrentBlock),
@@ -1585,59 +2013,59 @@ bool GVN::performPRE(Function& F) {
// own predecessor, on in blocks with predecessors
// that are not reachable.
if (*PI == CurrentBlock) {
- numWithout = 2;
+ NumWithout = 2;
break;
} else if (!localAvail.count(*PI)) {
- numWithout = 2;
+ NumWithout = 2;
break;
}
-
- DenseMap<uint32_t, Value*>::iterator predV =
- localAvail[*PI]->table.find(valno);
+
+ DenseMap<uint32_t, Value*>::iterator predV =
+ localAvail[*PI]->table.find(ValNo);
if (predV == localAvail[*PI]->table.end()) {
PREPred = *PI;
- numWithout++;
+ NumWithout++;
} else if (predV->second == CurInst) {
- numWithout = 2;
+ NumWithout = 2;
} else {
predMap[*PI] = predV->second;
- numWith++;
+ NumWith++;
}
}
-
+
// Don't do PRE when it might increase code size, i.e. when
// we would need to insert instructions in more than one pred.
- if (numWithout != 1 || numWith == 0)
+ if (NumWithout != 1 || NumWith == 0)
continue;
-
+
// We can't do PRE safely on a critical edge, so instead we schedule
// the edge to be split and perform the PRE the next time we iterate
// on the function.
- unsigned succNum = 0;
+ unsigned SuccNum = 0;
for (unsigned i = 0, e = PREPred->getTerminator()->getNumSuccessors();
i != e; ++i)
if (PREPred->getTerminator()->getSuccessor(i) == CurrentBlock) {
- succNum = i;
+ SuccNum = i;
break;
}
-
- if (isCriticalEdge(PREPred->getTerminator(), succNum)) {
- toSplit.push_back(std::make_pair(PREPred->getTerminator(), succNum));
+
+ if (isCriticalEdge(PREPred->getTerminator(), SuccNum)) {
+ toSplit.push_back(std::make_pair(PREPred->getTerminator(), SuccNum));
continue;
}
-
+
// Instantiate the expression the in predecessor that lacked it.
// Because we are going top-down through the block, all value numbers
// will be available in the predecessor by the time we need them. Any
// that weren't original present will have been instantiated earlier
// in this loop.
- Instruction* PREInstr = CurInst->clone(CurInst->getContext());
+ Instruction *PREInstr = CurInst->clone();
bool success = true;
for (unsigned i = 0, e = CurInst->getNumOperands(); i != e; ++i) {
Value *Op = PREInstr->getOperand(i);
if (isa<Argument>(Op) || isa<Constant>(Op) || isa<GlobalValue>(Op))
continue;
-
+
if (Value *V = lookupNumber(PREPred, VN.lookup(Op))) {
PREInstr->setOperand(i, V);
} else {
@@ -1645,25 +2073,25 @@ bool GVN::performPRE(Function& F) {
break;
}
}
-
+
// Fail out if we encounter an operand that is not available in
- // the PRE predecessor. This is typically because of loads which
+ // the PRE predecessor. This is typically because of loads which
// are not value numbered precisely.
if (!success) {
delete PREInstr;
DEBUG(verifyRemoved(PREInstr));
continue;
}
-
+
PREInstr->insertBefore(PREPred->getTerminator());
PREInstr->setName(CurInst->getName() + ".pre");
predMap[PREPred] = PREInstr;
- VN.add(PREInstr, valno);
+ VN.add(PREInstr, ValNo);
NumGVNPRE++;
-
+
// Update the availability map to include the new instruction.
- localAvail[PREPred]->table.insert(std::make_pair(valno, PREInstr));
-
+ localAvail[PREPred]->table.insert(std::make_pair(ValNo, PREInstr));
+
// Create a PHI to make the value available in this block.
PHINode* Phi = PHINode::Create(CurInst->getType(),
CurInst->getName() + ".pre-phi",
@@ -1671,15 +2099,15 @@ bool GVN::performPRE(Function& F) {
for (pred_iterator PI = pred_begin(CurrentBlock),
PE = pred_end(CurrentBlock); PI != PE; ++PI)
Phi->addIncoming(predMap[*PI], *PI);
-
- VN.add(Phi, valno);
- localAvail[CurrentBlock]->table[valno] = Phi;
-
+
+ VN.add(Phi, ValNo);
+ localAvail[CurrentBlock]->table[ValNo] = Phi;
+
CurInst->replaceAllUsesWith(Phi);
if (isa<PointerType>(Phi->getType()))
MD->invalidateCachedPointerInfo(Phi);
VN.erase(CurInst);
-
+
DEBUG(errs() << "GVN PRE removed: " << *CurInst << '\n');
MD->removeInstruction(CurInst);
CurInst->eraseFromParent();
@@ -1687,11 +2115,11 @@ bool GVN::performPRE(Function& F) {
Changed = true;
}
}
-
+
for (SmallVector<std::pair<TerminatorInst*, unsigned>, 4>::iterator
I = toSplit.begin(), E = toSplit.end(); I != E; ++I)
SplitCriticalEdge(I->first, I->second, this);
-
+
return Changed || toSplit.size();
}
@@ -1709,20 +2137,20 @@ bool GVN::iterateOnFunction(Function &F) {
}
// Top-down walk of the dominator tree
- bool changed = false;
+ bool Changed = false;
#if 0
// Needed for value numbering with phi construction to work.
ReversePostOrderTraversal<Function*> RPOT(&F);
for (ReversePostOrderTraversal<Function*>::rpo_iterator RI = RPOT.begin(),
RE = RPOT.end(); RI != RE; ++RI)
- changed |= processBlock(*RI);
+ Changed |= processBlock(*RI);
#else
for (df_iterator<DomTreeNode*> DI = df_begin(DT->getRootNode()),
DE = df_end(DT->getRootNode()); DI != DE; ++DI)
- changed |= processBlock(DI->getBlock());
+ Changed |= processBlock(DI->getBlock());
#endif
- return changed;
+ return Changed;
}
void GVN::cleanupGlobalSets() {
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/GVNPRE.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/GVNPRE.cpp
deleted file mode 100644
index b6296f7..0000000
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/GVNPRE.cpp
+++ /dev/null
@@ -1,1895 +0,0 @@
-//===- GVNPRE.cpp - Eliminate redundant values and expressions ------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This pass performs a hybrid of global value numbering and partial redundancy
-// elimination, known as GVN-PRE. It performs partial redundancy elimination on
-// values, rather than lexical expressions, allowing a more comprehensive view
-// the optimization. It replaces redundant values with uses of earlier
-// occurences of the same value. While this is beneficial in that it eliminates
-// unneeded computation, it also increases register pressure by creating large
-// live ranges, and should be used with caution on platforms that are very
-// sensitive to register pressure.
-//
-// Note that this pass does the value numbering itself, it does not use the
-// ValueNumbering analysis passes.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "gvnpre"
-#include "llvm/Value.h"
-#include "llvm/Transforms/Scalar.h"
-#include "llvm/Instructions.h"
-#include "llvm/Function.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/Analysis/Dominators.h"
-#include "llvm/ADT/BitVector.h"
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/DepthFirstIterator.h"
-#include "llvm/ADT/PostOrderIterator.h"
-#include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Transforms/Utils/UnifyFunctionExitNodes.h"
-#include "llvm/Support/CFG.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include <algorithm>
-#include <deque>
-#include <map>
-using namespace llvm;
-
-//===----------------------------------------------------------------------===//
-// ValueTable Class
-//===----------------------------------------------------------------------===//
-
-namespace {
-
-/// This class holds the mapping between values and value numbers. It is used
-/// as an efficient mechanism to determine the expression-wise equivalence of
-/// two values.
-
-struct Expression {
- enum ExpressionOpcode { ADD, FADD, SUB, FSUB, MUL, FMUL,
- UDIV, SDIV, FDIV, UREM, SREM,
- FREM, SHL, LSHR, ASHR, AND, OR, XOR, ICMPEQ,
- ICMPNE, ICMPUGT, ICMPUGE, ICMPULT, ICMPULE,
- ICMPSGT, ICMPSGE, ICMPSLT, ICMPSLE, FCMPOEQ,
- FCMPOGT, FCMPOGE, FCMPOLT, FCMPOLE, FCMPONE,
- FCMPORD, FCMPUNO, FCMPUEQ, FCMPUGT, FCMPUGE,
- FCMPULT, FCMPULE, FCMPUNE, EXTRACT, INSERT,
- SHUFFLE, SELECT, TRUNC, ZEXT, SEXT, FPTOUI,
- FPTOSI, UITOFP, SITOFP, FPTRUNC, FPEXT,
- PTRTOINT, INTTOPTR, BITCAST, GEP, EMPTY,
- TOMBSTONE };
-
- ExpressionOpcode opcode;
- const Type* type;
- uint32_t firstVN;
- uint32_t secondVN;
- uint32_t thirdVN;
- SmallVector<uint32_t, 4> varargs;
-
- Expression() { }
- explicit Expression(ExpressionOpcode o) : opcode(o) { }
-
- bool operator==(const Expression &other) const {
- if (opcode != other.opcode)
- return false;
- else if (opcode == EMPTY || opcode == TOMBSTONE)
- return true;
- else if (type != other.type)
- return false;
- else if (firstVN != other.firstVN)
- return false;
- else if (secondVN != other.secondVN)
- return false;
- else if (thirdVN != other.thirdVN)
- return false;
- else {
- if (varargs.size() != other.varargs.size())
- return false;
-
- for (size_t i = 0; i < varargs.size(); ++i)
- if (varargs[i] != other.varargs[i])
- return false;
-
- return true;
- }
- }
-
- bool operator!=(const Expression &other) const {
- if (opcode != other.opcode)
- return true;
- else if (opcode == EMPTY || opcode == TOMBSTONE)
- return false;
- else if (type != other.type)
- return true;
- else if (firstVN != other.firstVN)
- return true;
- else if (secondVN != other.secondVN)
- return true;
- else if (thirdVN != other.thirdVN)
- return true;
- else {
- if (varargs.size() != other.varargs.size())
- return true;
-
- for (size_t i = 0; i < varargs.size(); ++i)
- if (varargs[i] != other.varargs[i])
- return true;
-
- return false;
- }
- }
-};
-
-}
-
-namespace {
- class VISIBILITY_HIDDEN ValueTable {
- private:
- DenseMap<Value*, uint32_t> valueNumbering;
- DenseMap<Expression, uint32_t> expressionNumbering;
-
- uint32_t nextValueNumber;
-
- Expression::ExpressionOpcode getOpcode(BinaryOperator* BO);
- Expression::ExpressionOpcode getOpcode(CmpInst* C);
- Expression::ExpressionOpcode getOpcode(CastInst* C);
- Expression create_expression(BinaryOperator* BO);
- Expression create_expression(CmpInst* C);
- Expression create_expression(ShuffleVectorInst* V);
- Expression create_expression(ExtractElementInst* C);
- Expression create_expression(InsertElementInst* V);
- Expression create_expression(SelectInst* V);
- Expression create_expression(CastInst* C);
- Expression create_expression(GetElementPtrInst* G);
- public:
- ValueTable() { nextValueNumber = 1; }
- uint32_t lookup_or_add(Value* V);
- uint32_t lookup(Value* V) const;
- void add(Value* V, uint32_t num);
- void clear();
- void erase(Value* v);
- unsigned size();
- };
-}
-
-namespace llvm {
-template <> struct DenseMapInfo<Expression> {
- static inline Expression getEmptyKey() {
- return Expression(Expression::EMPTY);
- }
-
- static inline Expression getTombstoneKey() {
- return Expression(Expression::TOMBSTONE);
- }
-
- static unsigned getHashValue(const Expression e) {
- unsigned hash = e.opcode;
-
- hash = e.firstVN + hash * 37;
- hash = e.secondVN + hash * 37;
- hash = e.thirdVN + hash * 37;
-
- hash = ((unsigned)((uintptr_t)e.type >> 4) ^
- (unsigned)((uintptr_t)e.type >> 9)) +
- hash * 37;
-
- for (SmallVector<uint32_t, 4>::const_iterator I = e.varargs.begin(),
- E = e.varargs.end(); I != E; ++I)
- hash = *I + hash * 37;
-
- return hash;
- }
- static bool isEqual(const Expression &LHS, const Expression &RHS) {
- return LHS == RHS;
- }
- static bool isPod() { return true; }
-};
-}
-
-//===----------------------------------------------------------------------===//
-// ValueTable Internal Functions
-//===----------------------------------------------------------------------===//
-Expression::ExpressionOpcode
- ValueTable::getOpcode(BinaryOperator* BO) {
- switch(BO->getOpcode()) {
- case Instruction::Add:
- return Expression::ADD;
- case Instruction::FAdd:
- return Expression::FADD;
- case Instruction::Sub:
- return Expression::SUB;
- case Instruction::FSub:
- return Expression::FSUB;
- case Instruction::Mul:
- return Expression::MUL;
- case Instruction::FMul:
- return Expression::FMUL;
- case Instruction::UDiv:
- return Expression::UDIV;
- case Instruction::SDiv:
- return Expression::SDIV;
- case Instruction::FDiv:
- return Expression::FDIV;
- case Instruction::URem:
- return Expression::UREM;
- case Instruction::SRem:
- return Expression::SREM;
- case Instruction::FRem:
- return Expression::FREM;
- case Instruction::Shl:
- return Expression::SHL;
- case Instruction::LShr:
- return Expression::LSHR;
- case Instruction::AShr:
- return Expression::ASHR;
- case Instruction::And:
- return Expression::AND;
- case Instruction::Or:
- return Expression::OR;
- case Instruction::Xor:
- return Expression::XOR;
-
- // THIS SHOULD NEVER HAPPEN
- default:
- llvm_unreachable("Binary operator with unknown opcode?");
- return Expression::ADD;
- }
-}
-
-Expression::ExpressionOpcode ValueTable::getOpcode(CmpInst* C) {
- if (C->getOpcode() == Instruction::ICmp) {
- switch (C->getPredicate()) {
- case ICmpInst::ICMP_EQ:
- return Expression::ICMPEQ;
- case ICmpInst::ICMP_NE:
- return Expression::ICMPNE;
- case ICmpInst::ICMP_UGT:
- return Expression::ICMPUGT;
- case ICmpInst::ICMP_UGE:
- return Expression::ICMPUGE;
- case ICmpInst::ICMP_ULT:
- return Expression::ICMPULT;
- case ICmpInst::ICMP_ULE:
- return Expression::ICMPULE;
- case ICmpInst::ICMP_SGT:
- return Expression::ICMPSGT;
- case ICmpInst::ICMP_SGE:
- return Expression::ICMPSGE;
- case ICmpInst::ICMP_SLT:
- return Expression::ICMPSLT;
- case ICmpInst::ICMP_SLE:
- return Expression::ICMPSLE;
-
- // THIS SHOULD NEVER HAPPEN
- default:
- llvm_unreachable("Comparison with unknown predicate?");
- return Expression::ICMPEQ;
- }
- } else {
- switch (C->getPredicate()) {
- case FCmpInst::FCMP_OEQ:
- return Expression::FCMPOEQ;
- case FCmpInst::FCMP_OGT:
- return Expression::FCMPOGT;
- case FCmpInst::FCMP_OGE:
- return Expression::FCMPOGE;
- case FCmpInst::FCMP_OLT:
- return Expression::FCMPOLT;
- case FCmpInst::FCMP_OLE:
- return Expression::FCMPOLE;
- case FCmpInst::FCMP_ONE:
- return Expression::FCMPONE;
- case FCmpInst::FCMP_ORD:
- return Expression::FCMPORD;
- case FCmpInst::FCMP_UNO:
- return Expression::FCMPUNO;
- case FCmpInst::FCMP_UEQ:
- return Expression::FCMPUEQ;
- case FCmpInst::FCMP_UGT:
- return Expression::FCMPUGT;
- case FCmpInst::FCMP_UGE:
- return Expression::FCMPUGE;
- case FCmpInst::FCMP_ULT:
- return Expression::FCMPULT;
- case FCmpInst::FCMP_ULE:
- return Expression::FCMPULE;
- case FCmpInst::FCMP_UNE:
- return Expression::FCMPUNE;
-
- // THIS SHOULD NEVER HAPPEN
- default:
- llvm_unreachable("Comparison with unknown predicate?");
- return Expression::FCMPOEQ;
- }
- }
-}
-
-Expression::ExpressionOpcode
- ValueTable::getOpcode(CastInst* C) {
- switch(C->getOpcode()) {
- case Instruction::Trunc:
- return Expression::TRUNC;
- case Instruction::ZExt:
- return Expression::ZEXT;
- case Instruction::SExt:
- return Expression::SEXT;
- case Instruction::FPToUI:
- return Expression::FPTOUI;
- case Instruction::FPToSI:
- return Expression::FPTOSI;
- case Instruction::UIToFP:
- return Expression::UITOFP;
- case Instruction::SIToFP:
- return Expression::SITOFP;
- case Instruction::FPTrunc:
- return Expression::FPTRUNC;
- case Instruction::FPExt:
- return Expression::FPEXT;
- case Instruction::PtrToInt:
- return Expression::PTRTOINT;
- case Instruction::IntToPtr:
- return Expression::INTTOPTR;
- case Instruction::BitCast:
- return Expression::BITCAST;
-
- // THIS SHOULD NEVER HAPPEN
- default:
- llvm_unreachable("Cast operator with unknown opcode?");
- return Expression::BITCAST;
- }
-}
-
-Expression ValueTable::create_expression(BinaryOperator* BO) {
- Expression e;
-
- e.firstVN = lookup_or_add(BO->getOperand(0));
- e.secondVN = lookup_or_add(BO->getOperand(1));
- e.thirdVN = 0;
- e.type = BO->getType();
- e.opcode = getOpcode(BO);
-
- return e;
-}
-
-Expression ValueTable::create_expression(CmpInst* C) {
- Expression e;
-
- e.firstVN = lookup_or_add(C->getOperand(0));
- e.secondVN = lookup_or_add(C->getOperand(1));
- e.thirdVN = 0;
- e.type = C->getType();
- e.opcode = getOpcode(C);
-
- return e;
-}
-
-Expression ValueTable::create_expression(CastInst* C) {
- Expression e;
-
- e.firstVN = lookup_or_add(C->getOperand(0));
- e.secondVN = 0;
- e.thirdVN = 0;
- e.type = C->getType();
- e.opcode = getOpcode(C);
-
- return e;
-}
-
-Expression ValueTable::create_expression(ShuffleVectorInst* S) {
- Expression e;
-
- e.firstVN = lookup_or_add(S->getOperand(0));
- e.secondVN = lookup_or_add(S->getOperand(1));
- e.thirdVN = lookup_or_add(S->getOperand(2));
- e.type = S->getType();
- e.opcode = Expression::SHUFFLE;
-
- return e;
-}
-
-Expression ValueTable::create_expression(ExtractElementInst* E) {
- Expression e;
-
- e.firstVN = lookup_or_add(E->getOperand(0));
- e.secondVN = lookup_or_add(E->getOperand(1));
- e.thirdVN = 0;
- e.type = E->getType();
- e.opcode = Expression::EXTRACT;
-
- return e;
-}
-
-Expression ValueTable::create_expression(InsertElementInst* I) {
- Expression e;
-
- e.firstVN = lookup_or_add(I->getOperand(0));
- e.secondVN = lookup_or_add(I->getOperand(1));
- e.thirdVN = lookup_or_add(I->getOperand(2));
- e.type = I->getType();
- e.opcode = Expression::INSERT;
-
- return e;
-}
-
-Expression ValueTable::create_expression(SelectInst* I) {
- Expression e;
-
- e.firstVN = lookup_or_add(I->getCondition());
- e.secondVN = lookup_or_add(I->getTrueValue());
- e.thirdVN = lookup_or_add(I->getFalseValue());
- e.type = I->getType();
- e.opcode = Expression::SELECT;
-
- return e;
-}
-
-Expression ValueTable::create_expression(GetElementPtrInst* G) {
- Expression e;
-
- e.firstVN = lookup_or_add(G->getPointerOperand());
- e.secondVN = 0;
- e.thirdVN = 0;
- e.type = G->getType();
- e.opcode = Expression::GEP;
-
- for (GetElementPtrInst::op_iterator I = G->idx_begin(), E = G->idx_end();
- I != E; ++I)
- e.varargs.push_back(lookup_or_add(*I));
-
- return e;
-}
-
-//===----------------------------------------------------------------------===//
-// ValueTable External Functions
-//===----------------------------------------------------------------------===//
-
-/// lookup_or_add - Returns the value number for the specified value, assigning
-/// it a new number if it did not have one before.
-uint32_t ValueTable::lookup_or_add(Value* V) {
- DenseMap<Value*, uint32_t>::iterator VI = valueNumbering.find(V);
- if (VI != valueNumbering.end())
- return VI->second;
-
-
- if (BinaryOperator* BO = dyn_cast<BinaryOperator>(V)) {
- Expression e = create_expression(BO);
-
- DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
- if (EI != expressionNumbering.end()) {
- valueNumbering.insert(std::make_pair(V, EI->second));
- return EI->second;
- } else {
- expressionNumbering.insert(std::make_pair(e, nextValueNumber));
- valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
- return nextValueNumber++;
- }
- } else if (CmpInst* C = dyn_cast<CmpInst>(V)) {
- Expression e = create_expression(C);
-
- DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
- if (EI != expressionNumbering.end()) {
- valueNumbering.insert(std::make_pair(V, EI->second));
- return EI->second;
- } else {
- expressionNumbering.insert(std::make_pair(e, nextValueNumber));
- valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
- return nextValueNumber++;
- }
- } else if (ShuffleVectorInst* U = dyn_cast<ShuffleVectorInst>(V)) {
- Expression e = create_expression(U);
-
- DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
- if (EI != expressionNumbering.end()) {
- valueNumbering.insert(std::make_pair(V, EI->second));
- return EI->second;
- } else {
- expressionNumbering.insert(std::make_pair(e, nextValueNumber));
- valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
- return nextValueNumber++;
- }
- } else if (ExtractElementInst* U = dyn_cast<ExtractElementInst>(V)) {
- Expression e = create_expression(U);
-
- DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
- if (EI != expressionNumbering.end()) {
- valueNumbering.insert(std::make_pair(V, EI->second));
- return EI->second;
- } else {
- expressionNumbering.insert(std::make_pair(e, nextValueNumber));
- valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
- return nextValueNumber++;
- }
- } else if (InsertElementInst* U = dyn_cast<InsertElementInst>(V)) {
- Expression e = create_expression(U);
-
- DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
- if (EI != expressionNumbering.end()) {
- valueNumbering.insert(std::make_pair(V, EI->second));
- return EI->second;
- } else {
- expressionNumbering.insert(std::make_pair(e, nextValueNumber));
- valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
- return nextValueNumber++;
- }
- } else if (SelectInst* U = dyn_cast<SelectInst>(V)) {
- Expression e = create_expression(U);
-
- DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
- if (EI != expressionNumbering.end()) {
- valueNumbering.insert(std::make_pair(V, EI->second));
- return EI->second;
- } else {
- expressionNumbering.insert(std::make_pair(e, nextValueNumber));
- valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
- return nextValueNumber++;
- }
- } else if (CastInst* U = dyn_cast<CastInst>(V)) {
- Expression e = create_expression(U);
-
- DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
- if (EI != expressionNumbering.end()) {
- valueNumbering.insert(std::make_pair(V, EI->second));
- return EI->second;
- } else {
- expressionNumbering.insert(std::make_pair(e, nextValueNumber));
- valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
- return nextValueNumber++;
- }
- } else if (GetElementPtrInst* U = dyn_cast<GetElementPtrInst>(V)) {
- Expression e = create_expression(U);
-
- DenseMap<Expression, uint32_t>::iterator EI = expressionNumbering.find(e);
- if (EI != expressionNumbering.end()) {
- valueNumbering.insert(std::make_pair(V, EI->second));
- return EI->second;
- } else {
- expressionNumbering.insert(std::make_pair(e, nextValueNumber));
- valueNumbering.insert(std::make_pair(V, nextValueNumber));
-
- return nextValueNumber++;
- }
- } else {
- valueNumbering.insert(std::make_pair(V, nextValueNumber));
- return nextValueNumber++;
- }
-}
-
-/// lookup - Returns the value number of the specified value. Fails if
-/// the value has not yet been numbered.
-uint32_t ValueTable::lookup(Value* V) const {
- DenseMap<Value*, uint32_t>::iterator VI = valueNumbering.find(V);
- if (VI != valueNumbering.end())
- return VI->second;
- else
- llvm_unreachable("Value not numbered?");
-
- return 0;
-}
-
-/// add - Add the specified value with the given value number, removing
-/// its old number, if any
-void ValueTable::add(Value* V, uint32_t num) {
- DenseMap<Value*, uint32_t>::iterator VI = valueNumbering.find(V);
- if (VI != valueNumbering.end())
- valueNumbering.erase(VI);
- valueNumbering.insert(std::make_pair(V, num));
-}
-
-/// clear - Remove all entries from the ValueTable
-void ValueTable::clear() {
- valueNumbering.clear();
- expressionNumbering.clear();
- nextValueNumber = 1;
-}
-
-/// erase - Remove a value from the value numbering
-void ValueTable::erase(Value* V) {
- valueNumbering.erase(V);
-}
-
-/// size - Return the number of assigned value numbers
-unsigned ValueTable::size() {
- // NOTE: zero is never assigned
- return nextValueNumber;
-}
-
-namespace {
-
-//===----------------------------------------------------------------------===//
-// ValueNumberedSet Class
-//===----------------------------------------------------------------------===//
-
-class ValueNumberedSet {
- private:
- SmallPtrSet<Value*, 8> contents;
- BitVector numbers;
- public:
- ValueNumberedSet() { numbers.resize(1); }
- ValueNumberedSet(const ValueNumberedSet& other) {
- numbers = other.numbers;
- contents = other.contents;
- }
-
- typedef SmallPtrSet<Value*, 8>::iterator iterator;
-
- iterator begin() { return contents.begin(); }
- iterator end() { return contents.end(); }
-
- bool insert(Value* v) { return contents.insert(v); }
- void insert(iterator I, iterator E) { contents.insert(I, E); }
- void erase(Value* v) { contents.erase(v); }
- unsigned count(Value* v) { return contents.count(v); }
- size_t size() { return contents.size(); }
-
- void set(unsigned i) {
- if (i >= numbers.size())
- numbers.resize(i+1);
-
- numbers.set(i);
- }
-
- void operator=(const ValueNumberedSet& other) {
- contents = other.contents;
- numbers = other.numbers;
- }
-
- void reset(unsigned i) {
- if (i < numbers.size())
- numbers.reset(i);
- }
-
- bool test(unsigned i) {
- if (i >= numbers.size())
- return false;
-
- return numbers.test(i);
- }
-
- void clear() {
- contents.clear();
- numbers.clear();
- }
-};
-
-}
-
-//===----------------------------------------------------------------------===//
-// GVNPRE Pass
-//===----------------------------------------------------------------------===//
-
-namespace {
-
- class VISIBILITY_HIDDEN GVNPRE : public FunctionPass {
- bool runOnFunction(Function &F);
- public:
- static char ID; // Pass identification, replacement for typeid
- GVNPRE() : FunctionPass(&ID) {}
-
- private:
- ValueTable VN;
- SmallVector<Instruction*, 8> createdExpressions;
-
- DenseMap<BasicBlock*, ValueNumberedSet> availableOut;
- DenseMap<BasicBlock*, ValueNumberedSet> anticipatedIn;
- DenseMap<BasicBlock*, ValueNumberedSet> generatedPhis;
-
- // This transformation requires dominator postdominator info
- virtual void getAnalysisUsage(AnalysisUsage &AU) const {
- AU.setPreservesCFG();
- AU.addRequiredID(BreakCriticalEdgesID);
- AU.addRequired<UnifyFunctionExitNodes>();
- AU.addRequired<DominatorTree>();
- }
-
- // Helper fuctions
- // FIXME: eliminate or document these better
- void dump(ValueNumberedSet& s) const ;
- void clean(ValueNumberedSet& set) ;
- Value* find_leader(ValueNumberedSet& vals, uint32_t v) ;
- Value* phi_translate(Value* V, BasicBlock* pred, BasicBlock* succ) ;
- void phi_translate_set(ValueNumberedSet& anticIn, BasicBlock* pred,
- BasicBlock* succ, ValueNumberedSet& out) ;
-
- void topo_sort(ValueNumberedSet& set,
- SmallVector<Value*, 8>& vec) ;
-
- void cleanup() ;
- bool elimination() ;
-
- void val_insert(ValueNumberedSet& s, Value* v) ;
- void val_replace(ValueNumberedSet& s, Value* v) ;
- bool dependsOnInvoke(Value* V) ;
- void buildsets_availout(BasicBlock::iterator I,
- ValueNumberedSet& currAvail,
- ValueNumberedSet& currPhis,
- ValueNumberedSet& currExps,
- SmallPtrSet<Value*, 16>& currTemps);
- bool buildsets_anticout(BasicBlock* BB,
- ValueNumberedSet& anticOut,
- SmallPtrSet<BasicBlock*, 8>& visited);
- unsigned buildsets_anticin(BasicBlock* BB,
- ValueNumberedSet& anticOut,
- ValueNumberedSet& currExps,
- SmallPtrSet<Value*, 16>& currTemps,
- SmallPtrSet<BasicBlock*, 8>& visited);
- void buildsets(Function& F) ;
-
- void insertion_pre(Value* e, BasicBlock* BB,
- DenseMap<BasicBlock*, Value*>& avail,
- std::map<BasicBlock*,ValueNumberedSet>& new_set);
- unsigned insertion_mergepoint(SmallVector<Value*, 8>& workList,
- df_iterator<DomTreeNode*>& D,
- std::map<BasicBlock*, ValueNumberedSet>& new_set);
- bool insertion(Function& F) ;
-
- };
-
- char GVNPRE::ID = 0;
-
-}
-
-// createGVNPREPass - The public interface to this file...
-FunctionPass *llvm::createGVNPREPass() { return new GVNPRE(); }
-
-static RegisterPass<GVNPRE> X("gvnpre",
- "Global Value Numbering/Partial Redundancy Elimination");
-
-
-STATISTIC(NumInsertedVals, "Number of values inserted");
-STATISTIC(NumInsertedPhis, "Number of PHI nodes inserted");
-STATISTIC(NumEliminated, "Number of redundant instructions eliminated");
-
-/// find_leader - Given a set and a value number, return the first
-/// element of the set with that value number, or 0 if no such element
-/// is present
-Value* GVNPRE::find_leader(ValueNumberedSet& vals, uint32_t v) {
- if (!vals.test(v))
- return 0;
-
- for (ValueNumberedSet::iterator I = vals.begin(), E = vals.end();
- I != E; ++I)
- if (v == VN.lookup(*I))
- return *I;
-
- llvm_unreachable("No leader found, but present bit is set?");
- return 0;
-}
-
-/// val_insert - Insert a value into a set only if there is not a value
-/// with the same value number already in the set
-void GVNPRE::val_insert(ValueNumberedSet& s, Value* v) {
- uint32_t num = VN.lookup(v);
- if (!s.test(num))
- s.insert(v);
-}
-
-/// val_replace - Insert a value into a set, replacing any values already in
-/// the set that have the same value number
-void GVNPRE::val_replace(ValueNumberedSet& s, Value* v) {
- if (s.count(v)) return;
-
- uint32_t num = VN.lookup(v);
- Value* leader = find_leader(s, num);
- if (leader != 0)
- s.erase(leader);
- s.insert(v);
- s.set(num);
-}
-
-/// phi_translate - Given a value, its parent block, and a predecessor of its
-/// parent, translate the value into legal for the predecessor block. This
-/// means translating its operands (and recursively, their operands) through
-/// any phi nodes in the parent into values available in the predecessor
-Value* GVNPRE::phi_translate(Value* V, BasicBlock* pred, BasicBlock* succ) {
- if (V == 0)
- return 0;
-
- // Unary Operations
- if (CastInst* U = dyn_cast<CastInst>(V)) {
- Value* newOp1 = 0;
- if (isa<Instruction>(U->getOperand(0)))
- newOp1 = phi_translate(U->getOperand(0), pred, succ);
- else
- newOp1 = U->getOperand(0);
-
- if (newOp1 == 0)
- return 0;
-
- if (newOp1 != U->getOperand(0)) {
- Instruction* newVal = 0;
- if (CastInst* C = dyn_cast<CastInst>(U))
- newVal = CastInst::Create(C->getOpcode(),
- newOp1, C->getType(),
- C->getName()+".expr");
-
- uint32_t v = VN.lookup_or_add(newVal);
-
- Value* leader = find_leader(availableOut[pred], v);
- if (leader == 0) {
- createdExpressions.push_back(newVal);
- return newVal;
- } else {
- VN.erase(newVal);
- delete newVal;
- return leader;
- }
- }
-
- // Binary Operations
- } if (isa<BinaryOperator>(V) || isa<CmpInst>(V) ||
- isa<ExtractElementInst>(V)) {
- User* U = cast<User>(V);
-
- Value* newOp1 = 0;
- if (isa<Instruction>(U->getOperand(0)))
- newOp1 = phi_translate(U->getOperand(0), pred, succ);
- else
- newOp1 = U->getOperand(0);
-
- if (newOp1 == 0)
- return 0;
-
- Value* newOp2 = 0;
- if (isa<Instruction>(U->getOperand(1)))
- newOp2 = phi_translate(U->getOperand(1), pred, succ);
- else
- newOp2 = U->getOperand(1);
-
- if (newOp2 == 0)
- return 0;
-
- if (newOp1 != U->getOperand(0) || newOp2 != U->getOperand(1)) {
- Instruction* newVal = 0;
- if (BinaryOperator* BO = dyn_cast<BinaryOperator>(U))
- newVal = BinaryOperator::Create(BO->getOpcode(),
- newOp1, newOp2,
- BO->getName()+".expr");
- else if (CmpInst* C = dyn_cast<CmpInst>(U))
- newVal = CmpInst::Create(C->getOpcode(),
- C->getPredicate(),
- newOp1, newOp2,
- C->getName()+".expr");
- else if (ExtractElementInst* E = dyn_cast<ExtractElementInst>(U))
- newVal = ExtractElementInst::Create(newOp1, newOp2,
- E->getName()+".expr");
-
- uint32_t v = VN.lookup_or_add(newVal);
-
- Value* leader = find_leader(availableOut[pred], v);
- if (leader == 0) {
- createdExpressions.push_back(newVal);
- return newVal;
- } else {
- VN.erase(newVal);
- delete newVal;
- return leader;
- }
- }
-
- // Ternary Operations
- } else if (isa<ShuffleVectorInst>(V) || isa<InsertElementInst>(V) ||
- isa<SelectInst>(V)) {
- User* U = cast<User>(V);
-
- Value* newOp1 = 0;
- if (isa<Instruction>(U->getOperand(0)))
- newOp1 = phi_translate(U->getOperand(0), pred, succ);
- else
- newOp1 = U->getOperand(0);
-
- if (newOp1 == 0)
- return 0;
-
- Value* newOp2 = 0;
- if (isa<Instruction>(U->getOperand(1)))
- newOp2 = phi_translate(U->getOperand(1), pred, succ);
- else
- newOp2 = U->getOperand(1);
-
- if (newOp2 == 0)
- return 0;
-
- Value* newOp3 = 0;
- if (isa<Instruction>(U->getOperand(2)))
- newOp3 = phi_translate(U->getOperand(2), pred, succ);
- else
- newOp3 = U->getOperand(2);
-
- if (newOp3 == 0)
- return 0;
-
- if (newOp1 != U->getOperand(0) ||
- newOp2 != U->getOperand(1) ||
- newOp3 != U->getOperand(2)) {
- Instruction* newVal = 0;
- if (ShuffleVectorInst* S = dyn_cast<ShuffleVectorInst>(U))
- newVal = new ShuffleVectorInst(newOp1, newOp2, newOp3,
- S->getName() + ".expr");
- else if (InsertElementInst* I = dyn_cast<InsertElementInst>(U))
- newVal = InsertElementInst::Create(newOp1, newOp2, newOp3,
- I->getName() + ".expr");
- else if (SelectInst* I = dyn_cast<SelectInst>(U))
- newVal = SelectInst::Create(newOp1, newOp2, newOp3,
- I->getName() + ".expr");
-
- uint32_t v = VN.lookup_or_add(newVal);
-
- Value* leader = find_leader(availableOut[pred], v);
- if (leader == 0) {
- createdExpressions.push_back(newVal);
- return newVal;
- } else {
- VN.erase(newVal);
- delete newVal;
- return leader;
- }
- }
-
- // Varargs operators
- } else if (GetElementPtrInst* U = dyn_cast<GetElementPtrInst>(V)) {
- Value* newOp1 = 0;
- if (isa<Instruction>(U->getPointerOperand()))
- newOp1 = phi_translate(U->getPointerOperand(), pred, succ);
- else
- newOp1 = U->getPointerOperand();
-
- if (newOp1 == 0)
- return 0;
-
- bool changed_idx = false;
- SmallVector<Value*, 4> newIdx;
- for (GetElementPtrInst::op_iterator I = U->idx_begin(), E = U->idx_end();
- I != E; ++I)
- if (isa<Instruction>(*I)) {
- Value* newVal = phi_translate(*I, pred, succ);
- newIdx.push_back(newVal);
- if (newVal != *I)
- changed_idx = true;
- } else {
- newIdx.push_back(*I);
- }
-
- if (newOp1 != U->getPointerOperand() || changed_idx) {
- Instruction* newVal =
- GetElementPtrInst::Create(newOp1,
- newIdx.begin(), newIdx.end(),
- U->getName()+".expr");
-
- uint32_t v = VN.lookup_or_add(newVal);
-
- Value* leader = find_leader(availableOut[pred], v);
- if (leader == 0) {
- createdExpressions.push_back(newVal);
- return newVal;
- } else {
- VN.erase(newVal);
- delete newVal;
- return leader;
- }
- }
-
- // PHI Nodes
- } else if (PHINode* P = dyn_cast<PHINode>(V)) {
- if (P->getParent() == succ)
- return P->getIncomingValueForBlock(pred);
- }
-
- return V;
-}
-
-/// phi_translate_set - Perform phi translation on every element of a set
-void GVNPRE::phi_translate_set(ValueNumberedSet& anticIn,
- BasicBlock* pred, BasicBlock* succ,
- ValueNumberedSet& out) {
- for (ValueNumberedSet::iterator I = anticIn.begin(),
- E = anticIn.end(); I != E; ++I) {
- Value* V = phi_translate(*I, pred, succ);
- if (V != 0 && !out.test(VN.lookup_or_add(V))) {
- out.insert(V);
- out.set(VN.lookup(V));
- }
- }
-}
-
-/// dependsOnInvoke - Test if a value has an phi node as an operand, any of
-/// whose inputs is an invoke instruction. If this is true, we cannot safely
-/// PRE the instruction or anything that depends on it.
-bool GVNPRE::dependsOnInvoke(Value* V) {
- if (PHINode* p = dyn_cast<PHINode>(V)) {
- for (PHINode::op_iterator I = p->op_begin(), E = p->op_end(); I != E; ++I)
- if (isa<InvokeInst>(*I))
- return true;
- return false;
- } else {
- return false;
- }
-}
-
-/// clean - Remove all non-opaque values from the set whose operands are not
-/// themselves in the set, as well as all values that depend on invokes (see
-/// above)
-void GVNPRE::clean(ValueNumberedSet& set) {
- SmallVector<Value*, 8> worklist;
- worklist.reserve(set.size());
- topo_sort(set, worklist);
-
- for (unsigned i = 0; i < worklist.size(); ++i) {
- Value* v = worklist[i];
-
- // Handle unary ops
- if (CastInst* U = dyn_cast<CastInst>(v)) {
- bool lhsValid = !isa<Instruction>(U->getOperand(0));
- lhsValid |= set.test(VN.lookup(U->getOperand(0)));
- if (lhsValid)
- lhsValid = !dependsOnInvoke(U->getOperand(0));
-
- if (!lhsValid) {
- set.erase(U);
- set.reset(VN.lookup(U));
- }
-
- // Handle binary ops
- } else if (isa<BinaryOperator>(v) || isa<CmpInst>(v) ||
- isa<ExtractElementInst>(v)) {
- User* U = cast<User>(v);
-
- bool lhsValid = !isa<Instruction>(U->getOperand(0));
- lhsValid |= set.test(VN.lookup(U->getOperand(0)));
- if (lhsValid)
- lhsValid = !dependsOnInvoke(U->getOperand(0));
-
- bool rhsValid = !isa<Instruction>(U->getOperand(1));
- rhsValid |= set.test(VN.lookup(U->getOperand(1)));
- if (rhsValid)
- rhsValid = !dependsOnInvoke(U->getOperand(1));
-
- if (!lhsValid || !rhsValid) {
- set.erase(U);
- set.reset(VN.lookup(U));
- }
-
- // Handle ternary ops
- } else if (isa<ShuffleVectorInst>(v) || isa<InsertElementInst>(v) ||
- isa<SelectInst>(v)) {
- User* U = cast<User>(v);
-
- bool lhsValid = !isa<Instruction>(U->getOperand(0));
- lhsValid |= set.test(VN.lookup(U->getOperand(0)));
- if (lhsValid)
- lhsValid = !dependsOnInvoke(U->getOperand(0));
-
- bool rhsValid = !isa<Instruction>(U->getOperand(1));
- rhsValid |= set.test(VN.lookup(U->getOperand(1)));
- if (rhsValid)
- rhsValid = !dependsOnInvoke(U->getOperand(1));
-
- bool thirdValid = !isa<Instruction>(U->getOperand(2));
- thirdValid |= set.test(VN.lookup(U->getOperand(2)));
- if (thirdValid)
- thirdValid = !dependsOnInvoke(U->getOperand(2));
-
- if (!lhsValid || !rhsValid || !thirdValid) {
- set.erase(U);
- set.reset(VN.lookup(U));
- }
-
- // Handle varargs ops
- } else if (GetElementPtrInst* U = dyn_cast<GetElementPtrInst>(v)) {
- bool ptrValid = !isa<Instruction>(U->getPointerOperand());
- ptrValid |= set.test(VN.lookup(U->getPointerOperand()));
- if (ptrValid)
- ptrValid = !dependsOnInvoke(U->getPointerOperand());
-
- bool varValid = true;
- for (GetElementPtrInst::op_iterator I = U->idx_begin(), E = U->idx_end();
- I != E; ++I)
- if (varValid) {
- varValid &= !isa<Instruction>(*I) || set.test(VN.lookup(*I));
- varValid &= !dependsOnInvoke(*I);
- }
-
- if (!ptrValid || !varValid) {
- set.erase(U);
- set.reset(VN.lookup(U));
- }
- }
- }
-}
-
-/// topo_sort - Given a set of values, sort them by topological
-/// order into the provided vector.
-void GVNPRE::topo_sort(ValueNumberedSet& set, SmallVector<Value*, 8>& vec) {
- SmallPtrSet<Value*, 16> visited;
- SmallVector<Value*, 8> stack;
- for (ValueNumberedSet::iterator I = set.begin(), E = set.end();
- I != E; ++I) {
- if (visited.count(*I) == 0)
- stack.push_back(*I);
-
- while (!stack.empty()) {
- Value* e = stack.back();
-
- // Handle unary ops
- if (CastInst* U = dyn_cast<CastInst>(e)) {
- Value* l = find_leader(set, VN.lookup(U->getOperand(0)));
-
- if (l != 0 && isa<Instruction>(l) &&
- visited.count(l) == 0)
- stack.push_back(l);
- else {
- vec.push_back(e);
- visited.insert(e);
- stack.pop_back();
- }
-
- // Handle binary ops
- } else if (isa<BinaryOperator>(e) || isa<CmpInst>(e) ||
- isa<ExtractElementInst>(e)) {
- User* U = cast<User>(e);
- Value* l = find_leader(set, VN.lookup(U->getOperand(0)));
- Value* r = find_leader(set, VN.lookup(U->getOperand(1)));
-
- if (l != 0 && isa<Instruction>(l) &&
- visited.count(l) == 0)
- stack.push_back(l);
- else if (r != 0 && isa<Instruction>(r) &&
- visited.count(r) == 0)
- stack.push_back(r);
- else {
- vec.push_back(e);
- visited.insert(e);
- stack.pop_back();
- }
-
- // Handle ternary ops
- } else if (isa<InsertElementInst>(e) || isa<ShuffleVectorInst>(e) ||
- isa<SelectInst>(e)) {
- User* U = cast<User>(e);
- Value* l = find_leader(set, VN.lookup(U->getOperand(0)));
- Value* r = find_leader(set, VN.lookup(U->getOperand(1)));
- Value* m = find_leader(set, VN.lookup(U->getOperand(2)));
-
- if (l != 0 && isa<Instruction>(l) &&
- visited.count(l) == 0)
- stack.push_back(l);
- else if (r != 0 && isa<Instruction>(r) &&
- visited.count(r) == 0)
- stack.push_back(r);
- else if (m != 0 && isa<Instruction>(m) &&
- visited.count(m) == 0)
- stack.push_back(m);
- else {
- vec.push_back(e);
- visited.insert(e);
- stack.pop_back();
- }
-
- // Handle vararg ops
- } else if (GetElementPtrInst* U = dyn_cast<GetElementPtrInst>(e)) {
- Value* p = find_leader(set, VN.lookup(U->getPointerOperand()));
-
- if (p != 0 && isa<Instruction>(p) &&
- visited.count(p) == 0)
- stack.push_back(p);
- else {
- bool push_va = false;
- for (GetElementPtrInst::op_iterator I = U->idx_begin(),
- E = U->idx_end(); I != E; ++I) {
- Value * v = find_leader(set, VN.lookup(*I));
- if (v != 0 && isa<Instruction>(v) && visited.count(v) == 0) {
- stack.push_back(v);
- push_va = true;
- }
- }
-
- if (!push_va) {
- vec.push_back(e);
- visited.insert(e);
- stack.pop_back();
- }
- }
-
- // Handle opaque ops
- } else {
- visited.insert(e);
- vec.push_back(e);
- stack.pop_back();
- }
- }
-
- stack.clear();
- }
-}
-
-/// dump - Dump a set of values to standard error
-void GVNPRE::dump(ValueNumberedSet& s) const {
- DEBUG(errs() << "{ ");
- for (ValueNumberedSet::iterator I = s.begin(), E = s.end();
- I != E; ++I) {
- DEBUG(errs() << "" << VN.lookup(*I) << ": ");
- DEBUG((*I)->dump());
- }
- DEBUG(errs() << "}\n\n");
-}
-
-/// elimination - Phase 3 of the main algorithm. Perform full redundancy
-/// elimination by walking the dominator tree and removing any instruction that
-/// is dominated by another instruction with the same value number.
-bool GVNPRE::elimination() {
- bool changed_function = false;
-
- SmallVector<std::pair<Instruction*, Value*>, 8> replace;
- SmallVector<Instruction*, 8> erase;
-
- DominatorTree& DT = getAnalysis<DominatorTree>();
-
- for (df_iterator<DomTreeNode*> DI = df_begin(DT.getRootNode()),
- E = df_end(DT.getRootNode()); DI != E; ++DI) {
- BasicBlock* BB = DI->getBlock();
-
- for (BasicBlock::iterator BI = BB->begin(), BE = BB->end();
- BI != BE; ++BI) {
-
- if (isa<BinaryOperator>(BI) || isa<CmpInst>(BI) ||
- isa<ShuffleVectorInst>(BI) || isa<InsertElementInst>(BI) ||
- isa<ExtractElementInst>(BI) || isa<SelectInst>(BI) ||
- isa<CastInst>(BI) || isa<GetElementPtrInst>(BI)) {
-
- if (availableOut[BB].test(VN.lookup(BI)) &&
- !availableOut[BB].count(BI)) {
- Value *leader = find_leader(availableOut[BB], VN.lookup(BI));
- if (Instruction* Instr = dyn_cast<Instruction>(leader))
- if (Instr->getParent() != 0 && Instr != BI) {
- replace.push_back(std::make_pair(BI, leader));
- erase.push_back(BI);
- ++NumEliminated;
- }
- }
- }
- }
- }
-
- while (!replace.empty()) {
- std::pair<Instruction*, Value*> rep = replace.back();
- replace.pop_back();
- rep.first->replaceAllUsesWith(rep.second);
- changed_function = true;
- }
-
- for (SmallVector<Instruction*, 8>::iterator I = erase.begin(),
- E = erase.end(); I != E; ++I)
- (*I)->eraseFromParent();
-
- return changed_function;
-}
-
-/// cleanup - Delete any extraneous values that were created to represent
-/// expressions without leaders.
-void GVNPRE::cleanup() {
- while (!createdExpressions.empty()) {
- Instruction* I = createdExpressions.back();
- createdExpressions.pop_back();
-
- delete I;
- }
-}
-
-/// buildsets_availout - When calculating availability, handle an instruction
-/// by inserting it into the appropriate sets
-void GVNPRE::buildsets_availout(BasicBlock::iterator I,
- ValueNumberedSet& currAvail,
- ValueNumberedSet& currPhis,
- ValueNumberedSet& currExps,
- SmallPtrSet<Value*, 16>& currTemps) {
- // Handle PHI nodes
- if (PHINode* p = dyn_cast<PHINode>(I)) {
- unsigned num = VN.lookup_or_add(p);
-
- currPhis.insert(p);
- currPhis.set(num);
-
- // Handle unary ops
- } else if (CastInst* U = dyn_cast<CastInst>(I)) {
- Value* leftValue = U->getOperand(0);
-
- unsigned num = VN.lookup_or_add(U);
-
- if (isa<Instruction>(leftValue))
- if (!currExps.test(VN.lookup(leftValue))) {
- currExps.insert(leftValue);
- currExps.set(VN.lookup(leftValue));
- }
-
- if (!currExps.test(num)) {
- currExps.insert(U);
- currExps.set(num);
- }
-
- // Handle binary ops
- } else if (isa<BinaryOperator>(I) || isa<CmpInst>(I) ||
- isa<ExtractElementInst>(I)) {
- User* U = cast<User>(I);
- Value* leftValue = U->getOperand(0);
- Value* rightValue = U->getOperand(1);
-
- unsigned num = VN.lookup_or_add(U);
-
- if (isa<Instruction>(leftValue))
- if (!currExps.test(VN.lookup(leftValue))) {
- currExps.insert(leftValue);
- currExps.set(VN.lookup(leftValue));
- }
-
- if (isa<Instruction>(rightValue))
- if (!currExps.test(VN.lookup(rightValue))) {
- currExps.insert(rightValue);
- currExps.set(VN.lookup(rightValue));
- }
-
- if (!currExps.test(num)) {
- currExps.insert(U);
- currExps.set(num);
- }
-
- // Handle ternary ops
- } else if (isa<InsertElementInst>(I) || isa<ShuffleVectorInst>(I) ||
- isa<SelectInst>(I)) {
- User* U = cast<User>(I);
- Value* leftValue = U->getOperand(0);
- Value* rightValue = U->getOperand(1);
- Value* thirdValue = U->getOperand(2);
-
- VN.lookup_or_add(U);
-
- unsigned num = VN.lookup_or_add(U);
-
- if (isa<Instruction>(leftValue))
- if (!currExps.test(VN.lookup(leftValue))) {
- currExps.insert(leftValue);
- currExps.set(VN.lookup(leftValue));
- }
- if (isa<Instruction>(rightValue))
- if (!currExps.test(VN.lookup(rightValue))) {
- currExps.insert(rightValue);
- currExps.set(VN.lookup(rightValue));
- }
- if (isa<Instruction>(thirdValue))
- if (!currExps.test(VN.lookup(thirdValue))) {
- currExps.insert(thirdValue);
- currExps.set(VN.lookup(thirdValue));
- }
-
- if (!currExps.test(num)) {
- currExps.insert(U);
- currExps.set(num);
- }
-
- // Handle vararg ops
- } else if (GetElementPtrInst* U = dyn_cast<GetElementPtrInst>(I)) {
- Value* ptrValue = U->getPointerOperand();
-
- VN.lookup_or_add(U);
-
- unsigned num = VN.lookup_or_add(U);
-
- if (isa<Instruction>(ptrValue))
- if (!currExps.test(VN.lookup(ptrValue))) {
- currExps.insert(ptrValue);
- currExps.set(VN.lookup(ptrValue));
- }
-
- for (GetElementPtrInst::op_iterator OI = U->idx_begin(), OE = U->idx_end();
- OI != OE; ++OI)
- if (isa<Instruction>(*OI) && !currExps.test(VN.lookup(*OI))) {
- currExps.insert(*OI);
- currExps.set(VN.lookup(*OI));
- }
-
- if (!currExps.test(VN.lookup(U))) {
- currExps.insert(U);
- currExps.set(num);
- }
-
- // Handle opaque ops
- } else if (!I->isTerminator()){
- VN.lookup_or_add(I);
-
- currTemps.insert(I);
- }
-
- if (!I->isTerminator())
- if (!currAvail.test(VN.lookup(I))) {
- currAvail.insert(I);
- currAvail.set(VN.lookup(I));
- }
-}
-
-/// buildsets_anticout - When walking the postdom tree, calculate the ANTIC_OUT
-/// set as a function of the ANTIC_IN set of the block's predecessors
-bool GVNPRE::buildsets_anticout(BasicBlock* BB,
- ValueNumberedSet& anticOut,
- SmallPtrSet<BasicBlock*, 8>& visited) {
- if (BB->getTerminator()->getNumSuccessors() == 1) {
- if (BB->getTerminator()->getSuccessor(0) != BB &&
- visited.count(BB->getTerminator()->getSuccessor(0)) == 0) {
- return true;
- }
- else {
- phi_translate_set(anticipatedIn[BB->getTerminator()->getSuccessor(0)],
- BB, BB->getTerminator()->getSuccessor(0), anticOut);
- }
- } else if (BB->getTerminator()->getNumSuccessors() > 1) {
- BasicBlock* first = BB->getTerminator()->getSuccessor(0);
- for (ValueNumberedSet::iterator I = anticipatedIn[first].begin(),
- E = anticipatedIn[first].end(); I != E; ++I) {
- anticOut.insert(*I);
- anticOut.set(VN.lookup(*I));
- }
-
- for (unsigned i = 1; i < BB->getTerminator()->getNumSuccessors(); ++i) {
- BasicBlock* currSucc = BB->getTerminator()->getSuccessor(i);
- ValueNumberedSet& succAnticIn = anticipatedIn[currSucc];
-
- SmallVector<Value*, 16> temp;
-
- for (ValueNumberedSet::iterator I = anticOut.begin(),
- E = anticOut.end(); I != E; ++I)
- if (!succAnticIn.test(VN.lookup(*I)))
- temp.push_back(*I);
-
- for (SmallVector<Value*, 16>::iterator I = temp.begin(), E = temp.end();
- I != E; ++I) {
- anticOut.erase(*I);
- anticOut.reset(VN.lookup(*I));
- }
- }
- }
-
- return false;
-}
-
-/// buildsets_anticin - Walk the postdom tree, calculating ANTIC_OUT for
-/// each block. ANTIC_IN is then a function of ANTIC_OUT and the GEN
-/// sets populated in buildsets_availout
-unsigned GVNPRE::buildsets_anticin(BasicBlock* BB,
- ValueNumberedSet& anticOut,
- ValueNumberedSet& currExps,
- SmallPtrSet<Value*, 16>& currTemps,
- SmallPtrSet<BasicBlock*, 8>& visited) {
- ValueNumberedSet& anticIn = anticipatedIn[BB];
- unsigned old = anticIn.size();
-
- bool defer = buildsets_anticout(BB, anticOut, visited);
- if (defer)
- return 0;
-
- anticIn.clear();
-
- for (ValueNumberedSet::iterator I = anticOut.begin(),
- E = anticOut.end(); I != E; ++I) {
- anticIn.insert(*I);
- anticIn.set(VN.lookup(*I));
- }
- for (ValueNumberedSet::iterator I = currExps.begin(),
- E = currExps.end(); I != E; ++I) {
- if (!anticIn.test(VN.lookup(*I))) {
- anticIn.insert(*I);
- anticIn.set(VN.lookup(*I));
- }
- }
-
- for (SmallPtrSet<Value*, 16>::iterator I = currTemps.begin(),
- E = currTemps.end(); I != E; ++I) {
- anticIn.erase(*I);
- anticIn.reset(VN.lookup(*I));
- }
-
- clean(anticIn);
- anticOut.clear();
-
- if (old != anticIn.size())
- return 2;
- else
- return 1;
-}
-
-/// buildsets - Phase 1 of the main algorithm. Construct the AVAIL_OUT
-/// and the ANTIC_IN sets.
-void GVNPRE::buildsets(Function& F) {
- DenseMap<BasicBlock*, ValueNumberedSet> generatedExpressions;
- DenseMap<BasicBlock*, SmallPtrSet<Value*, 16> > generatedTemporaries;
-
- DominatorTree &DT = getAnalysis<DominatorTree>();
-
- // Phase 1, Part 1: calculate AVAIL_OUT
-
- // Top-down walk of the dominator tree
- for (df_iterator<DomTreeNode*> DI = df_begin(DT.getRootNode()),
- E = df_end(DT.getRootNode()); DI != E; ++DI) {
-
- // Get the sets to update for this block
- ValueNumberedSet& currExps = generatedExpressions[DI->getBlock()];
- ValueNumberedSet& currPhis = generatedPhis[DI->getBlock()];
- SmallPtrSet<Value*, 16>& currTemps = generatedTemporaries[DI->getBlock()];
- ValueNumberedSet& currAvail = availableOut[DI->getBlock()];
-
- BasicBlock* BB = DI->getBlock();
-
- // A block inherits AVAIL_OUT from its dominator
- if (DI->getIDom() != 0)
- currAvail = availableOut[DI->getIDom()->getBlock()];
-
- for (BasicBlock::iterator BI = BB->begin(), BE = BB->end();
- BI != BE; ++BI)
- buildsets_availout(BI, currAvail, currPhis, currExps,
- currTemps);
-
- }
-
- // Phase 1, Part 2: calculate ANTIC_IN
-
- SmallPtrSet<BasicBlock*, 8> visited;
- SmallPtrSet<BasicBlock*, 4> block_changed;
- for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
- block_changed.insert(FI);
-
- bool changed = true;
- unsigned iterations = 0;
-
- while (changed) {
- changed = false;
- ValueNumberedSet anticOut;
-
- // Postorder walk of the CFG
- for (po_iterator<BasicBlock*> BBI = po_begin(&F.getEntryBlock()),
- BBE = po_end(&F.getEntryBlock()); BBI != BBE; ++BBI) {
- BasicBlock* BB = *BBI;
-
- if (block_changed.count(BB) != 0) {
- unsigned ret = buildsets_anticin(BB, anticOut,generatedExpressions[BB],
- generatedTemporaries[BB], visited);
-
- if (ret == 0) {
- changed = true;
- continue;
- } else {
- visited.insert(BB);
-
- if (ret == 2)
- for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB);
- PI != PE; ++PI) {
- block_changed.insert(*PI);
- }
- else
- block_changed.erase(BB);
-
- changed |= (ret == 2);
- }
- }
- }
-
- iterations++;
- }
-}
-
-/// insertion_pre - When a partial redundancy has been identified, eliminate it
-/// by inserting appropriate values into the predecessors and a phi node in
-/// the main block
-void GVNPRE::insertion_pre(Value* e, BasicBlock* BB,
- DenseMap<BasicBlock*, Value*>& avail,
- std::map<BasicBlock*, ValueNumberedSet>& new_sets) {
- for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; ++PI) {
- Value* e2 = avail[*PI];
- if (!availableOut[*PI].test(VN.lookup(e2))) {
- User* U = cast<User>(e2);
-
- Value* s1 = 0;
- if (isa<BinaryOperator>(U->getOperand(0)) ||
- isa<CmpInst>(U->getOperand(0)) ||
- isa<ShuffleVectorInst>(U->getOperand(0)) ||
- isa<ExtractElementInst>(U->getOperand(0)) ||
- isa<InsertElementInst>(U->getOperand(0)) ||
- isa<SelectInst>(U->getOperand(0)) ||
- isa<CastInst>(U->getOperand(0)) ||
- isa<GetElementPtrInst>(U->getOperand(0)))
- s1 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(0)));
- else
- s1 = U->getOperand(0);
-
- Value* s2 = 0;
-
- if (isa<BinaryOperator>(U) ||
- isa<CmpInst>(U) ||
- isa<ShuffleVectorInst>(U) ||
- isa<ExtractElementInst>(U) ||
- isa<InsertElementInst>(U) ||
- isa<SelectInst>(U)) {
- if (isa<BinaryOperator>(U->getOperand(1)) ||
- isa<CmpInst>(U->getOperand(1)) ||
- isa<ShuffleVectorInst>(U->getOperand(1)) ||
- isa<ExtractElementInst>(U->getOperand(1)) ||
- isa<InsertElementInst>(U->getOperand(1)) ||
- isa<SelectInst>(U->getOperand(1)) ||
- isa<CastInst>(U->getOperand(1)) ||
- isa<GetElementPtrInst>(U->getOperand(1))) {
- s2 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(1)));
- } else {
- s2 = U->getOperand(1);
- }
- }
-
- // Ternary Operators
- Value* s3 = 0;
- if (isa<ShuffleVectorInst>(U) ||
- isa<InsertElementInst>(U) ||
- isa<SelectInst>(U)) {
- if (isa<BinaryOperator>(U->getOperand(2)) ||
- isa<CmpInst>(U->getOperand(2)) ||
- isa<ShuffleVectorInst>(U->getOperand(2)) ||
- isa<ExtractElementInst>(U->getOperand(2)) ||
- isa<InsertElementInst>(U->getOperand(2)) ||
- isa<SelectInst>(U->getOperand(2)) ||
- isa<CastInst>(U->getOperand(2)) ||
- isa<GetElementPtrInst>(U->getOperand(2))) {
- s3 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(2)));
- } else {
- s3 = U->getOperand(2);
- }
- }
-
- // Vararg operators
- SmallVector<Value*, 4> sVarargs;
- if (GetElementPtrInst* G = dyn_cast<GetElementPtrInst>(U)) {
- for (GetElementPtrInst::op_iterator OI = G->idx_begin(),
- OE = G->idx_end(); OI != OE; ++OI) {
- if (isa<BinaryOperator>(*OI) ||
- isa<CmpInst>(*OI) ||
- isa<ShuffleVectorInst>(*OI) ||
- isa<ExtractElementInst>(*OI) ||
- isa<InsertElementInst>(*OI) ||
- isa<SelectInst>(*OI) ||
- isa<CastInst>(*OI) ||
- isa<GetElementPtrInst>(*OI)) {
- sVarargs.push_back(find_leader(availableOut[*PI],
- VN.lookup(*OI)));
- } else {
- sVarargs.push_back(*OI);
- }
- }
- }
-
- Value* newVal = 0;
- if (BinaryOperator* BO = dyn_cast<BinaryOperator>(U))
- newVal = BinaryOperator::Create(BO->getOpcode(), s1, s2,
- BO->getName()+".gvnpre",
- (*PI)->getTerminator());
- else if (CmpInst* C = dyn_cast<CmpInst>(U))
- newVal = CmpInst::Create(C->getOpcode(),
- C->getPredicate(), s1, s2,
- C->getName()+".gvnpre",
- (*PI)->getTerminator());
- else if (ShuffleVectorInst* S = dyn_cast<ShuffleVectorInst>(U))
- newVal = new ShuffleVectorInst(s1, s2, s3, S->getName()+".gvnpre",
- (*PI)->getTerminator());
- else if (InsertElementInst* S = dyn_cast<InsertElementInst>(U))
- newVal = InsertElementInst::Create(s1, s2, s3, S->getName()+".gvnpre",
- (*PI)->getTerminator());
- else if (ExtractElementInst* S = dyn_cast<ExtractElementInst>(U))
- newVal = ExtractElementInst::Create(s1, s2, S->getName()+".gvnpre",
- (*PI)->getTerminator());
- else if (SelectInst* S = dyn_cast<SelectInst>(U))
- newVal = SelectInst::Create(s1, s2, s3, S->getName()+".gvnpre",
- (*PI)->getTerminator());
- else if (CastInst* C = dyn_cast<CastInst>(U))
- newVal = CastInst::Create(C->getOpcode(), s1, C->getType(),
- C->getName()+".gvnpre",
- (*PI)->getTerminator());
- else if (GetElementPtrInst* G = dyn_cast<GetElementPtrInst>(U))
- newVal = GetElementPtrInst::Create(s1, sVarargs.begin(), sVarargs.end(),
- G->getName()+".gvnpre",
- (*PI)->getTerminator());
-
- VN.add(newVal, VN.lookup(U));
-
- ValueNumberedSet& predAvail = availableOut[*PI];
- val_replace(predAvail, newVal);
- val_replace(new_sets[*PI], newVal);
- predAvail.set(VN.lookup(newVal));
-
- DenseMap<BasicBlock*, Value*>::iterator av = avail.find(*PI);
- if (av != avail.end())
- avail.erase(av);
- avail.insert(std::make_pair(*PI, newVal));
-
- ++NumInsertedVals;
- }
- }
-
- PHINode* p = 0;
-
- for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; ++PI) {
- if (p == 0)
- p = PHINode::Create(avail[*PI]->getType(), "gvnpre-join", BB->begin());
-
- p->addIncoming(avail[*PI], *PI);
- }
-
- VN.add(p, VN.lookup(e));
- val_replace(availableOut[BB], p);
- availableOut[BB].set(VN.lookup(e));
- generatedPhis[BB].insert(p);
- generatedPhis[BB].set(VN.lookup(e));
- new_sets[BB].insert(p);
- new_sets[BB].set(VN.lookup(e));
-
- ++NumInsertedPhis;
-}
-
-/// insertion_mergepoint - When walking the dom tree, check at each merge
-/// block for the possibility of a partial redundancy. If present, eliminate it
-unsigned GVNPRE::insertion_mergepoint(SmallVector<Value*, 8>& workList,
- df_iterator<DomTreeNode*>& D,
- std::map<BasicBlock*, ValueNumberedSet >& new_sets) {
- bool changed_function = false;
- bool new_stuff = false;
-
- BasicBlock* BB = D->getBlock();
- for (unsigned i = 0; i < workList.size(); ++i) {
- Value* e = workList[i];
-
- if (isa<BinaryOperator>(e) || isa<CmpInst>(e) ||
- isa<ExtractElementInst>(e) || isa<InsertElementInst>(e) ||
- isa<ShuffleVectorInst>(e) || isa<SelectInst>(e) || isa<CastInst>(e) ||
- isa<GetElementPtrInst>(e)) {
- if (availableOut[D->getIDom()->getBlock()].test(VN.lookup(e)))
- continue;
-
- DenseMap<BasicBlock*, Value*> avail;
- bool by_some = false;
- bool all_same = true;
- Value * first_s = 0;
-
- for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE;
- ++PI) {
- Value *e2 = phi_translate(e, *PI, BB);
- Value *e3 = find_leader(availableOut[*PI], VN.lookup(e2));
-
- if (e3 == 0) {
- DenseMap<BasicBlock*, Value*>::iterator av = avail.find(*PI);
- if (av != avail.end())
- avail.erase(av);
- avail.insert(std::make_pair(*PI, e2));
- all_same = false;
- } else {
- DenseMap<BasicBlock*, Value*>::iterator av = avail.find(*PI);
- if (av != avail.end())
- avail.erase(av);
- avail.insert(std::make_pair(*PI, e3));
-
- by_some = true;
- if (first_s == 0)
- first_s = e3;
- else if (first_s != e3)
- all_same = false;
- }
- }
-
- if (by_some && !all_same &&
- !generatedPhis[BB].test(VN.lookup(e))) {
- insertion_pre(e, BB, avail, new_sets);
-
- changed_function = true;
- new_stuff = true;
- }
- }
- }
-
- unsigned retval = 0;
- if (changed_function)
- retval += 1;
- if (new_stuff)
- retval += 2;
-
- return retval;
-}
-
-/// insert - Phase 2 of the main algorithm. Walk the dominator tree looking for
-/// merge points. When one is found, check for a partial redundancy. If one is
-/// present, eliminate it. Repeat this walk until no changes are made.
-bool GVNPRE::insertion(Function& F) {
- bool changed_function = false;
-
- DominatorTree &DT = getAnalysis<DominatorTree>();
-
- std::map<BasicBlock*, ValueNumberedSet> new_sets;
- bool new_stuff = true;
- while (new_stuff) {
- new_stuff = false;
- for (df_iterator<DomTreeNode*> DI = df_begin(DT.getRootNode()),
- E = df_end(DT.getRootNode()); DI != E; ++DI) {
- BasicBlock* BB = DI->getBlock();
-
- if (BB == 0)
- continue;
-
- ValueNumberedSet& availOut = availableOut[BB];
- ValueNumberedSet& anticIn = anticipatedIn[BB];
-
- // Replace leaders with leaders inherited from dominator
- if (DI->getIDom() != 0) {
- ValueNumberedSet& dom_set = new_sets[DI->getIDom()->getBlock()];
- for (ValueNumberedSet::iterator I = dom_set.begin(),
- E = dom_set.end(); I != E; ++I) {
- val_replace(new_sets[BB], *I);
- val_replace(availOut, *I);
- }
- }
-
- // If there is more than one predecessor...
- if (pred_begin(BB) != pred_end(BB) && ++pred_begin(BB) != pred_end(BB)) {
- SmallVector<Value*, 8> workList;
- workList.reserve(anticIn.size());
- topo_sort(anticIn, workList);
-
- unsigned result = insertion_mergepoint(workList, DI, new_sets);
- if (result & 1)
- changed_function = true;
- if (result & 2)
- new_stuff = true;
- }
- }
- }
-
- return changed_function;
-}
-
-// GVNPRE::runOnFunction - This is the main transformation entry point for a
-// function.
-//
-bool GVNPRE::runOnFunction(Function &F) {
- // Clean out global sets from any previous functions
- VN.clear();
- createdExpressions.clear();
- availableOut.clear();
- anticipatedIn.clear();
- generatedPhis.clear();
-
- bool changed_function = false;
-
- // Phase 1: BuildSets
- // This phase calculates the AVAIL_OUT and ANTIC_IN sets
- buildsets(F);
-
- // Phase 2: Insert
- // This phase inserts values to make partially redundant values
- // fully redundant
- changed_function |= insertion(F);
-
- // Phase 3: Eliminate
- // This phase performs trivial full redundancy elimination
- changed_function |= elimination();
-
- // Phase 4: Cleanup
- // This phase cleans up values that were created solely
- // as leaders for expressions
- cleanup();
-
- return changed_function;
-}
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
index ceca452..e2d9e0b 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
@@ -51,7 +51,6 @@
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/LoopPass.h"
#include "llvm/Support/CFG.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
@@ -68,7 +67,7 @@ STATISTIC(NumReplaced, "Number of exit values replaced");
STATISTIC(NumLFTR , "Number of loop exit tests replaced");
namespace {
- class VISIBILITY_HIDDEN IndVarSimplify : public LoopPass {
+ class IndVarSimplify : public LoopPass {
IVUsers *IU;
LoopInfo *LI;
ScalarEvolution *SE;
@@ -293,7 +292,7 @@ void IndVarSimplify::RewriteLoopExitValues(Loop *L,
if (NumPreds != 1) {
// Clone the PHI and delete the original one. This lets IVUsers and
// any other maps purge the original user from their records.
- PHINode *NewPN = PN->clone(PN->getContext());
+ PHINode *NewPN = PN->clone();
NewPN->takeName(PN);
NewPN->insertBefore(PN);
PN->replaceAllUsesWith(NewPN);
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/InstructionCombining.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/InstructionCombining.cpp
index b4bb0a8..561527c 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -42,6 +42,7 @@
#include "llvm/GlobalVariable.h"
#include "llvm/Operator.h"
#include "llvm/Analysis/ConstantFolding.h"
+#include "llvm/Analysis/MallocHelper.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
@@ -55,7 +56,6 @@
#include "llvm/Support/IRBuilder.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/PatternMatch.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
@@ -90,6 +90,7 @@ namespace {
/// Add - Add the specified instruction to the worklist if it isn't already
/// in it.
void Add(Instruction *I) {
+ DEBUG(errs() << "IC: ADD: " << *I << '\n');
if (WorklistMap.insert(std::make_pair(I, Worklist.size())).second)
Worklist.push_back(I);
}
@@ -159,9 +160,8 @@ namespace {
namespace {
- class VISIBILITY_HIDDEN InstCombiner
- : public FunctionPass,
- public InstVisitor<InstCombiner, Instruction*> {
+ class InstCombiner : public FunctionPass,
+ public InstVisitor<InstCombiner, Instruction*> {
TargetData *TD;
bool MustPreserveLCSSA;
bool MadeIRChange;
@@ -328,7 +328,7 @@ namespace {
// instruction. Instead, visit methods should return the value returned by
// this function.
Instruction *EraseInstFromFunction(Instruction &I) {
- DEBUG(errs() << "IC: erase " << I);
+ DEBUG(errs() << "IC: ERASE " << I << '\n');
assert(I.use_empty() && "Cannot erase instruction that is used!");
// Make sure that we reprocess all operands now that we reduced their
@@ -384,10 +384,15 @@ namespace {
Value *SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
APInt& UndefElts, unsigned Depth = 0);
- // FoldOpIntoPhi - Given a binary operator or cast instruction which has a
- // PHI node as operand #0, see if we can fold the instruction into the PHI
- // (which is only possible if all operands to the PHI are constants).
- Instruction *FoldOpIntoPhi(Instruction &I);
+ // FoldOpIntoPhi - Given a binary operator, cast instruction, or select
+ // which has a PHI node as operand #0, see if we can fold the instruction
+ // into the PHI (which is only possible if all operands to the PHI are
+ // constants).
+ //
+ // If AllowAggressive is true, FoldOpIntoPhi will allow certain transforms
+ // that would normally be unprofitable because they strongly encourage jump
+ // threading.
+ Instruction *FoldOpIntoPhi(Instruction &I, bool AllowAggressive = false);
// FoldPHIArgOpIntoPHI - If all operands to a PHI node are the same "unary"
// operator and they all are only used by the PHI, PHI together their
@@ -1938,20 +1943,34 @@ static Instruction *FoldOpIntoSelect(Instruction &Op, SelectInst *SI,
}
-/// FoldOpIntoPhi - Given a binary operator or cast instruction which has a PHI
-/// node as operand #0, see if we can fold the instruction into the PHI (which
-/// is only possible if all operands to the PHI are constants).
-Instruction *InstCombiner::FoldOpIntoPhi(Instruction &I) {
+/// FoldOpIntoPhi - Given a binary operator, cast instruction, or select which
+/// has a PHI node as operand #0, see if we can fold the instruction into the
+/// PHI (which is only possible if all operands to the PHI are constants).
+///
+/// If AllowAggressive is true, FoldOpIntoPhi will allow certain transforms
+/// that would normally be unprofitable because they strongly encourage jump
+/// threading.
+Instruction *InstCombiner::FoldOpIntoPhi(Instruction &I,
+ bool AllowAggressive) {
+ AllowAggressive = false;
PHINode *PN = cast<PHINode>(I.getOperand(0));
unsigned NumPHIValues = PN->getNumIncomingValues();
- if (!PN->hasOneUse() || NumPHIValues == 0) return 0;
-
- // Check to see if all of the operands of the PHI are constants. If there is
- // one non-constant value, remember the BB it is. If there is more than one
- // or if *it* is a PHI, bail out.
+ if (NumPHIValues == 0 ||
+ // We normally only transform phis with a single use, unless we're trying
+ // hard to make jump threading happen.
+ (!PN->hasOneUse() && !AllowAggressive))
+ return 0;
+
+
+ // Check to see if all of the operands of the PHI are simple constants
+ // (constantint/constantfp/undef). If there is one non-constant value,
+ // remember the BB it is in. If there is more than one or if *it* is a PHI,
+ // bail out. We don't do arbitrary constant expressions here because moving
+ // their computation can be expensive without a cost model.
BasicBlock *NonConstBB = 0;
for (unsigned i = 0; i != NumPHIValues; ++i)
- if (!isa<Constant>(PN->getIncomingValue(i))) {
+ if (!isa<Constant>(PN->getIncomingValue(i)) ||
+ isa<ConstantExpr>(PN->getIncomingValue(i))) {
if (NonConstBB) return 0; // More than one non-const value.
if (isa<PHINode>(PN->getIncomingValue(i))) return 0; // Itself a phi.
NonConstBB = PN->getIncomingBlock(i);
@@ -1966,7 +1985,7 @@ Instruction *InstCombiner::FoldOpIntoPhi(Instruction &I) {
// operation in that block. However, if this is a critical edge, we would be
// inserting the computation one some other paths (e.g. inside a loop). Only
// do this if the pred block is unconditionally branching into the phi block.
- if (NonConstBB) {
+ if (NonConstBB != 0 && !AllowAggressive) {
BranchInst *BI = dyn_cast<BranchInst>(NonConstBB->getTerminator());
if (!BI || !BI->isUnconditional()) return 0;
}
@@ -1978,7 +1997,29 @@ Instruction *InstCombiner::FoldOpIntoPhi(Instruction &I) {
NewPN->takeName(PN);
// Next, add all of the operands to the PHI.
- if (I.getNumOperands() == 2) {
+ if (SelectInst *SI = dyn_cast<SelectInst>(&I)) {
+ // We only currently try to fold the condition of a select when it is a phi,
+ // not the true/false values.
+ Value *TrueV = SI->getTrueValue();
+ Value *FalseV = SI->getFalseValue();
+ BasicBlock *PhiTransBB = PN->getParent();
+ for (unsigned i = 0; i != NumPHIValues; ++i) {
+ BasicBlock *ThisBB = PN->getIncomingBlock(i);
+ Value *TrueVInPred = TrueV->DoPHITranslation(PhiTransBB, ThisBB);
+ Value *FalseVInPred = FalseV->DoPHITranslation(PhiTransBB, ThisBB);
+ Value *InV = 0;
+ if (Constant *InC = dyn_cast<Constant>(PN->getIncomingValue(i))) {
+ InV = InC->isNullValue() ? FalseVInPred : TrueVInPred;
+ } else {
+ assert(PN->getIncomingBlock(i) == NonConstBB);
+ InV = SelectInst::Create(PN->getIncomingValue(i), TrueVInPred,
+ FalseVInPred,
+ "phitmp", NonConstBB->getTerminator());
+ Worklist.Add(cast<Instruction>(InV));
+ }
+ NewPN->addIncoming(InV, ThisBB);
+ }
+ } else if (I.getNumOperands() == 2) {
Constant *C = cast<Constant>(I.getOperand(1));
for (unsigned i = 0; i != NumPHIValues; ++i) {
Value *InV = 0;
@@ -5779,9 +5820,9 @@ Instruction *InstCombiner::visitFCmpInst(FCmpInst &I) {
// Fold trivial predicates.
if (I.getPredicate() == FCmpInst::FCMP_FALSE)
- return ReplaceInstUsesWith(I, ConstantInt::getFalse(*Context));
+ return ReplaceInstUsesWith(I, ConstantInt::get(I.getType(), 0));
if (I.getPredicate() == FCmpInst::FCMP_TRUE)
- return ReplaceInstUsesWith(I, ConstantInt::getTrue(*Context));
+ return ReplaceInstUsesWith(I, ConstantInt::get(I.getType(), 1));
// Simplify 'fcmp pred X, X'
if (Op0 == Op1) {
@@ -5790,11 +5831,11 @@ Instruction *InstCombiner::visitFCmpInst(FCmpInst &I) {
case FCmpInst::FCMP_UEQ: // True if unordered or equal
case FCmpInst::FCMP_UGE: // True if unordered, greater than, or equal
case FCmpInst::FCMP_ULE: // True if unordered, less than, or equal
- return ReplaceInstUsesWith(I, ConstantInt::getTrue(*Context));
+ return ReplaceInstUsesWith(I, ConstantInt::get(I.getType(), 1));
case FCmpInst::FCMP_OGT: // True if ordered and greater than
case FCmpInst::FCMP_OLT: // True if ordered and less than
case FCmpInst::FCMP_ONE: // True if ordered and operands are unequal
- return ReplaceInstUsesWith(I, ConstantInt::getFalse(*Context));
+ return ReplaceInstUsesWith(I, ConstantInt::get(I.getType(), 0));
case FCmpInst::FCMP_UNO: // True if unordered: isnan(X) | isnan(Y)
case FCmpInst::FCMP_ULT: // True if unordered or less than
@@ -5817,7 +5858,7 @@ Instruction *InstCombiner::visitFCmpInst(FCmpInst &I) {
}
if (isa<UndefValue>(Op1)) // fcmp pred X, undef -> undef
- return ReplaceInstUsesWith(I, UndefValue::get(Type::getInt1Ty(*Context)));
+ return ReplaceInstUsesWith(I, UndefValue::get(I.getType()));
// Handle fcmp with constant RHS
if (Constant *RHSC = dyn_cast<Constant>(Op1)) {
@@ -5840,7 +5881,7 @@ Instruction *InstCombiner::visitFCmpInst(FCmpInst &I) {
// block. If in the same block, we're encouraging jump threading. If
// not, we are just pessimizing the code by making an i1 phi.
if (LHSI->getParent() == I.getParent())
- if (Instruction *NV = FoldOpIntoPhi(I))
+ if (Instruction *NV = FoldOpIntoPhi(I, true))
return NV;
break;
case Instruction::SIToFP:
@@ -5885,17 +5926,17 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {
// icmp X, X
if (Op0 == Op1)
- return ReplaceInstUsesWith(I, ConstantInt::get(Type::getInt1Ty(*Context),
+ return ReplaceInstUsesWith(I, ConstantInt::get(I.getType(),
I.isTrueWhenEqual()));
if (isa<UndefValue>(Op1)) // X icmp undef -> undef
- return ReplaceInstUsesWith(I, UndefValue::get(Type::getInt1Ty(*Context)));
+ return ReplaceInstUsesWith(I, UndefValue::get(I.getType()));
// icmp <global/alloca*/null>, <global/alloca*/null> - Global/Stack value
// addresses never equal each other! We already know that Op0 != Op1.
- if ((isa<GlobalValue>(Op0) || isa<AllocaInst>(Op0) ||
+ if ((isa<GlobalValue>(Op0) || isa<AllocaInst>(Op0) || isMalloc(Op0) ||
isa<ConstantPointerNull>(Op0)) &&
- (isa<GlobalValue>(Op1) || isa<AllocaInst>(Op1) ||
+ (isa<GlobalValue>(Op1) || isa<AllocaInst>(Op1) || isMalloc(Op1) ||
isa<ConstantPointerNull>(Op1)))
return ReplaceInstUsesWith(I, ConstantInt::get(Type::getInt1Ty(*Context),
!I.isTrueWhenEqual()));
@@ -6196,11 +6237,11 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {
break;
case Instruction::PHI:
- // Only fold icmp into the PHI if the phi and fcmp are in the same
+ // Only fold icmp into the PHI if the phi and icmp are in the same
// block. If in the same block, we're encouraging jump threading. If
// not, we are just pessimizing the code by making an i1 phi.
if (LHSI->getParent() == I.getParent())
- if (Instruction *NV = FoldOpIntoPhi(I))
+ if (Instruction *NV = FoldOpIntoPhi(I, true))
return NV;
break;
case Instruction::Select: {
@@ -6233,8 +6274,20 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {
// can assume it is successful and remove the malloc.
if (LHSI->hasOneUse() && isa<ConstantPointerNull>(RHSC)) {
Worklist.Add(LHSI);
- return ReplaceInstUsesWith(I, ConstantInt::get(Type::getInt1Ty(*Context),
- !I.isTrueWhenEqual()));
+ return ReplaceInstUsesWith(I,
+ ConstantInt::get(Type::getInt1Ty(*Context),
+ !I.isTrueWhenEqual()));
+ }
+ break;
+ case Instruction::Call:
+ // If we have (malloc != null), and if the malloc has a single use, we
+ // can assume it is successful and remove the malloc.
+ if (isMalloc(LHSI) && LHSI->hasOneUse() &&
+ isa<ConstantPointerNull>(RHSC)) {
+ Worklist.Add(LHSI);
+ return ReplaceInstUsesWith(I,
+ ConstantInt::get(Type::getInt1Ty(*Context),
+ !I.isTrueWhenEqual()));
}
break;
}
@@ -8088,11 +8141,11 @@ Instruction *InstCombiner::commonPointerCastTransforms(CastInst &CI) {
// If we were able to index down into an element, create the GEP
// and bitcast the result. This eliminates one bitcast, potentially
// two.
- Value *NGEP = Builder->CreateGEP(OrigBase, NewIndices.begin(),
- NewIndices.end());
+ Value *NGEP = cast<GEPOperator>(GEP)->isInBounds() ?
+ Builder->CreateInBoundsGEP(OrigBase,
+ NewIndices.begin(), NewIndices.end()) :
+ Builder->CreateGEP(OrigBase, NewIndices.begin(), NewIndices.end());
NGEP->takeName(GEP);
- if (isa<Instruction>(NGEP) && cast<GEPOperator>(GEP)->isInBounds())
- cast<GEPOperator>(NGEP)->setIsInBounds(true);
if (isa<BitCastInst>(CI))
return new BitCastInst(NGEP, CI.getType());
@@ -8786,8 +8839,10 @@ Instruction *InstCombiner::visitBitCast(BitCastInst &CI) {
if (SrcPTy->getAddressSpace() != DstPTy->getAddressSpace())
return 0;
- // If we are casting a malloc or alloca to a pointer to a type of the same
+ // If we are casting a alloca to a pointer to a type of the same
// size, rewrite the allocation instruction to allocate the "right" type.
+ // There is no need to modify malloc calls because it is their bitcast that
+ // needs to be cleaned up.
if (AllocationInst *AI = dyn_cast<AllocationInst>(Src))
if (Instruction *V = PromoteCastOfAllocation(CI, *AI))
return V;
@@ -8807,11 +8862,8 @@ Instruction *InstCombiner::visitBitCast(BitCastInst &CI) {
// If we found a path from the src to dest, create the getelementptr now.
if (SrcElTy == DstElTy) {
SmallVector<Value*, 8> Idxs(NumZeros+1, ZeroUInt);
- Instruction *GEP = GetElementPtrInst::Create(Src,
- Idxs.begin(), Idxs.end(), "",
- ((Instruction*) NULL));
- cast<GEPOperator>(GEP)->setIsInBounds(true);
- return GEP;
+ return GetElementPtrInst::CreateInBounds(Src, Idxs.begin(), Idxs.end(), "",
+ ((Instruction*) NULL));
}
}
@@ -9187,6 +9239,14 @@ Instruction *InstCombiner::visitSelectInstWithICmp(SelectInst &SI,
return Changed ? &SI : 0;
}
+/// isDefinedInBB - Return true if the value is an instruction defined in the
+/// specified basicblock.
+static bool isDefinedInBB(const Value *V, const BasicBlock *BB) {
+ const Instruction *I = dyn_cast<Instruction>(V);
+ return I != 0 && I->getParent() == BB;
+}
+
+
Instruction *InstCombiner::visitSelectInst(SelectInst &SI) {
Value *CondVal = SI.getCondition();
Value *TrueVal = SI.getTrueValue();
@@ -9398,6 +9458,17 @@ Instruction *InstCombiner::visitSelectInst(SelectInst &SI) {
return FoldI;
}
+ // See if we can fold the select into a phi node. The true/false values have
+ // to be live in the predecessor blocks. If they are instructions in SI's
+ // block, we can't map to the predecessor.
+ if (isa<PHINode>(SI.getCondition()) &&
+ (!isDefinedInBB(SI.getTrueValue(), SI.getParent()) ||
+ isa<PHINode>(SI.getTrueValue())) &&
+ (!isDefinedInBB(SI.getFalseValue(), SI.getParent()) ||
+ isa<PHINode>(SI.getFalseValue())))
+ if (Instruction *NV = FoldOpIntoPhi(SI))
+ return NV;
+
if (BinaryOperator::isNot(CondVal)) {
SI.setOperand(0, BinaryOperator::getNotArgument(CondVal));
SI.setOperand(1, FalseVal);
@@ -9453,16 +9524,13 @@ static unsigned EnforceKnownAlignment(Value *V,
Align = PrefAlign;
}
}
- } else if (AllocationInst *AI = dyn_cast<AllocationInst>(V)) {
- // If there is a requested alignment and if this is an alloca, round up. We
- // don't do this for malloc, because some systems can't respect the request.
- if (isa<AllocaInst>(AI)) {
- if (AI->getAlignment() >= PrefAlign)
- Align = AI->getAlignment();
- else {
- AI->setAlignment(PrefAlign);
- Align = PrefAlign;
- }
+ } else if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
+ // If there is a requested alignment and if this is an alloca, round up.
+ if (AI->getAlignment() >= PrefAlign)
+ Align = AI->getAlignment();
+ else {
+ AI->setAlignment(PrefAlign);
+ Align = PrefAlign;
}
}
@@ -9801,7 +9869,7 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
TerminatorInst *TI = II->getParent()->getTerminator();
bool CannotRemove = false;
for (++BI; &*BI != TI; ++BI) {
- if (isa<AllocaInst>(BI)) {
+ if (isa<AllocaInst>(BI) || isMalloc(BI)) {
CannotRemove = true;
break;
}
@@ -10318,8 +10386,8 @@ Instruction *InstCombiner::transformCallThroughTrampoline(CallSite CS) {
return CS.getInstruction();
}
-/// FoldPHIArgBinOpIntoPHI - If we have something like phi [add (a,b), add(c,d)]
-/// and if a/b/c/d and the add's all have a single use, turn this into two phi's
+/// FoldPHIArgBinOpIntoPHI - If we have something like phi [add (a,b), add(a,c)]
+/// and if a/b/c and the add's all have a single use, turn this into a phi
/// and a single binop.
Instruction *InstCombiner::FoldPHIArgBinOpIntoPHI(PHINode &PN) {
Instruction *FirstInst = cast<Instruction>(PN.getIncomingValue(0));
@@ -10331,8 +10399,7 @@ Instruction *InstCombiner::FoldPHIArgBinOpIntoPHI(PHINode &PN) {
const Type *LHSType = LHSVal->getType();
const Type *RHSType = RHSVal->getType();
- // Scan to see if all operands are the same opcode, all have one use, and all
- // kill their operands (i.e. the operands have one use).
+ // Scan to see if all operands are the same opcode, and all have one use.
for (unsigned i = 1; i != PN.getNumIncomingValues(); ++i) {
Instruction *I = dyn_cast<Instruction>(PN.getIncomingValue(i));
if (!I || I->getOpcode() != Opc || !I->hasOneUse() ||
@@ -10352,6 +10419,13 @@ Instruction *InstCombiner::FoldPHIArgBinOpIntoPHI(PHINode &PN) {
if (I->getOperand(0) != LHSVal) LHSVal = 0;
if (I->getOperand(1) != RHSVal) RHSVal = 0;
}
+
+ // If both LHS and RHS would need a PHI, don't do this transformation,
+ // because it would increase the number of PHIs entering the block,
+ // which leads to higher register pressure. This is especially
+ // bad when the PHIs are in the header of a loop.
+ if (!LHSVal && !RHSVal)
+ return 0;
// Otherwise, this is safe to transform!
@@ -10406,9 +10480,13 @@ Instruction *InstCombiner::FoldPHIArgGEPIntoPHI(PHINode &PN) {
// This is true if all GEP bases are allocas and if all indices into them are
// constants.
bool AllBasePointersAreAllocas = true;
+
+ // We don't want to replace this phi if the replacement would require
+ // more than one phi, which leads to higher register pressure. This is
+ // especially bad when the PHIs are in the header of a loop.
+ bool NeededPhi = false;
- // Scan to see if all operands are the same opcode, all have one use, and all
- // kill their operands (i.e. the operands have one use).
+ // Scan to see if all operands are the same opcode, and all have one use.
for (unsigned i = 1; i != PN.getNumIncomingValues(); ++i) {
GetElementPtrInst *GEP= dyn_cast<GetElementPtrInst>(PN.getIncomingValue(i));
if (!GEP || !GEP->hasOneUse() || GEP->getType() != FirstInst->getType() ||
@@ -10437,7 +10515,16 @@ Instruction *InstCombiner::FoldPHIArgGEPIntoPHI(PHINode &PN) {
if (FirstInst->getOperand(op)->getType() !=GEP->getOperand(op)->getType())
return 0;
+
+ // If we already needed a PHI for an earlier operand, and another operand
+ // also requires a PHI, we'd be introducing more PHIs than we're
+ // eliminating, which increases register pressure on entry to the PHI's
+ // block.
+ if (NeededPhi)
+ return 0;
+
FixedOperands[op] = 0; // Needs a PHI.
+ NeededPhi = true;
}
}
@@ -10483,12 +10570,11 @@ Instruction *InstCombiner::FoldPHIArgGEPIntoPHI(PHINode &PN) {
}
Value *Base = FixedOperands[0];
- GetElementPtrInst *GEP =
+ return cast<GEPOperator>(FirstInst)->isInBounds() ?
+ GetElementPtrInst::CreateInBounds(Base, FixedOperands.begin()+1,
+ FixedOperands.end()) :
GetElementPtrInst::Create(Base, FixedOperands.begin()+1,
FixedOperands.end());
- if (cast<GEPOperator>(FirstInst)->isInBounds())
- cast<GEPOperator>(GEP)->setIsInBounds(true);
- return GEP;
}
@@ -10891,14 +10977,13 @@ Instruction *InstCombiner::visitGetElementPtrInst(GetElementPtrInst &GEP) {
Indices.append(GEP.idx_begin()+1, GEP.idx_end());
}
- if (!Indices.empty()) {
- GetElementPtrInst *NewGEP =
+ if (!Indices.empty())
+ return (cast<GEPOperator>(&GEP)->isInBounds() &&
+ Src->isInBounds()) ?
+ GetElementPtrInst::CreateInBounds(Src->getOperand(0), Indices.begin(),
+ Indices.end(), GEP.getName()) :
GetElementPtrInst::Create(Src->getOperand(0), Indices.begin(),
Indices.end(), GEP.getName());
- if (cast<GEPOperator>(&GEP)->isInBounds() && Src->isInBounds())
- cast<GEPOperator>(NewGEP)->setIsInBounds(true);
- return NewGEP;
- }
}
// Handle gep(bitcast x) and gep(gep x, 0, 0, 0).
@@ -10928,12 +11013,11 @@ Instruction *InstCombiner::visitGetElementPtrInst(GetElementPtrInst &GEP) {
if (CATy->getElementType() == XTy->getElementType()) {
// -> GEP i8* X, ...
SmallVector<Value*, 8> Indices(GEP.idx_begin()+1, GEP.idx_end());
- GetElementPtrInst *NewGEP =
+ return cast<GEPOperator>(&GEP)->isInBounds() ?
+ GetElementPtrInst::CreateInBounds(X, Indices.begin(), Indices.end(),
+ GEP.getName()) :
GetElementPtrInst::Create(X, Indices.begin(), Indices.end(),
GEP.getName());
- if (cast<GEPOperator>(&GEP)->isInBounds())
- cast<GEPOperator>(NewGEP)->setIsInBounds(true);
- return NewGEP;
}
if (const ArrayType *XATy = dyn_cast<ArrayType>(XTy->getElementType())){
@@ -10961,10 +11045,9 @@ Instruction *InstCombiner::visitGetElementPtrInst(GetElementPtrInst &GEP) {
Value *Idx[2];
Idx[0] = Constant::getNullValue(Type::getInt32Ty(*Context));
Idx[1] = GEP.getOperand(1);
- Value *NewGEP =
+ Value *NewGEP = cast<GEPOperator>(&GEP)->isInBounds() ?
+ Builder->CreateInBoundsGEP(X, Idx, Idx + 2, GEP.getName()) :
Builder->CreateGEP(X, Idx, Idx + 2, GEP.getName());
- if (cast<GEPOperator>(&GEP)->isInBounds())
- cast<GEPOperator>(NewGEP)->setIsInBounds(true);
// V and GEP are both pointer types --> BitCast
return new BitCastInst(NewGEP, GEP.getType());
}
@@ -11021,9 +11104,9 @@ Instruction *InstCombiner::visitGetElementPtrInst(GetElementPtrInst &GEP) {
Value *Idx[2];
Idx[0] = Constant::getNullValue(Type::getInt32Ty(*Context));
Idx[1] = NewIdx;
- Value *NewGEP = Builder->CreateGEP(X, Idx, Idx + 2, GEP.getName());
- if (cast<GEPOperator>(&GEP)->isInBounds())
- cast<GEPOperator>(NewGEP)->setIsInBounds(true);
+ Value *NewGEP = cast<GEPOperator>(&GEP)->isInBounds() ?
+ Builder->CreateInBoundsGEP(X, Idx, Idx + 2, GEP.getName()) :
+ Builder->CreateGEP(X, Idx, Idx + 2, GEP.getName());
// The NewGEP must be pointer typed, so must the old one -> BitCast
return new BitCastInst(NewGEP, GEP.getType());
}
@@ -11050,7 +11133,8 @@ Instruction *InstCombiner::visitGetElementPtrInst(GetElementPtrInst &GEP) {
if (Offset == 0) {
// If the bitcast is of an allocation, and the allocation will be
// converted to match the type of the cast, don't touch this.
- if (isa<AllocationInst>(BCI->getOperand(0))) {
+ if (isa<AllocationInst>(BCI->getOperand(0)) ||
+ isMalloc(BCI->getOperand(0))) {
// See if the bitcast simplifies, if so, don't nuke this GEP yet.
if (Instruction *I = visitBitCast(*BCI)) {
if (I != BCI) {
@@ -11071,10 +11155,11 @@ Instruction *InstCombiner::visitGetElementPtrInst(GetElementPtrInst &GEP) {
const Type *InTy =
cast<PointerType>(BCI->getOperand(0)->getType())->getElementType();
if (FindElementAtOffset(InTy, Offset, NewIndices, TD, Context)) {
- Value *NGEP = Builder->CreateGEP(BCI->getOperand(0), NewIndices.begin(),
- NewIndices.end());
- if (cast<GEPOperator>(&GEP)->isInBounds())
- cast<GEPOperator>(NGEP)->setIsInBounds(true);
+ Value *NGEP = cast<GEPOperator>(&GEP)->isInBounds() ?
+ Builder->CreateInBoundsGEP(BCI->getOperand(0), NewIndices.begin(),
+ NewIndices.end()) :
+ Builder->CreateGEP(BCI->getOperand(0), NewIndices.begin(),
+ NewIndices.end());
if (NGEP->getType() == GEP.getType())
return ReplaceInstUsesWith(GEP, NGEP);
@@ -11117,9 +11202,8 @@ Instruction *InstCombiner::visitAllocationInst(AllocationInst &AI) {
Value *Idx[2];
Idx[0] = NullIdx;
Idx[1] = NullIdx;
- Value *V = GetElementPtrInst::Create(New, Idx, Idx + 2,
- New->getName()+".sub", It);
- cast<GEPOperator>(V)->setIsInBounds(true);
+ Value *V = GetElementPtrInst::CreateInBounds(New, Idx, Idx + 2,
+ New->getName()+".sub", It);
// Now make everything use the getelementptr instead of the original
// allocation.
@@ -11181,6 +11265,21 @@ Instruction *InstCombiner::visitFreeInst(FreeInst &FI) {
EraseInstFromFunction(FI);
return EraseInstFromFunction(*MI);
}
+ if (isMalloc(Op)) {
+ if (CallInst* CI = extractMallocCallFromBitCast(Op)) {
+ if (Op->hasOneUse() && CI->hasOneUse()) {
+ EraseInstFromFunction(FI);
+ EraseInstFromFunction(*CI);
+ return EraseInstFromFunction(*cast<Instruction>(Op));
+ }
+ } else {
+ // Op is a call to malloc
+ if (Op->hasOneUse()) {
+ EraseInstFromFunction(FI);
+ return EraseInstFromFunction(*cast<Instruction>(Op));
+ }
+ }
+ }
return 0;
}
@@ -11488,11 +11587,9 @@ static Instruction *InstCombineStoreToCast(InstCombiner &IC, StoreInst &SI) {
// SIOp0 is a pointer to aggregate and this is a store to the first field,
// emit a GEP to index into its first field.
- if (!NewGEPIndices.empty()) {
- CastOp = IC.Builder->CreateGEP(CastOp, NewGEPIndices.begin(),
- NewGEPIndices.end());
- cast<GEPOperator>(CastOp)->setIsInBounds(true);
- }
+ if (!NewGEPIndices.empty())
+ CastOp = IC.Builder->CreateInBoundsGEP(CastOp, NewGEPIndices.begin(),
+ NewGEPIndices.end());
NewCast = IC.Builder->CreateCast(opcode, SIOp0, CastDstTy,
SIOp0->getName()+".c");
@@ -12091,7 +12188,7 @@ Instruction *InstCombiner::visitExtractElementInst(ExtractElementInst &EI) {
// that element. When the elements are not identical, we cannot replace yet
// (we do that below, but only when the index is constant).
Constant *op0 = C->getOperand(0);
- for (unsigned i = 1; i < C->getNumOperands(); ++i)
+ for (unsigned i = 1; i != C->getNumOperands(); ++i)
if (C->getOperand(i) != op0) {
op0 = 0;
break;
@@ -12104,8 +12201,7 @@ Instruction *InstCombiner::visitExtractElementInst(ExtractElementInst &EI) {
// find a previously computed scalar that was inserted into the vector.
if (ConstantInt *IdxC = dyn_cast<ConstantInt>(EI.getOperand(1))) {
unsigned IndexVal = IdxC->getZExtValue();
- unsigned VectorWidth =
- cast<VectorType>(EI.getOperand(0)->getType())->getNumElements();
+ unsigned VectorWidth = EI.getVectorOperandType()->getNumElements();
// If this is extracting an invalid index, turn this into undef, to avoid
// crashing the code below.
@@ -12142,43 +12238,20 @@ Instruction *InstCombiner::visitExtractElementInst(ExtractElementInst &EI) {
}
if (Instruction *I = dyn_cast<Instruction>(EI.getOperand(0))) {
- if (I->hasOneUse()) {
- // Push extractelement into predecessor operation if legal and
- // profitable to do so
- if (BinaryOperator *BO = dyn_cast<BinaryOperator>(I)) {
- bool isConstantElt = isa<ConstantInt>(EI.getOperand(1));
- if (CheapToScalarize(BO, isConstantElt)) {
- Value *newEI0 =
- Builder->CreateExtractElement(BO->getOperand(0), EI.getOperand(1),
- EI.getName()+".lhs");
- Value *newEI1 =
- Builder->CreateExtractElement(BO->getOperand(1), EI.getOperand(1),
- EI.getName()+".rhs");
- return BinaryOperator::Create(BO->getOpcode(), newEI0, newEI1);
- }
- } else if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
- unsigned AS = LI->getPointerAddressSpace();
- Value *Ptr = Builder->CreateBitCast(I->getOperand(0),
- PointerType::get(EI.getType(), AS),
- I->getOperand(0)->getName());
- Value *GEP =
- Builder->CreateGEP(Ptr, EI.getOperand(1), I->getName()+".gep");
- cast<GEPOperator>(GEP)->setIsInBounds(true);
-
- LoadInst *Load = Builder->CreateLoad(GEP, "tmp");
-
- // Make sure the Load goes before the load instruction in the source,
- // not wherever the extract happens to be.
- if (Instruction *P = dyn_cast<Instruction>(Ptr))
- P->moveBefore(I);
- if (Instruction *G = dyn_cast<Instruction>(GEP))
- G->moveBefore(I);
- Load->moveBefore(I);
-
- return ReplaceInstUsesWith(EI, Load);
- }
- }
- if (InsertElementInst *IE = dyn_cast<InsertElementInst>(I)) {
+ // Push extractelement into predecessor operation if legal and
+ // profitable to do so
+ if (BinaryOperator *BO = dyn_cast<BinaryOperator>(I)) {
+ if (I->hasOneUse() &&
+ CheapToScalarize(BO, isa<ConstantInt>(EI.getOperand(1)))) {
+ Value *newEI0 =
+ Builder->CreateExtractElement(BO->getOperand(0), EI.getOperand(1),
+ EI.getName()+".lhs");
+ Value *newEI1 =
+ Builder->CreateExtractElement(BO->getOperand(1), EI.getOperand(1),
+ EI.getName()+".rhs");
+ return BinaryOperator::Create(BO->getOpcode(), newEI0, newEI1);
+ }
+ } else if (InsertElementInst *IE = dyn_cast<InsertElementInst>(I)) {
// Extracting the inserted element?
if (IE->getOperand(2) == EI.getOperand(1))
return ReplaceInstUsesWith(EI, IE->getOperand(1));
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/JumpThreading.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/JumpThreading.cpp
index ff04cec..21b6ceb 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/JumpThreading.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/JumpThreading.cpp
@@ -26,7 +26,6 @@
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ValueHandle.h"
#include "llvm/Support/raw_ostream.h"
@@ -57,7 +56,7 @@ namespace {
/// In this case, the unconditional branch at the end of the first if can be
/// revectored to the false side of the second if.
///
- class VISIBILITY_HIDDEN JumpThreading : public FunctionPass {
+ class JumpThreading : public FunctionPass {
TargetData *TD;
#ifdef NDEBUG
SmallPtrSet<BasicBlock*, 16> LoopHeaders;
@@ -935,7 +934,7 @@ bool JumpThreading::ThreadEdge(BasicBlock *BB, BasicBlock *PredBB,
// Clone the non-phi instructions of BB into NewBB, keeping track of the
// mapping and using it to remap operands in the cloned instructions.
for (; !isa<TerminatorInst>(BI); ++BI) {
- Instruction *New = BI->clone(BI->getContext());
+ Instruction *New = BI->clone();
New->setName(BI->getName());
NewBB->getInstList().push_back(New);
ValueMapping[BI] = New;
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/LICM.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/LICM.cpp
index 64ca5cd..6df246f 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/LICM.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/LICM.cpp
@@ -36,7 +36,6 @@
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Instructions.h"
-#include "llvm/LLVMContext.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/LoopPass.h"
@@ -46,7 +45,6 @@
#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Transforms/Utils/PromoteMemToReg.h"
#include "llvm/Support/CFG.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/Debug.h"
@@ -74,7 +72,7 @@ EnableLICMConstantMotion("enable-licm-constant-variables", cl::Hidden,
"global variables"));
namespace {
- struct VISIBILITY_HIDDEN LICM : public LoopPass {
+ struct LICM : public LoopPass {
static char ID; // Pass identification, replacement for typeid
LICM() : LoopPass(&ID) {}
@@ -92,6 +90,7 @@ namespace {
AU.addRequired<AliasAnalysis>();
AU.addPreserved<ScalarEvolution>();
AU.addPreserved<DominanceFrontier>();
+ AU.addPreservedID(LoopSimplifyID);
}
bool doFinalization() {
@@ -476,8 +475,6 @@ void LICM::sink(Instruction &I) {
++NumSunk;
Changed = true;
- LLVMContext &Context = I.getContext();
-
// The case where there is only a single exit node of this loop is common
// enough that we handle it as a special (more efficient) case. It is more
// efficient to handle because there are no PHI nodes that need to be placed.
@@ -573,7 +570,7 @@ void LICM::sink(Instruction &I) {
ExitBlock->getInstList().insert(InsertPt, &I);
New = &I;
} else {
- New = I.clone(Context);
+ New = I.clone();
CurAST->copyValue(&I, New);
if (!I.getName().empty())
New->setName(I.getName()+".le");
@@ -596,7 +593,7 @@ void LICM::sink(Instruction &I) {
if (AI) {
std::vector<AllocaInst*> Allocas;
Allocas.push_back(AI);
- PromoteMemToReg(Allocas, *DT, *DF, Context, CurAST);
+ PromoteMemToReg(Allocas, *DT, *DF, AI->getContext(), CurAST);
}
}
}
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopDeletion.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopDeletion.cpp
index 525d03f..5f93756 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopDeletion.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopDeletion.cpp
@@ -15,19 +15,17 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "loop-delete"
-
#include "llvm/Transforms/Scalar.h"
#include "llvm/Analysis/LoopPass.h"
#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/SmallVector.h"
-
using namespace llvm;
STATISTIC(NumDeleted, "Number of loops deleted");
namespace {
- class VISIBILITY_HIDDEN LoopDeletion : public LoopPass {
+ class LoopDeletion : public LoopPass {
public:
static char ID; // Pass ID, replacement for typeid
LoopDeletion() : LoopPass(&ID) {}
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopIndexSplit.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopIndexSplit.cpp
index 259427e..5f9d370 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopIndexSplit.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopIndexSplit.cpp
@@ -51,7 +51,6 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "loop-index-split"
-
#include "llvm/Transforms/Scalar.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/LLVMContext.h"
@@ -61,7 +60,6 @@
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Cloning.h"
#include "llvm/Transforms/Utils/Local.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/Statistic.h"
@@ -73,8 +71,7 @@ STATISTIC(NumRestrictBounds, "Number of loop iteration space restricted");
namespace {
- class VISIBILITY_HIDDEN LoopIndexSplit : public LoopPass {
-
+ class LoopIndexSplit : public LoopPass {
public:
static char ID; // Pass ID, replacement for typeid
LoopIndexSplit() : LoopPass(&ID) {}
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopRotation.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopRotation.cpp
index 687304a..70c69bb 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopRotation.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopRotation.cpp
@@ -32,7 +32,7 @@ using namespace llvm;
STATISTIC(NumRotated, "Number of loops rotated");
namespace {
- class VISIBILITY_HIDDEN RenameData {
+ class RenameData {
public:
RenameData(Instruction *O, Value *P, Instruction *H)
: Original(O), PreHeader(P), Header(H) { }
@@ -42,8 +42,7 @@ namespace {
Instruction *Header; // New header replacement
};
- class VISIBILITY_HIDDEN LoopRotate : public LoopPass {
-
+ class LoopRotate : public LoopPass {
public:
static char ID; // Pass ID, replacement for typeid
LoopRotate() : LoopPass(&ID) {}
@@ -178,6 +177,11 @@ bool LoopRotate::rotateLoop(Loop *Lp, LPPassManager &LPM) {
// Now, this loop is suitable for rotation.
+ // Anything ScalarEvolution may know about this loop or the PHI nodes
+ // in its header will soon be invalidated.
+ if (ScalarEvolution *SE = getAnalysisIfAvailable<ScalarEvolution>())
+ SE->forgetLoopBackedgeTakenCount(L);
+
// Find new Loop header. NewHeader is a Header's one and only successor
// that is inside loop. Header's other successor is outside the
// loop. Otherwise loop is not suitable for rotation.
@@ -238,7 +242,7 @@ bool LoopRotate::rotateLoop(Loop *Lp, LPPassManager &LPM) {
// This is not a PHI instruction. Insert its clone into original pre-header.
// If this instruction is using a value from same basic block then
// update it to use value from cloned instruction.
- Instruction *C = In->clone(In->getContext());
+ Instruction *C = In->clone();
C->setName(In->getName());
OrigPreHeader->getInstList().push_back(C);
@@ -543,22 +547,7 @@ void LoopRotate::preserveCanonicalLoopForm(LPPassManager &LPM) {
// Preserve canonical loop form, which means Exit block should
// have only one predecessor.
- BasicBlock *NExit = SplitEdge(L->getLoopLatch(), Exit, this);
-
- // Preserve LCSSA.
- for (BasicBlock::iterator I = Exit->begin();
- (PN = dyn_cast<PHINode>(I)); ++I) {
- unsigned N = PN->getNumIncomingValues();
- for (unsigned index = 0; index != N; ++index)
- if (PN->getIncomingBlock(index) == NExit) {
- PHINode *NewPN = PHINode::Create(PN->getType(), PN->getName(),
- NExit->begin());
- NewPN->addIncoming(PN->getIncomingValue(index), L->getLoopLatch());
- PN->setIncomingValue(index, NewPN);
- PN->setIncomingBlock(index, NExit);
- break;
- }
- }
+ SplitEdge(L->getLoopLatch(), Exit, this);
assert(NewHeader && L->getHeader() == NewHeader &&
"Invalid loop header after loop rotation");
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index ed32f50..d8f6cc1 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -24,7 +24,6 @@
#include "llvm/Constants.h"
#include "llvm/Instructions.h"
#include "llvm/IntrinsicInst.h"
-#include "llvm/LLVMContext.h"
#include "llvm/Type.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Analysis/Dominators.h"
@@ -38,7 +37,6 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/CFG.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ValueHandle.h"
#include "llvm/Support/raw_ostream.h"
@@ -65,7 +63,7 @@ namespace {
/// IVInfo - This structure keeps track of one IV expression inserted during
/// StrengthReduceStridedIVUsers. It contains the stride, the common base, as
/// well as the PHI node and increment value created for rewrite.
- struct VISIBILITY_HIDDEN IVExpr {
+ struct IVExpr {
const SCEV *Stride;
const SCEV *Base;
PHINode *PHI;
@@ -76,7 +74,7 @@ namespace {
/// IVsOfOneStride - This structure keeps track of all IV expression inserted
/// during StrengthReduceStridedIVUsers for a particular stride of the IV.
- struct VISIBILITY_HIDDEN IVsOfOneStride {
+ struct IVsOfOneStride {
std::vector<IVExpr> IVs;
void addIV(const SCEV *const Stride, const SCEV *const Base, PHINode *PHI) {
@@ -84,7 +82,7 @@ namespace {
}
};
- class VISIBILITY_HIDDEN LoopStrengthReduce : public LoopPass {
+ class LoopStrengthReduce : public LoopPass {
IVUsers *IU;
LoopInfo *LI;
DominatorTree *DT;
@@ -485,36 +483,37 @@ void BasedUser::RewriteInstructionToUseNewBase(const SCEV *const &NewBase,
// loop because multiple copies sometimes do useful sinking of code in
// that case(?).
Instruction *OldLoc = dyn_cast<Instruction>(OperandValToReplace);
+ BasicBlock *PHIPred = PN->getIncomingBlock(i);
if (L->contains(OldLoc->getParent())) {
// If this is a critical edge, split the edge so that we do not insert
// the code on all predecessor/successor paths. We do this unless this
// is the canonical backedge for this loop, as this can make some
// inserted code be in an illegal position.
- BasicBlock *PHIPred = PN->getIncomingBlock(i);
if (e != 1 && PHIPred->getTerminator()->getNumSuccessors() > 1 &&
(PN->getParent() != L->getHeader() || !L->contains(PHIPred))) {
// First step, split the critical edge.
- SplitCriticalEdge(PHIPred, PN->getParent(), P, false);
+ BasicBlock *NewBB = SplitCriticalEdge(PHIPred, PN->getParent(),
+ P, false);
// Next step: move the basic block. In particular, if the PHI node
// is outside of the loop, and PredTI is in the loop, we want to
// move the block to be immediately before the PHI block, not
// immediately after PredTI.
- if (L->contains(PHIPred) && !L->contains(PN->getParent())) {
- BasicBlock *NewBB = PN->getIncomingBlock(i);
+ if (L->contains(PHIPred) && !L->contains(PN->getParent()))
NewBB->moveBefore(PN->getParent());
- }
// Splitting the edge can reduce the number of PHI entries we have.
e = PN->getNumIncomingValues();
+ PHIPred = NewBB;
+ i = PN->getBasicBlockIndex(PHIPred);
}
}
- Value *&Code = InsertedCode[PN->getIncomingBlock(i)];
+ Value *&Code = InsertedCode[PHIPred];
if (!Code) {
// Insert the code into the end of the predecessor block.
Instruction *InsertPt = (L->contains(OldLoc->getParent())) ?
- PN->getIncomingBlock(i)->getTerminator() :
+ PHIPred->getTerminator() :
OldLoc->getParent()->getTerminator();
Code = InsertCodeForBaseAtPosition(NewBase, PN->getType(),
Rewriter, InsertPt, L, LI);
@@ -2303,7 +2302,6 @@ void LoopStrengthReduce::OptimizeLoopTermCond(Loop *L) {
// one register value.
BasicBlock *LatchBlock = L->getLoopLatch();
BasicBlock *ExitingBlock = L->getExitingBlock();
- LLVMContext &Context = LatchBlock->getContext();
if (!ExitingBlock)
// Multiple exits, just look at the exit in the latch block if there is one.
@@ -2394,7 +2392,7 @@ void LoopStrengthReduce::OptimizeLoopTermCond(Loop *L) {
Cond->moveBefore(TermBr);
} else {
// Otherwise, clone the terminating condition and insert into the loopend.
- Cond = cast<ICmpInst>(Cond->clone(Context));
+ Cond = cast<ICmpInst>(Cond->clone());
Cond->setName(L->getHeader()->getName() + ".termcond");
LatchBlock->getInstList().insert(TermBr, Cond);
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopUnroll.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopUnroll.cpp
index c5a213f..837ec59 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopUnroll.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopUnroll.cpp
@@ -17,7 +17,6 @@
#include "llvm/Transforms/Scalar.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/LoopPass.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
@@ -40,7 +39,7 @@ UnrollAllowPartial("unroll-allow-partial", cl::init(false), cl::Hidden,
"-unroll-threshold loop size is reached."));
namespace {
- class VISIBILITY_HIDDEN LoopUnroll : public LoopPass {
+ class LoopUnroll : public LoopPass {
public:
static char ID; // Pass ID, replacement for typeid
LoopUnroll() : LoopPass(&ID) {}
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
index 06ee95c..b1f4214 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
@@ -44,7 +44,6 @@
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
@@ -62,7 +61,7 @@ Threshold("loop-unswitch-threshold", cl::desc("Max loop size to unswitch"),
cl::init(10), cl::Hidden);
namespace {
- class VISIBILITY_HIDDEN LoopUnswitch : public LoopPass {
+ class LoopUnswitch : public LoopPass {
LoopInfo *LI; // Loop information
LPPassManager *LPM;
@@ -113,6 +112,10 @@ namespace {
private:
+ virtual void releaseMemory() {
+ UnswitchedVals.clear();
+ }
+
/// RemoveLoopFromWorklist - If the specified loop is on the loop worklist,
/// remove it.
void RemoveLoopFromWorklist(Loop *L) {
@@ -519,7 +522,12 @@ void LoopUnswitch::EmitPreheaderBranchOnCondition(Value *LIC, Constant *Val,
std::swap(TrueDest, FalseDest);
// Insert the new branch.
- BranchInst::Create(TrueDest, FalseDest, BranchVal, InsertPt);
+ BranchInst *BI = BranchInst::Create(TrueDest, FalseDest, BranchVal, InsertPt);
+
+ // If either edge is critical, split it. This helps preserve LoopSimplify
+ // form for enclosing loops.
+ SplitCriticalEdge(BI, 0, this);
+ SplitCriticalEdge(BI, 1, this);
}
/// UnswitchTrivialCondition - Given a loop that has a trivial unswitchable
@@ -576,47 +584,11 @@ void LoopUnswitch::SplitExitEdges(Loop *L,
for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i) {
BasicBlock *ExitBlock = ExitBlocks[i];
- std::vector<BasicBlock*> Preds(pred_begin(ExitBlock), pred_end(ExitBlock));
-
- for (unsigned j = 0, e = Preds.size(); j != e; ++j) {
- BasicBlock* NewExitBlock = SplitEdge(Preds[j], ExitBlock, this);
- BasicBlock* StartBlock = Preds[j];
- BasicBlock* EndBlock;
- if (NewExitBlock->getSinglePredecessor() == ExitBlock) {
- EndBlock = NewExitBlock;
- NewExitBlock = EndBlock->getSinglePredecessor();
- } else {
- EndBlock = ExitBlock;
- }
-
- std::set<PHINode*> InsertedPHIs;
- PHINode* OldLCSSA = 0;
- for (BasicBlock::iterator I = EndBlock->begin();
- (OldLCSSA = dyn_cast<PHINode>(I)); ++I) {
- Value* OldValue = OldLCSSA->getIncomingValueForBlock(NewExitBlock);
- PHINode* NewLCSSA = PHINode::Create(OldLCSSA->getType(),
- OldLCSSA->getName() + ".us-lcssa",
- NewExitBlock->getTerminator());
- NewLCSSA->addIncoming(OldValue, StartBlock);
- OldLCSSA->setIncomingValue(OldLCSSA->getBasicBlockIndex(NewExitBlock),
- NewLCSSA);
- InsertedPHIs.insert(NewLCSSA);
- }
-
- BasicBlock::iterator InsertPt = EndBlock->getFirstNonPHI();
- for (BasicBlock::iterator I = NewExitBlock->begin();
- (OldLCSSA = dyn_cast<PHINode>(I)) && InsertedPHIs.count(OldLCSSA) == 0;
- ++I) {
- PHINode *NewLCSSA = PHINode::Create(OldLCSSA->getType(),
- OldLCSSA->getName() + ".us-lcssa",
- InsertPt);
- OldLCSSA->replaceAllUsesWith(NewLCSSA);
- NewLCSSA->addIncoming(OldLCSSA, NewExitBlock);
- }
-
- }
+ SmallVector<BasicBlock *, 4> Preds(pred_begin(ExitBlock),
+ pred_end(ExitBlock));
+ SplitBlockPredecessors(ExitBlock, Preds.data(), Preds.size(),
+ ".us-lcssa", this);
}
-
}
/// UnswitchNontrivialCondition - We determined that the loop is profitable
@@ -946,27 +918,35 @@ void LoopUnswitch::RewriteLoopBodyWithConditionConstant(Loop *L, Value *LIC,
// FIXME: This is a hack. We need to keep the successor around
// and hooked up so as to preserve the loop structure, because
// trying to update it is complicated. So instead we preserve the
- // loop structure and put the block on an dead code path.
-
- BasicBlock *SISucc = SI->getSuccessor(i);
- BasicBlock* Old = SI->getParent();
- BasicBlock* Split = SplitBlock(Old, SI, this);
-
- Instruction* OldTerm = Old->getTerminator();
- BranchInst::Create(Split, SISucc,
- ConstantInt::getTrue(Context), OldTerm);
-
- LPM->deleteSimpleAnalysisValue(Old->getTerminator(), L);
- Old->getTerminator()->eraseFromParent();
-
- PHINode *PN;
- for (BasicBlock::iterator II = SISucc->begin();
- (PN = dyn_cast<PHINode>(II)); ++II) {
- Value *InVal = PN->removeIncomingValue(Split, false);
- PN->addIncoming(InVal, Old);
- }
-
- SI->removeCase(i);
+ // loop structure and put the block on a dead code path.
+ BasicBlock *Switch = SI->getParent();
+ SplitEdge(Switch, SI->getSuccessor(i), this);
+ // Compute the successors instead of relying on the return value
+ // of SplitEdge, since it may have split the switch successor
+ // after PHI nodes.
+ BasicBlock *NewSISucc = SI->getSuccessor(i);
+ BasicBlock *OldSISucc = *succ_begin(NewSISucc);
+ // Create an "unreachable" destination.
+ BasicBlock *Abort = BasicBlock::Create(Context, "us-unreachable",
+ Switch->getParent(),
+ OldSISucc);
+ new UnreachableInst(Context, Abort);
+ // Force the new case destination to branch to the "unreachable"
+ // block while maintaining a (dead) CFG edge to the old block.
+ NewSISucc->getTerminator()->eraseFromParent();
+ BranchInst::Create(Abort, OldSISucc,
+ ConstantInt::getTrue(Context), NewSISucc);
+ // Release the PHI operands for this edge.
+ for (BasicBlock::iterator II = NewSISucc->begin();
+ PHINode *PN = dyn_cast<PHINode>(II); ++II)
+ PN->setIncomingValue(PN->getBasicBlockIndex(Switch),
+ UndefValue::get(PN->getType()));
+ // Tell the domtree about the new block. We don't fully update the
+ // domtree here -- instead we force it to do a full recomputation
+ // after the pass is complete -- but we do need to inform it of
+ // new blocks.
+ if (DT)
+ DT->addNewBlock(Abort, NewSISucc);
break;
}
}
@@ -980,7 +960,7 @@ void LoopUnswitch::RewriteLoopBodyWithConditionConstant(Loop *L, Value *LIC,
SimplifyCode(Worklist, L);
}
-/// SimplifyCode - Okay, now that we have simplified some instructions in the
+/// SimplifyCode - Okay, now that we have simplified some instructions in the
/// loop, walk over it and constant prop, dce, and fold control flow where
/// possible. Note that this is effectively a very simple loop-structure-aware
/// optimizer. During processing of this loop, L could very well be deleted, so
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
index 8d47e53..b131384 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
@@ -31,13 +31,14 @@ using namespace llvm;
STATISTIC(NumMemCpyInstr, "Number of memcpy instructions deleted");
STATISTIC(NumMemSetInfer, "Number of memsets inferred");
+STATISTIC(NumMoveToCpy, "Number of memmoves converted to memcpy");
/// isBytewiseValue - If the specified value can be set by repeating the same
/// byte in memory, return the i8 value that it is represented with. This is
/// true for all i8 values obviously, but is also true for i32 0, i32 -1,
/// i16 0xF0F0, double 0.0 etc. If the value can't be handled with a repeated
/// byte store (e.g. i16 0x1234), return null.
-static Value *isBytewiseValue(Value *V, LLVMContext& Context) {
+static Value *isBytewiseValue(Value *V, LLVMContext &Context) {
// All byte-wide stores are splatable, even of arbitrary variables.
if (V->getType() == Type::getInt8Ty(Context)) return V;
@@ -272,6 +273,7 @@ void MemsetRanges::addStore(int64_t Start, StoreInst *SI) {
if (Start < I->Start) {
I->Start = Start;
I->StartPtr = SI->getPointerOperand();
+ I->Alignment = SI->getAlignment();
}
// Now we know that Start <= I->End and Start >= I->Start (so the startpoint
@@ -296,8 +298,7 @@ void MemsetRanges::addStore(int64_t Start, StoreInst *SI) {
//===----------------------------------------------------------------------===//
namespace {
-
- class VISIBILITY_HIDDEN MemCpyOpt : public FunctionPass {
+ class MemCpyOpt : public FunctionPass {
bool runOnFunction(Function &F);
public:
static char ID; // Pass identification, replacement for typeid
@@ -315,9 +316,10 @@ namespace {
}
// Helper fuctions
- bool processStore(StoreInst *SI, BasicBlock::iterator& BBI);
- bool processMemCpy(MemCpyInst* M);
- bool performCallSlotOptzn(MemCpyInst* cpy, CallInst* C);
+ bool processStore(StoreInst *SI, BasicBlock::iterator &BBI);
+ bool processMemCpy(MemCpyInst *M);
+ bool processMemMove(MemMoveInst *M);
+ bool performCallSlotOptzn(MemCpyInst *cpy, CallInst *C);
bool iterateOnFunction(Function &F);
};
@@ -336,16 +338,18 @@ static RegisterPass<MemCpyOpt> X("memcpyopt",
/// some other patterns to fold away. In particular, this looks for stores to
/// neighboring locations of memory. If it sees enough consequtive ones
/// (currently 4) it attempts to merge them together into a memcpy/memset.
-bool MemCpyOpt::processStore(StoreInst *SI, BasicBlock::iterator& BBI) {
+bool MemCpyOpt::processStore(StoreInst *SI, BasicBlock::iterator &BBI) {
if (SI->isVolatile()) return false;
+ LLVMContext &Context = SI->getContext();
+
// There are two cases that are interesting for this code to handle: memcpy
// and memset. Right now we only handle memset.
// Ensure that the value being stored is something that can be memset'able a
// byte at a time like "0" or "-1" or any width, as well as things like
// 0xA0A0A0A0 and 0.0.
- Value *ByteVal = isBytewiseValue(SI->getOperand(0), SI->getContext());
+ Value *ByteVal = isBytewiseValue(SI->getOperand(0), Context);
if (!ByteVal)
return false;
@@ -386,8 +390,7 @@ bool MemCpyOpt::processStore(StoreInst *SI, BasicBlock::iterator& BBI) {
if (NextStore->isVolatile()) break;
// Check to see if this stored value is of the same byte-splattable value.
- if (ByteVal != isBytewiseValue(NextStore->getOperand(0),
- NextStore->getContext()))
+ if (ByteVal != isBytewiseValue(NextStore->getOperand(0), Context))
break;
// Check to see if this store is to a constant offset from the start ptr.
@@ -407,7 +410,6 @@ bool MemCpyOpt::processStore(StoreInst *SI, BasicBlock::iterator& BBI) {
// store as well. We try to avoid this unless there is at least something
// interesting as a small compile-time optimization.
Ranges.addStore(0, SI);
-
Function *MemSetF = 0;
@@ -431,17 +433,15 @@ bool MemCpyOpt::processStore(StoreInst *SI, BasicBlock::iterator& BBI) {
BasicBlock::iterator InsertPt = BI;
if (MemSetF == 0) {
- const Type *Tys[] = {Type::getInt64Ty(SI->getContext())};
- MemSetF = Intrinsic::getDeclaration(M, Intrinsic::memset,
- Tys, 1);
- }
+ const Type *Ty = Type::getInt64Ty(Context);
+ MemSetF = Intrinsic::getDeclaration(M, Intrinsic::memset, &Ty, 1);
+ }
// Get the starting pointer of the block.
StartPtr = Range.StartPtr;
// Cast the start ptr to be i8* as memset requires.
- const Type *i8Ptr =
- PointerType::getUnqual(Type::getInt8Ty(SI->getContext()));
+ const Type *i8Ptr = PointerType::getUnqual(Type::getInt8Ty(Context));
if (StartPtr->getType() != i8Ptr)
StartPtr = new BitCastInst(StartPtr, i8Ptr, StartPtr->getName(),
InsertPt);
@@ -449,10 +449,9 @@ bool MemCpyOpt::processStore(StoreInst *SI, BasicBlock::iterator& BBI) {
Value *Ops[] = {
StartPtr, ByteVal, // Start, value
// size
- ConstantInt::get(Type::getInt64Ty(SI->getContext()),
- Range.End-Range.Start),
+ ConstantInt::get(Type::getInt64Ty(Context), Range.End-Range.Start),
// align
- ConstantInt::get(Type::getInt32Ty(SI->getContext()), Range.Alignment)
+ ConstantInt::get(Type::getInt32Ty(Context), Range.Alignment)
};
Value *C = CallInst::Create(MemSetF, Ops, Ops+4, "", InsertPt);
DEBUG(errs() << "Replace stores:\n";
@@ -464,7 +463,8 @@ bool MemCpyOpt::processStore(StoreInst *SI, BasicBlock::iterator& BBI) {
BBI = BI;
// Zap all the stores.
- for (SmallVector<StoreInst*, 16>::const_iterator SI = Range.TheStores.begin(),
+ for (SmallVector<StoreInst*, 16>::const_iterator
+ SI = Range.TheStores.begin(),
SE = Range.TheStores.end(); SI != SE; ++SI)
(*SI)->eraseFromParent();
++NumMemSetInfer;
@@ -495,26 +495,26 @@ bool MemCpyOpt::performCallSlotOptzn(MemCpyInst *cpy, CallInst *C) {
// Deliberately get the source and destination with bitcasts stripped away,
// because we'll need to do type comparisons based on the underlying type.
- Value* cpyDest = cpy->getDest();
- Value* cpySrc = cpy->getSource();
+ Value *cpyDest = cpy->getDest();
+ Value *cpySrc = cpy->getSource();
CallSite CS = CallSite::get(C);
// We need to be able to reason about the size of the memcpy, so we require
// that it be a constant.
- ConstantInt* cpyLength = dyn_cast<ConstantInt>(cpy->getLength());
+ ConstantInt *cpyLength = dyn_cast<ConstantInt>(cpy->getLength());
if (!cpyLength)
return false;
// Require that src be an alloca. This simplifies the reasoning considerably.
- AllocaInst* srcAlloca = dyn_cast<AllocaInst>(cpySrc);
+ AllocaInst *srcAlloca = dyn_cast<AllocaInst>(cpySrc);
if (!srcAlloca)
return false;
// Check that all of src is copied to dest.
- TargetData* TD = getAnalysisIfAvailable<TargetData>();
+ TargetData *TD = getAnalysisIfAvailable<TargetData>();
if (!TD) return false;
- ConstantInt* srcArraySize = dyn_cast<ConstantInt>(srcAlloca->getArraySize());
+ ConstantInt *srcArraySize = dyn_cast<ConstantInt>(srcAlloca->getArraySize());
if (!srcArraySize)
return false;
@@ -527,9 +527,9 @@ bool MemCpyOpt::performCallSlotOptzn(MemCpyInst *cpy, CallInst *C) {
// Check that accessing the first srcSize bytes of dest will not cause a
// trap. Otherwise the transform is invalid since it might cause a trap
// to occur earlier than it otherwise would.
- if (AllocaInst* A = dyn_cast<AllocaInst>(cpyDest)) {
+ if (AllocaInst *A = dyn_cast<AllocaInst>(cpyDest)) {
// The destination is an alloca. Check it is larger than srcSize.
- ConstantInt* destArraySize = dyn_cast<ConstantInt>(A->getArraySize());
+ ConstantInt *destArraySize = dyn_cast<ConstantInt>(A->getArraySize());
if (!destArraySize)
return false;
@@ -538,13 +538,13 @@ bool MemCpyOpt::performCallSlotOptzn(MemCpyInst *cpy, CallInst *C) {
if (destSize < srcSize)
return false;
- } else if (Argument* A = dyn_cast<Argument>(cpyDest)) {
+ } else if (Argument *A = dyn_cast<Argument>(cpyDest)) {
// If the destination is an sret parameter then only accesses that are
// outside of the returned struct type can trap.
if (!A->hasStructRetAttr())
return false;
- const Type* StructTy = cast<PointerType>(A->getType())->getElementType();
+ const Type *StructTy = cast<PointerType>(A->getType())->getElementType();
uint64_t destSize = TD->getTypeAllocSize(StructTy);
if (destSize < srcSize)
@@ -560,14 +560,14 @@ bool MemCpyOpt::performCallSlotOptzn(MemCpyInst *cpy, CallInst *C) {
SmallVector<User*, 8> srcUseList(srcAlloca->use_begin(),
srcAlloca->use_end());
while (!srcUseList.empty()) {
- User* UI = srcUseList.back();
+ User *UI = srcUseList.back();
srcUseList.pop_back();
if (isa<BitCastInst>(UI)) {
for (User::use_iterator I = UI->use_begin(), E = UI->use_end();
I != E; ++I)
srcUseList.push_back(*I);
- } else if (GetElementPtrInst* G = dyn_cast<GetElementPtrInst>(UI)) {
+ } else if (GetElementPtrInst *G = dyn_cast<GetElementPtrInst>(UI)) {
if (G->hasAllZeroIndices())
for (User::use_iterator I = UI->use_begin(), E = UI->use_end();
I != E; ++I)
@@ -581,8 +581,8 @@ bool MemCpyOpt::performCallSlotOptzn(MemCpyInst *cpy, CallInst *C) {
// Since we're changing the parameter to the callsite, we need to make sure
// that what would be the new parameter dominates the callsite.
- DominatorTree& DT = getAnalysis<DominatorTree>();
- if (Instruction* cpyDestInst = dyn_cast<Instruction>(cpyDest))
+ DominatorTree &DT = getAnalysis<DominatorTree>();
+ if (Instruction *cpyDestInst = dyn_cast<Instruction>(cpyDest))
if (!DT.dominates(cpyDestInst, C))
return false;
@@ -590,7 +590,7 @@ bool MemCpyOpt::performCallSlotOptzn(MemCpyInst *cpy, CallInst *C) {
// unexpected manner, for example via a global, which we deduce from
// the use analysis, we also need to know that it does not sneakily
// access dest. We rely on AA to figure this out for us.
- AliasAnalysis& AA = getAnalysis<AliasAnalysis>();
+ AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
if (AA.getModRefInfo(C, cpy->getRawDest(), srcSize) !=
AliasAnalysis::NoModRef)
return false;
@@ -603,11 +603,11 @@ bool MemCpyOpt::performCallSlotOptzn(MemCpyInst *cpy, CallInst *C) {
cpyDest = CastInst::CreatePointerCast(cpyDest, cpySrc->getType(),
cpyDest->getName(), C);
changedArgument = true;
- if (CS.getArgument(i)->getType() != cpyDest->getType())
- CS.setArgument(i, CastInst::CreatePointerCast(cpyDest,
- CS.getArgument(i)->getType(), cpyDest->getName(), C));
- else
+ if (CS.getArgument(i)->getType() == cpyDest->getType())
CS.setArgument(i, cpyDest);
+ else
+ CS.setArgument(i, CastInst::CreatePointerCast(cpyDest,
+ CS.getArgument(i)->getType(), cpyDest->getName(), C));
}
if (!changedArgument)
@@ -615,7 +615,7 @@ bool MemCpyOpt::performCallSlotOptzn(MemCpyInst *cpy, CallInst *C) {
// Drop any cached information about the call, because we may have changed
// its dependence information by changing its parameter.
- MemoryDependenceAnalysis& MD = getAnalysis<MemoryDependenceAnalysis>();
+ MemoryDependenceAnalysis &MD = getAnalysis<MemoryDependenceAnalysis>();
MD.removeInstruction(C);
// Remove the memcpy
@@ -630,22 +630,22 @@ bool MemCpyOpt::performCallSlotOptzn(MemCpyInst *cpy, CallInst *C) {
/// copies X to Y, and memcpy B which copies Y to Z, then we can rewrite B to be
/// a memcpy from X to Z (or potentially a memmove, depending on circumstances).
/// This allows later passes to remove the first memcpy altogether.
-bool MemCpyOpt::processMemCpy(MemCpyInst* M) {
- MemoryDependenceAnalysis& MD = getAnalysis<MemoryDependenceAnalysis>();
+bool MemCpyOpt::processMemCpy(MemCpyInst *M) {
+ MemoryDependenceAnalysis &MD = getAnalysis<MemoryDependenceAnalysis>();
// The are two possible optimizations we can do for memcpy:
- // a) memcpy-memcpy xform which exposes redundance for DSE
- // b) call-memcpy xform for return slot optimization
+ // a) memcpy-memcpy xform which exposes redundance for DSE.
+ // b) call-memcpy xform for return slot optimization.
MemDepResult dep = MD.getDependency(M);
if (!dep.isClobber())
return false;
if (!isa<MemCpyInst>(dep.getInst())) {
- if (CallInst* C = dyn_cast<CallInst>(dep.getInst()))
+ if (CallInst *C = dyn_cast<CallInst>(dep.getInst()))
return performCallSlotOptzn(M, C);
return false;
}
- MemCpyInst* MDep = cast<MemCpyInst>(dep.getInst());
+ MemCpyInst *MDep = cast<MemCpyInst>(dep.getInst());
// We can only transforms memcpy's where the dest of one is the source of the
// other
@@ -654,8 +654,8 @@ bool MemCpyOpt::processMemCpy(MemCpyInst* M) {
// Second, the length of the memcpy's must be the same, or the preceeding one
// must be larger than the following one.
- ConstantInt* C1 = dyn_cast<ConstantInt>(MDep->getLength());
- ConstantInt* C2 = dyn_cast<ConstantInt>(M->getLength());
+ ConstantInt *C1 = dyn_cast<ConstantInt>(MDep->getLength());
+ ConstantInt *C2 = dyn_cast<ConstantInt>(M->getLength());
if (!C1 || !C2)
return false;
@@ -667,7 +667,7 @@ bool MemCpyOpt::processMemCpy(MemCpyInst* M) {
// Finally, we have to make sure that the dest of the second does not
// alias the source of the first
- AliasAnalysis& AA = getAnalysis<AliasAnalysis>();
+ AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
if (AA.alias(M->getRawDest(), CpySize, MDep->getRawSource(), DepSize) !=
AliasAnalysis::NoAlias)
return false;
@@ -679,17 +679,16 @@ bool MemCpyOpt::processMemCpy(MemCpyInst* M) {
return false;
// If all checks passed, then we can transform these memcpy's
- const Type *Tys[1];
- Tys[0] = M->getLength()->getType();
- Function* MemCpyFun = Intrinsic::getDeclaration(
+ const Type *Ty = M->getLength()->getType();
+ Function *MemCpyFun = Intrinsic::getDeclaration(
M->getParent()->getParent()->getParent(),
- M->getIntrinsicID(), Tys, 1);
+ M->getIntrinsicID(), &Ty, 1);
Value *Args[4] = {
M->getRawDest(), MDep->getRawSource(), M->getLength(), M->getAlignmentCst()
};
- CallInst* C = CallInst::Create(MemCpyFun, Args, Args+4, "", M);
+ CallInst *C = CallInst::Create(MemCpyFun, Args, Args+4, "", M);
// If C and M don't interfere, then this is a valid transformation. If they
@@ -708,41 +707,78 @@ bool MemCpyOpt::processMemCpy(MemCpyInst* M) {
return false;
}
-// MemCpyOpt::runOnFunction - This is the main transformation entry point for a
-// function.
-//
-bool MemCpyOpt::runOnFunction(Function& F) {
+/// processMemMove - Transforms memmove calls to memcpy calls when the src/dst
+/// are guaranteed not to alias.
+bool MemCpyOpt::processMemMove(MemMoveInst *M) {
+ AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
+
+ // If the memmove is a constant size, use it for the alias query, this allows
+ // us to optimize things like: memmove(P, P+64, 64);
+ uint64_t MemMoveSize = ~0ULL;
+ if (ConstantInt *Len = dyn_cast<ConstantInt>(M->getLength()))
+ MemMoveSize = Len->getZExtValue();
- bool changed = false;
- bool shouldContinue = true;
+ // See if the pointers alias.
+ if (AA.alias(M->getRawDest(), MemMoveSize, M->getRawSource(), MemMoveSize) !=
+ AliasAnalysis::NoAlias)
+ return false;
- while (shouldContinue) {
- shouldContinue = iterateOnFunction(F);
- changed |= shouldContinue;
- }
+ DEBUG(errs() << "MemCpyOpt: Optimizing memmove -> memcpy: " << *M << "\n");
- return changed;
-}
+ // If not, then we know we can transform this.
+ Module *Mod = M->getParent()->getParent()->getParent();
+ const Type *Ty = M->getLength()->getType();
+ M->setOperand(0, Intrinsic::getDeclaration(Mod, Intrinsic::memcpy, &Ty, 1));
+ // MemDep may have over conservative information about this instruction, just
+ // conservatively flush it from the cache.
+ getAnalysis<MemoryDependenceAnalysis>().removeInstruction(M);
-// MemCpyOpt::iterateOnFunction - Executes one iteration of GVN
+ ++NumMoveToCpy;
+ return true;
+}
+
+
+// MemCpyOpt::iterateOnFunction - Executes one iteration of GVN.
bool MemCpyOpt::iterateOnFunction(Function &F) {
- bool changed_function = false;
+ bool MadeChange = false;
- // Walk all instruction in the function
+ // Walk all instruction in the function.
for (Function::iterator BB = F.begin(), BBE = F.end(); BB != BBE; ++BB) {
for (BasicBlock::iterator BI = BB->begin(), BE = BB->end();
BI != BE;) {
- // Avoid invalidating the iterator
- Instruction* I = BI++;
+ // Avoid invalidating the iterator.
+ Instruction *I = BI++;
if (StoreInst *SI = dyn_cast<StoreInst>(I))
- changed_function |= processStore(SI, BI);
- else if (MemCpyInst* M = dyn_cast<MemCpyInst>(I)) {
- changed_function |= processMemCpy(M);
+ MadeChange |= processStore(SI, BI);
+ else if (MemCpyInst *M = dyn_cast<MemCpyInst>(I))
+ MadeChange |= processMemCpy(M);
+ else if (MemMoveInst *M = dyn_cast<MemMoveInst>(I)) {
+ if (processMemMove(M)) {
+ --BI; // Reprocess the new memcpy.
+ MadeChange = true;
+ }
}
}
}
- return changed_function;
+ return MadeChange;
+}
+
+// MemCpyOpt::runOnFunction - This is the main transformation entry point for a
+// function.
+//
+bool MemCpyOpt::runOnFunction(Function &F) {
+ bool MadeChange = false;
+ while (1) {
+ if (!iterateOnFunction(F))
+ break;
+ MadeChange = true;
+ }
+
+ return MadeChange;
}
+
+
+
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp
index 263c606..b8ac182 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp
@@ -93,7 +93,6 @@
#include "llvm/Analysis/Dominators.h"
#include "llvm/Assembly/Writer.h"
#include "llvm/Support/CFG.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/ConstantRange.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/InstVisitor.h"
@@ -377,12 +376,12 @@ namespace {
}
/// ValueNumbering stores the scope-specific value numbers for a given Value.
- class VISIBILITY_HIDDEN ValueNumbering {
+ class ValueNumbering {
/// VNPair is a tuple of {Value, index number, DomTreeDFS::Node}. It
/// includes the comparison operators necessary to allow you to store it
/// in a sorted vector.
- class VISIBILITY_HIDDEN VNPair {
+ class VNPair {
public:
Value *V;
unsigned index;
@@ -592,7 +591,7 @@ namespace {
///
/// The InequalityGraph class may invalidate Node*s after any mutator call.
/// @brief The InequalityGraph stores the relationships between values.
- class VISIBILITY_HIDDEN InequalityGraph {
+ class InequalityGraph {
ValueNumbering &VN;
DomTreeDFS::Node *TreeRoot;
@@ -608,7 +607,7 @@ namespace {
/// and contains a pointer to the other end. The edge contains a lattice
/// value specifying the relationship and an DomTreeDFS::Node specifying
/// the root in the dominator tree to which this edge applies.
- class VISIBILITY_HIDDEN Edge {
+ class Edge {
public:
Edge(unsigned T, LatticeVal V, DomTreeDFS::Node *ST)
: To(T), LV(V), Subtree(ST) {}
@@ -639,7 +638,7 @@ namespace {
/// for the node, as well as the relationships with the neighbours.
///
/// @brief A single node in the InequalityGraph.
- class VISIBILITY_HIDDEN Node {
+ class Node {
friend class InequalityGraph;
typedef SmallVector<Edge, 4> RelationsType;
@@ -904,12 +903,12 @@ namespace {
/// ValueRanges tracks the known integer ranges and anti-ranges of the nodes
/// in the InequalityGraph.
- class VISIBILITY_HIDDEN ValueRanges {
+ class ValueRanges {
ValueNumbering &VN;
TargetData *TD;
LLVMContext *Context;
- class VISIBILITY_HIDDEN ScopedRange {
+ class ScopedRange {
typedef std::vector<std::pair<DomTreeDFS::Node *, ConstantRange> >
RangeListType;
RangeListType RangeList;
@@ -1270,7 +1269,7 @@ namespace {
/// another discovered to be unreachable. This is used to cull the graph when
/// analyzing instructions, and to mark blocks with the "unreachable"
/// terminator instruction after the function has executed.
- class VISIBILITY_HIDDEN UnreachableBlocks {
+ class UnreachableBlocks {
private:
std::vector<BasicBlock *> DeadBlocks;
@@ -1324,7 +1323,7 @@ namespace {
/// variables, and forwards changes along to the InequalityGraph. It
/// also maintains the correct choice for "canonical" in the IG.
/// @brief VRPSolver calculates inferences from a new relationship.
- class VISIBILITY_HIDDEN VRPSolver {
+ class VRPSolver {
private:
friend class ValueRanges;
@@ -2266,7 +2265,7 @@ namespace {
/// one equivalent variable with another. It also tracks what
/// can't be equal and will solve setcc instructions when possible.
/// @brief Root of the predicate simplifier optimization.
- class VISIBILITY_HIDDEN PredicateSimplifier : public FunctionPass {
+ class PredicateSimplifier : public FunctionPass {
DomTreeDFS *DTDFS;
bool modified;
ValueNumbering *VN;
@@ -2295,7 +2294,7 @@ namespace {
/// PredicateSimplifier::proceedToSuccessor(s) interface to enter the
/// basic block.
/// @brief Performs abstract execution of the program.
- class VISIBILITY_HIDDEN Forwards : public InstVisitor<Forwards> {
+ class Forwards : public InstVisitor<Forwards> {
friend class InstVisitor<Forwards>;
PredicateSimplifier *PS;
DomTreeDFS::Node *DTNode;
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/Reassociate.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/Reassociate.cpp
index 9ef4ea8..e6ffac2 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/Reassociate.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/Reassociate.cpp
@@ -31,7 +31,6 @@
#include "llvm/Pass.h"
#include "llvm/Assembly/Writer.h"
#include "llvm/Support/CFG.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ValueHandle.h"
#include "llvm/Support/raw_ostream.h"
@@ -47,7 +46,7 @@ STATISTIC(NumAnnihil, "Number of expr tree annihilated");
STATISTIC(NumFactor , "Number of multiplies factored");
namespace {
- struct VISIBILITY_HIDDEN ValueEntry {
+ struct ValueEntry {
unsigned Rank;
Value *Op;
ValueEntry(unsigned R, Value *O) : Rank(R), Op(O) {}
@@ -72,7 +71,7 @@ static void PrintOps(Instruction *I, const std::vector<ValueEntry> &Ops) {
#endif
namespace {
- class VISIBILITY_HIDDEN Reassociate : public FunctionPass {
+ class Reassociate : public FunctionPass {
std::map<BasicBlock*, unsigned> RankMap;
std::map<AssertingVH<>, unsigned> ValueRankMap;
bool MadeChange;
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/Reg2Mem.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/Reg2Mem.cpp
index b0db317..99e1252 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/Reg2Mem.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/Reg2Mem.cpp
@@ -26,7 +26,6 @@
#include "llvm/BasicBlock.h"
#include "llvm/Instructions.h"
#include "llvm/ADT/Statistic.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/CFG.h"
#include <list>
using namespace llvm;
@@ -35,7 +34,7 @@ STATISTIC(NumRegsDemoted, "Number of registers demoted");
STATISTIC(NumPhisDemoted, "Number of phi-nodes demoted");
namespace {
- struct VISIBILITY_HIDDEN RegToMem : public FunctionPass {
+ struct RegToMem : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
RegToMem() : FunctionPass(&ID) {}
@@ -44,74 +43,17 @@ namespace {
AU.addPreservedID(BreakCriticalEdgesID);
}
- bool valueEscapes(Instruction* i) {
- BasicBlock* bb = i->getParent();
- for (Value::use_iterator ii = i->use_begin(), ie = i->use_end();
- ii != ie; ++ii)
- if (cast<Instruction>(*ii)->getParent() != bb ||
- isa<PHINode>(*ii))
+ bool valueEscapes(const Instruction *Inst) const {
+ const BasicBlock *BB = Inst->getParent();
+ for (Value::use_const_iterator UI = Inst->use_begin(),E = Inst->use_end();
+ UI != E; ++UI)
+ if (cast<Instruction>(*UI)->getParent() != BB ||
+ isa<PHINode>(*UI))
return true;
return false;
}
- virtual bool runOnFunction(Function &F) {
- if (!F.isDeclaration()) {
- // Insert all new allocas into entry block.
- BasicBlock* BBEntry = &F.getEntryBlock();
- assert(pred_begin(BBEntry) == pred_end(BBEntry) &&
- "Entry block to function must not have predecessors!");
-
- // Find first non-alloca instruction and create insertion point. This is
- // safe if block is well-formed: it always have terminator, otherwise
- // we'll get and assertion.
- BasicBlock::iterator I = BBEntry->begin();
- while (isa<AllocaInst>(I)) ++I;
-
- CastInst *AllocaInsertionPoint =
- CastInst::Create(Instruction::BitCast,
- Constant::getNullValue(Type::getInt32Ty(F.getContext())),
- Type::getInt32Ty(F.getContext()),
- "reg2mem alloca point", I);
-
- // Find the escaped instructions. But don't create stack slots for
- // allocas in entry block.
- std::list<Instruction*> worklist;
- for (Function::iterator ibb = F.begin(), ibe = F.end();
- ibb != ibe; ++ibb)
- for (BasicBlock::iterator iib = ibb->begin(), iie = ibb->end();
- iib != iie; ++iib) {
- if (!(isa<AllocaInst>(iib) && iib->getParent() == BBEntry) &&
- valueEscapes(iib)) {
- worklist.push_front(&*iib);
- }
- }
-
- // Demote escaped instructions
- NumRegsDemoted += worklist.size();
- for (std::list<Instruction*>::iterator ilb = worklist.begin(),
- ile = worklist.end(); ilb != ile; ++ilb)
- DemoteRegToStack(**ilb, false, AllocaInsertionPoint);
-
- worklist.clear();
-
- // Find all phi's
- for (Function::iterator ibb = F.begin(), ibe = F.end();
- ibb != ibe; ++ibb)
- for (BasicBlock::iterator iib = ibb->begin(), iie = ibb->end();
- iib != iie; ++iib)
- if (isa<PHINode>(iib))
- worklist.push_front(&*iib);
-
- // Demote phi nodes
- NumPhisDemoted += worklist.size();
- for (std::list<Instruction*>::iterator ilb = worklist.begin(),
- ile = worklist.end(); ilb != ile; ++ilb)
- DemotePHIToStack(cast<PHINode>(*ilb), AllocaInsertionPoint);
-
- return true;
- }
- return false;
- }
+ virtual bool runOnFunction(Function &F);
};
}
@@ -119,6 +61,66 @@ char RegToMem::ID = 0;
static RegisterPass<RegToMem>
X("reg2mem", "Demote all values to stack slots");
+
+bool RegToMem::runOnFunction(Function &F) {
+ if (F.isDeclaration())
+ return false;
+
+ // Insert all new allocas into entry block.
+ BasicBlock *BBEntry = &F.getEntryBlock();
+ assert(pred_begin(BBEntry) == pred_end(BBEntry) &&
+ "Entry block to function must not have predecessors!");
+
+ // Find first non-alloca instruction and create insertion point. This is
+ // safe if block is well-formed: it always have terminator, otherwise
+ // we'll get and assertion.
+ BasicBlock::iterator I = BBEntry->begin();
+ while (isa<AllocaInst>(I)) ++I;
+
+ CastInst *AllocaInsertionPoint =
+ new BitCastInst(Constant::getNullValue(Type::getInt32Ty(F.getContext())),
+ Type::getInt32Ty(F.getContext()),
+ "reg2mem alloca point", I);
+
+ // Find the escaped instructions. But don't create stack slots for
+ // allocas in entry block.
+ std::list<Instruction*> WorkList;
+ for (Function::iterator ibb = F.begin(), ibe = F.end();
+ ibb != ibe; ++ibb)
+ for (BasicBlock::iterator iib = ibb->begin(), iie = ibb->end();
+ iib != iie; ++iib) {
+ if (!(isa<AllocaInst>(iib) && iib->getParent() == BBEntry) &&
+ valueEscapes(iib)) {
+ WorkList.push_front(&*iib);
+ }
+ }
+
+ // Demote escaped instructions
+ NumRegsDemoted += WorkList.size();
+ for (std::list<Instruction*>::iterator ilb = WorkList.begin(),
+ ile = WorkList.end(); ilb != ile; ++ilb)
+ DemoteRegToStack(**ilb, false, AllocaInsertionPoint);
+
+ WorkList.clear();
+
+ // Find all phi's
+ for (Function::iterator ibb = F.begin(), ibe = F.end();
+ ibb != ibe; ++ibb)
+ for (BasicBlock::iterator iib = ibb->begin(), iie = ibb->end();
+ iib != iie; ++iib)
+ if (isa<PHINode>(iib))
+ WorkList.push_front(&*iib);
+
+ // Demote phi nodes
+ NumPhisDemoted += WorkList.size();
+ for (std::list<Instruction*>::iterator ilb = WorkList.begin(),
+ ile = WorkList.end(); ilb != ile; ++ilb)
+ DemotePHIToStack(cast<PHINode>(*ilb), AllocaInsertionPoint);
+
+ return true;
+}
+
+
// createDemoteRegisterToMemory - Provide an entry point to create this pass.
//
const PassInfo *const llvm::DemoteRegisterToMemoryID = &X;
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/SCCP.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/SCCP.cpp
index 155e91e..2f49d25 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/SCCP.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/SCCP.cpp
@@ -33,7 +33,6 @@
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Support/CallSite.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/InstVisitor.h"
@@ -60,7 +59,7 @@ namespace {
/// LatticeVal class - This class represents the different lattice values that
/// an LLVM value may occupy. It is a simple class with value semantics.
///
-class VISIBILITY_HIDDEN LatticeVal {
+class LatticeVal {
enum {
/// undefined - This LLVM Value has no known value yet.
undefined,
@@ -401,7 +400,9 @@ private:
void visitStoreInst (Instruction &I);
void visitLoadInst (LoadInst &I);
void visitGetElementPtrInst(GetElementPtrInst &I);
- void visitCallInst (CallInst &I) { visitCallSite(CallSite::get(&I)); }
+ void visitCallInst (CallInst &I) {
+ visitCallSite(CallSite::get(&I));
+ }
void visitInvokeInst (InvokeInst &II) {
visitCallSite(CallSite::get(&II));
visitTerminatorInst(II);
@@ -1262,6 +1263,10 @@ CallOverdefined:
for (Function::arg_iterator AI = F->arg_begin(), E = F->arg_end();
AI != E; ++AI, ++CAI) {
LatticeVal &IV = ValueState[AI];
+ if (AI->hasByValAttr() && !F->onlyReadsMemory()) {
+ IV.markOverdefined();
+ continue;
+ }
if (!IV.isOverdefined())
mergeInValue(IV, AI, getValueState(*CAI));
}
@@ -1506,7 +1511,7 @@ namespace {
/// SCCP Class - This class uses the SCCPSolver to implement a per-function
/// Sparse Conditional Constant Propagator.
///
- struct VISIBILITY_HIDDEN SCCP : public FunctionPass {
+ struct SCCP : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
SCCP() : FunctionPass(&ID) {}
@@ -1621,7 +1626,7 @@ namespace {
/// IPSCCP Class - This class implements interprocedural Sparse Conditional
/// Constant Propagation.
///
- struct VISIBILITY_HIDDEN IPSCCP : public ModulePass {
+ struct IPSCCP : public ModulePass {
static char ID;
IPSCCP() : ModulePass(&ID) {}
bool runOnModule(Module &M);
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
index 4812370..6d06959 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
@@ -38,7 +38,6 @@
#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/Support/IRBuilder.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
@@ -50,7 +49,7 @@ STATISTIC(NumConverted, "Number of aggregates converted to scalar");
STATISTIC(NumGlobals, "Number of allocas copied from constant global");
namespace {
- struct VISIBILITY_HIDDEN SROA : public FunctionPass {
+ struct SROA : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
explicit SROA(signed T = -1) : FunctionPass(&ID) {
if (T == -1)
@@ -245,8 +244,8 @@ bool SROA::performScalarRepl(Function &F) {
// constructs like "void foo() { int A[] = {1,2,3,4,5,6,7,8,9...}; }" if 'A'
// is only subsequently read.
if (Instruction *TheCopy = isOnlyCopiedFromConstantGlobal(AI)) {
- DEBUG(errs() << "Found alloca equal to global: " << *AI);
- DEBUG(errs() << " memcpy = " << *TheCopy);
+ DEBUG(errs() << "Found alloca equal to global: " << *AI << '\n');
+ DEBUG(errs() << " memcpy = " << *TheCopy << '\n');
Constant *TheSrc = cast<Constant>(TheCopy->getOperand(2));
AI->replaceAllUsesWith(ConstantExpr::getBitCast(TheSrc, AI->getType()));
TheCopy->eraseFromParent(); // Don't mutate the global.
@@ -307,7 +306,7 @@ bool SROA::performScalarRepl(Function &F) {
// we just get a lot of insert/extracts. If at least one vector is
// involved, then we probably really do have a union of vector/array.
if (VectorTy && isa<VectorType>(VectorTy) && HadAVector) {
- DEBUG(errs() << "CONVERT TO VECTOR: " << *AI << " TYPE = "
+ DEBUG(errs() << "CONVERT TO VECTOR: " << *AI << "\n TYPE = "
<< *VectorTy << '\n');
// Create and insert the vector alloca.
@@ -338,7 +337,7 @@ bool SROA::performScalarRepl(Function &F) {
/// predicate, do SROA now.
void SROA::DoScalarReplacement(AllocationInst *AI,
std::vector<AllocationInst*> &WorkList) {
- DEBUG(errs() << "Found inst to SROA: " << *AI);
+ DEBUG(errs() << "Found inst to SROA: " << *AI << '\n');
SmallVector<AllocaInst*, 32> ElementAllocas;
if (const StructType *ST = dyn_cast<StructType>(AI->getAllocatedType())) {
ElementAllocas.reserve(ST->getNumContainedTypes());
@@ -489,7 +488,7 @@ void SROA::isSafeElementUse(Value *Ptr, bool isFirstElt, AllocationInst *AI,
if (Info.isUnsafe) return;
break;
}
- DEBUG(errs() << " Transformation preventing inst: " << *User);
+ DEBUG(errs() << " Transformation preventing inst: " << *User << '\n');
return MarkUnsafe(Info);
case Instruction::Call:
if (MemIntrinsic *MI = dyn_cast<MemIntrinsic>(User)) {
@@ -499,10 +498,10 @@ void SROA::isSafeElementUse(Value *Ptr, bool isFirstElt, AllocationInst *AI,
break;
}
}
- DEBUG(errs() << " Transformation preventing inst: " << *User);
+ DEBUG(errs() << " Transformation preventing inst: " << *User << '\n');
return MarkUnsafe(Info);
default:
- DEBUG(errs() << " Transformation preventing inst: " << *User);
+ DEBUG(errs() << " Transformation preventing inst: " << *User << '\n');
return MarkUnsafe(Info);
}
}
@@ -927,7 +926,8 @@ void SROA::RewriteStoreUserOfWholeAlloca(StoreInst *SI,
IntegerType::get(SI->getContext(), AllocaSizeBits),
"", SI);
- DEBUG(errs() << "PROMOTING STORE TO WHOLE ALLOCA: " << *AI << *SI);
+ DEBUG(errs() << "PROMOTING STORE TO WHOLE ALLOCA: " << *AI << '\n' << *SI
+ << '\n');
// There are two forms here: AI could be an array or struct. Both cases
// have different ways to compute the element offset.
@@ -1043,7 +1043,8 @@ void SROA::RewriteLoadUserOfWholeAlloca(LoadInst *LI, AllocationInst *AI,
TD->getTypeAllocSizeInBits(LI->getType()) != AllocaSizeBits)
return;
- DEBUG(errs() << "PROMOTING LOAD OF WHOLE ALLOCA: " << *AI << *LI);
+ DEBUG(errs() << "PROMOTING LOAD OF WHOLE ALLOCA: " << *AI << '\n' << *LI
+ << '\n');
// There are two forms here: AI could be an array or struct. Both cases
// have different ways to compute the element offset.
@@ -1170,7 +1171,8 @@ int SROA::isSafeAllocaToScalarRepl(AllocationInst *AI) {
I != E; ++I) {
isSafeUseOfAllocation(cast<Instruction>(*I), AI, Info);
if (Info.isUnsafe) {
- DEBUG(errs() << "Cannot transform: " << *AI << " due to user: " << **I);
+ DEBUG(errs() << "Cannot transform: " << *AI << "\n due to user: "
+ << **I << '\n');
return 0;
}
}
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
index ca4292b..29712b3 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
@@ -30,7 +30,6 @@
#include "llvm/Module.h"
#include "llvm/Attributes.h"
#include "llvm/Support/CFG.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Pass.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SmallPtrSet.h"
@@ -40,7 +39,7 @@ using namespace llvm;
STATISTIC(NumSimpl, "Number of blocks simplified");
namespace {
- struct VISIBILITY_HIDDEN CFGSimplifyPass : public FunctionPass {
+ struct CFGSimplifyPass : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
CFGSimplifyPass() : FunctionPass(&ID) {}
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyHalfPowrLibCalls.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyHalfPowrLibCalls.cpp
index fb3d62e..13077fe 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyHalfPowrLibCalls.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyHalfPowrLibCalls.cpp
@@ -22,15 +22,13 @@
#include "llvm/Transforms/Utils/Cloning.h"
#include "llvm/Target/TargetData.h"
#include "llvm/ADT/STLExtras.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Config/config.h"
using namespace llvm;
namespace {
/// This pass optimizes well half_powr function calls.
///
- class VISIBILITY_HIDDEN SimplifyHalfPowrLibCalls : public FunctionPass {
+ class SimplifyHalfPowrLibCalls : public FunctionPass {
const TargetData *TD;
public:
static char ID; // Pass identification
@@ -59,8 +57,9 @@ FunctionPass *llvm::createSimplifyHalfPowrLibCallsPass() {
/// InlineHalfPowrs - Inline a sequence of adjacent half_powr calls, rearranging
/// their control flow to better facilitate subsequent optimization.
Instruction *
-SimplifyHalfPowrLibCalls::InlineHalfPowrs(const std::vector<Instruction *> &HalfPowrs,
- Instruction *InsertPt) {
+SimplifyHalfPowrLibCalls::
+InlineHalfPowrs(const std::vector<Instruction *> &HalfPowrs,
+ Instruction *InsertPt) {
std::vector<BasicBlock *> Bodies;
BasicBlock *NewBlock = 0;
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyLibCalls.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyLibCalls.cpp
index 761c309..57a7d05 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyLibCalls.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/SimplifyLibCalls.cpp
@@ -9,11 +9,9 @@
//
// This file implements a simple pass that applies a variety of small
// optimizations for calls to specific well-known function calls (e.g. runtime
-// library functions). For example, a call to the function "exit(3)" that
-// occurs within the main() function can be transformed into a simple "return 3"
-// instruction. Any optimization that takes this form (replace call to library
-// function with simpler code that provides the same result) belongs in this
-// file.
+// library functions). Any optimization that takes the very simple form
+// "replace call to library function with simpler code that provides the same
+// result" belongs in this file.
//
//===----------------------------------------------------------------------===//
@@ -30,7 +28,6 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Config/config.h"
@@ -46,7 +43,7 @@ STATISTIC(NumAnnotated, "Number of attributes added to library functions");
/// This class is the abstract base class for the set of optimizations that
/// corresponds to one library call.
namespace {
-class VISIBILITY_HIDDEN LibCallOptimization {
+class LibCallOptimization {
protected:
Function *Caller;
const TargetData *TD;
@@ -98,7 +95,8 @@ public:
/// 'floor'). This function is known to take a single of type matching 'Op'
/// and returns one value with the same type. If 'Op' is a long double, 'l'
/// is added as the suffix of name, if 'Op' is a float, we add a 'f' suffix.
- Value *EmitUnaryFloatFnCall(Value *Op, const char *Name, IRBuilder<> &B);
+ Value *EmitUnaryFloatFnCall(Value *Op, const char *Name, IRBuilder<> &B,
+ const AttrListPtr &Attrs);
/// EmitPutChar - Emit a call to the putchar function. This assumes that Char
/// is an integer.
@@ -224,7 +222,8 @@ Value *LibCallOptimization::EmitMemSet(Value *Dst, Value *Val,
/// returns one value with the same type. If 'Op' is a long double, 'l' is
/// added as the suffix of name, if 'Op' is a float, we add a 'f' suffix.
Value *LibCallOptimization::EmitUnaryFloatFnCall(Value *Op, const char *Name,
- IRBuilder<> &B) {
+ IRBuilder<> &B,
+ const AttrListPtr &Attrs) {
char NameBuffer[20];
if (Op->getType() != Type::getDoubleTy(*Context)) {
// If we need to add a suffix, copy into NameBuffer.
@@ -243,7 +242,7 @@ Value *LibCallOptimization::EmitUnaryFloatFnCall(Value *Op, const char *Name,
Value *Callee = M->getOrInsertFunction(Name, Op->getType(),
Op->getType(), NULL);
CallInst *CI = B.CreateCall(Callee, Op, Name);
-
+ CI->setAttributes(Attrs);
if (const Function *F = dyn_cast<Function>(Callee->stripPointerCasts()))
CI->setCallingConv(F->getCallingConv());
@@ -500,59 +499,13 @@ static bool IsOnlyUsedInZeroEqualityComparison(Value *V) {
}
//===----------------------------------------------------------------------===//
-// Miscellaneous LibCall Optimizations
-//===----------------------------------------------------------------------===//
-
-namespace {
-//===---------------------------------------===//
-// 'exit' Optimizations
-
-/// ExitOpt - int main() { exit(4); } --> int main() { return 4; }
-struct VISIBILITY_HIDDEN ExitOpt : public LibCallOptimization {
- virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
- // Verify we have a reasonable prototype for exit.
- if (Callee->arg_size() == 0 || !CI->use_empty())
- return 0;
-
- // Verify the caller is main, and that the result type of main matches the
- // argument type of exit.
- if (Caller->getName() != "main" || !Caller->hasExternalLinkage() ||
- Caller->getReturnType() != CI->getOperand(1)->getType())
- return 0;
-
- TerminatorInst *OldTI = CI->getParent()->getTerminator();
-
- // Drop all successor phi node entries.
- for (unsigned i = 0, e = OldTI->getNumSuccessors(); i != e; ++i)
- OldTI->getSuccessor(i)->removePredecessor(CI->getParent());
-
- // Remove all instructions after the exit.
- BasicBlock::iterator Dead = CI, E = OldTI; ++Dead;
- while (Dead != E) {
- BasicBlock::iterator Next = next(Dead);
- if (Dead->getType() != Type::getVoidTy(*Context))
- Dead->replaceAllUsesWith(UndefValue::get(Dead->getType()));
- Dead->eraseFromParent();
- Dead = Next;
- }
-
- // Insert a return instruction.
- OldTI->eraseFromParent();
- B.SetInsertPoint(B.GetInsertBlock());
- B.CreateRet(CI->getOperand(1));
-
- return CI;
- }
-};
-
-//===----------------------------------------------------------------------===//
// String and Memory LibCall Optimizations
//===----------------------------------------------------------------------===//
//===---------------------------------------===//
// 'strcat' Optimizations
-
-struct VISIBILITY_HIDDEN StrCatOpt : public LibCallOptimization {
+namespace {
+struct StrCatOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// Verify the "strcat" function prototype.
const FunctionType *FT = Callee->getFunctionType();
@@ -602,7 +555,7 @@ struct VISIBILITY_HIDDEN StrCatOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'strncat' Optimizations
-struct VISIBILITY_HIDDEN StrNCatOpt : public StrCatOpt {
+struct StrNCatOpt : public StrCatOpt {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// Verify the "strncat" function prototype.
const FunctionType *FT = Callee->getFunctionType();
@@ -650,7 +603,7 @@ struct VISIBILITY_HIDDEN StrNCatOpt : public StrCatOpt {
//===---------------------------------------===//
// 'strchr' Optimizations
-struct VISIBILITY_HIDDEN StrChrOpt : public LibCallOptimization {
+struct StrChrOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// Verify the "strchr" function prototype.
const FunctionType *FT = Callee->getFunctionType();
@@ -706,7 +659,7 @@ struct VISIBILITY_HIDDEN StrChrOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'strcmp' Optimizations
-struct VISIBILITY_HIDDEN StrCmpOpt : public LibCallOptimization {
+struct StrCmpOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// Verify the "strcmp" function prototype.
const FunctionType *FT = Callee->getFunctionType();
@@ -753,7 +706,7 @@ struct VISIBILITY_HIDDEN StrCmpOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'strncmp' Optimizations
-struct VISIBILITY_HIDDEN StrNCmpOpt : public LibCallOptimization {
+struct StrNCmpOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// Verify the "strncmp" function prototype.
const FunctionType *FT = Callee->getFunctionType();
@@ -799,7 +752,7 @@ struct VISIBILITY_HIDDEN StrNCmpOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'strcpy' Optimizations
-struct VISIBILITY_HIDDEN StrCpyOpt : public LibCallOptimization {
+struct StrCpyOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// Verify the "strcpy" function prototype.
const FunctionType *FT = Callee->getFunctionType();
@@ -830,7 +783,7 @@ struct VISIBILITY_HIDDEN StrCpyOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'strncpy' Optimizations
-struct VISIBILITY_HIDDEN StrNCpyOpt : public LibCallOptimization {
+struct StrNCpyOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
if (FT->getNumParams() != 3 || FT->getReturnType() != FT->getParamType(0) ||
@@ -879,7 +832,7 @@ struct VISIBILITY_HIDDEN StrNCpyOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'strlen' Optimizations
-struct VISIBILITY_HIDDEN StrLenOpt : public LibCallOptimization {
+struct StrLenOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
if (FT->getNumParams() != 1 ||
@@ -905,7 +858,7 @@ struct VISIBILITY_HIDDEN StrLenOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'strto*' Optimizations
-struct VISIBILITY_HIDDEN StrToOpt : public LibCallOptimization {
+struct StrToOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
if ((FT->getNumParams() != 2 && FT->getNumParams() != 3) ||
@@ -927,7 +880,7 @@ struct VISIBILITY_HIDDEN StrToOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'memcmp' Optimizations
-struct VISIBILITY_HIDDEN MemCmpOpt : public LibCallOptimization {
+struct MemCmpOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
if (FT->getNumParams() != 3 || !isa<PointerType>(FT->getParamType(0)) ||
@@ -974,7 +927,7 @@ struct VISIBILITY_HIDDEN MemCmpOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'memcpy' Optimizations
-struct VISIBILITY_HIDDEN MemCpyOpt : public LibCallOptimization {
+struct MemCpyOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// These optimizations require TargetData.
if (!TD) return 0;
@@ -995,7 +948,7 @@ struct VISIBILITY_HIDDEN MemCpyOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'memmove' Optimizations
-struct VISIBILITY_HIDDEN MemMoveOpt : public LibCallOptimization {
+struct MemMoveOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// These optimizations require TargetData.
if (!TD) return 0;
@@ -1025,7 +978,7 @@ struct VISIBILITY_HIDDEN MemMoveOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'memset' Optimizations
-struct VISIBILITY_HIDDEN MemSetOpt : public LibCallOptimization {
+struct MemSetOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// These optimizations require TargetData.
if (!TD) return 0;
@@ -1051,7 +1004,7 @@ struct VISIBILITY_HIDDEN MemSetOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'pow*' Optimizations
-struct VISIBILITY_HIDDEN PowOpt : public LibCallOptimization {
+struct PowOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
// Just make sure this has 2 arguments of the same FP type, which match the
@@ -1066,7 +1019,7 @@ struct VISIBILITY_HIDDEN PowOpt : public LibCallOptimization {
if (Op1C->isExactlyValue(1.0)) // pow(1.0, x) -> 1.0
return Op1C;
if (Op1C->isExactlyValue(2.0)) // pow(2.0, x) -> exp2(x)
- return EmitUnaryFloatFnCall(Op2, "exp2", B);
+ return EmitUnaryFloatFnCall(Op2, "exp2", B, Callee->getAttributes());
}
ConstantFP *Op2C = dyn_cast<ConstantFP>(Op2);
@@ -1076,16 +1029,20 @@ struct VISIBILITY_HIDDEN PowOpt : public LibCallOptimization {
return ConstantFP::get(CI->getType(), 1.0);
if (Op2C->isExactlyValue(0.5)) {
- // FIXME: This is not safe for -0.0 and -inf. This can only be done when
- // 'unsafe' math optimizations are allowed.
- // x pow(x, 0.5) sqrt(x)
- // ---------------------------------------------
- // -0.0 +0.0 -0.0
- // -inf +inf NaN
-#if 0
- // pow(x, 0.5) -> sqrt(x)
- return B.CreateCall(get_sqrt(), Op1, "sqrt");
-#endif
+ // Expand pow(x, 0.5) to (x == -infinity ? +infinity : fabs(sqrt(x))).
+ // This is faster than calling pow, and still handles negative zero
+ // and negative infinite correctly.
+ // TODO: In fast-math mode, this could be just sqrt(x).
+ // TODO: In finite-only mode, this could be just fabs(sqrt(x)).
+ Value *Inf = ConstantFP::getInfinity(CI->getType());
+ Value *NegInf = ConstantFP::getInfinity(CI->getType(), true);
+ Value *Sqrt = EmitUnaryFloatFnCall(Op1, "sqrt", B,
+ Callee->getAttributes());
+ Value *FAbs = EmitUnaryFloatFnCall(Sqrt, "fabs", B,
+ Callee->getAttributes());
+ Value *FCmp = B.CreateFCmpOEQ(Op1, NegInf, "tmp");
+ Value *Sel = B.CreateSelect(FCmp, Inf, FAbs, "tmp");
+ return Sel;
}
if (Op2C->isExactlyValue(1.0)) // pow(x, 1.0) -> x
@@ -1102,7 +1059,7 @@ struct VISIBILITY_HIDDEN PowOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'exp2' Optimizations
-struct VISIBILITY_HIDDEN Exp2Opt : public LibCallOptimization {
+struct Exp2Opt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
// Just make sure this has 1 argument of FP type, which matches the
@@ -1152,7 +1109,7 @@ struct VISIBILITY_HIDDEN Exp2Opt : public LibCallOptimization {
//===---------------------------------------===//
// Double -> Float Shrinking Optimizations for Unary Functions like 'floor'
-struct VISIBILITY_HIDDEN UnaryDoubleFPOpt : public LibCallOptimization {
+struct UnaryDoubleFPOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
if (FT->getNumParams() != 1 || FT->getReturnType() != Type::getDoubleTy(*Context) ||
@@ -1166,7 +1123,8 @@ struct VISIBILITY_HIDDEN UnaryDoubleFPOpt : public LibCallOptimization {
// floor((double)floatval) -> (double)floorf(floatval)
Value *V = Cast->getOperand(0);
- V = EmitUnaryFloatFnCall(V, Callee->getName().data(), B);
+ V = EmitUnaryFloatFnCall(V, Callee->getName().data(), B,
+ Callee->getAttributes());
return B.CreateFPExt(V, Type::getDoubleTy(*Context));
}
};
@@ -1178,7 +1136,7 @@ struct VISIBILITY_HIDDEN UnaryDoubleFPOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'ffs*' Optimizations
-struct VISIBILITY_HIDDEN FFSOpt : public LibCallOptimization {
+struct FFSOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
// Just make sure this has 2 arguments of the same FP type, which match the
@@ -1213,7 +1171,7 @@ struct VISIBILITY_HIDDEN FFSOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'isdigit' Optimizations
-struct VISIBILITY_HIDDEN IsDigitOpt : public LibCallOptimization {
+struct IsDigitOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
// We require integer(i32)
@@ -1234,7 +1192,7 @@ struct VISIBILITY_HIDDEN IsDigitOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'isascii' Optimizations
-struct VISIBILITY_HIDDEN IsAsciiOpt : public LibCallOptimization {
+struct IsAsciiOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
// We require integer(i32)
@@ -1253,7 +1211,7 @@ struct VISIBILITY_HIDDEN IsAsciiOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'abs', 'labs', 'llabs' Optimizations
-struct VISIBILITY_HIDDEN AbsOpt : public LibCallOptimization {
+struct AbsOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
// We require integer(integer) where the types agree.
@@ -1275,7 +1233,7 @@ struct VISIBILITY_HIDDEN AbsOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'toascii' Optimizations
-struct VISIBILITY_HIDDEN ToAsciiOpt : public LibCallOptimization {
+struct ToAsciiOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
const FunctionType *FT = Callee->getFunctionType();
// We require i32(i32)
@@ -1296,7 +1254,7 @@ struct VISIBILITY_HIDDEN ToAsciiOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'printf' Optimizations
-struct VISIBILITY_HIDDEN PrintFOpt : public LibCallOptimization {
+struct PrintFOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// Require one fixed pointer argument and an integer/void result.
const FunctionType *FT = Callee->getFunctionType();
@@ -1359,7 +1317,7 @@ struct VISIBILITY_HIDDEN PrintFOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'sprintf' Optimizations
-struct VISIBILITY_HIDDEN SPrintFOpt : public LibCallOptimization {
+struct SPrintFOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// Require two fixed pointer arguments and an integer result.
const FunctionType *FT = Callee->getFunctionType();
@@ -1431,7 +1389,7 @@ struct VISIBILITY_HIDDEN SPrintFOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'fwrite' Optimizations
-struct VISIBILITY_HIDDEN FWriteOpt : public LibCallOptimization {
+struct FWriteOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// Require a pointer, an integer, an integer, a pointer, returning integer.
const FunctionType *FT = Callee->getFunctionType();
@@ -1466,7 +1424,7 @@ struct VISIBILITY_HIDDEN FWriteOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'fputs' Optimizations
-struct VISIBILITY_HIDDEN FPutsOpt : public LibCallOptimization {
+struct FPutsOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// These optimizations require TargetData.
if (!TD) return 0;
@@ -1491,7 +1449,7 @@ struct VISIBILITY_HIDDEN FPutsOpt : public LibCallOptimization {
//===---------------------------------------===//
// 'fprintf' Optimizations
-struct VISIBILITY_HIDDEN FPrintFOpt : public LibCallOptimization {
+struct FPrintFOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
// Require two fixed paramters as pointers and integer result.
const FunctionType *FT = Callee->getFunctionType();
@@ -1553,10 +1511,8 @@ struct VISIBILITY_HIDDEN FPrintFOpt : public LibCallOptimization {
namespace {
/// This pass optimizes well known library functions from libc and libm.
///
- class VISIBILITY_HIDDEN SimplifyLibCalls : public FunctionPass {
+ class SimplifyLibCalls : public FunctionPass {
StringMap<LibCallOptimization*> Optimizations;
- // Miscellaneous LibCall Optimizations
- ExitOpt Exit;
// String and Memory LibCall Optimizations
StrCatOpt StrCat; StrNCatOpt StrNCat; StrChrOpt StrChr; StrCmpOpt StrCmp;
StrNCmpOpt StrNCmp; StrCpyOpt StrCpy; StrNCpyOpt StrNCpy; StrLenOpt StrLen;
@@ -1603,9 +1559,6 @@ FunctionPass *llvm::createSimplifyLibCallsPass() {
/// Optimizations - Populate the Optimizations map with all the optimizations
/// we know.
void SimplifyLibCalls::InitOptimizations() {
- // Miscellaneous LibCall Optimizations
- Optimizations["exit"] = &Exit;
-
// String and Memory LibCall Optimizations
Optimizations["strcat"] = &StrCat;
Optimizations["strncat"] = &StrNCat;
@@ -1907,7 +1860,13 @@ bool SimplifyLibCalls::doInitialization(Module &M) {
}
break;
case 'm':
- if (Name == "memcmp") {
+ if (Name == "malloc") {
+ if (FTy->getNumParams() != 1 ||
+ !isa<PointerType>(FTy->getReturnType()))
+ continue;
+ setDoesNotThrow(F);
+ setDoesNotAlias(F, 0);
+ } else if (Name == "memcmp") {
if (FTy->getNumParams() != 3 ||
!isa<PointerType>(FTy->getParamType(0)) ||
!isa<PointerType>(FTy->getParamType(1)))
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/TailDuplication.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/TailDuplication.cpp
index 4bd9436..68689d6 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/TailDuplication.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/TailDuplication.cpp
@@ -30,7 +30,6 @@
#include "llvm/Analysis/ConstantFolding.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/Statistic.h"
@@ -46,7 +45,7 @@ TailDupThreshold("taildup-threshold",
cl::init(1), cl::Hidden);
namespace {
- class VISIBILITY_HIDDEN TailDup : public FunctionPass {
+ class TailDup : public FunctionPass {
bool runOnFunction(Function &F);
public:
static char ID; // Pass identification, replacement for typeid
@@ -129,7 +128,7 @@ bool TailDup::shouldEliminateUnconditionalBranch(TerminatorInst *TI,
// other instructions.
if (isa<CallInst>(I) || isa<InvokeInst>(I)) return false;
- // Allso alloca and malloc.
+ // Also alloca and malloc.
if (isa<AllocationInst>(I)) return false;
// Some vector instructions can expand into a number of instructions.
@@ -306,7 +305,7 @@ void TailDup::eliminateUnconditionalBranch(BranchInst *Branch) {
// keeping track of the mapping...
//
for (; BI != DestBlock->end(); ++BI) {
- Instruction *New = BI->clone(BI->getContext());
+ Instruction *New = BI->clone();
New->setName(BI->getName());
SourceBlock->getInstList().push_back(New);
ValueMapping[BI] = New;
diff --git a/libclamav/c++/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp b/libclamav/c++/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
index b84a1f0..b56e170 100644
--- a/libclamav/c++/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
@@ -60,14 +60,13 @@
#include "llvm/Pass.h"
#include "llvm/Support/CFG.h"
#include "llvm/ADT/Statistic.h"
-#include "llvm/Support/Compiler.h"
using namespace llvm;
STATISTIC(NumEliminated, "Number of tail calls removed");
STATISTIC(NumAccumAdded, "Number of accumulators introduced");
namespace {
- struct VISIBILITY_HIDDEN TailCallElim : public FunctionPass {
+ struct TailCallElim : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
TailCallElim() : FunctionPass(&ID) {}
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
index c3d6194..4931ab3 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
@@ -24,6 +24,7 @@
#include "llvm/Analysis/Dominators.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Transforms/Utils/Local.h"
+#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/ValueHandle.h"
#include <algorithm>
@@ -319,7 +320,8 @@ BasicBlock *llvm::SplitBlock(BasicBlock *Old, Instruction *SplitPt, Pass *P) {
++SplitIt;
BasicBlock *New = Old->splitBasicBlock(SplitIt, Old->getName()+".split");
- // The new block lives in whichever loop the old one did.
+ // The new block lives in whichever loop the old one did. This preserves
+ // LCSSA as well, because we force the split point to be after any PHI nodes.
if (LoopInfo* LI = P->getAnalysisIfAvailable<LoopInfo>())
if (Loop *L = LI->getLoopFor(Old))
L->addBasicBlockToLoop(New, LI->getBase());
@@ -353,8 +355,12 @@ BasicBlock *llvm::SplitBlock(BasicBlock *Old, Instruction *SplitPt, Pass *P) {
/// Preds array, which has NumPreds elements in it. The new block is given a
/// suffix of 'Suffix'.
///
-/// This currently updates the LLVM IR, AliasAnalysis, DominatorTree and
-/// DominanceFrontier, but no other analyses.
+/// This currently updates the LLVM IR, AliasAnalysis, DominatorTree,
+/// DominanceFrontier, LoopInfo, and LCCSA but no other analyses.
+/// In particular, it does not preserve LoopSimplify (because it's
+/// complicated to handle the case where one of the edges being split
+/// is an exit of a loop with other exits).
+///
BasicBlock *llvm::SplitBlockPredecessors(BasicBlock *BB,
BasicBlock *const *Preds,
unsigned NumPreds, const char *Suffix,
@@ -366,19 +372,44 @@ BasicBlock *llvm::SplitBlockPredecessors(BasicBlock *BB,
// The new block unconditionally branches to the old block.
BranchInst *BI = BranchInst::Create(BB, NewBB);
+ LoopInfo *LI = P ? P->getAnalysisIfAvailable<LoopInfo>() : 0;
+ Loop *L = LI ? LI->getLoopFor(BB) : 0;
+ bool PreserveLCSSA = P->mustPreserveAnalysisID(LCSSAID);
+
// Move the edges from Preds to point to NewBB instead of BB.
- for (unsigned i = 0; i != NumPreds; ++i)
+ // While here, if we need to preserve loop analyses, collect
+ // some information about how this split will affect loops.
+ bool HasLoopExit = false;
+ bool IsLoopEntry = !!L;
+ bool SplitMakesNewLoopHeader = false;
+ for (unsigned i = 0; i != NumPreds; ++i) {
Preds[i]->getTerminator()->replaceUsesOfWith(BB, NewBB);
-
+
+ if (LI) {
+ // If we need to preserve LCSSA, determine if any of
+ // the preds is a loop exit.
+ if (PreserveLCSSA)
+ if (Loop *PL = LI->getLoopFor(Preds[i]))
+ if (!PL->contains(BB))
+ HasLoopExit = true;
+ // If we need to preserve LoopInfo, note whether any of the
+ // preds crosses an interesting loop boundary.
+ if (L) {
+ if (L->contains(Preds[i]))
+ IsLoopEntry = false;
+ else
+ SplitMakesNewLoopHeader = true;
+ }
+ }
+ }
+
// Update dominator tree and dominator frontier if available.
DominatorTree *DT = P ? P->getAnalysisIfAvailable<DominatorTree>() : 0;
if (DT)
DT->splitBlock(NewBB);
if (DominanceFrontier *DF = P ? P->getAnalysisIfAvailable<DominanceFrontier>():0)
DF->splitBlock(NewBB);
- AliasAnalysis *AA = P ? P->getAnalysisIfAvailable<AliasAnalysis>() : 0;
-
-
+
// Insert a new PHI node into NewBB for every PHI node in BB and that new PHI
// node becomes an incoming value for BB's phi node. However, if the Preds
// list is empty, we need to insert dummy entries into the PHI nodes in BB to
@@ -389,20 +420,42 @@ BasicBlock *llvm::SplitBlockPredecessors(BasicBlock *BB,
cast<PHINode>(I)->addIncoming(UndefValue::get(I->getType()), NewBB);
return NewBB;
}
+
+ AliasAnalysis *AA = P ? P->getAnalysisIfAvailable<AliasAnalysis>() : 0;
+
+ if (L) {
+ if (IsLoopEntry) {
+ if (Loop *PredLoop = LI->getLoopFor(Preds[0])) {
+ // Add the new block to the nearest enclosing loop (and not an
+ // adjacent loop).
+ while (PredLoop && !PredLoop->contains(BB))
+ PredLoop = PredLoop->getParentLoop();
+ if (PredLoop)
+ PredLoop->addBasicBlockToLoop(NewBB, LI->getBase());
+ }
+ } else {
+ L->addBasicBlockToLoop(NewBB, LI->getBase());
+ if (SplitMakesNewLoopHeader)
+ L->moveToHeader(NewBB);
+ }
+ }
// Otherwise, create a new PHI node in NewBB for each PHI node in BB.
for (BasicBlock::iterator I = BB->begin(); isa<PHINode>(I); ) {
PHINode *PN = cast<PHINode>(I++);
// Check to see if all of the values coming in are the same. If so, we
- // don't need to create a new PHI node.
- Value *InVal = PN->getIncomingValueForBlock(Preds[0]);
- for (unsigned i = 1; i != NumPreds; ++i)
- if (InVal != PN->getIncomingValueForBlock(Preds[i])) {
- InVal = 0;
- break;
- }
-
+ // don't need to create a new PHI node, unless it's needed for LCSSA.
+ Value *InVal = 0;
+ if (!HasLoopExit) {
+ InVal = PN->getIncomingValueForBlock(Preds[0]);
+ for (unsigned i = 1; i != NumPreds; ++i)
+ if (InVal != PN->getIncomingValueForBlock(Preds[i])) {
+ InVal = 0;
+ break;
+ }
+ }
+
if (InVal) {
// If all incoming values for the new PHI would be the same, just don't
// make a new PHI. Instead, just remove the incoming values from the old
@@ -427,16 +480,6 @@ BasicBlock *llvm::SplitBlockPredecessors(BasicBlock *BB,
// Add an incoming value to the PHI node in the loop for the preheader
// edge.
PN->addIncoming(InVal, NewBB);
-
- // Check to see if we can eliminate this phi node.
- if (Value *V = PN->hasConstantValue(DT != 0)) {
- Instruction *I = dyn_cast<Instruction>(V);
- if (!I || DT == 0 || DT->dominates(I, PN)) {
- PN->replaceAllUsesWith(V);
- if (AA) AA->deleteValue(PN);
- PN->eraseFromParent();
- }
- }
}
return NewBB;
@@ -620,7 +663,7 @@ void llvm::CopyPrecedingStopPoint(Instruction *I,
if (I != I->getParent()->begin()) {
BasicBlock::iterator BBI = I; --BBI;
if (DbgStopPointInst *DSPI = dyn_cast<DbgStopPointInst>(BBI)) {
- CallInst *newDSPI = DSPI->clone(I->getContext());
+ CallInst *newDSPI = DSPI->clone();
newDSPI->insertBefore(InsertPos);
}
}
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
index 632aa2b..849b2b5 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
@@ -21,6 +21,7 @@
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Analysis/Dominators.h"
#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/ProfileInfo.h"
#include "llvm/Function.h"
#include "llvm/Instructions.h"
#include "llvm/Type.h"
@@ -44,6 +45,7 @@ namespace {
AU.addPreserved<DominatorTree>();
AU.addPreserved<DominanceFrontier>();
AU.addPreserved<LoopInfo>();
+ AU.addPreserved<ProfileInfo>();
// No loop canonicalization guarantees are broken by this pass.
AU.addPreservedID(LoopSimplifyID);
@@ -115,6 +117,38 @@ bool llvm::isCriticalEdge(const TerminatorInst *TI, unsigned SuccNum,
return false;
}
+/// CreatePHIsForSplitLoopExit - When a loop exit edge is split, LCSSA form
+/// may require new PHIs in the new exit block. This function inserts the
+/// new PHIs, as needed. Preds is a list of preds inside the loop, SplitBB
+/// is the new loop exit block, and DestBB is the old loop exit, now the
+/// successor of SplitBB.
+static void CreatePHIsForSplitLoopExit(SmallVectorImpl<BasicBlock *> &Preds,
+ BasicBlock *SplitBB,
+ BasicBlock *DestBB) {
+ // SplitBB shouldn't have anything non-trivial in it yet.
+ assert(SplitBB->getFirstNonPHI() == SplitBB->getTerminator() &&
+ "SplitBB has non-PHI nodes!");
+
+ // For each PHI in the destination block...
+ for (BasicBlock::iterator I = DestBB->begin();
+ PHINode *PN = dyn_cast<PHINode>(I); ++I) {
+ unsigned Idx = PN->getBasicBlockIndex(SplitBB);
+ Value *V = PN->getIncomingValue(Idx);
+ // If the input is a PHI which already satisfies LCSSA, don't create
+ // a new one.
+ if (const PHINode *VP = dyn_cast<PHINode>(V))
+ if (VP->getParent() == SplitBB)
+ continue;
+ // Otherwise a new PHI is needed. Create one and populate it.
+ PHINode *NewPN = PHINode::Create(PN->getType(), "split",
+ SplitBB->getTerminator());
+ for (unsigned i = 0, e = Preds.size(); i != e; ++i)
+ NewPN->addIncoming(V, Preds[i]);
+ // Update the original PHI.
+ PN->setIncomingValue(Idx, NewPN);
+ }
+}
+
/// SplitCriticalEdge - If this edge is a critical edge, insert a new node to
/// split the critical edge. This will update DominatorTree and
/// DominatorFrontier information if it is available, thus calling this pass
@@ -122,9 +156,9 @@ bool llvm::isCriticalEdge(const TerminatorInst *TI, unsigned SuccNum,
/// false otherwise. This ensures that all edges to that dest go to one block
/// instead of each going to a different block.
//
-bool llvm::SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum, Pass *P,
- bool MergeIdenticalEdges) {
- if (!isCriticalEdge(TI, SuccNum, MergeIdenticalEdges)) return false;
+BasicBlock *llvm::SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum,
+ Pass *P, bool MergeIdenticalEdges) {
+ if (!isCriticalEdge(TI, SuccNum, MergeIdenticalEdges)) return 0;
BasicBlock *TIBB = TI->getParent();
BasicBlock *DestBB = TI->getSuccessor(SuccNum);
@@ -172,7 +206,7 @@ bool llvm::SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum, Pass *P,
// If we don't have a pass object, we can't update anything...
- if (P == 0) return true;
+ if (P == 0) return NewBB;
// Now update analysis information. Since the only predecessor of NewBB is
// the TIBB, TIBB clearly dominates NewBB. TIBB usually doesn't dominate
@@ -254,9 +288,9 @@ bool llvm::SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum, Pass *P,
// Update LoopInfo if it is around.
if (LoopInfo *LI = P->getAnalysisIfAvailable<LoopInfo>()) {
- // If one or the other blocks were not in a loop, the new block is not
- // either, and thus LI doesn't need to be updated.
- if (Loop *TIL = LI->getLoopFor(TIBB))
+ if (Loop *TIL = LI->getLoopFor(TIBB)) {
+ // If one or the other blocks were not in a loop, the new block is not
+ // either, and thus LI doesn't need to be updated.
if (Loop *DestLoop = LI->getLoopFor(DestBB)) {
if (TIL == DestLoop) {
// Both in the same loop, the NewBB joins loop.
@@ -278,6 +312,65 @@ bool llvm::SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum, Pass *P,
P->addBasicBlockToLoop(NewBB, LI->getBase());
}
}
+ // If TIBB is in a loop and DestBB is outside of that loop, split the
+ // other exit blocks of the loop that also have predecessors outside
+ // the loop, to maintain a LoopSimplify guarantee.
+ if (!TIL->contains(DestBB) &&
+ P->mustPreserveAnalysisID(LoopSimplifyID)) {
+ assert(!TIL->contains(NewBB) &&
+ "Split point for loop exit is contained in loop!");
+
+ // Update LCSSA form in the newly created exit block.
+ if (P->mustPreserveAnalysisID(LCSSAID)) {
+ SmallVector<BasicBlock *, 1> OrigPred;
+ OrigPred.push_back(TIBB);
+ CreatePHIsForSplitLoopExit(OrigPred, NewBB, DestBB);
+ }
+
+ // For each unique exit block...
+ SmallVector<BasicBlock *, 4> ExitBlocks;
+ TIL->getExitBlocks(ExitBlocks);
+ for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i) {
+ // Collect all the preds that are inside the loop, and note
+ // whether there are any preds outside the loop.
+ SmallVector<BasicBlock *, 4> Preds;
+ bool HasPredOutsideOfLoop = false;
+ BasicBlock *Exit = ExitBlocks[i];
+ for (pred_iterator I = pred_begin(Exit), E = pred_end(Exit);
+ I != E; ++I)
+ if (TIL->contains(*I))
+ Preds.push_back(*I);
+ else
+ HasPredOutsideOfLoop = true;
+ // If there are any preds not in the loop, we'll need to split
+ // the edges. The Preds.empty() check is needed because a block
+ // may appear multiple times in the list. We can't use
+ // getUniqueExitBlocks above because that depends on LoopSimplify
+ // form, which we're in the process of restoring!
+ if (!Preds.empty() && HasPredOutsideOfLoop) {
+ BasicBlock *NewExitBB =
+ SplitBlockPredecessors(Exit, Preds.data(), Preds.size(),
+ "split", P);
+ if (P->mustPreserveAnalysisID(LCSSAID))
+ CreatePHIsForSplitLoopExit(Preds, NewExitBB, Exit);
+ }
+ }
+ }
+ // LCSSA form was updated above for the case where LoopSimplify is
+ // available, which means that all predecessors of loop exit blocks
+ // are within the loop. Without LoopSimplify form, it would be
+ // necessary to insert a new phi.
+ assert((!P->mustPreserveAnalysisID(LCSSAID) ||
+ P->mustPreserveAnalysisID(LoopSimplifyID)) &&
+ "SplitCriticalEdge doesn't know how to update LCCSA form "
+ "without LoopSimplify!");
+ }
}
- return true;
+
+ // Update ProfileInfo if it is around.
+ if (ProfileInfo *PI = P->getAnalysisIfAvailable<ProfileInfo>()) {
+ PI->splitEdge(TIBB,DestBB,NewBB,MergeIdenticalEdges);
+ }
+
+ return NewBB;
}
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/CloneFunction.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/CloneFunction.cpp
index fd72ca1..f042bc9 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/CloneFunction.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/CloneFunction.cpp
@@ -43,7 +43,7 @@ BasicBlock *llvm::CloneBasicBlock(const BasicBlock *BB,
// Loop over all instructions, and copy them over.
for (BasicBlock::const_iterator II = BB->begin(), IE = BB->end();
II != IE; ++II) {
- Instruction *NewInst = II->clone(BB->getContext());
+ Instruction *NewInst = II->clone();
if (II->hasName())
NewInst->setName(II->getName()+NameSuffix);
NewBB->getInstList().push_back(NewInst);
@@ -248,7 +248,7 @@ void PruningFunctionCloner::CloneBlock(const BasicBlock *BB,
continue;
}
- Instruction *NewInst = II->clone(BB->getContext());
+ Instruction *NewInst = II->clone();
if (II->hasName())
NewInst->setName(II->getName()+NameSuffix);
NewBB->getInstList().push_back(NewInst);
@@ -296,7 +296,7 @@ void PruningFunctionCloner::CloneBlock(const BasicBlock *BB,
}
if (!TerminatorDone) {
- Instruction *NewInst = OldTI->clone(BB->getContext());
+ Instruction *NewInst = OldTI->clone();
if (OldTI->hasName())
NewInst->setName(OldTI->getName()+NameSuffix);
NewBB->getInstList().push_back(NewInst);
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/InlineCost.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/InlineCost.cpp
index fe4d060..a61b1a9 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/InlineCost.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/InlineCost.cpp
@@ -11,7 +11,6 @@
//
//===----------------------------------------------------------------------===//
-
#include "llvm/Transforms/Utils/InlineCost.h"
#include "llvm/Support/CallSite.h"
#include "llvm/CallingConv.h"
@@ -51,7 +50,7 @@ unsigned InlineCostAnalyzer::FunctionInfo::
// Unfortunately, we don't know the pointer that may get propagated here,
// so we can't make this decision.
if (Inst.mayReadFromMemory() || Inst.mayHaveSideEffects() ||
- isa<AllocationInst>(Inst))
+ isa<AllocationInst>(Inst))
continue;
bool AllOperandsConstant = true;
@@ -103,7 +102,7 @@ unsigned InlineCostAnalyzer::FunctionInfo::
/// analyzeFunction - Fill in the current structure with information gleaned
/// from the specified function.
void InlineCostAnalyzer::FunctionInfo::analyzeFunction(Function *F) {
- unsigned NumInsts = 0, NumBlocks = 0, NumVectorInsts = 0;
+ unsigned NumInsts = 0, NumBlocks = 0, NumVectorInsts = 0, NumRets = 0;
// Look at the size of the callee. Each basic block counts as 20 units, and
// each instruction counts as 5.
@@ -156,6 +155,9 @@ void InlineCostAnalyzer::FunctionInfo::analyzeFunction(Function *F) {
if (GEPI->hasAllConstantIndices())
continue;
}
+
+ if (isa<ReturnInst>(II))
+ ++NumRets;
++NumInsts;
}
@@ -163,6 +165,11 @@ void InlineCostAnalyzer::FunctionInfo::analyzeFunction(Function *F) {
++NumBlocks;
}
+ // A function with exactly one return has it removed during the inlining
+ // process (see InlineFunction), so don't count it.
+ if (NumRets==1)
+ --NumInsts;
+
this->NumBlocks = NumBlocks;
this->NumInsts = NumInsts;
this->NumVectorInsts = NumVectorInsts;
@@ -185,11 +192,10 @@ InlineCost InlineCostAnalyzer::getInlineCost(CallSite CS,
Function *Callee = CS.getCalledFunction();
Function *Caller = TheCall->getParent()->getParent();
- // Don't inline functions which can be redefined at link-time to mean
- // something else.
- if (Callee->mayBeOverridden() ||
- // Don't inline functions marked noinline.
- Callee->hasFnAttr(Attribute::NoInline) || NeverInline.count(Callee))
+ // Don't inline functions which can be redefined at link-time to mean
+ // something else. Don't inline functions marked noinline.
+ if (Callee->mayBeOverridden() ||
+ Callee->hasFnAttr(Attribute::NoInline) || NeverInline.count(Callee))
return llvm::InlineCost::getNever();
// InlineCost - This value measures how good of an inline candidate this call
@@ -290,6 +296,7 @@ InlineCost InlineCostAnalyzer::getInlineCost(CallSite CS,
// likely to be inlined, look at factors that make us not want to inline it.
// Don't inline into something too big, which would make it bigger.
+ // "size" here is the number of basic blocks, not instructions.
//
InlineCost += Caller->size()/15;
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/InlineFunction.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/InlineFunction.cpp
index 4e738e4..f9efc34 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/InlineFunction.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/InlineFunction.cpp
@@ -40,16 +40,14 @@ bool llvm::InlineFunction(InvokeInst *II, CallGraph *CG, const TargetData *TD,
/// HandleCallsInBlockInlinedThroughInvoke - When we inline a basic block into
-/// an invoke, we have to check all of all of the calls that can throw into
+/// an invoke, we have to turn all of the calls that can throw into
/// invokes. This function analyze BB to see if there are any calls, and if so,
/// it rewrites them to be invokes that jump to InvokeDest and fills in the PHI
-/// nodes in that block with the values specified in InvokeDestPHIValues. If
-/// CallerCGN is specified, this function updates the call graph.
+/// nodes in that block with the values specified in InvokeDestPHIValues.
///
static void HandleCallsInBlockInlinedThroughInvoke(BasicBlock *BB,
BasicBlock *InvokeDest,
- const SmallVectorImpl<Value*> &InvokeDestPHIValues,
- CallGraphNode *CallerCGN) {
+ const SmallVectorImpl<Value*> &InvokeDestPHIValues) {
for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) {
Instruction *I = BBI++;
@@ -76,24 +74,10 @@ static void HandleCallsInBlockInlinedThroughInvoke(BasicBlock *BB,
II->setCallingConv(CI->getCallingConv());
II->setAttributes(CI->getAttributes());
- // Make sure that anything using the call now uses the invoke!
+ // Make sure that anything using the call now uses the invoke! This also
+ // updates the CallGraph if present.
CI->replaceAllUsesWith(II);
- // Update the callgraph if present.
- if (CallerCGN) {
- // We should be able to do this:
- // (*CG)[Caller]->replaceCallSite(CI, II);
- // but that fails if the old call site isn't in the call graph,
- // which, because of LLVM bug 3601, it sometimes isn't.
- for (CallGraphNode::iterator NI = CallerCGN->begin(), NE = CallerCGN->end();
- NI != NE; ++NI) {
- if (NI->first == CI) {
- NI->first = II;
- break;
- }
- }
- }
-
// Delete the unconditional branch inserted by splitBasicBlock
BB->getInstList().pop_back();
Split->getInstList().pop_front(); // Delete the original call
@@ -120,8 +104,7 @@ static void HandleCallsInBlockInlinedThroughInvoke(BasicBlock *BB,
/// block of the inlined code (the last block is the end of the function),
/// and InlineCodeInfo is information about the code that got inlined.
static void HandleInlinedInvoke(InvokeInst *II, BasicBlock *FirstNewBlock,
- ClonedCodeInfo &InlinedCodeInfo,
- CallGraph *CG) {
+ ClonedCodeInfo &InlinedCodeInfo) {
BasicBlock *InvokeDest = II->getUnwindDest();
SmallVector<Value*, 8> InvokeDestPHIValues;
@@ -150,13 +133,10 @@ static void HandleInlinedInvoke(InvokeInst *II, BasicBlock *FirstNewBlock,
return;
}
- CallGraphNode *CallerCGN = 0;
- if (CG) CallerCGN = (*CG)[Caller];
-
for (Function::iterator BB = FirstNewBlock, E = Caller->end(); BB != E; ++BB){
if (InlinedCodeInfo.ContainsCalls)
HandleCallsInBlockInlinedThroughInvoke(BB, InvokeDest,
- InvokeDestPHIValues, CallerCGN);
+ InvokeDestPHIValues);
if (UnwindInst *UI = dyn_cast<UnwindInst>(BB->getTerminator())) {
// An UnwindInst requires special handling when it gets inlined into an
@@ -212,7 +192,7 @@ static void UpdateCallGraphAfterInlining(CallSite CS,
}
for (; I != E; ++I) {
- const Instruction *OrigCall = I->first.getInstruction();
+ const Value *OrigCall = I->first;
DenseMap<const Value*, Value*>::iterator VMI = ValueMap.find(OrigCall);
// Only copy the edge if the call was inlined!
@@ -394,7 +374,7 @@ bool llvm::InlineFunction(CallSite CS, CallGraph *CG, const TargetData *TD,
BI != BE; ++BI) {
if (DbgStopPointInst *DSPI = dyn_cast<DbgStopPointInst>(BI)) {
if (DbgRegionEndInst *NewDREI =
- dyn_cast<DbgRegionEndInst>(DREI->clone(Context)))
+ dyn_cast<DbgRegionEndInst>(DREI->clone()))
NewDREI->insertAfter(DSPI);
break;
}
@@ -539,7 +519,7 @@ bool llvm::InlineFunction(CallSite CS, CallGraph *CG, const TargetData *TD,
// any inlined 'unwind' instructions into branches to the invoke exception
// destination, and call instructions into invoke instructions.
if (InvokeInst *II = dyn_cast<InvokeInst>(TheCall))
- HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo, CG);
+ HandleInlinedInvoke(II, FirstNewBlock, InlinedFunctionInfo);
// If we cloned in _exactly one_ basic block, and if that block ends in a
// return instruction, we splice the body of the inlined callee directly into
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/LCSSA.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/LCSSA.cpp
index 84fcc64..48e6a17 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/LCSSA.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/LCSSA.cpp
@@ -58,6 +58,7 @@ namespace {
DominatorTree *DT;
std::vector<BasicBlock*> LoopBlocks;
PredIteratorCache PredCache;
+ Loop *L;
virtual bool runOnLoop(Loop *L, LPPassManager &LPM);
@@ -72,9 +73,9 @@ namespace {
AU.setPreservesCFG();
AU.addRequiredID(LoopSimplifyID);
AU.addPreservedID(LoopSimplifyID);
- AU.addRequired<LoopInfo>();
+ AU.addRequiredTransitive<LoopInfo>();
AU.addPreserved<LoopInfo>();
- AU.addRequired<DominatorTree>();
+ AU.addRequiredTransitive<DominatorTree>();
AU.addPreserved<ScalarEvolution>();
AU.addPreserved<DominatorTree>();
@@ -86,6 +87,13 @@ namespace {
AU.addPreserved<DominanceFrontier>();
}
private:
+
+ /// verifyAnalysis() - Verify loop nest.
+ virtual void verifyAnalysis() const {
+ // Check the special guarantees that LCSSA makes.
+ assert(L->isLCSSAForm() && "LCSSA form not preserved!");
+ }
+
void getLoopValuesUsedOutsideLoop(Loop *L,
SetVector<Instruction*> &AffectedValues,
const SmallVector<BasicBlock*, 8>& exitBlocks);
@@ -107,7 +115,8 @@ Pass *llvm::createLCSSAPass() { return new LCSSA(); }
const PassInfo *const llvm::LCSSAID = &X;
/// runOnFunction - Process all loops in the function, inner-most out.
-bool LCSSA::runOnLoop(Loop *L, LPPassManager &LPM) {
+bool LCSSA::runOnLoop(Loop *l, LPPassManager &LPM) {
+ L = l;
PredCache.clear();
LI = &LPM.getAnalysis<LoopInfo>();
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/Local.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/Local.cpp
index 18ce81d..b622611 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/Local.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/Local.cpp
@@ -24,6 +24,7 @@
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/Analysis/ConstantFolding.h"
#include "llvm/Analysis/DebugInfo.h"
+#include "llvm/Analysis/ProfileInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/Support/MathExtras.h"
@@ -294,7 +295,7 @@ llvm::RecursivelyDeleteDeadPHINode(PHINode *PN) {
/// between them, moving the instructions in the predecessor into DestBB and
/// deleting the predecessor block.
///
-void llvm::MergeBasicBlockIntoOnlyPred(BasicBlock *DestBB) {
+void llvm::MergeBasicBlockIntoOnlyPred(BasicBlock *DestBB, Pass *P) {
// If BB has single-entry PHI nodes, fold them.
while (PHINode *PN = dyn_cast<PHINode>(DestBB->begin())) {
Value *NewVal = PN->getIncomingValue(0);
@@ -314,6 +315,13 @@ void llvm::MergeBasicBlockIntoOnlyPred(BasicBlock *DestBB) {
// Anything that branched to PredBB now branches to DestBB.
PredBB->replaceAllUsesWith(DestBB);
+ if (P) {
+ ProfileInfo *PI = P->getAnalysisIfAvailable<ProfileInfo>();
+ if (PI) {
+ PI->replaceAllUses(PredBB, DestBB);
+ PI->removeEdge(ProfileInfo::getEdge(PredBB, DestBB));
+ }
+ }
// Nuke BB.
PredBB->eraseFromParent();
}
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/LoopSimplify.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/LoopSimplify.cpp
index c981a01..c22708a 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/LoopSimplify.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/LoopSimplify.cpp
@@ -41,7 +41,8 @@
#include "llvm/Type.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/Dominators.h"
-#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/LoopPass.h"
+#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Support/CFG.h"
@@ -56,43 +57,41 @@ STATISTIC(NumInserted, "Number of pre-header or exit blocks inserted");
STATISTIC(NumNested , "Number of nested loops split out");
namespace {
- struct VISIBILITY_HIDDEN LoopSimplify : public FunctionPass {
+ struct VISIBILITY_HIDDEN LoopSimplify : public LoopPass {
static char ID; // Pass identification, replacement for typeid
- LoopSimplify() : FunctionPass(&ID) {}
+ LoopSimplify() : LoopPass(&ID) {}
// AA - If we have an alias analysis object to update, this is it, otherwise
// this is null.
AliasAnalysis *AA;
LoopInfo *LI;
DominatorTree *DT;
- virtual bool runOnFunction(Function &F);
+ Loop *L;
+ virtual bool runOnLoop(Loop *L, LPPassManager &LPM);
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
// We need loop information to identify the loops...
- AU.addRequired<LoopInfo>();
- AU.addRequired<DominatorTree>();
+ AU.addRequiredTransitive<LoopInfo>();
+ AU.addRequiredTransitive<DominatorTree>();
AU.addPreserved<LoopInfo>();
AU.addPreserved<DominatorTree>();
AU.addPreserved<DominanceFrontier>();
AU.addPreserved<AliasAnalysis>();
+ AU.addPreserved<ScalarEvolution>();
AU.addPreservedID(BreakCriticalEdgesID); // No critical edges added.
}
/// verifyAnalysis() - Verify loop nest.
void verifyAnalysis() const {
-#ifndef NDEBUG
- LoopInfo *NLI = &getAnalysis<LoopInfo>();
- for (LoopInfo::iterator I = NLI->begin(), E = NLI->end(); I != E; ++I)
- (*I)->verifyLoop();
-#endif
+ assert(L->isLoopSimplifyForm() && "LoopSimplify form not preserved!");
}
private:
- bool ProcessLoop(Loop *L);
+ bool ProcessLoop(Loop *L, LPPassManager &LPM);
BasicBlock *RewriteLoopExitBlock(Loop *L, BasicBlock *Exit);
BasicBlock *InsertPreheaderForLoop(Loop *L);
- Loop *SeparateNestedLoop(Loop *L);
+ Loop *SeparateNestedLoop(Loop *L, LPPassManager &LPM);
void InsertUniqueBackedgeBlock(Loop *L, BasicBlock *Preheader);
void PlaceSplitBlockCarefully(BasicBlock *NewBB,
SmallVectorImpl<BasicBlock*> &SplitPreds,
@@ -106,73 +105,19 @@ X("loopsimplify", "Canonicalize natural loops", true);
// Publically exposed interface to pass...
const PassInfo *const llvm::LoopSimplifyID = &X;
-FunctionPass *llvm::createLoopSimplifyPass() { return new LoopSimplify(); }
+Pass *llvm::createLoopSimplifyPass() { return new LoopSimplify(); }
/// runOnFunction - Run down all loops in the CFG (recursively, but we could do
/// it in any convenient order) inserting preheaders...
///
-bool LoopSimplify::runOnFunction(Function &F) {
+bool LoopSimplify::runOnLoop(Loop *l, LPPassManager &LPM) {
+ L = l;
bool Changed = false;
LI = &getAnalysis<LoopInfo>();
AA = getAnalysisIfAvailable<AliasAnalysis>();
DT = &getAnalysis<DominatorTree>();
- // Check to see that no blocks (other than the header) in loops have
- // predecessors that are not in loops. This is not valid for natural loops,
- // but can occur if the blocks are unreachable. Since they are unreachable we
- // can just shamelessly destroy their terminators to make them not branch into
- // the loop!
- for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
- // This case can only occur for unreachable blocks. Blocks that are
- // unreachable can't be in loops, so filter those blocks out.
- if (LI->getLoopFor(BB)) continue;
-
- bool BlockUnreachable = false;
- TerminatorInst *TI = BB->getTerminator();
-
- // Check to see if any successors of this block are non-loop-header loops
- // that are not the header.
- for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) {
- // If this successor is not in a loop, BB is clearly ok.
- Loop *L = LI->getLoopFor(TI->getSuccessor(i));
- if (!L) continue;
-
- // If the succ is the loop header, and if L is a top-level loop, then this
- // is an entrance into a loop through the header, which is also ok.
- if (L->getHeader() == TI->getSuccessor(i) && L->getParentLoop() == 0)
- continue;
-
- // Otherwise, this is an entrance into a loop from some place invalid.
- // Either the loop structure is invalid and this is not a natural loop (in
- // which case the compiler is buggy somewhere else) or BB is unreachable.
- BlockUnreachable = true;
- break;
- }
-
- // If this block is ok, check the next one.
- if (!BlockUnreachable) continue;
-
- // Otherwise, this block is dead. To clean up the CFG and to allow later
- // loop transformations to ignore this case, we delete the edges into the
- // loop by replacing the terminator.
-
- // Remove PHI entries from the successors.
- for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i)
- TI->getSuccessor(i)->removePredecessor(BB);
-
- // Add a new unreachable instruction before the old terminator.
- new UnreachableInst(TI->getContext(), TI);
-
- // Delete the dead terminator.
- if (AA) AA->deleteValue(TI);
- if (!TI->use_empty())
- TI->replaceAllUsesWith(UndefValue::get(TI->getType()));
- TI->eraseFromParent();
- Changed |= true;
- }
-
- for (LoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I)
- Changed |= ProcessLoop(*I);
+ Changed |= ProcessLoop(L, LPM);
return Changed;
}
@@ -180,17 +125,37 @@ bool LoopSimplify::runOnFunction(Function &F) {
/// ProcessLoop - Walk the loop structure in depth first order, ensuring that
/// all loops have preheaders.
///
-bool LoopSimplify::ProcessLoop(Loop *L) {
+bool LoopSimplify::ProcessLoop(Loop *L, LPPassManager &LPM) {
bool Changed = false;
ReprocessLoop:
-
- // Canonicalize inner loops before outer loops. Inner loop canonicalization
- // can provide work for the outer loop to canonicalize.
- for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I)
- Changed |= ProcessLoop(*I);
-
- assert(L->getBlocks()[0] == L->getHeader() &&
- "Header isn't first block in loop?");
+
+ // Check to see that no blocks (other than the header) in this loop that has
+ // predecessors that are not in the loop. This is not valid for natural
+ // loops, but can occur if the blocks are unreachable. Since they are
+ // unreachable we can just shamelessly delete those CFG edges!
+ for (Loop::block_iterator BB = L->block_begin(), E = L->block_end();
+ BB != E; ++BB) {
+ if (*BB == L->getHeader()) continue;
+
+ SmallPtrSet<BasicBlock *, 4> BadPreds;
+ for (pred_iterator PI = pred_begin(*BB), PE = pred_end(*BB); PI != PE; ++PI)
+ if (!L->contains(*PI))
+ BadPreds.insert(*PI);
+
+ // Delete each unique out-of-loop (and thus dead) predecessor.
+ for (SmallPtrSet<BasicBlock *, 4>::iterator I = BadPreds.begin(),
+ E = BadPreds.end(); I != E; ++I) {
+ // Inform each successor of each dead pred.
+ for (succ_iterator SI = succ_begin(*I), SE = succ_end(*I); SI != SE; ++SI)
+ (*SI)->removePredecessor(*I);
+ // Zap the dead pred's terminator and replace it with unreachable.
+ TerminatorInst *TI = (*I)->getTerminator();
+ TI->replaceAllUsesWith(UndefValue::get(TI->getType()));
+ (*I)->getTerminator()->eraseFromParent();
+ new UnreachableInst((*I)->getContext(), *I);
+ Changed = true;
+ }
+ }
// Does the loop already have a preheader? If so, don't insert one.
BasicBlock *Preheader = L->getLoopPreheader();
@@ -231,10 +196,9 @@ ReprocessLoop:
// this for loops with a giant number of backedges, just factor them into a
// common backedge instead.
if (NumBackedges < 8) {
- if (Loop *NL = SeparateNestedLoop(L)) {
+ if (SeparateNestedLoop(L, LPM)) {
++NumNested;
// This is a big restructuring change, reprocess the whole loop.
- ProcessLoop(NL);
Changed = true;
// GCC doesn't tail recursion eliminate this.
goto ReprocessLoop;
@@ -255,7 +219,7 @@ ReprocessLoop:
PHINode *PN;
for (BasicBlock::iterator I = L->getHeader()->begin();
(PN = dyn_cast<PHINode>(I++)); )
- if (Value *V = PN->hasConstantValue()) {
+ if (Value *V = PN->hasConstantValue(DT)) {
if (AA) AA->deleteValue(PN);
PN->replaceAllUsesWith(V);
PN->eraseFromParent();
@@ -310,9 +274,10 @@ ReprocessLoop:
DomTreeNode *Node = DT->getNode(ExitingBlock);
const std::vector<DomTreeNodeBase<BasicBlock> *> &Children =
Node->getChildren();
- for (unsigned k = 0, g = Children.size(); k != g; ++k) {
- DT->changeImmediateDominator(Children[k], Node->getIDom());
- if (DF) DF->changeImmediateDominator(Children[k]->getBlock(),
+ while (!Children.empty()) {
+ DomTreeNode *Child = Children.front();
+ DT->changeImmediateDominator(Child, Node->getIDom());
+ if (DF) DF->changeImmediateDominator(Child->getBlock(),
Node->getIDom()->getBlock(),
DT);
}
@@ -346,15 +311,6 @@ BasicBlock *LoopSimplify::InsertPreheaderForLoop(Loop *L) {
BasicBlock *NewBB =
SplitBlockPredecessors(Header, &OutsideBlocks[0], OutsideBlocks.size(),
".preheader", this);
-
-
- //===--------------------------------------------------------------------===//
- // Update analysis results now that we have performed the transformation
- //
-
- // We know that we have loop information to update... update it now.
- if (Loop *Parent = L->getParentLoop())
- Parent->addBasicBlockToLoop(NewBB, LI->getBase());
// Make sure that NewBB is put someplace intelligent, which doesn't mess up
// code layout too horribly.
@@ -377,17 +333,6 @@ BasicBlock *LoopSimplify::RewriteLoopExitBlock(Loop *L, BasicBlock *Exit) {
LoopBlocks.size(), ".loopexit",
this);
- // Update Loop Information - we know that the new block will be in whichever
- // loop the Exit block is in. Note that it may not be in that immediate loop,
- // if the successor is some other loop header. In that case, we continue
- // walking up the loop tree to find a loop that contains both the successor
- // block and the predecessor block.
- Loop *SuccLoop = LI->getLoopFor(Exit);
- while (SuccLoop && !SuccLoop->contains(L->getHeader()))
- SuccLoop = SuccLoop->getParentLoop();
- if (SuccLoop)
- SuccLoop->addBasicBlockToLoop(NewBB, LI->getBase());
-
return NewBB;
}
@@ -417,14 +362,13 @@ static PHINode *FindPHIToPartitionLoops(Loop *L, DominatorTree *DT,
for (BasicBlock::iterator I = L->getHeader()->begin(); isa<PHINode>(I); ) {
PHINode *PN = cast<PHINode>(I);
++I;
- if (Value *V = PN->hasConstantValue())
- if (!isa<Instruction>(V) || DT->dominates(cast<Instruction>(V), PN)) {
- // This is a degenerate PHI already, don't modify it!
- PN->replaceAllUsesWith(V);
- if (AA) AA->deleteValue(PN);
- PN->eraseFromParent();
- continue;
- }
+ if (Value *V = PN->hasConstantValue(DT)) {
+ // This is a degenerate PHI already, don't modify it!
+ PN->replaceAllUsesWith(V);
+ if (AA) AA->deleteValue(PN);
+ PN->eraseFromParent();
+ continue;
+ }
// Scan this PHI node looking for a use of the PHI node by itself.
for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
@@ -491,7 +435,7 @@ void LoopSimplify::PlaceSplitBlockCarefully(BasicBlock *NewBB,
/// If we are able to separate out a loop, return the new outer loop that was
/// created.
///
-Loop *LoopSimplify::SeparateNestedLoop(Loop *L) {
+Loop *LoopSimplify::SeparateNestedLoop(Loop *L, LPPassManager &LPM) {
PHINode *PN = FindPHIToPartitionLoops(L, DT, AA);
if (PN == 0) return 0; // No known way to partition.
@@ -522,17 +466,20 @@ Loop *LoopSimplify::SeparateNestedLoop(Loop *L) {
else
LI->changeTopLevelLoop(L, NewOuter);
- // This block is going to be our new header block: add it to this loop and all
- // parent loops.
- NewOuter->addBasicBlockToLoop(NewBB, LI->getBase());
-
// L is now a subloop of our outer loop.
NewOuter->addChildLoop(L);
+ // Add the new loop to the pass manager queue.
+ LPM.insertLoopIntoQueue(NewOuter);
+
for (Loop::block_iterator I = L->block_begin(), E = L->block_end();
I != E; ++I)
NewOuter->addBlockEntry(*I);
+ // Now reset the header in L, which had been moved by
+ // SplitBlockPredecessors for the outer loop.
+ L->moveToHeader(Header);
+
// Determine which blocks should stay in L and which should be moved out to
// the Outer loop now.
std::set<BasicBlock*> BlocksInL;
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/LowerAllocations.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/LowerAllocations.cpp
index 7276d55..2df953c 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/LowerAllocations.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/LowerAllocations.cpp
@@ -33,13 +33,13 @@ namespace {
/// @free calls.
///
class VISIBILITY_HIDDEN LowerAllocations : public BasicBlockPass {
- Constant *MallocFunc; // Functions in the module we are processing
- Constant *FreeFunc; // Initialized by doInitialization
+ Constant *FreeFunc; // Functions in the module we are processing
+ // Initialized by doInitialization
bool LowerMallocArgToInteger;
public:
static char ID; // Pass ID, replacement for typeid
explicit LowerAllocations(bool LowerToInt = false)
- : BasicBlockPass(&ID), MallocFunc(0), FreeFunc(0),
+ : BasicBlockPass(&ID), FreeFunc(0),
LowerMallocArgToInteger(LowerToInt) {}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
@@ -88,10 +88,6 @@ Pass *llvm::createLowerAllocationsPass(bool LowerMallocArgToInteger) {
//
bool LowerAllocations::doInitialization(Module &M) {
const Type *BPTy = PointerType::getUnqual(Type::getInt8Ty(M.getContext()));
- // Prototype malloc as "char* malloc(...)", because we don't know in
- // doInitialization whether size_t is int or long.
- FunctionType *FT = FunctionType::get(BPTy, true);
- MallocFunc = M.getOrInsertFunction("malloc", FT);
FreeFunc = M.getOrInsertFunction("free" , Type::getVoidTy(M.getContext()),
BPTy, (Type *)0);
return true;
@@ -102,7 +98,7 @@ bool LowerAllocations::doInitialization(Module &M) {
//
bool LowerAllocations::runOnBasicBlock(BasicBlock &BB) {
bool Changed = false;
- assert(MallocFunc && FreeFunc && "Pass not initialized!");
+ assert(FreeFunc && "Pass not initialized!");
BasicBlock::InstListType &BBIL = BB.getInstList();
@@ -112,50 +108,12 @@ bool LowerAllocations::runOnBasicBlock(BasicBlock &BB) {
// Loop over all of the instructions, looking for malloc or free instructions
for (BasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; ++I) {
if (MallocInst *MI = dyn_cast<MallocInst>(I)) {
- const Type *AllocTy = MI->getType()->getElementType();
-
- // malloc(type) becomes i8 *malloc(size)
- Value *MallocArg;
- if (LowerMallocArgToInteger)
- MallocArg = ConstantInt::get(Type::getInt64Ty(BB.getContext()),
- TD.getTypeAllocSize(AllocTy));
- else
- MallocArg = ConstantExpr::getSizeOf(AllocTy);
- MallocArg =
- ConstantExpr::getTruncOrBitCast(cast<Constant>(MallocArg),
- IntPtrTy);
-
- if (MI->isArrayAllocation()) {
- if (isa<ConstantInt>(MallocArg) &&
- cast<ConstantInt>(MallocArg)->isOne()) {
- MallocArg = MI->getOperand(0); // Operand * 1 = Operand
- } else if (Constant *CO = dyn_cast<Constant>(MI->getOperand(0))) {
- CO =
- ConstantExpr::getIntegerCast(CO, IntPtrTy, false /*ZExt*/);
- MallocArg = ConstantExpr::getMul(CO,
- cast<Constant>(MallocArg));
- } else {
- Value *Scale = MI->getOperand(0);
- if (Scale->getType() != IntPtrTy)
- Scale = CastInst::CreateIntegerCast(Scale, IntPtrTy, false /*ZExt*/,
- "", I);
-
- // Multiply it by the array size if necessary...
- MallocArg = BinaryOperator::Create(Instruction::Mul, Scale,
- MallocArg, "", I);
- }
- }
-
- // Create the call to Malloc.
- CallInst *MCall = CallInst::Create(MallocFunc, MallocArg, "", I);
- MCall->setTailCall();
-
- // Create a cast instruction to convert to the right type...
- Value *MCast;
- if (MCall->getType() != Type::getVoidTy(BB.getContext()))
- MCast = new BitCastInst(MCall, MI->getType(), "", I);
- else
- MCast = Constant::getNullValue(MI->getType());
+ Value *ArraySize = MI->getOperand(0);
+ if (ArraySize->getType() != IntPtrTy)
+ ArraySize = CastInst::CreateIntegerCast(ArraySize, IntPtrTy,
+ false /*ZExt*/, "", I);
+ Value *MCast = CallInst::CreateMalloc(I, IntPtrTy,
+ MI->getAllocatedType(), ArraySize);
// Replace all uses of the old malloc inst with the cast inst
MI->replaceAllUsesWith(MCast);
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
index 6a56a8d..9ca06bd 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
@@ -41,7 +41,6 @@ STATISTIC(NumSingleStore, "Number of alloca's promoted with a single store");
STATISTIC(NumDeadAlloca, "Number of dead alloca's removed");
STATISTIC(NumPHIInsert, "Number of PHI nodes inserted");
-// Provide DenseMapInfo for all pointers.
namespace llvm {
template<>
struct DenseMapInfo<std::pair<BasicBlock*, unsigned> > {
@@ -294,10 +293,9 @@ namespace {
// As we scan the uses of the alloca instruction, keep track of stores,
// and decide whether all of the loads and stores to the alloca are within
// the same basic block.
- for (Value::use_iterator U = AI->use_begin(), E = AI->use_end();
- U != E;) {
- Instruction *User = cast<Instruction>(*U);
- ++U;
+ for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end();
+ UI != E;) {
+ Instruction *User = cast<Instruction>(*UI++);
if (BitCastInst *BC = dyn_cast<BitCastInst>(User)) {
// Remove any uses of this alloca in DbgInfoInstrinsics.
assert(BC->hasOneUse() && "Unexpected alloca uses!");
@@ -306,7 +304,8 @@ namespace {
BC->eraseFromParent();
continue;
}
- else if (StoreInst *SI = dyn_cast<StoreInst>(User)) {
+
+ if (StoreInst *SI = dyn_cast<StoreInst>(User)) {
// Remember the basic blocks which define new values for the alloca
DefiningBlocks.push_back(SI->getParent());
AllocaPointerVal = SI->getOperand(0);
@@ -494,17 +493,14 @@ void PromoteMem2Reg::run() {
PHINode *PN = I->second;
// If this PHI node merges one value and/or undefs, get the value.
- if (Value *V = PN->hasConstantValue(true)) {
- if (!isa<Instruction>(V) ||
- properlyDominates(cast<Instruction>(V), PN)) {
- if (AST && isa<PointerType>(PN->getType()))
- AST->deleteValue(PN);
- PN->replaceAllUsesWith(V);
- PN->eraseFromParent();
- NewPhiNodes.erase(I++);
- EliminatedAPHI = true;
- continue;
- }
+ if (Value *V = PN->hasConstantValue(&DT)) {
+ if (AST && isa<PointerType>(PN->getType()))
+ AST->deleteValue(PN);
+ PN->replaceAllUsesWith(V);
+ PN->eraseFromParent();
+ NewPhiNodes.erase(I++);
+ EliminatedAPHI = true;
+ continue;
}
++I;
}
@@ -606,7 +602,9 @@ ComputeLiveInBlocks(AllocaInst *AI, AllocaInfo &Info,
LiveInBlockWorklist.pop_back();
--i, --e;
break;
- } else if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
+ }
+
+ if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
if (LI->getOperand(0) != AI) continue;
// Okay, we found a load before a store to the alloca. It is actually
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/SSI.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/SSI.cpp
index 036dc36..e5a1dd1 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/SSI.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/SSI.cpp
@@ -80,36 +80,43 @@ void SSI::insertSigmaFunctions(SmallVectorImpl<Instruction *> &value) {
if (!needConstruction[i])
continue;
- bool need = false;
for (Value::use_iterator begin = value[i]->use_begin(), end =
value[i]->use_end(); begin != end; ++begin) {
// Test if the Use of the Value is in a comparator
- CmpInst *CI = dyn_cast<CmpInst>(begin);
- if (CI && isUsedInTerminator(CI)) {
- // Basic Block of the Instruction
- BasicBlock *BB = CI->getParent();
- // Last Instruction of the Basic Block
- const TerminatorInst *TI = BB->getTerminator();
-
- for (unsigned j = 0, e = TI->getNumSuccessors(); j < e; ++j) {
- // Next Basic Block
- BasicBlock *BB_next = TI->getSuccessor(j);
- if (BB_next != BB &&
- BB_next->getSinglePredecessor() != NULL &&
- dominateAny(BB_next, value[i])) {
- PHINode *PN = PHINode::Create(
- value[i]->getType(), SSI_SIG, BB_next->begin());
- PN->addIncoming(value[i], BB);
- sigmas.insert(std::make_pair(PN, i));
- created.insert(PN);
- need = true;
- defsites[i].push_back(BB_next);
- ++NumSigmaInserted;
+ if (CmpInst *CI = dyn_cast<CmpInst>(begin)) {
+ // Iterates through all uses of CmpInst
+ for (Value::use_iterator begin_ci = CI->use_begin(), end_ci =
+ CI->use_end(); begin_ci != end_ci; ++begin_ci) {
+ // Test if any use of CmpInst is in a Terminator
+ if (TerminatorInst *TI = dyn_cast<TerminatorInst>(begin_ci)) {
+ insertSigma(TI, value[i], i);
}
}
}
}
- needConstruction[i] = need;
+ }
+}
+
+/// Inserts Sigma Functions in every BasicBlock successor to Terminator
+/// Instruction TI. All inserted Sigma Function are related to Instruction I.
+///
+void SSI::insertSigma(TerminatorInst *TI, Instruction *I, unsigned pos) {
+ // Basic Block of the Terminator Instruction
+ BasicBlock *BB = TI->getParent();
+ for (unsigned i = 0, e = TI->getNumSuccessors(); i < e; ++i) {
+ // Next Basic Block
+ BasicBlock *BB_next = TI->getSuccessor(i);
+ if (BB_next != BB &&
+ BB_next->getSinglePredecessor() != NULL &&
+ dominateAny(BB_next, I)) {
+ PHINode *PN = PHINode::Create(I->getType(), SSI_SIG, BB_next->begin());
+ PN->addIncoming(I, BB);
+ sigmas.insert(std::make_pair(PN, pos));
+ created.insert(PN);
+ needConstruction[pos] = true;
+ defsites[pos].push_back(BB_next);
+ ++NumSigmaInserted;
+ }
}
}
@@ -371,20 +378,6 @@ unsigned SSI::getPositionSigma(PHINode *PN) {
return val->second;
}
-/// Return true if the the Comparison Instruction is an operator
-/// of the Terminator instruction of its Basic Block.
-///
-unsigned SSI::isUsedInTerminator(CmpInst *CI) {
- TerminatorInst *TI = CI->getParent()->getTerminator();
- if (TI->getNumOperands() == 0) {
- return false;
- } else if (CI == TI->getOperand(0)) {
- return true;
- } else {
- return false;
- }
-}
-
/// Initializes
///
void SSI::init(SmallVectorImpl<Instruction *> &value) {
diff --git a/libclamav/c++/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/libclamav/c++/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 0938c44..92b1335 100644
--- a/libclamav/c++/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/libclamav/c++/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -16,7 +16,6 @@
#include "llvm/Constants.h"
#include "llvm/Instructions.h"
#include "llvm/IntrinsicInst.h"
-#include "llvm/LLVMContext.h"
#include "llvm/Type.h"
#include "llvm/DerivedTypes.h"
#include "llvm/GlobalVariable.h"
@@ -911,7 +910,7 @@ HoistTerminator:
return true;
// Okay, it is safe to hoist the terminator.
- Instruction *NT = I1->clone(BB1->getContext());
+ Instruction *NT = I1->clone();
BIParent->getInstList().insert(BI, NT);
if (NT->getType() != Type::getVoidTy(BB1->getContext())) {
I1->replaceAllUsesWith(NT);
@@ -1151,7 +1150,6 @@ static bool BlockIsSimpleEnoughToThreadThrough(BasicBlock *BB) {
/// ultimate destination.
static bool FoldCondBranchOnPHI(BranchInst *BI) {
BasicBlock *BB = BI->getParent();
- LLVMContext &Context = BB->getContext();
PHINode *PN = dyn_cast<PHINode>(BI->getCondition());
// NOTE: we currently cannot transform this case if the PHI node is used
// outside of the block.
@@ -1205,7 +1203,7 @@ static bool FoldCondBranchOnPHI(BranchInst *BI) {
TranslateMap[PN] = PN->getIncomingValueForBlock(PredBB);
} else {
// Clone the instruction.
- Instruction *N = BBI->clone(Context);
+ Instruction *N = BBI->clone();
if (BBI->hasName()) N->setName(BBI->getName()+".c");
// Update operands due to translation.
@@ -1218,7 +1216,7 @@ static bool FoldCondBranchOnPHI(BranchInst *BI) {
}
// Check for trivial simplification.
- if (Constant *C = ConstantFoldInstruction(N, Context)) {
+ if (Constant *C = ConstantFoldInstruction(N, BB->getContext())) {
TranslateMap[BBI] = C;
delete N; // Constant folded away, don't need actual inst
} else {
@@ -1554,7 +1552,7 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI) {
// Clone Cond into the predecessor basic block, and or/and the
// two conditions together.
- Instruction *New = Cond->clone(BB->getContext());
+ Instruction *New = Cond->clone();
PredBlock->getInstList().insert(PBI, New);
New->takeName(Cond);
Cond->setName(New->getName()+".old");
@@ -1814,7 +1812,7 @@ bool llvm::SimplifyCFG(BasicBlock *BB) {
<< "INTO UNCOND BRANCH PRED: " << *Pred);
Instruction *UncondBranch = Pred->getTerminator();
// Clone the return and add it to the end of the predecessor.
- Instruction *NewRet = RI->clone(BB->getContext());
+ Instruction *NewRet = RI->clone();
Pred->getInstList().push_back(NewRet);
BasicBlock::iterator BBI = RI;
diff --git a/libclamav/c++/llvm/lib/VMCore/AsmWriter.cpp b/libclamav/c++/llvm/lib/VMCore/AsmWriter.cpp
index 5062075..34ce7bb 100644
--- a/libclamav/c++/llvm/lib/VMCore/AsmWriter.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/AsmWriter.cpp
@@ -32,6 +32,7 @@
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/CFG.h"
+#include "llvm/Support/Dwarf.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/FormattedStream.h"
@@ -50,15 +51,15 @@ AssemblyAnnotationWriter::~AssemblyAnnotationWriter() {}
static const Module *getModuleFromVal(const Value *V) {
if (const Argument *MA = dyn_cast<Argument>(V))
return MA->getParent() ? MA->getParent()->getParent() : 0;
-
+
if (const BasicBlock *BB = dyn_cast<BasicBlock>(V))
return BB->getParent() ? BB->getParent()->getParent() : 0;
-
+
if (const Instruction *I = dyn_cast<Instruction>(V)) {
const Function *M = I->getParent() ? I->getParent()->getParent() : 0;
return M ? M->getParent() : 0;
}
-
+
if (const GlobalValue *GV = dyn_cast<GlobalValue>(V))
return GV->getParent();
return 0;
@@ -97,7 +98,7 @@ static void PrintLLVMName(raw_ostream &OS, const StringRef &Name,
case LabelPrefix: break;
case LocalPrefix: OS << '%'; break;
}
-
+
// Scan the name to see if it needs quotes first.
bool NeedsQuotes = isdigit(Name[0]);
if (!NeedsQuotes) {
@@ -109,13 +110,13 @@ static void PrintLLVMName(raw_ostream &OS, const StringRef &Name,
}
}
}
-
+
// If we didn't need any quotes, just write out the name in one blast.
if (!NeedsQuotes) {
OS << Name;
return;
}
-
+
// Okay, we need quotes. Output the quotes and escape any scary characters as
// needed.
OS << '"';
@@ -127,7 +128,7 @@ static void PrintLLVMName(raw_ostream &OS, const StringRef &Name,
/// prefixed with % (if the string only contains simple characters) or is
/// surrounded with ""'s (if it has special chars in it). Print it out.
static void PrintLLVMName(raw_ostream &OS, const Value *V) {
- PrintLLVMName(OS, V->getName(),
+ PrintLLVMName(OS, V->getName(),
isa<GlobalValue>(V) ? GlobalPrefix : LocalPrefix);
}
@@ -174,11 +175,11 @@ void TypePrinting::CalcTypeName(const Type *Ty,
return;
}
}
-
+
// Check to see if the Type is already on the stack...
unsigned Slot = 0, CurSize = TypeStack.size();
while (Slot < CurSize && TypeStack[Slot] != Ty) ++Slot; // Scan for type
-
+
// This is another base case for the recursion. In this case, we know
// that we have looped back to a type that we have previously visited.
// Generate the appropriate upreference to handle this.
@@ -186,9 +187,9 @@ void TypePrinting::CalcTypeName(const Type *Ty,
OS << '\\' << unsigned(CurSize-Slot); // Here's the upreference
return;
}
-
+
TypeStack.push_back(Ty); // Recursive case: Add us to the stack..
-
+
switch (Ty->getTypeID()) {
case Type::VoidTyID: OS << "void"; break;
case Type::FloatTyID: OS << "float"; break;
@@ -201,7 +202,7 @@ void TypePrinting::CalcTypeName(const Type *Ty,
case Type::IntegerTyID:
OS << 'i' << cast<IntegerType>(Ty)->getBitWidth();
break;
-
+
case Type::FunctionTyID: {
const FunctionType *FTy = cast<FunctionType>(Ty);
CalcTypeName(FTy->getReturnType(), TypeStack, OS);
@@ -265,7 +266,7 @@ void TypePrinting::CalcTypeName(const Type *Ty,
OS << "<unrecognized-type>";
break;
}
-
+
TypeStack.pop_back(); // Remove self from stack.
}
@@ -283,13 +284,13 @@ void TypePrinting::print(const Type *Ty, raw_ostream &OS,
return;
}
}
-
+
// Otherwise we have a type that has not been named but is a derived type.
// Carefully recurse the type hierarchy to print out any contained symbolic
// names.
SmallVector<const Type *, 16> TypeStack;
std::string TypeName;
-
+
raw_string_ostream TypeOS(TypeName);
CalcTypeName(Ty, TypeStack, TypeOS, IgnoreTopLevelName);
OS << TypeOS.str();
@@ -305,13 +306,13 @@ namespace {
// objects, we keep several helper maps.
DenseSet<const Value*> VisitedConstants;
DenseSet<const Type*> VisitedTypes;
-
+
TypePrinting &TP;
std::vector<const Type*> &NumberedTypes;
public:
TypeFinder(TypePrinting &tp, std::vector<const Type*> &numberedTypes)
: TP(tp), NumberedTypes(numberedTypes) {}
-
+
void Run(const Module &M) {
// Get types from the type symbol table. This gets opaque types referened
// only through derived named types.
@@ -319,7 +320,7 @@ namespace {
for (TypeSymbolTable::const_iterator TI = ST.begin(), E = ST.end();
TI != E; ++TI)
IncorporateType(TI->second);
-
+
// Get types from global variables.
for (Module::const_global_iterator I = M.global_begin(),
E = M.global_end(); I != E; ++I) {
@@ -327,18 +328,18 @@ namespace {
if (I->hasInitializer())
IncorporateValue(I->getInitializer());
}
-
+
// Get types from aliases.
for (Module::const_alias_iterator I = M.alias_begin(),
E = M.alias_end(); I != E; ++I) {
IncorporateType(I->getType());
IncorporateValue(I->getAliasee());
}
-
+
// Get types from functions.
for (Module::const_iterator FI = M.begin(), E = M.end(); FI != E; ++FI) {
IncorporateType(FI->getType());
-
+
for (Function::const_iterator BB = FI->begin(), E = FI->end();
BB != E;++BB)
for (BasicBlock::const_iterator II = BB->begin(),
@@ -352,40 +353,40 @@ namespace {
}
}
}
-
+
private:
void IncorporateType(const Type *Ty) {
// Check to see if we're already visited this type.
if (!VisitedTypes.insert(Ty).second)
return;
-
+
// If this is a structure or opaque type, add a name for the type.
if (((isa<StructType>(Ty) && cast<StructType>(Ty)->getNumElements())
|| isa<OpaqueType>(Ty)) && !TP.hasTypeName(Ty)) {
TP.addTypeName(Ty, "%"+utostr(unsigned(NumberedTypes.size())));
NumberedTypes.push_back(Ty);
}
-
+
// Recursively walk all contained types.
for (Type::subtype_iterator I = Ty->subtype_begin(),
E = Ty->subtype_end(); I != E; ++I)
- IncorporateType(*I);
+ IncorporateType(*I);
}
-
+
/// IncorporateValue - This method is used to walk operand lists finding
/// types hiding in constant expressions and other operands that won't be
/// walked in other ways. GlobalValues, basic blocks, instructions, and
/// inst operands are all explicitly enumerated.
void IncorporateValue(const Value *V) {
if (V == 0 || !isa<Constant>(V) || isa<GlobalValue>(V)) return;
-
+
// Already visited?
if (!VisitedConstants.insert(V).second)
return;
-
+
// Check this type.
IncorporateType(V->getType());
-
+
// Look in operands for types.
const Constant *C = cast<Constant>(V);
for (Constant::const_op_iterator I = C->op_begin(),
@@ -399,18 +400,18 @@ namespace {
/// AddModuleTypesToPrinter - Add all of the symbolic type names for types in
/// the specified module to the TypePrinter and all numbered types to it and the
/// NumberedTypes table.
-static void AddModuleTypesToPrinter(TypePrinting &TP,
+static void AddModuleTypesToPrinter(TypePrinting &TP,
std::vector<const Type*> &NumberedTypes,
const Module *M) {
if (M == 0) return;
-
+
// If the module has a symbol table, take all global types and stuff their
// names into the TypeNames map.
const TypeSymbolTable &ST = M->getTypeSymbolTable();
for (TypeSymbolTable::const_iterator TI = ST.begin(), E = ST.end();
TI != E; ++TI) {
const Type *Ty = cast<Type>(TI->second);
-
+
// As a heuristic, don't insert pointer to primitive types, because
// they are used too often to have a single useful name.
if (const PointerType *PTy = dyn_cast<PointerType>(Ty)) {
@@ -419,11 +420,11 @@ static void AddModuleTypesToPrinter(TypePrinting &TP,
!isa<OpaqueType>(PETy))
continue;
}
-
+
// Likewise don't insert primitives either.
if (Ty->isInteger() || Ty->isPrimitiveType())
continue;
-
+
// Get the name as a string and insert it into TypeNames.
std::string NameStr;
raw_string_ostream NameROS(NameStr);
@@ -432,7 +433,7 @@ static void AddModuleTypesToPrinter(TypePrinting &TP,
NameOS.flush();
TP.addTypeName(Ty, NameStr);
}
-
+
// Walk the entire module to find references to unnamed structure and opaque
// types. This is required for correctness by opaque types (because multiple
// uses of an unnamed opaque type needs to be referred to by the same ID) and
@@ -464,15 +465,15 @@ class SlotTracker {
public:
/// ValueMap - A mapping of Values to slot numbers.
typedef DenseMap<const Value*, unsigned> ValueMap;
-
-private:
+
+private:
/// TheModule - The module for which we are holding slot numbers.
const Module* TheModule;
-
+
/// TheFunction - The function for which we are holding slot numbers.
const Function* TheFunction;
bool FunctionProcessed;
-
+
/// TheMDNode - The MDNode for which we are holding slot numbers.
const MDNode *TheMDNode;
@@ -482,11 +483,11 @@ private:
/// mMap - The TypePlanes map for the module level data.
ValueMap mMap;
unsigned mNext;
-
+
/// fMap - The TypePlanes map for the function level data.
ValueMap fMap;
unsigned fNext;
-
+
/// mdnMap - Map for MDNodes.
ValueMap mdnMap;
unsigned mdnNext;
@@ -561,22 +562,22 @@ private:
static SlotTracker *createSlotTracker(const Value *V) {
if (const Argument *FA = dyn_cast<Argument>(V))
return new SlotTracker(FA->getParent());
-
+
if (const Instruction *I = dyn_cast<Instruction>(V))
return new SlotTracker(I->getParent()->getParent());
-
+
if (const BasicBlock *BB = dyn_cast<BasicBlock>(V))
return new SlotTracker(BB->getParent());
-
+
if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(V))
return new SlotTracker(GV->getParent());
-
+
if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(V))
- return new SlotTracker(GA->getParent());
-
+ return new SlotTracker(GA->getParent());
+
if (const Function *Func = dyn_cast<Function>(V))
return new SlotTracker(Func);
-
+
return 0;
}
@@ -617,7 +618,7 @@ inline void SlotTracker::initialize() {
processModule();
TheModule = 0; ///< Prevent re-processing next time we're called.
}
-
+
if (TheFunction && !FunctionProcessed)
processFunction();
@@ -632,20 +633,20 @@ inline void SlotTracker::initialize() {
// variable initializers and create slots for them.
void SlotTracker::processModule() {
ST_DEBUG("begin processModule!\n");
-
+
// Add all of the unnamed global variables to the value table.
for (Module::const_global_iterator I = TheModule->global_begin(),
E = TheModule->global_end(); I != E; ++I) {
- if (!I->hasName())
+ if (!I->hasName())
CreateModuleSlot(I);
if (I->hasInitializer()) {
- if (MDNode *N = dyn_cast<MDNode>(I->getInitializer()))
+ if (MDNode *N = dyn_cast<MDNode>(I->getInitializer()))
CreateMetadataSlot(N);
}
}
-
+
// Add metadata used by named metadata.
- for (Module::const_named_metadata_iterator
+ for (Module::const_named_metadata_iterator
I = TheModule->named_metadata_begin(),
E = TheModule->named_metadata_end(); I != E; ++I) {
const NamedMDNode *NMD = I;
@@ -661,7 +662,7 @@ void SlotTracker::processModule() {
I != E; ++I)
if (!I->hasName())
CreateModuleSlot(I);
-
+
ST_DEBUG("end processModule!\n");
}
@@ -669,33 +670,43 @@ void SlotTracker::processModule() {
void SlotTracker::processFunction() {
ST_DEBUG("begin processFunction!\n");
fNext = 0;
-
+
// Add all the function arguments with no names.
for(Function::const_arg_iterator AI = TheFunction->arg_begin(),
AE = TheFunction->arg_end(); AI != AE; ++AI)
if (!AI->hasName())
CreateFunctionSlot(AI);
-
+
ST_DEBUG("Inserting Instructions:\n");
-
+
+ MetadataContext &TheMetadata = TheFunction->getContext().getMetadata();
+
// Add all of the basic blocks and instructions with no names.
for (Function::const_iterator BB = TheFunction->begin(),
E = TheFunction->end(); BB != E; ++BB) {
if (!BB->hasName())
CreateFunctionSlot(BB);
- for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E;
+ for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E;
++I) {
if (I->getType() != Type::getVoidTy(TheFunction->getContext()) &&
!I->hasName())
CreateFunctionSlot(I);
- for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (MDNode *N = dyn_cast_or_null<MDNode>(I->getOperand(i)))
CreateMetadataSlot(N);
+
+ // Process metadata attached with this instruction.
+ const MetadataContext::MDMapTy *MDs = TheMetadata.getMDs(I);
+ if (MDs)
+ for (MetadataContext::MDMapTy::const_iterator MI = MDs->begin(),
+ ME = MDs->end(); MI != ME; ++MI)
+ if (MDNode *MDN = dyn_cast_or_null<MDNode>(MI->second))
+ CreateMetadataSlot(MDN);
}
}
-
+
FunctionProcessed = true;
-
+
ST_DEBUG("end processFunction!\n");
}
@@ -736,7 +747,7 @@ void SlotTracker::purgeFunction() {
int SlotTracker::getGlobalSlot(const GlobalValue *V) {
// Check for uninitialized state and do lazy initialization.
initialize();
-
+
// Find the type plane in the module map
ValueMap::iterator MI = mMap.find(V);
return MI == mMap.end() ? -1 : (int)MI->second;
@@ -746,7 +757,7 @@ int SlotTracker::getGlobalSlot(const GlobalValue *V) {
int SlotTracker::getMetadataSlot(const MDNode *N) {
// Check for uninitialized state and do lazy initialization.
initialize();
-
+
// Find the type plane in the module map
ValueMap::iterator MI = mdnMap.find(N);
return MI == mdnMap.end() ? -1 : (int)MI->second;
@@ -756,10 +767,10 @@ int SlotTracker::getMetadataSlot(const MDNode *N) {
/// getLocalSlot - Get the slot number for a value that is local to a function.
int SlotTracker::getLocalSlot(const Value *V) {
assert(!isa<Constant>(V) && "Can't get a constant or global slot with this!");
-
+
// Check for uninitialized state and do lazy initialization.
initialize();
-
+
ValueMap::iterator FI = fMap.find(V);
return FI == fMap.end() ? -1 : (int)FI->second;
}
@@ -768,13 +779,13 @@ int SlotTracker::getLocalSlot(const Value *V) {
/// CreateModuleSlot - Insert the specified GlobalValue* into the slot table.
void SlotTracker::CreateModuleSlot(const GlobalValue *V) {
assert(V && "Can't insert a null Value into SlotTracker!");
- assert(V->getType() != Type::getVoidTy(V->getContext()) &&
+ assert(V->getType() != Type::getVoidTy(V->getContext()) &&
"Doesn't need a slot!");
assert(!V->hasName() && "Doesn't need a slot!");
-
+
unsigned DestSlot = mNext++;
mMap[V] = DestSlot;
-
+
ST_DEBUG(" Inserting value [" << V->getType() << "] = " << V << " slot=" <<
DestSlot << " [");
// G = Global, F = Function, A = Alias, o = other
@@ -785,21 +796,21 @@ void SlotTracker::CreateModuleSlot(const GlobalValue *V) {
/// CreateSlot - Create a new slot for the specified value if it has no name.
void SlotTracker::CreateFunctionSlot(const Value *V) {
- assert(V->getType() != Type::getVoidTy(TheFunction->getContext()) &&
+ assert(V->getType() != Type::getVoidTy(TheFunction->getContext()) &&
!V->hasName() && "Doesn't need a slot!");
-
+
unsigned DestSlot = fNext++;
fMap[V] = DestSlot;
-
+
// G = Global, F = Function, o = other
ST_DEBUG(" Inserting value [" << V->getType() << "] = " << V << " slot=" <<
DestSlot << " [o]\n");
-}
+}
/// CreateModuleSlot - Insert the specified MDNode* into the slot table.
void SlotTracker::CreateMetadataSlot(const MDNode *N) {
assert(N && "Can't insert a null Value into SlotTracker!");
-
+
ValueMap::iterator I = mdnMap.find(N);
if (I != mdnMap.end())
return;
@@ -807,11 +818,11 @@ void SlotTracker::CreateMetadataSlot(const MDNode *N) {
unsigned DestSlot = mdnNext++;
mdnMap[N] = DestSlot;
- for (MDNode::const_elem_iterator MDI = N->elem_begin(),
+ for (MDNode::const_elem_iterator MDI = N->elem_begin(),
MDE = N->elem_end(); MDI != MDE; ++MDI) {
const Value *TV = *MDI;
if (TV)
- if (const MDNode *N2 = dyn_cast<MDNode>(TV))
+ if (const MDNode *N2 = dyn_cast<MDNode>(TV))
CreateMetadataSlot(N2);
}
}
@@ -859,19 +870,43 @@ static const char *getPredicateText(unsigned predicate) {
return pred;
}
+static void WriteMDNodeComment(const MDNode *Node,
+ formatted_raw_ostream &Out) {
+ if (Node->getNumElements() < 1)
+ return;
+ ConstantInt *CI = dyn_cast_or_null<ConstantInt>(Node->getElement(0));
+ if (!CI) return;
+ unsigned Val = CI->getZExtValue();
+ unsigned Tag = Val & ~LLVMDebugVersionMask;
+ if (Val >= LLVMDebugVersion) {
+ if (Tag == dwarf::DW_TAG_auto_variable)
+ Out << "; [ DW_TAG_auto_variable ]";
+ else if (Tag == dwarf::DW_TAG_arg_variable)
+ Out << "; [ DW_TAG_arg_variable ]";
+ else if (Tag == dwarf::DW_TAG_return_variable)
+ Out << "; [ DW_TAG_return_variable ]";
+ else if (Tag == dwarf::DW_TAG_vector_type)
+ Out << "; [ DW_TAG_vector_type ]";
+ else if (Tag == dwarf::DW_TAG_user_base)
+ Out << "; [ DW_TAG_user_base ]";
+ else
+ Out << "; [" << dwarf::TagString(Tag) << " ]";
+ }
+}
+
static void WriteMDNodes(formatted_raw_ostream &Out, TypePrinting &TypePrinter,
SlotTracker &Machine) {
SmallVector<const MDNode *, 16> Nodes;
Nodes.resize(Machine.mdnSize());
- for (SlotTracker::ValueMap::iterator I =
- Machine.mdnBegin(), E = Machine.mdnEnd(); I != E; ++I)
+ for (SlotTracker::ValueMap::iterator I =
+ Machine.mdnBegin(), E = Machine.mdnEnd(); I != E; ++I)
Nodes[I->second] = cast<MDNode>(I->first);
for (unsigned i = 0, e = Nodes.size(); i != e; ++i) {
Out << '!' << i << " = metadata ";
const MDNode *Node = Nodes[i];
Out << "!{";
- for (MDNode::const_elem_iterator NI = Node->elem_begin(),
+ for (MDNode::const_elem_iterator NI = Node->elem_begin(),
NE = Node->elem_end(); NI != NE;) {
const Value *V = *NI;
if (!V)
@@ -888,7 +923,10 @@ static void WriteMDNodes(formatted_raw_ostream &Out, TypePrinting &TypePrinter,
if (++NI != NE)
Out << ", ";
}
- Out << "}\n";
+
+ Out << "}";
+ WriteMDNodeComment(Node, Out);
+ Out << "\n";
}
}
@@ -918,7 +956,7 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
Out << CI->getValue();
return;
}
-
+
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
if (&CFP->getValueAPF().getSemantics() == &APFloat::IEEEdouble ||
&CFP->getValueAPF().getSemantics() == &APFloat::IEEEsingle) {
@@ -956,14 +994,14 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
APFloat apf = CFP->getValueAPF();
// Floats are represented in ASCII IR as double, convert.
if (!isDouble)
- apf.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
+ apf.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
&ignored);
- Out << "0x" <<
- utohex_buffer(uint64_t(apf.bitcastToAPInt().getZExtValue()),
+ Out << "0x" <<
+ utohex_buffer(uint64_t(apf.bitcastToAPInt().getZExtValue()),
Buffer+40);
return;
}
-
+
// Some form of long double. These appear as a magic letter identifying
// the type, then a fixed number of hex digits.
Out << "0x";
@@ -1016,12 +1054,12 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
}
return;
}
-
+
if (isa<ConstantAggregateZero>(CV)) {
Out << "zeroinitializer";
return;
}
-
+
if (const ConstantArray *CA = dyn_cast<ConstantArray>(CV)) {
// As a special case, print the array as a string if it is an array of
// i8 with ConstantInt values.
@@ -1049,7 +1087,7 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
}
return;
}
-
+
if (const ConstantStruct *CS = dyn_cast<ConstantStruct>(CV)) {
if (CS->getType()->isPacked())
Out << '<';
@@ -1071,13 +1109,13 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
}
Out << ' ';
}
-
+
Out << '}';
if (CS->getType()->isPacked())
Out << '>';
return;
}
-
+
if (const ConstantVector *CP = dyn_cast<ConstantVector>(CV)) {
const Type *ETy = CP->getType()->getElementType();
assert(CP->getNumOperands() > 0 &&
@@ -1095,17 +1133,17 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
Out << '>';
return;
}
-
+
if (isa<ConstantPointerNull>(CV)) {
Out << "null";
return;
}
-
+
if (isa<UndefValue>(CV)) {
Out << "undef";
return;
}
-
+
if (const MDNode *Node = dyn_cast<MDNode>(CV)) {
Out << "!" << Machine->getMetadataSlot(Node);
return;
@@ -1140,7 +1178,7 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
Out << ')';
return;
}
-
+
Out << "<placeholder or erroneous Constant>";
}
@@ -1156,14 +1194,14 @@ static void WriteAsOperandInternal(raw_ostream &Out, const Value *V,
PrintLLVMName(Out, V);
return;
}
-
+
const Constant *CV = dyn_cast<Constant>(V);
if (CV && !isa<GlobalValue>(CV)) {
assert(TypePrinter && "Constants require TypePrinting!");
WriteConstantInt(Out, CV, *TypePrinter, Machine);
return;
}
-
+
if (const InlineAsm *IA = dyn_cast<InlineAsm>(V)) {
Out << "asm ";
if (IA->hasSideEffects())
@@ -1188,6 +1226,11 @@ static void WriteAsOperandInternal(raw_ostream &Out, const Value *V,
return;
}
+ if (V->getValueID() == Value::PseudoSourceValueVal) {
+ V->print(Out);
+ return;
+ }
+
char Prefix = '%';
int Slot;
if (Machine) {
@@ -1211,7 +1254,7 @@ static void WriteAsOperandInternal(raw_ostream &Out, const Value *V,
Slot = -1;
}
}
-
+
if (Slot != -1)
Out << Prefix << Slot;
else
@@ -1251,20 +1294,26 @@ class AssemblyWriter {
TypePrinting TypePrinter;
AssemblyAnnotationWriter *AnnotationWriter;
std::vector<const Type*> NumberedTypes;
+ DenseMap<unsigned, const char *> MDNames;
- // Each MDNode is assigned unique MetadataIDNo.
- std::map<const MDNode *, unsigned> MDNodes;
- unsigned MetadataIDNo;
public:
inline AssemblyWriter(formatted_raw_ostream &o, SlotTracker &Mac,
const Module *M,
AssemblyAnnotationWriter *AAW)
- : Out(o), Machine(Mac), TheModule(M), AnnotationWriter(AAW), MetadataIDNo(0) {
+ : Out(o), Machine(Mac), TheModule(M), AnnotationWriter(AAW) {
AddModuleTypesToPrinter(TypePrinter, NumberedTypes, M);
+ // FIXME: Provide MDPrinter
+ MetadataContext &TheMetadata = M->getContext().getMetadata();
+ const StringMap<unsigned> *Names = TheMetadata.getHandlerNames();
+ for (StringMapConstIterator<unsigned> I = Names->begin(),
+ E = Names->end(); I != E; ++I) {
+ const StringMapEntry<unsigned> &Entry = *I;
+ MDNames[I->second] = Entry.getKeyData();
+ }
}
void write(const Module *M) { printModule(M); }
-
+
void write(const GlobalValue *G) {
if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(G))
printGlobal(GV);
@@ -1275,15 +1324,13 @@ public:
else
llvm_unreachable("Unknown global");
}
-
+
void write(const BasicBlock *BB) { printBasicBlock(BB); }
void write(const Instruction *I) { printInstruction(*I); }
void writeOperand(const Value *Op, bool PrintType);
void writeParamOperand(const Value *Operand, Attributes Attrs);
- const Module* getModule() { return TheModule; }
-
private:
void printModule(const Module *M);
void printTypeSymbolTable(const TypeSymbolTable &ST);
@@ -1313,7 +1360,7 @@ void AssemblyWriter::writeOperand(const Value *Operand, bool PrintType) {
}
}
-void AssemblyWriter::writeParamOperand(const Value *Operand,
+void AssemblyWriter::writeParamOperand(const Value *Operand,
Attributes Attrs) {
if (Operand == 0) {
Out << "<null operand!>";
@@ -1361,7 +1408,7 @@ void AssemblyWriter::printModule(const Module *M) {
PrintEscapedString(std::string(Asm.begin()+CurPos, Asm.end()), Out);
Out << "\"\n";
}
-
+
// Loop over the dependent libraries and emit them.
Module::lib_iterator LI = M->lib_begin();
Module::lib_iterator LE = M->lib_end();
@@ -1386,7 +1433,7 @@ void AssemblyWriter::printModule(const Module *M) {
for (Module::const_global_iterator I = M->global_begin(), E = M->global_end();
I != E; ++I)
printGlobal(I);
-
+
// Output all aliases.
if (!M->alias_empty()) Out << "\n";
for (Module::const_alias_iterator I = M->alias_begin(), E = M->alias_end();
@@ -1457,7 +1504,7 @@ void AssemblyWriter::printGlobal(const GlobalVariable *GV) {
if (!GV->hasInitializer() && GV->hasExternalLinkage())
Out << "external ";
-
+
PrintLinkage(GV->getLinkage(), Out);
PrintVisibility(GV->getVisibility(), Out);
@@ -1471,7 +1518,7 @@ void AssemblyWriter::printGlobal(const GlobalVariable *GV) {
Out << ' ';
writeOperand(GV->getInitializer(), false);
}
-
+
if (GV->hasSection())
Out << ", section \"" << GV->getSection() << '"';
if (GV->getAlignment())
@@ -1494,9 +1541,9 @@ void AssemblyWriter::printAlias(const GlobalAlias *GA) {
Out << "alias ";
PrintLinkage(GA->getLinkage(), Out);
-
+
const Constant *Aliasee = GA->getAliasee();
-
+
if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(Aliasee)) {
TypePrinter.print(GV->getType(), Out);
Out << ' ';
@@ -1518,7 +1565,7 @@ void AssemblyWriter::printAlias(const GlobalAlias *GA) {
"Unsupported aliasee");
writeOperand(CE, false);
}
-
+
printInfoComment(*GA);
Out << '\n';
}
@@ -1527,13 +1574,13 @@ void AssemblyWriter::printTypeSymbolTable(const TypeSymbolTable &ST) {
// Emit all numbered types.
for (unsigned i = 0, e = NumberedTypes.size(); i != e; ++i) {
Out << '%' << i << " = type ";
-
+
// Make sure we print out at least one level of the type structure, so
// that we do not get %2 = type %2
TypePrinter.printAtLeastOneLevel(NumberedTypes[i], Out);
Out << '\n';
}
-
+
// Print the named types.
for (TypeSymbolTable::const_iterator TI = ST.begin(), TE = ST.end();
TI != TE; ++TI) {
@@ -1559,7 +1606,7 @@ void AssemblyWriter::printFunction(const Function *F) {
Out << "declare ";
else
Out << "define ";
-
+
PrintLinkage(F->getLinkage(), Out);
PrintVisibility(F->getVisibility(), Out);
@@ -1604,10 +1651,10 @@ void AssemblyWriter::printFunction(const Function *F) {
for (unsigned i = 0, e = FT->getNumParams(); i != e; ++i) {
// Insert commas as we go... the first arg doesn't get a comma
if (i) Out << ", ";
-
+
// Output type...
TypePrinter.print(FT->getParamType(i), Out);
-
+
Attributes ArgAttrs = Attrs.getParamAttributes(i+1);
if (ArgAttrs != Attribute::None)
Out << ' ' << Attribute::getAsString(ArgAttrs);
@@ -1647,7 +1694,7 @@ void AssemblyWriter::printFunction(const Function *F) {
/// printArgument - This member is called for every argument that is passed into
/// the function. Simply print it out
///
-void AssemblyWriter::printArgument(const Argument *Arg,
+void AssemblyWriter::printArgument(const Argument *Arg,
Attributes Attrs) {
// Output type...
TypePrinter.print(Arg->getType(), Out);
@@ -1687,7 +1734,7 @@ void AssemblyWriter::printBasicBlock(const BasicBlock *BB) {
Out.PadToColumn(50);
Out << ";";
pred_const_iterator PI = pred_begin(BB), PE = pred_end(BB);
-
+
if (PI == PE) {
Out << " No predecessors!";
} else {
@@ -1973,7 +2020,7 @@ void AssemblyWriter::printInstruction(const Instruction &I) {
writeOperand(I.getOperand(i), PrintAllTypes);
}
}
-
+
// Print post operand alignment for load/store
if (isa<LoadInst>(I) && cast<LoadInst>(I).getAlignment()) {
Out << ", align " << cast<LoadInst>(I).getAlignment();
@@ -1981,6 +2028,16 @@ void AssemblyWriter::printInstruction(const Instruction &I) {
Out << ", align " << cast<StoreInst>(I).getAlignment();
}
+ // Print Metadata info
+ MetadataContext &TheMetadata = I.getContext().getMetadata();
+ const MetadataContext::MDMapTy *MDMap = TheMetadata.getMDs(&I);
+ if (MDMap)
+ for (MetadataContext::MDMapTy::const_iterator MI = MDMap->begin(),
+ ME = MDMap->end(); MI != ME; ++MI)
+ if (const MDNode *MD = dyn_cast_or_null<MDNode>(MI->second))
+ Out << ", !" << MDNames[MI->first]
+ << " !" << Machine.getMetadataSlot(MD);
+
printInfoComment(I);
}
@@ -2046,7 +2103,7 @@ void Value::print(raw_ostream &ROS, AssemblyAnnotationWriter *AAW) const {
MDNode *MD = dyn_cast_or_null<MDNode>(N->getElement(i));
if (MD)
OS << '!' << SlotTable.getMetadataSlot(MD);
- else
+ else
OS << "null";
}
OS << "}\n";
@@ -2062,10 +2119,17 @@ void Value::print(raw_ostream &ROS, AssemblyAnnotationWriter *AAW) const {
} else if (isa<InlineAsm>(this)) {
WriteAsOperand(OS, this, true, 0);
} else {
- llvm_unreachable("Unknown value to print out!");
+ // Otherwise we don't know what it is. Call the virtual function to
+ // allow a subclass to print itself.
+ printCustom(OS);
}
}
+// Value::printCustom - subclasses should override this to implement printing.
+void Value::printCustom(raw_ostream &OS) const {
+ llvm_unreachable("Unknown value to print out!");
+}
+
// Value::dump - allow easy printing of Values from the debugger.
void Value::dump() const { print(errs()); errs() << '\n'; }
diff --git a/libclamav/c++/llvm/lib/VMCore/ConstantFold.cpp b/libclamav/c++/llvm/lib/VMCore/ConstantFold.cpp
index 701a195..5411549 100644
--- a/libclamav/c++/llvm/lib/VMCore/ConstantFold.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/ConstantFold.cpp
@@ -12,9 +12,8 @@
// ConstantExpr::get* methods to automatically fold constants when possible.
//
// The current constant folding implementation is implemented in two pieces: the
-// template-based folder for simple primitive constants like ConstantInt, and
-// the special case hackery that we use to symbolically evaluate expressions
-// that use ConstantExprs.
+// pieces that don't need TargetData, and the pieces that do. This is to avoid
+// a dependence in VMCore on Target.
//
//===----------------------------------------------------------------------===//
@@ -24,6 +23,7 @@
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/GlobalAlias.h"
+#include "llvm/GlobalVariable.h"
#include "llvm/LLVMContext.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Compiler.h"
@@ -73,7 +73,7 @@ static Constant *BitCastConstantVector(LLVMContext &Context, ConstantVector *CV,
static unsigned
foldConstantCastPair(
unsigned opc, ///< opcode of the second cast constant expression
- const ConstantExpr*Op, ///< the first cast constant expression
+ ConstantExpr *Op, ///< the first cast constant expression
const Type *DstTy ///< desintation type of the first cast
) {
assert(Op && Op->isCast() && "Can't fold cast of cast without a cast!");
@@ -156,7 +156,7 @@ static Constant *FoldBitCast(LLVMContext &Context,
return ConstantPointerNull::get(cast<PointerType>(DestTy));
// Handle integral constant input.
- if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
if (DestTy->isInteger())
// Integral -> Integral. This is a no-op because the bit widths must
// be the same. Consequently, we just fold to V.
@@ -171,7 +171,7 @@ static Constant *FoldBitCast(LLVMContext &Context,
}
// Handle ConstantFP input.
- if (const ConstantFP *FP = dyn_cast<ConstantFP>(V))
+ if (ConstantFP *FP = dyn_cast<ConstantFP>(V))
// FP -> Integral.
return ConstantInt::get(Context, FP->getValueAPF().bitcastToAPInt());
@@ -180,7 +180,7 @@ static Constant *FoldBitCast(LLVMContext &Context,
Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context,
- unsigned opc, const Constant *V,
+ unsigned opc, Constant *V,
const Type *DestTy) {
if (isa<UndefValue>(V)) {
// zext(undef) = 0, because the top bits will be zero.
@@ -197,7 +197,7 @@ Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context,
// If the cast operand is a constant expression, there's a few things we can
// do to try to simplify it.
- if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
+ if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
if (CE->isCast()) {
// Try hard to fold cast of cast because they are often eliminable.
if (unsigned newOpc = foldConstantCastPair(opc, CE, DestTy))
@@ -220,7 +220,7 @@ Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context,
// If the cast operand is a constant vector, perform the cast by
// operating on each element. In the cast of bitcasts, the element
// count may be mismatched; don't attempt to handle that here.
- if (const ConstantVector *CV = dyn_cast<ConstantVector>(V))
+ if (ConstantVector *CV = dyn_cast<ConstantVector>(V))
if (isa<VectorType>(DestTy) &&
cast<VectorType>(DestTy)->getNumElements() ==
CV->getType()->getNumElements()) {
@@ -238,7 +238,7 @@ Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context,
switch (opc) {
case Instruction::FPTrunc:
case Instruction::FPExt:
- if (const ConstantFP *FPC = dyn_cast<ConstantFP>(V)) {
+ if (ConstantFP *FPC = dyn_cast<ConstantFP>(V)) {
bool ignored;
APFloat Val = FPC->getValueAPF();
Val.convert(DestTy == Type::getFloatTy(Context) ? APFloat::IEEEsingle :
@@ -252,7 +252,7 @@ Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context,
return 0; // Can't fold.
case Instruction::FPToUI:
case Instruction::FPToSI:
- if (const ConstantFP *FPC = dyn_cast<ConstantFP>(V)) {
+ if (ConstantFP *FPC = dyn_cast<ConstantFP>(V)) {
const APFloat &V = FPC->getValueAPF();
bool ignored;
uint64_t x[2];
@@ -273,7 +273,7 @@ Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context,
return 0; // Other pointer types cannot be casted
case Instruction::UIToFP:
case Instruction::SIToFP:
- if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
APInt api = CI->getValue();
const uint64_t zero[] = {0, 0};
APFloat apf = APFloat(APInt(DestTy->getPrimitiveSizeInBits(),
@@ -285,7 +285,7 @@ Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context,
}
return 0;
case Instruction::ZExt:
- if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
uint32_t BitWidth = cast<IntegerType>(DestTy)->getBitWidth();
APInt Result(CI->getValue());
Result.zext(BitWidth);
@@ -293,7 +293,7 @@ Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context,
}
return 0;
case Instruction::SExt:
- if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
uint32_t BitWidth = cast<IntegerType>(DestTy)->getBitWidth();
APInt Result(CI->getValue());
Result.sext(BitWidth);
@@ -301,7 +301,7 @@ Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context,
}
return 0;
case Instruction::Trunc:
- if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
uint32_t BitWidth = cast<IntegerType>(DestTy)->getBitWidth();
APInt Result(CI->getValue());
Result.trunc(BitWidth);
@@ -309,7 +309,7 @@ Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context,
}
return 0;
case Instruction::BitCast:
- return FoldBitCast(Context, const_cast<Constant*>(V), DestTy);
+ return FoldBitCast(Context, V, DestTy);
default:
assert(!"Invalid CE CastInst opcode");
break;
@@ -320,30 +320,29 @@ Constant *llvm::ConstantFoldCastInstruction(LLVMContext &Context,
}
Constant *llvm::ConstantFoldSelectInstruction(LLVMContext&,
- const Constant *Cond,
- const Constant *V1,
- const Constant *V2) {
- if (const ConstantInt *CB = dyn_cast<ConstantInt>(Cond))
- return const_cast<Constant*>(CB->getZExtValue() ? V1 : V2);
-
- if (isa<UndefValue>(V1)) return const_cast<Constant*>(V2);
- if (isa<UndefValue>(V2)) return const_cast<Constant*>(V1);
- if (isa<UndefValue>(Cond)) return const_cast<Constant*>(V1);
- if (V1 == V2) return const_cast<Constant*>(V1);
+ Constant *Cond,
+ Constant *V1, Constant *V2) {
+ if (ConstantInt *CB = dyn_cast<ConstantInt>(Cond))
+ return CB->getZExtValue() ? V1 : V2;
+
+ if (isa<UndefValue>(V1)) return V2;
+ if (isa<UndefValue>(V2)) return V1;
+ if (isa<UndefValue>(Cond)) return V1;
+ if (V1 == V2) return V1;
return 0;
}
Constant *llvm::ConstantFoldExtractElementInstruction(LLVMContext &Context,
- const Constant *Val,
- const Constant *Idx) {
+ Constant *Val,
+ Constant *Idx) {
if (isa<UndefValue>(Val)) // ee(undef, x) -> undef
return UndefValue::get(cast<VectorType>(Val->getType())->getElementType());
if (Val->isNullValue()) // ee(zero, x) -> zero
return Constant::getNullValue(
cast<VectorType>(Val->getType())->getElementType());
- if (const ConstantVector *CVal = dyn_cast<ConstantVector>(Val)) {
- if (const ConstantInt *CIdx = dyn_cast<ConstantInt>(Idx)) {
+ if (ConstantVector *CVal = dyn_cast<ConstantVector>(Val)) {
+ if (ConstantInt *CIdx = dyn_cast<ConstantInt>(Idx)) {
return CVal->getOperand(CIdx->getZExtValue());
} else if (isa<UndefValue>(Idx)) {
// ee({w,x,y,z}, undef) -> w (an arbitrary value).
@@ -354,17 +353,17 @@ Constant *llvm::ConstantFoldExtractElementInstruction(LLVMContext &Context,
}
Constant *llvm::ConstantFoldInsertElementInstruction(LLVMContext &Context,
- const Constant *Val,
- const Constant *Elt,
- const Constant *Idx) {
- const ConstantInt *CIdx = dyn_cast<ConstantInt>(Idx);
+ Constant *Val,
+ Constant *Elt,
+ Constant *Idx) {
+ ConstantInt *CIdx = dyn_cast<ConstantInt>(Idx);
if (!CIdx) return 0;
APInt idxVal = CIdx->getValue();
if (isa<UndefValue>(Val)) {
// Insertion of scalar constant into vector undef
// Optimize away insertion of undef
if (isa<UndefValue>(Elt))
- return const_cast<Constant*>(Val);
+ return Val;
// Otherwise break the aggregate undef into multiple undefs and do
// the insertion
unsigned numOps =
@@ -372,9 +371,9 @@ Constant *llvm::ConstantFoldInsertElementInstruction(LLVMContext &Context,
std::vector<Constant*> Ops;
Ops.reserve(numOps);
for (unsigned i = 0; i < numOps; ++i) {
- const Constant *Op =
+ Constant *Op =
(idxVal == i) ? Elt : UndefValue::get(Elt->getType());
- Ops.push_back(const_cast<Constant*>(Op));
+ Ops.push_back(Op);
}
return ConstantVector::get(Ops);
}
@@ -382,7 +381,7 @@ Constant *llvm::ConstantFoldInsertElementInstruction(LLVMContext &Context,
// Insertion of scalar constant into vector aggregate zero
// Optimize away insertion of zero
if (Elt->isNullValue())
- return const_cast<Constant*>(Val);
+ return Val;
// Otherwise break the aggregate zero into multiple zeros and do
// the insertion
unsigned numOps =
@@ -390,20 +389,20 @@ Constant *llvm::ConstantFoldInsertElementInstruction(LLVMContext &Context,
std::vector<Constant*> Ops;
Ops.reserve(numOps);
for (unsigned i = 0; i < numOps; ++i) {
- const Constant *Op =
+ Constant *Op =
(idxVal == i) ? Elt : Constant::getNullValue(Elt->getType());
- Ops.push_back(const_cast<Constant*>(Op));
+ Ops.push_back(Op);
}
return ConstantVector::get(Ops);
}
- if (const ConstantVector *CVal = dyn_cast<ConstantVector>(Val)) {
+ if (ConstantVector *CVal = dyn_cast<ConstantVector>(Val)) {
// Insertion of scalar constant into vector constant
std::vector<Constant*> Ops;
Ops.reserve(CVal->getNumOperands());
for (unsigned i = 0; i < CVal->getNumOperands(); ++i) {
- const Constant *Op =
+ Constant *Op =
(idxVal == i) ? Elt : cast<Constant>(CVal->getOperand(i));
- Ops.push_back(const_cast<Constant*>(Op));
+ Ops.push_back(Op);
}
return ConstantVector::get(Ops);
}
@@ -413,9 +412,9 @@ Constant *llvm::ConstantFoldInsertElementInstruction(LLVMContext &Context,
/// GetVectorElement - If C is a ConstantVector, ConstantAggregateZero or Undef
/// return the specified element value. Otherwise return null.
-static Constant *GetVectorElement(LLVMContext &Context, const Constant *C,
+static Constant *GetVectorElement(LLVMContext &Context, Constant *C,
unsigned EltNo) {
- if (const ConstantVector *CV = dyn_cast<ConstantVector>(C))
+ if (ConstantVector *CV = dyn_cast<ConstantVector>(C))
return CV->getOperand(EltNo);
const Type *EltTy = cast<VectorType>(C->getType())->getElementType();
@@ -427,9 +426,9 @@ static Constant *GetVectorElement(LLVMContext &Context, const Constant *C,
}
Constant *llvm::ConstantFoldShuffleVectorInstruction(LLVMContext &Context,
- const Constant *V1,
- const Constant *V2,
- const Constant *Mask) {
+ Constant *V1,
+ Constant *V2,
+ Constant *Mask) {
// Undefined shuffle mask -> undefined value.
if (isa<UndefValue>(Mask)) return UndefValue::get(V1->getType());
@@ -465,12 +464,12 @@ Constant *llvm::ConstantFoldShuffleVectorInstruction(LLVMContext &Context,
}
Constant *llvm::ConstantFoldExtractValueInstruction(LLVMContext &Context,
- const Constant *Agg,
+ Constant *Agg,
const unsigned *Idxs,
unsigned NumIdx) {
// Base case: no indices, so return the entire value.
if (NumIdx == 0)
- return const_cast<Constant *>(Agg);
+ return Agg;
if (isa<UndefValue>(Agg)) // ev(undef, x) -> undef
return UndefValue::get(ExtractValueInst::getIndexedType(Agg->getType(),
@@ -489,88 +488,92 @@ Constant *llvm::ConstantFoldExtractValueInstruction(LLVMContext &Context,
}
Constant *llvm::ConstantFoldInsertValueInstruction(LLVMContext &Context,
- const Constant *Agg,
- const Constant *Val,
+ Constant *Agg,
+ Constant *Val,
const unsigned *Idxs,
unsigned NumIdx) {
// Base case: no indices, so replace the entire value.
if (NumIdx == 0)
- return const_cast<Constant *>(Val);
+ return Val;
if (isa<UndefValue>(Agg)) {
// Insertion of constant into aggregate undef
- // Optimize away insertion of undef
+ // Optimize away insertion of undef.
if (isa<UndefValue>(Val))
- return const_cast<Constant*>(Agg);
+ return Agg;
+
// Otherwise break the aggregate undef into multiple undefs and do
- // the insertion
+ // the insertion.
const CompositeType *AggTy = cast<CompositeType>(Agg->getType());
unsigned numOps;
if (const ArrayType *AR = dyn_cast<ArrayType>(AggTy))
numOps = AR->getNumElements();
else
numOps = cast<StructType>(AggTy)->getNumElements();
+
std::vector<Constant*> Ops(numOps);
for (unsigned i = 0; i < numOps; ++i) {
const Type *MemberTy = AggTy->getTypeAtIndex(i);
- const Constant *Op =
+ Constant *Op =
(*Idxs == i) ?
ConstantFoldInsertValueInstruction(Context, UndefValue::get(MemberTy),
Val, Idxs+1, NumIdx-1) :
UndefValue::get(MemberTy);
- Ops[i] = const_cast<Constant*>(Op);
+ Ops[i] = Op;
}
- if (isa<StructType>(AggTy))
- return ConstantStruct::get(Context, Ops);
- else
- return ConstantArray::get(cast<ArrayType>(AggTy), Ops);
+
+ if (const StructType* ST = dyn_cast<StructType>(AggTy))
+ return ConstantStruct::get(Context, Ops, ST->isPacked());
+ return ConstantArray::get(cast<ArrayType>(AggTy), Ops);
}
+
if (isa<ConstantAggregateZero>(Agg)) {
// Insertion of constant into aggregate zero
- // Optimize away insertion of zero
+ // Optimize away insertion of zero.
if (Val->isNullValue())
- return const_cast<Constant*>(Agg);
+ return Agg;
+
// Otherwise break the aggregate zero into multiple zeros and do
- // the insertion
+ // the insertion.
const CompositeType *AggTy = cast<CompositeType>(Agg->getType());
unsigned numOps;
if (const ArrayType *AR = dyn_cast<ArrayType>(AggTy))
numOps = AR->getNumElements();
else
numOps = cast<StructType>(AggTy)->getNumElements();
+
std::vector<Constant*> Ops(numOps);
for (unsigned i = 0; i < numOps; ++i) {
const Type *MemberTy = AggTy->getTypeAtIndex(i);
- const Constant *Op =
+ Constant *Op =
(*Idxs == i) ?
ConstantFoldInsertValueInstruction(Context,
Constant::getNullValue(MemberTy),
Val, Idxs+1, NumIdx-1) :
Constant::getNullValue(MemberTy);
- Ops[i] = const_cast<Constant*>(Op);
+ Ops[i] = Op;
}
- if (isa<StructType>(AggTy))
- return ConstantStruct::get(Context, Ops);
- else
- return ConstantArray::get(cast<ArrayType>(AggTy), Ops);
+
+ if (const StructType* ST = dyn_cast<StructType>(AggTy))
+ return ConstantStruct::get(Context, Ops, ST->isPacked());
+ return ConstantArray::get(cast<ArrayType>(AggTy), Ops);
}
+
if (isa<ConstantStruct>(Agg) || isa<ConstantArray>(Agg)) {
- // Insertion of constant into aggregate constant
+ // Insertion of constant into aggregate constant.
std::vector<Constant*> Ops(Agg->getNumOperands());
for (unsigned i = 0; i < Agg->getNumOperands(); ++i) {
- const Constant *Op =
+ Constant *Op =
(*Idxs == i) ?
ConstantFoldInsertValueInstruction(Context, Agg->getOperand(i),
Val, Idxs+1, NumIdx-1) :
Agg->getOperand(i);
- Ops[i] = const_cast<Constant*>(Op);
+ Ops[i] = Op;
}
- Constant *C;
- if (isa<StructType>(Agg->getType()))
- C = ConstantStruct::get(Context, Ops);
- else
- C = ConstantArray::get(cast<ArrayType>(Agg->getType()), Ops);
- return C;
+
+ if (const StructType* ST = dyn_cast<StructType>(Agg->getType()))
+ return ConstantStruct::get(Context, Ops, ST->isPacked());
+ return ConstantArray::get(cast<ArrayType>(Agg->getType()), Ops);
}
return 0;
@@ -579,13 +582,12 @@ Constant *llvm::ConstantFoldInsertValueInstruction(LLVMContext &Context,
Constant *llvm::ConstantFoldBinaryInstruction(LLVMContext &Context,
unsigned Opcode,
- const Constant *C1,
- const Constant *C2) {
+ Constant *C1, Constant *C2) {
// No compile-time operations on this type yet.
if (C1->getType() == Type::getPPC_FP128Ty(Context))
return 0;
- // Handle UndefValue up front
+ // Handle UndefValue up front.
if (isa<UndefValue>(C1) || isa<UndefValue>(C2)) {
switch (Opcode) {
case Instruction::Xor:
@@ -606,23 +608,23 @@ Constant *llvm::ConstantFoldBinaryInstruction(LLVMContext &Context,
case Instruction::SRem:
if (!isa<UndefValue>(C2)) // undef / X -> 0
return Constant::getNullValue(C1->getType());
- return const_cast<Constant*>(C2); // X / undef -> undef
+ return C2; // X / undef -> undef
case Instruction::Or: // X | undef -> -1
if (const VectorType *PTy = dyn_cast<VectorType>(C1->getType()))
return Constant::getAllOnesValue(PTy);
return Constant::getAllOnesValue(C1->getType());
case Instruction::LShr:
if (isa<UndefValue>(C2) && isa<UndefValue>(C1))
- return const_cast<Constant*>(C1); // undef lshr undef -> undef
+ return C1; // undef lshr undef -> undef
return Constant::getNullValue(C1->getType()); // X lshr undef -> 0
// undef lshr X -> 0
case Instruction::AShr:
if (!isa<UndefValue>(C2))
- return const_cast<Constant*>(C1); // undef ashr X --> undef
+ return C1; // undef ashr X --> undef
else if (isa<UndefValue>(C1))
- return const_cast<Constant*>(C1); // undef ashr undef -> undef
+ return C1; // undef ashr undef -> undef
else
- return const_cast<Constant*>(C1); // X ashr undef --> X
+ return C1; // X ashr undef --> X
case Instruction::Shl:
// undef << X -> 0 or X << undef -> 0
return Constant::getNullValue(C1->getType());
@@ -630,23 +632,23 @@ Constant *llvm::ConstantFoldBinaryInstruction(LLVMContext &Context,
}
// Handle simplifications when the RHS is a constant int.
- if (const ConstantInt *CI2 = dyn_cast<ConstantInt>(C2)) {
+ if (ConstantInt *CI2 = dyn_cast<ConstantInt>(C2)) {
switch (Opcode) {
case Instruction::Add:
- if (CI2->equalsInt(0)) return const_cast<Constant*>(C1); // X + 0 == X
+ if (CI2->equalsInt(0)) return C1; // X + 0 == X
break;
case Instruction::Sub:
- if (CI2->equalsInt(0)) return const_cast<Constant*>(C1); // X - 0 == X
+ if (CI2->equalsInt(0)) return C1; // X - 0 == X
break;
case Instruction::Mul:
- if (CI2->equalsInt(0)) return const_cast<Constant*>(C2); // X * 0 == 0
+ if (CI2->equalsInt(0)) return C2; // X * 0 == 0
if (CI2->equalsInt(1))
- return const_cast<Constant*>(C1); // X * 1 == X
+ return C1; // X * 1 == X
break;
case Instruction::UDiv:
case Instruction::SDiv:
if (CI2->equalsInt(1))
- return const_cast<Constant*>(C1); // X / 1 == X
+ return C1; // X / 1 == X
if (CI2->equalsInt(0))
return UndefValue::get(CI2->getType()); // X / 0 == undef
break;
@@ -658,11 +660,11 @@ Constant *llvm::ConstantFoldBinaryInstruction(LLVMContext &Context,
return UndefValue::get(CI2->getType()); // X % 0 == undef
break;
case Instruction::And:
- if (CI2->isZero()) return const_cast<Constant*>(C2); // X & 0 == 0
+ if (CI2->isZero()) return C2; // X & 0 == 0
if (CI2->isAllOnesValue())
- return const_cast<Constant*>(C1); // X & -1 == X
+ return C1; // X & -1 == X
- if (const ConstantExpr *CE1 = dyn_cast<ConstantExpr>(C1)) {
+ if (ConstantExpr *CE1 = dyn_cast<ConstantExpr>(C1)) {
// (zext i32 to i64) & 4294967295 -> (zext i32 to i64)
if (CE1->getOpcode() == Instruction::ZExt) {
unsigned DstWidth = CI2->getType()->getBitWidth();
@@ -670,7 +672,7 @@ Constant *llvm::ConstantFoldBinaryInstruction(LLVMContext &Context,
CE1->getOperand(0)->getType()->getPrimitiveSizeInBits();
APInt PossiblySetBits(APInt::getLowBitsSet(DstWidth, SrcWidth));
if ((PossiblySetBits & CI2->getValue()) == PossiblySetBits)
- return const_cast<Constant*>(C1);
+ return C1;
}
// If and'ing the address of a global with a constant, fold it.
@@ -696,26 +698,39 @@ Constant *llvm::ConstantFoldBinaryInstruction(LLVMContext &Context,
}
break;
case Instruction::Or:
- if (CI2->equalsInt(0)) return const_cast<Constant*>(C1); // X | 0 == X
+ if (CI2->equalsInt(0)) return C1; // X | 0 == X
if (CI2->isAllOnesValue())
- return const_cast<Constant*>(C2); // X | -1 == -1
+ return C2; // X | -1 == -1
break;
case Instruction::Xor:
- if (CI2->equalsInt(0)) return const_cast<Constant*>(C1); // X ^ 0 == X
+ if (CI2->equalsInt(0)) return C1; // X ^ 0 == X
+
+ if (ConstantExpr *CE1 = dyn_cast<ConstantExpr>(C1)) {
+ switch (CE1->getOpcode()) {
+ default: break;
+ case Instruction::ICmp:
+ case Instruction::FCmp:
+ // cmp pred ^ true -> cmp !pred
+ assert(CI2->equalsInt(1));
+ CmpInst::Predicate pred = (CmpInst::Predicate)CE1->getPredicate();
+ pred = CmpInst::getInversePredicate(pred);
+ return ConstantExpr::getCompare(pred, CE1->getOperand(0),
+ CE1->getOperand(1));
+ }
+ }
break;
case Instruction::AShr:
// ashr (zext C to Ty), C2 -> lshr (zext C, CSA), C2
- if (const ConstantExpr *CE1 = dyn_cast<ConstantExpr>(C1))
+ if (ConstantExpr *CE1 = dyn_cast<ConstantExpr>(C1))
if (CE1->getOpcode() == Instruction::ZExt) // Top bits known zero.
- return ConstantExpr::getLShr(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2));
+ return ConstantExpr::getLShr(C1, C2);
break;
}
}
// At this point we know neither constant is an UndefValue.
- if (const ConstantInt *CI1 = dyn_cast<ConstantInt>(C1)) {
- if (const ConstantInt *CI2 = dyn_cast<ConstantInt>(C2)) {
+ if (ConstantInt *CI1 = dyn_cast<ConstantInt>(C1)) {
+ if (ConstantInt *CI2 = dyn_cast<ConstantInt>(C2)) {
using namespace APIntOps;
const APInt &C1V = CI1->getValue();
const APInt &C2V = CI2->getValue();
@@ -782,13 +797,13 @@ Constant *llvm::ConstantFoldBinaryInstruction(LLVMContext &Context,
case Instruction::LShr:
case Instruction::AShr:
case Instruction::Shl:
- if (CI1->equalsInt(0)) return const_cast<Constant*>(C1);
+ if (CI1->equalsInt(0)) return C1;
break;
default:
break;
}
- } else if (const ConstantFP *CFP1 = dyn_cast<ConstantFP>(C1)) {
- if (const ConstantFP *CFP2 = dyn_cast<ConstantFP>(C2)) {
+ } else if (ConstantFP *CFP1 = dyn_cast<ConstantFP>(C1)) {
+ if (ConstantFP *CFP2 = dyn_cast<ConstantFP>(C2)) {
APFloat C1V = CFP1->getValueAPF();
APFloat C2V = CFP2->getValueAPF();
APFloat C3V = C1V; // copy for modification
@@ -813,14 +828,14 @@ Constant *llvm::ConstantFoldBinaryInstruction(LLVMContext &Context,
}
}
} else if (const VectorType *VTy = dyn_cast<VectorType>(C1->getType())) {
- const ConstantVector *CP1 = dyn_cast<ConstantVector>(C1);
- const ConstantVector *CP2 = dyn_cast<ConstantVector>(C2);
+ ConstantVector *CP1 = dyn_cast<ConstantVector>(C1);
+ ConstantVector *CP2 = dyn_cast<ConstantVector>(C2);
if ((CP1 != NULL || isa<ConstantAggregateZero>(C1)) &&
(CP2 != NULL || isa<ConstantAggregateZero>(C2))) {
std::vector<Constant*> Res;
const Type* EltTy = VTy->getElementType();
- const Constant *C1 = 0;
- const Constant *C2 = 0;
+ Constant *C1 = 0;
+ Constant *C2 = 0;
switch (Opcode) {
default:
break;
@@ -828,144 +843,126 @@ Constant *llvm::ConstantFoldBinaryInstruction(LLVMContext &Context,
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getAdd(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getAdd(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::FAdd:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getFAdd(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getFAdd(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::Sub:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getSub(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getSub(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::FSub:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getFSub(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getFSub(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::Mul:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getMul(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getMul(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::FMul:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getFMul(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getFMul(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::UDiv:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getUDiv(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getUDiv(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::SDiv:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getSDiv(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getSDiv(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::FDiv:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getFDiv(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getFDiv(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::URem:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getURem(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getURem(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::SRem:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getSRem(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getSRem(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::FRem:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getFRem(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getFRem(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::And:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getAnd(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getAnd(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::Or:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getOr(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getOr(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::Xor:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getXor(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getXor(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::LShr:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getLShr(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getLShr(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::AShr:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getAShr(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getAShr(C1, C2));
}
return ConstantVector::get(Res);
case Instruction::Shl:
for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i) {
C1 = CP1 ? CP1->getOperand(i) : Constant::getNullValue(EltTy);
C2 = CP2 ? CP2->getOperand(i) : Constant::getNullValue(EltTy);
- Res.push_back(ConstantExpr::getShl(const_cast<Constant*>(C1),
- const_cast<Constant*>(C2)));
+ Res.push_back(ConstantExpr::getShl(C1, C2));
}
return ConstantVector::get(Res);
}
@@ -1006,6 +1003,35 @@ Constant *llvm::ConstantFoldBinaryInstruction(LLVMContext &Context,
}
}
+ // i1 can be simplified in many cases.
+ if (C1->getType() == Type::getInt1Ty(Context)) {
+ switch (Opcode) {
+ case Instruction::Add:
+ case Instruction::Sub:
+ return ConstantExpr::getXor(C1, C2);
+ case Instruction::Mul:
+ return ConstantExpr::getAnd(C1, C2);
+ case Instruction::Shl:
+ case Instruction::LShr:
+ case Instruction::AShr:
+ // We can assume that C2 == 0. If it were one the result would be
+ // undefined because the shift value is as large as the bitwidth.
+ return C1;
+ case Instruction::SDiv:
+ case Instruction::UDiv:
+ // We can assume that C2 == 1. If it were zero the result would be
+ // undefined through division by zero.
+ return C1;
+ case Instruction::URem:
+ case Instruction::SRem:
+ // We can assume that C2 == 1. If it were zero the result would be
+ // undefined through division by zero.
+ return ConstantInt::getFalse(Context);
+ default:
+ break;
+ }
+ }
+
// We don't know how to fold this.
return 0;
}
@@ -1079,8 +1105,7 @@ static int IdxCompare(LLVMContext &Context, Constant *C1, Constant *C2,
/// operand is always the most "complex" of the two. We consider ConstantFP
/// to be the simplest, and ConstantExprs to be the most complex.
static FCmpInst::Predicate evaluateFCmpRelation(LLVMContext &Context,
- const Constant *V1,
- const Constant *V2) {
+ Constant *V1, Constant *V2) {
assert(V1->getType() == V2->getType() &&
"Cannot compare values of different types!");
@@ -1095,18 +1120,16 @@ static FCmpInst::Predicate evaluateFCmpRelation(LLVMContext &Context,
if (!isa<ConstantExpr>(V2)) {
// We distilled thisUse the standard constant folder for a few cases
ConstantInt *R = 0;
- Constant *C1 = const_cast<Constant*>(V1);
- Constant *C2 = const_cast<Constant*>(V2);
R = dyn_cast<ConstantInt>(
- ConstantExpr::getFCmp(FCmpInst::FCMP_OEQ, C1, C2));
+ ConstantExpr::getFCmp(FCmpInst::FCMP_OEQ, V1, V2));
if (R && !R->isZero())
return FCmpInst::FCMP_OEQ;
R = dyn_cast<ConstantInt>(
- ConstantExpr::getFCmp(FCmpInst::FCMP_OLT, C1, C2));
+ ConstantExpr::getFCmp(FCmpInst::FCMP_OLT, V1, V2));
if (R && !R->isZero())
return FCmpInst::FCMP_OLT;
R = dyn_cast<ConstantInt>(
- ConstantExpr::getFCmp(FCmpInst::FCMP_OGT, C1, C2));
+ ConstantExpr::getFCmp(FCmpInst::FCMP_OGT, V1, V2));
if (R && !R->isZero())
return FCmpInst::FCMP_OGT;
@@ -1121,7 +1144,7 @@ static FCmpInst::Predicate evaluateFCmpRelation(LLVMContext &Context,
} else {
// Ok, the LHS is known to be a constantexpr. The RHS can be any of a
// constantexpr or a simple constant.
- const ConstantExpr *CE1 = cast<ConstantExpr>(V1);
+ ConstantExpr *CE1 = cast<ConstantExpr>(V1);
switch (CE1->getOpcode()) {
case Instruction::FPTrunc:
case Instruction::FPExt:
@@ -1151,8 +1174,8 @@ static FCmpInst::Predicate evaluateFCmpRelation(LLVMContext &Context,
/// GlobalValues, followed by ConstantExpr's (the most complex).
///
static ICmpInst::Predicate evaluateICmpRelation(LLVMContext &Context,
- const Constant *V1,
- const Constant *V2,
+ Constant *V1,
+ Constant *V2,
bool isSigned) {
assert(V1->getType() == V2->getType() &&
"Cannot compare different types of values!");
@@ -1163,18 +1186,16 @@ static ICmpInst::Predicate evaluateICmpRelation(LLVMContext &Context,
// We distilled this down to a simple case, use the standard constant
// folder.
ConstantInt *R = 0;
- Constant *C1 = const_cast<Constant*>(V1);
- Constant *C2 = const_cast<Constant*>(V2);
ICmpInst::Predicate pred = ICmpInst::ICMP_EQ;
- R = dyn_cast<ConstantInt>(ConstantExpr::getICmp(pred, C1, C2));
+ R = dyn_cast<ConstantInt>(ConstantExpr::getICmp(pred, V1, V2));
if (R && !R->isZero())
return pred;
pred = isSigned ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT;
- R = dyn_cast<ConstantInt>(ConstantExpr::getICmp(pred, C1, C2));
+ R = dyn_cast<ConstantInt>(ConstantExpr::getICmp(pred, V1, V2));
if (R && !R->isZero())
return pred;
pred = isSigned ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT;
- R = dyn_cast<ConstantInt>(ConstantExpr::getICmp(pred, C1, C2));
+ R = dyn_cast<ConstantInt>(ConstantExpr::getICmp(pred, V1, V2));
if (R && !R->isZero())
return pred;
@@ -1214,8 +1235,8 @@ static ICmpInst::Predicate evaluateICmpRelation(LLVMContext &Context,
} else {
// Ok, the LHS is known to be a constantexpr. The RHS can be any of a
// constantexpr, a CPR, or a simple constant.
- const ConstantExpr *CE1 = cast<ConstantExpr>(V1);
- const Constant *CE1Op0 = CE1->getOperand(0);
+ ConstantExpr *CE1 = cast<ConstantExpr>(V1);
+ Constant *CE1Op0 = CE1->getOperand(0);
switch (CE1->getOpcode()) {
case Instruction::Trunc:
@@ -1234,28 +1255,12 @@ static ICmpInst::Predicate evaluateICmpRelation(LLVMContext &Context,
// null pointer, do the comparison with the pre-casted value.
if (V2->isNullValue() &&
(isa<PointerType>(CE1->getType()) || CE1->getType()->isInteger())) {
- bool sgnd = isSigned;
if (CE1->getOpcode() == Instruction::ZExt) isSigned = false;
if (CE1->getOpcode() == Instruction::SExt) isSigned = true;
return evaluateICmpRelation(Context, CE1Op0,
Constant::getNullValue(CE1Op0->getType()),
- sgnd);
+ isSigned);
}
-
- // If the dest type is a pointer type, and the RHS is a constantexpr cast
- // from the same type as the src of the LHS, evaluate the inputs. This is
- // important for things like "icmp eq (cast 4 to int*), (cast 5 to int*)",
- // which happens a lot in compilers with tagged integers.
- if (const ConstantExpr *CE2 = dyn_cast<ConstantExpr>(V2))
- if (CE2->isCast() && isa<PointerType>(CE1->getType()) &&
- CE1->getOperand(0)->getType() == CE2->getOperand(0)->getType() &&
- CE1->getOperand(0)->getType()->isInteger()) {
- bool sgnd = isSigned;
- if (CE1->getOpcode() == Instruction::ZExt) isSigned = false;
- if (CE1->getOpcode() == Instruction::SExt) isSigned = true;
- return evaluateICmpRelation(Context, CE1->getOperand(0),
- CE2->getOperand(0), sgnd);
- }
break;
case Instruction::GetElementPtr:
@@ -1272,7 +1277,7 @@ static ICmpInst::Predicate evaluateICmpRelation(LLVMContext &Context,
else
// If its not weak linkage, the GVal must have a non-zero address
// so the result is greater-than
- return isSigned ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT;
+ return isSigned ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT;
} else if (isa<ConstantPointerNull>(CE1Op0)) {
// If we are indexing from a null pointer, check to see if we have any
// non-zero indices.
@@ -1311,8 +1316,8 @@ static ICmpInst::Predicate evaluateICmpRelation(LLVMContext &Context,
}
}
} else {
- const ConstantExpr *CE2 = cast<ConstantExpr>(V2);
- const Constant *CE2Op0 = CE2->getOperand(0);
+ ConstantExpr *CE2 = cast<ConstantExpr>(V2);
+ Constant *CE2Op0 = CE2->getOperand(0);
// There are MANY other foldings that we could perform here. They will
// probably be added on demand, as they seem needed.
@@ -1329,6 +1334,14 @@ static ICmpInst::Predicate evaluateICmpRelation(LLVMContext &Context,
// ordering of the resultant pointers.
unsigned i = 1;
+ // The logic below assumes that the result of the comparison
+ // can be determined by finding the first index that differs.
+ // This doesn't work if there is over-indexing in any
+ // subsequent indices, so check for that case first.
+ if (!CE1->isGEPWithNoNotionalOverIndexing() ||
+ !CE2->isGEPWithNoNotionalOverIndexing())
+ return ICmpInst::BAD_ICMP_PREDICATE; // Might be equal.
+
// Compare all of the operands the GEP's have in common.
gep_type_iterator GTI = gep_type_begin(CE1);
for (;i != CE1->getNumOperands() && i != CE2->getNumOperands();
@@ -1371,8 +1384,7 @@ static ICmpInst::Predicate evaluateICmpRelation(LLVMContext &Context,
Constant *llvm::ConstantFoldCompareInstruction(LLVMContext &Context,
unsigned short pred,
- const Constant *C1,
- const Constant *C2) {
+ Constant *C1, Constant *C2) {
const Type *ResultTy;
if (const VectorType *VT = dyn_cast<VectorType>(C1->getType()))
ResultTy = VectorType::get(Type::getInt1Ty(Context), VT->getNumElements());
@@ -1416,6 +1428,20 @@ Constant *llvm::ConstantFoldCompareInstruction(LLVMContext &Context,
}
}
+ // If the comparison is a comparison between two i1's, simplify it.
+ if (C1->getType() == Type::getInt1Ty(Context)) {
+ switch(pred) {
+ case ICmpInst::ICMP_EQ:
+ if (isa<ConstantInt>(C2))
+ return ConstantExpr::getXor(C1, ConstantExpr::getNot(C2));
+ return ConstantExpr::getXor(ConstantExpr::getNot(C1), C2);
+ case ICmpInst::ICMP_NE:
+ return ConstantExpr::getXor(C1, C2);
+ default:
+ break;
+ }
+ }
+
if (isa<ConstantInt>(C1) && isa<ConstantInt>(C2)) {
APInt V1 = cast<ConstantInt>(C1)->getValue();
APInt V2 = cast<ConstantInt>(C2)->getValue();
@@ -1569,64 +1595,57 @@ Constant *llvm::ConstantFoldCompareInstruction(LLVMContext &Context,
case ICmpInst::ICMP_EQ: // We know the constants are equal!
// If we know the constants are equal, we can decide the result of this
// computation precisely.
- Result = (pred == ICmpInst::ICMP_EQ ||
- pred == ICmpInst::ICMP_ULE ||
- pred == ICmpInst::ICMP_SLE ||
- pred == ICmpInst::ICMP_UGE ||
- pred == ICmpInst::ICMP_SGE);
+ Result = ICmpInst::isTrueWhenEqual((ICmpInst::Predicate)pred);
break;
case ICmpInst::ICMP_ULT:
- // If we know that C1 < C2, we can decide the result of this computation
- // precisely.
- Result = (pred == ICmpInst::ICMP_ULT ||
- pred == ICmpInst::ICMP_NE ||
- pred == ICmpInst::ICMP_ULE);
+ switch (pred) {
+ case ICmpInst::ICMP_ULT: case ICmpInst::ICMP_NE: case ICmpInst::ICMP_ULE:
+ Result = 1; break;
+ case ICmpInst::ICMP_UGT: case ICmpInst::ICMP_EQ: case ICmpInst::ICMP_UGE:
+ Result = 0; break;
+ }
break;
case ICmpInst::ICMP_SLT:
- // If we know that C1 < C2, we can decide the result of this computation
- // precisely.
- Result = (pred == ICmpInst::ICMP_SLT ||
- pred == ICmpInst::ICMP_NE ||
- pred == ICmpInst::ICMP_SLE);
+ switch (pred) {
+ case ICmpInst::ICMP_SLT: case ICmpInst::ICMP_NE: case ICmpInst::ICMP_SLE:
+ Result = 1; break;
+ case ICmpInst::ICMP_SGT: case ICmpInst::ICMP_EQ: case ICmpInst::ICMP_SGE:
+ Result = 0; break;
+ }
break;
case ICmpInst::ICMP_UGT:
- // If we know that C1 > C2, we can decide the result of this computation
- // precisely.
- Result = (pred == ICmpInst::ICMP_UGT ||
- pred == ICmpInst::ICMP_NE ||
- pred == ICmpInst::ICMP_UGE);
+ switch (pred) {
+ case ICmpInst::ICMP_UGT: case ICmpInst::ICMP_NE: case ICmpInst::ICMP_UGE:
+ Result = 1; break;
+ case ICmpInst::ICMP_ULT: case ICmpInst::ICMP_EQ: case ICmpInst::ICMP_ULE:
+ Result = 0; break;
+ }
break;
case ICmpInst::ICMP_SGT:
- // If we know that C1 > C2, we can decide the result of this computation
- // precisely.
- Result = (pred == ICmpInst::ICMP_SGT ||
- pred == ICmpInst::ICMP_NE ||
- pred == ICmpInst::ICMP_SGE);
+ switch (pred) {
+ case ICmpInst::ICMP_SGT: case ICmpInst::ICMP_NE: case ICmpInst::ICMP_SGE:
+ Result = 1; break;
+ case ICmpInst::ICMP_SLT: case ICmpInst::ICMP_EQ: case ICmpInst::ICMP_SLE:
+ Result = 0; break;
+ }
break;
case ICmpInst::ICMP_ULE:
- // If we know that C1 <= C2, we can only partially decide this relation.
if (pred == ICmpInst::ICMP_UGT) Result = 0;
- if (pred == ICmpInst::ICMP_ULT) Result = 1;
+ if (pred == ICmpInst::ICMP_ULT || pred == ICmpInst::ICMP_ULE) Result = 1;
break;
case ICmpInst::ICMP_SLE:
- // If we know that C1 <= C2, we can only partially decide this relation.
if (pred == ICmpInst::ICMP_SGT) Result = 0;
- if (pred == ICmpInst::ICMP_SLT) Result = 1;
+ if (pred == ICmpInst::ICMP_SLT || pred == ICmpInst::ICMP_SLE) Result = 1;
break;
-
case ICmpInst::ICMP_UGE:
- // If we know that C1 >= C2, we can only partially decide this relation.
if (pred == ICmpInst::ICMP_ULT) Result = 0;
- if (pred == ICmpInst::ICMP_UGT) Result = 1;
+ if (pred == ICmpInst::ICMP_UGT || pred == ICmpInst::ICMP_UGE) Result = 1;
break;
case ICmpInst::ICMP_SGE:
- // If we know that C1 >= C2, we can only partially decide this relation.
if (pred == ICmpInst::ICMP_SLT) Result = 0;
- if (pred == ICmpInst::ICMP_SGT) Result = 1;
+ if (pred == ICmpInst::ICMP_SGT || pred == ICmpInst::ICMP_SGE) Result = 1;
break;
-
case ICmpInst::ICMP_NE:
- // If we know that C1 != C2, we can only partially decide this relation.
if (pred == ICmpInst::ICMP_EQ) Result = 0;
if (pred == ICmpInst::ICMP_NE) Result = 1;
break;
@@ -1636,6 +1655,32 @@ Constant *llvm::ConstantFoldCompareInstruction(LLVMContext &Context,
if (Result != -1)
return ConstantInt::get(Type::getInt1Ty(Context), Result);
+ // If the right hand side is a bitcast, try using its inverse to simplify
+ // it by moving it to the left hand side.
+ if (ConstantExpr *CE2 = dyn_cast<ConstantExpr>(C2)) {
+ if (CE2->getOpcode() == Instruction::BitCast) {
+ Constant *CE2Op0 = CE2->getOperand(0);
+ Constant *Inverse = ConstantExpr::getBitCast(C1, CE2Op0->getType());
+ return ConstantExpr::getICmp(pred, Inverse, CE2Op0);
+ }
+ }
+
+ // If the left hand side is an extension, try eliminating it.
+ if (ConstantExpr *CE1 = dyn_cast<ConstantExpr>(C1)) {
+ if (CE1->getOpcode() == Instruction::SExt ||
+ CE1->getOpcode() == Instruction::ZExt) {
+ Constant *CE1Op0 = CE1->getOperand(0);
+ Constant *CE1Inverse = ConstantExpr::getTrunc(CE1, CE1Op0->getType());
+ if (CE1Inverse == CE1Op0) {
+ // Check whether we can safely truncate the right hand side.
+ Constant *C2Inverse = ConstantExpr::getTrunc(C2, CE1Op0->getType());
+ if (ConstantExpr::getZExt(C2Inverse, C2->getType()) == C2) {
+ return ConstantExpr::getICmp(pred, CE1Inverse, C2Inverse);
+ }
+ }
+ }
+ }
+
if (!isa<ConstantExpr>(C1) && isa<ConstantExpr>(C2)) {
// If C2 is a constant expr and C1 isn't, flip them around and fold the
// other way if possible.
@@ -1665,13 +1710,33 @@ Constant *llvm::ConstantFoldCompareInstruction(LLVMContext &Context,
return 0;
}
+/// isInBoundsIndices - Test whether the given sequence of *normalized* indices
+/// is "inbounds".
+static bool isInBoundsIndices(Constant *const *Idxs, size_t NumIdx) {
+ // No indices means nothing that could be out of bounds.
+ if (NumIdx == 0) return true;
+
+ // If the first index is zero, it's in bounds.
+ if (Idxs[0]->isNullValue()) return true;
+
+ // If the first index is one and all the rest are zero, it's in bounds,
+ // by the one-past-the-end rule.
+ if (!cast<ConstantInt>(Idxs[0])->isOne())
+ return false;
+ for (unsigned i = 1, e = NumIdx; i != e; ++i)
+ if (!Idxs[i]->isNullValue())
+ return false;
+ return true;
+}
+
Constant *llvm::ConstantFoldGetElementPtr(LLVMContext &Context,
- const Constant *C,
+ Constant *C,
+ bool inBounds,
Constant* const *Idxs,
unsigned NumIdx) {
if (NumIdx == 0 ||
(NumIdx == 1 && Idxs[0]->isNullValue()))
- return const_cast<Constant*>(C);
+ return C;
if (isa<UndefValue>(C)) {
const PointerType *Ptr = cast<PointerType>(C->getType());
@@ -1701,7 +1766,7 @@ Constant *llvm::ConstantFoldGetElementPtr(LLVMContext &Context,
}
}
- if (ConstantExpr *CE = dyn_cast<ConstantExpr>(const_cast<Constant*>(C))) {
+ if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
// Combine Indices - If the source pointer to this getelementptr instruction
// is a getelementptr instruction, combine the indices of the two
// getelementptr instructions into a single instruction.
@@ -1738,9 +1803,13 @@ Constant *llvm::ConstantFoldGetElementPtr(LLVMContext &Context,
NewIndices.push_back(Combined);
NewIndices.insert(NewIndices.end(), Idxs+1, Idxs+NumIdx);
- return ConstantExpr::getGetElementPtr(CE->getOperand(0),
- &NewIndices[0],
- NewIndices.size());
+ return (inBounds && cast<GEPOperator>(CE)->isInBounds()) ?
+ ConstantExpr::getInBoundsGetElementPtr(CE->getOperand(0),
+ &NewIndices[0],
+ NewIndices.size()) :
+ ConstantExpr::getGetElementPtr(CE->getOperand(0),
+ &NewIndices[0],
+ NewIndices.size());
}
}
@@ -1756,7 +1825,10 @@ Constant *llvm::ConstantFoldGetElementPtr(LLVMContext &Context,
if (const ArrayType *CAT =
dyn_cast<ArrayType>(cast<PointerType>(C->getType())->getElementType()))
if (CAT->getElementType() == SAT->getElementType())
- return ConstantExpr::getGetElementPtr(
+ return inBounds ?
+ ConstantExpr::getInBoundsGetElementPtr(
+ (Constant*)CE->getOperand(0), Idxs, NumIdx) :
+ ConstantExpr::getGetElementPtr(
(Constant*)CE->getOperand(0), Idxs, NumIdx);
}
@@ -1781,5 +1853,69 @@ Constant *llvm::ConstantFoldGetElementPtr(LLVMContext &Context,
return ConstantExpr::getIntToPtr(Base, CE->getType());
}
}
+
+ // Check to see if any array indices are not within the corresponding
+ // notional array bounds. If so, try to determine if they can be factored
+ // out into preceding dimensions.
+ bool Unknown = false;
+ SmallVector<Constant *, 8> NewIdxs;
+ const Type *Ty = C->getType();
+ const Type *Prev = 0;
+ for (unsigned i = 0; i != NumIdx;
+ Prev = Ty, Ty = cast<CompositeType>(Ty)->getTypeAtIndex(Idxs[i]), ++i) {
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(Idxs[i])) {
+ if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty))
+ if (ATy->getNumElements() <= INT64_MAX &&
+ ATy->getNumElements() != 0 &&
+ CI->getSExtValue() >= (int64_t)ATy->getNumElements()) {
+ if (isa<SequentialType>(Prev)) {
+ // It's out of range, but we can factor it into the prior
+ // dimension.
+ NewIdxs.resize(NumIdx);
+ ConstantInt *Factor = ConstantInt::get(CI->getType(),
+ ATy->getNumElements());
+ NewIdxs[i] = ConstantExpr::getSRem(CI, Factor);
+
+ Constant *PrevIdx = Idxs[i-1];
+ Constant *Div = ConstantExpr::getSDiv(CI, Factor);
+
+ // Before adding, extend both operands to i64 to avoid
+ // overflow trouble.
+ if (PrevIdx->getType() != Type::getInt64Ty(Context))
+ PrevIdx = ConstantExpr::getSExt(PrevIdx,
+ Type::getInt64Ty(Context));
+ if (Div->getType() != Type::getInt64Ty(Context))
+ Div = ConstantExpr::getSExt(Div,
+ Type::getInt64Ty(Context));
+
+ NewIdxs[i-1] = ConstantExpr::getAdd(PrevIdx, Div);
+ } else {
+ // It's out of range, but the prior dimension is a struct
+ // so we can't do anything about it.
+ Unknown = true;
+ }
+ }
+ } else {
+ // We don't know if it's in range or not.
+ Unknown = true;
+ }
+ }
+
+ // If we did any factoring, start over with the adjusted indices.
+ if (!NewIdxs.empty()) {
+ for (unsigned i = 0; i != NumIdx; ++i)
+ if (!NewIdxs[i]) NewIdxs[i] = Idxs[i];
+ return inBounds ?
+ ConstantExpr::getInBoundsGetElementPtr(C, NewIdxs.data(),
+ NewIdxs.size()) :
+ ConstantExpr::getGetElementPtr(C, NewIdxs.data(), NewIdxs.size());
+ }
+
+ // If all indices are known integers and normalized, we can do a simple
+ // check for the "inbounds" property.
+ if (!Unknown && !inBounds &&
+ isa<GlobalVariable>(C) && isInBoundsIndices(Idxs, NumIdx))
+ return ConstantExpr::getInBoundsGetElementPtr(C, Idxs, NumIdx);
+
return 0;
}
diff --git a/libclamav/c++/llvm/lib/VMCore/ConstantFold.h b/libclamav/c++/llvm/lib/VMCore/ConstantFold.h
index afa9978..cc97001 100644
--- a/libclamav/c++/llvm/lib/VMCore/ConstantFold.h
+++ b/libclamav/c++/llvm/lib/VMCore/ConstantFold.h
@@ -29,41 +29,40 @@ namespace llvm {
Constant *ConstantFoldCastInstruction(
LLVMContext &Context,
unsigned opcode, ///< The opcode of the cast
- const Constant *V, ///< The source constant
+ Constant *V, ///< The source constant
const Type *DestTy ///< The destination type
);
Constant *ConstantFoldSelectInstruction(LLVMContext &Context,
- const Constant *Cond,
- const Constant *V1,
- const Constant *V2);
+ Constant *Cond,
+ Constant *V1, Constant *V2);
Constant *ConstantFoldExtractElementInstruction(LLVMContext &Context,
- const Constant *Val,
- const Constant *Idx);
+ Constant *Val,
+ Constant *Idx);
Constant *ConstantFoldInsertElementInstruction(LLVMContext &Context,
- const Constant *Val,
- const Constant *Elt,
- const Constant *Idx);
+ Constant *Val,
+ Constant *Elt,
+ Constant *Idx);
Constant *ConstantFoldShuffleVectorInstruction(LLVMContext &Context,
- const Constant *V1,
- const Constant *V2,
- const Constant *Mask);
+ Constant *V1,
+ Constant *V2,
+ Constant *Mask);
Constant *ConstantFoldExtractValueInstruction(LLVMContext &Context,
- const Constant *Agg,
+ Constant *Agg,
const unsigned *Idxs,
unsigned NumIdx);
Constant *ConstantFoldInsertValueInstruction(LLVMContext &Context,
- const Constant *Agg,
- const Constant *Val,
- const unsigned* Idxs,
+ Constant *Agg,
+ Constant *Val,
+ const unsigned *Idxs,
unsigned NumIdx);
Constant *ConstantFoldBinaryInstruction(LLVMContext &Context,
- unsigned Opcode, const Constant *V1,
- const Constant *V2);
+ unsigned Opcode, Constant *V1,
+ Constant *V2);
Constant *ConstantFoldCompareInstruction(LLVMContext &Context,
unsigned short predicate,
- const Constant *C1,
- const Constant *C2);
- Constant *ConstantFoldGetElementPtr(LLVMContext &Context, const Constant *C,
+ Constant *C1, Constant *C2);
+ Constant *ConstantFoldGetElementPtr(LLVMContext &Context, Constant *C,
+ bool inBounds,
Constant* const *Idxs, unsigned NumIdx);
} // End llvm namespace
diff --git a/libclamav/c++/llvm/lib/VMCore/Constants.cpp b/libclamav/c++/llvm/lib/VMCore/Constants.cpp
index fd32661..2da95b0 100644
--- a/libclamav/c++/llvm/lib/VMCore/Constants.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/Constants.cpp
@@ -28,6 +28,7 @@
#include "llvm/Support/ManagedStatic.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/System/Mutex.h"
#include "llvm/System/RWMutex.h"
#include "llvm/System/Threading.h"
@@ -435,6 +436,12 @@ ConstantFP* ConstantFP::get(LLVMContext &Context, const APFloat& V) {
return Slot;
}
+ConstantFP *ConstantFP::getInfinity(const Type *Ty, bool Negative) {
+ const fltSemantics &Semantics = *TypeToFloatSemantics(Ty);
+ return ConstantFP::get(Ty->getContext(),
+ APFloat::getInf(Semantics, Negative));
+}
+
ConstantFP::ConstantFP(const Type *Ty, const APFloat& V)
: Constant(Ty, ConstantFPVal, 0, 0), Val(V) {
assert(&V.getSemantics() == TypeToFloatSemantics(Ty) &&
@@ -475,6 +482,10 @@ ConstantArray::ConstantArray(const ArrayType *T,
Constant *ConstantArray::get(const ArrayType *Ty,
const std::vector<Constant*> &V) {
+ for (unsigned i = 0, e = V.size(); i != e; ++i) {
+ assert(V[i]->getType() == Ty->getElementType() &&
+ "Wrong type in array element initializer");
+ }
LLVMContextImpl *pImpl = Ty->getContext().pImpl;
// If this is an all-zero array, return a ConstantAggregateZero object
if (!V.empty()) {
@@ -632,21 +643,18 @@ Constant* ConstantVector::get(Constant* const* Vals, unsigned NumVals) {
}
Constant* ConstantExpr::getNSWAdd(Constant* C1, Constant* C2) {
- Constant *C = getAdd(C1, C2);
- // Set nsw attribute, assuming constant folding didn't eliminate the
- // Add.
- if (AddOperator *Add = dyn_cast<AddOperator>(C))
- Add->setHasNoSignedWrap(true);
- return C;
+ return getTy(C1->getType(), Instruction::Add, C1, C2,
+ OverflowingBinaryOperator::NoSignedWrap);
+}
+
+Constant* ConstantExpr::getNSWSub(Constant* C1, Constant* C2) {
+ return getTy(C1->getType(), Instruction::Sub, C1, C2,
+ OverflowingBinaryOperator::NoSignedWrap);
}
Constant* ConstantExpr::getExactSDiv(Constant* C1, Constant* C2) {
- Constant *C = getSDiv(C1, C2);
- // Set exact attribute, assuming constant folding didn't eliminate the
- // SDiv.
- if (SDivOperator *SDiv = dyn_cast<SDivOperator>(C))
- SDiv->setIsExact(true);
- return C;
+ return getTy(C1->getType(), Instruction::SDiv, C1, C2,
+ SDivOperator::IsExact);
}
// Utility function for determining if a ConstantExpr is a CastOp or not. This
@@ -660,6 +668,31 @@ bool ConstantExpr::isCompare() const {
return getOpcode() == Instruction::ICmp || getOpcode() == Instruction::FCmp;
}
+bool ConstantExpr::isGEPWithNoNotionalOverIndexing() const {
+ if (getOpcode() != Instruction::GetElementPtr) return false;
+
+ gep_type_iterator GEPI = gep_type_begin(this), E = gep_type_end(this);
+ User::const_op_iterator OI = next(this->op_begin());
+
+ // Skip the first index, as it has no static limit.
+ ++GEPI;
+ ++OI;
+
+ // The remaining indices must be compile-time known integers within the
+ // bounds of the corresponding notional static array types.
+ for (; GEPI != E; ++GEPI, ++OI) {
+ ConstantInt *CI = dyn_cast<ConstantInt>(*OI);
+ if (!CI) return false;
+ if (const ArrayType *ATy = dyn_cast<ArrayType>(*GEPI))
+ if (CI->getValue().getActiveBits() > 64 ||
+ CI->getZExtValue() >= ATy->getNumElements())
+ return false;
+ }
+
+ // All the indices checked out.
+ return true;
+}
+
bool ConstantExpr::hasIndices() const {
return getOpcode() == Instruction::ExtractValue ||
getOpcode() == Instruction::InsertValue;
@@ -729,15 +762,19 @@ ConstantExpr::getWithOperandReplaced(unsigned OpNo, Constant *Op) const {
for (unsigned i = 1, e = getNumOperands(); i != e; ++i)
Ops[i-1] = getOperand(i);
if (OpNo == 0)
- return ConstantExpr::getGetElementPtr(Op, &Ops[0], Ops.size());
+ return cast<GEPOperator>(this)->isInBounds() ?
+ ConstantExpr::getInBoundsGetElementPtr(Op, &Ops[0], Ops.size()) :
+ ConstantExpr::getGetElementPtr(Op, &Ops[0], Ops.size());
Ops[OpNo-1] = Op;
- return ConstantExpr::getGetElementPtr(getOperand(0), &Ops[0], Ops.size());
+ return cast<GEPOperator>(this)->isInBounds() ?
+ ConstantExpr::getInBoundsGetElementPtr(getOperand(0), &Ops[0], Ops.size()) :
+ ConstantExpr::getGetElementPtr(getOperand(0), &Ops[0], Ops.size());
}
default:
assert(getNumOperands() == 2 && "Must be binary operator?");
Op0 = (OpNo == 0) ? Op : getOperand(0);
Op1 = (OpNo == 1) ? Op : getOperand(1);
- return ConstantExpr::get(getOpcode(), Op0, Op1);
+ return ConstantExpr::get(getOpcode(), Op0, Op1, SubclassData);
}
}
@@ -779,13 +816,15 @@ getWithOperands(Constant* const *Ops, unsigned NumOps) const {
case Instruction::ShuffleVector:
return ConstantExpr::getShuffleVector(Ops[0], Ops[1], Ops[2]);
case Instruction::GetElementPtr:
- return ConstantExpr::getGetElementPtr(Ops[0], &Ops[1], NumOps-1);
+ return cast<GEPOperator>(this)->isInBounds() ?
+ ConstantExpr::getInBoundsGetElementPtr(Ops[0], &Ops[1], NumOps-1) :
+ ConstantExpr::getGetElementPtr(Ops[0], &Ops[1], NumOps-1);
case Instruction::ICmp:
case Instruction::FCmp:
return ConstantExpr::getCompare(getPredicate(), Ops[0], Ops[1]);
default:
assert(getNumOperands() == 2 && "Must be binary operator?");
- return ConstantExpr::get(getOpcode(), Ops[0], Ops[1]);
+ return ConstantExpr::get(getOpcode(), Ops[0], Ops[1], SubclassData);
}
}
@@ -854,8 +893,6 @@ bool ConstantFP::isValueValidForType(const Type *Ty, const APFloat& Val) {
//===----------------------------------------------------------------------===//
// Factory Function Implementation
-static char getValType(ConstantAggregateZero *CPZ) { return 0; }
-
ConstantAggregateZero* ConstantAggregateZero::get(const Type* Ty) {
assert((isa<StructType>(Ty) || isa<ArrayType>(Ty) || isa<VectorType>(Ty)) &&
"Cannot create an aggregate zero of non-aggregate type!");
@@ -984,11 +1021,6 @@ Constant *ConstantVector::getSplatValue() {
//---- ConstantPointerNull::get() implementation...
//
-static char getValType(ConstantPointerNull *) {
- return 0;
-}
-
-
ConstantPointerNull *ConstantPointerNull::get(const PointerType *Ty) {
// Implicitly locked.
return Ty->getContext().pImpl->NullPtrConstants.getOrCreate(Ty, 0);
@@ -1006,10 +1038,6 @@ void ConstantPointerNull::destroyConstant() {
//---- UndefValue::get() implementation...
//
-static char getValType(UndefValue *) {
- return 0;
-}
-
UndefValue *UndefValue::get(const Type *Ty) {
// Implicitly locked.
return Ty->getContext().pImpl->UndefValueConstants.getOrCreate(Ty, 0);
@@ -1026,17 +1054,6 @@ void UndefValue::destroyConstant() {
//---- ConstantExpr::get() implementations...
//
-static ExprMapKeyType getValType(ConstantExpr *CE) {
- std::vector<Constant*> Operands;
- Operands.reserve(CE->getNumOperands());
- for (unsigned i = 0, e = CE->getNumOperands(); i != e; ++i)
- Operands.push_back(cast<Constant>(CE->getOperand(i)));
- return ExprMapKeyType(CE->getOpcode(), Operands,
- CE->isCompare() ? CE->getPredicate() : 0,
- CE->hasIndices() ?
- CE->getIndices() : SmallVector<unsigned, 4>());
-}
-
/// This is a utility function to handle folding of casts and lookup of the
/// cast in the ExprConstants map. It is used by the various get* methods below.
static inline Constant *getFoldedCast(
@@ -1280,7 +1297,8 @@ Constant *ConstantExpr::getBitCast(Constant *C, const Type *DstTy) {
}
Constant *ConstantExpr::getTy(const Type *ReqTy, unsigned Opcode,
- Constant *C1, Constant *C2) {
+ Constant *C1, Constant *C2,
+ unsigned Flags) {
// Check the operands for consistency first
assert(Opcode >= Instruction::BinaryOpsBegin &&
Opcode < Instruction::BinaryOpsEnd &&
@@ -1294,7 +1312,7 @@ Constant *ConstantExpr::getTy(const Type *ReqTy, unsigned Opcode,
return FC; // Fold a few common cases...
std::vector<Constant*> argVec(1, C1); argVec.push_back(C2);
- ExprMapKeyType Key(Opcode, argVec);
+ ExprMapKeyType Key(Opcode, argVec, 0, Flags);
LLVMContextImpl *pImpl = ReqTy->getContext().pImpl;
@@ -1322,7 +1340,8 @@ Constant *ConstantExpr::getCompareTy(unsigned short predicate,
}
}
-Constant *ConstantExpr::get(unsigned Opcode, Constant *C1, Constant *C2) {
+Constant *ConstantExpr::get(unsigned Opcode, Constant *C1, Constant *C2,
+ unsigned Flags) {
// API compatibility: Adjust integer opcodes to floating-point opcodes.
if (C1->getType()->isFPOrFPVector()) {
if (Opcode == Instruction::Add) Opcode = Instruction::FAdd;
@@ -1387,7 +1406,7 @@ Constant *ConstantExpr::get(unsigned Opcode, Constant *C1, Constant *C2) {
}
#endif
- return getTy(C1->getType(), Opcode, C1, C2);
+ return getTy(C1->getType(), Opcode, C1, C2, Flags);
}
Constant* ConstantExpr::getSizeOf(const Type* Ty) {
@@ -1462,7 +1481,8 @@ Constant *ConstantExpr::getGetElementPtrTy(const Type *ReqTy, Constant *C,
"GEP indices invalid!");
if (Constant *FC = ConstantFoldGetElementPtr(
- ReqTy->getContext(), C, (Constant**)Idxs, NumIdx))
+ ReqTy->getContext(), C, /*inBounds=*/false,
+ (Constant**)Idxs, NumIdx))
return FC; // Fold a few common cases...
assert(isa<PointerType>(C->getType()) &&
@@ -1481,6 +1501,37 @@ Constant *ConstantExpr::getGetElementPtrTy(const Type *ReqTy, Constant *C,
return pImpl->ExprConstants.getOrCreate(ReqTy, Key);
}
+Constant *ConstantExpr::getInBoundsGetElementPtrTy(const Type *ReqTy,
+ Constant *C,
+ Value* const *Idxs,
+ unsigned NumIdx) {
+ assert(GetElementPtrInst::getIndexedType(C->getType(), Idxs,
+ Idxs+NumIdx) ==
+ cast<PointerType>(ReqTy)->getElementType() &&
+ "GEP indices invalid!");
+
+ if (Constant *FC = ConstantFoldGetElementPtr(
+ ReqTy->getContext(), C, /*inBounds=*/true,
+ (Constant**)Idxs, NumIdx))
+ return FC; // Fold a few common cases...
+
+ assert(isa<PointerType>(C->getType()) &&
+ "Non-pointer type for constant GetElementPtr expression");
+ // Look up the constant in the table first to ensure uniqueness
+ std::vector<Constant*> ArgVec;
+ ArgVec.reserve(NumIdx+1);
+ ArgVec.push_back(C);
+ for (unsigned i = 0; i != NumIdx; ++i)
+ ArgVec.push_back(cast<Constant>(Idxs[i]));
+ const ExprMapKeyType Key(Instruction::GetElementPtr, ArgVec, 0,
+ GEPOperator::IsInBounds);
+
+ LLVMContextImpl *pImpl = ReqTy->getContext().pImpl;
+
+ // Implicitly locked.
+ return pImpl->ExprConstants.getOrCreate(ReqTy, Key);
+}
+
Constant *ConstantExpr::getGetElementPtr(Constant *C, Value* const *Idxs,
unsigned NumIdx) {
// Get the result type of the getelementptr!
@@ -1494,12 +1545,12 @@ Constant *ConstantExpr::getGetElementPtr(Constant *C, Value* const *Idxs,
Constant *ConstantExpr::getInBoundsGetElementPtr(Constant *C,
Value* const *Idxs,
unsigned NumIdx) {
- Constant *Result = getGetElementPtr(C, Idxs, NumIdx);
- // Set in bounds attribute, assuming constant folding didn't eliminate the
- // GEP.
- if (GEPOperator *GEP = dyn_cast<GEPOperator>(Result))
- GEP->setIsInBounds(true);
- return Result;
+ // Get the result type of the getelementptr!
+ const Type *Ty =
+ GetElementPtrInst::getIndexedType(C->getType(), Idxs, Idxs+NumIdx);
+ assert(Ty && "GEP indices invalid!");
+ unsigned As = cast<PointerType>(C->getType())->getAddressSpace();
+ return getInBoundsGetElementPtrTy(PointerType::get(Ty, As), C, Idxs, NumIdx);
}
Constant *ConstantExpr::getGetElementPtr(Constant *C, Constant* const *Idxs,
@@ -1819,15 +1870,6 @@ const char *ConstantExpr::getOpcodeName() const {
/// work, but would be really slow because it would have to unique each updated
/// array instance.
-static std::vector<Constant*> getValType(ConstantArray *CA) {
- std::vector<Constant*> Elements;
- Elements.reserve(CA->getNumOperands());
- for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i)
- Elements.push_back(cast<Constant>(CA->getOperand(i)));
- return Elements;
-}
-
-
void ConstantArray::replaceUsesOfWithOnConstant(Value *From, Value *To,
Use *U) {
assert(isa<Constant>(To) && "Cannot make Constant refer to non-constant!");
@@ -1836,7 +1878,7 @@ void ConstantArray::replaceUsesOfWithOnConstant(Value *From, Value *To,
LLVMContext &Context = getType()->getContext();
LLVMContextImpl *pImpl = Context.pImpl;
- std::pair<LLVMContextImpl::ArrayConstantsTy::MapKey, Constant*> Lookup;
+ std::pair<LLVMContextImpl::ArrayConstantsTy::MapKey, ConstantArray*> Lookup;
Lookup.first.first = getType();
Lookup.second = this;
@@ -1880,7 +1922,7 @@ void ConstantArray::replaceUsesOfWithOnConstant(Value *From, Value *To,
pImpl->ArrayConstants.InsertOrGetItem(Lookup, Exists);
if (Exists) {
- Replacement = cast<Constant>(I->second);
+ Replacement = I->second;
} else {
// Okay, the new shape doesn't exist in the system yet. Instead of
// creating a new constant array, inserting it, replaceallusesof'ing the
@@ -1914,14 +1956,6 @@ void ConstantArray::replaceUsesOfWithOnConstant(Value *From, Value *To,
destroyConstant();
}
-static std::vector<Constant*> getValType(ConstantStruct *CS) {
- std::vector<Constant*> Elements;
- Elements.reserve(CS->getNumOperands());
- for (unsigned i = 0, e = CS->getNumOperands(); i != e; ++i)
- Elements.push_back(cast<Constant>(CS->getOperand(i)));
- return Elements;
-}
-
void ConstantStruct::replaceUsesOfWithOnConstant(Value *From, Value *To,
Use *U) {
assert(isa<Constant>(To) && "Cannot make Constant refer to non-constant!");
@@ -1930,7 +1964,7 @@ void ConstantStruct::replaceUsesOfWithOnConstant(Value *From, Value *To,
unsigned OperandToUpdate = U-OperandList;
assert(getOperand(OperandToUpdate) == From && "ReplaceAllUsesWith broken!");
- std::pair<LLVMContextImpl::StructConstantsTy::MapKey, Constant*> Lookup;
+ std::pair<LLVMContextImpl::StructConstantsTy::MapKey, ConstantStruct*> Lookup;
Lookup.first.first = getType();
Lookup.second = this;
std::vector<Constant*> &Values = Lookup.first.second;
@@ -1967,7 +2001,7 @@ void ConstantStruct::replaceUsesOfWithOnConstant(Value *From, Value *To,
pImpl->StructConstants.InsertOrGetItem(Lookup, Exists);
if (Exists) {
- Replacement = cast<Constant>(I->second);
+ Replacement = I->second;
} else {
// Okay, the new shape doesn't exist in the system yet. Instead of
// creating a new constant struct, inserting it, replaceallusesof'ing the
@@ -1990,14 +2024,6 @@ void ConstantStruct::replaceUsesOfWithOnConstant(Value *From, Value *To,
destroyConstant();
}
-static std::vector<Constant*> getValType(ConstantVector *CP) {
- std::vector<Constant*> Elements;
- Elements.reserve(CP->getNumOperands());
- for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i)
- Elements.push_back(CP->getOperand(i));
- return Elements;
-}
-
void ConstantVector::replaceUsesOfWithOnConstant(Value *From, Value *To,
Use *U) {
assert(isa<Constant>(To) && "Cannot make Constant refer to non-constant!");
@@ -2104,7 +2130,7 @@ void ConstantExpr::replaceUsesOfWithOnConstant(Value *From, Value *ToV,
Constant *C2 = getOperand(1);
if (C1 == From) C1 = To;
if (C2 == From) C2 = To;
- Replacement = ConstantExpr::get(getOpcode(), C1, C2);
+ Replacement = ConstantExpr::get(getOpcode(), C1, C2, SubclassData);
} else {
llvm_unreachable("Unknown ConstantExpr type!");
return;
@@ -2118,4 +2144,3 @@ void ConstantExpr::replaceUsesOfWithOnConstant(Value *From, Value *ToV,
// Delete the old constant!
destroyConstant();
}
-
diff --git a/libclamav/c++/llvm/lib/VMCore/ConstantsContext.h b/libclamav/c++/llvm/lib/VMCore/ConstantsContext.h
index f4a2cde..526b4b1 100644
--- a/libclamav/c++/llvm/lib/VMCore/ConstantsContext.h
+++ b/libclamav/c++/llvm/lib/VMCore/ConstantsContext.h
@@ -16,7 +16,6 @@
#define LLVM_CONSTANTSCONTEXT_H
#include "llvm/Instructions.h"
-#include "llvm/Metadata.h"
#include "llvm/Operator.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
@@ -54,10 +53,12 @@ public:
void *operator new(size_t s) {
return User::operator new(s, 2);
}
- BinaryConstantExpr(unsigned Opcode, Constant *C1, Constant *C2)
+ BinaryConstantExpr(unsigned Opcode, Constant *C1, Constant *C2,
+ unsigned Flags)
: ConstantExpr(C1->getType(), Opcode, &Op<0>(), 2) {
Op<0>() = C1;
Op<1>() = C2;
+ SubclassOptionalData = Flags;
}
/// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
@@ -207,9 +208,12 @@ class GetElementPtrConstantExpr : public ConstantExpr {
public:
static GetElementPtrConstantExpr *Create(Constant *C,
const std::vector<Constant*>&IdxList,
- const Type *DestTy) {
- return
+ const Type *DestTy,
+ unsigned Flags) {
+ GetElementPtrConstantExpr *Result =
new(IdxList.size() + 1) GetElementPtrConstantExpr(C, IdxList, DestTy);
+ Result->SubclassOptionalData = Flags;
+ return Result;
}
/// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
@@ -236,54 +240,54 @@ struct CompareConstantExpr : public ConstantExpr {
};
template <>
-struct OperandTraits<UnaryConstantExpr> : FixedNumOperandTraits<1> {
+struct OperandTraits<UnaryConstantExpr> : public FixedNumOperandTraits<1> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(UnaryConstantExpr, Value)
template <>
-struct OperandTraits<BinaryConstantExpr> : FixedNumOperandTraits<2> {
+struct OperandTraits<BinaryConstantExpr> : public FixedNumOperandTraits<2> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BinaryConstantExpr, Value)
template <>
-struct OperandTraits<SelectConstantExpr> : FixedNumOperandTraits<3> {
+struct OperandTraits<SelectConstantExpr> : public FixedNumOperandTraits<3> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SelectConstantExpr, Value)
template <>
-struct OperandTraits<ExtractElementConstantExpr> : FixedNumOperandTraits<2> {
+struct OperandTraits<ExtractElementConstantExpr> : public FixedNumOperandTraits<2> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ExtractElementConstantExpr, Value)
template <>
-struct OperandTraits<InsertElementConstantExpr> : FixedNumOperandTraits<3> {
+struct OperandTraits<InsertElementConstantExpr> : public FixedNumOperandTraits<3> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InsertElementConstantExpr, Value)
template <>
-struct OperandTraits<ShuffleVectorConstantExpr> : FixedNumOperandTraits<3> {
+struct OperandTraits<ShuffleVectorConstantExpr> : public FixedNumOperandTraits<3> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ShuffleVectorConstantExpr, Value)
template <>
-struct OperandTraits<ExtractValueConstantExpr> : FixedNumOperandTraits<1> {
+struct OperandTraits<ExtractValueConstantExpr> : public FixedNumOperandTraits<1> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ExtractValueConstantExpr, Value)
template <>
-struct OperandTraits<InsertValueConstantExpr> : FixedNumOperandTraits<2> {
+struct OperandTraits<InsertValueConstantExpr> : public FixedNumOperandTraits<2> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InsertValueConstantExpr, Value)
template <>
-struct OperandTraits<GetElementPtrConstantExpr> : VariadicOperandTraits<1> {
+struct OperandTraits<GetElementPtrConstantExpr> : public VariadicOperandTraits<1> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GetElementPtrConstantExpr, Value)
template <>
-struct OperandTraits<CompareConstantExpr> : FixedNumOperandTraits<2> {
+struct OperandTraits<CompareConstantExpr> : public FixedNumOperandTraits<2> {
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CompareConstantExpr, Value)
@@ -292,26 +296,32 @@ struct ExprMapKeyType {
ExprMapKeyType(unsigned opc,
const std::vector<Constant*> &ops,
- unsigned short pred = 0,
+ unsigned short flags = 0,
+ unsigned short optionalflags = 0,
const IndexList &inds = IndexList())
- : opcode(opc), predicate(pred), operands(ops), indices(inds) {}
- uint16_t opcode;
- uint16_t predicate;
+ : opcode(opc), subclassoptionaldata(optionalflags), subclassdata(flags),
+ operands(ops), indices(inds) {}
+ uint8_t opcode;
+ uint8_t subclassoptionaldata;
+ uint16_t subclassdata;
std::vector<Constant*> operands;
IndexList indices;
bool operator==(const ExprMapKeyType& that) const {
return this->opcode == that.opcode &&
- this->predicate == that.predicate &&
+ this->subclassdata == that.subclassdata &&
+ this->subclassoptionaldata == that.subclassoptionaldata &&
this->operands == that.operands &&
this->indices == that.indices;
}
bool operator<(const ExprMapKeyType & that) const {
- return this->opcode < that.opcode ||
- (this->opcode == that.opcode && this->predicate < that.predicate) ||
- (this->opcode == that.opcode && this->predicate == that.predicate &&
- this->operands < that.operands) ||
- (this->opcode == that.opcode && this->predicate == that.predicate &&
- this->operands == that.operands && this->indices < that.indices);
+ if (this->opcode != that.opcode) return this->opcode < that.opcode;
+ if (this->operands != that.operands) return this->operands < that.operands;
+ if (this->subclassdata != that.subclassdata)
+ return this->subclassdata < that.subclassdata;
+ if (this->subclassoptionaldata != that.subclassoptionaldata)
+ return this->subclassoptionaldata < that.subclassoptionaldata;
+ if (this->indices != that.indices) return this->indices < that.indices;
+ return false;
}
bool operator!=(const ExprMapKeyType& that) const {
@@ -340,10 +350,11 @@ struct ConstantCreator {
}
};
-template<class ConstantClass, class TypeClass>
-struct ConvertConstant {
- static void convert(ConstantClass *OldC, const TypeClass *NewTy) {
- llvm_unreachable("This type cannot be converted!");
+template<class ConstantClass>
+struct ConstantKeyData {
+ typedef void ValType;
+ static ValType getValType(ConstantClass *C) {
+ llvm_unreachable("Unknown Constant type!");
}
};
@@ -355,7 +366,8 @@ struct ConstantCreator<ConstantExpr, Type, ExprMapKeyType> {
return new UnaryConstantExpr(V.opcode, V.operands[0], Ty);
if ((V.opcode >= Instruction::BinaryOpsBegin &&
V.opcode < Instruction::BinaryOpsEnd))
- return new BinaryConstantExpr(V.opcode, V.operands[0], V.operands[1]);
+ return new BinaryConstantExpr(V.opcode, V.operands[0], V.operands[1],
+ V.subclassoptionaldata);
if (V.opcode == Instruction::Select)
return new SelectConstantExpr(V.operands[0], V.operands[1],
V.operands[2]);
@@ -374,17 +386,18 @@ struct ConstantCreator<ConstantExpr, Type, ExprMapKeyType> {
return new ExtractValueConstantExpr(V.operands[0], V.indices, Ty);
if (V.opcode == Instruction::GetElementPtr) {
std::vector<Constant*> IdxList(V.operands.begin()+1, V.operands.end());
- return GetElementPtrConstantExpr::Create(V.operands[0], IdxList, Ty);
+ return GetElementPtrConstantExpr::Create(V.operands[0], IdxList, Ty,
+ V.subclassoptionaldata);
}
// The compare instructions are weird. We have to encode the predicate
// value and it is combined with the instruction opcode by multiplying
// the opcode by one hundred. We must decode this to get the predicate.
if (V.opcode == Instruction::ICmp)
- return new CompareConstantExpr(Ty, Instruction::ICmp, V.predicate,
+ return new CompareConstantExpr(Ty, Instruction::ICmp, V.subclassdata,
V.operands[0], V.operands[1]);
if (V.opcode == Instruction::FCmp)
- return new CompareConstantExpr(Ty, Instruction::FCmp, V.predicate,
+ return new CompareConstantExpr(Ty, Instruction::FCmp, V.subclassdata,
V.operands[0], V.operands[1]);
llvm_unreachable("Invalid ConstantExpr!");
return 0;
@@ -392,47 +405,18 @@ struct ConstantCreator<ConstantExpr, Type, ExprMapKeyType> {
};
template<>
-struct ConvertConstant<ConstantExpr, Type> {
- static void convert(ConstantExpr *OldC, const Type *NewTy) {
- Constant *New;
- switch (OldC->getOpcode()) {
- case Instruction::Trunc:
- case Instruction::ZExt:
- case Instruction::SExt:
- case Instruction::FPTrunc:
- case Instruction::FPExt:
- case Instruction::UIToFP:
- case Instruction::SIToFP:
- case Instruction::FPToUI:
- case Instruction::FPToSI:
- case Instruction::PtrToInt:
- case Instruction::IntToPtr:
- case Instruction::BitCast:
- New = ConstantExpr::getCast(OldC->getOpcode(), OldC->getOperand(0),
- NewTy);
- break;
- case Instruction::Select:
- New = ConstantExpr::getSelectTy(NewTy, OldC->getOperand(0),
- OldC->getOperand(1),
- OldC->getOperand(2));
- break;
- default:
- assert(OldC->getOpcode() >= Instruction::BinaryOpsBegin &&
- OldC->getOpcode() < Instruction::BinaryOpsEnd);
- New = ConstantExpr::getTy(NewTy, OldC->getOpcode(), OldC->getOperand(0),
- OldC->getOperand(1));
- break;
- case Instruction::GetElementPtr:
- // Make everyone now use a constant of the new type...
- std::vector<Value*> Idx(OldC->op_begin()+1, OldC->op_end());
- New = ConstantExpr::getGetElementPtrTy(NewTy, OldC->getOperand(0),
- &Idx[0], Idx.size());
- break;
- }
-
- assert(New != OldC && "Didn't replace constant??");
- OldC->uncheckedReplaceAllUsesWith(New);
- OldC->destroyConstant(); // This constant is now dead, destroy it.
+struct ConstantKeyData<ConstantExpr> {
+ typedef ExprMapKeyType ValType;
+ static ValType getValType(ConstantExpr *CE) {
+ std::vector<Constant*> Operands;
+ Operands.reserve(CE->getNumOperands());
+ for (unsigned i = 0, e = CE->getNumOperands(); i != e; ++i)
+ Operands.push_back(cast<Constant>(CE->getOperand(i)));
+ return ExprMapKeyType(CE->getOpcode(), Operands,
+ CE->isCompare() ? CE->getPredicate() : 0,
+ CE->getRawSubclassOptionalData(),
+ CE->hasIndices() ?
+ CE->getIndices() : SmallVector<unsigned, 4>());
}
};
@@ -445,63 +429,46 @@ struct ConstantCreator<ConstantAggregateZero, Type, ValType> {
};
template<>
-struct ConstantCreator<MDNode, Type, std::vector<Value*> > {
- static MDNode *create(const Type* Ty, const std::vector<Value*> &V) {
- return new MDNode(Ty->getContext(), &V[0], V.size());
- }
-};
-
-template<>
-struct ConvertConstant<ConstantVector, VectorType> {
- static void convert(ConstantVector *OldC, const VectorType *NewTy) {
- // Make everyone now use a constant of the new type...
- std::vector<Constant*> C;
- for (unsigned i = 0, e = OldC->getNumOperands(); i != e; ++i)
- C.push_back(cast<Constant>(OldC->getOperand(i)));
- Constant *New = ConstantVector::get(NewTy, C);
- assert(New != OldC && "Didn't replace constant??");
- OldC->uncheckedReplaceAllUsesWith(New);
- OldC->destroyConstant(); // This constant is now dead, destroy it.
+struct ConstantKeyData<ConstantVector> {
+ typedef std::vector<Constant*> ValType;
+ static ValType getValType(ConstantVector *CP) {
+ std::vector<Constant*> Elements;
+ Elements.reserve(CP->getNumOperands());
+ for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i)
+ Elements.push_back(CP->getOperand(i));
+ return Elements;
}
};
template<>
-struct ConvertConstant<ConstantAggregateZero, Type> {
- static void convert(ConstantAggregateZero *OldC, const Type *NewTy) {
- // Make everyone now use a constant of the new type...
- Constant *New = ConstantAggregateZero::get(NewTy);
- assert(New != OldC && "Didn't replace constant??");
- OldC->uncheckedReplaceAllUsesWith(New);
- OldC->destroyConstant(); // This constant is now dead, destroy it.
+struct ConstantKeyData<ConstantAggregateZero> {
+ typedef char ValType;
+ static ValType getValType(ConstantAggregateZero *C) {
+ return 0;
}
};
template<>
-struct ConvertConstant<ConstantArray, ArrayType> {
- static void convert(ConstantArray *OldC, const ArrayType *NewTy) {
- // Make everyone now use a constant of the new type...
- std::vector<Constant*> C;
- for (unsigned i = 0, e = OldC->getNumOperands(); i != e; ++i)
- C.push_back(cast<Constant>(OldC->getOperand(i)));
- Constant *New = ConstantArray::get(NewTy, C);
- assert(New != OldC && "Didn't replace constant??");
- OldC->uncheckedReplaceAllUsesWith(New);
- OldC->destroyConstant(); // This constant is now dead, destroy it.
+struct ConstantKeyData<ConstantArray> {
+ typedef std::vector<Constant*> ValType;
+ static ValType getValType(ConstantArray *CA) {
+ std::vector<Constant*> Elements;
+ Elements.reserve(CA->getNumOperands());
+ for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i)
+ Elements.push_back(cast<Constant>(CA->getOperand(i)));
+ return Elements;
}
};
template<>
-struct ConvertConstant<ConstantStruct, StructType> {
- static void convert(ConstantStruct *OldC, const StructType *NewTy) {
- // Make everyone now use a constant of the new type...
- std::vector<Constant*> C;
- for (unsigned i = 0, e = OldC->getNumOperands(); i != e; ++i)
- C.push_back(cast<Constant>(OldC->getOperand(i)));
- Constant *New = ConstantStruct::get(NewTy, C);
- assert(New != OldC && "Didn't replace constant??");
-
- OldC->uncheckedReplaceAllUsesWith(New);
- OldC->destroyConstant(); // This constant is now dead, destroy it.
+struct ConstantKeyData<ConstantStruct> {
+ typedef std::vector<Constant*> ValType;
+ static ValType getValType(ConstantStruct *CS) {
+ std::vector<Constant*> Elements;
+ Elements.reserve(CS->getNumOperands());
+ for (unsigned i = 0, e = CS->getNumOperands(); i != e; ++i)
+ Elements.push_back(cast<Constant>(CS->getOperand(i)));
+ return Elements;
}
};
@@ -514,13 +481,10 @@ struct ConstantCreator<ConstantPointerNull, PointerType, ValType> {
};
template<>
-struct ConvertConstant<ConstantPointerNull, PointerType> {
- static void convert(ConstantPointerNull *OldC, const PointerType *NewTy) {
- // Make everyone now use a constant of the new type...
- Constant *New = ConstantPointerNull::get(NewTy);
- assert(New != OldC && "Didn't replace constant??");
- OldC->uncheckedReplaceAllUsesWith(New);
- OldC->destroyConstant(); // This constant is now dead, destroy it.
+struct ConstantKeyData<ConstantPointerNull> {
+ typedef char ValType;
+ static ValType getValType(ConstantPointerNull *C) {
+ return 0;
}
};
@@ -533,13 +497,10 @@ struct ConstantCreator<UndefValue, Type, ValType> {
};
template<>
-struct ConvertConstant<UndefValue, Type> {
- static void convert(UndefValue *OldC, const Type *NewTy) {
- // Make everyone now use a constant of the new type.
- Constant *New = UndefValue::get(NewTy);
- assert(New != OldC && "Didn't replace constant??");
- OldC->uncheckedReplaceAllUsesWith(New);
- OldC->destroyConstant(); // This constant is now dead, destroy it.
+struct ConstantKeyData<UndefValue> {
+ typedef char ValType;
+ static ValType getValType(UndefValue *C) {
+ return 0;
}
};
@@ -547,10 +508,11 @@ template<class ValType, class TypeClass, class ConstantClass,
bool HasLargeKey = false /*true for arrays and structs*/ >
class ValueMap : public AbstractTypeUser {
public:
- typedef std::pair<const Type*, ValType> MapKey;
- typedef std::map<MapKey, Value *> MapTy;
- typedef std::map<Value*, typename MapTy::iterator> InverseMapTy;
- typedef std::map<const Type*, typename MapTy::iterator> AbstractTypeMapTy;
+ typedef std::pair<const TypeClass*, ValType> MapKey;
+ typedef std::map<MapKey, ConstantClass *> MapTy;
+ typedef std::map<ConstantClass *, typename MapTy::iterator> InverseMapTy;
+ typedef std::map<const DerivedType*, typename MapTy::iterator>
+ AbstractTypeMapTy;
private:
/// Map - This is the main map from the element descriptor to the Constants.
/// This is the primary way we avoid creating two of the same shape
@@ -591,7 +553,7 @@ public:
/// I->second == 0, and should be filled in.
/// NOTE: This function is not locked. It is the caller's responsibility
// to enforce proper synchronization.
- typename MapTy::iterator InsertOrGetItem(std::pair<MapKey, Constant *>
+ typename MapTy::iterator InsertOrGetItem(std::pair<MapKey, ConstantClass *>
&InsertVal,
bool &Exists) {
std::pair<typename MapTy::iterator, bool> IP = Map.insert(InsertVal);
@@ -611,7 +573,7 @@ private:
typename MapTy::iterator I =
Map.find(MapKey(static_cast<const TypeClass*>(CP->getRawType()),
- getValType(CP)));
+ ConstantKeyData<ConstantClass>::getValType(CP)));
if (I == Map.end() || I->second != CP) {
// FIXME: This should not use a linear scan. If this gets to be a
// performance problem, someone should look at this.
@@ -621,6 +583,22 @@ private:
return I;
}
+ void AddAbstractTypeUser(const Type *Ty, typename MapTy::iterator I) {
+ // If the type of the constant is abstract, make sure that an entry
+ // exists for it in the AbstractTypeMap.
+ if (Ty->isAbstract()) {
+ const DerivedType *DTy = static_cast<const DerivedType *>(Ty);
+ typename AbstractTypeMapTy::iterator TI = AbstractTypeMap.find(DTy);
+
+ if (TI == AbstractTypeMap.end()) {
+ // Add ourselves to the ATU list of the type.
+ cast<DerivedType>(DTy)->addAbstractTypeUser(this);
+
+ AbstractTypeMap.insert(TI, std::make_pair(DTy, I));
+ }
+ }
+ }
+
ConstantClass* Create(const TypeClass *Ty, const ValType &V,
typename MapTy::iterator I) {
ConstantClass* Result =
@@ -632,19 +610,7 @@ private:
if (HasLargeKey) // Remember the reverse mapping if needed.
InverseMap.insert(std::make_pair(Result, I));
- // If the type of the constant is abstract, make sure that an entry
- // exists for it in the AbstractTypeMap.
- if (Ty->isAbstract()) {
- typename AbstractTypeMapTy::iterator TI =
- AbstractTypeMap.find(Ty);
-
- if (TI == AbstractTypeMap.end()) {
- // Add ourselves to the ATU list of the type.
- cast<DerivedType>(Ty)->addAbstractTypeUser(this);
-
- AbstractTypeMap.insert(TI, std::make_pair(Ty, I));
- }
- }
+ AddAbstractTypeUser(Ty, I);
return Result;
}
@@ -660,7 +626,7 @@ public:
typename MapTy::iterator I = Map.find(Lookup);
// Is it in the map?
if (I != Map.end())
- Result = static_cast<ConstantClass *>(I->second);
+ Result = I->second;
if (!Result) {
// If no preexisting value, create one now...
@@ -670,6 +636,43 @@ public:
return Result;
}
+ void UpdateAbstractTypeMap(const DerivedType *Ty,
+ typename MapTy::iterator I) {
+ assert(AbstractTypeMap.count(Ty) &&
+ "Abstract type not in AbstractTypeMap?");
+ typename MapTy::iterator &ATMEntryIt = AbstractTypeMap[Ty];
+ if (ATMEntryIt == I) {
+ // Yes, we are removing the representative entry for this type.
+ // See if there are any other entries of the same type.
+ typename MapTy::iterator TmpIt = ATMEntryIt;
+
+ // First check the entry before this one...
+ if (TmpIt != Map.begin()) {
+ --TmpIt;
+ if (TmpIt->first.first != Ty) // Not the same type, move back...
+ ++TmpIt;
+ }
+
+ // If we didn't find the same type, try to move forward...
+ if (TmpIt == ATMEntryIt) {
+ ++TmpIt;
+ if (TmpIt == Map.end() || TmpIt->first.first != Ty)
+ --TmpIt; // No entry afterwards with the same type
+ }
+
+ // If there is another entry in the map of the same abstract type,
+ // update the AbstractTypeMap entry now.
+ if (TmpIt != ATMEntryIt) {
+ ATMEntryIt = TmpIt;
+ } else {
+ // Otherwise, we are removing the last instance of this type
+ // from the table. Remove from the ATM, and from user list.
+ cast<DerivedType>(Ty)->removeAbstractTypeUser(this);
+ AbstractTypeMap.erase(Ty);
+ }
+ }
+ }
+
void remove(ConstantClass *CP) {
sys::SmartScopedLock<true> Lock(ValueMapLock);
typename MapTy::iterator I = FindExistingElement(CP);
@@ -681,47 +684,13 @@ public:
// Now that we found the entry, make sure this isn't the entry that
// the AbstractTypeMap points to.
- const TypeClass *Ty = static_cast<const TypeClass *>(I->first.first);
- if (Ty->isAbstract()) {
- assert(AbstractTypeMap.count(Ty) &&
- "Abstract type not in AbstractTypeMap?");
- typename MapTy::iterator &ATMEntryIt = AbstractTypeMap[Ty];
- if (ATMEntryIt == I) {
- // Yes, we are removing the representative entry for this type.
- // See if there are any other entries of the same type.
- typename MapTy::iterator TmpIt = ATMEntryIt;
-
- // First check the entry before this one...
- if (TmpIt != Map.begin()) {
- --TmpIt;
- if (TmpIt->first.first != Ty) // Not the same type, move back...
- ++TmpIt;
- }
-
- // If we didn't find the same type, try to move forward...
- if (TmpIt == ATMEntryIt) {
- ++TmpIt;
- if (TmpIt == Map.end() || TmpIt->first.first != Ty)
- --TmpIt; // No entry afterwards with the same type
- }
-
- // If there is another entry in the map of the same abstract type,
- // update the AbstractTypeMap entry now.
- if (TmpIt != ATMEntryIt) {
- ATMEntryIt = TmpIt;
- } else {
- // Otherwise, we are removing the last instance of this type
- // from the table. Remove from the ATM, and from user list.
- cast<DerivedType>(Ty)->removeAbstractTypeUser(this);
- AbstractTypeMap.erase(Ty);
- }
- }
- }
+ const TypeClass *Ty = I->first.first;
+ if (Ty->isAbstract())
+ UpdateAbstractTypeMap(static_cast<const DerivedType *>(Ty), I);
Map.erase(I);
}
-
/// MoveConstantToNewSlot - If we are about to change C to be the element
/// specified by I, update our internal data structures to reflect this
/// fact.
@@ -757,8 +726,7 @@ public:
void refineAbstractType(const DerivedType *OldTy, const Type *NewTy) {
sys::SmartScopedLock<true> Lock(ValueMapLock);
- typename AbstractTypeMapTy::iterator I =
- AbstractTypeMap.find(cast<Type>(OldTy));
+ typename AbstractTypeMapTy::iterator I = AbstractTypeMap.find(OldTy);
assert(I != AbstractTypeMap.end() &&
"Abstract type not in AbstractTypeMap?");
@@ -767,11 +735,39 @@ public:
// leaving will remove() itself, causing the AbstractTypeMapEntry to be
// eliminated eventually.
do {
- ConvertConstant<ConstantClass, TypeClass>::convert(
- static_cast<ConstantClass *>(I->second->second),
- cast<TypeClass>(NewTy));
-
- I = AbstractTypeMap.find(cast<Type>(OldTy));
+ ConstantClass *C = I->second->second;
+ MapKey Key(cast<TypeClass>(NewTy),
+ ConstantKeyData<ConstantClass>::getValType(C));
+
+ std::pair<typename MapTy::iterator, bool> IP =
+ Map.insert(std::make_pair(Key, C));
+ if (IP.second) {
+ // The map didn't previously have an appropriate constant in the
+ // new type.
+
+ // Remove the old entry.
+ typename MapTy::iterator OldI =
+ Map.find(MapKey(cast<TypeClass>(OldTy), IP.first->first.second));
+ assert(OldI != Map.end() && "Constant not in map!");
+ UpdateAbstractTypeMap(OldTy, OldI);
+ Map.erase(OldI);
+
+ // Set the constant's type. This is done in place!
+ setType(C, NewTy);
+
+ // Update the inverse map so that we know that this constant is now
+ // located at descriptor I.
+ if (HasLargeKey)
+ InverseMap[C] = IP.first;
+
+ AddAbstractTypeUser(NewTy, IP.first);
+ } else {
+ // The map already had an appropriate constant in the new type, so
+ // there's no longer a need for the old constant.
+ C->uncheckedReplaceAllUsesWith(IP.first->second);
+ C->destroyConstant(); // This constant is now dead, destroy it.
+ }
+ I = AbstractTypeMap.find(OldTy);
} while (I != AbstractTypeMap.end());
}
diff --git a/libclamav/c++/llvm/lib/VMCore/Core.cpp b/libclamav/c++/llvm/lib/VMCore/Core.cpp
index b2aa9f4..77fd432 100644
--- a/libclamav/c++/llvm/lib/VMCore/Core.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/Core.cpp
@@ -1118,7 +1118,8 @@ unsigned LLVMGetFunctionCallConv(LLVMValueRef Fn) {
}
void LLVMSetFunctionCallConv(LLVMValueRef Fn, unsigned CC) {
- return unwrap<Function>(Fn)->setCallingConv(CC);
+ return unwrap<Function>(Fn)->setCallingConv(
+ static_cast<CallingConv::ID>(CC));
}
const char *LLVMGetGC(LLVMValueRef Fn) {
@@ -1362,9 +1363,9 @@ unsigned LLVMGetInstructionCallConv(LLVMValueRef Instr) {
void LLVMSetInstructionCallConv(LLVMValueRef Instr, unsigned CC) {
Value *V = unwrap(Instr);
if (CallInst *CI = dyn_cast<CallInst>(V))
- return CI->setCallingConv(CC);
+ return CI->setCallingConv(static_cast<CallingConv::ID>(CC));
else if (InvokeInst *II = dyn_cast<InvokeInst>(V))
- return II->setCallingConv(CC);
+ return II->setCallingConv(static_cast<CallingConv::ID>(CC));
llvm_unreachable("LLVMSetInstructionCallConv applies only to call and invoke!");
}
@@ -1627,6 +1628,10 @@ LLVMValueRef LLVMBuildNeg(LLVMBuilderRef B, LLVMValueRef V, const char *Name) {
return wrap(unwrap(B)->CreateNeg(unwrap(V), Name));
}
+LLVMValueRef LLVMBuildFNeg(LLVMBuilderRef B, LLVMValueRef V, const char *Name) {
+ return wrap(unwrap(B)->CreateFNeg(unwrap(V), Name));
+}
+
LLVMValueRef LLVMBuildNot(LLVMBuilderRef B, LLVMValueRef V, const char *Name) {
return wrap(unwrap(B)->CreateNot(unwrap(V), Name));
}
diff --git a/libclamav/c++/llvm/lib/VMCore/Dominators.cpp b/libclamav/c++/llvm/lib/VMCore/Dominators.cpp
index bb73aaf..b49faf8 100644
--- a/libclamav/c++/llvm/lib/VMCore/Dominators.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/Dominators.cpp
@@ -24,9 +24,20 @@
#include "llvm/Analysis/DominatorInternals.h"
#include "llvm/Instructions.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/CommandLine.h"
#include <algorithm>
using namespace llvm;
+// Always verify dominfo if expensive checking is enabled.
+#ifdef XDEBUG
+bool VerifyDomInfo = true;
+#else
+bool VerifyDomInfo = false;
+#endif
+static cl::opt<bool,true>
+VerifyDomInfoX("verify-dom-info", cl::location(VerifyDomInfo),
+ cl::desc("Verify dominator info (time consuming)"));
+
//===----------------------------------------------------------------------===//
// DominatorTree Implementation
//===----------------------------------------------------------------------===//
@@ -48,10 +59,45 @@ bool DominatorTree::runOnFunction(Function &F) {
return false;
}
+void DominatorTree::verifyAnalysis() const {
+ if (!VerifyDomInfo) return;
+
+ Function &F = *getRoot()->getParent();
+
+ DominatorTree OtherDT;
+ OtherDT.getBase().recalculate(F);
+ assert(!compare(OtherDT) && "Invalid DominatorTree info!");
+}
+
void DominatorTree::print(raw_ostream &OS, const Module *) const {
DT->print(OS);
}
+// dominates - Return true if A dominates a use in B. This performs the
+// special checks necessary if A and B are in the same basic block.
+bool DominatorTree::dominates(const Instruction *A, const Instruction *B) const{
+ const BasicBlock *BBA = A->getParent(), *BBB = B->getParent();
+
+ // If A is an invoke instruction, its value is only available in this normal
+ // successor block.
+ if (const InvokeInst *II = dyn_cast<InvokeInst>(A))
+ BBA = II->getNormalDest();
+
+ if (BBA != BBB) return dominates(BBA, BBB);
+
+ // It is not possible to determine dominance between two PHI nodes
+ // based on their ordering.
+ if (isa<PHINode>(A) && isa<PHINode>(B))
+ return false;
+
+ // Loop through the basic block until we find A or B.
+ BasicBlock::const_iterator I = BBA->begin();
+ for (; &*I != A && &*I != B; ++I)
+ /*empty*/;
+
+ return &*I == A;
+}
+
//===----------------------------------------------------------------------===//
@@ -62,6 +108,17 @@ char DominanceFrontier::ID = 0;
static RegisterPass<DominanceFrontier>
G("domfrontier", "Dominance Frontier Construction", true, true);
+void DominanceFrontier::verifyAnalysis() const {
+ if (!VerifyDomInfo) return;
+
+ DominatorTree &DT = getAnalysis<DominatorTree>();
+
+ DominanceFrontier OtherDF;
+ const std::vector<BasicBlock*> &DTRoots = DT.getRoots();
+ OtherDF.calculate(DT, DT.getNode(DTRoots[0]));
+ assert(!compare(OtherDF) && "Invalid DominanceFrontier info!");
+}
+
// NewBB is split and now it has one successor. Update dominace frontier to
// reflect this change.
void DominanceFrontier::splitBlock(BasicBlock *NewBB) {
diff --git a/libclamav/c++/llvm/lib/VMCore/Instruction.cpp b/libclamav/c++/llvm/lib/VMCore/Instruction.cpp
index 815dd7e..4df536e 100644
--- a/libclamav/c++/llvm/lib/VMCore/Instruction.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/Instruction.cpp
@@ -11,11 +11,13 @@
//
//===----------------------------------------------------------------------===//
+#include "LLVMContextImpl.h"
#include "llvm/Type.h"
#include "llvm/Instructions.h"
#include "llvm/Function.h"
#include "llvm/Constants.h"
#include "llvm/GlobalVariable.h"
+#include "llvm/Module.h"
#include "llvm/Support/CallSite.h"
#include "llvm/Support/LeakDetector.h"
using namespace llvm;
@@ -49,6 +51,10 @@ Instruction::Instruction(const Type *ty, unsigned it, Use *Ops, unsigned NumOps,
// Out of line virtual method, so the vtable, etc has a home.
Instruction::~Instruction() {
assert(Parent == 0 && "Instruction still linked in the program!");
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsDeleted(this);
+ }
}
@@ -291,11 +297,11 @@ bool Instruction::isUsedOutsideOfBlock(const BasicBlock *BB) const {
return true;
continue;
}
-
+
if (PN->getIncomingBlock(UI) != BB)
return true;
}
- return false;
+ return false;
}
/// mayReadFromMemory - Return true if this instruction may read memory.
@@ -375,6 +381,27 @@ bool Instruction::isCommutative(unsigned op) {
}
}
+// Code here matches isMalloc from MallocHelper, which is not in VMCore.
+static bool isMalloc(const Value* I) {
+ const CallInst *CI = dyn_cast<CallInst>(I);
+ if (!CI) {
+ const BitCastInst *BCI = dyn_cast<BitCastInst>(I);
+ if (!BCI) return false;
+
+ CI = dyn_cast<CallInst>(BCI->getOperand(0));
+ }
+
+ if (!CI) return false;
+
+ const Module* M = CI->getParent()->getParent()->getParent();
+ Constant *MallocFunc = M->getFunction("malloc");
+
+ if (CI->getOperand(0) != MallocFunc)
+ return false;
+
+ return true;
+}
+
bool Instruction::isSafeToSpeculativelyExecute() const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
if (Constant *C = dyn_cast<Constant>(getOperand(i)))
@@ -400,7 +427,7 @@ bool Instruction::isSafeToSpeculativelyExecute() const {
case Load: {
if (cast<LoadInst>(this)->isVolatile())
return false;
- if (isa<AllocationInst>(getOperand(0)))
+ if (isa<AllocationInst>(getOperand(0)) || isMalloc(getOperand(0)))
return true;
if (GlobalVariable *GV = dyn_cast<GlobalVariable>(getOperand(0)))
return !GV->hasExternalWeakLinkage();
diff --git a/libclamav/c++/llvm/lib/VMCore/Instructions.cpp b/libclamav/c++/llvm/lib/VMCore/Instructions.cpp
index e4cf5f4..c2fddfa 100644
--- a/libclamav/c++/llvm/lib/VMCore/Instructions.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/Instructions.cpp
@@ -12,15 +12,19 @@
//
//===----------------------------------------------------------------------===//
+#include "LLVMContextImpl.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/Instructions.h"
+#include "llvm/Module.h"
#include "llvm/Operator.h"
+#include "llvm/Analysis/Dominators.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/CallSite.h"
#include "llvm/Support/ConstantRange.h"
#include "llvm/Support/MathExtras.h"
+
using namespace llvm;
//===----------------------------------------------------------------------===//
@@ -45,10 +49,10 @@ CallSite::CallSite(Instruction *C) {
I.setPointer(C);
I.setInt(isa<CallInst>(C));
}
-unsigned CallSite::getCallingConv() const {
+CallingConv::ID CallSite::getCallingConv() const {
CALLSITE_DELEGATE_GETTER(getCallingConv());
}
-void CallSite::setCallingConv(unsigned CC) {
+void CallSite::setCallingConv(CallingConv::ID CC) {
CALLSITE_DELEGATE_SETTER(setCallingConv(CC));
}
const AttrListPtr &CallSite::getAttributes() const {
@@ -226,13 +230,17 @@ void PHINode::resizeOperands(unsigned NumOps) {
/// hasConstantValue - If the specified PHI node always merges together the same
/// value, return the value, otherwise return null.
///
-Value *PHINode::hasConstantValue(bool AllowNonDominatingInstruction) const {
- // If the PHI node only has one incoming value, eliminate the PHI node...
+/// If the PHI has undef operands, but all the rest of the operands are
+/// some unique value, return that value if it can be proved that the
+/// value dominates the PHI. If DT is null, use a conservative check,
+/// otherwise use DT to test for dominance.
+///
+Value *PHINode::hasConstantValue(DominatorTree *DT) const {
+ // If the PHI node only has one incoming value, eliminate the PHI node.
if (getNumIncomingValues() == 1) {
if (getIncomingValue(0) != this) // not X = phi X
return getIncomingValue(0);
- else
- return UndefValue::get(getType()); // Self cycle is dead.
+ return UndefValue::get(getType()); // Self cycle is dead.
}
// Otherwise if all of the incoming values are the same for the PHI, replace
@@ -246,8 +254,7 @@ Value *PHINode::hasConstantValue(bool AllowNonDominatingInstruction) const {
} else if (getIncomingValue(i) != this) { // Not the PHI node itself...
if (InVal && getIncomingValue(i) != InVal)
return 0; // Not the same, bail out.
- else
- InVal = getIncomingValue(i);
+ InVal = getIncomingValue(i);
}
// The only case that could cause InVal to be null is if we have a PHI node
@@ -260,12 +267,20 @@ Value *PHINode::hasConstantValue(bool AllowNonDominatingInstruction) const {
// instruction, we cannot always return X as the result of the PHI node. Only
// do this if X is not an instruction (thus it must dominate the PHI block),
// or if the client is prepared to deal with this possibility.
- if (HasUndefInput && !AllowNonDominatingInstruction)
- if (Instruction *IV = dyn_cast<Instruction>(InVal))
- // If it's in the entry block, it dominates everything.
- if (IV->getParent() != &IV->getParent()->getParent()->getEntryBlock() ||
- isa<InvokeInst>(IV))
- return 0; // Cannot guarantee that InVal dominates this PHINode.
+ if (!HasUndefInput || !isa<Instruction>(InVal))
+ return InVal;
+
+ Instruction *IV = cast<Instruction>(InVal);
+ if (DT) {
+ // We have a DominatorTree. Do a precise test.
+ if (!DT->dominates(IV, this))
+ return 0;
+ } else {
+ // If it is in the entry block, it obviously dominates everything.
+ if (IV->getParent() != &IV->getParent()->getParent()->getEntryBlock() ||
+ isa<InvokeInst>(IV))
+ return 0; // Cannot guarantee that InVal dominates this PHINode.
+ }
// All of the incoming values are the same, return the value now.
return InVal;
@@ -427,6 +442,111 @@ bool CallInst::paramHasAttr(unsigned i, Attributes attr) const {
return false;
}
+/// IsConstantOne - Return true only if val is constant int 1
+static bool IsConstantOne(Value *val) {
+ assert(val && "IsConstantOne does not work with NULL val");
+ return isa<ConstantInt>(val) && cast<ConstantInt>(val)->isOne();
+}
+
+static Value *checkArraySize(Value *Amt, const Type *IntPtrTy) {
+ if (!Amt)
+ Amt = ConstantInt::get(IntPtrTy, 1);
+ else {
+ assert(!isa<BasicBlock>(Amt) &&
+ "Passed basic block into malloc size parameter! Use other ctor");
+ assert(Amt->getType() == IntPtrTy &&
+ "Malloc array size is not an intptr!");
+ }
+ return Amt;
+}
+
+static Value *createMalloc(Instruction *InsertBefore, BasicBlock *InsertAtEnd,
+ const Type *IntPtrTy, const Type *AllocTy,
+ Value *ArraySize, const Twine &NameStr) {
+ assert(((!InsertBefore && InsertAtEnd) || (InsertBefore && !InsertAtEnd)) &&
+ "createMalloc needs either InsertBefore or InsertAtEnd");
+
+ // malloc(type) becomes:
+ // bitcast (i8* malloc(typeSize)) to type*
+ // malloc(type, arraySize) becomes:
+ // bitcast (i8 *malloc(typeSize*arraySize)) to type*
+ Value *AllocSize = ConstantExpr::getSizeOf(AllocTy);
+ AllocSize = ConstantExpr::getTruncOrBitCast(cast<Constant>(AllocSize),
+ IntPtrTy);
+ ArraySize = checkArraySize(ArraySize, IntPtrTy);
+
+ if (!IsConstantOne(ArraySize)) {
+ if (IsConstantOne(AllocSize)) {
+ AllocSize = ArraySize; // Operand * 1 = Operand
+ } else if (Constant *CO = dyn_cast<Constant>(ArraySize)) {
+ Constant *Scale = ConstantExpr::getIntegerCast(CO, IntPtrTy,
+ false /*ZExt*/);
+ // Malloc arg is constant product of type size and array size
+ AllocSize = ConstantExpr::getMul(Scale, cast<Constant>(AllocSize));
+ } else {
+ // Multiply type size by the array size...
+ if (InsertBefore)
+ AllocSize = BinaryOperator::CreateMul(ArraySize, AllocSize,
+ "mallocsize", InsertBefore);
+ else
+ AllocSize = BinaryOperator::CreateMul(ArraySize, AllocSize,
+ "mallocsize", InsertAtEnd);
+ }
+ }
+
+ assert(AllocSize->getType() == IntPtrTy && "malloc arg is wrong size");
+ // Create the call to Malloc.
+ BasicBlock* BB = InsertBefore ? InsertBefore->getParent() : InsertAtEnd;
+ Module* M = BB->getParent()->getParent();
+ const Type *BPTy = PointerType::getUnqual(Type::getInt8Ty(BB->getContext()));
+ // prototype malloc as "void *malloc(size_t)"
+ Constant *MallocF = M->getOrInsertFunction("malloc", BPTy, IntPtrTy, NULL);
+ if (!cast<Function>(MallocF)->doesNotAlias(0))
+ cast<Function>(MallocF)->setDoesNotAlias(0);
+ const PointerType *AllocPtrType = PointerType::getUnqual(AllocTy);
+ CallInst *MCall = NULL;
+ Value *MCast = NULL;
+ if (InsertBefore) {
+ MCall = CallInst::Create(MallocF, AllocSize, "malloccall", InsertBefore);
+ // Create a cast instruction to convert to the right type...
+ MCast = new BitCastInst(MCall, AllocPtrType, NameStr, InsertBefore);
+ } else {
+ MCall = CallInst::Create(MallocF, AllocSize, "malloccall", InsertAtEnd);
+ // Create a cast instruction to convert to the right type...
+ MCast = new BitCastInst(MCall, AllocPtrType, NameStr);
+ }
+ MCall->setTailCall();
+ assert(MCall->getType() != Type::getVoidTy(BB->getContext()) &&
+ "Malloc has void return type");
+
+ return MCast;
+}
+
+/// CreateMalloc - Generate the IR for a call to malloc:
+/// 1. Compute the malloc call's argument as the specified type's size,
+/// possibly multiplied by the array size if the array size is not
+/// constant 1.
+/// 2. Call malloc with that argument.
+/// 3. Bitcast the result of the malloc call to the specified type.
+Value *CallInst::CreateMalloc(Instruction *InsertBefore, const Type *IntPtrTy,
+ const Type *AllocTy, Value *ArraySize,
+ const Twine &Name) {
+ return createMalloc(InsertBefore, NULL, IntPtrTy, AllocTy, ArraySize, Name);
+}
+
+/// CreateMalloc - Generate the IR for a call to malloc:
+/// 1. Compute the malloc call's argument as the specified type's size,
+/// possibly multiplied by the array size if the array size is not
+/// constant 1.
+/// 2. Call malloc with that argument.
+/// 3. Bitcast the result of the malloc call to the specified type.
+/// Note: This function does not add the bitcast to the basic block, that is the
+/// responsibility of the caller.
+Value *CallInst::CreateMalloc(BasicBlock *InsertAtEnd, const Type *IntPtrTy,
+ const Type *AllocTy, Value *ArraySize,
+ const Twine &Name) {
+ return createMalloc(NULL, InsertAtEnd, IntPtrTy, AllocTy, ArraySize, Name);
+}
//===----------------------------------------------------------------------===//
// InvokeInst Implementation
@@ -1158,6 +1278,13 @@ bool GetElementPtrInst::hasAllConstantIndices() const {
return true;
}
+void GetElementPtrInst::setIsInBounds(bool B) {
+ cast<GEPOperator>(this)->setIsInBounds(B);
+}
+
+bool GetElementPtrInst::isInBounds() const {
+ return cast<GEPOperator>(this)->isInBounds();
+}
//===----------------------------------------------------------------------===//
// ExtractElementInst Implementation
@@ -1647,7 +1774,7 @@ bool BinaryOperator::isFNeg(const Value *V) {
if (const BinaryOperator *Bop = dyn_cast<BinaryOperator>(V))
if (Bop->getOpcode() == Instruction::FSub)
if (Constant* C = dyn_cast<Constant>(Bop->getOperand(0)))
- return C->isNegativeZeroValue();
+ return C->isNegativeZeroValue();
return false;
}
@@ -1703,6 +1830,30 @@ bool BinaryOperator::swapOperands() {
return false;
}
+void BinaryOperator::setHasNoUnsignedWrap(bool b) {
+ cast<OverflowingBinaryOperator>(this)->setHasNoUnsignedWrap(b);
+}
+
+void BinaryOperator::setHasNoSignedWrap(bool b) {
+ cast<OverflowingBinaryOperator>(this)->setHasNoSignedWrap(b);
+}
+
+void BinaryOperator::setIsExact(bool b) {
+ cast<SDivOperator>(this)->setIsExact(b);
+}
+
+bool BinaryOperator::hasNoUnsignedWrap() const {
+ return cast<OverflowingBinaryOperator>(this)->hasNoUnsignedWrap();
+}
+
+bool BinaryOperator::hasNoSignedWrap() const {
+ return cast<OverflowingBinaryOperator>(this)->hasNoSignedWrap();
+}
+
+bool BinaryOperator::isExact() const {
+ return cast<SDivOperator>(this)->isExact();
+}
+
//===----------------------------------------------------------------------===//
// CastInst Class
//===----------------------------------------------------------------------===//
@@ -2864,231 +3015,373 @@ void SwitchInst::setSuccessorV(unsigned idx, BasicBlock *B) {
// Define these methods here so vtables don't get emitted into every translation
// unit that uses these classes.
-GetElementPtrInst *GetElementPtrInst::clone(LLVMContext&) const {
+GetElementPtrInst *GetElementPtrInst::clone() const {
GetElementPtrInst *New = new(getNumOperands()) GetElementPtrInst(*this);
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-BinaryOperator *BinaryOperator::clone(LLVMContext&) const {
+BinaryOperator *BinaryOperator::clone() const {
BinaryOperator *New = Create(getOpcode(), Op<0>(), Op<1>());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-FCmpInst* FCmpInst::clone(LLVMContext &Context) const {
+FCmpInst* FCmpInst::clone() const {
FCmpInst *New = new FCmpInst(getPredicate(), Op<0>(), Op<1>());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-ICmpInst* ICmpInst::clone(LLVMContext &Context) const {
+ICmpInst* ICmpInst::clone() const {
ICmpInst *New = new ICmpInst(getPredicate(), Op<0>(), Op<1>());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-ExtractValueInst *ExtractValueInst::clone(LLVMContext&) const {
+ExtractValueInst *ExtractValueInst::clone() const {
ExtractValueInst *New = new ExtractValueInst(*this);
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-InsertValueInst *InsertValueInst::clone(LLVMContext&) const {
+InsertValueInst *InsertValueInst::clone() const {
InsertValueInst *New = new InsertValueInst(*this);
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-MallocInst *MallocInst::clone(LLVMContext&) const {
+MallocInst *MallocInst::clone() const {
MallocInst *New = new MallocInst(getAllocatedType(),
(Value*)getOperand(0),
getAlignment());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-AllocaInst *AllocaInst::clone(LLVMContext&) const {
+AllocaInst *AllocaInst::clone() const {
AllocaInst *New = new AllocaInst(getAllocatedType(),
(Value*)getOperand(0),
getAlignment());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-FreeInst *FreeInst::clone(LLVMContext&) const {
+FreeInst *FreeInst::clone() const {
FreeInst *New = new FreeInst(getOperand(0));
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-LoadInst *LoadInst::clone(LLVMContext&) const {
+LoadInst *LoadInst::clone() const {
LoadInst *New = new LoadInst(getOperand(0),
Twine(), isVolatile(),
getAlignment());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-StoreInst *StoreInst::clone(LLVMContext&) const {
+StoreInst *StoreInst::clone() const {
StoreInst *New = new StoreInst(getOperand(0), getOperand(1),
isVolatile(), getAlignment());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-TruncInst *TruncInst::clone(LLVMContext&) const {
+TruncInst *TruncInst::clone() const {
TruncInst *New = new TruncInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-ZExtInst *ZExtInst::clone(LLVMContext&) const {
+ZExtInst *ZExtInst::clone() const {
ZExtInst *New = new ZExtInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-SExtInst *SExtInst::clone(LLVMContext&) const {
+SExtInst *SExtInst::clone() const {
SExtInst *New = new SExtInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-FPTruncInst *FPTruncInst::clone(LLVMContext&) const {
+FPTruncInst *FPTruncInst::clone() const {
FPTruncInst *New = new FPTruncInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-FPExtInst *FPExtInst::clone(LLVMContext&) const {
+FPExtInst *FPExtInst::clone() const {
FPExtInst *New = new FPExtInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-UIToFPInst *UIToFPInst::clone(LLVMContext&) const {
+UIToFPInst *UIToFPInst::clone() const {
UIToFPInst *New = new UIToFPInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-SIToFPInst *SIToFPInst::clone(LLVMContext&) const {
+SIToFPInst *SIToFPInst::clone() const {
SIToFPInst *New = new SIToFPInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-FPToUIInst *FPToUIInst::clone(LLVMContext&) const {
+FPToUIInst *FPToUIInst::clone() const {
FPToUIInst *New = new FPToUIInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-FPToSIInst *FPToSIInst::clone(LLVMContext&) const {
+FPToSIInst *FPToSIInst::clone() const {
FPToSIInst *New = new FPToSIInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-PtrToIntInst *PtrToIntInst::clone(LLVMContext&) const {
+PtrToIntInst *PtrToIntInst::clone() const {
PtrToIntInst *New = new PtrToIntInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-IntToPtrInst *IntToPtrInst::clone(LLVMContext&) const {
+IntToPtrInst *IntToPtrInst::clone() const {
IntToPtrInst *New = new IntToPtrInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-BitCastInst *BitCastInst::clone(LLVMContext&) const {
+BitCastInst *BitCastInst::clone() const {
BitCastInst *New = new BitCastInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-CallInst *CallInst::clone(LLVMContext&) const {
+CallInst *CallInst::clone() const {
CallInst *New = new(getNumOperands()) CallInst(*this);
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-SelectInst *SelectInst::clone(LLVMContext&) const {
+SelectInst *SelectInst::clone() const {
SelectInst *New = SelectInst::Create(getOperand(0),
getOperand(1),
getOperand(2));
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-VAArgInst *VAArgInst::clone(LLVMContext&) const {
+VAArgInst *VAArgInst::clone() const {
VAArgInst *New = new VAArgInst(getOperand(0), getType());
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-ExtractElementInst *ExtractElementInst::clone(LLVMContext&) const {
+ExtractElementInst *ExtractElementInst::clone() const {
ExtractElementInst *New = ExtractElementInst::Create(getOperand(0),
getOperand(1));
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-InsertElementInst *InsertElementInst::clone(LLVMContext&) const {
+InsertElementInst *InsertElementInst::clone() const {
InsertElementInst *New = InsertElementInst::Create(getOperand(0),
getOperand(1),
getOperand(2));
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-ShuffleVectorInst *ShuffleVectorInst::clone(LLVMContext&) const {
+ShuffleVectorInst *ShuffleVectorInst::clone() const {
ShuffleVectorInst *New = new ShuffleVectorInst(getOperand(0),
getOperand(1),
getOperand(2));
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-PHINode *PHINode::clone(LLVMContext&) const {
+PHINode *PHINode::clone() const {
PHINode *New = new PHINode(*this);
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-ReturnInst *ReturnInst::clone(LLVMContext&) const {
+ReturnInst *ReturnInst::clone() const {
ReturnInst *New = new(getNumOperands()) ReturnInst(*this);
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-BranchInst *BranchInst::clone(LLVMContext&) const {
+BranchInst *BranchInst::clone() const {
unsigned Ops(getNumOperands());
BranchInst *New = new(Ops, Ops == 1) BranchInst(*this);
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-SwitchInst *SwitchInst::clone(LLVMContext&) const {
+SwitchInst *SwitchInst::clone() const {
SwitchInst *New = new SwitchInst(*this);
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-InvokeInst *InvokeInst::clone(LLVMContext&) const {
+InvokeInst *InvokeInst::clone() const {
InvokeInst *New = new(getNumOperands()) InvokeInst(*this);
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata()) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
+ }
return New;
}
-UnwindInst *UnwindInst::clone(LLVMContext &C) const {
- UnwindInst *New = new UnwindInst(C);
+UnwindInst *UnwindInst::clone() const {
+ LLVMContext &Context = getContext();
+ UnwindInst *New = new UnwindInst(Context);
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata())
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
return New;
}
-UnreachableInst *UnreachableInst::clone(LLVMContext &C) const {
- UnreachableInst *New = new UnreachableInst(C);
+UnreachableInst *UnreachableInst::clone() const {
+ LLVMContext &Context = getContext();
+ UnreachableInst *New = new UnreachableInst(Context);
New->SubclassOptionalData = SubclassOptionalData;
+ if (hasMetadata())
+ Context.pImpl->TheMetadata.ValueIsCloned(this, New);
return New;
}
diff --git a/libclamav/c++/llvm/lib/VMCore/IntrinsicInst.cpp b/libclamav/c++/llvm/lib/VMCore/IntrinsicInst.cpp
index 8bdc968..5f33d0e 100644
--- a/libclamav/c++/llvm/lib/VMCore/IntrinsicInst.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/IntrinsicInst.cpp
@@ -61,17 +61,11 @@ Value *DbgInfoIntrinsic::StripCast(Value *C) {
Value *DbgStopPointInst::getFileName() const {
// Once the operand indices are verified, update this assert
assert(LLVMDebugVersion == (7 << 16) && "Verify operand indices");
- GlobalVariable *GV = cast<GlobalVariable>(getContext());
- if (!GV->hasInitializer()) return NULL;
- ConstantStruct *CS = cast<ConstantStruct>(GV->getInitializer());
- return CS->getOperand(3);
+ return getContext()->getElement(3);
}
Value *DbgStopPointInst::getDirectory() const {
// Once the operand indices are verified, update this assert
assert(LLVMDebugVersion == (7 << 16) && "Verify operand indices");
- GlobalVariable *GV = cast<GlobalVariable>(getContext());
- if (!GV->hasInitializer()) return NULL;
- ConstantStruct *CS = cast<ConstantStruct>(GV->getInitializer());
- return CS->getOperand(4);
+ return getContext()->getElement(4);
}
diff --git a/libclamav/c++/llvm/lib/VMCore/LLVMContext.cpp b/libclamav/c++/llvm/lib/VMCore/LLVMContext.cpp
index 95ceeae..39ed7ed 100644
--- a/libclamav/c++/llvm/lib/VMCore/LLVMContext.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/LLVMContext.cpp
@@ -13,9 +13,11 @@
//===----------------------------------------------------------------------===//
#include "llvm/LLVMContext.h"
+#include "llvm/Metadata.h"
#include "llvm/Constants.h"
#include "llvm/Instruction.h"
#include "llvm/Support/ManagedStatic.h"
+#include "llvm/Support/ValueHandle.h"
#include "LLVMContextImpl.h"
#include <set>
@@ -44,25 +46,31 @@ GetElementPtrConstantExpr::GetElementPtrConstantExpr
}
bool LLVMContext::RemoveDeadMetadata() {
- std::vector<const MDNode *> DeadMDNodes;
+ std::vector<WeakVH> DeadMDNodes;
bool Changed = false;
while (1) {
- for (LLVMContextImpl::MDNodeMapTy::MapTy::iterator
- I = pImpl->MDNodes.map_begin(),
- E = pImpl->MDNodes.map_end(); I != E; ++I) {
- const MDNode *N = cast<MDNode>(I->second);
+ for (FoldingSet<MDNode>::iterator
+ I = pImpl->MDNodeSet.begin(),
+ E = pImpl->MDNodeSet.end(); I != E; ++I) {
+ MDNode *N = &(*I);
if (N->use_empty())
- DeadMDNodes.push_back(N);
+ DeadMDNodes.push_back(WeakVH(N));
}
if (DeadMDNodes.empty())
return Changed;
while (!DeadMDNodes.empty()) {
- const MDNode *N = DeadMDNodes.back(); DeadMDNodes.pop_back();
- delete N;
+ Value *V = DeadMDNodes.back(); DeadMDNodes.pop_back();
+ if (const MDNode *N = dyn_cast_or_null<MDNode>(V))
+ if (N->use_empty())
+ delete N;
}
}
return Changed;
}
+
+MetadataContext &LLVMContext::getMetadata() {
+ return pImpl->TheMetadata;
+}
diff --git a/libclamav/c++/llvm/lib/VMCore/LLVMContextImpl.h b/libclamav/c++/llvm/lib/VMCore/LLVMContextImpl.h
index 2faf6ac..83888c3 100644
--- a/libclamav/c++/llvm/lib/VMCore/LLVMContextImpl.h
+++ b/libclamav/c++/llvm/lib/VMCore/LLVMContextImpl.h
@@ -19,6 +19,7 @@
#include "LeaksContext.h"
#include "TypesContext.h"
#include "llvm/LLVMContext.h"
+#include "llvm/Metadata.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/System/Mutex.h"
@@ -106,13 +107,10 @@ public:
StringMap<MDString*> MDStringCache;
+ FoldingSet<MDNode> MDNodeSet;
+
ValueMap<char, Type, ConstantAggregateZero> AggZeroConstants;
- typedef ValueMap<std::vector<Value*>, Type, MDNode, true /*largekey*/>
- MDNodeMapTy;
-
- MDNodeMapTy MDNodes;
-
typedef ValueMap<std::vector<Constant*>, ArrayType,
ConstantArray, true /*largekey*/> ArrayConstantsTy;
ArrayConstantsTy ArrayConstants;
@@ -181,6 +179,7 @@ public:
typedef DenseMap<Value*, ValueHandleBase*> ValueHandlesTy;
ValueHandlesTy ValueHandles;
+ MetadataContext TheMetadata;
LLVMContextImpl(LLVMContext &C) : TheTrueVal(0), TheFalseVal(0),
VoidTy(C, Type::VoidTyID),
LabelTy(C, Type::LabelTyID),
@@ -202,16 +201,18 @@ public:
ArrayConstants.freeConstants();
StructConstants.freeConstants();
VectorConstants.freeConstants();
-
AggZeroConstants.freeConstants();
NullPtrConstants.freeConstants();
UndefValueConstants.freeConstants();
- for (IntMapTy::iterator I=IntConstants.begin(), E=IntConstants.end();
+ for (FoldingSet<MDNode>::iterator I = MDNodeSet.begin(),
+ E = MDNodeSet.end(); I != E; ++I)
+ I->dropAllReferences();
+ for (IntMapTy::iterator I = IntConstants.begin(), E = IntConstants.end();
I != E; ++I) {
if (I->second->use_empty())
delete I->second;
}
- for (FPMapTy::iterator I=FPConstants.begin(), E=FPConstants.end();
+ for (FPMapTy::iterator I = FPConstants.begin(), E = FPConstants.end();
I != E; ++I) {
if (I->second->use_empty())
delete I->second;
diff --git a/libclamav/c++/llvm/lib/VMCore/Mangler.cpp b/libclamav/c++/llvm/lib/VMCore/Mangler.cpp
index 8c91843..33eb044 100644
--- a/libclamav/c++/llvm/lib/VMCore/Mangler.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/Mangler.cpp
@@ -12,11 +12,12 @@
//===----------------------------------------------------------------------===//
#include "llvm/Support/Mangler.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/Module.h"
+#include "llvm/Function.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
static char HexDigit(int V) {
@@ -46,8 +47,9 @@ std::string Mangler::makeNameProper(const std::string &X,
++I; // Skip over the marker.
}
- // Mangle the first letter specially, don't allow numbers.
- if (*I >= '0' && *I <= '9')
+ // Mangle the first letter specially, don't allow numbers unless the target
+ // explicitly allows them.
+ if (!SymbolsCanStartWithDigit && *I >= '0' && *I <= '9')
Result += MangleLetter(*I++);
for (std::string::const_iterator E = X.end(); I != E; ++I) {
@@ -158,11 +160,55 @@ std::string Mangler::getMangledName(const GlobalValue *GV, const char *Suffix,
return makeNameProper("__unnamed_" + utostr(ID) + Suffix, PrefixTy);
}
+
+/// getNameWithPrefix - Fill OutName with the name of the appropriate prefix
+/// and the specified global variable's name. If the global variable doesn't
+/// have a name, this fills in a unique name for the global.
+void Mangler::getNameWithPrefix(SmallVectorImpl<char> &OutName,
+ const GlobalValue *GV,
+ bool isImplicitlyPrivate) {
+
+ // If the global is anonymous or not led with \1, then add the appropriate
+ // prefix.
+ if (!GV->hasName() || GV->getName()[0] != '\1') {
+ if (GV->hasPrivateLinkage() || isImplicitlyPrivate)
+ OutName.append(PrivatePrefix, PrivatePrefix+strlen(PrivatePrefix));
+ else if (GV->hasLinkerPrivateLinkage())
+ OutName.append(LinkerPrivatePrefix,
+ LinkerPrivatePrefix+strlen(LinkerPrivatePrefix));;
+ OutName.append(Prefix, Prefix+strlen(Prefix));
+ }
+
+ // If the global has a name, just append it now.
+ if (GV->hasName()) {
+ StringRef Name = GV->getName();
+
+ // Strip off the prefix marker if present.
+ if (Name[0] != '\1')
+ OutName.append(Name.begin(), Name.end());
+ else
+ OutName.append(Name.begin()+1, Name.end());
+ return;
+ }
+
+ // If the global variable doesn't have a name, return a unique name for the
+ // global based on a numbering.
+
+ // Get the ID for the global, assigning a new one if we haven't got one
+ // already.
+ unsigned &ID = AnonGlobalIDs[GV];
+ if (ID == 0) ID = NextAnonGlobalID++;
+
+ // Must mangle the global into a unique ID.
+ raw_svector_ostream(OutName) << "__unnamed_" << ID;
+}
+
+
Mangler::Mangler(Module &M, const char *prefix, const char *privatePrefix,
const char *linkerPrivatePrefix)
: Prefix(prefix), PrivatePrefix(privatePrefix),
LinkerPrivatePrefix(linkerPrivatePrefix), UseQuotes(false),
- NextAnonGlobalID(1) {
+ SymbolsCanStartWithDigit(false), NextAnonGlobalID(1) {
std::fill(AcceptableChars, array_endof(AcceptableChars), 0);
// Letters and numbers are acceptable.
@@ -177,4 +223,5 @@ Mangler::Mangler(Module &M, const char *prefix, const char *privatePrefix,
markCharAcceptable('_');
markCharAcceptable('$');
markCharAcceptable('.');
+ markCharAcceptable('@');
}
diff --git a/libclamav/c++/llvm/lib/VMCore/Metadata.cpp b/libclamav/c++/llvm/lib/VMCore/Metadata.cpp
index 60ec1c5..2f2345f 100644
--- a/libclamav/c++/llvm/lib/VMCore/Metadata.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/Metadata.cpp
@@ -15,6 +15,7 @@
#include "llvm/Metadata.h"
#include "llvm/LLVMContext.h"
#include "llvm/Module.h"
+#include "llvm/Instruction.h"
#include "SymbolTableListTraitsImpl.h"
using namespace llvm;
@@ -72,18 +73,40 @@ MDNode::MDNode(LLVMContext &C, Value*const* Vals, unsigned NumVals)
// Only record metadata uses.
if (MetadataBase *MB = dyn_cast_or_null<MetadataBase>(Vals[i]))
OperandList[NumOperands++] = MB;
- Node.push_back(WeakVH(Vals[i]));
+ else if(Vals[i] &&
+ Vals[i]->getType()->getTypeID() == Type::MetadataTyID)
+ OperandList[NumOperands++] = Vals[i];
+ Node.push_back(ElementVH(Vals[i], this));
}
}
+void MDNode::Profile(FoldingSetNodeID &ID) const {
+ for (const_elem_iterator I = elem_begin(), E = elem_end(); I != E; ++I)
+ ID.AddPointer(*I);
+}
+
MDNode *MDNode::get(LLVMContext &Context, Value*const* Vals, unsigned NumVals) {
LLVMContextImpl *pImpl = Context.pImpl;
- std::vector<Value*> V;
- V.reserve(NumVals);
- for (unsigned i = 0; i < NumVals; ++i)
- V.push_back(Vals[i]);
+ FoldingSetNodeID ID;
+ for (unsigned i = 0; i != NumVals; ++i)
+ ID.AddPointer(Vals[i]);
+
+ pImpl->ConstantsLock.reader_acquire();
+ void *InsertPoint;
+ MDNode *N = pImpl->MDNodeSet.FindNodeOrInsertPos(ID, InsertPoint);
+ pImpl->ConstantsLock.reader_release();
- return pImpl->MDNodes.getOrCreate(Type::getMetadataTy(Context), V);
+ if (!N) {
+ sys::SmartScopedWriter<true> Writer(pImpl->ConstantsLock);
+ N = pImpl->MDNodeSet.FindNodeOrInsertPos(ID, InsertPoint);
+ if (!N) {
+ // InsertPoint will have been set by the FindNodeOrInsertPos call.
+ N = new MDNode(Context, Vals, NumVals);
+ pImpl->MDNodeSet.InsertNode(N, InsertPoint);
+ }
+ }
+
+ return N;
}
/// dropAllReferences - Remove all uses and clear node vector.
@@ -92,19 +115,99 @@ void MDNode::dropAllReferences() {
Node.clear();
}
-static std::vector<Value*> getValType(MDNode *N) {
- std::vector<Value*> Elements;
- Elements.reserve(N->getNumElements());
- for (unsigned i = 0, e = N->getNumElements(); i != e; ++i)
- Elements.push_back(N->getElement(i));
- return Elements;
-}
-
MDNode::~MDNode() {
- getType()->getContext().pImpl->MDNodes.remove(this);
+ {
+ LLVMContextImpl *pImpl = getType()->getContext().pImpl;
+ sys::SmartScopedWriter<true> Writer(pImpl->ConstantsLock);
+ pImpl->MDNodeSet.RemoveNode(this);
+ }
dropAllReferences();
}
+// Replace value from this node's element list.
+void MDNode::replaceElement(Value *From, Value *To) {
+ if (From == To || !getType())
+ return;
+ LLVMContext &Context = getType()->getContext();
+ LLVMContextImpl *pImpl = Context.pImpl;
+
+ // Find value. This is a linear search, do something if it consumes
+ // lot of time. It is possible that to have multiple instances of
+ // From in this MDNode's element list.
+ SmallVector<unsigned, 4> Indexes;
+ unsigned Index = 0;
+ for (SmallVector<ElementVH, 4>::iterator I = Node.begin(),
+ E = Node.end(); I != E; ++I, ++Index) {
+ Value *V = *I;
+ if (V && V == From)
+ Indexes.push_back(Index);
+ }
+
+ if (Indexes.empty())
+ return;
+
+ // Remove "this" from the context map.
+ {
+ sys::SmartScopedWriter<true> Writer(pImpl->ConstantsLock);
+ pImpl->MDNodeSet.RemoveNode(this);
+ }
+
+ // MDNode only lists metadata elements in operand list, because MDNode
+ // used by MDNode is considered a valid use. However on the side, MDNode
+ // using a non-metadata value is not considered a "use" of non-metadata
+ // value.
+ SmallVector<unsigned, 4> OpIndexes;
+ unsigned OpIndex = 0;
+ for (User::op_iterator OI = op_begin(), OE = op_end();
+ OI != OE; ++OI, OpIndex++) {
+ if (*OI == From)
+ OpIndexes.push_back(OpIndex);
+ }
+ if (MetadataBase *MDTo = dyn_cast_or_null<MetadataBase>(To)) {
+ for (SmallVector<unsigned, 4>::iterator OI = OpIndexes.begin(),
+ OE = OpIndexes.end(); OI != OE; ++OI)
+ setOperand(*OI, MDTo);
+ } else {
+ for (SmallVector<unsigned, 4>::iterator OI = OpIndexes.begin(),
+ OE = OpIndexes.end(); OI != OE; ++OI)
+ setOperand(*OI, 0);
+ }
+
+ // Replace From element(s) in place.
+ for (SmallVector<unsigned, 4>::iterator I = Indexes.begin(), E = Indexes.end();
+ I != E; ++I) {
+ unsigned Index = *I;
+ Node[Index] = ElementVH(To, this);
+ }
+
+ // Insert updated "this" into the context's folding node set.
+ // If a node with same element list already exist then before inserting
+ // updated "this" into the folding node set, replace all uses of existing
+ // node with updated "this" node.
+ FoldingSetNodeID ID;
+ Profile(ID);
+ pImpl->ConstantsLock.reader_acquire();
+ void *InsertPoint;
+ MDNode *N = pImpl->MDNodeSet.FindNodeOrInsertPos(ID, InsertPoint);
+ pImpl->ConstantsLock.reader_release();
+
+ if (N) {
+ N->replaceAllUsesWith(this);
+ delete N;
+ N = 0;
+ }
+
+ {
+ sys::SmartScopedWriter<true> Writer(pImpl->ConstantsLock);
+ N = pImpl->MDNodeSet.FindNodeOrInsertPos(ID, InsertPoint);
+ if (!N) {
+ // InsertPoint will have been set by the FindNodeOrInsertPos call.
+ N = this;
+ pImpl->MDNodeSet.InsertNode(N, InsertPoint);
+ }
+ }
+}
+
//===----------------------------------------------------------------------===//
//NamedMDNode implementation
//
@@ -149,3 +252,155 @@ void NamedMDNode::dropAllReferences() {
NamedMDNode::~NamedMDNode() {
dropAllReferences();
}
+
+//===----------------------------------------------------------------------===//
+//Metadata implementation
+//
+
+/// RegisterMDKind - Register a new metadata kind and return its ID.
+/// A metadata kind can be registered only once.
+unsigned MetadataContext::RegisterMDKind(const char *Name) {
+ assert (validName(Name) && "Invalid custome metadata name!");
+ unsigned Count = MDHandlerNames.size();
+ assert(MDHandlerNames.find(Name) == MDHandlerNames.end()
+ && "Already registered MDKind!");
+ MDHandlerNames[Name] = Count + 1;
+ return Count + 1;
+}
+
+/// validName - Return true if Name is a valid custom metadata handler name.
+bool MetadataContext::validName(const char *Name) {
+ if (!Name)
+ return false;
+
+ if (!isalpha(*Name))
+ return false;
+
+ unsigned Length = strlen(Name);
+ unsigned Count = 1;
+ ++Name;
+ while (Name &&
+ (isalnum(*Name) || *Name == '_' || *Name == '-' || *Name == '.')) {
+ ++Name;
+ ++Count;
+ }
+ if (Length != Count)
+ return false;
+ return true;
+}
+
+/// getMDKind - Return metadata kind. If the requested metadata kind
+/// is not registered then return 0.
+unsigned MetadataContext::getMDKind(const char *Name) {
+ assert (validName(Name) && "Invalid custome metadata name!");
+ StringMap<unsigned>::iterator I = MDHandlerNames.find(Name);
+ if (I == MDHandlerNames.end())
+ return 0;
+
+ return I->getValue();
+}
+
+/// addMD - Attach the metadata of given kind with an Instruction.
+void MetadataContext::addMD(unsigned MDKind, MDNode *Node, Instruction *Inst) {
+ assert (Node && "Unable to add custome metadata");
+ Inst->HasMetadata = true;
+ MDStoreTy::iterator I = MetadataStore.find(Inst);
+ if (I == MetadataStore.end()) {
+ MDMapTy Info;
+ Info.push_back(std::make_pair(MDKind, Node));
+ MetadataStore.insert(std::make_pair(Inst, Info));
+ return;
+ }
+
+ MDMapTy &Info = I->second;
+ // If there is an entry for this MDKind then replace it.
+ for (unsigned i = 0, e = Info.size(); i != e; ++i) {
+ MDPairTy &P = Info[i];
+ if (P.first == MDKind) {
+ Info[i] = std::make_pair(MDKind, Node);
+ return;
+ }
+ }
+
+ // Otherwise add a new entry.
+ Info.push_back(std::make_pair(MDKind, Node));
+ return;
+}
+
+/// removeMD - Remove metadata of given kind attached with an instuction.
+void MetadataContext::removeMD(unsigned Kind, Instruction *Inst) {
+ MDStoreTy::iterator I = MetadataStore.find(Inst);
+ if (I == MetadataStore.end())
+ return;
+
+ MDMapTy &Info = I->second;
+ for (MDMapTy::iterator MI = Info.begin(), ME = Info.end(); MI != ME; ++MI) {
+ MDPairTy &P = *MI;
+ if (P.first == Kind) {
+ Info.erase(MI);
+ return;
+ }
+ }
+
+ return;
+}
+
+/// removeMDs - Remove all metadata attached with an instruction.
+void MetadataContext::removeMDs(const Instruction *Inst) {
+ // Find Metadata handles for this instruction.
+ MDStoreTy::iterator I = MetadataStore.find(Inst);
+ assert (I != MetadataStore.end() && "Invalid custom metadata info!");
+ MDMapTy &Info = I->second;
+
+ // FIXME : Give all metadata handlers a chance to adjust.
+
+ // Remove the entries for this instruction.
+ Info.clear();
+ MetadataStore.erase(I);
+}
+
+
+/// getMD - Get the metadata of given kind attached with an Instruction.
+/// If the metadata is not found then return 0.
+MDNode *MetadataContext::getMD(unsigned MDKind, const Instruction *Inst) {
+ MDStoreTy::iterator I = MetadataStore.find(Inst);
+ if (I == MetadataStore.end())
+ return NULL;
+
+ MDMapTy &Info = I->second;
+ for (MDMapTy::iterator I = Info.begin(), E = Info.end(); I != E; ++I)
+ if (I->first == MDKind)
+ return dyn_cast_or_null<MDNode>(I->second);
+ return NULL;
+}
+
+/// getMDs - Get the metadata attached with an Instruction.
+const MetadataContext::MDMapTy *MetadataContext::getMDs(const Instruction *Inst) {
+ MDStoreTy::iterator I = MetadataStore.find(Inst);
+ if (I == MetadataStore.end())
+ return NULL;
+
+ return &(I->second);
+}
+
+/// getHandlerNames - Get handler names. This is used by bitcode
+/// writer.
+const StringMap<unsigned> *MetadataContext::getHandlerNames() {
+ return &MDHandlerNames;
+}
+
+/// ValueIsCloned - This handler is used to update metadata store
+/// when In1 is cloned to create In2.
+void MetadataContext::ValueIsCloned(const Instruction *In1, Instruction *In2) {
+ // Find Metadata handles for In1.
+ MDStoreTy::iterator I = MetadataStore.find(In1);
+ assert (I != MetadataStore.end() && "Invalid custom metadata info!");
+
+ // FIXME : Give all metadata handlers a chance to adjust.
+
+ MDMapTy &In1Info = I->second;
+ MDMapTy In2Info;
+ for (MDMapTy::iterator I = In1Info.begin(), E = In1Info.end(); I != E; ++I)
+ if (MDNode *MD = dyn_cast_or_null<MDNode>(I->second))
+ addMD(I->first, MD, In2);
+}
diff --git a/libclamav/c++/llvm/lib/VMCore/PassManager.cpp b/libclamav/c++/llvm/lib/VMCore/PassManager.cpp
index 375151f..f10bc6f 100644
--- a/libclamav/c++/llvm/lib/VMCore/PassManager.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/PassManager.cpp
@@ -13,6 +13,7 @@
#include "llvm/PassManagers.h"
+#include "llvm/Assembly/Writer.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Timer.h"
#include "llvm/Module.h"
@@ -22,7 +23,6 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/System/Mutex.h"
#include "llvm/System/Threading.h"
-#include "llvm/Analysis/Dominators.h"
#include "llvm-c/Core.h"
#include <algorithm>
#include <cstdio>
@@ -45,16 +45,6 @@ enum PassDebugLevel {
None, Arguments, Structure, Executions, Details
};
-// Always verify dominfo if expensive checking is enabled.
-#ifdef XDEBUG
-bool VerifyDomInfo = true;
-#else
-bool VerifyDomInfo = false;
-#endif
-static cl::opt<bool,true>
-VerifyDomInfoX("verify-dom-info", cl::location(VerifyDomInfo),
- cl::desc("Verify dominator info (time consuming)"));
-
static cl::opt<enum PassDebugLevel>
PassDebugging("debug-pass", cl::Hidden,
cl::desc("Print PassManager debugging information"),
@@ -67,6 +57,15 @@ PassDebugging("debug-pass", cl::Hidden,
clEnumValEnd));
} // End of llvm namespace
+/// isPassDebuggingExecutionsOrMore - Return true if -debug-pass=Executions
+/// or higher is specified.
+bool PMDataManager::isPassDebuggingExecutionsOrMore() const {
+ return PassDebugging >= Executions;
+}
+
+
+
+
void PassManagerPrettyStackEntry::print(raw_ostream &OS) const {
if (V == 0 && M == 0)
OS << "Releasing pass '";
@@ -388,25 +387,19 @@ public:
// null. It may be called multiple times.
static void createTheTimeInfo();
- void passStarted(Pass *P) {
+ /// passStarted - This method creates a timer for the given pass if it doesn't
+ /// already have one, and starts the timer.
+ Timer *passStarted(Pass *P) {
if (dynamic_cast<PMDataManager *>(P))
- return;
+ return 0;
sys::SmartScopedLock<true> Lock(*TimingInfoMutex);
std::map<Pass*, Timer>::iterator I = TimingData.find(P);
if (I == TimingData.end())
I=TimingData.insert(std::make_pair(P, Timer(P->getPassName(), TG))).first;
- I->second.startTimer();
- }
-
- void passEnded(Pass *P) {
- if (dynamic_cast<PMDataManager *>(P))
- return;
-
- sys::SmartScopedLock<true> Lock(*TimingInfoMutex);
- std::map<Pass*, Timer>::iterator I = TimingData.find(P);
- assert(I != TimingData.end() && "passStarted/passEnded not nested right!");
- I->second.stopTimer();
+ Timer *T = &I->second;
+ T->startTimer();
+ return T;
}
};
@@ -700,47 +693,13 @@ void PMDataManager::verifyPreservedAnalysis(Pass *P) {
for (AnalysisUsage::VectorType::const_iterator I = PreservedSet.begin(),
E = PreservedSet.end(); I != E; ++I) {
AnalysisID AID = *I;
- if (Pass *AP = findAnalysisPass(AID, true))
- AP->verifyAnalysis();
- }
-}
-
-/// verifyDomInfo - Verify dominator information if it is available.
-void PMDataManager::verifyDomInfo(Pass &P, Function &F) {
- if (!VerifyDomInfo || !P.getResolver())
- return;
-
- DominatorTree *DT = P.getAnalysisIfAvailable<DominatorTree>();
- if (!DT)
- return;
+ if (Pass *AP = findAnalysisPass(AID, true)) {
- DominatorTree OtherDT;
- OtherDT.getBase().recalculate(F);
- if (DT->compare(OtherDT)) {
- errs() << "Dominator Information for " << F.getName() << "\n";
- errs() << "Pass '" << P.getPassName() << "'\n";
- errs() << "----- Valid -----\n";
- OtherDT.dump();
- errs() << "----- Invalid -----\n";
- DT->dump();
- llvm_unreachable("Invalid dominator info");
- }
-
- DominanceFrontier *DF = P.getAnalysisIfAvailable<DominanceFrontier>();
- if (!DF)
- return;
-
- DominanceFrontier OtherDF;
- std::vector<BasicBlock*> DTRoots = DT->getRoots();
- OtherDF.calculate(*DT, DT->getNode(DTRoots[0]));
- if (DF->compare(OtherDF)) {
- errs() << "Dominator Information for " << F.getName() << "\n";
- errs() << "Pass '" << P.getPassName() << "'\n";
- errs() << "----- Valid -----\n";
- OtherDF.dump();
- errs() << "----- Invalid -----\n";
- DF->dump();
- llvm_unreachable("Invalid dominator info");
+ Timer *T = 0;
+ if (TheTimeInfo) T = TheTimeInfo->passStarted(AP);
+ AP->verifyAnalysis();
+ if (T) T->stopTimer();
+ }
}
}
@@ -806,34 +765,35 @@ void PMDataManager::removeDeadPasses(Pass *P, const StringRef &Msg,
}
for (SmallVector<Pass *, 12>::iterator I = DeadPasses.begin(),
- E = DeadPasses.end(); I != E; ++I) {
+ E = DeadPasses.end(); I != E; ++I)
+ freePass(*I, Msg, DBG_STR);
+}
- dumpPassInfo(*I, FREEING_MSG, DBG_STR, Msg);
+void PMDataManager::freePass(Pass *P, const StringRef &Msg,
+ enum PassDebuggingString DBG_STR) {
+ dumpPassInfo(P, FREEING_MSG, DBG_STR, Msg);
- {
- // If the pass crashes releasing memory, remember this.
- PassManagerPrettyStackEntry X(*I);
-
- if (TheTimeInfo) TheTimeInfo->passStarted(*I);
- (*I)->releaseMemory();
- if (TheTimeInfo) TheTimeInfo->passEnded(*I);
- }
- if (const PassInfo *PI = (*I)->getPassInfo()) {
- std::map<AnalysisID, Pass*>::iterator Pos =
- AvailableAnalysis.find(PI);
+ {
+ // If the pass crashes releasing memory, remember this.
+ PassManagerPrettyStackEntry X(P);
+
+ Timer *T = StartPassTimer(P);
+ P->releaseMemory();
+ StopPassTimer(P, T);
+ }
- // It is possible that pass is already removed from the AvailableAnalysis
- if (Pos != AvailableAnalysis.end())
- AvailableAnalysis.erase(Pos);
+ if (const PassInfo *PI = P->getPassInfo()) {
+ // Remove the pass itself (if it is not already removed).
+ AvailableAnalysis.erase(PI);
- // Remove all interfaces this pass implements, for which it is also
- // listed as the available implementation.
- const std::vector<const PassInfo*> &II = PI->getInterfacesImplemented();
- for (unsigned i = 0, e = II.size(); i != e; ++i) {
- Pos = AvailableAnalysis.find(II[i]);
- if (Pos != AvailableAnalysis.end() && Pos->second == *I)
- AvailableAnalysis.erase(Pos);
- }
+ // Remove all interfaces this pass implements, for which it is also
+ // listed as the available implementation.
+ const std::vector<const PassInfo*> &II = PI->getInterfacesImplemented();
+ for (unsigned i = 0, e = II.size(); i != e; ++i) {
+ std::map<AnalysisID, Pass*>::iterator Pos =
+ AvailableAnalysis.find(II[i]);
+ if (Pos != AvailableAnalysis.end() && Pos->second == P)
+ AvailableAnalysis.erase(Pos);
}
}
}
@@ -1041,10 +1001,10 @@ void PMDataManager::dumpPassInfo(Pass *P, enum PassDebuggingString S1,
errs() << "' on Module '" << Msg << "'...\n";
break;
case ON_LOOP_MSG:
- errs() << "' on Loop " << Msg << "'...\n";
+ errs() << "' on Loop '" << Msg << "'...\n";
break;
case ON_CG_MSG:
- errs() << "' on Call Graph " << Msg << "'...\n";
+ errs() << "' on Call Graph Nodes '" << Msg << "'...\n";
break;
default:
break;
@@ -1076,10 +1036,10 @@ void PMDataManager::dumpAnalysisUsage(const StringRef &Msg, const Pass *P,
return;
errs() << (void*)P << std::string(getDepth()*2+3, ' ') << Msg << " Analyses:";
for (unsigned i = 0; i != Set.size(); ++i) {
- if (i) errs() << ",";
- errs() << " " << Set[i]->getPassName();
+ if (i) errs() << ',';
+ errs() << ' ' << Set[i]->getPassName();
}
- errs() << "\n";
+ errs() << '\n';
}
/// Add RequiredPass into list of lower level passes required by pass P.
@@ -1152,9 +1112,9 @@ bool BBPassManager::runOnFunction(Function &F) {
// If the pass crashes, remember this.
PassManagerPrettyStackEntry X(BP, *I);
- if (TheTimeInfo) TheTimeInfo->passStarted(BP);
+ Timer *T = StartPassTimer(BP);
Changed |= BP->runOnBasicBlock(*I);
- if (TheTimeInfo) TheTimeInfo->passEnded(BP);
+ StopPassTimer(BP, T);
}
if (Changed)
@@ -1367,9 +1327,9 @@ bool FPPassManager::runOnFunction(Function &F) {
{
PassManagerPrettyStackEntry X(FP, F);
- if (TheTimeInfo) TheTimeInfo->passStarted(FP);
+ Timer *T = StartPassTimer(FP);
Changed |= FP->runOnFunction(F);
- if (TheTimeInfo) TheTimeInfo->passEnded(FP);
+ StopPassTimer(FP, T);
}
if (Changed)
@@ -1380,9 +1340,6 @@ bool FPPassManager::runOnFunction(Function &F) {
removeNotPreservedAnalysis(FP);
recordAvailableAnalysis(FP);
removeDeadPasses(FP, F.getName(), ON_FUNCTION_MSG);
-
- // If dominator information is available then verify the info if requested.
- verifyDomInfo(*FP, F);
}
return Changed;
}
@@ -1443,9 +1400,9 @@ MPPassManager::runOnModule(Module &M) {
{
PassManagerPrettyStackEntry X(MP, M);
- if (TheTimeInfo) TheTimeInfo->passStarted(MP);
+ Timer *T = StartPassTimer(MP);
Changed |= MP->runOnModule(M);
- if (TheTimeInfo) TheTimeInfo->passEnded(MP);
+ StopPassTimer(MP, T);
}
if (Changed)
@@ -1581,15 +1538,15 @@ void TimingInfo::createTheTimeInfo() {
}
/// If TimingInfo is enabled then start pass timer.
-void llvm::StartPassTimer(Pass *P) {
+Timer *llvm::StartPassTimer(Pass *P) {
if (TheTimeInfo)
- TheTimeInfo->passStarted(P);
+ return TheTimeInfo->passStarted(P);
+ return 0;
}
/// If TimingInfo is enabled then stop pass timer.
-void llvm::StopPassTimer(Pass *P) {
- if (TheTimeInfo)
- TheTimeInfo->passEnded(P);
+void llvm::StopPassTimer(Pass *P, Timer *T) {
+ if (T) T->stopTimer();
}
//===----------------------------------------------------------------------===//
diff --git a/libclamav/c++/llvm/lib/VMCore/Type.cpp b/libclamav/c++/llvm/lib/VMCore/Type.cpp
index 1abeffa..087464d 100644
--- a/libclamav/c++/llvm/lib/VMCore/Type.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/Type.cpp
@@ -42,6 +42,9 @@ using namespace llvm;
AbstractTypeUser::~AbstractTypeUser() {}
+void AbstractTypeUser::setType(Value *V, const Type *NewTy) {
+ V->VTy = NewTy;
+}
//===----------------------------------------------------------------------===//
// Type Class Implementation
@@ -362,38 +365,14 @@ const IntegerType *Type::getInt64Ty(LLVMContext &C) {
/// isValidReturnType - Return true if the specified type is valid as a return
/// type.
bool FunctionType::isValidReturnType(const Type *RetTy) {
- if (RetTy->isFirstClassType()) {
- if (const PointerType *PTy = dyn_cast<PointerType>(RetTy))
- return PTy->getElementType() != Type::getMetadataTy(RetTy->getContext());
- return true;
- }
- if (RetTy == Type::getVoidTy(RetTy->getContext()) ||
- RetTy == Type::getMetadataTy(RetTy->getContext()) ||
- isa<OpaqueType>(RetTy))
- return true;
-
- // If this is a multiple return case, verify that each return is a first class
- // value and that there is at least one value.
- const StructType *SRetTy = dyn_cast<StructType>(RetTy);
- if (SRetTy == 0 || SRetTy->getNumElements() == 0)
- return false;
-
- for (unsigned i = 0, e = SRetTy->getNumElements(); i != e; ++i)
- if (!SRetTy->getElementType(i)->isFirstClassType())
- return false;
- return true;
+ return RetTy->getTypeID() != LabelTyID &&
+ RetTy->getTypeID() != MetadataTyID;
}
/// isValidArgumentType - Return true if the specified type is valid as an
/// argument type.
bool FunctionType::isValidArgumentType(const Type *ArgTy) {
- if ((!ArgTy->isFirstClassType() && !isa<OpaqueType>(ArgTy)) ||
- (isa<PointerType>(ArgTy) &&
- cast<PointerType>(ArgTy)->getElementType() ==
- Type::getMetadataTy(ArgTy->getContext())))
- return false;
-
- return true;
+ return ArgTy->isFirstClassType() || isa<OpaqueType>(ArgTy);
}
FunctionType::FunctionType(const Type *Result,
@@ -509,9 +488,11 @@ void DerivedType::dropAllTypeUses() {
// Change the rest of the types to be Int32Ty's. It doesn't matter what we
// pick so long as it doesn't point back to this type. We choose something
- // concrete to avoid overhead for adding to AbstracTypeUser lists and stuff.
+ // concrete to avoid overhead for adding to AbstractTypeUser lists and
+ // stuff.
+ const Type *ConcreteTy = Type::getInt32Ty(getContext());
for (unsigned i = 1, e = NumContainedTys; i != e; ++i)
- ContainedTys[i] = Type::getInt32Ty(getContext());
+ ContainedTys[i] = ConcreteTy;
}
}
@@ -828,16 +809,8 @@ ArrayType *ArrayType::get(const Type *ElementType, uint64_t NumElements) {
}
bool ArrayType::isValidElementType(const Type *ElemTy) {
- if (ElemTy == Type::getVoidTy(ElemTy->getContext()) ||
- ElemTy == Type::getLabelTy(ElemTy->getContext()) ||
- ElemTy == Type::getMetadataTy(ElemTy->getContext()))
- return false;
-
- if (const PointerType *PTy = dyn_cast<PointerType>(ElemTy))
- if (PTy->getElementType() == Type::getMetadataTy(ElemTy->getContext()))
- return false;
-
- return true;
+ return ElemTy->getTypeID() != VoidTyID && ElemTy->getTypeID() != LabelTyID &&
+ ElemTy->getTypeID() != MetadataTyID && !isa<FunctionType>(ElemTy);
}
VectorType *VectorType::get(const Type *ElementType, unsigned NumElements) {
@@ -861,11 +834,8 @@ VectorType *VectorType::get(const Type *ElementType, unsigned NumElements) {
}
bool VectorType::isValidElementType(const Type *ElemTy) {
- if (ElemTy->isInteger() || ElemTy->isFloatingPoint() ||
- isa<OpaqueType>(ElemTy))
- return true;
-
- return false;
+ return ElemTy->isInteger() || ElemTy->isFloatingPoint() ||
+ isa<OpaqueType>(ElemTy);
}
//===----------------------------------------------------------------------===//
@@ -908,16 +878,8 @@ StructType *StructType::get(LLVMContext &Context, const Type *type, ...) {
}
bool StructType::isValidElementType(const Type *ElemTy) {
- if (ElemTy == Type::getVoidTy(ElemTy->getContext()) ||
- ElemTy == Type::getLabelTy(ElemTy->getContext()) ||
- ElemTy == Type::getMetadataTy(ElemTy->getContext()))
- return false;
-
- if (const PointerType *PTy = dyn_cast<PointerType>(ElemTy))
- if (PTy->getElementType() == Type::getMetadataTy(ElemTy->getContext()))
- return false;
-
- return true;
+ return ElemTy->getTypeID() != VoidTyID && ElemTy->getTypeID() != LabelTyID &&
+ ElemTy->getTypeID() != MetadataTyID && !isa<FunctionType>(ElemTy);
}
@@ -927,7 +889,7 @@ bool StructType::isValidElementType(const Type *ElemTy) {
PointerType *PointerType::get(const Type *ValueType, unsigned AddressSpace) {
assert(ValueType && "Can't get a pointer to <null> type!");
- assert(ValueType != Type::getVoidTy(ValueType->getContext()) &&
+ assert(ValueType->getTypeID() != VoidTyID &&
"Pointer to void is not valid, use i8* instead!");
assert(isValidElementType(ValueType) && "Invalid type for pointer element!");
PointerValType PVT(ValueType, AddressSpace);
@@ -954,15 +916,9 @@ PointerType *Type::getPointerTo(unsigned addrs) const {
}
bool PointerType::isValidElementType(const Type *ElemTy) {
- if (ElemTy == Type::getVoidTy(ElemTy->getContext()) ||
- ElemTy == Type::getLabelTy(ElemTy->getContext()))
- return false;
-
- if (const PointerType *PTy = dyn_cast<PointerType>(ElemTy))
- if (PTy->getElementType() == Type::getMetadataTy(ElemTy->getContext()))
- return false;
-
- return true;
+ return ElemTy->getTypeID() != VoidTyID &&
+ ElemTy->getTypeID() != LabelTyID &&
+ ElemTy->getTypeID() != MetadataTyID;
}
@@ -1046,7 +1002,7 @@ void DerivedType::unlockedRefineAbstractTypeTo(const Type *NewType) {
// refined, that we will not continue using a dead reference...
//
PATypeHolder NewTy(NewType);
- // Any PATypeHolders referring to this type will now automatically forward o
+ // Any PATypeHolders referring to this type will now automatically forward to
// the type we are resolved to.
ForwardType = NewType;
if (NewType->isAbstract())
diff --git a/libclamav/c++/llvm/lib/VMCore/TypeSymbolTable.cpp b/libclamav/c++/llvm/lib/VMCore/TypeSymbolTable.cpp
index eba2e00..f31ea66 100644
--- a/libclamav/c++/llvm/lib/VMCore/TypeSymbolTable.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/TypeSymbolTable.cpp
@@ -79,7 +79,7 @@ Type* TypeSymbolTable::remove(iterator Entry) {
#if DEBUG_SYMBOL_TABLE
dump();
- errs() << " Removing Value: " << Result->getName() << "\n";
+ errs() << " Removing Value: " << Result->getDescription() << "\n";
#endif
tmap.erase(Entry);
diff --git a/libclamav/c++/llvm/lib/VMCore/Use.cpp b/libclamav/c++/llvm/lib/VMCore/Use.cpp
index b25415a..b7fd92f 100644
--- a/libclamav/c++/llvm/lib/VMCore/Use.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/Use.cpp
@@ -128,7 +128,7 @@ void Use::zap(Use *Start, const Use *Stop, bool del) {
// AugmentedUse layout struct
//===----------------------------------------------------------------------===//
-struct AugmentedUse : Use {
+struct AugmentedUse : public Use {
PointerIntPair<User*, 1, Tag> ref;
AugmentedUse(); // not implemented
};
diff --git a/libclamav/c++/llvm/lib/VMCore/Value.cpp b/libclamav/c++/llvm/lib/VMCore/Value.cpp
index f674062..9fce24a 100644
--- a/libclamav/c++/llvm/lib/VMCore/Value.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/Value.cpp
@@ -44,8 +44,8 @@ static inline const Type *checkType(const Type *Ty) {
}
Value::Value(const Type *ty, unsigned scid)
- : SubclassID(scid), HasValueHandle(0), SubclassOptionalData(0),
- SubclassData(0), VTy(checkType(ty)),
+ : SubclassID(scid), HasValueHandle(0), HasMetadata(0),
+ SubclassOptionalData(0), SubclassData(0), VTy(checkType(ty)),
UseList(0), Name(0) {
if (isa<CallInst>(this) || isa<InvokeInst>(this))
assert((VTy->isFirstClassType() ||
@@ -60,10 +60,15 @@ Value::Value(const Type *ty, unsigned scid)
}
Value::~Value() {
+ if (HasMetadata) {
+ LLVMContext &Context = getContext();
+ Context.pImpl->TheMetadata.ValueIsDeleted(this);
+ }
+
// Notify all ValueHandles (if present) that this value is going away.
if (HasValueHandle)
ValueHandleBase::ValueIsDeleted(this);
-
+
#ifndef NDEBUG // Only in -g mode...
// Check to make sure that there are no uses of this value that are still
// around when the value is destroyed. If there are, then we have a dangling
@@ -84,7 +89,7 @@ Value::~Value() {
// at this point.
if (Name)
Name->Destroy();
-
+
// There should be no uses of this object anymore, remove it.
LeakDetector::removeGarbageObject(this);
}
@@ -137,13 +142,13 @@ static bool getSymTab(Value *V, ValueSymbolTable *&ST) {
if (Function *PP = P->getParent())
ST = &PP->getValueSymbolTable();
} else if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
- if (Function *P = BB->getParent())
+ if (Function *P = BB->getParent())
ST = &P->getValueSymbolTable();
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
- if (Module *P = GV->getParent())
+ if (Module *P = GV->getParent())
ST = &P->getValueSymbolTable();
} else if (Argument *A = dyn_cast<Argument>(V)) {
- if (Function *P = A->getParent())
+ if (Function *P = A->getParent())
ST = &P->getValueSymbolTable();
} else if (NamedMDNode *N = dyn_cast<NamedMDNode>(V)) {
if (Module *P = N->getParent()) {
@@ -187,7 +192,7 @@ void Value::setName(const Twine &NewName) {
assert(getType() != Type::getVoidTy(getContext()) &&
"Cannot assign a name to void values!");
-
+
// Get the symbol table to update for this object.
ValueSymbolTable *ST;
if (getSymTab(this, ST))
@@ -200,19 +205,19 @@ void Value::setName(const Twine &NewName) {
Name = 0;
return;
}
-
+
if (Name)
Name->Destroy();
-
+
// NOTE: Could optimize for the case the name is shrinking to not deallocate
// then reallocated.
-
+
// Create the new name.
Name = ValueName::Create(NameStr, NameStr+NameLen);
Name->setValue(this);
return;
}
-
+
// NOTE: Could optimize for the case the name is shrinking to not deallocate
// then reallocated.
if (hasName()) {
@@ -231,7 +236,7 @@ void Value::setName(const Twine &NewName) {
/// takeName - transfer the name from V to this value, setting V's name to
-/// empty. It is an error to call V->takeName(V).
+/// empty. It is an error to call V->takeName(V).
void Value::takeName(Value *V) {
ValueSymbolTable *ST = 0;
// If this value has a name, drop it.
@@ -243,19 +248,19 @@ void Value::takeName(Value *V) {
if (V->hasName()) V->setName("");
return; // Cannot set a name on this value (e.g. constant).
}
-
+
// Remove old name.
if (ST)
ST->removeValueName(Name);
Name->Destroy();
Name = 0;
- }
-
+ }
+
// Now we know that this has no name.
-
+
// If V has no name either, we're done.
if (!V->hasName()) return;
-
+
// Get this's symtab if we didn't before.
if (!ST) {
if (getSymTab(this, ST)) {
@@ -264,12 +269,12 @@ void Value::takeName(Value *V) {
return; // Cannot set a name on this value (e.g. constant).
}
}
-
+
// Get V's ST, this should always succed, because V has a name.
ValueSymbolTable *VST;
bool Failure = getSymTab(V, VST);
assert(!Failure && "V has a name, so it should have a ST!"); Failure=Failure;
-
+
// If these values are both in the same symtab, we can do this very fast.
// This works even if both values have no symtab yet.
if (ST == VST) {
@@ -279,16 +284,16 @@ void Value::takeName(Value *V) {
Name->setValue(this);
return;
}
-
+
// Otherwise, things are slightly more complex. Remove V's name from VST and
// then reinsert it into ST.
-
+
if (VST)
VST->removeValueName(V->Name);
Name = V->Name;
V->Name = 0;
Name->setValue(this);
-
+
if (ST)
ST->reinsertValue(this);
}
@@ -304,7 +309,7 @@ void Value::uncheckedReplaceAllUsesWith(Value *New) {
// Notify all ValueHandles (if present) that this value is going away.
if (HasValueHandle)
ValueHandleBase::ValueIsRAUWd(this, New);
-
+
while (!use_empty()) {
Use &U = *UseList;
// Must handle Constants specially, we cannot call replaceUsesOfWith on a
@@ -315,7 +320,7 @@ void Value::uncheckedReplaceAllUsesWith(Value *New) {
continue;
}
}
-
+
U.set(New);
}
}
@@ -377,7 +382,7 @@ Value *Value::getUnderlyingObject() {
/// return the value in the PHI node corresponding to PredBB. If not, return
/// ourself. This is useful if you want to know the value something has in a
/// predecessor block.
-Value *Value::DoPHITranslation(const BasicBlock *CurBB,
+Value *Value::DoPHITranslation(const BasicBlock *CurBB,
const BasicBlock *PredBB) {
PHINode *PN = dyn_cast<PHINode>(this);
if (PN && PN->getParent() == CurBB)
@@ -395,7 +400,7 @@ LLVMContext &Value::getContext() const { return VTy->getContext(); }
/// List is known to point into the existing use list.
void ValueHandleBase::AddToExistingUseList(ValueHandleBase **List) {
assert(List && "Handle list is null?");
-
+
// Splice ourselves into the list.
Next = *List;
*List = this;
@@ -409,9 +414,9 @@ void ValueHandleBase::AddToExistingUseList(ValueHandleBase **List) {
/// AddToUseList - Add this ValueHandle to the use list for VP.
void ValueHandleBase::AddToUseList() {
assert(VP && "Null pointer doesn't have a use list!");
-
+
LLVMContextImpl *pImpl = VP->getContext().pImpl;
-
+
if (VP->HasValueHandle) {
// If this value already has a ValueHandle, then it must be in the
// ValueHandles map already.
@@ -420,7 +425,7 @@ void ValueHandleBase::AddToUseList() {
AddToExistingUseList(&Entry);
return;
}
-
+
// Ok, it doesn't have any handles yet, so we must insert it into the
// DenseMap. However, doing this insertion could cause the DenseMap to
// reallocate itself, which would invalidate all of the PrevP pointers that
@@ -428,19 +433,19 @@ void ValueHandleBase::AddToUseList() {
// updating the stale pointers only if needed.
DenseMap<Value*, ValueHandleBase*> &Handles = pImpl->ValueHandles;
const void *OldBucketPtr = Handles.getPointerIntoBucketsArray();
-
+
ValueHandleBase *&Entry = Handles[VP];
assert(Entry == 0 && "Value really did already have handles?");
AddToExistingUseList(&Entry);
VP->HasValueHandle = true;
-
+
// If reallocation didn't happen or if this was the first insertion, don't
// walk the table.
- if (Handles.isPointerIntoBucketsArray(OldBucketPtr) ||
+ if (Handles.isPointerIntoBucketsArray(OldBucketPtr) ||
Handles.size() == 1) {
return;
}
-
+
// Okay, reallocation did happen. Fix the Prev Pointers.
for (DenseMap<Value*, ValueHandleBase*>::iterator I = Handles.begin(),
E = Handles.end(); I != E; ++I) {
@@ -456,14 +461,14 @@ void ValueHandleBase::RemoveFromUseList() {
// Unlink this from its use list.
ValueHandleBase **PrevPtr = getPrevPtr();
assert(*PrevPtr == this && "List invariant broken");
-
+
*PrevPtr = Next;
if (Next) {
assert(Next->getPrevPtr() == &Next && "List invariant broken");
Next->setPrevPtr(PrevPtr);
return;
}
-
+
// If the Next pointer was null, then it is possible that this was the last
// ValueHandle watching VP. If so, delete its entry from the ValueHandles
// map.
@@ -484,12 +489,12 @@ void ValueHandleBase::ValueIsDeleted(Value *V) {
LLVMContextImpl *pImpl = V->getContext().pImpl;
ValueHandleBase *Entry = pImpl->ValueHandles[V];
assert(Entry && "Value bit set but no entries exist");
-
+
while (Entry) {
// Advance pointer to avoid invalidation.
ValueHandleBase *ThisNode = Entry;
Entry = Entry->Next;
-
+
switch (ThisNode->getKind()) {
case Assert:
#ifndef NDEBUG // Only in -g mode...
@@ -498,6 +503,11 @@ void ValueHandleBase::ValueIsDeleted(Value *V) {
#endif
llvm_unreachable("An asserting value handle still pointed to this"
" value!");
+ case Tracking:
+ // Mark that this value has been deleted by setting it to an invalid Value
+ // pointer.
+ ThisNode->operator=(DenseMapInfo<Value *>::getTombstoneKey());
+ break;
case Weak:
// Weak just goes to null, which will unlink it from the list.
ThisNode->operator=(0);
@@ -508,7 +518,7 @@ void ValueHandleBase::ValueIsDeleted(Value *V) {
break;
}
}
-
+
// All callbacks and weak references should be dropped by now.
assert(!V->HasValueHandle && "All references to V were not removed?");
}
@@ -517,23 +527,30 @@ void ValueHandleBase::ValueIsDeleted(Value *V) {
void ValueHandleBase::ValueIsRAUWd(Value *Old, Value *New) {
assert(Old->HasValueHandle &&"Should only be called if ValueHandles present");
assert(Old != New && "Changing value into itself!");
-
+
// Get the linked list base, which is guaranteed to exist since the
// HasValueHandle flag is set.
LLVMContextImpl *pImpl = Old->getContext().pImpl;
ValueHandleBase *Entry = pImpl->ValueHandles[Old];
assert(Entry && "Value bit set but no entries exist");
-
+
while (Entry) {
// Advance pointer to avoid invalidation.
ValueHandleBase *ThisNode = Entry;
Entry = Entry->Next;
-
+
switch (ThisNode->getKind()) {
case Assert:
// Asserting handle does not follow RAUW implicitly.
break;
+ case Tracking:
+ // Tracking goes to new value like a WeakVH. Note that this may make it
+ // something incompatible with its templated type. We don't want to have a
+ // virtual (or inline) interface to handle this though, so instead we make
+ // the TrackingVH accessors guarantee that a client never sees this value.
+
+ // FALLTHROUGH
case Weak:
// Weak goes to the new value, which will unlink it from Old's list.
ThisNode->operator=(New);
diff --git a/libclamav/c++/llvm/lib/VMCore/Verifier.cpp b/libclamav/c++/llvm/lib/VMCore/Verifier.cpp
index eed4e2d..4f7c847 100644
--- a/libclamav/c++/llvm/lib/VMCore/Verifier.cpp
+++ b/libclamav/c++/llvm/lib/VMCore/Verifier.cpp
@@ -50,12 +50,14 @@
#include "llvm/ModuleProvider.h"
#include "llvm/Pass.h"
#include "llvm/PassManager.h"
+#include "llvm/TypeSymbolTable.h"
#include "llvm/Analysis/Dominators.h"
#include "llvm/Assembly/Writer.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/Support/CallSite.h"
#include "llvm/Support/CFG.h"
#include "llvm/Support/InstVisitor.h"
+#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
@@ -105,8 +107,55 @@ PreVer("preverify", "Preliminary module verification");
static const PassInfo *const PreVerifyID = &PreVer;
namespace {
- struct VISIBILITY_HIDDEN
- Verifier : public FunctionPass, InstVisitor<Verifier> {
+ class TypeSet : public AbstractTypeUser {
+ public:
+ TypeSet() {}
+
+ /// Insert a type into the set of types.
+ bool insert(const Type *Ty) {
+ if (!Types.insert(Ty))
+ return false;
+ if (Ty->isAbstract())
+ Ty->addAbstractTypeUser(this);
+ return true;
+ }
+
+ // Remove ourselves as abstract type listeners for any types that remain
+ // abstract when the TypeSet is destroyed.
+ ~TypeSet() {
+ for (SmallSetVector<const Type *, 16>::iterator I = Types.begin(),
+ E = Types.end(); I != E; ++I) {
+ const Type *Ty = *I;
+ if (Ty->isAbstract())
+ Ty->removeAbstractTypeUser(this);
+ }
+ }
+
+ // Abstract type user interface.
+
+ /// Remove types from the set when refined. Do not insert the type it was
+ /// refined to because that type hasn't been verified yet.
+ void refineAbstractType(const DerivedType *OldTy, const Type *NewTy) {
+ Types.remove(OldTy);
+ OldTy->removeAbstractTypeUser(this);
+ }
+
+ /// Stop listening for changes to a type which is no longer abstract.
+ void typeBecameConcrete(const DerivedType *AbsTy) {
+ AbsTy->removeAbstractTypeUser(this);
+ }
+
+ void dump() const {}
+
+ private:
+ SmallSetVector<const Type *, 16> Types;
+
+ // Disallow copying.
+ TypeSet(const TypeSet &);
+ TypeSet &operator=(const TypeSet &);
+ };
+
+ struct Verifier : public FunctionPass, public InstVisitor<Verifier> {
static char ID; // Pass ID, replacement for typeid
bool Broken; // Is this module found to be broken?
bool RealPass; // Are we not being run by a PassManager?
@@ -114,7 +163,7 @@ namespace {
// What to do if verification fails.
Module *Mod; // Module we are verifying right now
DominatorTree *DT; // Dominator Tree, caution can be null!
-
+
std::string Messages;
raw_string_ostream MessagesStr;
@@ -124,6 +173,9 @@ namespace {
/// an instruction in the same block.
SmallPtrSet<Instruction*, 16> InstsInThisBlock;
+ /// Types - keep track of the types that have been checked already.
+ TypeSet Types;
+
Verifier()
: FunctionPass(&ID),
Broken(false), RealPass(true), action(AbortProcessAction),
@@ -233,9 +285,9 @@ namespace {
void visitFunction(Function &F);
void visitBasicBlock(BasicBlock &BB);
using InstVisitor<Verifier>::visit;
-
+
void visit(Instruction &I);
-
+
void visitTruncInst(TruncInst &I);
void visitZExtInst(ZExtInst &I);
void visitSExtInst(SExtInst &I);
@@ -282,6 +334,7 @@ namespace {
bool isReturnValue, const Value *V);
void VerifyFunctionAttrs(const FunctionType *FT, const AttrListPtr &Attrs,
const Value *V);
+ void VerifyType(const Type *Ty);
void WriteValue(const Value *V) {
if (!V) return;
@@ -314,14 +367,23 @@ namespace {
Broken = true;
}
- void CheckFailed(const Twine &Message, const Value* V1,
- const Type* T2, const Value* V3 = 0) {
+ void CheckFailed(const Twine &Message, const Value *V1,
+ const Type *T2, const Value *V3 = 0) {
MessagesStr << Message.str() << "\n";
WriteValue(V1);
WriteType(T2);
WriteValue(V3);
Broken = true;
}
+
+ void CheckFailed(const Twine &Message, const Type *T1,
+ const Type *T2 = 0, const Type *T3 = 0) {
+ MessagesStr << Message.str() << "\n";
+ WriteType(T1);
+ WriteType(T2);
+ WriteType(T3);
+ Broken = true;
+ }
};
} // End anonymous namespace
@@ -360,14 +422,14 @@ void Verifier::visitGlobalValue(GlobalValue &GV) {
Assert1(!GV.hasDLLImportLinkage() || GV.isDeclaration(),
"Global is marked as dllimport, but not external", &GV);
-
+
Assert1(!GV.hasAppendingLinkage() || isa<GlobalVariable>(GV),
"Only global variables can have appending linkage!", &GV);
if (GV.hasAppendingLinkage()) {
- GlobalVariable &GVar = cast<GlobalVariable>(GV);
- Assert1(isa<ArrayType>(GVar.getType()->getElementType()),
- "Only global arrays can have appending linkage!", &GV);
+ GlobalVariable *GVar = dyn_cast<GlobalVariable>(&GV);
+ Assert1(GVar && isa<ArrayType>(GVar->getType()->getElementType()),
+ "Only global arrays can have appending linkage!", GVar);
}
}
@@ -385,28 +447,6 @@ void Verifier::visitGlobalVariable(GlobalVariable &GV) {
Assert1(!GV.isConstant(), "'common' global may not be marked constant!",
&GV);
}
-
- // Verify that any metadata used in a global initializer points only to
- // other globals.
- if (MDNode *FirstNode = dyn_cast<MDNode>(GV.getInitializer())) {
- SmallVector<const MDNode *, 4> NodesToAnalyze;
- NodesToAnalyze.push_back(FirstNode);
- while (!NodesToAnalyze.empty()) {
- const MDNode *N = NodesToAnalyze.back();
- NodesToAnalyze.pop_back();
-
- for (MDNode::const_elem_iterator I = N->elem_begin(),
- E = N->elem_end(); I != E; ++I)
- if (const Value *V = *I) {
- if (const MDNode *Next = dyn_cast<MDNode>(V))
- NodesToAnalyze.push_back(Next);
- else
- Assert3(isa<Constant>(V),
- "reference to instruction from global metadata node",
- &GV, N, V);
- }
- }
- }
} else {
Assert1(GV.hasExternalLinkage() || GV.hasDLLImportLinkage() ||
GV.hasExternalWeakLinkage(),
@@ -445,6 +485,8 @@ void Verifier::visitGlobalAlias(GlobalAlias &GA) {
}
void Verifier::verifyTypeSymbolTable(TypeSymbolTable &ST) {
+ for (TypeSymbolTable::iterator I = ST.begin(), E = ST.end(); I != E; ++I)
+ VerifyType(I->second);
}
// VerifyParameterAttrs - Check the given attributes for an argument or return
@@ -535,16 +577,17 @@ void Verifier::VerifyFunctionAttrs(const FunctionType *FT,
static bool VerifyAttributeCount(const AttrListPtr &Attrs, unsigned Params) {
if (Attrs.isEmpty())
return true;
-
+
unsigned LastSlot = Attrs.getNumSlots() - 1;
unsigned LastIndex = Attrs.getSlot(LastSlot).Index;
if (LastIndex <= Params
|| (LastIndex == (unsigned)~0
&& (LastSlot == 0 || Attrs.getSlot(LastSlot - 1).Index <= Params)))
return true;
-
+
return false;
}
+
// visitFunction - Verify that a function is ok.
//
void Verifier::visitFunction(Function &F) {
@@ -557,12 +600,12 @@ void Verifier::visitFunction(Function &F) {
"# formal arguments must match # of arguments for function type!",
&F, FT);
Assert1(F.getReturnType()->isFirstClassType() ||
- F.getReturnType() == Type::getVoidTy(F.getContext()) ||
+ F.getReturnType()->getTypeID() == Type::VoidTyID ||
isa<StructType>(F.getReturnType()),
"Functions cannot return aggregate values!", &F);
Assert1(!F.hasStructRetAttr() ||
- F.getReturnType() == Type::getVoidTy(F.getContext()),
+ F.getReturnType()->getTypeID() == Type::VoidTyID,
"Invalid struct return type!", &F);
const AttrListPtr &Attrs = F.getAttributes();
@@ -586,12 +629,9 @@ void Verifier::visitFunction(Function &F) {
"Varargs functions must have C calling conventions!", &F);
break;
}
-
+
bool isLLVMdotName = F.getName().size() >= 5 &&
F.getName().substr(0, 5) == "llvm.";
- if (!isLLVMdotName)
- Assert1(F.getReturnType() != Type::getMetadataTy(F.getContext()),
- "Function may not return metadata unless it's an intrinsic", &F);
// Check that the argument values match the function type for this function...
unsigned i = 0;
@@ -621,9 +661,20 @@ void Verifier::visitFunction(Function &F) {
Assert1(pred_begin(Entry) == pred_end(Entry),
"Entry block to function must not have predecessors!", Entry);
}
+
+ // If this function is actually an intrinsic, verify that it is only used in
+ // direct call/invokes, never having its "address taken".
+ if (F.getIntrinsicID()) {
+ for (Value::use_iterator UI = F.use_begin(), E = F.use_end(); UI != E;++UI){
+ User *U = cast<User>(UI);
+ if ((isa<CallInst>(U) || isa<InvokeInst>(U)) && UI.getOperandNo() == 0)
+ continue; // Direct calls/invokes are ok.
+
+ Assert1(0, "Invalid user of intrinsic instruction!", U);
+ }
+ }
}
-
// verifyBasicBlock - Verify that a basic block is well formed...
//
void Verifier::visitBasicBlock(BasicBlock &BB) {
@@ -640,7 +691,6 @@ void Verifier::visitBasicBlock(BasicBlock &BB) {
std::sort(Preds.begin(), Preds.end());
PHINode *PN;
for (BasicBlock::iterator I = BB.begin(); (PN = dyn_cast<PHINode>(I));++I) {
-
// Ensure that PHI nodes have at least one entry!
Assert1(PN->getNumIncomingValues() != 0,
"PHI nodes must have at least one entry. If the block is dead, "
@@ -688,7 +738,7 @@ void Verifier::visitTerminatorInst(TerminatorInst &I) {
void Verifier::visitReturnInst(ReturnInst &RI) {
Function *F = RI.getParent()->getParent();
unsigned N = RI.getNumOperands();
- if (F->getReturnType() == Type::getVoidTy(RI.getContext()))
+ if (F->getReturnType()->getTypeID() == Type::VoidTyID)
Assert2(N == 0,
"Found return instr that returns non-void in Function of void "
"return type!", &RI, F->getReturnType());
@@ -716,7 +766,7 @@ void Verifier::visitReturnInst(ReturnInst &RI) {
CheckFailed("Function return type does not match operand "
"type of return inst!", &RI, F->getReturnType());
}
-
+
// Check to make sure that the return value has necessary properties for
// terminators...
visitTerminatorInst(RI);
@@ -743,7 +793,6 @@ void Verifier::visitSelectInst(SelectInst &SI) {
visitInstruction(SI);
}
-
/// visitUserOp1 - User defined operators shouldn't live beyond the lifetime of
/// a pass, if any exist, it's an error.
///
@@ -868,8 +917,8 @@ void Verifier::visitSIToFPInst(SIToFPInst &I) {
const Type *SrcTy = I.getOperand(0)->getType();
const Type *DestTy = I.getType();
- bool SrcVec = SrcTy->getTypeID() == Type::VectorTyID;
- bool DstVec = DestTy->getTypeID() == Type::VectorTyID;
+ bool SrcVec = isa<VectorType>(SrcTy);
+ bool DstVec = isa<VectorType>(DestTy);
Assert1(SrcVec == DstVec,
"SIToFP source and dest must both be vector or scalar", &I);
@@ -989,11 +1038,15 @@ void Verifier::visitPHINode(PHINode &PN) {
"PHI nodes not grouped at top of basic block!",
&PN, PN.getParent());
- // Check that all of the operands of the PHI node have the same type as the
- // result.
- for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i)
+ // Check that all of the values of the PHI node have the same type as the
+ // result, and that the incoming blocks are really basic blocks.
+ for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
Assert1(PN.getType() == PN.getIncomingValue(i)->getType(),
"PHI node operands are not the same type as the result!", &PN);
+ Assert1(isa<BasicBlock>(PN.getOperand(
+ PHINode::getOperandNumForIncomingBlock(i))),
+ "PHI node incoming block is not a BasicBlock!", &PN);
+ }
// All other PHI node constraints are checked in the visitBasicBlock method.
@@ -1006,9 +1059,9 @@ void Verifier::VerifyCallSite(CallSite CS) {
Assert1(isa<PointerType>(CS.getCalledValue()->getType()),
"Called function must be a pointer!", I);
const PointerType *FPTy = cast<PointerType>(CS.getCalledValue()->getType());
+
Assert1(isa<FunctionType>(FPTy->getElementType()),
"Called function is not pointer to function type!", I);
-
const FunctionType *FTy = cast<FunctionType>(FPTy->getElementType());
// Verify that the correct number of arguments are being passed
@@ -1048,8 +1101,6 @@ void Verifier::VerifyCallSite(CallSite CS) {
// Verify that there's no metadata unless it's a direct call to an intrinsic.
if (!CS.getCalledFunction() || CS.getCalledFunction()->getName().size() < 5 ||
CS.getCalledFunction()->getName().substr(0, 5) != "llvm.") {
- Assert1(FTy->getReturnType() != Type::getMetadataTy(I->getContext()),
- "Only intrinsics may return metadata", I);
for (FunctionType::param_iterator PI = FTy->param_begin(),
PE = FTy->param_end(); PI != PE; ++PI)
Assert1(PI->get() != Type::getMetadataTy(I->getContext()),
@@ -1214,22 +1265,21 @@ void Verifier::visitGetElementPtrInst(GetElementPtrInst &GEP) {
}
void Verifier::visitLoadInst(LoadInst &LI) {
- const Type *ElTy =
- cast<PointerType>(LI.getOperand(0)->getType())->getElementType();
+ const PointerType *PTy = dyn_cast<PointerType>(LI.getOperand(0)->getType());
+ Assert1(PTy, "Load operand must be a pointer.", &LI);
+ const Type *ElTy = PTy->getElementType();
Assert2(ElTy == LI.getType(),
"Load result type does not match pointer operand type!", &LI, ElTy);
- Assert1(ElTy != Type::getMetadataTy(LI.getContext()),
- "Can't load metadata!", &LI);
visitInstruction(LI);
}
void Verifier::visitStoreInst(StoreInst &SI) {
- const Type *ElTy =
- cast<PointerType>(SI.getOperand(1)->getType())->getElementType();
+ const PointerType *PTy = dyn_cast<PointerType>(SI.getOperand(1)->getType());
+ Assert1(PTy, "Load operand must be a pointer.", &SI);
+ const Type *ElTy = PTy->getElementType();
Assert2(ElTy == SI.getOperand(0)->getType(),
- "Stored value type does not match pointer operand type!", &SI, ElTy);
- Assert1(ElTy != Type::getMetadataTy(SI.getContext()),
- "Can't store metadata!", &SI);
+ "Stored value type does not match pointer operand type!",
+ &SI, ElTy);
visitInstruction(SI);
}
@@ -1273,11 +1323,10 @@ void Verifier::visitInstruction(Instruction &I) {
Assert1(*UI != (User*)&I || !DT->isReachableFromEntry(BB),
"Only PHI nodes may reference their own value!", &I);
}
-
+
// Verify that if this is a terminator that it is at the end of the block.
if (isa<TerminatorInst>(I))
Assert1(BB->getTerminator() == &I, "Terminator not at end of block!", &I);
-
// Check that void typed values don't have names
Assert1(I.getType() != Type::getVoidTy(I.getContext()) || !I.hasName(),
@@ -1285,33 +1334,28 @@ void Verifier::visitInstruction(Instruction &I) {
// Check that the return value of the instruction is either void or a legal
// value type.
- Assert1(I.getType() == Type::getVoidTy(I.getContext()) ||
- I.getType()->isFirstClassType()
- || ((isa<CallInst>(I) || isa<InvokeInst>(I))
- && isa<StructType>(I.getType())),
+ Assert1(I.getType()->getTypeID() == Type::VoidTyID ||
+ I.getType()->isFirstClassType(),
"Instruction returns a non-scalar type!", &I);
- // Check that the instruction doesn't produce metadata or metadata*. Calls
- // all already checked against the callee type.
- Assert1(I.getType() != Type::getMetadataTy(I.getContext()) ||
+ // Check that the instruction doesn't produce metadata. Calls are already
+ // checked against the callee type.
+ Assert1(I.getType()->getTypeID() != Type::MetadataTyID ||
isa<CallInst>(I) || isa<InvokeInst>(I),
"Invalid use of metadata!", &I);
- if (const PointerType *PTy = dyn_cast<PointerType>(I.getType()))
- Assert1(PTy->getElementType() != Type::getMetadataTy(I.getContext()),
- "Instructions may not produce pointer to metadata.", &I);
-
-
// Check that all uses of the instruction, if they are instructions
// themselves, actually have parent basic blocks. If the use is not an
// instruction, it is an error!
for (User::use_iterator UI = I.use_begin(), UE = I.use_end();
UI != UE; ++UI) {
- Assert1(isa<Instruction>(*UI), "Use of instruction is not an instruction!",
- *UI);
- Instruction *Used = cast<Instruction>(*UI);
- Assert2(Used->getParent() != 0, "Instruction referencing instruction not"
- " embedded in a basic block!", &I, Used);
+ if (Instruction *Used = dyn_cast<Instruction>(*UI))
+ Assert2(Used->getParent() != 0, "Instruction referencing instruction not"
+ " embedded in a basic block!", &I, Used);
+ else {
+ CheckFailed("Use of instruction is not an instruction!", *UI);
+ return;
+ }
}
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
@@ -1323,11 +1367,6 @@ void Verifier::visitInstruction(Instruction &I) {
Assert1(0, "Instruction operands must be first-class values!", &I);
}
- if (const PointerType *PTy =
- dyn_cast<PointerType>(I.getOperand(i)->getType()))
- Assert1(PTy->getElementType() != Type::getMetadataTy(I.getContext()),
- "Invalid use of metadata pointer.", &I);
-
if (Function *F = dyn_cast<Function>(I.getOperand(i))) {
// Check to make sure that the "address of" an intrinsic function is never
// taken.
@@ -1361,7 +1400,9 @@ void Verifier::visitInstruction(Instruction &I) {
// value in the predecessor basic blocks they correspond to.
BasicBlock *UseBlock = BB;
if (isa<PHINode>(I))
- UseBlock = cast<BasicBlock>(I.getOperand(i+1));
+ UseBlock = dyn_cast<BasicBlock>(I.getOperand(i+1));
+ Assert2(UseBlock, "Invoke operand is PHI node with bad incoming-BB",
+ Op, &I);
if (isa<PHINode>(I) && UseBlock == OpBlock) {
// Special case of a phi node in the normal destination or the unwind
@@ -1394,9 +1435,9 @@ void Verifier::visitInstruction(Instruction &I) {
} else if (isa<PHINode>(I)) {
// PHI nodes are more difficult than other nodes because they actually
// "use" the value in the predecessor basic blocks they correspond to.
- BasicBlock *PredBB = cast<BasicBlock>(I.getOperand(i+1));
- Assert2(DT->dominates(OpBlock, PredBB) ||
- !DT->isReachableFromEntry(PredBB),
+ BasicBlock *PredBB = dyn_cast<BasicBlock>(I.getOperand(i+1));
+ Assert2(PredBB && (DT->dominates(OpBlock, PredBB) ||
+ !DT->isReachableFromEntry(PredBB)),
"Instruction does not dominate all uses!", Op, &I);
} else {
if (OpBlock == BB) {
@@ -1417,6 +1458,61 @@ void Verifier::visitInstruction(Instruction &I) {
}
}
InstsInThisBlock.insert(&I);
+
+ VerifyType(I.getType());
+}
+
+/// VerifyType - Verify that a type is well formed.
+///
+void Verifier::VerifyType(const Type *Ty) {
+ if (!Types.insert(Ty)) return;
+
+ switch (Ty->getTypeID()) {
+ case Type::FunctionTyID: {
+ const FunctionType *FTy = cast<FunctionType>(Ty);
+
+ const Type *RetTy = FTy->getReturnType();
+ Assert2(FunctionType::isValidReturnType(RetTy),
+ "Function type with invalid return type", RetTy, FTy);
+ VerifyType(RetTy);
+
+ for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i) {
+ const Type *ElTy = FTy->getParamType(i);
+ Assert2(FunctionType::isValidArgumentType(ElTy),
+ "Function type with invalid parameter type", ElTy, FTy);
+ VerifyType(ElTy);
+ }
+ } break;
+ case Type::StructTyID: {
+ const StructType *STy = cast<StructType>(Ty);
+ for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
+ const Type *ElTy = STy->getElementType(i);
+ Assert2(StructType::isValidElementType(ElTy),
+ "Structure type with invalid element type", ElTy, STy);
+ VerifyType(ElTy);
+ }
+ } break;
+ case Type::ArrayTyID: {
+ const ArrayType *ATy = cast<ArrayType>(Ty);
+ Assert1(ArrayType::isValidElementType(ATy->getElementType()),
+ "Array type with invalid element type", ATy);
+ VerifyType(ATy->getElementType());
+ } break;
+ case Type::PointerTyID: {
+ const PointerType *PTy = cast<PointerType>(Ty);
+ Assert1(PointerType::isValidElementType(PTy->getElementType()),
+ "Pointer type with invalid element type", PTy);
+ VerifyType(PTy->getElementType());
+ } break;
+ case Type::VectorTyID: {
+ const VectorType *VTy = cast<VectorType>(Ty);
+ Assert1(VectorType::isValidElementType(VTy->getElementType()),
+ "Vector type with invalid element type", VTy);
+ VerifyType(VTy->getElementType());
+ } break;
+ default:
+ break;
+ }
}
// Flags used by TableGen to mark intrinsic parameters with the
@@ -1430,11 +1526,11 @@ void Verifier::visitIntrinsicFunctionCall(Intrinsic::ID ID, CallInst &CI) {
Function *IF = CI.getCalledFunction();
Assert1(IF->isDeclaration(), "Intrinsic functions should never be defined!",
IF);
-
+
#define GET_INTRINSIC_VERIFIER
#include "llvm/Intrinsics.gen"
#undef GET_INTRINSIC_VERIFIER
-
+
switch (ID) {
default:
break;
@@ -1461,7 +1557,7 @@ void Verifier::visitIntrinsicFunctionCall(Intrinsic::ID ID, CallInst &CI) {
Assert1(isa<Constant>(CI.getOperand(2)),
"llvm.gcroot parameter #2 must be a constant.", &CI);
}
-
+
Assert1(CI.getParent()->getParent()->hasGC(),
"Enclosing function does not use GC.", &CI);
break;
@@ -1660,7 +1756,7 @@ void Verifier::VerifyIntrinsicPrototype(Intrinsic::ID ID, Function *F,
va_list VA;
va_start(VA, ParamNum);
const FunctionType *FTy = F->getFunctionType();
-
+
// For overloaded intrinsics, the Suffix of the function name must match the
// types of the arguments. This variable keeps track of the expected
// suffix, to be checked at the end.
@@ -1761,7 +1857,7 @@ bool llvm::verifyModule(const Module &M, VerifierFailureAction action,
Verifier *V = new Verifier(action);
PM.add(V);
PM.run(const_cast<Module&>(M));
-
+
if (ErrorInfo && V->Broken)
*ErrorInfo = V->MessagesStr.str();
return V->Broken;
diff --git a/libclamav/c++/llvm/test/Analysis/Andersens/2007-11-19-InlineAsm.ll b/libclamav/c++/llvm/test/Analysis/Andersens/2007-11-19-InlineAsm.ll
index c1ab6c7..5ba3499 100644
--- a/libclamav/c++/llvm/test/Analysis/Andersens/2007-11-19-InlineAsm.ll
+++ b/libclamav/c++/llvm/test/Analysis/Andersens/2007-11-19-InlineAsm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -anders-aa -disable-output
+; RUN: opt < %s -anders-aa -disable-output
define void @x(i16 %Y) {
entry:
diff --git a/libclamav/c++/llvm/test/Analysis/Andersens/2008-03-19-External.ll b/libclamav/c++/llvm/test/Analysis/Andersens/2008-03-19-External.ll
index c4f1ff0..a973103 100644
--- a/libclamav/c++/llvm/test/Analysis/Andersens/2008-03-19-External.ll
+++ b/libclamav/c++/llvm/test/Analysis/Andersens/2008-03-19-External.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -anders-aa -gvn | llvm-dis | not grep undef
+; RUN: opt < %s -anders-aa -gvn -S | not grep undef
; PR2160
declare void @f(i32*)
diff --git a/libclamav/c++/llvm/test/Analysis/Andersens/2008-04-07-Memcpy.ll b/libclamav/c++/llvm/test/Analysis/Andersens/2008-04-07-Memcpy.ll
index 9354449..5a50dd5 100644
--- a/libclamav/c++/llvm/test/Analysis/Andersens/2008-04-07-Memcpy.ll
+++ b/libclamav/c++/llvm/test/Analysis/Andersens/2008-04-07-Memcpy.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -anders-aa -gvn | llvm-dis | not grep undef
+; RUN: opt < %s -anders-aa -gvn -S | not grep undef
; PR2169
declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind
diff --git a/libclamav/c++/llvm/test/Analysis/Andersens/2008-12-27-BuiltinWrongType.ll b/libclamav/c++/llvm/test/Analysis/Andersens/2008-12-27-BuiltinWrongType.ll
index 5f5da74..da67511 100644
--- a/libclamav/c++/llvm/test/Analysis/Andersens/2008-12-27-BuiltinWrongType.ll
+++ b/libclamav/c++/llvm/test/Analysis/Andersens/2008-12-27-BuiltinWrongType.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -anders-aa
+; RUN: opt < %s -anders-aa
; PR3262
@.str15 = external global [3 x i8] ; <[3 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/Analysis/Andersens/basictest.ll b/libclamav/c++/llvm/test/Analysis/Andersens/basictest.ll
index 0005e09..47226dd 100644
--- a/libclamav/c++/llvm/test/Analysis/Andersens/basictest.ll
+++ b/libclamav/c++/llvm/test/Analysis/Andersens/basictest.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -anders-aa -aa-eval 2>/dev/null
+; RUN: opt < %s -anders-aa -aa-eval 2>/dev/null
define void @test1() {
%X = malloc i32*
diff --git a/libclamav/c++/llvm/test/Analysis/Andersens/external.ll b/libclamav/c++/llvm/test/Analysis/Andersens/external.ll
index 8a4be25..13c12dc 100644
--- a/libclamav/c++/llvm/test/Analysis/Andersens/external.ll
+++ b/libclamav/c++/llvm/test/Analysis/Andersens/external.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -anders-aa -gvn -deadargelim | llvm-dis | grep store | not grep null
+; RUN: opt < %s -anders-aa -gvn -deadargelim -S | grep store | not grep null
; Because the 'internal' function is passed to an external function, we don't
; know what the incoming values will alias. As such, we cannot do the
diff --git a/libclamav/c++/llvm/test/Analysis/Andersens/modreftest.ll b/libclamav/c++/llvm/test/Analysis/Andersens/modreftest.ll
index f86c7f7..e0c2edc 100644
--- a/libclamav/c++/llvm/test/Analysis/Andersens/modreftest.ll
+++ b/libclamav/c++/llvm/test/Analysis/Andersens/modreftest.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -anders-aa -gvn -instcombine | llvm-dis \
+; RUN: opt < %s -anders-aa -gvn -instcombine -S \
; RUN: | grep {ret i1 true}
@G = internal global i32* null
diff --git a/libclamav/c++/llvm/test/Analysis/Andersens/modreftest2.ll b/libclamav/c++/llvm/test/Analysis/Andersens/modreftest2.ll
index 0ba91df..562c961 100644
--- a/libclamav/c++/llvm/test/Analysis/Andersens/modreftest2.ll
+++ b/libclamav/c++/llvm/test/Analysis/Andersens/modreftest2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -anders-aa -gvn | llvm-dis \
+; RUN: opt < %s -anders-aa -gvn -S \
; RUN: | not grep {ret i32 undef}
;; From PR 2160
diff --git a/libclamav/c++/llvm/test/Analysis/Andersens/trivialtest.ll b/libclamav/c++/llvm/test/Analysis/Andersens/trivialtest.ll
index ce37516..f9f938f 100644
--- a/libclamav/c++/llvm/test/Analysis/Andersens/trivialtest.ll
+++ b/libclamav/c++/llvm/test/Analysis/Andersens/trivialtest.ll
@@ -1,3 +1,3 @@
-; RUN: llvm-as < %s | opt -anders-aa -disable-output
+; RUN: opt < %s -anders-aa -disable-output
define void @foo() { ret void }
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll
index 8ba66df..6b50a16 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll
@@ -2,7 +2,7 @@
; is performed. It is not legal to delete the second load instruction because
; the value computed by the first load instruction is changed by the store.
-; RUN: llvm-as < %s | opt -gvn -instcombine | llvm-dis | grep DONOTREMOVE
+; RUN: opt < %s -gvn -instcombine -S | grep DONOTREMOVE
define i32 @test() {
%A = alloca i32
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-03-04-GEPCrash.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-03-04-GEPCrash.ll
index 0a15deb..4f8eabb 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-03-04-GEPCrash.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-03-04-GEPCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -basicaa -aa-eval -disable-output 2>/dev/null
+; RUN: opt < %s -basicaa -aa-eval -disable-output 2>/dev/null
; Test for a bug in BasicAA which caused a crash when querying equality of P1&P2
define void @test({[2 x i32],[2 x i32]}* %A, i64 %X, i64 %Y) {
%P1 = getelementptr {[2 x i32],[2 x i32]}* %A, i64 0, i32 0, i64 %X
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll
index 4b3cc6a..f7e8295 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -gvn -instcombine | llvm-dis | grep sub
+; RUN: opt < %s -gvn -instcombine -S | grep sub
; BasicAA was incorrectly concluding that P1 and P2 didn't conflict!
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-04-25-GEPCrash.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-04-25-GEPCrash.ll
index 8456131..97bc38e 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-04-25-GEPCrash.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-04-25-GEPCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -basicaa -aa-eval -disable-output 2>/dev/null
+; RUN: opt < %s -basicaa -aa-eval -disable-output 2>/dev/null
; Test for a bug in BasicAA which caused a crash when querying equality of P1&P2
define void @test([17 x i16]* %mask_bits) {
%P1 = getelementptr [17 x i16]* %mask_bits, i64 0, i64 0
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll
index c9049c8..d439dfc 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -licm -disable-output
+; RUN: opt < %s -licm -disable-output
%struct..apr_array_header_t = type { i32*, i32, i32, i32, i8* }
%struct..apr_table_t = type { %struct..apr_array_header_t, i32, [32 x i32], [32 x i32] }
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-06-01-AliasCrash.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-06-01-AliasCrash.ll
index c673a32..0abd384 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-06-01-AliasCrash.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-06-01-AliasCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -basicaa -aa-eval -disable-output 2>/dev/null
+; RUN: opt < %s -basicaa -aa-eval -disable-output 2>/dev/null
define i32 @MTConcat([3 x i32]* %a.1) {
%tmp.961 = getelementptr [3 x i32]* %a.1, i64 0, i64 4
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-07-03-BasicAACrash.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-07-03-BasicAACrash.ll
index d385961..3e813fa 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-07-03-BasicAACrash.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-07-03-BasicAACrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -basicaa -aa-eval -disable-output 2>/dev/null
+; RUN: opt < %s -basicaa -aa-eval -disable-output 2>/dev/null
%struct..RefPoint = type { i32, { i32, i8, i8 } }
%struct..RefRect = type { %struct..RefPoint, %struct..RefPoint }
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll
index e2bb86d..637d8f0 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll
@@ -1,6 +1,6 @@
; In this test, a local alloca cannot alias an incoming argument.
-; RUN: llvm-as < %s | opt -gvn -instcombine | llvm-dis | not grep sub
+; RUN: opt < %s -gvn -instcombine -S | not grep sub
define i32 @test(i32* %P) {
%X = alloca i32
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll
index 99eae16..911f78c 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll
@@ -1,7 +1,7 @@
; This testcase consists of alias relations which should be completely
; resolvable by basicaa.
-; RUN: llvm-as < %s | opt -aa-eval -print-may-aliases -disable-output \
+; RUN: opt < %s -aa-eval -print-may-aliases -disable-output \
; RUN: |& not grep May:
%T = type { i32, [10 x i8] }
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll
index 639cb0a..8166b97 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll
@@ -1,7 +1,7 @@
; This testcase consists of alias relations which should be completely
; resolvable by basicaa, but require analysis of getelementptr constant exprs.
-; RUN: llvm-as < %s | opt -aa-eval -print-may-aliases -disable-output \
+; RUN: opt < %s -aa-eval -print-may-aliases -disable-output \
; RUN: |& not grep May:
%T = type { i32, [10 x i8] }
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll
index 407932c..e1cfd03 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -dse | llvm-dis | grep {store i32 0}
+; RUN: opt < %s -dse -S | grep {store i32 0}
define void @test({i32,i32 }* %P) {
%Q = getelementptr {i32,i32}* %P, i32 1
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2004-12-08-BasicAACrash.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2004-12-08-BasicAACrash.ll
index 58d4da1..81248db 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2004-12-08-BasicAACrash.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2004-12-08-BasicAACrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -licm
+; RUN: opt < %s -licm
%"java/lang/Object" = type { %struct.llvm_java_object_base }
%"java/lang/StringBuffer" = type { "java/lang/Object", i32, { "java/lang/Object", i32, [0 x i8] }*, i1 }
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2004-12-08-BasicAACrash2.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2004-12-08-BasicAACrash2.ll
index d96438f..0e03db3 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2004-12-08-BasicAACrash2.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2004-12-08-BasicAACrash2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -dse
+; RUN: opt < %s -dse
%"java/lang/Object" = type { %struct.llvm_java_object_base }
%"java/lang/StringBuffer" = type { "java/lang/Object", i32, { "java/lang/Object", i32, [0 x i8] }*, i1 }
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2005-03-09-BrokenBasicAA.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2005-03-09-BrokenBasicAA.ll
index 21c86b7..4564263 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2005-03-09-BrokenBasicAA.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2005-03-09-BrokenBasicAA.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -basicaa -gvn -instcombine |\
+; RUN: opt < %s -basicaa -gvn -instcombine |\
; RUN: llvm-dis | grep {load i32\\* %A}
declare double* @useit(i32*)
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll
index b8e3019..5d08312 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -aa-eval -disable-output |& grep {2 no alias respon}
+; RUN: opt < %s -aa-eval -disable-output |& grep {2 no alias respon}
; TEST that A[1][0] may alias A[0][i].
define void @test(i32 %N) {
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll
index cc10e4b..85f53a6 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -licm -disable-output
+; RUN: opt < %s -licm -disable-output
target datalayout = "E-p:32:32"
target triple = "powerpc-apple-darwin8.7.0"
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-01-13-BasePointerBadNoAlias.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-01-13-BasePointerBadNoAlias.ll
index 08c483d..917bf25 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-01-13-BasePointerBadNoAlias.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-01-13-BasePointerBadNoAlias.ll
@@ -1,7 +1,7 @@
; PR1109
-; RUN: llvm-as < %s | opt -basicaa -gvn -instcombine | llvm-dis | \
+; RUN: opt < %s -basicaa -gvn -instcombine -S | \
; RUN: grep {sub i32}
-; RUN: llvm-as < %s | opt -basicaa -gvn -instcombine | llvm-dis | \
+; RUN: opt < %s -basicaa -gvn -instcombine -S | \
; RUN: not grep {ret i32 0}
; END.
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-01-NoAliasAndCalls.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-01-NoAliasAndCalls.ll
index 3b6eb11..e6a26e3 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-01-NoAliasAndCalls.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-01-NoAliasAndCalls.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s -o - | opt -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {MayAlias:.*i32\\* %., i32\\* %.} | grep {%x} | grep {%y}
+; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {MayAlias:.*i32\\* %., i32\\* %.} | grep {%x} | grep {%y}
declare i32* @unclear(i32* %a)
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-01-NoAliasAndGEP.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-01-NoAliasAndGEP.ll
index 9936afb..7f33fa4 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-01-NoAliasAndGEP.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-01-NoAliasAndGEP.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as %s -o - | opt -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {9 no alias}
-; RUN: llvm-as %s -o - | opt -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {6 may alias}
-; RUN: llvm-as %s -o - | opt -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {MayAlias:.*i32\\* %Ipointer, i32\\* %Jpointer}
+; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {9 no alias}
+; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {6 may alias}
+; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {MayAlias:.*i32\\* %Ipointer, i32\\* %Jpointer}
define void @foo(i32* noalias %p, i32* noalias %q, i32 %i, i32 %j) {
%Ipointer = getelementptr i32* %p, i32 %i
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-05-GetOverloadedModRef.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-05-GetOverloadedModRef.ll
index 15aaa02..035299e 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-05-GetOverloadedModRef.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-08-05-GetOverloadedModRef.ll
@@ -1,5 +1,5 @@
; PR1600
-; RUN: llvm-as < %s | opt -basicaa -gvn -instcombine | llvm-dis | \
+; RUN: opt < %s -basicaa -gvn -instcombine -S | \
; RUN: grep {ret i32 0}
; END.
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-10-24-ArgumentsGlobals.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-10-24-ArgumentsGlobals.ll
index 61ab80d..78f24b5 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-10-24-ArgumentsGlobals.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-10-24-ArgumentsGlobals.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -basicaa -gvn -dce | llvm-dis | grep tmp7
+; RUN: opt < %s -basicaa -gvn -dce -S | grep tmp7
%struct.A = type { i32 }
%struct.B = type { %struct.A }
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll
index 5a938cf..f0f1535 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -gvn -disable-output
+; RUN: opt < %s -gvn -disable-output
; PR1774
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll
index 2f0c769..8028afb 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -gvn -disable-output
+; RUN: opt < %s -gvn -disable-output
; PR1782
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2008-04-15-Byval.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2008-04-15-Byval.ll
index ee16909..2069401 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2008-04-15-Byval.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2008-04-15-Byval.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -std-compile-opts | llvm-dis | grep store
+; RUN: opt < %s -std-compile-opts -S | grep store
; ModuleID = 'small2.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll
index 40d1e32..ba29f3a 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -gvn -disable-output
+; RUN: opt < %s -gvn -disable-output
; PR2395
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll
index d2e823e..06018cc 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -aa-eval |& grep {1 no alias response}
+; RUN: opt < %s -aa-eval |& grep {1 no alias response}
declare noalias i32* @_Znwj(i32 %x) nounwind
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2008-12-09-GEP-IndicesAlias.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2008-12-09-GEP-IndicesAlias.ll
index 967a36e..aaf9061 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2008-12-09-GEP-IndicesAlias.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2008-12-09-GEP-IndicesAlias.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -aa-eval -print-all-alias-modref-info -disable-output |& grep {MustAlias:.*%R,.*%r}
+; RUN: opt < %s -aa-eval -print-all-alias-modref-info -disable-output |& grep {MustAlias:.*%R,.*%r}
; Make sure that basicaa thinks R and r are must aliases.
define i32 @test(i8 * %P) {
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/2009-03-04-GEPNoalias.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/2009-03-04-GEPNoalias.ll
index f3891ec..3ab5d03 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/2009-03-04-GEPNoalias.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/2009-03-04-GEPNoalias.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -basicaa -gvn | llvm-dis | grep load
+; RUN: opt < %s -basicaa -gvn -S | grep load
declare noalias i32* @noalias()
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/byval.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/byval.ll
index f064419..cdcafdf 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/byval.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/byval.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -gvn | llvm-dis | grep {ret i32 1}
+; RUN: opt < %s -gvn -S | grep {ret i32 1}
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8"
%struct.x = type { i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/cas.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/cas.ll
index 9bbb5e7..87772bf 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/cas.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/cas.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -basicaa -gvn | llvm-dis | grep load | count 1
+; RUN: opt < %s -basicaa -gvn -S | grep load | count 1
@flag0 = internal global i32 zeroinitializer
@turn = internal global i32 zeroinitializer
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/constant-over-index.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/constant-over-index.ll
index e92995b..95f94d0 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/constant-over-index.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/constant-over-index.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -aa-eval -print-all-alias-modref-info \
+; RUN: opt < %s -aa-eval -print-all-alias-modref-info \
; RUN: |& grep {MayAlias: double\\* \[%\]p.0.i.0, double\\* \[%\]p3\$}
; PR4267
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/featuretest.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/featuretest.ll
index e807f88..737ee45 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/featuretest.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/featuretest.ll
@@ -1,7 +1,7 @@
; This testcase tests for various features the basicaa test should be able to
; determine, as noted in the comments.
-; RUN: llvm-as < %s | opt -basicaa -gvn -instcombine -dce | llvm-dis | not grep REMOVE
+; RUN: opt < %s -basicaa -gvn -instcombine -dce -S | not grep REMOVE
@Global = external global { i32 }
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/gcsetest.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/gcsetest.ll
index 1d55ca9..a903362 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/gcsetest.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/gcsetest.ll
@@ -2,8 +2,8 @@
; disambiguating some obvious cases. All loads should be removable in
; this testcase.
-; RUN: llvm-as < %s | opt -basicaa -gvn -instcombine -dce \
-; RUN: | llvm-dis | not grep load
+; RUN: opt < %s -basicaa -gvn -instcombine -dce -S \
+; RUN: | not grep load
@A = global i32 7
@B = global i32 8
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/global-size.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/global-size.ll
index ce92a69..0a643d4 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/global-size.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/global-size.ll
@@ -1,7 +1,7 @@
; A store or load cannot alias a global if the accessed amount is larger then
; the global.
-; RUN: llvm-as < %s | opt -basicaa -gvn -instcombine | llvm-dis | not grep load
+; RUN: opt < %s -basicaa -gvn -instcombine -S | not grep load
@B = global i16 8 ; <i16*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/modref.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/modref.ll
index 819f956..8f7c0a7 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/modref.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/modref.ll
@@ -1,5 +1,5 @@
; A very rudimentary test on AliasAnalysis::getModRefInfo.
-; RUN: llvm-as < %s | opt -print-all-alias-modref-info -aa-eval -disable-output |& \
+; RUN: opt < %s -print-all-alias-modref-info -aa-eval -disable-output |& \
; RUN: not grep NoModRef
define i32 @callee() {
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/no-escape-call.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/no-escape-call.ll
index ab1fea7..ccabce9 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/no-escape-call.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/no-escape-call.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -basicaa -gvn -instcombine | llvm-dis | grep {ret i1 true}
+; RUN: opt < %s -basicaa -gvn -instcombine -S | grep {ret i1 true}
; PR2436
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/nocapture.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/nocapture.ll
index 0ca444c..7970fbb 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/nocapture.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/nocapture.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -basicaa -gvn -instcombine | llvm-dis | grep {ret i32 0}
+; RUN: opt < %s -basicaa -gvn -instcombine -S | grep {ret i32 0}
declare i32* @test(i32* nocapture)
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/pure-const-dce.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/pure-const-dce.ll
index b01b5c5..54e6e79 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/pure-const-dce.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/pure-const-dce.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | opt -basicaa -gvn | llvm-dis | grep TestConst | count 2
-; RUN: llvm-as < %s | opt -basicaa -gvn | llvm-dis | grep TestPure | count 3
-; RUN: llvm-as < %s | opt -basicaa -gvn | llvm-dis | grep TestNone | count 4
+; RUN: opt < %s -basicaa -gvn -S | grep TestConst | count 2
+; RUN: opt < %s -basicaa -gvn -S | grep TestPure | count 3
+; RUN: opt < %s -basicaa -gvn -S | grep TestNone | count 4
@g = global i32 0 ; <i32*> [#uses=1]
define i32 @test() {
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/store-promote.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/store-promote.ll
index 033a184..d8e7c75 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/store-promote.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/store-promote.ll
@@ -2,7 +2,7 @@
; disambiguating some obvious cases. If LICM is able to disambiguate the
; two pointers, then the load should be hoisted, and the store sunk.
-; RUN: llvm-as < %s | opt -basicaa -licm | llvm-dis | FileCheck %s
+; RUN: opt < %s -basicaa -licm -S | FileCheck %s
@A = global i32 7 ; <i32*> [#uses=3]
@B = global i32 8 ; <i32*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/Analysis/BasicAA/tailcall-modref.ll b/libclamav/c++/llvm/test/Analysis/BasicAA/tailcall-modref.ll
index ac4ea40..f7d6c57 100644
--- a/libclamav/c++/llvm/test/Analysis/BasicAA/tailcall-modref.ll
+++ b/libclamav/c++/llvm/test/Analysis/BasicAA/tailcall-modref.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -basicaa -gvn -instcombine |\
+; RUN: opt < %s -basicaa -gvn -instcombine |\
; RUN: llvm-dis | grep {ret i32 0}
declare void @foo(i32*)
diff --git a/libclamav/c++/llvm/test/Analysis/CallGraph/2008-09-09-DirectCall.ll b/libclamav/c++/llvm/test/Analysis/CallGraph/2008-09-09-DirectCall.ll
index 456ffa2..6e34209 100644
--- a/libclamav/c++/llvm/test/Analysis/CallGraph/2008-09-09-DirectCall.ll
+++ b/libclamav/c++/llvm/test/Analysis/CallGraph/2008-09-09-DirectCall.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -print-callgraph -disable-output |& \
+; RUN: opt < %s -print-callgraph -disable-output |& \
; RUN: grep {Calls function 'callee'} | count 2
define internal void @callee(...) {
diff --git a/libclamav/c++/llvm/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll b/libclamav/c++/llvm/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll
index ffc27bb..12849b7 100644
--- a/libclamav/c++/llvm/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll
+++ b/libclamav/c++/llvm/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -print-callgraph -disable-output |& \
+; RUN: opt < %s -print-callgraph -disable-output |& \
; RUN: grep {Calls function}
@a = global void ()* @f ; <void ()**> [#uses=0]
diff --git a/libclamav/c++/llvm/test/Analysis/Dominators/2006-10-02-BreakCritEdges.ll b/libclamav/c++/llvm/test/Analysis/Dominators/2006-10-02-BreakCritEdges.ll
index 997ee2a..e31f416 100644
--- a/libclamav/c++/llvm/test/Analysis/Dominators/2006-10-02-BreakCritEdges.ll
+++ b/libclamav/c++/llvm/test/Analysis/Dominators/2006-10-02-BreakCritEdges.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -domtree -break-crit-edges -analyze \
+; RUN: opt < %s -domtree -break-crit-edges -analyze \
; RUN: -domtree | grep {3.*%brtrue }
; PR932
diff --git a/libclamav/c++/llvm/test/Analysis/Dominators/2007-01-14-BreakCritEdges.ll b/libclamav/c++/llvm/test/Analysis/Dominators/2007-01-14-BreakCritEdges.ll
index 697dad2..96dc739 100644
--- a/libclamav/c++/llvm/test/Analysis/Dominators/2007-01-14-BreakCritEdges.ll
+++ b/libclamav/c++/llvm/test/Analysis/Dominators/2007-01-14-BreakCritEdges.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -domtree -break-crit-edges -domtree -disable-output
+; RUN: opt < %s -domtree -break-crit-edges -domtree -disable-output
; PR1110
%struct.OggVorbis_File = type { i8*, i32, i64, i64, %struct.ogg_sync_state, i32, i64*, i64*, i32*, i64*, %struct.vorbis_info*, %struct.vorbis_comment*, i64, i32, i32, i32, double, double, %struct.ogg_stream_state, %struct.vorbis_dsp_state, %struct.vorbis_block, %struct.ov_callbacks }
diff --git a/libclamav/c++/llvm/test/Analysis/Dominators/2007-07-11-SplitBlock.ll b/libclamav/c++/llvm/test/Analysis/Dominators/2007-07-11-SplitBlock.ll
index 3dc6eda..52fdd2b 100644
--- a/libclamav/c++/llvm/test/Analysis/Dominators/2007-07-11-SplitBlock.ll
+++ b/libclamav/c++/llvm/test/Analysis/Dominators/2007-07-11-SplitBlock.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -loop-rotate -loop-unswitch -disable-output
+; RUN: opt < %s -loop-rotate -loop-unswitch -disable-output
define i32 @stringSearch_Clib(i32 %count) {
entry:
diff --git a/libclamav/c++/llvm/test/Analysis/Dominators/2007-07-12-SplitBlock.ll b/libclamav/c++/llvm/test/Analysis/Dominators/2007-07-12-SplitBlock.ll
index 1748daf..b46f0c7 100644
--- a/libclamav/c++/llvm/test/Analysis/Dominators/2007-07-12-SplitBlock.ll
+++ b/libclamav/c++/llvm/test/Analysis/Dominators/2007-07-12-SplitBlock.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -loop-rotate -licm -loop-unswitch -disable-output
+; RUN: opt < %s -loop-rotate -licm -loop-unswitch -disable-output
define i32 @main(i32 %argc, i8** %argv) {
entry:
diff --git a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/2008-09-03-ReadGlobals.ll b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/2008-09-03-ReadGlobals.ll
index aba6082..17ace8a 100644
--- a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/2008-09-03-ReadGlobals.ll
+++ b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/2008-09-03-ReadGlobals.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -globalsmodref-aa -gvn | llvm-dis | grep call | count 2
+; RUN: opt < %s -globalsmodref-aa -gvn -S | grep call | count 2
@g = internal global i32 0 ; <i32*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/aliastest.ll b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/aliastest.ll
index 5ea90fe..3e5d119 100644
--- a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/aliastest.ll
+++ b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/aliastest.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -globalsmodref-aa -gvn | llvm-dis | not grep load
+; RUN: opt < %s -globalsmodref-aa -gvn -S | not grep load
@X = internal global i32 4 ; <i32*> [#uses=1]
define i32 @test(i32* %P) {
diff --git a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/chaining-analysis.ll b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/chaining-analysis.ll
index 137b2c1..b1d4593 100644
--- a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/chaining-analysis.ll
+++ b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/chaining-analysis.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -globalsmodref-aa -gvn | llvm-dis | not grep load
+; RUN: opt < %s -globalsmodref-aa -gvn -S | not grep load
; This test requires the use of previous analyses to determine that
; doesnotmodX does not modify X (because 'sin' doesn't).
diff --git a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/indirect-global.ll b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/indirect-global.ll
index ff5a0b9..4074909 100644
--- a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/indirect-global.ll
+++ b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/indirect-global.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -globalsmodref-aa -gvn -instcombine | llvm-dis | \
+; RUN: opt < %s -globalsmodref-aa -gvn -instcombine -S | \
; RUN: grep {ret i32 0}
@G = internal global i32* null ; <i32**> [#uses=3]
diff --git a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/modreftest.ll b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/modreftest.ll
index ffcb84d..257c0ee 100644
--- a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/modreftest.ll
+++ b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/modreftest.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -globalsmodref-aa -gvn | llvm-dis | not grep load
+; RUN: opt < %s -globalsmodref-aa -gvn -S | not grep load
@X = internal global i32 4 ; <i32*> [#uses=2]
define i32 @test(i32* %P) {
diff --git a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/purecse.ll b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/purecse.ll
index dc3f6ad..994aff8 100644
--- a/libclamav/c++/llvm/test/Analysis/GlobalsModRef/purecse.ll
+++ b/libclamav/c++/llvm/test/Analysis/GlobalsModRef/purecse.ll
@@ -1,5 +1,5 @@
; Test that pure functions are cse'd away
-; RUN: llvm-as < %s | opt -globalsmodref-aa -gvn -instcombine | \
+; RUN: opt < %s -globalsmodref-aa -gvn -instcombine | \
; RUN: llvm-dis | not grep sub
define i32 @pure(i32 %X) {
diff --git a/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/alias.ll b/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/alias.ll
index 46d38af..a5f504b 100644
--- a/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/alias.ll
+++ b/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/alias.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -disable-output -analyze -lda | FileCheck %s
+; RUN: opt < %s -disable-output -analyze -lda | FileCheck %s
;; x[5] = x[6] // with x being a pointer passed as argument
diff --git a/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-strong.ll b/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-strong.ll
index 7b9296e..3270895 100644
--- a/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-strong.ll
+++ b/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-strong.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -disable-output -analyze -lda | FileCheck %s
+; RUN: opt < %s -disable-output -analyze -lda | FileCheck %s
@x = common global [256 x i32] zeroinitializer, align 4
@y = common global [256 x i32] zeroinitializer, align 4
diff --git a/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-weak-crossing.ll b/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-weak-crossing.ll
index 1e37750..3d9f258 100644
--- a/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-weak-crossing.ll
+++ b/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-weak-crossing.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -disable-output -analyze -lda | FileCheck %s
+; RUN: opt < %s -disable-output -analyze -lda | FileCheck %s
@x = common global [256 x i32] zeroinitializer, align 4
@y = common global [256 x i32] zeroinitializer, align 4
diff --git a/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-weak-zero.ll b/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-weak-zero.ll
index 72fc2db..4433138 100644
--- a/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-weak-zero.ll
+++ b/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/siv-weak-zero.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -disable-output -analyze -lda | FileCheck %s
+; RUN: opt < %s -disable-output -analyze -lda | FileCheck %s
@x = common global [256 x i32] zeroinitializer, align 4
@y = common global [256 x i32] zeroinitializer, align 4
diff --git a/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/ziv.ll b/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/ziv.ll
index 3b265ba..0a93762 100644
--- a/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/ziv.ll
+++ b/libclamav/c++/llvm/test/Analysis/LoopDependenceAnalysis/ziv.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -disable-output -analyze -lda | FileCheck %s
+; RUN: opt < %s -disable-output -analyze -lda | FileCheck %s
@x = common global [256 x i32] zeroinitializer, align 4
diff --git a/libclamav/c++/llvm/test/Analysis/LoopInfo/2003-05-15-NestingProblem.ll b/libclamav/c++/llvm/test/Analysis/LoopInfo/2003-05-15-NestingProblem.ll
index 34b9c44..617c23f 100644
--- a/libclamav/c++/llvm/test/Analysis/LoopInfo/2003-05-15-NestingProblem.ll
+++ b/libclamav/c++/llvm/test/Analysis/LoopInfo/2003-05-15-NestingProblem.ll
@@ -1,7 +1,7 @@
; This testcase was incorrectly computing that the loopentry.7 loop was
; not a child of the loopentry.6 loop.
;
-; RUN: llvm-as < %s | opt -analyze -loops | \
+; RUN: opt < %s -analyze -loops | \
; RUN: grep {^ Loop at depth 4 containing: %loopentry.7<header><latch><exit>}
define void @getAndMoveToFrontDecode() {
diff --git a/libclamav/c++/llvm/test/Analysis/PointerTracking/sizes.ll b/libclamav/c++/llvm/test/Analysis/PointerTracking/sizes.ll
index 5da4dcc..c0b0606 100644
--- a/libclamav/c++/llvm/test/Analysis/PointerTracking/sizes.ll
+++ b/libclamav/c++/llvm/test/Analysis/PointerTracking/sizes.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -pointertracking -analyze | FileCheck %s
+; RUN: opt < %s -pointertracking -analyze | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
@.str = internal constant [5 x i8] c"1234\00" ; <[5 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll b/libclamav/c++/llvm/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll
index b272f92..b73b7f0 100644
--- a/libclamav/c++/llvm/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll
+++ b/libclamav/c++/llvm/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -postdomfrontier \
+; RUN: opt < %s -analyze -postdomfrontier \
; RUN: -disable-verify
; ModuleID = '2006-09-26-PostDominanceFrontier.bc'
target datalayout = "e-p:64:64"
diff --git a/libclamav/c++/llvm/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll b/libclamav/c++/llvm/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll
index 51e4c2a..1ec056b 100644
--- a/libclamav/c++/llvm/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll
+++ b/libclamav/c++/llvm/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -postdomfrontier -disable-output
+; RUN: opt < %s -postdomfrontier -disable-output
define void @SManager() {
entry:
diff --git a/libclamav/c++/llvm/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll b/libclamav/c++/llvm/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll
index 4deec98..767e5db 100644
--- a/libclamav/c++/llvm/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll
+++ b/libclamav/c++/llvm/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -postdomfrontier -disable-output
+; RUN: opt < %s -postdomfrontier -disable-output
define void @args_out_of_range() {
entry:
diff --git a/libclamav/c++/llvm/test/Analysis/PostDominators/pr1098.ll b/libclamav/c++/llvm/test/Analysis/PostDominators/pr1098.ll
index b54a9fe..afb4776 100644
--- a/libclamav/c++/llvm/test/Analysis/PostDominators/pr1098.ll
+++ b/libclamav/c++/llvm/test/Analysis/PostDominators/pr1098.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -postdomtree -analyze | grep entry
+; RUN: opt < %s -postdomtree -analyze | grep entry
; PR932
define void @foo(i1 %x) {
diff --git a/libclamav/c++/llvm/test/Analysis/Profiling/edge-profiling.ll b/libclamav/c++/llvm/test/Analysis/Profiling/edge-profiling.ll
new file mode 100644
index 0000000..cbaf476
--- /dev/null
+++ b/libclamav/c++/llvm/test/Analysis/Profiling/edge-profiling.ll
@@ -0,0 +1,139 @@
+; Test the edge profiling instrumentation.
+; RUN: opt < %s -insert-edge-profiling -S | FileCheck %s
+
+; ModuleID = '<stdin>'
+
+ at .str = private constant [12 x i8] c"hello world\00", align 1 ; <[12 x i8]*> [#uses=1]
+ at .str1 = private constant [6 x i8] c"franz\00", align 1 ; <[6 x i8]*> [#uses=1]
+ at .str2 = private constant [9 x i8] c"argc > 2\00", align 1 ; <[9 x i8]*> [#uses=1]
+ at .str3 = private constant [9 x i8] c"argc = 1\00", align 1 ; <[9 x i8]*> [#uses=1]
+ at .str4 = private constant [6 x i8] c"fritz\00", align 1 ; <[6 x i8]*> [#uses=1]
+ at .str5 = private constant [10 x i8] c"argc <= 1\00", align 1 ; <[10 x i8]*> [#uses=1]
+; CHECK:@EdgeProfCounters
+; CHECK:[19 x i32]
+; CHECK:zeroinitializer
+
+define void @oneblock() nounwind {
+entry:
+; CHECK:entry:
+; CHECK:%OldFuncCounter
+; CHECK:load
+; CHECK:getelementptr
+; CHECK:@EdgeProfCounters
+; CHECK:i32 0
+; CHECK:i32 0
+; CHECK:%NewFuncCounter
+; CHECK:add
+; CHECK:%OldFuncCounter
+; CHECK:store
+; CHECK:%NewFuncCounter
+; CHECK:getelementptr
+; CHECK:@EdgeProfCounters
+ %0 = call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @.str, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @puts(i8*)
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+; CHECK:entry:
+ %argc_addr = alloca i32 ; <i32*> [#uses=4]
+ %argv_addr = alloca i8** ; <i8***> [#uses=1]
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %j = alloca i32 ; <i32*> [#uses=4]
+ %i = alloca i32 ; <i32*> [#uses=4]
+ %0 = alloca i32 ; <i32*> [#uses=2]
+; CHECK:call
+; CHECK:@llvm_start_edge_profiling
+; CHECK:@EdgeProfCounters
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %argc, i32* %argc_addr
+ store i8** %argv, i8*** %argv_addr
+ store i32 0, i32* %i, align 4
+ br label %bb10
+
+bb: ; preds = %bb10
+; CHECK:bb:
+ %1 = load i32* %argc_addr, align 4 ; <i32> [#uses=1]
+ %2 = icmp sgt i32 %1, 1 ; <i1> [#uses=1]
+ br i1 %2, label %bb1, label %bb8
+
+bb1: ; preds = %bb
+; CHECK:bb1:
+ store i32 0, i32* %j, align 4
+ br label %bb6
+
+bb2: ; preds = %bb6
+; CHECK:bb2:
+ %3 = call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+ %4 = load i32* %argc_addr, align 4 ; <i32> [#uses=1]
+ %5 = icmp sgt i32 %4, 2 ; <i1> [#uses=1]
+ br i1 %5, label %bb3, label %bb4
+
+bb3: ; preds = %bb2
+; CHECK:bb3:
+ %6 = call i32 @puts(i8* getelementptr inbounds ([9 x i8]* @.str2, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+ br label %bb5
+
+bb4: ; preds = %bb2
+; CHECK:bb4:
+ %7 = call i32 @puts(i8* getelementptr inbounds ([9 x i8]* @.str3, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+ br label %bb11
+
+bb5: ; preds = %bb3
+; CHECK:bb5:
+ %8 = call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str4, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+ %9 = load i32* %j, align 4 ; <i32> [#uses=1]
+ %10 = add nsw i32 %9, 1 ; <i32> [#uses=1]
+ store i32 %10, i32* %j, align 4
+ br label %bb6
+
+bb6: ; preds = %bb5, %bb1
+; CHECK:bb6:
+ %11 = load i32* %j, align 4 ; <i32> [#uses=1]
+ %12 = load i32* %argc_addr, align 4 ; <i32> [#uses=1]
+ %13 = icmp slt i32 %11, %12 ; <i1> [#uses=1]
+ br i1 %13, label %bb2, label %bb7
+
+bb7: ; preds = %bb6
+; CHECK:bb7:
+ br label %bb9
+
+bb8: ; preds = %bb
+; CHECK:bb8:
+ %14 = call i32 @puts(i8* getelementptr inbounds ([10 x i8]* @.str5, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+ br label %bb9
+
+bb9: ; preds = %bb8, %bb7
+; CHECK:bb9:
+ %15 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %16 = add nsw i32 %15, 1 ; <i32> [#uses=1]
+ store i32 %16, i32* %i, align 4
+ br label %bb10
+
+bb10: ; preds = %bb9, %entry
+; CHECK:bb10:
+ %17 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %18 = icmp ne i32 %17, 3 ; <i1> [#uses=1]
+ br i1 %18, label %bb, label %bb11
+; CHECK:br
+; CHECK:label %bb10.bb11_crit_edge
+
+; CHECK:bb10.bb11_crit_edge:
+; CHECK:br
+; CHECK:label %bb11
+
+bb11: ; preds = %bb10, %bb4
+; CHECK:bb11:
+ call void @oneblock() nounwind
+ store i32 0, i32* %0, align 4
+ %19 = load i32* %0, align 4 ; <i32> [#uses=1]
+ store i32 %19, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %bb11
+; CHECK:return:
+ %retval12 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval12
+}
diff --git a/libclamav/c++/llvm/test/Analysis/Profiling/profiling-tool-chain.ll b/libclamav/c++/llvm/test/Analysis/Profiling/profiling-tool-chain.ll
index 0ddc11d..5ac31b5 100644
--- a/libclamav/c++/llvm/test/Analysis/Profiling/profiling-tool-chain.ll
+++ b/libclamav/c++/llvm/test/Analysis/Profiling/profiling-tool-chain.ll
@@ -1,11 +1,23 @@
; RUN: llvm-as %s -o %t1
-; RUN: opt %t1 -insert-edge-profiling -o %t2
-; RUN: llvm-dis < %t2 | FileCheck --check-prefix=INST %s
-; RUN: rm -f llvmprof.out
-; RUN: lli -load %llvmlibsdir/profile_rt%shlibext %t2
-; RUN: lli -load %llvmlibsdir/profile_rt%shlibext %t2 1 2
-; RUN: llvm-prof -print-all-code %t1 | FileCheck --check-prefix=PROF %s
-; RUN: rm llvmprof.out
+
+; FIXME: The RUX parts of the test are disabled for now, they aren't working on
+; llvm-gcc-x86_64-darwin10-selfhost.
+
+; Test the edge optimal profiling instrumentation.
+; RUN: opt %t1 -insert-optimal-edge-profiling -o %t2
+; RUX: llvm-dis < %t2 | FileCheck --check-prefix=INST %s
+
+; Test the creation, reading and displaying of profile
+; RUX: rm -f llvmprof.out
+; RUX: lli -load %llvmlibsdir/profile_rt%shlibext %t2
+; RUX: lli -load %llvmlibsdir/profile_rt%shlibext %t2 1 2
+; RUX: llvm-prof -print-all-code %t1 | FileCheck --check-prefix=PROF %s
+
+; Test the loaded profile also with verifier.
+; RUX opt %t1 -profile-loader -profile-verifier -o %t3
+
+; Test profile estimator.
+; RUN: opt %t1 -profile-estimator -profile-verifier -o %t3
; PROF: 1. 2/4 oneblock
; PROF: 2. 2/4 main
@@ -25,8 +37,6 @@
; PROF: 14. 2.63158% 2/76 main() - return
; ModuleID = '<stdin>'
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
-target triple = "x86_64-unknown-linux-gnu"
@.str = private constant [12 x i8] c"hello world\00", align 1 ; <[12 x i8]*> [#uses=1]
@.str1 = private constant [6 x i8] c"franz\00", align 1 ; <[6 x i8]*> [#uses=1]
@@ -34,9 +44,29 @@ target triple = "x86_64-unknown-linux-gnu"
@.str3 = private constant [9 x i8] c"argc = 1\00", align 1 ; <[9 x i8]*> [#uses=1]
@.str4 = private constant [6 x i8] c"fritz\00", align 1 ; <[6 x i8]*> [#uses=1]
@.str5 = private constant [10 x i8] c"argc <= 1\00", align 1 ; <[10 x i8]*> [#uses=1]
-; INST:@EdgeProfCounters
-; INST:[19 x i32]
-; INST:zeroinitializer
+; INST:@OptEdgeProfCounters
+; INST:[21 x i32]
+; INST:[i32 0,
+; INST:i32 -1,
+; INST:i32 -1,
+; INST:i32 -1,
+; INST:i32 -1,
+; INST:i32 -1,
+; INST:i32 -1,
+; INST:i32 -1,
+; INST:i32 -1,
+; INST:i32 0,
+; INST:i32 0,
+; INST:i32 -1,
+; INST:i32 -1,
+; INST:i32 -1,
+; INST:i32 0,
+; INST:i32 0,
+; INST:i32 -1,
+; INST:i32 -1,
+; INST:i32 0,
+; INST:i32 -1,
+; INST:i32 -1]
; PROF:;;; %oneblock called 2 times.
; PROF:;;;
@@ -63,8 +93,8 @@ entry:
%i = alloca i32 ; <i32*> [#uses=4]
%0 = alloca i32 ; <i32*> [#uses=2]
; INST:call
-; INST:@llvm_start_edge_profiling
-; INST:@EdgeProfCounters
+; INST:@llvm_start_opt_edge_profiling
+; INST:@OptEdgeProfCounters
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
store i32 %argc, i32* %argc_addr
store i8** %argv, i8*** %argv_addr
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
index bf27e77..7f82ea4 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: -scalar-evolution-max-iterations=0 | grep {Loop bb: backedge-taken count is 100}
; PR1533
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-08-06-MisinterpretBranch.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-08-06-MisinterpretBranch.ll
index e3393d5..e67e4d0 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-08-06-MisinterpretBranch.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-08-06-MisinterpretBranch.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -indvars -adce -simplifycfg | llvm-dis | grep "icmp s"
+; RUN: opt < %s -indvars -adce -simplifycfg -S | grep "icmp s"
; PR1598
define i32 @f(i32 %a, i32 %b, i32 %x, i32 %y) {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-08-06-Unsigned.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-08-06-Unsigned.ll
index 95f932a..f623da1 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-08-06-Unsigned.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-08-06-Unsigned.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -scalar-evolution -analyze -disable-output | grep {Loop bb: backedge-taken count is (-1 + (-1 \\* %x) + %y)}
+; RUN: opt < %s -scalar-evolution -analyze -disable-output | grep {Loop bb: backedge-taken count is (-1 + (-1 \\* %x) + %y)}
; PR1597
define i32 @f(i32 %x, i32 %y) {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-09-27-LargeStepping.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-09-27-LargeStepping.ll
index e5e47d5..817090f 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-09-27-LargeStepping.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-09-27-LargeStepping.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: -scalar-evolution-max-iterations=0 | grep {backedge-taken count is 13}
; PR1706
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-11-14-SignedAddRec.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-11-14-SignedAddRec.ll
index 66ca755..514920f 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-11-14-SignedAddRec.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-11-14-SignedAddRec.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -indvars | llvm-dis | grep printd | grep 1206807378
+; RUN: opt < %s -indvars -S | grep printd | grep 1206807378
; PR1798
declare void @printd(i32)
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-11-18-OrInstruction.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-11-18-OrInstruction.ll
index 01f338a..2b3c982 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-11-18-OrInstruction.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2007-11-18-OrInstruction.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | grep -e {--> %b}
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | grep -e {--> %b}
; PR1810
define void @fun() {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-11-ReversedCondition.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-11-ReversedCondition.ll
index b9a53b3..c8e483e 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-11-ReversedCondition.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-11-ReversedCondition.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -scalar-evolution -analyze -disable-output | grep {Loop header: backedge-taken count is (0 smax %n)}
+; RUN: opt < %s -scalar-evolution -analyze -disable-output | grep {Loop header: backedge-taken count is (0 smax %n)}
define void @foo(i32 %n) {
entry:
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll
index b943bc7..cb9a182 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-12-SMAXTripCount.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -scalar-evolution -analyze -disable-output | grep {Loop loop: backedge-taken count is (100 + (-100 smax %n))}
+; RUN: opt < %s -scalar-evolution -analyze -disable-output | grep {Loop loop: backedge-taken count is (100 + (-100 smax %n))}
; PR2002
define void @foo(i8 %n) {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-15-UMax.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-15-UMax.ll
index 59b5109..bf9f4a9 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-15-UMax.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-02-15-UMax.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | grep umax
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | grep umax
; PR2003
define i32 @foo(i32 %n) {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-05-25-NegativeStepToZero.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-05-25-NegativeStepToZero.ll
index 5453ae3..8d15b77 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-05-25-NegativeStepToZero.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-05-25-NegativeStepToZero.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: -scalar-evolution-max-iterations=0 | grep {backedge-taken count is 61}
; PR2364
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-06-12-BinomialInt64.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-06-12-BinomialInt64.ll
index cbe5c97..d503329 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-06-12-BinomialInt64.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-06-12-BinomialInt64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution 2>/dev/null
+; RUN: opt < %s -analyze -scalar-evolution 2>/dev/null
; PR2433
define i32 @main1(i32 %argc, i8** %argv) nounwind {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect1.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect1.ll
index 6ba0f25..850b670 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect1.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output |& not grep smax
+; RUN: opt < %s -analyze -scalar-evolution -disable-output |& not grep smax
; PR2261
@lut = common global [256 x i8] zeroinitializer, align 32 ; <[256 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect2.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect2.ll
index 3c022e7..59e9fda 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect2.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-12-UnneededSelect2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output |& not grep smax
+; RUN: opt < %s -analyze -scalar-evolution -disable-output |& not grep smax
; PR2070
define i32 @a(i32 %x) nounwind {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-19-InfiniteLoop.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-19-InfiniteLoop.ll
index 5dcad53..989ac51 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-19-InfiniteLoop.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-19-InfiniteLoop.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: -scalar-evolution-max-iterations=0 | grep Unpredictable
; PR2088
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-19-WrappingIV.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-19-WrappingIV.ll
index 54c929d..803c7d1 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-19-WrappingIV.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-19-WrappingIV.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: -scalar-evolution-max-iterations=0 | grep {backedge-taken count is 113}
; PR2088
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-29-SGTTripCount.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-29-SGTTripCount.ll
index 527b8b0..97d0640 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-29-SGTTripCount.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-29-SGTTripCount.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: -scalar-evolution-max-iterations=0 | \
; RUN: grep -F "backedge-taken count is (-1 + (-1 * %j))"
; PR2607
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-29-SMinExpr.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-29-SMinExpr.ll
index 9051dc7..7f4de91 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-29-SMinExpr.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-07-29-SMinExpr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: -scalar-evolution-max-iterations=0 | \
; RUN: grep -F "backedge-taken count is (-2147483632 + ((-1 + (-1 * %x)) smax (-1 + (-1 * %y))))"
; PR2607
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-08-04-IVOverflow.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-08-04-IVOverflow.ll
index f8e1cfc..fa09895 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-08-04-IVOverflow.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-08-04-IVOverflow.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: -scalar-evolution-max-iterations=0 | grep -F "Exits: 20028"
; PR2621
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-08-04-LongAddRec.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-08-04-LongAddRec.ll
index fbd249f..5a28117 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-08-04-LongAddRec.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-08-04-LongAddRec.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: -scalar-evolution-max-iterations=0 | grep -F "Exits: -19168"
; PR2621
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-02-QuadraticCrash.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-02-QuadraticCrash.ll
index 1e9d0bf..9daff99 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-02-QuadraticCrash.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-02-QuadraticCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output
+; RUN: opt < %s -analyze -scalar-evolution -disable-output
; PR1827
declare void @use(i32)
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-15-CubicOOM.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-15-CubicOOM.ll
index c0b3a1f..5a2c366 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-15-CubicOOM.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-15-CubicOOM.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output
+; RUN: opt < %s -analyze -scalar-evolution -disable-output
; PR2602
define i32 @a() nounwind {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll
index 56d1fe7..daeb26a 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output |& \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output |& \
; RUN: grep {Loop bb: backedge-taken count is (7 + (-1 \\* %argc))}
; XFAIL: *
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride1.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride1.ll
index 8fb1604..9dda78b 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride1.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: | grep {Loop bb: Unpredictable backedge-taken count\\.}
; ScalarEvolution can't compute a trip count because it doesn't know if
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll
index d506f9c..bcbe92f 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output |& grep {/u 3}
+; RUN: opt < %s -analyze -scalar-evolution -disable-output |& grep {/u 3}
; XFAIL: *
define i32 @f(i32 %x) nounwind readnone {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll
index 643d2f8..2ee107a 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | grep {backedge-taken count is 255}
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | grep {backedge-taken count is 255}
; XFAIL: *
define i32 @foo(i32 %x, i32 %y, i32* %lam, i32* %alp) nounwind {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll
index 995a1d9..0cfd84c 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | grep {0 smax}
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | grep {0 smax}
; XFAIL: *
define i32 @f(i32 %c.idx.val) {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-14-StrideAndSigned.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-14-StrideAndSigned.ll
index 8e064c7..4ec358c 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-14-StrideAndSigned.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-14-StrideAndSigned.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output |& \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output |& \
; RUN: grep {(((-1 \\* %i0) + (100005 smax %i0)) /u 5)}
; XFAIL: *
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-15-DontUseSDiv.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-15-DontUseSDiv.ll
index 950c1d2..1fe1068 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-15-DontUseSDiv.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2008-12-15-DontUseSDiv.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output |& grep {/u 5}
+; RUN: opt < %s -analyze -scalar-evolution -disable-output |& grep {/u 5}
; XFAIL: *
define i8 @foo0(i8 %i0) nounwind {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-01-02-SignedNegativeStride.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-01-02-SignedNegativeStride.ll
index 65c4cdb..9d13695 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-01-02-SignedNegativeStride.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-01-02-SignedNegativeStride.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | not grep {/u -1}
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | not grep {/u -1}
; PR3275
@g_16 = external global i16 ; <i16*> [#uses=3]
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-04-22-TruncCast.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-04-22-TruncCast.ll
index 6aced23..78a7fd0 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-04-22-TruncCast.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-04-22-TruncCast.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | grep {(trunc i} | not grep ext
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | grep {(trunc i} | not grep ext
define i16 @test1(i8 %x) {
%A = sext i8 %x to i32
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-05-09-PointerEdgeCount.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-05-09-PointerEdgeCount.ll
index 5e5128b..6ed2614 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-05-09-PointerEdgeCount.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-05-09-PointerEdgeCount.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | grep {count is 2}
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | grep {count is 2}
; PR3171
%struct.Foo = type { i32 }
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-07-04-GroupConstantsWidthMismatch.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-07-04-GroupConstantsWidthMismatch.ll
index b5d588e..a4358aa 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-07-04-GroupConstantsWidthMismatch.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/2009-07-04-GroupConstantsWidthMismatch.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution
+; RUN: opt < %s -analyze -scalar-evolution
; PR4501
define void @test() {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
index 27a546f..fcc6fc3 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: -scalar-evolution-max-iterations=0 | grep {backedge-taken count is 100}
; PR1101
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/and-xor.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/and-xor.ll
index 94cca83..90d947f 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/and-xor.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/and-xor.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -scalar-evolution -analyze -disable-output \
+; RUN: opt < %s -scalar-evolution -analyze -disable-output \
; RUN: | grep {\\--> (zext} | count 2
define i32 @foo(i32 %x) {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll
index 3fe0336..f638eb3 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output
+; RUN: opt < %s -analyze -scalar-evolution -disable-output
; PR4537
; ModuleID = 'b.bc'
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-1.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-1.ll
index 121e0ac..31b95e1 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-1.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -iv-users
+; RUN: opt < %s -iv-users
; PR4538
; ModuleID = 'bugpoint-reduced-simplified.bc'
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-smax-0.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-smax-0.ll
index ce7ee77..b733d6a 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-smax-0.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-smax-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -scalar-evolution -analyze -disable-output | grep {Loop bb3: backedge-taken count is (-1 + %n)}
+; RUN: opt < %s -scalar-evolution -analyze -disable-output | grep {Loop bb3: backedge-taken count is (-1 + %n)}
; We don't want to use a max in the trip count expression in
; this testcase.
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-smax-1.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-smax-1.ll
index 74117cf..0bc9ce8 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-smax-1.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/avoid-smax-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -indvars | llvm-dis > %t
+; RUN: opt < %s -indvars -S > %t
; RUN: grep select %t | count 2
; RUN: grep {icmp ne i32.\* %w } %t
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/div-overflow.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/div-overflow.ll
index cb64b85..0c01044 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/div-overflow.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/div-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -scalar-evolution -analyze -disable-output \
+; RUN: opt < %s -scalar-evolution -analyze -disable-output \
; RUN: | grep {\\--> ((-128 \\* %a) /u -128)}
; Don't let ScalarEvolution fold this div away.
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/do-loop.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/do-loop.ll
index 85c38e4..f8d7da7 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/do-loop.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/do-loop.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | grep smax
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | grep smax
; PR1614
define i32 @f(i32 %x, i32 %y) {
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/max-trip-count.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/max-trip-count.ll
index 8791bb5..506401d 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/max-trip-count.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/max-trip-count.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: | grep {\{%d,+,\[^\{\}\]\*\}<bb>}
; ScalarEvolution should be able to understand the loop and eliminate the casts.
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/nsw-offset.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/nsw-offset.ll
new file mode 100644
index 0000000..1e165bf
--- /dev/null
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/nsw-offset.ll
@@ -0,0 +1,76 @@
+; RUN: opt < %s -S -analyze -scalar-evolution -disable-output | FileCheck %s
+
+; ScalarEvolution should be able to fold away the sign-extensions
+; on this loop with a primary induction variable incremented with
+; a nsw add of 2.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+
+define void @foo(i32 %n, double* nocapture %d, double* nocapture %q) nounwind {
+entry:
+ %0 = icmp sgt i32 %n, 0 ; <i1> [#uses=1]
+ br i1 %0, label %bb.nph, label %return
+
+bb.nph: ; preds = %entry
+ br label %bb
+
+bb: ; preds = %bb.nph, %bb1
+ %i.01 = phi i32 [ %16, %bb1 ], [ 0, %bb.nph ] ; <i32> [#uses=5]
+
+; CHECK: %1 = sext i32 %i.01 to i64
+; CHECK: --> {0,+,2}<bb>
+ %1 = sext i32 %i.01 to i64 ; <i64> [#uses=1]
+
+; CHECK: %2 = getelementptr inbounds double* %d, i64 %1
+; CHECK: --> {%d,+,16}<bb>
+ %2 = getelementptr inbounds double* %d, i64 %1 ; <double*> [#uses=1]
+
+ %3 = load double* %2, align 8 ; <double> [#uses=1]
+ %4 = sext i32 %i.01 to i64 ; <i64> [#uses=1]
+ %5 = getelementptr inbounds double* %q, i64 %4 ; <double*> [#uses=1]
+ %6 = load double* %5, align 8 ; <double> [#uses=1]
+ %7 = or i32 %i.01, 1 ; <i32> [#uses=1]
+
+; CHECK: %8 = sext i32 %7 to i64
+; CHECK: --> {1,+,2}<bb>
+ %8 = sext i32 %7 to i64 ; <i64> [#uses=1]
+
+; CHECK: %9 = getelementptr inbounds double* %q, i64 %8
+; CHECK: {(8 + %q),+,16}<bb>
+ %9 = getelementptr inbounds double* %q, i64 %8 ; <double*> [#uses=1]
+
+; Artificially repeat the above three instructions, this time using
+; add nsw instead of or.
+ %t7 = add nsw i32 %i.01, 1 ; <i32> [#uses=1]
+
+; CHECK: %t8 = sext i32 %t7 to i64
+; CHECK: --> {1,+,2}<bb>
+ %t8 = sext i32 %t7 to i64 ; <i64> [#uses=1]
+
+; CHECK: %t9 = getelementptr inbounds double* %q, i64 %t8
+; CHECK: {(8 + %q),+,16}<bb>
+ %t9 = getelementptr inbounds double* %q, i64 %t8 ; <double*> [#uses=1]
+
+ %10 = load double* %9, align 8 ; <double> [#uses=1]
+ %11 = fadd double %6, %10 ; <double> [#uses=1]
+ %12 = fadd double %11, 3.200000e+00 ; <double> [#uses=1]
+ %13 = fmul double %3, %12 ; <double> [#uses=1]
+ %14 = sext i32 %i.01 to i64 ; <i64> [#uses=1]
+ %15 = getelementptr inbounds double* %d, i64 %14 ; <double*> [#uses=1]
+ store double %13, double* %15, align 8
+ %16 = add nsw i32 %i.01, 2 ; <i32> [#uses=2]
+ br label %bb1
+
+bb1: ; preds = %bb
+ %17 = icmp slt i32 %16, %n ; <i1> [#uses=1]
+ br i1 %17, label %bb, label %bb1.return_crit_edge
+
+bb1.return_crit_edge: ; preds = %bb1
+ br label %return
+
+return: ; preds = %bb1.return_crit_edge, %entry
+ ret void
+}
+
+; CHECK: Loop bb: backedge-taken count is ((-1 + %n) /u 2)
+; CHECK: Loop bb: max backedge-taken count is 1073741823
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/nsw.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/nsw.ll
index 26528c9..c31edab 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/nsw.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/nsw.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | grep { --> {.*,+,.*}<bb>} | count 8
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | grep { --> {.*,+,.*}<bb>} | count 8
; The addrecs in this loop are analyzable only by using nsw information.
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/pointer-sign-bits.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/pointer-sign-bits.ll
index 05cb81b..4de006c 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/pointer-sign-bits.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/pointer-sign-bits.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output
+; RUN: opt < %s -analyze -scalar-evolution -disable-output
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
%JavaObject = type { [0 x i32 (...)*]*, i8* }
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/pr3909.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/pr3909.ll
index 80720c7..10e328d 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/pr3909.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/pr3909.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -indvars -disable-output
+; RUN: opt < %s -indvars -disable-output
; PR 3909
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/scev-aa.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/scev-aa.ll
index 2208b3d..0dcf529 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/scev-aa.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/scev-aa.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -scev-aa -aa-eval -print-all-alias-modref-info \
+; RUN: opt < %s -scev-aa -aa-eval -print-all-alias-modref-info \
; RUN: |& FileCheck %s
; At the time of this writing, all of these CHECK lines are cases that
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-inreg.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-inreg.ll
index 8a88f0f..1612835 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-inreg.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-inreg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output > %t
+; RUN: opt < %s -analyze -scalar-evolution -disable-output > %t
; RUN: grep {sext i57 \{0,+,199\}<bb> to i64} %t | count 1
; RUN: grep {sext i59 \{0,+,199\}<bb> to i64} %t | count 1
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-0.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-0.ll
index 17f2dff..8f887c4 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-0.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -disable-output -scalar-evolution -analyze \
+; RUN: opt < %s -disable-output -scalar-evolution -analyze \
; RUN: | grep { --> \{-128,+,1\}<bb1> Exits: 127} | count 5
; Convert (sext {-128,+,1}) to {sext(-128),+,sext(1)}, since the
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-1.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-1.ll
index ca6ad0a..02c3206 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-1.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -disable-output -scalar-evolution -analyze \
+; RUN: opt < %s -disable-output -scalar-evolution -analyze \
; RUN: | grep { --> (sext i. \{.\*,+,.\*\}<bb1> to i64)} | count 5
; Don't convert (sext {...,+,...}) to {sext(...),+,sext(...)} in cases
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-2.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-2.ll
index 10bcc47..b25c237 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-2.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/sext-iv-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | FileCheck %s
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | FileCheck %s
; CHECK: %tmp3 = sext i8 %tmp2 to i32
; CHECK: --> (sext i8 {0,+,1}<bb1> to i32) Exits: -1
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/smax.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/smax.ll
index 366dfde..39de8d6 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/smax.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/smax.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | grep smax | count 2
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | grep \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | grep smax | count 2
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | grep \
; RUN: {%. smax %. smax %.}
; PR1614
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count.ll
index c5be858..66cc304 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: -scalar-evolution-max-iterations=0 | grep {backedge-taken count is 10000}
; PR1101
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count2.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count2.ll
index 374a562..bbe6435 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count2.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output | \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output | \
; RUN: grep {backedge-taken count is 4}
; PR1101
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count3.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count3.ll
index 35c8683..2409831 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count3.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -scalar-evolution -analyze -disable-output \
+; RUN: opt < %s -scalar-evolution -analyze -disable-output \
; RUN: | grep {Loop bb3\\.i: Unpredictable backedge-taken count\\.}
; ScalarEvolution can't compute a trip count because it doesn't know if
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count4.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count4.ll
index 49c4e13..e8d59cf 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count4.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: | grep {sext.*trunc.*Exits: 11}
; ScalarEvolution should be able to compute a loop exit value for %indvar.i8.
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count5.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count5.ll
index 822dc26..2512a96 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count5.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output > %t
+; RUN: opt < %s -analyze -scalar-evolution -disable-output > %t
; RUN: grep sext %t | count 2
; RUN: not grep {(sext} %t
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count6.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count6.ll
index a667409..5833286 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count6.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -disable-output -scalar-evolution \
+; RUN: opt < %s -analyze -disable-output -scalar-evolution \
; RUN: | grep {max backedge-taken count is 1\$}
@mode_table = global [4 x i32] zeroinitializer ; <[4 x i32]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count7.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count7.ll
index cea826e..0cd8d7c 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count7.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count7.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: | grep {Loop bb7.i: Unpredictable backedge-taken count\\.}
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count8.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count8.ll
index 21ccc47..c49f5ce 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count8.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/trip-count8.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: | grep {Loop for\\.body: backedge-taken count is (-1 + \[%\]ecx)}
; PR4599
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/xor-and.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/xor-and.ll
index 8430524..c8339d7 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/xor-and.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/xor-and.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -scalar-evolution -disable-output -analyze \
+; RUN: opt < %s -scalar-evolution -disable-output -analyze \
; RUN: | grep {\\--> (zext i4 (-8 + (trunc i64 (8 \\* %x) to i4)) to i64)}
; ScalarEvolution shouldn't try to analyze %z into something like
diff --git a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/zext-wrap.ll b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/zext-wrap.ll
index 052d036..9ff99be 100644
--- a/libclamav/c++/llvm/test/Analysis/ScalarEvolution/zext-wrap.ll
+++ b/libclamav/c++/llvm/test/Analysis/ScalarEvolution/zext-wrap.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -analyze -scalar-evolution -disable-output \
+; RUN: opt < %s -analyze -scalar-evolution -disable-output \
; RUN: | FileCheck %s
; PR4569
diff --git a/libclamav/c++/llvm/test/Assembler/2002-04-07-HexFloatConstants.ll b/libclamav/c++/llvm/test/Assembler/2002-04-07-HexFloatConstants.ll
index 5c54b39..b0d7cc0 100644
--- a/libclamav/c++/llvm/test/Assembler/2002-04-07-HexFloatConstants.ll
+++ b/libclamav/c++/llvm/test/Assembler/2002-04-07-HexFloatConstants.ll
@@ -5,7 +5,7 @@
; of the bug that was causing the Olden Health benchmark to output incorrect
; results!
;
-; RUN: llvm-as < %s | opt -constprop | llvm-dis > %t.1
+; RUN: opt -constprop -S > %t.1 < %s
; RUN: llvm-as < %s | llvm-dis | llvm-as | opt -constprop | \
; RUN: llvm-dis > %t.2
; RUN: diff %t.1 %t.2
diff --git a/libclamav/c++/llvm/test/Assembler/2002-04-29-NameBinding.ll b/libclamav/c++/llvm/test/Assembler/2002-04-29-NameBinding.ll
index 9665aef..7960c20 100644
--- a/libclamav/c++/llvm/test/Assembler/2002-04-29-NameBinding.ll
+++ b/libclamav/c++/llvm/test/Assembler/2002-04-29-NameBinding.ll
@@ -4,7 +4,7 @@
; Check by running globaldce, which will remove the constant if there are
; no references to it!
;
-; RUN: llvm-as < %s | opt -globaldce | llvm-dis | \
+; RUN: opt < %s -globaldce -S | \
; RUN: not grep constant
;
diff --git a/libclamav/c++/llvm/test/Assembler/2002-08-19-BytecodeReader.ll b/libclamav/c++/llvm/test/Assembler/2002-08-19-BytecodeReader.ll
index e42cda0..e211014 100644
--- a/libclamav/c++/llvm/test/Assembler/2002-08-19-BytecodeReader.ll
+++ b/libclamav/c++/llvm/test/Assembler/2002-08-19-BytecodeReader.ll
@@ -1,7 +1,7 @@
; Testcase that seems to break the bytecode reader. This comes from the
; "crafty" spec benchmark.
;
-; RUN: llvm-as < %s | opt -instcombine | llvm-dis | llvm-as
+; RUN: opt < %s -instcombine | llvm-dis
%CHESS_POSITION = type { i32, i32 }
@pawn_probes = external global i32 ; <i32*> [#uses=0]
diff --git a/libclamav/c++/llvm/test/Assembler/2003-08-20-ConstantExprGEP-Fold.ll b/libclamav/c++/llvm/test/Assembler/2003-08-20-ConstantExprGEP-Fold.ll
index 6f31f16..50cdeed 100644
--- a/libclamav/c++/llvm/test/Assembler/2003-08-20-ConstantExprGEP-Fold.ll
+++ b/libclamav/c++/llvm/test/Assembler/2003-08-20-ConstantExprGEP-Fold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -instcombine -simplifycfg | llvm-dis | not grep br
+; RUN: opt < %s -instcombine -simplifycfg -S | not grep br
@.str_1 = internal constant [6 x i8] c"_Bool\00" ; <[6 x i8]*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/Assembler/2008-02-20-MultipleReturnValue.ll b/libclamav/c++/llvm/test/Assembler/2008-02-20-MultipleReturnValue.ll
index 5b2ed7e..32c893a 100644
--- a/libclamav/c++/llvm/test/Assembler/2008-02-20-MultipleReturnValue.ll
+++ b/libclamav/c++/llvm/test/Assembler/2008-02-20-MultipleReturnValue.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -verify | llvm-dis | llvm-as -disable-output
+; RUN: opt < %s -verify -S | llvm-as -disable-output
define {i32, i8} @foo(i32 %p) {
ret i32 1, i8 2
diff --git a/libclamav/c++/llvm/test/Assembler/2009-02-28-StripOpaqueName.ll b/libclamav/c++/llvm/test/Assembler/2009-02-28-StripOpaqueName.ll
index eef5d36..f61a44c 100644
--- a/libclamav/c++/llvm/test/Assembler/2009-02-28-StripOpaqueName.ll
+++ b/libclamav/c++/llvm/test/Assembler/2009-02-28-StripOpaqueName.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -strip | llvm-dis | llvm-as | llvm-dis
+; RUN: opt < %s -strip -S | llvm-as | llvm-dis
; Stripping the name from A should not break references to it.
%A = type opaque
diff --git a/libclamav/c++/llvm/test/Assembler/ConstantExprFold.ll b/libclamav/c++/llvm/test/Assembler/ConstantExprFold.ll
index 89edc24..d3d374a 100644
--- a/libclamav/c++/llvm/test/Assembler/ConstantExprFold.ll
+++ b/libclamav/c++/llvm/test/Assembler/ConstantExprFold.ll
@@ -19,6 +19,7 @@ global i64* inttoptr (i64 xor (i64 ptrtoint (i64* @A to i64), i64 0) to i64*) ;
@B = external global %Ty
global i1 icmp slt (i64* @A, i64* getelementptr (i64* @A, i64 1)) ; true
+global i1 icmp ult (i64* @A, i64* getelementptr (i64* @A, i64 1)) ; true
global i1 icmp slt (i64* @A, i64* getelementptr (i64* @A, i64 0)) ; false
global i1 icmp slt (i32* getelementptr (%Ty* @B, i64 0, i32 0),
i32* getelementptr (%Ty* @B, i64 0, i32 1)) ; true
diff --git a/libclamav/c++/llvm/test/Assembler/anon-functions.ll b/libclamav/c++/llvm/test/Assembler/anon-functions.ll
index e08063e..ac06e8c 100644
--- a/libclamav/c++/llvm/test/Assembler/anon-functions.ll
+++ b/libclamav/c++/llvm/test/Assembler/anon-functions.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s |llvm-dis | llvm-as | llvm-dis
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis
; PR3611
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/Assembler/flags-plain.ll b/libclamav/c++/llvm/test/Assembler/flags-plain.ll
deleted file mode 100644
index bf3d5d8..0000000
--- a/libclamav/c++/llvm/test/Assembler/flags-plain.ll
+++ /dev/null
@@ -1,28 +0,0 @@
-; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-
- at addr = external global i64
-
-define i64 @add_plain_ce() {
-; CHECK: ret i64 add (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 add (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
-
-define i64 @sub_plain_ce() {
-; CHECK: ret i64 sub (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 sub (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
-
-define i64 @mul_plain_ce() {
-; CHECK: ret i64 mul (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 mul (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
-
-define i64 @sdiv_plain_ce() {
-; CHECK: ret i64 sdiv (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 sdiv (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
-
-define i64* @gep_plain_ce() {
-; CHECK: ret i64* getelementptr (i64* @addr, i64 171)
- ret i64* getelementptr (i64* @addr, i64 171)
-}
diff --git a/libclamav/c++/llvm/test/Assembler/flags-reversed.ll b/libclamav/c++/llvm/test/Assembler/flags-reversed.ll
deleted file mode 100644
index 25fa6a0..0000000
--- a/libclamav/c++/llvm/test/Assembler/flags-reversed.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-
- at addr = external global i64
-
-define i64 @add_both_reversed_ce() {
-; CHECK: ret i64 add nuw nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 add nsw nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
-
-define i64 @sub_both_reversed_ce() {
-; CHECK: ret i64 sub nuw nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 sub nsw nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
-
-define i64 @mul_both_reversed_ce() {
-; CHECK: ret i64 mul nuw nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 mul nsw nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
diff --git a/libclamav/c++/llvm/test/Assembler/flags-signed.ll b/libclamav/c++/llvm/test/Assembler/flags-signed.ll
deleted file mode 100644
index 9c40813..0000000
--- a/libclamav/c++/llvm/test/Assembler/flags-signed.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-
- at addr = external global i64
-
-define i64 @add_signed_ce() {
-; CHECK: ret i64 add nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 add nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
-
-define i64 @sub_signed_ce() {
-; CHECK: ret i64 sub nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 sub nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
-
-define i64 @mul_signed_ce() {
-; CHECK: ret i64 mul nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 mul nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
diff --git a/libclamav/c++/llvm/test/Assembler/flags-unsigned.ll b/libclamav/c++/llvm/test/Assembler/flags-unsigned.ll
deleted file mode 100644
index 1ddffca..0000000
--- a/libclamav/c++/llvm/test/Assembler/flags-unsigned.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-
- at addr = external global i64
-
-define i64 @add_unsigned_ce() {
-; CHECK: ret i64 add nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 add nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
-
-define i64 @sub_unsigned_ce() {
-; CHECK: ret i64 sub nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 sub nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
-
-define i64 @mul_unsigned_ce() {
-; CHECK: ret i64 mul nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
- ret i64 mul nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
-}
diff --git a/libclamav/c++/llvm/test/Assembler/flags.ll b/libclamav/c++/llvm/test/Assembler/flags.ll
index 981a4e5..3241909 100644
--- a/libclamav/c++/llvm/test/Assembler/flags.ll
+++ b/libclamav/c++/llvm/test/Assembler/flags.ll
@@ -141,4 +141,72 @@ define i64* @gep_nw_ce() {
ret i64* getelementptr inbounds (i64* @addr, i64 171)
}
+define i64 @add_plain_ce() {
+; CHECK: ret i64 add (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 add (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+
+define i64 @sub_plain_ce() {
+; CHECK: ret i64 sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+
+define i64 @mul_plain_ce() {
+; CHECK: ret i64 mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+
+define i64 @sdiv_plain_ce() {
+; CHECK: ret i64 sdiv (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 sdiv (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+
+define i64* @gep_plain_ce() {
+; CHECK: ret i64* getelementptr (i64* @addr, i64 171)
+ ret i64* getelementptr (i64* @addr, i64 171)
+}
+
+define i64 @add_both_reversed_ce() {
+; CHECK: ret i64 add nuw nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 add nsw nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+define i64 @sub_both_reversed_ce() {
+; CHECK: ret i64 sub nuw nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 sub nsw nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+
+define i64 @mul_both_reversed_ce() {
+; CHECK: ret i64 mul nuw nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 mul nsw nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+
+define i64 @add_signed_ce() {
+; CHECK: ret i64 add nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 add nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+
+define i64 @sub_signed_ce() {
+; CHECK: ret i64 sub nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 sub nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+
+define i64 @mul_signed_ce() {
+; CHECK: ret i64 mul nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 mul nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+
+define i64 @add_unsigned_ce() {
+; CHECK: ret i64 add nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 add nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+
+define i64 @sub_unsigned_ce() {
+; CHECK: ret i64 sub nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 sub nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
+
+define i64 @mul_unsigned_ce() {
+; CHECK: ret i64 mul nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
+ ret i64 mul nuw (i64 ptrtoint (i64* @addr to i64), i64 91)
+}
diff --git a/libclamav/c++/llvm/test/Assembler/getelementptr.ll b/libclamav/c++/llvm/test/Assembler/getelementptr.ll
index 10e5011..803d6d3 100644
--- a/libclamav/c++/llvm/test/Assembler/getelementptr.ll
+++ b/libclamav/c++/llvm/test/Assembler/getelementptr.ll
@@ -1,11 +1,21 @@
-; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis
+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+
+; Verify that over-indexed getelementptrs are folded.
+ at A = external global [2 x [3 x [5 x [7 x i32]]]]
+ at B = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 0, i64 0, i64 2, i64 1, i64 7523)
+; CHECK: @B = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 36, i64 0, i64 1, i64 0, i64 5) ; <i32**> [#uses=0]
+ at C = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 3, i64 2, i64 0, i64 0, i64 7523)
+; CHECK: @C = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 39, i64 1, i64 1, i64 4, i64 5) ; <i32**> [#uses=0]
;; Verify that i16 indices work.
@x = external global {i32, i32}
@y = global i32* getelementptr ({i32, i32}* @x, i16 42, i32 0)
+; CHECK: @y = global i32* getelementptr (%0* @x, i16 42, i32 0)
; see if i92 indices work too.
define i32 *@test({i32, i32}* %t, i92 %n) {
+; CHECK: @test
+; CHECK: %B = getelementptr %0* %t, i92 %n, i32 0
%B = getelementptr {i32, i32}* %t, i92 %n, i32 0
ret i32* %B
}
diff --git a/libclamav/c++/llvm/test/Assembler/insertextractvalue.ll b/libclamav/c++/llvm/test/Assembler/insertextractvalue.ll
index 3581238..2f5521f 100644
--- a/libclamav/c++/llvm/test/Assembler/insertextractvalue.ll
+++ b/libclamav/c++/llvm/test/Assembler/insertextractvalue.ll
@@ -21,3 +21,9 @@ define float @dar({{i32},{float, double}}* %p) nounwind {
store {{i32},{float, double}} insertvalue ({{i32},{float, double}} zeroinitializer, double 20.0, 1, 1), {{i32},{float, double}}* %p
ret float extractvalue ({{i32},{float, double}} zeroinitializer, 1, 0)
}
+
+
+; PR4963
+define <{ i32, i32 }> @test57() {
+ ret <{ i32, i32 }> insertvalue (<{ i32, i32 }> zeroinitializer, i32 4, 1)
+}
diff --git a/libclamav/c++/llvm/test/CMakeLists.txt b/libclamav/c++/llvm/test/CMakeLists.txt
new file mode 100644
index 0000000..627b57d
--- /dev/null
+++ b/libclamav/c++/llvm/test/CMakeLists.txt
@@ -0,0 +1,31 @@
+include(GetTargetTriple)
+get_target_triple(target)
+
+foreach(c ${LLVM_TARGETS_TO_BUILD})
+ set(TARGETS_BUILT "${TARGETS_BUILT} ${c}")
+endforeach(c)
+set(TARGETS_TO_BUILD ${TARGETS_BUILT})
+
+include(FindPythonInterp)
+if(PYTHONINTERP_FOUND)
+ get_target_property(LLVM_TOOLS_PATH llvm-config RUNTIME_OUTPUT_DIRECTORY)
+
+ configure_file(
+ ${CMAKE_CURRENT_SOURCE_DIR}/site.exp.in
+ ${CMAKE_CURRENT_BINARY_DIR}/site.exp)
+
+ add_custom_target(llvm-test
+ COMMAND sed -e "s#\@LLVM_SOURCE_DIR\@#${LLVM_MAIN_SRC_DIR}#"
+ -e "s#\@LLVM_BINARY_DIR\@#${LLVM_BINARY_DIR}#"
+ -e "s#\@LLVM_TOOLS_DIR\@#${LLVM_TOOLS_PATH}/${CMAKE_CFG_INTDIR}#"
+ -e "s#\@LLVMGCC_DIR\@##"
+ ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in >
+ ${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg
+ COMMAND ${PYTHON_EXECUTABLE}
+ ${LLVM_SOURCE_DIR}/utils/lit/lit.py
+ -sv
+ ${CMAKE_CURRENT_BINARY_DIR}
+ DEPENDS
+ COMMENT "Running LLVM regression tests")
+
+endif()
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
index caa9a98..a0235f7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6
+; RUN: llc < %s -march=arm -mattr=+v6
%struct.layer_data = type { i32, [2048 x i8], i8*, [16 x i8], i32, i8*, i32, i32, [64 x i32], [64 x i32], [64 x i32], [64 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [12 x [64 x i16]] }
@ld = external global %struct.layer_data* ; <%struct.layer_data**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
index 6e11b16..81483cb 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2
@quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
@dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
index 7317e62..83b26d3 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
define fastcc i8* @read_sleb128(i8* %p, i32* %val) {
br label %bb
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll
index 07390ad..33f935e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -relocation-model=pic \
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \
; RUN: -mattr=+v6 | grep r9
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -relocation-model=pic \
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \
; RUN: -mattr=+v6 -arm-reserve-r9 -ifcvt-limit=0 -stats |& grep asm-printer
; | grep 35
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
index 32daf83..b0953dc 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
; PR1257
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll
index 6d3f640..d741112 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
; PR1266
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
index f927ef4..e4635f5 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi
; PR1279
%struct.rtx_def = type { i16, i8, i8, %struct.u }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll
index 55d2993..ea27676 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi
; PR1279
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
index ef5a1ae..f24def3 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-apple-darwin
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin
%struct.H_TBL = type { [17 x i8], [256 x i8], i32 }
%struct.Q_TBL = type { [64 x i16], i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll
index e412127..b543c57 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-03-PEIBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | not grep {add.*#0}
+; RUN: llc < %s -march=arm | not grep {add.*#0}
define i32 @foo() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
index 42f5034..e001cde 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -relocation-model=pic | \
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | \
; RUN: not grep LPC9
%struct.B = type { i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
index ec70a59..a89e937 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "arm-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
index f3f82bc..c73b679 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-apple-darwin
%struct.Connection = type { i32, [10 x i8], i32 }
%struct.IntChunk = type { %struct.cppobjtype, i32, i32*, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-07-jumptoentry.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-07-jumptoentry.ll
index 11431be..26864f1 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-07-jumptoentry.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-07-jumptoentry.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | not grep 1_0
+; RUN: llc < %s | not grep 1_0
; This used to create an extra branch to 'entry', LBB1_0.
; ModuleID = 'bug.bc'
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
index c3596e7..f2a8ee1 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge | grep bl.*baz | count 1
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge | grep bl.*quux | count 1
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge -enable-eh | grep bl.*baz | count 1
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge -enable-eh | grep bl.*quux | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*quux | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*quux | count 1
; Check that calls to baz and quux are tail-merged.
; PR1628
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
index 41ab1e5..2758505 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge | grep bl.*baz | count 1
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge | grep bl.*quux | count 1
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge -enable-eh | grep bl.*baz | count 1
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge -enable-eh | grep bl.*quux | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*quux | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*quux | count 1
; Check that calls to baz and quux are tail-merged.
; PR1628
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll
index 58c5f89..b3b0769 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6
+; RUN: llc < %s -march=arm -mattr=+v6
define i32 @test3() {
tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll
index 430b368..7b15ded 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi
; PR1406
%struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
index 4c4a933..061bf5e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
@@ -1,11 +1,11 @@
-; RUN: llvm-as < %s | llc -march=arm | grep bl.*baz | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep bl.*quux | count 1
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge=0 | grep bl.*baz | count 2
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge=0 | grep bl.*quux | count 2
-; RUN: llvm-as < %s | llc -march=arm -enable-eh | grep bl.*baz | count 1
-; RUN: llvm-as < %s | llc -march=arm -enable-eh | grep bl.*quux | count 1
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge=0 -enable-eh | grep bl.*baz | count 2
-; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge=0 -enable-eh | grep bl.*quux | count 2
+; RUN: llc < %s -march=arm | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm | grep bl.*quux | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge=0 | grep bl.*baz | count 2
+; RUN: llc < %s -march=arm -enable-tail-merge=0 | grep bl.*quux | count 2
+; RUN: llc < %s -march=arm -enable-eh | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm -enable-eh | grep bl.*quux | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge=0 -enable-eh | grep bl.*baz | count 2
+; RUN: llc < %s -march=arm -enable-tail-merge=0 -enable-eh | grep bl.*quux | count 2
; Check that tail merging is the default on ARM, and that -enable-tail-merge=0 works.
; PR1628
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
index de32a26..d2eb85d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | not grep {str.*\\!}
+; RUN: llc < %s -march=arm | not grep {str.*\\!}
%struct.shape_edge_t = type { %struct.shape_edge_t*, %struct.shape_edge_t*, i32, i32, i32, i32 }
%struct.shape_path_t = type { %struct.shape_edge_t*, %struct.shape_edge_t*, i32, i32, i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll
index d21a8f2..030486a 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1424
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
index 3cfcdef..30b72e0 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6
; PR1609
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
index ec170f8..ff01506 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi -regalloc=local
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=local
; PR1925
%struct.encode_aux_nearestmatch = type { i32*, i32*, i32*, i32*, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
index b81d575..06bc987 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -regalloc=local
+; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=local
; PR1925
%"struct.kc::impl_Ccode_option" = type { %"struct.kc::impl_abstract_phylum" }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
index ca34275..a604c5c 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | not grep 255
+; RUN: llc < %s -march=arm -mattr=+v6 | not grep 255
define i32 @main(i32 %argc, i8** %argv) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
index 70f1774..78c6222 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
@accum = external global { double, double } ; <{ double, double }*> [#uses=1]
@.str = external constant [4 x i8] ; <[4 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
index 610f5ea..234c7b6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-apple-darwin
@numBinsY = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
index 80ccddf..77418be 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-apple-darwin
%struct.CONTENTBOX = type { i32, i32, i32, i32, i32 }
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll
index 3cd757f..33bd4de 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-apple-darwin
declare void @foo(i8*, i8*, i32, i32, i32, i32, i32, i32, i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
index 035af08..71aa603 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-apple-darwin
%struct.BiContextType = type { i16, i8, i32 }
%struct.Bitstream = type { i32, i32, i8, i32, i32, i8, i8, i32, i32, i8*, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
index e98126b..aa61d86 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-apple-darwin
%struct.Decoders = type { i32**, i16***, i16****, i16***, i16**, i8**, i8** }
@decoders = external global %struct.Decoders ; <%struct.Decoders*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-07-17-Fdiv.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-07-17-Fdiv.ll
index aa75970..4cb768e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-07-17-Fdiv.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-07-17-Fdiv.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define float @f(float %a, float %b) nounwind {
%tmp = fdiv float %a, %b
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
index 6ea75eb..83fde07 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
; PR2589
define void @main({ i32 }*) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
index 0a79e86..adb0112 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6 -relocation-model=pic | grep comm
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 -relocation-model=pic | grep comm
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.__gcov_var = type { %struct.FILE*, i32, i32, i32, i32, i32, i32, [1025 x i32] }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-09-14-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-09-14-CoalescerBug.ll
index c601b90..5f9d9ae 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-09-14-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-09-14-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-apple-darwin
@"\01LC1" = external constant [288 x i8] ; <[288 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll
index b3ea6fc..d3bc3e1 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-apple-darwin
define void @gcov_exit() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-11-18-ScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-11-18-ScavengerAssert.ll
index 164e964..601a516 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-11-18-ScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-11-18-ScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2
define hidden i64 @__muldi3(i64 %u, i64 %v) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll
index 3f17a51..35ca7b4 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin9 -stats |& grep asm-printer | grep 164
+; RUN: llc < %s -mtriple=arm-apple-darwin9 -stats |& grep asm-printer | grep 154
%"struct.Adv5::Ekin<3>" = type <{ i8 }>
%"struct.Adv5::X::Energyflux<3>" = type { double }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
index 48e663d..4c0c59c 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2
target triple = "arm-apple-darwin9"
%struct.FILE_POS = type { i8, i8, i16, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
index d7befa0..a48f003 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR3610
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-s0:0:64-f80:32:32"
target triple = "arm-elf"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
index bd5b719..bc5e602 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2
target triple = "arm-apple-darwin9"
@a = external global double ; <double*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
index 399ed30..0ec17ae 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin9 -mattr=+vfp2
+; RUN: llc < %s -mtriple=armv6-apple-darwin9 -mattr=+vfp2
; rdar://6653182
%struct.ggBRDF = type { i32 (...)** }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
index 0ec6d7d..a1ce384 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
%struct.hit_t = type { %struct.v_t, double }
%struct.node_t = type { %struct.hit_t, %struct.hit_t, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
index 11c05c6..3526722 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | grep {swi 107}
+; RUN: llc < %s -march=arm | grep {swi 107}
define i32 @_swilseek(i32) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
index c00b1fb..f6b3d2c 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
; PR3795
define fastcc void @_D3foo3fooFAriZv({ i32, { double, double }* } %d_arg, i32 %x_arg) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll
index c7e343c..99907fc 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-FREM.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
declare i32 @printf(i8*, ...)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
index f394847..05d2f26 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* %CONST) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
index 223fa0f..deb092b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
; PR3954
define void @foo(...) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
index 2bca6e6..670d204 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linuxeabi-unknown-gnu -mattr=+v6
+; RUN: llc < %s -mtriple=arm-linuxeabi-unknown-gnu -mattr=+v6
; PR4166
%"byte[]" = type { i32, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
index d03b7ce..75610ff 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=local
+; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=local
; PR4100
@.str = external constant [30 x i8] ; <[30 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
index 35d4306..7046fcc 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
%struct.List = type { %struct.List*, i32 }
@Node5 = external constant %struct.List ; <%struct.List*> [#uses=1]
@"\01LC" = external constant [7 x i8] ; <[7 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
index f942c9f..2fc9eb3 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | grep swp
+; RUN: llc < %s -march=arm | grep swp
; PR4091
define void @foo(i32 %i, i32* %p) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
index 7cd35b9..403e3f6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6,+vfp2
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6,+vfp2
@"\01LC" = external constant [15 x i8] ; <[15 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
index 5eaae7a..98e0023 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6
%struct.anon = type { i16, i16 }
%struct.cab_archive = type { i32, i16, i16, i16, i16, i8, %struct.cab_folder*, %struct.cab_file* }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-12-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-12-RegScavengerAssert.ll
index 45b4bd4..27888d7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-12-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-12-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin
+; RUN: llc < %s -mtriple=armv6-apple-darwin
type { i32, i32, %struct.D_Sym**, [3 x %struct.D_Sym*] } ; type %0
type { i32, %struct.D_Reduction** } ; type %1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll
index c715a18..a0f903b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin
+; RUN: llc < %s -mtriple=armv6-apple-darwin
%struct.term = type { i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll
index cbe2385..b56b684 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv6-eabi -mattr=+vfp2 -float-abi=hard
+; RUN: llc < %s -mtriple=armv6-eabi -mattr=+vfp2 -float-abi=hard
; PR4419
define float @__ieee754_acosf(float %x) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
index 5c8d7b0..e068be7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin
+; RUN: llc < %s -mtriple=armv6-apple-darwin
%struct.rtunion = type { i64 }
%struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
index 27cad7c..17efe00 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
@nn = external global i32 ; <i32*> [#uses=1]
@al_len = external global i32 ; <i32*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
index 3a14d67..f520be3 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
@no_mat = external global i32 ; <i32*> [#uses=1]
@no_mis = external global i32 ; <i32*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
index f94b59d..eee6ff9 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
@JJ = external global i32* ; <i32**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
index bca7f79..93c92b1 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
@r = external global i32 ; <i32*> [#uses=1]
@qr = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
index 0c90592..277283d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
@XX = external global i32* ; <i32**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
index dfccefc..5c0e5fa 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
@qr = external global i32 ; <i32*> [#uses=1]
@II = external global i32* ; <i32**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll
index ea502cd..e1e94b6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6
+; RUN: llc < %s -march=arm -mattr=+v6
define void @test(i8* %x) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll
index 48b9080..ee93fde 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin10 -mattr=+vfp2 | grep fcmpezd | count 13
+; RUN: llc < %s -mtriple=armv6-apple-darwin10 -mattr=+vfp2 | grep fcmpezd | count 13
%struct.EDGE_PAIR = type { %struct.edge_rec*, %struct.edge_rec* }
%struct.VEC2 = type { double, double, double }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
index 5dd336b..b4b989b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin10
+; RUN: llc < %s -mtriple=armv6-apple-darwin10
%struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
%struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
index ad2be6e..24f4990 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
%struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
%struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
index dc1f73a..e1d19d1 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv7-apple-darwin10 -mattr=+vfp3
+; RUN: llc < %s -mtriple=armv7-apple-darwin10 -mattr=+vfp3
@a = external global double ; <double*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
index bdf5131..2d4e58d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon
+; RUN: llc < %s -march=arm -mattr=+neon
; PR4657
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll
index c16a2d1..65ffed2 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv6-elf
+; RUN: llc < %s -mtriple=armv6-elf
; PR4528
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll
index cb27473..9e5372a 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv6-elf
+; RUN: llc < %s -mtriple=armv6-elf
; PR4528
define arm_aapcscc i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
index 15fa145..18d68f7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
; PR4528
; Inline asm is allowed to contain operands "=&r", "0".
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll
index 54196dc..a46482c 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
; PR4716
define arm_aapcscc void @_start() nounwind naked {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
index 08038b0..84915c4 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
+; RUN: llc < %s -march=arm -mattr=+vfp2 -post-RA-scheduler -mcpu=cortex-a8
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
index e32bca9..a21ffc3 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
index ddc16de..e3d8ea6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
new file mode 100644
index 0000000..9123377
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
+
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-apple-darwin9"
+
+ at .str = external constant [36 x i8], align 1 ; <[36 x i8]*> [#uses=0]
+ at .str1 = external constant [31 x i8], align 1 ; <[31 x i8]*> [#uses=1]
+ at .str2 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1]
+
+declare arm_apcscc i32 @getUnknown(i32, ...) nounwind
+
+declare void @llvm.va_start(i8*) nounwind
+
+declare void @llvm.va_end(i8*) nounwind
+
+declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind
+
+define arm_apcscc i32 @main() nounwind {
+entry:
+ %0 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; <i32> [#uses=0]
+ %1 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; <i32> [#uses=0]
+ %2 = tail call arm_apcscc i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; <i32> [#uses=1]
+ %3 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-23-linkerprivate.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-23-linkerprivate.ll
index 93fb151..0fad533 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-23-linkerprivate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-23-linkerprivate.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-apple-darwin | FileCheck %s
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | FileCheck %s
; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm'
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll
index 5d11570..c6ef256 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mattr=+neon | not grep fldmfdd
+; RUN: llc < %s -mattr=+neon | not grep fldmfdd
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
target triple = "thumbv7-elf"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll
index fbe0a23..bc5bfe9 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mattr=+neon | not grep fldmfdd
+; RUN: llc < %s -mattr=+neon | not grep fldmfdd
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
target triple = "thumbv7-elf"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll
index 4a044a5..d5178b4 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mattr=+neon
+; RUN: llc < %s -mattr=+neon
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
target triple = "thumbv7-elf"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll
index 3b1413b..266fce6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mattr=+neon
+; RUN: llc < %s -mattr=+neon
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
target triple = "thumbv7-elf"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
new file mode 100644
index 0000000..b6cf880
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
@@ -0,0 +1,103 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin9 -march=arm | FileCheck %s
+
+%struct.A = type { i32* }
+
+define arm_apcscc void @"\01-[MyFunction Name:]"() {
+entry:
+ %save_filt.1 = alloca i32 ; <i32*> [#uses=2]
+ %save_eptr.0 = alloca i8* ; <i8**> [#uses=2]
+ %a = alloca %struct.A ; <%struct.A*> [#uses=3]
+ %eh_exception = alloca i8* ; <i8**> [#uses=5]
+ %eh_selector = alloca i32 ; <i32*> [#uses=3]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ call arm_apcscc void @_ZN1AC1Ev(%struct.A* %a)
+ invoke arm_apcscc void @_Z3barv()
+ to label %invcont unwind label %lpad
+
+invcont: ; preds = %entry
+ call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind
+ br label %return
+
+bb: ; preds = %ppad
+ %eh_select = load i32* %eh_selector ; <i32> [#uses=1]
+ store i32 %eh_select, i32* %save_filt.1, align 4
+ %eh_value = load i8** %eh_exception ; <i8*> [#uses=1]
+ store i8* %eh_value, i8** %save_eptr.0, align 4
+ call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind
+ %0 = load i8** %save_eptr.0, align 4 ; <i8*> [#uses=1]
+ store i8* %0, i8** %eh_exception, align 4
+ %1 = load i32* %save_filt.1, align 4 ; <i32> [#uses=1]
+ store i32 %1, i32* %eh_selector, align 4
+ br label %Unwind
+
+return: ; preds = %invcont
+ ret void
+
+lpad: ; preds = %entry
+ %eh_ptr = call i8* @llvm.eh.exception() ; <i8*> [#uses=1]
+ store i8* %eh_ptr, i8** %eh_exception
+ %eh_ptr1 = load i8** %eh_exception ; <i8*> [#uses=1]
+ %eh_select2 = call i32 (i8*, i8*, ...)* @llvm.eh.selector.i32(i8* %eh_ptr1, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i32 0) ; <i32> [#uses=1]
+ store i32 %eh_select2, i32* %eh_selector
+ br label %ppad
+
+ppad: ; preds = %lpad
+ br label %bb
+
+Unwind: ; preds = %bb
+ %eh_ptr3 = load i8** %eh_exception ; <i8*> [#uses=1]
+ call arm_apcscc void @_Unwind_SjLj_Resume(i8* %eh_ptr3)
+ unreachable
+}
+
+define linkonce_odr arm_apcscc void @_ZN1AC1Ev(%struct.A* %this) {
+entry:
+ %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store %struct.A* %this, %struct.A** %this_addr
+ %0 = call arm_apcscc i8* @_Znwm(i32 4) ; <i8*> [#uses=1]
+ %1 = bitcast i8* %0 to i32* ; <i32*> [#uses=1]
+ %2 = load %struct.A** %this_addr, align 4 ; <%struct.A*> [#uses=1]
+ %3 = getelementptr inbounds %struct.A* %2, i32 0, i32 0 ; <i32**> [#uses=1]
+ store i32* %1, i32** %3, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare arm_apcscc i8* @_Znwm(i32)
+
+define linkonce_odr arm_apcscc void @_ZN1AD1Ev(%struct.A* %this) nounwind {
+entry:
+ %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store %struct.A* %this, %struct.A** %this_addr
+ %0 = load %struct.A** %this_addr, align 4 ; <%struct.A*> [#uses=1]
+ %1 = getelementptr inbounds %struct.A* %0, i32 0, i32 0 ; <i32**> [#uses=1]
+ %2 = load i32** %1, align 4 ; <i32*> [#uses=1]
+ %3 = bitcast i32* %2 to i8* ; <i8*> [#uses=1]
+ call arm_apcscc void @_ZdlPv(i8* %3) nounwind
+ br label %bb
+
+bb: ; preds = %entry
+ br label %return
+
+return: ; preds = %bb
+ ret void
+}
+;CHECK: L_LSDA_1:
+
+declare arm_apcscc void @_ZdlPv(i8*) nounwind
+
+declare arm_apcscc void @_Z3barv()
+
+declare i8* @llvm.eh.exception() nounwind
+
+declare i32 @llvm.eh.selector.i32(i8*, i8*, ...) nounwind
+
+declare i32 @llvm.eh.typeid.for.i32(i8*) nounwind
+
+declare arm_apcscc i32 @__gxx_personality_sj0(...)
+
+declare arm_apcscc void @_Unwind_SjLj_Resume(i8*)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
new file mode 100644
index 0000000..e1e60e6
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; pr4843
+define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
+;CHECK: v2regbug:
+;CHECK: vzip.16
+ %tmp1 = load <4 x i16>* %B
+ %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>
+ ret <4 x i16> %tmp2
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll
new file mode 100644
index 0000000..f0301a8
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll
@@ -0,0 +1,106 @@
+; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-apple-darwin9"
+
+ at history = internal global [2 x [56 x i32]] [[56 x i32] [i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0], [56 x i32] [i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0]] ; <[2 x [56 x i32]]*> [#uses=3]
+ at nodes = internal global i64 0 ; <i64*> [#uses=4]
+ at .str = private constant [9 x i8] c"##-<=>+#\00", align 1 ; <[9 x i8]*> [#uses=2]
+ at .str1 = private constant [6 x i8] c"%c%d\0A\00", align 1 ; <[6 x i8]*> [#uses=1]
+ at .str2 = private constant [16 x i8] c"Fhourstones 2.0\00", align 1 ; <[16 x i8]*> [#uses=1]
+ at .str3 = private constant [54 x i8] c"Using %d transposition table entries with %d probes.\0A\00", align 1 ; <[54 x i8]*> [#uses=1]
+ at .str4 = private constant [31 x i8] c"Solving %d-ply position after \00", align 1 ; <[31 x i8]*> [#uses=1]
+ at .str5 = private constant [7 x i8] c" . . .\00", align 1 ; <[7 x i8]*> [#uses=1]
+ at .str6 = private constant [28 x i8] c"score = %d (%c) work = %d\0A\00", align 1 ; <[28 x i8]*> [#uses=1]
+ at .str7 = private constant [36 x i8] c"%lu pos / %lu msec = %.1f Kpos/sec\0A\00", align 1 ; <[36 x i8]*> [#uses=1]
+ at plycnt = internal global i32 0 ; <i32*> [#uses=21]
+ at dias = internal global [19 x i32] zeroinitializer ; <[19 x i32]*> [#uses=43]
+ at columns = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=18]
+ at height = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=21]
+ at rows = internal global [8 x i32] zeroinitializer ; <[8 x i32]*> [#uses=20]
+ at colthr = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=5]
+ at moves = internal global [44 x i32] zeroinitializer ; <[44 x i32]*> [#uses=9]
+ at .str8 = private constant [3 x i8] c"%d\00", align 1 ; <[3 x i8]*> [#uses=1]
+ at he = internal global i8* null ; <i8**> [#uses=9]
+ at hits = internal global i64 0 ; <i64*> [#uses=8]
+ at posed = internal global i64 0 ; <i64*> [#uses=7]
+ at ht = internal global i32* null ; <i32**> [#uses=5]
+ at .str16 = private constant [19 x i8] c"store rate = %.3f\0A\00", align 1 ; <[19 x i8]*> [#uses=1]
+ at .str117 = private constant [45 x i8] c"- %5.3f < %5.3f = %5.3f > %5.3f + %5.3f\0A\00", align 1 ; <[45 x i8]*> [#uses=1]
+ at .str218 = private constant [6 x i8] c"%7d%c\00", align 1 ; <[6 x i8]*> [#uses=1]
+ at .str319 = private constant [30 x i8] c"Failed to allocate %u bytes.\0A\00", align 1 ; <[30 x i8]*> [#uses=1]
+
+declare arm_apcscc i32 @puts(i8* nocapture) nounwind
+
+declare arm_apcscc i32 @getchar() nounwind
+
+define internal arm_apcscc i32 @transpose() nounwind readonly {
+; CHECK: push
+entry:
+ %0 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 1), align 4 ; <i32> [#uses=1]
+ %1 = shl i32 %0, 7 ; <i32> [#uses=1]
+ %2 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 2), align 4 ; <i32> [#uses=1]
+ %3 = or i32 %1, %2 ; <i32> [#uses=1]
+ %4 = shl i32 %3, 7 ; <i32> [#uses=1]
+ %5 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 3), align 4 ; <i32> [#uses=1]
+ %6 = or i32 %4, %5 ; <i32> [#uses=3]
+ %7 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 7), align 4 ; <i32> [#uses=1]
+ %8 = shl i32 %7, 7 ; <i32> [#uses=1]
+ %9 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 6), align 4 ; <i32> [#uses=1]
+ %10 = or i32 %8, %9 ; <i32> [#uses=1]
+ %11 = shl i32 %10, 7 ; <i32> [#uses=1]
+ %12 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 5), align 4 ; <i32> [#uses=1]
+ %13 = or i32 %11, %12 ; <i32> [#uses=3]
+ %14 = icmp ugt i32 %6, %13 ; <i1> [#uses=2]
+ %.pn2.in.i = select i1 %14, i32 %6, i32 %13 ; <i32> [#uses=1]
+ %.pn1.in.i = select i1 %14, i32 %13, i32 %6 ; <i32> [#uses=1]
+ %.pn2.i = shl i32 %.pn2.in.i, 7 ; <i32> [#uses=1]
+ %.pn3.i = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 4) ; <i32> [#uses=1]
+ %.pn.in.in.i = or i32 %.pn2.i, %.pn3.i ; <i32> [#uses=1]
+ %.pn.in.i = zext i32 %.pn.in.in.i to i64 ; <i64> [#uses=1]
+ %.pn.i = shl i64 %.pn.in.i, 21 ; <i64> [#uses=1]
+ %.pn1.i = zext i32 %.pn1.in.i to i64 ; <i64> [#uses=1]
+ %iftmp.22.0.i = or i64 %.pn.i, %.pn1.i ; <i64> [#uses=2]
+ %15 = lshr i64 %iftmp.22.0.i, 17 ; <i64> [#uses=1]
+ %16 = trunc i64 %15 to i32 ; <i32> [#uses=2]
+ %17 = urem i64 %iftmp.22.0.i, 1050011 ; <i64> [#uses=1]
+ %18 = trunc i64 %17 to i32 ; <i32> [#uses=1]
+ %19 = urem i32 %16, 179 ; <i32> [#uses=1]
+ %20 = or i32 %19, 131072 ; <i32> [#uses=1]
+ %21 = load i32** @ht, align 4 ; <i32*> [#uses=1]
+ br label %bb5
+
+bb: ; preds = %bb5
+ %22 = getelementptr inbounds i32* %21, i32 %x.0 ; <i32*> [#uses=1]
+ %23 = load i32* %22, align 4 ; <i32> [#uses=1]
+ %24 = icmp eq i32 %23, %16 ; <i1> [#uses=1]
+ br i1 %24, label %bb1, label %bb2
+
+bb1: ; preds = %bb
+ %25 = load i8** @he, align 4 ; <i8*> [#uses=1]
+ %26 = getelementptr inbounds i8* %25, i32 %x.0 ; <i8*> [#uses=1]
+ %27 = load i8* %26, align 1 ; <i8> [#uses=1]
+ %28 = sext i8 %27 to i32 ; <i32> [#uses=1]
+ ret i32 %28
+
+bb2: ; preds = %bb
+ %29 = add nsw i32 %20, %x.0 ; <i32> [#uses=3]
+ %30 = add i32 %29, -1050011 ; <i32> [#uses=1]
+ %31 = icmp sgt i32 %29, 1050010 ; <i1> [#uses=1]
+ %. = select i1 %31, i32 %30, i32 %29 ; <i32> [#uses=1]
+ %32 = add i32 %33, 1 ; <i32> [#uses=1]
+ br label %bb5
+
+bb5: ; preds = %bb2, %entry
+ %33 = phi i32 [ 0, %entry ], [ %32, %bb2 ] ; <i32> [#uses=2]
+ %x.0 = phi i32 [ %18, %entry ], [ %., %bb2 ] ; <i32> [#uses=3]
+ %34 = icmp sgt i32 %33, 7 ; <i1> [#uses=1]
+ br i1 %34, label %bb7, label %bb
+
+bb7: ; preds = %bb5
+ ret i32 -128
+}
+
+declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind
+
+declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll
new file mode 100644
index 0000000..f654a16
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll
@@ -0,0 +1,10 @@
+; RUN: llc -mattr=+neon < %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_apcscc void @foo() {
+entry:
+ %0 = insertelement <4 x i32> undef, i32 -1, i32 3
+ store <4 x i32> %0, <4 x i32>* undef, align 16
+ unreachable
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
new file mode 100644
index 0000000..98cab9a
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
@@ -0,0 +1,18 @@
+; RUN: llc -O1 -march=arm -mattr=+vfp2 < %s | FileCheck %s
+; pr4939
+
+define void @test(double* %x, double* %y) nounwind {
+ %1 = load double* %x, align 4
+ %2 = load double* %y, align 4
+ %3 = fsub double -0.000000e+00, %1
+ %4 = fcmp ugt double %2, %3
+ br i1 %4, label %bb1, label %bb2
+
+bb1:
+;CHECK: fstdhi
+ store double %1, double* %y, align 4
+ br label %bb2
+
+bb2:
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-10-postdec.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-10-postdec.ll
new file mode 100644
index 0000000..10653b5
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-10-postdec.ll
@@ -0,0 +1,11 @@
+; RUN: llc -march=arm < %s | FileCheck %s
+; Radar 7213850
+
+define i32 @test(i8* %d, i32 %x, i32 %y) nounwind {
+ %1 = ptrtoint i8* %d to i32
+;CHECK: sub
+ %2 = sub i32 %x, %1
+ %3 = add nsw i32 %2, %y
+ store i8 0, i8* %d, align 1
+ ret i32 %3
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
new file mode 100644
index 0000000..13adb24
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
@@ -0,0 +1,61 @@
+; RUN: llc -mattr=+neon < %s
+; PR4965
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-eabi"
+
+%struct.fr = type { [6 x %struct.pl] }
+%struct.obb = type { %"struct.m4", %"struct.p3" }
+%struct.pl = type { %"struct.p3" }
+%"struct.m4" = type { %"struct.p3", %"struct.p3", %"struct.p3", %"struct.p3" }
+%"struct.p3" = type { <4 x float> }
+
+declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+define arm_aapcs_vfpcc i8 @foo(%struct.fr* nocapture %this, %struct.obb* %box) nounwind {
+entry:
+ %val.i.i = load <4 x float>* undef ; <<4 x float>> [#uses=1]
+ %val2.i.i = load <4 x float>* null ; <<4 x float>> [#uses=1]
+ %elt3.i.i = getelementptr inbounds %struct.obb* %box, i32 0, i32 0, i32 2, i32 0 ; <<4 x float>*> [#uses=1]
+ %val4.i.i = load <4 x float>* %elt3.i.i ; <<4 x float>> [#uses=1]
+ %0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
+ %1 = fadd <4 x float> undef, zeroinitializer ; <<4 x float>> [#uses=1]
+ br label %bb33
+
+bb: ; preds = %bb33
+ %2 = fmul <4 x float> %val.i.i, undef ; <<4 x float>> [#uses=1]
+ %3 = fmul <4 x float> %val2.i.i, undef ; <<4 x float>> [#uses=1]
+ %4 = fadd <4 x float> %3, %2 ; <<4 x float>> [#uses=1]
+ %5 = fmul <4 x float> %val4.i.i, undef ; <<4 x float>> [#uses=1]
+ %6 = fadd <4 x float> %5, %4 ; <<4 x float>> [#uses=1]
+ %7 = bitcast <4 x float> %6 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %8 = and <4 x i32> %7, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=1]
+ %9 = or <4 x i32> %8, undef ; <<4 x i32>> [#uses=1]
+ %10 = bitcast <4 x i32> %9 to <4 x float> ; <<4 x float>> [#uses=1]
+ %11 = shufflevector <4 x float> %10, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
+ %12 = shufflevector <2 x float> %11, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %13 = fmul <4 x float> undef, %12 ; <<4 x float>> [#uses=1]
+ %14 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=1]
+ %15 = fadd <4 x float> %14, %13 ; <<4 x float>> [#uses=1]
+ %16 = fadd <4 x float> undef, %15 ; <<4 x float>> [#uses=1]
+ %17 = fadd <4 x float> %1, %16 ; <<4 x float>> [#uses=1]
+ %18 = fmul <4 x float> zeroinitializer, %17 ; <<4 x float>> [#uses=1]
+ %19 = insertelement <4 x float> %18, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=2]
+ %20 = shufflevector <4 x float> %19, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
+ %21 = shufflevector <4 x float> %19, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
+ %22 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %20, <2 x float> %21) nounwind ; <<2 x float>> [#uses=2]
+ %23 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %22, <2 x float> %22) nounwind ; <<2 x float>> [#uses=2]
+ %24 = shufflevector <2 x float> %23, <2 x float> %23, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %25 = fadd <4 x float> %24, zeroinitializer ; <<4 x float>> [#uses=1]
+ %tmp46 = extractelement <4 x float> %25, i32 0 ; <float> [#uses=1]
+ %26 = fcmp olt float %tmp46, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %26, label %bb41, label %bb33
+
+bb33: ; preds = %bb, %entry
+ br i1 undef, label %bb34, label %bb
+
+bb34: ; preds = %bb33
+ ret i8 undef
+
+bb41: ; preds = %bb
+ ret i8 1
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
new file mode 100644
index 0000000..758b59a
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a9
+
+define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+ %1 = ptrtoint i8* %pBuffer to i32
+
+ %lsr.iv2641 = inttoptr i32 %1 to float*
+ %tmp29 = add i32 %1, 4
+ %tmp2930 = inttoptr i32 %tmp29 to float*
+ %tmp31 = add i32 %1, 8
+ %tmp3132 = inttoptr i32 %tmp31 to float*
+ %tmp33 = add i32 %1, 12
+ %tmp3334 = inttoptr i32 %tmp33 to float*
+ %tmp35 = add i32 %1, 16
+ %tmp3536 = inttoptr i32 %tmp35 to float*
+ %tmp37 = add i32 %1, 20
+ %tmp3738 = inttoptr i32 %tmp37 to float*
+ %tmp39 = add i32 %1, 24
+ %tmp3940 = inttoptr i32 %tmp39 to float*
+ %2 = load float* %lsr.iv2641, align 4
+ %3 = load float* %tmp2930, align 4
+ %4 = load float* %tmp3132, align 4
+ %5 = load float* %tmp3334, align 4
+ %6 = load float* %tmp3536, align 4
+ %7 = load float* %tmp3738, align 4
+ %8 = load float* %tmp3940, align 4
+ %9 = insertelement <4 x float> undef, float %6, i32 0
+ %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> zeroinitializer
+ %11 = insertelement <4 x float> %10, float %7, i32 1
+ %12 = insertelement <4 x float> %11, float %8, i32 2
+ %13 = insertelement <4 x float> undef, float %2, i32 0
+ %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> zeroinitializer
+ %15 = insertelement <4 x float> %14, float %3, i32 1
+ %16 = insertelement <4 x float> %15, float %4, i32 2
+ %17 = insertelement <4 x float> %16, float %5, i32 3
+ %18 = fsub <4 x float> zeroinitializer, %12
+ %19 = shufflevector <4 x float> %18, <4 x float> undef, <4 x i32> zeroinitializer
+ %20 = shufflevector <4 x float> %17, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+ %21 = shufflevector <2 x float> %20, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+
+ ret <4 x float> %21
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll
new file mode 100644
index 0000000..980f8ce
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a9
+
+; PR4986
+
+define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+entry:
+ br i1 undef, label %return, label %bb.preheader
+
+bb.preheader: ; preds = %entry
+ br label %bb
+
+bb: ; preds = %bb, %bb.preheader
+ %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1]
+ %2 = insertelement <4 x float> %1, float undef, i32 2 ; <<4 x float>> [#uses=1]
+ %3 = insertelement <4 x float> %2, float undef, i32 3 ; <<4 x float>> [#uses=1]
+ %4 = fmul <4 x float> undef, %3 ; <<4 x float>> [#uses=1]
+ %5 = extractelement <4 x float> %4, i32 3 ; <float> [#uses=1]
+ store float %5, float* undef, align 4
+ br i1 undef, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
+
+define arm_aapcs_vfpcc <4 x float> @bar(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+ %1 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %2 = insertelement <4 x float> %1, float undef, i32 1 ; <<4 x float>> [#uses=1]
+ %3 = insertelement <4 x float> %2, float undef, i32 2 ; <<4 x float>> [#uses=1]
+ %4 = insertelement <4 x float> %3, float undef, i32 3 ; <<4 x float>> [#uses=1]
+ %5 = shufflevector <4 x float> %4, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
+ %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]
+ ret <4 x float> %6
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll
new file mode 100644
index 0000000..aace475
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon
+
+; PR5024
+
+%bar = type { <4 x float> }
+%foo = type { %bar, %bar, %bar, %bar }
+
+declare arm_aapcs_vfpcc <4 x float> @bbb(%bar*) nounwind
+
+define arm_aapcs_vfpcc void @aaa(%foo* noalias sret %agg.result, %foo* %tfrm) nounwind {
+entry:
+ %0 = call arm_aapcs_vfpcc <4 x float> @bbb(%bar* undef) nounwind ; <<4 x float>> [#uses=0]
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll
new file mode 100644
index 0000000..30931a2
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon
+
+; PR5024
+
+%bar = type { %foo, %foo }
+%foo = type { <4 x float> }
+
+declare arm_aapcs_vfpcc float @aaa(%foo* nocapture) nounwind readonly
+
+declare arm_aapcs_vfpcc %bar* @bbb(%bar*, <4 x float>, <4 x float>) nounwind
+
+define arm_aapcs_vfpcc void @ccc(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+entry:
+ br i1 undef, label %return, label %bb.nph
+
+bb.nph: ; preds = %entry
+ %0 = call arm_aapcs_vfpcc %bar* @bbb(%bar* undef, <4 x float> undef, <4 x float> undef) nounwind ; <%bar*> [#uses=0]
+ %1 = call arm_aapcs_vfpcc float @aaa(%foo* undef) nounwind ; <float> [#uses=0]
+ unreachable
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
new file mode 100644
index 0000000..2ff479b
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon
+
+; PR5024
+
+%struct.1 = type { %struct.4, %struct.4 }
+%struct.4 = type { <4 x float> }
+
+define arm_aapcs_vfpcc %struct.1* @hhh3(%struct.1* %this, <4 x float> %lenation.0, <4 x float> %legalation.0) nounwind {
+entry:
+ %0 = call arm_aapcs_vfpcc %struct.4* @sss1(%struct.4* undef, float 0.000000e+00) nounwind ; <%struct.4*> [#uses=0]
+ %1 = call arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4* null, float 5.000000e-01) nounwind ; <%struct.4*> [#uses=0]
+ %val92 = load <4 x float>* null ; <<4 x float>> [#uses=1]
+ %2 = call arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4* undef, <4 x float> %val92) nounwind ; <%struct.4*> [#uses=0]
+ ret %struct.1* %this
+}
+
+declare arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4*, float) nounwind
+
+declare arm_aapcs_vfpcc %struct.4* @sss1(%struct.4*, float) nounwind
+
+declare arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4*, <4 x float>) nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll
new file mode 100644
index 0000000..6281775
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; pr4926
+
+define arm_apcscc void @test_vget_lanep16() nounwind {
+entry:
+ %arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1]
+ %out_poly16_t = alloca i16 ; <i16*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+; CHECK: fldd
+ %0 = load <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1]
+ %1 = extractelement <4 x i16> %0, i32 1 ; <i16> [#uses=1]
+ store i16 %1, i16* %out_poly16_t, align 2
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll
new file mode 100644
index 0000000..ea2693a
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8
+; PR5055
+
+module asm ".globl\09__aeabi_f2lz"
+module asm ".set\09__aeabi_f2lz, __fixsfdi"
+module asm ""
+
+define arm_aapcs_vfpcc i64 @__fixsfdi(float %a) nounwind {
+entry:
+ %0 = fcmp olt float %a, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %0, label %bb, label %bb1
+
+bb: ; preds = %entry
+ %1 = fsub float -0.000000e+00, %a ; <float> [#uses=1]
+ %2 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %1) nounwind ; <i64> [#uses=1]
+ %3 = sub i64 0, %2 ; <i64> [#uses=1]
+ ret i64 %3
+
+bb1: ; preds = %entry
+ %4 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %a) nounwind ; <i64> [#uses=1]
+ ret i64 %4
+}
+
+declare arm_aapcs_vfpcc i64 @__fixunssfdi(float)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
new file mode 100644
index 0000000..53bd668
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -mcpu=arm10tdmi | FileCheck %s
+; PR4687
+
+%0 = type { double, double }
+
+define arm_aapcscc void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind {
+; CHECK: foo:
+; CHECK: bl __adddf3
+; CHECK-NOT: strd
+; CHECK: mov
+ %x76 = fmul double %y.0, 0.000000e+00 ; <double> [#uses=1]
+ %x77 = fadd double %y.0, 0.000000e+00 ; <double> [#uses=1]
+ %tmpr = fadd double %x.0, %x76 ; <double> [#uses=1]
+ %agg.result.0 = getelementptr %0* %agg.result, i32 0, i32 0 ; <double*> [#uses=1]
+ store double %tmpr, double* %agg.result.0, align 8
+ %agg.result.1 = getelementptr %0* %agg.result, i32 0, i32 1 ; <double*> [#uses=1]
+ store double %x77, double* %agg.result.1, align 8
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/addrmode.ll b/libclamav/c++/llvm/test/CodeGen/ARM/addrmode.ll
index a3832c0..9ccff07 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/addrmode.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/addrmode.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -stats |& grep asm-printer | grep 4
+; RUN: llc < %s -march=arm -stats |& grep asm-printer | grep 4
define i32 @t1(i32 %a) {
%b = mul i32 %a, 9
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/aliases.ll b/libclamav/c++/llvm/test/CodeGen/ARM/aliases.ll
index ea39da8..b2c0314 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/aliases.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/aliases.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=arm-linux-gnueabi -o %t
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -o %t
; RUN: grep set %t | count 5
; RUN: grep globl %t | count 4
; RUN: grep weak %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/align.ll b/libclamav/c++/llvm/test/CodeGen/ARM/align.ll
index bb336ce..d73abe6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/align.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/align.ll
@@ -1,9 +1,9 @@
-; RUN: llvm-as < %s | llc -march=arm | grep align.*1 | count 1
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi | \
+; RUN: llc < %s -march=arm | grep align.*1 | count 1
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | \
; RUN: grep align.*2 | count 2
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi | \
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | \
; RUN: grep align.*3 | count 2
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | \
+; RUN: llc < %s -mtriple=arm-apple-darwin | \
; RUN: grep align.*2 | count 4
@a = global i1 true
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/alloca.ll b/libclamav/c++/llvm/test/CodeGen/ARM/alloca.ll
index f7e450f..15cf677 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/alloca.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/alloca.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnu | \
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | \
; RUN: grep {mov r11, sp}
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnu | \
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | \
; RUN: grep {mov sp, r11}
define void @f(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/argaddr.ll b/libclamav/c++/llvm/test/CodeGen/ARM/argaddr.ll
index 080827d..116a32f 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/argaddr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/argaddr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define void @f(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arguments-nosplit-double.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arguments-nosplit-double.ll
index 57ff95c..770e41d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arguments-nosplit-double.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arguments-nosplit-double.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi | not grep r3
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | not grep r3
; PR4059
define i32 @f(i64 %z, i32 %a, double %b) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arguments-nosplit-i64.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arguments-nosplit-i64.ll
index 5464674..815edfd 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arguments-nosplit-i64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arguments-nosplit-i64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi | not grep r3
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | not grep r3
; PR4058
define i32 @f(i64 %z, i32 %a, i64 %b) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arguments.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arguments.ll
index 833e22d..ad5b2d6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arguments.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arguments.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi | \
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | \
; RUN: grep {mov r0, r2} | count 1
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | \
+; RUN: llc < %s -mtriple=arm-apple-darwin | \
; RUN: grep {mov r0, r1} | count 1
define i32 @f(i32 %a, i64 %b) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arguments2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arguments2.ll
index eb7e45b..a515ad7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arguments2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arguments2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
define i32 @f(i32 %a, i128 %b) {
%tmp = call i32 @g(i128 %b)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arguments3.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arguments3.ll
index 97c0405..58f64c6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arguments3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arguments3.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
define i64 @f(i32 %a, i128 %b) {
%tmp = call i64 @g(i128 %b)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arguments4.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arguments4.ll
index 63ba64b..f5f4207 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arguments4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arguments4.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
define float @f(i32 %a, i128 %b) {
%tmp = call float @g(i128 %b)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arguments5.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arguments5.ll
index 2000ff7..388a8eb 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arguments5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arguments5.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
define double @f(i32 %a, i128 %b) {
%tmp = call double @g(i128 %b)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arguments6.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arguments6.ll
index a18c621..3f757fe 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arguments6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arguments6.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
define i128 @f(i32 %a, i128 %b) {
%tmp = call i128 @g(i128 %b)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arguments7.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arguments7.ll
index 489ffd4..038e417 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arguments7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arguments7.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
define double @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, double %b) {
%tmp = call double @g(i32 %a2, i32 %a3, i32 %a4, i32 %a5, double %b)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arguments8.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arguments8.ll
index 5ff7e09..6999a4d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arguments8.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arguments8.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
define i64 @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i64 %b) {
%tmp = call i64 @g(i32 %a2, i32 %a3, i32 %a4, i32 %a5, i64 %b)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arguments_f64_backfill.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arguments_f64_backfill.ll
index 07d928a..690f488 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arguments_f64_backfill.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arguments_f64_backfill.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi -mattr=+vfp2 -float-abi=hard | grep {fcpys s0, s1}
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -mattr=+vfp2 -float-abi=hard | grep {fcpys s0, s1}
define float @f(float %z, double %a, float %b) {
%tmp = call float @g(float %b)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arm-asm.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arm-asm.ll
index b260b13..2e35e39 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arm-asm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arm-asm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define void @frame_dummy() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arm-frameaddr.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arm-frameaddr.ll
index f1e4c2a..2739860 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arm-frameaddr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arm-frameaddr.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep mov | grep r7
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi | grep mov | grep r11
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | grep r7
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | grep r11
; PR4344
; PR4416
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/arm-negative-stride.ll b/libclamav/c++/llvm/test/CodeGen/ARM/arm-negative-stride.ll
index 553c2fb..c4b4ec6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/arm-negative-stride.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/arm-negative-stride.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | grep {str r1, \\\[r.*, -r.*, lsl #2\}
+; RUN: llc < %s -march=arm | grep {str r1, \\\[r.*, -r.*, lsl #2\}
define void @test(i32* %P, i32 %A, i32 %i) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/bfc.ll b/libclamav/c++/llvm/test/CodeGen/ARM/bfc.ll
index 8bec9fe..53392de 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/bfc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/bfc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6t2 | grep "bfc " | count 3
+; RUN: llc < %s -march=arm -mattr=+v6t2 | grep "bfc " | count 3
; 4278190095 = 0xff00000f
define i32 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/bic.ll b/libclamav/c++/llvm/test/CodeGen/ARM/bic.ll
index b4ea433..b16dcc6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/bic.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/bic.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | grep {bic\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*} | count 2
+; RUN: llc < %s -march=arm | grep {bic\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*} | count 2
define i32 @f1(i32 %a, i32 %b) {
%tmp = xor i32 %b, 4294967295
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/bits.ll b/libclamav/c++/llvm/test/CodeGen/ARM/bits.ll
index 0ac4f9a..9e94efe 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/bits.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/bits.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm > %t
+; RUN: llc < %s -march=arm > %t
; RUN: grep and %t | count 1
; RUN: grep orr %t | count 1
; RUN: grep eor %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/branch.ll b/libclamav/c++/llvm/test/CodeGen/ARM/branch.ll
deleted file mode 100644
index 7f6b183..0000000
--- a/libclamav/c++/llvm/test/CodeGen/ARM/branch.ll
+++ /dev/null
@@ -1,57 +0,0 @@
-; RUN: llvm-as < %s | llc -march=arm -disable-arm-if-conversion > %t
-; RUN: grep bne %t
-; RUN: grep bge %t
-; RUN: grep bhs %t
-; RUN: grep blo %t
-
-define void @f1(i32 %a, i32 %b, i32* %v) {
-entry:
- %tmp = icmp eq i32 %a, %b ; <i1> [#uses=1]
- br i1 %tmp, label %cond_true, label %return
-
-cond_true: ; preds = %entry
- store i32 0, i32* %v
- ret void
-
-return: ; preds = %entry
- ret void
-}
-
-define void @f2(i32 %a, i32 %b, i32* %v) {
-entry:
- %tmp = icmp slt i32 %a, %b ; <i1> [#uses=1]
- br i1 %tmp, label %cond_true, label %return
-
-cond_true: ; preds = %entry
- store i32 0, i32* %v
- ret void
-
-return: ; preds = %entry
- ret void
-}
-
-define void @f3(i32 %a, i32 %b, i32* %v) {
-entry:
- %tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
- br i1 %tmp, label %cond_true, label %return
-
-cond_true: ; preds = %entry
- store i32 0, i32* %v
- ret void
-
-return: ; preds = %entry
- ret void
-}
-
-define void @f4(i32 %a, i32 %b, i32* %v) {
-entry:
- %tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
- br i1 %tmp, label %return, label %cond_true
-
-cond_true: ; preds = %entry
- store i32 0, i32* %v
- ret void
-
-return: ; preds = %entry
- ret void
-}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/bx_fold.ll b/libclamav/c++/llvm/test/CodeGen/ARM/bx_fold.ll
index 437b318..0e3e070 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/bx_fold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/bx_fold.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm
-; RUN: llvm-as < %s | llc -march=arm | not grep bx
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | not grep bx
define void @test(i32 %Ptr, i8* %L) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/call.ll b/libclamav/c++/llvm/test/CodeGen/ARM/call.ll
index 6b19665..52246c3 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/call.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/call.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm | grep {mov lr, pc}
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v5t | grep blx
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi\
+; RUN: llc < %s -march=arm | grep {mov lr, pc}
+; RUN: llc < %s -march=arm -mattr=+v5t | grep blx
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\
; RUN: -relocation-model=pic | grep {PLT}
@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/call_nolink.ll b/libclamav/c++/llvm/test/CodeGen/ARM/call_nolink.ll
index 1af6fad..efe29d8 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/call_nolink.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/call_nolink.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
; RUN: not grep {bx lr}
%struct.anon = type { i32 (i32, i32, i32)*, i32, i32, [3 x i32], i8*, i8*, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/carry.ll b/libclamav/c++/llvm/test/CodeGen/ARM/carry.ll
index 3bf2dc0..294de5f 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/carry.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/carry.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm | grep "subs r" | count 2
-; RUN: llvm-as < %s | llc -march=arm | grep "adc r"
-; RUN: llvm-as < %s | llc -march=arm | grep "sbc r" | count 2
+; RUN: llc < %s -march=arm | grep "subs r" | count 2
+; RUN: llc < %s -march=arm | grep "adc r"
+; RUN: llc < %s -march=arm | grep "sbc r" | count 2
define i64 @f1(i64 %a, i64 %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/clz.ll b/libclamav/c++/llvm/test/CodeGen/ARM/clz.ll
index 389fb2c..d2235c9 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/clz.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/clz.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v5t | grep clz
+; RUN: llc < %s -march=arm -mattr=+v5t | grep clz
declare i32 @llvm.ctlz.i32(i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/compare-call.ll b/libclamav/c++/llvm/test/CodeGen/ARM/compare-call.ll
index fcb8b17..5f3ed1d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/compare-call.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/compare-call.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2 | \
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | \
; RUN: grep fcmpes
define void @test3(float* %glob, i32 %X) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/constants.ll b/libclamav/c++/llvm/test/CodeGen/ARM/constants.ll
index 095157b..e2d8ddc 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/constants.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/constants.ll
@@ -1,13 +1,13 @@
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep {mov r0, #0} | count 1
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep {mov r0, #255$} | count 1
-; RUN: llvm-as < %s | llc -march=arm -asm-verbose | \
+; RUN: llc < %s -march=arm -asm-verbose | \
; RUN: grep {mov r0.*256} | count 1
-; RUN: llvm-as < %s | llc -march=arm -asm-verbose | grep {orr.*256} | count 1
-; RUN: llvm-as < %s | llc -march=arm -asm-verbose | grep {mov r0, .*-1073741761} | count 1
-; RUN: llvm-as < %s | llc -march=arm -asm-verbose | grep {mov r0, .*1008} | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep {cmp r0, #1, 16} | count 1
+; RUN: llc < %s -march=arm -asm-verbose | grep {orr.*256} | count 1
+; RUN: llc < %s -march=arm -asm-verbose | grep {mov r0, .*-1073741761} | count 1
+; RUN: llc < %s -march=arm -asm-verbose | grep {mov r0, .*1008} | count 1
+; RUN: llc < %s -march=arm | grep {cmp r0, #1, 16} | count 1
define i32 @f1() {
ret i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/cse-libcalls.ll b/libclamav/c++/llvm/test/CodeGen/ARM/cse-libcalls.ll
index 4f4091a..0dcf9dd 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/cse-libcalls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/cse-libcalls.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | grep {bl.\*__ltdf} | count 1
+; RUN: llc < %s -march=arm | grep {bl.\*__ltdf} | count 1
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ctors_dtors.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ctors_dtors.ll
index 714ca61..fb94626 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ctors_dtors.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ctors_dtors.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | FileCheck %s -check-prefix=ELF
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=GNUEABI
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
+; RUN: llc < %s -mtriple=arm-linux-gnu | FileCheck %s -check-prefix=ELF
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=GNUEABI
; DARWIN: .section __DATA,__mod_init_func,mod_init_funcs
; DARWIN: .section __DATA,__mod_term_func,mod_term_funcs
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/div.ll b/libclamav/c++/llvm/test/CodeGen/ARM/div.ll
index 1085ec7..2f724e7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/div.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/div.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm > %t
+; RUN: llc < %s -march=arm > %t
; RUN: grep __divsi3 %t
; RUN: grep __udivsi3 %t
; RUN: grep __modsi3 %t
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/dyn-stackalloc.ll b/libclamav/c++/llvm/test/CodeGen/ARM/dyn-stackalloc.ll
index e0cd4e1..92e2d13 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/dyn-stackalloc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/dyn-stackalloc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/extloadi1.ll b/libclamav/c++/llvm/test/CodeGen/ARM/extloadi1.ll
index 2e9041c..dc45ce7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/extloadi1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/extloadi1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
@handler_installed.6144.b = external global i1 ; <i1*> [#uses=1]
define void @__mf_sigusr1_respond() {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fabss.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fabss.ll
index ffe859d..5690a01 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fabss.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fabss.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fabss\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E {vabs.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E {fabss\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E {vabs.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E {fabss\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fabss\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vabs.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fabss\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vabs.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fabss\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
define float @test(float %a, float %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fadds.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fadds.ll
index 5d59f2b..a01f868 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fadds.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fadds.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fadds\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E {vadd.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E {fadds\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E {vadd.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E {fadds\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fadds\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vadd.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fadds\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vadd.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fadds\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
define float @test(float %a, float %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fcopysign.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fcopysign.ll
index 66acda9..bf7c305 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fcopysign.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fcopysign.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm | grep bic | count 2
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2 | \
+; RUN: llc < %s -march=arm | grep bic | count 2
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | \
; RUN: grep fneg | count 2
define float @test1(float %x, double %y) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fdivs.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fdivs.ll
index 56c0dab..2af250d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fdivs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fdivs.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fdivs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E {fdivs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E {fdivs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E {fdivs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E {fdivs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fdivs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {fdivs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fdivs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {fdivs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fdivs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
define float @test(float %a, float %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fixunsdfdi.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fixunsdfdi.ll
index 777a3d6..ebf1d84 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fixunsdfdi.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fixunsdfdi.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
-; RUN: llvm-as < %s | llc -march=arm -mattr=vfp2 | not grep fstd
+; RUN: llc < %s -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=vfp2 | not grep fstd
define hidden i64 @__fixunsdfdi(double %x) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fmacs.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fmacs.ll
index 822d399..1a1cd07 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fmacs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fmacs.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E {vmla.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E {vmla.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmla.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmla.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
define float @test(float %acc, float %a, float %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fmdrr-fmrrd.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fmdrr-fmrrd.ll
index 315e623..eb72faf 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fmdrr-fmrrd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fmdrr-fmrrd.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=vfp2 | not grep fmdrr
-; RUN: llvm-as < %s | llc -march=arm -mattr=vfp2 | not grep fmrrd
+; RUN: llc < %s -march=arm -mattr=vfp2 | not grep fmdrr
+; RUN: llc < %s -march=arm -mattr=vfp2 | not grep fmrrd
; naive codegen for this is:
; _i:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fmscs.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fmscs.ll
index 8162177..c6e6d40 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fmscs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fmscs.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fmscs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E {fmscs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E {fmscs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E {fmscs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E {fmscs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fmscs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {fmscs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fmscs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {fmscs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fmscs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
define float @test(float %acc, float %a, float %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fmuls.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fmuls.ll
index 56e6374..cb5dade 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fmuls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fmuls.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fmuls\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E {fmuls\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E {fmuls\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fmuls\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fmuls\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fmuls\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
define float @test(float %a, float %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fnegs.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fnegs.ll
index 0be12ab..7da443d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fnegs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fnegs.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fnegs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E {vneg.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 2
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E {fnegs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E {vneg.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 2
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E {fnegs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2
+; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fnegs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vneg.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fnegs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vneg.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 2
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fnegs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2
define float @test1(float* %a) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fnmacs.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fnmacs.ll
index 0fda67f..e57bbbb 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fnmacs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fnmacs.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E {vmls.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E {vmls.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmls.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmls.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
define float @test(float %acc, float %a, float %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fnmscs.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fnmscs.ll
index a48e75a..3ae437d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fnmscs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fnmscs.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | FileCheck %s
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | FileCheck %s
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | FileCheck %s
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | FileCheck %s
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
define float @test1(float %acc, float %a, float %b) nounwind {
; CHECK: fnmscs s2, s1, s0
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fnmul.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fnmul.ll
index 7bbda2d..613b347 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fnmul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fnmul.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2 | grep fnmuld
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2 -enable-sign-dependent-rounding-fp-math | grep fmul
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep fnmuld
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -enable-sign-dependent-rounding-fp-math | grep fmul
define double @t1(double %a, double %b) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fnmuls.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fnmuls.ll
index 486119b..efd87d2 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fnmuls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fnmuls.ll
@@ -1,9 +1,9 @@
; XFAIL: *
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | FileCheck %s
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | FileCheck %s
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | FileCheck %s
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | FileCheck %s
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
define float @test1(float %a, float %b) nounwind {
; CHECK: fnmscs s2, s1, s0
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/formal.ll b/libclamav/c++/llvm/test/CodeGen/ARM/formal.ll
index 6d6d108..4ac10ba 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/formal.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/formal.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=+vfp2
declare void @bar(i64 %x, i64 %y)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fp.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fp.ll
index ba199db..301a796 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 > %t
+; RUN: llc < %s -march=arm -mattr=+vfp2 > %t
; RUN: grep fmsr %t | count 4
; RUN: grep fsitos %t
; RUN: grep fmrs %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fp_convert.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fp_convert.ll
index fa9e97e..9ce2ac5 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fp_convert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fp_convert.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | FileCheck %s -check-prefix=NEON
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | FileCheck %s -check-prefix=VFP2
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON
-; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEON
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
define i32 @test1(float %a, float %b) {
; VFP2: test1:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fparith.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fparith.ll
index 568a6c4..7386b91 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fparith.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fparith.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 > %t
+; RUN: llc < %s -march=arm -mattr=+vfp2 > %t
; RUN: grep fadds %t
; RUN: grep faddd %t
; RUN: grep fmuls %t
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fpcmp.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fpcmp.ll
index ce0f402..8370fbb 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fpcmp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fpcmp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 > %t
+; RUN: llc < %s -march=arm -mattr=+vfp2 > %t
; RUN: grep movmi %t
; RUN: grep moveq %t
; RUN: grep movgt %t
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fpcmp_ueq.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fpcmp_ueq.ll
index 3e749af..67f70e9 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fpcmp_ueq.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fpcmp_ueq.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm | grep moveq
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep movvs
+; RUN: llc < %s -march=arm | grep moveq
+; RUN: llc < %s -march=arm -mattr=+vfp2 | grep movvs
define i32 @f7(float %a, float %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fpconv.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fpconv.ll
index 218b25f..5420106 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fpconv.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fpconv.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 > %t
+; RUN: llc < %s -march=arm -mattr=+vfp2 > %t
; RUN: grep fcvtsd %t
; RUN: grep fcvtds %t
; RUN: grep ftosizs %t
@@ -9,7 +9,7 @@
; RUN: grep fsitod %t
; RUN: grep fuitos %t
; RUN: grep fuitod %t
-; RUN: llvm-as < %s | llc -march=arm > %t
+; RUN: llc < %s -march=arm > %t
; RUN: grep truncdfsf2 %t
; RUN: grep extendsfdf2 %t
; RUN: grep fixsfsi %t
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fpmem.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fpmem.ll
index 13653bb..fa897bf 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fpmem.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fpmem.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep {mov r0, #0} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
+; RUN: llc < %s -march=arm -mattr=+vfp2 | \
; RUN: grep {flds.*\\\[} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
+; RUN: llc < %s -march=arm -mattr=+vfp2 | \
; RUN: grep {fsts.*\\\[} | count 1
define float @f1(float %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fpow.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fpow.ll
index 461a2c9..6d48792 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fpow.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fpow.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define double @t(double %x, double %y) nounwind optsize {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fpowi.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fpowi.ll
index ab09fff..174106b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fpowi.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fpowi.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi | grep powidf2
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep powidf2
; PR1287
; ModuleID = '<stdin>'
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fptoint.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fptoint.ll
index 41168ac..0d270b0 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fptoint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fptoint.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2 | grep fmrs | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6,+vfp2 | not grep fmrrd
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep fmrs | count 1
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | not grep fmrrd
@i = weak global i32 0 ; <i32*> [#uses=2]
@u = weak global i32 0 ; <i32*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/fsubs.ll b/libclamav/c++/llvm/test/CodeGen/ARM/fsubs.ll
index e318237..060dd46 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/fsubs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/fsubs.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fsubs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E {vsub.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E {fsubs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fsubs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vsub.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fsubs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
define float @test(float %a, float %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/hardfloat_neon.ll b/libclamav/c++/llvm/test/CodeGen/ARM/hardfloat_neon.ll
index 728370a..4abf04b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/hardfloat_neon.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/hardfloat_neon.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi -mattr=+neon -float-abi=hard
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -mattr=+neon -float-abi=hard
define <16 x i8> @vmulQi8_reg(<16 x i8> %A, <16 x i8> %B) nounwind {
%tmp1 = mul <16 x i8> %A, %B
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/hello.ll b/libclamav/c++/llvm/test/CodeGen/ARM/hello.ll
index 16231da..ccdc7bf 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/hello.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/hello.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi | grep mov | count 1
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu --disable-fp-elim | \
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1
+; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \
; RUN: grep mov | count 3
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep mov | count 2
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2
@str = internal constant [12 x i8] c"Hello World\00"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis-2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis-2.ll
index 6cf69aa..90f5308 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis-2.ll
@@ -1,9 +1,12 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldr | count 2
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
@x = weak hidden global i32 0 ; <i32*> [#uses=1]
define i32 @t() nounwind readonly {
entry:
+; CHECK: t:
+; CHECK: ldr
+; CHECK-NEXT: ldr
%0 = load i32* @x, align 4 ; <i32> [#uses=1]
ret i32 %0
}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis-3.ll b/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis-3.ll
index 4477f2a..3bd710a 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis-3.ll
@@ -1,12 +1,15 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldr | count 6
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep non_lazy_ptr
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep long | count 4
+; RUN: llc < %s -mtriple=arm-apple-darwin9 | FileCheck %s
@x = external hidden global i32 ; <i32*> [#uses=1]
@y = extern_weak hidden global i32 ; <i32*> [#uses=1]
define i32 @t() nounwind readonly {
entry:
+; CHECK: LCPI1_0:
+; CHECK-NEXT: .long _x
+; CHECK: LCPI1_1:
+; CHECK-NEXT: .long _y
+
%0 = load i32* @x, align 4 ; <i32> [#uses=1]
%1 = load i32* @y, align 4 ; <i32> [#uses=1]
%2 = add i32 %1, %0 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis.ll b/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis.ll
index 93f81ec..3544ae8 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/hidden-vis.ll
@@ -1,18 +1,23 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | \
-; RUN: grep .private_extern | count 2
+; RUN: llc < %s -mtriple=arm-linux | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
-%struct.Person = type { i32 }
@a = hidden global i32 0
@b = external global i32
+define weak hidden void @t1() nounwind {
+; LINUX: .hidden t1
+; LINUX: t1:
-define weak hidden void @_ZN6Person13privateMethodEv(%struct.Person* %this) {
+; DARWIN: .private_extern _t1
+; DARWIN: t1:
ret void
}
-declare void @function(i32)
+define weak void @t2() nounwind {
+; LINUX: t2:
+; LINUX: .hidden a
-define weak void @_ZN6PersonC1Ei(%struct.Person* %this, i32 %_c) {
+; DARWIN: t2:
+; DARWIN: .private_extern _a
ret void
}
-
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/iabs.ll b/libclamav/c++/llvm/test/CodeGen/ARM/iabs.ll
index ede6d74..1054f27 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/iabs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/iabs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -stats |& \
+; RUN: llc < %s -march=arm -stats |& \
; RUN: grep {3 .*Number of machine instrs printed}
;; Integer absolute value, should produce something as good as: ARM:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt1.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt1.ll
index 7d42955..e6aa044 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt1.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm
-; RUN: llvm-as < %s | llc -march=arm | grep bx | count 1
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | grep bx | count 1
define i32 @t1(i32 %a, i32 %b) {
%tmp2 = icmp eq i32 %a, 0
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt2.ll
index 3942061..ce57d73 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt2.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=arm
-; RUN: llvm-as < %s | llc -march=arm | grep bxlt | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep bxgt | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep bxge | count 1
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | grep bxlt | count 1
+; RUN: llc < %s -march=arm | grep bxgt | count 1
+; RUN: llc < %s -march=arm | grep bxge | count 1
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
%tmp2 = icmp sgt i32 %c, 10
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt3.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt3.ll
index 620bcbe..f7ebac6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt3.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm
-; RUN: llvm-as < %s | llc -march=arm | grep cmpne | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep bx | count 2
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | grep cmpne | count 1
+; RUN: llc < %s -march=arm | grep bx | count 2
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
switch i32 %c, label %cond_next [
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt4.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt4.ll
index ce5a679..f28c61b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt4.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm
-; RUN: llvm-as < %s | llc -march=arm | grep subgt | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep suble | count 1
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | grep subgt | count 1
+; RUN: llc < %s -march=arm | grep suble | count 1
; FIXME: Check for # of unconditional branch after adding branch folding post ifcvt.
define i32 @t(i32 %a, i32 %b) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt5.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt5.ll
index f8d4f82..e9145ac 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt5.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
-; RUN: llvm-as < %s | llc -march=arm | grep blge | count 1
+; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
@x = external global i32* ; <i32**> [#uses=1]
@@ -11,6 +10,8 @@ entry:
}
define void @t1(i32 %a, i32 %b) {
+; CHECK: t1:
+; CHECK: ldmltfd sp!, {r7, pc}
entry:
%tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt6.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt6.ll
index 63c4a08..5824115 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt6.ll
@@ -1,10 +1,6 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=arm -mtriple=arm-apple-darwin
-; RUN: llvm-as < %s | \
-; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep cmpne | count 1
-; RUN: llvm-as < %s | \
-; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep ldmhi | count 1
define void @foo(i32 %X, i32 %Y) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt7.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt7.ll
index 6bb4b56..f9cf88f 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt7.ll
@@ -1,13 +1,8 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=arm -mtriple=arm-apple-darwin
-; RUN: llvm-as < %s | \
-; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep cmpeq | count 1
-; RUN: llvm-as < %s | \
-; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep moveq | count 1
-; RUN: llvm-as < %s | \
-; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep ldmeq | count 1
; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of BB1.
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt8.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt8.ll
index 85bd8c7..6cb8e7b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt8.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt8.ll
@@ -1,7 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=arm -mtriple=arm-apple-darwin
-; RUN: llvm-as < %s | \
-; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep ldmne | count 1
%struct.SString = type { i8*, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt9.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt9.ll
index bbd2f2e..05bdc45 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt9.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ifcvt9.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define fastcc void @t() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll b/libclamav/c++/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll
index 832858e..febe6f5 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm
-; RUN: llvm-as < %s | llc -mtriple=arm-linux
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -mtriple=arm-linux
define void @foo(<8 x float>* %f, <8 x float>* %g, <4 x i64>* %y)
{
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/imm.ll b/libclamav/c++/llvm/test/CodeGen/ARM/imm.ll
index 998adba..6f25f9d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/imm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/imm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | not grep CPI
+; RUN: llc < %s -march=arm | not grep CPI
define i32 @test1(i32 %A) {
%B = add i32 %A, -268435441 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll b/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll
index 2ceceae..45dfcf0 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
; Test ARM-mode "I" constraint, for any Data Processing immediate.
define i32 @testI(i32 %x) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm.ll b/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm.ll
index 2f7332a..d522348 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6
+; RUN: llc < %s -march=arm -mattr=+v6
define i32 @test1(i32 %tmp54) {
%tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 ) ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm2.ll
index 69394eb..a99bccf 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/inlineasm2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=+vfp2
define double @__ieee754_sqrt(double %x) {
%tmp2 = tail call double asm "fsqrtd ${0:P}, ${1:P}", "=w,w"( double %x )
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/insn-sched1.ll b/libclamav/c++/llvm/test/CodeGen/ARM/insn-sched1.ll
index f203443..59f0d53 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/insn-sched1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/insn-sched1.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6 |\
+; RUN: llc < %s -march=arm -mattr=+v6
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 |\
; RUN: grep mov | count 3
define i32 @test(i32 %x) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ispositive.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ispositive.ll
index 7e8eb42..5116ac8 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ispositive.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ispositive.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | grep {mov r0, r0, lsr #31}
+; RUN: llc < %s -march=arm | grep {mov r0, r0, lsr #31}
define i32 @test1(i32 %X) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/large-stack.ll b/libclamav/c++/llvm/test/CodeGen/ARM/large-stack.ll
index b1738a4..ddf0f0e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/large-stack.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/large-stack.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define void @test1() {
%tmp = alloca [ 64 x i32 ] , align 4
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ldm.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ldm.ll
index 6a05457..774b3c0 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ldm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ldm.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep ldmia | count 2
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep ldmib | count 1
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | \
+; RUN: llc < %s -mtriple=arm-apple-darwin | \
; RUN: grep {ldmfd sp\!} | count 3
@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ldr.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ldr.ll
index ea99655..954fb5b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ldr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ldr.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm | grep {ldr r0} | count 7
-; RUN: llvm-as < %s | llc -march=arm | grep mov | grep 1
-; RUN: llvm-as < %s | llc -march=arm | not grep mvn
-; RUN: llvm-as < %s | llc -march=arm | grep ldr | grep lsl
-; RUN: llvm-as < %s | llc -march=arm | grep ldr | grep lsr
+; RUN: llc < %s -march=arm | grep {ldr r0} | count 7
+; RUN: llc < %s -march=arm | grep mov | grep 1
+; RUN: llc < %s -march=arm | not grep mvn
+; RUN: llc < %s -march=arm | grep ldr | grep lsl
+; RUN: llc < %s -march=arm | grep ldr | grep lsr
define i32 @f1(i32* %v) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ldr_ext.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ldr_ext.ll
index dc76a1c..d29eb02 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ldr_ext.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ldr_ext.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | FileCheck %s
+; RUN: llc < %s -march=arm | FileCheck %s
define i32 @test1(i8* %t1) nounwind {
; CHECK: ldrb
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ldr_frame.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ldr_frame.ll
index 4431506..a3abdb6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ldr_frame.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ldr_frame.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | not grep mov
+; RUN: llc < %s -march=arm | not grep mov
define i32 @f1() {
%buf = alloca [32 x i32], align 4
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ldr_post.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ldr_post.ll
index 0491563..97a48e1 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ldr_post.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ldr_post.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep {ldr.*\\\[.*\],} | count 1
define i32 @test(i32 %a, i32 %b, i32 %c) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ldr_pre.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ldr_pre.ll
index 7e44742..7c44284 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ldr_pre.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ldr_pre.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep {ldr.*\\!} | count 2
define i32* @test1(i32* %X, i32* %dest) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ldrd.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ldrd.ll
index f1bee05..8f7ae55 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ldrd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ldrd.ll
@@ -1,12 +1,20 @@
-; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin | grep ldrd
-; RUN: llvm-as < %s | llc -mtriple=armv5-apple-darwin | not grep ldrd
-; RUN: llvm-as < %s | llc -mtriple=armv6-eabi | not grep ldrd
+; RUN: llc < %s -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=V6
+; RUN: llc < %s -mtriple=armv5-apple-darwin | FileCheck %s -check-prefix=V5
+; RUN: llc < %s -mtriple=armv6-eabi | FileCheck %s -check-prefix=EABI
; rdar://r6949835
@b = external global i64*
define i64 @t(i64 %a) nounwind readonly {
entry:
+;V6: ldrd r2, [r2]
+
+;V5: ldr r3, [r2]
+;V5-NEXT: ldr r2, [r2, #+4]
+
+;EABI: ldr r3, [r2]
+;EABI-NEXT: ldr r2, [r2, #+4]
+
%0 = load i64** @b, align 4
%1 = load i64* %0, align 4
%2 = mul i64 %1, %a
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/load-global.ll b/libclamav/c++/llvm/test/CodeGen/ARM/load-global.ll
index 8896ead..56a4a47 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/load-global.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/load-global.ll
@@ -1,14 +1,10 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=arm-apple-darwin -relocation-model=static | \
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | \
; RUN: not grep {L_G\$non_lazy_ptr}
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | \
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | \
; RUN: grep {L_G\$non_lazy_ptr} | count 2
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=arm-apple-darwin -relocation-model=pic | \
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | \
; RUN: grep {ldr.*pc} | count 1
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=arm-linux-gnueabi -relocation-model=pic | \
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | \
; RUN: grep {GOT} | count 1
@G = external global i32
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/load.ll b/libclamav/c++/llvm/test/CodeGen/ARM/load.ll
index 0509732..253b0e1 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/load.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/load.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm > %t
+; RUN: llc < %s -march=arm > %t
; RUN: grep ldrsb %t
; RUN: grep ldrb %t
; RUN: grep ldrsh %t
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/long-setcc.ll b/libclamav/c++/llvm/test/CodeGen/ARM/long-setcc.ll
index 4bab330..c76a5e4 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/long-setcc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/long-setcc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | grep cmp | count 1
+; RUN: llc < %s -march=arm | grep cmp | count 1
define i1 @t1(i64 %x) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/long.ll b/libclamav/c++/llvm/test/CodeGen/ARM/long.ll
index fe0ee54..2fcaac0 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/long.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/long.ll
@@ -1,13 +1,13 @@
-; RUN: llvm-as < %s | llc -march=arm -asm-verbose | \
+; RUN: llc < %s -march=arm -asm-verbose | \
; RUN: grep -- {-2147483648} | count 3
-; RUN: llvm-as < %s | llc -march=arm | grep mvn | count 3
-; RUN: llvm-as < %s | llc -march=arm | grep adds | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep adc | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep {subs } | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep sbc | count 1
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | grep mvn | count 3
+; RUN: llc < %s -march=arm | grep adds | count 1
+; RUN: llc < %s -march=arm | grep adc | count 1
+; RUN: llc < %s -march=arm | grep {subs } | count 1
+; RUN: llc < %s -march=arm | grep sbc | count 1
+; RUN: llc < %s -march=arm | \
; RUN: grep smull | count 1
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep umull | count 1
define i64 @f1() {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/long_shift.ll b/libclamav/c++/llvm/test/CodeGen/ARM/long_shift.ll
index 55d0cdc..057b5f0 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/long_shift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/long_shift.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm > %t
+; RUN: llc < %s -march=arm > %t
; RUN: grep rrx %t | count 1
; RUN: grep __ashldi3 %t
; RUN: grep __ashrdi3 %t
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/lsr-code-insertion.ll b/libclamav/c++/llvm/test/CodeGen/ARM/lsr-code-insertion.ll
index 0a92279..507ec2c 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/lsr-code-insertion.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/lsr-code-insertion.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -stats |& grep {40.*Number of machine instrs printed}
-; RUN: llvm-as < %s | llc -stats |& grep {.*Number of re-materialization}
+; RUN: llc < %s -stats |& grep {40.*Number of machine instrs printed}
+; RUN: llc < %s -stats |& grep {.*Number of re-materialization}
; This test really wants to check that the resultant "cond_true" block only
; has a single store in it, and that cond_true55 only has code to materialize
; the constant and do a store. We do *not* want something like this:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll b/libclamav/c++/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll
index 02902f2..8130019 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | grep lsl | grep -F {lsl #2\]}
+; RUN: llc < %s -march=arm | grep lsl | grep -F {lsl #2\]}
; Should use scaled addressing mode.
define void @sintzero(i32* %a) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/mem.ll b/libclamav/c++/llvm/test/CodeGen/ARM/mem.ll
index e983165..f46c7a5 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/mem.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/mem.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm | grep strb
-; RUN: llvm-as < %s | llc -march=arm | grep strh
+; RUN: llc < %s -march=arm | grep strb
+; RUN: llc < %s -march=arm | grep strh
define void @f1() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/memcpy-inline.ll b/libclamav/c++/llvm/test/CodeGen/ARM/memcpy-inline.ll
index 4bf0b4f..ed20c32 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/memcpy-inline.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/memcpy-inline.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldmia
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep stmia
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldrb
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin | grep ldrh
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldmia
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep stmia
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldrb
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldrh
%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
@src = external global %struct.x
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/memfunc.ll b/libclamav/c++/llvm/test/CodeGen/ARM/memfunc.ll
index 0b58bf6..41d5944 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/memfunc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/memfunc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define void @f() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/mls.ll b/libclamav/c++/llvm/test/CodeGen/ARM/mls.ll
index fd3a7b6..85407fa 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/mls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/mls.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6t2 | grep {mls\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1
+; RUN: llc < %s -march=arm -mattr=+v6t2 | grep {mls\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1
define i32 @f1(i32 %a, i32 %b, i32 %c) {
%tmp1 = mul i32 %a, %b
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/mul.ll b/libclamav/c++/llvm/test/CodeGen/ARM/mul.ll
index 3543b5d..466a802 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/mul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/mul.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm | grep mul | count 2
-; RUN: llvm-as < %s | llc -march=arm | grep lsl | count 2
+; RUN: llc < %s -march=arm | grep mul | count 2
+; RUN: llc < %s -march=arm | grep lsl | count 2
define i32 @f1(i32 %u) {
%tmp = mul i32 %u, %u
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/mul_const.ll b/libclamav/c++/llvm/test/CodeGen/ARM/mul_const.ll
index f5ace18..93188cd 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/mul_const.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/mul_const.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | FileCheck %s
+; RUN: llc < %s -march=arm | FileCheck %s
define i32 @t1(i32 %v) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/mulhi.ll b/libclamav/c++/llvm/test/CodeGen/ARM/mulhi.ll
index de75e96..148f291 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/mulhi.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/mulhi.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \
+; RUN: llc < %s -march=arm -mattr=+v6
+; RUN: llc < %s -march=arm -mattr=+v6 | \
; RUN: grep smmul | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep umull | count 1
+; RUN: llc < %s -march=arm | grep umull | count 1
define i32 @smulhi(i32 %x, i32 %y) {
%tmp = sext i32 %x to i64 ; <i64> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/mvn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/mvn.ll
index a7ef907..571c21a 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/mvn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/mvn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | grep mvn | count 8
+; RUN: llc < %s -march=arm | grep mvn | count 8
define i32 @f1() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/neon_arith1.ll b/libclamav/c++/llvm/test/CodeGen/ARM/neon_arith1.ll
index 18b516f..5892737 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/neon_arith1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/neon_arith1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep vadd
+; RUN: llc < %s -march=arm -mattr=+neon | grep vadd
define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/neon_ld1.ll b/libclamav/c++/llvm/test/CodeGen/ARM/neon_ld1.ll
index 8901ba1..2796dec 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/neon_ld1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/neon_ld1.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fldd | count 4
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fstd
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fmrrd
+; RUN: llc < %s -march=arm -mattr=+neon | grep fldd | count 4
+; RUN: llc < %s -march=arm -mattr=+neon | grep fstd
+; RUN: llc < %s -march=arm -mattr=+neon | grep fmrrd
define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/neon_ld2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/neon_ld2.ll
index a26904a..547bab7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/neon_ld2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/neon_ld2.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep vldmia | count 4
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep vstmia | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fmrrd | count 2
+; RUN: llc < %s -march=arm -mattr=+neon | grep vldmia | count 4
+; RUN: llc < %s -march=arm -mattr=+neon | grep vstmia | count 1
+; RUN: llc < %s -march=arm -mattr=+neon | grep fmrrd | count 2
define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/pack.ll b/libclamav/c++/llvm/test/CodeGen/ARM/pack.ll
index 151beac..1e2e7aa 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/pack.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/pack.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \
+; RUN: llc < %s -march=arm -mattr=+v6 | \
; RUN: grep pkhbt | count 5
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \
+; RUN: llc < %s -march=arm -mattr=+v6 | \
; RUN: grep pkhtb | count 4
define i32 @test1(i32 %X, i32 %Y) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/pr3502.ll b/libclamav/c++/llvm/test/CodeGen/ARM/pr3502.ll
index dee3fc4..606d969 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/pr3502.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/pr3502.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-none-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-none-linux-gnueabi
;pr3502
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/private.ll b/libclamav/c++/llvm/test/CodeGen/ARM/private.ll
index e5eeccb..03376a4 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/private.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/private.ll
@@ -1,6 +1,6 @@
; Test to make sure that the 'private' is used correctly.
;
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi > %t
+; RUN: llc < %s -mtriple=arm-linux-gnueabi > %t
; RUN: grep .Lfoo: %t
; RUN: egrep bl.*\.Lfoo %t
; RUN: grep .Lbaz: %t
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/remat.ll b/libclamav/c++/llvm/test/CodeGen/ARM/remat.ll
index 454d36b..50da997 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/remat.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/remat.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 2
+; RUN: llc < %s -mtriple=arm-apple-darwin
+; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 5
%struct.CONTENTBOX = type { i32, i32, i32, i32, i32 }
%struct.LOCBOX = type { i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret0.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret0.ll
index 792b169..5c312eb 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define i32 @test() {
ret i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg1.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg1.ll
index 48a1fda..1ab947b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define i32 @test(i32 %a1) {
ret i32 %a1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg2.ll
index a74870f..84477d0 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define i32 @test(i32 %a1, i32 %a2) {
ret i32 %a2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg3.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg3.ll
index 9210e7b..f7f9057 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define i32 @test(i32 %a1, i32 %a2, i32 %a3) {
ret i32 %a3
}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg4.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg4.ll
index a9c66e9..f7b3e4a 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define i32 @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
ret i32 %a4
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg5.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg5.ll
index 620a017..c4f9fb5 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_arg5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define i32 @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5) {
ret i32 %a5
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f32_arg2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f32_arg2.ll
index 287d92b..2bafea6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f32_arg2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f32_arg2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=+vfp2
define float @test_f32(float %a1, float %a2) {
ret float %a2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f32_arg5.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f32_arg5.ll
index 3418be9..c6ce60e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f32_arg5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f32_arg5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=+vfp2
define float @test_f32_arg5(float %a1, float %a2, float %a3, float %a4, float %a5) {
ret float %a5
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg2.ll
index 66848d5..386e85f 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=+vfp2
define double @test_f64(double %a1, double %a2) {
ret double %a2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_reg_split.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_reg_split.ll
index 626ee6f..bdb0a60 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_reg_split.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_reg_split.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mcpu=arm8 -mattr=+vfp2
+; RUN: llc < %s -march=arm -mcpu=arm8 -mattr=+vfp2
define double @test_double_arg_reg_split(i32 %a1, double %a2) {
ret double %a2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_split.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_split.ll
index b03b604..4f841a3 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_split.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_split.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=+vfp2
define double @test_double_arg_split(i64 %a1, i32 %a2, double %a3) {
ret double %a3
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_stack.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_stack.ll
index ba3ec7f..2144317 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_stack.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_f64_arg_stack.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=+vfp2
define double @test_double_arg_stack(i64 %a1, i32 %a2, i32 %a3, double %a4) {
ret double %a4
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_i128_arg2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_i128_arg2.ll
index 0fe98e6..908c34f 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_i128_arg2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_i128_arg2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=+vfp2
define i128 @test_i128(i128 %a1, i128 %a2, i128 %a3) {
ret i128 %a3
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg2.ll
index b015a96..b1a1024 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=+vfp2
define i64 @test_i64(i64 %a1, i64 %a2) {
ret i64 %a2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg3.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg3.ll
index 5dfecca..ffc1d2f 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=+vfp2
define i64 @test_i64_arg3(i64 %a1, i64 %a2, i64 %a3) {
ret i64 %a3
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg_split.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg_split.ll
index 5bd5cb2..956bce5 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg_split.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_i64_arg_split.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=+vfp2
define i64 @test_i64_arg_split(i64 %a1, i32 %a2, i64 %a3) {
ret i64 %a3
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/ret_void.ll b/libclamav/c++/llvm/test/CodeGen/ARM/ret_void.ll
index 68db8c4..2b7ae05 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/ret_void.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/ret_void.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
define void @test() {
ret void
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/rev.ll b/libclamav/c++/llvm/test/CodeGen/ARM/rev.ll
index 68f6264..1c12268 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/rev.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/rev.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | grep rev16
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | grep revsh
+; RUN: llc < %s -march=arm -mattr=+v6 | grep rev16
+; RUN: llc < %s -march=arm -mattr=+v6 | grep revsh
define i32 @test1(i32 %X) {
%tmp1 = lshr i32 %X, 8 ; <i32> [#uses=3]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/section.ll b/libclamav/c++/llvm/test/CodeGen/ARM/section.ll
index aa65845..7a566d4 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/section.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/section.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux | \
+; RUN: llc < %s -mtriple=arm-linux | \
; RUN: grep {__DTOR_END__:}
-; RUN: llvm-as < %s | llc -mtriple=arm-linux | \
+; RUN: llc < %s -mtriple=arm-linux | \
; RUN: grep {\\.section.\\.dtors,"aw",.progbits}
@__DTOR_END__ = internal global [1 x i32] zeroinitializer, section ".dtors" ; <[1 x i32]*> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/select.ll b/libclamav/c++/llvm/test/CodeGen/ARM/select.ll
index 5148a5b..d1565d1 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/select.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/select.ll
@@ -1,10 +1,10 @@
-; RUN: llvm-as < %s | llc -march=arm | grep moveq | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep movgt | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep movlt | count 3
-; RUN: llvm-as < %s | llc -march=arm | grep movle | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep movls | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep movhi | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
+; RUN: llc < %s -march=arm | grep moveq | count 1
+; RUN: llc < %s -march=arm | grep movgt | count 1
+; RUN: llc < %s -march=arm | grep movlt | count 3
+; RUN: llc < %s -march=arm | grep movle | count 1
+; RUN: llc < %s -march=arm | grep movls | count 1
+; RUN: llc < %s -march=arm | grep movhi | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | \
; RUN: grep fcpydmi | count 1
define i32 @f1(i32 %a.s) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/select_xform.ll b/libclamav/c++/llvm/test/CodeGen/ARM/select_xform.ll
index 6855e32..7fd91ce 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/select_xform.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/select_xform.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | grep mov | count 2
+; RUN: llc < %s -march=arm | grep mov | count 2
define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
%tmp1 = icmp sgt i32 %c, 10
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/shifter_operand.ll b/libclamav/c++/llvm/test/CodeGen/ARM/shifter_operand.ll
index cae1c44..2bbe9fd 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/shifter_operand.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/shifter_operand.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm | grep add | grep lsl
-; RUN: llvm-as < %s | llc -march=arm | grep bic | grep asr
+; RUN: llc < %s -march=arm | grep add | grep lsl
+; RUN: llc < %s -march=arm | grep bic | grep asr
define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/smul.ll b/libclamav/c++/llvm/test/CodeGen/ARM/smul.ll
index 7a4e488..b7ab2e7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/smul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/smul.ll
@@ -1,10 +1,10 @@
-; RUN: llvm-as < %s | llc -march=arm
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v5TE
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v5TE | \
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm -mattr=+v5TE
+; RUN: llc < %s -march=arm -mattr=+v5TE | \
; RUN: grep smulbt | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v5TE | \
+; RUN: llc < %s -march=arm -mattr=+v5TE | \
; RUN: grep smultt | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v5TE | \
+; RUN: llc < %s -march=arm -mattr=+v5TE | \
; RUN: grep smlabt | count 1
@x = weak global i16 0 ; <i16*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/spill-q.ll b/libclamav/c++/llvm/test/CodeGen/ARM/spill-q.ll
index 8775e05..f4b27a7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/spill-q.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/spill-q.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv7-elf -mattr=+neon | FileCheck %s
+; RUN: llc < %s -mtriple=armv7-elf -mattr=+neon | FileCheck %s
; PR4789
%bar = type { float, float, float }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/stack-frame.ll b/libclamav/c++/llvm/test/CodeGen/ARM/stack-frame.ll
index c3dd65a..1dd57dd 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/stack-frame.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/stack-frame.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm
-; RUN: llvm-as < %s | llc -march=arm | grep add | count 1
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | grep add | count 1
define void @f1() {
%c = alloca i8, align 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/stm.ll b/libclamav/c++/llvm/test/CodeGen/ARM/stm.ll
index ed5e4c5..22a7ecb 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/stm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/stm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | grep stm | count 2
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | grep stm | count 2
@"\01LC" = internal constant [32 x i8] c"Boolean Not: %d %d %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[32 x i8]*> [#uses=1]
@"\01LC1" = internal constant [26 x i8] c"Bitwise Not: %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[26 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/str_post.ll b/libclamav/c++/llvm/test/CodeGen/ARM/str_post.ll
index ba81380..801b9ce 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/str_post.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/str_post.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep {strh .*\\\[.*\], #-4} | count 1
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep {str .*\\\[.*\],} | count 1
define i16 @test1(i32* %X, i16* %A) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/str_pre-2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/str_pre-2.ll
index e9f1945..f8d3df2 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/str_pre-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/str_pre-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {str.*\\!}
-; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #+4}
+; RUN: llc < %s -mtriple=arm-linux-gnu | grep {str.*\\!}
+; RUN: llc < %s -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #+4}
@b = external global i64*
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/str_pre.ll b/libclamav/c++/llvm/test/CodeGen/ARM/str_pre.ll
index c02663f..e56e3f2 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/str_pre.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/str_pre.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep {str.*\\!} | count 2
define void @test1(i32* %X, i32* %A, i32** %dest) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/str_trunc.ll b/libclamav/c++/llvm/test/CodeGen/ARM/str_trunc.ll
index 77c66ec..2f1166b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/str_trunc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/str_trunc.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep strb | count 1
-; RUN: llvm-as < %s | llc -march=arm | \
+; RUN: llc < %s -march=arm | \
; RUN: grep strh | count 1
define void @test1(i32 %v, i16* %ptr) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/sxt_rot.ll b/libclamav/c++/llvm/test/CodeGen/ARM/sxt_rot.ll
index e9f302c..4752f17 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/sxt_rot.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/sxt_rot.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \
+; RUN: llc < %s -march=arm -mattr=+v6 | \
; RUN: grep sxtb | count 2
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \
+; RUN: llc < %s -march=arm -mattr=+v6 | \
; RUN: grep sxtb | grep ror | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \
+; RUN: llc < %s -march=arm -mattr=+v6 | \
; RUN: grep sxtab | count 1
define i32 @test0(i8 %A) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/t2-imm.ll b/libclamav/c++/llvm/test/CodeGen/ARM/t2-imm.ll
new file mode 100644
index 0000000..8b619bf
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/t2-imm.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s
+
+define i32 @f6(i32 %a) {
+; CHECK:f6
+; CHECK: movw r0, #1123
+; CHECK: movt r0, #1000
+ %tmp = add i32 0, 65537123
+ ret i32 %tmp
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/thread_pointer.ll b/libclamav/c++/llvm/test/CodeGen/ARM/thread_pointer.ll
index 6476b48..3143387 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/thread_pointer.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/thread_pointer.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
; RUN: grep {__aeabi_read_tp}
define i8* @test() {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/tls1.ll b/libclamav/c++/llvm/test/CodeGen/ARM/tls1.ll
index 6866a42..1087094 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/tls1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/tls1.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
; RUN: grep {i(tpoff)}
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
; RUN: grep {__aeabi_read_tp}
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi \
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \
; RUN: -relocation-model=pic | grep {__tls_get_addr}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/tls2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/tls2.ll
index 90e3bcf..3284720 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/tls2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/tls2.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
; RUN: grep {i(gottpoff)}
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
; RUN: grep {ldr r., \[pc, r.\]}
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi \
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \
; RUN: -relocation-model=pic | grep {__tls_get_addr}
@i = external thread_local global i32 ; <i32*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/tls3.ll b/libclamav/c++/llvm/test/CodeGen/ARM/tls3.ll
index df2913b..df7a4ca 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/tls3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/tls3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
; RUN: grep {tbss}
%struct.anon = type { i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/trunc_ldr.ll b/libclamav/c++/llvm/test/CodeGen/ARM/trunc_ldr.ll
index 6111ec9..3033c2b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/trunc_ldr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/trunc_ldr.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm | grep ldrb.*7 | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep ldrsb.*7 | count 1
+; RUN: llc < %s -march=arm | grep ldrb.*7 | count 1
+; RUN: llc < %s -march=arm | grep ldrsb.*7 | count 1
%struct.A = type { i8, i8, i8, i8, i16, i8, i8, %struct.B** }
%struct.B = type { float, float, i32, i32, i32, [0 x i8] }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll b/libclamav/c++/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll
index 0e85fb6..2da08b6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm | not grep orr
-; RUN: llvm-as < %s | llc -march=arm | not grep mov
+; RUN: llc < %s -march=arm | not grep orr
+; RUN: llc < %s -march=arm | not grep mov
define void @bar(i8* %P, i16* %Q) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/tst_teq.ll b/libclamav/c++/llvm/test/CodeGen/ARM/tst_teq.ll
index bdeee3f..c83111e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/tst_teq.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/tst_teq.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm | grep tst
-; RUN: llvm-as < %s | llc -march=arm | grep teq
+; RUN: llc < %s -march=arm | grep tst
+; RUN: llc < %s -march=arm | grep teq
define i32 @f(i32 %a) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/uint64tof64.ll b/libclamav/c++/llvm/test/CodeGen/ARM/uint64tof64.ll
index 055c3c3..32eb225 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/uint64tof64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/uint64tof64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+vfp2
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.__sFILEX = type opaque
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/unaligned_load_store.ll b/libclamav/c++/llvm/test/CodeGen/ARM/unaligned_load_store.ll
index 6fd9c2a..fcaa2b3 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/unaligned_load_store.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/unaligned_load_store.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm | FileCheck %s -check-prefix=GENERIC
-; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=DARWIN_V6
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v7a | FileCheck %s -check-prefix=V7
+; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=GENERIC
+; RUN: llc < %s -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=DARWIN_V6
+; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s -check-prefix=V7
; rdar://7113725
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/unord.ll b/libclamav/c++/llvm/test/CodeGen/ARM/unord.ll
index 149afc4..bd28034 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/unord.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/unord.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm | grep movne | count 1
-; RUN: llvm-as < %s | llc -march=arm | grep moveq | count 1
+; RUN: llc < %s -march=arm | grep movne | count 1
+; RUN: llc < %s -march=arm | grep moveq | count 1
define i32 @f1(float %X, float %Y) {
%tmp = fcmp uno float %X, %Y
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/uxt_rot.ll b/libclamav/c++/llvm/test/CodeGen/ARM/uxt_rot.ll
index 09c74eb..6307795 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/uxt_rot.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/uxt_rot.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | grep uxtb | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | grep uxtab | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | grep uxth | count 1
+; RUN: llc < %s -march=arm -mattr=+v6 | grep uxtb | count 1
+; RUN: llc < %s -march=arm -mattr=+v6 | grep uxtab | count 1
+; RUN: llc < %s -march=arm -mattr=+v6 | grep uxth | count 1
define i8 @test1(i32 %A.u) zeroext {
%B.u = trunc i32 %A.u to i8
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/uxtb.ll b/libclamav/c++/llvm/test/CodeGen/ARM/uxtb.ll
index 73e918b..9d6e4bd 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/uxtb.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/uxtb.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin | \
+; RUN: llc < %s -mtriple=armv6-apple-darwin | \
; RUN: grep uxt | count 10
define i32 @test1(i32 %x) {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vaba.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vaba.ll
index 8569a38..5d58e29 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vaba.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vaba.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
;CHECK: vabas8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vabal.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vabal.ll
index 93af951..89efd5b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vabal.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vabal.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
;CHECK: vabals8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vabd.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vabd.ll
index e764840..db762bd 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vabd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vabd.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: vabds8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vabdl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vabdl.ll
index 5a5f9d2..23840f7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vabdl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vabdl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: vabdls8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vabs.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vabs.ll
index 1195f08..f1aafed 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vabs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vabs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
;CHECK: vabss8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vacge.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vacge.ll
index 7e2519a..b178446 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vacge.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vacge.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
;CHECK: vacgef32:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vacgt.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vacgt.ll
index 2a9c7ae..fd01163 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vacgt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vacgt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
;CHECK: vacgtf32:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vadd.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vadd.ll
index cebf27c..9d2deb9 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vadd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vadd.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: vaddi8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vaddhn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vaddhn.ll
index ee36646..aba5712 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vaddhn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vaddhn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
;CHECK: vaddhni16:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vaddl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vaddl.ll
index 21c9600..3a31b95 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vaddl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vaddl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: vaddls8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vaddw.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vaddw.ll
index 3e9a8de..6d0459e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vaddw.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vaddw.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
;CHECK: vaddws8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vand.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vand.ll
index d61e435..653a70b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vand.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vand.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: v_andi8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vargs.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vargs.ll
index 4bf79c0..5f3536c 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vargs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vargs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llc < %s -march=arm
@str = internal constant [43 x i8] c"Hello World %d %d %d %d %d %d %d %d %d %d\0A\00" ; <[43 x i8]*> [#uses=1]
define i32 @main() {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vargs_align.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vargs_align.ll
index 1f2f05b..e4ef9e3 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vargs_align.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vargs_align.ll
@@ -1,7 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi | \
-; RUN: grep {add sp, sp, #16} | count 1
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnu | \
-; RUN: grep {add sp, sp, #12} | count 2
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=EABI
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | FileCheck %s -check-prefix=OABI
define i32 @f(i32 %a, ...) {
entry:
@@ -18,4 +16,8 @@ entry:
return: ; preds = %entry
%retval2 = load i32* %retval ; <i32> [#uses=1]
ret i32 %retval2
+; EABI: add sp, sp, #12
+; EABI: add sp, sp, #16
+; OABI: add sp, sp, #12
+; OABI: add sp, sp, #12
}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vbic.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vbic.ll
index 591f491..2f79232 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vbic.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vbic.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: v_bici8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vbsl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vbsl.ll
index bf81304..9f3bb4e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vbsl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vbsl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
;CHECK: v_bsli8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vceq.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vceq.ll
index 6e545b7..e478751 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vceq.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vceq.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: vceqi8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vcge.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vcge.ll
index 6017d41..b8debd9 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vcge.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vcge.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: vcges8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vcgt.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vcgt.ll
index 47115ca..eae29b2 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vcgt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vcgt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: vcgts8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vcls.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vcls.ll
index 25b94db..43bd3f9 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vcls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vcls.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
;CHECK: vclss8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vclz.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vclz.ll
index cd9daa5..ec439db 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vclz.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vclz.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
;CHECK: vclz8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vcnt.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vcnt.ll
index bf98eef..7e045ee 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vcnt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vcnt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
;CHECK: vcnt8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vcombine.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vcombine.ll
index 2a62ba8..e673305 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vcombine.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vcombine.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon
+; RUN: llc < %s -march=arm -mattr=+neon
define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
%tmp1 = load <8 x i8>* %A
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vcvt.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vcvt.ll
index b89b82b..795caa4 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vcvt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vcvt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
;CHECK: vcvt_f32tos32:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vcvt_n.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vcvt_n.ll
index ac86b73..0ee9976 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vcvt_n.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vcvt_n.ll
@@ -1,28 +1,32 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep {vcvt\\.s32\\.f32} %t | count 2
-; RUN: grep {vcvt\\.u32\\.f32} %t | count 2
-; RUN: grep {vcvt\\.f32\\.s32} %t | count 2
-; RUN: grep {vcvt\\.f32\\.u32} %t | count 2
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
+;CHECK: vcvt_f32tos32:
+;CHECK: vcvt.s32.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
ret <2 x i32> %tmp2
}
define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
+;CHECK: vcvt_f32tou32:
+;CHECK: vcvt.u32.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
ret <2 x i32> %tmp2
}
define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
+;CHECK: vcvt_s32tof32:
+;CHECK: vcvt.f32.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
ret <2 x float> %tmp2
}
define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
+;CHECK: vcvt_u32tof32:
+;CHECK: vcvt.f32.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
ret <2 x float> %tmp2
@@ -34,24 +38,32 @@ declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwi
declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
+;CHECK: vcvtQ_f32tos32:
+;CHECK: vcvt.s32.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
ret <4 x i32> %tmp2
}
define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
+;CHECK: vcvtQ_f32tou32:
+;CHECK: vcvt.u32.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
ret <4 x i32> %tmp2
}
define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
+;CHECK: vcvtQ_s32tof32:
+;CHECK: vcvt.f32.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
ret <4 x float> %tmp2
}
define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
+;CHECK: vcvtQ_u32tof32:
+;CHECK: vcvt.f32.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
ret <4 x float> %tmp2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vdup.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vdup.ll
index 37f8dcb..cee24c8 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vdup.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vdup.ll
@@ -1,9 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep vdup.8 %t | count 4
-; RUN: grep vdup.16 %t | count 4
-; RUN: grep vdup.32 %t | count 10
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @v_dup8(i8 %A) nounwind {
+;CHECK: v_dup8:
+;CHECK: vdup.8
%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
%tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
%tmp3 = insertelement <8 x i8> %tmp2, i8 %A, i32 2
@@ -16,6 +15,8 @@ define <8 x i8> @v_dup8(i8 %A) nounwind {
}
define <4 x i16> @v_dup16(i16 %A) nounwind {
+;CHECK: v_dup16:
+;CHECK: vdup.16
%tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
%tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
%tmp3 = insertelement <4 x i16> %tmp2, i16 %A, i32 2
@@ -24,18 +25,24 @@ define <4 x i16> @v_dup16(i16 %A) nounwind {
}
define <2 x i32> @v_dup32(i32 %A) nounwind {
+;CHECK: v_dup32:
+;CHECK: vdup.32
%tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
%tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
ret <2 x i32> %tmp2
}
define <2 x float> @v_dupfloat(float %A) nounwind {
+;CHECK: v_dupfloat:
+;CHECK: vdup.32
%tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0
%tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1
ret <2 x float> %tmp2
}
define <16 x i8> @v_dupQ8(i8 %A) nounwind {
+;CHECK: v_dupQ8:
+;CHECK: vdup.8
%tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
%tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
%tmp3 = insertelement <16 x i8> %tmp2, i8 %A, i32 2
@@ -56,6 +63,8 @@ define <16 x i8> @v_dupQ8(i8 %A) nounwind {
}
define <8 x i16> @v_dupQ16(i16 %A) nounwind {
+;CHECK: v_dupQ16:
+;CHECK: vdup.16
%tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
%tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
%tmp3 = insertelement <8 x i16> %tmp2, i16 %A, i32 2
@@ -68,6 +77,8 @@ define <8 x i16> @v_dupQ16(i16 %A) nounwind {
}
define <4 x i32> @v_dupQ32(i32 %A) nounwind {
+;CHECK: v_dupQ32:
+;CHECK: vdup.32
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
%tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
%tmp3 = insertelement <4 x i32> %tmp2, i32 %A, i32 2
@@ -76,6 +87,8 @@ define <4 x i32> @v_dupQ32(i32 %A) nounwind {
}
define <4 x float> @v_dupQfloat(float %A) nounwind {
+;CHECK: v_dupQfloat:
+;CHECK: vdup.32
%tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0
%tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1
%tmp3 = insertelement <4 x float> %tmp2, float %A, i32 2
@@ -86,54 +99,72 @@ define <4 x float> @v_dupQfloat(float %A) nounwind {
; Check to make sure it works with shuffles, too.
define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
+;CHECK: v_shuffledup8:
+;CHECK: vdup.8
%tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
ret <8 x i8> %tmp2
}
define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
+;CHECK: v_shuffledup16:
+;CHECK: vdup.16
%tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
ret <4 x i16> %tmp2
}
define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
+;CHECK: v_shuffledup32:
+;CHECK: vdup.32
%tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
ret <2 x i32> %tmp2
}
define <2 x float> @v_shuffledupfloat(float %A) nounwind {
+;CHECK: v_shuffledupfloat:
+;CHECK: vdup.32
%tmp1 = insertelement <2 x float> undef, float %A, i32 0
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
ret <2 x float> %tmp2
}
define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
+;CHECK: v_shuffledupQ8:
+;CHECK: vdup.8
%tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer
ret <16 x i8> %tmp2
}
define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
+;CHECK: v_shuffledupQ16:
+;CHECK: vdup.16
%tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer
ret <8 x i16> %tmp2
}
define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
+;CHECK: v_shuffledupQ32:
+;CHECK: vdup.32
%tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %tmp2
}
define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
+;CHECK: v_shuffledupQfloat:
+;CHECK: vdup.32
%tmp1 = insertelement <4 x float> undef, float %A, i32 0
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
ret <4 x float> %tmp2
}
define <2 x float> @v_shuffledupfloat2(float* %A) nounwind {
+;CHECK: v_shuffledupfloat2:
+;CHECK: vdup.32
%tmp0 = load float* %A
%tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
@@ -141,6 +172,8 @@ define <2 x float> @v_shuffledupfloat2(float* %A) nounwind {
}
define <4 x float> @v_shuffledupQfloat2(float* %A) nounwind {
+;CHECK: v_shuffledupQfloat2:
+;CHECK: vdup.32
%tmp0 = load float* %A
%tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vdup_lane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vdup_lane.ll
index adadc9f..313260a 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vdup_lane.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vdup_lane.ll
@@ -1,52 +1,89 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep vdup.8 %t | count 2
-; RUN: grep vdup.16 %t | count 2
-; RUN: grep vdup.32 %t | count 4
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
+;CHECK: vduplane8:
+;CHECK: vdup.8
%tmp1 = load <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
ret <8 x i8> %tmp2
}
define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
+;CHECK: vduplane16:
+;CHECK: vdup.16
%tmp1 = load <4 x i16>* %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
ret <4 x i16> %tmp2
}
define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
+;CHECK: vduplane32:
+;CHECK: vdup.32
%tmp1 = load <2 x i32>* %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
ret <2 x i32> %tmp2
}
define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
+;CHECK: vduplanefloat:
+;CHECK: vdup.32
%tmp1 = load <2 x float>* %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
ret <2 x float> %tmp2
}
define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
+;CHECK: vduplaneQ8:
+;CHECK: vdup.8
%tmp1 = load <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
ret <16 x i8> %tmp2
}
define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
+;CHECK: vduplaneQ16:
+;CHECK: vdup.16
%tmp1 = load <4 x i16>* %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
ret <8 x i16> %tmp2
}
define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
+;CHECK: vduplaneQ32:
+;CHECK: vdup.32
%tmp1 = load <2 x i32>* %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
ret <4 x i32> %tmp2
}
define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
+;CHECK: vduplaneQfloat:
+;CHECK: vdup.32
%tmp1 = load <2 x float>* %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
ret <4 x float> %tmp2
}
+
+define arm_apcscc <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone {
+entry:
+ %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
+ ret <2 x i64> %0
+}
+
+define arm_apcscc <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone {
+entry:
+ %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+ ret <2 x i64> %0
+}
+
+define arm_apcscc <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone {
+entry:
+ %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 1, i32 1>
+ ret <2 x double> %0
+}
+
+define arm_apcscc <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone {
+entry:
+ %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0>
+ ret <2 x double> %0
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/veor.ll b/libclamav/c++/llvm/test/CodeGen/ARM/veor.ll
index 47a5f3f..febceb4 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/veor.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/veor.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep veor %t | count 8
-; Note: function names do not include "veor" to allow simple grep for opcodes
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: v_eori8:
+;CHECK: veor
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
%tmp3 = xor <8 x i8> %tmp1, %tmp2
@@ -10,6 +10,8 @@ define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
}
define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: v_eori16:
+;CHECK: veor
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
%tmp3 = xor <4 x i16> %tmp1, %tmp2
@@ -17,6 +19,8 @@ define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
}
define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: v_eori32:
+;CHECK: veor
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
%tmp3 = xor <2 x i32> %tmp1, %tmp2
@@ -24,6 +28,8 @@ define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
}
define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: v_eori64:
+;CHECK: veor
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
%tmp3 = xor <1 x i64> %tmp1, %tmp2
@@ -31,6 +37,8 @@ define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
}
define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: v_eorQi8:
+;CHECK: veor
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
%tmp3 = xor <16 x i8> %tmp1, %tmp2
@@ -38,6 +46,8 @@ define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
}
define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: v_eorQi16:
+;CHECK: veor
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
%tmp3 = xor <8 x i16> %tmp1, %tmp2
@@ -45,6 +55,8 @@ define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
}
define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: v_eorQi32:
+;CHECK: veor
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
%tmp3 = xor <4 x i32> %tmp1, %tmp2
@@ -52,6 +64,8 @@ define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
}
define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: v_eorQi64:
+;CHECK: veor
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
%tmp3 = xor <2 x i64> %tmp1, %tmp2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vext.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vext.ll
index 46dd6bd..20d953b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vext.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vext.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define arm_apcscc <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK: test_vextd:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vfcmp.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vfcmp.ll
index 690b0ee..6946d02 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vfcmp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vfcmp.ll
@@ -1,14 +1,12 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep {vceq\\.f32} %t | count 1
-; RUN: grep {vcgt\\.f32} %t | count 9
-; RUN: grep {vcge\\.f32} %t | count 5
-; RUN: grep vorr %t | count 4
-; RUN: grep vmvn %t | count 7
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
; This tests fcmp operations that do not map directly to NEON instructions.
; une is implemented with VCEQ/VMVN
define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcunef32:
+;CHECK: vceq.f32
+;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
%tmp3 = fcmp une <2 x float> %tmp1, %tmp2
@@ -18,6 +16,8 @@ define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
; olt is implemented with VCGT
define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcoltf32:
+;CHECK: vcgt.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
%tmp3 = fcmp olt <2 x float> %tmp1, %tmp2
@@ -27,6 +27,8 @@ define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
; ole is implemented with VCGE
define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcolef32:
+;CHECK: vcge.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
%tmp3 = fcmp ole <2 x float> %tmp1, %tmp2
@@ -36,6 +38,9 @@ define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
; uge is implemented with VCGT/VMVN
define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcugef32:
+;CHECK: vcgt.f32
+;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
%tmp3 = fcmp uge <2 x float> %tmp1, %tmp2
@@ -45,6 +50,9 @@ define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
; ule is implemented with VCGT/VMVN
define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vculef32:
+;CHECK: vcgt.f32
+;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
%tmp3 = fcmp ule <2 x float> %tmp1, %tmp2
@@ -54,6 +62,9 @@ define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
; ugt is implemented with VCGE/VMVN
define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcugtf32:
+;CHECK: vcge.f32
+;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
%tmp3 = fcmp ugt <2 x float> %tmp1, %tmp2
@@ -63,6 +74,9 @@ define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
; ult is implemented with VCGE/VMVN
define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcultf32:
+;CHECK: vcge.f32
+;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
%tmp3 = fcmp ult <2 x float> %tmp1, %tmp2
@@ -72,6 +86,11 @@ define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
; ueq is implemented with VCGT/VCGT/VORR/VMVN
define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcueqf32:
+;CHECK: vcgt.f32
+;CHECK-NEXT: vcgt.f32
+;CHECK-NEXT: vorr
+;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
%tmp3 = fcmp ueq <2 x float> %tmp1, %tmp2
@@ -81,6 +100,10 @@ define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
; one is implemented with VCGT/VCGT/VORR
define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vconef32:
+;CHECK: vcgt.f32
+;CHECK-NEXT: vcgt.f32
+;CHECK-NEXT: vorr
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
%tmp3 = fcmp one <2 x float> %tmp1, %tmp2
@@ -90,6 +113,11 @@ define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
; uno is implemented with VCGT/VCGE/VORR/VMVN
define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcunof32:
+;CHECK: vcge.f32
+;CHECK-NEXT: vcgt.f32
+;CHECK-NEXT: vorr
+;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
%tmp3 = fcmp uno <2 x float> %tmp1, %tmp2
@@ -99,6 +127,10 @@ define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
; ord is implemented with VCGT/VCGE/VORR
define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcordf32:
+;CHECK: vcge.f32
+;CHECK-NEXT: vcgt.f32
+;CHECK-NEXT: vorr
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
%tmp3 = fcmp ord <2 x float> %tmp1, %tmp2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vfp.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vfp.ll
index f58da44..50000e3 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vfp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vfp.ll
@@ -1,19 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN: grep fabs | count 2
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN: grep fmscs | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN: grep fcvt | count 2
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN: grep fuito | count 2
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN: grep fto.i | count 4
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN: grep bmi | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN: grep bgt | count 1
-; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | \
-; RUN: grep fcmpezs | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define void @test(float* %P, double* %D) {
%A = load float* %P ; <float> [#uses=1]
@@ -28,16 +13,20 @@ declare float @fabsf(float)
declare double @fabs(double)
define void @test_abs(float* %P, double* %D) {
+;CHECK: test_abs:
%a = load float* %P ; <float> [#uses=1]
+;CHECK: fabss
%b = call float @fabsf( float %a ) ; <float> [#uses=1]
store float %b, float* %P
%A = load double* %D ; <double> [#uses=1]
+;CHECK: fabsd
%B = call double @fabs( double %A ) ; <double> [#uses=1]
store double %B, double* %D
ret void
}
define void @test_add(float* %P, double* %D) {
+;CHECK: test_add:
%a = load float* %P ; <float> [#uses=2]
%b = fadd float %a, %a ; <float> [#uses=1]
store float %b, float* %P
@@ -48,9 +37,12 @@ define void @test_add(float* %P, double* %D) {
}
define void @test_ext_round(float* %P, double* %D) {
+;CHECK: test_ext_round:
%a = load float* %P ; <float> [#uses=1]
+;CHECK: fcvtds
%b = fpext float %a to double ; <double> [#uses=1]
%A = load double* %D ; <double> [#uses=1]
+;CHECK: fcvtsd
%B = fptrunc double %A to float ; <float> [#uses=1]
store double %b, double* %D
store float %B, float* %P
@@ -58,9 +50,11 @@ define void @test_ext_round(float* %P, double* %D) {
}
define void @test_fma(float* %P1, float* %P2, float* %P3) {
+;CHECK: test_fma:
%a1 = load float* %P1 ; <float> [#uses=1]
%a2 = load float* %P2 ; <float> [#uses=1]
%a3 = load float* %P3 ; <float> [#uses=1]
+;CHECK: fmscs
%X = fmul float %a1, %a2 ; <float> [#uses=1]
%Y = fsub float %X, %a3 ; <float> [#uses=1]
store float %Y, float* %P1
@@ -68,42 +62,55 @@ define void @test_fma(float* %P1, float* %P2, float* %P3) {
}
define i32 @test_ftoi(float* %P1) {
+;CHECK: test_ftoi:
%a1 = load float* %P1 ; <float> [#uses=1]
+;CHECK: ftosizs
%b1 = fptosi float %a1 to i32 ; <i32> [#uses=1]
ret i32 %b1
}
define i32 @test_ftou(float* %P1) {
+;CHECK: test_ftou:
%a1 = load float* %P1 ; <float> [#uses=1]
+;CHECK: ftouizs
%b1 = fptoui float %a1 to i32 ; <i32> [#uses=1]
ret i32 %b1
}
define i32 @test_dtoi(double* %P1) {
+;CHECK: test_dtoi:
%a1 = load double* %P1 ; <double> [#uses=1]
+;CHECK: ftosizd
%b1 = fptosi double %a1 to i32 ; <i32> [#uses=1]
ret i32 %b1
}
define i32 @test_dtou(double* %P1) {
+;CHECK: test_dtou:
%a1 = load double* %P1 ; <double> [#uses=1]
+;CHECK: ftouizd
%b1 = fptoui double %a1 to i32 ; <i32> [#uses=1]
ret i32 %b1
}
define void @test_utod(double* %P1, i32 %X) {
+;CHECK: test_utod:
+;CHECK: fuitod
%b1 = uitofp i32 %X to double ; <double> [#uses=1]
store double %b1, double* %P1
ret void
}
define void @test_utod2(double* %P1, i8 %X) {
+;CHECK: test_utod2:
+;CHECK: fuitod
%b1 = uitofp i8 %X to double ; <double> [#uses=1]
store double %b1, double* %P1
ret void
}
define void @test_cmp(float* %glob, i32 %X) {
+;CHECK: test_cmp:
entry:
%tmp = load float* %glob ; <float> [#uses=2]
%tmp3 = getelementptr float* %glob, i32 2 ; <float*> [#uses=1]
@@ -111,6 +118,8 @@ entry:
%tmp.upgrd.1 = fcmp oeq float %tmp, %tmp4 ; <i1> [#uses=1]
%tmp5 = fcmp uno float %tmp, %tmp4 ; <i1> [#uses=1]
%tmp6 = or i1 %tmp.upgrd.1, %tmp5 ; <i1> [#uses=1]
+;CHECK: bmi
+;CHECK-NEXT: bgt
br i1 %tmp6, label %cond_true, label %cond_false
cond_true: ; preds = %entry
@@ -129,8 +138,10 @@ declare i32 @bar(...)
declare i32 @baz(...)
define void @test_cmpfp0(float* %glob, i32 %X) {
+;CHECK: test_cmpfp0:
entry:
%tmp = load float* %glob ; <float> [#uses=1]
+;CHECK: fcmpezs
%tmp.upgrd.3 = fcmp ogt float %tmp, 0.000000e+00 ; <i1> [#uses=1]
br i1 %tmp.upgrd.3, label %cond_true, label %cond_false
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vget_lane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vget_lane.ll
index a361ba2..b4f093c 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vget_lane.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vget_lane.ll
@@ -1,11 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep {vmov\\.s8} %t | count 2
-; RUN: grep {vmov\\.s16} %t | count 2
-; RUN: grep {vmov\\.u8} %t | count 2
-; RUN: grep {vmov\\.u16} %t | count 2
-; RUN: grep {vmov\\.32} %t | count 2
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
+;CHECK: vget_lanes8:
+;CHECK: vmov.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = extractelement <8 x i8> %tmp1, i32 1
%tmp3 = sext i8 %tmp2 to i32
@@ -13,6 +10,8 @@ define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
}
define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
+;CHECK: vget_lanes16:
+;CHECK: vmov.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = extractelement <4 x i16> %tmp1, i32 1
%tmp3 = sext i16 %tmp2 to i32
@@ -20,6 +19,8 @@ define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
}
define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
+;CHECK: vget_laneu8:
+;CHECK: vmov.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = extractelement <8 x i8> %tmp1, i32 1
%tmp3 = zext i8 %tmp2 to i32
@@ -27,6 +28,8 @@ define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
}
define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
+;CHECK: vget_laneu16:
+;CHECK: vmov.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = extractelement <4 x i16> %tmp1, i32 1
%tmp3 = zext i16 %tmp2 to i32
@@ -35,6 +38,8 @@ define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
; Do a vector add to keep the extraction from being done directly from memory.
define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
+;CHECK: vget_lanei32:
+;CHECK: vmov.32
%tmp1 = load <2 x i32>* %A
%tmp2 = add <2 x i32> %tmp1, %tmp1
%tmp3 = extractelement <2 x i32> %tmp2, i32 1
@@ -42,6 +47,8 @@ define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
}
define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
+;CHECK: vgetQ_lanes8:
+;CHECK: vmov.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = extractelement <16 x i8> %tmp1, i32 1
%tmp3 = sext i8 %tmp2 to i32
@@ -49,6 +56,8 @@ define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
}
define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
+;CHECK: vgetQ_lanes16:
+;CHECK: vmov.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = extractelement <8 x i16> %tmp1, i32 1
%tmp3 = sext i16 %tmp2 to i32
@@ -56,6 +65,8 @@ define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
}
define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
+;CHECK: vgetQ_laneu8:
+;CHECK: vmov.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = extractelement <16 x i8> %tmp1, i32 1
%tmp3 = zext i8 %tmp2 to i32
@@ -63,6 +74,8 @@ define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
}
define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
+;CHECK: vgetQ_laneu16:
+;CHECK: vmov.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = extractelement <8 x i16> %tmp1, i32 1
%tmp3 = zext i16 %tmp2 to i32
@@ -71,6 +84,8 @@ define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
; Do a vector add to keep the extraction from being done directly from memory.
define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
+;CHECK: vgetQ_lanei32:
+;CHECK: vmov.32
%tmp1 = load <4 x i32>* %A
%tmp2 = add <4 x i32> %tmp1, %tmp1
%tmp3 = extractelement <4 x i32> %tmp2, i32 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vget_lane2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vget_lane2.ll
index e8aa82a..1981bf9 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vget_lane2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vget_lane2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mattr=+neon | FileCheck %s
+; RUN: llc < %s -mattr=+neon | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
target triple = "thumbv7-elf"
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vhadd.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vhadd.ll
index 5e7503d..d767097 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vhadd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vhadd.ll
@@ -1,12 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep {vhadd\\.s8} %t | count 2
-; RUN: grep {vhadd\\.s16} %t | count 2
-; RUN: grep {vhadd\\.s32} %t | count 2
-; RUN: grep {vhadd\\.u8} %t | count 2
-; RUN: grep {vhadd\\.u16} %t | count 2
-; RUN: grep {vhadd\\.u32} %t | count 2
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vhadds8:
+;CHECK: vhadd.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
@@ -14,6 +10,8 @@ define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
}
define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vhadds16:
+;CHECK: vhadd.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -21,6 +19,8 @@ define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
}
define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vhadds32:
+;CHECK: vhadd.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -28,6 +28,8 @@ define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
}
define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vhaddu8:
+;CHECK: vhadd.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
@@ -35,6 +37,8 @@ define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
}
define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vhaddu16:
+;CHECK: vhadd.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -42,6 +46,8 @@ define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
}
define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vhaddu32:
+;CHECK: vhadd.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -49,6 +55,8 @@ define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
}
define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vhaddQs8:
+;CHECK: vhadd.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
@@ -56,6 +64,8 @@ define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
}
define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vhaddQs16:
+;CHECK: vhadd.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
@@ -63,6 +73,8 @@ define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
}
define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vhaddQs32:
+;CHECK: vhadd.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
@@ -70,6 +82,8 @@ define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
}
define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vhaddQu8:
+;CHECK: vhadd.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
@@ -77,6 +91,8 @@ define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
}
define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vhaddQu16:
+;CHECK: vhadd.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
@@ -84,6 +100,8 @@ define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
}
define <4 x i32> @vhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vhaddQu32:
+;CHECK: vhadd.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vhsub.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vhsub.ll
index 32a66e5..0f0d027 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vhsub.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vhsub.ll
@@ -1,12 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
-; RUN: grep {vhsub\\.s8} %t | count 2
-; RUN: grep {vhsub\\.s16} %t | count 2
-; RUN: grep {vhsub\\.s32} %t | count 2
-; RUN: grep {vhsub\\.u8} %t | count 2
-; RUN: grep {vhsub\\.u16} %t | count 2
-; RUN: grep {vhsub\\.u32} %t | count 2
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vhsubs8:
+;CHECK: vhsub.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
@@ -14,6 +10,8 @@ define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
}
define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vhsubs16:
+;CHECK: vhsub.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -21,6 +19,8 @@ define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
}
define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vhsubs32:
+;CHECK: vhsub.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -28,6 +28,8 @@ define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
}
define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vhsubu8:
+;CHECK: vhsub.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
@@ -35,6 +37,8 @@ define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
}
define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vhsubu16:
+;CHECK: vhsub.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
%tmp3 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -42,6 +46,8 @@ define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
}
define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vhsubu32:
+;CHECK: vhsub.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
%tmp3 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -49,6 +55,8 @@ define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
}
define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vhsubQs8:
+;CHECK: vhsub.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
@@ -56,6 +64,8 @@ define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
}
define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vhsubQs16:
+;CHECK: vhsub.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
@@ -63,6 +73,8 @@ define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
}
define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vhsubQs32:
+;CHECK: vhsub.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
@@ -70,6 +82,8 @@ define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
}
define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vhsubQu8:
+;CHECK: vhsub.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
%tmp3 = call <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
@@ -77,6 +91,8 @@ define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
}
define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vhsubQu16:
+;CHECK: vhsub.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
%tmp3 = call <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
@@ -84,6 +100,8 @@ define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
}
define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vhsubQu32:
+;CHECK: vhsub.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
%tmp3 = call <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vicmp.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vicmp.ll
index 2cb3eba..fb0f4cc 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vicmp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vicmp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vceq\\.i8} %t | count 2
; RUN: grep {vceq\\.i16} %t | count 2
; RUN: grep {vceq\\.i32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vld1.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vld1.ll
index 81f1bde..f5383aa 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vld1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vld1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vld1i8(i8* %A) nounwind {
;CHECK: vld1i8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vld2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vld2.ll
index 168b62b..36e54bd 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vld2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vld2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vld3.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vld3.ll
index 5e528c0..aa38bb0 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vld3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vld3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
%struct.__builtin_neon_v8qi3 = type { <8 x i8>, <8 x i8>, <8 x i8> }
%struct.__builtin_neon_v4hi3 = type { <4 x i16>, <4 x i16>, <4 x i16> }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vld4.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vld4.ll
index 48125be..4d59a88 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vld4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vld4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
%struct.__builtin_neon_v8qi4 = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
%struct.__builtin_neon_v4hi4 = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vldlane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vldlane.ll
new file mode 100644
index 0000000..01334a6
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vldlane.ll
@@ -0,0 +1,187 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
+%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
+%struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
+%struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
+
+define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vld2lanei8:
+;CHECK: vld2.8
+ %tmp1 = load <8 x i8>* %B
+ %tmp2 = call %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v8qi2 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp2, 1
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vld2lanei16:
+;CHECK: vld2.16
+ %tmp1 = load <4 x i16>* %B
+ %tmp2 = call %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vld2lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v4hi2 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v4hi2 %tmp2, 1
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vld2lanei32:
+;CHECK: vld2.32
+ %tmp1 = load <2 x i32>* %B
+ %tmp2 = call %struct.__builtin_neon_v2si2 @llvm.arm.neon.vld2lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v2si2 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v2si2 %tmp2, 1
+ %tmp5 = add <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vld2lanef:
+;CHECK: vld2.32
+ %tmp1 = load <2 x float>* %B
+ %tmp2 = call %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vld2lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v2sf2 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v2sf2 %tmp2, 1
+ %tmp5 = add <2 x float> %tmp3, %tmp4
+ ret <2 x float> %tmp5
+}
+
+declare %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind readonly
+declare %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vld2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32) nounwind readonly
+declare %struct.__builtin_neon_v2si2 @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind readonly
+declare %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vld2lane.v2f32(i8*, <2 x float>, <2 x float>, i32) nounwind readonly
+
+%struct.__builtin_neon_v8qi3 = type { <8 x i8>, <8 x i8>, <8 x i8> }
+%struct.__builtin_neon_v4hi3 = type { <4 x i16>, <4 x i16>, <4 x i16> }
+%struct.__builtin_neon_v2si3 = type { <2 x i32>, <2 x i32>, <2 x i32> }
+%struct.__builtin_neon_v2sf3 = type { <2 x float>, <2 x float>, <2 x float> }
+
+define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vld3lanei8:
+;CHECK: vld3.8
+ %tmp1 = load <8 x i8>* %B
+ %tmp2 = call %struct.__builtin_neon_v8qi3 @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 1
+ %tmp5 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 2
+ %tmp6 = add <8 x i8> %tmp3, %tmp4
+ %tmp7 = add <8 x i8> %tmp5, %tmp6
+ ret <8 x i8> %tmp7
+}
+
+define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vld3lanei16:
+;CHECK: vld3.16
+ %tmp1 = load <4 x i16>* %B
+ %tmp2 = call %struct.__builtin_neon_v4hi3 @llvm.arm.neon.vld3lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v4hi3 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v4hi3 %tmp2, 1
+ %tmp5 = extractvalue %struct.__builtin_neon_v4hi3 %tmp2, 2
+ %tmp6 = add <4 x i16> %tmp3, %tmp4
+ %tmp7 = add <4 x i16> %tmp5, %tmp6
+ ret <4 x i16> %tmp7
+}
+
+define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vld3lanei32:
+;CHECK: vld3.32
+ %tmp1 = load <2 x i32>* %B
+ %tmp2 = call %struct.__builtin_neon_v2si3 @llvm.arm.neon.vld3lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v2si3 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v2si3 %tmp2, 1
+ %tmp5 = extractvalue %struct.__builtin_neon_v2si3 %tmp2, 2
+ %tmp6 = add <2 x i32> %tmp3, %tmp4
+ %tmp7 = add <2 x i32> %tmp5, %tmp6
+ ret <2 x i32> %tmp7
+}
+
+define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vld3lanef:
+;CHECK: vld3.32
+ %tmp1 = load <2 x float>* %B
+ %tmp2 = call %struct.__builtin_neon_v2sf3 @llvm.arm.neon.vld3lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v2sf3 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v2sf3 %tmp2, 1
+ %tmp5 = extractvalue %struct.__builtin_neon_v2sf3 %tmp2, 2
+ %tmp6 = add <2 x float> %tmp3, %tmp4
+ %tmp7 = add <2 x float> %tmp5, %tmp6
+ ret <2 x float> %tmp7
+}
+
+declare %struct.__builtin_neon_v8qi3 @llvm.arm.neon.vld3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind readonly
+declare %struct.__builtin_neon_v4hi3 @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind readonly
+declare %struct.__builtin_neon_v2si3 @llvm.arm.neon.vld3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind readonly
+declare %struct.__builtin_neon_v2sf3 @llvm.arm.neon.vld3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind readonly
+
+%struct.__builtin_neon_v8qi4 = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
+%struct.__builtin_neon_v4hi4 = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
+%struct.__builtin_neon_v2si4 = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
+%struct.__builtin_neon_v2sf4 = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
+
+define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vld4lanei8:
+;CHECK: vld4.8
+ %tmp1 = load <8 x i8>* %B
+ %tmp2 = call %struct.__builtin_neon_v8qi4 @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 1
+ %tmp5 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 2
+ %tmp6 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 3
+ %tmp7 = add <8 x i8> %tmp3, %tmp4
+ %tmp8 = add <8 x i8> %tmp5, %tmp6
+ %tmp9 = add <8 x i8> %tmp7, %tmp8
+ ret <8 x i8> %tmp9
+}
+
+define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vld4lanei16:
+;CHECK: vld4.16
+ %tmp1 = load <4 x i16>* %B
+ %tmp2 = call %struct.__builtin_neon_v4hi4 @llvm.arm.neon.vld4lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v4hi4 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v4hi4 %tmp2, 1
+ %tmp5 = extractvalue %struct.__builtin_neon_v4hi4 %tmp2, 2
+ %tmp6 = extractvalue %struct.__builtin_neon_v4hi4 %tmp2, 3
+ %tmp7 = add <4 x i16> %tmp3, %tmp4
+ %tmp8 = add <4 x i16> %tmp5, %tmp6
+ %tmp9 = add <4 x i16> %tmp7, %tmp8
+ ret <4 x i16> %tmp9
+}
+
+define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vld4lanei32:
+;CHECK: vld4.32
+ %tmp1 = load <2 x i32>* %B
+ %tmp2 = call %struct.__builtin_neon_v2si4 @llvm.arm.neon.vld4lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v2si4 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v2si4 %tmp2, 1
+ %tmp5 = extractvalue %struct.__builtin_neon_v2si4 %tmp2, 2
+ %tmp6 = extractvalue %struct.__builtin_neon_v2si4 %tmp2, 3
+ %tmp7 = add <2 x i32> %tmp3, %tmp4
+ %tmp8 = add <2 x i32> %tmp5, %tmp6
+ %tmp9 = add <2 x i32> %tmp7, %tmp8
+ ret <2 x i32> %tmp9
+}
+
+define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vld4lanef:
+;CHECK: vld4.32
+ %tmp1 = load <2 x float>* %B
+ %tmp2 = call %struct.__builtin_neon_v2sf4 @llvm.arm.neon.vld4lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__builtin_neon_v2sf4 %tmp2, 0
+ %tmp4 = extractvalue %struct.__builtin_neon_v2sf4 %tmp2, 1
+ %tmp5 = extractvalue %struct.__builtin_neon_v2sf4 %tmp2, 2
+ %tmp6 = extractvalue %struct.__builtin_neon_v2sf4 %tmp2, 3
+ %tmp7 = add <2 x float> %tmp3, %tmp4
+ %tmp8 = add <2 x float> %tmp5, %tmp6
+ %tmp9 = add <2 x float> %tmp7, %tmp8
+ ret <2 x float> %tmp9
+}
+
+declare %struct.__builtin_neon_v8qi4 @llvm.arm.neon.vld4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind readonly
+declare %struct.__builtin_neon_v4hi4 @llvm.arm.neon.vld4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind readonly
+declare %struct.__builtin_neon_v2si4 @llvm.arm.neon.vld4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind readonly
+declare %struct.__builtin_neon_v2sf4 @llvm.arm.neon.vld4lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32) nounwind readonly
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmax.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmax.ll
index 65f6076..85ff310 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmax.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmax.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vmax\\.s8} %t | count 2
; RUN: grep {vmax\\.s16} %t | count 2
; RUN: grep {vmax\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmin.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmin.ll
index 08a3f09..ecde35a 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmin.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmin.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vmin\\.s8} %t | count 2
; RUN: grep {vmin\\.s16} %t | count 2
; RUN: grep {vmin\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmla.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmla.ll
index ed77e11..3103d7f 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmla.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmla.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vmla\\.i8} %t | count 2
; RUN: grep {vmla\\.i16} %t | count 2
; RUN: grep {vmla\\.i32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmlal.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmlal.ll
index 7fd00ba..08c4d88 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmlal.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmlal.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vmlal\\.s8} %t | count 1
; RUN: grep {vmlal\\.s16} %t | count 1
; RUN: grep {vmlal\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmlal_lane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmlal_lane.ll
new file mode 100644
index 0000000..5bb0621
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmlal_lane.ll
@@ -0,0 +1,47 @@
+; RUN: llc -mattr=+neon < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlal_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmlal_lanes16
+; CHECK: vmlal.s16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlal_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmlal_lanes32
+; CHECK: vmlal.s32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlal_laneu16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmlal_laneu16
+; CHECK: vmlal.u16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlal_laneu32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmlal_laneu32
+; CHECK: vmlal.u32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmls.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmls.ll
index d519b7e..d3996a3 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmls.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vmls\\.i8} %t | count 2
; RUN: grep {vmls\\.i16} %t | count 2
; RUN: grep {vmls\\.i32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmlsl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmlsl.ll
index 94910dc..253157d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmlsl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmlsl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vmlsl\\.s8} %t | count 1
; RUN: grep {vmlsl\\.s16} %t | count 1
; RUN: grep {vmlsl\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmlsl_lane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmlsl_lane.ll
new file mode 100644
index 0000000..1effbd6
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmlsl_lane.ll
@@ -0,0 +1,47 @@
+; RUN: llc -mattr=+neon < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmlsl_lanes16
+; CHECK: vmlsl.s16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmlsl_lanes32
+; CHECK: vmlsl.s32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_laneu16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmlsl_laneu16
+; CHECK: vmlsl.u16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_laneu32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmlsl_laneu32
+; CHECK: vmlsl.u32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmov.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmov.ll
index af9c8e2..c4cb204 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmov.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmov.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep vmov.i8 %t | count 2
; RUN: grep vmov.i16 %t | count 4
; RUN: grep vmov.i32 %t | count 12
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmovl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmovl.ll
index 09a77af..4757680 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmovl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmovl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vmovl\\.s8} %t | count 1
; RUN: grep {vmovl\\.s16} %t | count 1
; RUN: grep {vmovl\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmovn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmovn.ll
index d4d027c..173bb52 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmovn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmovn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vmovn\\.i16} %t | count 1
; RUN: grep {vmovn\\.i32} %t | count 1
; RUN: grep {vmovn\\.i64} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmul.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmul.ll
index eb9ae7b..38abcca 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmul.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vmul\\.i8} %t | count 2
; RUN: grep {vmul\\.i16} %t | count 2
; RUN: grep {vmul\\.i32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmul_lane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmul_lane.ll
new file mode 100644
index 0000000..7edd873
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmul_lane.ll
@@ -0,0 +1,57 @@
+; RUN: llc -mattr=+neon < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmul_lanef32:
+; CHECK: vmul.f32 d0, d0, d1[0]
+ %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1]
+ %1 = fmul <2 x float> %0, %arg0_float32x2_t ; <<2 x float>> [#uses=1]
+ ret <2 x float> %1
+}
+
+define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmul_lanes16:
+; CHECK: vmul.i16 d0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$
+ %1 = mul <4 x i16> %0, %arg0_int16x4_t ; <<4 x i16>> [#uses=1]
+ ret <4 x i16> %1
+}
+
+define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmul_lanes32:
+; CHECK: vmul.i32 d0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = mul <2 x i32> %0, %arg0_int32x2_t ; <<2 x i32>> [#uses=1]
+ ret <2 x i32> %1
+}
+
+define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmulQ_lanef32:
+; CHECK: vmul.f32 q0, q0, d2[1]
+ %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$
+ %1 = fmul <4 x float> %0, %arg0_float32x4_t ; <<4 x float>> [#uses=1]
+ ret <4 x float> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmulQ_lanes16:
+; CHECK: vmul.i16 q0, q0, d2[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %1 = mul <8 x i16> %0, %arg0_int16x8_t ; <<8 x i16>> [#uses=1]
+ ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmulQ_lanes32:
+; CHECK: vmul.i32 q0, q0, d2[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$
+ %1 = mul <4 x i32> %0, %arg0_int32x4_t ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmull.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmull.ll
index 2fe6f37..c3bd141 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmull.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmull.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vmull\\.s8} %t | count 1
; RUN: grep {vmull\\.s16} %t | count 1
; RUN: grep {vmull\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmull_lane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmull_lane.ll
new file mode 100644
index 0000000..72cb3b1
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmull_lane.ll
@@ -0,0 +1,47 @@
+; RUN: llc -mattr=+neon < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmull_lanes16
+; CHECK: vmull.s16 q0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmull_lanes32
+; CHECK: vmull.s32 q0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmull_laneu16
+; CHECK: vmull.u16 q0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %arg0_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmull_laneu32
+; CHECK: vmull.u32 q0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %arg0_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vmvn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vmvn.ll
index 9bc1352..f71777b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vmvn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vmvn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep vmvn %t | count 8
; Note: function names do not include "vmvn" to allow simple grep for opcodes
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vneg.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vneg.ll
index 9fa527f..e5dc832 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vneg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vneg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vneg\\.s8} %t | count 2
; RUN: grep {vneg\\.s16} %t | count 2
; RUN: grep {vneg\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vorn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vorn.ll
index cee744c..23cbbf0 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vorn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vorn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep vorn %t | count 8
; Note: function names do not include "vorn" to allow simple grep for opcodes
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vorr.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vorr.ll
index 39f4814..5788bb2 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vorr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vorr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep vorr %t | count 8
; Note: function names do not include "vorr" to allow simple grep for opcodes
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vpadal.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vpadal.ll
index c41c532..8423b1b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vpadal.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vpadal.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vpadal\\.s8} %t | count 2
; RUN: grep {vpadal\\.s16} %t | count 2
; RUN: grep {vpadal\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vpadd.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vpadd.ll
index b551fc0..3e6179d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vpadd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vpadd.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vpadd\\.i8} %t | count 1
; RUN: grep {vpadd\\.i16} %t | count 1
; RUN: grep {vpadd\\.i32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vpaddl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vpaddl.ll
index babb495..d975710 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vpaddl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vpaddl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vpaddl\\.s8} %t | count 2
; RUN: grep {vpaddl\\.s16} %t | count 2
; RUN: grep {vpaddl\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vpmax.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vpmax.ll
index 90ae70f..8f6fb57 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vpmax.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vpmax.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vpmax\\.s8} %t | count 1
; RUN: grep {vpmax\\.s16} %t | count 1
; RUN: grep {vpmax\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vpmin.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vpmin.ll
index 0f982f4..3771258 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vpmin.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vpmin.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vpmin\\.s8} %t | count 1
; RUN: grep {vpmin\\.s16} %t | count 1
; RUN: grep {vpmin\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqRdmulh_lane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqRdmulh_lane.ll
new file mode 100644
index 0000000..f308c52
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqRdmulh_lane.ll
@@ -0,0 +1,47 @@
+; RUN: llc -mattr=+neon < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqRdmulhQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqRdmulhQ_lanes16
+; CHECK: vqrdmulh.s16 q0, q0, d2[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> ; <<8 x i16>> [#uses=1]
+ %1 = tail call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; <<8 x i16>> [#uses=1]
+ ret <8 x i16> %1
+}
+
+declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqRdmulhQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqRdmulhQ_lanes32
+; CHECK: vqrdmulh.s32 q0, q0, d2[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define arm_aapcs_vfpcc <4 x i16> @test_vqRdmulh_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqRdmulh_lanes16
+; CHECK: vqrdmulh.s16 d0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i16>> [#uses=1]
+ ret <4 x i16> %1
+}
+
+declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x i32> @test_vqRdmulh_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqRdmulh_lanes32
+; CHECK: vqrdmulh.s32 d0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i32>> [#uses=1]
+ ret <2 x i32> %1
+}
+
+declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqabs.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqabs.ll
index 04b8ad9..84e5938 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqabs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqabs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqabs\\.s8} %t | count 2
; RUN: grep {vqabs\\.s16} %t | count 2
; RUN: grep {vqabs\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqadd.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqadd.ll
index c9e2359..bce677a 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqadd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqadd.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqadd\\.s8} %t | count 2
; RUN: grep {vqadd\\.s16} %t | count 2
; RUN: grep {vqadd\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlal.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlal.ll
index f05bf53..3f9cde2 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlal.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlal.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqdmlal\\.s16} %t | count 1
; RUN: grep {vqdmlal\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlal_lanes.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlal_lanes.ll
new file mode 100644
index 0000000..ff532f3
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlal_lanes.ll
@@ -0,0 +1,25 @@
+; RUN: llc -mattr=+neon < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlal_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmlal_lanes16
+; CHECK: vqdmlal.s16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x i64> @test_vqdmlal_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmlal_lanes32
+; CHECK: vqdmlal.s32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlsl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlsl.ll
index 2b71ed5..2802916 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlsl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlsl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqdmlsl\\.s16} %t | count 1
; RUN: grep {vqdmlsl\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlsl_lanes.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlsl_lanes.ll
new file mode 100644
index 0000000..1a834ff
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmlsl_lanes.ll
@@ -0,0 +1,25 @@
+; RUN: llc -mattr=+neon < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsl_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmlsl_lanes16
+; CHECK: vqdmlsl.s16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x i64> @test_vqdmlsl_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmlsl_lanes32
+; CHECK: vqdmlsl.s32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmulh.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmulh.ll
index dd686dd..1600dc5 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmulh.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmulh.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqdmulh\\.s16} %t | count 2
; RUN: grep {vqdmulh\\.s32} %t | count 2
; RUN: grep {vqrdmulh\\.s16} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmulh_lane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmulh_lane.ll
new file mode 100644
index 0000000..874f5f3
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmulh_lane.ll
@@ -0,0 +1,47 @@
+; RUN: llc -mattr=+neon < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmulhQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmulhQ_lanes16
+; CHECK: vqdmulh.s16 q0, q0, d2[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> ; <<8 x i16>> [#uses=1]
+ %1 = tail call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; <<8 x i16>> [#uses=1]
+ ret <8 x i16> %1
+}
+
+declare <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmulhQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmulhQ_lanes32
+; CHECK: vqdmulh.s32 q0, q0, d2[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define arm_aapcs_vfpcc <4 x i16> @test_vqdmulh_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmulh_lanes16
+; CHECK: vqdmulh.s16 d0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i16>> [#uses=1]
+ ret <4 x i16> %1
+}
+
+declare <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x i32> @test_vqdmulh_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmulh_lanes32
+; CHECK: vqdmulh.s32 d0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i32>> [#uses=1]
+ ret <2 x i32> %1
+}
+
+declare <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmull.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmull.ll
index 3ff90f7..8ddd4d6 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmull.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmull.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqdmull\\.s16} %t | count 1
; RUN: grep {vqdmull\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqdmull_lane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmull_lane.ll
new file mode 100644
index 0000000..21f4e94
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqdmull_lane.ll
@@ -0,0 +1,25 @@
+; RUN: llc -mattr=+neon < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmull_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmull_lanes16
+; CHECK: vqdmull.s16 q0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x i64> @test_vqdmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmull_lanes32
+; CHECK: vqdmull.s32 q0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqmovn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqmovn.ll
index 78e6d23..06e5f1e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqmovn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqmovn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqmovn\\.s16} %t | count 1
; RUN: grep {vqmovn\\.s32} %t | count 1
; RUN: grep {vqmovn\\.s64} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqneg.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqneg.ll
index 72035f0..3626559 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqneg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqneg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqneg\\.s8} %t | count 2
; RUN: grep {vqneg\\.s16} %t | count 2
; RUN: grep {vqneg\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqrshl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqrshl.ll
index 63e03c1..e680f93 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqrshl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqrshl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqrshl\\.s8} %t | count 2
; RUN: grep {vqrshl\\.s16} %t | count 2
; RUN: grep {vqrshl\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqrshrn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqrshrn.ll
index 38f98f2..bb046fa 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqrshrn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqrshrn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqrshrn\\.s16} %t | count 1
; RUN: grep {vqrshrn\\.s32} %t | count 1
; RUN: grep {vqrshrn\\.s64} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqshl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqshl.ll
index 60b04bd..bfc4e88 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqshl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqshl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqshl\\.s8} %t | count 4
; RUN: grep {vqshl\\.s16} %t | count 4
; RUN: grep {vqshl\\.s32} %t | count 4
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqshrn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqshrn.ll
index 6bd607a..fb53c36 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqshrn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqshrn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqshrn\\.s16} %t | count 1
; RUN: grep {vqshrn\\.s32} %t | count 1
; RUN: grep {vqshrn\\.s64} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vqsub.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vqsub.ll
index 07052f7..bae4ebe 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vqsub.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vqsub.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vqsub\\.s8} %t | count 2
; RUN: grep {vqsub\\.s16} %t | count 2
; RUN: grep {vqsub\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vraddhn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vraddhn.ll
index d69e545..b3f2f0d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vraddhn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vraddhn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vraddhn\\.i16} %t | count 1
; RUN: grep {vraddhn\\.i32} %t | count 1
; RUN: grep {vraddhn\\.i64} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vrecpe.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vrecpe.ll
index 622725b..a97054f 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vrecpe.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vrecpe.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vrecpe\\.u32} %t | count 2
; RUN: grep {vrecpe\\.f32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vrecps.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vrecps.ll
index 7ded415..5ddd60b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vrecps.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vrecps.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vrecps\\.f32} %t | count 2
define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vrev.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vrev.ll
index 994d89d..f0a04a4 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vrev.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vrev.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
;CHECK: test_vrev64D8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vrhadd.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vrhadd.ll
index 4f6437c..6fa9f5e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vrhadd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vrhadd.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vrhadd\\.s8} %t | count 2
; RUN: grep {vrhadd\\.s16} %t | count 2
; RUN: grep {vrhadd\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vrshl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vrshl.ll
index fbbf548..df051e9 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vrshl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vrshl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vrshl\\.s8} %t | count 2
; RUN: grep {vrshl\\.s16} %t | count 2
; RUN: grep {vrshl\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vrshrn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vrshrn.ll
index 8af24fd..3dd21bc 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vrshrn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vrshrn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vrshrn\\.i16} %t | count 1
; RUN: grep {vrshrn\\.i32} %t | count 1
; RUN: grep {vrshrn\\.i64} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vrsqrte.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vrsqrte.ll
index 4f11977..5eb9494 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vrsqrte.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vrsqrte.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vrsqrte\\.u32} %t | count 2
; RUN: grep {vrsqrte\\.f32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vrsqrts.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vrsqrts.ll
index 3fd0567..46a4ce9 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vrsqrts.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vrsqrts.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vrsqrts\\.f32} %t | count 2
define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vrsubhn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vrsubhn.ll
index 5870923..4691783 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vrsubhn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vrsubhn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vrsubhn\\.i16} %t | count 1
; RUN: grep {vrsubhn\\.i32} %t | count 1
; RUN: grep {vrsubhn\\.i64} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vset_lane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vset_lane.ll
index f45f92a..bb20ded 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vset_lane.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vset_lane.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vmov\\.8} %t | count 2
; RUN: grep {vmov\\.16} %t | count 2
; RUN: grep {vmov\\.32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vshift.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vshift.ll
index 8c5c4aa..346d7e2 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vshift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vshift.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vshl\\.s8} %t | count 2
; RUN: grep {vshl\\.s16} %t | count 2
; RUN: grep {vshl\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vshift_split.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vshift_split.ll
index a44db66..f05921f 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vshift_split.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vshift_split.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=-neon
+; RUN: llc < %s -march=arm -mattr=-neon
; Example that requires splitting and expanding a vector shift.
define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vshiftins.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vshiftins.ll
index cb7cbb8..251efdc 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vshiftins.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vshiftins.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vsli\\.8} %t | count 2
; RUN: grep {vsli\\.16} %t | count 2
; RUN: grep {vsli\\.32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vshl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vshl.ll
index 993126e..773b184 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vshl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vshl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vshl\\.s8} %t | count 2
; RUN: grep {vshl\\.s16} %t | count 2
; RUN: grep {vshl\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vshll.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vshll.ll
index f81c09a..5407662 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vshll.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vshll.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vshll\\.s8} %t | count 1
; RUN: grep {vshll\\.s16} %t | count 1
; RUN: grep {vshll\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vshrn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vshrn.ll
index bc640cb..26834e7 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vshrn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vshrn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vshrn\\.i16} %t | count 1
; RUN: grep {vshrn\\.i32} %t | count 1
; RUN: grep {vshrn\\.i64} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vsra.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vsra.ll
index e2829dc..10cefc2 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vsra.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vsra.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vsra\\.s8} %t | count 2
; RUN: grep {vsra\\.s16} %t | count 2
; RUN: grep {vsra\\.s32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vst1.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vst1.ll
index 8fbae12..602b124 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vst1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vst1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
;CHECK: vst1i8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vst2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vst2.ll
index 3e2d028..587b17d 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vst2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vst2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
;CHECK: vst2i8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vst3.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vst3.ll
index 0a47efa..a851d0a 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vst3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vst3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
;CHECK: vst3i8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vst4.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vst4.ll
index fa745eb..8966b62 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vst4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vst4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
;CHECK: vst4i8:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vstlane.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vstlane.ll
new file mode 100644
index 0000000..391b702
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vstlane.ll
@@ -0,0 +1,113 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vst2lanei8:
+;CHECK: vst2.8
+ %tmp1 = load <8 x i8>* %B
+ call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vst2lanei16:
+;CHECK: vst2.16
+ %tmp1 = load <4 x i16>* %B
+ call void @llvm.arm.neon.vst2lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vst2lanei32:
+;CHECK: vst2.32
+ %tmp1 = load <2 x i32>* %B
+ call void @llvm.arm.neon.vst2lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vst2lanef:
+;CHECK: vst2.32
+ %tmp1 = load <2 x float>* %B
+ call void @llvm.arm.neon.vst2lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ ret void
+}
+
+declare void @llvm.arm.neon.vst2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.v2f32(i8*, <2 x float>, <2 x float>, i32) nounwind
+
+define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vst3lanei8:
+;CHECK: vst3.8
+ %tmp1 = load <8 x i8>* %B
+ call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vst3lanei16:
+;CHECK: vst3.16
+ %tmp1 = load <4 x i16>* %B
+ call void @llvm.arm.neon.vst3lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vst3lanei32:
+;CHECK: vst3.32
+ %tmp1 = load <2 x i32>* %B
+ call void @llvm.arm.neon.vst3lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vst3lanef:
+;CHECK: vst3.32
+ %tmp1 = load <2 x float>* %B
+ call void @llvm.arm.neon.vst3lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ ret void
+}
+
+declare void @llvm.arm.neon.vst3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
+
+
+define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vst4lanei8:
+;CHECK: vst4.8
+ %tmp1 = load <8 x i8>* %B
+ call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vst4lanei16:
+;CHECK: vst4.16
+ %tmp1 = load <4 x i16>* %B
+ call void @llvm.arm.neon.vst4lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vst4lanei32:
+;CHECK: vst4.32
+ %tmp1 = load <2 x i32>* %B
+ call void @llvm.arm.neon.vst4lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vst4lanef:
+;CHECK: vst4.32
+ %tmp1 = load <2 x float>* %B
+ call void @llvm.arm.neon.vst4lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ ret void
+}
+
+declare void @llvm.arm.neon.vst4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vsub.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vsub.ll
index 85dea41..8419a1b 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vsub.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vsub.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vsub\\.i8} %t | count 2
; RUN: grep {vsub\\.i16} %t | count 2
; RUN: grep {vsub\\.i32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vsubhn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vsubhn.ll
index 5adc9ed..f1eafa8 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vsubhn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vsubhn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vsubhn\\.i16} %t | count 1
; RUN: grep {vsubhn\\.i32} %t | count 1
; RUN: grep {vsubhn\\.i64} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vsubl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vsubl.ll
index d2af455..6cd867f 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vsubl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vsubl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vsubl\\.s8} %t | count 1
; RUN: grep {vsubl\\.s16} %t | count 1
; RUN: grep {vsubl\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vsubw.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vsubw.ll
index 30bec55..d83b19c 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vsubw.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vsubw.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vsubw\\.s8} %t | count 1
; RUN: grep {vsubw\\.s16} %t | count 1
; RUN: grep {vsubw\\.s32} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vtbl.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vtbl.ll
index 6e3e500..89653b0 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vtbl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vtbl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
%struct.__builtin_neon_v8qi3 = type { <8 x i8>, <8 x i8>, <8 x i8> }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vtrn.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vtrn.ll
index 3310efc..be55daa 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vtrn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vtrn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vtst.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vtst.ll
index 2f6ec3f..df7fb3e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vtst.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vtst.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: llc < %s -march=arm -mattr=+neon > %t
; RUN: grep {vtst\\.i8} %t | count 2
; RUN: grep {vtst\\.i16} %t | count 2
; RUN: grep {vtst\\.i32} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vuzp.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vuzp.ll
index e901e66..411f59e 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vuzp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vuzp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/vzip.ll b/libclamav/c++/llvm/test/CodeGen/ARM/vzip.ll
index 5927ea6..a1509b9 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/vzip.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/vzip.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/weak.ll b/libclamav/c++/llvm/test/CodeGen/ARM/weak.ll
index dadd1b9..5ac4b8c 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/weak.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/weak.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=arm | grep .weak.*f
-; RUN: llvm-as < %s | llc -march=arm | grep .weak.*h
+; RUN: llc < %s -march=arm | grep .weak.*f
+; RUN: llc < %s -march=arm | grep .weak.*h
define weak i32 @f() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/ARM/weak2.ll b/libclamav/c++/llvm/test/CodeGen/ARM/weak2.ll
index a57a767..cf327bb 100644
--- a/libclamav/c++/llvm/test/CodeGen/ARM/weak2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/ARM/weak2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm | grep .weak
+; RUN: llc < %s -march=arm | grep .weak
define i32 @f(i32 %a) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2002-04-14-UnexpectedUnsignedType.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2002-04-14-UnexpectedUnsignedType.ll
index f6d95cb..dd382cf 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2002-04-14-UnexpectedUnsignedType.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2002-04-14-UnexpectedUnsignedType.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s -o - | llc
+; RUN: llc < %s
; This caused the backend to assert out with:
; SparcInstrInfo.cpp:103: failed assertion `0 && "Unexpected unsigned type"'
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2002-04-16-StackFrameSizeAlignment.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2002-04-16-StackFrameSizeAlignment.ll
index d77b9e1..751ed40 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2002-04-16-StackFrameSizeAlignment.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2002-04-16-StackFrameSizeAlignment.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; Compiling this file produces:
; Sparc.cpp:91: failed assertion `(offset - OFFSET) % getStackFrameSizeAlignment() == 0'
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-phifcmpd.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-phifcmpd.ll
index cf17ef4..6fb1799 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-phifcmpd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-phifcmpd.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @QRiterate(i32 %p.1, double %tmp.212) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-useboolinotherbb.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-useboolinotherbb.ll
index 03b2a16..14bb000 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-useboolinotherbb.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-useboolinotherbb.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @QRiterate(double %tmp.212) {
%tmp.213 = fcmp une double %tmp.212, 0.000000e+00 ; <i1> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-usefsubasbool.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-usefsubasbool.ll
index b456eeb..cc0eb5c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-usefsubasbool.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-27-usefsubasbool.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @QRiterate(double %tmp.212) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-28-ManyArgs.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-28-ManyArgs.ll
index 595700a..c6fbdae 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-28-ManyArgs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-28-ManyArgs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
;; Date: May 28, 2003.
;; From: test/Programs/External/SPEC/CINT2000/175.vpr.llvm.bc
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-30-BadFoldGEP.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-30-BadFoldGEP.ll
index 41c90bd..10d3a11 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-30-BadFoldGEP.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-30-BadFoldGEP.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
;; Date: May 28, 2003.
;; From: test/Programs/External/SPEC/CINT2000/254.gap.llvm.bc
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-30-BadPreselectPhi.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-30-BadPreselectPhi.ll
index 43bff82..f7c3e42 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-30-BadPreselectPhi.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2003-05-30-BadPreselectPhi.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
;; Date: May 28, 2003.
;; From: test/Programs/SingleSource/richards_benchmark.c
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-06-BadIntCmp.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-06-BadIntCmp.ll
index d66ea18..1d1aad5 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-06-BadIntCmp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-06-BadIntCmp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
;; Date: May 28, 2003.
;; From: test/Programs/MultiSource/Olden-perimeter/maketree.c
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-07-BadLongConst.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-07-BadLongConst.ll
index 80738d5..64312ba 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-07-BadLongConst.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-07-BadLongConst.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@.str_1 = internal constant [42 x i8] c" ui = %u (0x%x)\09\09UL-ui = %lld (0x%llx)\0A\00" ; <[42 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-08-BadCastToBool.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-08-BadCastToBool.ll
index 4532b76..8019caa 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-08-BadCastToBool.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-08-BadCastToBool.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
;; Date: Jul 8, 2003.
;; From: test/Programs/MultiSource/Olden-perimeter
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll
index 54880db..4e6fe1c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
;; Date: Jul 29, 2003.
;; From: test/Programs/MultiSource/Ptrdist-bc
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll
index 10d4069..393062a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -enable-correct-eh-support
+; RUN: llc < %s -enable-correct-eh-support
define i32 @test() {
unwind
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2004-05-09-LiveVarPartialRegister.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2004-05-09-LiveVarPartialRegister.ll
index 1f58ce1..d4a4cf8 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2004-05-09-LiveVarPartialRegister.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2004-05-09-LiveVarPartialRegister.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@global_long_1 = linkonce global i64 7 ; <i64*> [#uses=1]
@global_long_2 = linkonce global i64 49 ; <i64*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll
index ed8b2a2..7fd2361 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @intersect_pixel() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2005-04-09-GlobalInPHI.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2005-04-09-GlobalInPHI.ll
index 37aaa32..353e411 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2005-04-09-GlobalInPHI.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2005-04-09-GlobalInPHI.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%struct.TypHeader = type { i32, %struct.TypHeader**, [3 x i8], i8 }
@.str_67 = external global [4 x i8] ; <[4 x i8]*> [#uses=1]
@.str_87 = external global [17 x i8] ; <[17 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2005-07-12-memcpy-i64-length.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2005-07-12-memcpy-i64-length.ll
index ab3a31d..733202c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2005-07-12-memcpy-i64-length.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2005-07-12-memcpy-i64-length.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; Test that llvm.memcpy works with a i64 length operand on all targets.
declare void @llvm.memcpy.i64(i8*, i8*, i64, i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2005-10-18-ZeroSizeStackObject.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2005-10-18-ZeroSizeStackObject.ll
index b2bea1c..08060bf 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2005-10-18-ZeroSizeStackObject.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2005-10-18-ZeroSizeStackObject.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @test() {
%X = alloca { } ; <{ }*> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2005-10-21-longlonggtu.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2005-10-21-longlonggtu.ll
index b355b02..53a9cd0 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2005-10-21-longlonggtu.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2005-10-21-longlonggtu.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define float @t(i64 %u_arg) {
%u = bitcast i64 %u_arg to i64 ; <i64> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2005-12-01-Crash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2005-12-01-Crash.ll
index ee72ee1..a9eedde 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2005-12-01-Crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2005-12-01-Crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@str = external global [36 x i8] ; <[36 x i8]*> [#uses=0]
@str.upgrd.1 = external global [29 x i8] ; <[29 x i8]*> [#uses=0]
@str1 = external global [29 x i8] ; <[29 x i8]*> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2005-12-12-ExpandSextInreg.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2005-12-12-ExpandSextInreg.ll
index bd2e043..349540f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2005-12-12-ExpandSextInreg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2005-12-12-ExpandSextInreg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i64 @test(i64 %A) {
%B = trunc i64 %A to i8 ; <i8> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-01-12-BadSetCCFold.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-01-12-BadSetCCFold.ll
index 1a555b3..42e8ed0 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-01-12-BadSetCCFold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-01-12-BadSetCCFold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; ModuleID = '2006-01-12-BadSetCCFold.ll'
%struct.node_t = type { double*, %struct.node_t*, %struct.node_t**, double**, double*, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-01-18-InvalidBranchOpcodeAssert.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-01-18-InvalidBranchOpcodeAssert.ll
index b1e08c7..f06d341 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-01-18-InvalidBranchOpcodeAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-01-18-InvalidBranchOpcodeAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; This crashed the PPC backend.
define void @test() {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-02-12-InsertLibcall.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-02-12-InsertLibcall.ll
index bacf8b5..5508272 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-02-12-InsertLibcall.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-02-12-InsertLibcall.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@G = external global i32 ; <i32*> [#uses=1]
define void @encode_one_frame(i64 %tmp.2i) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-03-01-dagcombineinfloop.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-03-01-dagcombineinfloop.ll
index 9607ebe..2a6cc0c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-03-01-dagcombineinfloop.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-03-01-dagcombineinfloop.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; Infinite loop in the dag combiner, reduced from 176.gcc.
%struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
%struct.anon = type { i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-11-vecload.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-11-vecload.ll
index cc96d8f..a68ed83 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-11-vecload.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-11-vecload.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah
+; RUN: llc < %s -march=x86 -mcpu=yonah
; The vload was getting memoized to the previous scalar load!
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-26-SetCCAnd.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-26-SetCCAnd.ll
index b99aa98..8465b82 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-26-SetCCAnd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-26-SetCCAnd.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR748
@G = external global i16 ; <i16*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-28-Sign-extend-bool.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
index 6b9bf11..22d8f99 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i32 @test(i32 %tmp93) {
%tmp98 = shl i32 %tmp93, 31 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
index 59ed295..1a9fa9f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.SYMBOL_TABLE_ENTRY = type { [9 x i8], [9 x i8], i32, i32, i32, %struct.SYMBOL_TABLE_ENTRY* }
%struct.__sFILEX = type opaque
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
index b644bd2..a3720a9 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0
+; RUN: llc < %s -O0
define float @test(i32 %tmp12771278) {
switch i32 %tmp12771278, label %bb1279 [
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
index 1aa3c62..bd922b3 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0
+; RUN: llc < %s -O0
%struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32 }
@cl_pf_opts = external global %struct.cl_perfunc_opts ; <%struct.cl_perfunc_opts*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll
index 8e8f186..c4f2fb0 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%struct.rtunion = type { i64 }
%struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] }
@ix86_cpu = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-07-03-schedulers.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-07-03-schedulers.ll
index 597ee56..756bd5d 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-07-03-schedulers.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-07-03-schedulers.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -pre-RA-sched=default
-; RUN: llvm-as < %s | llc -pre-RA-sched=list-burr
-; RUN: llvm-as < %s | llc -pre-RA-sched=fast
+; RUN: llc < %s -pre-RA-sched=default
+; RUN: llc < %s -pre-RA-sched=list-burr
+; RUN: llc < %s -pre-RA-sched=fast
; PR859
; The top-down schedulers are excluded here because they don't yet support
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-08-30-CoalescerCrash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-08-30-CoalescerCrash.ll
index 7f8af5d..cbe8b15 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-08-30-CoalescerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-08-30-CoalescerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.VEC_edge = type { i32, i32, [1 x %struct.edge_def*] }
%struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll
index c6d0dfe..4b332b3 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -regalloc=local
+; RUN: llc < %s -regalloc=local
%struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
@search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-09-06-SwitchLowering.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-09-06-SwitchLowering.ll
index 2134d33..3d592b3 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-09-06-SwitchLowering.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-09-06-SwitchLowering.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @foo() {
br label %cond_true813.i
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-10-27-CondFolding.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-10-27-CondFolding.ll
index b3cfb99..51902c8 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-10-27-CondFolding.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-10-27-CondFolding.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @start_pass_huff(i32 %gather_statistics) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-10-29-Crash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-10-29-Crash.ll
index cabec54..7dcb52c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-10-29-Crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-10-29-Crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @form_component_prediction(i32 %dy) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-11-06-MemIntrinsicExpand.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-11-06-MemIntrinsicExpand.ll
index a773759..ad3e49f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-11-06-MemIntrinsicExpand.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-11-06-MemIntrinsicExpand.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep adc
+; RUN: llc < %s -march=x86 | not grep adc
; PR987
declare void @llvm.memcpy.i64(i8*, i8*, i64, i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-11-20-DAGCombineCrash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
index 95ef53c..26d0f4f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1011
%struct.mng_data = type { i8* (%struct.mng_data*, i32)*, i32, i32, i32, i8, i8, i32, i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2006-12-16-InlineAsmCrash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2006-12-16-InlineAsmCrash.ll
index 91ac3b9..50a244b 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2006-12-16-InlineAsmCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2006-12-16-InlineAsmCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR1049
target datalayout = "e-p:32:32"
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-01-15-LoadSelectCycle.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-01-15-LoadSelectCycle.ll
index 49203d9..255b120 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-01-15-LoadSelectCycle.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-01-15-LoadSelectCycle.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1114
declare i1 @foo()
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-16-BranchFold.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-16-BranchFold.ll
index 0a8e49e..6bf5631 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-16-BranchFold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-16-BranchFold.ll
@@ -1,5 +1,5 @@
; PR 1200
-; RUN: llvm-as < %s | llc -enable-tail-merge=0 | not grep jmp
+; RUN: llc < %s -enable-tail-merge=0 | not grep jmp
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll
index 8b7db47..a8f0e57 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll
@@ -1,5 +1,5 @@
; PR1219
-; RUN: llvm-as < %s | llc -march=x86 | grep {movl \$1, %eax}
+; RUN: llc < %s -march=x86 | grep {movl \$1, %eax}
define i32 @test(i1 %X) {
old_entry1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-25-invoke.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-25-invoke.ll
index 6dba99e..6e20eaa 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-25-invoke.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-02-25-invoke.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1224
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll
index 9cbf314..339f0f7 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; XFAIL: sparc-sun-solaris2
; PR1308
; PR1557
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
index 1418bbf..a0b1403 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0
+; RUN: llc < %s -O0
; PR 1323
; ModuleID = 'test.bc'
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-14-BitTestsBadMask.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-14-BitTestsBadMask.ll
index 5490687..00337b9 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-14-BitTestsBadMask.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-14-BitTestsBadMask.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep 8388635
-; RUN: llvm-as < %s | llc -march=x86-64 | grep 4294981120
+; RUN: llc < %s -march=x86 | grep 8388635
+; RUN: llc < %s -march=x86-64 | grep 4294981120
; PR 1325
; ModuleID = 'bugpoint.test.bc'
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-17-lsr-crash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-17-lsr-crash.ll
index 4257e9f..98f87e5 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-17-lsr-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-17-lsr-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @foo(i32 %inTextSize) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-BitTestsBadMask.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-BitTestsBadMask.ll
index 16d7a16..3e8857f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-BitTestsBadMask.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-BitTestsBadMask.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep je | count 3
-; RUN: llvm-as < %s | llc -march=x86-64 | grep 4297064449
+; RUN: llc < %s -march=x86 | grep je | count 3
+; RUN: llc < %s -march=x86-64 | grep 4297064449
; PR 1325+
define i32 @foo(i8 %bar) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
index 0ea13a2..af522dc 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; Test that we can have an "X" output constraint.
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-LargeMemObject.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-LargeMemObject.ll
index 9424ea7..f2c9b7f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-LargeMemObject.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-27-LargeMemObject.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%struct..0anon = type { [100 x i32] }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
index 71b4c85..568b88f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1228
"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Alloc_hider" = type { i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll
index 8a42790..533aa4a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -enable-eh -march=x86
+; RUN: llc < %s -enable-eh -march=x86
%struct.exception = type { i8, i8, i32, i8*, i8*, i32, i8* }
@program_error = external global %struct.exception ; <%struct.exception*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-05-Personality.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-05-Personality.ll
index 0fa0e2f..2749326 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-05-Personality.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-05-Personality.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -enable-eh -o - | grep zPLR
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -enable-eh -o - | grep zPLR
@error = external global i8 ; <i8*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll
index a61108a..b989819 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* }
%struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, i8*, i32)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32* }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll
index 0b98ebe..33a3645 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -enable-eh -asm-verbose -o - | \
+; RUN: llc < %s -march=x86 -enable-eh -asm-verbose -o - | \
; RUN: grep -A 3 {Llabel138.*Region start} | grep {3.*Action}
; PR1422
; PR1508
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll
index cedee6f..e220be6 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -o -
+; RUN: llc < %s -o -
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll
index 98871d0..bd26481 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -enable-eh
+; RUN: llc < %s -enable-eh
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll
index 41fdb71..fc9164f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -enable-eh
+; RUN: llc < %s -enable-eh
; PR1833
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2008-01-25-dag-combine-mul.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2008-01-25-dag-combine-mul.ll
index 4b25444..314bb05 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2008-01-25-dag-combine-mul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2008-01-25-dag-combine-mul.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; rdar://5707064
define i32 @f(i16* %pc) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2008-01-30-LoadCrash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2008-01-30-LoadCrash.ll
index 8ed4139..70c3aaa 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2008-01-30-LoadCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2008-01-30-LoadCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@letters.3100 = external constant [63 x i8] ; <[63 x i8]*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-04-Ctlz.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-04-Ctlz.ll
index 4639b6f..288bfd2 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-04-Ctlz.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-04-Ctlz.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@.str = internal constant [14 x i8] c"%lld %d %d %d\00"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll
index 9acb852..8bf82df 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i32 @main() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-20-MatchingMem.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-20-MatchingMem.ll
index ef60f92..da1aeb5 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-20-MatchingMem.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-20-MatchingMem.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1133
define void @test(i32* %X) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-25-NegateZero.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-25-NegateZero.ll
index 0169307..97db667 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-25-NegateZero.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-25-NegateZero.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; rdar://5763967
define void @test() {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll
index b2112f3..10b3d44 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2096
%struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* }
%struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, i8*, i32)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32* }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll
index a60d101..4f95dfe 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2603
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2009-03-17-LSR-APInt.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2009-03-17-LSR-APInt.ll
index c584402..6281ada 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2009-03-17-LSR-APInt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2009-03-17-LSR-APInt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR3806
%struct..0__pthread_mutex_s = type { i32, i32, i32, i32, i32, i32, %struct.__pthread_list_t }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
index 40ad3de..9a9c1a1 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -soft-float
+; RUN: llc < %s -soft-float
; PR3899
@m = external global <2 x double>;
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2009-04-10-SinkCrash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2009-04-10-SinkCrash.ll
index 3637a06..125f875 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2009-04-10-SinkCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2009-04-10-SinkCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @QRiterate(i32 %p.1, double %tmp.212) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
index 405a6a8..577b547 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; rdar://6836460
define i32 @test(i128* %P) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll b/libclamav/c++/llvm/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll
index 59e7d0c..112cac4 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR4317
declare i32 @b()
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/APIntLoadStore.ll b/libclamav/c++/llvm/test/CodeGen/Generic/APIntLoadStore.ll
index 57ddae2..7c71a33 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/APIntLoadStore.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/APIntLoadStore.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc > %t
+; RUN: llc < %s > %t
@i1_l = external global i1 ; <i1*> [#uses=1]
@i1_s = external global i1 ; <i1*> [#uses=1]
@i2_l = external global i2 ; <i2*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/APIntParam.ll b/libclamav/c++/llvm/test/CodeGen/Generic/APIntParam.ll
index f80f71b..8aa0b49 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/APIntParam.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/APIntParam.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc > %t
+; RUN: llc < %s > %t
@i1_s = external global i1 ; <i1*> [#uses=1]
@i2_s = external global i2 ; <i2*> [#uses=1]
@i3_s = external global i3 ; <i3*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/APIntSextParam.ll b/libclamav/c++/llvm/test/CodeGen/Generic/APIntSextParam.ll
index 9fb06cb..acc0eeb 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/APIntSextParam.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/APIntSextParam.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc > %t
+; RUN: llc < %s > %t
@i1_s = external global i1 ; <i1*> [#uses=1]
@i2_s = external global i2 ; <i2*> [#uses=1]
@i3_s = external global i3 ; <i3*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/APIntZextParam.ll b/libclamav/c++/llvm/test/CodeGen/Generic/APIntZextParam.ll
index ea7743e..173b9fd 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/APIntZextParam.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/APIntZextParam.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc > %t
+; RUN: llc < %s > %t
@i1_s = external global i1 ; <i1*> [#uses=1]
@i2_s = external global i2 ; <i2*> [#uses=1]
@i3_s = external global i3 ; <i3*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/BasicInstrs.ll b/libclamav/c++/llvm/test/CodeGen/Generic/BasicInstrs.ll
index e65cbf7..578431e 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/BasicInstrs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/BasicInstrs.ll
@@ -1,7 +1,7 @@
; New testcase, this contains a bunch of simple instructions that should be
; handled by a code generator.
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i32 @add(i32 %A, i32 %B) {
%R = add i32 %A, %B ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/BurgBadRegAlloc.ll b/libclamav/c++/llvm/test/CodeGen/Generic/BurgBadRegAlloc.ll
index 3ccc9a0..99d856a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/BurgBadRegAlloc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/BurgBadRegAlloc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
;; Register allocation is doing a very poor job on this routine from yyparse
;; in Burg:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/ConstantExprLowering.ll b/libclamav/c++/llvm/test/CodeGen/Generic/ConstantExprLowering.ll
index d265415..428d712 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/ConstantExprLowering.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/ConstantExprLowering.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@.str_1 = internal constant [16 x i8] c"%d %d %d %d %d\0A\00" ; <[16 x i8]*> [#uses=1]
@XA = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/GC/alloc_loop.ll b/libclamav/c++/llvm/test/CodeGen/Generic/GC/alloc_loop.ll
index b1fee68..fb78ba2 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/GC/alloc_loop.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/GC/alloc_loop.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
declare i8* @llvm_gc_allocate(i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/GC/argpromotion.ll b/libclamav/c++/llvm/test/CodeGen/Generic/GC/argpromotion.ll
index 5df947a..dda376d 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/GC/argpromotion.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/GC/argpromotion.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -anders-aa -argpromotion
+; RUN: opt < %s -anders-aa -argpromotion
declare void @llvm.gcroot(i8**, i8*)
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/GC/deadargelim.ll b/libclamav/c++/llvm/test/CodeGen/Generic/GC/deadargelim.ll
index c5a56f6..1760190 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/GC/deadargelim.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/GC/deadargelim.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -deadargelim
+; RUN: opt < %s -deadargelim
declare void @llvm.gcroot(i8**, i8*)
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/GC/frame_size.ll b/libclamav/c++/llvm/test/CodeGen/Generic/GC/frame_size.ll
index 75626c1..31783cd 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/GC/frame_size.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/GC/frame_size.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -asm-verbose | grep {frame size} | grep -v 0x0
+; RUN: llc < %s -asm-verbose | grep {frame size} | grep -v 0x0
declare void @llvm.gcroot(i8** %value, i8* %tag)
declare void @g() gc "ocaml"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/GC/inline.ll b/libclamav/c++/llvm/test/CodeGen/Generic/GC/inline.ll
index 157e19d..9da33ae 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/GC/inline.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/GC/inline.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -inline | llvm-dis | grep example
+; RUN: opt < %s -inline -S | grep example
%IntArray = type { i32, [0 x i32*] }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/GC/inline2.ll b/libclamav/c++/llvm/test/CodeGen/Generic/GC/inline2.ll
index b45ef7c..1594705 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/GC/inline2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/GC/inline2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | opt -inline | llvm-dis | grep sample
-; RUN: llvm-as < %s | opt -inline | llvm-dis | grep example
+; RUN: opt < %s -inline -S | grep sample
+; RUN: opt < %s -inline -S | grep example
%IntArray = type { i32, [0 x i32*] }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/GC/lower_gcroot.ll b/libclamav/c++/llvm/test/CodeGen/Generic/GC/lower_gcroot.ll
index bd5a2bd..c2d418a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/GC/lower_gcroot.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/GC/lower_gcroot.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%Env = type i8*
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/GC/redundant_init.ll b/libclamav/c++/llvm/test/CodeGen/Generic/GC/redundant_init.ll
index 4499603..10c70e7 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/GC/redundant_init.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/GC/redundant_init.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | \
+; RUN: llc < %s -march=x86 | \
; RUN: ignore grep {movl..0} | count 0
%struct.obj = type { i8*, %struct.obj* }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/GC/simple_ocaml.ll b/libclamav/c++/llvm/test/CodeGen/Generic/GC/simple_ocaml.ll
index a33e035..f765dc0 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/GC/simple_ocaml.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/GC/simple_ocaml.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc | grep caml.*__frametable
-; RUN: llvm-as < %s | llc -march=x86 | grep {movl .0}
+; RUN: llc < %s | grep caml.*__frametable
+; RUN: llc < %s -march=x86 | grep {movl .0}
%struct.obj = type { i8*, %struct.obj* }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/SwitchLowering.ll b/libclamav/c++/llvm/test/CodeGen/Generic/SwitchLowering.ll
index 9fdfd8d..29a0e82 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/SwitchLowering.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/SwitchLowering.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep cmp | count 1
+; RUN: llc < %s -march=x86 | grep cmp | count 1
; PR964
define i8* @FindChar(i8* %CurPtr) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/add-with-overflow-24.ll b/libclamav/c++/llvm/test/CodeGen/Generic/add-with-overflow-24.ll
index debdeb2..63f5a22 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/add-with-overflow-24.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/add-with-overflow-24.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@ok = internal constant [4 x i8] c"%d\0A\00"
@no = internal constant [4 x i8] c"no\0A\00"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/add-with-overflow.ll b/libclamav/c++/llvm/test/CodeGen/Generic/add-with-overflow.ll
index 5c3d540..0c2c960 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/add-with-overflow.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/add-with-overflow.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc
-; RUN: llvm-as < %s | llc -fast-isel
+; RUN: llc < %s
+; RUN: llc < %s -fast-isel
@ok = internal constant [4 x i8] c"%d\0A\00"
@no = internal constant [4 x i8] c"no\0A\00"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/addc-fold2.ll b/libclamav/c++/llvm/test/CodeGen/Generic/addc-fold2.ll
index 8f3cdd0..34f5ac1 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/addc-fold2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/addc-fold2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep add
-; RUN: llvm-as < %s | llc -march=x86 | not grep adc
+; RUN: llc < %s -march=x86 | grep add
+; RUN: llc < %s -march=x86 | not grep adc
define i64 @test(i64 %A, i32 %B) {
%tmp12 = zext i32 %B to i64 ; <i64> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/asm-large-immediate.ll b/libclamav/c++/llvm/test/CodeGen/Generic/asm-large-immediate.ll
index 7064913..605665b 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/asm-large-immediate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/asm-large-immediate.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep 68719476738
+; RUN: llc < %s | grep 68719476738
define void @test() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/badCallArgLRLLVM.ll b/libclamav/c++/llvm/test/CodeGen/Generic/badCallArgLRLLVM.ll
index 5638474..4ed88df 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/badCallArgLRLLVM.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/badCallArgLRLLVM.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; This caused a problem because the argument of a call was defined by
; the return value of another call that appears later in the code.
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/badFoldGEP.ll b/libclamav/c++/llvm/test/CodeGen/Generic/badFoldGEP.ll
index 8de1251..2d4474b 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/badFoldGEP.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/badFoldGEP.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
;; GetMemInstArgs() folded the two getElementPtr instructions together,
;; producing an illegal getElementPtr. That's because the type generated
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/badarg6.ll b/libclamav/c++/llvm/test/CodeGen/Generic/badarg6.ll
index 1ff7df4..d6e5ac5 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/badarg6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/badarg6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; On this code, llc did not pass the sixth argument (%reg321) to printf.
; It passed the first five in %o0 - %o4, but never initialized %o5.
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/badlive.ll b/libclamav/c++/llvm/test/CodeGen/Generic/badlive.ll
index 0114fb0..43b03e3 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/badlive.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/badlive.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i32 @main() {
bb0:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/bool-to-double.ll b/libclamav/c++/llvm/test/CodeGen/Generic/bool-to-double.ll
index d6c9e52..81350a4 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/bool-to-double.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/bool-to-double.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define double @test(i1 %X) {
%Y = uitofp i1 %X to double ; <double> [#uses=1]
ret double %Y
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/bool-vector.ll b/libclamav/c++/llvm/test/CodeGen/Generic/bool-vector.ll
index e0f2a70..4758697 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/bool-vector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/bool-vector.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1845
define void @boolVectorSelect(<4 x i1>* %boolVectorPtr) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/call-ret0.ll b/libclamav/c++/llvm/test/CodeGen/Generic/call-ret0.ll
index 7ab966b..a8e00cd 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/call-ret0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/call-ret0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i32 @foo(i32 %x) {
ret i32 %x
}
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/call-ret42.ll b/libclamav/c++/llvm/test/CodeGen/Generic/call-ret42.ll
index ac9bd92..95cc286 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/call-ret42.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/call-ret42.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i32 @foo(i32 %x) {
ret i32 42
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/call-void.ll b/libclamav/c++/llvm/test/CodeGen/Generic/call-void.ll
index b882689..9ed4179 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/call-void.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/call-void.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @foo() {
ret void
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/call2-ret0.ll b/libclamav/c++/llvm/test/CodeGen/Generic/call2-ret0.ll
index 8c7e892..4e57ef8 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/call2-ret0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/call2-ret0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i32 @bar(i32 %x) {
ret i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/cast-fp.ll b/libclamav/c++/llvm/test/CodeGen/Generic/cast-fp.ll
index 5f05d85..590b7ce 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/cast-fp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/cast-fp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@a_fstr = internal constant [8 x i8] c"a = %f\0A\00" ; <[8 x i8]*> [#uses=1]
@a_lstr = internal constant [10 x i8] c"a = %lld\0A\00" ; <[10 x i8]*> [#uses=1]
@a_dstr = internal constant [8 x i8] c"a = %d\0A\00" ; <[8 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/constindices.ll b/libclamav/c++/llvm/test/CodeGen/Generic/constindices.ll
index 6366fd5..7deb30f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/constindices.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/constindices.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; Test that a sequence of constant indices are folded correctly
; into the equivalent offset at compile-time.
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/debug-info.ll b/libclamav/c++/llvm/test/CodeGen/Generic/debug-info.ll
index d1bb66d..20d9f91 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/debug-info.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/debug-info.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%lldb.compile_unit = type { i32, i16, i16, i8*, i8*, i8*, { }* }
@d.compile_unit7 = external global %lldb.compile_unit ; <%lldb.compile_unit*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/div-neg-power-2.ll b/libclamav/c++/llvm/test/CodeGen/Generic/div-neg-power-2.ll
index 3bc4899..246cd03 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/div-neg-power-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/div-neg-power-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i32 @test(i32 %X) {
%Y = sdiv i32 %X, -2 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/empty-load-store.ll b/libclamav/c++/llvm/test/CodeGen/Generic/empty-load-store.ll
index d7bb371..bca7305 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/empty-load-store.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/empty-load-store.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2612
@current_foo = internal global { } zeroinitializer
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/externally_available.ll b/libclamav/c++/llvm/test/CodeGen/Generic/externally_available.ll
index 73b6b98..7976cc9 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/externally_available.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/externally_available.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | not grep test_
+; RUN: llc < %s | not grep test_
; test_function should not be emitted to the .s file.
define available_externally i32 @test_function() {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/fastcall.ll b/libclamav/c++/llvm/test/CodeGen/Generic/fastcall.ll
index 65e66c7..35e04f1 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/fastcall.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/fastcall.ll
@@ -1,5 +1,5 @@
; Test fastcc works. Test from bug 2770.
-; RUN: llvm-as < %s | llc -relocation-model=pic
+; RUN: llc < %s -relocation-model=pic
%struct.__gcov_var = type { i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/fneg-fabs.ll b/libclamav/c++/llvm/test/CodeGen/Generic/fneg-fabs.ll
index 2709fa1..2f2f597 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/fneg-fabs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/fneg-fabs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define double @fneg(double %X) {
%Y = fsub double -0.000000e+00, %X ; <double> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/fp-to-int-invalid.ll b/libclamav/c++/llvm/test/CodeGen/Generic/fp-to-int-invalid.ll
index 73176b1..cdcc3a2 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/fp-to-int-invalid.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/fp-to-int-invalid.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR4057
define void @test_cast_float_to_char(i8* %result) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/fp_to_int.ll b/libclamav/c++/llvm/test/CodeGen/Generic/fp_to_int.ll
index 609de65..ad94413 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/fp_to_int.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/fp_to_int.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i8 @test1(double %X) {
%tmp.1 = fptosi double %X to i8 ; <i8> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/fpowi-promote.ll b/libclamav/c++/llvm/test/CodeGen/Generic/fpowi-promote.ll
index 55c2d2a..82628ef 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/fpowi-promote.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/fpowi-promote.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386
+; RUN: llc < %s
+; RUN: llc < %s -march=x86 -mcpu=i386
; PR1239
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/fwdtwice.ll b/libclamav/c++/llvm/test/CodeGen/Generic/fwdtwice.ll
index 05e831a..6b38f04 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/fwdtwice.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/fwdtwice.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
;;
;; Test the sequence:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/getresult-undef.ll b/libclamav/c++/llvm/test/CodeGen/Generic/getresult-undef.ll
index 7905ff5..c675535 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/getresult-undef.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/getresult-undef.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define double @foo() {
%t = getresult {double, double} undef, 1
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/global-ret0.ll b/libclamav/c++/llvm/test/CodeGen/Generic/global-ret0.ll
index 8fcef33..74bff87 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/global-ret0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/global-ret0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@g = global i32 0 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/hello.ll b/libclamav/c++/llvm/test/CodeGen/Generic/hello.ll
index 705423f..705945c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/hello.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/hello.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@.str_1 = internal constant [7 x i8] c"hello\0A\00" ; <[7 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/i128-addsub.ll b/libclamav/c++/llvm/test/CodeGen/Generic/i128-addsub.ll
index 10f0acc..e7cbf4a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/i128-addsub.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/i128-addsub.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/i128-arith.ll b/libclamav/c++/llvm/test/CodeGen/Generic/i128-arith.ll
index 9a67084..cf10463 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/i128-arith.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/i128-arith.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i64 @foo(i64 %x, i64 %y, i32 %amt) {
%tmp0 = zext i64 %x to i128
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/inline-asm-special-strings.ll b/libclamav/c++/llvm/test/CodeGen/Generic/inline-asm-special-strings.ll
index e52e0be..d18221e 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/inline-asm-special-strings.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/inline-asm-special-strings.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep "foo 0 0"
+; RUN: llc < %s | grep "foo 0 0"
define void @bar() nounwind {
tail call void asm sideeffect "foo ${:uid} ${:uid}", ""() nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/intrinsics.ll b/libclamav/c++/llvm/test/CodeGen/Generic/intrinsics.ll
index 373bec9..9a42c3e 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/intrinsics.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
;; SQRT
declare float @llvm.sqrt.f32(float)
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/invalid-memcpy.ll b/libclamav/c++/llvm/test/CodeGen/Generic/invalid-memcpy.ll
index e3acf0c..8448565 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/invalid-memcpy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/invalid-memcpy.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; This testcase is invalid (the alignment specified for memcpy is
; greater than the alignment guaranteed for Qux or C.0.1173), but it
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/isunord.ll b/libclamav/c++/llvm/test/CodeGen/Generic/isunord.ll
index fa465d4..ebbba01 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/isunord.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/isunord.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
declare i1 @llvm.isunordered.f64(double, double)
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/llvm-ct-intrinsics.ll b/libclamav/c++/llvm/test/CodeGen/Generic/llvm-ct-intrinsics.ll
index 66f409e..1db7549 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/llvm-ct-intrinsics.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/llvm-ct-intrinsics.ll
@@ -1,5 +1,5 @@
; Make sure this testcase is supported by all code generators
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
declare i64 @llvm.ctpop.i64(i64)
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll b/libclamav/c++/llvm/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll
index f21b645..282e973 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
declare { i64, double } @wild()
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/negintconst.ll b/libclamav/c++/llvm/test/CodeGen/Generic/negintconst.ll
index a2b3d69..67d775e 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/negintconst.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/negintconst.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; Test that a negative constant smaller than 64 bits (e.g., int)
; is correctly implemented with sign-extension.
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/nested-select.ll b/libclamav/c++/llvm/test/CodeGen/Generic/nested-select.ll
index 6f45f0f..f81fed3 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/nested-select.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/nested-select.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -o /dev/null
+; RUN: llc < %s -o /dev/null
; Test that select of a select works
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/phi-immediate-factoring.ll b/libclamav/c++/llvm/test/CodeGen/Generic/phi-immediate-factoring.ll
index e0f6759..9f9f921 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/phi-immediate-factoring.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/phi-immediate-factoring.ll
@@ -1,5 +1,5 @@
; PR1296
-; RUN: llvm-as < %s | llc -march=x86 | grep {movl \$1} | count 1
+; RUN: llc < %s -march=x86 | grep {movl \$1} | count 1
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/pr2625.ll b/libclamav/c++/llvm/test/CodeGen/Generic/pr2625.ll
index c1f585d..3e3dc4b 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/pr2625.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/pr2625.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2625
define i32 @main({ i32, { i32 } }*) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/pr3288.ll b/libclamav/c++/llvm/test/CodeGen/Generic/pr3288.ll
index ff0384d..b62710f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/pr3288.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/pr3288.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR3288
define void @a() {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/print-add.ll b/libclamav/c++/llvm/test/CodeGen/Generic/print-add.ll
index 4f1cb5e..95608dc 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/print-add.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/print-add.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@.str_1 = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/print-arith-fp.ll b/libclamav/c++/llvm/test/CodeGen/Generic/print-arith-fp.ll
index 1e27061..d129ff8 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/print-arith-fp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/print-arith-fp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@a_str = internal constant [8 x i8] c"a = %f\0A\00" ; <[8 x i8]*> [#uses=1]
@b_str = internal constant [8 x i8] c"b = %f\0A\00" ; <[8 x i8]*> [#uses=1]
@add_str = internal constant [12 x i8] c"a + b = %f\0A\00" ; <[12 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/print-arith-int.ll b/libclamav/c++/llvm/test/CodeGen/Generic/print-arith-int.ll
index cf27515..ce938cf 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/print-arith-int.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/print-arith-int.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@a_str = internal constant [8 x i8] c"a = %d\0A\00" ; <[8 x i8]*> [#uses=1]
@b_str = internal constant [8 x i8] c"b = %d\0A\00" ; <[8 x i8]*> [#uses=1]
@add_str = internal constant [12 x i8] c"a + b = %d\0A\00" ; <[12 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/print-int.ll b/libclamav/c++/llvm/test/CodeGen/Generic/print-int.ll
index 58f5047..7ca4b3d 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/print-int.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/print-int.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@.str_1 = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/print-mul-exp.ll b/libclamav/c++/llvm/test/CodeGen/Generic/print-mul-exp.ll
index 0666775..90fc55b 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/print-mul-exp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/print-mul-exp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@a_str = internal constant [8 x i8] c"a = %d\0A\00" ; <[8 x i8]*> [#uses=1]
@a_mul_str = internal constant [13 x i8] c"a * %d = %d\0A\00" ; <[13 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/print-mul.ll b/libclamav/c++/llvm/test/CodeGen/Generic/print-mul.ll
index 1d9452a..0707f3c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/print-mul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/print-mul.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@a_str = internal constant [8 x i8] c"a = %d\0A\00" ; <[8 x i8]*> [#uses=1]
@b_str = internal constant [8 x i8] c"b = %d\0A\00" ; <[8 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/print-shift.ll b/libclamav/c++/llvm/test/CodeGen/Generic/print-shift.ll
index 8992e8d..6c5d222 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/print-shift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/print-shift.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
@a_str = internal constant [8 x i8] c"a = %d\0A\00" ; <[8 x i8]*> [#uses=1]
@b_str = internal constant [8 x i8] c"b = %d\0A\00" ; <[8 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/ret0.ll b/libclamav/c++/llvm/test/CodeGen/Generic/ret0.ll
index 489f31c..9e628a1 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/ret0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/ret0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i32 @main() {
ret i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/ret42.ll b/libclamav/c++/llvm/test/CodeGen/Generic/ret42.ll
index 0cbe176..f5cd33d 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/ret42.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/ret42.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i32 @main() {
ret i32 42
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/select-cc.ll b/libclamav/c++/llvm/test/CodeGen/Generic/select-cc.ll
index 85e68d1..b653e2a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/select-cc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/select-cc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2504
define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/select.ll b/libclamav/c++/llvm/test/CodeGen/Generic/select.ll
index a532703..63052c1 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/select.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/select.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%Domain = type { i8*, i32, i32*, i32, i32, i32*, %Domain* }
@AConst = constant i32 123 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/shift-int64.ll b/libclamav/c++/llvm/test/CodeGen/Generic/shift-int64.ll
index 31be2d6..670ef20 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/shift-int64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/shift-int64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i64 @test_imm(i64 %X) {
%Y = ashr i64 %X, 17 ; <i64> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/spillccr.ll b/libclamav/c++/llvm/test/CodeGen/Generic/spillccr.ll
index 8545133..0a774c6 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/spillccr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/spillccr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s -o - | llc
+; RUN: llc < %s
; July 6, 2002 -- LLC Regression test
; This test case checks if the integer CC register %xcc (or %ccr)
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/stack-protector.ll b/libclamav/c++/llvm/test/CodeGen/Generic/stack-protector.ll
index a11a714..a59c649 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/stack-protector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/stack-protector.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -o - | grep {__stack_chk_guard}
-; RUN: llvm-as < %s | llc -o - | grep {__stack_chk_fail}
+; RUN: llc < %s -o - | grep {__stack_chk_guard}
+; RUN: llc < %s -o - | grep {__stack_chk_fail}
@"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00" ; <[11 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/stacksave-restore.ll b/libclamav/c++/llvm/test/CodeGen/Generic/stacksave-restore.ll
index fd3dd67..b124b5f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/stacksave-restore.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/stacksave-restore.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
declare i8* @llvm.stacksave()
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/storetrunc-fp.ll b/libclamav/c++/llvm/test/CodeGen/Generic/storetrunc-fp.ll
index 0f7bb0b..7f7c7f7 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/storetrunc-fp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/storetrunc-fp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @foo(double %a, double %b, float* %fp) {
%c = fadd double %a, %b
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/switch-crit-edge-constant.ll b/libclamav/c++/llvm/test/CodeGen/Generic/switch-crit-edge-constant.ll
index d71fe56..1f2ab0d 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/switch-crit-edge-constant.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/switch-crit-edge-constant.ll
@@ -1,5 +1,5 @@
; PR925
-; RUN: llvm-as < %s | llc -march=x86 | \
+; RUN: llc < %s -march=x86 | \
; RUN: grep mov.*str1 | count 1
target datalayout = "e-p:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower-feature-2.ll b/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower-feature-2.ll
index d3833e7..d6e5647 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower-feature-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower-feature-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -o %t
+; RUN: llc < %s -march=x86 -o %t
; RUN: grep jb %t | count 1
; RUN: grep \\\$6 %t | count 2
; RUN: grep 1024 %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower-feature.ll b/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower-feature.ll
index 0523401..65fdf5a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower-feature.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower-feature.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=x86 -o - | grep {\$7} | count 1
-; RUN: llvm-as < %s | llc -march=x86 -o - | grep {\$6} | count 1
-; RUN: llvm-as < %s | llc -march=x86 -o - | grep 1024 | count 1
-; RUN: llvm-as < %s | llc -march=x86 -o - | grep jb | count 2
-; RUN: llvm-as < %s | llc -march=x86 -o - | grep je | count 1
+; RUN: llc < %s -march=x86 -o - | grep {\$7} | count 1
+; RUN: llc < %s -march=x86 -o - | grep {\$6} | count 1
+; RUN: llc < %s -march=x86 -o - | grep 1024 | count 1
+; RUN: llc < %s -march=x86 -o - | grep jb | count 2
+; RUN: llc < %s -march=x86 -o - | grep je | count 1
define i32 @main(i32 %tmp158) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower.ll b/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower.ll
index b1aad3f..eb240ed 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/switch-lower.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1197
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/trap.ll b/libclamav/c++/llvm/test/CodeGen/Generic/trap.ll
index 4dfc1a6..67d1a7a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/trap.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/trap.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define i32 @test() noreturn nounwind {
entry:
tail call void @llvm.trap( )
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/v-split.ll b/libclamav/c++/llvm/test/CodeGen/Generic/v-split.ll
index 44601d0..634b562 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/v-split.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/v-split.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%f8 = type <8 x float>
define void @test_f8(%f8 *%P, %f8* %Q, %f8 *%S) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/vector-casts.ll b/libclamav/c++/llvm/test/CodeGen/Generic/vector-casts.ll
index 12104a3..a26918b 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/vector-casts.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/vector-casts.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2671
define void @a(<2 x double>* %p, <2 x i8>* %q) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/vector-constantexpr.ll b/libclamav/c++/llvm/test/CodeGen/Generic/vector-constantexpr.ll
index 441c4a0..d8e0258 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/vector-constantexpr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/vector-constantexpr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @""(float* %inregs, float* %outregs) {
%a_addr.i = alloca <4 x float> ; <<4 x float>*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/vector-identity-shuffle.ll b/libclamav/c++/llvm/test/CodeGen/Generic/vector-identity-shuffle.ll
index 61b44af..332d6d8 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/vector-identity-shuffle.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/vector-identity-shuffle.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @test(<4 x float>* %tmp2.i) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Generic/vector.ll b/libclamav/c++/llvm/test/CodeGen/Generic/vector.ll
index f283256..a0f9a02 100644
--- a/libclamav/c++/llvm/test/CodeGen/Generic/vector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Generic/vector.ll
@@ -1,5 +1,5 @@
; Test that vectors are scalarized/lowered correctly.
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%d8 = type <8 x double>
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll
index 70f294a..f95465c 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
define void @test() {
%tr1 = lshr i32 1, 0 ; <i32> [#uses=0]
ret void
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll
index 93a9123..c3bfa49 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
define void @main() {
%tr4 = shl i64 1, 0 ; <i64> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll
index 1a1aca4..dea654a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
define void @main() {
%shamt = add i8 0, 1 ; <i8> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll
index 3e490b1..fc190a4 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep .comm.*X,0
+; RUN: llc < %s -march=ppc32 | not grep .comm.*X,0
@X = linkonce global { } zeroinitializer ; <{ }*> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll
index f84caaf..ad02ece 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
define i32 @main() {
%setle = icmp sle i64 1, 0 ; <i1> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll
index 7b3e9b4..671bf80 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
define i64 @test() {
ret i64 undef
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll
index 8e8fee2..95012c3 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll
@@ -1,6 +1,6 @@
; this should not crash the ppc backend
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
define i32 @test(i32 %j.0.0.i) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll
index 428dd0c..5d1df46 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll
@@ -1,6 +1,6 @@
; This function should have exactly one call to fixdfdi, no more!
-; RUN: llvm-as < %s | llc -march=ppc32 -mattr=-64bit | \
+; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
; RUN: grep {bl .*fixdfdi} | count 1
define double @test2(double %tmp.7705) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll
index 54f24c6..8a5d3b0 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll
@@ -1,7 +1,7 @@
; This was erroneously being turned into an rlwinm instruction.
; The sign bit does matter in this case.
-; RUN: llvm-as < %s | llc -march=ppc32 | grep srawi
+; RUN: llc < %s -march=ppc32 | grep srawi
define i32 @test(i32 %X) {
%Y = and i32 %X, -2 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
index d56cffc..047a12b 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "E-p:32:32"
target triple = "powerpc-apple-darwin8.2.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll
index 1b3bde8..97bb48e 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | not grep {, f1}
+; RUN: llc < %s | not grep {, f1}
target datalayout = "E-p:32:32"
target triple = "powerpc-apple-darwin8.2.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
index 86ad718..fbf2540 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define void @iterative_hash_host_wide_int() {
%zero = alloca i32 ; <i32*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll
index 8500260..172e348 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
define double @CalcSpeed(float %tmp127) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll
index a536fa1..969772e 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
; RUN: grep {vspltish v.*, 10}
define void @test(<8 x i16>* %P) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll
index b79cce2..d225664 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
+; RUN: llc < %s -march=ppc32 -mcpu=g5
; END.
define void @test(i8* %stack) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll
index e1033c3..0205d10 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
; END.
%struct.attr_desc = type { i8*, %struct.attr_desc*, %struct.attr_value*, %struct.attr_value*, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
index 33807ca..1b8b064 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin | grep extsw | count 2
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin | grep extsw | count 2
@lens = external global i8* ; <i8**> [#uses=1]
@vals = external global i32* ; <i32**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll
index c25cf21..65dd568 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
-define void @img2buf(i32 %symbol_size_in_bytes, i16* %ui16) {
+define void @img2buf(i32 %symbol_size_in_bytes, i16* %ui16) nounwind {
%tmp93 = load i16* null ; <i16> [#uses=1]
%tmp99 = call i16 @llvm.bswap.i16( i16 %tmp93 ) ; <i16> [#uses=1]
store i16 %tmp99, i16* %ui16
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll
index 1043e45..a947e5c 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsldoi
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vor
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsldoi
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vor
define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) {
%tmp76 = shufflevector <4 x float> %fp0, <4 x float> %fp1, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll
index aff4ede..cb76b5c 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
%struct..0anon = type { i32 }
%struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-09-28-shift_64.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-09-28-shift_64.ll
index 5210dd1..f748a8b 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-09-28-shift_64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-09-28-shift_64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc64
target datalayout = "E-p:64:64"
target triple = "powerpc64-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
index 7a65c00..57ed250 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -combiner-alias-analysis | grep f5
+; RUN: llc < %s -march=ppc32 -combiner-alias-analysis | grep f5
target datalayout = "E-p:32:32"
target triple = "powerpc-apple-darwin8.2.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll
index 6621cec..002a064 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep IMPLICIT_DEF
+; RUN: llc < %s -march=ppc32 | not grep IMPLICIT_DEF
define void @foo(i64 %X) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
index 313568c..3d462b4 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep xor
+; RUN: llc < %s -march=ppc32 | grep xor
target datalayout = "E-p:32:32"
target triple = "powerpc-apple-darwin8.7.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll
index 6dc1ff0..3284f0a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc64
define i32* @foo(i32 %n) {
%A = alloca i32, i32 %n ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
index 80ef479..49b3b9d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwimi
+; RUN: llc < %s -march=ppc32 | grep rlwimi
define void @test(i16 %div.0.i.i.i.i, i32 %L_num.0.i.i.i.i, i32 %tmp1.i.i206.i.i, i16* %P) {
%X = shl i16 %div.0.i.i.i.i, 1 ; <i16> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll
index 7680c21..61b9967 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
+; RUN: llc < %s -march=ppc32 -mcpu=g5
define void @glgRunProcessor15() {
%tmp26355.i = shufflevector <4 x float> zeroinitializer, <4 x float> < float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000 >, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >; <<4 x float>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
index be3b863..ba86304 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=ppc64
-; RUN: llvm-as < %s | llc -march=ppc32
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s -march=ppc64
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s
define void @bitap() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
index 058166f..6d9a3fa 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=ppc64
-; RUN: llvm-as < %s | llc -march=ppc32
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s -march=ppc64
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s
@qsz.b = external global i1 ; <i1*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll
index 19fedf9..805528c 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep extsb
-; RUN: llvm-as < %s | llc -march=ppc32 | grep extsh
+; RUN: llc < %s -march=ppc32 | grep extsb
+; RUN: llc < %s -march=ppc32 | grep extsh
define i32 @p1(i8 %c, i16 %s) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll
index e23c3ce..7b00ac6 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
; RUN: grep cntlzw
define i32 @foo() nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
index f2c951e..0c45472 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -march=ppc64
define i16 @test(i8* %d1, i16* %d2) {
%tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 ) ; <i16> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
index d476462..fe5145d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -march=ppc64
; Test two things: 1) that a frameidx can be rewritten in an inline asm
; 2) that inline asms can handle reg+imm addr modes.
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll
index 97f6a01..621d43b 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | \
; RUN: grep align.*3
@X = global <{i32, i32}> <{ i32 1, i32 123 }>
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll
index 5a3d3b5..f48f365 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "E-p:32:32"
target triple = "powerpc-apple-darwin8.8.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll
index 3eef9c5..0473857 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep mflr | count 1
+; RUN: llc < %s | grep mflr | count 1
target datalayout = "e-p:32:32"
target triple = "powerpc-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll
index 098e748..e93395a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64 -mcpu=g5 | grep cntlzd
+; RUN: llc < %s -march=ppc64 -mcpu=g5 | grep cntlzd
define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) {
%tmp19 = load i64* %t
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll
index 637208b..d43916d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
+; RUN: llc < %s -march=ppc32 -mcpu=g5
define void @test(<4 x float>*, { { i16, i16, i32 } }*) {
xOperationInitMasks.exit:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll
index 656b831..86fd947 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {foo r3, r4}
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {bari r3, 47}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {foo r3, r4}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {bari r3, 47}
; PR1351
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
index ba0f8fe..f2fdedf 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc | grep {subfc r3,r5,r4}
-; RUN: llvm-as < %s | llc | grep {subfze r4,r2}
-; RUN: llvm-as < %s | llc -regalloc=local | grep {subfc r5,r2,r4}
-; RUN: llvm-as < %s | llc -regalloc=local | grep {subfze r2,r3}
+; RUN: llc < %s | grep {subfc r3,r5,r4}
+; RUN: llc < %s | grep {subfze r4,r2}
+; RUN: llc < %s -regalloc=local | grep {subfc r5,r2,r4}
+; RUN: llc < %s -regalloc=local | grep {subfze r2,r3}
; The first argument of subfc must not be the same as any other register.
; PR1357
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
index 989a751..1df5140 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1382
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll
index b64de68..e4e9314 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "powerpc-apple-darwin8.8.0"
%struct..0anon = type { i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll
index 5a86418..42f2152 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*baz | count 2
-; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*quux | count 2
-; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge | grep bl.*baz | count 1
-; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge=1 | grep bl.*quux | count 1
+; RUN: llc < %s -march=ppc32 | grep bl.*baz | count 2
+; RUN: llc < %s -march=ppc32 | grep bl.*quux | count 2
+; RUN: llc < %s -march=ppc32 -enable-tail-merge | grep bl.*baz | count 1
+; RUN: llc < %s -march=ppc32 -enable-tail-merge=1 | grep bl.*quux | count 1
; Check that tail merging is not the default on ppc, and that -enable-tail-merge works.
; ModuleID = 'tail.c'
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll
index ae853f6..2938c70 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll
@@ -1,7 +1,7 @@
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "powerpc-apple-darwin8.8.0"
-; RUN: llvm-as < %s | llc -march=ppc32 | grep {rlwinm r3, r3, 23, 30, 30}
+; RUN: llc < %s -march=ppc32 | grep {rlwinm r3, r3, 23, 30, 30}
; PR1473
define i8 @foo(i16 zeroext %a) zeroext {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll
index 58260ec..6de7a09 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mattr=+altivec
+; RUN: llc < %s -march=ppc32 -mattr=+altivec
%struct.XATest = type { float, i16, i8, i8 }
%struct.XArrayRange = type { i8, i8, i8, i8 }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll
index 34df7bb..06f40d9 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc64
; PR1596
%struct._obstack_chunk = type { i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll
index 9c8fa97..82ef2b8 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64 | grep dst | count 4
+; RUN: llc < %s -march=ppc64 | grep dst | count 4
define hidden void @_Z4borkPc(i8* %image) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll
index c5e7a4d..ea7de98 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64 | grep lwzx
+; RUN: llc < %s -march=ppc64 | grep lwzx
%struct.__db_region = type { %struct.__mutex_t, [4 x i8], %struct.anon, i32, [1 x i32] }
%struct.__mutex_t = type { i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-08-unaligned.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-08-unaligned.ll
index f6bd333..898c470 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-08-unaligned.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-08-unaligned.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc | grep stfd | count 3
-; RUN: llvm-as < %s | llc | grep stfs | count 1
-; RUN: llvm-as < %s | llc | grep lfd | count 2
-; RUN: llvm-as < %s | llc | grep lfs | count 2
+; RUN: llc < %s | grep stfd | count 3
+; RUN: llc < %s | grep stfs | count 1
+; RUN: llc < %s | grep lfd | count 2
+; RUN: llc < %s | grep lfs | count 2
; ModuleID = 'foo.c'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll
index bb7aba4..d12698b 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc64
%struct.TCMalloc_SpinLock = type { i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll
index f4b87cf..5cfe54e 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin
declare void @cxa_atexit_check_1(i8*)
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll
index e71a8fb..c4152b4 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
; rdar://5538377
%struct.disk_unsigned = type { i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll
index bd11b5d..84fadd1 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64 -mattr=+altivec
+; RUN: llc < %s -march=ppc64 -mattr=+altivec
%struct.inoutprops = type <{ i8, [3 x i8] }>
define void @bork(float* %argA, float* %argB, float* %res, i8 %inoutspec.0) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
index bca6e5a..ee61478 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic
%struct.NSError = type opaque
%struct.NSManagedObjectContext = type opaque
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
index 80ef6f1..5a07a9b 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic
%struct.NSError = type opaque
%struct.NSManagedObjectContext = type opaque
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll
index e49d59a..a9f242b 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
%struct.HDescriptor = type <{ i32, i32 }>
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll
index a0649e0..439ef14 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -enable-eh
+; RUN: llc < %s -enable-eh
;; Formerly crashed, see PR 1508
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc64-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
index aca0faa..d1f0285 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
+; RUN: llc < %s
+; RUN: llc < %s -march=ppc32 -mcpu=g3
+; RUN: llc < %s -march=ppc32 -mcpu=g5
; PR1811
define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>*
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll
index 38ae87c..db2ab87 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep nop
+; RUN: llc < %s -march=ppc32 | grep nop
target triple = "powerpc-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll
index 5b9cd1d..791e9e6 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
%struct.Handle = type { %struct.oopDesc** }
%struct.JNI_ArgumentPusher = type { %struct.SignatureIterator, %struct.JavaCallArguments* }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll
index 5edf6b7..cfa1b10 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin -regalloc=local
+; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=local
define i32 @bork(i64 %foo, i64 %bar) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
index 8101a35..e50fac4 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin -enable-ppc32-regscavenger
+; RUN: llc < %s -mtriple=powerpc-apple-darwin -enable-ppc32-regscavenger
declare i8* @bar(i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll
index 919de33..222dde4 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc64-regscavenger
+; RUN: llc < %s -march=ppc64 -enable-ppc64-regscavenger
@.str242 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1]
define fastcc void @ParseContent(i8* %buf, i32 %bufsize) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
index eaeccc5..9f35b83 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -enable-ppc32-regscavenger
+; RUN: llc < %s -march=ppc32 -enable-ppc32-regscavenger
%struct._cpp_strbuf = type { i8*, i32, i32 }
%struct.cpp_string = type { i32, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll
index 061c585..dd425f5 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc64-regscavenger
+; RUN: llc < %s -march=ppc64 -enable-ppc64-regscavenger
define i16 @test(i8* %d1, i16* %d2) {
%tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 )
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll
index 395c986..a8fef05 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc64
define fastcc i8* @page_rec_get_next(i8* %rec) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll
index 67c167a..8776d9a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
%struct..0objc_object = type { %struct.objc_class* }
%struct.NSArray = type { %struct..0objc_object }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll
index 0b748d2..8e5bf56 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
define i32 @t(i64 %byteStart, i32 %activeIndex) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll
index 410736d..2706337 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
define fastcc i64 @nonzero_bits1() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll
index 357ab10..839098e 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
; Avoid reading memory that's already freed.
@llvm.used = appending global [1 x i8*] [ i8* bitcast (i32 (i64)* @_Z13GetSectorSizey to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll
index a390e52..7b6d491 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
@_ZL10DeviceCode = internal global i16 0 ; <i16*> [#uses=1]
@.str19 = internal constant [64 x i8] c"unlock_then_erase_sector: failed to erase block (status= 0x%x)\0A\00" ; <[64 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll
index 5c40b9e..d42c814 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
target triple = "powerpc-apple-darwin9.2.2"
define i256 @func(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind readnone {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll
index d337e37..6b40b24 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
define void @t() nounwind {
call void null( ppc_fp128 undef )
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll
index 92b5ca2..862559b 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
@g = external global ppc_fp128
@h = external global ppc_fp128
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
index d3238d2..83c5511 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
; <rdar://problem/6020042>
define i32 @bork() nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll
index b6b9c89..8802b97 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vadduhm
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsubuhm
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vadduhm
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubuhm
define <4 x i32> @test() nounwind {
ret <4 x i32> < i32 4293066722, i32 4293066722, i32 4293066722, i32 4293066722>
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-Bswap.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-Bswap.ll
index 7060fe5..4a834f9 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-Bswap.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-Bswap.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin9"
%struct.BiPartSrcDescriptor = type <{ %"struct.BiPartSrcDescriptor::$_105" }>
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-Fabs.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-Fabs.ll
index f55ffac..17737d9 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-Fabs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-Fabs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin9"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
index 32e3642..5cd8c34 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin9"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
index a7f8181..dc1e936 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin9"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll
index 2ccca25..c9c05e1 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin | grep lwz | grep 228
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin | grep lwz | grep 228
@"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll
index b625ceb..97844dd 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
%struct.CGLDI = type { %struct.cgli*, i32, i32, i32, i32, i32, i8*, i32, void (%struct.CGLSI*, i32, %struct.CGLDI*)*, i8*, %struct.vv_t }
%struct.cgli = type { i32, %struct.cgli*, void (%struct.cgli*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32)*, i32, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i8*, i32*, %struct._cgro*, %struct._cgro*, float, float, float, float, i32, i8*, float, i8*, [16 x i32] }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
index 00ca811..91c36ef 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; XFAIL: *
; PR2356
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll
index c760b41..f474a6d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc64
define void @__divtc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
index 071c788..f4c06fb 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -o - | not grep fixunstfsi
+; RUN: llc < %s -march=ppc32 -o - | not grep fixunstfsi
define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll
index af9a54e..83f3f6f 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
; PR2986
@argc = external global i32 ; <i32*> [#uses=1]
@buffer = external global [32 x i8], align 4 ; <[32 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll
index 0ad5b06..20683b9 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2988
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin10.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll
index f5b3e93..9ed7f6f 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin9.5
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin9.5
define void @__multc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-12-12-EH.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-12-12-EH.ll
index 21218f5..b56c22a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-12-12-EH.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2008-12-12-EH.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | grep ^.L_Z1fv.eh
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | grep ^.L_Z1fv.eh
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh
define void @_Z1fv() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll
index 0cf5518..d49d58d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin9.5
+; RUN: llc < %s -mtriple=powerpc-apple-darwin9.5
; rdar://6499616
%llvm.dbg.anchor.type = type { i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll
index a898de0..172531e 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin10
+; RUN: llc < %s -mtriple=powerpc-apple-darwin10
; rdar://6692215
define fastcc void @_qsort(i8* %a, i32 %n, i32 %es, i32 (i8*, i8*)* %cmp, i32 %depth_limit) nounwind optsize ssp {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll
index 4ea43ec..29d115d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin10
+; RUN: llc < %s -mtriple=powerpc-apple-darwin10
; PR4280
define i32 @__fixunssfsi(float %a) nounwind readnone {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll
index d636e80..f64e3dc 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -verify-machineinstrs
+; RUN: llc < %s -march=ppc32 -verify-machineinstrs
; Machine code verifier will call isRegTiedToDefOperand() on /all/ register use
; operands. We must make sure that the operand flag is found correctly.
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
index e1fa30a..5d09696 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | FileCheck %s
+; RUN: llc < %s -march=ppc32 | FileCheck %s
; ModuleID = '<stdin>'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin10.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll
index 6fe33e8..12c4c99 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=ppc-apple-darwin | FileCheck %s
+; RUN: llc < %s -march=ppc32 -mtriple=ppc-apple-darwin | FileCheck %s
; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm'
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-09-18-carrybit.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
new file mode 100644
index 0000000..6c23a61
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
@@ -0,0 +1,62 @@
+; RUN: llc -march=ppc32 < %s | FileCheck %s
+; ModuleID = '<stdin>'
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9.6"
+
+define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind {
+entry:
+; CHECK: foo:
+; CHECK: subfc
+; CHECK: subfe
+; CHECK: subfc
+; CHECK: subfe
+ %tmp0 = add i64 %r.0.ph, -1 ; <i64> [#uses=1]
+ br label %bb40
+
+bb40: ; preds = %bb40, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb40 ] ; <i32> [#uses=1]
+ %carry.0274 = phi i32 [ 0, %entry ], [%tmp122, %bb40 ] ; <i32> [#uses=1]
+ %r.0273 = phi i64 [ %r.0.ph, %entry ], [ %tmp124, %bb40 ] ; <i64> [#uses=2]
+ %q.0272 = phi i64 [ %q.0.ph, %entry ], [ %ins169, %bb40 ] ; <i64> [#uses=3]
+ %tmp1 = lshr i64 %r.0273, 31 ; <i64> [#uses=1]
+ %tmp2 = trunc i64 %tmp1 to i32 ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp2, -2 ; <i32> [#uses=1]
+ %tmp213 = trunc i64 %r.0273 to i32 ; <i32> [#uses=2]
+ %tmp106 = lshr i32 %tmp213, 31 ; <i32> [#uses=1]
+ %tmp107 = or i32 %tmp3, %tmp106 ; <i32> [#uses=1]
+ %tmp215 = zext i32 %tmp107 to i64 ; <i64> [#uses=1]
+ %tmp216 = shl i64 %tmp215, 32 ; <i64> [#uses=1]
+ %tmp108 = shl i32 %tmp213, 1 ; <i32> [#uses=1]
+ %tmp109 = lshr i64 %q.0272, 63 ; <i64> [#uses=1]
+ %tmp110 = trunc i64 %tmp109 to i32 ; <i32> [#uses=1]
+ %tmp111 = or i32 %tmp108, %tmp110 ; <i32> [#uses=1]
+ %tmp222 = zext i32 %tmp111 to i64 ; <i64> [#uses=1]
+ %ins224 = or i64 %tmp216, %tmp222 ; <i64> [#uses=2]
+ %tmp112 = lshr i64 %q.0272, 31 ; <i64> [#uses=1]
+ %tmp113 = trunc i64 %tmp112 to i32 ; <i32> [#uses=1]
+ %tmp114 = and i32 %tmp113, -2 ; <i32> [#uses=1]
+ %tmp158 = trunc i64 %q.0272 to i32 ; <i32> [#uses=2]
+ %tmp115 = lshr i32 %tmp158, 31 ; <i32> [#uses=1]
+ %tmp116 = or i32 %tmp114, %tmp115 ; <i32> [#uses=1]
+ %tmp160 = zext i32 %tmp116 to i64 ; <i64> [#uses=1]
+ %tmp161 = shl i64 %tmp160, 32 ; <i64> [#uses=1]
+ %tmp117 = shl i32 %tmp158, 1 ; <i32> [#uses=1]
+ %tmp118 = or i32 %tmp117, %carry.0274 ; <i32> [#uses=1]
+ %tmp167 = zext i32 %tmp118 to i64 ; <i64> [#uses=1]
+ %ins169 = or i64 %tmp161, %tmp167 ; <i64> [#uses=2]
+ %tmp119 = sub i64 %tmp0, %ins224 ; <i64> [#uses=1]
+ %tmp120 = ashr i64 %tmp119, 63 ; <i64> [#uses=2]
+ %tmp121 = trunc i64 %tmp120 to i32 ; <i32> [#uses=1]
+ %tmp122 = and i32 %tmp121, 1 ; <i32> [#uses=2]
+ %tmp123 = and i64 %tmp120, %q.0.ph ; <i64> [#uses=1]
+ %tmp124 = sub i64 %ins224, %tmp123 ; <i64> [#uses=2]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %sr1.1.ph ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb41.bb42_crit_edge, label %bb40
+
+bb41.bb42_crit_edge: ; preds = %bb40
+ %phitmp278 = zext i32 %tmp122 to i64 ; <i64> [#uses=1]
+ %tmp125 = shl i64 %ins169, 1 ; <i64> [#uses=1]
+ %tmp126 = or i64 %phitmp278, %tmp125 ; <i64> [#uses=2]
+ ret i64 %tmp126
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/Atomics-32.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/Atomics-32.ll
index f3246fd..03905a3 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/Atomics-32.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/Atomics-32.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
; ModuleID = 'Atomics.c'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin9"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/Atomics-64.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/Atomics-64.ll
index c3de710..1dc4310 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/Atomics-64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/Atomics-64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc64
; ModuleID = 'Atomics.c'
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc64-apple-darwin9"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-alloca.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-alloca.ll
index 0a653e8..25fc626 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-alloca.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-alloca.ll
@@ -1,10 +1,10 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32
-; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC64
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-NOFP
-; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-NOFP
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC64
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-NOFP
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-NOFP
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP
; CHECK-PPC32: stw r31, 20(r1)
; CHECK-PPC32: lwz r1, 0(r1)
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-leaf.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-leaf.ll
index 11b6470..c2e1d6b 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-leaf.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-leaf.ll
@@ -1,34 +1,34 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: not grep {stw r31, 20(r1)}
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: not grep {stwu r1, -.*(r1)}
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: not grep {addi r1, r1, }
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: not grep {lwz r31, 20(r1)}
-; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \
+; RUN: llc < %s -march=ppc32 -disable-fp-elim | \
; RUN: not grep {stw r31, 20(r1)}
-; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \
+; RUN: llc < %s -march=ppc32 -disable-fp-elim | \
; RUN: not grep {stwu r1, -.*(r1)}
-; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \
+; RUN: llc < %s -march=ppc32 -disable-fp-elim | \
; RUN: not grep {addi r1, r1, }
-; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \
+; RUN: llc < %s -march=ppc32 -disable-fp-elim | \
; RUN: not grep {lwz r31, 20(r1)}
-; RUN: llvm-as < %s | llc -march=ppc64 | \
+; RUN: llc < %s -march=ppc64 | \
; RUN: not grep {std r31, 40(r1)}
-; RUN: llvm-as < %s | llc -march=ppc64 | \
+; RUN: llc < %s -march=ppc64 | \
; RUN: not grep {stdu r1, -.*(r1)}
-; RUN: llvm-as < %s | llc -march=ppc64 | \
+; RUN: llc < %s -march=ppc64 | \
; RUN: not grep {addi r1, r1, }
-; RUN: llvm-as < %s | llc -march=ppc64 | \
+; RUN: llc < %s -march=ppc64 | \
; RUN: not grep {ld r31, 40(r1)}
-; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \
+; RUN: llc < %s -march=ppc64 -disable-fp-elim | \
; RUN: not grep {stw r31, 40(r1)}
-; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \
+; RUN: llc < %s -march=ppc64 -disable-fp-elim | \
; RUN: not grep {stdu r1, -.*(r1)}
-; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \
+; RUN: llc < %s -march=ppc64 -disable-fp-elim | \
; RUN: not grep {addi r1, r1, }
-; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \
+; RUN: llc < %s -march=ppc64 -disable-fp-elim | \
; RUN: not grep {ld r31, 40(r1)}
define i32* @f1() {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-small.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-small.ll
index c12dd44..6875704 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-small.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/Frames-small.ll
@@ -1,25 +1,21 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1
; RUN not grep {stw r31, 20(r1)} %t1
; RUN: grep {stwu r1, -16448(r1)} %t1
; RUN: grep {addi r1, r1, 16448} %t1
-; RUN: llvm-as < %s | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: not grep {lwz r31, 20(r1)}
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
; RUN: -o %t2
; RUN: grep {stw r31, 20(r1)} %t2
; RUN: grep {stwu r1, -16448(r1)} %t2
; RUN: grep {addi r1, r1, 16448} %t2
; RUN: grep {lwz r31, 20(r1)} %t2
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3
; RUN: not grep {std r31, 40(r1)} %t3
; RUN: grep {stdu r1, -16496(r1)} %t3
; RUN: grep {addi r1, r1, 16496} %t3
; RUN: not grep {ld r31, 40(r1)} %t3
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
; RUN: -o %t4
; RUN: grep {std r31, 40(r1)} %t4
; RUN: grep {stdu r1, -16496(r1)} %t4
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
index 1705379..0f7acac 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \
; RUN: grep {stw r3, 32751}
-; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin | \
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
; RUN: grep {stw r3, 32751}
-; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin | \
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
; RUN: grep {std r2, 9024}
define void @test() {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/addc.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/addc.ll
index 3e6fe27..09a7fbd 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/addc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/addc.ll
@@ -1,5 +1,5 @@
; All of these should be codegen'd without loading immediates
-; RUN: llvm-as < %s | llc -march=ppc32 -o %t
+; RUN: llc < %s -march=ppc32 -o %t
; RUN: grep addc %t | count 1
; RUN: grep adde %t | count 1
; RUN: grep addze %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/addi-reassoc.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/addi-reassoc.ll
index bee8660..2b71ce6 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/addi-reassoc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/addi-reassoc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep addi
+; RUN: llc < %s -march=ppc32 | not grep addi
%struct.X = type { [5 x i8] }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/align.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/align.ll
index 7ffbe36..e619faa 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/align.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/align.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep align.4 | count 1
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep align.2 | count 1
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep align.3 | count 1
@A = global <4 x i32> < i32 10, i32 20, i32 30, i32 40 > ; <<4 x i32>*> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/and-branch.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/and-branch.ll
index f0bb5ea..0484f88 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/and-branch.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/and-branch.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep mfcr
+; RUN: llc < %s -march=ppc32 | not grep mfcr
define void @foo(i32 %X, i32 %Y, i32 %Z) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/and-elim.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/and-elim.ll
index eef8f51..3685361 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/and-elim.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/and-elim.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwin
+; RUN: llc < %s -march=ppc32 | not grep rlwin
define void @test(i8* %P) {
%W = load i8* %P
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/and-imm.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/and-imm.ll
index 9c80649..64a45e5 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/and-imm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/and-imm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep {ori\\|lis}
+; RUN: llc < %s -march=ppc32 | not grep {ori\\|lis}
; andi. r3, r3, 32769
define i32 @test(i32 %X) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/and_add.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/and_add.ll
index b034841..517e775 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/and_add.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/and_add.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -o %t
+; RUN: llc < %s -march=ppc32 -o %t
; RUN: grep slwi %t
; RUN: not grep addi %t
; RUN: not grep rlwinm %t
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/and_sext.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/and_sext.ll
index e0e498d..c6d234e 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/and_sext.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/and_sext.ll
@@ -1,6 +1,6 @@
; These tests should not contain a sign extend.
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsh
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsb
+; RUN: llc < %s -march=ppc32 | not grep extsh
+; RUN: llc < %s -march=ppc32 | not grep extsb
define i32 @test1(i32 %mode.0.i.0) {
%tmp.79 = trunc i32 %mode.0.i.0 to i16
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/and_sra.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/and_sra.ll
index c780605..e6c02d8 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/and_sra.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/and_sra.ll
@@ -1,5 +1,5 @@
; Neither of these functions should contain algebraic right shifts
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep srawi
+; RUN: llc < %s -march=ppc32 | not grep srawi
define i32 @test1(i32 %mode.0.i.0) {
%tmp.79 = bitcast i32 %mode.0.i.0 to i32 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/atomic-1.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/atomic-1.ll
index f6bb298..ec4e42d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/atomic-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/atomic-1.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep lwarx | count 3
-; RUN: llvm-as < %s | llc -march=ppc32 | grep stwcx. | count 4
+; RUN: llc < %s -march=ppc32 | grep lwarx | count 3
+; RUN: llc < %s -march=ppc32 | grep stwcx. | count 4
define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
%tmp = call i32 @llvm.atomic.load.add.i32( i32* %mem, i32 %val )
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/atomic-2.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/atomic-2.ll
index 77b7b08..6d9daef 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/atomic-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/atomic-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc64 | grep ldarx | count 3
-; RUN: llvm-as < %s | llc -march=ppc64 | grep stdcx. | count 4
+; RUN: llc < %s -march=ppc64 | grep ldarx | count 3
+; RUN: llc < %s -march=ppc64 | grep stdcx. | count 4
define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
%tmp = call i64 @llvm.atomic.load.add.i64( i64* %mem, i64 %val )
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/available-externally.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/available-externally.ll
index 6c06529..fdead7d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/available-externally.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/available-externally.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -relocation-model=static | FileCheck %s -check-prefix=STATIC
-; RUN: llvm-as < %s | llc -relocation-model=pic | FileCheck %s -check-prefix=PIC
-; RUN: llvm-as < %s | llc -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC
+; RUN: llc < %s -relocation-model=static | FileCheck %s -check-prefix=STATIC
+; RUN: llc < %s -relocation-model=pic | FileCheck %s -check-prefix=PIC
+; RUN: llc < %s -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC
; PR4482
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "powerpc-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-actual-args.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-actual-args.ll
index d239357..009f468 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-actual-args.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-actual-args.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep {addc 4, 4, 6}
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep {adde 3, 3, 5}
define i64 @foo(i64 %x, i64 %y) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-call-result.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-call-result.ll
index ab136f6..fe85404 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-call-result.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-call-result.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep {addic 4, 4, 1}
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep {addze 3, 3}
declare i64 @foo()
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-formal-args.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-formal-args.ll
index 08589f4..e46e1ec 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-formal-args.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/big-endian-formal-args.ll
@@ -1,10 +1,10 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep {li 6, 3}
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep {li 4, 2}
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep {li 3, 0}
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep {mr 5, 3}
declare void @bar(i64 %x, i64 %y)
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/branch-opt.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/branch-opt.ll
index 4aa55a3..cc02e40 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/branch-opt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/branch-opt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep {b LBB.*} | count 4
target datalayout = "E-p:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/bswap-load-store.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/bswap-load-store.ll
index e450eb8..7eb3bbb 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/bswap-load-store.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/bswap-load-store.ll
@@ -1,11 +1,11 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwinm
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwimi
-; RUN: llvm-as < %s | llc -march=ppc64 | \
+; RUN: llc < %s -march=ppc32 | not grep rlwinm
+; RUN: llc < %s -march=ppc32 | not grep rlwimi
+; RUN: llc < %s -march=ppc64 | \
; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4
-; RUN: llvm-as < %s | llc -march=ppc64 | not grep rlwinm
-; RUN: llvm-as < %s | llc -march=ppc64 | not grep rlwimi
+; RUN: llc < %s -march=ppc64 | not grep rlwinm
+; RUN: llc < %s -march=ppc64 | not grep rlwimi
define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
%tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/buildvec_canonicalize.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/buildvec_canonicalize.ll
index 20ff3db..0454c58 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/buildvec_canonicalize.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/buildvec_canonicalize.ll
@@ -1,11 +1,9 @@
; There should be exactly one vxor here.
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
+; RUN: llc < %s -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
; RUN: grep vxor | count 1
; There should be exactly one vsplti here.
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
+; RUN: llc < %s -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
; RUN: grep vsplti | count 1
define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/calls.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/calls.ll
index 034c141..0db184f 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/calls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/calls.ll
@@ -1,10 +1,10 @@
; Test various forms of calls.
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep {bl } | count 2
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep {bctrl} | count 1
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep {bla } | count 1
declare void @foo()
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/cmp-cmp.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/cmp-cmp.ll
index 07964d5..35a5e42 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/cmp-cmp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/cmp-cmp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep mfcr
+; RUN: llc < %s -march=ppc32 | not grep mfcr
define void @test(i64 %X) {
%tmp1 = and i64 %X, 3 ; <i64> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/compare-duplicate.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/compare-duplicate.ll
index df2dfdc..f5108c3 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/compare-duplicate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/compare-duplicate.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin8 | not grep slwi
+; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | not grep slwi
define i32 @test(i32 %A, i32 %B) {
%C = sub i32 %B, %A
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/compare-simm.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/compare-simm.ll
index b0ef2d3..5ba0500 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/compare-simm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/compare-simm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
; RUN: grep {cmpwi cr0, r3, -1}
define i32 @test(i32 %x) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/constants.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/constants.ll
index b58f59a..8901e02 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/constants.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/constants.ll
@@ -1,9 +1,9 @@
; All of these routines should be perform optimal load of constants.
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep lis | count 5
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep ori | count 3
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep {li } | count 4
define i32 @f1() {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/cr_spilling.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/cr_spilling.ll
index 4584c71..b215868 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/cr_spilling.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/cr_spilling.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o -
+; RUN: llc < %s -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o -
; PR1638
@.str242 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/cttz.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/cttz.ll
index 2c51e8a..ab493a0 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/cttz.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/cttz.ll
@@ -1,5 +1,5 @@
; Make sure this testcase does not use ctpop
-; RUN: llvm-as < %s | llc -march=ppc32 | grep -i cntlzw
+; RUN: llc < %s -march=ppc32 | grep -i cntlzw
declare i32 @llvm.cttz.i32(i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/darwin-labels.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/darwin-labels.ll
index ceebc70..af23369 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/darwin-labels.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/darwin-labels.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep {foo bar":}
+; RUN: llc < %s | grep {foo bar":}
target datalayout = "E-p:32:32"
target triple = "powerpc-apple-darwin8.2.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/delete-node.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/delete-node.ll
index 0b1d734..a26c211 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/delete-node.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/delete-node.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
; The DAGCombiner leaves behind a dead node in this testcase. Currently
; ISel is ignoring dead nodes, though it would be preferable for
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/div-2.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/div-2.ll
index 26e6221..2fc916f 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/div-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/div-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep srawi
-; RUN: llvm-as < %s | llc -march=ppc32 | grep blr
+; RUN: llc < %s -march=ppc32 | not grep srawi
+; RUN: llc < %s -march=ppc32 | grep blr
define i32 @test1(i32 %X) {
%Y = and i32 %X, 15 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
index 7be8a34..558fd1b 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
@@ -1,12 +1,12 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep eqv | count 3
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
; RUN: grep andc | count 3
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep orc | count 2
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
; RUN: grep nor | count 3
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep nand | count 1
define i32 @EQV1(i32 %X, i32 %Y) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/extsh.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/extsh.ll
index 5eca8ce..506ff86 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/extsh.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/extsh.ll
@@ -1,5 +1,5 @@
; This should turn into a single extsh
-; RUN: llvm-as < %s | llc -march=ppc32 | grep extsh | count 1
+; RUN: llc < %s -march=ppc32 | grep extsh | count 1
define i32 @test(i32 %X) {
%tmp.81 = shl i32 %X, 16 ; <i32> [#uses=1]
%tmp.82 = ashr i32 %tmp.81, 16 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/fabs.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/fabs.ll
index 54e49b0..6ef740f 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/fabs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/fabs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin | grep {fabs f1, f1}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | grep {fabs f1, f1}
define double @fabs(double %f) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/fma.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/fma.ll
index 4a6fe70..815c72c 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/fma.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/fma.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: egrep {fn?madd|fn?msub} | count 8
define double @test_FMADD1(double %A, double %B, double %C) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/fnabs.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/fnabs.ll
index 6c10dfb..bbd5c71 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/fnabs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/fnabs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep fnabs
+; RUN: llc < %s -march=ppc32 | grep fnabs
declare double @fabs(double)
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/fneg.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/fneg.ll
index 9579a74..0bd31bb 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/fneg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/fneg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep fneg
+; RUN: llc < %s -march=ppc32 | not grep fneg
define double @test1(double %a, double %b, double %c, double %d) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/fold-li.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/fold-li.ll
index 2ac79f1..92d8da5 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/fold-li.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/fold-li.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | \
+; RUN: llc < %s -march=ppc32 | \
; RUN: grep -v align | not grep li
;; Test that immediates are folded into these instructions correctly.
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/fp-branch.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/fp-branch.ll
index 3db6ced..673da02 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/fp-branch.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/fp-branch.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep fcmp | count 1
+; RUN: llc < %s -march=ppc32 | grep fcmp | count 1
declare i1 @llvm.isunordered.f64(double, double)
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/fp-int-fp.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/fp-int-fp.ll
index 1b78b01..18f7f83 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/fp-int-fp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/fp-int-fp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep r1
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep r1
define double @test1(double %X) {
%Y = fptosi double %X to i64 ; <i64> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/fp_to_uint.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/fp_to_uint.ll
index 43502bb..1360b62 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/fp_to_uint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/fp_to_uint.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep fctiwz | count 1
+; RUN: llc < %s -march=ppc32 | grep fctiwz | count 1
define i16 @foo(float %a) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/fpcopy.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/fpcopy.ll
index 7d80596..7b9446b 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/fpcopy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/fpcopy.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep fmr
+; RUN: llc < %s -march=ppc32 | not grep fmr
define double @test(float %F) {
%F.upgrd.1 = fpext float %F to double ; <double> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/frounds.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/frounds.ll
index 0d8e621..8eeadc3 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/frounds.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/frounds.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
define i32 @foo() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/fsqrt.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/fsqrt.ll
index 1260c60..74a8725 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/fsqrt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/fsqrt.ll
@@ -1,17 +1,13 @@
; fsqrt should be generated when the fsqrt feature is enabled, but not
; otherwise.
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
; RUN: grep {fsqrt f1, f1}
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
-; RUN: grep {fsqrt f1, f1}
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
+; RUN: grep {fsqrt f1, f1}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
; RUN: not grep {fsqrt f1, f1}
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \
; RUN: not grep {fsqrt f1, f1}
declare double @llvm.sqrt.f64(double)
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/hello.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/hello.ll
index 1d7275f..ea27e92 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/hello.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/hello.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -march=ppc64
; PR1399
@.str = internal constant [13 x i8] c"Hello World!\00"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/hidden-vis-2.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/hidden-vis-2.ll
index 4c9ae55..e9e2c0a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/hidden-vis-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/hidden-vis-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin9 | grep non_lazy_ptr | count 6
+; RUN: llc < %s -mtriple=powerpc-apple-darwin9 | grep non_lazy_ptr | count 6
@x = external hidden global i32 ; <i32*> [#uses=1]
@y = extern_weak hidden global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/hidden-vis.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/hidden-vis.ll
index e04c89a..b2cc143 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/hidden-vis.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/hidden-vis.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin9 | not grep non_lazy_ptr
+; RUN: llc < %s -mtriple=powerpc-apple-darwin9 | not grep non_lazy_ptr
@x = weak hidden global i32 0 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/i128-and-beyond.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/i128-and-beyond.ll
index 9e0d6c3..51bcab2 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/i128-and-beyond.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/i128-and-beyond.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep 4294967295 | count 28
+; RUN: llc < %s -march=ppc32 | grep 4294967295 | count 28
; These static initializers are too big to hand off to assemblers
; as monolithic blobs.
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/i64_fp.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/i64_fp.ll
index 5ff2684..d53c948 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/i64_fp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/i64_fp.ll
@@ -1,21 +1,21 @@
; fcfid and fctid should be generated when the 64bit feature is enabled, but not
; otherwise.
-; RUN: llvm-as < %s | llc -march=ppc32 -mattr=+64bit | \
+; RUN: llc < %s -march=ppc32 -mattr=+64bit | \
; RUN: grep fcfid
-; RUN: llvm-as < %s | llc -march=ppc32 -mattr=+64bit | \
+; RUN: llc < %s -march=ppc32 -mattr=+64bit | \
; RUN: grep fctidz
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
; RUN: grep fcfid
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
; RUN: grep fctidz
-; RUN: llvm-as < %s | llc -march=ppc32 -mattr=-64bit | \
+; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
; RUN: not grep fcfid
-; RUN: llvm-as < %s | llc -march=ppc32 -mattr=-64bit | \
+; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
; RUN: not grep fctidz
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g4 | \
+; RUN: llc < %s -march=ppc32 -mcpu=g4 | \
; RUN: not grep fcfid
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g4 | \
+; RUN: llc < %s -march=ppc32 -mcpu=g4 | \
; RUN: not grep fctidz
define double @X(double %Y) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/iabs.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/iabs.ll
index 677b41b..a43f09c 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/iabs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/iabs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -stats |& \
+; RUN: llc < %s -march=ppc32 -stats |& \
; RUN: grep {4 .*Number of machine instrs printed}
;; Integer absolute value, should produce something as good as:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/illegal-element-type.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/illegal-element-type.ll
index 54a0665..58bd055 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/illegal-element-type.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/illegal-element-type.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3
+; RUN: llc < %s -march=ppc32 -mcpu=g3
define void @foo() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/inlineasm-copy.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/inlineasm-copy.ll
index c0a3979..e1ff82d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/inlineasm-copy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/inlineasm-copy.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep mr
+; RUN: llc < %s -march=ppc32 | not grep mr
define i32 @test(i32 %Y, i32 %X) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/int-fp-conv-0.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/int-fp-conv-0.ll
index 82a1826..983d2b8 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/int-fp-conv-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/int-fp-conv-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64 > %t
+; RUN: llc < %s -march=ppc64 > %t
; RUN: grep __floattitf %t
; RUN: grep __fixunstfti %t
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/int-fp-conv-1.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/int-fp-conv-1.ll
index 583408c..6c82723 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/int-fp-conv-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/int-fp-conv-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64 | grep __floatditf
+; RUN: llc < %s -march=ppc64 | grep __floatditf
define i64 @__fixunstfdi(ppc_fp128 %a) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/invalid-memcpy.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/invalid-memcpy.ll
index 6df968d..3b1f306 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/invalid-memcpy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/invalid-memcpy.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -march=ppc64
; This testcase is invalid (the alignment specified for memcpy is
; greater than the alignment guaranteed for Qux or C.0.1173, but it
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/inverted-bool-compares.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/inverted-bool-compares.ll
index f8c5f11..aa7e4d6 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/inverted-bool-compares.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/inverted-bool-compares.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep xori
+; RUN: llc < %s -march=ppc32 | not grep xori
define i32 @test(i1 %B, i32* %P) {
br i1 %B, label %T, label %F
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/ispositive.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/ispositive.ll
index 192d738..4161e34 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/ispositive.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/ispositive.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
; RUN: grep {srwi r3, r3, 31}
define i32 @test1(i32 %X) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/itofp128.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/itofp128.ll
index 4d74511..6d9ef95 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/itofp128.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/itofp128.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc64
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc64-apple-darwin9.2.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/lha.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/lha.ll
index e8f73ee..3a100c1 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/lha.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/lha.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep lha
+; RUN: llc < %s -march=ppc32 | grep lha
define i32 @test(i16* %a) {
%tmp.1 = load i16* %a ; <i16> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/load-constant-addr.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/load-constant-addr.ll
index d2be04e..f1d061c 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/load-constant-addr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/load-constant-addr.ll
@@ -1,6 +1,6 @@
; Should fold the ori into the lfs.
-; RUN: llvm-as < %s | llc -march=ppc32 | grep lfs
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep ori
+; RUN: llc < %s -march=ppc32 | grep lfs
+; RUN: llc < %s -march=ppc32 | not grep ori
define float @test() {
%tmp.i = load float* inttoptr (i32 186018016 to float*) ; <float> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/long-compare.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/long-compare.ll
index 7b90725..94c2526 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/long-compare.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/long-compare.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep cntlzw
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep xori
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep {li }
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep {mr }
+; RUN: llc < %s -march=ppc32 | grep cntlzw
+; RUN: llc < %s -march=ppc32 | not grep xori
+; RUN: llc < %s -march=ppc32 | not grep {li }
+; RUN: llc < %s -march=ppc32 | not grep {mr }
define i1 @test(i64 %x) {
%tmp = icmp ult i64 %x, 4294967296
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/longdbl-truncate.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/longdbl-truncate.ll
index a873824..e5f63c6 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/longdbl-truncate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/longdbl-truncate.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/mask64.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/mask64.ll
index 69d2200..139621a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/mask64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/mask64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc64-apple-darwin9.2.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/mem-rr-addr-mode.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/mem-rr-addr-mode.ll
index fd0e1d4..5661ef9 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/mem-rr-addr-mode.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/mem-rr-addr-mode.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep li.*16
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep addi
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep li.*16
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep addi
; Codegen lvx (R+16) as t = li 16, lvx t,R
; This shares the 16 between the two loads.
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/mem_update.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/mem_update.ll
index a152762..b267719 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/mem_update.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/mem_update.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -enable-ppc-preinc | \
+; RUN: llc < %s -march=ppc32 -enable-ppc-preinc | \
; RUN: not grep addi
-; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc-preinc | \
+; RUN: llc < %s -march=ppc64 -enable-ppc-preinc | \
; RUN: not grep addi
@Glob = global i64 4 ; <i64*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/mul-neg-power-2.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/mul-neg-power-2.ll
index 90446d7..9688d6e 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/mul-neg-power-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/mul-neg-power-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep mul
+; RUN: llc < %s -march=ppc32 | not grep mul
define i32 @test1(i32 %a) {
%tmp.1 = mul i32 %a, -2 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/mul-with-overflow.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/mul-with-overflow.ll
index 0276846..f03e3cb 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/mul-with-overflow.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/mul-with-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
define i1 @a(i32 %x) zeroext nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/mulhs.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/mulhs.ll
index e6e7b5c..9ab8d99 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/mulhs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/mulhs.ll
@@ -1,5 +1,5 @@
; All of these ands and shifts should be folded into rlwimi's
-; RUN: llvm-as < %s | llc -march=ppc32 -o %t
+; RUN: llc < %s -march=ppc32 -o %t
; RUN: not grep mulhwu %t
; RUN: not grep srawi %t
; RUN: not grep add %t
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/multiple-return-values.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/multiple-return-values.ll
index 3f75f7d..b9317f9 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/multiple-return-values.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/multiple-return-values.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -march=ppc64
define {i64, float} @bar(i64 %a, float %b) {
%y = add i64 %a, 7
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/neg.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/neg.ll
index c135599..c673912 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/neg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/neg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep neg
+; RUN: llc < %s -march=ppc32 | grep neg
define i32 @test(i32 %X) {
%Y = sub i32 0, %X ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/no-dead-strip.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/no-dead-strip.ll
index e7ceaae..3459413 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/no-dead-strip.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/no-dead-strip.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep {no_dead_strip.*_X}
+; RUN: llc < %s | grep {no_dead_strip.*_X}
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "powerpc-apple-darwin8.8.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/or-addressing-mode.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/or-addressing-mode.ll
index 9b6e955..e50374e 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/or-addressing-mode.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/or-addressing-mode.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin8 | not grep ori
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin8 | not grep rlwimi
+; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | not grep ori
+; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | not grep rlwimi
define i32 @test1(i8* %P) {
%tmp.2.i = ptrtoint i8* %P to i32 ; <i32> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-1-opt.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-1-opt.ll
index e3c5ab1..2fc1720 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-1-opt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-1-opt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc > %t
+; RUN: llc < %s > %t
; ModuleID = '<stdin>'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-1.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-1.ll
index a487de7..1047fe5 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -std-compile-opts | llc > %t
+; RUN: opt < %s -std-compile-opts | llc > %t
; ModuleID = 'ld3.c'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-2.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-2.ll
index 4318226..7eee354 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc64
define i64 @__fixtfdi(ppc_fp128 %a) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-3.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-3.ll
index 3a51f4d..5043b62 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
%struct.stp_sequence = type { double, double }
define i32 @stp_sequence_set_short_data(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-4.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-4.ll
index 16d6178..104a25e 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/ppcf128-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
define ppc_fp128 @__floatditf(i64 %u) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/pr3711_widen_bit.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/pr3711_widen_bit.ll
index e601e96..7abdeda 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/pr3711_widen_bit.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/pr3711_widen_bit.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
+; RUN: llc < %s -march=ppc32 -mcpu=g5
; Test that causes a abort in expanding a bit convert due to a missing support
; for widening.
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/private.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/private.ll
index 30cf938..d6e6770 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/private.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/private.ll
@@ -1,11 +1,11 @@
; Test to make sure that the 'private' is used correctly.
;
-; RUN: llvm-as < %s | llc -mtriple=powerpc-unknown-linux-gnu > %t
+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu > %t
; RUN: grep .Lfoo: %t
; RUN: grep bl.*\.Lfoo %t
; RUN: grep .Lbaz: %t
; RUN: grep lis.*\.Lbaz %t
-; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin > %t
+; RUN: llc < %s -mtriple=powerpc-apple-darwin > %t
; RUN: grep L_foo: %t
; RUN: grep bl.*\L_foo %t
; RUN: grep L_baz: %t
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/reg-coalesce-simple.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/reg-coalesce-simple.ll
index b86ed1a..e0ddb42 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/reg-coalesce-simple.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/reg-coalesce-simple.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep or
+; RUN: llc < %s -march=ppc32 | not grep or
%struct.foo = type { i32, i32, [0 x i8] }
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/retaddr.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/retaddr.ll
index f4cad34..9f8647d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/retaddr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/retaddr.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep mflr
-; RUN: llvm-as < %s | llc -march=ppc32 | grep lwz
-; RUN: llvm-as < %s | llc -march=ppc64 | grep {ld r., 16(r1)}
+; RUN: llc < %s -march=ppc32 | grep mflr
+; RUN: llc < %s -march=ppc32 | grep lwz
+; RUN: llc < %s -march=ppc64 | grep {ld r., 16(r1)}
target triple = "powerpc-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/return-val-i128.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/return-val-i128.ll
index 27a5004..e14a438 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/return-val-i128.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/return-val-i128.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64
+; RUN: llc < %s -march=ppc64
define i128 @__fixsfdi(float %a) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi-commute.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi-commute.ll
index f8a42b5..6410c63 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi-commute.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi-commute.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwimi
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep {or }
+; RUN: llc < %s -march=ppc32 | grep rlwimi
+; RUN: llc < %s -march=ppc32 | not grep {or }
; Make sure there is no register-register copies here.
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi.ll
index 5e310bb..556ca3d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi.ll
@@ -1,6 +1,6 @@
; All of these ands and shifts should be folded into rlwimi's
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep and
-; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwimi | count 8
+; RUN: llc < %s -march=ppc32 | not grep and
+; RUN: llc < %s -march=ppc32 | grep rlwimi | count 8
define i32 @test1(i32 %x, i32 %y) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi2.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi2.ll
index 3cb2e7b..59a3655 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi2.ll
@@ -1,5 +1,5 @@
; All of these ands and shifts should be folded into rlwimi's
-; RUN: llvm-as < %s | llc -march=ppc32 -o %t
+; RUN: llc < %s -march=ppc32 -o %t
; RUN: grep rlwimi %t | count 3
; RUN: grep srwi %t | count 1
; RUN: not grep slwi %t
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi3.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi3.ll
index fedcfbf..05d37bf 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwimi3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -stats |& \
+; RUN: llc < %s -march=ppc32 -stats |& \
; RUN: grep {Number of machine instrs printed} | grep 12
define i16 @Trans16Bit(i32 %srcA, i32 %srcB, i32 %alpha) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwinm.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwinm.ll
index d92b77c..699f6e7 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwinm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwinm.ll
@@ -1,5 +1,5 @@
; All of these ands and shifts should be folded into rlwimi's
-; RUN: llvm-as < %s | llc -march=ppc32 -o %t
+; RUN: llc < %s -march=ppc32 -o %t
; RUN: not grep and %t
; RUN: not grep srawi %t
; RUN: not grep srwi %t
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwinm2.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwinm2.ll
index 7ddea4e..46542d8 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwinm2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/rlwinm2.ll
@@ -1,5 +1,5 @@
; All of these ands and shifts should be folded into rlw[i]nm instructions
-; RUN: llvm-as < %s | llc -march=ppc32 -o %t
+; RUN: llc < %s -march=ppc32 -o %t
; RUN: not grep and %t
; RUN: not grep srawi %t
; RUN: not grep srwi %t
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl-2.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl-2.ll
index df10459..d32ef59 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl-2.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwinm | count 4
-; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwnm | count 2
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep or
+; RUN: llc < %s -march=ppc32 | grep rlwinm | count 4
+; RUN: llc < %s -march=ppc32 | grep rlwnm | count 2
+; RUN: llc < %s -march=ppc32 | not grep or
define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
%shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl-64.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl-64.ll
index 3963d9a..674c9e4 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl-64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl-64.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc64 | grep rldicl
-; RUN: llvm-as < %s | llc -march=ppc64 | grep rldcl
+; RUN: llc < %s -march=ppc64 | grep rldicl
+; RUN: llc < %s -march=ppc64 | grep rldcl
; PR1613
define i64 @t1(i64 %A) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl.ll
index aab5c83..56fc4a8 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/rotl.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwnm | count 2
-; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwinm | count 2
+; RUN: llc < %s -march=ppc32 | grep rlwnm | count 2
+; RUN: llc < %s -march=ppc32 | grep rlwinm | count 2
define i32 @rotlw(i32 %x, i32 %sh) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/sections.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/sections.ll
index 21374d0..1af3709 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/sections.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/sections.ll
@@ -1,5 +1,5 @@
; Test to make sure that bss sections are printed with '.section' directive.
-; RUN: llvm-as < %s | llc -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
@A = global i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/select-cc.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/select-cc.ll
index f9464c4..ccc6489 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/select-cc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/select-cc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32
+; RUN: llc < %s -march=ppc32
; PR3011
define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/select_lt0.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/select_lt0.ll
index 86eb201..95ba84a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/select_lt0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/select_lt0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep cmp
+; RUN: llc < %s -march=ppc32 | not grep cmp
define i32 @seli32_1(i32 %a) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/setcc_no_zext.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/setcc_no_zext.ll
index c31f35c..9b2036e 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/setcc_no_zext.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/setcc_no_zext.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwinm
+; RUN: llc < %s -march=ppc32 | not grep rlwinm
define i32 @setcc_one_or_zero(i32* %a) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/seteq-0.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/seteq-0.ll
index 0f0afe9..688b29a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/seteq-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/seteq-0.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
; RUN: grep {srwi r., r., 5}
define i32 @eq0(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/shift128.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/shift128.ll
index cf5b3fc..8e518c1 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/shift128.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/shift128.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64 | grep sld | count 5
+; RUN: llc < %s -march=ppc64 | grep sld | count 5
define i128 @foo_lshr(i128 %x, i128 %y) {
%r = lshr i128 %x, %y
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/shl_elim.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/shl_elim.ll
index 3dc4772..f177c4a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/shl_elim.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/shl_elim.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep slwi
+; RUN: llc < %s -march=ppc32 | not grep slwi
define i32 @test1(i64 %a) {
%tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/shl_sext.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/shl_sext.ll
index 61e5cdb..1f35eb4 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/shl_sext.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/shl_sext.ll
@@ -1,5 +1,5 @@
; This test should not contain a sign extend
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsb
+; RUN: llc < %s -march=ppc32 | not grep extsb
define i32 @test(i32 %mode.0.i.0) {
%tmp.79 = trunc i32 %mode.0.i.0 to i8 ; <i8> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/sign_ext_inreg1.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/sign_ext_inreg1.ll
index 0e67f77..2679c8e 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/sign_ext_inreg1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/sign_ext_inreg1.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep srwi
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwimi
+; RUN: llc < %s -march=ppc32 | grep srwi
+; RUN: llc < %s -march=ppc32 | not grep rlwimi
define i32 @baz(i64 %a) {
%tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/small-arguments.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/small-arguments.ll
index e211e86..31bcee6 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/small-arguments.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/small-arguments.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep {extsh\\|rlwinm}
+; RUN: llc < %s -march=ppc32 | not grep {extsh\\|rlwinm}
declare i16 @foo() signext
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/stfiwx-2.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/stfiwx-2.ll
index 5c4a834..c49b25c 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/stfiwx-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/stfiwx-2.ll
@@ -1,6 +1,6 @@
; This cannot be a stfiwx
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep stb
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep stfiwx
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep stb
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep stfiwx
define void @test(float %F, i8* %P) {
%I = fptosi float %F to i32
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/stfiwx.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/stfiwx.ll
index 765c326..d1c3f52 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/stfiwx.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/stfiwx.ll
@@ -1,9 +1,7 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=stfiwx -o %t1
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=stfiwx -o %t1
; RUN: grep stfiwx %t1
; RUN: not grep r1 %t1
-; RUN: llvm-as < %s | \
-; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx \
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx \
; RUN: -o %t2
; RUN: not grep stfiwx %t2
; RUN: grep r1 %t2
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/store-load-fwd.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/store-load-fwd.ll
index 5cc4784..25663c1 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/store-load-fwd.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/store-load-fwd.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | not grep lwz
+; RUN: llc < %s -march=ppc32 | not grep lwz
define i32 @test(i32* %P) {
store i32 1, i32* %P
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/subc.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/subc.ll
index 1722074..5914dca 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/subc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/subc.ll
@@ -1,5 +1,5 @@
; All of these should be codegen'd without loading immediates
-; RUN: llvm-as < %s | llc -march=ppc32 -o %t
+; RUN: llc < %s -march=ppc32 -o %t
; RUN: grep subfc %t | count 1
; RUN: grep subfe %t | count 1
; RUN: grep subfze %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcall1-64.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcall1-64.ll
index f39b40b..e9c83a5 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcall1-64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcall1-64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc64 -tailcallopt | grep TC_RETURNd8
+; RUN: llc < %s -march=ppc64 -tailcallopt | grep TC_RETURNd8
define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
entry:
ret i32 %a3
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcall1.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcall1.ll
index 1fc4b94..08f3392 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcall1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcall1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -tailcallopt | grep TC_RETURN
+; RUN: llc < %s -march=ppc32 -tailcallopt | grep TC_RETURN
define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
entry:
ret i32 %a3
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcallpic1.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcallpic1.ll
index 678d366..f3f5028 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcallpic1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/tailcallpic1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -tailcallopt -mtriple=powerpc-apple-darwin -relocation-model=pic | grep TC_RETURN
+; RUN: llc < %s -tailcallopt -mtriple=powerpc-apple-darwin -relocation-model=pic | grep TC_RETURN
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll
index d559a94..8a1288a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR4534
; ModuleID = 'tango.net.ftp.FtpClient.bc'
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/trampoline.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/trampoline.ll
index 530c782..bc05bb1 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/trampoline.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/trampoline.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep {__trampoline_setup}
+; RUN: llc < %s -march=ppc32 | grep {__trampoline_setup}
module asm "\09.lazy_reference .objc_class_name_NSImageRep"
module asm "\09.objc_class_name_NSBitmapImageRep=0"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/unsafe-math.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/unsafe-math.ll
index d211b3b..ef97912 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/unsafe-math.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/unsafe-math.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 | grep fmul | count 2
-; RUN: llvm-as < %s | llc -march=ppc32 -enable-unsafe-fp-math | \
+; RUN: llc < %s -march=ppc32 | grep fmul | count 2
+; RUN: llc < %s -march=ppc32 -enable-unsafe-fp-math | \
; RUN: grep fmul | count 1
define double @foo(double %X) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vcmp-fold.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vcmp-fold.ll
index 815bb0a..7a42c27 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vcmp-fold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vcmp-fold.ll
@@ -1,6 +1,6 @@
; This should fold the "vcmpbfp." and "vcmpbfp" instructions into a single
; "vcmpbfp.".
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vcmpbfp | count 1
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vcmpbfp | count 1
define void @test(<4 x float>* %x, <4 x float>* %y, i32* %P) {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_br_cmp.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_br_cmp.ll
index 8cbab5c..c34d850 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_br_cmp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_br_cmp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 -o %t
+; RUN: llc < %s -march=ppc32 -mcpu=g5 -o %t
; RUN: grep vcmpeqfp. %t
; RUN: not grep mfcr %t
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_call.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_call.ll
index 8e7a08e..4511315 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_call.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_call.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
+; RUN: llc < %s -march=ppc32 -mcpu=g5
define <4 x i32> @test_arg(<4 x i32> %A, <4 x i32> %B) {
%C = add <4 x i32> %A, %B ; <<4 x i32>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_constants.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_constants.ll
index c4b42b9..32c6f48 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_constants.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_constants.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep CPI
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep CPI
define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
%tmp = load <4 x i32>* %P1 ; <<4 x i32>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_fneg.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_fneg.ll
index 9fdbffd..e01e659 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_fneg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_fneg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsubfp
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubfp
define void @t(<4 x float>* %A) {
%tmp2 = load <4 x float>* %A
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_insert.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_insert.ll
index 04bbe65..185454c 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_insert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_insert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep sth
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep sth
define <8 x i16> @insert(<8 x i16> %foo, i16 %a) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_misaligned.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_misaligned.ll
index 15376ca..d7ed64a 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_misaligned.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_misaligned.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
+; RUN: llc < %s -march=ppc32 -mcpu=g5
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_mul.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_mul.ll
index b061fa9..80f4de4 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_mul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_mul.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep mullw
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmsumuhm
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep mullw
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vmsumuhm
define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
%tmp = load <4 x i32>* %X ; <<4 x i32>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll
index 5bb1b60..2c3594d 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vperm
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vperm
define <4 x float> @test_uu72(<4 x float>* %P1, <4 x float>* %P2) {
%V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_shift.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_shift.ll
index 0cc699c..646fb5f 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_shift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_shift.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
+; RUN: llc < %s -march=ppc32 -mcpu=g5
; PR3628
define void @update(<4 x i32> %val, <4 x i32>* %dst) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_shuffle.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_shuffle.ll
index 1289dca..8270632 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_shuffle.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_shuffle.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | opt -instcombine | \
+; RUN: opt < %s -instcombine | \
; RUN: llc -march=ppc32 -mcpu=g5 | not grep vperm
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 > %t
+; RUN: llc < %s -march=ppc32 -mcpu=g5 > %t
; RUN: grep vsldoi %t | count 2
; RUN: grep vmrgh %t | count 7
; RUN: grep vmrgl %t | count 6
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_splat.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_splat.ll
index 7f466bf..6123728 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_splat.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_splat.ll
@@ -1,7 +1,7 @@
; Test that vectors are scalarized/lowered correctly.
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 | \
+; RUN: llc < %s -march=ppc32 -mcpu=g3 | \
; RUN: grep stfs | count 4
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 -o %t
+; RUN: llc < %s -march=ppc32 -mcpu=g5 -o %t
; RUN: grep vspltw %t | count 2
; RUN: grep vsplti %t | count 3
; RUN: grep vsplth %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_vrsave.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_vrsave.ll
index 7d5fadb..2a03d58 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_vrsave.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_vrsave.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 -o %t
+; RUN: llc < %s -march=ppc32 -mcpu=g5 -o %t
; RUN: grep vrlw %t
; RUN: not grep spr %t
; RUN: not grep vrsave %t
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_zero.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_zero.ll
index 7350e91..f862b2c 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_zero.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vec_zero.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vxor
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vxor
define void @foo(<4 x float>* %P) {
%T = load <4 x float>* %P ; <<4 x float>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vector-identity-shuffle.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vector-identity-shuffle.ll
index aefd266..dfa2e35 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vector-identity-shuffle.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vector-identity-shuffle.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep test:
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vperm
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep test:
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vperm
define void @test(<4 x float>* %tmp2.i) {
%tmp2.i.upgrd.1 = load <4 x float>* %tmp2.i ; <<4 x float>> [#uses=4]
diff --git a/libclamav/c++/llvm/test/CodeGen/PowerPC/vector.ll b/libclamav/c++/llvm/test/CodeGen/PowerPC/vector.ll
index a6c17b4..ee4da31 100644
--- a/libclamav/c++/llvm/test/CodeGen/PowerPC/vector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/PowerPC/vector.ll
@@ -1,6 +1,6 @@
; Test that vectors are scalarized/lowered correctly.
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 > %t
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 > %t
+; RUN: llc < %s -march=ppc32 -mcpu=g5 > %t
+; RUN: llc < %s -march=ppc32 -mcpu=g3 > %t
%d8 = type <8 x double>
%f1 = type <1 x float>
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll
index 19c156d..1e61b23 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin
+; RUN: llc < %s -mtriple=thumb-apple-darwin
%struct.rtx_def = type { i8 }
@str = external global [7 x i8]
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/2007-02-02-JoinIntervalsCrash.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/2007-02-02-JoinIntervalsCrash.ll
index ee52cf0..be2b839 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/2007-02-02-JoinIntervalsCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/2007-02-02-JoinIntervalsCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin
+; RUN: llc < %s -mtriple=thumb-apple-darwin
%struct.color_sample = type { i32 }
%struct.ref = type { %struct.color_sample, i16, i16 }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/2007-03-06-AddR7.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/2007-03-06-AddR7.ll
index ad3e195..8d139e9 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/2007-03-06-AddR7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/2007-03-06-AddR7.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=thumb
-; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin -relocation-model=pic \
+; RUN: llc < %s -march=thumb
+; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic \
; RUN: -mattr=+v6,+vfp2 | not grep {add r., r7, #2 \\* 4}
%struct.__fooAllocator = type opaque
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll
index 159be4e..2074bfd 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | not grep r11
+; RUN: llc < %s | not grep r11
target triple = "thumb-linux-gnueabi"
%struct.__sched_param = type { i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-06-18-ThumbCommuteMul.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-06-18-ThumbCommuteMul.ll
index 9b2aba9..5c883b3 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-06-18-ThumbCommuteMul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-06-18-ThumbCommuteMul.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb | grep r0 | count 1
+; RUN: llc < %s -march=thumb | grep r0 | count 1
define i32 @a(i32 %x, i32 %y) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll
index 5fd2e73..471a82f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv6-elf | not grep "subs sp"
+; RUN: llc < %s -mtriple=thumbv6-elf | not grep "subs sp"
; PR4567
define arm_apcscc i8* @__gets_chk(i8* %s, i32 %slen) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll
index 3e18d29..6e035d0 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv6-apple-darwin10
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin10
@Time.2535 = external global i64 ; <i64*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll
index b0dc242..f195348 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv6-apple-darwin -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin -relocation-model=pic -disable-fp-elim
%struct.LinkList = type { i32, %struct.LinkList* }
%struct.List = type { i32, i32* }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll
index 5c13488..ef4b5ce 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv6-apple-darwin
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin
%struct.BF_KEY = type { [18 x i32], [1024 x i32] }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll
index 4c4253d..b6e67b1 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv6-apple-darwin
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin
%struct.vorbis_comment = type { i8**, i32*, i32, i8* }
@.str16 = external constant [2 x i8], align 1 ; <[2 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-20-ISelBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
index 1f0a404..1627f61 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv6-apple-darwin -relocation-model=pic -disable-fp-elim -mattr=+v6 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin -relocation-model=pic -disable-fp-elim -mattr=+v6 | FileCheck %s
; rdar://7157006
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/asmprinter-bug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/asmprinter-bug.ll
index f5553b4..1e3c070 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/asmprinter-bug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/asmprinter-bug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv6-apple-darwin10 | grep rsbs | grep {#0}
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin10 | grep rsbs | grep {#0}
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.__sFILEX = type opaque
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
index cd76250..acfdc91 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=thumb | not grep {ldr sp}
-; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin | \
+; RUN: llc < %s -march=thumb | not grep {ldr sp}
+; RUN: llc < %s -mtriple=thumb-apple-darwin | \
; RUN: not grep {sub.*r7}
-; RUN: llvm-as < %s | llc -march=thumb | grep 4294967280
+; RUN: llc < %s -march=thumb | grep 4294967280
%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/fpconv.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/fpconv.ll
index 2003131..7da36dd 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/fpconv.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/fpconv.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb
+; RUN: llc < %s -march=thumb
define float @f1(double %x) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/fpow.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/fpow.ll
index e5b92ad..be3dc0b 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/fpow.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/fpow.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb
+; RUN: llc < %s -march=thumb
define double @t(double %x, double %y) nounwind optsize {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/frame_thumb.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/frame_thumb.ll
index 270e331..0cac755 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/frame_thumb.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/frame_thumb.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin \
+; RUN: llc < %s -mtriple=thumb-apple-darwin \
; RUN: -disable-fp-elim | not grep {r11}
-; RUN: llvm-as < %s | llc -mtriple=thumb-linux-gnueabi \
+; RUN: llc < %s -mtriple=thumb-linux-gnueabi \
; RUN: -disable-fp-elim | not grep {r11}
define i32 @f() {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/iabs.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/iabs.ll
index 13084f6..d7cdcd8 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/iabs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/iabs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -stats |& \
+; RUN: llc < %s -march=thumb -stats |& \
; RUN: grep {4 .*Number of machine instrs printed}
;; Integer absolute value, should produce something as good as:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/inlineasm-imm-thumb.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/inlineasm-imm-thumb.ll
index 2c872e7..5c8a52a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/inlineasm-imm-thumb.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/inlineasm-imm-thumb.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb
+; RUN: llc < %s -march=thumb
; Test Thumb-mode "I" constraint, for ADD immediate.
define i32 @testI(i32 %x) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/ispositive.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/ispositive.ll
index 5891b1f..eac3ef2 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/ispositive.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/ispositive.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb | FileCheck %s
+; RUN: llc < %s -march=thumb | FileCheck %s
define i32 @test1(i32 %X) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/large-stack.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/large-stack.ll
index f7c9ed0..02de36a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/large-stack.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/large-stack.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb | grep {ldr.*LCP} | count 5
+; RUN: llc < %s -march=thumb | grep {ldr.*LCP} | count 5
define void @test1() {
%tmp = alloca [ 64 x i32 ] , align 4
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/ldr_ext.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/ldr_ext.ll
index 73b97f2..9a28124 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/ldr_ext.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/ldr_ext.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=thumb | FileCheck %s -check-prefix=V5
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+v6 | FileCheck %s -check-prefix=V6
+; RUN: llc < %s -march=thumb | FileCheck %s -check-prefix=V5
+; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s -check-prefix=V6
; rdar://7176514
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/ldr_frame.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/ldr_frame.ll
index 4dd2c47..81782cd 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/ldr_frame.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/ldr_frame.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb | FileCheck %s
+; RUN: llc < %s -march=thumb | FileCheck %s
define i32 @f1() {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/long-setcc.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/long-setcc.ll
index df6d137..8f2d98f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/long-setcc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/long-setcc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb | grep cmp | count 1
+; RUN: llc < %s -march=thumb | grep cmp | count 1
define i1 @t1(i64 %x) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/long.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/long.ll
index 2287443..e3ef44a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/long.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/long.ll
@@ -1,10 +1,10 @@
-; RUN: llvm-as < %s | llc -march=thumb | \
+; RUN: llc < %s -march=thumb | \
; RUN: grep mvn | count 1
-; RUN: llvm-as < %s | llc -march=thumb | \
+; RUN: llc < %s -march=thumb | \
; RUN: grep adc | count 1
-; RUN: llvm-as < %s | llc -march=thumb | \
+; RUN: llc < %s -march=thumb | \
; RUN: grep sbc | count 1
-; RUN: llvm-as < %s | llc -march=thumb | grep __muldi3
+; RUN: llc < %s -march=thumb | grep __muldi3
define i64 @f1() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/long_shift.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/long_shift.ll
index ce16721..2431714 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/long_shift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/long_shift.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb
+; RUN: llc < %s -march=thumb
define i64 @f0(i64 %A, i64 %B) {
%tmp = bitcast i64 %A to i64
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/mul.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/mul.ll
index 90f6e25..c1a2fb2 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/mul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/mul.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=thumb | grep mul | count 3
-; RUN: llvm-as < %s | llc -march=thumb | grep lsl | count 1
+; RUN: llc < %s -march=thumb | grep mul | count 3
+; RUN: llc < %s -march=thumb | grep lsl | count 1
define i32 @f1(i32 %u) {
%tmp = mul i32 %u, %u
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/pop.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/pop.ll
new file mode 100644
index 0000000..c5e86ad
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/pop.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
+; rdar://7268481
+
+define arm_apcscc void @t(i8* %a, ...) nounwind {
+; CHECK: t:
+; CHECK: pop {r3}
+; CHECK-NEXT: add sp, #3 * 4
+; CHECK-NEXT: bx r3
+entry:
+ %a.addr = alloca i8*
+ store i8* %a, i8** %a.addr
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/push.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/push.ll
new file mode 100644
index 0000000..63773c4
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/push.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-fp-elim | FileCheck %s
+; rdar://7268481
+
+define arm_apcscc void @t() nounwind {
+; CHECK: t:
+; CHECK-NEXT : push {r7}
+entry:
+ call void asm sideeffect ".long 0xe7ffdefe", ""() nounwind
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/select.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/select.ll
index ae75549..7a183b0 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/select.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/select.ll
@@ -1,10 +1,10 @@
-; RUN: llvm-as < %s | llc -march=thumb | grep beq | count 1
-; RUN: llvm-as < %s | llc -march=thumb | grep bgt | count 1
-; RUN: llvm-as < %s | llc -march=thumb | grep blt | count 3
-; RUN: llvm-as < %s | llc -march=thumb | grep ble | count 1
-; RUN: llvm-as < %s | llc -march=thumb | grep bls | count 1
-; RUN: llvm-as < %s | llc -march=thumb | grep bhi | count 1
-; RUN: llvm-as < %s | llc -march=thumb | grep __ltdf2
+; RUN: llc < %s -march=thumb | grep beq | count 1
+; RUN: llc < %s -march=thumb | grep bgt | count 1
+; RUN: llc < %s -march=thumb | grep blt | count 3
+; RUN: llc < %s -march=thumb | grep ble | count 1
+; RUN: llc < %s -march=thumb | grep bls | count 1
+; RUN: llc < %s -march=thumb | grep bhi | count 1
+; RUN: llc < %s -march=thumb | grep __ltdf2
define i32 @f1(i32 %a.s) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/stack-frame.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/stack-frame.ll
index 756d257..b103b33 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/stack-frame.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/stack-frame.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=thumb
-; RUN: llvm-as < %s | llc -march=thumb | grep add | count 1
+; RUN: llc < %s -march=thumb
+; RUN: llc < %s -march=thumb | grep add | count 1
define void @f1() {
%c = alloca i8, align 1
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/thumb-imm.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/thumb-imm.ll
index 2be393a..74a57ff 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/thumb-imm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/thumb-imm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb | not grep CPI
+; RUN: llc < %s -march=thumb | not grep CPI
define i32 @test1() {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/tst_teq.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/tst_teq.ll
index 0456951..21ada3e 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/tst_teq.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/tst_teq.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb | grep tst
+; RUN: llc < %s -march=thumb | grep tst
define i32 @f(i32 %a) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/unord.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/unord.ll
index 4202d26..39458ae 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/unord.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/unord.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=thumb | grep bne | count 1
-; RUN: llvm-as < %s | llc -march=thumb | grep beq | count 1
+; RUN: llc < %s -march=thumb | grep bne | count 1
+; RUN: llc < %s -march=thumb | grep beq | count 1
define i32 @f1(float %X, float %Y) {
%tmp = fcmp uno float %X, %Y
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb/vargs.ll b/libclamav/c++/llvm/test/CodeGen/Thumb/vargs.ll
index a18010f..16a9c44 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb/vargs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb/vargs.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=thumb
-; RUN: llvm-as < %s | llc -mtriple=thumb-linux | grep pop | count 1
-; RUN: llvm-as < %s | llc -mtriple=thumb-darwin | grep pop | count 2
+; RUN: llc < %s -march=thumb
+; RUN: llc < %s -mtriple=thumb-linux | grep pop | count 1
+; RUN: llc < %s -mtriple=thumb-darwin | grep pop | count 2
@str = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll
index c1fceee..8f2283f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
target triple = "thumbv6t2-elf"
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
index 0766a57..ec649c3 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mattr=+vfp2,+thumb2 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+vfp2,+thumb2 | FileCheck %s
; rdar://7076238
@"\01LC" = external constant [36 x i8], align 1 ; <[36 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll
index 9d208ce..4d21f9b 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mattr=+vfp2,+thumb2
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+vfp2,+thumb2
; rdar://7083961
define arm_apcscc i32 @value(i64 %b1, i64 %b2) nounwind readonly {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll
index 0330cc5..f74d12e 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.JHUFF_TBL = type { [17 x i8], [256 x i8], i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
index 5a59654..a8e86d5 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s
@csize = external global [100 x [20 x [4 x i8]]] ; <[100 x [20 x [4 x i8]]]*> [#uses=1]
@vsize = external global [100 x [20 x [4 x i8]]] ; <[100 x [20 x [4 x i8]]]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll
index 2f4683a..6cbfd0d 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim
type { void (%"struct.xalanc_1_8::FormatterToXML"*, i16)*, i32 } ; type %0
type { void (%"struct.xalanc_1_8::FormatterToXML"*, i16*)*, i32 } ; type %1
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll
index 3486b71..ebe9d46 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-none-linux-gnueabi
+; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi
; PR4681
%struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i32, i32, [40 x i8] }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll
index 55e24df..319d29b 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -mattr=+neon,+neonfp -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+neon -arm-use-neon-fp -relocation-model=pic -disable-fp-elim
type { %struct.GAP } ; type %0
type { i16, i8, i8 } ; type %1
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll
index 2abcce5..a62b612 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -mattr=+neon,+neonfp -relocation-model=pic -disable-fp-elim -O3
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+neon -arm-use-neon-fp -relocation-model=pic -disable-fp-elim -O3
type { i16, i8, i8 } ; type %0
type { [2 x i32], [2 x i32] } ; type %1
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
index f2a2729..3cbb212 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mattr=+neon,+neonfp
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mattr=+neon,+neonfp | grep fcpys | count 1
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp | grep fcpys | count 1
; rdar://7117307
%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll
index a0fdfd7..acf562c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mattr=+neon,+neonfp
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp
; rdar://7117307
%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll
index 5fc737e..3ada026 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mattr=+neon,+neonfp
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp
; rdar://7117307
%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
index bdc23ba..03f9fac 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s
; PR4659
; PR4682
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-07-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-07-CoalescerBug.ll
index 4cd5b1e..93f5a0f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-07-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-07-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv7-eabi -mattr=+vfp2
+; RUN: llc < %s -mtriple=armv7-eabi -mattr=+vfp2
; PR4686
%a = type { i32 (...)** }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
index ee888d4..090ed2d 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -mattr=+neonfp
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -arm-use-neon-fp
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.JHUFF_TBL = type { [17 x i8], [256 x i8], i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll
index 0d47c50..a0f9918 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=armv7-eabi -mattr=+vfp2
+; RUN: llc < %s -mtriple=armv7-eabi -mattr=+vfp2
; PR4686
@g_d = external global double ; <double*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll
index 4c07aa0..cbe250b 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -mattr=+vfp2
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+vfp2
define arm_apcscc float @t1(i32 %v0) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
new file mode 100644
index 0000000..e84e867
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
@@ -0,0 +1,154 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
+
+%struct.pix_pos = type { i32, i32, i32, i32, i32, i32 }
+
+ at getNeighbour = external global void (i32, i32, i32, i32, %struct.pix_pos*)*, align 4 ; <void (i32, i32, i32, i32, %struct.pix_pos*)**> [#uses=2]
+
+define arm_apcscc void @t() nounwind {
+; CHECK: t:
+; CHECK: ittt eq
+; CHECK-NEXT: addeq
+; CHECK-NEXT: movweq
+; CHECK-NEXT: movteq
+entry:
+ %pix_a.i294 = alloca [4 x %struct.pix_pos], align 4 ; <[4 x %struct.pix_pos]*> [#uses=2]
+ br i1 undef, label %land.rhs, label %lor.end
+
+land.rhs: ; preds = %entry
+ br label %lor.end
+
+lor.end: ; preds = %land.rhs, %entry
+ switch i32 0, label %if.end371 [
+ i32 10, label %if.then366
+ i32 14, label %if.then366
+ ]
+
+if.then366: ; preds = %lor.end, %lor.end
+ unreachable
+
+if.end371: ; preds = %lor.end
+ %arrayidx56.2.i = getelementptr [4 x %struct.pix_pos]* %pix_a.i294, i32 0, i32 2 ; <%struct.pix_pos*> [#uses=1]
+ %arrayidx56.3.i = getelementptr [4 x %struct.pix_pos]* %pix_a.i294, i32 0, i32 3 ; <%struct.pix_pos*> [#uses=1]
+ br i1 undef, label %for.body1857, label %for.end4557
+
+for.body1857: ; preds = %if.end371
+ br i1 undef, label %if.then1867, label %for.cond1933
+
+if.then1867: ; preds = %for.body1857
+ unreachable
+
+for.cond1933: ; preds = %for.body1857
+ br i1 undef, label %for.body1940, label %if.then4493
+
+for.body1940: ; preds = %for.cond1933
+ %shl = shl i32 undef, 2 ; <i32> [#uses=1]
+ %shl1959 = shl i32 undef, 2 ; <i32> [#uses=4]
+ br i1 undef, label %if.then1992, label %if.else2003
+
+if.then1992: ; preds = %for.body1940
+ %tmp14.i302 = load i32* undef ; <i32> [#uses=4]
+ %add.i307452 = or i32 %shl1959, 1 ; <i32> [#uses=1]
+ %sub.i308 = add i32 %shl, -1 ; <i32> [#uses=4]
+ call arm_apcscc void undef(i32 %tmp14.i302, i32 %sub.i308, i32 %shl1959, i32 0, %struct.pix_pos* undef) nounwind
+ %tmp49.i309 = load void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; <void (i32, i32, i32, i32, %struct.pix_pos*)*> [#uses=1]
+ call arm_apcscc void %tmp49.i309(i32 %tmp14.i302, i32 %sub.i308, i32 %add.i307452, i32 0, %struct.pix_pos* null) nounwind
+ %tmp49.1.i = load void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; <void (i32, i32, i32, i32, %struct.pix_pos*)*> [#uses=1]
+ call arm_apcscc void %tmp49.1.i(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.2.i) nounwind
+ call arm_apcscc void undef(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.3.i) nounwind
+ unreachable
+
+if.else2003: ; preds = %for.body1940
+ switch i32 undef, label %if.then2015 [
+ i32 10, label %if.then4382
+ i32 14, label %if.then4382
+ ]
+
+if.then2015: ; preds = %if.else2003
+ br i1 undef, label %if.else2298, label %if.then2019
+
+if.then2019: ; preds = %if.then2015
+ br i1 undef, label %if.then2065, label %if.else2081
+
+if.then2065: ; preds = %if.then2019
+ br label %if.end2128
+
+if.else2081: ; preds = %if.then2019
+ br label %if.end2128
+
+if.end2128: ; preds = %if.else2081, %if.then2065
+ unreachable
+
+if.else2298: ; preds = %if.then2015
+ br i1 undef, label %land.lhs.true2813, label %cond.end2841
+
+land.lhs.true2813: ; preds = %if.else2298
+ br i1 undef, label %cond.end2841, label %cond.true2824
+
+cond.true2824: ; preds = %land.lhs.true2813
+ br label %cond.end2841
+
+cond.end2841: ; preds = %cond.true2824, %land.lhs.true2813, %if.else2298
+ br i1 undef, label %for.cond2882.preheader, label %for.cond2940.preheader
+
+for.cond2882.preheader: ; preds = %cond.end2841
+ %mul3693 = shl i32 undef, 1 ; <i32> [#uses=2]
+ br i1 undef, label %if.then3689, label %if.else3728
+
+for.cond2940.preheader: ; preds = %cond.end2841
+ br label %for.inc3040
+
+for.inc3040: ; preds = %for.inc3040, %for.cond2940.preheader
+ br label %for.inc3040
+
+if.then3689: ; preds = %for.cond2882.preheader
+ %add3695 = add nsw i32 %mul3693, %shl1959 ; <i32> [#uses=1]
+ %mul3697 = shl i32 %add3695, 2 ; <i32> [#uses=2]
+ %arrayidx3705 = getelementptr inbounds i16* undef, i32 1 ; <i16*> [#uses=1]
+ %tmp3706 = load i16* %arrayidx3705 ; <i16> [#uses=1]
+ %conv3707 = sext i16 %tmp3706 to i32 ; <i32> [#uses=1]
+ %add3708 = add nsw i32 %conv3707, %mul3697 ; <i32> [#uses=1]
+ %arrayidx3724 = getelementptr inbounds i16* null, i32 1 ; <i16*> [#uses=1]
+ %tmp3725 = load i16* %arrayidx3724 ; <i16> [#uses=1]
+ %conv3726 = sext i16 %tmp3725 to i32 ; <i32> [#uses=1]
+ %add3727 = add nsw i32 %conv3726, %mul3697 ; <i32> [#uses=1]
+ br label %if.end3770
+
+if.else3728: ; preds = %for.cond2882.preheader
+ %mul3733 = add i32 %shl1959, 1073741816 ; <i32> [#uses=1]
+ %add3735 = add nsw i32 %mul3733, %mul3693 ; <i32> [#uses=1]
+ %mul3737 = shl i32 %add3735, 2 ; <i32> [#uses=2]
+ %tmp3746 = load i16* undef ; <i16> [#uses=1]
+ %conv3747 = sext i16 %tmp3746 to i32 ; <i32> [#uses=1]
+ %add3748 = add nsw i32 %conv3747, %mul3737 ; <i32> [#uses=1]
+ %arrayidx3765 = getelementptr inbounds i16* null, i32 1 ; <i16*> [#uses=1]
+ %tmp3766 = load i16* %arrayidx3765 ; <i16> [#uses=1]
+ %conv3767 = sext i16 %tmp3766 to i32 ; <i32> [#uses=1]
+ %add3768 = add nsw i32 %conv3767, %mul3737 ; <i32> [#uses=1]
+ br label %if.end3770
+
+if.end3770: ; preds = %if.else3728, %if.then3689
+ %vec2_y.1 = phi i32 [ %add3727, %if.then3689 ], [ %add3768, %if.else3728 ] ; <i32> [#uses=0]
+ %vec1_y.2 = phi i32 [ %add3708, %if.then3689 ], [ %add3748, %if.else3728 ] ; <i32> [#uses=0]
+ unreachable
+
+if.then4382: ; preds = %if.else2003, %if.else2003
+ switch i32 undef, label %if.then4394 [
+ i32 10, label %if.else4400
+ i32 14, label %if.else4400
+ ]
+
+if.then4394: ; preds = %if.then4382
+ unreachable
+
+if.else4400: ; preds = %if.then4382, %if.then4382
+ br label %for.cond4451.preheader
+
+for.cond4451.preheader: ; preds = %for.cond4451.preheader, %if.else4400
+ br label %for.cond4451.preheader
+
+if.then4493: ; preds = %for.cond1933
+ unreachable
+
+for.end4557: ; preds = %if.end371
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/carry.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/carry.ll
index a55c16f..de6f6e2 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/carry.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/carry.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i64 @f1(i64 %a, i64 %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/frameless.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/frameless.ll
index 1b6bb62..c3c8cf1 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/frameless.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/frameless.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -disable-fp-elim | not grep mov
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux -disable-fp-elim | not grep mov
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | not grep mov
+; RUN: llc < %s -mtriple=thumbv7-linux -disable-fp-elim | not grep mov
define arm_apcscc void @t() nounwind readnone {
ret void
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/frameless2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/frameless2.ll
index 0fd480e..7cc7b19 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/frameless2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/frameless2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -disable-fp-elim | not grep r7
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | not grep r7
%struct.noise3 = type { [3 x [17 x i32]] }
%struct.noiseguard = type { i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/large-stack.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/large-stack.ll
index d183da4..865b17b 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/large-stack.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/large-stack.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define void @test1() {
; CHECK: test1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/load-global.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/load-global.ll
index 4aad567..4fd4525 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/load-global.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/load-global.ll
@@ -1,11 +1,7 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=thumbv7-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=STATIC
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=thumbv7-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=thumbv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=STATIC
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX
@G = external global i32
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/mul_const.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/mul_const.ll
index 091516a..9a2ec93 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/mul_const.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/mul_const.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; rdar://7069502
define i32 @t1(i32 %v) nounwind readnone {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/pic-load.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/pic-load.ll
index 92862c8..1f8aea9 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/pic-load.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/pic-load.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -relocation-model=pic | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -relocation-model=pic | FileCheck %s
%struct.anon = type { void ()* }
%struct.one_atexit_routine = type { %struct.anon, i32, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-adc.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-adc.ll
index dd1cd1d..702df91 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-adc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-adc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; 734439407618 = 0x000000ab00000002
define i64 @f1(i64 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add.ll
index d4f408f..d42ea71 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add.ll
@@ -1,11 +1,11 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #255
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #256
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #257
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #4094
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #4095
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep #4096
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add | grep lsl | grep #8
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #255
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #256
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #257
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #4094
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #4095
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #4096
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep lsl | grep #8
define i32 @t2ADDrc_255(i32 %lhs) {
%Rd = add i32 %lhs, 255;
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add2.ll
index 2e2d20b..e496654 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; 171 = 0x000000ab
define i32 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add3.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add3.ll
index 1e6341e..8d472cb 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {addw\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#4095} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {addw\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#4095} | count 1
define i32 @f1(i32 %a) {
%tmp = add i32 %a, 4095
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add4.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add4.ll
index 34620bc..b94e84d 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; 171 = 0x000000ab
define i64 @f1(i64 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add5.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add5.ll
index e2d859b..8b3a4f6 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add6.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add6.ll
index ca6df05..0ecaa79 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-add6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i64 @f1(i64 %a, i64 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-and.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-and.ll
index ea5b096..8e2245a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-and.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-and.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-and2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-and2.ll
index 266d256..1e2666f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-and2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-and2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#66846720} | count 5
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#66846720} | count 5
; 171 = 0x000000ab
define i32 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-asr.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-asr.ll
index 82c3661..a0a60e6 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-asr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-asr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-asr2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-asr2.ll
index cdbb742..9c8634f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-asr2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-asr2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bcc.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bcc.ll
index bd40e3b..e1f9cdb 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bcc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bcc.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep it
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it
define i32 @t1(i32 %a, i32 %b, i32 %c) {
; CHECK: t1
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bfc.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bfc.ll
index a612b9b..d33cf7e 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bfc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bfc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "bfc " | count 3
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep "bfc " | count 3
; 4278190095 = 0xff00000f
define i32 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bic.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bic.ll
index 9c799cf..4e35383 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bic.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bic.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
; CHECK: f1:
@@ -69,3 +69,37 @@ define i32 @f8(i32 %a, i32 %b) {
%tmp2 = and i32 %tmp1, %a
ret i32 %tmp2
}
+
+; ~0x000000bb = 4294967108
+define i32 @f9(i32 %a) {
+ %tmp = and i32 %a, 4294967108
+ ret i32 %tmp
+
+; CHECK: f9:
+; CHECK: bic r0, r0, #187
+}
+
+; ~0x00aa00aa = 4283826005
+define i32 @f10(i32 %a) {
+ %tmp = and i32 %a, 4283826005
+ ret i32 %tmp
+
+; CHECK: f10:
+; CHECK: bic r0, r0, #11141290
+}
+
+; ~0xcc00cc00 = 872363007
+define i32 @f11(i32 %a) {
+ %tmp = and i32 %a, 872363007
+ ret i32 %tmp
+; CHECK: f11:
+; CHECK: bic r0, r0, #-872363008
+}
+
+; ~0x00110000 = 4293853183
+define i32 @f12(i32 %a) {
+ %tmp = and i32 %a, 4293853183
+ ret i32 %tmp
+; CHECK: f12:
+; CHECK: bic r0, r0, #1114112
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bic2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bic2.ll
deleted file mode 100644
index b8abdba..0000000
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-bic2.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "bic " | grep {#187\\|#11141290\\|#3422604288\\|#1114112} | count 4
-
-; ~0x000000bb = 4294967108
-define i32 @f1(i32 %a) {
- %tmp = and i32 %a, 4294967108
- ret i32 %tmp
-}
-
-; ~0x00aa00aa = 4283826005
-define i32 @f2(i32 %a) {
- %tmp = and i32 %a, 4283826005
- ret i32 %tmp
-}
-
-; ~0xcc00cc00 = 872363007
-define i32 @f3(i32 %a) {
- %tmp = and i32 %a, 872363007
- ret i32 %tmp
-}
-
-; ~0x00110000 = 4293853183
-define i32 @f4(i32 %a) {
- %tmp = and i32 %a, 4293853183
- ret i32 %tmp
-}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-branch.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-branch.ll
index 1dcaac0..b46cb5f 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-branch.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-branch.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 -disable-arm-if-conversion | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define void @f1(i32 %a, i32 %b, i32* %v) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-call.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-call.ll
index 5265ea6..7dc6b26 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-call.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-call.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s -check-prefix=DARWIN
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux -mattr=+thumb2 | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s -check-prefix=DARWIN
+; RUN: llc < %s -mtriple=thumbv7-linux -mattr=+thumb2 | FileCheck %s -check-prefix=LINUX
@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-clz.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-clz.ll
index e5f94a6..0bed058 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-clz.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-clz.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2,+v7a | grep "clz " | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | grep "clz " | count 1
define i32 @f1(i32 %a) {
%tmp = tail call i32 @llvm.ctlz.i32(i32 %a)
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmn.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmn.ll
index f7dc083..401c56a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmn.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1
define i1 @f1(i32 %a, i32 %b) {
%nb = sub i32 0, %b
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmn2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmn2.ll
index 0946513..c1fcac0 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmn2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmn2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "cmn\\.w " | grep {#187\\|#11141290\\|#3422604288\\|#1114112} | count 4
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep "cmn\\.w " | grep {#187\\|#11141290\\|#-872363008\\|#1114112} | count 4
; -0x000000bb = 4294967109
define i1 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmp.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmp.ll
index 68f3877..d4773bb 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; 0x000000bb = 187
define i1 @f1(i32 %a) {
@@ -19,7 +19,7 @@ define i1 @f2(i32 %a) {
; 0xcc00cc00 = 3422604288
define i1 @f3(i32 %a) {
; CHECK: f3:
-; CHECK: cmp.w r0, #3422604288
+; CHECK: cmp.w r0, #-872363008
%tmp = icmp ne i32 %a, 3422604288
ret i1 %tmp
}
@@ -27,7 +27,7 @@ define i1 @f3(i32 %a) {
; 0xdddddddd = 3722304989
define i1 @f4(i32 %a) {
; CHECK: f4:
-; CHECK: cmp.w r0, #3722304989
+; CHECK: cmp.w r0, #-572662307
%tmp = icmp ne i32 %a, 3722304989
ret i1 %tmp
}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmp2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmp2.ll
index 8bbdb79..55c321d 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmp2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-cmp2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i1 @f1(i32 %a, i32 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-eor.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-eor.ll
index 9d65808..b7e2766 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-eor.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-eor.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-eor2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-eor2.ll
index 11784ca..185634c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-eor2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-eor2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "eor " | grep {#187\\|#11141290\\|#3422604288\\|#1114112\\|#3722304989} | count 5
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep "eor " | grep {#187\\|#11141290\\|#-872363008\\|#1114112\\|#-572662307} | count 5
; 0x000000bb = 187
define i32 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ifcvt1.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
index be1fb6e..71199ab 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK: t1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ifcvt2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
index 299ab4d..d917ffe 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
define void @foo(i32 %X, i32 %Y) {
entry:
@@ -31,7 +31,7 @@ entry:
; CHECK: CountTree:
; CHECK: it eq
; CHECK: cmpeq
-; CHECK: beq.n
+; CHECK: bne
; CHECK: itt eq
; CHECK: moveq
; CHECK: popeq
@@ -82,7 +82,7 @@ define fastcc void @t2() nounwind {
entry:
; CHECK: t2:
; CHECK: cmp r0, #0
-; CHECK: beq.n
+; CHECK: beq
br i1 undef, label %bb.i.i3, label %growMapping.exit
bb.i.i3: ; preds = %entry
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ifcvt3.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ifcvt3.ll
new file mode 100644
index 0000000..1d45d3c
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ifcvt3.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
+
+; There shouldn't be a unconditional branch at end of bb52.
+; rdar://7184787
+
+ at posed = external global i64 ; <i64*> [#uses=1]
+
+define i1 @ab_bb52(i64 %.reload78, i64* %.out, i64* %.out1) nounwind {
+newFuncRoot:
+ br label %bb52
+
+bb52.bb55_crit_edge.exitStub: ; preds = %bb52
+ store i64 %0, i64* %.out
+ store i64 %2, i64* %.out1
+ ret i1 true
+
+bb52.bb53_crit_edge.exitStub: ; preds = %bb52
+ store i64 %0, i64* %.out
+ store i64 %2, i64* %.out1
+ ret i1 false
+
+bb52: ; preds = %newFuncRoot
+; CHECK: movne
+; CHECK: moveq
+; CHECK: pop
+; CHECK-NEXT: LBB1_2:
+ %0 = load i64* @posed, align 4 ; <i64> [#uses=3]
+ %1 = sub i64 %0, %.reload78 ; <i64> [#uses=1]
+ %2 = ashr i64 %1, 1 ; <i64> [#uses=3]
+ %3 = icmp eq i64 %2, 0 ; <i1> [#uses=1]
+ br i1 %3, label %bb52.bb55_crit_edge.exitStub, label %bb52.bb53_crit_edge.exitStub
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-jtb.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-jtb.ll
index ee483ac..7d093ec 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-jtb.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-jtb.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep tbb
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep tbb
; Do not use tbb / tbh if any destination is before the jumptable.
; rdar://7102917
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldm.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldm.ll
index f036557..da2874d 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr.ll
index ef9fb9e..94888fd 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32* %v) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_ext.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_ext.ll
index d48ecef..9e6aef4 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_ext.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_ext.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ldrb | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ldrh | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ldrsb | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ldrsh | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep ldrb | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep ldrh | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep ldrsb | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep ldrsh | count 1
define i32 @test1(i8* %v.pntr.s0.u1) {
%tmp.u = load i8* %v.pntr.s0.u1
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_post.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_post.ll
index 79ffa82..d1af4ba 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_post.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_post.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep {ldr.*\\\[.*\],} | count 1
define i32 @test(i32 %a, i32 %b, i32 %c) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_pre.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_pre.ll
index f773e63..9cc3f4a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_pre.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldr_pre.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep {ldr.*\\!} | count 3
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep {ldrsb.*\\!} | count 1
define i32* @test1(i32* %X, i32* %dest) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldrb.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldrb.ll
index 4fae85b..bf10097 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldrb.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldrb.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i8 @f1(i8* %v) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldrd.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldrd.ll
new file mode 100644
index 0000000..22d4e88
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldrd.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
+
+ at b = external global i64*
+
+define i64 @t(i64 %a) nounwind readonly {
+entry:
+;CHECK: ldrd r2, [r2]
+ %0 = load i64** @b, align 4
+ %1 = load i64* %0, align 4
+ %2 = mul i64 %1, %a
+ ret i64 %2
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldrh.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldrh.ll
index 1993524..f1fb79c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldrh.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ldrh.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i16 @f1(i16* %v) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsl.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsl.ll
index 65c7daa..6b0818a 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsl.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsl2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsl2.ll
index 4bdfd01..f283eef 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsl2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsl2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr.ll
index c60e928..7cbee54 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr2.ll
index 3e20acd..87800f9 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr3.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr3.ll
index 9bc4b5b..5cfd3f5 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-lsr3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2
+; RUN: llc < %s -march=thumb -mattr=+thumb2
define i1 @test1(i64 %poscnt, i32 %work) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mla.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mla.ll
index 0772d7f..be66425 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mla.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mla.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {mla\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 2
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {mla\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 2
define i32 @f1(i32 %a, i32 %b, i32 %c) {
%tmp1 = mul i32 %a, %b
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mls.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mls.ll
index 6d1640f..782def9 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mls.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {mls\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {mls\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1
define i32 @f1(i32 %a, i32 %b, i32 %c) {
%tmp1 = mul i32 %a, %b
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov.ll
index a44f815..e9fdec8 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; Test #<const>
@@ -41,7 +41,7 @@ define i32 @t2_const_var2_1_fail_4(i32 %lhs) {
; var 2.2 - 0xab00ab00
define i32 @t2_const_var2_2_ok_1(i32 %lhs) {
;CHECK: t2_const_var2_2_ok_1:
-;CHECK: #2868947712
+;CHECK: #-1426019584
%ret = add i32 %lhs, 2868947712 ; 0xab00ab00
ret i32 %ret
}
@@ -77,7 +77,7 @@ define i32 @t2_const_var2_2_fail_4(i32 %lhs) {
; var 2.3 - 0xabababab
define i32 @t2_const_var2_3_ok_1(i32 %lhs) {
;CHECK: t2_const_var2_3_ok_1:
-;CHECK: #2880154539
+;CHECK: #-1414812757
%ret = add i32 %lhs, 2880154539 ; 0xabababab
ret i32 %ret
}
@@ -141,7 +141,7 @@ define i32 @t2_const_var3_3_ok_1(i32 %lhs) {
define i32 @t2_const_var3_4_ok_1(i32 %lhs) {
;CHECK: t2_const_var3_4_ok_1:
-;CHECK: #4026531840
+;CHECK: #-268435456
%ret = add i32 %lhs, 4026531840 ; 0xF0000000
ret i32 %ret
}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov2.ll
index d2f8c0b..a02f4f0 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov2.ll
@@ -1,10 +1,11 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt | grep #1234
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep movt
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @t2MOVTi16_ok_1(i32 %a) {
+; CHECK: t2MOVTi16_ok_1:
+; CHECK: movs r1, #0
+; CHECK-NEXT: movt r1, #1234
+; CHECK: movw r1, #65535
+; CHECK-NEXT: movt r1, #1234
%1 = and i32 %a, 65535
%2 = shl i32 1234, 16
%3 = or i32 %1, %2
@@ -13,6 +14,11 @@ define i32 @t2MOVTi16_ok_1(i32 %a) {
}
define i32 @t2MOVTi16_test_1(i32 %a) {
+; CHECK: t2MOVTi16_test_1:
+; CHECK: movs r1, #0
+; CHECK-NEXT: movt r1, #1234
+; CHECK: movw r1, #65535
+; CHECK-NEXT: movt r1, #1234
%1 = shl i32 255, 8
%2 = shl i32 1234, 8
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
@@ -24,6 +30,11 @@ define i32 @t2MOVTi16_test_1(i32 %a) {
}
define i32 @t2MOVTi16_test_2(i32 %a) {
+; CHECK: t2MOVTi16_test_2:
+; CHECK: movs r1, #0
+; CHECK-NEXT: movt r1, #1234
+; CHECK: movw r1, #65535
+; CHECK-NEXT: movt r1, #1234
%1 = shl i32 255, 8
%2 = shl i32 1234, 8
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
@@ -36,6 +47,11 @@ define i32 @t2MOVTi16_test_2(i32 %a) {
}
define i32 @t2MOVTi16_test_3(i32 %a) {
+; CHECK: t2MOVTi16_test_3:
+; CHECK: movs r1, #0
+; CHECK-NEXT: movt r1, #1234
+; CHECK: movw r1, #65535
+; CHECK-NEXT: movt r1, #1234
%1 = shl i32 255, 8
%2 = shl i32 1234, 8
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
@@ -50,6 +66,11 @@ define i32 @t2MOVTi16_test_3(i32 %a) {
}
define i32 @t2MOVTi16_test_nomatch_1(i32 %a) {
+; CHECK: t2MOVTi16_test_nomatch_1:
+; CHECK: movw r1, #16384
+; CHECK-NEXT: movt r1, #154
+; CHECK: movw r1, #65535
+; CHECK-NEXT: movt r1, #154
%1 = shl i32 255, 8
%2 = shl i32 1234, 8
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
@@ -58,7 +79,6 @@ define i32 @t2MOVTi16_test_nomatch_1(i32 %a) {
%6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
%7 = lshr i32 %6, 3
%8 = or i32 %5, %7
-
ret i32 %8
}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov3.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov3.ll
index e64f639..46af6fb 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; 171 = 0x000000ab
define i32 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov4.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov4.ll
index 74c522f..06fa238 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mov4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {movw\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#65535} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {movw\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#65535} | count 1
define i32 @f6(i32 %a) {
%tmp = add i32 0, 65535
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mul.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mul.ll
index 7b57423..b1515b5 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mul.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mulhi.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mulhi.ll
index 7b41509..5d47770 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mulhi.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mulhi.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep smmul | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep umull | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep smmul | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep umull | count 1
define i32 @smulhi(i32 %x, i32 %y) {
%tmp = sext i32 %x to i64 ; <i64> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mvn.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mvn.ll
index 5c560b7..a8c8f83 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mvn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mvn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
; 0x000000bb = 187
define i32 @f1(i32 %a) {
@@ -19,7 +19,7 @@ define i32 @f2(i32 %a) {
; 0xcc00cc00 = 3422604288
define i32 @f3(i32 %a) {
; CHECK: f3:
-; CHECK: mvn r0, #3422604288
+; CHECK: mvn r0, #-872363008
%tmp = xor i32 4294967295, 3422604288
ret i32 %tmp
}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mvn2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mvn2.ll
index ba1d7ca..375d0aa 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mvn2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-mvn2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-neg.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-neg.ll
index 7a26c58..6bf11ec 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-neg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-neg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orn.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orn.ll
index 92c4564..d4222c2 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orn.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*$} | count 4
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*$} | count 4
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1
define i32 @f1(i32 %a, i32 %b) {
%tmp = xor i32 %b, 4294967295
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orn2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orn2.ll
index 7758edd..7b01882 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orn2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orn2.ll
@@ -1,4 +1,5 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} | grep {#187\\|#11141290\\|#3422604288\\|#1114112} | count 4
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} |\
+; RUN: grep {#187\\|#11141290\\|#-872363008\\|#1114112} | count 4
; 0x000000bb = 187
define i32 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orr.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orr.ll
index 221991e..89ab7b1 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orr2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orr2.ll
index 6f2b62c..759a5b8 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orr2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-orr2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} | grep {#187\\|#11141290\\|#3422604288\\|#1145324612\\|#1114112} | count 5
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orr\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} | grep {#187\\|#11141290\\|#-872363008\\|#1145324612\\|#1114112} | count 5
; 0x000000bb = 187
define i32 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-pack.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-pack.ll
index dd7729e..a982249 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-pack.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-pack.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep pkhbt | count 5
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep pkhtb | count 4
define i32 @test1(i32 %X, i32 %Y) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rev.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rev.ll
index 4205ed1..27b1672 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rev.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rev.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2,+v7a | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s
define i32 @f1(i32 %a) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rev16.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rev16.ll
index d45d1ff..39b6ac3 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rev16.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rev16.ll
@@ -1,7 +1,7 @@
; XFAIL: *
; fixme rev16 pattern is not matching
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rev16\\W*r\[0-9\]*,\\W*r\[0-9\]*} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rev16\\W*r\[0-9\]*,\\W*r\[0-9\]*} | count 1
; 0xff00ff00 = 4278255360
; 0x00ff00ff = 16711935
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ror.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ror.ll
index a10490f..01adb52 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ror.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ror.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {ror\\.w\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} | grep 22 | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {ror\\.w\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} | grep 22 | count 1
define i32 @f1(i32 %a) {
%l8 = shl i32 %a, 10
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ror2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ror2.ll
index 8efe03f..ffd1dd7 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ror2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-ror2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rsb.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rsb.ll
index 5779687..4611e94 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rsb.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rsb.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1
define i32 @f2(i32 %a, i32 %b) {
%tmp = shl i32 %b, 5
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rsb2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rsb2.ll
index 6e68aa3..84a3796 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rsb2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-rsb2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#66846720} | count 5
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#66846720} | count 5
; 171 = 0x000000ab
define i32 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sbc.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sbc.ll
index 78d6d33..ad96291 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sbc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sbc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i64 @f1(i64 %a, i64 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-select.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-select.ll
index 91639a1..2dcf8aa 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-select.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-select.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a.s) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll
index 5332c2d..b4274ad 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | count 3
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mvn | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep it | count 3
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep mov | count 3
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep mvn | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep it | count 3
define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
%tmp1 = icmp sgt i32 %c, 10
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-shifter.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-shifter.ll
index 9bd6e43..7746cd3 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-shifter.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-shifter.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsl
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsr
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep asr
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ror
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep mov
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep lsl
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep lsr
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep asr
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep ror
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep mov
define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) {
%A = shl i32 %Y, 16
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-smla.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-smla.ll
index 0c65f23..66cc884 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-smla.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-smla.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep smlabt | count 1
define i32 @f3(i32 %a, i16 %x, i32 %y) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-smul.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-smul.ll
index ebbb982..cdbf4ca 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-smul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-smul.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep smulbt | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep smultt | count 1
@x = weak global i16 0 ; <i16*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-spill-q.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-spill-q.ll
index 3c8e820..0a7221c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-spill-q.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-spill-q.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-elf -mattr=+neon | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-elf -mattr=+neon | FileCheck %s
; PR4789
%bar = type { float, float, float }
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str.ll
index 10c6f87..3eeec8c 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32* %v) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str_post.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str_post.ll
index 536011c..bee5810 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str_post.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str_post.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep {strh .*\\\[.*\], #-4} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep {str .*\\\[.*\],} | count 1
define i16 @test1(i32* %X, i16* %A) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str_pre.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str_pre.ll
index 1e93b70..6c804ee 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str_pre.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-str_pre.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep {str.*\\!} | count 2
define void @test1(i32* %X, i32* %A, i32** %dest) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-strb.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-strb.ll
index e59f037..1ebb938 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-strb.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-strb.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i8 @f1(i8 %a, i8* %v) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-strh.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-strh.ll
index d3925ff..b0eb8c1 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-strh.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-strh.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i16 @f1(i16 %a, i16* %v) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub.ll
index d2120ae..95335a2 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; 171 = 0x000000ab
define i32 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub2.ll
index c7ebd22..6813f76 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {subw\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#4095} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {subw\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#4095} | count 1
define i32 @f1(i32 %a) {
%tmp = sub i32 %a, 4095
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub4.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub4.ll
index 1ba2450..a040d17 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub5.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub5.ll
index 1110dad..c3b56bc 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sub5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i64 @f1(i64 %a, i64 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
index 4afe354..33ed543 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep sxtb | count 2
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep sxtb | grep ror | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep sxtab | count 1
define i32 @test0(i8 %A) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tbb.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tbb.ll
index 9437233..5dc3cc3 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tbb.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tbb.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin | FileCheck %s
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s
define void @bar(i32 %n.u) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tbh.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tbh.ll
index 3a6d758..c5cb6f3 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tbh.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tbh.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s
; Thumb2 target should reorder the bb's in order to use tbb / tbh.
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-teq.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-teq.ll
index 94e097d..634d318 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-teq.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-teq.ll
@@ -1,4 +1,5 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#187\\|#11141290\\|#3422604288\\|#1114112\\|#3722304989} | count 10
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*#\[0-9\]*} | \
+; RUN: grep {#187\\|#11141290\\|#-872363008\\|#1114112\\|#-572662307} | count 10
; 0x000000bb = 187
define i1 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-teq2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-teq2.ll
index 2ec76ff..c6867d9 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-teq2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-teq2.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1
define i1 @f1(i32 %a, i32 %b) {
%tmp = xor i32 %a, %b
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tst.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tst.ll
index b5321c9..525a817 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tst.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tst.ll
@@ -1,4 +1,5 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {tst\\.w\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#187\\|#11141290\\|#3422604288\\|#1114112\\|#3722304989} | count 10
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {tst\\.w\\W*r\[0-9\],\\W*#\[0-9\]*} | \
+; RUN: grep {#187\\|#11141290\\|#-872363008\\|#1114112\\|#-572662307} | count 10
; 0x000000bb = 187
define i1 @f1(i32 %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tst2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tst2.ll
index 49044a4..db202dd 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tst2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-tst2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i1 @f1(i32 %a, i32 %b) {
; CHECK: f1:
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
index 0d1cc18..37919dd 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep uxtb | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep uxtab | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep uxth | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep uxtb | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep uxtab | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep uxth | count 1
define i8 @test1(i32 %A.u) zeroext {
%B.u = trunc i32 %A.u to i8
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
index 28a5fe4..4022d95 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
; RUN: grep uxt | count 10
define i32 @test1(i32 %x) {
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/tls1.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/tls1.ll
index 6abb6eb..1e55557 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/tls1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/tls1.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi | \
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi | \
; RUN: grep {i(tpoff)}
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi | \
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi | \
; RUN: grep {__aeabi_read_tp}
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi \
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi \
; RUN: -relocation-model=pic | grep {__tls_get_addr}
diff --git a/libclamav/c++/llvm/test/CodeGen/Thumb2/tls2.ll b/libclamav/c++/llvm/test/CodeGen/Thumb2/tls2.ll
index 7187ca1..b8a0657 100644
--- a/libclamav/c++/llvm/test/CodeGen/Thumb2/tls2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/Thumb2/tls2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi | FileCheck %s -check-prefix=CHECK-NOT-PIC
-; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi | FileCheck %s -check-prefix=CHECK-NOT-PIC
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC
@i = external thread_local global i32 ; <i32*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2002-12-23-LocalRAProblem.ll b/libclamav/c++/llvm/test/CodeGen/X86/2002-12-23-LocalRAProblem.ll
deleted file mode 100644
index df4a8f5..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/2002-12-23-LocalRAProblem.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86 -regalloc=simple
-
-define i32 @main() {
- ; %A = 0
- %A = add i32 0, 0 ; <i32> [#uses=1]
- ; %B = 1
- %B = add i32 0, 1 ; <i32> [#uses=2]
- br label %bb1
-bb1: ; preds = %0
- ; %X = 0*1 = 0
- %X = mul i32 %A, %B ; <i32> [#uses=0]
- ; %r = 0
- %R = sub i32 %B, 1 ; <i32> [#uses=1]
- ret i32 %R
-}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2002-12-23-SubProblem.ll b/libclamav/c++/llvm/test/CodeGen/X86/2002-12-23-SubProblem.ll
deleted file mode 100644
index 68200ff..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/2002-12-23-SubProblem.ll
+++ /dev/null
@@ -1,7 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86 -regalloc=simple
-
-define i32 @main(i32 %B) {
- ;%B = add i32 0, 1;
- %R = sub i32 %B, 1 ; %r = 0
- ret i32 %R
-}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll b/libclamav/c++/llvm/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll
index 2b4242a..2484860 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll
@@ -3,7 +3,7 @@
; it makes a ton of annoying overlapping live ranges. This code should not
; cause spills!
;
-; RUN: llvm-as < %s | llc -march=x86 -stats |& not grep spilled
+; RUN: llc < %s -march=x86 -stats |& not grep spilled
target datalayout = "e-p:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2003-08-23-DeadBlockTest.ll b/libclamav/c++/llvm/test/CodeGen/X86/2003-08-23-DeadBlockTest.ll
index a4d5589..5c40eea 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2003-08-23-DeadBlockTest.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2003-08-23-DeadBlockTest.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i32 @test() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2003-11-03-GlobalBool.ll b/libclamav/c++/llvm/test/CodeGen/X86/2003-11-03-GlobalBool.ll
index 4de3c79..8b0a185 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2003-11-03-GlobalBool.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2003-11-03-GlobalBool.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | \
+; RUN: llc < %s -march=x86 | \
; RUN: not grep {.byte\[\[:space:\]\]*true}
@X = global i1 true ; <i1*> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2004-02-12-Memcpy.ll b/libclamav/c++/llvm/test/CodeGen/X86/2004-02-12-Memcpy.ll
index 56bb21c..f15a1b4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2004-02-12-Memcpy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2004-02-12-Memcpy.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-pc-linux-gnu | grep movs | count 1
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep movs | count 1
@A = global [32 x i32] zeroinitializer
@B = global [32 x i32] zeroinitializer
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2004-02-13-FrameReturnAddress.ll b/libclamav/c++/llvm/test/CodeGen/X86/2004-02-13-FrameReturnAddress.ll
index ee3169a..fea2b54 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2004-02-13-FrameReturnAddress.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2004-02-13-FrameReturnAddress.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {(%esp}
-; RUN: llvm-as < %s | llc -march=x86 | grep {pushl %ebp} | count 1
-; RUN: llvm-as < %s | llc -march=x86 | grep {popl %ebp} | count 1
+; RUN: llc < %s -march=x86 | grep {(%esp}
+; RUN: llc < %s -march=x86 | grep {pushl %ebp} | count 1
+; RUN: llc < %s -march=x86 | grep {popl %ebp} | count 1
declare i8* @llvm.returnaddress(i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2004-02-14-InefficientStackPointer.ll b/libclamav/c++/llvm/test/CodeGen/X86/2004-02-14-InefficientStackPointer.ll
index b25dfaf..f986ebd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2004-02-14-InefficientStackPointer.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2004-02-14-InefficientStackPointer.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep -i ESP | not grep sub
+; RUN: llc < %s -march=x86 | grep -i ESP | not grep sub
define i32 @test(i32 %X) {
ret i32 %X
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2004-02-22-Casts.ll b/libclamav/c++/llvm/test/CodeGen/X86/2004-02-22-Casts.ll
index 40d5f39..dabf7d3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2004-02-22-Casts.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2004-02-22-Casts.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i1 @test1(double %X) {
%V = fcmp one double %X, 0.000000e+00 ; <i1> [#uses=1]
ret i1 %V
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2004-03-30-Select-Max.ll b/libclamav/c++/llvm/test/CodeGen/X86/2004-03-30-Select-Max.ll
index 5021fd8..b6631b6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2004-03-30-Select-Max.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2004-03-30-Select-Max.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep {j\[lgbe\]}
+; RUN: llc < %s -march=x86 | not grep {j\[lgbe\]}
define i32 @max(i32 %A, i32 %B) {
%gt = icmp sgt i32 %A, %B ; <i1> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2004-04-09-SameValueCoalescing.ll b/libclamav/c++/llvm/test/CodeGen/X86/2004-04-09-SameValueCoalescing.ll
index 633a615..c62fee1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2004-04-09-SameValueCoalescing.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2004-04-09-SameValueCoalescing.ll
@@ -2,7 +2,7 @@
; overlapping live intervals. When two overlapping intervals have the same
; value, they can be joined though.
;
-; RUN: llvm-as < %s | llc -march=x86 -regalloc=linearscan | \
+; RUN: llc < %s -march=x86 -regalloc=linearscan | \
; RUN: not grep {mov %\[A-Z\]\\\{2,3\\\}, %\[A-Z\]\\\{2,3\\\}}
define i64 @test(i64 %x) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2004-04-13-FPCMOV-Crash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2004-04-13-FPCMOV-Crash.ll
index 858605c..f8ed016 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2004-04-13-FPCMOV-Crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2004-04-13-FPCMOV-Crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define double @test(double %d) {
%X = select i1 false, double %d, double %d ; <double> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2004-06-10-StackifierCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2004-06-10-StackifierCrash.ll
index 1a51bee..036aa6a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2004-06-10-StackifierCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2004-06-10-StackifierCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i1 @T(double %X) {
%V = fcmp oeq double %X, %X ; <i1> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2004-10-08-SelectSetCCFold.ll b/libclamav/c++/llvm/test/CodeGen/X86/2004-10-08-SelectSetCCFold.ll
index 9ee773c..db3af01 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2004-10-08-SelectSetCCFold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2004-10-08-SelectSetCCFold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i1 @test(i1 %C, i1 %D, i32 %X, i32 %Y) {
%E = icmp slt i32 %X, %Y ; <i1> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2005-01-17-CycleInDAG.ll b/libclamav/c++/llvm/test/CodeGen/X86/2005-01-17-CycleInDAG.ll
index 37cff57..32fafc6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2005-01-17-CycleInDAG.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2005-01-17-CycleInDAG.ll
@@ -3,7 +3,7 @@
; is invalid code (there is no correct way to order the instruction). Check
; that we do not fold the load into the sub.
-; RUN: llvm-as < %s | llc -march=x86 | not grep sub.*GLOBAL
+; RUN: llc < %s -march=x86 | not grep sub.*GLOBAL
@GLOBAL = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll b/libclamav/c++/llvm/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll
index 762047b..30a6ac6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep 18446744073709551612
+; RUN: llc < %s -march=x86 | not grep 18446744073709551612
@A = external global i32 ; <i32*> [#uses=1]
@Y = global i32* getelementptr (i32* @A, i32 -1) ; <i32**> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2005-05-08-FPStackifierPHI.ll b/libclamav/c++/llvm/test/CodeGen/X86/2005-05-08-FPStackifierPHI.ll
index 04035ac..5266009 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2005-05-08-FPStackifierPHI.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2005-05-08-FPStackifierPHI.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=generic
+; RUN: llc < %s -march=x86 -mcpu=generic
; Make sure LLC doesn't crash in the stackifier due to FP PHI nodes.
define void @radfg_() {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
index 817b281..d906da4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | \
+; RUN: llc < %s -march=x86 | \
; RUN: grep shld | count 1
;
; Check that the isel does not fold the shld, which already folds a load
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll
index 51d2fb2..dc69ef8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep {subl.*%esp}
+; RUN: llc < %s -march=x86 | not grep {subl.*%esp}
define i32 @f(i32 %a, i32 %b) {
%tmp.2 = mul i32 %a, %a ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll
index c410c46..0421896 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -stats |& \
+; RUN: llc < %s -march=x86 -stats |& \
; RUN: grep asm-printer | grep 7
define i32 @g(i32 %a, i32 %b) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-04-04-CrossBlockCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-04-04-CrossBlockCrash.ll
index 743790c..c106f57 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-04-04-CrossBlockCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-04-04-CrossBlockCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah
+; RUN: llc < %s -march=x86 -mcpu=yonah
; END.
target datalayout = "e-p:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
index 4a0b5c3..8783a11 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=x86 -mtriple=i686-apple-darwin8 -relocation-model=static > %t
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin8 -relocation-model=static > %t
; RUN: grep {movl _last} %t | count 1
; RUN: grep {cmpl.*_last} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll
index f283666..49f3a95 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah -stats |& \
+; RUN: llc < %s -march=x86 -mcpu=yonah -stats |& \
; RUN: not grep {Number of register spills}
; END.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-02-InstrSched1.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-02-InstrSched1.ll
index 72dab39..7d0a6ab 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-02-InstrSched1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-02-InstrSched1.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=x86 -relocation-model=static -stats |& \
+; RUN: llc < %s -march=x86 -relocation-model=static -stats |& \
; RUN: grep asm-printer | grep 14
;
@size20 = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-02-InstrSched2.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-02-InstrSched2.ll
index 48ed2b9..23954d7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-02-InstrSched2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-02-InstrSched2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -stats |& \
+; RUN: llc < %s -march=x86 -stats |& \
; RUN: grep asm-printer | grep 13
define void @_ZN9__gnu_cxx9hashtableISt4pairIKPKciES3_NS_4hashIS3_EESt10_Select1stIS5_E5eqstrSaIiEE14find_or_insertERKS5__cond_true456.i(i8* %tmp435.i, i32* %tmp449.i.out) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll
index 900abe5..8421483 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll
@@ -1,7 +1,7 @@
; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
; fixed, the movb should go away as well.
-; RUN: llvm-as < %s | llc -march=x86 -relocation-model=static | \
+; RUN: llc < %s -march=x86 -relocation-model=static | \
; RUN: grep movl
@B = external global i32 ; <i32*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-08-InstrSched.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-08-InstrSched.ll
index c39b377..d58d638 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-08-InstrSched.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-08-InstrSched.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=x86 -relocation-model=static | not grep {subl.*%esp}
+; RUN: llc < %s -march=x86 -relocation-model=static | not grep {subl.*%esp}
@A = external global i16* ; <i16**> [#uses=1]
@B = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-11-InstrSched.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-11-InstrSched.ll
index 6c0e76b..89b127c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-11-InstrSched.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-11-InstrSched.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -realign-stack=0 |&\
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats -realign-stack=0 |&\
; RUN: grep {asm-printer} | grep 31
target datalayout = "e-p:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-17-VectorArg.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-17-VectorArg.ll
index 217cbe1..b36d61e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-17-VectorArg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-17-VectorArg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
define <4 x float> @opRSQ(<4 x float> %a) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-22-FPSetEQ.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-22-FPSetEQ.ll
index ae18c90..083d068 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-22-FPSetEQ.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-22-FPSetEQ.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep setnp
-; RUN: llvm-as < %s | llc -march=x86 -enable-unsafe-fp-math | \
+; RUN: llc < %s -march=x86 | grep setnp
+; RUN: llc < %s -march=x86 -enable-unsafe-fp-math | \
; RUN: not grep setnp
define i32 @test(float %f) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-25-CycleInDAG.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-25-CycleInDAG.ll
index 78838d1..0288278 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-05-25-CycleInDAG.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-05-25-CycleInDAG.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i32 @test() {
br i1 false, label %cond_next33, label %cond_true12
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
index 760fe36..4ea364d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR825
define i64 @test() {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
index 1db3921..568fbbc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR828
target datalayout = "e-p:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-19-ATTAsm.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-19-ATTAsm.ll
index 78167f6..c8fd10f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-19-ATTAsm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-19-ATTAsm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=att
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att
; PR834
; END.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-20-InlineAsm.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-20-InlineAsm.ll
index 08510a8..cac47cd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-20-InlineAsm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-20-InlineAsm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR833
@G = weak global i32 0 ; <i32*> [#uses=3]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll
index a82612b..deae086 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep -- 4294967240
+; RUN: llc < %s -march=x86 | grep -- 4294967240
; PR853
@X = global i32* inttoptr (i64 -56 to i32*) ; <i32**> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-31-SingleRegClass.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-31-SingleRegClass.ll
index 2a521ad..3159cec 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-07-31-SingleRegClass.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-07-31-SingleRegClass.ll
@@ -1,5 +1,5 @@
; PR850
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=att > %t
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att > %t
; RUN: grep {movl 4(%eax),%ebp} %t
; RUN: grep {movl 0(%eax), %ebx} %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-08-07-CycleInDAG.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-08-07-CycleInDAG.ll
index 194cd66..aea707e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-08-07-CycleInDAG.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-08-07-CycleInDAG.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
%struct.foo = type opaque
define fastcc i32 @test(%struct.foo* %v, %struct.foo* %vi) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-08-16-CycleInDAG.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-08-16-CycleInDAG.ll
index f2a8855..5fee326 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-08-16-CycleInDAG.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-08-16-CycleInDAG.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
%struct.expr = type { %struct.rtx_def*, i32, %struct.expr*, %struct.occr*, %struct.occr*, %struct.rtx_def* }
%struct.hash_table = type { %struct.expr**, i32, i32, i32 }
%struct.occr = type { %struct.occr*, %struct.rtx_def*, i8, i8 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll
index c1d81d5..a19d8f7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 | \
+; RUN: llc < %s -march=x86 -mcpu=i386 | \
; RUN: not grep {movl %eax, %edx}
define i32 @foo(i32 %t, i32 %C) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-09-01-CycleInDAG.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-09-01-CycleInDAG.ll
index dd21c04..1e890bb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-09-01-CycleInDAG.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-09-01-CycleInDAG.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin8"
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll
index cc988f2..795d464 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR933
define fastcc i1 @test() {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll
index e8055f5..bf9fa57 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse | grep movaps
+; RUN: llc < %s -march=x86 -mattr=sse | grep movaps
; Test that the load is NOT folded into the intrinsic, which would zero the top
; elts of the loaded vector.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-09-CycleInDAG.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-09-CycleInDAG.ll
index d627d1b..fbb14ee 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-09-CycleInDAG.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-09-CycleInDAG.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define void @_ZN13QFSFileEngine4readEPcx() {
%tmp201 = load i32* null ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll
index 5dc1cb3..b1f0451 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep shrl
+; RUN: llc < %s -march=x86 | grep shrl
; Bug in FindModifiedNodeSlot cause tmp14 load to become a zextload and shr 31
; is then optimized away.
@tree_code_type = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-12-CycleInDAG.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-12-CycleInDAG.ll
index 31eb070..3b987ac 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-12-CycleInDAG.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-12-CycleInDAG.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
%struct.function = type opaque
%struct.lang_decl = type opaque
%struct.location_t = type { i8*, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-13-CycleInDAG.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-13-CycleInDAG.ll
index 2b53f26..6ed2e7b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-13-CycleInDAG.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-13-CycleInDAG.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
@str = external global [18 x i8] ; <[18 x i8]*> [#uses=1]
define void @test() {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
index 8ec032a..4fd8072 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -asm-verbose | FileCheck %s
+; RUN: llc < %s -march=x86 -asm-verbose | FileCheck %s
@str = internal constant [14 x i8] c"Hello world!\0A\00" ; <[14 x i8]*> [#uses=1]
@str.upgrd.1 = internal constant [13 x i8] c"Blah world!\0A\00" ; <[13 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-11-12-CSRetCC.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-11-12-CSRetCC.ll
index 1a92852..91210ea 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-11-12-CSRetCC.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-11-12-CSRetCC.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {subl \$4, %esp}
+; RUN: llc < %s -march=x86 | grep {subl \$4, %esp}
target triple = "i686-pc-linux-gnu"
@str = internal constant [9 x i8] c"%f+%f*i\0A\00" ; <[9 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll
index 60a737d..e839d72 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep movb %t | count 2
; RUN: grep {movzb\[wl\]} %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-11-27-SelectLegalize.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-11-27-SelectLegalize.ll
index 1222a37..ea2e6db 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-11-27-SelectLegalize.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-11-27-SelectLegalize.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep test.*1
+; RUN: llc < %s -march=x86 | grep test.*1
; PR1016
define i32 @test(i32 %A, i32 %B, i32 %C) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-11-28-Memcpy.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-11-28-Memcpy.ll
index a58bedc..8c1573f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-11-28-Memcpy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-11-28-Memcpy.ll
@@ -1,8 +1,6 @@
; PR1022, PR1023
-; RUN: llvm-as < %s | llc -march=x86 | \
-; RUN: grep 3721182122 | count 2
-; RUN: llvm-as < %s | llc -march=x86 | \
-; RUN: grep -E {movl _?bytes2} | count 1
+; RUN: llc < %s -march=x86 | grep -- -573785174 | count 2
+; RUN: llc < %s -march=x86 | grep -E {movl _?bytes2} | count 1
@fmt = constant [4 x i8] c"%x\0A\00" ; <[4 x i8]*> [#uses=2]
@bytes = constant [4 x i8] c"\AA\BB\CC\DD" ; <[4 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2006-12-19-IntelSyntax.ll b/libclamav/c++/llvm/test/CodeGen/X86/2006-12-19-IntelSyntax.ll
index 17234b8..f81b303 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2006-12-19-IntelSyntax.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2006-12-19-IntelSyntax.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel
; PR1061
target datalayout = "e-p:32:32"
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-01-08-InstrSched.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-01-08-InstrSched.ll
index 012e593..e1bae32 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-01-08-InstrSched.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-01-08-InstrSched.ll
@@ -1,5 +1,5 @@
; PR1075
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
define float @foo(float %x) nounwind {
%tmp1 = fmul float %x, 3.000000e+00
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
index c03d982..5e7c0a7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep leaq %t
; RUN: not grep {,%rsp)} %t
; PR1103
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-01-29-InlineAsm-ir.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-01-29-InlineAsm-ir.ll
index b1c86f4..e83e2e5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-01-29-InlineAsm-ir.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-01-29-InlineAsm-ir.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; Test 'ri' constraint.
define void @run_init_process() {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
index 26d3e36..93e8808 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {orl \$1, %eax}
-; RUN: llvm-as < %s | llc -march=x86 | grep {leal 3(,%eax,8)}
+; RUN: llc < %s -march=x86 | grep {orl \$1, %eax}
+; RUN: llc < %s -march=x86 | grep {leal 3(,%eax,8)}
;; This example can't fold the or into an LEA.
define i32 @test(float ** %tmp2, i32 %tmp12) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll
index 365768a..954c95d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-pc-linux-gnu -relocation-model=pic
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu -relocation-model=pic
; PR1027
%struct._IO_FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct._IO_FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i32, i32, [40 x i8] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-02-25-FastCCStack.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-02-25-FastCCStack.ll
index 3b1eb1f..2e2b56d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-02-25-FastCCStack.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-02-25-FastCCStack.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium3
+; RUN: llc < %s -march=x86 -mcpu=pentium3
define internal fastcc double @ggc_rlimit_bound(double %limit) {
ret double %limit
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll
index 721b6e7..112d1ab 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin8 -mattr=+sse2
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin8 -mattr=+sse2 | not grep movhlps
+; RUN: llc < %s -mtriple=x86_64-apple-darwin8 -mattr=+sse2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin8 -mattr=+sse2 | not grep movhlps
define void @test() nounwind {
test.exit:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll
index 4c69ec7..4cac9b4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-darwin | \
+; RUN: llc < %s -march=x86 -mtriple=i686-darwin | \
; RUN: grep push | count 3
define void @foo(i8** %buf, i32 %size, i32 %col, i8* %p) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-16-InlineAsm.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-16-InlineAsm.ll
index c98c89a..9580726 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-16-InlineAsm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-16-InlineAsm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; ModuleID = 'a.bc'
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll
index 6965849..70936fb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR1259
define void @test() {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
index babcf6a..44d68dd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i32 @test(i16 %tmp40414244) {
%tmp48 = call i32 asm sideeffect "inl ${1:w}, $0", "={ax},N{dx},~{dirflag},~{fpsr},~{flags}"( i16 %tmp40414244 )
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
index 9bdb249..3312e01 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {mov %gs:72, %eax}
+; RUN: llc < %s -march=x86 | grep {mov %gs:72, %eax}
target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin9"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
index 6e1adf8..c1b1ad1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mcpu=yonah -march=x86 | \
+; RUN: llc < %s -mcpu=yonah -march=x86 | \
; RUN: grep {cmpltsd %xmm0, %xmm0}
target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin9"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
index e440cdb..30453d5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {psrlw \$8, %xmm0}
+; RUN: llc < %s -march=x86 | grep {psrlw \$8, %xmm0}
target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin9"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-26-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-26-CoalescerBug.ll
index 7ce0584..9676f14 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-03-26-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-03-26-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
@data = external global [339 x i64]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll
index 840fc7d..9f09e88 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1314
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
@@ -7,7 +7,7 @@ target triple = "x86_64-unknown-linux-gnu"
%struct.bc_struct = type { i32, i32, i32, i32, %struct.bc_struct*, i8*, i8* }
@_programStartTime = external global %struct.CycleCount ; <%struct.CycleCount*> [#uses=1]
-define fastcc i32 @bc_divide(%struct.bc_struct* %n1, %struct.bc_struct* %n2, %struct.bc_struct** %quot, i32 %scale) {
+define fastcc i32 @bc_divide(%struct.bc_struct* %n1, %struct.bc_struct* %n2, %struct.bc_struct** %quot, i32 %scale) nounwind {
entry:
%tmp7.i46 = tail call i64 asm sideeffect ".byte 0x0f,0x31", "={dx},=*{ax},~{dirflag},~{fpsr},~{flags}"( i64* getelementptr (%struct.CycleCount* @_programStartTime, i32 0, i32 1) ) ; <i64> [#uses=0]
%tmp221 = sdiv i32 10, 0 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
index 514d665..f48c132 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah
+; RUN: llc < %s -march=x86 -mcpu=yonah
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll
index f9671a4..4604f46 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -relocation-model=pic --disable-fp-elim
+; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=pic --disable-fp-elim
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.__sFILEX = type opaque
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-24-Huge-Stack.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-24-Huge-Stack.ll
index 74e6e72..7528129 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-24-Huge-Stack.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-24-Huge-Stack.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep 4294967112
+; RUN: llc < %s -march=x86-64 | not grep 4294967112
; PR1348
%struct.md5_ctx = type { i32, i32, i32, i32, [2 x i32], i32, [128 x i8], [4294967288 x i8] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-24-VectorCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-24-VectorCrash.ll
index 3e08e50..e38992d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-24-VectorCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-24-VectorCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mcpu=yonah
+; RUN: llc < %s -mcpu=yonah
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll
index ac85a9d..113d0eb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -o - -march=x86 -mattr=+mmx | grep paddq | count 2
-; RUN: llvm-as < %s | llc -o - -march=x86 -mattr=+mmx | grep movq | count 2
+; RUN: llc < %s -o - -march=x86 -mattr=+mmx | grep paddq | count 2
+; RUN: llc < %s -o - -march=x86 -mattr=+mmx | grep movq | count 2
define <1 x i64> @unsigned_add3(<1 x i64>* %a, <1 x i64>* %b, i32 %count) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
index cbd6a73..85a2ecc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | not grep {bsrl.*10}
+; RUN: llc < %s | not grep {bsrl.*10}
; PR1356
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-05-05-VecCastExpand.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-05-05-VecCastExpand.ll
index b0bcf5c..e58b193 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-05-05-VecCastExpand.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-05-05-VecCastExpand.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 -mattr=+sse
+; RUN: llc < %s -march=x86 -mcpu=i386 -mattr=+sse
; PR1371
@str = external global [18 x i8] ; <[18 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-05-07-InvokeSRet.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-05-07-InvokeSRet.ll
index ff7aac0..a3ff2f6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-05-07-InvokeSRet.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-05-07-InvokeSRet.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -enable-eh -disable-fp-elim | not grep {addl .12, %esp}
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -enable-eh -disable-fp-elim | not grep {addl .12, %esp}
; PR1398
%struct.S = type { i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll
index 61f8b2c..8ef2538 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
%struct.XDesc = type <{ i32, %struct.OpaqueXDataStorageType** }>
%struct.OpaqueXDataStorageType = type opaque
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-05-15-maskmovq.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-05-15-maskmovq.ll
index d9836e4..2093b8f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-05-15-maskmovq.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-05-15-maskmovq.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mcpu=yonah
+; RUN: llc < %s -mcpu=yonah
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll
index 64ccef3..989dfc5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep punpckhwd
+; RUN: llc < %s -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep punpckhwd
declare <8 x i16> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-04-X86-64-CtorAsmBugs.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-04-X86-64-CtorAsmBugs.ll
index 5d09075..321e116 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-04-X86-64-CtorAsmBugs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-04-X86-64-CtorAsmBugs.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep GOTPCREL
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep ".align.*3"
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep GOTPCREL
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep ".align.*3"
%struct.A = type { [1024 x i8] }
@_ZN1A1aE = global %struct.A zeroinitializer, align 32 ; <%struct.A*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-04-tailmerge4.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-04-tailmerge4.ll
index 0ad5396..baf2377 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-04-tailmerge4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-04-tailmerge4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -enable-eh -asm-verbose | grep invcont131
+; RUN: llc < %s -enable-eh -asm-verbose | grep invcont131
; PR 1496: tail merge was incorrectly removing this block
; ModuleID = 'report.1.bc'
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-05-LSR-Dominator.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-05-LSR-Dominator.ll
index 3e7776a..36a97ef 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-05-LSR-Dominator.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-05-LSR-Dominator.ll
@@ -1,5 +1,5 @@
; PR1495
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-14-branchfold.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-14-branchfold.ll
index 7756d06..2680b15 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-14-branchfold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-14-branchfold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=i686 | not grep jmp
+; RUN: llc < %s -march=x86 -mcpu=i686 | not grep jmp
; check that branch folding understands FP_REG_KILL is not a branch
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-15-IntToMMX.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-15-IntToMMX.ll
index e608ac3..6128d8b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-15-IntToMMX.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-15-IntToMMX.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep paddusw
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep paddusw
@R = external global <1 x i64> ; <<1 x i64>*> [#uses=1]
define void @foo(<1 x i64> %A, <1 x i64> %B) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-28-X86-64-isel.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-28-X86-64-isel.ll
index af11f12..9d42c49 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-28-X86-64-isel.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-28-X86-64-isel.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2
+; RUN: llc < %s -march=x86-64 -mattr=+sse2
define void @test() {
%tmp1 = call <8 x i16> @llvm.x86.sse2.pmins.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 7, i32 7, i32 7, i32 7 > to <8 x i16>) )
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-29-DAGCombinerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-29-DAGCombinerBug.ll
index bcd265a..d2d6388 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-29-DAGCombinerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-29-DAGCombinerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
define void @test() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll
index 66a58c7..dc11eec 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
define void @test(<4 x float>* %arg) {
%tmp89 = getelementptr <4 x float>* %arg, i64 3
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
index 18850b1..2c513f1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {movd %rsi, %mm0}
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {movd %rdi, %mm1}
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {paddusw %mm0, %mm1}
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {movd %rsi, %mm0}
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {movd %rdi, %mm1}
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {paddusw %mm0, %mm1}
@R = external global <1 x i64> ; <<1 x i64>*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-07-10-StackerAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-07-10-StackerAssert.ll
index 7f09b52..d611677 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-07-10-StackerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-07-10-StackerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -mcpu=athlon -relocation-model=pic
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -mcpu=athlon -relocation-model=pic
; PR1545
@.str97 = external constant [56 x i8] ; <[56 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-07-18-Vector-Extract.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-07-18-Vector-Extract.ll
index c0bd282..8625b27 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-07-18-Vector-Extract.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-07-18-Vector-Extract.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse | grep {movq (%rdi), %rax}
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse | grep {movq 8(%rdi), %rax}
+; RUN: llc < %s -march=x86-64 -mattr=+sse | grep {movq (%rdi), %rax}
+; RUN: llc < %s -march=x86-64 -mattr=+sse | grep {movq 8(%rdi), %rax}
define i64 @foo_0(<2 x i64>* %val) {
entry:
%val12 = getelementptr <2 x i64>* %val, i32 0, i32 0 ; <i64*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll
index 8eda0ab..3cd8052 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep movl
+; RUN: llc < %s -march=x86 | not grep movl
define i8 @t(i8 zeroext %x, i8 zeroext %y) zeroext {
%tmp2 = add i8 %x, 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
index e9ea843..7768f36 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep "movb %ah, %r"
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep "movb %ah, %r"
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, [4 x i8], i64 }
%struct.PyBoolScalarObject = type { i64, %struct._typeobject*, i8 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
index b62d2c6..e93092f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {movsbl}
+; RUN: llc < %s -march=x86 | grep {movsbl}
@X = global i32 0 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-08-13-AppendingLinkage.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-08-13-AppendingLinkage.ll
index f6ed0fe..c90a85f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-08-13-AppendingLinkage.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-08-13-AppendingLinkage.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep drectve
+; RUN: llc < %s -march=x86 | not grep drectve
; PR1607
%hlvm_programs_element = type { i8*, i32 (i32, i8**)* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-08-13-SpillerReuse.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-08-13-SpillerReuse.ll
index edcb823..d6ea510 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-08-13-SpillerReuse.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-08-13-SpillerReuse.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | grep "48(%esp)" | count 5
+; RUN: llc < %s -mtriple=i686-apple-darwin | grep "48(%esp)" | count 5
%struct..0anon = type { i32 }
%struct.rtvec_def = type { i32, [1 x %struct..0anon] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-03-X86-64-EhSelector.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-09-03-X86-64-EhSelector.ll
deleted file mode 100644
index dac7880..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-03-X86-64-EhSelector.ll
+++ /dev/null
@@ -1,38 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -enable-eh
-; PR1632
-
-define void @_Z1fv() {
-entry:
- invoke void @_Z1gv( )
- to label %return unwind label %unwind
-
-unwind: ; preds = %entry
- br i1 false, label %eh_then, label %cleanup20
-
-eh_then: ; preds = %unwind
- invoke void @__cxa_end_catch( )
- to label %return unwind label %unwind10
-
-unwind10: ; preds = %eh_then
- %eh_select13 = tail call i64 (i8*, i8*, ...)* @llvm.eh.selector.i64( i8* null, i8* bitcast (void ()* @__gxx_personality_v0 to i8*), i32 1 ) ; <i32> [#uses=2]
- %tmp18 = icmp slt i64 %eh_select13, 0 ; <i1> [#uses=1]
- br i1 %tmp18, label %filter, label %cleanup20
-
-filter: ; preds = %unwind10
- unreachable
-
-cleanup20: ; preds = %unwind10, %unwind
- %eh_selector.0 = phi i64 [ 0, %unwind ], [ %eh_select13, %unwind10 ] ; <i32> [#uses=0]
- ret void
-
-return: ; preds = %eh_then, %entry
- ret void
-}
-
-declare void @_Z1gv()
-
-declare i64 @llvm.eh.selector.i64(i8*, i8*, ...)
-
-declare void @__gxx_personality_v0()
-
-declare void @__cxa_end_catch()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-05-InvalidAsm.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-09-05-InvalidAsm.ll
index b6a5fc9..5acb051 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-05-InvalidAsm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-09-05-InvalidAsm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -x86-asm-syntax=intel | not grep {lea\[\[:space:\]\]R}
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -x86-asm-syntax=intel | not grep {lea\[\[:space:\]\]R}
%struct.AGenericCall = type { %struct.AGenericManager*, %struct.ComponentParameters*, i32* }
%struct.AGenericManager = type <{ i8 }>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-06-ExtWeakAliasee.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-09-06-ExtWeakAliasee.ll
index 4f95b76..c5d2a46 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-06-ExtWeakAliasee.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-09-06-ExtWeakAliasee.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep weak | count 2
+; RUN: llc < %s -march=x86 | grep weak | count 2
@__gthrw_pthread_once = alias weak i32 (i32*, void ()*)* @pthread_once ; <i32 (i32*, void ()*)*> [#uses=0]
declare extern_weak i32 @pthread_once(i32*, void ()*)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll
index 6a313be..56ee2a3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-apple-darwin -enable-eh | grep {isNullOrNil].eh"} | count 2
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin -enable-eh | grep {isNullOrNil].eh"} | count 2
%struct.NSString = type { }
%struct._objc__method_prototype_list = type opaque
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-18-ShuffleXformBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-09-18-ShuffleXformBug.ll
index 835e4ca..0ae1897 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-18-ShuffleXformBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-09-18-ShuffleXformBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep 170
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep -- -86
define i16 @f(<4 x float>* %tmp116117.i1061.i) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
index be51c04..4a56ee4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc | grep powixf2
-; RUN: llvm-as < %s | llc | grep fsqrt
+; RUN: llc < %s | grep powixf2
+; RUN: llc < %s | grep fsqrt
; ModuleID = 'yyy.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
index a733bb3..6fc8ec9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep pushf
+; RUN: llc < %s -march=x86 | not grep pushf
%struct.gl_texture_image = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8* }
%struct.gl_texture_object = type { i32, i32, i32, float, [4 x i32], i32, i32, i32, i32, i32, float, [11 x %struct.gl_texture_image*], [1024 x i8], i32, i32, i32, i8, i8*, i8, void (%struct.gl_texture_object*, i32, float*, float*, float*, float*, i8*, i8*, i8*, i8*)*, %struct.gl_texture_object* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-05-3AddrConvert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-05-3AddrConvert.ll
index e9fbe79..67323e8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-05-3AddrConvert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-05-3AddrConvert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep lea
+; RUN: llc < %s -march=x86 | grep lea
%struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] }
%struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
index e2fdbb3..fc11347 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep movb
+; RUN: llc < %s -march=x86 | not grep movb
define i16 @f(i32* %bp, i32* %ss) signext {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll
index fd914a1..ea1bbc4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep addss | not grep esp
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep addss | not grep esp
define fastcc void @fht(float* %fz, i16 signext %n) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
index 3016a01..a3872ad 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep sarl | not grep esp
+; RUN: llc < %s -march=x86 | grep sarl | not grep esp
define i16 @t(i16* %qmatrix, i16* %dct, i16* %acBaseTable, i16* %acExtTable, i16 signext %acBaseRes, i16 signext %acMaskRes, i16 signext %acExtRes, i32* %bitptr, i32* %source, i32 %markerPrefix, i8** %byteptr, i32 %scale, i32 %round, i32 %bits) signext {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-14-CoalescerCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-14-CoalescerCrash.ll
index 6cac558..8a55935 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-14-CoalescerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-14-CoalescerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
+; RUN: llc < %s -mtriple=x86_64-apple-darwin
%struct._Unwind_Context = type { }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll
index 4ea4244..1e4ae84 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-linux-gnu
+; RUN: llc < %s -mtriple=x86_64-linux-gnu
; PR1729
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-CoalescerCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-CoalescerCrash.ll
index a414ef0..fbcac50 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-CoalescerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-CoalescerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
+; RUN: llc < %s -mtriple=x86_64-apple-darwin
define i64 @__ashldi3(i64 %u, i64 %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-IllegalAsm.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-IllegalAsm.ll
index 5332fa1..6d0cb47 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-IllegalAsm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-IllegalAsm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-linux-gnu | grep movb | not grep x
+; RUN: llc < %s -mtriple=x86_64-linux-gnu | grep movb | not grep x
; PR1734
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-fp80_select.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-fp80_select.ll
index 2fcf76b..3f9845c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-fp80_select.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-16-fp80_select.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin9"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-17-IllegalAsm.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-17-IllegalAsm.ll
index f3cdfee..c0bb55e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-17-IllegalAsm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-17-IllegalAsm.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-linux-gnu | grep addb | not grep x
-; RUN: llvm-as < %s | llc -mtriple=x86_64-linux-gnu | grep cmpb | not grep x
+; RUN: llc < %s -mtriple=x86_64-linux-gnu | grep addb | not grep x
+; RUN: llc < %s -mtriple=x86_64-linux-gnu | grep cmpb | not grep x
; PR1734
target triple = "x86_64-unknown-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll
index e649999..600bd1f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | grep inc | not grep PTR
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | grep inc | not grep PTR
define i16 @t(i32* %bitptr, i32* %source, i8** %byteptr, i32 %scale, i32 %round) signext {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll
index 450911a..984094d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1748
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
index 9013e90..86d3bbf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 1
+; RUN: llc < %s -march=x86 | grep mov | count 1
define i16 @t() signext {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-30-LSRCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-30-LSRCrash.ll
index 1c912a0..42db98b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-30-LSRCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-30-LSRCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i32 @unique(i8* %full, i32 %p, i32 %len, i32 %mode, i32 %verbos, i32 %flags) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-31-extractelement-i64.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-31-extractelement-i64.ll
index f73a910..1b8e67d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-10-31-extractelement-i64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-10-31-extractelement-i64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2
+; RUN: llc < %s -march=x86 -mattr=sse2
; ModuleID = 'yyy.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-01-ISelCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-01-ISelCrash.ll
index 704efd0..019c6a8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-01-ISelCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-01-ISelCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
%"struct.K::JL" = type <{ i8 }>
%struct.jv = type { i64 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-02-BadAsm.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-02-BadAsm.ll
index 4ae4d2f..4e11cda 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-02-BadAsm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-02-BadAsm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movl | not grep rax
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movl | not grep rax
%struct.color_sample = type { i64 }
%struct.gs_matrix = type { float, i64, float, i64, float, i64, float, i64, float, i64, float, i64 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-03-x86-64-q-constraint.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-03-x86-64-q-constraint.ll
index ffa6e44..27ec826 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-03-x86-64-q-constraint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-03-x86-64-q-constraint.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1763
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-LiveIntervalCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-LiveIntervalCrash.ll
index 889b122..4045618 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-LiveIntervalCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-LiveIntervalCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
; PR1766
%struct.dentry = type { %struct.dentry_operations* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll
index 7e41f36..6b871aa 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
; PR1767
define void @xor_sse_2(i64 %bytes, i64* %p1, i64* %p2) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
index de33c61..8e586a7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -relocation-model=static | grep {foo _str$}
+; RUN: llc < %s -relocation-model=static | grep {foo _str$}
; PR1761
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-06-InstrSched.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-06-InstrSched.ll
index a4e44e1..f6db0d0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-06-InstrSched.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-06-InstrSched.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep lea
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep lea
define float @foo(i32* %x, float* %y, i32 %c) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-07-MulBy4.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-07-MulBy4.ll
index d7fb684..d5b630b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-07-MulBy4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-07-MulBy4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep imul
+; RUN: llc < %s -march=x86 | not grep imul
%struct.eebb = type { %struct.eebb*, i16* }
%struct.hf = type { %struct.hf*, i16*, i8*, i32, i32, %struct.eebb*, i32, i32, i8*, i8*, i8*, i8*, i16*, i8*, i16*, %struct.ri, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [30 x i32], %struct.eebb, i32, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll
index bec43f0..9c004f9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=att | grep movl | count 2
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=att | not grep movb
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att | grep movl | count 2
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att | not grep movb
%struct.double_int = type { i64, i64 }
%struct.tree_common = type <{ i8, [3 x i8] }>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
index 46422bc..0626d28 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& \
; RUN: grep {1 .*folded into instructions}
; Increment in loop bb.128.i adjusted to 2, to prevent loop reversal from
; kicking in.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-30-TestLoadFolding.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-30-TestLoadFolding.ll
index 0d43a6e..debb461 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-11-30-TestLoadFolding.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-11-30-TestLoadFolding.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -stats |& \
+; RUN: llc < %s -march=x86 -stats |& \
; RUN: grep {1 .*folded into instructions}
-; RUN: llvm-as < %s | llc -march=x86 | grep cmp | count 4
+; RUN: llc < %s -march=x86 | grep cmp | count 4
%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll
index cb7a3dc..ca995cc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | not grep IMPLICIT_DEF
+; RUN: llc < %s -mtriple=i686-apple-darwin | not grep IMPLICIT_DEF
%struct.__sbuf = type { i8*, i32 }
%struct.ggBRDF = type { i32 (...)** }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll
index 8ad7705..455de91 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu
; PR1799
%struct.c34007g__designated___XUB = type { i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll
index 6309f3c..265d968 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {(%esp)} | count 2
+; RUN: llc < %s -march=x86 | grep {(%esp)} | count 2
; PR1872
%struct.c34007g__designated___XUB = type { i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-08-IllegalCMP.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-08-IllegalCMP.ll
index fddfd4f..7aec613 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-08-IllegalCMP.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-08-IllegalCMP.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
index 8a1520c..b040095 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep pushf
+; RUN: llc < %s -march=x86 | not grep pushf
%struct.indexentry = type { i32, i8*, i8*, i8*, i8*, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-09-LongDoubleSin.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-09-LongDoubleSin.ll
index 962d6ec..6997d53 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-09-LongDoubleSin.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-09-LongDoubleSin.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -o - | grep sinl
+; RUN: llc < %s -o - | grep sinl
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll
index 38020c1..d795610 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -regalloc=local
+; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=local
define void @SolveCubic(double %a, double %b, double %c, double %d, i32* %solutions, double* %x) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-InvalidDAGCombineXform.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-InvalidDAGCombineXform.ll
index 4feb078..e91f52e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-InvalidDAGCombineXform.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-InvalidDAGCombineXform.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep IMPLICIT_DEF
+; RUN: llc < %s -march=x86 | not grep IMPLICIT_DEF
%struct.node_t = type { double*, %struct.node_t*, %struct.node_t**, double**, double*, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-Trampoline.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-Trampoline.ll
index 4510edb..704b2ba 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-Trampoline.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-16-Trampoline.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
%struct.FRAME.gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets = type { i32, i32, void (i32, i32)*, i8 (i32, i32)* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-25-EmptyFunction.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-25-EmptyFunction.ll
index ffb82ae..b936686 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-01-25-EmptyFunction.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-01-25-EmptyFunction.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep nop
+; RUN: llc < %s -march=x86 | grep nop
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-05-ISelCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-05-ISelCrash.ll
index 6885cf1..443a32d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-05-ISelCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-05-ISelCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR1975
@nodes = external global i64 ; <i64*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll
index 6db6537..d2d5149 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep xor | grep CPI
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep xor | grep CPI
define void @casin({ double, double }* sret %agg.result, double %z.0, double %z.1) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll
index 230af57..b772d77 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep andpd | not grep esp
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep andpd | not grep esp
declare double @llvm.sqrt.f64(double) nounwind readnone
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-14-BitMiscompile.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-14-BitMiscompile.ll
index 5bf8456..1983f1d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-14-BitMiscompile.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-14-BitMiscompile.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep and
+; RUN: llc < %s -march=x86 | grep and
define i32 @test(i1 %A) {
%B = zext i1 %A to i32 ; <i32> [#uses=1]
%C = sub i32 0, %B ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-18-TailMergingBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
index 47c8677..9b52c5c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah -stats |& grep {Number of block tails merged} | grep 9
+; RUN: llc < %s -march=x86 -mcpu=yonah -stats |& grep {Number of block tails merged} | grep 9
; PR1909
@.str = internal constant [48 x i8] c"transformed bounds: (%.2f, %.2f), (%.2f, %.2f)\0A\00" ; <[48 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
index 557d00c..5115e48 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc | grep {a:} | not grep ax
-; RUN: llvm-as < %s | llc | grep {b:} | not grep ax
+; RUN: llc < %s | grep {a:} | not grep ax
+; RUN: llc < %s | grep {b:} | not grep ax
; PR2078
; The clobber list says that "ax" is clobbered. Make sure that eax isn't
; allocated to the input/output register.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll
index 8cf3642..6b1eefe 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -regalloc=local -march=x86 -mattr=+mmx | grep esi
+; RUN: llc < %s -regalloc=local -march=x86 -mattr=+mmx | grep esi
; PR2082
; Local register allocator was refusing to use ESI, EDI, and EBP so it ran out of
; registers.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-22-ReMatBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-22-ReMatBug.ll
index f78d526..8d6bb0d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-22-ReMatBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-22-ReMatBug.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of re-materialization} | grep 3
-; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of dead spill slots removed}
+; RUN: llc < %s -march=x86 -stats |& grep {Number of re-materialization} | grep 3
; rdar://5761454
%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-25-InlineAsmBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-25-InlineAsmBug.ll
index ff7cf5e..1d31859 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-25-InlineAsmBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-25-InlineAsmBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -mattr=+sse2
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -mattr=+sse2
; PR2076
define void @h264_h_loop_filter_luma_mmx2(i8* %pix, i32 %stride, i32 %alpha, i32 %beta, i8* %tc0) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll
index 5d60bde..6615b8c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
%struct.XX = type <{ i8 }>
%struct.YY = type { i64 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll
index 3ba31f4..0b4eb3a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll
index fe0ee8a..ad7950c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
%struct.CompAtom = type <{ %struct.Position, float, i32 }>
%struct.Lattice = type { %struct.Position, %struct.Position, %struct.Position, %struct.Position, %struct.Position, %struct.Position, %struct.Position, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-27-PEICrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-27-PEICrash.ll
index 055eabb..d842967 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-02-27-PEICrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-02-27-PEICrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
define i64 @__divsc3(float %a, float %b, float %c, float %d) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-06-frem-fpstack.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-06-frem-fpstack.ll
index 2d7182e..70a83b5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-06-frem-fpstack.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-06-frem-fpstack.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386
+; RUN: llc < %s -march=x86 -mcpu=i386
; PR2122
define float @func(float %a, float %b) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-07-APIntBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-07-APIntBug.ll
index 5d1ccad..84e4827 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-07-APIntBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-07-APIntBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 | not grep 255
+; RUN: llc < %s -march=x86 -mcpu=i386 | not grep 255
%struct.CONSTRAINT = type { i32, i32, i32, i32 }
%struct.FIRST_UNION = type { %struct.anon }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll
index 1098988..cd2d609 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu -relocation-model=pic -disable-fp-elim
-; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu -relocation-model=pic -disable-fp-elim -schedule-livein-copies | not grep {Number of register spills}
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -relocation-model=pic -disable-fp-elim -schedule-livein-copies | not grep {Number of register spills}
; PR2134
declare fastcc i8* @w_addchar(i8*, i32*, i32*, i8 signext ) nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-12-ThreadLocalAlias.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-12-ThreadLocalAlias.ll
index 0f83b39..e673d31 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-12-ThreadLocalAlias.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-12-ThreadLocalAlias.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -relocation-model=pic | grep TLSGD | count 2
+; RUN: llc < %s -relocation-model=pic | grep TLSGD | count 2
; PR2137
; ModuleID = '1.c'
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-13-TwoAddrPassCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-13-TwoAddrPassCrash.ll
index 4a896e9..c6ba22e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-13-TwoAddrPassCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-13-TwoAddrPassCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i16 @t(i32 %depth) signext nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-14-SpillerCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-14-SpillerCrash.ll
index 544c9b5..8946415 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-14-SpillerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-14-SpillerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu
; PR2138
%struct.__locale_struct = type { [13 x %struct.locale_data*], i16*, i32*, i32*, [13 x i8*] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-18-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-18-CoalescerBug.ll
index 4b6758d..ccc4d75 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-18-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-18-CoalescerBug.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim | grep movss | count 1
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -stats |& grep {Number of re-materialization} | grep 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim | grep movss | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -stats |& grep {Number of re-materialization} | grep 1
%struct..0objc_object = type opaque
%struct.OhBoy = type { }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll
index 2fad32a..eaa883c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i32 @t() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-23-DarwinAsmComments.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-23-DarwinAsmComments.ll
index 6cf731b..4dc3a10 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-23-DarwinAsmComments.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-23-DarwinAsmComments.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -asm-verbose | grep {#} | not grep -v {##}
+; RUN: llc < %s -mtriple=i386-apple-darwin -asm-verbose | grep {#} | not grep -v {##}
%struct.AGenericCall = type { %struct.AGenericManager*, %struct.ComponentParameters*, i32* }
%struct.AGenericManager = type <{ i8 }>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-25-TwoAddrPassBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-25-TwoAddrPassBug.ll
index 53bb054..2d868e0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-25-TwoAddrPassBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-25-TwoAddrPassBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
define void @t() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
index 83e1d60..305968a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -relocation-model=pic -disable-fp-elim | grep add | grep 12 | not grep non_lazy_ptr
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -disable-fp-elim | grep add | grep 12 | not grep non_lazy_ptr
; Don't fold re-materialized load into a two address instruction
%"struct.Smarts::Runnable" = type { i32 (...)**, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-02-unnamedEH.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-02-unnamedEH.ll
index 3e7f713..a9f368b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-02-unnamedEH.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-02-unnamedEH.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep unnamed_1.eh
+; RUN: llc < %s | grep unnamed_1.eh
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-08-CoalescerCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-08-CoalescerCrash.ll
index f5de113..dc8c097 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-08-CoalescerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-08-CoalescerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx
+; RUN: llc < %s -march=x86 -mattr=+mmx
define i32 @t2() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll
index fea54c4..41fbdd1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep jmp
+; RUN: llc < %s -march=x86 | not grep jmp
%struct..0anon = type { i32 }
%struct.binding_level = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.binding_level*, i8, i8, i8, i8, i8, i32, %struct.tree_node* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
index 4bb8c6d..83eb61a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local
+; RUN: llc < %s -mtriple=x86_64-apple-darwin
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local
%struct.CGPoint = type { double, double }
%struct.NSArray = type { %struct.NSObject }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-16-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-16-CoalescerBug.ll
index 30accad..3ccc0fe 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-16-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-16-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define void @Hubba(i8* %saveunder, i32 %firstBlob, i32 %select) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
index 3e0662a..6e8891b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep movw | not grep {, %e}
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep movw | not grep {, %e}
%struct.DBC_t = type { i32, i8*, i16, %struct.DBC_t*, i8*, i8*, i8*, i8*, i8*, %struct.DBC_t*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i32*, i8, i16, %struct.DRVOPT*, i16 }
%struct.DRVOPT = type { i16, i32, i8, %struct.DRVOPT* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
index c69ff33..ac48285 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep xorl | grep {%e}
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep xorl | grep {%e}
; Make sure xorl operands are 32-bit registers.
%struct.tm = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll
index 09fdc70..6389267 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep 120
+; RUN: llc < %s -march=x86 | not grep 120
; Don't accidentally add the offset twice for trailing bytes.
%struct.S63 = type { [63 x i8] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-24-pblendw-fold-crash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-24-pblendw-fold-crash.ll
index 838c2ea..4eaca17 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-24-pblendw-fold-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-24-pblendw-fold-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mattr=+sse41
+; RUN: llc < %s -mattr=+sse41
; rdar://5886601
; gcc testsuite: gcc.target/i386/sse4_1-pblendw.c
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
index 82721a5..38d6aa6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep {1 \$2 3}
+; RUN: llc < %s | grep {1 \$2 3}
; rdar://5720231
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-28-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-28-CoalescerBug.ll
index f93ad9a..5b97eb7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-28-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-28-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movl > %t
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movl > %t
; RUN: not grep {r\[abcd\]x} %t
; RUN: not grep {r\[ds\]i} %t
; RUN: not grep {r\[bs\]p} %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-28-CyclicSchedUnit.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-28-CyclicSchedUnit.ll
index 6613faf..6e8e98d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-04-28-CyclicSchedUnit.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-04-28-CyclicSchedUnit.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i64 @t(i64 %maxIdleDuration) nounwind {
call void asm sideeffect "wrmsr", "{cx},A,~{dirflag},~{fpsr},~{flags}"( i32 416, i64 0 ) nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
index d7b5f25..a708224 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -enable-unsafe-fp-math -march=x86 | grep jnp
+; RUN: llc < %s -enable-unsafe-fp-math -march=x86 | grep jnp
; rdar://5902801
declare void @test2()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-09-PHIElimBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-09-PHIElimBug.ll
index c0b1961..cea0076 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-09-PHIElimBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-09-PHIElimBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
%struct.V = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x i32>, float*, float*, float*, float*, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
index 9bcd1f3..5ceb546 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
define fastcc void @glgVectorFloatConversion() nounwind {
%tmp12745 = load <4 x float>* null, align 16 ; <<4 x float>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-12-tailmerge-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
index 8751328..1f95a24 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep abort | count 1
+; RUN: llc < %s | grep abort | count 1
; Calls to abort should all be merged
; ModuleID = '5898899.c'
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
index 9ecd581..9cf50f4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -O0 -fast-isel=false | grep mov | count 5
+; RUN: llc < %s -march=x86 -O0 -fast-isel=false | grep mov | count 5
; PR2343
%llvm.dbg.anchor.type = type { i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
index c9e30d8..19a7354 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movups | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movups | count 2
define void @a(<4 x float>* %x) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-28-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-28-CoalescerBug.ll
index 68f6cce..32bf8d4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-28-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-28-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
; PR2289
define void @_ada_ca11001() {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll
index 02db2ed..f1a19ec 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -regalloc=local
+; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=local
@_ZTVN10Evaluation10GridOutputILi3EEE = external constant [5 x i32 (...)*] ; <[5 x i32 (...)*]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll
index d282761..236b7cd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim | grep subl | grep 24
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim | grep subl | grep 24
%struct.argument_t = type { i8*, %struct.argument_t*, i32, %struct.ipc_type_t*, i32, void (...)*, void (...)*, void (...)*, void (...)*, void (...)*, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, %struct.routine*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, i32, i32, i32, i32, i32, i32 }
%struct.ipc_type_t = type { i8*, %struct.ipc_type_t*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, %struct.ipc_type_t*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll
index 0cde7cf..90af387 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep movsd
-; RUN: llvm-as < %s | llc -march=x86 | grep movw
-; RUN: llvm-as < %s | llc -march=x86 | grep addw
+; RUN: llc < %s -march=x86 | not grep movsd
+; RUN: llc < %s -march=x86 | grep movw
+; RUN: llc < %s -march=x86 | grep addw
; These transforms are turned off for volatile loads and stores.
; Check that they weren't turned off for all loads and stores!
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll
index 2b64212..500cd1f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movsd | count 5
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movl | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd | count 5
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movl | count 2
@atomic = global double 0.000000e+00 ; <double*> [#uses=1]
@atomic2 = global double 0.000000e+00 ; <double*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-16-SubregsBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-16-SubregsBug.ll
index 75513b6..4d4819a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-16-SubregsBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-16-SubregsBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep mov | count 4
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep mov | count 4
define i16 @test(i16* %tmp179) nounwind {
%tmp180 = load i16* %tmp179, align 2 ; <i16> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-18-BadShuffle.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-18-BadShuffle.ll
index ba0a1f9..66f9065 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-18-BadShuffle.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-18-BadShuffle.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 -mattr=+sse2 | grep pinsrw
+; RUN: llc < %s -march=x86 -mcpu=i386 -mattr=+sse2 | grep pinsrw
; Test to make sure we actually insert the bottom element of the vector
define <8 x i16> @a(<8 x i16> %a) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-25-VecISelBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-25-VecISelBug.ll
index f369986..72d1907 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-06-25-VecISelBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-06-25-VecISelBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep pslldq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep pslldq
define void @t() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-07-DanglingDeadInsts.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-07-DanglingDeadInsts.ll
index 3586f87..46341fc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-07-DanglingDeadInsts.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-07-DanglingDeadInsts.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9
+; RUN: llc < %s -mtriple=i386-apple-darwin9
%struct.ogg_stream_state = type { i8*, i32, i32, i32, i32*, i64*, i32, i32, i32, i32, [282 x i8], i32, i32, i32, i32, i32, i64, i64 }
%struct.res_state = type { i32, i32, i32, i32, float*, float*, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-09-ELFSectionAttributes.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-09-ELFSectionAttributes.ll
index 5fb3e57..1a786ef 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-09-ELFSectionAttributes.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-09-ELFSectionAttributes.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep ax
+; RUN: llc < %s | grep ax
; PR2024
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-11-SHLBy1.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-11-SHLBy1.ll
index 5b94a35..ff2b05f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-11-SHLBy1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-11-SHLBy1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -o - | not grep shr
+; RUN: llc < %s -march=x86-64 -o - | not grep shr
define i128 @sl(i128 %x) {
%t = shl i128 %x, 1
ret i128 %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-11-SpillerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-11-SpillerBug.ll
index d7a4892..f75e605 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-11-SpillerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-11-SpillerBug.ll
@@ -1,9 +1,10 @@
-; RUN: llvm-as < %s | llc -march=x86 -relocation-model=static -disable-fp-elim | FileCheck %s
+; RUN: llc < %s -march=x86 -relocation-model=static -disable-fp-elim | FileCheck %s
; PR2536
-; CHECK: movw %ax
+; CHECK: movw %cx
; CHECK-NEXT: andl $65534, %
+; CHECK-NEXT: movl %
; CHECK-NEXT: movl $17
@g_5 = external global i16 ; <i16*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-16-CoalescerCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-16-CoalescerCrash.ll
index aa9ee50..f56604b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-16-CoalescerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-16-CoalescerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
+; RUN: llc < %s -mtriple=x86_64-apple-darwin
%struct.SV = type { i8*, i64, i64 }
@"\01LC25" = external constant [8 x i8] ; <[8 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-19-movups-spills.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-19-movups-spills.ll
index ae30385..98919ee 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-19-movups-spills.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-19-movups-spills.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux -realign-stack=1 -mattr=sse2 | grep movaps | count 75
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux -realign-stack=0 -mattr=sse2 | grep movaps | count 1
+; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=1 -mattr=sse2 | grep movaps | count 75
+; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=0 -mattr=sse2 | grep movaps | count 1
; PR2539
external global <4 x float>, align 1 ; <<4 x float>*>:0 [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-22-CombinerCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-22-CombinerCrash.ll
index a18564f..0f67145 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-22-CombinerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-22-CombinerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
; PR2566
external global i16 ; <i16*>:0 [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-23-VSetCC.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-23-VSetCC.ll
index 5936a9b..684ca5c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-07-23-VSetCC.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-07-23-VSetCC.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium
+; RUN: llc < %s -march=x86 -mcpu=pentium
; PR2575
define void @entry(i32 %m_task_id, i32 %start_x, i32 %end_x) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-05-SpillerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-05-SpillerBug.ll
index 2ebbe6e..1d166f4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-05-SpillerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-05-SpillerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 56
+; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 59
; PR2568
@g_3 = external global i16 ; <i16*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-06-RewriterBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-06-RewriterBug.ll
index 9371c2a..4428035 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-06-RewriterBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-06-RewriterBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR2596
@data = external global [400 x i64] ; <[400 x i64]*> [#uses=5]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll
index b09211d..32f6ca0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movzbl
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movzbl
define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-19-SubAndFetch.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
index 72efa16..8475e8d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86-64 | FileCheck %s
@var = external global i64 ; <i64*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-23-64Bit-maskmovq.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-23-64Bit-maskmovq.ll
index 2c6828b..c76dd7d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-23-64Bit-maskmovq.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-23-64Bit-maskmovq.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
%struct.DrawHelper = type { void (i32, %struct.QT_FT_Span*, i8*)*, void (i32, %struct.QT_FT_Span*, i8*)*, void (%struct.QRasterBuffer*, i32, i32, i32, i8*, i32, i32, i32)*, void (%struct.QRasterBuffer*, i32, i32, i32, i8*, i32, i32, i32)*, void (%struct.QRasterBuffer*, i32, i32, i32, i32, i32)* }
%struct.QBasicAtomic = type { i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
index a0f4fcf..eacb4a5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movd | count 1
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movq
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movd | count 1
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movq
; PR2677
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
index f793b52..101b3c5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mcpu=core2 | grep pxor | count 2
-; RUN: llvm-as < %s | llc -mcpu=core2 | not grep movapd
+; RUN: llc < %s -mcpu=core2 | grep pxor | count 2
+; RUN: llc < %s -mcpu=core2 | not grep movapd
; PR2715
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
index 8aa330e..b92c789 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
@@ -1,6 +1,6 @@
; Check that eh_return & unwind_init were properly lowered
-; RUN: llvm-as < %s | llc | grep %ebp | count 7
-; RUN: llvm-as < %s | llc | grep %ecx | count 5
+; RUN: llc < %s | grep %ebp | count 7
+; RUN: llc < %s | grep %ecx | count 5
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i386-pc-linux"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
index 80eeba7..00ab735 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
@@ -1,6 +1,6 @@
; Check that eh_return & unwind_init were properly lowered
-; RUN: llvm-as < %s | llc | grep %rbp | count 5
-; RUN: llvm-as < %s | llc | grep %rcx | count 3
+; RUN: llc < %s | grep %rbp | count 5
+; RUN: llc < %s | grep %rcx | count 3
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll
index ffe10d4..60be0d5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep cvttpd2pi | count 1
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep cvtpi2pd | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep cvttpd2pi | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep cvtpi2pd | count 1
; PR2687
define <2 x double> @a(<2 x i32> %x) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-09-LinearScanBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-09-LinearScanBug.ll
index 30a2b15..b3312d9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-09-LinearScanBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-09-LinearScanBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin
+; RUN: llc < %s -mtriple=i386-apple-darwin
; PR2757
@g_3 = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug.ll
index 02dd04d..108f243 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR2783
@g_15 = external global i16 ; <i16*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
index 9403344..534f990 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR2748
@g_73 = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-17-inline-asm-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-17-inline-asm-1.ll
index ed8d345..74429c3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-17-inline-asm-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-17-inline-asm-1.ll
@@ -1,11 +1,11 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep "movl %eax, %eax"
-; RUN: llvm-as < %s | llc -march=x86 | not grep "movl %edx, %edx"
-; RUN: llvm-as < %s | llc -march=x86 | not grep "movl (%eax), %eax"
-; RUN: llvm-as < %s | llc -march=x86 | not grep "movl (%edx), %edx"
-; RUN: llvm-as < %s | llc -march=x86 -regalloc=local | not grep "movl %eax, %eax"
-; RUN: llvm-as < %s | llc -march=x86 -regalloc=local | not grep "movl %edx, %edx"
-; RUN: llvm-as < %s | llc -march=x86 -regalloc=local | not grep "movl (%eax), %eax"
-; RUN: llvm-as < %s | llc -march=x86 -regalloc=local | not grep "movl (%edx), %edx"
+; RUN: llc < %s -march=x86 | not grep "movl %eax, %eax"
+; RUN: llc < %s -march=x86 | not grep "movl %edx, %edx"
+; RUN: llc < %s -march=x86 | not grep "movl (%eax), %eax"
+; RUN: llc < %s -march=x86 | not grep "movl (%edx), %edx"
+; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl %eax, %eax"
+; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl %edx, %edx"
+; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl (%eax), %eax"
+; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl (%edx), %edx"
; %0 must not be put in EAX or EDX.
; In the first asm, $0 and $2 must not be put in EAX.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
index 62e3233..f5bd307 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep "#%ebp %edi %esi 8(%edx) %eax (%ebx)"
-; RUN: llvm-as < %s | llc -march=x86 -regalloc=local | grep "#%edi %edx %ebp 8(%ebx) %eax (%esi)"
+; RUN: llc < %s -march=x86 | grep "#%ebp %edi %esi 8(%edx) %eax (%ebx)"
+; RUN: llc < %s -march=x86 -regalloc=local | grep "#%edi %edx %ebp 8(%ebx) %eax (%esi)"
; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers
; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
; operand. There are many combinations that work; this is what llc puts out now.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-19-RegAllocBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-19-RegAllocBug.ll
index 47feb83..a8f2912 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-19-RegAllocBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-19-RegAllocBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin
+; RUN: llc < %s -mtriple=i386-apple-darwin
; PR2808
@g_3 = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-25-sseregparm-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-25-sseregparm-1.ll
index d103f14..c92a8f4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-25-sseregparm-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-25-sseregparm-1.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movs | count 2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep fld | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movs | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep fld | count 2
; check 'inreg' attribute for sse_regparm
define double @foo1() inreg nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-26-FrameAddrBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-26-FrameAddrBug.ll
index b1f5ab5..f1ada28 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-26-FrameAddrBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-26-FrameAddrBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9
+; RUN: llc < %s -mtriple=i386-apple-darwin9
%struct._Unwind_Context = type { [18 x i8*], i8*, i8*, i8*, %struct.dwarf_eh_bases, i32, i32, i32, [18 x i8] }
%struct._Unwind_Exception = type { i64, void (i32, %struct._Unwind_Exception*)*, i32, i32, [3 x i32] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-29-ReMatBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-29-ReMatBug.ll
index d4da01a..c36cf39 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-29-ReMatBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-29-ReMatBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -disable-fp-elim
%struct..0objc_selector = type opaque
%struct.NSString = type opaque
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-29-VolatileBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-29-VolatileBug.ll
index 4f6eb59..935c4c5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-09-29-VolatileBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-09-29-VolatileBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep movz
+; RUN: llc < %s -march=x86 | not grep movz
; PR2835
@g_407 = internal global i32 0 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-02-Atomics32-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-02-Atomics32-2.ll
index e74280c..b48c4ad 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-02-Atomics32-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-02-Atomics32-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
;; This version includes 64-bit version of binary operators (in 32-bit mode).
;; Swap, cmp-and-swap not supported yet in this mode.
; ModuleID = 'Atomics.c'
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-MMXISelBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-MMXISelBug.ll
index bd1ad59..7f7b1a4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-MMXISelBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-MMXISelBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx,+sse2
+; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2
; PR2850
@tmp_V2i = common global <2 x i32> zeroinitializer ; <<2 x i32>*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll
index 837aad5..a135cd4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll
@@ -1,7 +1,7 @@
; ModuleID = 'nan.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-f80:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8"
-; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2,-sse3,-sse | grep fldl
+; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fldl
; This NaN should be shortened to a double (not a float).
declare x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %f)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
index d2e9b45..bd48105 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
@@ -1,7 +1,7 @@
; ModuleID = 'nan.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-f80:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8"
-; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2,-sse3,-sse | grep fldt | count 3
+; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fldt | count 3
; it is not safe to shorten any of these NaNs.
declare x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %f)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-07-SSEISelBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-07-SSEISelBug.ll
index 4808986..bc57612 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-07-SSEISelBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-07-SSEISelBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2
+; RUN: llc < %s -march=x86 -mattr=+sse,-sse2
define <4 x float> @f(float %w) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-11-CallCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-11-CallCrash.ll
index 979b787..efc6125 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-11-CallCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-11-CallCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2735
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin7"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-13-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-13-CoalescerBug.ll
index 608372e..4d3f8c2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-13-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-13-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR2775
define i32 @func_77(i8 zeroext %p_79) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-16-SpillerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-16-SpillerBug.ll
index 4318f1d..b8ca364 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-16-SpillerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-16-SpillerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | grep {andl.*7.*edx}
+; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | grep {andl.*7.*edi}
%struct.XXDActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 }
%struct.XXDAlphaTest = type { float, i16, i8, i8 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-16-VecUnaryOp.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-16-VecUnaryOp.ll
index e1dc7b6..de4c1e7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-16-VecUnaryOp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-16-VecUnaryOp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
; PR2762
define void @foo(<4 x i32>* %p, <4 x double>* %q) {
%n = load <4 x i32>* %p
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
index eb2ec37..b2e6061 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
define void @test(i64 %x) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll
index 33e8c49..353d1c7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
; from gcc.c-torture/compile/920520-1.c
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-24-FlippedCompare.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-24-FlippedCompare.ll
index d6ae05e..421b931 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-24-FlippedCompare.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-24-FlippedCompare.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o - | not grep {ucomiss\[^,\]*esp}
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o - | not grep {ucomiss\[^,\]*esp}
define void @f(float %wt) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-27-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-27-CoalescerBug.ll
index ad13b85..afeb358 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-27-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-27-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats |& not grep {Number of register spills}
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& not grep {Number of register spills}
define fastcc void @fourn(double* %data, i32 %isign) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-27-StackRealignment.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-27-StackRealignment.ll
index d8b0e70..784bc72 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-27-StackRealignment.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-27-StackRealignment.ll
@@ -2,8 +2,8 @@
; Until it does, we shouldn't use movaps to access the stack. On targets with
; sufficiently aligned stack (e.g. darwin) we should.
-; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu -mcpu=yonah | not grep movaps
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin9 -mcpu=yonah | grep movaps | count 2
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -mcpu=yonah | not grep movaps
+; RUN: llc < %s -mtriple=i686-apple-darwin9 -mcpu=yonah | grep movaps | count 2
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-29-ExpandVAARG.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-29-ExpandVAARG.ll
index 41776b2..7ad94f1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-10-29-ExpandVAARG.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-10-29-ExpandVAARG.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR2977
define i8* @ap_php_conv_p2(){
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-03-F80VAARG.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-03-F80VAARG.ll
index 36a054a..507799b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-03-F80VAARG.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-03-F80VAARG.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -o - | not grep 10
+; RUN: llc < %s -march=x86 -o - | not grep 10
declare void @llvm.va_start(i8*) nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-06-testb.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-06-testb.ll
index 7acc7ca..f8f317c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-06-testb.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-06-testb.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep testb
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep testb
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-13-inlineasm-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-13-inlineasm-3.ll
index 7487548..1dc97fc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-13-inlineasm-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-13-inlineasm-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu
; PR 1779
; Using 'A' constraint and a tied constraint together used to crash.
; ModuleID = '<stdin>'
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll
index fe1870e..2e114ab 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu | grep 63551 | count 1
-; ModuleID = '<stdin>'
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu | grep -- -1985 | count 1
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll
index faf7cd4..7c811af 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu | grep 63551
-; ModuleID = '<stdin>'
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu | grep -- -1985
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-ULT-Sign.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
index 6c26b68..6dca141 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu | grep "jns" | count 1
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu | grep "jns" | count 1
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-01-SpillerAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-01-SpillerAssert.ll
index 81b25da..d96d806 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-01-SpillerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-01-SpillerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
; PR3124
%struct.cpuinfo_x86 = type { i8, i8, i8, i8, i32, i8, i8, i8, i32, i32, [9 x i32], [16 x i8], [64 x i8], i32, i32, i32, i64, %struct.cpumask_t, i16, i16, i16, i16, i16, i16, i16, i16, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll
index ca5a80c..1f8bd45 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | not grep lea
+; RUN: llc < %s -mtriple=i386-apple-darwin | not grep lea
; The inner loop should use [reg] addressing, not [reg+reg] addressing.
; rdar://6403965
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-IllegalResultType.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-IllegalResultType.ll
index 01e0f7e..4b72cb9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-IllegalResultType.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-IllegalResultType.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR3117
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-1.ll
index 48bb4e4..fe5bff3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep "(%esp)" | count 2
+; RUN: llc < %s -march=x86 | grep "(%esp)" | count 2
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5"
; a - a should be found and removed, leaving refs to only L and P
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-2.ll
index ba7dfbb..4cb1b42 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep "(%esp)" | count 2
+; RUN: llc < %s -march=x86 | grep "(%esp)" | count 2
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5"
; a - a should be found and removed, leaving refs to only L and P
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-3.ll
index 5fb639d..d5a676a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-02-dagcombine-3.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep add | count 2
-; RUN: llvm-as < %s | llc -march=x86 | grep sub | grep -v subsections | count 1
+; RUN: llc < %s -march=x86 | grep add | count 2
+; RUN: llc < %s -march=x86 | grep sub | grep -v subsections | count 1
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5"
; this should be rearranged to have two +s and one -
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-05-SpillerCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-05-SpillerCrash.ll
index b6b5cbd..7fd2e6f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-05-SpillerCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-05-SpillerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9.5 -mattr=+sse41 -relocation-model=pic
+; RUN: llc < %s -mtriple=i386-apple-darwin9.5 -mattr=+sse41 -relocation-model=pic
%struct.XXActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 }
%struct.XXAlphaTest = type { float, i16, i8, i8 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll
index b2efe64..e97b63d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu | grep ^.L_Z1fv.eh
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-unknown-linux-gnu | grep ^.L_Z1fv.eh
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-apple-darwin9 | grep ^__Z1fv.eh
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-apple-darwin9 | grep ^__Z1fv.eh
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu | grep ^.L_Z1fv.eh
+; RUN: llc < %s -march=x86 -mtriple=i686-unknown-linux-gnu | grep ^.L_Z1fv.eh
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin9 | grep ^__Z1fv.eh
+; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 | grep ^__Z1fv.eh
define void @_Z1fv() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-16-BadShift.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-16-BadShift.ll
index 46b7018..6c70c5b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-16-BadShift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-16-BadShift.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | not grep shrl
+; RUN: llc < %s | not grep shrl
; Note: this test is really trying to make sure that the shift
; returns the right result; shrl is most likely wrong,
; but if CodeGen starts legitimately using an shrl here,
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-16-dagcombine-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-16-dagcombine-4.ll
index 193d290..3080d08 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-16-dagcombine-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-16-dagcombine-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep "(%esp)" | count 2
+; RUN: llc < %s -march=x86 | grep "(%esp)" | count 2
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5"
; a - a should be found and removed, leaving refs to only L and P
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
index ad1615b..13a9080 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
; PR3149
; Make sure the copy after inline asm is not coalesced away.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-22-dagcombine-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-22-dagcombine-5.ll
index 24be521..75773e0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-22-dagcombine-5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-22-dagcombine-5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep "(%esp)" | count 2
+; RUN: llc < %s -march=x86 | grep "(%esp)" | count 2
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5"
; -(-a) - a should be found and removed, leaving refs to only L and P
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-23-crazy-address.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-23-crazy-address.ll
index e53a91e..2edcaea 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-23-crazy-address.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-23-crazy-address.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -relocation-model=static | grep {lea.*X.*esp} | count 2
+; RUN: llc < %s -march=x86 -relocation-model=static | grep {lea.*X.*esp} | count 2
@X = external global [0 x i32]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-23-dagcombine-6.ll b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-23-dagcombine-6.ll
index 13cb9db..bae9283 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2008-12-23-dagcombine-6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2008-12-23-dagcombine-6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep "(%esp)" | count 4
+; RUN: llc < %s -march=x86 | grep "(%esp)" | count 4
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5"
; a - a should be found and removed, leaving refs to only L and P
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-12-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-12-CoalescerBug.ll
index 7c800d4..27a7113 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-12-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-12-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu | grep movq | count 2
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | grep movq | count 2
; PR3311
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll
index ecf71f6..9c71469 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx -enable-legalize-types-checking
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx -enable-legalize-types-checking
declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-16-SchedulerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-16-SchedulerBug.ll
index ff20dc1..99bef6c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-16-SchedulerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-16-SchedulerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin
+; RUN: llc < %s -mtriple=i386-apple-darwin
; rdar://6501631
%CF = type { %Register }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-16-UIntToFP.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-16-UIntToFP.ll
index 340608a..2eab5f1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-16-UIntToFP.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-16-UIntToFP.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-18-ConstantExprCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-18-ConstantExprCrash.ll
index 8857df3..f895336 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-18-ConstantExprCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-18-ConstantExprCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; rdar://6505632
; reduced from 483.xalancbmk
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-25-NoSSE.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-25-NoSSE.ll
index b12e413..0583ef1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-25-NoSSE.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-25-NoSSE.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=-sse,-sse2 | not grep xmm
+; RUN: llc < %s -march=x86-64 -mattr=-sse,-sse2 | not grep xmm
; PR3402
target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-26-WrongCheck.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-26-WrongCheck.ll
index db9dbb6..117ff47 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-26-WrongCheck.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-26-WrongCheck.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -enable-legalize-types-checking
+; RUN: llc < %s -march=x86 -enable-legalize-types-checking
; PR3393
define void @foo(i32 inreg %x) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-27-NullStrings.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-27-NullStrings.ll
index 229d726..8684f4a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-27-NullStrings.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-27-NullStrings.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s
; CHECK: .section __TEXT,__cstring,cstring_literals
@x = internal constant [1 x i8] zeroinitializer ; <[1 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll
index b7f37c9..ce3ea82 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9.6 -regalloc=local -disable-fp-elim
+; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=local -disable-fp-elim
; rdar://6538384
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift.ll
index 360b4f0..4eb0ec1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep and
+; RUN: llc < %s -march=x86 | not grep and
; PR3401
define void @x(i288 %i) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift2.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift2.ll
index 2b5b189..9d24084 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {mov.*56}
+; RUN: llc < %s -march=x86 | grep {mov.*56}
; PR3449
define void @test(<8 x double>* %P, i64* %Q) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift3.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift3.ll
index c92c86a..1b531e3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-01-31-BigShift3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR3450
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-01-LargeMask.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-01-LargeMask.ll
index f2a964f..c4042e6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-01-LargeMask.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-01-LargeMask.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR3453
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll
index 5f97ee7..e75af13 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR3411
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
index 1f29bdb..6ba046a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep { - 92}
+; RUN: llc < %s | grep { - 92}
; PR3481
; The offset should print as -92, not +17179869092
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-05-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-05-CoalescerBug.ll
index 39cad73..0ffa8fd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-05-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-05-CoalescerBug.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse41 | grep movss | count 2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse41 | grep movaps | count 4
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movss | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movaps | count 4
define i1 @t([2 x float]* %y, [2 x float]* %w, i32, [2 x float]* %x.pn59, i32 %smax190, i32 %j.1180, <4 x float> %wu.2179, <4 x float> %wr.2178, <4 x float>* %tmp89.out, <4 x float>* %tmp107.out, i32* %indvar.next218.out) nounwind {
newFuncRoot:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-07-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-07-CoalescerBug.ll
index 784c97a..2d0bbe6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-07-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-07-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -relocation-model=pic -stats |& grep {Number of valno def marked dead} | grep 1
+; RUN: llc < %s -march=x86 -relocation-model=pic -stats |& grep {Number of valno def marked dead} | grep 1
; rdar://6566708
target triple = "i386-apple-darwin9.6"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-08-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-08-CoalescerBug.ll
index cd30c1e..908cc08 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-08-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-08-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR3486
define i32 @foo(i8 signext %p_26) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll
index 7b73a86..1284b0d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR3537
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.6"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
index b0c4449..72c7ee9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s
+; RUN: llc < %s -march=x86-64
; PR3538
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
index ddd15f7..2e148ad 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {\$-81920} | count 3
-; RUN: llvm-as < %s | llc -march=x86 | grep {\$4294885376} | count 1
+; RUN: llc < %s -march=x86 | grep {\$-81920} | count 3
+; RUN: llc < %s -march=x86 | grep {\$4294885376} | count 1
; ModuleID = 'shant.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-SpillerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-SpillerBug.ll
index 1d10319..4f8a5e7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-SpillerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-12-SpillerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-apple-darwin8
+; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin8
; PR3561
define hidden void @__mulxc3({ x86_fp80, x86_fp80 }* noalias nocapture sret %agg.result, x86_fp80 %a, x86_fp80 %b, x86_fp80 %c, x86_fp80 %d) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll
index 54fcd43..58a7f9f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-apple-darwin8 -pre-alloc-split
+; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin8 -pre-alloc-split
define i32 @main() nounwind {
bb4.i.thread:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-21-ExtWeakInitializer.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-21-ExtWeakInitializer.ll
index a6bb7b8..b3dd13c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-21-ExtWeakInitializer.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-21-ExtWeakInitializer.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep weak | count 3
+; RUN: llc < %s | grep weak | count 3
; PR3629
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-25-CommuteBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-25-CommuteBug.ll
index 3dbfa80..7ea6998 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-25-CommuteBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-25-CommuteBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats |& not grep commuted
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& not grep commuted
; rdar://6608609
define <2 x double> @t(<2 x double> %A, <2 x double> %B, <2 x double> %C) nounwind readnone {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
index 8bf6c23..cb1b1ef 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse3 -stats |& not grep {machine-licm}
+; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& not grep {machine-licm}
; rdar://6627786
target triple = "x86_64-apple-darwin10.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-03-BTHang.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-03-BTHang.ll
index 0f338d8..bb95925 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-03-BTHang.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-03-BTHang.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; rdar://6642541
%struct.HandleBlock = type { [30 x i32], [990 x i8*], %struct.HandleBlockTrailer }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-03-BitcastLongDouble.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-03-BitcastLongDouble.ll
index 6f16ced..9deeceb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-03-BitcastLongDouble.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-03-BitcastLongDouble.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR3686
; rdar://6661799
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-05-burr-list-crash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-05-burr-list-crash.ll
index ccedaae..411a0c9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-05-burr-list-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-05-burr-list-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-07-FPConstSelect.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-07-FPConstSelect.ll
index 28302c0..39caddc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-07-FPConstSelect.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-07-FPConstSelect.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not grep xmm
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep xmm
; This should do a single load into the fp stack for the return, not diddle with xmm registers.
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-09-APIntCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-09-APIntCrash.ll
index d7b5269..896c968 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-09-APIntCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-09-APIntCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
; PR3763
%struct.__block_descriptor = type { i64, i64 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-09-SpillerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-09-SpillerBug.ll
index 2ccd771..4224210 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-09-SpillerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-09-SpillerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu
; PR3706
define void @__mulxc3(x86_fp80 %b) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-10-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-10-CoalescerBug.ll
index 3d979e9..90dff88 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-10-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-10-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
+; RUN: llc < %s -mtriple=x86_64-apple-darwin
; rdar://r6661945
%struct.WINDOW = type { i16, i16, i16, i16, i16, i16, i16, i32, i32, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.ldat*, i16, i16, i32, i32, %struct.WINDOW*, %struct.pdat, i16, %struct.cchar_t }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-11-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-11-CoalescerBug.ll
index 1f56317..d5ba93e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-11-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-11-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 -stats |& grep regcoalescing | grep commuting
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -stats |& grep regcoalescing | grep commuting
@lookupTable5B = external global [64 x i32], align 32 ; <[64 x i32]*> [#uses=1]
@lookupTable3B = external global [16 x i32], align 32 ; <[16 x i32]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-12-CPAlignBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-12-CPAlignBug.ll
index ec060e4..3564f01 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-12-CPAlignBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-12-CPAlignBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mattr=+sse2 | not grep {.space}
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 | not grep {.space}
; rdar://6668548
declare double @llvm.sqrt.f64(double) nounwind readonly
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-13-PHIElimBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-13-PHIElimBug.ll
index b01556d..878fa51 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-13-PHIElimBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-13-PHIElimBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep -A 2 {call.*f} | grep movl
+; RUN: llc < %s -march=x86 | grep -A 2 {call.*f} | grep movl
; Check the register copy comes after the call to f and before the call to g
; PR3784
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll
index 091aab4..adbd241 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -asm-verbose | grep -A 1 lpad | grep Llabel
+; RUN: llc < %s -march=x86 -asm-verbose | grep -A 1 lpad | grep Llabel
; Check that register copies in the landing pad come after the EH_LABEL
declare i32 @f()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-16-SpillerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-16-SpillerBug.ll
index 09782a2..80e7639 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-16-SpillerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-16-SpillerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -stats |& grep virtregrewriter | not grep {stores unfolded}
+; RUN: llc < %s -mtriple=i386-apple-darwin -stats |& grep virtregrewriter | not grep {stores unfolded}
; rdar://6682365
; Do not clobber a register if another spill slot is available in it and it's marked "do not clobber".
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-LinearScanBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
index b5298ae..06dfdc0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0
+; RUN: llc < %s -mtriple=i386-apple-darwin -O0
define fastcc void @optimize_bit_field() nounwind {
bb4:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
index b30d41e..b5873ba 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-linux -relocation-model=static -stats -info-output-file - > %t
+; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static -stats -info-output-file - > %t
; RUN: not grep spill %t
; RUN: not grep {%rsp} %t
; RUN: not grep {%rbp} %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-i80-fp80.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-i80-fp80.ll
index 0619e12..e542325 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-i80-fp80.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-23-i80-fp80.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep 302245289961712575840256
-; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep K40018000000000000000
+; RUN: opt < %s -instcombine -S | grep 302245289961712575840256
+; RUN: opt < %s -instcombine -S | grep K40018000000000000000
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin9"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-25-TestBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-25-TestBug.ll
index 9b22d12..f40fddc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-25-TestBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-25-TestBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -o %t
+; RUN: llc < %s -march=x86 -o %t
; RUN: not grep and %t
; RUN: not grep shr %t
; rdar://6661955
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-26-NoImplicitFPBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-26-NoImplicitFPBug.ll
index 8f36797..f486479 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-03-26-NoImplicitFPBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-03-26-NoImplicitFPBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
define double @t(double %x) nounwind ssp noimplicitfloat {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
index 1d4d2b6..97bbd93 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; rdar://6774324
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin10.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
index bf1c8df..27f11cf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast-isel
+; RUN: llc < %s -fast-isel
; radr://6772169
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin10"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-12-picrel.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-12-picrel.ll
index 73062ab..f194280 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-12-picrel.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-12-picrel.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small > %t
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small > %t
; RUN: grep leaq %t | count 1
@dst = external global [131072 x i32]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll
index d6f4b94..ff8cf0a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin
+; RUN: llc < %s -mtriple=i386-apple-darwin
; rdar://6781755
; PR3934
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert.ll
index 7f94c6c..4362ba4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; rdar://6781755
; PR3934
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
index 0d66f69..bfa3eaa 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil
+; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil
; rdar://6787136
%struct.X = type { i8, [32 x i8] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll
index 3e60f6b..f46eed4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of modref unfolded}
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of modref unfolded}
; XFAIL: *
; 69408 removed the opportunity for this optimization to work
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
index 985eb21..4d25b0f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of registers downgraded}
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 84
; rdar://6802189
; Test if linearscan is unfavoring registers for allocation to allow more reuse
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
index 750dba7..c6e6e50 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
@@ -1,7 +1,13 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -mattr=-sse41,-sse3,+sse2 | \
-; RUN: %prcontext {14} 2 | grep {(%ebp)} | count 1
+; RUN: llc -mtriple=i386-apple-darwin10.0 -relocation-model=pic \
+; RUN: -disable-fp-elim -mattr=-sse41,-sse3,+sse2 < %s | \
+; RUN: FileCheck %s
; rdar://6808032
+; CHECK: pextrw $14
+; CHECK-NEXT: movzbl
+; CHECK-NEXT: (%ebp)
+; CHECK-NEXT: pinsrw
+
define void @update(i8** %args_list) nounwind {
entry:
%cmp.i = icmp eq i32 0, 0 ; <i1> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-24.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-24.ll
index 2835c2d..c1ec45f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-24.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-24.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -regalloc=local -relocation-model=pic > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -regalloc=local -relocation-model=pic > %t
; RUN: grep {leal.*TLSGD.*___tls_get_addr} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=local -relocation-model=pic > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=local -relocation-model=pic > %t2
; RUN: grep {leaq.*TLSGD.*__tls_get_addr} %t2
; PR4004
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
index 981d327..94d3eb2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 2
+; RUN: llc < %s -march=x86-64 | grep mov | count 2
; rdar://6806252
define i64 @test(i32* %tmp13) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll
index b804a5b..7981a52 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
; PR4034
%struct.BiContextType = type { i16, i8 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll
index 1b757b1..d77e528 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9
+; RUN: llc < %s -mtriple=i386-apple-darwin9
; PR4056
define void @int163(i32 %p_4, i32 %p_5) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll
index 70cb4ff..f025654 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9
+; RUN: llc < %s -mtriple=i386-apple-darwin9
; PR4051
define void @int163(i32 %p_4, i32 %p_5) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll
index 0fb000c..0a2fcdb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-unknown-linux-gnu | grep cmpxchgl | not grep eax
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | grep cmpxchgl | not grep eax
; PR4076
type { i8, i8, i8 } ; type %0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll
index fc31c0b..a2fd2e4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep {movl.*%ebx, 8(%esi)}
+; RUN: llc < %s | grep {movl.*%ebx, 8(%esi)}
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-LinearScanBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-LinearScanBug.ll
index 767eb31..6843723 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-LinearScanBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-LinearScanBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin10
+; RUN: llc < %s -mtriple=i386-apple-darwin10
; rdar://6837009
type { %struct.pf_state*, %struct.pf_state*, %struct.pf_state*, i32 } ; type %0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-RegAllocAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-RegAllocAssert.ll
index c02c045..d1f9cf8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-RegAllocAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-29-RegAllocAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10 -disable-fp-elim -relocation-model=pic
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -disable-fp-elim -relocation-model=pic
; PR4099
type { [62 x %struct.Bitvec*] } ; type %0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-scale.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-scale.ll
index 0766dc7..e4c756c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-04-scale.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-04-scale.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-unknown-linux-gnu
+; RUN: llc < %s -march=x86 -mtriple=i386-unknown-linux-gnu
; PR3995
%struct.vtable = type { i32 (...)** }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
index 284c6e2..738b5fb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -relocation-model=static > %t
+; RUN: llc < %s -relocation-model=static > %t
; RUN: grep "1: ._pv_cpu_ops+8" %t
; RUN: grep "2: ._G" %t
; PR4152
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-11-tailmerge-crash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-11-tailmerge-crash.ll
index 8178725..a5e28c0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-11-tailmerge-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-11-tailmerge-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR4188
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-19-SingleElementExtractElement.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-19-SingleElementExtractElement.ll
index 42bf9e9..6e062fb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-19-SingleElementExtractElement.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-19-SingleElementExtractElement.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
; PR3886
define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-23-available_externally.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-23-available_externally.ll
index f4881ba..94773d9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-23-available_externally.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-23-available_externally.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -relocation-model=pic | grep atoi | grep PLT
+; RUN: llc < %s -relocation-model=pic | grep atoi | grep PLT
; PR4253
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
index 6f2bef4..8a0b244 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep -E {sar|shl|mov|or} | count 4
+; RUN: llc < %s | grep -E {sar|shl|mov|or} | count 4
; Check that the shr(shl X, 56), 48) is not mistakenly turned into
; a shr (X, -8) that gets subsequently "optimized away" as undef
; PR4254
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll
index 7bdfcb3..2fd42f4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
%struct.tempsym_t = type { i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll
index 373f91f..af552d4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep {movzbl %\[abcd\]h,}
+; RUN: llc < %s -march=x86-64 | not grep {movzbl %\[abcd\]h,}
define void @BZ2_bzDecompress_bb5_2E_outer_bb35_2E_i_bb54_2E_i(i32*, i32 %c_nblock_used.2.i, i32 %.reload51, i32* %.out, i32* %.out1, i32* %.out2, i32* %.out3) nounwind {
newFuncRoot:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-02-RewriterBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-02-RewriterBug.ll
index ea33b16..779f985 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-02-RewriterBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-02-RewriterBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-undermydesk-freebsd8.0 -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -mtriple=x86_64-undermydesk-freebsd8.0 -relocation-model=pic -disable-fp-elim
; PR4225
define void @sha256_block1(i32* nocapture %arr, i8* nocapture %in, i64 %num) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
index a96fcb2..e6f3008 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep "subq.*\\\$40, \\\%rsp"
+; RUN: llc < %s | grep "subq.*\\\$40, \\\%rsp"
target triple = "x86_64-mingw64"
define x86_fp80 @a(i64 %x) nounwind readnone {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
index a0b13f7..cb64bf2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -o %t1
+; RUN: llc < %s -o %t1
; RUN: grep "subq.*\\\$72, \\\%rsp" %t1
; RUN: grep "movaps \\\%xmm8, 32\\\(\\\%rsp\\\)" %t1
; RUN: grep "movaps \\\%xmm7, 48\\\(\\\%rsp\\\)" %t1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
index fa90fa9..9415732 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
type { %struct.GAP } ; type %0
type { i16, i8, i8 } ; type %1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll
index 94df530..336f17e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | not grep movl
+; RUN: llc < %s -march=x86 -mattr=+mmx | not grep movl
define <8 x i8> @a(i8 zeroext %x) nounwind {
%r = insertelement <8 x i8> undef, i8 %x, i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-VZextByteShort.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
index 220423a..5c51480 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx,+sse2 > %t1
+; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 > %t1
; RUN: grep movzwl %t1 | count 2
; RUN: grep movzbl %t1 | count 2
; RUN: grep movd %t1 | count 4
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll
index 2e3f195..8bb3dc6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define <2 x i64> @_mm_insert_epi16(<2 x i64> %a, i32 %b, i32 %imm) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-sitofpCrash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-sitofpCrash.ll
index 589a880..e361804 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-sitofpCrash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-05-sitofpCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse
+; RUN: llc < %s -march=x86 -mattr=+sse
; PR2598
define <2 x float> @a(<2 x i32> %i) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-06-ConcatVectors.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-06-ConcatVectors.ll
index a46fd1a..92419fc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-06-ConcatVectors.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-06-ConcatVectors.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
define <2 x i64> @_mm_movpi64_pi64(<1 x i64> %a, <1 x i64> %b) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
index c3687a5..07ef53e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep movl | count 2
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep movl | count 2
define i64 @a(i32 %a, i32 %b) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
index 001b7fc..673e936 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -tailcallopt -march=x86-64 -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep fstpt
-; RUN: llvm-as < %s | llc -tailcallopt -march=x86-64 -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep xmm
+; RUN: llc < %s -tailcallopt -march=x86-64 -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep fstpt
+; RUN: llc < %s -tailcallopt -march=x86-64 -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep xmm
; Check that x86-64 tail calls support x86_fp80 and v2f32 types. (Tail call
; calling convention out of sync with standard c calling convention on x86_64)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll
index 095e6a1..feb5780 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | not grep TAILCALL
+; RUN: llc < %s -march=x86 -tailcallopt | not grep TAILCALL
; Bug 4396. This tail call can NOT be optimized.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll
index d6ff5b6..228cd48 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2
+; RUN: llc < %s -march=x86 -mattr=+sse,-sse2
; PR2484
define <4 x float> @f4523(<4 x float> %a,<4 x float> %b) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-06-TwoAddrAssert.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-06-TwoAddrAssert.ll
index 71b46f2..fcc71ae 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-06-TwoAddrAssert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-06-TwoAddrAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=x86_64-unknown-freebsd7.2
+; RUN: llc < %s -march=x86 -mtriple=x86_64-unknown-freebsd7.2
; PR4478
%struct.sockaddr = type <{ i8, i8, [14 x i8] }>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-07-SplitICmp.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-07-SplitICmp.ll
index 9a7b52d..eb9378b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-07-SplitICmp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-07-SplitICmp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -disable-mmx
+; RUN: llc < %s -march=x86 -disable-mmx
define void @test2(<2 x i32> %A, <2 x i32> %B, <2 x i32>* %C) nounwind {
%D = icmp sgt <2 x i32> %A, %B
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-09-ExtractBoolFromVector.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-09-ExtractBoolFromVector.ll
index 62a62a6..0fdfdcb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-09-ExtractBoolFromVector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-09-ExtractBoolFromVector.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR3037
define void @entry(<4 x i8>* %dest) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-15-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-15-CoalescerBug.ll
index ce91800..eabaf77 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-15-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-15-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10
%struct.ANY = type { i8* }
%struct.AV = type { %struct.XPVAV*, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-16-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-16-CoalescerBug.ll
index f79b3da..48af440 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-16-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-16-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10
; rdar://7059496
%struct.brinfo = type <{ %struct.brinfo*, %struct.brinfo*, i8*, i32, i32, i32, i8, i8, i8, i8 }>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-16-LoadFoldingBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-16-LoadFoldingBug.ll
index 86aa38c..e21c892 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-16-LoadFoldingBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-16-LoadFoldingBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
; CHECK: _foo:
; CHECK: pavgw LCPI1_4(%rip)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-17-StackColoringBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-17-StackColoringBug.ll
index 172b6ec..3e5bd34 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-17-StackColoringBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-17-StackColoringBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu -disable-fp-elim -color-ss-with-regs | not grep dil
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -disable-fp-elim -color-ss-with-regs | not grep dil
; PR4552
target triple = "i386-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-19-AsmExtraOperands.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-19-AsmExtraOperands.ll
index 31322cf..a0095ab 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-19-AsmExtraOperands.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-19-AsmExtraOperands.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
; PR4583
define i32 @atomic_cmpset_long(i64* %dst, i64 %exp, i64 %src) nounwind ssp noredzone noimplicitfloat {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-20-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-20-CoalescerBug.ll
index 8f12f0b..e99edd6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-20-CoalescerBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-20-CoalescerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10
; PR4587
; rdar://7072590
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll
index 51aa88d..e83b3a7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
@bsBuff = internal global i32 0 ; <i32*> [#uses=1]
@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @bsGetUInt32 to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll
index 083538a..b9b09a3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
; PR4669
declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-06-branchfolder-crash.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-06-branchfolder-crash.ll
index 2c8cf0c..b329c91 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-06-branchfolder-crash.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-06-branchfolder-crash.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O3
+; RUN: llc < %s -O3
; PR4626
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-06-inlineasm.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-06-inlineasm.ll
index b1c2b28..cc2f3d8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-06-inlineasm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-06-inlineasm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR4668
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-08-CastError.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-08-CastError.ll
index 6edc518..9456d91 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-08-CastError.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-08-CastError.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-mingw64 | grep movabsq
+; RUN: llc < %s -mtriple=x86_64-mingw64 | grep movabsq
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll
index be910ff..a94fce0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep LJT
+; RUN: llc < %s | grep LJT
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin10"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-14-Win64MemoryIndirectArg.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-14-Win64MemoryIndirectArg.ll
index 5431462..6b0d6d9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-14-Win64MemoryIndirectArg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-14-Win64MemoryIndirectArg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target triple = "x86_64-mingw"
; ModuleID = 'mm.bc'
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll
index 8fa27eb..5f6cf3b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-pc-linux | FileCheck %s
+; RUN: llc < %s -march=x86 -mtriple=i386-pc-linux | FileCheck %s
@a = external global i96, align 4
@b = external global i64, align 8
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll
index 5e74f9e..790fd88 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR4753
; This function has a sub-register reuse undone.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-23-linkerprivate.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-23-linkerprivate.ll
index 615c963..3da8f00 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/2009-08-23-linkerprivate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-08-23-linkerprivate.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-apple-darwin | FileCheck %s
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin | FileCheck %s
; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm'
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-09-07-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-07-CoalescerBug.ll
new file mode 100644
index 0000000..55432be
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-07-CoalescerBug.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-freebsd7.2 -code-model=kernel | FileCheck %s
+; PR4689
+
+%struct.__s = type { [8 x i8] }
+%struct.pcb = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i16, i8* }
+%struct.pcpu = type { i32*, i32*, i32*, i32*, %struct.pcb*, i64, i32, i32, i32, i32 }
+
+define i64 @hammer_time(i64 %modulep, i64 %physfree) nounwind ssp noredzone noimplicitfloat {
+; CHECK: hammer_time:
+; CHECK: movq $Xrsvd, %rax
+; CHECK: movq $Xrsvd, %rdi
+; CHECK: movq $Xrsvd, %r8
+entry:
+ br i1 undef, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ br label %for.body
+
+for.body: ; preds = %for.inc, %if.end
+ switch i32 undef, label %if.then76 [
+ i32 9, label %for.inc
+ i32 10, label %for.inc
+ i32 11, label %for.inc
+ i32 12, label %for.inc
+ ]
+
+if.then76: ; preds = %for.body
+ unreachable
+
+for.inc: ; preds = %for.body, %for.body, %for.body, %for.body
+ br i1 undef, label %for.end, label %for.body
+
+for.end: ; preds = %for.inc
+ call void asm sideeffect "mov $1,%gs:$0", "=*m,r,~{dirflag},~{fpsr},~{flags}"(%struct.__s* bitcast (%struct.pcb** getelementptr (%struct.pcpu* null, i32 0, i32 4) to %struct.__s*), i64 undef) nounwind
+ br label %for.body170
+
+for.body170: ; preds = %for.body170, %for.end
+ store i64 or (i64 and (i64 or (i64 ptrtoint (void (i32, i32, i32, i32)* @Xrsvd to i64), i64 2097152), i64 2162687), i64 or (i64 or (i64 and (i64 shl (i64 ptrtoint (void (i32, i32, i32, i32)* @Xrsvd to i64), i64 32), i64 -281474976710656), i64 140737488355328), i64 15393162788864)), i64* undef
+ br i1 undef, label %for.end175, label %for.body170
+
+for.end175: ; preds = %for.body170
+ unreachable
+}
+
+declare void @Xrsvd(i32, i32, i32, i32) ssp noredzone noimplicitfloat
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll
new file mode 100644
index 0000000..9e58872
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim | FileCheck %s
+
+; It's not legal to fold a load from 32-bit stack slot into a 64-bit
+; instruction. If done, the instruction does a 64-bit load and that's not
+; safe. This can happen we a subreg_to_reg 0 has been coalesced. One
+; exception is when the instruction that folds the load is a move, then we
+; can simply turn it into a 32-bit load from the stack slot.
+; rdar://7170444
+
+%struct.ComplexType = type { i32 }
+
+define i32 @t(i32 %clientPort, i32 %pluginID, i32 %requestID, i32 %objectID, i64 %serverIdentifier, i64 %argumentsData, i32 %argumentsLength) ssp {
+entry:
+; CHECK: _t:
+; CHECK: movl 16(%rbp),
+; CHECK: movl 16(%rbp), %edx
+ %0 = zext i32 %argumentsLength to i64 ; <i64> [#uses=1]
+ %1 = zext i32 %clientPort to i64 ; <i64> [#uses=1]
+ %2 = inttoptr i64 %1 to %struct.ComplexType* ; <%struct.ComplexType*> [#uses=1]
+ %3 = invoke i8* @pluginInstance(i8* undef, i32 %pluginID)
+ to label %invcont unwind label %lpad ; <i8*> [#uses=1]
+
+invcont: ; preds = %entry
+ %4 = add i32 %requestID, %pluginID ; <i32> [#uses=0]
+ %5 = invoke zeroext i8 @invoke(i8* %3, i32 %objectID, i8* undef, i64 %argumentsData, i32 %argumentsLength, i64* undef, i32* undef)
+ to label %invcont1 unwind label %lpad ; <i8> [#uses=0]
+
+invcont1: ; preds = %invcont
+ %6 = getelementptr inbounds %struct.ComplexType* %2, i64 0, i32 0 ; <i32*> [#uses=1]
+ %7 = load i32* %6, align 4 ; <i32> [#uses=1]
+ invoke void @booleanAndDataReply(i32 %7, i32 undef, i32 %requestID, i32 undef, i64 undef, i32 undef)
+ to label %invcont2 unwind label %lpad
+
+invcont2: ; preds = %invcont1
+ ret i32 0
+
+lpad: ; preds = %invcont1, %invcont, %entry
+ %8 = call i32 @vm_deallocate(i32 undef, i64 0, i64 %0) ; <i32> [#uses=0]
+ unreachable
+}
+
+declare i32 @vm_deallocate(i32, i64, i64)
+
+declare i8* @pluginInstance(i8*, i32)
+
+declare zeroext i8 @invoke(i8*, i32, i8*, i64, i32, i64*, i32*)
+
+declare void @booleanAndDataReply(i32, i32, i32, i32, i64, i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-09-16-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-16-CoalescerBug.ll
new file mode 100644
index 0000000..18b5a17
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-16-CoalescerBug.ll
@@ -0,0 +1,64 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10
+; PR4910
+
+%0 = type { i32, i32, i32, i32 }
+
+ at boot_cpu_id = external global i32 ; <i32*> [#uses=1]
+ at cpu_logical = common global i32 0, align 4 ; <i32*> [#uses=1]
+
+define void @topo_probe_0xb() nounwind ssp {
+entry:
+ br label %for.cond
+
+for.cond: ; preds = %for.inc38, %entry
+ %0 = phi i32 [ 0, %entry ], [ %inc40, %for.inc38 ] ; <i32> [#uses=3]
+ %cmp = icmp slt i32 %0, 3 ; <i1> [#uses=1]
+ br i1 %cmp, label %for.body, label %for.end41
+
+for.body: ; preds = %for.cond
+ %1 = tail call %0 asm sideeffect "cpuid", "={ax},={bx},={cx},={dx},0,{cx},~{dirflag},~{fpsr},~{flags}"(i32 11, i32 %0) nounwind ; <%0> [#uses=3]
+ %asmresult.i = extractvalue %0 %1, 0 ; <i32> [#uses=1]
+ %asmresult10.i = extractvalue %0 %1, 2 ; <i32> [#uses=1]
+ %and = and i32 %asmresult.i, 31 ; <i32> [#uses=2]
+ %shr42 = lshr i32 %asmresult10.i, 8 ; <i32> [#uses=1]
+ %and12 = and i32 %shr42, 255 ; <i32> [#uses=2]
+ %cmp14 = icmp eq i32 %and12, 0 ; <i1> [#uses=1]
+ br i1 %cmp14, label %for.end41, label %lor.lhs.false
+
+lor.lhs.false: ; preds = %for.body
+ %asmresult9.i = extractvalue %0 %1, 1 ; <i32> [#uses=1]
+ %and7 = and i32 %asmresult9.i, 65535 ; <i32> [#uses=1]
+ %cmp16 = icmp eq i32 %and7, 0 ; <i1> [#uses=1]
+ br i1 %cmp16, label %for.end41, label %for.cond17.preheader
+
+for.cond17.preheader: ; preds = %lor.lhs.false
+ %tmp24 = load i32* @boot_cpu_id ; <i32> [#uses=1]
+ %shr26 = ashr i32 %tmp24, %and ; <i32> [#uses=1]
+ br label %for.body20
+
+for.body20: ; preds = %for.body20, %for.cond17.preheader
+ %2 = phi i32 [ 0, %for.cond17.preheader ], [ %inc32, %for.body20 ] ; <i32> [#uses=2]
+ %cnt.143 = phi i32 [ 0, %for.cond17.preheader ], [ %inc.cnt.1, %for.body20 ] ; <i32> [#uses=1]
+ %shr23 = ashr i32 %2, %and ; <i32> [#uses=1]
+ %cmp27 = icmp eq i32 %shr23, %shr26 ; <i1> [#uses=1]
+ %inc = zext i1 %cmp27 to i32 ; <i32> [#uses=1]
+ %inc.cnt.1 = add i32 %inc, %cnt.143 ; <i32> [#uses=2]
+ %inc32 = add nsw i32 %2, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %inc32, 255 ; <i1> [#uses=1]
+ br i1 %exitcond, label %for.end, label %for.body20
+
+for.end: ; preds = %for.body20
+ %cmp34 = icmp eq i32 %and12, 1 ; <i1> [#uses=1]
+ br i1 %cmp34, label %if.then35, label %for.inc38
+
+if.then35: ; preds = %for.end
+ store i32 %inc.cnt.1, i32* @cpu_logical
+ br label %for.inc38
+
+for.inc38: ; preds = %for.end, %if.then35
+ %inc40 = add nsw i32 %0, 1 ; <i32> [#uses=1]
+ br label %for.cond
+
+for.end41: ; preds = %lor.lhs.false, %for.body, %for.cond
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll
new file mode 100644
index 0000000..646806e
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s
+
+; PR4958
+
+define i32 @main() nounwind ssp {
+entry:
+; CHECK: main:
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ br label %bb
+
+bb: ; preds = %bb1, %entry
+; CHECK: movl %e
+; CHECK-NEXT: addl $1
+; CHECK-NEXT: movl %e
+; CHECK-NEXT: adcl $0
+ %i.0 = phi i64 [ 0, %entry ], [ %0, %bb1 ] ; <i64> [#uses=1]
+ %0 = add nsw i64 %i.0, 1 ; <i64> [#uses=2]
+ %1 = icmp sgt i32 0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %bb2, label %bb1
+
+bb1: ; preds = %bb
+ %2 = icmp sle i64 %0, 1 ; <i1> [#uses=1]
+ br i1 %2, label %bb, label %bb2
+
+bb2: ; preds = %bb1, %bb
+ br label %return
+
+return: ; preds = %bb2
+ ret i32 0
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-09-19-earlyclobber.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-19-earlyclobber.ll
new file mode 100644
index 0000000..4f44cae
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-19-earlyclobber.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s | FileCheck %s
+; ModuleID = '4964.c'
+; PR 4964
+; Registers other than RAX, RCX are OK, but they must be different.
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin10.0"
+ type { i64, i64 } ; type %0
+
+define i64 @flsst(i64 %find) nounwind ssp {
+entry:
+; CHECK: FOO %rax %rcx
+ %asmtmp = tail call %0 asm sideeffect "FOO $0 $1 $2", "=r,=&r,rm,~{dirflag},~{fpsr},~{flags},~{cc}"(i64 %find) nounwind ; <%0> [#uses=1]
+ %asmresult = extractvalue %0 %asmtmp, 0 ; <i64> [#uses=1]
+ ret i64 %asmresult
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
new file mode 100644
index 0000000..80b8835
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10.0 -relocation-model=pic | FileCheck %s
+
+define void @dot(i16* nocapture %A, i32 %As, i16* nocapture %B, i32 %Bs, i16* nocapture %C, i32 %N) nounwind ssp {
+; CHECK: dot:
+; CHECK: decl %
+; CHECK-NEXT: jne
+entry:
+ %0 = icmp sgt i32 %N, 0 ; <i1> [#uses=1]
+ br i1 %0, label %bb, label %bb2
+
+bb: ; preds = %bb, %entry
+ %i.03 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
+ %sum.04 = phi i32 [ 0, %entry ], [ %10, %bb ] ; <i32> [#uses=1]
+ %1 = mul i32 %i.03, %As ; <i32> [#uses=1]
+ %2 = getelementptr i16* %A, i32 %1 ; <i16*> [#uses=1]
+ %3 = load i16* %2, align 2 ; <i16> [#uses=1]
+ %4 = sext i16 %3 to i32 ; <i32> [#uses=1]
+ %5 = mul i32 %i.03, %Bs ; <i32> [#uses=1]
+ %6 = getelementptr i16* %B, i32 %5 ; <i16*> [#uses=1]
+ %7 = load i16* %6, align 2 ; <i16> [#uses=1]
+ %8 = sext i16 %7 to i32 ; <i32> [#uses=1]
+ %9 = mul i32 %8, %4 ; <i32> [#uses=1]
+ %10 = add i32 %9, %sum.04 ; <i32> [#uses=2]
+ %indvar.next = add i32 %i.03, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb1.bb2_crit_edge, label %bb
+
+bb1.bb2_crit_edge: ; preds = %bb
+ %phitmp = trunc i32 %10 to i16 ; <i16> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %entry, %bb1.bb2_crit_edge
+ %sum.0.lcssa = phi i16 [ %phitmp, %bb1.bb2_crit_edge ], [ 0, %entry ] ; <i16> [#uses=1]
+ store i16 %sum.0.lcssa, i16* %C, align 2
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-09-22-CoalescerBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-22-CoalescerBug.ll
new file mode 100644
index 0000000..33f35f8
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-22-CoalescerBug.ll
@@ -0,0 +1,124 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp {
+entry:
+ br i1 undef, label %bb, label %bb1
+
+bb: ; preds = %entry
+ ret i32 3
+
+bb1: ; preds = %entry
+ br i1 undef, label %bb3, label %bb2
+
+bb2: ; preds = %bb1
+ ret i32 3
+
+bb3: ; preds = %bb1
+ br i1 undef, label %bb.i18, label %quantum_getwidth.exit
+
+bb.i18: ; preds = %bb.i18, %bb3
+ br i1 undef, label %bb.i18, label %quantum_getwidth.exit
+
+quantum_getwidth.exit: ; preds = %bb.i18, %bb3
+ br i1 undef, label %bb4, label %bb6.preheader
+
+bb4: ; preds = %quantum_getwidth.exit
+ unreachable
+
+bb6.preheader: ; preds = %quantum_getwidth.exit
+ br i1 undef, label %bb.i1, label %bb1.i2
+
+bb.i1: ; preds = %bb6.preheader
+ unreachable
+
+bb1.i2: ; preds = %bb6.preheader
+ br i1 undef, label %bb2.i, label %bb3.i4
+
+bb2.i: ; preds = %bb1.i2
+ unreachable
+
+bb3.i4: ; preds = %bb1.i2
+ br i1 undef, label %quantum_new_qureg.exit, label %bb4.i
+
+bb4.i: ; preds = %bb3.i4
+ unreachable
+
+quantum_new_qureg.exit: ; preds = %bb3.i4
+ br i1 undef, label %bb9, label %bb11.thread
+
+bb11.thread: ; preds = %quantum_new_qureg.exit
+ %.cast.i = zext i32 undef to i64 ; <i64> [#uses=1]
+ br label %bb.i37
+
+bb9: ; preds = %quantum_new_qureg.exit
+ unreachable
+
+bb.i37: ; preds = %bb.i37, %bb11.thread
+ %0 = load i64* undef, align 8 ; <i64> [#uses=1]
+ %1 = shl i64 %0, %.cast.i ; <i64> [#uses=1]
+ store i64 %1, i64* undef, align 8
+ br i1 undef, label %bb.i37, label %quantum_addscratch.exit
+
+quantum_addscratch.exit: ; preds = %bb.i37
+ br i1 undef, label %bb12.preheader, label %bb14
+
+bb12.preheader: ; preds = %quantum_addscratch.exit
+ unreachable
+
+bb14: ; preds = %quantum_addscratch.exit
+ br i1 undef, label %bb17, label %bb.nph
+
+bb.nph: ; preds = %bb14
+ unreachable
+
+bb17: ; preds = %bb14
+ br i1 undef, label %bb1.i7, label %quantum_measure.exit
+
+bb1.i7: ; preds = %bb17
+ br label %quantum_measure.exit
+
+quantum_measure.exit: ; preds = %bb1.i7, %bb17
+ switch i32 undef, label %bb21 [
+ i32 -1, label %bb18
+ i32 0, label %bb20
+ ]
+
+bb18: ; preds = %quantum_measure.exit
+ unreachable
+
+bb20: ; preds = %quantum_measure.exit
+ unreachable
+
+bb21: ; preds = %quantum_measure.exit
+ br i1 undef, label %quantum_frac_approx.exit, label %bb1.i
+
+bb1.i: ; preds = %bb21
+ unreachable
+
+quantum_frac_approx.exit: ; preds = %bb21
+ br i1 undef, label %bb25, label %bb26
+
+bb25: ; preds = %quantum_frac_approx.exit
+ unreachable
+
+bb26: ; preds = %quantum_frac_approx.exit
+ br i1 undef, label %quantum_gcd.exit, label %bb.i
+
+bb.i: ; preds = %bb.i, %bb26
+ br i1 undef, label %quantum_gcd.exit, label %bb.i
+
+quantum_gcd.exit: ; preds = %bb.i, %bb26
+ br i1 undef, label %bb32, label %bb33
+
+bb32: ; preds = %quantum_gcd.exit
+ br i1 undef, label %bb.i.i, label %quantum_delete_qureg.exit
+
+bb.i.i: ; preds = %bb32
+ ret i32 0
+
+quantum_delete_qureg.exit: ; preds = %bb32
+ ret i32 0
+
+bb33: ; preds = %quantum_gcd.exit
+ unreachable
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/2009-09-23-LiveVariablesBug.ll b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-23-LiveVariablesBug.ll
new file mode 100644
index 0000000..d37d4b8
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/2009-09-23-LiveVariablesBug.ll
@@ -0,0 +1,91 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10
+
+; rdar://7247745
+
+%struct._lck_mtx_ = type { %union.anon }
+%struct._lck_rw_t_internal_ = type <{ i16, i8, i8, i32, i32, i32 }>
+%struct.anon = type { i64, i64, [2 x i8], i8, i8, i32 }
+%struct.memory_object = type { i32, i32, %struct.memory_object_pager_ops* }
+%struct.memory_object_control = type { i32, i32, %struct.vm_object* }
+%struct.memory_object_pager_ops = type { void (%struct.memory_object*)*, void (%struct.memory_object*)*, i32 (%struct.memory_object*, %struct.memory_object_control*, i32)*, i32 (%struct.memory_object*)*, i32 (%struct.memory_object*, i64, i32, i32, i32*)*, i32 (%struct.memory_object*, i64, i32, i64*, i32*, i32, i32, i32)*, i32 (%struct.memory_object*, i64, i32)*, i32 (%struct.memory_object*, i64, i64, i32)*, i32 (%struct.memory_object*, i64, i64, i32)*, i32 (%struct.memory_object*, i32)*, i32 (%struct.memory_object*)*, i8* }
+%struct.queue_entry = type { %struct.queue_entry*, %struct.queue_entry* }
+%struct.upl = type { %struct._lck_mtx_, i32, i32, %struct.vm_object*, i64, i32, i64, %struct.vm_object*, i32, i8* }
+%struct.upl_page_info = type <{ i32, i8, [3 x i8] }>
+%struct.vm_object = type { %struct.queue_entry, %struct._lck_rw_t_internal_, i64, %struct.vm_page*, i32, i32, i32, i32, %struct.vm_object*, %struct.vm_object*, i64, %struct.memory_object*, i64, %struct.memory_object_control*, i32, i16, i16, [2 x i8], i8, i8, %struct.queue_entry, %struct.queue_entry, i64, i32, i32, i32, i8*, i64, i8, i8, [2 x i8], %struct.queue_entry }
+%struct.vm_page = type { %struct.queue_entry, %struct.queue_entry, %struct.vm_page*, %struct.vm_object*, i64, [2 x i8], i8, i8, i32, i8, i8, i8, i8, i32 }
+%union.anon = type { %struct.anon }
+
+declare i64 @OSAddAtomic64(i64, i64*) noredzone noimplicitfloat
+
+define i32 @upl_commit_range(%struct.upl* %upl, i32 %offset, i32 %size, i32 %flags, %struct.upl_page_info* %page_list, i32 %count, i32* nocapture %empty) nounwind noredzone noimplicitfloat {
+entry:
+ br i1 undef, label %if.then, label %if.end
+
+if.end: ; preds = %entry
+ br i1 undef, label %if.end143, label %if.then136
+
+if.then136: ; preds = %if.end
+ unreachable
+
+if.end143: ; preds = %if.end
+ br i1 undef, label %if.else155, label %if.then153
+
+if.then153: ; preds = %if.end143
+ br label %while.cond
+
+if.else155: ; preds = %if.end143
+ unreachable
+
+while.cond: ; preds = %if.end1039, %if.then153
+ br i1 undef, label %if.then1138, label %while.body
+
+while.body: ; preds = %while.cond
+ br i1 undef, label %if.end260, label %if.then217
+
+if.then217: ; preds = %while.body
+ br i1 undef, label %if.end260, label %if.then230
+
+if.then230: ; preds = %if.then217
+ br i1 undef, label %if.then246, label %if.end260
+
+if.then246: ; preds = %if.then230
+ br label %if.end260
+
+if.end260: ; preds = %if.then246, %if.then230, %if.then217, %while.body
+ br i1 undef, label %if.end296, label %if.then266
+
+if.then266: ; preds = %if.end260
+ unreachable
+
+if.end296: ; preds = %if.end260
+ br i1 undef, label %if.end1039, label %if.end306
+
+if.end306: ; preds = %if.end296
+ br i1 undef, label %if.end796, label %if.then616
+
+if.then616: ; preds = %if.end306
+ br i1 undef, label %commit_next_page, label %do.body716
+
+do.body716: ; preds = %if.then616
+ %call721 = call i64 @OSAddAtomic64(i64 1, i64* undef) nounwind noredzone noimplicitfloat ; <i64> [#uses=0]
+ call void asm sideeffect "movq\090x0($0),%rdi\0A\09movq\090x8($0),%rsi\0A\09.section __DATA, __data\0A\09.globl __dtrace_probeDOLLAR${:uid}4794___vminfo____pgrec\0A\09__dtrace_probeDOLLAR${:uid}4794___vminfo____pgrec:.quad 1f\0A\09.text\0A\091:nop\0A\09nop\0A\09nop\0A\09", "r,~{memory},~{di},~{si},~{dirflag},~{fpsr},~{flags}"(i64* undef) nounwind
+ br label %commit_next_page
+
+if.end796: ; preds = %if.end306
+ unreachable
+
+commit_next_page: ; preds = %do.body716, %if.then616
+ br i1 undef, label %if.end1039, label %if.then1034
+
+if.then1034: ; preds = %commit_next_page
+ br label %if.end1039
+
+if.end1039: ; preds = %if.then1034, %commit_next_page, %if.end296
+ br label %while.cond
+
+if.then1138: ; preds = %while.cond
+ unreachable
+
+if.then: ; preds = %entry
+ ret i32 4
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/20090313-signext.ll b/libclamav/c++/llvm/test/CodeGen/X86/20090313-signext.ll
index 7313670..de930d5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/20090313-signext.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/20090313-signext.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=pic > %t
+; RUN: llc < %s -march=x86-64 -relocation-model=pic > %t
; RUN: grep {movswl %ax, %edi} %t
; RUN: grep {movw (%rax), %ax} %t
; XFAIL: *
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/Atomics-32.ll b/libclamav/c++/llvm/test/CodeGen/X86/Atomics-32.ll
index 2a3e228..0e9b73e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/Atomics-32.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/Atomics-32.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
;; Note the 64-bit variants are not supported yet (in 32-bit mode).
; ModuleID = 'Atomics.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/Atomics-64.ll b/libclamav/c++/llvm/test/CodeGen/X86/Atomics-64.ll
index 37b2e33..ac174b9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/Atomics-64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/Atomics-64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; ModuleID = 'Atomics.c'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/abi-isel.ll b/libclamav/c++/llvm/test/CodeGen/X86/abi-isel.ll
index 3f1d0b6..a6fd2d8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/abi-isel.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/abi-isel.ll
@@ -1,16 +1,16 @@
-; RUN: llvm-as < %s | llc -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-STATIC
-; RUN: llvm-as < %s | llc -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-PIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-PIC
-; RUN: llvm-as < %s | llc -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-64-STATIC
-; RUN: llvm-as < %s | llc -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=LINUX-64-PIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-64-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=LINUX-64-PIC
-; RUN: llvm-as < %s | llc -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-32-STATIC
-; RUN: llvm-as < %s | llc -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC
-; RUN: llvm-as < %s | llc -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-PIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-32-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-PIC
-; RUN: llvm-as < %s | llc -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-64-STATIC
-; RUN: llvm-as < %s | llc -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC
-; RUN: llvm-as < %s | llc -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-64-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC
@src = external global [131072 x i32]
@dst = external global [131072 x i32]
@@ -72,12 +72,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _foo00:
-; DARWIN-32-PIC: call "L1$pb"
-; DARWIN-32-PIC-NEXT: "L1$pb":
+; DARWIN-32-PIC: call L1$pb
+; DARWIN-32-PIC-NEXT: L1$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L1$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L1$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L1$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L1$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -144,12 +144,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _fxo00:
-; DARWIN-32-PIC: call "L2$pb"
-; DARWIN-32-PIC-NEXT: "L2$pb":
+; DARWIN-32-PIC: call L2$pb
+; DARWIN-32-PIC-NEXT: L2$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L2$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L2$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L2$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L2$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -208,11 +208,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _foo01:
-; DARWIN-32-PIC: call "L3$pb"
-; DARWIN-32-PIC-NEXT: "L3$pb":
+; DARWIN-32-PIC: call L3$pb
+; DARWIN-32-PIC-NEXT: L3$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L3$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L3$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L3$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L3$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -268,11 +268,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _fxo01:
-; DARWIN-32-PIC: call "L4$pb"
-; DARWIN-32-PIC-NEXT: "L4$pb":
+; DARWIN-32-PIC: call L4$pb
+; DARWIN-32-PIC-NEXT: L4$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L4$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L4$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L4$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L4$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -342,12 +342,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _foo02:
-; DARWIN-32-PIC: call "L5$pb"
-; DARWIN-32-PIC-NEXT: "L5$pb":
+; DARWIN-32-PIC: call L5$pb
+; DARWIN-32-PIC-NEXT: L5$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L5$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L5$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L5$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L5$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -424,12 +424,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _fxo02:
-; DARWIN-32-PIC: call "L6$pb"
-; DARWIN-32-PIC-NEXT: "L6$pb":
+; DARWIN-32-PIC: call L6$pb
+; DARWIN-32-PIC-NEXT: L6$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L6$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L6$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L6$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L6$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -497,11 +497,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _foo03:
-; DARWIN-32-PIC: call "L7$pb"
-; DARWIN-32-PIC-NEXT: "L7$pb":
+; DARWIN-32-PIC: call L7$pb
+; DARWIN-32-PIC-NEXT: L7$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _dsrc-"L7$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _ddst-"L7$pb"(%eax)
+; DARWIN-32-PIC-NEXT: movl _dsrc-L7$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _ddst-L7$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _foo03:
@@ -551,11 +551,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _foo04:
-; DARWIN-32-PIC: call "L8$pb"
-; DARWIN-32-PIC-NEXT: "L8$pb":
+; DARWIN-32-PIC: call L8$pb
+; DARWIN-32-PIC-NEXT: L8$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ddst-"L8$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-"L8$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal _ddst-L8$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L8$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _foo04:
@@ -619,11 +619,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _foo05:
-; DARWIN-32-PIC: call "L9$pb"
-; DARWIN-32-PIC-NEXT: "L9$pb":
+; DARWIN-32-PIC: call L9$pb
+; DARWIN-32-PIC-NEXT: L9$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _dsrc-"L9$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl _dptr-"L9$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _dsrc-L9$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _dptr-L9$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -682,11 +682,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _foo06:
-; DARWIN-32-PIC: call "L10$pb"
-; DARWIN-32-PIC-NEXT: "L10$pb":
+; DARWIN-32-PIC: call L10$pb
+; DARWIN-32-PIC-NEXT: L10$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _lsrc-"L10$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _ldst-"L10$pb"(%eax)
+; DARWIN-32-PIC-NEXT: movl _lsrc-L10$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _ldst-L10$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _foo06:
@@ -735,11 +735,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _foo07:
-; DARWIN-32-PIC: call "L11$pb"
-; DARWIN-32-PIC-NEXT: "L11$pb":
+; DARWIN-32-PIC: call L11$pb
+; DARWIN-32-PIC-NEXT: L11$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ldst-"L11$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-"L11$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal _ldst-L11$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L11$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _foo07:
@@ -801,11 +801,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _foo08:
-; DARWIN-32-PIC: call "L12$pb"
-; DARWIN-32-PIC-NEXT: "L12$pb":
+; DARWIN-32-PIC: call L12$pb
+; DARWIN-32-PIC-NEXT: L12$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _lsrc-"L12$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl _lptr-"L12$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _lsrc-L12$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _lptr-L12$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -868,12 +868,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qux00:
-; DARWIN-32-PIC: call "L13$pb"
-; DARWIN-32-PIC-NEXT: "L13$pb":
+; DARWIN-32-PIC: call L13$pb
+; DARWIN-32-PIC-NEXT: L13$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L13$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L13$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L13$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L13$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -939,12 +939,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qxx00:
-; DARWIN-32-PIC: call "L14$pb"
-; DARWIN-32-PIC-NEXT: "L14$pb":
+; DARWIN-32-PIC: call L14$pb
+; DARWIN-32-PIC-NEXT: L14$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L14$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L14$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L14$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L14$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -1005,12 +1005,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qux01:
-; DARWIN-32-PIC: call "L15$pb"
-; DARWIN-32-PIC-NEXT: "L15$pb":
+; DARWIN-32-PIC: call L15$pb
+; DARWIN-32-PIC-NEXT: L15$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L15$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L15$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: addl $64, %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L15$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L15$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -1071,12 +1071,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qxx01:
-; DARWIN-32-PIC: call "L16$pb"
-; DARWIN-32-PIC-NEXT: "L16$pb":
+; DARWIN-32-PIC: call L16$pb
+; DARWIN-32-PIC-NEXT: L16$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L16$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L16$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: addl $64, %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L16$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L16$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -1150,12 +1150,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qux02:
-; DARWIN-32-PIC: call "L17$pb"
-; DARWIN-32-PIC-NEXT: "L17$pb":
+; DARWIN-32-PIC: call L17$pb
+; DARWIN-32-PIC-NEXT: L17$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L17$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L17$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L17$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L17$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -1233,12 +1233,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qxx02:
-; DARWIN-32-PIC: call "L18$pb"
-; DARWIN-32-PIC-NEXT: "L18$pb":
+; DARWIN-32-PIC: call L18$pb
+; DARWIN-32-PIC-NEXT: L18$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L18$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L18$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L18$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L18$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -1306,11 +1306,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qux03:
-; DARWIN-32-PIC: call "L19$pb"
-; DARWIN-32-PIC-NEXT: "L19$pb":
+; DARWIN-32-PIC: call L19$pb
+; DARWIN-32-PIC-NEXT: L19$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _dsrc+64-"L19$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _ddst+64-"L19$pb"(%eax)
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L19$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L19$pb)+64(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _qux03:
@@ -1361,11 +1361,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qux04:
-; DARWIN-32-PIC: call "L20$pb"
-; DARWIN-32-PIC-NEXT: "L20$pb":
+; DARWIN-32-PIC: call L20$pb
+; DARWIN-32-PIC-NEXT: L20$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ddst+64-"L20$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-"L20$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal (_ddst-L20$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L20$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _qux04:
@@ -1430,11 +1430,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qux05:
-; DARWIN-32-PIC: call "L21$pb"
-; DARWIN-32-PIC-NEXT: "L21$pb":
+; DARWIN-32-PIC: call L21$pb
+; DARWIN-32-PIC-NEXT: L21$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _dsrc+64-"L21$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl _dptr-"L21$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L21$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _dptr-L21$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -1493,11 +1493,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qux06:
-; DARWIN-32-PIC: call "L22$pb"
-; DARWIN-32-PIC-NEXT: "L22$pb":
+; DARWIN-32-PIC: call L22$pb
+; DARWIN-32-PIC-NEXT: L22$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _lsrc+64-"L22$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _ldst+64-"L22$pb"(%eax)
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L22$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L22$pb)+64(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _qux06:
@@ -1546,11 +1546,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qux07:
-; DARWIN-32-PIC: call "L23$pb"
-; DARWIN-32-PIC-NEXT: "L23$pb":
+; DARWIN-32-PIC: call L23$pb
+; DARWIN-32-PIC-NEXT: L23$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ldst+64-"L23$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-"L23$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal (_ldst-L23$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L23$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _qux07:
@@ -1613,11 +1613,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _qux08:
-; DARWIN-32-PIC: call "L24$pb"
-; DARWIN-32-PIC-NEXT: "L24$pb":
+; DARWIN-32-PIC: call L24$pb
+; DARWIN-32-PIC-NEXT: L24$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _lsrc+64-"L24$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl _lptr-"L24$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L24$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _lptr-L24$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -1686,13 +1686,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ind00:
-; DARWIN-32-PIC: call "L25$pb"
-; DARWIN-32-PIC-NEXT: "L25$pb":
+; DARWIN-32-PIC: call L25$pb
+; DARWIN-32-PIC-NEXT: L25$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L25$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L25$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L25$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L25$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -1764,13 +1764,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ixd00:
-; DARWIN-32-PIC: call "L26$pb"
-; DARWIN-32-PIC-NEXT: "L26$pb":
+; DARWIN-32-PIC: call L26$pb
+; DARWIN-32-PIC-NEXT: L26$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L26$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L26$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L26$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L26$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -1840,13 +1840,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ind01:
-; DARWIN-32-PIC: call "L27$pb"
-; DARWIN-32-PIC-NEXT: "L27$pb":
+; DARWIN-32-PIC: call L27$pb
+; DARWIN-32-PIC-NEXT: L27$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
; DARWIN-32-PIC-NEXT: shll $2, %ecx
-; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-"L27$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L27$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L27$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L27$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -1916,13 +1916,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ixd01:
-; DARWIN-32-PIC: call "L28$pb"
-; DARWIN-32-PIC-NEXT: "L28$pb":
+; DARWIN-32-PIC: call L28$pb
+; DARWIN-32-PIC-NEXT: L28$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
; DARWIN-32-PIC-NEXT: shll $2, %ecx
-; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-"L28$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L28$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L28$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L28$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -2001,13 +2001,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ind02:
-; DARWIN-32-PIC: call "L29$pb"
-; DARWIN-32-PIC-NEXT: "L29$pb":
+; DARWIN-32-PIC: call L29$pb
+; DARWIN-32-PIC-NEXT: L29$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L29$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L29$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L29$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L29$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -2090,13 +2090,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ixd02:
-; DARWIN-32-PIC: call "L30$pb"
-; DARWIN-32-PIC-NEXT: "L30$pb":
+; DARWIN-32-PIC: call L30$pb
+; DARWIN-32-PIC-NEXT: L30$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L30$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L30$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L30$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L30$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -2170,12 +2170,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ind03:
-; DARWIN-32-PIC: call "L31$pb"
-; DARWIN-32-PIC-NEXT: "L31$pb":
+; DARWIN-32-PIC: call L31$pb
+; DARWIN-32-PIC-NEXT: L31$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _dsrc-"L31$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl %edx, _ddst-"L31$pb"(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: movl _dsrc-L31$pb(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, _ddst-L31$pb(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _ind03:
@@ -2242,12 +2242,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ind04:
-; DARWIN-32-PIC: call "L32$pb"
-; DARWIN-32-PIC-NEXT: "L32$pb":
+; DARWIN-32-PIC: call L32$pb
+; DARWIN-32-PIC-NEXT: L32$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _ddst-"L32$pb"(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-"L32$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal _ddst-L32$pb(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L32$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _ind04:
@@ -2320,12 +2320,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ind05:
-; DARWIN-32-PIC: call "L33$pb"
-; DARWIN-32-PIC-NEXT: "L33$pb":
+; DARWIN-32-PIC: call L33$pb
+; DARWIN-32-PIC-NEXT: L33$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _dsrc-"L33$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl _dptr-"L33$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _dsrc-L33$pb(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _dptr-L33$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -2395,12 +2395,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ind06:
-; DARWIN-32-PIC: call "L34$pb"
-; DARWIN-32-PIC-NEXT: "L34$pb":
+; DARWIN-32-PIC: call L34$pb
+; DARWIN-32-PIC-NEXT: L34$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _lsrc-"L34$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl %edx, _ldst-"L34$pb"(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: movl _lsrc-L34$pb(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, _ldst-L34$pb(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _ind06:
@@ -2466,12 +2466,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ind07:
-; DARWIN-32-PIC: call "L35$pb"
-; DARWIN-32-PIC-NEXT: "L35$pb":
+; DARWIN-32-PIC: call L35$pb
+; DARWIN-32-PIC-NEXT: L35$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _ldst-"L35$pb"(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-"L35$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal _ldst-L35$pb(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L35$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _ind07:
@@ -2543,12 +2543,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _ind08:
-; DARWIN-32-PIC: call "L36$pb"
-; DARWIN-32-PIC-NEXT: "L36$pb":
+; DARWIN-32-PIC: call L36$pb
+; DARWIN-32-PIC-NEXT: L36$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _lsrc-"L36$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl _lptr-"L36$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _lsrc-L36$pb(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _lptr-L36$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -2621,13 +2621,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _off00:
-; DARWIN-32-PIC: call "L37$pb"
-; DARWIN-32-PIC-NEXT: "L37$pb":
+; DARWIN-32-PIC: call L37$pb
+; DARWIN-32-PIC-NEXT: L37$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L37$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L37$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L37$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L37$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -2700,13 +2700,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _oxf00:
-; DARWIN-32-PIC: call "L38$pb"
-; DARWIN-32-PIC-NEXT: "L38$pb":
+; DARWIN-32-PIC: call L38$pb
+; DARWIN-32-PIC-NEXT: L38$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L38$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L38$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L38$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L38$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -2777,13 +2777,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _off01:
-; DARWIN-32-PIC: call "L39$pb"
-; DARWIN-32-PIC-NEXT: "L39$pb":
+; DARWIN-32-PIC: call L39$pb
+; DARWIN-32-PIC-NEXT: L39$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L39$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L39$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L39$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L39$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -2854,13 +2854,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _oxf01:
-; DARWIN-32-PIC: call "L40$pb"
-; DARWIN-32-PIC-NEXT: "L40$pb":
+; DARWIN-32-PIC: call L40$pb
+; DARWIN-32-PIC-NEXT: L40$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L40$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L40$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L40$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L40$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -2940,13 +2940,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _off02:
-; DARWIN-32-PIC: call "L41$pb"
-; DARWIN-32-PIC-NEXT: "L41$pb":
+; DARWIN-32-PIC: call L41$pb
+; DARWIN-32-PIC-NEXT: L41$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L41$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L41$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L41$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L41$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -3030,13 +3030,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _oxf02:
-; DARWIN-32-PIC: call "L42$pb"
-; DARWIN-32-PIC-NEXT: "L42$pb":
+; DARWIN-32-PIC: call L42$pb
+; DARWIN-32-PIC-NEXT: L42$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L42$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L42$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L42$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L42$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -3111,12 +3111,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _off03:
-; DARWIN-32-PIC: call "L43$pb"
-; DARWIN-32-PIC-NEXT: "L43$pb":
+; DARWIN-32-PIC: call L43$pb
+; DARWIN-32-PIC-NEXT: L43$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _dsrc+64-"L43$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl %edx, _ddst+64-"L43$pb"(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L43$pb)+64(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L43$pb)+64(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _off03:
@@ -3184,12 +3184,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _off04:
-; DARWIN-32-PIC: call "L44$pb"
-; DARWIN-32-PIC-NEXT: "L44$pb":
+; DARWIN-32-PIC: call L44$pb
+; DARWIN-32-PIC-NEXT: L44$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _ddst+64-"L44$pb"(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-"L44$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal (_ddst-L44$pb)+64(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L44$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _off04:
@@ -3263,12 +3263,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _off05:
-; DARWIN-32-PIC: call "L45$pb"
-; DARWIN-32-PIC-NEXT: "L45$pb":
+; DARWIN-32-PIC: call L45$pb
+; DARWIN-32-PIC-NEXT: L45$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _dsrc+64-"L45$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl _dptr-"L45$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L45$pb)+64(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _dptr-L45$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -3339,12 +3339,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _off06:
-; DARWIN-32-PIC: call "L46$pb"
-; DARWIN-32-PIC-NEXT: "L46$pb":
+; DARWIN-32-PIC: call L46$pb
+; DARWIN-32-PIC-NEXT: L46$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _lsrc+64-"L46$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl %edx, _ldst+64-"L46$pb"(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L46$pb)+64(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L46$pb)+64(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _off06:
@@ -3411,12 +3411,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _off07:
-; DARWIN-32-PIC: call "L47$pb"
-; DARWIN-32-PIC-NEXT: "L47$pb":
+; DARWIN-32-PIC: call L47$pb
+; DARWIN-32-PIC-NEXT: L47$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _ldst+64-"L47$pb"(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-"L47$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal (_ldst-L47$pb)+64(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L47$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _off07:
@@ -3489,12 +3489,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _off08:
-; DARWIN-32-PIC: call "L48$pb"
-; DARWIN-32-PIC-NEXT: "L48$pb":
+; DARWIN-32-PIC: call L48$pb
+; DARWIN-32-PIC-NEXT: L48$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _lsrc+64-"L48$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl _lptr-"L48$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L48$pb)+64(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _lptr-L48$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -3560,12 +3560,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _moo00:
-; DARWIN-32-PIC: call "L49$pb"
-; DARWIN-32-PIC-NEXT: "L49$pb":
+; DARWIN-32-PIC: call L49$pb
+; DARWIN-32-PIC-NEXT: L49$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L49$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L49$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L49$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L49$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -3626,12 +3626,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _moo01:
-; DARWIN-32-PIC: call "L50$pb"
-; DARWIN-32-PIC-NEXT: "L50$pb":
+; DARWIN-32-PIC: call L50$pb
+; DARWIN-32-PIC-NEXT: L50$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl $262144, %ecx
-; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-"L50$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L50$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L50$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L50$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -3705,12 +3705,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _moo02:
-; DARWIN-32-PIC: call "L51$pb"
-; DARWIN-32-PIC-NEXT: "L51$pb":
+; DARWIN-32-PIC: call L51$pb
+; DARWIN-32-PIC-NEXT: L51$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L51$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L51$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L51$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L51$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -3778,11 +3778,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _moo03:
-; DARWIN-32-PIC: call "L52$pb"
-; DARWIN-32-PIC-NEXT: "L52$pb":
+; DARWIN-32-PIC: call L52$pb
+; DARWIN-32-PIC-NEXT: L52$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _dsrc+262144-"L52$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _ddst+262144-"L52$pb"(%eax)
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L52$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L52$pb)+262144(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _moo03:
@@ -3833,11 +3833,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _moo04:
-; DARWIN-32-PIC: call "L53$pb"
-; DARWIN-32-PIC-NEXT: "L53$pb":
+; DARWIN-32-PIC: call L53$pb
+; DARWIN-32-PIC-NEXT: L53$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ddst+262144-"L53$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-"L53$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal (_ddst-L53$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L53$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _moo04:
@@ -3902,11 +3902,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _moo05:
-; DARWIN-32-PIC: call "L54$pb"
-; DARWIN-32-PIC-NEXT: "L54$pb":
+; DARWIN-32-PIC: call L54$pb
+; DARWIN-32-PIC-NEXT: L54$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _dsrc+262144-"L54$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl _dptr-"L54$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L54$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _dptr-L54$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -3965,11 +3965,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _moo06:
-; DARWIN-32-PIC: call "L55$pb"
-; DARWIN-32-PIC-NEXT: "L55$pb":
+; DARWIN-32-PIC: call L55$pb
+; DARWIN-32-PIC-NEXT: L55$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _lsrc+262144-"L55$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _ldst+262144-"L55$pb"(%eax)
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L55$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L55$pb)+262144(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _moo06:
@@ -4018,11 +4018,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _moo07:
-; DARWIN-32-PIC: call "L56$pb"
-; DARWIN-32-PIC-NEXT: "L56$pb":
+; DARWIN-32-PIC: call L56$pb
+; DARWIN-32-PIC-NEXT: L56$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ldst+262144-"L56$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-"L56$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal (_ldst-L56$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L56$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _moo07:
@@ -4085,11 +4085,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _moo08:
-; DARWIN-32-PIC: call "L57$pb"
-; DARWIN-32-PIC-NEXT: "L57$pb":
+; DARWIN-32-PIC: call L57$pb
+; DARWIN-32-PIC-NEXT: L57$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _lsrc+262144-"L57$pb"(%eax), %ecx
-; DARWIN-32-PIC-NEXT: movl _lptr-"L57$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L57$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _lptr-L57$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -4159,13 +4159,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _big00:
-; DARWIN-32-PIC: call "L58$pb"
-; DARWIN-32-PIC-NEXT: "L58$pb":
+; DARWIN-32-PIC: call L58$pb
+; DARWIN-32-PIC-NEXT: L58$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L58$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L58$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L58$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L58$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -4236,13 +4236,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _big01:
-; DARWIN-32-PIC: call "L59$pb"
-; DARWIN-32-PIC-NEXT: "L59$pb":
+; DARWIN-32-PIC: call L59$pb
+; DARWIN-32-PIC-NEXT: L59$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L59$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L59$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: leal 262144(%edx,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L59$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L59$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
; DARWIN-32-PIC-NEXT: ret
@@ -4322,13 +4322,13 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _big02:
-; DARWIN-32-PIC: call "L60$pb"
-; DARWIN-32-PIC-NEXT: "L60$pb":
+; DARWIN-32-PIC: call L60$pb
+; DARWIN-32-PIC-NEXT: L60$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L60$pb"(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L60$pb(%eax), %edx
; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L60$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L60$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -4403,12 +4403,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _big03:
-; DARWIN-32-PIC: call "L61$pb"
-; DARWIN-32-PIC-NEXT: "L61$pb":
+; DARWIN-32-PIC: call L61$pb
+; DARWIN-32-PIC-NEXT: L61$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _dsrc+262144-"L61$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl %edx, _ddst+262144-"L61$pb"(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L61$pb)+262144(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L61$pb)+262144(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _big03:
@@ -4476,12 +4476,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _big04:
-; DARWIN-32-PIC: call "L62$pb"
-; DARWIN-32-PIC-NEXT: "L62$pb":
+; DARWIN-32-PIC: call L62$pb
+; DARWIN-32-PIC-NEXT: L62$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _ddst+262144-"L62$pb"(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-"L62$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal (_ddst-L62$pb)+262144(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L62$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _big04:
@@ -4555,12 +4555,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _big05:
-; DARWIN-32-PIC: call "L63$pb"
-; DARWIN-32-PIC-NEXT: "L63$pb":
+; DARWIN-32-PIC: call L63$pb
+; DARWIN-32-PIC-NEXT: L63$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _dsrc+262144-"L63$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl _dptr-"L63$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L63$pb)+262144(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _dptr-L63$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -4631,12 +4631,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _big06:
-; DARWIN-32-PIC: call "L64$pb"
-; DARWIN-32-PIC-NEXT: "L64$pb":
+; DARWIN-32-PIC: call L64$pb
+; DARWIN-32-PIC-NEXT: L64$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _lsrc+262144-"L64$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl %edx, _ldst+262144-"L64$pb"(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L64$pb)+262144(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L64$pb)+262144(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _big06:
@@ -4703,12 +4703,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _big07:
-; DARWIN-32-PIC: call "L65$pb"
-; DARWIN-32-PIC-NEXT: "L65$pb":
+; DARWIN-32-PIC: call L65$pb
+; DARWIN-32-PIC-NEXT: L65$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _ldst+262144-"L65$pb"(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-"L65$pb"(%eax)
+; DARWIN-32-PIC-NEXT: leal (_ldst-L65$pb)+262144(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L65$pb(%eax)
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _big07:
@@ -4781,12 +4781,12 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _big08:
-; DARWIN-32-PIC: call "L66$pb"
-; DARWIN-32-PIC-NEXT: "L66$pb":
+; DARWIN-32-PIC: call L66$pb
+; DARWIN-32-PIC-NEXT: L66$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _lsrc+262144-"L66$pb"(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: movl _lptr-"L66$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L66$pb)+262144(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _lptr-L66$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4)
; DARWIN-32-PIC-NEXT: ret
@@ -4840,10 +4840,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bar00:
-; DARWIN-32-PIC: call "L67$pb"
-; DARWIN-32-PIC-NEXT: "L67$pb":
+; DARWIN-32-PIC: call L67$pb
+; DARWIN-32-PIC-NEXT: L67$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L67$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L67$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bar00:
@@ -4887,10 +4887,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bxr00:
-; DARWIN-32-PIC: call "L68$pb"
-; DARWIN-32-PIC-NEXT: "L68$pb":
+; DARWIN-32-PIC: call L68$pb
+; DARWIN-32-PIC-NEXT: L68$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L68$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L68$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bxr00:
@@ -4934,10 +4934,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bar01:
-; DARWIN-32-PIC: call "L69$pb"
-; DARWIN-32-PIC-NEXT: "L69$pb":
+; DARWIN-32-PIC: call L69$pb
+; DARWIN-32-PIC-NEXT: L69$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L69$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L69$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bar01:
@@ -4981,10 +4981,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bxr01:
-; DARWIN-32-PIC: call "L70$pb"
-; DARWIN-32-PIC-NEXT: "L70$pb":
+; DARWIN-32-PIC: call L70$pb
+; DARWIN-32-PIC-NEXT: L70$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L70$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L70$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bxr01:
@@ -5028,10 +5028,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bar02:
-; DARWIN-32-PIC: call "L71$pb"
-; DARWIN-32-PIC-NEXT: "L71$pb":
+; DARWIN-32-PIC: call L71$pb
+; DARWIN-32-PIC-NEXT: L71$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L71$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L71$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bar02:
@@ -5075,10 +5075,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bar03:
-; DARWIN-32-PIC: call "L72$pb"
-; DARWIN-32-PIC-NEXT: "L72$pb":
+; DARWIN-32-PIC: call L72$pb
+; DARWIN-32-PIC-NEXT: L72$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _dsrc-"L72$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _dsrc-L72$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bar03:
@@ -5122,10 +5122,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bar04:
-; DARWIN-32-PIC: call "L73$pb"
-; DARWIN-32-PIC-NEXT: "L73$pb":
+; DARWIN-32-PIC: call L73$pb
+; DARWIN-32-PIC-NEXT: L73$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ddst-"L73$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _ddst-L73$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bar04:
@@ -5169,10 +5169,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bar05:
-; DARWIN-32-PIC: call "L74$pb"
-; DARWIN-32-PIC-NEXT: "L74$pb":
+; DARWIN-32-PIC: call L74$pb
+; DARWIN-32-PIC-NEXT: L74$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _dptr-"L74$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _dptr-L74$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bar05:
@@ -5216,10 +5216,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bar06:
-; DARWIN-32-PIC: call "L75$pb"
-; DARWIN-32-PIC-NEXT: "L75$pb":
+; DARWIN-32-PIC: call L75$pb
+; DARWIN-32-PIC-NEXT: L75$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _lsrc-"L75$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _lsrc-L75$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bar06:
@@ -5263,10 +5263,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bar07:
-; DARWIN-32-PIC: call "L76$pb"
-; DARWIN-32-PIC-NEXT: "L76$pb":
+; DARWIN-32-PIC: call L76$pb
+; DARWIN-32-PIC-NEXT: L76$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ldst-"L76$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _ldst-L76$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bar07:
@@ -5310,10 +5310,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bar08:
-; DARWIN-32-PIC: call "L77$pb"
-; DARWIN-32-PIC-NEXT: "L77$pb":
+; DARWIN-32-PIC: call L77$pb
+; DARWIN-32-PIC-NEXT: L77$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _lptr-"L77$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _lptr-L77$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bar08:
@@ -5357,10 +5357,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _har00:
-; DARWIN-32-PIC: call "L78$pb"
-; DARWIN-32-PIC-NEXT: "L78$pb":
+; DARWIN-32-PIC: call L78$pb
+; DARWIN-32-PIC-NEXT: L78$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L78$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L78$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _har00:
@@ -5404,10 +5404,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _hxr00:
-; DARWIN-32-PIC: call "L79$pb"
-; DARWIN-32-PIC-NEXT: "L79$pb":
+; DARWIN-32-PIC: call L79$pb
+; DARWIN-32-PIC-NEXT: L79$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L79$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L79$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _hxr00:
@@ -5451,10 +5451,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _har01:
-; DARWIN-32-PIC: call "L80$pb"
-; DARWIN-32-PIC-NEXT: "L80$pb":
+; DARWIN-32-PIC: call L80$pb
+; DARWIN-32-PIC-NEXT: L80$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L80$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L80$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _har01:
@@ -5498,10 +5498,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _hxr01:
-; DARWIN-32-PIC: call "L81$pb"
-; DARWIN-32-PIC-NEXT: "L81$pb":
+; DARWIN-32-PIC: call L81$pb
+; DARWIN-32-PIC-NEXT: L81$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L81$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L81$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _hxr01:
@@ -5549,10 +5549,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _har02:
-; DARWIN-32-PIC: call "L82$pb"
-; DARWIN-32-PIC-NEXT: "L82$pb":
+; DARWIN-32-PIC: call L82$pb
+; DARWIN-32-PIC-NEXT: L82$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L82$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L82$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -5600,10 +5600,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _har03:
-; DARWIN-32-PIC: call "L83$pb"
-; DARWIN-32-PIC-NEXT: "L83$pb":
+; DARWIN-32-PIC: call L83$pb
+; DARWIN-32-PIC-NEXT: L83$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _dsrc-"L83$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _dsrc-L83$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _har03:
@@ -5647,10 +5647,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _har04:
-; DARWIN-32-PIC: call "L84$pb"
-; DARWIN-32-PIC-NEXT: "L84$pb":
+; DARWIN-32-PIC: call L84$pb
+; DARWIN-32-PIC-NEXT: L84$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ddst-"L84$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _ddst-L84$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _har04:
@@ -5697,10 +5697,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _har05:
-; DARWIN-32-PIC: call "L85$pb"
-; DARWIN-32-PIC-NEXT: "L85$pb":
+; DARWIN-32-PIC: call L85$pb
+; DARWIN-32-PIC-NEXT: L85$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _dptr-"L85$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _dptr-L85$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _har05:
@@ -5744,10 +5744,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _har06:
-; DARWIN-32-PIC: call "L86$pb"
-; DARWIN-32-PIC-NEXT: "L86$pb":
+; DARWIN-32-PIC: call L86$pb
+; DARWIN-32-PIC-NEXT: L86$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _lsrc-"L86$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _lsrc-L86$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _har06:
@@ -5791,10 +5791,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _har07:
-; DARWIN-32-PIC: call "L87$pb"
-; DARWIN-32-PIC-NEXT: "L87$pb":
+; DARWIN-32-PIC: call L87$pb
+; DARWIN-32-PIC-NEXT: L87$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ldst-"L87$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _ldst-L87$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _har07:
@@ -5840,10 +5840,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _har08:
-; DARWIN-32-PIC: call "L88$pb"
-; DARWIN-32-PIC-NEXT: "L88$pb":
+; DARWIN-32-PIC: call L88$pb
+; DARWIN-32-PIC-NEXT: L88$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _lptr-"L88$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _lptr-L88$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _har08:
@@ -5889,10 +5889,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bat00:
-; DARWIN-32-PIC: call "L89$pb"
-; DARWIN-32-PIC-NEXT: "L89$pb":
+; DARWIN-32-PIC: call L89$pb
+; DARWIN-32-PIC-NEXT: L89$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L89$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L89$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: addl $64, %eax
; DARWIN-32-PIC-NEXT: ret
@@ -5942,10 +5942,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bxt00:
-; DARWIN-32-PIC: call "L90$pb"
-; DARWIN-32-PIC-NEXT: "L90$pb":
+; DARWIN-32-PIC: call L90$pb
+; DARWIN-32-PIC-NEXT: L90$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L90$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L90$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: addl $64, %eax
; DARWIN-32-PIC-NEXT: ret
@@ -5995,10 +5995,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bat01:
-; DARWIN-32-PIC: call "L91$pb"
-; DARWIN-32-PIC-NEXT: "L91$pb":
+; DARWIN-32-PIC: call L91$pb
+; DARWIN-32-PIC-NEXT: L91$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L91$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L91$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: addl $64, %eax
; DARWIN-32-PIC-NEXT: ret
@@ -6048,10 +6048,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bxt01:
-; DARWIN-32-PIC: call "L92$pb"
-; DARWIN-32-PIC-NEXT: "L92$pb":
+; DARWIN-32-PIC: call L92$pb
+; DARWIN-32-PIC-NEXT: L92$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L92$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L92$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: addl $64, %eax
; DARWIN-32-PIC-NEXT: ret
@@ -6110,10 +6110,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bat02:
-; DARWIN-32-PIC: call "L93$pb"
-; DARWIN-32-PIC-NEXT: "L93$pb":
+; DARWIN-32-PIC: call L93$pb
+; DARWIN-32-PIC-NEXT: L93$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L93$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L93$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: addl $64, %eax
; DARWIN-32-PIC-NEXT: ret
@@ -6166,10 +6166,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bat03:
-; DARWIN-32-PIC: call "L94$pb"
-; DARWIN-32-PIC-NEXT: "L94$pb":
+; DARWIN-32-PIC: call L94$pb
+; DARWIN-32-PIC-NEXT: L94$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _dsrc+64-"L94$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal (_dsrc-L94$pb)+64(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bat03:
@@ -6214,10 +6214,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bat04:
-; DARWIN-32-PIC: call "L95$pb"
-; DARWIN-32-PIC-NEXT: "L95$pb":
+; DARWIN-32-PIC: call L95$pb
+; DARWIN-32-PIC-NEXT: L95$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ddst+64-"L95$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal (_ddst-L95$pb)+64(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bat04:
@@ -6271,10 +6271,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bat05:
-; DARWIN-32-PIC: call "L96$pb"
-; DARWIN-32-PIC-NEXT: "L96$pb":
+; DARWIN-32-PIC: call L96$pb
+; DARWIN-32-PIC-NEXT: L96$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _dptr-"L96$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _dptr-L96$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: addl $64, %eax
; DARWIN-32-PIC-NEXT: ret
@@ -6322,10 +6322,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bat06:
-; DARWIN-32-PIC: call "L97$pb"
-; DARWIN-32-PIC-NEXT: "L97$pb":
+; DARWIN-32-PIC: call L97$pb
+; DARWIN-32-PIC-NEXT: L97$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _lsrc+64-"L97$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal (_lsrc-L97$pb)+64(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bat06:
@@ -6369,10 +6369,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bat07:
-; DARWIN-32-PIC: call "L98$pb"
-; DARWIN-32-PIC-NEXT: "L98$pb":
+; DARWIN-32-PIC: call L98$pb
+; DARWIN-32-PIC-NEXT: L98$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ldst+64-"L98$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal (_ldst-L98$pb)+64(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bat07:
@@ -6425,10 +6425,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bat08:
-; DARWIN-32-PIC: call "L99$pb"
-; DARWIN-32-PIC-NEXT: "L99$pb":
+; DARWIN-32-PIC: call L99$pb
+; DARWIN-32-PIC-NEXT: L99$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl _lptr-"L99$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _lptr-L99$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: addl $64, %eax
; DARWIN-32-PIC-NEXT: ret
@@ -6478,11 +6478,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bam00:
-; DARWIN-32-PIC: call "L100$pb"
-; DARWIN-32-PIC-NEXT: "L100$pb":
+; DARWIN-32-PIC: call L100$pb
+; DARWIN-32-PIC-NEXT: L100$pb:
; DARWIN-32-PIC-NEXT: popl %ecx
; DARWIN-32-PIC-NEXT: movl $262144, %eax
-; DARWIN-32-PIC-NEXT: addl L_src$non_lazy_ptr-"L100$pb"(%ecx), %eax
+; DARWIN-32-PIC-NEXT: addl L_src$non_lazy_ptr-L100$pb(%ecx), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bam00:
@@ -6531,11 +6531,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bam01:
-; DARWIN-32-PIC: call "L101$pb"
-; DARWIN-32-PIC-NEXT: "L101$pb":
+; DARWIN-32-PIC: call L101$pb
+; DARWIN-32-PIC-NEXT: L101$pb:
; DARWIN-32-PIC-NEXT: popl %ecx
; DARWIN-32-PIC-NEXT: movl $262144, %eax
-; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-"L101$pb"(%ecx), %eax
+; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L101$pb(%ecx), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bam01:
@@ -6584,11 +6584,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bxm01:
-; DARWIN-32-PIC: call "L102$pb"
-; DARWIN-32-PIC-NEXT: "L102$pb":
+; DARWIN-32-PIC: call L102$pb
+; DARWIN-32-PIC-NEXT: L102$pb:
; DARWIN-32-PIC-NEXT: popl %ecx
; DARWIN-32-PIC-NEXT: movl $262144, %eax
-; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-"L102$pb"(%ecx), %eax
+; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L102$pb(%ecx), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bxm01:
@@ -6646,10 +6646,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bam02:
-; DARWIN-32-PIC: call "L103$pb"
-; DARWIN-32-PIC-NEXT: "L103$pb":
+; DARWIN-32-PIC: call L103$pb
+; DARWIN-32-PIC-NEXT: L103$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L103$pb"(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L103$pb(%eax), %ecx
; DARWIN-32-PIC-NEXT: movl $262144, %eax
; DARWIN-32-PIC-NEXT: addl (%ecx), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -6702,10 +6702,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bam03:
-; DARWIN-32-PIC: call "L104$pb"
-; DARWIN-32-PIC-NEXT: "L104$pb":
+; DARWIN-32-PIC: call L104$pb
+; DARWIN-32-PIC-NEXT: L104$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _dsrc+262144-"L104$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal (_dsrc-L104$pb)+262144(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bam03:
@@ -6750,10 +6750,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bam04:
-; DARWIN-32-PIC: call "L105$pb"
-; DARWIN-32-PIC-NEXT: "L105$pb":
+; DARWIN-32-PIC: call L105$pb
+; DARWIN-32-PIC-NEXT: L105$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ddst+262144-"L105$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal (_ddst-L105$pb)+262144(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bam04:
@@ -6807,11 +6807,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bam05:
-; DARWIN-32-PIC: call "L106$pb"
-; DARWIN-32-PIC-NEXT: "L106$pb":
+; DARWIN-32-PIC: call L106$pb
+; DARWIN-32-PIC-NEXT: L106$pb:
; DARWIN-32-PIC-NEXT: popl %ecx
; DARWIN-32-PIC-NEXT: movl $262144, %eax
-; DARWIN-32-PIC-NEXT: addl _dptr-"L106$pb"(%ecx), %eax
+; DARWIN-32-PIC-NEXT: addl _dptr-L106$pb(%ecx), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bam05:
@@ -6858,10 +6858,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bam06:
-; DARWIN-32-PIC: call "L107$pb"
-; DARWIN-32-PIC-NEXT: "L107$pb":
+; DARWIN-32-PIC: call L107$pb
+; DARWIN-32-PIC-NEXT: L107$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _lsrc+262144-"L107$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal (_lsrc-L107$pb)+262144(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bam06:
@@ -6905,10 +6905,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bam07:
-; DARWIN-32-PIC: call "L108$pb"
-; DARWIN-32-PIC-NEXT: "L108$pb":
+; DARWIN-32-PIC: call L108$pb
+; DARWIN-32-PIC-NEXT: L108$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _ldst+262144-"L108$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal (_ldst-L108$pb)+262144(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bam07:
@@ -6961,11 +6961,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _bam08:
-; DARWIN-32-PIC: call "L109$pb"
-; DARWIN-32-PIC-NEXT: "L109$pb":
+; DARWIN-32-PIC: call L109$pb
+; DARWIN-32-PIC-NEXT: L109$pb:
; DARWIN-32-PIC-NEXT: popl %ecx
; DARWIN-32-PIC-NEXT: movl $262144, %eax
-; DARWIN-32-PIC-NEXT: addl _lptr-"L109$pb"(%ecx), %eax
+; DARWIN-32-PIC-NEXT: addl _lptr-L109$pb(%ecx), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _bam08:
@@ -7021,11 +7021,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cat00:
-; DARWIN-32-PIC: call "L110$pb"
-; DARWIN-32-PIC-NEXT: "L110$pb":
+; DARWIN-32-PIC: call L110$pb
+; DARWIN-32-PIC-NEXT: L110$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L110$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L110$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -7082,11 +7082,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cxt00:
-; DARWIN-32-PIC: call "L111$pb"
-; DARWIN-32-PIC-NEXT: "L111$pb":
+; DARWIN-32-PIC: call L111$pb
+; DARWIN-32-PIC-NEXT: L111$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L111$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L111$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -7143,11 +7143,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cat01:
-; DARWIN-32-PIC: call "L112$pb"
-; DARWIN-32-PIC-NEXT: "L112$pb":
+; DARWIN-32-PIC: call L112$pb
+; DARWIN-32-PIC-NEXT: L112$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L112$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L112$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -7204,11 +7204,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cxt01:
-; DARWIN-32-PIC: call "L113$pb"
-; DARWIN-32-PIC-NEXT: "L113$pb":
+; DARWIN-32-PIC: call L113$pb
+; DARWIN-32-PIC-NEXT: L113$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L113$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L113$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -7272,10 +7272,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cat02:
-; DARWIN-32-PIC: call "L114$pb"
-; DARWIN-32-PIC-NEXT: "L114$pb":
+; DARWIN-32-PIC: call L114$pb
+; DARWIN-32-PIC-NEXT: L114$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L114$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L114$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
@@ -7336,11 +7336,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cat03:
-; DARWIN-32-PIC: call "L115$pb"
-; DARWIN-32-PIC-NEXT: "L115$pb":
+; DARWIN-32-PIC: call L115$pb
+; DARWIN-32-PIC-NEXT: L115$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _dsrc+64-"L115$pb"(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: leal (_dsrc-L115$pb)+64(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _cat03:
@@ -7395,11 +7395,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cat04:
-; DARWIN-32-PIC: call "L116$pb"
-; DARWIN-32-PIC-NEXT: "L116$pb":
+; DARWIN-32-PIC: call L116$pb
+; DARWIN-32-PIC-NEXT: L116$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _ddst+64-"L116$pb"(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: leal (_ddst-L116$pb)+64(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _cat04:
@@ -7461,11 +7461,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cat05:
-; DARWIN-32-PIC: call "L117$pb"
-; DARWIN-32-PIC-NEXT: "L117$pb":
+; DARWIN-32-PIC: call L117$pb
+; DARWIN-32-PIC-NEXT: L117$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _dptr-"L117$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _dptr-L117$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -7521,11 +7521,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cat06:
-; DARWIN-32-PIC: call "L118$pb"
-; DARWIN-32-PIC-NEXT: "L118$pb":
+; DARWIN-32-PIC: call L118$pb
+; DARWIN-32-PIC-NEXT: L118$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _lsrc+64-"L118$pb"(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: leal (_lsrc-L118$pb)+64(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _cat06:
@@ -7580,11 +7580,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cat07:
-; DARWIN-32-PIC: call "L119$pb"
-; DARWIN-32-PIC-NEXT: "L119$pb":
+; DARWIN-32-PIC: call L119$pb
+; DARWIN-32-PIC-NEXT: L119$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _ldst+64-"L119$pb"(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: leal (_ldst-L119$pb)+64(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _cat07:
@@ -7645,11 +7645,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cat08:
-; DARWIN-32-PIC: call "L120$pb"
-; DARWIN-32-PIC-NEXT: "L120$pb":
+; DARWIN-32-PIC: call L120$pb
+; DARWIN-32-PIC-NEXT: L120$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _lptr-"L120$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _lptr-L120$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -7706,11 +7706,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cam00:
-; DARWIN-32-PIC: call "L121$pb"
-; DARWIN-32-PIC-NEXT: "L121$pb":
+; DARWIN-32-PIC: call L121$pb
+; DARWIN-32-PIC-NEXT: L121$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-"L121$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L121$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -7767,11 +7767,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cxm00:
-; DARWIN-32-PIC: call "L122$pb"
-; DARWIN-32-PIC-NEXT: "L122$pb":
+; DARWIN-32-PIC: call L122$pb
+; DARWIN-32-PIC-NEXT: L122$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-"L122$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L122$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -7828,11 +7828,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cam01:
-; DARWIN-32-PIC: call "L123$pb"
-; DARWIN-32-PIC-NEXT: "L123$pb":
+; DARWIN-32-PIC: call L123$pb
+; DARWIN-32-PIC-NEXT: L123$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-"L123$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L123$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -7889,11 +7889,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cxm01:
-; DARWIN-32-PIC: call "L124$pb"
-; DARWIN-32-PIC-NEXT: "L124$pb":
+; DARWIN-32-PIC: call L124$pb
+; DARWIN-32-PIC-NEXT: L124$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-"L124$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L124$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -7957,10 +7957,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cam02:
-; DARWIN-32-PIC: call "L125$pb"
-; DARWIN-32-PIC-NEXT: "L125$pb":
+; DARWIN-32-PIC: call L125$pb
+; DARWIN-32-PIC-NEXT: L125$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-"L125$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L125$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: movl (%eax), %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
@@ -8021,11 +8021,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cam03:
-; DARWIN-32-PIC: call "L126$pb"
-; DARWIN-32-PIC-NEXT: "L126$pb":
+; DARWIN-32-PIC: call L126$pb
+; DARWIN-32-PIC-NEXT: L126$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _dsrc+262144-"L126$pb"(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: leal (_dsrc-L126$pb)+262144(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _cam03:
@@ -8080,11 +8080,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cam04:
-; DARWIN-32-PIC: call "L127$pb"
-; DARWIN-32-PIC-NEXT: "L127$pb":
+; DARWIN-32-PIC: call L127$pb
+; DARWIN-32-PIC-NEXT: L127$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _ddst+262144-"L127$pb"(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: leal (_ddst-L127$pb)+262144(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _cam04:
@@ -8146,11 +8146,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cam05:
-; DARWIN-32-PIC: call "L128$pb"
-; DARWIN-32-PIC-NEXT: "L128$pb":
+; DARWIN-32-PIC: call L128$pb
+; DARWIN-32-PIC-NEXT: L128$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _dptr-"L128$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _dptr-L128$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -8206,11 +8206,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cam06:
-; DARWIN-32-PIC: call "L129$pb"
-; DARWIN-32-PIC-NEXT: "L129$pb":
+; DARWIN-32-PIC: call L129$pb
+; DARWIN-32-PIC-NEXT: L129$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _lsrc+262144-"L129$pb"(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: leal (_lsrc-L129$pb)+262144(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _cam06:
@@ -8265,11 +8265,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cam07:
-; DARWIN-32-PIC: call "L130$pb"
-; DARWIN-32-PIC-NEXT: "L130$pb":
+; DARWIN-32-PIC: call L130$pb
+; DARWIN-32-PIC-NEXT: L130$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: leal _ldst+262144-"L130$pb"(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: leal (_ldst-L130$pb)+262144(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _cam07:
@@ -8330,11 +8330,11 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _cam08:
-; DARWIN-32-PIC: call "L131$pb"
-; DARWIN-32-PIC-NEXT: "L131$pb":
+; DARWIN-32-PIC: call L131$pb
+; DARWIN-32-PIC-NEXT: L131$pb:
; DARWIN-32-PIC-NEXT: popl %eax
; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: movl _lptr-"L131$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl _lptr-L131$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
; DARWIN-32-PIC-NEXT: ret
@@ -8644,10 +8644,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _address:
-; DARWIN-32-PIC: call "L134$pb"
-; DARWIN-32-PIC-NEXT: "L134$pb":
+; DARWIN-32-PIC: call L134$pb
+; DARWIN-32-PIC-NEXT: L134$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_callee$non_lazy_ptr-"L134$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl L_callee$non_lazy_ptr-L134$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _address:
@@ -8693,10 +8693,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _laddress:
-; DARWIN-32-PIC: call "L135$pb"
-; DARWIN-32-PIC-NEXT: "L135$pb":
+; DARWIN-32-PIC: call L135$pb
+; DARWIN-32-PIC-NEXT: L135$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _lcallee-"L135$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _lcallee-L135$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _laddress:
@@ -8740,10 +8740,10 @@ entry:
; DARWIN-32-DYNAMIC-NEXT: ret
; DARWIN-32-PIC: _daddress:
-; DARWIN-32-PIC: call "L136$pb"
-; DARWIN-32-PIC-NEXT: "L136$pb":
+; DARWIN-32-PIC: call L136$pb
+; DARWIN-32-PIC-NEXT: L136$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: leal _dcallee-"L136$pb"(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal _dcallee-L136$pb(%eax), %eax
; DARWIN-32-PIC-NEXT: ret
; DARWIN-64-STATIC: _daddress:
@@ -9224,10 +9224,10 @@ entry:
; DARWIN-32-PIC: _icaller:
; DARWIN-32-PIC: pushl %esi
; DARWIN-32-PIC-NEXT: subl $8, %esp
-; DARWIN-32-PIC-NEXT: call "L143$pb"
-; DARWIN-32-PIC-NEXT: "L143$pb":
+; DARWIN-32-PIC-NEXT: call L143$pb
+; DARWIN-32-PIC-NEXT: L143$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-"L143$pb"(%eax), %esi
+; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L143$pb(%eax), %esi
; DARWIN-32-PIC-NEXT: call *(%esi)
; DARWIN-32-PIC-NEXT: call *(%esi)
; DARWIN-32-PIC-NEXT: addl $8, %esp
@@ -9310,11 +9310,11 @@ entry:
; DARWIN-32-PIC: _dicaller:
; DARWIN-32-PIC: pushl %esi
; DARWIN-32-PIC-NEXT: subl $8, %esp
-; DARWIN-32-PIC-NEXT: call "L144$pb"
-; DARWIN-32-PIC-NEXT: "L144$pb":
+; DARWIN-32-PIC-NEXT: call L144$pb
+; DARWIN-32-PIC-NEXT: L144$pb:
; DARWIN-32-PIC-NEXT: popl %esi
-; DARWIN-32-PIC-NEXT: call *_difunc-"L144$pb"(%esi)
-; DARWIN-32-PIC-NEXT: call *_difunc-"L144$pb"(%esi)
+; DARWIN-32-PIC-NEXT: call *_difunc-L144$pb(%esi)
+; DARWIN-32-PIC-NEXT: call *_difunc-L144$pb(%esi)
; DARWIN-32-PIC-NEXT: addl $8, %esp
; DARWIN-32-PIC-NEXT: popl %esi
; DARWIN-32-PIC-NEXT: ret
@@ -9391,11 +9391,11 @@ entry:
; DARWIN-32-PIC: _licaller:
; DARWIN-32-PIC: pushl %esi
; DARWIN-32-PIC-NEXT: subl $8, %esp
-; DARWIN-32-PIC-NEXT: call "L145$pb"
-; DARWIN-32-PIC-NEXT: "L145$pb":
+; DARWIN-32-PIC-NEXT: call L145$pb
+; DARWIN-32-PIC-NEXT: L145$pb:
; DARWIN-32-PIC-NEXT: popl %esi
-; DARWIN-32-PIC-NEXT: call *_lifunc-"L145$pb"(%esi)
-; DARWIN-32-PIC-NEXT: call *_lifunc-"L145$pb"(%esi)
+; DARWIN-32-PIC-NEXT: call *_lifunc-L145$pb(%esi)
+; DARWIN-32-PIC-NEXT: call *_lifunc-L145$pb(%esi)
; DARWIN-32-PIC-NEXT: addl $8, %esp
; DARWIN-32-PIC-NEXT: popl %esi
; DARWIN-32-PIC-NEXT: ret
@@ -9476,10 +9476,10 @@ entry:
; DARWIN-32-PIC: _itailcaller:
; DARWIN-32-PIC: pushl %esi
; DARWIN-32-PIC-NEXT: subl $8, %esp
-; DARWIN-32-PIC-NEXT: call "L146$pb"
-; DARWIN-32-PIC-NEXT: "L146$pb":
+; DARWIN-32-PIC-NEXT: call L146$pb
+; DARWIN-32-PIC-NEXT: L146$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-"L146$pb"(%eax), %esi
+; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L146$pb(%eax), %esi
; DARWIN-32-PIC-NEXT: call *(%esi)
; DARWIN-32-PIC-NEXT: call *(%esi)
; DARWIN-32-PIC-NEXT: addl $8, %esp
@@ -9553,10 +9553,10 @@ entry:
; DARWIN-32-PIC: _ditailcaller:
; DARWIN-32-PIC: subl $12, %esp
-; DARWIN-32-PIC-NEXT: call "L147$pb"
-; DARWIN-32-PIC-NEXT: "L147$pb":
+; DARWIN-32-PIC-NEXT: call L147$pb
+; DARWIN-32-PIC-NEXT: L147$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: call *_difunc-"L147$pb"(%eax)
+; DARWIN-32-PIC-NEXT: call *_difunc-L147$pb(%eax)
; DARWIN-32-PIC-NEXT: addl $12, %esp
; DARWIN-32-PIC-NEXT: ret
@@ -9619,10 +9619,10 @@ entry:
; DARWIN-32-PIC: _litailcaller:
; DARWIN-32-PIC: subl $12, %esp
-; DARWIN-32-PIC-NEXT: call "L148$pb"
-; DARWIN-32-PIC-NEXT: "L148$pb":
+; DARWIN-32-PIC-NEXT: call L148$pb
+; DARWIN-32-PIC-NEXT: L148$pb:
; DARWIN-32-PIC-NEXT: popl %eax
-; DARWIN-32-PIC-NEXT: call *_lifunc-"L148$pb"(%eax)
+; DARWIN-32-PIC-NEXT: call *_lifunc-L148$pb(%eax)
; DARWIN-32-PIC-NEXT: addl $12, %esp
; DARWIN-32-PIC-NEXT: ret
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/add-trick32.ll b/libclamav/c++/llvm/test/CodeGen/X86/add-trick32.ll
index 42909b4..e86045d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/add-trick32.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/add-trick32.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: not grep add %t
; RUN: grep subl %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/add-trick64.ll b/libclamav/c++/llvm/test/CodeGen/X86/add-trick64.ll
index 5466d9d..2f1fcee 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/add-trick64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/add-trick64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: not grep add %t
; RUN: grep subq %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/add-with-overflow.ll b/libclamav/c++/llvm/test/CodeGen/X86/add-with-overflow.ll
index d015ceb..0f705dc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/add-with-overflow.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/add-with-overflow.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 2
-; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 2
-; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jo} | count 2
-; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jb} | count 2
+; RUN: llc < %s -march=x86 | grep {jo} | count 2
+; RUN: llc < %s -march=x86 | grep {jb} | count 2
+; RUN: llc < %s -march=x86 -O0 | grep {jo} | count 2
+; RUN: llc < %s -march=x86 -O0 | grep {jb} | count 2
@ok = internal constant [4 x i8] c"%d\0A\00"
@no = internal constant [4 x i8] c"no\0A\00"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/aliases.ll b/libclamav/c++/llvm/test/CodeGen/X86/aliases.ll
index 3cfe1aa..0b26859 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/aliases.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/aliases.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=i686-pc-linux-gnu -asm-verbose=false -o %t
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -asm-verbose=false -o %t
; RUN: grep set %t | count 7
; RUN: grep globl %t | count 6
; RUN: grep weak %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/aligned-comm.ll b/libclamav/c++/llvm/test/CodeGen/X86/aligned-comm.ll
index b2dc77d..c0f3a81 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/aligned-comm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/aligned-comm.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin10 | grep {array,16512,7}
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | grep {array,16512,7}
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin8 | not grep {7}
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -mtriple=i386-apple-darwin10 | grep {array,16512,7}
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | grep {array,16512,7}
+; RUN: llc < %s -mtriple=i386-apple-darwin8 | not grep {7}
; Darwin 9+ should get alignment on common symbols. Darwin8 does
; not support this.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/all-ones-vector.ll b/libclamav/c++/llvm/test/CodeGen/X86/all-ones-vector.ll
index 01c0e36..10fecad 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/all-ones-vector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/all-ones-vector.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 | grep pcmpeqd | count 4
+; RUN: llc < %s -march=x86 -mattr=sse2 | grep pcmpeqd | count 4
define <4 x i32> @ioo() nounwind {
ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/alloca-align-rounding.ll b/libclamav/c++/llvm/test/CodeGen/X86/alloca-align-rounding.ll
index 0bd97c2..f45e9b8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/alloca-align-rounding.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/alloca-align-rounding.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-apple-darwin | grep and | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=i686-pc-linux | grep and | count 1
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin | grep and | count 1
+; RUN: llc < %s -march=x86-64 -mtriple=i686-pc-linux | grep and | count 1
declare void @bar(<2 x i64>* %n)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/and-or-fold.ll b/libclamav/c++/llvm/test/CodeGen/X86/and-or-fold.ll
index 3501047..7733b8a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/and-or-fold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/and-or-fold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep and | count 1
+; RUN: llc < %s -march=x86 | grep and | count 1
; The dag combiner should fold together (x&127)|(y&16711680) -> (x|y)&c1
; in this case.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/and-su.ll b/libclamav/c++/llvm/test/CodeGen/X86/and-su.ll
index bdc8454..b5ac23b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/and-su.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/and-su.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {(%} | count 1
+; RUN: llc < %s -march=x86 | grep {(%} | count 1
; Don't duplicate the load.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/anyext-uses.ll b/libclamav/c++/llvm/test/CodeGen/X86/anyext-uses.ll
index e8c3cf0..0cf169e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/anyext-uses.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/anyext-uses.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep mov %t | count 8
; RUN: not grep implicit %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/anyext.ll b/libclamav/c++/llvm/test/CodeGen/X86/anyext.ll
index c5f03ab..106fe83 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/anyext.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/anyext.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movzbl | count 2
+; RUN: llc < %s -march=x86-64 | grep movzbl | count 2
; Use movzbl to avoid partial-register updates.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/arg-cast.ll b/libclamav/c++/llvm/test/CodeGen/X86/arg-cast.ll
index 2e2bc3c..c111514 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/arg-cast.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/arg-cast.ll
@@ -1,7 +1,7 @@
; This should compile to movl $2147483647, %eax + andl only.
-; RUN: llvm-as < %s | llc | grep andl
-; RUN: llvm-as < %s | llc | not grep movsd
-; RUN: llvm-as < %s | llc | grep esp | not grep add
+; RUN: llc < %s | grep andl
+; RUN: llc < %s | not grep movsd
+; RUN: llc < %s | grep esp | not grep add
; rdar://5736574
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/asm-block-labels.ll b/libclamav/c++/llvm/test/CodeGen/X86/asm-block-labels.ll
index 284a9fb..a43d430 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/asm-block-labels.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/asm-block-labels.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -std-compile-opts | llc
+; RUN: opt < %s -std-compile-opts | llc
; ModuleID = 'block12.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/asm-global-imm.ll b/libclamav/c++/llvm/test/CodeGen/X86/asm-global-imm.ll
index 333c768..96da224 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/asm-global-imm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/asm-global-imm.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -relocation-model=static | \
+; RUN: llc < %s -march=x86 -relocation-model=static | \
; RUN: grep {test1 \$_GV}
-; RUN: llvm-as < %s | llc -march=x86 -relocation-model=static | \
+; RUN: llc < %s -march=x86 -relocation-model=static | \
; RUN: grep {test2 _GV}
; PR882
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/asm-indirect-mem.ll b/libclamav/c++/llvm/test/CodeGen/X86/asm-indirect-mem.ll
index 7f3353f..c57aa99 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/asm-indirect-mem.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/asm-indirect-mem.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2267
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/asm-modifier-P.ll b/libclamav/c++/llvm/test/CodeGen/X86/asm-modifier-P.ll
index a77e8fc..6139da8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/asm-modifier-P.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/asm-modifier-P.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-unknown-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC-32
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-unknown-linux-gnu -relocation-model=static | FileCheck %s -check-prefix=CHECK-STATIC-32
-; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=static | FileCheck %s -check-prefix=CHECK-STATIC-64
-; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC-64
+; RUN: llc < %s -march=x86 -mtriple=i686-unknown-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC-32
+; RUN: llc < %s -march=x86 -mtriple=i686-unknown-linux-gnu -relocation-model=static | FileCheck %s -check-prefix=CHECK-STATIC-32
+; RUN: llc < %s -march=x86-64 -relocation-model=static | FileCheck %s -check-prefix=CHECK-STATIC-64
+; RUN: llc < %s -march=x86-64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC-64
; PR3379
; XFAIL: *
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/asm-modifier.ll b/libclamav/c++/llvm/test/CodeGen/X86/asm-modifier.ll
index 10a362f..44f972e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/asm-modifier.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/asm-modifier.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | FileCheck %s
+; RUN: llc < %s | FileCheck %s
; ModuleID = 'asm.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.6"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/atomic_add.ll b/libclamav/c++/llvm/test/CodeGen/X86/atomic_add.ll
index c009210..d00f8e8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/atomic_add.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/atomic_add.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86-64 | FileCheck %s
; rdar://7103704
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/atomic_op.ll b/libclamav/c++/llvm/test/CodeGen/X86/atomic_op.ll
index de73ca3..3ef1887 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/atomic_op.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/atomic_op.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -o %t1
+; RUN: llc < %s -march=x86 -o %t1
; RUN: grep "lock" %t1 | count 17
; RUN: grep "xaddl" %t1 | count 4
; RUN: grep "cmpxchgl" %t1 | count 13
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/attribute-sections.ll b/libclamav/c++/llvm/test/CodeGen/X86/attribute-sections.ll
index 0dba6e6..3035334 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/attribute-sections.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/attribute-sections.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX
declare i32 @foo()
@G0 = global i32 ()* @foo, section ".init_array"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/avoid-lea-scale2.ll b/libclamav/c++/llvm/test/CodeGen/X86/avoid-lea-scale2.ll
index c84662d..8003de2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/avoid-lea-scale2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/avoid-lea-scale2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {leal.*-2(\[%\]rdi,\[%\]rdi)}
+; RUN: llc < %s -march=x86-64 | grep {leal.*-2(\[%\]rdi,\[%\]rdi)}
define i32 @foo(i32 %x) nounwind readnone {
%t0 = shl i32 %x, 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/avoid-loop-align-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/avoid-loop-align-2.ll
index 9f0aeb3..03e69e7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/avoid-loop-align-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/avoid-loop-align-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep align | count 3
+; RUN: llc < %s -march=x86 | grep align | count 3
@x = external global i32* ; <i32**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/avoid-loop-align.ll b/libclamav/c++/llvm/test/CodeGen/X86/avoid-loop-align.ll
index dfc5818..3e68f94 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/avoid-loop-align.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/avoid-loop-align.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep align | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep align | count 1
@A = common global [100 x i32] zeroinitializer, align 32 ; <[100 x i32]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/bitcast-int-to-vector.ll b/libclamav/c++/llvm/test/CodeGen/X86/bitcast-int-to-vector.ll
index 370bec0..4c25979 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/bitcast-int-to-vector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/bitcast-int-to-vector.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i1 @foo(i64 %a)
{
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/bitcast.ll b/libclamav/c++/llvm/test/CodeGen/X86/bitcast.ll
index f575409..c34c675 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/bitcast.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/bitcast.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
; PR1033
define i64 @test1(double %t) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/bitcast2.ll b/libclamav/c++/llvm/test/CodeGen/X86/bitcast2.ll
index 3e26931..48922b5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/bitcast2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/bitcast2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movd | count 2
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep rsp
+; RUN: llc < %s -march=x86-64 | grep movd | count 2
+; RUN: llc < %s -march=x86-64 | not grep rsp
define i64 @test1(double %A) {
%B = bitcast double %A to i64
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/break-anti-dependencies.ll b/libclamav/c++/llvm/test/CodeGen/X86/break-anti-dependencies.ll
index b9ce10f..6b245c1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/break-anti-dependencies.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/break-anti-dependencies.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -disable-post-RA-scheduler=false -break-anti-dependencies=false > %t
+; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=false > %t
; RUN: grep {%xmm0} %t | count 14
; RUN: not grep {%xmm1} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -disable-post-RA-scheduler=false -break-anti-dependencies > %t
+; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies > %t
; RUN: grep {%xmm0} %t | count 7
; RUN: grep {%xmm1} %t | count 7
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/bss_pagealigned.ll b/libclamav/c++/llvm/test/CodeGen/X86/bss_pagealigned.ll
new file mode 100644
index 0000000..4a1049b
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/bss_pagealigned.ll
@@ -0,0 +1,21 @@
+; RUN: llc --code-model=kernel -march=x86-64 <%s | FileCheck %s
+; PR4933
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+%struct.kmem_cache_order_objects = type { i64 }
+declare i8* @memset(i8*, i32, i64)
+define void @unxlate_dev_mem_ptr(i64 %phis, i8* %addr) nounwind {
+ %pte.addr.i = alloca %struct.kmem_cache_order_objects*
+ %call8 = call i8* @memset(i8* bitcast ([512 x %struct.kmem_cache_order_objects]* @bm_pte to i8*), i32 0, i64 4096)
+; CHECK: movq $bm_pte, %rdi
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: movl $4096, %edx
+; CHECK-NEXT: call memset
+ ret void
+}
+ at bm_pte = internal global [512 x %struct.kmem_cache_order_objects] zeroinitializer, section ".bss.page_aligned", align 4096
+; CHECK: .section .bss.page_aligned,"aw", at nobits
+; CHECK-NEXT: .align 4096
+; CHECK-NEXT: bm_pte:
+; CHECK-NEXT: .zero 4096
+; CHECK-NEXT: .size bm_pte, 4096
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/bswap-inline-asm.ll b/libclamav/c++/llvm/test/CodeGen/X86/bswap-inline-asm.ll
index 91f8310..5bf58fa 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/bswap-inline-asm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/bswap-inline-asm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: not grep APP %t
; RUN: grep bswapq %t | count 2
; RUN: grep bswapl %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/bswap.ll b/libclamav/c++/llvm/test/CodeGen/X86/bswap.ll
index 592e25b..0a72c1c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/bswap.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/bswap.ll
@@ -1,8 +1,8 @@
; bswap should be constant folded when it is passed a constant argument
-; RUN: llvm-as < %s | llc -march=x86 | \
+; RUN: llc < %s -march=x86 | \
; RUN: grep bswapl | count 3
-; RUN: llvm-as < %s | llc -march=x86 | grep rolw | count 1
+; RUN: llc < %s -march=x86 | grep rolw | count 1
declare i16 @llvm.bswap.i16(i16)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/bt.ll b/libclamav/c++/llvm/test/CodeGen/X86/bt.ll
index a76242c..ec447e5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/bt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/bt.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep btl | count 28
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium4 | grep btl | not grep esp
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=penryn | grep btl | not grep esp
+; RUN: llc < %s -march=x86 | grep btl | count 28
+; RUN: llc < %s -march=x86 -mcpu=pentium4 | grep btl | not grep esp
+; RUN: llc < %s -march=x86 -mcpu=penryn | grep btl | not grep esp
; PR3253
; The register+memory form of the BT instruction should be usable on
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/byval.ll b/libclamav/c++/llvm/test/CodeGen/X86/byval.ll
index a75214a..af36e1b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/byval.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/byval.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movq 8(%rsp), %rax}
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86-64 | grep {movq 8(%rsp), %rax}
+; RUN: llc < %s -march=x86 > %t
; RUN: grep {movl 8(%esp), %edx} %t
; RUN: grep {movl 4(%esp), %eax} %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/byval2.ll b/libclamav/c++/llvm/test/CodeGen/X86/byval2.ll
index f85c8ff..71129f5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/byval2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/byval2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsq | count 2
-; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsl | count 2
+; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2
+; RUN: llc < %s -march=x86 | grep rep.movsl | count 2
%struct.s = type { i64, i64, i64, i64, i64, i64, i64, i64,
i64, i64, i64, i64, i64, i64, i64, i64,
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/byval3.ll b/libclamav/c++/llvm/test/CodeGen/X86/byval3.ll
index 707a4c5..504e0be 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/byval3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/byval3.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsq | count 2
-; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsl | count 2
+; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2
+; RUN: llc < %s -march=x86 | grep rep.movsl | count 2
%struct.s = type { i32, i32, i32, i32, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32,
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/byval4.ll b/libclamav/c++/llvm/test/CodeGen/X86/byval4.ll
index 5576c36..4db9d65 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/byval4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/byval4.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsq | count 2
-; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsl | count 2
+; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2
+; RUN: llc < %s -march=x86 | grep rep.movsl | count 2
%struct.s = type { i16, i16, i16, i16, i16, i16, i16, i16,
i16, i16, i16, i16, i16, i16, i16, i16,
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/byval5.ll b/libclamav/c++/llvm/test/CodeGen/X86/byval5.ll
index c6f4588..69c115b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/byval5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/byval5.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsq | count 2
-; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsl | count 2
+; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2
+; RUN: llc < %s -march=x86 | grep rep.movsl | count 2
%struct.s = type { i8, i8, i8, i8, i8, i8, i8, i8,
i8, i8, i8, i8, i8, i8, i8, i8,
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/byval6.ll b/libclamav/c++/llvm/test/CodeGen/X86/byval6.ll
index 47269d2..b060369 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/byval6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/byval6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep add | not grep 16
+; RUN: llc < %s -march=x86 | grep add | not grep 16
%struct.W = type { x86_fp80, x86_fp80 }
@B = global %struct.W { x86_fp80 0xK4001A000000000000000, x86_fp80 0xK4001C000000000000000 }, align 32
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/byval7.ll b/libclamav/c++/llvm/test/CodeGen/X86/byval7.ll
index 6b64c6c..0da93ba 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/byval7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/byval7.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | egrep {add|lea} | grep 16
+; RUN: llc < %s -march=x86 -mcpu=yonah | egrep {add|lea} | grep 16
%struct.S = type { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>,
<2 x i64> }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/call-imm.ll b/libclamav/c++/llvm/test/CodeGen/X86/call-imm.ll
index 6e9c70d..87785bc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/call-imm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/call-imm.ll
@@ -1,11 +1,11 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-darwin-apple -relocation-model=static | grep {call.*12345678}
-; RUN: llvm-as < %s | llc -mtriple=i386-darwin-apple -relocation-model=pic | not grep {call.*12345678}
-; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux -relocation-model=dynamic-no-pic | grep {call.*12345678}
+; RUN: llc < %s -mtriple=i386-darwin-apple -relocation-model=static | grep {call.*12345678}
+; RUN: llc < %s -mtriple=i386-darwin-apple -relocation-model=pic | not grep {call.*12345678}
+; RUN: llc < %s -mtriple=i386-pc-linux -relocation-model=dynamic-no-pic | grep {call.*12345678}
; Call to immediate is not safe on x86-64 unless we *know* that the
; call will be within 32-bits pcrel from the dest immediate.
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {call.*\*%rax}
+; RUN: llc < %s -march=x86-64 | grep {call.*\*%rax}
; PR3666
; PR3773
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/call-push.ll b/libclamav/c++/llvm/test/CodeGen/X86/call-push.ll
index ad9b796..7bae5cd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/call-push.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/call-push.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -disable-fp-elim | grep subl | count 1
+; RUN: llc < %s -march=x86 -disable-fp-elim | grep subl | count 1
%struct.decode_t = type { i8, i8, i8, i8, i16, i8, i8, %struct.range_t** }
%struct.range_t = type { float, float, i32, i32, i32, [0 x i8] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/change-compare-stride-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/change-compare-stride-0.ll
index 87194d6..d520a6f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/change-compare-stride-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/change-compare-stride-0.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
-; RUN: grep {cmpl \$4294966818,} %t
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep {cmpl \$-478,} %t
; RUN: not grep inc %t
; RUN: not grep {leal 1(} %t
; RUN: not grep {leal -1(} %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/change-compare-stride-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/change-compare-stride-1.ll
index 49b691f..a9ddbdb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/change-compare-stride-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/change-compare-stride-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep {cmpq \$-478,} %t
; RUN: not grep inc %t
; RUN: not grep {leal 1(} %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/clz.ll b/libclamav/c++/llvm/test/CodeGen/X86/clz.ll
index c3b3b41..3f27187 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/clz.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/clz.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep bsr | count 2
-; RUN: llvm-as < %s | llc -march=x86 | grep bsf
-; RUN: llvm-as < %s | llc -march=x86 | grep cmov | count 3
+; RUN: llc < %s -march=x86 | grep bsr | count 2
+; RUN: llc < %s -march=x86 | grep bsf
+; RUN: llc < %s -march=x86 | grep cmov | count 3
define i32 @t1(i32 %x) nounwind {
%tmp = tail call i32 @llvm.ctlz.i32( i32 %x )
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/cmov-i8-eflags.ll b/libclamav/c++/llvm/test/CodeGen/X86/cmov-i8-eflags.ll
deleted file mode 100644
index e81ce58..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/cmov-i8-eflags.ll
+++ /dev/null
@@ -1,55 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | %prcontext {setne %al} 1 | grep test | count 2
-; PR4814
-
-; CodeGen shouldn't try to do a setne after an expanded 8-bit conditional
-; move without recomputing EFLAGS, because the expansion of the conditional
-; move with control flow may clobber EFLAGS (e.g., with xor, to set the
-; register to zero).
-
-; The prcontext usage above is a little awkward; the important part is that
-; there's a test before the setne.
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
-
- at g_3 = external global i8 ; <i8*> [#uses=1]
- at g_96 = external global i8 ; <i8*> [#uses=2]
- at g_100 = external global i8 ; <i8*> [#uses=2]
- at _2E_str = external constant [15 x i8], align 1 ; <[15 x i8]*> [#uses=1]
-
-define i32 @main() nounwind {
-entry:
- %0 = load i8* @g_3, align 1 ; <i8> [#uses=2]
- %1 = sext i8 %0 to i32 ; <i32> [#uses=1]
- %.lobit.i = lshr i8 %0, 7 ; <i8> [#uses=1]
- %tmp.i = zext i8 %.lobit.i to i32 ; <i32> [#uses=1]
- %tmp.not.i = xor i32 %tmp.i, 1 ; <i32> [#uses=1]
- %iftmp.17.0.i.i = ashr i32 %1, %tmp.not.i ; <i32> [#uses=1]
- %retval56.i.i = trunc i32 %iftmp.17.0.i.i to i8 ; <i8> [#uses=1]
- %2 = icmp eq i8 %retval56.i.i, 0 ; <i1> [#uses=2]
- %g_96.promoted.i = load i8* @g_96 ; <i8> [#uses=3]
- %3 = icmp eq i8 %g_96.promoted.i, 0 ; <i1> [#uses=2]
- br i1 %3, label %func_4.exit.i, label %bb.i.i.i
-
-bb.i.i.i: ; preds = %entry
- %4 = volatile load i8* @g_100, align 1 ; <i8> [#uses=0]
- br label %func_4.exit.i
-
-func_4.exit.i: ; preds = %bb.i.i.i, %entry
- %.not.i = xor i1 %2, true ; <i1> [#uses=1]
- %brmerge.i = or i1 %3, %.not.i ; <i1> [#uses=1]
- %.mux.i = select i1 %2, i8 %g_96.promoted.i, i8 0 ; <i8> [#uses=1]
- br i1 %brmerge.i, label %func_1.exit, label %bb.i.i
-
-bb.i.i: ; preds = %func_4.exit.i
- %5 = volatile load i8* @g_100, align 1 ; <i8> [#uses=0]
- br label %func_1.exit
-
-func_1.exit: ; preds = %bb.i.i, %func_4.exit.i
- %g_96.tmp.0.i = phi i8 [ %g_96.promoted.i, %bb.i.i ], [ %.mux.i, %func_4.exit.i ] ; <i8> [#uses=2]
- store i8 %g_96.tmp.0.i, i8* @g_96
- %6 = zext i8 %g_96.tmp.0.i to i32 ; <i32> [#uses=1]
- %7 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr ([15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind ; <i32> [#uses=0]
- ret i32 0
-}
-
-declare i32 @printf(i8* nocapture, ...) nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/cmov.ll b/libclamav/c++/llvm/test/CodeGen/X86/cmov.ll
new file mode 100644
index 0000000..f3c9a7a
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/cmov.ll
@@ -0,0 +1,157 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+
+define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
+entry:
+; CHECK: test1:
+; CHECK: btl
+; CHECK-NEXT: movl $12, %eax
+; CHECK-NEXT: cmovae (%rcx), %eax
+; CHECK-NEXT: ret
+
+ %0 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %1 = and i32 %0, 1 ; <i32> [#uses=1]
+ %toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1]
+ %v = load i32* %vp
+ %.0 = select i1 %toBool, i32 %v, i32 12 ; <i32> [#uses=1]
+ ret i32 %.0
+}
+define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
+entry:
+; CHECK: test2:
+; CHECK: btl
+; CHECK-NEXT: movl $12, %eax
+; CHECK-NEXT: cmovb (%rcx), %eax
+; CHECK-NEXT: ret
+
+ %0 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %1 = and i32 %0, 1 ; <i32> [#uses=1]
+ %toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1]
+ %v = load i32* %vp
+ %.0 = select i1 %toBool, i32 12, i32 %v ; <i32> [#uses=1]
+ ret i32 %.0
+}
+
+
+; x86's 32-bit cmov doesn't clobber the high 32 bits of the destination
+; if the condition is false. An explicit zero-extend (movl) is needed
+; after the cmov.
+
+declare void @bar(i64) nounwind
+
+define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
+; CHECK: test3:
+; CHECK: cmovne %edi, %esi
+; CHECK-NEXT: movl %esi, %edi
+
+ %c = trunc i64 %a to i32
+ %d = trunc i64 %b to i32
+ %e = select i1 %p, i32 %c, i32 %d
+ %f = zext i32 %e to i64
+ call void @bar(i64 %f)
+ ret void
+}
+
+
+
+; CodeGen shouldn't try to do a setne after an expanded 8-bit conditional
+; move without recomputing EFLAGS, because the expansion of the conditional
+; move with control flow may clobber EFLAGS (e.g., with xor, to set the
+; register to zero).
+
+; The test is a little awkward; the important part is that there's a test before the
+; setne.
+; PR4814
+
+
+ at g_3 = external global i8 ; <i8*> [#uses=1]
+ at g_96 = external global i8 ; <i8*> [#uses=2]
+ at g_100 = external global i8 ; <i8*> [#uses=2]
+ at _2E_str = external constant [15 x i8], align 1 ; <[15 x i8]*> [#uses=1]
+
+define i32 @test4() nounwind {
+entry:
+ %0 = load i8* @g_3, align 1 ; <i8> [#uses=2]
+ %1 = sext i8 %0 to i32 ; <i32> [#uses=1]
+ %.lobit.i = lshr i8 %0, 7 ; <i8> [#uses=1]
+ %tmp.i = zext i8 %.lobit.i to i32 ; <i32> [#uses=1]
+ %tmp.not.i = xor i32 %tmp.i, 1 ; <i32> [#uses=1]
+ %iftmp.17.0.i.i = ashr i32 %1, %tmp.not.i ; <i32> [#uses=1]
+ %retval56.i.i = trunc i32 %iftmp.17.0.i.i to i8 ; <i8> [#uses=1]
+ %2 = icmp eq i8 %retval56.i.i, 0 ; <i1> [#uses=2]
+ %g_96.promoted.i = load i8* @g_96 ; <i8> [#uses=3]
+ %3 = icmp eq i8 %g_96.promoted.i, 0 ; <i1> [#uses=2]
+ br i1 %3, label %func_4.exit.i, label %bb.i.i.i
+
+bb.i.i.i: ; preds = %entry
+ %4 = volatile load i8* @g_100, align 1 ; <i8> [#uses=0]
+ br label %func_4.exit.i
+
+; CHECK: test4:
+; CHECK: g_100
+; CHECK: testb
+; CHECK: testb %al, %al
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: testb
+
+func_4.exit.i: ; preds = %bb.i.i.i, %entry
+ %.not.i = xor i1 %2, true ; <i1> [#uses=1]
+ %brmerge.i = or i1 %3, %.not.i ; <i1> [#uses=1]
+ %.mux.i = select i1 %2, i8 %g_96.promoted.i, i8 0 ; <i8> [#uses=1]
+ br i1 %brmerge.i, label %func_1.exit, label %bb.i.i
+
+bb.i.i: ; preds = %func_4.exit.i
+ %5 = volatile load i8* @g_100, align 1 ; <i8> [#uses=0]
+ br label %func_1.exit
+
+func_1.exit: ; preds = %bb.i.i, %func_4.exit.i
+ %g_96.tmp.0.i = phi i8 [ %g_96.promoted.i, %bb.i.i ], [ %.mux.i, %func_4.exit.i ] ; <i8> [#uses=2]
+ store i8 %g_96.tmp.0.i, i8* @g_96
+ %6 = zext i8 %g_96.tmp.0.i to i32 ; <i32> [#uses=1]
+ %7 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr ([15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i32 @printf(i8* nocapture, ...) nounwind
+
+
+; Should compile to setcc | -2.
+; rdar://6668608
+define i32 @test5(i32* nocapture %P) nounwind readonly {
+entry:
+; CHECK: test5:
+; CHECK: setg %al
+; CHECK: movzbl %al, %eax
+; CHECK: orl $-2, %eax
+; CHECK: ret
+
+ %0 = load i32* %P, align 4 ; <i32> [#uses=1]
+ %1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1]
+ %iftmp.0.0 = select i1 %1, i32 -1, i32 -2 ; <i32> [#uses=1]
+ ret i32 %iftmp.0.0
+}
+
+define i32 @test6(i32* nocapture %P) nounwind readonly {
+entry:
+; CHECK: test6:
+; CHECK: setl %al
+; CHECK: movzbl %al, %eax
+; CHECK: leal 4(%rax,%rax,8), %eax
+; CHECK: ret
+ %0 = load i32* %P, align 4 ; <i32> [#uses=1]
+ %1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1]
+ %iftmp.0.0 = select i1 %1, i32 4, i32 13 ; <i32> [#uses=1]
+ ret i32 %iftmp.0.0
+}
+
+
+; Don't try to use a 16-bit conditional move to do an 8-bit select,
+; because it isn't worth it. Just use a branch instead.
+define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind {
+; CHECK: test7:
+; CHECK: testb $1, %dil
+; CHECK-NEXT: jne LBB
+
+ %d = select i1 %c, i8 %a, i8 %b
+ ret i8 %d
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/cmp-test.ll b/libclamav/c++/llvm/test/CodeGen/X86/cmp-test.ll
index 91c8a87..898c09b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/cmp-test.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/cmp-test.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep cmp | count 1
-; RUN: llvm-as < %s | llc -march=x86 | grep test | count 1
+; RUN: llc < %s -march=x86 | grep cmp | count 1
+; RUN: llc < %s -march=x86 | grep test | count 1
define i32 @f1(i32 %X, i32* %y) {
%tmp = load i32* %y ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/cmp0.ll b/libclamav/c++/llvm/test/CodeGen/X86/cmp0.ll
index f66f90c..de89374 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/cmp0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/cmp0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep -v cmp
+; RUN: llc < %s -march=x86-64 | grep -v cmp
define i64 @foo(i64 %x) {
%t = icmp eq i64 %x, 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/cmp1.ll b/libclamav/c++/llvm/test/CodeGen/X86/cmp1.ll
index 241618c..d4aa399 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/cmp1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/cmp1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep -v cmp
+; RUN: llc < %s -march=x86-64 | grep -v cmp
define i64 @foo(i64 %x) {
%t = icmp slt i64 %x, 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/cmp2.ll b/libclamav/c++/llvm/test/CodeGen/X86/cmp2.ll
index 2c046ff..9a8e00c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/cmp2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/cmp2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep ucomisd | grep CPI | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep ucomisd | grep CPI | count 2
define i32 @test(double %A) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/coalesce-esp.ll b/libclamav/c++/llvm/test/CodeGen/X86/coalesce-esp.ll
index ede9b59..0fe4e56 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/coalesce-esp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/coalesce-esp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep {movl %esp, %eax}
+; RUN: llc < %s | grep {movl %esp, %eax}
; PR4572
; Don't coalesce with %esp if it would end up putting %esp in
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute1.ll b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute1.ll
index 9939424..8aa0bfd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
; PR1877
@NNTOT = weak global i32 0 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute2.ll b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute2.ll
index c67e0f5..5d10bba 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep paddw | count 2
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep mov
+; RUN: llc < %s -march=x86-64 | grep paddw | count 2
+; RUN: llc < %s -march=x86-64 | not grep mov
; The 2-addr pass should ensure that identical code is produced for these functions
; no extra copy should be generated.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute3.ll b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute3.ll
index 7d4a80a..e5bd448 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | count 6
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | count 6
%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute4.ll b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute4.ll
index 9628f93..02a9781 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
; PR1501
define float @foo(i32* %x, float* %y, i32 %c) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute5.ll b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute5.ll
index c730ea7..510d115 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-commute5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
define i32 @t() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-cross.ll b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-cross.ll
index 1da214c..7d6f399 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-cross.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-cross.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin10 | not grep movaps
+; RUN: llc < %s -mtriple=i386-apple-darwin10 | not grep movaps
; rdar://6509240
type { %struct.TValue } ; type %0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-remat.ll b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-remat.ll
index ab029f4..4db520f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/coalescer-remat.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/coalescer-remat.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep xor | count 3
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep xor | count 3
@val = internal global i64 0 ; <i64*> [#uses=1]
@"\01LC" = internal constant [7 x i8] c"0x%lx\0A\00" ; <[7 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/code_placement.ll b/libclamav/c++/llvm/test/CodeGen/X86/code_placement.ll
index 5516795..9747183 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/code_placement.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/code_placement.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | %prcontext jmp 1 | grep align
+; RUN: llc -march=x86 < %s | FileCheck %s
@Te0 = external global [256 x i32] ; <[256 x i32]*> [#uses=5]
@Te1 = external global [256 x i32] ; <[256 x i32]*> [#uses=4]
@@ -12,6 +12,8 @@ entry:
%tmp15 = add i32 %r, -1 ; <i32> [#uses=1]
%tmp.16 = zext i32 %tmp15 to i64 ; <i64> [#uses=2]
br label %bb
+; CHECK: jmp
+; CHECK-NEXT: align
bb: ; preds = %bb1, %entry
%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %bb1 ] ; <i64> [#uses=3]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/codegen-prepare-cast.ll b/libclamav/c++/llvm/test/CodeGen/X86/codegen-prepare-cast.ll
index ae3eb5f..2a8ead8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/codegen-prepare-cast.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/codegen-prepare-cast.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
; PR4297
target datalayout =
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/codemodel.ll b/libclamav/c++/llvm/test/CodeGen/X86/codemodel.ll
index 7743628..b6ca1ce 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/codemodel.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/codemodel.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -code-model=small | FileCheck -check-prefix CHECK-SMALL %s
-; RUN: llvm-as < %s | llc -code-model=kernel | FileCheck -check-prefix CHECK-KERNEL %s
+; RUN: llc < %s -code-model=small | FileCheck -check-prefix CHECK-SMALL %s
+; RUN: llc < %s -code-model=kernel | FileCheck -check-prefix CHECK-KERNEL %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/combine-lds.ll b/libclamav/c++/llvm/test/CodeGen/X86/combine-lds.ll
index a78a042..b49d081 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/combine-lds.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/combine-lds.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep fldl | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep fldl | count 1
define double @doload64(i64 %x) nounwind {
%tmp717 = bitcast i64 %x to double
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/combiner-aa-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/combiner-aa-0.ll
index d2913ab..a61ef7a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/combiner-aa-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/combiner-aa-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -combiner-global-alias-analysis -combiner-alias-analysis
+; RUN: llc < %s -march=x86-64 -combiner-global-alias-analysis -combiner-alias-analysis
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
%struct.Hash_Key = type { [4 x i32], i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/combiner-aa-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/combiner-aa-1.ll
new file mode 100644
index 0000000..58a7129
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/combiner-aa-1.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s --combiner-alias-analysis --combiner-global-alias-analysis
+; PR4880
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+
+%struct.alst_node = type { %struct.node }
+%struct.arg_node = type { %struct.node, i8*, %struct.alst_node* }
+%struct.arglst_node = type { %struct.alst_node, %struct.arg_node*, %struct.arglst_node* }
+%struct.lam_node = type { %struct.alst_node, %struct.arg_node*, %struct.alst_node* }
+%struct.node = type { i32 (...)**, %struct.node* }
+
+define i32 @._ZN8lam_node18resolve_name_clashEP8arg_nodeP9alst_node._ZNK8lam_nodeeqERK8exp_node._ZN11arglst_nodeD0Ev(%struct.lam_node* %this.this, %struct.arg_node* %outer_arg, %struct.alst_node* %env.cmp, %struct.arglst_node* %this, i32 %functionID) {
+comb_entry:
+ %.SV59 = alloca %struct.node* ; <%struct.node**> [#uses=1]
+ %0 = load i32 (...)*** null, align 4 ; <i32 (...)**> [#uses=1]
+ %1 = getelementptr inbounds i32 (...)** %0, i32 3 ; <i32 (...)**> [#uses=1]
+ %2 = load i32 (...)** %1, align 4 ; <i32 (...)*> [#uses=1]
+ store %struct.node* undef, %struct.node** %.SV59
+ %3 = bitcast i32 (...)* %2 to i32 (%struct.node*)* ; <i32 (%struct.node*)*> [#uses=1]
+ %4 = tail call i32 %3(%struct.node* undef) ; <i32> [#uses=0]
+ unreachable
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/commute-cmov.ll b/libclamav/c++/llvm/test/CodeGen/X86/commute-cmov.ll
deleted file mode 100644
index 30c7347..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/commute-cmov.ll
+++ /dev/null
@@ -1,30 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86 | FileCheck %s
-
-define i32 @test1(i32 %x, i32 %n, i32 %w, i32 %v) nounwind readnone {
-entry:
-; CHECK: test1:
-; CHECK: btl
-; CHECK-NEXT: movl $12, %eax
-; CHECK-NEXT: cmovae 16(%esp), %eax
-; CHECK-NEXT: ret
-
- %0 = lshr i32 %x, %n ; <i32> [#uses=1]
- %1 = and i32 %0, 1 ; <i32> [#uses=1]
- %toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1]
- %.0 = select i1 %toBool, i32 %v, i32 12 ; <i32> [#uses=1]
- ret i32 %.0
-}
-define i32 @test2(i32 %x, i32 %n, i32 %w, i32 %v) nounwind readnone {
-entry:
-; CHECK: test2:
-; CHECK: btl
-; CHECK-NEXT: movl $12, %eax
-; CHECK-NEXT: cmovb 16(%esp), %eax
-; CHECK-NEXT: ret
-
- %0 = lshr i32 %x, %n ; <i32> [#uses=1]
- %1 = and i32 %0, 1 ; <i32> [#uses=1]
- %toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1]
- %.0 = select i1 %toBool, i32 12, i32 %v ; <i32> [#uses=1]
- ret i32 %.0
-}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/commute-intrinsic.ll b/libclamav/c++/llvm/test/CodeGen/X86/commute-intrinsic.ll
index 12c0e03..d810cb1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/commute-intrinsic.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/commute-intrinsic.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mattr=+sse2 -relocation-model=static | not grep movaps
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -relocation-model=static | not grep movaps
@a = external global <2 x i64> ; <<2 x i64>*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/commute-two-addr.ll b/libclamav/c++/llvm/test/CodeGen/X86/commute-two-addr.ll
index 224f5d5..56ea26b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/commute-two-addr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/commute-two-addr.ll
@@ -2,7 +2,7 @@
; insertion of register-register copies.
; Make sure there are only 3 mov's for each testcase
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {\\\<mov\\\>} | count 6
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/compare-add.ll b/libclamav/c++/llvm/test/CodeGen/X86/compare-add.ll
index aa69a31..358ee59 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/compare-add.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/compare-add.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep add
+; RUN: llc < %s -march=x86 | not grep add
define i1 @X(i32 %X) {
%Y = add i32 %X, 14 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/compare-inf.ll b/libclamav/c++/llvm/test/CodeGen/X86/compare-inf.ll
new file mode 100644
index 0000000..2be90c9
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/compare-inf.ll
@@ -0,0 +1,76 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+; Convert oeq and une to ole/oge/ule/uge when comparing with infinity
+; and negative infinity, because those are more efficient on x86.
+
+; CHECK: oeq_inff:
+; CHECK: ucomiss
+; CHECK: jae
+define float @oeq_inff(float %x, float %y) nounwind readonly {
+ %t0 = fcmp oeq float %x, 0x7FF0000000000000
+ %t1 = select i1 %t0, float 1.0, float %y
+ ret float %t1
+}
+
+; CHECK: oeq_inf:
+; CHECK: ucomisd
+; CHECK: jae
+define double @oeq_inf(double %x, double %y) nounwind readonly {
+ %t0 = fcmp oeq double %x, 0x7FF0000000000000
+ %t1 = select i1 %t0, double 1.0, double %y
+ ret double %t1
+}
+
+; CHECK: une_inff:
+; CHECK: ucomiss
+; CHECK: jb
+define float @une_inff(float %x, float %y) nounwind readonly {
+ %t0 = fcmp une float %x, 0x7FF0000000000000
+ %t1 = select i1 %t0, float 1.0, float %y
+ ret float %t1
+}
+
+; CHECK: une_inf:
+; CHECK: ucomisd
+; CHECK: jb
+define double @une_inf(double %x, double %y) nounwind readonly {
+ %t0 = fcmp une double %x, 0x7FF0000000000000
+ %t1 = select i1 %t0, double 1.0, double %y
+ ret double %t1
+}
+
+; CHECK: oeq_neg_inff:
+; CHECK: ucomiss
+; CHECK: jae
+define float @oeq_neg_inff(float %x, float %y) nounwind readonly {
+ %t0 = fcmp oeq float %x, 0xFFF0000000000000
+ %t1 = select i1 %t0, float 1.0, float %y
+ ret float %t1
+}
+
+; CHECK: oeq_neg_inf:
+; CHECK: ucomisd
+; CHECK: jae
+define double @oeq_neg_inf(double %x, double %y) nounwind readonly {
+ %t0 = fcmp oeq double %x, 0xFFF0000000000000
+ %t1 = select i1 %t0, double 1.0, double %y
+ ret double %t1
+}
+
+; CHECK: une_neg_inff:
+; CHECK: ucomiss
+; CHECK: jb
+define float @une_neg_inff(float %x, float %y) nounwind readonly {
+ %t0 = fcmp une float %x, 0xFFF0000000000000
+ %t1 = select i1 %t0, float 1.0, float %y
+ ret float %t1
+}
+
+; CHECK: une_neg_inf:
+; CHECK: ucomisd
+; CHECK: jb
+define double @une_neg_inf(double %x, double %y) nounwind readonly {
+ %t0 = fcmp une double %x, 0xFFF0000000000000
+ %t1 = select i1 %t0, double 1.0, double %y
+ ret double %t1
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/compare_folding.ll b/libclamav/c++/llvm/test/CodeGen/X86/compare_folding.ll
index c6cda4a..84c152d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/compare_folding.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/compare_folding.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | \
+; RUN: llc < %s -march=x86 -mcpu=yonah | \
; RUN: grep movsd | count 1
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | \
+; RUN: llc < %s -march=x86 -mcpu=yonah | \
; RUN: grep ucomisd
declare i1 @llvm.isunordered.f64(double, double)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/compiler_used.ll b/libclamav/c++/llvm/test/CodeGen/X86/compiler_used.ll
index b67bc36..be8de5e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/compiler_used.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/compiler_used.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | grep no_dead_strip | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | grep no_dead_strip | count 1
; We should have a .no_dead_strip directive for Z but not for X/Y.
@X = internal global i8 4
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/complex-fca.ll b/libclamav/c++/llvm/test/CodeGen/X86/complex-fca.ll
index 05adb50..7e7acaa 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/complex-fca.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/complex-fca.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 2
+; RUN: llc < %s -march=x86 | grep mov | count 2
define void @ccosl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 } %z) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/const-select.ll b/libclamav/c++/llvm/test/CodeGen/X86/const-select.ll
index 6e3156b..ca8cc14 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/const-select.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/const-select.ll
@@ -2,7 +2,7 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin7"
-; RUN: llvm-as < %s | llc | grep {LCPI1_0(,%eax,4)}
+; RUN: llc < %s | grep {LCPI1_0(,%eax,4)}
define float @f(i32 %x) nounwind readnone {
entry:
%0 = icmp eq i32 %x, 0 ; <i1> [#uses=1]
@@ -10,7 +10,7 @@ entry:
ret float %iftmp.0.0
}
-; RUN: llvm-as < %s | llc | grep {movsbl.*(%e.x,%e.x,4), %eax}
+; RUN: llc < %s | grep {movsbl.*(%e.x,%e.x,4), %eax}
define signext i8 @test(i8* nocapture %P, double %F) nounwind readonly {
entry:
%0 = fcmp olt double %F, 4.200000e+01 ; <i1> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/constant-pool-remat-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/constant-pool-remat-0.ll
index 80be854..05388f9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/constant-pool-remat-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/constant-pool-remat-0.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep LCPI | count 3
-; RUN: llvm-as < %s | llc -march=x86-64 -stats -info-output-file - | grep asm-printer | grep 6
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep LCPI | count 3
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -info-output-file - | grep asm-printer | grep 12
+; RUN: llc < %s -march=x86-64 | grep LCPI | count 3
+; RUN: llc < %s -march=x86-64 -stats -info-output-file - | grep asm-printer | grep 6
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep LCPI | count 3
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats -info-output-file - | grep asm-printer | grep 12
declare float @qux(float %y)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/constpool.ll b/libclamav/c++/llvm/test/CodeGen/X86/constpool.ll
index 60d51e5..2aac486 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/constpool.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/constpool.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc
-; RUN: llvm-as < %s | llc -fast-isel
-; RUN: llvm-as < %s | llc -march=x86-64
-; RUN: llvm-as < %s | llc -fast-isel -march=x86-64
+; RUN: llc < %s
+; RUN: llc < %s -fast-isel
+; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -fast-isel -march=x86-64
; PR4466
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll b/libclamav/c++/llvm/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
index c0c1767..2b4b832 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -o %t -stats -info-output-file - | \
+; RUN: llc < %s -march=x86-64 -o %t -stats -info-output-file - | \
; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 5
; RUN: grep {leal 1(\%rsi),} %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/copysign-zero.ll b/libclamav/c++/llvm/test/CodeGen/X86/copysign-zero.ll
index a08fa65..47522d8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/copysign-zero.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/copysign-zero.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc | not grep orpd
-; RUN: llvm-as < %s | llc | grep andpd | count 1
+; RUN: llc < %s | not grep orpd
+; RUN: llc < %s | grep andpd | count 1
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/critical-edge-split.ll b/libclamav/c++/llvm/test/CodeGen/X86/critical-edge-split.ll
index 4539ef6..4fe554d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/critical-edge-split.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/critical-edge-split.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -tailcallopt=false -stats -info-output-file - | grep asm-printer | grep 31
+; RUN: llc < %s -mtriple=i386-apple-darwin -tailcallopt=false -stats -info-output-file - | grep asm-printer | grep 31
%CC = type { %Register }
%II = type { %"struct.XX::II::$_74" }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/cstring.ll b/libclamav/c++/llvm/test/CodeGen/X86/cstring.ll
index 27d6181..5b5a766 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/cstring.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/cstring.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | not grep comm
+; RUN: llc < %s -mtriple=i386-apple-darwin | not grep comm
; rdar://6479858
@str1 = internal constant [1 x i8] zeroinitializer
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/dag-rauw-cse.ll b/libclamav/c++/llvm/test/CodeGen/X86/dag-rauw-cse.ll
index ba84711..edcfeb7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/dag-rauw-cse.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/dag-rauw-cse.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {orl \$1}
+; RUN: llc < %s -march=x86 | grep {orl \$1}
; PR3018
define i32 @test(i32 %A) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/dagcombine-buildvector.ll b/libclamav/c++/llvm/test/CodeGen/X86/dagcombine-buildvector.ll
index 95e27b0..c0ee2ac 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/dagcombine-buildvector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/dagcombine-buildvector.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=penryn -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx -o %t
; RUN: grep unpcklpd %t | count 1
; RUN: grep movapd %t | count 1
; RUN: grep movaps %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/dagcombine-cse.ll b/libclamav/c++/llvm/test/CodeGen/X86/dagcombine-cse.ll
index a673ebf..c3c7990 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/dagcombine-cse.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/dagcombine-cse.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 14
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 14
define i32 @t(i8* %ref_frame_ptr, i32 %ref_frame_stride, i32 %idxX, i32 %idxY) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/darwin-bzero.ll b/libclamav/c++/llvm/test/CodeGen/X86/darwin-bzero.ll
index c292140..a3c1e6f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/darwin-bzero.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/darwin-bzero.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin10 | grep __bzero
+; RUN: llc < %s -mtriple=i386-apple-darwin10 | grep __bzero
declare void @llvm.memset.i32(i8*, i8, i32, i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/darwin-no-dead-strip.ll b/libclamav/c++/llvm/test/CodeGen/X86/darwin-no-dead-strip.ll
index 63325b7..452d1f8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/darwin-no-dead-strip.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/darwin-no-dead-strip.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep no_dead_strip
+; RUN: llc < %s | grep no_dead_strip
target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin8.7.2"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/darwin-quote.ll b/libclamav/c++/llvm/test/CodeGen/X86/darwin-quote.ll
new file mode 100644
index 0000000..8fddc11
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/darwin-quote.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
+
+
+define internal i64 @baz() nounwind {
+ %tmp = load i64* @"+x"
+ ret i64 %tmp
+; CHECK: _baz:
+; CHECK: movl "L_+x$non_lazy_ptr", %ecx
+}
+
+
+@"+x" = external global i64
+
+; CHECK: "L_+x$non_lazy_ptr":
+; CHECK: .indirect_symbol "_+x"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/darwin-stub.ll b/libclamav/c++/llvm/test/CodeGen/X86/darwin-stub.ll
index 79eb31a..b4d2e1a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/darwin-stub.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/darwin-stub.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep stub
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | not grep stub
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep stub
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | not grep stub
@"\01LC" = internal constant [13 x i8] c"Hello World!\00" ; <[13 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/div_const.ll b/libclamav/c++/llvm/test/CodeGen/X86/div_const.ll
index aa690f7..f0ada41 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/div_const.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/div_const.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep 365384439
+; RUN: llc < %s -march=x86 | grep 365384439
define i32 @f9188_mul365384439_shift27(i32 %A) {
%tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/divrem.ll b/libclamav/c++/llvm/test/CodeGen/X86/divrem.ll
index a611edd..e86b52f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/divrem.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/divrem.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep div | count 8
+; RUN: llc < %s -march=x86-64 | grep div | count 8
define void @si64(i64 %x, i64 %y, i64* %p, i64* %q) {
%r = sdiv i64 %x, %y
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/dll-linkage.ll b/libclamav/c++/llvm/test/CodeGen/X86/dll-linkage.ll
index a6b3073..c634c7e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/dll-linkage.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/dll-linkage.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-pc-mingw32 | FileCheck %s
+; RUN: llc < %s -mtriple=i386-pc-mingw32 | FileCheck %s
declare dllimport void @foo()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/dollar-name.ll b/libclamav/c++/llvm/test/CodeGen/X86/dollar-name.ll
index 885700e..3b26319 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/dollar-name.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/dollar-name.ll
@@ -1,12 +1,13 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux | grep {(\$bar)} | count 1
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux | grep {(\$qux)} | count 1
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux | grep {(\$hen)} | count 1
+; RUN: llc < %s -march=x86 -mtriple=i386-linux | FileCheck %s
; PR1339
@"$bar" = global i32 zeroinitializer
@"$qux" = external global i32
define i32 @"$foo"() nounwind {
+; CHECK: movl ($bar),
+; CHECK: addl ($qux),
+; CHECK: call ($hen)
%m = load i32* @"$bar"
%n = load i32* @"$qux"
%t = add i32 %m, %n
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/dyn-stackalloc.ll b/libclamav/c++/llvm/test/CodeGen/X86/dyn-stackalloc.ll
index 049a32c..1df0920 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/dyn-stackalloc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/dyn-stackalloc.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=x86 | not egrep {\\\$4294967289|-7\\(}
-; RUN: llvm-as < %s | llc -march=x86 | egrep {\\\$4294967280|-16\\(}
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {\\-16}
+; RUN: llc < %s -march=x86 | not egrep {\\\$4294967289|-7}
+; RUN: llc < %s -march=x86 | egrep {\\\$4294967280|-16}
+; RUN: llc < %s -march=x86-64 | grep {\\-16}
-define void @t() {
+define void @t() nounwind {
A:
br label %entry
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/empty-struct-return-type.ll b/libclamav/c++/llvm/test/CodeGen/X86/empty-struct-return-type.ll
index 3dd9b11..34cd5d9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/empty-struct-return-type.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/empty-struct-return-type.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep call
+; RUN: llc < %s -march=x86-64 | grep call
; PR4688
; Return types can be empty structs, which can be awkward.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/epilogue.ll b/libclamav/c++/llvm/test/CodeGen/X86/epilogue.ll
index 5a378e1..52dcb61 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/epilogue.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/epilogue.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep lea
-; RUN: llvm-as < %s | llc -march=x86 | grep {movl %ebp}
+; RUN: llc < %s -march=x86 | not grep lea
+; RUN: llc < %s -march=x86 | grep {movl %ebp}
declare void @bar(<2 x i64>* %n)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/extend.ll b/libclamav/c++/llvm/test/CodeGen/X86/extend.ll
index a54b6f1..9553b1b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/extend.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/extend.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | grep movzx | count 1
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | grep movsx | count 1
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | grep movzx | count 1
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | grep movsx | count 1
@G1 = internal global i8 0 ; <i8*> [#uses=1]
@G2 = internal global i8 0 ; <i8*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/extern_weak.ll b/libclamav/c++/llvm/test/CodeGen/X86/extern_weak.ll
index 0cc5630..01e32aa 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/extern_weak.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/extern_weak.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | grep weak_reference | count 2
+; RUN: llc < %s -mtriple=i686-apple-darwin | grep weak_reference | count 2
@Y = global i32 (i8*)* @X ; <i32 (i8*)**> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/extmul128.ll b/libclamav/c++/llvm/test/CodeGen/X86/extmul128.ll
index df48765..9b59829 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/extmul128.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/extmul128.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep mul | count 2
+; RUN: llc < %s -march=x86-64 | grep mul | count 2
define i128 @i64_sext_i128(i64 %a, i64 %b) {
%aa = sext i64 %a to i128
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/extmul64.ll b/libclamav/c++/llvm/test/CodeGen/X86/extmul64.ll
index 635da48..9e20ded 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/extmul64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/extmul64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mul | count 2
+; RUN: llc < %s -march=x86 | grep mul | count 2
define i64 @i32_sext_i64(i32 %a, i32 %b) {
%aa = sext i32 %a to i64
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/extract-combine.ll b/libclamav/c++/llvm/test/CodeGen/X86/extract-combine.ll
index 95cd8f2..2040e87 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/extract-combine.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/extract-combine.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mcpu=core2 -o %t
+; RUN: llc < %s -march=x86-64 -mcpu=core2 -o %t
; RUN: not grep unpcklps %t
define i32 @foo() nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/extract-extract.ll b/libclamav/c++/llvm/test/CodeGen/X86/extract-extract.ll
index 1e0ce9a..ad79ab9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/extract-extract.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/extract-extract.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 >/dev/null
+; RUN: llc < %s -march=x86 >/dev/null
; PR4699
; Handle this extractvalue-of-extractvalue case without getting in
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/extractelement-from-arg.ll b/libclamav/c++/llvm/test/CodeGen/X86/extractelement-from-arg.ll
index 44704b6..4ea37f0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/extractelement-from-arg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/extractelement-from-arg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s -o - | llc -march=x86-64 -mattr=+sse2
+; RUN: llc < %s -march=x86-64 -mattr=+sse2
define void @test(float* %R, <4 x float> %X) nounwind {
%tmp = extractelement <4 x float> %X, i32 3
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/extractelement-load.ll b/libclamav/c++/llvm/test/CodeGen/X86/extractelement-load.ll
index 601690e..ee57d9b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/extractelement-load.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/extractelement-load.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as %s -o - | llc -march=x86 -mattr=+sse2 -mcpu=yonah | not grep movd
-; RUN: llvm-as %s -o - | llc -march=x86-64 -mattr=+sse2 -mcpu=core2 | not grep movd
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | not grep movd
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | not grep movd
define i32 @t(<2 x i64>* %val) nounwind {
%tmp2 = load <2 x i64>* %val, align 16 ; <<2 x i64>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/extractelement-shuffle.ll b/libclamav/c++/llvm/test/CodeGen/X86/extractelement-shuffle.ll
index b00c8e4..12a2ef3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/extractelement-shuffle.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/extractelement-shuffle.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; Examples that exhibits a bug in DAGCombine. The case is triggered by the
; following program. The bug is DAGCombine assumes that the bit convert
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/extractps.ll b/libclamav/c++/llvm/test/CodeGen/X86/extractps.ll
index 484d2c4..14778f0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/extractps.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/extractps.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=penryn > %t
+; RUN: llc < %s -march=x86 -mcpu=penryn > %t
; RUN: not grep movd %t
; RUN: grep {movss %xmm} %t | count 1
; RUN: grep {extractps \\\$1, %xmm0, } %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fabs.ll b/libclamav/c++/llvm/test/CodeGen/X86/fabs.ll
index 7ac8e04..54947c3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fabs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fabs.ll
@@ -1,8 +1,7 @@
; Make sure this testcase codegens to the fabs instruction, not a call to fabsf
-; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2,-sse3,-sse | grep fabs\$ | \
+; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fabs\$ | \
; RUN: count 2
-; RUN: llvm-as < %s | \
-; RUN: llc -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
+; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
; RUN: grep fabs\$ | count 3
declare float @fabsf(float)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-callee-pops.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-callee-pops.ll
index 941f708..5e88ed7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-callee-pops.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-callee-pops.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=x86 -x86-asm-syntax=intel -mcpu=yonah | grep {ret 20}
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=yonah | grep {ret 20}
; Check that a fastcc function pops its stack variables before returning.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-merge-stack-adj.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
index 3f3aa46..e151821 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {add ESP, 8}
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-pass-in-regs.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-pass-in-regs.ll
index c8621a7..fe96c0c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-pass-in-regs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-cc-pass-in-regs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {mov EDX, 1}
; check that fastcc is passing stuff in regs.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-bail.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-bail.ll
index fb4f37e..9072c5c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-bail.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-bail.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -O0
+; RUN: llc < %s -march=x86 -O0
; This file is for regression tests for cases where FastISel needs
; to gracefully bail out and let SelectionDAGISel take over.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-bc.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-bc.ll
index c713387..f2696ce 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-bc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-bc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -O0 -march=x86-64 -mattr=+mmx | FileCheck %s
+; RUN: llc < %s -O0 -march=x86-64 -mattr=+mmx | FileCheck %s
; PR4684
target datalayout =
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-call.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-call.ll
index 9945746..5fcdbbb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-call.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-call.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast-isel -march=x86 | grep and
+; RUN: llc < %s -fast-isel -march=x86 | grep and
define i32 @t() nounwind {
tak:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-constpool.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-constpool.ll
index ac2595a..84d10f3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-constpool.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-constpool.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast-isel | grep {LCPI1_0(%rip)}
+; RUN: llc < %s -fast-isel | grep {LCPI1_0(%rip)}
; Make sure fast isel uses rip-relative addressing when required.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin9.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-fneg.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-fneg.ll
new file mode 100644
index 0000000..5ffd48b
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-fneg.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86-64 | FileCheck %s
+; RUN: llc < %s -fast-isel -march=x86 -mattr=+sse2 | grep xor | count 2
+
+; CHECK: doo:
+; CHECK: xor
+define double @doo(double %x) nounwind {
+ %y = fsub double -0.0, %x
+ ret double %y
+}
+
+; CHECK: foo:
+; CHECK: xor
+define float @foo(float %x) nounwind {
+ %y = fsub float -0.0, %x
+ ret float %y
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-gep-sext.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-gep-sext.ll
deleted file mode 100644
index 4e988f5..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-gep-sext.ll
+++ /dev/null
@@ -1,17 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -O0 | grep movslq
-; RUN: llvm-as < %s | llc -march=x86 -O0
-; PR3181
-
-; GEP indices are interpreted as signed integers, so they
-; should be sign-extended to 64 bits on 64-bit targets.
-
-define i32 @foo(i32 %t3, i32* %t1) nounwind {
- %t9 = getelementptr i32* %t1, i32 %t3 ; <i32*> [#uses=1]
- %t15 = load i32* %t9 ; <i32> [#uses=1]
- ret i32 %t15
-}
-define i32 @bar(i64 %t3, i32* %t1) nounwind {
- %t9 = getelementptr i32* %t1, i64 %t3 ; <i32*> [#uses=1]
- %t15 = load i32* %t9 ; <i32> [#uses=1]
- ret i32 %t15
-}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-gep.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-gep.ll
new file mode 100644
index 0000000..5b8acec
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-gep.ll
@@ -0,0 +1,53 @@
+; RUN: llc < %s -march=x86-64 -O0 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -march=x86 -O0 | FileCheck %s --check-prefix=X32
+
+; GEP indices are interpreted as signed integers, so they
+; should be sign-extended to 64 bits on 64-bit targets.
+; PR3181
+define i32 @test1(i32 %t3, i32* %t1) nounwind {
+ %t9 = getelementptr i32* %t1, i32 %t3 ; <i32*> [#uses=1]
+ %t15 = load i32* %t9 ; <i32> [#uses=1]
+ ret i32 %t15
+; X32: test1:
+; X32: movl (%ecx,%eax,4), %eax
+; X32: ret
+
+; X64: test1:
+; X64: movslq %edi, %rax
+; X64: movl (%rsi,%rax,4), %eax
+; X64: ret
+
+}
+define i32 @test2(i64 %t3, i32* %t1) nounwind {
+ %t9 = getelementptr i32* %t1, i64 %t3 ; <i32*> [#uses=1]
+ %t15 = load i32* %t9 ; <i32> [#uses=1]
+ ret i32 %t15
+; X32: test2:
+; X32: movl (%eax,%ecx,4), %eax
+; X32: ret
+
+; X64: test2:
+; X64: movl (%rsi,%rdi,4), %eax
+; X64: ret
+}
+
+
+
+; PR4984
+define i8 @test3(i8* %start) nounwind {
+entry:
+ %A = getelementptr i8* %start, i64 -2 ; <i8*> [#uses=1]
+ %B = load i8* %A, align 1 ; <i8> [#uses=1]
+ ret i8 %B
+
+
+; X32: test3:
+; X32: movl 4(%esp), %eax
+; X32: movb -2(%eax), %al
+; X32: ret
+
+; X64: test3:
+; X64: movb -2(%rdi), %al
+; X64: ret
+
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-gv.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-gv.ll
index b2f8850..34f8b38 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-gv.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-gv.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast-isel | grep {_kill at GOTPCREL(%rip)}
+; RUN: llc < %s -fast-isel | grep {_kill at GOTPCREL(%rip)}
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin10.0"
@f = global i8 (...)* @kill ; <i8 (...)**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-i1.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-i1.ll
index e1ff792..d066578 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-i1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-i1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -fast-isel | grep {andb \$1, %}
+; RUN: llc < %s -march=x86 -fast-isel | grep {andb \$1, %}
declare i64 @bar(i64)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-mem.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-mem.ll
index dfee4f2..35ec1e7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-mem.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-mem.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -fast-isel -mtriple=i386-apple-darwin | \
+; RUN: llc < %s -fast-isel -mtriple=i386-apple-darwin | \
; RUN: grep lazy_ptr, | count 2
-; RUN: llvm-as < %s | llc -fast-isel -march=x86 -relocation-model=static | \
+; RUN: llc < %s -fast-isel -march=x86 -relocation-model=static | \
; RUN: grep lea
@src = external global i32
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-phys.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-phys.ll
index 91dcca5..158ef55 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-phys.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-phys.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast-isel -fast-isel-abort -march=x86
+; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86
define i8 @t2(i8 %a, i8 %c) nounwind {
%tmp = shl i8 %a, %c
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-shift-imm.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-shift-imm.ll
index 7d8c9f5..35f7a72 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-shift-imm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-shift-imm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {sarl \$80, %eax}
+; RUN: llc < %s -march=x86 -O0 | grep {sarl \$80, %eax}
; PR3242
define i32 @foo(i32 %x) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-tailcall.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-tailcall.ll
index 6f4d202..c3e527c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-tailcall.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-tailcall.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast-isel -tailcallopt -march=x86 | not grep add
+; RUN: llc < %s -fast-isel -tailcallopt -march=x86 | not grep add
; PR4154
; On x86, -tailcallopt changes the ABI so the caller shouldn't readjust
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-tls.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-tls.ll
index 4dd14e6..a5e6642 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-tls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-tls.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -relocation-model=pic -mtriple=i686-unknown-linux-gnu -fast-isel | grep __tls_get_addr
+; RUN: llc < %s -march=x86 -relocation-model=pic -mtriple=i686-unknown-linux-gnu -fast-isel | grep __tls_get_addr
; PR3654
@v = thread_local global i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-trunc.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-trunc.ll
index 039f114..69b26c5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-trunc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel-trunc.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -fast-isel -fast-isel-abort
-; RUN: llvm-as < %s | llc -march=x86-64 -fast-isel -fast-isel-abort
+; RUN: llc < %s -march=x86 -fast-isel -fast-isel-abort
+; RUN: llc < %s -march=x86-64 -fast-isel -fast-isel-abort
define i8 @t1(i32 %x) signext nounwind {
%tmp1 = trunc i32 %x to i8
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel.ll b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel.ll
index 8d6ddb4..3dcd736 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fast-isel.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fast-isel.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -fast-isel -fast-isel-abort -march=x86 -mattr=sse2
+; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86 -mattr=sse2
; This tests very minimal fast-isel functionality.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fastcall-correct-mangling.ll b/libclamav/c++/llvm/test/CodeGen/X86/fastcall-correct-mangling.ll
index 303fce5..2b48f5f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fastcall-correct-mangling.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fastcall-correct-mangling.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-unknown-mingw32 | \
+; RUN: llc < %s -mtriple=i386-unknown-mingw32 | \
; RUN: grep {@12}
; Check that a fastcall function gets correct mangling
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fastcc-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/fastcc-2.ll
index 40c753e..d044a2a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fastcc-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fastcc-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | grep movsd
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | count 1
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep movsd
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | count 1
define i32 @foo() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fastcc-byval.ll b/libclamav/c++/llvm/test/CodeGen/X86/fastcc-byval.ll
index 94da505..52b3e57 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fastcc-byval.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fastcc-byval.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -tailcallopt=false | grep {movl\[\[:space:\]\]*8(%esp), %eax} | count 2
+; RUN: llc < %s -tailcallopt=false | grep {movl\[\[:space:\]\]*8(%esp), %eax} | count 2
; PR3122
; rdar://6400815
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fastcc-sret.ll b/libclamav/c++/llvm/test/CodeGen/X86/fastcc-sret.ll
index 7fc111b..d457418 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fastcc-sret.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fastcc-sret.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -tailcallopt=false | grep ret | not grep 4
+; RUN: llc < %s -march=x86 -tailcallopt=false | grep ret | not grep 4
%struct.foo = type { [4 x i32] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fastcc.ll b/libclamav/c++/llvm/test/CodeGen/X86/fastcc.ll
index f18f34d..c70005b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fastcc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fastcc.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | grep ecx | grep 0
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | grep xmm0 | grep 8
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | grep ecx | grep 0
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | grep xmm0 | grep 8
@d = external global double ; <double*> [#uses=1]
@c = external global double ; <double*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/field-extract-use-trunc.ll b/libclamav/c++/llvm/test/CodeGen/X86/field-extract-use-trunc.ll
index c4f9587..6020530 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/field-extract-use-trunc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/field-extract-use-trunc.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep sar | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep sar
+; RUN: llc < %s -march=x86 | grep sar | count 1
+; RUN: llc < %s -march=x86-64 | not grep sar
define i32 @test(i32 %f12) {
%tmp7.25 = lshr i32 %f12, 16
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fildll.ll b/libclamav/c++/llvm/test/CodeGen/X86/fildll.ll
index 65944fd..c5a3765 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fildll.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fildll.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=att -mattr=-sse2 | grep fildll | count 2
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att -mattr=-sse2 | grep fildll | count 2
define fastcc double @sint64_to_fp(i64 %X) {
%R = sitofp i64 %X to double ; <double> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fmul-zero.ll b/libclamav/c++/llvm/test/CodeGen/X86/fmul-zero.ll
index 73aa713..03bad65 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fmul-zero.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fmul-zero.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -enable-unsafe-fp-math | not grep mulps
-; RUN: llvm-as < %s | llc -march=x86-64 | grep mulps
+; RUN: llc < %s -march=x86-64 -enable-unsafe-fp-math | not grep mulps
+; RUN: llc < %s -march=x86-64 | grep mulps
define void @test14(<4 x float>*) nounwind {
load <4 x float>* %0, align 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-add.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-add.ll
index 2828ad2..5e80ea5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-add.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-add.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {cmpb \$0, (%r.\*,%r.\*)}
+; RUN: llc < %s -march=x86-64 | grep {cmpb \$0, (%r.\*,%r.\*)}
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin9.6"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-and-shift.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-and-shift.ll
index 705b795..9f79f77 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-and-shift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-and-shift.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep and
+; RUN: llc < %s -march=x86 | not grep and
define i32 @t1(i8* %X, i32 %i) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-call-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-call-2.ll
index 349f986..7a2b038 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-call-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-call-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep mov | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep mov | count 1
@f = external global void ()* ; <void ()**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-call-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-call-3.ll
index 824ae00..337a7ed 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-call-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-call-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep call | grep 560
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep call | grep 560
; rdar://6522427
%"struct.clang::Action" = type { %"struct.clang::ActionBase" }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-call.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-call.ll
index 5399171..603e9ad 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-call.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-call.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep mov
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep mov
+; RUN: llc < %s -march=x86 | not grep mov
+; RUN: llc < %s -march=x86-64 | not grep mov
declare void @bar()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-imm.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-imm.ll
index 1623f31..f1fcbcf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-imm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-imm.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep inc
-; RUN: llvm-as < %s | llc -march=x86 | grep add | grep 4
+; RUN: llc < %s -march=x86 | grep inc
+; RUN: llc < %s -march=x86 | grep add | grep 4
define i32 @test(i32 %X) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-load.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-load.ll
index 6e3da5c..eb182da 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-load.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-load.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
%struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
%struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (...)*, void (...)*, i8*, i8 }
@stmt_obstack = external global %struct.obstack ; <%struct.obstack*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-mul-lohi.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-mul-lohi.ll
index 312427a..0351eca 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-mul-lohi.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-mul-lohi.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep lea
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep lea
+; RUN: llc < %s -march=x86 | not grep lea
+; RUN: llc < %s -march=x86-64 | not grep lea
@B = external global [1000 x i8], align 32
@A = external global [1000 x i8], align 32
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-0.ll
index f558aca..ef5202f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-0.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI1_2 | count 2
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI1_2 | count 2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1
; This testcase shouldn't need to spill the -1 value,
; so it should just use pcmpeqd to materialize an all-ones vector.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-1.ll
index e2141eb..cc4198d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 > %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
; RUN: grep pcmpeqd %t | count 1
; RUN: grep xor %t | count 1
; RUN: not grep LCP %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll
index 2b75781..49f8795 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1
; This testcase should need to spill the -1 value on x86-32,
; so it shouldn't use pcmpeqd to materialize an all-ones vector; it
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fold-sext-trunc.ll b/libclamav/c++/llvm/test/CodeGen/X86/fold-sext-trunc.ll
index 1016b10..2605123 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fold-sext-trunc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fold-sext-trunc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movslq | count 1
+; RUN: llc < %s -march=x86-64 | grep movslq | count 1
; PR4050
type { i64 } ; type %0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp-immediate-shorten.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp-immediate-shorten.ll
index 32ba217..cafc61a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp-immediate-shorten.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp-immediate-shorten.ll
@@ -1,6 +1,6 @@
;; Test that this FP immediate is stored in the constant pool as a float.
-; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2,-sse3 | \
+; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3 | \
; RUN: grep {.long.1123418112}
define double @D() {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp-in-intregs.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp-in-intregs.ll
index 15606c3..08ea77d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp-in-intregs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp-in-intregs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not egrep {\(\(xor\|and\)ps\|movd\)}
+; RUN: llc < %s -march=x86 -mcpu=yonah | not egrep {\(\(xor\|and\)ps\|movd\)}
; These operations should be done in integer registers, eliminating constant
; pool loads, movd's etc.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-2results.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-2results.ll
index f47fd74..321e267 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-2results.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-2results.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep fldz
-; RUN: llvm-as < %s | llc -march=x86-64 | grep fld1
+; RUN: llc < %s -march=x86 | grep fldz
+; RUN: llc < %s -march=x86-64 | grep fld1
; This is basically this code on x86-64:
; _Complex long double test() { return 1.0; }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-O0-crash.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-O0-crash.ll
new file mode 100644
index 0000000..4768ea2
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-O0-crash.ll
@@ -0,0 +1,30 @@
+; RUN: llc %s -O0 -fast-isel -regalloc=local -o -
+; PR4767
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin10"
+
+define void @fn(x86_fp80 %x) nounwind ssp {
+entry:
+ %x.addr = alloca x86_fp80 ; <x86_fp80*> [#uses=5]
+ store x86_fp80 %x, x86_fp80* %x.addr
+ br i1 false, label %cond.true, label %cond.false
+
+cond.true: ; preds = %entry
+ %tmp = load x86_fp80* %x.addr ; <x86_fp80> [#uses=1]
+ %tmp1 = load x86_fp80* %x.addr ; <x86_fp80> [#uses=1]
+ %cmp = fcmp oeq x86_fp80 %tmp, %tmp1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+cond.false: ; preds = %entry
+ %tmp2 = load x86_fp80* %x.addr ; <x86_fp80> [#uses=1]
+ %tmp3 = load x86_fp80* %x.addr ; <x86_fp80> [#uses=1]
+ %cmp4 = fcmp une x86_fp80 %tmp2, %tmp3 ; <i1> [#uses=1]
+ br i1 %cmp4, label %if.then, label %if.end
+
+if.then: ; preds = %cond.false, %cond.true
+ br label %if.end
+
+if.end: ; preds = %if.then, %cond.false, %cond.true
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-compare.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-compare.ll
index 4e61d0f..4bdf459 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-compare.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-compare.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 | \
+; RUN: llc < %s -march=x86 -mcpu=i386 | \
; RUN: grep {fucomi.*st.\[12\]}
; PR1012
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-direct-ret.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-direct-ret.ll
index 78be2a3..5a28bb5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-direct-ret.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-direct-ret.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep fstp
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not grep movsd
+; RUN: llc < %s -march=x86 | not grep fstp
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep movsd
declare double @foo()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret-conv.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret-conv.ll
index 5254e1c..f220b24 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret-conv.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret-conv.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -mcpu=yonah | grep cvtss2sd
-; RUN: llvm-as < %s | llc -mcpu=yonah | grep fstps
-; RUN: llvm-as < %s | llc -mcpu=yonah | not grep cvtsd2ss
+; RUN: llc < %s -mcpu=yonah | grep cvtss2sd
+; RUN: llc < %s -mcpu=yonah | grep fstps
+; RUN: llc < %s -mcpu=yonah | not grep cvtsd2ss
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret-store.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret-store.ll
index 56392de..05dfc54 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret-store.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret-store.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mcpu=yonah | not grep movss
+; RUN: llc < %s -mcpu=yonah | not grep movss
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret.ll
index 3e6ad54..c83a0cb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-ret.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=i686-apple-darwin8 -mcpu=yonah -march=x86 > %t
+; RUN: llc < %s -mtriple=i686-apple-darwin8 -mcpu=yonah -march=x86 > %t
; RUN: grep fldl %t | count 1
; RUN: not grep xmm %t
; RUN: grep {sub.*esp} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-retcopy.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-retcopy.ll
index 997f8df..67dcb18 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-retcopy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-retcopy.ll
@@ -1,5 +1,5 @@
; This should not copy the result of foo into an xmm register.
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah -mtriple=i686-apple-darwin9 | not grep xmm
+; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=i686-apple-darwin9 | not grep xmm
; rdar://5689903
declare double @foo()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-set-st1.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-set-st1.ll
index 00a73ae..894897a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-set-st1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp-stack-set-st1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep fxch | count 2
+; RUN: llc < %s -march=x86 | grep fxch | count 2
define i32 @main() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp2sint.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp2sint.ll
index 80f7efb..1675444 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp2sint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp2sint.ll
@@ -1,6 +1,6 @@
;; LowerFP_TO_SINT should not create a stack object if it's not needed.
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep add
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep add
define i32 @main(i32 %argc, i8** %argv) {
cond_false.i.i.i: ; preds = %bb.i5
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp_constant_op.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp_constant_op.ll
index f2017b9..8e823ed 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp_constant_op.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp_constant_op.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -mcpu=i486 | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=i486 | \
; RUN: grep {fadd\\|fsub\\|fdiv\\|fmul} | not grep -i ST
; Test that the load of the constant is folded into the operation.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp_load_cast_fold.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp_load_cast_fold.ll
index 5452326..a160ac6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp_load_cast_fold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp_load_cast_fold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep fild | not grep ESP
+; RUN: llc < %s -march=x86 | grep fild | not grep ESP
define double @short(i16* %P) {
%V = load i16* %P ; <i16> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fp_load_fold.ll b/libclamav/c++/llvm/test/CodeGen/X86/fp_load_fold.ll
index 655ad3d..0145069 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fp_load_fold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fp_load_fold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: grep -i ST | not grep {fadd\\|fsub\\|fdiv\\|fmul}
; Test that the load of the memory location is folded into the operation.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/fsxor-alignment.ll b/libclamav/c++/llvm/test/CodeGen/X86/fsxor-alignment.ll
index 4d25fca..6a8dbcf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/fsxor-alignment.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/fsxor-alignment.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -enable-unsafe-fp-math | \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -enable-unsafe-fp-math | \
; RUN: grep -v sp | grep xorps | count 2
; Don't fold the incoming stack arguments into the xorps instructions used
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/full-lsr.ll b/libclamav/c++/llvm/test/CodeGen/X86/full-lsr.ll
index 4a85779..68575bc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/full-lsr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/full-lsr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -enable-full-lsr >%t
+; RUN: llc < %s -march=x86 -enable-full-lsr >%t
; RUN: grep {addl \\\$4,} %t | count 3
; RUN: not grep {,%} %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/ga-offset.ll b/libclamav/c++/llvm/test/CodeGen/X86/ga-offset.ll
index aaa2f84..9f6d3f7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/ga-offset.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/ga-offset.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: not grep lea %t
; RUN: not grep add %t
; RUN: grep mov %t | count 1
-; RUN: llvm-as < %s | llc -mtriple=x86_64-linux -relocation-model=static > %t
+; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static > %t
; RUN: not grep lea %t
; RUN: not grep add %t
; RUN: grep mov %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/global-sections-tls.ll b/libclamav/c++/llvm/test/CodeGen/X86/global-sections-tls.ll
index a80cf32..2c23030 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/global-sections-tls.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/global-sections-tls.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX
; PR4639
@G1 = internal thread_local global i32 0 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/global-sections.ll b/libclamav/c++/llvm/test/CodeGen/X86/global-sections.ll
index a3eaa5f..38948a7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/global-sections.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/global-sections.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9.7 | FileCheck %s -check-prefix=DARWIN
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=i386-apple-darwin9.7 | FileCheck %s -check-prefix=DARWIN
; int G1;
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/h-register-addressing-32.ll b/libclamav/c++/llvm/test/CodeGen/X86/h-register-addressing-32.ll
index 41d9128..76ffd66 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/h-register-addressing-32.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/h-register-addressing-32.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {movzbl %\[abcd\]h,} | count 7
+; RUN: llc < %s -march=x86 | grep {movzbl %\[abcd\]h,} | count 7
; Use h-register extract and zero-extend.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/h-register-addressing-64.ll b/libclamav/c++/llvm/test/CodeGen/X86/h-register-addressing-64.ll
index b38e0e4..98817f3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/h-register-addressing-64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/h-register-addressing-64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movzbl %\[abcd\]h,} | count 7
+; RUN: llc < %s -march=x86-64 | grep {movzbl %\[abcd\]h,} | count 7
; Use h-register extract and zero-extend.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/h-register-store.ll b/libclamav/c++/llvm/test/CodeGen/X86/h-register-store.ll
index e867242..d30e6b3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/h-register-store.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/h-register-store.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep mov %t | count 6
; RUN: grep {movb %ah, (%rsi)} %t | count 3
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: grep mov %t | count 3
; RUN: grep {movb %ah, (%e} %t | count 3
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/h-registers-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/h-registers-0.ll
index 2777be9..878fd93 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/h-registers-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/h-registers-0.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movzbl %\[abcd\]h,} | count 4
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86-64 | grep {movzbl %\[abcd\]h,} | count 4
+; RUN: llc < %s -march=x86 > %t
; RUN: grep {incb %ah} %t | count 3
; RUN: grep {movzbl %ah,} %t | count 3
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/h-registers-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/h-registers-1.ll
index 789f3dd..e97ebab 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/h-registers-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/h-registers-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep {movzbl %\[abcd\]h,} %t | count 8
; RUN: grep {%\[abcd\]h} %t | not grep {%r\[\[:digit:\]\]*d}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/h-registers-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/h-registers-2.ll
index 5541583..16e13f8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/h-registers-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/h-registers-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: grep {movzbl %\[abcd\]h,} %t | count 1
; RUN: grep {shll \$3,} %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/h-registers-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/h-registers-3.ll
index d353a22..8a0b07b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/h-registers-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/h-registers-3.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 1
+; RUN: llc < %s -march=x86 | grep mov | count 1
+; RUN: llc < %s -march=x86-64 | grep mov | count 1
define zeroext i8 @foo() nounwind ssp {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-2.ll
index e000547..74554d1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | grep mov | count 1
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin9 | not grep GOT
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | grep mov | count 1
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | not grep GOT
@x = weak hidden global i32 0 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-3.ll
index 81dc76e..4be881e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-3.ll
@@ -1,13 +1,17 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | grep mov | count 3
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | grep non_lazy_ptr
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | grep long | count 2
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin9 | not grep GOT
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | FileCheck %s -check-prefix=X64
@x = external hidden global i32 ; <i32*> [#uses=1]
@y = extern_weak hidden global i32 ; <i32*> [#uses=1]
define i32 @t() nounwind readonly {
entry:
+; X32: _t:
+; X32: movl _y, %eax
+
+; X64: _t:
+; X64: movl _y(%rip), %eax
+
%0 = load i32* @x, align 4 ; <i32> [#uses=1]
%1 = load i32* @y, align 4 ; <i32> [#uses=1]
%2 = add i32 %1, %0 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-4.ll
index e6936de..a8aede5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis-4.ll
@@ -1,11 +1,12 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | grep non_lazy_ptr
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | grep long
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | grep comm
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s
@x = common hidden global i32 0 ; <i32*> [#uses=1]
define i32 @t() nounwind readonly {
entry:
+; CHECK: t:
+; CHECK: movl _x, %eax
+; CHECK: .comm _x,4
%0 = load i32* @x, align 4 ; <i32> [#uses=1]
ret i32 %0
}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis.ll b/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis.ll
index 058850c..a948bdf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/hidden-vis.ll
@@ -1,20 +1,24 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu | \
-; RUN: grep .hidden | count 2
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin8.8.0 | \
-; RUN: grep .private_extern | count 2
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=i686-apple-darwin8 | FileCheck %s -check-prefix=DARWIN
-%struct.Person = type { i32 }
@a = hidden global i32 0
@b = external global i32
+define weak hidden void @t1() nounwind {
+; LINUX: .hidden t1
+; LINUX: t1:
-define weak hidden void @_ZN6Person13privateMethodEv(%struct.Person* %this) {
+; DARWIN: .private_extern _t1
+; DARWIN: t1:
ret void
}
-declare void @function(i32)
+define weak void @t2() nounwind {
+; LINUX: t2:
+; LINUX: .hidden a
-define weak void @_ZN6PersonC1Ei(%struct.Person* %this, i32 %_c) {
+; DARWIN: t2:
+; DARWIN: .private_extern _a
ret void
}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/i128-and-beyond.ll b/libclamav/c++/llvm/test/CodeGen/X86/i128-and-beyond.ll
index db94b0e..907a6b8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/i128-and-beyond.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/i128-and-beyond.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-pc-linux-gnu | grep 18446744073709551615 | count 14
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep 18446744073709551615 | count 14
; These static initializers are too big to hand off to assemblers
; as monolithic blobs.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/i128-immediate.ll b/libclamav/c++/llvm/test/CodeGen/X86/i128-immediate.ll
index 6939933..c47569e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/i128-immediate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/i128-immediate.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movq | count 2
+; RUN: llc < %s -march=x86-64 | grep movq | count 2
define i128 @__addvti3() {
ret i128 -1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/i128-mul.ll b/libclamav/c++/llvm/test/CodeGen/X86/i128-mul.ll
index f8c732e..e9d30d6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/i128-mul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/i128-mul.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
; PR1198
define i64 @foo(i64 %x, i64 %y) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/i128-ret.ll b/libclamav/c++/llvm/test/CodeGen/X86/i128-ret.ll
index 179a013..277f428 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/i128-ret.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/i128-ret.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movq 8(%rdi), %rdx}
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movq (%rdi), %rax}
+; RUN: llc < %s -march=x86-64 | grep {movq 8(%rdi), %rdx}
+; RUN: llc < %s -march=x86-64 | grep {movq (%rdi), %rax}
define i128 @test(i128 *%P) {
%A = load i128* %P
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/i256-add.ll b/libclamav/c++/llvm/test/CodeGen/X86/i256-add.ll
index 280ed6b..5a7a7a7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/i256-add.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/i256-add.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: grep adcl %t | count 7
; RUN: grep sbbl %t | count 7
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/i2k.ll b/libclamav/c++/llvm/test/CodeGen/X86/i2k.ll
index 712302d..6116c2e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/i2k.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/i2k.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define void @foo(i2011* %x, i2011* %y, i2011* %p) nounwind {
%a = load i2011* %x
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/i64-mem-copy.ll b/libclamav/c++/llvm/test/CodeGen/X86/i64-mem-copy.ll
index 0d2b29c..847e209 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/i64-mem-copy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/i64-mem-copy.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movq.*(%rsi), %rax}
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {movsd.*(%eax),}
+; RUN: llc < %s -march=x86-64 | grep {movq.*(%rsi), %rax}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movsd.*(%eax),}
; Uses movsd to load / store i64 values if sse2 is available.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/iabs.ll b/libclamav/c++/llvm/test/CodeGen/X86/iabs.ll
index ca751ae..6a79ee8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/iabs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/iabs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -stats |& \
+; RUN: llc < %s -march=x86-64 -stats |& \
; RUN: grep {6 .*Number of machine instrs printed}
;; Integer absolute value, should produce something at least as good as:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/illegal-asm.ll b/libclamav/c++/llvm/test/CodeGen/X86/illegal-asm.ll
index 03cc507..43128dc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/illegal-asm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/illegal-asm.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -disable-fp-elim
-; RUN: llvm-as < %s | llc -mtriple=i386-linux -disable-fp-elim
+; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim
+; RUN: llc < %s -mtriple=i386-linux -disable-fp-elim
; XFAIL: *
; Expected to run out of registers during allocation.
; PR3864
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/illegal-insert.ll b/libclamav/c++/llvm/test/CodeGen/X86/illegal-insert.ll
index 59773b2..dbf1b14 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/illegal-insert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/illegal-insert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s -o - | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
define <4 x double> @foo0(<4 x double> %t) {
%r = insertelement <4 x double> %t, double 2.3, i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/illegal-vector-args-return.ll b/libclamav/c++/llvm/test/CodeGen/X86/illegal-vector-args-return.ll
index 5ed6ddb..cecf77a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/illegal-vector-args-return.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/illegal-vector-args-return.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {mulpd %xmm3, %xmm1}
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {mulpd %xmm2, %xmm0}
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {addps %xmm3, %xmm1}
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {addps %xmm2, %xmm0}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {mulpd %xmm3, %xmm1}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {mulpd %xmm2, %xmm0}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {addps %xmm3, %xmm1}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {addps %xmm2, %xmm0}
define <4 x double> @foo(<4 x double> %x, <4 x double> %z) {
%y = fmul <4 x double> %x, %z
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/imp-def-copies.ll b/libclamav/c++/llvm/test/CodeGen/X86/imp-def-copies.ll
index 3d2f656..9117840 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/imp-def-copies.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/imp-def-copies.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep mov
+; RUN: llc < %s -march=x86 | not grep mov
%struct.active_line = type { %struct.gs_fixed_point, %struct.gs_fixed_point, i32, i32, i32, %struct.line_segment*, i32, i16, i16, %struct.active_line*, %struct.active_line* }
%struct.gs_fixed_point = type { i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/imul-lea-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/imul-lea-2.ll
index 0a2df1c..1cb54b3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/imul-lea-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/imul-lea-2.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep lea | count 3
-; RUN: llvm-as < %s | llc -march=x86-64 | grep shl | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep imul
+; RUN: llc < %s -march=x86-64 | grep lea | count 3
+; RUN: llc < %s -march=x86-64 | grep shl | count 1
+; RUN: llc < %s -march=x86-64 | not grep imul
define i64 @t1(i64 %a) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/imul-lea.ll b/libclamav/c++/llvm/test/CodeGen/X86/imul-lea.ll
index 6403a26..4e8e2af 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/imul-lea.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/imul-lea.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep lea
+; RUN: llc < %s -march=x86 | grep lea
declare i32 @foo()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-2addr.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-2addr.ll
index 6196294..4a2c7fc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-2addr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-2addr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep movq
+; RUN: llc < %s -march=x86-64 | not grep movq
define i64 @t(i64 %a, i64 %b) nounwind ssp {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-flag-clobber.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-flag-clobber.ll
index 3c536b7..51ea843 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-flag-clobber.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-flag-clobber.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | %prcontext test 1 | grep j
+; RUN: llc -march=x86-64 < %s | FileCheck %s
; PR3701
define i64 @t(i64* %arg) nounwind {
@@ -7,6 +7,8 @@ define i64 @t(i64* %arg) nounwind {
; <label>:1 ; preds = %0
%2 = icmp eq i64* null, %arg ; <i1> [#uses=1]
%3 = tail call i64* asm sideeffect "movl %fs:0,$0", "=r,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%struct.thread*> [#uses=0]
+; CHECK: test
+; CHECK-NEXT: j
br i1 %2, label %4, label %5
; <label>:4 ; preds = %1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack.ll
index 31d94d8..09b0929 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define x86_fp80 @test1() {
%tmp85 = call x86_fp80 asm sideeffect "fld0", "={st(0)}"()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack2.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack2.ll
index 9685618..ffa6ee6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: grep {fld %%st(0)} %t
; PR4185
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack3.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack3.ll
index ac89a1d..17945fe 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: grep {fld %%st(0)} %t
; PR4459
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack4.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack4.ll
index c9122fa..bae2970 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR4484
declare x86_fp80 @ceil()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack5.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack5.ll
index 64f3788..8b219cf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-fpstack5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR4485
define void @test(x86_fp80* %a) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-modifier-n.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-modifier-n.ll
index 97eac38..5e76b6c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-modifier-n.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-modifier-n.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep { 37}
+; RUN: llc < %s -march=x86 | grep { 37}
; rdar://7008959
define void @bork() nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-mrv.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-mrv.ll
index ca39c12..78d7e77 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-mrv.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-mrv.ll
@@ -1,8 +1,8 @@
; PR2094
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movslq
-; RUN: llvm-as < %s | llc -march=x86-64 | grep addps
-; RUN: llvm-as < %s | llc -march=x86-64 | grep paddd
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep movq
+; RUN: llc < %s -march=x86-64 | grep movslq
+; RUN: llc < %s -march=x86-64 | grep addps
+; RUN: llc < %s -march=x86-64 | grep paddd
+; RUN: llc < %s -march=x86-64 | not grep movq
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-out-regs.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-out-regs.ll
index 01f1397..46966f5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-out-regs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-out-regs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-unknown-linux-gnu
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu
; PR3391
@pci_indirect = external global { } ; <{ }*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-pic.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-pic.ll
index 04ad48d..0b5ff08 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-pic.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-pic.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -relocation-model=pic | grep lea
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -relocation-model=pic | grep call
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | grep lea
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | grep call
@main_q = internal global i8* null ; <i8**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-q-regs.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-q-regs.ll
index 19df81b..ab44206 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-q-regs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-q-regs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
; rdar://7066579
type { i64, i64, i64, i64, i64 } ; type %0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-tied.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-tied.ll
index 9cc944b..1f4a13f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-tied.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-tied.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 -O0 | grep {movl %edx, 12(%esp)} | count 2
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 | grep {movl %edx, 12(%esp)} | count 2
; rdar://6992609
target triple = "i386-apple-darwin9.0"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-x-scalar.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-x-scalar.ll
index aafbbd1..5a9628b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-x-scalar.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm-x-scalar.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah
+; RUN: llc < %s -march=x86 -mcpu=yonah
define void @test1() {
tail call void asm sideeffect "ucomiss $0", "x"( float 0x41E0000000000000)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm.ll b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm.ll
index 02988fc..c66d7a8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/inline-asm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/inline-asm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define i32 @test1() nounwind {
; Dest is AX, dest type = i32.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll
index a0347ea..2243f93 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 3
+; RUN: llc < %s -march=x86 | grep mov | count 3
define fastcc i32 @sqlite3ExprResolveNames() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-2.ll
index 5c0b0d3..f2c9cc7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep movw
+; RUN: llc < %s -march=x86-64 | not grep movw
define i16 @test5(i16 %f12) nounwind {
%f11 = shl i16 %f12, 2 ; <i16> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll
index 3213723..e443085 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 11
+; RUN: llc < %s -march=x86-64 | grep mov | count 11
%struct.COMPOSITE = type { i8, i16, i16 }
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/insertelement-copytoregs.ll b/libclamav/c++/llvm/test/CodeGen/X86/insertelement-copytoregs.ll
index 0eef517..34a29ca 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/insertelement-copytoregs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/insertelement-copytoregs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep -v IMPLICIT_DEF
+; RUN: llc < %s -march=x86-64 | grep -v IMPLICIT_DEF
define void @foo(<2 x float>* %p) {
%t = insertelement <2 x float> undef, float 0.0, i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/insertelement-legalize.ll b/libclamav/c++/llvm/test/CodeGen/X86/insertelement-legalize.ll
index 95e17b4..18aade2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/insertelement-legalize.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/insertelement-legalize.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -disable-mmx
+; RUN: llc < %s -march=x86 -disable-mmx
; Test to check that we properly legalize an insert vector element
define void @test(<2 x i64> %val, <2 x i64>* %dst, i64 %x) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/invalid-shift-immediate.ll b/libclamav/c++/llvm/test/CodeGen/X86/invalid-shift-immediate.ll
index 5c47f5e..77a9f7e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/invalid-shift-immediate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/invalid-shift-immediate.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR2098
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/isel-sink.ll b/libclamav/c++/llvm/test/CodeGen/X86/isel-sink.ll
index 4e68b77..0f94b23 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/isel-sink.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/isel-sink.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep lea
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-apple-darwin8 | \
+; RUN: llc < %s -march=x86 | not grep lea
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin8 | \
; RUN: grep {movl \$4, (.*,.*,4)}
define i32 @test(i32* %X, i32 %B) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/isel-sink2.ll b/libclamav/c++/llvm/test/CodeGen/X86/isel-sink2.ll
index 9d9c747..5ed0e00 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/isel-sink2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/isel-sink2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: grep {movb.7(%...)} %t
; RUN: not grep leal %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/isel-sink3.ll b/libclamav/c++/llvm/test/CodeGen/X86/isel-sink3.ll
index 4e678c4..8d3d97a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/isel-sink3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/isel-sink3.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc | grep {addl.\$4, %ecx}
-; RUN: llvm-as < %s | llc | not grep leal
+; RUN: llc < %s | grep {addl.\$4, %ecx}
+; RUN: llc < %s | not grep leal
; this should not sink %1 into bb1, that would increase reg pressure.
; rdar://6399178
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/isint.ll b/libclamav/c++/llvm/test/CodeGen/X86/isint.ll
index 7acc5cc..507a328 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/isint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/isint.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 > %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
; RUN: not grep cmp %t
; RUN: not grep xor %t
; RUN: grep jne %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/isnan.ll b/libclamav/c++/llvm/test/CodeGen/X86/isnan.ll
index 65916ff..4d465c0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/isnan.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/isnan.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep call
+; RUN: llc < %s -march=x86 | not grep call
declare i1 @llvm.isunordered.f64(double)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/isnan2.ll b/libclamav/c++/llvm/test/CodeGen/X86/isnan2.ll
index 18fe29a..7753346 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/isnan2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/isnan2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not grep pxor
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep pxor
; This should not need to materialize 0.0 to evaluate the condition.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/ispositive.ll b/libclamav/c++/llvm/test/CodeGen/X86/ispositive.ll
index 3799b9c..8adf723 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/ispositive.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/ispositive.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {shrl.*31}
+; RUN: llc < %s -march=x86 | grep {shrl.*31}
define i32 @test1(i32 %X) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/iv-users-in-other-loops.ll b/libclamav/c++/llvm/test/CodeGen/X86/iv-users-in-other-loops.ll
index f97ac4d..c695c29 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/iv-users-in-other-loops.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/iv-users-in-other-loops.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -o %t
+; RUN: llc < %s -march=x86-64 -o %t
; RUN: grep inc %t | count 1
; RUN: grep dec %t | count 2
; RUN: grep addq %t | count 13
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/jump_sign.ll b/libclamav/c++/llvm/test/CodeGen/X86/jump_sign.ll
index cb7d627..5e8e162 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/jump_sign.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/jump_sign.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep jns
+; RUN: llc < %s -march=x86 | grep jns
define i32 @f(i32 %X) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/ldzero.ll b/libclamav/c++/llvm/test/CodeGen/X86/ldzero.ll
index 2db78a2..dab04bc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/ldzero.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/ldzero.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; verify PR 1700 is still fixed
; ModuleID = 'hh.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/lea-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/lea-2.ll
index a33b71c..6930350 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/lea-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/lea-2.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {lea EAX, DWORD PTR \\\[... + 4\\*... - 5\\\]}
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: not grep add
define i32 @test1(i32 %A, i32 %B) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/lea-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/lea-3.ll
index 39122bb..44413d6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/lea-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/lea-3.ll
@@ -1,10 +1,10 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {leal (%rdi,%rdi,2), %eax}
+; RUN: llc < %s -march=x86-64 | grep {leal (%rdi,%rdi,2), %eax}
define i32 @test(i32 %a) {
%tmp2 = mul i32 %a, 3 ; <i32> [#uses=1]
ret i32 %tmp2
}
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {leaq (,%rdi,4), %rax}
+; RUN: llc < %s -march=x86-64 | grep {leaq (,%rdi,4), %rax}
define i64 @test2(i64 %a) {
%tmp2 = shl i64 %a, 2
%tmp3 = or i64 %tmp2, %a
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/lea-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/lea-4.ll
index 8f0835f..2171204 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/lea-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/lea-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep lea | count 2
+; RUN: llc < %s -march=x86-64 | grep lea | count 2
define zeroext i16 @t1(i32 %on_off) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/lea-neg.ll b/libclamav/c++/llvm/test/CodeGen/X86/lea-neg.ll
deleted file mode 100644
index a559e15..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/lea-neg.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
-; RUN: grep negl %t | count 1
-; RUN: not grep {sub\[bwlq\]} %t
-; RUN: grep mov %t | count 1
-; RUN: grep {leal -4(} %t | count 1
-
-; ISel the add of -4 with a neg and use an lea for the rest of the
-; arithemtic.
-
-define i32 @test(i32 %x_offs) nounwind readnone {
-entry:
- %t0 = icmp sgt i32 %x_offs, 4 ; <i1> [#uses=1]
- br i1 %t0, label %bb.nph, label %bb2
-
-bb.nph: ; preds = %entry
- %tmp = add i32 %x_offs, -5 ; <i32> [#uses=1]
- %tmp6 = lshr i32 %tmp, 2 ; <i32> [#uses=1]
- %tmp7 = mul i32 %tmp6, -4 ; <i32> [#uses=1]
- %tmp8 = add i32 %tmp7, %x_offs ; <i32> [#uses=1]
- %tmp9 = add i32 %tmp8, -4 ; <i32> [#uses=1]
- ret i32 %tmp9
-
-bb2: ; preds = %entry
- ret i32 %x_offs
-}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/lea-recursion.ll b/libclamav/c++/llvm/test/CodeGen/X86/lea-recursion.ll
index 390e35a..3f32fd2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/lea-recursion.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/lea-recursion.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep lea | count 12
+; RUN: llc < %s -march=x86-64 | grep lea | count 12
; This testcase was written to demonstrate an instruction-selection problem,
; however it also happens to expose a limitation in the DAGCombiner's
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/lea.ll b/libclamav/c++/llvm/test/CodeGen/X86/lea.ll
index 30a477a..22a9644 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/lea.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/lea.ll
@@ -1,9 +1,34 @@
-; RUN: llvm-as < %s | llc -march=x86
-; RUN: llvm-as < %s | llc -march=x86 | not grep orl
+; RUN: llc < %s -march=x86-64 | FileCheck %s
-define i32 @test(i32 %x) {
- %tmp1 = shl i32 %x, 3 ; <i32> [#uses=1]
- %tmp2 = add i32 %tmp1, 7 ; <i32> [#uses=1]
+define i32 @test1(i32 %x) nounwind {
+ %tmp1 = shl i32 %x, 3
+ %tmp2 = add i32 %tmp1, 7
ret i32 %tmp2
+; CHECK: test1:
+; CHECK: leal 7(,%rdi,8), %eax
}
+
+; ISel the add of -4 with a neg and use an lea for the rest of the
+; arithemtic.
+define i32 @test2(i32 %x_offs) nounwind readnone {
+entry:
+ %t0 = icmp sgt i32 %x_offs, 4
+ br i1 %t0, label %bb.nph, label %bb2
+
+bb.nph:
+ %tmp = add i32 %x_offs, -5
+ %tmp6 = lshr i32 %tmp, 2
+ %tmp7 = mul i32 %tmp6, -4
+ %tmp8 = add i32 %tmp7, %x_offs
+ %tmp9 = add i32 %tmp8, -4
+ ret i32 %tmp9
+
+bb2:
+ ret i32 %x_offs
+; CHECK: test2:
+; CHECK: leal -5(%rdi), %eax
+; CHECK: andl $-4, %eax
+; CHECK: negl %eax
+; CHECK: leal -4(%rdi,%rax), %eax
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/legalizedag_vec.ll b/libclamav/c++/llvm/test/CodeGen/X86/legalizedag_vec.ll
index 8d8683d..574b46a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/legalizedag_vec.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/legalizedag_vec.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=sse2 -disable-mmx -o %t
; RUN: grep {call.*divdi3} %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/lfence.ll b/libclamav/c++/llvm/test/CodeGen/X86/lfence.ll
index 0721d73..7a96ca3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/lfence.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/lfence.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep lfence
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep lfence
declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/limited-prec.ll b/libclamav/c++/llvm/test/CodeGen/X86/limited-prec.ll
index 6afaea4..7bf4ac2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/limited-prec.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/limited-prec.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -limit-float-precision=6 -march=x86 | \
+; RUN: llc < %s -limit-float-precision=6 -march=x86 | \
; RUN: not grep exp | not grep log | not grep pow
-; RUN: llvm-as < %s | llc -limit-float-precision=12 -march=x86 | \
+; RUN: llc < %s -limit-float-precision=12 -march=x86 | \
; RUN: not grep exp | not grep log | not grep pow
-; RUN: llvm-as < %s | llc -limit-float-precision=18 -march=x86 | \
+; RUN: llc < %s -limit-float-precision=18 -march=x86 | \
; RUN: not grep exp | not grep log | not grep pow
define float @f1(float %x) nounwind noinline {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/live-out-reg-info.ll b/libclamav/c++/llvm/test/CodeGen/X86/live-out-reg-info.ll
index ffaf3c1..7132777 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/live-out-reg-info.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/live-out-reg-info.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {testb \[$\]1,}
+; RUN: llc < %s -march=x86-64 | grep {testb \[$\]1,}
; Make sure dagcombine doesn't eliminate the comparison due
; to an off-by-one bug with ComputeMaskedBits information.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/local-liveness.ll b/libclamav/c++/llvm/test/CodeGen/X86/local-liveness.ll
index 18d999b..321f208 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/local-liveness.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/local-liveness.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -regalloc=local | grep {subl %eax, %edx}
+; RUN: llc < %s -march=x86 -regalloc=local | grep {subl %eax, %edx}
; Local regalloc shouldn't assume that both the uses of the
; sub instruction are kills, because one of them is tied
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/long-setcc.ll b/libclamav/c++/llvm/test/CodeGen/X86/long-setcc.ll
index 8d9ebfb..e0165fb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/long-setcc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/long-setcc.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep cmp | count 1
-; RUN: llvm-as < %s | llc -march=x86 | grep shr | count 1
-; RUN: llvm-as < %s | llc -march=x86 | grep xor | count 1
+; RUN: llc < %s -march=x86 | grep cmp | count 1
+; RUN: llc < %s -march=x86 | grep shr | count 1
+; RUN: llc < %s -march=x86 | grep xor | count 1
define i1 @t1(i64 %x) nounwind {
%B = icmp slt i64 %x, 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/longlong-deadload.ll b/libclamav/c++/llvm/test/CodeGen/X86/longlong-deadload.ll
index a8e2c31..9a4c8f2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/longlong-deadload.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/longlong-deadload.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep '4{(%...)}
+; RUN: llc < %s -march=x86 | not grep '4{(%...)}
; This should not load or store the top part of *P.
define void @test(i64* %P) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/loop-hoist.ll b/libclamav/c++/llvm/test/CodeGen/X86/loop-hoist.ll
index cf63f30..b52066d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/loop-hoist.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/loop-hoist.ll
@@ -1,6 +1,6 @@
; LSR should hoist the load from the "Arr" stub out of the loop.
-; RUN: llvm-as < %s | llc -relocation-model=dynamic-no-pic -mtriple=i686-apple-darwin8.7.2 | FileCheck %s
+; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=i686-apple-darwin8.7.2 | FileCheck %s
; CHECK: _foo:
; CHECK: L_Arr$non_lazy_ptr
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce-2.ll
index 8ea5bdb..30b5114 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce-2.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -relocation-model=pic | \
+; RUN: llc < %s -march=x86 -relocation-model=pic | \
; RUN: grep {, 4} | count 1
-; RUN: llvm-as < %s | llc -march=x86 | not grep lea
+; RUN: llc < %s -march=x86 | not grep lea
;
; Make sure the common loop invariant A is hoisted up to preheader,
; since too many registers are needed to subsume it into the addressing modes.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce-3.ll
index b6bb814..70c9134 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -relocation-model=dynamic-no-pic | \
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=dynamic-no-pic | \
; RUN: grep {A+} | count 2
;
; Make sure the common loop invariant A is not hoisted up to preheader,
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce.ll b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce.ll
index 8737101..4cb56ca 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -relocation-model=static | \
+; RUN: llc < %s -march=x86 -relocation-model=static | \
; RUN: grep {A+} | count 2
;
; Make sure the common loop invariant A is not hoisted up to preheader,
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce2.ll b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce2.ll
index 507a9e5..a1f38a7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -relocation-model=pic | grep {\$pb} | grep mov
+; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=pic | grep {\$pb} | grep mov
;
; Make sure the PIC label flags2-"L1$pb" is not moved up to the preheader.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce3.ll b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce3.ll
index 4e95bdd..e340edd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce3.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep cmp | grep 240
-; RUN: llvm-as < %s | llc -march=x86 | grep inc | count 1
+; RUN: llc < %s -march=x86 | grep cmp | grep 240
+; RUN: llc < %s -march=x86 | grep inc | count 1
define i32 @foo(i32 %A, i32 %B, i32 %C, i32 %D) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce4.ll b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce4.ll
index 711f223..87b606f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce4.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep cmp | grep 64
-; RUN: llvm-as < %s | llc -march=x86 | not grep inc
+; RUN: llc < %s -march=x86 | grep cmp | grep 64
+; RUN: llc < %s -march=x86 | not grep inc
@state = external global [0 x i32] ; <[0 x i32]*> [#uses=4]
@S = external global [0 x i32] ; <[0 x i32]*> [#uses=4]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce5.ll b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce5.ll
index 6e037e2..4ec2a02 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep inc | count 1
+; RUN: llc < %s -march=x86 | grep inc | count 1
@X = weak global i16 0 ; <i16*> [#uses=1]
@Y = weak global i16 0 ; <i16*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce6.ll b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce6.ll
index fa8b57a..81da82e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep inc
+; RUN: llc < %s -march=x86-64 | not grep inc
define fastcc i32 @decodeMP3(i32 %isize, i32* %done) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce7.ll b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce7.ll
index b6a130a..4b565a6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce7.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep imul
+; RUN: llc < %s -march=x86 | not grep imul
target triple = "i386-apple-darwin9.6"
%struct.III_psy_xmin = type { [22 x double], [13 x [3 x double]] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce8.ll b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce8.ll
index 1846c7d..e14cd8a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce8.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/loop-strength-reduce8.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep leal | not grep 16
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep leal | not grep 16
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.bitmap_element = type { %struct.bitmap_element*, %struct.bitmap_element*, i32, [2 x i64] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll b/libclamav/c++/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
index c998268..474450a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
@@ -1,4 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | %prcontext decq 1 | grep jne
+; RUN: llc -march=x86-64 < %s | FileCheck %s
+
+; CHECK: decq
+; CHECK-NEXT: jne
@Te0 = external global [256 x i32] ; <[256 x i32]*> [#uses=5]
@Te1 = external global [256 x i32] ; <[256 x i32]*> [#uses=4]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/lsr-negative-stride.ll b/libclamav/c++/llvm/test/CodeGen/X86/lsr-negative-stride.ll
index 28d041f..b08356c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/lsr-negative-stride.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/lsr-negative-stride.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: not grep neg %t
; RUN: not grep sub.*esp %t
; RUN: not grep esi %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/lsr-sort.ll b/libclamav/c++/llvm/test/CodeGen/X86/lsr-sort.ll
index 00e1d69..4058989 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/lsr-sort.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/lsr-sort.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep inc %t | count 1
; RUN: not grep incw %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/masked-iv-safe.ll b/libclamav/c++/llvm/test/CodeGen/X86/masked-iv-safe.ll
index 0bf347c..bc493bd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/masked-iv-safe.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/masked-iv-safe.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: not grep and %t
; RUN: not grep movz %t
; RUN: not grep sar %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/masked-iv-unsafe.ll b/libclamav/c++/llvm/test/CodeGen/X86/masked-iv-unsafe.ll
index 639a7a6..f23c020 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/masked-iv-unsafe.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/masked-iv-unsafe.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep and %t | count 6
; RUN: grep movzb %t | count 6
; RUN: grep sar %t | count 12
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/maskmovdqu.ll b/libclamav/c++/llvm/test/CodeGen/X86/maskmovdqu.ll
index 4d1ed1d..7796f0e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/maskmovdqu.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/maskmovdqu.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep -i EDI
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2 | grep -i RDI
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep -i EDI
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep -i RDI
; rdar://6573467
define void @test(<16 x i8> %a, <16 x i8> %b, i32 %dummy, i8* %c) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/memcpy-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/memcpy-2.ll
index 0fccc35..2dc939e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/memcpy-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/memcpy-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 7
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 5
+; RUN: llc < %s -march=x86 -mattr=-sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 7
+; RUN: llc < %s -march=x86 -mattr=+sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 5
%struct.ParmT = type { [25 x i8], i8, i8* }
@.str12 = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" ; <[25 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/memcpy.ll b/libclamav/c++/llvm/test/CodeGen/X86/memcpy.ll
index 97a2dd5..24530cd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/memcpy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/memcpy.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep call.*memcpy | count 2
+; RUN: llc < %s -march=x86-64 | grep call.*memcpy | count 2
declare void @llvm.memcpy.i64(i8*, i8*, i64, i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/memmove-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/memmove-0.ll
index a2b452d..d405068 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/memmove-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/memmove-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-pc-linux-gnu | grep {call memcpy}
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {call memcpy}
declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/memmove-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/memmove-1.ll
index 3b2debc..2057be8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/memmove-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/memmove-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-pc-linux-gnu | grep {call memmove}
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {call memmove}
declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/memmove-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/memmove-2.ll
index 37bbe0b..68a9f4d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/memmove-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/memmove-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-pc-linux-gnu | not grep call
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | not grep call
declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/memmove-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/memmove-3.ll
index 2e692c7..d8a419c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/memmove-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/memmove-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-pc-linux-gnu | grep {call memmove}
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {call memmove}
declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/memmove-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/memmove-4.ll
index f23c7d5..027db1f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/memmove-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/memmove-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | not grep call
+; RUN: llc < %s | not grep call
target triple = "i686-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/memset-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/memset-2.ll
index 0011a7c..7deb52f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/memset-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/memset-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc | not grep rep
-; RUN: llvm-as < %s | llc | grep memset
+; RUN: llc < %s | not grep rep
+; RUN: llc < %s | grep memset
target triple = "i386"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/memset.ll b/libclamav/c++/llvm/test/CodeGen/X86/memset.ll
index 564174c..cf7464d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/memset.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/memset.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 9
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 3
+; RUN: llc < %s -march=x86 -mattr=-sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 9
+; RUN: llc < %s -march=x86 -mattr=+sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 3
%struct.x = type { i16, i16 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/memset64-on-x86-32.ll b/libclamav/c++/llvm/test/CodeGen/X86/memset64-on-x86-32.ll
index d76d4d4..da8fc51 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/memset64-on-x86-32.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/memset64-on-x86-32.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep stosl
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movq | count 10
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep stosl
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movq | count 10
define void @bork() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mfence.ll b/libclamav/c++/llvm/test/CodeGen/X86/mfence.ll
index 6abdbce..a1b2283 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mfence.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mfence.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep sfence
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep lfence
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep mfence
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep sfence
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep lfence
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mfence
declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mingw-alloca.ll b/libclamav/c++/llvm/test/CodeGen/X86/mingw-alloca.ll
index 53d2350..7dcd84d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mingw-alloca.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mingw-alloca.ll
@@ -1,14 +1,12 @@
-; RUN: llvm-as < %s | llc -o %t
-; RUN: grep __alloca %t | count 2
-; RUN: grep 4294967288 %t
-; RUN: grep {pushl %eax} %t
-; RUN: grep 8028 %t | count 2
+; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i386-pc-mingw32"
-define void @foo1(i32 %N) {
+define void @foo1(i32 %N) nounwind {
entry:
+; CHECK: _foo1:
+; CHECK: call __alloca
%tmp14 = alloca i32, i32 %N ; <i32*> [#uses=1]
call void @bar1( i32* %tmp14 )
ret void
@@ -16,8 +14,13 @@ entry:
declare void @bar1(i32*)
-define void @foo2(i32 inreg %N) {
+define void @foo2(i32 inreg %N) nounwind {
entry:
+; CHECK: _foo2:
+; CHECK: andl $-16, %esp
+; CHECK: pushl %eax
+; CHECK: call __alloca
+; CHECK: movl 8028(%esp), %eax
%A2 = alloca [2000 x i32], align 16 ; <[2000 x i32]*> [#uses=1]
%A2.sub = getelementptr [2000 x i32]* %A2, i32 0, i32 0 ; <i32*> [#uses=1]
call void @bar2( i32* %A2.sub, i32 %N )
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-arg-passing.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-arg-passing.ll
index 9496cbb..426e98e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-arg-passing.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-arg-passing.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mattr=+mmx | grep mm0 | count 3
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mattr=+mmx | grep esp | count 1
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep xmm0
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep rdi
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | not grep movups
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | grep mm0 | count 3
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | grep esp | count 1
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep xmm0
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep rdi
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | not grep movups
;
; On Darwin x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2].
; On Darwin x86-32, v1i64 values are passed in memory.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-arg-passing2.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-arg-passing2.ll
index aac614a..c42af08 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-arg-passing2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-arg-passing2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep movq2dq | count 1
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep movdq2q | count 2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep movq2dq | count 1
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep movdq2q | count 2
@g_v8qi = external global <8 x i8>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-arith.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-arith.ll
index 501786e..e4dfdbf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-arith.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-arith.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx
+; RUN: llc < %s -march=x86 -mattr=+mmx
;; A basic sanity check to make sure that MMX arithmetic actually compiles.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-bitcast-to-i64.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-bitcast-to-i64.ll
index c6bb489..1fd8f67 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-bitcast-to-i64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-bitcast-to-i64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movd | count 4
+; RUN: llc < %s -march=x86-64 | grep movd | count 4
define i64 @foo(<1 x i64>* %p) {
%t = load <1 x i64>* %p
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-copy-gprs.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-copy-gprs.ll
index 2047ce7..3607043 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-copy-gprs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-copy-gprs.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movq.*(%rsi), %rax}
-; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2 | grep {movl.*4(%eax),}
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {movsd.(%eax),}
+; RUN: llc < %s -march=x86-64 | grep {movq.*(%rsi), %rax}
+; RUN: llc < %s -march=x86 -mattr=-sse2 | grep {movl.*4(%eax),}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movsd.(%eax),}
; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs,
; increases the places that need to use emms.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-emms.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-emms.ll
index 60ba84d..5ff2588 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-emms.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-emms.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep emms
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep emms
define void @foo() {
entry:
call void @llvm.x86.mmx.emms( )
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-insert-element.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-insert-element.ll
index 0aa476d..a063ee1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-insert-element.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-insert-element.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | not grep movq
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep psllq
+; RUN: llc < %s -march=x86 -mattr=+mmx | not grep movq
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep psllq
define <2 x i32> @qux(i32 %A) nounwind {
%tmp3 = insertelement <2 x i32> < i32 0, i32 undef >, i32 %A, i32 1 ; <<2 x i32>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-pinsrw.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-pinsrw.ll
index f1d04fa..3af09f4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-pinsrw.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-pinsrw.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep pinsrw | count 1
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep pinsrw | count 1
; PR2562
external global i16 ; <i16*>:0 [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-punpckhdq.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-punpckhdq.ll
index 126fc9d..0af7e01 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-punpckhdq.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-punpckhdq.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep punpckhdq | count 1
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep punpckhdq | count 1
define void @bork(<1 x i64>* %x) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-s2v.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-s2v.ll
index 4ec2403..c98023c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-s2v.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-s2v.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx
+; RUN: llc < %s -march=x86 -mattr=+mmx
; PR2574
define void @entry(i32 %m_task_id, i32 %start_x, i32 %end_x) {; <label>:0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-shift.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-shift.ll
index 277cf07..dd0aa2c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-shift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-shift.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep psllq | grep 32
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep psllq | grep 32
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep psrad
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep psrlw
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep psllq | grep 32
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psllq | grep 32
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep psrad
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psrlw
define i64 @t1(<1 x i64> %mm1) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-shuffle.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-shuffle.ll
index 4b91cb9..e3125c7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-shuffle.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-shuffle.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mcpu=yonah
+; RUN: llc < %s -mcpu=yonah
; PR1427
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-vzmovl-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-vzmovl-2.ll
index 4dd1e47..8253c20 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-vzmovl-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-vzmovl-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep pxor
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep punpckldq
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep pxor
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep punpckldq
%struct.vS1024 = type { [8 x <4 x i32>] }
%struct.vS512 = type { [4 x <4 x i32>] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mmx-vzmovl.ll b/libclamav/c++/llvm/test/CodeGen/X86/mmx-vzmovl.ll
index 95f9579..d21e240 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mmx-vzmovl.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mmx-vzmovl.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep movd
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep movq
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep movd
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep movq
define void @foo(<1 x i64>* %a, <1 x i64>* %b) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/movfs.ll b/libclamav/c++/llvm/test/CodeGen/X86/movfs.ll
index af102d4..823e986 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/movfs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/movfs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep fs
+; RUN: llc < %s -march=x86 | grep fs
define i32 @foo() nounwind readonly {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/movgs.ll b/libclamav/c++/llvm/test/CodeGen/X86/movgs.ll
index f621849..b04048b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/movgs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/movgs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep gs
+; RUN: llc < %s -march=x86 | grep gs
define i32 @foo() nounwind readonly {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mul-legalize.ll b/libclamav/c++/llvm/test/CodeGen/X86/mul-legalize.ll
index 487614f..eca9e6f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mul-legalize.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mul-legalize.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep 24576
+; RUN: llc < %s -march=x86 | grep 24576
; PR2135
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mul-remat.ll b/libclamav/c++/llvm/test/CodeGen/X86/mul-remat.ll
index ffc8cc0..3fa0050 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mul-remat.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mul-remat.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 1
+; RUN: llc < %s -march=x86 | grep mov | count 1
; PR1874
define i32 @test(i32 %a, i32 %b) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mul-shift-reassoc.ll b/libclamav/c++/llvm/test/CodeGen/X86/mul-shift-reassoc.ll
index f0ecb5b..3777d8b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mul-shift-reassoc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mul-shift-reassoc.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep lea
-; RUN: llvm-as < %s | llc -march=x86 | not grep add
+; RUN: llc < %s -march=x86 | grep lea
+; RUN: llc < %s -march=x86 | not grep add
define i32 @test(i32 %X, i32 %Y) {
; Push the shl through the mul to allow an LEA to be formed, instead
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mul128.ll b/libclamav/c++/llvm/test/CodeGen/X86/mul128.ll
index c0ce6b3..6825b99 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mul128.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mul128.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep mul | count 3
+; RUN: llc < %s -march=x86-64 | grep mul | count 3
define i128 @foo(i128 %t, i128 %u) {
%k = mul i128 %t, %u
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/mul64.ll b/libclamav/c++/llvm/test/CodeGen/X86/mul64.ll
index cd0f802..5a25c5d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/mul64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/mul64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mul | count 3
+; RUN: llc < %s -march=x86 | grep mul | count 3
define i64 @foo(i64 %t, i64 %u) {
%k = mul i64 %t, %u
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/multiple-return-values-cross-block.ll b/libclamav/c++/llvm/test/CodeGen/X86/multiple-return-values-cross-block.ll
index f632b87..e9837d0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/multiple-return-values-cross-block.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/multiple-return-values-cross-block.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
declare {x86_fp80, x86_fp80} @test()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/multiple-return-values.ll b/libclamav/c++/llvm/test/CodeGen/X86/multiple-return-values.ll
index 5f7a83f..018d997 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/multiple-return-values.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/multiple-return-values.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
define {i64, float} @bar(i64 %a, float %b) {
%y = add i64 %a, 7
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/nancvt.ll b/libclamav/c++/llvm/test/CodeGen/X86/nancvt.ll
index 96cac0d..0b56644 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/nancvt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/nancvt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -std-compile-opts | llc > %t
+; RUN: opt < %s -std-compile-opts | llc > %t
; RUN: grep 2147027116 %t | count 3
; RUN: grep 2147228864 %t | count 3
; RUN: grep 2146502828 %t | count 3
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/narrow_op-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/narrow_op-1.ll
index 0ee11b4..18f1108 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/narrow_op-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/narrow_op-1.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep orb | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 | grep orb | grep 1
-; RUN: llvm-as < %s | llc -march=x86-64 | grep orl | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 | grep orl | grep 16842752
+; RUN: llc < %s -march=x86-64 | grep orb | count 1
+; RUN: llc < %s -march=x86-64 | grep orb | grep 1
+; RUN: llc < %s -march=x86-64 | grep orl | count 1
+; RUN: llc < %s -march=x86-64 | grep orl | grep 16842752
%struct.bf = type { i64, i16, i16, i32 }
@bfi = common global %struct.bf zeroinitializer, align 16
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/narrow_op-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/narrow_op-2.ll
index b441794..796ef7a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/narrow_op-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/narrow_op-2.ll
@@ -1,12 +1,14 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep andb | count 2
-; RUN: llvm-as < %s | llc -march=x86-64 | grep andb | grep 254
-; RUN: llvm-as < %s | llc -march=x86-64 | grep andb | grep 253
+; RUN: llc < %s -march=x86-64 | FileCheck %s
%struct.bf = type { i64, i16, i16, i32 }
@bfi = external global %struct.bf*
define void @t1() nounwind ssp {
entry:
+
+; CHECK: andb $-2, 10(
+; CHECK: andb $-3, 10(
+
%0 = load %struct.bf** @bfi, align 8
%1 = getelementptr %struct.bf* %0, i64 0, i32 1
%2 = bitcast i16* %1 to i32*
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/neg_fp.ll b/libclamav/c++/llvm/test/CodeGen/X86/neg_fp.ll
index d5e7c29..57164f2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/neg_fp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/neg_fp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse41 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse41 -o %t
; RUN: grep xorps %t | count 1
; Test that when we don't -enable-unsafe-fp-math, we don't do the optimization
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/negate-add-zero.ll b/libclamav/c++/llvm/test/CodeGen/X86/negate-add-zero.ll
index 689639f..c3f412e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/negate-add-zero.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/negate-add-zero.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -enable-unsafe-fp-math -march=x86 | not grep xor
+; RUN: llc < %s -enable-unsafe-fp-math -march=x86 | not grep xor
; PR3374
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/negative-sin.ll b/libclamav/c++/llvm/test/CodeGen/X86/negative-sin.ll
index 8cc1bec..7842eb8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/negative-sin.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/negative-sin.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -enable-unsafe-fp-math -march=x86-64 | \
+; RUN: llc < %s -enable-unsafe-fp-math -march=x86-64 | \
; RUN: not egrep {addsd|subsd|xor}
declare double @sin(double %f)
@@ -6,7 +6,7 @@ declare double @sin(double %f)
define double @foo(double %e)
{
%f = fsub double 0.0, %e
- %g = call double @sin(double %f)
+ %g = call double @sin(double %f) readonly
%h = fsub double 0.0, %g
ret double %h
}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/negative-subscript.ll b/libclamav/c++/llvm/test/CodeGen/X86/negative-subscript.ll
index f2bd315..28f7d6b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/negative-subscript.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/negative-subscript.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; rdar://6559995
@a = external global [255 x i8*], align 32
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/negative_zero.ll b/libclamav/c++/llvm/test/CodeGen/X86/negative_zero.ll
index 3c47b8f..29474c2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/negative_zero.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/negative_zero.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2,-sse3 | grep fchs
+; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3 | grep fchs
define double @T() {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/nobt.ll b/libclamav/c++/llvm/test/CodeGen/X86/nobt.ll
index 5529428..35090e3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/nobt.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/nobt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep btl
+; RUN: llc < %s -march=x86 | not grep btl
; This tests some cases where BT must not be generated. See also bt.ll.
; Fixes 20040709-[12].c in gcc testsuite.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/nofence.ll b/libclamav/c++/llvm/test/CodeGen/X86/nofence.ll
index 132ac94..244d2e9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/nofence.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/nofence.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep fence
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep fence
declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/omit-label.ll b/libclamav/c++/llvm/test/CodeGen/X86/omit-label.ll
index 9ff6816..0ec03eb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/omit-label.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/omit-label.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -asm-verbose=false -mtriple=x86_64-linux-gnu | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -mtriple=x86_64-linux-gnu | FileCheck %s
; PR4126
; PR4732
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/opt-ext-uses.ll b/libclamav/c++/llvm/test/CodeGen/X86/opt-ext-uses.ll
index 322850c..fa2aef5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/opt-ext-uses.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/opt-ext-uses.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep movw | count 1
+; RUN: llc < %s -march=x86 | grep movw | count 1
define i16 @t() signext {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-0.ll
index 90c1456..162c7a5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep cmov
+; RUN: llc < %s -march=x86 | not grep cmov
; LSR should be able to eliminate the max computations by
; making the loops use slt/ult comparisons instead of ne comparisons.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-1.ll
index 084e181..ad6c24d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep cmov
+; RUN: llc < %s -march=x86-64 | not grep cmov
; LSR should be able to eliminate both smax and umax expressions
; in loop trip counts.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-2.ll
index effc3fc..8851c5b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/optimize-max-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep cmov %t | count 2
; RUN: grep jne %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/or-branch.ll b/libclamav/c++/llvm/test/CodeGen/X86/or-branch.ll
index 20886d5..9ebf890 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/or-branch.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/or-branch.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep set
+; RUN: llc < %s -march=x86 | not grep set
define void @foo(i32 %X, i32 %Y, i32 %Z) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/overlap-shift.ll b/libclamav/c++/llvm/test/CodeGen/X86/overlap-shift.ll
index 7584a70..c1fc041 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/overlap-shift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/overlap-shift.ll
@@ -6,7 +6,7 @@
; Check that the shift gets turned into an LEA.
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: not grep {mov E.X, E.X}
@G = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/packed_struct.ll b/libclamav/c++/llvm/test/CodeGen/X86/packed_struct.ll
index 2a781e7..da6e8f8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/packed_struct.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/packed_struct.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: grep foos+5 %t
; RUN: grep foos+1 %t
; RUN: grep foos+9 %t
@@ -15,7 +15,7 @@ target triple = "i686-pc-linux-gnu"
@foos = external global %struct.anon ; <%struct.anon*> [#uses=3]
@bara = weak global [4 x <{ i32, i8 }>] zeroinitializer ; <[4 x <{ i32, i8 }>]*> [#uses=2]
-define i32 @foo() {
+define i32 @foo() nounwind {
entry:
%tmp = load i32* getelementptr (%struct.anon* @foos, i32 0, i32 1) ; <i32> [#uses=1]
%tmp3 = load i32* getelementptr (%struct.anon* @foos, i32 0, i32 2) ; <i32> [#uses=1]
@@ -25,7 +25,7 @@ entry:
ret i32 %tmp7
}
-define i8 @bar() {
+define i8 @bar() nounwind {
entry:
%tmp = load i8* getelementptr ([4 x <{ i32, i8 }>]* @bara, i32 0, i32 0, i32 1) ; <i8> [#uses=1]
%tmp4 = load i8* getelementptr ([4 x <{ i32, i8 }>]* @bara, i32 0, i32 3, i32 1) ; <i8> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/peep-test-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/peep-test-0.ll
index 8dcd23a..e521d8e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/peep-test-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/peep-test-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: not grep cmp %t
; RUN: not grep test %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/peep-test-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/peep-test-1.ll
index 85e3bf2..f83f0f6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/peep-test-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/peep-test-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: grep dec %t | count 1
; RUN: not grep test %t
; RUN: not grep cmp %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/peep-test-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/peep-test-2.ll
index 788f610..2745172 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/peep-test-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/peep-test-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep testl
+; RUN: llc < %s -march=x86 | grep testl
; It's tempting to eliminate the testl instruction here and just use the
; EFLAGS value from the incl, however it can't be known whether the add
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/peep-test-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/peep-test-3.ll
new file mode 100644
index 0000000..13a69ed
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/peep-test-3.ll
@@ -0,0 +1,89 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+; rdar://7226797
+
+; LLVM should omit the testl and use the flags result from the orl.
+
+; CHECK: or:
+define void @or(float* %A, i32 %IA, i32 %N) nounwind {
+entry:
+ %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1]
+ %1 = and i32 %0, 3 ; <i32> [#uses=1]
+ %2 = xor i32 %IA, 1 ; <i32> [#uses=1]
+; CHECK: orl %ecx, %edx
+; CHECK-NEXT: je
+ %3 = or i32 %2, %1 ; <i32> [#uses=1]
+ %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1]
+ br i1 %4, label %return, label %bb
+
+bb: ; preds = %entry
+ store float 0.000000e+00, float* %A, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
+; CHECK: xor:
+define void @xor(float* %A, i32 %IA, i32 %N) nounwind {
+entry:
+ %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1]
+ %1 = and i32 %0, 3 ; <i32> [#uses=1]
+; CHECK: xorl $1, %e
+; CHECK-NEXT: je
+ %2 = xor i32 %IA, 1 ; <i32> [#uses=1]
+ %3 = xor i32 %2, %1 ; <i32> [#uses=1]
+ %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1]
+ br i1 %4, label %return, label %bb
+
+bb: ; preds = %entry
+ store float 0.000000e+00, float* %A, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
+; CHECK: and:
+define void @and(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
+entry:
+ store i8 0, i8* %p
+ %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1]
+ %1 = and i32 %0, 3 ; <i32> [#uses=1]
+ %2 = xor i32 %IA, 1 ; <i32> [#uses=1]
+; CHECK: andl $3, %
+; CHECK-NEXT: movb %
+; CHECK-NEXT: je
+ %3 = and i32 %2, %1 ; <i32> [#uses=1]
+ %t = trunc i32 %3 to i8
+ store i8 %t, i8* %p
+ %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1]
+ br i1 %4, label %return, label %bb
+
+bb: ; preds = %entry
+ store float 0.000000e+00, float* null, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
+
+; Just like @and, but without the trunc+store. This should use a testl
+; instead of an andl.
+; CHECK: test:
+define void @test(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
+entry:
+ store i8 0, i8* %p
+ %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1]
+ %1 = and i32 %0, 3 ; <i32> [#uses=1]
+ %2 = xor i32 %IA, 1 ; <i32> [#uses=1]
+; CHECK: testb $3, %
+; CHECK-NEXT: je
+ %3 = and i32 %2, %1 ; <i32> [#uses=1]
+ %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1]
+ br i1 %4, label %return, label %bb
+
+bb: ; preds = %entry
+ store float 0.000000e+00, float* null, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/peep-vector-extract-concat.ll b/libclamav/c++/llvm/test/CodeGen/X86/peep-vector-extract-concat.ll
index e6c88bb..e4ab2b5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/peep-vector-extract-concat.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/peep-vector-extract-concat.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2,-sse41 | grep {pshufd \$3, %xmm0, %xmm0}
+; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep {pshufd \$3, %xmm0, %xmm0}
define float @foo(<8 x float> %a) nounwind {
%c = extractelement <8 x float> %a, i32 3
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/peep-vector-extract-insert.ll b/libclamav/c++/llvm/test/CodeGen/X86/peep-vector-extract-insert.ll
index 77332d0..5e18044 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/peep-vector-extract-insert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/peep-vector-extract-insert.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {pxor %xmm0, %xmm0} | count 2
+; RUN: llc < %s -march=x86-64 | grep {pxor %xmm0, %xmm0} | count 2
define float @foo(<4 x float> %a) {
%b = insertelement <4 x float> %a, float 0.0, i32 3
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/personality.ll b/libclamav/c++/llvm/test/CodeGen/X86/personality.ll
new file mode 100644
index 0000000..5acf04c
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/personality.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s -check-prefix=X32
+; PR1632
+
+define void @_Z1fv() {
+entry:
+ invoke void @_Z1gv( )
+ to label %return unwind label %unwind
+
+unwind: ; preds = %entry
+ br i1 false, label %eh_then, label %cleanup20
+
+eh_then: ; preds = %unwind
+ invoke void @__cxa_end_catch( )
+ to label %return unwind label %unwind10
+
+unwind10: ; preds = %eh_then
+ %eh_select13 = tail call i64 (i8*, i8*, ...)* @llvm.eh.selector.i64( i8* null, i8* bitcast (void ()* @__gxx_personality_v0 to i8*), i32 1 ) ; <i32> [#uses=2]
+ %tmp18 = icmp slt i64 %eh_select13, 0 ; <i1> [#uses=1]
+ br i1 %tmp18, label %filter, label %cleanup20
+
+filter: ; preds = %unwind10
+ unreachable
+
+cleanup20: ; preds = %unwind10, %unwind
+ %eh_selector.0 = phi i64 [ 0, %unwind ], [ %eh_select13, %unwind10 ] ; <i32> [#uses=0]
+ ret void
+
+return: ; preds = %eh_then, %entry
+ ret void
+}
+
+declare void @_Z1gv()
+
+declare i64 @llvm.eh.selector.i64(i8*, i8*, ...)
+
+declare void @__gxx_personality_v0()
+
+declare void @__cxa_end_catch()
+
+; X64: Leh_frame_common_begin:
+; X64: .long ___gxx_personality_v0 at GOTPCREL+4
+
+; X32: Leh_frame_common_begin:
+; X32: .long L___gxx_personality_v0$non_lazy_ptr-
+; ....
+
+; X32: .section __IMPORT,__pointers,non_lazy_symbol_pointers
+; X32: L___gxx_personality_v0$non_lazy_ptr:
+; X32: .indirect_symbol ___gxx_personality_v0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/phys_subreg_coalesce-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/phys_subreg_coalesce-2.ll
index 7ca3ea8..23c509c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/phys_subreg_coalesce-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/phys_subreg_coalesce-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 5
+; RUN: llc < %s -march=x86 | grep mov | count 5
; PR2659
define i32 @binomial(i32 %n, i32 %k) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/phys_subreg_coalesce.ll b/libclamav/c++/llvm/test/CodeGen/X86/phys_subreg_coalesce.ll
index 3bbc55d..2c855ce 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/phys_subreg_coalesce.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/phys_subreg_coalesce.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin9 -mattr=+sse2 | not grep movl
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+sse2 | not grep movl
%struct.dpoint = type { double, double }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pic-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/pic-1.ll
deleted file mode 100644
index 299fa59..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/pic-1.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=i686-pc-linux-gnu -relocation-model=pic -o %t
-; RUN: grep _GLOBAL_OFFSET_TABLE_ %t
-; RUN: grep piclabel %t | count 3
-; RUN: grep GOT %t | count 3
-; RUN: not grep GOTOFF %t
-
- at ptr = external global i32*
- at dst = external global i32
- at src = external global i32
-
-define void @foo() nounwind {
-entry:
- store i32* @dst, i32** @ptr
- %tmp.s = load i32* @src
- store i32 %tmp.s, i32* @dst
- ret void
-}
-
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pic-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/pic-2.ll
deleted file mode 100644
index de90cb7..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/pic-2.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -relocation-model=pic \
-; RUN: -o %t
-; RUN: grep _GLOBAL_OFFSET_TABLE_ %t
-; RUN: grep piclabel %t | count 3
-; RUN: grep GOTOFF %t | count 4
-
- at ptr = internal global i32* null
- at dst = internal global i32 0
- at src = internal global i32 0
-
-define void @foo() {
-entry:
- store i32* @dst, i32** @ptr
- %tmp.s = load i32* @src
- store i32 %tmp.s, i32* @dst
- ret void
-}
-
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pic-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/pic-3.ll
deleted file mode 100644
index 245cae8..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/pic-3.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -relocation-model=pic | FileCheck %s
-
-; CHECK: bar:
-; CHECK: call .Lllvm$1.$piclabel
-; CHECK: popl %ebx
-; CHECK: addl $_GLOBAL_OFFSET_TABLE_ + [.-.Lllvm$1.$piclabel], %ebx
-; CHECK: call foo at PLT
-
-
-define void @bar() nounwind {
-entry:
- call void(...)* @foo()
- br label %return
-return:
- ret void
-}
-
-declare void @foo(...)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pic-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/pic-4.ll
deleted file mode 100644
index 317c04b..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/pic-4.ll
+++ /dev/null
@@ -1,22 +0,0 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=i686-pc-linux-gnu -relocation-model=pic -o %t
-; RUN: grep _GLOBAL_OFFSET_TABLE_ %t
-; RUN: grep piclabel %t | count 3
-; RUN: grep PLT %t | count 1
-; RUN: grep GOT %t | count 1
-; RUN: not grep GOTOFF %t
-
- at pfoo = external global void(...)*
-
-define void @bar() {
-entry:
- %tmp = call void(...)*(...)* @afoo()
- store void(...)* %tmp, void(...)** @pfoo
- %tmp1 = load void(...)** @pfoo
- call void(...)* %tmp1()
- br label %return
-return:
- ret void
-}
-
-declare void(...)* @afoo(...)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pic-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/pic-5.ll
deleted file mode 100644
index 789e7db..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/pic-5.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -relocation-model=pic \
-; RUN: -o %t
-; RUN: grep _GLOBAL_OFFSET_TABLE_ %t
-; RUN: grep piclabel %t | count 3
-; RUN: grep PLT %t | count 1
-
- at ptr = external global i32*
-
-define void @foo() {
-entry:
- %ptr = malloc i32, i32 10
- ret void
-}
-
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pic-6.ll b/libclamav/c++/llvm/test/CodeGen/X86/pic-6.ll
deleted file mode 100644
index 922521d..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/pic-6.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -relocation-model=pic \
-; RUN: -o %t
-; RUN: grep _GLOBAL_OFFSET_TABLE_ %t
-; RUN: grep piclabel %t | count 3
-; RUN: grep GOT %t | count 3
-
- at ptr = global i32* null
- at dst = global i32 0
- at src = global i32 0
-
-define void @foo() {
-entry:
- store i32* @dst, i32** @ptr
- %tmp.s = load i32* @src
- store i32 %tmp.s, i32* @dst
- ret void
-}
-
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pic-cpool.ll b/libclamav/c++/llvm/test/CodeGen/X86/pic-cpool.ll
deleted file mode 100644
index 6189fb2..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/pic-cpool.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -relocation-model=pic \
-; RUN: -o %t
-; RUN: grep _GLOBAL_OFFSET_TABLE_ %t
-; RUN: grep piclabel %t | count 3
-; RUN: grep GOTOFF %t | count 1
-; RUN: grep CPI %t | count 2
-
-define double @foo(i32 %a.u) nounwind {
-entry:
- %tmp = icmp eq i32 %a.u,0
- %retval = select i1 %tmp, double 4.561230e+02, double 1.234560e+02
- ret double %retval
-}
-
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pic-jtbl.ll b/libclamav/c++/llvm/test/CodeGen/X86/pic-jtbl.ll
deleted file mode 100644
index 81ca9db..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/pic-jtbl.ll
+++ /dev/null
@@ -1,61 +0,0 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -relocation-model=pic \
-; RUN: -o %t
-; RUN: grep _GLOBAL_OFFSET_TABLE_ %t
-; RUN: grep piclabel %t | count 3
-; RUN: grep PLT %t | count 6
-; RUN: grep GOTOFF %t | count 14
-; RUN: grep JTI %t | count 2
-
-; X86-64:
-; RUN: llvm-as < %s | llc -mtriple=x86_64-pc-linux-gnu -relocation-model=pic > %t
-; RUN: grep {LJTI1_0(%rip)} %t
-define void @bar(i32 %n.u) nounwind {
-entry:
- switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ]
-bb:
- tail call void(...)* @foo1()
- ret void
-bb1:
- tail call void(...)* @foo2()
- ret void
-bb2:
- tail call void(...)* @foo6()
- ret void
-bb3:
- tail call void(...)* @foo3()
- ret void
-bb4:
- tail call void(...)* @foo4()
- ret void
-bb5:
- tail call void(...)* @foo5()
- ret void
-bb6:
- tail call void(...)* @foo1()
- ret void
-bb7:
- tail call void(...)* @foo2()
- ret void
-bb8:
- tail call void(...)* @foo6()
- ret void
-bb9:
- tail call void(...)* @foo3()
- ret void
-bb10:
- tail call void(...)* @foo4()
- ret void
-bb11:
- tail call void(...)* @foo5()
- ret void
-bb12:
- tail call void(...)* @foo6()
- ret void
-}
-
-declare void @foo1(...)
-declare void @foo2(...)
-declare void @foo6(...)
-declare void @foo3(...)
-declare void @foo4(...)
-declare void @foo5(...)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pic-load-remat.ll b/libclamav/c++/llvm/test/CodeGen/X86/pic-load-remat.ll
index cb4e640..7729752 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pic-load-remat.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pic-load-remat.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | grep psllw | grep pb
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | grep psllw | grep pb
define void @f() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pic.ll b/libclamav/c++/llvm/test/CodeGen/X86/pic.ll
new file mode 100644
index 0000000..e9218ed
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pic.ll
@@ -0,0 +1,209 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=LINUX
+
+ at ptr = external global i32*
+ at dst = external global i32
+ at src = external global i32
+
+define void @test1() nounwind {
+entry:
+ store i32* @dst, i32** @ptr
+ %tmp.s = load i32* @src
+ store i32 %tmp.s, i32* @dst
+ ret void
+
+; LINUX: test1:
+; LINUX: .LBB1_0:
+; LINUX: call .L1$pb
+; LINUX-NEXT: .L1$pb:
+; LINUX-NEXT: popl
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref1-.L1$pb),
+; LINUX: movl dst at GOT(%eax),
+; LINUX: movl ptr at GOT(%eax),
+; LINUX: movl src at GOT(%eax),
+; LINUX: ret
+}
+
+ at ptr2 = global i32* null
+ at dst2 = global i32 0
+ at src2 = global i32 0
+
+define void @test2() nounwind {
+entry:
+ store i32* @dst2, i32** @ptr2
+ %tmp.s = load i32* @src2
+ store i32 %tmp.s, i32* @dst2
+ ret void
+
+; LINUX: test2:
+; LINUX: call .L2$pb
+; LINUX-NEXT: .L2$pb:
+; LINUX-NEXT: popl
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref2-.L2$pb), %eax
+; LINUX: movl dst2 at GOT(%eax),
+; LINUX: movl ptr2 at GOT(%eax),
+; LINUX: movl src2 at GOT(%eax),
+; LINUX: ret
+
+}
+
+declare i8* @malloc(i32)
+
+define void @test3() nounwind {
+entry:
+ %ptr = call i8* @malloc(i32 40)
+ ret void
+; LINUX: test3:
+; LINUX: pushl %ebx
+; LINUX-NEXT: subl $8, %esp
+; LINUX-NEXT: call .L3$pb
+; LINUX-NEXT: .L3$pb:
+; LINUX-NEXT: popl %ebx
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref3-.L3$pb), %ebx
+; LINUX: movl $40, (%esp)
+; LINUX: call malloc at PLT
+; LINUX: addl $8, %esp
+; LINUX: popl %ebx
+; LINUX: ret
+}
+
+ at pfoo = external global void(...)*
+
+define void @test4() nounwind {
+entry:
+ %tmp = call void(...)*(...)* @afoo()
+ store void(...)* %tmp, void(...)** @pfoo
+ %tmp1 = load void(...)** @pfoo
+ call void(...)* %tmp1()
+ ret void
+; LINUX: test4:
+; LINUX: call .L4$pb
+; LINUX-NEXT: .L4$pb:
+; LINUX: popl
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref4-.L4$pb),
+; LINUX: movl pfoo at GOT(%esi),
+; LINUX: call afoo at PLT
+; LINUX: call *
+}
+
+declare void(...)* @afoo(...)
+
+define void @test5() nounwind {
+entry:
+ call void(...)* @foo()
+ ret void
+; LINUX: test5:
+; LINUX: call .L5$pb
+; LINUX: popl %ebx
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref5-.L5$pb), %ebx
+; LINUX: call foo at PLT
+}
+
+declare void @foo(...)
+
+
+ at ptr6 = internal global i32* null
+ at dst6 = internal global i32 0
+ at src6 = internal global i32 0
+
+define void @test6() nounwind {
+entry:
+ store i32* @dst6, i32** @ptr6
+ %tmp.s = load i32* @src6
+ store i32 %tmp.s, i32* @dst6
+ ret void
+
+; LINUX: test6:
+; LINUX: call .L6$pb
+; LINUX-NEXT: .L6$pb:
+; LINUX-NEXT: popl %eax
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref6-.L6$pb), %eax
+; LINUX: leal dst6 at GOTOFF(%eax), %ecx
+; LINUX: movl %ecx, ptr6 at GOTOFF(%eax)
+; LINUX: movl src6 at GOTOFF(%eax), %ecx
+; LINUX: movl %ecx, dst6 at GOTOFF(%eax)
+; LINUX: ret
+}
+
+
+;; Test constant pool references.
+define double @test7(i32 %a.u) nounwind {
+entry:
+ %tmp = icmp eq i32 %a.u,0
+ %retval = select i1 %tmp, double 4.561230e+02, double 1.234560e+02
+ ret double %retval
+
+; LINUX: .LCPI7_0:
+
+; LINUX: test7:
+; LINUX: call .L7$pb
+; LINUX: .L7$pb:
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref7-.L7$pb),
+; LINUX: fldl .LCPI7_0 at GOTOFF(
+}
+
+
+;; Test jump table references.
+define void @test8(i32 %n.u) nounwind {
+entry:
+ switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ]
+bb:
+ tail call void(...)* @foo1()
+ ret void
+bb1:
+ tail call void(...)* @foo2()
+ ret void
+bb2:
+ tail call void(...)* @foo6()
+ ret void
+bb3:
+ tail call void(...)* @foo3()
+ ret void
+bb4:
+ tail call void(...)* @foo4()
+ ret void
+bb5:
+ tail call void(...)* @foo5()
+ ret void
+bb6:
+ tail call void(...)* @foo1()
+ ret void
+bb7:
+ tail call void(...)* @foo2()
+ ret void
+bb8:
+ tail call void(...)* @foo6()
+ ret void
+bb9:
+ tail call void(...)* @foo3()
+ ret void
+bb10:
+ tail call void(...)* @foo4()
+ ret void
+bb11:
+ tail call void(...)* @foo5()
+ ret void
+bb12:
+ tail call void(...)* @foo6()
+ ret void
+
+; LINUX: test8:
+; LINUX: call .L8$pb
+; LINUX: .L8$pb:
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref8-.L8$pb),
+; LINUX: addl .LJTI8_0 at GOTOFF(
+; LINUX: jmpl *%ecx
+
+; LINUX: .LJTI8_0:
+; LINUX: .long .LBB8_2 at GOTOFF
+; LINUX: .long .LBB8_2 at GOTOFF
+; LINUX: .long .LBB8_7 at GOTOFF
+; LINUX: .long .LBB8_3 at GOTOFF
+; LINUX: .long .LBB8_7 at GOTOFF
+}
+
+declare void @foo1(...)
+declare void @foo2(...)
+declare void @foo6(...)
+declare void @foo3(...)
+declare void @foo4(...)
+declare void @foo5(...)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pic_jumptable.ll b/libclamav/c++/llvm/test/CodeGen/X86/pic_jumptable.ll
index 04245d1..b3750c1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pic_jumptable.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pic_jumptable.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i386-linux-gnu -asm-verbose=false | not grep -F .text
-; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | not grep lea
-; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | grep add | count 2
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep 'lJTI'
+; RUN: llc < %s -relocation-model=pic -mtriple=i386-linux-gnu -asm-verbose=false | not grep -F .text
+; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | not grep lea
+; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | grep add | count 2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep 'lJTI'
; rdar://6971437
declare void @_Z3bari(i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pmul.ll b/libclamav/c++/llvm/test/CodeGen/X86/pmul.ll
index e00d1e5..e2746a8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pmul.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pmul.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -stack-alignment=16 > %t
+; RUN: llc < %s -march=x86 -mattr=sse41 -stack-alignment=16 > %t
; RUN: grep pmul %t | count 12
; RUN: grep mov %t | count 12
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/postalloc-coalescing.ll b/libclamav/c++/llvm/test/CodeGen/X86/postalloc-coalescing.ll
index 9c44a5a..a171436 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/postalloc-coalescing.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/postalloc-coalescing.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 3
+; RUN: llc < %s -march=x86 | grep mov | count 3
define fastcc i32 @_Z18yy_get_next_bufferv() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr1462.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr1462.ll
index 7f9037a..62549a5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr1462.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr1462.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1462
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr1489.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr1489.ll
index 10fa96a..c9e24bf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr1489.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr1489.ll
@@ -1,12 +1,12 @@
-; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 1082126238 | count 3
-; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 3058016715 | count 1
+; RUN: llc < %s -disable-fp-elim -O0 -mcpu=i486 | grep 1082126238 | count 3
+; RUN: llc < %s -disable-fp-elim -O0 -mcpu=i486 | grep -- -1236950581 | count 1
;; magic constants are 3.999f and half of 3.999
; ModuleID = '1489.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8"
@.str = internal constant [13 x i8] c"%d %d %d %d\0A\00" ; <[13 x i8]*> [#uses=1]
-define i32 @quux() {
+define i32 @quux() nounwind {
entry:
%tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1]
%tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
@@ -16,7 +16,7 @@ entry:
declare i32 @lrintf(float)
-define i32 @foo() {
+define i32 @foo() nounwind {
entry:
%tmp1 = tail call i32 @lrint( double 3.999000e+00 ) ; <i32> [#uses=1]
%tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
@@ -26,7 +26,7 @@ entry:
declare i32 @lrint(double)
-define i32 @bar() {
+define i32 @bar() nounwind {
entry:
%tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1]
%tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
@@ -34,7 +34,7 @@ entry:
ret i32 %tmp23
}
-define i32 @baz() {
+define i32 @baz() nounwind {
entry:
%tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1]
%tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
@@ -42,7 +42,7 @@ entry:
ret i32 %tmp23
}
-define i32 @main() {
+define i32 @main() nounwind {
entry:
%tmp = tail call i32 @baz( ) ; <i32> [#uses=1]
%tmp1 = tail call i32 @bar( ) ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr1505.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr1505.ll
index e9e3d90..883a806 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr1505.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr1505.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mcpu=i486 | not grep fldl
+; RUN: llc < %s -mcpu=i486 | not grep fldl
; PR1505
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr1505b.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr1505b.ll
index c70e327..12736cd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr1505b.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr1505b.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mcpu=i486 | grep fstpl | count 4
-; RUN: llvm-as < %s | llc -mcpu=i486 | grep fstps | count 3
+; RUN: llc < %s -mcpu=i486 | grep fstpl | count 4
+; RUN: llc < %s -mcpu=i486 | grep fstps | count 3
; PR1505
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr2177.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr2177.ll
index b03c990..e941bf7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr2177.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr2177.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2177
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr2182.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr2182.ll
index f65725d..f97663c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr2182.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr2182.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep {addl \$3, (%eax)} | count 4
+; RUN: llc < %s | grep {addl \$3, (%eax)} | count 4
; PR2182
target datalayout =
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr2326.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr2326.ll
index 6cf750c..f82dcb5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr2326.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr2326.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep sete
+; RUN: llc < %s -march=x86 | grep sete
; PR2326
define i32 @func_59(i32 %p_60) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr2623.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr2623.ll
index 51c86b7..5d0eb5d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr2623.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr2623.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2623
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr2656.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr2656.ll
index 96976b8..afd7114 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr2656.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr2656.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {xorps.\*sp} | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {xorps.\*sp} | count 1
; PR2656
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr2659.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr2659.ll
index 00e6e7b..0760e4c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr2659.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr2659.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 5
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 5
; PR2659
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr2849.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr2849.ll
index 673598f..0fec481 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr2849.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr2849.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2849
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr2924.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr2924.ll
index 2cab563..b9e8dc1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr2924.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr2924.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR2924
target datalayout =
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr2982.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr2982.ll
index f5dc1f4..3f9a595 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr2982.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr2982.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR2982
target datalayout =
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3154.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3154.ll
index 73f5101..18df97c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3154.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3154.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu -mattr=+sse2
-; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu -mattr=+sse2 -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -mattr=+sse2
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -mattr=+sse2 -relocation-model=pic -disable-fp-elim
; PR3154
define void @ff_flac_compute_autocorr_sse2(i32* %data, i32 %len, i32 %lag, double* %autoc) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3216.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3216.ll
index fdc814e..38c9f32 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3216.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3216.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {sar. \$5}
+; RUN: llc < %s -march=x86 | grep {sar. \$5}
@foo = global i8 127
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3241.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3241.ll
index 665a763..2f7917b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3241.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3241.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR3241
@g_620 = external global i32
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3243.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3243.ll
index 7be887b..483b5bf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3243.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3243.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR3243
declare signext i16 @safe_mul_func_int16_t_s_s(i16 signext, i32) nounwind readnone optsize
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3244.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3244.ll
index 0765f86..2598c2f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3244.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3244.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR3244
@g_62 = external global i16 ; <i16*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3250.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3250.ll
index dce154f..cccbf54 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3250.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3250.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR3250
declare i32 @safe_sub_func_short_u_u(i16 signext, i16 signext) nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3317.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3317.ll
index aa5ee7c..9d6626b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3317.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3317.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
; PR3317
%ArraySInt16 = type { %JavaObject, i8*, [0 x i16] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3366.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3366.ll
index a6f3e92..f813e2e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3366.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3366.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep movzbl
+; RUN: llc < %s -march=x86 | grep movzbl
; PR3366
define void @_ada_c34002a() nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3457.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3457.ll
index d4a9810..f7af927 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3457.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3457.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | not grep fstpt
+; RUN: llc < %s -mtriple=i386-apple-darwin | not grep fstpt
; PR3457
; rdar://6548010
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3495-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3495-2.ll
index f67ff75..1372a15 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3495-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3495-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of reloads omited}
+; RUN: llc < %s -march=x86 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of reloads omited}
target triple = "i386-apple-darwin9.6"
%struct.constraintVCGType = type { i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3495.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3495.ll
index ca6204c..4b62bf4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3495.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3495.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of reloads omited} | grep 2
-; RUN: llvm-as < %s | llc -march=x86 -stats |& not grep {Number of available reloads turned into copies}
-; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {Number of machine instrs printed} | grep 39
+; RUN: llc < %s -march=x86 -stats |& grep {Number of reloads omited} | grep 1
+; RUN: llc < %s -march=x86 -stats |& grep {Number of available reloads turned into copies} | grep 1
+; RUN: llc < %s -march=x86 -stats |& grep {Number of machine instrs printed} | grep 40
; PR3495
; The loop reversal kicks in once here, resulting in one fewer instruction.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pr3522.ll b/libclamav/c++/llvm/test/CodeGen/X86/pr3522.ll
index f743700..7cdeaa0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pr3522.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pr3522.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -stats |& not grep machine-sink
+; RUN: llc < %s -march=x86 -stats |& not grep machine-sink
; PR3522
target triple = "i386-pc-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pre-split1.ll b/libclamav/c++/llvm/test/CodeGen/X86/pre-split1.ll
index 4f9a582..e89b507 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pre-split1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pre-split1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
; XFAIL: *
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pre-split10.ll b/libclamav/c++/llvm/test/CodeGen/X86/pre-split10.ll
index 60297e9..db039bd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pre-split10.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pre-split10.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split
define i32 @main(i32 %argc, i8** %argv) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pre-split2.ll b/libclamav/c++/llvm/test/CodeGen/X86/pre-split2.ll
index 2009ad8..ba902f9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pre-split2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pre-split2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
; RUN: grep {pre-alloc-split} | count 2
define i32 @t(i32 %arg) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pre-split3.ll b/libclamav/c++/llvm/test/CodeGen/X86/pre-split3.ll
index f34f144..2e31420 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pre-split3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pre-split3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
define i32 @t(i32 %arg) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pre-split4.ll b/libclamav/c++/llvm/test/CodeGen/X86/pre-split4.ll
index a570f73..10cef27 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pre-split4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pre-split4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 2
define i32 @main(i32 %argc, i8** %argv) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pre-split5.ll b/libclamav/c++/llvm/test/CodeGen/X86/pre-split5.ll
index b83003f..8def460 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pre-split5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pre-split5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split
target triple = "i386-apple-darwin9.5"
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pre-split6.ll b/libclamav/c++/llvm/test/CodeGen/X86/pre-split6.ll
index e771b80..d38e630 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pre-split6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pre-split6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split | grep {divsd 8} | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split | grep {divsd 8} | count 1
@current_surfaces.b = external global i1 ; <i1*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pre-split7.ll b/libclamav/c++/llvm/test/CodeGen/X86/pre-split7.ll
index cd9d205..0b81c0b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pre-split7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pre-split7.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split
@object_distance = external global double, align 8 ; <double*> [#uses=1]
@axis_slope_angle = external global double, align 8 ; <double*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pre-split8.ll b/libclamav/c++/llvm/test/CodeGen/X86/pre-split8.ll
index 2259819..ea4b949 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pre-split8.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pre-split8.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
@current_surfaces.b = external global i1 ; <i1*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/pre-split9.ll b/libclamav/c++/llvm/test/CodeGen/X86/pre-split9.ll
index 1be960f..c27d925 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/pre-split9.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/pre-split9.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
@current_surfaces.b = external global i1 ; <i1*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/prefetch.ll b/libclamav/c++/llvm/test/CodeGen/X86/prefetch.ll
index d6517f7..fac5915 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/prefetch.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/prefetch.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse > %t
+; RUN: llc < %s -march=x86 -mattr=+sse > %t
; RUN: grep prefetchnta %t
; RUN: grep prefetcht0 %t
; RUN: grep prefetcht1 %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/private-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/private-2.ll
index 7478128..8aa744e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/private-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/private-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10 | grep L__ZZ20
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | grep L__ZZ20
; Quote should be outside of private prefix.
; rdar://6855766x
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/private.ll b/libclamav/c++/llvm/test/CodeGen/X86/private.ll
index caf1035..22b6f35 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/private.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/private.ll
@@ -1,9 +1,9 @@
; Test to make sure that the 'private' is used correctly.
;
-; RUN: llvm-as < %s | llc -mtriple=x86_64-pc-linux | grep .Lfoo:
-; RUN: llvm-as < %s | llc -mtriple=x86_64-pc-linux | grep call.*\.Lfoo
-; RUN: llvm-as < %s | llc -mtriple=x86_64-pc-linux | grep .Lbaz:
-; RUN: llvm-as < %s | llc -mtriple=x86_64-pc-linux | grep movl.*\.Lbaz
+; RUN: llc < %s -mtriple=x86_64-pc-linux | grep .Lfoo:
+; RUN: llc < %s -mtriple=x86_64-pc-linux | grep call.*\.Lfoo
+; RUN: llc < %s -mtriple=x86_64-pc-linux | grep .Lbaz:
+; RUN: llc < %s -mtriple=x86_64-pc-linux | grep movl.*\.Lbaz
declare void @foo()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/ptrtoint-constexpr.ll b/libclamav/c++/llvm/test/CodeGen/X86/ptrtoint-constexpr.ll
index bd6aa07..72a428e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/ptrtoint-constexpr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/ptrtoint-constexpr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-linux | FileCheck %s
+; RUN: llc < %s -mtriple=i386-linux | FileCheck %s
%union.x = type { i64 }
; CHECK: .globl r
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/rdtsc.ll b/libclamav/c++/llvm/test/CodeGen/X86/rdtsc.ll
index f5d947f..f21a44c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/rdtsc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/rdtsc.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep rdtsc
-; RUN: llvm-as < %s | llc -march=x86-64 | grep rdtsc
+; RUN: llc < %s -march=x86 | grep rdtsc
+; RUN: llc < %s -march=x86-64 | grep rdtsc
declare i64 @llvm.readcyclecounter()
define i64 @foo() {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/red-zone.ll b/libclamav/c++/llvm/test/CodeGen/X86/red-zone.ll
index 405edba..1ffb4e3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/red-zone.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/red-zone.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86-64 | FileCheck %s
; First without noredzone.
; CHECK: f0:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/red-zone2.ll b/libclamav/c++/llvm/test/CodeGen/X86/red-zone2.ll
index dea7d7e..9557d17 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/red-zone2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/red-zone2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep subq %t | count 1
; RUN: grep addq %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/regpressure.ll b/libclamav/c++/llvm/test/CodeGen/X86/regpressure.ll
index 6d8cfbb..e0b5f7a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/regpressure.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/regpressure.ll
@@ -1,7 +1,7 @@
;; Both functions in this testcase should codegen to the same function, and
;; neither of them should require spilling anything to the stack.
-; RUN: llvm-as < %s | llc -march=x86 -stats |& \
+; RUN: llc < %s -march=x86 -stats |& \
; RUN: not grep {Number of register spills}
;; This can be compiled to use three registers if the loads are not
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/rem-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/rem-2.ll
index 3e17fc0..1b2af4b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/rem-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/rem-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep cltd
+; RUN: llc < %s -march=x86 | not grep cltd
define i32 @test(i32 %X) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/rem.ll b/libclamav/c++/llvm/test/CodeGen/X86/rem.ll
index bba1f9b..394070e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/rem.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/rem.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep div
+; RUN: llc < %s -march=x86 | not grep div
define i32 @test1(i32 %X) {
%tmp1 = srem i32 %X, 255 ; <i32> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/remat-constant.ll b/libclamav/c++/llvm/test/CodeGen/X86/remat-constant.ll
index 8dfed5e..3e81320 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/remat-constant.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/remat-constant.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-linux -relocation-model=static | grep xmm | count 2
+; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static | grep xmm | count 2
declare void @bar() nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/remat-mov-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/remat-mov-1.ll
index 98b7bb4..d71b7a5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/remat-mov-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/remat-mov-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep 4294967295 | grep mov | count 2
+; RUN: llc < %s -march=x86 | grep -- -1 | grep mov | count 2
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.ImgT = type { i8, i8*, i8*, %struct.FILE*, i32, i32, i32, i32, i8*, double*, float*, float*, float*, i32*, double, double, i32*, double*, i32*, i32* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/remat-scalar-zero.ll b/libclamav/c++/llvm/test/CodeGen/X86/remat-scalar-zero.ll
new file mode 100644
index 0000000..790ae83
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/remat-scalar-zero.ll
@@ -0,0 +1,95 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu > %t
+; RUN: not grep xor %t
+; RUN: not grep movap %t
+; RUN: grep {\\.zero} %t
+
+; Remat should be able to fold the zero constant into the div instructions
+; as a constant-pool load.
+
+define void @foo(double* nocapture %x, double* nocapture %y) nounwind {
+entry:
+ %tmp1 = load double* %x ; <double> [#uses=1]
+ %arrayidx4 = getelementptr inbounds double* %x, i64 1 ; <double*> [#uses=1]
+ %tmp5 = load double* %arrayidx4 ; <double> [#uses=1]
+ %arrayidx8 = getelementptr inbounds double* %x, i64 2 ; <double*> [#uses=1]
+ %tmp9 = load double* %arrayidx8 ; <double> [#uses=1]
+ %arrayidx12 = getelementptr inbounds double* %x, i64 3 ; <double*> [#uses=1]
+ %tmp13 = load double* %arrayidx12 ; <double> [#uses=1]
+ %arrayidx16 = getelementptr inbounds double* %x, i64 4 ; <double*> [#uses=1]
+ %tmp17 = load double* %arrayidx16 ; <double> [#uses=1]
+ %arrayidx20 = getelementptr inbounds double* %x, i64 5 ; <double*> [#uses=1]
+ %tmp21 = load double* %arrayidx20 ; <double> [#uses=1]
+ %arrayidx24 = getelementptr inbounds double* %x, i64 6 ; <double*> [#uses=1]
+ %tmp25 = load double* %arrayidx24 ; <double> [#uses=1]
+ %arrayidx28 = getelementptr inbounds double* %x, i64 7 ; <double*> [#uses=1]
+ %tmp29 = load double* %arrayidx28 ; <double> [#uses=1]
+ %arrayidx32 = getelementptr inbounds double* %x, i64 8 ; <double*> [#uses=1]
+ %tmp33 = load double* %arrayidx32 ; <double> [#uses=1]
+ %arrayidx36 = getelementptr inbounds double* %x, i64 9 ; <double*> [#uses=1]
+ %tmp37 = load double* %arrayidx36 ; <double> [#uses=1]
+ %arrayidx40 = getelementptr inbounds double* %x, i64 10 ; <double*> [#uses=1]
+ %tmp41 = load double* %arrayidx40 ; <double> [#uses=1]
+ %arrayidx44 = getelementptr inbounds double* %x, i64 11 ; <double*> [#uses=1]
+ %tmp45 = load double* %arrayidx44 ; <double> [#uses=1]
+ %arrayidx48 = getelementptr inbounds double* %x, i64 12 ; <double*> [#uses=1]
+ %tmp49 = load double* %arrayidx48 ; <double> [#uses=1]
+ %arrayidx52 = getelementptr inbounds double* %x, i64 13 ; <double*> [#uses=1]
+ %tmp53 = load double* %arrayidx52 ; <double> [#uses=1]
+ %arrayidx56 = getelementptr inbounds double* %x, i64 14 ; <double*> [#uses=1]
+ %tmp57 = load double* %arrayidx56 ; <double> [#uses=1]
+ %arrayidx60 = getelementptr inbounds double* %x, i64 15 ; <double*> [#uses=1]
+ %tmp61 = load double* %arrayidx60 ; <double> [#uses=1]
+ %arrayidx64 = getelementptr inbounds double* %x, i64 16 ; <double*> [#uses=1]
+ %tmp65 = load double* %arrayidx64 ; <double> [#uses=1]
+ %div = fdiv double %tmp1, 0.000000e+00 ; <double> [#uses=1]
+ store double %div, double* %y
+ %div70 = fdiv double %tmp5, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx72 = getelementptr inbounds double* %y, i64 1 ; <double*> [#uses=1]
+ store double %div70, double* %arrayidx72
+ %div74 = fdiv double %tmp9, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx76 = getelementptr inbounds double* %y, i64 2 ; <double*> [#uses=1]
+ store double %div74, double* %arrayidx76
+ %div78 = fdiv double %tmp13, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx80 = getelementptr inbounds double* %y, i64 3 ; <double*> [#uses=1]
+ store double %div78, double* %arrayidx80
+ %div82 = fdiv double %tmp17, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx84 = getelementptr inbounds double* %y, i64 4 ; <double*> [#uses=1]
+ store double %div82, double* %arrayidx84
+ %div86 = fdiv double %tmp21, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx88 = getelementptr inbounds double* %y, i64 5 ; <double*> [#uses=1]
+ store double %div86, double* %arrayidx88
+ %div90 = fdiv double %tmp25, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx92 = getelementptr inbounds double* %y, i64 6 ; <double*> [#uses=1]
+ store double %div90, double* %arrayidx92
+ %div94 = fdiv double %tmp29, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx96 = getelementptr inbounds double* %y, i64 7 ; <double*> [#uses=1]
+ store double %div94, double* %arrayidx96
+ %div98 = fdiv double %tmp33, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx100 = getelementptr inbounds double* %y, i64 8 ; <double*> [#uses=1]
+ store double %div98, double* %arrayidx100
+ %div102 = fdiv double %tmp37, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx104 = getelementptr inbounds double* %y, i64 9 ; <double*> [#uses=1]
+ store double %div102, double* %arrayidx104
+ %div106 = fdiv double %tmp41, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx108 = getelementptr inbounds double* %y, i64 10 ; <double*> [#uses=1]
+ store double %div106, double* %arrayidx108
+ %div110 = fdiv double %tmp45, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx112 = getelementptr inbounds double* %y, i64 11 ; <double*> [#uses=1]
+ store double %div110, double* %arrayidx112
+ %div114 = fdiv double %tmp49, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx116 = getelementptr inbounds double* %y, i64 12 ; <double*> [#uses=1]
+ store double %div114, double* %arrayidx116
+ %div118 = fdiv double %tmp53, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx120 = getelementptr inbounds double* %y, i64 13 ; <double*> [#uses=1]
+ store double %div118, double* %arrayidx120
+ %div122 = fdiv double %tmp57, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx124 = getelementptr inbounds double* %y, i64 14 ; <double*> [#uses=1]
+ store double %div122, double* %arrayidx124
+ %div126 = fdiv double %tmp61, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx128 = getelementptr inbounds double* %y, i64 15 ; <double*> [#uses=1]
+ store double %div126, double* %arrayidx128
+ %div130 = fdiv double %tmp65, 0.000000e+00 ; <double> [#uses=1]
+ %arrayidx132 = getelementptr inbounds double* %y, i64 16 ; <double*> [#uses=1]
+ store double %div130, double* %arrayidx132
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/ret-addr.ll b/libclamav/c++/llvm/test/CodeGen/X86/ret-addr.ll
index 06a10c6..b7b57ab 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/ret-addr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/ret-addr.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -disable-fp-elim -march=x86 | not grep xor
-; RUN: llvm-as < %s | llc -disable-fp-elim -march=x86-64 | not grep xor
+; RUN: llc < %s -disable-fp-elim -march=x86 | not grep xor
+; RUN: llc < %s -disable-fp-elim -march=x86-64 | not grep xor
define i8* @h() nounwind readnone optsize {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/ret-i64-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/ret-i64-0.ll
index c59e4cf..bca0f05 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/ret-i64-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/ret-i64-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep xor | count 2
+; RUN: llc < %s -march=x86 | grep xor | count 2
define i64 @foo() nounwind {
ret i64 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/ret-mmx.ll b/libclamav/c++/llvm/test/CodeGen/X86/ret-mmx.ll
index 178ff4e..04b57dd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/ret-mmx.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/ret-mmx.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx,+sse2
+; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2
; rdar://6602459
@g_v1di = external global <1 x i64>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/rip-rel-address.ll b/libclamav/c++/llvm/test/CodeGen/X86/rip-rel-address.ll
index a41b8a9..24ff07b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/rip-rel-address.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/rip-rel-address.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=pic -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=PIC64
-; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu -relocation-model=static | FileCheck %s -check-prefix=STATIC64
+; RUN: llc < %s -march=x86-64 -relocation-model=pic -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=PIC64
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -relocation-model=static | FileCheck %s -check-prefix=STATIC64
; Use %rip-relative addressing even in static mode on x86-64, because
; it has a smaller encoding.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/rodata-relocs.ll b/libclamav/c++/llvm/test/CodeGen/X86/rodata-relocs.ll
index b800e09..276f8bb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/rodata-relocs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/rodata-relocs.ll
@@ -1,10 +1,10 @@
-; RUN: llvm-as < %s | llc -relocation-model=static | grep rodata | count 3
-; RUN: llvm-as < %s | llc -relocation-model=static | grep -F "rodata.cst" | count 2
-; RUN: llvm-as < %s | llc -relocation-model=pic | grep rodata | count 2
-; RUN: llvm-as < %s | llc -relocation-model=pic | grep -F ".data.rel.ro" | count 2
-; RUN: llvm-as < %s | llc -relocation-model=pic | grep -F ".data.rel.ro.local" | count 1
-; RUN: llvm-as < %s | llc -relocation-model=pic | grep -F ".data.rel" | count 4
-; RUN: llvm-as < %s | llc -relocation-model=pic | grep -F ".data.rel.local" | count 1
+; RUN: llc < %s -relocation-model=static | grep rodata | count 3
+; RUN: llc < %s -relocation-model=static | grep -F "rodata.cst" | count 2
+; RUN: llc < %s -relocation-model=pic | grep rodata | count 2
+; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.ro" | count 2
+; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.ro.local" | count 1
+; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel" | count 4
+; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.local" | count 1
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/rot16.ll b/libclamav/c++/llvm/test/CodeGen/X86/rot16.ll
index c196ce2..42ece47 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/rot16.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/rot16.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: grep rol %t | count 3
; RUN: grep ror %t | count 1
; RUN: grep shld %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/rot32.ll b/libclamav/c++/llvm/test/CodeGen/X86/rot32.ll
index 7cebcb8..655ed27 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/rot32.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/rot32.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: grep rol %t | count 3
; RUN: grep ror %t | count 1
; RUN: grep shld %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/rot64.ll b/libclamav/c++/llvm/test/CodeGen/X86/rot64.ll
index 2408359..4e082bb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/rot64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/rot64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep rol %t | count 3
; RUN: grep ror %t | count 1
; RUN: grep shld %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/rotate.ll b/libclamav/c++/llvm/test/CodeGen/X86/rotate.ll
index c567c0d..1e20273 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/rotate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/rotate.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {ro\[rl\]} | count 12
define i32 @rotl32(i32 %A, i8 %Amt) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/rotate2.ll b/libclamav/c++/llvm/test/CodeGen/X86/rotate2.ll
index 40e954c..2eea399 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/rotate2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/rotate2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep rol | count 2
+; RUN: llc < %s -march=x86-64 | grep rol | count 2
define i64 @test1(i64 %x) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/scalar-extract.ll b/libclamav/c++/llvm/test/CodeGen/X86/scalar-extract.ll
index f545bb6..2845838 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/scalar-extract.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/scalar-extract.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+mmx -o %t
; RUN: not grep movq %t
; Check that widening doesn't introduce a mmx register in this case when
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/scalar-min-max-fill-operand.ll b/libclamav/c++/llvm/test/CodeGen/X86/scalar-min-max-fill-operand.ll
index 6a6283a..fe40758 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/scalar-min-max-fill-operand.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/scalar-min-max-fill-operand.ll
@@ -1,20 +1,20 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep min | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 | grep max | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 2
+; RUN: llc < %s -march=x86-64 | grep min | count 1
+; RUN: llc < %s -march=x86-64 | grep max | count 1
+; RUN: llc < %s -march=x86-64 | grep mov | count 2
declare float @bar()
-define float @foo(float %a)
+define float @foo(float %a) nounwind
{
%s = call float @bar()
%t = fcmp olt float %s, %a
%u = select i1 %t, float %s, float %a
ret float %u
}
-define float @hem(float %a)
+define float @hem(float %a) nounwind
{
%s = call float @bar()
- %t = fcmp uge float %s, %a
+ %t = fcmp ogt float %s, %a
%u = select i1 %t, float %s, float %a
ret float %u
}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/scalar_sse_minmax.ll b/libclamav/c++/llvm/test/CodeGen/X86/scalar_sse_minmax.ll
index 8c030b8..bc4ab5d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/scalar_sse_minmax.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/scalar_sse_minmax.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,+sse2 | \
+; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 | \
; RUN: grep mins | count 3
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,+sse2 | \
+; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 | \
; RUN: grep maxs | count 2
declare i1 @llvm.isunordered.f64(double, double)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/scalarize-bitcast.ll b/libclamav/c++/llvm/test/CodeGen/X86/scalarize-bitcast.ll
index a07f939..f6b29ec 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/scalarize-bitcast.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/scalarize-bitcast.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
; PR3886
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/scev-interchange.ll b/libclamav/c++/llvm/test/CodeGen/X86/scev-interchange.ll
index fcb70bc..81c919f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/scev-interchange.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/scev-interchange.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
%"struct.DataOutBase::GmvFlags" = type { i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/select-i8.ll b/libclamav/c++/llvm/test/CodeGen/X86/select-i8.ll
deleted file mode 100644
index 8b2444d..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/select-i8.ll
+++ /dev/null
@@ -1,12 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
-; RUN: not grep movz %t
-; RUN: not grep cmov %t
-; RUN: grep movb %t | count 2
-
-; Don't try to use a 16-bit conditional move to do an 8-bit select,
-; because it isn't worth it. Just use a branch instead.
-
-define i8 @foo(i1 inreg %c, i8 inreg %a, i8 inreg %b) {
- %d = select i1 %c, i8 %a, i8 %b
- ret i8 %d
-}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/select-no-cmov.ll b/libclamav/c++/llvm/test/CodeGen/X86/select-no-cmov.ll
deleted file mode 100644
index 71636f9..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/select-no-cmov.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: llvm-as < %s | llc | not grep cmov
-
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
-target triple = "i386-apple-darwin7"
-
-; Should compile to setcc | -2.
-; rdar://6668608
-define i32 @test(i32* nocapture %P) nounwind readonly {
-entry:
- %0 = load i32* %P, align 4 ; <i32> [#uses=1]
- %1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1]
- %iftmp.0.0 = select i1 %1, i32 -1, i32 -2 ; <i32> [#uses=1]
- ret i32 %iftmp.0.0
-}
-
-; setl %al
-; movzbl %al, %eax
-; leal 4(%eax,%eax,8), %eax
-define i32 @test2(i32* nocapture %P) nounwind readonly {
-entry:
- %0 = load i32* %P, align 4 ; <i32> [#uses=1]
- %1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1]
- %iftmp.0.0 = select i1 %1, i32 4, i32 13 ; <i32> [#uses=1]
- ret i32 %iftmp.0.0
-}
-
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/select-zero-one.ll b/libclamav/c++/llvm/test/CodeGen/X86/select-zero-one.ll
index 70785e9..c38a020 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/select-zero-one.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/select-zero-one.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep cmov
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep xor
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movzbl | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep cmov
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xor
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movzbl | count 1
@r1 = weak global i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/select.ll b/libclamav/c++/llvm/test/CodeGen/X86/select.ll
index e5d6101..95ed9e9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/select.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/select.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not grep set
+; RUN: llc < %s -march=x86 -mcpu=pentium
+; RUN: llc < %s -march=x86 -mcpu=yonah
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep set
define i1 @boolSel(i1 %A, i1 %B, i1 %C) nounwind {
%X = select i1 %A, i1 %B, i1 %C ; <i1> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/setoeq.ll b/libclamav/c++/llvm/test/CodeGen/X86/setoeq.ll
index 25a2b7e..4a9c1ba 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/setoeq.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/setoeq.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep set | count 2
-; RUN: llvm-as < %s | llc -march=x86 | grep and
+; RUN: llc < %s -march=x86 | grep set | count 2
+; RUN: llc < %s -march=x86 | grep and
define zeroext i8 @t(double %x) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/setuge.ll b/libclamav/c++/llvm/test/CodeGen/X86/setuge.ll
index 3f1d882..4ca2f18 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/setuge.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/setuge.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep set
+; RUN: llc < %s -march=x86 | not grep set
declare i1 @llvm.isunordered.f32(float, float)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sext-load.ll b/libclamav/c++/llvm/test/CodeGen/X86/sext-load.ll
index a6d1080..c9b39d3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sext-load.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sext-load.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep movsbl
+; RUN: llc < %s -march=x86 | grep movsbl
define i32 @foo(i32 %X) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sext-ret-val.ll b/libclamav/c++/llvm/test/CodeGen/X86/sext-ret-val.ll
index 946e6c7..da1a187 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sext-ret-val.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sext-ret-val.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep movzbl | count 1
+; RUN: llc < %s -march=x86 | grep movzbl | count 1
; rdar://6699246
define signext i8 @t1(i8* %A) nounwind readnone ssp {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sext-select.ll b/libclamav/c++/llvm/test/CodeGen/X86/sext-select.ll
index 839ebc2..4aca040 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sext-select.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sext-select.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep movsw
+; RUN: llc < %s -march=x86 | grep movsw
; PR2139
declare void @abort()
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sext-trunc.ll b/libclamav/c++/llvm/test/CodeGen/X86/sext-trunc.ll
index 97b4666..2eaf425 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sext-trunc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sext-trunc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: llc < %s -march=x86 > %t
; RUN: grep movsbl %t
; RUN: not grep movz %t
; RUN: not grep and %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sfence.ll b/libclamav/c++/llvm/test/CodeGen/X86/sfence.ll
index fc75ccb..4782879 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sfence.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sfence.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep sfence
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep sfence
declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shift-and.ll b/libclamav/c++/llvm/test/CodeGen/X86/shift-and.ll
index b6d78a4..fd278c2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shift-and.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shift-and.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep and | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep and
+; RUN: llc < %s -march=x86 | grep and | count 1
+; RUN: llc < %s -march=x86-64 | not grep and
define i32 @t1(i32 %t, i32 %val) nounwind {
%shamt = and i32 %t, 31
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shift-coalesce.ll b/libclamav/c++/llvm/test/CodeGen/X86/shift-coalesce.ll
index 4662628..d38f9a8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shift-coalesce.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shift-coalesce.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {shld.*CL}
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: not grep {mov CL, BL}
; PR687
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shift-codegen.ll b/libclamav/c++/llvm/test/CodeGen/X86/shift-codegen.ll
index deb4ed1..4cba183 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shift-codegen.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shift-codegen.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -relocation-model=static -march=x86 | \
+; RUN: llc < %s -relocation-model=static -march=x86 | \
; RUN: grep {shll \$3} | count 2
; This should produce two shll instructions, not any lea's.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shift-combine.ll b/libclamav/c++/llvm/test/CodeGen/X86/shift-combine.ll
index 543bb22..e443ac1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shift-combine.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shift-combine.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | not grep shrl
+; RUN: llc < %s | not grep shrl
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shift-double.ll b/libclamav/c++/llvm/test/CodeGen/X86/shift-double.ll
index 24017fe..5adee7c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shift-double.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shift-double.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {sh\[lr\]d} | count 5
define i64 @test1(i64 %X, i8 %C) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shift-folding.ll b/libclamav/c++/llvm/test/CodeGen/X86/shift-folding.ll
index d268232..872817f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shift-folding.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shift-folding.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | \
+; RUN: llc < %s -march=x86 | \
; RUN: grep {s\[ah\]\[rl\]l} | count 1
define i32* @test1(i32* %P, i32 %X) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shift-i128.ll b/libclamav/c++/llvm/test/CodeGen/X86/shift-i128.ll
index fc22a3c..c4d15ae 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shift-i128.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shift-i128.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
define void @t(i128 %x, i128 %a, i128* nocapture %r) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shift-i256.ll b/libclamav/c++/llvm/test/CodeGen/X86/shift-i256.ll
index 4a29b86..d5f65a6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shift-i256.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shift-i256.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
define void @t(i256 %x, i256 %a, i256* nocapture %r) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shift-one.ll b/libclamav/c++/llvm/test/CodeGen/X86/shift-one.ll
index dd49b7e..0f80f90 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shift-one.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shift-one.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep leal
+; RUN: llc < %s -march=x86 | not grep leal
@x = external global i32 ; <i32*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shift-parts.ll b/libclamav/c++/llvm/test/CodeGen/X86/shift-parts.ll
index a09b417..ce4f538 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shift-parts.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shift-parts.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep shrdq
+; RUN: llc < %s -march=x86-64 | grep shrdq
; PR4736
%0 = type { i32, i8, [35 x i8] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shl_elim.ll b/libclamav/c++/llvm/test/CodeGen/X86/shl_elim.ll
index d3616f4..4458891 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shl_elim.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shl_elim.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {movl 8(.esp), %eax}
-; RUN: llvm-as < %s | llc -march=x86 | grep {shrl .eax}
-; RUN: llvm-as < %s | llc -march=x86 | grep {movswl .ax, .eax}
+; RUN: llc < %s -march=x86 | grep {movl 8(.esp), %eax}
+; RUN: llc < %s -march=x86 | grep {shrl .eax}
+; RUN: llc < %s -march=x86 | grep {movswl .ax, .eax}
define i32 @test1(i64 %a) {
%tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shrink-fp-const1.ll b/libclamav/c++/llvm/test/CodeGen/X86/shrink-fp-const1.ll
index 3406aee..49b9fa3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shrink-fp-const1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shrink-fp-const1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2 | not grep cvtss2sd
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | not grep cvtss2sd
; PR1264
define double @foo(double %x) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/shrink-fp-const2.ll b/libclamav/c++/llvm/test/CodeGen/X86/shrink-fp-const2.ll
index 7e48b1b..3d5203b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/shrink-fp-const2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/shrink-fp-const2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep flds
+; RUN: llc < %s -march=x86 | grep flds
; This should be a flds, not fldt.
define x86_fp80 @test2() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sincos.ll b/libclamav/c++/llvm/test/CodeGen/X86/sincos.ll
index 2721595..13f9329 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sincos.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sincos.ll
@@ -1,50 +1,48 @@
; Make sure this testcase codegens to the sin and cos instructions, not calls
-; RUN: llvm-as < %s | \
-; RUN: llc -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
+; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
; RUN: grep sin\$ | count 3
-; RUN: llvm-as < %s | \
-; RUN: llc -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
+; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
; RUN: grep cos\$ | count 3
-declare float @sinf(float)
+declare float @sinf(float) readonly
-declare double @sin(double)
+declare double @sin(double) readonly
-declare x86_fp80 @sinl(x86_fp80)
+declare x86_fp80 @sinl(x86_fp80) readonly
define float @test1(float %X) {
- %Y = call float @sinf(float %X)
+ %Y = call float @sinf(float %X) readonly
ret float %Y
}
define double @test2(double %X) {
- %Y = call double @sin(double %X)
+ %Y = call double @sin(double %X) readonly
ret double %Y
}
define x86_fp80 @test3(x86_fp80 %X) {
- %Y = call x86_fp80 @sinl(x86_fp80 %X)
+ %Y = call x86_fp80 @sinl(x86_fp80 %X) readonly
ret x86_fp80 %Y
}
-declare float @cosf(float)
+declare float @cosf(float) readonly
-declare double @cos(double)
+declare double @cos(double) readonly
-declare x86_fp80 @cosl(x86_fp80)
+declare x86_fp80 @cosl(x86_fp80) readonly
define float @test4(float %X) {
- %Y = call float @cosf(float %X)
+ %Y = call float @cosf(float %X) readonly
ret float %Y
}
define double @test5(double %X) {
- %Y = call double @cos(double %X)
+ %Y = call double @cos(double %X) readonly
ret double %Y
}
define x86_fp80 @test6(x86_fp80 %X) {
- %Y = call x86_fp80 @cosl(x86_fp80 %X)
+ %Y = call x86_fp80 @cosl(x86_fp80 %X) readonly
ret x86_fp80 %Y
}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sink-hoist.ll b/libclamav/c++/llvm/test/CodeGen/X86/sink-hoist.ll
new file mode 100644
index 0000000..0f4e63f
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sink-hoist.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s
+
+; Currently, floating-point selects are lowered to CFG triangles.
+; This means that one side of the select is always unconditionally
+; evaluated, however with MachineSink we can sink the other side so
+; that it's conditionally evaluated.
+
+; CHECK: foo:
+; CHECK-NEXT: divsd
+; CHECK: testb $1, %dil
+; CHECK-NEXT: jne
+; CHECK: divsd
+
+define double @foo(double %x, double %y, i1 %c) nounwind {
+ %a = fdiv double %x, 3.2
+ %b = fdiv double %y, 3.3
+ %z = select i1 %c, double %a, double %b
+ ret double %z
+}
+
+; Hoist floating-point constant-pool loads out of loops.
+
+; CHECK: bar:
+; CHECK: movsd
+; CHECK: align
+define void @bar(double* nocapture %p, i64 %n) nounwind {
+entry:
+ %0 = icmp sgt i64 %n, 0
+ br i1 %0, label %bb, label %return
+
+bb:
+ %i.03 = phi i64 [ 0, %entry ], [ %3, %bb ]
+ %scevgep = getelementptr double* %p, i64 %i.03
+ %1 = load double* %scevgep, align 8
+ %2 = fdiv double 3.200000e+00, %1
+ store double %2, double* %scevgep, align 8
+ %3 = add nsw i64 %i.03, 1
+ %exitcond = icmp eq i64 %3, %n
+ br i1 %exitcond, label %return, label %bb
+
+return:
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/small-byval-memcpy.ll b/libclamav/c++/llvm/test/CodeGen/X86/small-byval-memcpy.ll
index 8b87f74..9ec9182 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/small-byval-memcpy.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/small-byval-memcpy.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | not grep movs
+; RUN: llc < %s | not grep movs
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow-2.ll
index c3dbfd7..7c23adb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mul | count 1
-; RUN: llvm-as < %s | llc -march=x86 | grep add | count 3
+; RUN: llc < %s -march=x86 | grep mul | count 1
+; RUN: llc < %s -march=x86 | grep add | count 3
define i32 @t1(i32 %a, i32 %b) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow-3.ll
index aa5e67a..49c31f5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {jno} | count 1
+; RUN: llc < %s -march=x86 | grep {jno} | count 1
@ok = internal constant [4 x i8] c"%d\0A\00"
@no = internal constant [4 x i8] c"no\0A\00"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow.ll b/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow.ll
index 6aefc03..6d125e4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/smul-with-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 1
+; RUN: llc < %s -march=x86 | grep {jo} | count 1
@ok = internal constant [4 x i8] c"%d\0A\00"
@no = internal constant [4 x i8] c"no\0A\00"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/soft-fp.ll b/libclamav/c++/llvm/test/CodeGen/X86/soft-fp.ll
index 0c697de..a52135d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/soft-fp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/soft-fp.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -soft-float | not grep xmm
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2 -soft-float | not grep xmm
+; RUN: llc < %s -march=x86 -mattr=+sse2 -soft-float | not grep xmm
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 -soft-float | not grep xmm
%struct.__va_list_tag = type { i32, i32, i8*, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/split-eh-lpad-edges.ll b/libclamav/c++/llvm/test/CodeGen/X86/split-eh-lpad-edges.ll
index 281ee77..fd40a7f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/split-eh-lpad-edges.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/split-eh-lpad-edges.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep jmp
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep jmp
; rdar://6647639
%struct.FetchPlanHeader = type { i8*, i8*, i32, i8*, i8*, i8*, i8*, i8*, %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)*, %struct.__attributeDescriptionFlags }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/split-select.ll b/libclamav/c++/llvm/test/CodeGen/X86/split-select.ll
index 0b7804d..07d4d52 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/split-select.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/split-select.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep test | count 1
+; RUN: llc < %s -march=x86-64 | grep test | count 1
define void @foo(i1 %c, <2 x i16> %a, <2 x i16> %b, <2 x i16>* %p) {
%x = select i1 %c, <2 x i16> %a, <2 x i16> %b
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/split-vector-rem.ll b/libclamav/c++/llvm/test/CodeGen/X86/split-vector-rem.ll
index 8c88769..681c6b0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/split-vector-rem.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/split-vector-rem.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep div | count 16
-; RUN: llvm-as < %s | llc -march=x86-64 | grep fmodf | count 8
+; RUN: llc < %s -march=x86-64 | grep div | count 16
+; RUN: llc < %s -march=x86-64 | grep fmodf | count 8
define <8 x i32> @foo(<8 x i32> %t, <8 x i32> %u) {
%m = srem <8 x i32> %t, %u
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sret.ll b/libclamav/c++/llvm/test/CodeGen/X86/sret.ll
index 30e5af4..b945530 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sret.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sret.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep ret | grep 4
+; RUN: llc < %s -march=x86 | grep ret | grep 4
%struct.foo = type { [4 x i32] }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-0.ll
index 5a888b2..b12a87d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep mov
+; RUN: llc < %s -march=x86-64 | not grep mov
define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
%t = load <4 x float>* %p
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-1.ll
index 0edc6e0..c7a5cd5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movap | count 2
+; RUN: llc < %s -march=x86-64 | grep movap | count 2
define <4 x float> @foo(<4 x float>* %p) nounwind {
%t = load <4 x float>* %p
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-10.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-10.ll
index 1a23eb2..0f91697 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-10.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-10.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movups | count 1
+; RUN: llc < %s -march=x86-64 | grep movups | count 1
define <2 x i64> @bar(<2 x i64>* %p) nounwind {
%t = load <2 x i64>* %p, align 8
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-11.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-11.ll
index a10b102..aa1b437 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-11.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-11.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah -mtriple=i686-apple-darwin8 | grep movaps
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah -mtriple=linux | grep movups
+; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=i686-apple-darwin8 | grep movaps
+; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=linux | grep movups
define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-12.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-12.ll
index 297f1c4..4f025b9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-12.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-12.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep unpck %t | count 2
; RUN: grep shuf %t | count 2
; RUN: grep ps %t | count 4
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-2.ll
index ba693a2..102c3fb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movup | count 2
+; RUN: llc < %s -march=x86-64 | grep movup | count 2
define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
%t = load <4 x float>* %p, align 4
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-3.ll
index 5bbcd59..c42f7f0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movap | count 2
+; RUN: llc < %s -march=x86-64 | grep movap | count 2
define void @foo(<4 x float>* %p, <4 x float> %x) nounwind {
store <4 x float> %x, <4 x float>* %p
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-4.ll
index f7e5fe3..4c59934 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movup | count 2
+; RUN: llc < %s -march=x86-64 | grep movup | count 2
define void @foo(<4 x float>* %p, <4 x float> %x) nounwind {
store <4 x float> %x, <4 x float>* %p, align 4
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-5.ll
index 19e0eaf..21cd231 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movaps | count 1
+; RUN: llc < %s -march=x86-64 | grep movaps | count 1
define <2 x i64> @bar(<2 x i64>* %p) nounwind {
%t = load <2 x i64>* %p
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-6.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-6.ll
index dace291..0bbf422 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movups | count 1
+; RUN: llc < %s -march=x86-64 | grep movups | count 1
define <2 x i64> @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
%t = load <2 x i64>* %p, align 8
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-7.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-7.ll
index 7fb65b5..5784481 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-7.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movaps | count 1
+; RUN: llc < %s -march=x86-64 | grep movaps | count 1
define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
store <2 x i64> %x, <2 x i64>* %p
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-8.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-8.ll
index 17a3d29..cfeff81 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-8.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-8.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movups | count 1
+; RUN: llc < %s -march=x86-64 | grep movups | count 1
define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
store <2 x i64> %x, <2 x i64>* %p, align 8
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-9.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-9.ll
index 24b437a..cb26b95 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-align-9.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-align-9.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movup | count 2
+; RUN: llc < %s -march=x86-64 | grep movup | count 2
define <4 x float> @foo(<4 x float>* %p) nounwind {
%t = load <4 x float>* %p, align 4
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-fcopysign.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-fcopysign.ll
index d8c3283..0e0e4a9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-fcopysign.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-fcopysign.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep test
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep test
define float @tst1(float %a, float %b) {
%tmp = tail call float @copysignf( float %b, float %a )
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-load-ret.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-load-ret.ll
index cbf3eb0..1ebcb1a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-load-ret.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-load-ret.ll
@@ -1,7 +1,5 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=x86 -mcpu=yonah | not grep movss
-; RUN: llvm-as < %s | \
-; RUN: llc -march=x86 -mcpu=yonah | not grep xmm
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep movss
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep xmm
define double @test1(double* %P) {
%X = load double* %P ; <double> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-minmax.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-minmax.ll
new file mode 100644
index 0000000..17ffb5e
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-minmax.ll
@@ -0,0 +1,392 @@
+; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s
+
+; Some of these patterns can be matched as SSE min or max. Some of
+; then can be matched provided that the operands are swapped.
+; Some of them can't be matched at all and require a comparison
+; and a conditional branch.
+
+; The naming convention is {,x_}{o,u}{gt,lt,ge,le}{,_inverse}
+; x_ : use 0.0 instead of %y
+; _inverse : swap the arms of the select.
+
+; CHECK: ogt:
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @ogt(double %x, double %y) nounwind {
+ %c = fcmp ogt double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: olt:
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @olt(double %x, double %y) nounwind {
+ %c = fcmp olt double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: ogt_inverse:
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @ogt_inverse(double %x, double %y) nounwind {
+ %c = fcmp ogt double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: olt_inverse:
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @olt_inverse(double %x, double %y) nounwind {
+ %c = fcmp olt double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: oge:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+define double @oge(double %x, double %y) nounwind {
+ %c = fcmp oge double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: ole:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+define double @ole(double %x, double %y) nounwind {
+ %c = fcmp ole double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: oge_inverse:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+define double @oge_inverse(double %x, double %y) nounwind {
+ %c = fcmp oge double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: ole_inverse:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+define double @ole_inverse(double %x, double %y) nounwind {
+ %c = fcmp ole double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: x_ogt:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ogt(double %x) nounwind {
+ %c = fcmp ogt double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_olt:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_olt(double %x) nounwind {
+ %c = fcmp olt double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_ogt_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ogt_inverse(double %x) nounwind {
+ %c = fcmp ogt double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_olt_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_olt_inverse(double %x) nounwind {
+ %c = fcmp olt double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_oge:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_oge(double %x) nounwind {
+ %c = fcmp oge double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_ole:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ole(double %x) nounwind {
+ %c = fcmp ole double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_oge_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_oge_inverse(double %x) nounwind {
+ %c = fcmp oge double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_ole_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ole_inverse(double %x) nounwind {
+ %c = fcmp ole double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: ugt:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+define double @ugt(double %x, double %y) nounwind {
+ %c = fcmp ugt double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: ult:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+define double @ult(double %x, double %y) nounwind {
+ %c = fcmp ult double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: ugt_inverse:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+define double @ugt_inverse(double %x, double %y) nounwind {
+ %c = fcmp ugt double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: ult_inverse:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+define double @ult_inverse(double %x, double %y) nounwind {
+ %c = fcmp ult double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: uge:
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @uge(double %x, double %y) nounwind {
+ %c = fcmp uge double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: ule:
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @ule(double %x, double %y) nounwind {
+ %c = fcmp ule double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: uge_inverse:
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @uge_inverse(double %x, double %y) nounwind {
+ %c = fcmp uge double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: ule_inverse:
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @ule_inverse(double %x, double %y) nounwind {
+ %c = fcmp ule double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: x_ugt:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ugt(double %x) nounwind {
+ %c = fcmp ugt double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_ult:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ult(double %x) nounwind {
+ %c = fcmp ult double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_ugt_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ugt_inverse(double %x) nounwind {
+ %c = fcmp ugt double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_ult_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ult_inverse(double %x) nounwind {
+ %c = fcmp ult double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_uge:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_uge(double %x) nounwind {
+ %c = fcmp uge double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_ule:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ule(double %x) nounwind {
+ %c = fcmp ule double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_uge_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_uge_inverse(double %x) nounwind {
+ %c = fcmp uge double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_ule_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ule_inverse(double %x) nounwind {
+ %c = fcmp ule double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; Test a few more misc. cases.
+
+; CHECK: clampTo3k_a:
+; CHECK: minsd
+define double @clampTo3k_a(double %x) nounwind readnone {
+entry:
+ %0 = fcmp ogt double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_b:
+; CHECK: minsd
+define double @clampTo3k_b(double %x) nounwind readnone {
+entry:
+ %0 = fcmp uge double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_c:
+; CHECK: maxsd
+define double @clampTo3k_c(double %x) nounwind readnone {
+entry:
+ %0 = fcmp olt double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_d:
+; CHECK: maxsd
+define double @clampTo3k_d(double %x) nounwind readnone {
+entry:
+ %0 = fcmp ule double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_e:
+; CHECK: maxsd
+define double @clampTo3k_e(double %x) nounwind readnone {
+entry:
+ %0 = fcmp olt double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_f:
+; CHECK: maxsd
+define double @clampTo3k_f(double %x) nounwind readnone {
+entry:
+ %0 = fcmp ule double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_g:
+; CHECK: minsd
+define double @clampTo3k_g(double %x) nounwind readnone {
+entry:
+ %0 = fcmp ogt double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_h:
+; CHECK: minsd
+define double @clampTo3k_h(double %x) nounwind readnone {
+entry:
+ %0 = fcmp uge double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse-varargs.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse-varargs.ll
index 806126d..da38f0e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse-varargs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse-varargs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep xmm | grep esp
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep xmm | grep esp
define i32 @t() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse2.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse2.ll
index 97ef3ab..9f926f2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse2.ll
@@ -1,5 +1,5 @@
; Tests for SSE2 and below, without SSE3+.
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin10 -mcpu=pentium4 | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 | FileCheck %s
define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind {
%tmp3 = load <2 x double>* %A, align 16
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse3.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse3.ll
index 8732579..703635c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse3.ll
@@ -1,6 +1,6 @@
; These are tests for SSE3 codegen. Yonah has SSE3 and earlier but not SSSE3+.
-; RUN: llvm-as < %s | llc -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9\
+; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9\
; RUN: | FileCheck %s --check-prefix=X64
; Test for v8xi16 lowering where we extract the first element of the vector and
@@ -92,8 +92,8 @@ define <8 x i16> @t7(<8 x i16> %A, <8 x i16> %B) nounwind {
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 0, i32 3, i32 2, i32 4, i32 6, i32 4, i32 7 >
ret <8 x i16> %tmp
; X64: t7:
-; X64: pshuflw $176, %xmm0, %xmm0
-; X64: pshufhw $200, %xmm0, %xmm0
+; X64: pshuflw $-80, %xmm0, %xmm0
+; X64: pshufhw $-56, %xmm0, %xmm0
; X64: ret
}
@@ -120,8 +120,8 @@ define void @t8(<2 x i64>* %res, <2 x i64>* %A) nounwind {
store <2 x i64> %tmp15.upgrd.2, <2 x i64>* %res
ret void
; X64: t8:
-; X64: pshuflw $198, (%rsi), %xmm0
-; X64: pshufhw $198, %xmm0, %xmm0
+; X64: pshuflw $-58, (%rsi), %xmm0
+; X64: pshufhw $-58, %xmm0, %xmm0
; X64: movaps %xmm0, (%rdi)
; X64: ret
}
@@ -243,7 +243,7 @@ entry:
; X64: t15:
; X64: pextrw $7, %xmm0, %eax
; X64: punpcklqdq %xmm1, %xmm0
-; X64: pshuflw $128, %xmm0, %xmm0
+; X64: pshuflw $-128, %xmm0, %xmm0
; X64: pinsrw $2, %eax, %xmm0
; X64: ret
}
@@ -265,7 +265,7 @@ entry:
; X64: movd %xmm1, %edx
; X64: pinsrw $0, %edx, %xmm1
; X64: movzbl %cl, %ecx
-; X64: andw $65280, %ax
+; X64: andw $-256, %ax
; X64: orw %cx, %ax
; X64: movaps %xmm1, %xmm0
; X64: pinsrw $1, %eax, %xmm0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse41.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse41.ll
index 1d33539..a734c05 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse41.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse41.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X32
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X64
@g16 = external global i16
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse42.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse42.ll
index 1652294..c9c4d01 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse42.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse42.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X32
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64
declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind
declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sse_reload_fold.ll b/libclamav/c++/llvm/test/CodeGen/X86/sse_reload_fold.ll
index 547763e..dc3d6fe 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sse_reload_fold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sse_reload_fold.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -march=x86-64 -mattr=+64bit,+sse3 -print-failed-fuse-candidates |& \
+; RUN: llc < %s -march=x86-64 -mattr=+64bit,+sse3 -print-failed-fuse-candidates |& \
; RUN: grep fail | count 1
declare float @test_f(float %f)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/stack-align.ll b/libclamav/c++/llvm/test/CodeGen/X86/stack-align.ll
index dda6f0d..cb65e9b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/stack-align.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/stack-align.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -relocation-model=static -mcpu=yonah | grep {andpd.*4(%esp), %xmm}
+; RUN: llc < %s -relocation-model=static -mcpu=yonah | grep {andpd.*4(%esp), %xmm}
; The double argument is at 4(esp) which is 16-byte aligned, allowing us to
; fold the load into the andpd.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/stack-color-with-reg-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/stack-color-with-reg-2.ll
index bc4182f..c1f2672 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/stack-color-with-reg-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/stack-color-with-reg-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs | grep {movl\[\[:space:\]\]%eax, %ebx}
+; RUN: llc < %s -mtriple=i386-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs | grep {movl\[\[:space:\]\]%eax, %ebx}
%"struct..0$_67" = type { i32, %"struct.llvm::MachineOperand"**, %"struct.llvm::MachineOperand"* }
%"struct..1$_69" = type { i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/stack-color-with-reg.ll b/libclamav/c++/llvm/test/CodeGen/X86/stack-color-with-reg.ll
index 114e9bf..672f77e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/stack-color-with-reg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/stack-color-with-reg.ll
@@ -1,7 +1,6 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
-; RUN: grep stackcoloring %t | grep "loads eliminated"
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 5
-; RUN: grep asm-printer %t | grep 182
+; RUN: grep asm-printer %t | grep 179
type { [62 x %struct.Bitvec*] } ; type %0
type { i8* } ; type %1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/stdarg.ll b/libclamav/c++/llvm/test/CodeGen/X86/stdarg.ll
index 7207057..9778fa1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/stdarg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/stdarg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {testb \[%\]al, \[%\]al}
+; RUN: llc < %s -march=x86-64 | grep {testb \[%\]al, \[%\]al}
%struct.__va_list_tag = type { i32, i32, i8*, i8* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/store-empty-member.ll b/libclamav/c++/llvm/test/CodeGen/X86/store-empty-member.ll
new file mode 100644
index 0000000..37f86c6
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/store-empty-member.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+
+; Don't crash on an empty struct member.
+
+; CHECK: movl $2, 4(%esp)
+; CHECK: movl $1, (%esp)
+
+%testType = type {i32, [0 x i32], i32}
+
+define void @foo() nounwind {
+ %1 = alloca %testType
+ volatile store %testType {i32 1, [0 x i32] zeroinitializer, i32 2}, %testType* %1
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/store-fp-constant.ll b/libclamav/c++/llvm/test/CodeGen/X86/store-fp-constant.ll
index 70cb046..206886b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/store-fp-constant.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/store-fp-constant.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep rodata
-; RUN: llvm-as < %s | llc -march=x86 | not grep literal
+; RUN: llc < %s -march=x86 | not grep rodata
+; RUN: llc < %s -march=x86 | not grep literal
;
; Check that no FP constants in this testcase ends up in the
; constant pool.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/store-global-address.ll b/libclamav/c++/llvm/test/CodeGen/X86/store-global-address.ll
index 0695eee..c8d4cbc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/store-global-address.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/store-global-address.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep movl | count 1
+; RUN: llc < %s -march=x86 | grep movl | count 1
@dst = global i32 0 ; <i32*> [#uses=1]
@ptr = global i32* null ; <i32**> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/store_op_load_fold.ll b/libclamav/c++/llvm/test/CodeGen/X86/store_op_load_fold.ll
index acef174..66d0e47 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/store_op_load_fold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/store_op_load_fold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep mov
+; RUN: llc < %s -march=x86 | not grep mov
;
; Test the add and load are folded into the store instruction.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/store_op_load_fold2.ll b/libclamav/c++/llvm/test/CodeGen/X86/store_op_load_fold2.ll
index 09aaba1..0ccfe47 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/store_op_load_fold2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/store_op_load_fold2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: grep {and DWORD PTR} | count 2
target datalayout = "e-p:32:32"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/storetrunc-fp.ll b/libclamav/c++/llvm/test/CodeGen/X86/storetrunc-fp.ll
index 945cf48..03ad093 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/storetrunc-fp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/storetrunc-fp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep flds
+; RUN: llc < %s -march=x86 | not grep flds
define void @foo(x86_fp80 %a, x86_fp80 %b, float* %fp) {
%c = fadd x86_fp80 %a, %b
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/stride-nine-with-base-reg.ll b/libclamav/c++/llvm/test/CodeGen/X86/stride-nine-with-base-reg.ll
index cc26487..7aae9eb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/stride-nine-with-base-reg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/stride-nine-with-base-reg.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -relocation-model=static | not grep lea
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep lea
+; RUN: llc < %s -march=x86 -relocation-model=static | not grep lea
+; RUN: llc < %s -march=x86-64 | not grep lea
; P should be sunk into the loop and folded into the address mode. There
; shouldn't be any lea instructions inside the loop.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/stride-reuse.ll b/libclamav/c++/llvm/test/CodeGen/X86/stride-reuse.ll
index 277a443..a99a9c9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/stride-reuse.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/stride-reuse.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep lea
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep lea
+; RUN: llc < %s -march=x86 | not grep lea
+; RUN: llc < %s -march=x86-64 | not grep lea
@B = external global [1000 x float], align 32
@A = external global [1000 x float], align 32
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/sub-with-overflow.ll b/libclamav/c++/llvm/test/CodeGen/X86/sub-with-overflow.ll
index 98f0252..19f4079 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/sub-with-overflow.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/sub-with-overflow.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 1
-; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 1
+; RUN: llc < %s -march=x86 | grep {jo} | count 1
+; RUN: llc < %s -march=x86 | grep {jb} | count 1
@ok = internal constant [4 x i8] c"%d\0A\00"
@no = internal constant [4 x i8] c"no\0A\00"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-0.ll
index 6b60f65..d718c85 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 1
+; RUN: llc < %s -march=x86-64 | grep mov | count 1
; Do eliminate the zero-extension instruction and rely on
; x86-64's implicit zero-extension!
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-1.ll
index aa26f06..a297728 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {leal .*), %e.\*} | count 1
+; RUN: llc < %s -march=x86-64 | grep {leal .*), %e.\*} | count 1
; Don't eliminate or coalesce away the explicit zero-extension!
; This is currently using an leal because of a 3-addressification detail,
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-2.ll
index d0b40cd..49d2e88 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movl
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movl
; rdar://6707985
%XXOO = type { %"struct.XXC::XXCC", i8*, %"struct.XXC::XXOO::$_71" }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-3.ll
index 6634538..931ae75 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep imull
+; RUN: llc < %s -march=x86-64 | grep imull
; Don't eliminate or coalesce away the explicit zero-extension!
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-4.ll
index bb6af39..0ea5541 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: not grep leaq %t
; RUN: not grep incq %t
; RUN: not grep decq %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-5.ll
index 81b262a..ba4c307 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86-64 > %t
; RUN: grep addl %t
; RUN: not egrep {movl|movq} %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-6.ll b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-6.ll
index f18eef7..76430cd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/subreg-to-reg-6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
define i64 @foo() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/switch-zextload.ll b/libclamav/c++/llvm/test/CodeGen/X86/switch-zextload.ll
index f3c701f..55425bc 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/switch-zextload.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/switch-zextload.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 1
+; RUN: llc < %s -march=x86 | grep mov | count 1
; Do zextload, instead of a load and a separate zext.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/swizzle.ll b/libclamav/c++/llvm/test/CodeGen/X86/swizzle.ll
index d00bb9a..23e0c24 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/swizzle.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/swizzle.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movlps
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movsd
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep movups
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movlps
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep movups
; rdar://6523650
%struct.vector4_t = type { <4 x float> }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcall-i1.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcall-i1.ll
index 0ec6a77..8ef1f11 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcall-i1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcall-i1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep TAILCALL
+; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL
define fastcc i1 @i1test(i32, i32, i32, i32) {
entry:
%4 = tail call fastcc i1 @i1test( i32 %0, i32 %1, i32 %2, i32 %3)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcall-stackalign.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcall-stackalign.ll
index ff960b8..110472c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcall-stackalign.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcall-stackalign.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=i686-unknown-linux -tailcallopt | grep -A 1 call | grep -A 1 tailcaller | grep subl | grep 12
+; RUN: llc < %s -mtriple=i686-unknown-linux -tailcallopt | grep -A 1 call | grep -A 1 tailcaller | grep subl | grep 12
; Linux has 8 byte alignment so the params cause stack size 20 when tailcallopt
; is enabled, ensure that a normal fastcc call has matching stack size
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcall-structret.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcall-structret.ll
index e94d7d8..d8be4b2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcall-structret.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcall-structret.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep TAILCALL
+; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL
define fastcc { { i8*, i8* }*, i8*} @init({ { i8*, i8* }*, i8*}, i32) {
entry:
%2 = tail call fastcc { { i8*, i8* }*, i8* } @init({ { i8*, i8*}*, i8*} %0, i32 %1)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcall-void.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcall-void.ll
index 27b2a28..4e578d1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcall-void.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcall-void.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep TAILCALL
+; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL
define fastcc void @i1test(i32, i32, i32, i32) {
entry:
tail call fastcc void @i1test( i32 %0, i32 %1, i32 %2, i32 %3)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcall1.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcall1.ll
index deedb86..a4f87c0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcall1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcall1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep TAILCALL
+; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL
define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
entry:
ret i32 %a3
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcallbyval.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcallbyval.ll
index 916be56..7002560 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcallbyval.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcallbyval.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep TAILCALL
-; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep {movl\[\[:space:\]\]*4(%esp), %eax} | count 1
+; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL
+; RUN: llc < %s -march=x86 -tailcallopt | grep {movl\[\[:space:\]\]*4(%esp), %eax} | count 1
%struct.s = type {i32, i32, i32, i32, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i32, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcallbyval64.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcallbyval64.ll
index 7b65863..7c685b8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcallbyval64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcallbyval64.ll
@@ -1,15 +1,15 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -tailcallopt | grep TAILCALL
+; RUN: llc < %s -march=x86-64 -tailcallopt | grep TAILCALL
; Expect 2 rep;movs because of tail call byval lowering.
-; RUN: llvm-as < %s | llc -march=x86-64 -tailcallopt | grep rep | wc -l | grep 2
+; RUN: llc < %s -march=x86-64 -tailcallopt | grep rep | wc -l | grep 2
; A sequence of copyto/copyfrom virtual registers is used to deal with byval
; lowering appearing after moving arguments to registers. The following two
; checks verify that the register allocator changes those sequences to direct
; moves to argument register where it can (for registers that are not used in
; byval lowering - not rsi, not rdi, not rcx).
; Expect argument 4 to be moved directly to register edx.
-; RUN: llvm-as < %s | llc -march=x86-64 -tailcallopt | grep movl | grep {7} | grep edx
+; RUN: llc < %s -march=x86-64 -tailcallopt | grep movl | grep {7} | grep edx
; Expect argument 6 to be moved directly to register r8.
-; RUN: llvm-as < %s | llc -march=x86-64 -tailcallopt | grep movl | grep {17} | grep r8
+; RUN: llc < %s -march=x86-64 -tailcallopt | grep movl | grep {17} | grep r8
%struct.s = type { i64, i64, i64, i64, i64, i64, i64, i64,
i64, i64, i64, i64, i64, i64, i64, i64,
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcallfp.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcallfp.ll
index f614935..c0b609a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcallfp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcallfp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -tailcallopt | not grep call
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -tailcallopt | not grep call
define fastcc i32 @bar(i32 %X, i32(double, i32) *%FP) {
%Y = tail call fastcc i32 %FP(double 0.0, i32 %X)
ret i32 %Y
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcallfp2.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcallfp2.ll
index 151701e..be4f96c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcallfp2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcallfp2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -tailcallopt | grep {jmp} | grep {\\*%eax}
+; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%eax}
declare i32 @putchar(i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcallpic1.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcallpic1.ll
index 54074eb..60e3be5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcallpic1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcallpic1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -tailcallopt -mtriple=i686-pc-linux-gnu -relocation-model=pic | grep TAILCALL
+; RUN: llc < %s -tailcallopt -mtriple=i686-pc-linux-gnu -relocation-model=pic | grep TAILCALL
define protected fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcallpic2.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcallpic2.ll
index 60818e4..eaa7631 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcallpic2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcallpic2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -tailcallopt -mtriple=i686-pc-linux-gnu -relocation-model=pic | grep -v TAILCALL
+; RUN: llc < %s -tailcallopt -mtriple=i686-pc-linux-gnu -relocation-model=pic | grep -v TAILCALL
define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tailcallstack64.ll b/libclamav/c++/llvm/test/CodeGen/X86/tailcallstack64.ll
index eced067..73c59bb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tailcallstack64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tailcallstack64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -tailcallopt -march=x86-64 | FileCheck %s
+; RUN: llc < %s -tailcallopt -march=x86-64 | FileCheck %s
; Check that lowered arguments on the stack do not overwrite each other.
; Add %in1 %p1 to a different temporary register (%eax).
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/test-nofold.ll b/libclamav/c++/llvm/test/CodeGen/X86/test-nofold.ll
index a24a9a0..772ff6c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/test-nofold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/test-nofold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep {testl.*%e.x.*%e.x}
+; RUN: llc < %s -march=x86 -mcpu=yonah | grep {testl.*%e.x.*%e.x}
; rdar://5752025
; We don't want to fold the and into the test, because the and clobbers its
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/test-shrink.ll b/libclamav/c++/llvm/test/CodeGen/X86/test-shrink.ll
index bbf727a..1d63693 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/test-shrink.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/test-shrink.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | FileCheck %s --check-prefix=CHECK-64
-; RUN: llvm-as < %s | llc -march=x86 | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
; CHECK-64: g64xh:
; CHECK-64: testb $8, %ah
@@ -104,10 +104,10 @@ no:
ret void
}
; CHECK-64: g64x16:
-; CHECK-64: testw $32896, %di
+; CHECK-64: testw $-32640, %di
; CHECK-64: ret
; CHECK-32: g64x16:
-; CHECK-32: testw $32896, %ax
+; CHECK-32: testw $-32640, %ax
; CHECK-32: ret
define void @g64x16(i64 inreg %x) nounwind {
%t = and i64 %x, 32896
@@ -121,10 +121,10 @@ no:
ret void
}
; CHECK-64: g32x16:
-; CHECK-64: testw $32896, %di
+; CHECK-64: testw $-32640, %di
; CHECK-64: ret
; CHECK-32: g32x16:
-; CHECK-32: testw $32896, %ax
+; CHECK-32: testw $-32640, %ax
; CHECK-32: ret
define void @g32x16(i32 inreg %x) nounwind {
%t = and i32 %x, 32896
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/testl-commute.ll b/libclamav/c++/llvm/test/CodeGen/X86/testl-commute.ll
index dbbef0a..3d5f672 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/testl-commute.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/testl-commute.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep {testl.*\(%r.i\), %} | count 3
+; RUN: llc < %s | grep {testl.*\(%r.i\), %} | count 3
; rdar://5671654
; The loads should fold into the testl instructions, no matter how
; the inputs are commuted.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls-pic.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls-pic.ll
index aa3d808..4cad837 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls-pic.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls-pic.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic | FileCheck -check-prefix=X32 %s
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic | FileCheck -check-prefix=X64 %s
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic | FileCheck -check-prefix=X32 %s
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic | FileCheck -check-prefix=X64 %s
@i = thread_local global i32 15
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls1.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls1.ll
index 85ff360..0cae5c4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls1.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movl %gs:i at NTPOFF, %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movl %fs:i at TPOFF, %eax} %t2
@i = thread_local global i32 15
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls10.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls10.ll
index 2f5f02b..fb61596 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls10.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls10.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movl %gs:0, %eax} %t
; RUN: grep {leal i at NTPOFF(%eax), %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movq %fs:0, %rax} %t2
; RUN: grep {leaq i at TPOFF(%rax), %rax} %t2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls11.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls11.ll
index b6aed9a..a2c1a1f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls11.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls11.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movw %gs:i at NTPOFF, %ax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movw %fs:i at TPOFF, %ax} %t2
@i = thread_local global i16 15
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls12.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls12.ll
index b528839..c29f6ad 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls12.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls12.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movb %gs:i at NTPOFF, %al} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movb %fs:i at TPOFF, %al} %t2
@i = thread_local global i8 15
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls13.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls13.ll
index ec23a41..08778ec 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls13.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls13.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movswl %gs:i at NTPOFF, %eax} %t
; RUN: grep {movzwl %gs:j at NTPOFF, %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movswl %fs:i at TPOFF, %edi} %t2
; RUN: grep {movzwl %fs:j at TPOFF, %edi} %t2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls14.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls14.ll
index 941601e..88426dd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls14.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls14.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movsbl %gs:i at NTPOFF, %eax} %t
; RUN: grep {movzbl %gs:j at NTPOFF, %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movsbl %fs:i at TPOFF, %edi} %t2
; RUN: grep {movzbl %fs:j at TPOFF, %edi} %t2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls15.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls15.ll
index 62f3677..7abf070 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls15.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls15.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movl %gs:0, %eax} %t | count 1
; RUN: grep {leal i at NTPOFF(%eax), %ecx} %t
; RUN: grep {leal j at NTPOFF(%eax), %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movq %fs:0, %rax} %t2 | count 1
; RUN: grep {leaq i at TPOFF(%rax), %rcx} %t2
; RUN: grep {leaq j at TPOFF(%rax), %rax} %t2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls2.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls2.ll
index baa51bb..5a94296 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls2.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movl %gs:0, %eax} %t
; RUN: grep {leal i at NTPOFF(%eax), %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movq %fs:0, %rax} %t2
; RUN: grep {leaq i at TPOFF(%rax), %rax} %t2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls3.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls3.ll
index 0618499..7327cc4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls3.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movl i at INDNTPOFF, %eax} %t
; RUN: grep {movl %gs:(%eax), %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movq i at GOTTPOFF(%rip), %rax} %t2
; RUN: grep {movl %fs:(%rax), %eax} %t2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls4.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls4.ll
index 33f221b..d2e40e3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls4.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movl %gs:0, %eax} %t
; RUN: grep {addl i at INDNTPOFF, %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movq %fs:0, %rax} %t2
; RUN: grep {addq i at GOTTPOFF(%rip), %rax} %t2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls5.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls5.ll
index ff7b9e0..4d2cc02 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls5.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movl %gs:i at NTPOFF, %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movl %fs:i at TPOFF, %eax} %t2
@i = internal thread_local global i32 15
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls6.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls6.ll
index ab53929..505106e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls6.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movl %gs:0, %eax} %t
; RUN: grep {leal i at NTPOFF(%eax), %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movq %fs:0, %rax} %t2
; RUN: grep {leaq i at TPOFF(%rax), %rax} %t2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls7.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls7.ll
index 6a7739b..e9116e7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls7.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movl %gs:i at NTPOFF, %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movl %fs:i at TPOFF, %eax} %t2
@i = hidden thread_local global i32 15
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls8.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls8.ll
index fd9d472..375af94 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls8.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls8.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movl %gs:0, %eax} %t
; RUN: grep {leal i at NTPOFF(%eax), %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movq %fs:0, %rax} %t2
; RUN: grep {leaq i at TPOFF(%rax), %rax} %t2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/tls9.ll b/libclamav/c++/llvm/test/CodeGen/X86/tls9.ll
index bc0a6f0..214146f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/tls9.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/tls9.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
; RUN: grep {movl %gs:i at NTPOFF, %eax} %t
-; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
; RUN: grep {movl %fs:i at TPOFF, %eax} %t2
@i = external hidden thread_local global i32
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/trap.ll b/libclamav/c++/llvm/test/CodeGen/X86/trap.ll
index 9a013ff..03ae6bf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/trap.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/trap.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep ud2
+; RUN: llc < %s -march=x86 -mcpu=yonah | grep ud2
define i32 @test() noreturn nounwind {
entry:
tail call void @llvm.trap( )
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/trunc-to-bool.ll b/libclamav/c++/llvm/test/CodeGen/X86/trunc-to-bool.ll
index 25a1191..374d404 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/trunc-to-bool.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/trunc-to-bool.ll
@@ -1,7 +1,7 @@
; An integer truncation to i1 should be done with an and instruction to make
; sure only the LSBit survives. Test that this is the case both for a returned
; value and as the operand of a branch.
-; RUN: llvm-as < %s | llc -march=x86 | grep {\\(and\\)\\|\\(test.*\\\$1\\)} | \
+; RUN: llc < %s -march=x86 | grep {\\(and\\)\\|\\(test.*\\\$1\\)} | \
; RUN: count 5
define i1 @test1(i32 %X) zeroext {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-coalesce-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-coalesce-2.ll
index 3fe4cd1..6f16a25 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-coalesce-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-coalesce-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& \
; RUN: grep {twoaddrinstr} | grep {Number of instructions aggressively commuted}
; rdar://6480363
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-coalesce.ll b/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-coalesce.ll
index 5293b77..d0e13f6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-coalesce.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-coalesce.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 5
+; RUN: llc < %s -march=x86 | grep mov | count 5
; rdar://6523745
@"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-delete.ll b/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-delete.ll
index bbf4e62..77e3c75 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-delete.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-delete.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -stats |& grep {twoaddrinstr} | grep {Number of dead instructions deleted}
+; RUN: llc < %s -march=x86 -stats |& grep {twoaddrinstr} | grep {Number of dead instructions deleted}
%struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] }
%struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-pass-sink.ll b/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-pass-sink.ll
index 7655880..077fee0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-pass-sink.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-pass-sink.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats |& grep {Number of 3-address instructions sunk}
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& grep {Number of 3-address instructions sunk}
define void @t2(<2 x i64>* %vDct, <2 x i64>* %vYp, i8* %skiplist, <2 x i64> %a1) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-remat.ll b/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-remat.ll
index b74b70c..4940c78 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-remat.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/twoaddr-remat.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep 59796 | count 3
+; RUN: llc < %s -march=x86 | grep 59796 | count 3
%Args = type %Value*
%Exec = type opaque*
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/uint_to_fp-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/uint_to_fp-2.ll
index d630437..da5105d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/uint_to_fp-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/uint_to_fp-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movsd | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd | count 1
; rdar://6504833
define float @f(i32 %x) nounwind readnone {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/uint_to_fp.ll b/libclamav/c++/llvm/test/CodeGen/X86/uint_to_fp.ll
index 148437f..41ee194 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/uint_to_fp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/uint_to_fp.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not grep {sub.*esp}
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep cvtsi2ss
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep {sub.*esp}
+; RUN: llc < %s -march=x86 -mcpu=yonah | grep cvtsi2ss
; rdar://6034396
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/umul-with-carry.ll b/libclamav/c++/llvm/test/CodeGen/X86/umul-with-carry.ll
index 547e179..7416051 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/umul-with-carry.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/umul-with-carry.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {jc} | count 1
+; RUN: llc < %s -march=x86 | grep {jc} | count 1
; XFAIL: *
; FIXME: umul-with-overflow not supported yet.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/umul-with-overflow.ll b/libclamav/c++/llvm/test/CodeGen/X86/umul-with-overflow.ll
index 9e69154..d522bd8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/umul-with-overflow.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/umul-with-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep "\\\\\\\<mul"
+; RUN: llc < %s -march=x86 | grep "\\\\\\\<mul"
declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
define i1 @a(i32 %x) zeroext nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/urem-i8-constant.ll b/libclamav/c++/llvm/test/CodeGen/X86/urem-i8-constant.ll
index bc93684..e3cb69c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/urem-i8-constant.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/urem-i8-constant.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep 111
+; RUN: llc < %s -march=x86 | grep 111
define i8 @foo(i8 %tmp325) {
%t546 = urem i8 %tmp325, 37
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/v4f32-immediate.ll b/libclamav/c++/llvm/test/CodeGen/X86/v4f32-immediate.ll
index bd6045c..b5ebaa7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/v4f32-immediate.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/v4f32-immediate.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse | grep movaps
+; RUN: llc < %s -march=x86 -mattr=+sse | grep movaps
define <4 x float> @foo() {
ret <4 x float> <float 0x4009C9D0A0000000, float 0x4002666660000000, float 0x3FF3333340000000, float 0x3FB99999A0000000>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/variable-sized-darwin-bzero.ll b/libclamav/c++/llvm/test/CodeGen/X86/variable-sized-darwin-bzero.ll
index b0cdf49..4817db2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/variable-sized-darwin-bzero.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/variable-sized-darwin-bzero.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mtriple=i686-apple-darwin10 | grep __bzero
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin10 | grep __bzero
declare void @llvm.memset.i64(i8*, i8, i64, i32)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/variadic-node-pic.ll b/libclamav/c++/llvm/test/CodeGen/X86/variadic-node-pic.ll
index 4d76445..1182a30 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/variadic-node-pic.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/variadic-node-pic.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -relocation-model=pic -code-model=large
+; RUN: llc < %s -relocation-model=pic -code-model=large
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_add.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_add.ll
index 72415a3..7c77d11 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_add.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_add.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
define <2 x i64> @test(<2 x i64> %a, <2 x i64> %b) {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_align.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_align.ll
index d88104d..e273115 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_align.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_align.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mcpu=yonah -relocation-model=static | grep movaps | count 2
+; RUN: llc < %s -mcpu=yonah -relocation-model=static | grep movaps | count 2
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_call.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_call.ll
index ebdac7d..b3efc7b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_call.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_call.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin8 | \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin8 | \
; RUN: grep {subl.*60}
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin8 | \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin8 | \
; RUN: grep {movaps.*32}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_clear.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_clear.ll
index ca2e430..166d436 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_clear.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_clear.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t
; RUN: not grep and %t
; RUN: not grep psrldq %t
; RUN: grep xorps %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_compare.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_compare.ll
index fc30763..c8c7257 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_compare.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_compare.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | FileCheck %s
+; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_ctbits.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_ctbits.ll
index f057c9a..f0158d6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_ctbits.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_ctbits.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>)
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_extract-sse4.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_extract-sse4.ll
index c1d431f..dab5dd1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_extract-sse4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_extract-sse4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse41 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse41 -o %t
; RUN: grep extractps %t | count 1
; RUN: grep pextrd %t | count 1
; RUN: not grep pshufd %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_extract.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_extract.ll
index 9b59e2d..b013730 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_extract.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_extract.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse41 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 -o %t
; RUN: grep movss %t | count 3
; RUN: grep movhlps %t | count 1
; RUN: grep pshufd %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_fneg.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_fneg.ll
index a801472..d49c70e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_fneg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_fneg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
define <4 x float> @t1(<4 x float> %Q) {
%tmp15 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %Q
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_i64.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_i64.ll
index 80c65be..462e16e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_i64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_i64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
; RUN: grep movq %t | count 2
; Used movq to load i64 into a v2i64 when the top i64 is 0.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_ins_extract-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_ins_extract-1.ll
index c7eb221..2951193 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_ins_extract-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_ins_extract-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep {(%esp,%eax,4)} | count 4
+; RUN: llc < %s -march=x86 -mcpu=yonah | grep {(%esp,%eax,4)} | count 4
; Inserts and extracts with variable indices must be lowered
; to memory accesses.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_ins_extract.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_ins_extract.ll
index 7882839..bf43deb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_ins_extract.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_ins_extract.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -scalarrepl -instcombine | \
+; RUN: opt < %s -scalarrepl -instcombine | \
; RUN: llc -march=x86 -mcpu=yonah | not grep sub.*esp
; This checks that various insert/extract idiom work without going to the
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-2.ll
index 8d0bcc4..b08044b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-2.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse41 | grep {\$36,} | count 2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse41 | grep shufps | count 2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse41 | grep pinsrw | count 1
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse41 | grep movhpd | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2,-sse41 | grep unpcklpd | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep {\$36,} | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep shufps | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep pinsrw | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movhpd | count 1
+; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep unpcklpd | count 1
define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind {
%tmp1 = insertelement <4 x float> %tmp, float %s, i32 3
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-3.ll
index e43eca4..a18cd86 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2,-sse41 | grep punpcklqdq | count 1
+; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep punpcklqdq | count 1
define <2 x i64> @t1(i64 %s, <2 x i64> %tmp) nounwind {
%tmp1 = insertelement <2 x i64> %tmp, i64 %s, i32 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-5.ll
index 1a9768a..291fc04 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 > %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
; RUN: grep psllq %t | grep 32
; RUN: grep pslldq %t | grep 12
; RUN: grep psrldq %t | grep 8
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-6.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-6.ll
index 5ef270f..54aa43f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-6.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pslldq
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 6
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pslldq
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 6
define <4 x float> @t3(<4 x float>* %P) nounwind {
%tmp1 = load <4 x float>* %P
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-7.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-7.ll
index 8cfc63a..9ede10f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-7.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx -mtriple=i686-apple-darwin9 -o - | grep punpckldq
+; RUN: llc < %s -march=x86 -mattr=+mmx -mtriple=i686-apple-darwin9 -o - | grep punpckldq
define <2 x i32> @mmx_movzl(<2 x i32> %x) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-8.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-8.ll
index d0d9486..650951c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-8.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert-8.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse41 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse41 -o %t
; tests variable insert and extract of a 4 x i32
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert.ll
index 3a9464c..a7274a9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse41 | grep movss | count 1
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse41 | not grep pinsrw
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movss | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | not grep pinsrw
define void @test(<4 x float>* %F, i32 %I) {
%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert_4.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert_4.ll
index a0aa0c0..2c31e56 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_insert_4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_insert_4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep 1084227584 | count 1
+; RUN: llc < %s -march=x86 -mcpu=yonah | grep 1084227584 | count 1
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_loadsingles.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_loadsingles.ll
index 6712276..8812c4f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_loadsingles.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_loadsingles.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
define <4 x float> @a(<4 x float> %a, float* nocapture %p) nounwind readonly {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_logical.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_logical.ll
index f895762..1dc0b16 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_logical.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_logical.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 > %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
; RUN: grep xorps %t | count 2
; RUN: grep andnps %t
; RUN: grep movaps %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_return.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_return.ll
index 106966f..66762b4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_return.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_return.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 > %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
; RUN: grep xorps %t | count 1
; RUN: grep movaps %t | count 1
; RUN: not grep shuf %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_select.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_select.ll
index ecb825b..033e9f7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_select.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_select.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse
+; RUN: llc < %s -march=x86 -mattr=+sse
define void @test(i32 %C, <4 x float>* %A, <4 x float>* %B) {
%tmp = load <4 x float>* %A ; <<4 x float>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-2.ll
index ae9530d..a8f1187 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-2.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movss | count 1
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movd | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movss | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 1
define <4 x float> @test1(float %a) nounwind {
%tmp = insertelement <4 x float> zeroinitializer, float %a, i32 0 ; <<4 x float>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-3.ll
index 2bf8e50..ada17e0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
; RUN: grep pshufd %t | count 2
define <4 x float> @test(float %a) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-4.ll
index da7ef80..332c8b7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pinsrw | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pinsrw | count 2
define <2 x i64> @test(i16 %a) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-5.ll
index f97b411..f811a74 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
; RUN: grep movlhps %t | count 1
; RUN: grep movq %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-6.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-6.ll
index 304fbe4..0713d95 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
; RUN: grep movss %t | count 1
; RUN: grep movq %t | count 1
; RUN: grep shufps %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-7.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-7.ll
index 6f98c51..d993178 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-7.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movsd | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd | count 1
define <2 x i64> @test(<2 x i64>* %p) nounwind {
%tmp = bitcast <2 x i64>* %p to double*
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-8.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-8.ll
index cca436b..9697f11 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-8.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-8.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep movsd
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movd.*%rdi,.*%xmm0}
+; RUN: llc < %s -march=x86-64 | not grep movsd
+; RUN: llc < %s -march=x86-64 | grep {movd.*%rdi,.*%xmm0}
define <2 x i64> @test(i64 %i) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-9.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-9.ll
index 5c1b8f5..3656e5f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-9.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-9.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movd | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movlhps.*%xmm0, %xmm0}
+; RUN: llc < %s -march=x86-64 | grep movd | count 1
+; RUN: llc < %s -march=x86-64 | grep {movlhps.*%xmm0, %xmm0}
define <2 x i64> @test3(i64 %A) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-A.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-A.ll
index f33263f..f05eecf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-A.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-A.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep {movl.*\$1, %}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movl.*\$1, %}
define <2 x i64> @test1() nounwind {
entry:
ret <2 x i64> < i64 1, i64 0 >
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-B.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-B.ll
index d318964..f5b3e8b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-B.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-B.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep movaps
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep esp | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep movaps
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep esp | count 2
; These should both generate something like this:
;_test3:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-C.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-C.ll
index fc86853..7636ac3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-C.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-C.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movq
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep mov | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2 | grep movd
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mov | count 1
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd
define <2 x i64> @t1(i64 %x) nounwind {
%tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-D.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-D.ll
index 71bdd84..3d6369e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-D.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-D.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
define <4 x i32> @t(i32 %x, i32 %y) nounwind {
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-E.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-E.ll
index ee63234..d78be66 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-E.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-E.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
define <4 x float> @t(float %X) nounwind {
%tmp11 = insertelement <4 x float> undef, float %X, i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-F.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-F.ll
index db83eb2..4f0acb2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-F.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-F.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movq
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movsd
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep mov | count 3
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mov | count 3
define <2 x i64> @t1(<2 x i64>* %ptr) nounwind {
%tmp45 = bitcast <2 x i64>* %ptr to <2 x i32>*
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-G.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-G.ll
index f81907c..4a542fe 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-G.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-G.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movss
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movss
define fastcc void @t(<4 x float> %A) nounwind {
%tmp41896 = extractelement <4 x float> %A, i32 0 ; <float> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-H.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-H.ll
index ea7b853..5037e36 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-H.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-H.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep movz
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep movz
define <2 x i64> @doload64(i16 signext %x) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-I.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-I.ll
index e1c44d0..64f36f9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-I.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-I.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movd
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep xorp
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xorp
define void @t1() nounwind {
%tmp298.i.i = load <4 x float>* null, align 16
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-J.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-J.ll
index 488d360..d90ab85 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set-J.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set-J.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movss
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movss
; PR2472
define <4 x i32> @a(<4 x i32> %a) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_set.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_set.ll
index 77636ed..c316df8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_set.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_set.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep punpckl | count 7
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep punpckl | count 7
define void @test(<8 x i16>* %b, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {
%tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0 ; <<8 x i16>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shift.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shift.ll
index 9c595bc..ddf0469 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shift.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shift.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep psllw
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep psrlq
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep psraw
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psllw
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psrlq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psraw
define <2 x i64> @t1(<2 x i64> %b1, <2 x i64> %c) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shift2.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shift2.ll
index b73f5f4..c5f9dc4 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shift2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shift2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep CPI
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep CPI
define <2 x i64> @t1(<2 x i64> %b1, <2 x i64> %c) nounwind {
%tmp1 = bitcast <2 x i64> %b1 to <8 x i16>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shift3.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shift3.ll
index 2641c5d..1ebf455 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shift3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shift3.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep psllq
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep psraw
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movd | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psllq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psraw
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 2
define <2 x i64> @t1(<2 x i64> %x1, i32 %bits) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-10.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-10.ll
index f4ffa91..a63e386 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-10.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-10.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
; RUN: grep unpcklps %t | count 1
; RUN: grep pshufd %t | count 1
; RUN: not grep {sub.*esp} %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-11.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-11.ll
index 463858f..640745a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-11.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-11.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | not grep mov
+; RUN: llc < %s -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | not grep mov
define <4 x i32> @test() nounwind {
%tmp131 = call <2 x i64> @llvm.x86.sse2.psrl.dq( <2 x i64> < i64 -1, i64 -1 >, i32 96 ) ; <<2 x i64>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-14.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-14.ll
index 6e8d0b8..f0cfc44 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-14.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-14.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movd | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2 | grep movd | count 2
-; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2 | grep movq | count 3
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep xor
+; RUN: llc < %s -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 1
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 2
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 3
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xor
define <4 x i32> @t1(i32 %a) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-15.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-15.ll
index 062f77c..5a9b8fd 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-15.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-15.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
define <2 x i64> @t00(<2 x i64> %a, <2 x i64> %b) nounwind {
%tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 0, i32 0 >
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-16.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-16.ll
index 98133fa..470f676 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-16.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-16.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin -o %t
; RUN: grep shufps %t | count 4
; RUN: grep movaps %t | count 2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t
; RUN: grep pshufd %t | count 4
; RUN: not grep shufps %t
; RUN: not grep mov %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-17.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-17.ll
index 992d791..9c33abb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-17.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-17.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {movd.*%rdi, %xmm0}
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep xor
+; RUN: llc < %s -march=x86-64 | grep {movd.*%rdi, %xmm0}
+; RUN: llc < %s -march=x86-64 | not grep xor
; PR2108
define <2 x i64> @doload64(i64 %x) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-18.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-18.ll
index 8539263..1104a4a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-18.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-18.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin8.8.0 | grep mov | count 7
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin8.8.0 | grep mov | count 7
%struct.vector4_t = type { <4 x float> }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-19.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-19.ll
index 4e7db20..9fc09df 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-19.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-19.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 4
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 4
; PR2485
define <4 x i32> @t(<4 x i32> %a, <4 x i32> %b) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-20.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-20.ll
index 7189084..6d1bac0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-20.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-20.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 3
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 3
define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-22.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-22.ll
index bd4ae25..5307ced 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-22.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-22.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium-m -o %t
+; RUN: llc < %s -march=x86 -mcpu=pentium-m -o %t
; RUN: grep movlhps %t | count 1
; RUN: grep pshufd %t | count 1
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t
+; RUN: llc < %s -march=x86 -mcpu=core2 -o %t
; RUN: grep movlhps %t | count 1
; RUN: grep movddup %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-23.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-23.ll
index 7e8aa5d..05a3a1e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-23.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-23.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep punpck
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufd
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep punpck
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pshufd
define i32 @t() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-24.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-24.ll
index 170ba35..7562f1d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-24.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-24.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep punpck
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep punpck
define i32 @t() nounwind optsize {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-25.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-25.ll
index ea7dddc..2aa2d25 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-25.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-25.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -o %t
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
; RUN: grep unpcklps %t | count 3
; RUN: grep unpckhps %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-26.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-26.ll
index 0a31129..8cc15d1 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-26.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-26.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -o %t
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
; RUN: grep unpcklps %t | count 1
; RUN: grep unpckhps %t | count 3
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-27.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-27.ll
index e687e83..d700ccb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-27.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-27.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -o %t
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
; RUN: grep addps %t | count 2
; RUN: grep mulps %t | count 2
; RUN: grep subps %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-28.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-28.ll
index e07ac7e..343685b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-28.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-28.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t
+; RUN: llc < %s -march=x86 -mcpu=core2 -o %t
; RUN: grep pshufb %t | count 1
; FIXME: this test has a superfluous punpcklqdq pre-pshufb currently.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-3.ll
index a3bca0f..556f103 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
; RUN: grep movlhps %t | count 1
; RUN: grep movhlps %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-30.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-30.ll
index eab4a66..3f69150 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-30.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-30.ll
@@ -1,11 +1,11 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -disable-mmx -o %t
-; RUN: grep pshufhw %t | grep 161 | count 1
+; RUN: llc < %s -march=x86 -mattr=sse41 -disable-mmx -o %t
+; RUN: grep pshufhw %t | grep -- -95 | count 1
; RUN: grep shufps %t | count 1
; RUN: not grep pslldq %t
; Test case when creating pshufhw, we incorrectly set the higher order bit
; for an undef,
-define void @test(<8 x i16>* %dest, <8 x i16> %in) {
+define void @test(<8 x i16>* %dest, <8 x i16> %in) nounwind {
entry:
%0 = load <8 x i16>* %dest
%1 = shufflevector <8 x i16> %0, <8 x i16> %in, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14>
@@ -14,7 +14,7 @@ entry:
}
; A test case where we shouldn't generate a punpckldq but a pshufd and a pslldq
-define void @test2(<4 x i32>* %dest, <4 x i32> %in) {
+define void @test2(<4 x i32>* %dest, <4 x i32> %in) nounwind {
entry:
%0 = shufflevector <4 x i32> %in, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> < i32 undef, i32 5, i32 undef, i32 2>
store <4 x i32> %0, <4 x i32>* %dest
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-31.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-31.ll
index 7300ef3..bb06e15 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-31.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-31.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t
+; RUN: llc < %s -march=x86 -mcpu=core2 -o %t
; RUN: grep pshufb %t | count 1
define <8 x i16> @shuf3(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-34.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-34.ll
index 6123602..d057b3f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-34.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-34.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 | grep pshufb | count 2
+; RUN: llc < %s -march=x86 -mcpu=core2 | grep pshufb | count 2
define <8 x i16> @shuf2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-35.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-35.ll
index 83ce027..7f0fcb5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-35.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-35.ll
@@ -1,10 +1,10 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah -stack-alignment=16 -o %t
+; RUN: llc < %s -march=x86 -mcpu=yonah -stack-alignment=16 -o %t
; RUN: grep pextrw %t | count 13
; RUN: grep pinsrw %t | count 14
; RUN: grep rolw %t | count 13
; RUN: not grep esp %t
; RUN: not grep ebp %t
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -stack-alignment=16 -o %t
+; RUN: llc < %s -march=x86 -mcpu=core2 -stack-alignment=16 -o %t
; RUN: grep pshufb %t | count 3
define <16 x i8> @shuf1(<16 x i8> %T0) nounwind readnone {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-36.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-36.ll
index 87cca73..8a93a7e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-36.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-36.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -o %t
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
; RUN: grep pshufb %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-4.ll
index 3c03baa..829fedf 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 > %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
; RUN: grep shuf %t | count 2
; RUN: not grep unpck %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-5.ll
index aa786fc..c24167a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
; RUN: grep movhlps %t | count 1
; RUN: grep shufps %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-6.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-6.ll
index a98167f..f034b0a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
; RUN: grep movapd %t | count 1
; RUN: grep movaps %t | count 1
; RUN: grep movups %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-7.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-7.ll
index 1cb8964..4cdca09 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-7.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
; RUN: grep xorps %t | count 1
; RUN: not grep shufps %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-8.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-8.ll
index 73d75e6..964ce7b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-8.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-8.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | \
+; RUN: llc < %s -march=x86 -mattr=+sse2 | \
; RUN: not grep shufps
define void @test(<4 x float>* %res, <4 x float>* %A) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-9.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-9.ll
index 1a29871..2bef24d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-9.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle-9.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
; RUN: grep punpck %t | count 2
; RUN: not grep pextrw %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle.ll
index faad3ea..c05b79a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_shuffle.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t
+; RUN: llc < %s -march=x86 -mcpu=core2 -o %t
; RUN: grep shufp %t | count 1
; RUN: grep movupd %t | count 1
; RUN: grep pshufhw %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-2.ll
index c6e3ddd..cde5ae9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufd | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pshufd | count 1
define void @test(<2 x i64>* %P, i8 %x) nounwind {
%tmp = insertelement <16 x i8> zeroinitializer, i8 %x, i32 0 ; <<16 x i8>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-3.ll
index 678df11..649b85c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -o %t
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
; RUN: grep punpcklwd %t | count 4
; RUN: grep punpckhwd %t | count 4
; RUN: grep "pshufd" %t | count 8
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-4.ll
index f632faa..d9941e6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_splat-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -o %t
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
; RUN: grep punpcklbw %t | count 16
; RUN: grep punpckhbw %t | count 16
; RUN: grep "pshufd" %t | count 16
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_splat.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_splat.ll
index 89914fd..a87fbd0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_splat.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_splat.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufd
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse3 | grep movddup
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pshufd
+; RUN: llc < %s -march=x86 -mattr=+sse3 | grep movddup
define void @test_v4sf(<4 x float>* %P, <4 x float>* %Q, float %X) nounwind {
%tmp = insertelement <4 x float> zeroinitializer, float %X, i32 0 ; <<4 x float>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_ss_load_fold.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_ss_load_fold.ll
index 9cfb1ec..b1613fb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_ss_load_fold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_ss_load_fold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,+sse2 -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 -o %t
; RUN: grep minss %t | grep CPI | count 2
; RUN: grep CPI %t | not grep movss
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_zero-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_zero-2.ll
index efdf564..e42b538 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_zero-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_zero-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
define i32 @t() {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_zero.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_zero.ll
index 0a7a543..ae5af58 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_zero.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_zero.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep xorps | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep xorps | count 2
define void @foo(<4 x float>* %P) {
%T = load <4 x float>* %P ; <<4 x float>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vec_zero_cse.ll b/libclamav/c++/llvm/test/CodeGen/X86/vec_zero_cse.ll
index 0ccf745..296378c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vec_zero_cse.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vec_zero_cse.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 1
-; RUN: llvm-as < %s | llc -relocation-model=static -march=x86 -mcpu=yonah | grep xorps | count 1
-; RUN: llvm-as < %s | llc -relocation-model=static -march=x86 -mcpu=yonah | grep pcmpeqd | count 2
+; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 1
+; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep xorps | count 1
+; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pcmpeqd | count 2
@M1 = external global <1 x i64>
@M2 = external global <2 x i32>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vector-intrinsics.ll b/libclamav/c++/llvm/test/CodeGen/X86/vector-intrinsics.ll
index 3291658..edf58b9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vector-intrinsics.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vector-intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep call | count 16
+; RUN: llc < %s -march=x86-64 | grep call | count 16
declare <4 x double> @llvm.sin.v4f64(<4 x double> %p)
declare <4 x double> @llvm.cos.v4f64(<4 x double> %p)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vector-rem.ll b/libclamav/c++/llvm/test/CodeGen/X86/vector-rem.ll
index cfdd34e..51cd872 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vector-rem.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vector-rem.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep div | count 8
-; RUN: llvm-as < %s | llc -march=x86-64 | grep fmodf | count 4
+; RUN: llc < %s -march=x86-64 | grep div | count 8
+; RUN: llc < %s -march=x86-64 | grep fmodf | count 4
define <4 x i32> @foo(<4 x i32> %t, <4 x i32> %u) {
%m = srem <4 x i32> %t, %u
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vector-variable-idx.ll b/libclamav/c++/llvm/test/CodeGen/X86/vector-variable-idx.ll
index 82927e9..2a4d18c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vector-variable-idx.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vector-variable-idx.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movss | count 2
+; RUN: llc < %s -march=x86-64 | grep movss | count 2
; PR2676
define float @foo(<4 x float> %p, i32 %t) {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vector.ll b/libclamav/c++/llvm/test/CodeGen/X86/vector.ll
index 8e1de2f..3fff849 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vector.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vector.ll
@@ -1,6 +1,6 @@
; Test that vectors are scalarized/lowered correctly.
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 > %t
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah > %t
+; RUN: llc < %s -march=x86 -mcpu=i386 > %t
+; RUN: llc < %s -march=x86 -mcpu=yonah > %t
%d8 = type <8 x double>
%f1 = type <1 x float>
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vfcmp.ll b/libclamav/c++/llvm/test/CodeGen/X86/vfcmp.ll
index 6179165..f5f5293 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vfcmp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vfcmp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
; PR2620
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/volatile.ll b/libclamav/c++/llvm/test/CodeGen/X86/volatile.ll
index f919b5d..5e1e0c8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/volatile.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/volatile.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 | grep movsd | count 5
-; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -O0 | grep movsd | count 5
+; RUN: llc < %s -march=x86 -mattr=sse2 | grep movsd | count 5
+; RUN: llc < %s -march=x86 -mattr=sse2 -O0 | grep movsd | count 5
@x = external global double
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vortex-bug.ll b/libclamav/c++/llvm/test/CodeGen/X86/vortex-bug.ll
index d62bb24..40f1117 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vortex-bug.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vortex-bug.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
%struct.blktkntype = type { i32, i32 }
%struct.fieldstruc = type { [128 x i8], %struct.blktkntype*, i32, i32 }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vshift-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/vshift-1.ll
index 66a8b46..ae845e0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vshift-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vshift-1.ll
@@ -1,13 +1,12 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx -o %t
-; RUN: grep psllq %t | count 2
-; RUN: grep pslld %t | count 2
-; RUN: grep psllw %t | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
; test vector shifts converted to proper SSE2 vector shifts when the shift
; amounts are the same.
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
entry:
+; CHECK: shift1a:
+; CHECK: psllq
%shl = shl <2 x i64> %val, < i64 32, i64 32 >
store <2 x i64> %shl, <2 x i64>* %dst
ret void
@@ -15,6 +14,9 @@ entry:
define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
entry:
+; CHECK: shift1b:
+; CHECK: movd
+; CHECK-NEXT: psllq
%0 = insertelement <2 x i64> undef, i64 %amt, i32 0
%1 = insertelement <2 x i64> %0, i64 %amt, i32 1
%shl = shl <2 x i64> %val, %1
@@ -25,6 +27,8 @@ entry:
define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
entry:
+; CHECK: shift2a:
+; CHECK: pslld
%shl = shl <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
store <4 x i32> %shl, <4 x i32>* %dst
ret void
@@ -32,6 +36,9 @@ entry:
define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
entry:
+; CHECK: shift2b:
+; CHECK: movd
+; CHECK-NEXT: pslld
%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
%1 = insertelement <4 x i32> %0, i32 %amt, i32 1
%2 = insertelement <4 x i32> %1, i32 %amt, i32 2
@@ -43,13 +50,20 @@ entry:
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
entry:
+; CHECK: shift3a:
+; CHECK: psllw
%shl = shl <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
store <8 x i16> %shl, <8 x i16>* %dst
ret void
}
+; Make sure the shift amount is properly zero extended.
define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
entry:
+; CHECK: shift3b:
+; CHECK: movzwl
+; CHECK: movd
+; CHECK-NEXT: psllw
%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vshift-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/vshift-2.ll
index d47a28f..36feb11 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vshift-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vshift-2.ll
@@ -1,13 +1,12 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx -o %t
-; RUN: grep psrlq %t | count 2
-; RUN: grep psrld %t | count 2
-; RUN: grep psrlw %t | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
; test vector shifts converted to proper SSE2 vector shifts when the shift
; amounts are the same.
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
entry:
+; CHECK: shift1a:
+; CHECK: psrlq
%lshr = lshr <2 x i64> %val, < i64 32, i64 32 >
store <2 x i64> %lshr, <2 x i64>* %dst
ret void
@@ -15,6 +14,9 @@ entry:
define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
entry:
+; CHECK: shift1b:
+; CHECK: movd
+; CHECK-NEXT: psrlq
%0 = insertelement <2 x i64> undef, i64 %amt, i32 0
%1 = insertelement <2 x i64> %0, i64 %amt, i32 1
%lshr = lshr <2 x i64> %val, %1
@@ -24,6 +26,8 @@ entry:
define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
entry:
+; CHECK: shift2a:
+; CHECK: psrld
%lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 >
store <4 x i32> %lshr, <4 x i32>* %dst
ret void
@@ -31,6 +35,9 @@ entry:
define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
entry:
+; CHECK: shift2b:
+; CHECK: movd
+; CHECK-NEXT: psrld
%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
%1 = insertelement <4 x i32> %0, i32 %amt, i32 1
%2 = insertelement <4 x i32> %1, i32 %amt, i32 2
@@ -43,13 +50,20 @@ entry:
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
entry:
+; CHECK: shift3a:
+; CHECK: psrlw
%lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
store <8 x i16> %lshr, <8 x i16>* %dst
ret void
}
+; properly zero extend the shift amount
define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
entry:
+; CHECK: shift3b:
+; CHECK: movzwl
+; CHECK: movd
+; CHECK-NEXT: psrlw
%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vshift-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/vshift-3.ll
index ec08776..20d3f48 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vshift-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vshift-3.ll
@@ -1,13 +1,15 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx -o %t
-; RUN: grep psrad %t | count 2
-; RUN: grep psraw %t | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
; test vector shifts converted to proper SSE2 vector shifts when the shift
; amounts are the same.
; Note that x86 does have ashr
+
+; shift1a can't use a packed shift
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
entry:
+; CHECK: shift1a:
+; CHECK: sarl
%ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
store <2 x i64> %ashr, <2 x i64>* %dst
ret void
@@ -15,6 +17,8 @@ entry:
define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
entry:
+; CHECK: shift2a:
+; CHECK: psrad $5
%ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
store <4 x i32> %ashr, <4 x i32>* %dst
ret void
@@ -22,6 +26,9 @@ entry:
define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
entry:
+; CHECK: shift2b:
+; CHECK: movd
+; CHECK-NEXT: psrad
%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
%1 = insertelement <4 x i32> %0, i32 %amt, i32 1
%2 = insertelement <4 x i32> %1, i32 %amt, i32 2
@@ -33,6 +40,8 @@ entry:
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
entry:
+; CHECK: shift3a:
+; CHECK: psraw $5
%ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
store <8 x i16> %ashr, <8 x i16>* %dst
ret void
@@ -40,6 +49,10 @@ entry:
define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
entry:
+; CHECK: shift3b:
+; CHECK: movzwl
+; CHECK: movd
+; CHECK-NEXT: psraw
%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vshift-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/vshift-4.ll
index 332e851..9773cbe 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vshift-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vshift-4.ll
@@ -1,21 +1,23 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx -o %t
-; RUN: grep psllq %t | count 1
-; RUN: grep pslld %t | count 3
-; RUN: grep psllw %t | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
; test vector shifts converted to proper SSE2 vector shifts when the shift
; amounts are the same when using a shuffle splat.
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
entry:
+; CHECK: shift1a:
+; CHECK: psllq
%shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%shl = shl <2 x i64> %val, %shamt
store <2 x i64> %shl, <2 x i64>* %dst
ret void
}
+; shift1b can't use a packed shift
define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
entry:
+; CHECK: shift1b:
+; CHECK: shll
%shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
%shl = shl <2 x i64> %val, %shamt
store <2 x i64> %shl, <2 x i64>* %dst
@@ -24,6 +26,8 @@ entry:
define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
entry:
+; CHECK: shift2a:
+; CHECK: pslld
%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%shl = shl <4 x i32> %val, %shamt
store <4 x i32> %shl, <4 x i32>* %dst
@@ -32,6 +36,8 @@ entry:
define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
entry:
+; CHECK: shift2b:
+; CHECK: pslld
%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
%shl = shl <4 x i32> %val, %shamt
store <4 x i32> %shl, <4 x i32>* %dst
@@ -40,6 +46,8 @@ entry:
define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
entry:
+; CHECK: shift2c:
+; CHECK: pslld
%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%shl = shl <4 x i32> %val, %shamt
store <4 x i32> %shl, <4 x i32>* %dst
@@ -48,6 +56,9 @@ entry:
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
entry:
+; CHECK: shift3a:
+; CHECK: movzwl
+; CHECK: psllw
%shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
%shl = shl <8 x i16> %val, %shamt
store <8 x i16> %shl, <8 x i16>* %dst
@@ -56,6 +67,9 @@ entry:
define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
entry:
+; CHECK: shift3b:
+; CHECK: movzwl
+; CHECK: psllw
%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vshift-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/vshift-5.ll
new file mode 100644
index 0000000..a543f38
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vshift-5.ll
@@ -0,0 +1,56 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
+
+; When loading the shift amount from memory, avoid generating the splat.
+
+define void @shift5a(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
+entry:
+; CHECK: shift5a:
+; CHECK: movd
+; CHECK-NEXT: pslld
+ %amt = load i32* %pamt
+ %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+ %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
+ %shl = shl <4 x i32> %val, %shamt
+ store <4 x i32> %shl, <4 x i32>* %dst
+ ret void
+}
+
+
+define void @shift5b(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
+entry:
+; CHECK: shift5b:
+; CHECK: movd
+; CHECK-NEXT: psrad
+ %amt = load i32* %pamt
+ %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+ %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
+ %shr = ashr <4 x i32> %val, %shamt
+ store <4 x i32> %shr, <4 x i32>* %dst
+ ret void
+}
+
+
+define void @shift5c(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+entry:
+; CHECK: shift5c:
+; CHECK: movd
+; CHECK-NEXT: pslld
+ %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+ %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
+ %shl = shl <4 x i32> %val, %shamt
+ store <4 x i32> %shl, <4 x i32>* %dst
+ ret void
+}
+
+
+define void @shift5d(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+entry:
+; CHECK: shift5d:
+; CHECK: movd
+; CHECK-NEXT: psrad
+ %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+ %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
+ %shr = ashr <4 x i32> %val, %shamt
+ store <4 x i32> %shr, <4 x i32>* %dst
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vshift_scalar.ll b/libclamav/c++/llvm/test/CodeGen/X86/vshift_scalar.ll
index 8895cdf..9dd8478 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vshift_scalar.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vshift_scalar.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; Legalization test that requires scalarizing a vector.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vshift_split.ll b/libclamav/c++/llvm/test/CodeGen/X86/vshift_split.ll
index a1376e5..359d36d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vshift_split.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vshift_split.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
; Example that requires splitting and expanding a vector shift.
define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/vshift_split2.ll b/libclamav/c++/llvm/test/CodeGen/X86/vshift_split2.ll
index e943849..0f8c2b8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/vshift_split2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/vshift_split2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah
+; RUN: llc < %s -march=x86 -mcpu=yonah
; Legalization example that requires splitting a large vector into smaller pieces.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/weak.ll b/libclamav/c++/llvm/test/CodeGen/X86/weak.ll
index 28638af..8590e8d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/weak.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/weak.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llc < %s -march=x86
@a = extern_weak global i32 ; <i32*> [#uses=1]
@b = global i32* @a ; <i32**> [#uses=0]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/wide-integer-fold.ll b/libclamav/c++/llvm/test/CodeGen/X86/wide-integer-fold.ll
index 64c6d98..b3b4d24 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/wide-integer-fold.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/wide-integer-fold.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86-64 | FileCheck %s
; CHECK: movq $-65535, %rax
; DAGCombiner should fold this to a simple constant.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-1.ll
index 1408cb6..8f607f5 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; RUN: grep paddb %t | count 1
; RUN: grep pextrb %t | count 1
; RUN: not grep pextrw %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-2.ll
index 4ae57bc..e2420f0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; RUN: grep paddb %t | count 1
; RUN: grep pand %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-3.ll
index a77aa34..a22d254 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; RUN: grep paddw %t | count 1
; RUN: grep movd %t | count 2
; RUN: grep pextrw %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-4.ll
index 8ffbba6..898bff0 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; RUN: grep psubw %t | count 1
; RUN: grep pmullw %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-5.ll
index 68d87a6..1ecf09d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; RUN: grep pmulld %t | count 1
; RUN: grep psubd %t | count 1
; RUN: grep movaps %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-6.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-6.ll
index 226c397..3583258 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_arith-6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; RUN: grep mulps %t | count 1
; RUN: grep addps %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-1.ll
index 58b1d4e..441a360 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; RUN: grep paddw %t | count 1
; RUN: grep movd %t | count 1
; RUN: grep pextrd %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-2.ll
index d1b65ad..ded5707 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; RUN: grep pextrd %t | count 5
; RUN: grep movd %t | count 3
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-3.ll
index fb6ca5d..67a760f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; RUN: grep paddd %t | count 1
; RUN: grep pextrd %t | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-4.ll
index 0f3cddc..614eeed 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; RUN: grep sarb %t | count 8
; v8i8 that is widen to v16i8 then split
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-5.ll
index 1c66bc1..92618d6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-5.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; bitcast a i64 to v2i32
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-6.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-6.ll
index 730fc71..386f749 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_cast-6.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse41 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse41 -disable-mmx -o %t
; RUN: grep movd %t | count 1
; Test bit convert that requires widening in the operand.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-1.ll
index d674244..ccc8b4f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; RUN: grep pshufd %t | count 1
; RUN: grep paddd %t | count 1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-2.ll
index 4f21896..9b7ab74 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; sign extension v2i32 to v2i16
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-3.ll
index bf3df04..4ec76a9 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-3.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; grep cvtsi2ss %t | count 1
; sign to float v2i16 to v2f32
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-4.ll
index a0c45fc..61a26a8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_conv-4.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; unsigned to float v7i16 to v7f32
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_load-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_load-0.ll
new file mode 100644
index 0000000..f6c4af0
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_load-0.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -o - -march=x86-64 | FileCheck %s
+; PR4891
+
+; Both loads should happen before either store.
+
+; CHECK: movl (%rdi), %eax
+; CHECK: movl (%rsi), %ecx
+; CHECK: movl %ecx, (%rdi)
+; CHECK: movl %eax, (%rsi)
+
+define void @short2_int_swap(<2 x i16>* nocapture %b, i32* nocapture %c) nounwind {
+entry:
+ %0 = load <2 x i16>* %b, align 2 ; <<2 x i16>> [#uses=1]
+ %1 = load i32* %c, align 4 ; <i32> [#uses=1]
+ %tmp1 = bitcast i32 %1 to <2 x i16> ; <<2 x i16>> [#uses=1]
+ store <2 x i16> %tmp1, <2 x i16>* %b, align 2
+ %tmp5 = bitcast <2 x i16> %0 to <1 x i32> ; <<1 x i32>> [#uses=1]
+ %tmp3 = extractelement <1 x i32> %tmp5, i32 0 ; <i32> [#uses=1]
+ store i32 %tmp3, i32* %c, align 4
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_load-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_load-1.ll
new file mode 100644
index 0000000..2d34b31
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_load-1.ll
@@ -0,0 +1,45 @@
+; RUN: llc %s -o - -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -disable-mmx | FileCheck %s
+; PR4891
+
+; This load should be before the call, not after.
+
+; CHECK: movq compl+128(%rip), %xmm0
+; CHECK: movaps %xmm0, (%rsp)
+; CHECK: call killcommon
+
+ at compl = linkonce global [20 x i64] zeroinitializer, align 64 ; <[20 x i64]*> [#uses=1]
+
+declare void @killcommon(i32* noalias)
+
+define void @reset(<2 x float>* noalias %garbage1) {
+"file complex.c, line 27, bb1":
+ %changed = alloca i32, align 4 ; <i32*> [#uses=3]
+ br label %"file complex.c, line 27, bb13"
+
+"file complex.c, line 27, bb13": ; preds = %"file complex.c, line 27, bb1"
+ store i32 0, i32* %changed, align 4
+ %r2 = getelementptr float* bitcast ([20 x i64]* @compl to float*), i64 32 ; <float*> [#uses=1]
+ %r3 = bitcast float* %r2 to <2 x float>* ; <<2 x float>*> [#uses=1]
+ %r4 = load <2 x float>* %r3, align 4 ; <<2 x float>> [#uses=1]
+ call void @killcommon(i32* %changed)
+ br label %"file complex.c, line 34, bb4"
+
+"file complex.c, line 34, bb4": ; preds = %"file complex.c, line 27, bb13"
+ %r5 = load i32* %changed, align 4 ; <i32> [#uses=1]
+ %r6 = icmp eq i32 %r5, 0 ; <i1> [#uses=1]
+ %r7 = zext i1 %r6 to i32 ; <i32> [#uses=1]
+ %r8 = icmp ne i32 %r7, 0 ; <i1> [#uses=1]
+ br i1 %r8, label %"file complex.c, line 34, bb7", label %"file complex.c, line 27, bb5"
+
+"file complex.c, line 27, bb5": ; preds = %"file complex.c, line 34, bb4"
+ br label %"file complex.c, line 35, bb6"
+
+"file complex.c, line 35, bb6": ; preds = %"file complex.c, line 27, bb5"
+ %r11 = ptrtoint <2 x float>* %garbage1 to i64 ; <i64> [#uses=1]
+ %r12 = inttoptr i64 %r11 to <2 x float>* ; <<2 x float>*> [#uses=1]
+ store <2 x float> %r4, <2 x float>* %r12, align 4
+ br label %"file complex.c, line 34, bb7"
+
+"file complex.c, line 34, bb7": ; preds = %"file complex.c, line 35, bb6", %"file complex.c, line 34, bb4"
+ ret void
+}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_select-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_select-1.ll
index 6efc453..aca0b67 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_select-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_select-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; widening select v6i32 and then a sub
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_shuffle-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_shuffle-1.ll
index c6ae17f..15da870 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_shuffle-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_shuffle-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; widening shuffle v3float and then a add
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/widen_shuffle-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/widen_shuffle-2.ll
index 2ce0189..617cc1d 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/widen_shuffle-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/widen_shuffle-2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse42 -disable-mmx -o %t
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t
; widening shuffle v3float and then a add
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-and-mask.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-and-mask.ll
index 3d61e5d..3c73891 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-and-mask.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-and-mask.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep {movl.*%edi, %eax}
+; RUN: llc < %s | grep {movl.*%edi, %eax}
; This should be a single mov, not a load of immediate + andq.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-arg.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-arg.ll
index 22a095b..ec8dd8e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-arg.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-arg.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep {movl %edi, %eax}
+; RUN: llc < %s | grep {movl %edi, %eax}
; The input value is already sign extended, don't re-extend it.
; This testcase corresponds to:
; int test(short X) { return (int)X; }
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-asm.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-asm.ll
index 8ccf8b6..2640e59 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-asm.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-asm.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
; PR1029
target datalayout = "e-p:64:64"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-dead-stack-adjust.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-dead-stack-adjust.ll
index 15a30de..79316f2 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-dead-stack-adjust.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-dead-stack-adjust.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc | not grep rsp
-; RUN: llvm-as < %s | llc | grep cvttsd2siq
+; RUN: llc < %s | not grep rsp
+; RUN: llc < %s | grep cvttsd2siq
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-disp.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-disp.ll
index 4a8f6cd..d8059eb 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-disp.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-disp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 2
+; RUN: llc < %s -march=x86-64 | grep mov | count 2
; Fold an offset into an address even if it's not a 32-bit
; signed integer.
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-frameaddr.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-frameaddr.ll
index 8006099..57163d3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-frameaddr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-frameaddr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movq | grep rbp
+; RUN: llc < %s -march=x86-64 | grep movq | grep rbp
define i64* @stack_end_address() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-gv-offset.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-gv-offset.ll
index b89e1b9..365e4af 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-gv-offset.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-gv-offset.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep lea
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep lea
%struct.x = type { float, double }
@X = global %struct.x { float 1.000000e+00, double 2.000000e+00 }, align 16 ; <%struct.x*> [#uses=2]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-malloc.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-malloc.ll
index 4beb5c2..b4f1fa6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-malloc.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-malloc.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {shll.*3, %edi}
+; RUN: llc < %s -march=x86-64 | grep {shll.*3, %edi}
; PR3829
; The generated code should multiply by 3 (sizeof i8*) as an i32,
; not as an i64!
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-mem.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-mem.ll
index 3677ace..d15f516 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-mem.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-mem.ll
@@ -1,10 +1,9 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -o %t1
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -o %t1
; RUN: grep GOTPCREL %t1 | count 4
; RUN: grep %%rip %t1 | count 6
; RUN: grep movq %t1 | count 6
; RUN: grep leaq %t1 | count 1
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=static -o %t2
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=static -o %t2
; RUN: grep movl %t2 | count 2
; RUN: grep movq %t2 | count 2
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-1.ll
index 016528a..b21918e 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-1.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {call f at PLT} %t1
define void @g() {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-10.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-10.ll
index e0fcc05..0f65e57 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-10.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-10.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {call g at PLT} %t1
@g = alias weak i32 ()* @f
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-11.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-11.ll
index e5cad9e..ef81685 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-11.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-11.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {call __fixunsxfti at PLT} %t1
define i128 @f(x86_fp80 %a) nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-2.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-2.ll
index 0fc62ff..a52c564 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-2.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {call f} %t1
; RUN: not grep {call f at PLT} %t1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-3.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-3.ll
index 671b94d..246c00f 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-3.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-3.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {call f} %t1
; RUN: not grep {call f at PLT} %t1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-4.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-4.ll
index 10428dc..90fc119 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-4.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-4.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {movq a at GOTPCREL(%rip),} %t1
@a = global i32 0
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-5.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-5.ll
index a1f658f..6369bde 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-5.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-5.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {movl a(%rip),} %t1
; RUN: not grep GOTPCREL %t1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-6.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-6.ll
index 8897818..6e19ad3 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-6.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-6.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {movl a(%rip),} %t1
; RUN: not grep GOTPCREL %t1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-7.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-7.ll
index 57e78b6..4d98ee6 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-7.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-7.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {movq f at GOTPCREL(%rip),} %t1
define void ()* @g() nounwind {
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-8.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-8.ll
index 6231991..d3b567c 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-8.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-8.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {leaq f(%rip),} %t1
; RUN: not grep GOTPCREL %t1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-9.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-9.ll
index 3ad1d95..0761031 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-9.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-pic-9.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-as < %s | \
-; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {leaq f(%rip),} %t1
; RUN: not grep GOTPCREL %t1
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-ret0.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-ret0.ll
index d4252e7..c74f6d8 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-ret0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-ret0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 1
+; RUN: llc < %s -march=x86-64 | grep mov | count 1
define i32 @f() nounwind {
tail call void @t( i32 1 ) nounwind
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-shortint.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-shortint.ll
index 369527f..7f96543 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-shortint.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-shortint.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc | grep movswl
+; RUN: llc < %s | grep movswl
target datalayout = "e-p:64:64"
target triple = "x86_64-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-sret-return.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-sret-return.ll
index 458030c..3ee1a0b 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-sret-return.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-sret-return.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc
+; RUN: llc < %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-varargs.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-varargs.ll
index 2964dd3..428f449 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-64-varargs.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-64-varargs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -code-model=large -relocation-model=static | grep call | not grep rax
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -code-model=large -relocation-model=static | grep call | not grep rax
@.str = internal constant [26 x i8] c"%d, %f, %d, %lld, %d, %f\0A\00" ; <[26 x i8]*> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-frameaddr.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-frameaddr.ll
index b9d6d13..d595874 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-frameaddr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-frameaddr.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | grep ebp
+; RUN: llc < %s -march=x86 | grep mov | grep ebp
define i8* @t() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-frameaddr2.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-frameaddr2.ll
index f50ab07..c509115 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-frameaddr2.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-frameaddr2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 3
+; RUN: llc < %s -march=x86 | grep mov | count 3
define i8* @t() nounwind {
entry:
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/x86-store-gv-addr.ll b/libclamav/c++/llvm/test/CodeGen/X86/x86-store-gv-addr.ll
index 799340d..089517a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/x86-store-gv-addr.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/x86-store-gv-addr.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=static | not grep lea
-; RUN: llvm-as < %s | llc -mtriple=x86_64-pc-linux-gnu -relocation-model=static | not grep lea
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=static | not grep lea
+; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -relocation-model=static | not grep lea
@v = external global i32, align 8
@v_addr = external global i32*, align 8
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/xmm-r64.ll b/libclamav/c++/llvm/test/CodeGen/X86/xmm-r64.ll
index f7d2143..2a6b5c7 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/xmm-r64.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/xmm-r64.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64
+; RUN: llc < %s -march=x86-64
define <4 x i32> @test() {
%tmp1039 = call <4 x i32> @llvm.x86.sse2.psll.d( <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <<4 x i32>> [#uses=1]
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/xor-undef.ll b/libclamav/c++/llvm/test/CodeGen/X86/xor-undef.ll
deleted file mode 100644
index 0e60d4e..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/xor-undef.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep xor | count 2
-
-define <4 x i32> @t1() {
- %tmp = xor <4 x i32> undef, undef
- ret <4 x i32> %tmp
-}
-
-define i32 @t2() {
- %tmp = xor i32 undef, undef
- ret i32 %tmp
-}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/xor.ll b/libclamav/c++/llvm/test/CodeGen/X86/xor.ll
new file mode 100644
index 0000000..7bd06bb
--- /dev/null
+++ b/libclamav/c++/llvm/test/CodeGen/X86/xor.ll
@@ -0,0 +1,133 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64
+
+; Though it is undefined, we want xor undef,undef to produce zero.
+define <4 x i32> @test1() nounwind {
+ %tmp = xor <4 x i32> undef, undef
+ ret <4 x i32> %tmp
+
+; X32: test1:
+; X32: xorps %xmm0, %xmm0
+; X32: ret
+}
+
+; Though it is undefined, we want xor undef,undef to produce zero.
+define i32 @test2() nounwind{
+ %tmp = xor i32 undef, undef
+ ret i32 %tmp
+; X32: test2:
+; X32: xorl %eax, %eax
+; X32: ret
+}
+
+define i32 @test3(i32 %a, i32 %b) nounwind {
+entry:
+ %tmp1not = xor i32 %b, -2
+ %tmp3 = and i32 %tmp1not, %a
+ %tmp4 = lshr i32 %tmp3, 1
+ ret i32 %tmp4
+
+; X64: test3:
+; X64: notl %esi
+; X64: andl %edi, %esi
+; X64: movl %esi, %eax
+; X64: shrl %eax
+; X64: ret
+
+; X32: test3:
+; X32: movl 8(%esp), %eax
+; X32: notl %eax
+; X32: andl 4(%esp), %eax
+; X32: shrl %eax
+; X32: ret
+}
+
+define i32 @test4(i32 %a, i32 %b) nounwind {
+entry:
+ br label %bb
+bb:
+ %b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
+ %a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
+ %tmp3 = xor i32 %a_addr.0, %b_addr.0
+ %tmp4not = xor i32 %tmp3, 2147483647
+ %tmp6 = and i32 %tmp4not, %b_addr.0
+ %tmp8 = shl i32 %tmp6, 1
+ %tmp10 = icmp eq i32 %tmp8, 0
+ br i1 %tmp10, label %bb12, label %bb
+bb12:
+ ret i32 %tmp3
+
+; X64: test4:
+; X64: notl [[REG:%[a-z]+]]
+; X64: andl {{.*}}[[REG]]
+; X32: test4:
+; X32: notl [[REG:%[a-z]+]]
+; X32: andl {{.*}}[[REG]]
+}
+
+define i16 @test5(i16 %a, i16 %b) nounwind {
+entry:
+ br label %bb
+bb:
+ %b_addr.0 = phi i16 [ %b, %entry ], [ %tmp8, %bb ]
+ %a_addr.0 = phi i16 [ %a, %entry ], [ %tmp3, %bb ]
+ %tmp3 = xor i16 %a_addr.0, %b_addr.0
+ %tmp4not = xor i16 %tmp3, 32767
+ %tmp6 = and i16 %tmp4not, %b_addr.0
+ %tmp8 = shl i16 %tmp6, 1
+ %tmp10 = icmp eq i16 %tmp8, 0
+ br i1 %tmp10, label %bb12, label %bb
+bb12:
+ ret i16 %tmp3
+; X64: test5:
+; X64: notw [[REG:%[a-z]+]]
+; X64: andw {{.*}}[[REG]]
+; X32: test5:
+; X32: notw [[REG:%[a-z]+]]
+; X32: andw {{.*}}[[REG]]
+}
+
+define i8 @test6(i8 %a, i8 %b) nounwind {
+entry:
+ br label %bb
+bb:
+ %b_addr.0 = phi i8 [ %b, %entry ], [ %tmp8, %bb ]
+ %a_addr.0 = phi i8 [ %a, %entry ], [ %tmp3, %bb ]
+ %tmp3 = xor i8 %a_addr.0, %b_addr.0
+ %tmp4not = xor i8 %tmp3, 127
+ %tmp6 = and i8 %tmp4not, %b_addr.0
+ %tmp8 = shl i8 %tmp6, 1
+ %tmp10 = icmp eq i8 %tmp8, 0
+ br i1 %tmp10, label %bb12, label %bb
+bb12:
+ ret i8 %tmp3
+; X64: test6:
+; X64: notb [[REG:%[a-z]+]]
+; X64: andb {{.*}}[[REG]]
+; X32: test6:
+; X32: notb [[REG:%[a-z]+]]
+; X32: andb {{.*}}[[REG]]
+}
+
+define i32 @test7(i32 %a, i32 %b) nounwind {
+entry:
+ br label %bb
+bb:
+ %b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
+ %a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
+ %tmp3 = xor i32 %a_addr.0, %b_addr.0
+ %tmp4not = xor i32 %tmp3, 2147483646
+ %tmp6 = and i32 %tmp4not, %b_addr.0
+ %tmp8 = shl i32 %tmp6, 1
+ %tmp10 = icmp eq i32 %tmp8, 0
+ br i1 %tmp10, label %bb12, label %bb
+bb12:
+ ret i32 %tmp3
+; X64: test7:
+; X64: xorl $2147483646, [[REG:%[a-z]+]]
+; X64: andl {{.*}}[[REG]]
+; X32: test7:
+; X32: xorl $2147483646, [[REG:%[a-z]+]]
+; X32: andl {{.*}}[[REG]]
+}
+
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/xor_not.ll b/libclamav/c++/llvm/test/CodeGen/X86/xor_not.ll
deleted file mode 100644
index 0b1abdf..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/xor_not.ll
+++ /dev/null
@@ -1,74 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep {not\[lwb\]} | count 4
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {not\[lwb\]} | count 4
-define i32 @test(i32 %a, i32 %b) nounwind {
-entry:
- %tmp1not = xor i32 %b, -2
- %tmp3 = and i32 %tmp1not, %a
- %tmp4 = lshr i32 %tmp3, 1
- ret i32 %tmp4
-}
-
-define i32 @sum32(i32 %a, i32 %b) nounwind {
-entry:
- br label %bb
-bb:
- %b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
- %a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
- %tmp3 = xor i32 %a_addr.0, %b_addr.0
- %tmp4not = xor i32 %tmp3, 2147483647
- %tmp6 = and i32 %tmp4not, %b_addr.0
- %tmp8 = shl i32 %tmp6, 1
- %tmp10 = icmp eq i32 %tmp8, 0
- br i1 %tmp10, label %bb12, label %bb
-bb12:
- ret i32 %tmp3
-}
-
-define i16 @sum16(i16 %a, i16 %b) nounwind {
-entry:
- br label %bb
-bb:
- %b_addr.0 = phi i16 [ %b, %entry ], [ %tmp8, %bb ]
- %a_addr.0 = phi i16 [ %a, %entry ], [ %tmp3, %bb ]
- %tmp3 = xor i16 %a_addr.0, %b_addr.0
- %tmp4not = xor i16 %tmp3, 32767
- %tmp6 = and i16 %tmp4not, %b_addr.0
- %tmp8 = shl i16 %tmp6, 1
- %tmp10 = icmp eq i16 %tmp8, 0
- br i1 %tmp10, label %bb12, label %bb
-bb12:
- ret i16 %tmp3
-}
-
-define i8 @sum8(i8 %a, i8 %b) nounwind {
-entry:
- br label %bb
-bb:
- %b_addr.0 = phi i8 [ %b, %entry ], [ %tmp8, %bb ]
- %a_addr.0 = phi i8 [ %a, %entry ], [ %tmp3, %bb ]
- %tmp3 = xor i8 %a_addr.0, %b_addr.0
- %tmp4not = xor i8 %tmp3, 127
- %tmp6 = and i8 %tmp4not, %b_addr.0
- %tmp8 = shl i8 %tmp6, 1
- %tmp10 = icmp eq i8 %tmp8, 0
- br i1 %tmp10, label %bb12, label %bb
-bb12:
- ret i8 %tmp3
-}
-
-define i32 @test2(i32 %a, i32 %b) nounwind {
-entry:
- br label %bb
-bb:
- %b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
- %a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
- %tmp3 = xor i32 %a_addr.0, %b_addr.0
- %tmp4not = xor i32 %tmp3, 2147483646
- %tmp6 = and i32 %tmp4not, %b_addr.0
- %tmp8 = shl i32 %tmp6, 1
- %tmp10 = icmp eq i32 %tmp8, 0
- br i1 %tmp10, label %bb12, label %bb
-bb12:
- ret i32 %tmp3
-}
-
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/xorl.ll b/libclamav/c++/llvm/test/CodeGen/X86/xorl.ll
deleted file mode 100644
index def2f06..0000000
--- a/libclamav/c++/llvm/test/CodeGen/X86/xorl.ll
+++ /dev/null
@@ -1,85 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86 | grep xorl | count 1
-
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
-target triple = "i386-apple-darwin9"
- %struct.block_symbol = type { [3 x %struct.cgraph_rtl_info], %struct.object_block*, i64 }
- %struct.rtx_def = type <{ i16, i8, i8, %struct.u }>
- %struct.u = type { %struct.block_symbol }
- %struct.cgraph_rtl_info = type { i32 }
- %struct.object_block = type { %struct.section*, i32, i64, %struct.VEC_rtx_gc*, %struct.VEC_rtx_gc* }
- %struct.section = type { %struct.unnamed_section }
- %struct.VEC_rtx_base = type { i32, i32, [1 x %struct.rtx_def*] }
- %struct.VEC_rtx_gc = type { %struct.VEC_rtx_base }
- %struct.tree_common = type <{ %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8, [3 x i8] }>
- %struct.tree_complex = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node* }
- %struct.tree_node = type { %struct.tree_complex, [116 x i8] }
- %struct.unnamed_section = type { %struct.cgraph_rtl_info, void (i8*)*, i8*, %struct.section* }
- %union.tree_ann_d = type opaque
-
-define %struct.rtx_def* @expand_call() nounwind {
-entry:
- br i1 false, label %bb216, label %bb171
-bb171: ; preds = %entry
- ret %struct.rtx_def* null
-bb216: ; preds = %entry
- br i1 false, label %bb336, label %bb222
-bb222: ; preds = %bb216
- ret %struct.rtx_def* null
-bb336: ; preds = %bb216
- br i1 false, label %bb429, label %bb417
-bb417: ; preds = %bb336
- ret %struct.rtx_def* null
-bb429: ; preds = %bb336
- br i1 false, label %bb713, label %bb493
-bb493: ; preds = %bb429
- ret %struct.rtx_def* null
-bb713: ; preds = %bb429
- br i1 false, label %bb810, label %bb797
-bb797: ; preds = %bb713
- ret %struct.rtx_def* null
-bb810: ; preds = %bb713
- br i1 false, label %bb822, label %bb815
-bb815: ; preds = %bb810
- ret %struct.rtx_def* null
-bb822: ; preds = %bb810
- br label %bb1652.preheader
-bb919: ; preds = %bb1652.preheader
- ret %struct.rtx_def* null
-bb1657: ; preds = %bb1652.preheader
- br i1 false, label %bb1666, label %bb1652.preheader
-bb1652.preheader: ; preds = %bb1657, %bb822
- br i1 false, label %bb1657, label %bb919
-bb1666: ; preds = %bb1657
- br i1 false, label %bb1815.preheader, label %bb1870
-bb1815.preheader: ; preds = %bb1666
- br i1 false, label %bb1693, label %bb1828
-bb1693: ; preds = %bb1815.preheader
- br i1 false, label %bb1718, label %bb1703
-bb1703: ; preds = %bb1693
- ret %struct.rtx_def* null
-bb1718: ; preds = %bb1693
- br i1 false, label %bb1741, label %bb1828
-bb1741: ; preds = %bb1718
- switch i8 0, label %bb1775 [
- i8 54, label %bb1798
- i8 58, label %bb1798
- i8 55, label %bb1798
- ]
-bb1775: ; preds = %bb1741
- ret %struct.rtx_def* null
-bb1798: ; preds = %bb1741, %bb1741, %bb1741
- %tmp1811 = add i32 0, 0 ; <i32> [#uses=1]
- br label %bb1828
-bb1828: ; preds = %bb1798, %bb1718, %bb1815.preheader
- %copy_to_evaluate_size.1.lcssa = phi i32 [ 0, %bb1815.preheader ], [ %tmp1811, %bb1798 ], [ 0, %bb1718 ] ; <i32> [#uses=1]
- %tmp1830 = shl i32 %copy_to_evaluate_size.1.lcssa, 1 ; <i32> [#uses=1]
- %tmp18301831 = sext i32 %tmp1830 to i64 ; <i64> [#uses=1]
- %tmp1835 = icmp slt i64 %tmp18301831, 0 ; <i1> [#uses=1]
- %tmp1835.not = xor i1 %tmp1835, true ; <i1> [#uses=1]
- %bothcond6193 = and i1 %tmp1835.not, false ; <i1> [#uses=1]
- br i1 %bothcond6193, label %bb1845, label %bb1870
-bb1845: ; preds = %bb1828
- ret %struct.rtx_def* null
-bb1870: ; preds = %bb1828, %bb1666
- ret %struct.rtx_def* null
-}
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/zero-remat.ll b/libclamav/c++/llvm/test/CodeGen/X86/zero-remat.ll
index 0bf5282..3e3bb95 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/zero-remat.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/zero-remat.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | FileCheck %s --check-prefix=CHECK-64
-; RUN: llvm-as < %s | llc -march=x86-64 -stats -info-output-file - | grep asm-printer | grep 12
-; RUN: llvm-as < %s | llc -march=x86 | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc < %s -march=x86-64 -stats -info-output-file - | grep asm-printer | grep 12
+; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
declare void @bar(double %x)
declare void @barf(float %x)
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/zext-inreg-0.ll b/libclamav/c++/llvm/test/CodeGen/X86/zext-inreg-0.ll
index 1a73464..ae6221a 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/zext-inreg-0.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/zext-inreg-0.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep and
-; RUN: llvm-as < %s | llc -march=x86-64 > %t
+; RUN: llc < %s -march=x86 | not grep and
+; RUN: llc < %s -march=x86-64 > %t
; RUN: not grep and %t
; RUN: not grep movzbq %t
; RUN: not grep movzwq %t
diff --git a/libclamav/c++/llvm/test/CodeGen/X86/zext-inreg-1.ll b/libclamav/c++/llvm/test/CodeGen/X86/zext-inreg-1.ll
index bc8e482..17fe374 100644
--- a/libclamav/c++/llvm/test/CodeGen/X86/zext-inreg-1.ll
+++ b/libclamav/c++/llvm/test/CodeGen/X86/zext-inreg-1.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep and
+; RUN: llc < %s -march=x86 | not grep and
; These tests differ from the ones in zext-inreg-0.ll in that
; on x86-64 they do require and instructions.
diff --git a/libclamav/c++/llvm/test/Feature/embeddedmetadata.ll b/libclamav/c++/llvm/test/Feature/embeddedmetadata.ll
deleted file mode 100644
index 6912cd9..0000000
--- a/libclamav/c++/llvm/test/Feature/embeddedmetadata.ll
+++ /dev/null
@@ -1,20 +0,0 @@
-; RUN: llvm-as < %s | llvm-dis | not grep undef
-
-declare i8 @llvm.something(metadata %a, i32 %b, metadata %c)
-
-;; Simple MDNode
-!21 = metadata !{i17 123, null, metadata !"foobar"}
-
-define void @foo() {
- ;; Intrinsic using MDNode and MDString
- %x = call i8 @llvm.something(metadata !21, i32 42, metadata !"bar")
- ret void
-}
-
-;; Test forward reference
-declare i8 @llvm.f2(metadata %a)
-define void @f2() {
- %x = call i8 @llvm.f2(metadata !2)
- ret void
-}
-!2 = metadata !{i32 420}
diff --git a/libclamav/c++/llvm/test/Feature/float.ll b/libclamav/c++/llvm/test/Feature/float.ll
index 632cfb7..6c6c5dd 100644
--- a/libclamav/c++/llvm/test/Feature/float.ll
+++ b/libclamav/c++/llvm/test/Feature/float.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llvm-dis > t1.ll
-; RUN: llvm-as t1.ll -o - | llvm-dis > t2.ll
-; RUN: diff t1.ll t2.ll
+; RUN: llvm-as < %s | llvm-dis > %t1.ll
+; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
+; RUN: diff %t1.ll %t2.ll
@F1 = global float 0x4010000000000000
@D1 = global double 0x4010000000000000
diff --git a/libclamav/c++/llvm/test/Feature/inlineasm.ll b/libclamav/c++/llvm/test/Feature/inlineasm.ll
index e4318f7..6be5722 100644
--- a/libclamav/c++/llvm/test/Feature/inlineasm.ll
+++ b/libclamav/c++/llvm/test/Feature/inlineasm.ll
@@ -1,6 +1,6 @@
-; RUN: llvm-as < %s | llvm-dis > t1.ll
-; RUN: llvm-as t1.ll -o - | llvm-dis > t2.ll
-; RUN: diff t1.ll t2.ll
+; RUN: llvm-as < %s | llvm-dis > %t1.ll
+; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
+; RUN: diff %t1.ll %t2.ll
module asm "this is an inline asm block"
module asm "this is another inline asm block"
diff --git a/libclamav/c++/llvm/test/Feature/load_module.ll b/libclamav/c++/llvm/test/Feature/load_module.ll
index 356eceb..e2e222f 100644
--- a/libclamav/c++/llvm/test/Feature/load_module.ll
+++ b/libclamav/c++/llvm/test/Feature/load_module.ll
@@ -1,6 +1,6 @@
; PR1318
-; RUN: llvm-as < %s | opt -load=%llvmlibsdir/LLVMHello%shlibext -hello \
-; RUN: -disable-output - |& grep Hello
+; RUN: opt < %s -load=%llvmlibsdir/LLVMHello%shlibext -hello \
+; RUN: -disable-output |& grep Hello
@junk = global i32 0
diff --git a/libclamav/c++/llvm/test/Feature/md_on_instruction.ll b/libclamav/c++/llvm/test/Feature/md_on_instruction.ll
new file mode 100644
index 0000000..d765cd8
--- /dev/null
+++ b/libclamav/c++/llvm/test/Feature/md_on_instruction.ll
@@ -0,0 +1,23 @@
+; RUN: llvm-as < %s -disable-output
+
+define i32 @foo() nounwind ssp {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ call void @llvm.dbg.func.start(metadata !0)
+ store i32 42, i32* %retval, !dbg !3
+ br label %0, !dbg !3
+
+; <label>:0 ; preds = %entry
+ call void @llvm.dbg.region.end(metadata !0)
+ %1 = load i32* %retval, !dbg !3 ; <i32> [#uses=1]
+ ret i32 %1, !dbg !3
+}
+
+declare void @llvm.dbg.func.start(metadata) nounwind readnone
+
+declare void @llvm.dbg.region.end(metadata) nounwind readnone
+
+!0 = metadata !{i32 458798, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 1, metadata !2, i1 false, i1 true}
+!1 = metadata !{i32 458769, i32 0, i32 12, metadata !"foo.c", metadata !"/tmp", metadata !"clang 1.0", i1 true, i1 false, metadata !"", i32 0}
+!2 = metadata !{i32 458788, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
+!3 = metadata !{i32 1, i32 13, metadata !1, metadata !1}
diff --git a/libclamav/c++/llvm/test/Feature/md_on_instruction2.ll b/libclamav/c++/llvm/test/Feature/md_on_instruction2.ll
new file mode 100644
index 0000000..da9e49e
--- /dev/null
+++ b/libclamav/c++/llvm/test/Feature/md_on_instruction2.ll
@@ -0,0 +1,22 @@
+; RUN: llvm-as < %s | llvm-dis | grep " !dbg " | count 4
+define i32 @foo() nounwind ssp {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ call void @llvm.dbg.func.start(metadata !0)
+ store i32 42, i32* %retval, !dbg !3
+ br label %0, !dbg !3
+
+; <label>:0 ; preds = %entry
+ call void @llvm.dbg.region.end(metadata !0)
+ %1 = load i32* %retval, !dbg !3 ; <i32> [#uses=1]
+ ret i32 %1, !dbg !3
+}
+
+declare void @llvm.dbg.func.start(metadata) nounwind readnone
+
+declare void @llvm.dbg.region.end(metadata) nounwind readnone
+
+!0 = metadata !{i32 458798, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 1, metadata !2, i1 false, i1 true}
+!1 = metadata !{i32 458769, i32 0, i32 12, metadata !"foo.c", metadata !"/tmp", metadata !"clang 1.0", i1 true, i1 false, metadata !"", i32 0}
+!2 = metadata !{i32 458788, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
+!3 = metadata !{i32 1, i32 13, metadata !1, metadata !1}
diff --git a/libclamav/c++/llvm/test/Feature/weak_constant.ll b/libclamav/c++/llvm/test/Feature/weak_constant.ll
index d27adfe..9025aaa 100644
--- a/libclamav/c++/llvm/test/Feature/weak_constant.ll
+++ b/libclamav/c++/llvm/test/Feature/weak_constant.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -std-compile-opts | llvm-dis > %t
+; RUN: opt < %s -std-compile-opts -S > %t
; RUN: grep undef %t | count 1
; RUN: grep 5 %t | count 1
; RUN: grep 7 %t | count 1
diff --git a/libclamav/c++/llvm/test/Integer/varargs_bt.ll b/libclamav/c++/llvm/test/Integer/varargs_bt.ll
index e740fd3..25ad58a 100644
--- a/libclamav/c++/llvm/test/Integer/varargs_bt.ll
+++ b/libclamav/c++/llvm/test/Integer/varargs_bt.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s -o - | llvm-dis > %t1.ll;
+; RUN: llvm-as %s -o - | llvm-dis > %t1.ll
; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
; RUN: diff %t1.ll %t2.ll
diff --git a/libclamav/c++/llvm/test/Makefile b/libclamav/c++/llvm/test/Makefile
index 36b3223..6c931e3 100644
--- a/libclamav/c++/llvm/test/Makefile
+++ b/libclamav/c++/llvm/test/Makefile
@@ -28,16 +28,41 @@ endif
ifdef VERBOSE
RUNTESTFLAGS := $(VERBOSE)
+LIT_ARGS := -v
+else
+LIT_ARGS := -s -v
endif
ifdef TESTSUITE
+LIT_TESTSUITE := $(TESTSUITE)
CLEANED_TESTSUITE := $(patsubst %/,%,$(TESTSUITE))
CLEANED_TESTSUITE := $(patsubst test/%,%,$(CLEANED_TESTSUITE))
RUNTESTFLAGS += --tool $(CLEANED_TESTSUITE)
+else
+LIT_TESTSUITE := .
endif
ifdef VG
-VALGRIND := valgrind --tool=memcheck --quiet --trace-children=yes --error-exitcode=3 --leak-check=full
+VALGRIND := valgrind --tool=memcheck --quiet --trace-children=yes --error-exitcode=3 --leak-check=full $(VALGRIND_EXTRA_ARGS)
+endif
+
+# Check what to run for -all.
+LIT_ALL_TESTSUITES := $(LIT_TESTSUITE)
+
+extra-lit-site-cfgs::
+.PHONY: extra-lit-site-cfgs
+
+ifneq ($(strip $(filter check-local-all,$(MAKECMDGOALS))),)
+ifndef TESTSUITE
+ifeq ($(shell test -d $(PROJ_SRC_DIR)/../tools/clang && echo OK), OK)
+LIT_ALL_TESTSUITES += $(PROJ_OBJ_DIR)/../tools/clang/test
+
+# Force creation of Clang's lit.site.cfg.
+clang-lit-site-cfg: FORCE
+ $(MAKE) -C $(PROJ_OBJ_DIR)/../tools/clang/test lit.site.cfg
+extra-lit-site-cfgs:: clang-lit-site-cfg
+endif
+endif
endif
IGNORE_TESTS :=
@@ -46,8 +71,6 @@ ifndef RUNLLVM2CPP
IGNORE_TESTS += llvm2cpp.exp
endif
-IGNORE_TESTS += $(filter-out $(BINDINGS_TO_BUILD:=.exp),$(ALL_BINDINGS:=.exp))
-
ifdef IGNORE_TESTS
RUNTESTFLAGS += --ignore "$(strip $(IGNORE_TESTS))"
endif
@@ -62,13 +85,29 @@ endif
ifneq ($(RUNTEST),)
check-local:: site.exp
( $(ULIMIT) \
- PATH="$(LLVMToolDir):$(LLVM_SRC_ROOT)/test/Scripts:$(PATH)" \
+ PATH="$(LLVMToolDir):$(LLVM_SRC_ROOT)/test/Scripts:$(LLVMGCCDIR)/bin:$(PATH)" \
$(RUNTEST) $(RUNTESTFLAGS) )
else
check-local:: site.exp
@echo "*** dejagnu not found. Make sure 'runtest' is in your PATH, then reconfigure LLVM."
endif
+check-local-lit:: lit.site.cfg Unit/lit.site.cfg
+ ( $(ULIMIT) \
+ $(LLVM_SRC_ROOT)/utils/lit/lit.py \
+ --path "$(LLVMToolDir)" \
+ --path "$(LLVM_SRC_ROOT)/test/Scripts" \
+ --path "$(LLVMGCCDIR)/bin" \
+ $(LIT_ARGS) $(LIT_TESTSUITE) )
+
+check-local-all:: lit.site.cfg Unit/lit.site.cfg extra-lit-site-cfgs
+ ( $(ULIMIT) \
+ $(LLVM_SRC_ROOT)/utils/lit/lit.py \
+ --path "$(LLVMToolDir)" \
+ --path "$(LLVM_SRC_ROOT)/test/Scripts" \
+ --path "$(LLVMGCCDIR)/bin" \
+ $(LIT_ARGS) $(LIT_ALL_TESTSUITES) )
+
ifdef TESTONE
CLEANED_TESTONE := $(patsubst %/,%,$(TESTONE))
CLEANED_TESTONE := $(patsubst test/%,%,$(CLEANED_TESTONE))
@@ -104,9 +143,9 @@ else
BUGPOINT_TOPTS=""
endif
-ifneq ($(OCAMLC),)
-CC_FOR_OCAMLC := $(shell $(OCAMLC) -config | grep native_c_compiler | sed -e 's/native_c_compiler: //')
-CXX_FOR_OCAMLC := $(subst gcc,g++,$(CC_FOR_OCAMLC))
+ifneq ($(OCAMLOPT),)
+CC_FOR_OCAMLOPT := $(shell $(OCAMLOPT) -config | grep native_c_compiler | sed -e 's/native_c_compiler: //')
+CXX_FOR_OCAMLOPT := $(subst gcc,g++,$(CC_FOR_OCAMLOPT))
endif
FORCE:
@@ -120,9 +159,9 @@ site.exp: FORCE
@echo 'set TARGETS_TO_BUILD "$(TARGETS_TO_BUILD)"' >> site.tmp
@echo 'set llvmgcc_langs "$(LLVMGCC_LANGS)"' >> site.tmp
@echo 'set llvmgcc_version "$(LLVMGCC_VERSION)"' >> site.tmp
- @echo 'set prcontext "$(TCLSH) $(LLVM_SRC_ROOT)/test/Scripts/prcontext.tcl"' >> site.tmp
@echo 'set llvmtoolsdir "$(ToolDir)"' >>site.tmp
@echo 'set llvmlibsdir "$(LibDir)"' >>site.tmp
+ @echo 'set llvm_bindings "$(BINDINGS_TO_BUILD)"' >> site.tmp
@echo 'set srcroot "$(LLVM_SRC_ROOT)"' >>site.tmp
@echo 'set objroot "$(LLVM_OBJ_ROOT)"' >>site.tmp
@echo 'set srcdir "$(LLVM_SRC_ROOT)/test"' >>site.tmp
@@ -137,7 +176,7 @@ site.exp: FORCE
@echo 'set llvmgccmajvers "$(LLVMGCC_MAJVERS)"' >> site.tmp
@echo 'set bugpoint_topts $(BUGPOINT_TOPTS)' >> site.tmp
@echo 'set shlibext "$(SHLIBEXT)"' >> site.tmp
- @echo 'set ocamlc "$(OCAMLC) -cc \"$(CXX_FOR_OCAMLC)\" -I $(LibDir)/ocaml"' >> site.tmp
+ @echo 'set ocamlopt "$(OCAMLOPT) -cc \"$(CXX_FOR_OCAMLOPT)\" -I $(LibDir)/ocaml"' >> site.tmp
@echo 'set valgrind "$(VALGRIND)"' >> site.tmp
@echo 'set grep "$(GREP)"' >>site.tmp
@echo 'set gas "$(GAS)"' >>site.tmp
@@ -148,3 +187,26 @@ site.exp: FORCE
@-rm -f site.bak
@test ! -f site.exp || mv site.exp site.bak
@mv site.tmp site.exp
+
+lit.site.cfg: site.exp
+ @echo "Making LLVM 'lit.site.cfg' file..."
+ @sed -e "s#@LLVM_SOURCE_DIR@#$(LLVM_SRC_ROOT)#g" \
+ -e "s#@LLVM_BINARY_DIR@#$(LLVM_OBJ_ROOT)#g" \
+ -e "s#@LLVM_TOOLS_DIR@#$(ToolDir)#g" \
+ -e "s#@LLVMGCCDIR@#$(LLVMGCCDIR)#g" \
+ $(PROJ_SRC_DIR)/lit.site.cfg.in > $@
+
+Unit/lit.site.cfg: Unit/.dir FORCE
+ @echo "Making LLVM unittest 'lit.site.cfg' file..."
+ @echo "## Autogenerated by Makefile ##" > $@
+ @echo "# Do not edit!" >> $@
+ @echo >> $@
+ @echo "# Preserve some key paths for use by main LLVM test suite config." >> $@
+ @echo "config.llvm_obj_root = \"\"\"$(LLVM_OBJ_ROOT)\"\"\"" >> $@
+ @echo >> $@
+ @echo "# Remember the build mode." >> $@
+ @echo "config.llvm_build_mode = \"\"\"$(BuildMode)\"\"\"" >> $@
+ @echo >> $@
+ @echo "# Let the main config do the real work." >> $@
+ @echo "lit.load_config(config, \"\"\"$(LLVM_SRC_ROOT)/test/Unit/lit.cfg\"\"\")" >> $@
+
diff --git a/libclamav/c++/llvm/test/Other/2002-01-31-CallGraph.ll b/libclamav/c++/llvm/test/Other/2002-01-31-CallGraph.ll
index bb4c23e..0e4c877 100644
--- a/libclamav/c++/llvm/test/Other/2002-01-31-CallGraph.ll
+++ b/libclamav/c++/llvm/test/Other/2002-01-31-CallGraph.ll
@@ -1,6 +1,6 @@
; Call graph construction crash: Not handling indirect calls right
;
-; RUN: llvm-as < %s | opt -analyze -print-callgraph >& /dev/null
+; RUN: opt < %s -analyze -print-callgraph >& /dev/null
;
%FunTy = type i32 (i32)
diff --git a/libclamav/c++/llvm/test/Other/2002-02-24-InlineBrokePHINodes.ll b/libclamav/c++/llvm/test/Other/2002-02-24-InlineBrokePHINodes.ll
index cbb1a89..db26942 100644
--- a/libclamav/c++/llvm/test/Other/2002-02-24-InlineBrokePHINodes.ll
+++ b/libclamav/c++/llvm/test/Other/2002-02-24-InlineBrokePHINodes.ll
@@ -1,7 +1,7 @@
; Inlining used to break PHI nodes. This tests that they are correctly updated
; when a node is split around the call instruction. The verifier caught the error.
;
-; RUN: llvm-as < %s | opt -inline
+; RUN: opt < %s -inline
;
define i64 @test(i64 %X) {
diff --git a/libclamav/c++/llvm/test/Other/2002-03-11-ConstPropCrash.ll b/libclamav/c++/llvm/test/Other/2002-03-11-ConstPropCrash.ll
index 90dc002..a6d4f5b 100644
--- a/libclamav/c++/llvm/test/Other/2002-03-11-ConstPropCrash.ll
+++ b/libclamav/c++/llvm/test/Other/2002-03-11-ConstPropCrash.ll
@@ -5,7 +5,7 @@
;
; Fixed by adding new arguments to ConstantFoldTerminator
;
-; RUN: llvm-as < %s | opt -constprop
+; RUN: opt < %s -constprop
define void @build_tree(i32 %ml) {
; <label>:0
diff --git a/libclamav/c++/llvm/test/Other/2003-02-19-LoopInfoNestingBug.ll b/libclamav/c++/llvm/test/Other/2003-02-19-LoopInfoNestingBug.ll
index d294553..267b0e8 100644
--- a/libclamav/c++/llvm/test/Other/2003-02-19-LoopInfoNestingBug.ll
+++ b/libclamav/c++/llvm/test/Other/2003-02-19-LoopInfoNestingBug.ll
@@ -2,7 +2,7 @@
; figure out that loop "Inner" should be nested inside of leep "LoopHeader",
; and instead nests it just inside loop "Top"
;
-; RUN: llvm-as < %s | opt -analyze -loops | \
+; RUN: opt < %s -analyze -loops | \
; RUN: grep { Loop at depth 3 containing: %Inner<header><latch><exit>}
;
define void @test() {
diff --git a/libclamav/c++/llvm/test/Other/2006-02-05-PassManager.ll b/libclamav/c++/llvm/test/Other/2006-02-05-PassManager.ll
index c5f50ec..0ab5411 100644
--- a/libclamav/c++/llvm/test/Other/2006-02-05-PassManager.ll
+++ b/libclamav/c++/llvm/test/Other/2006-02-05-PassManager.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -domtree -gvn -domtree -constmerge -disable-output
+; RUN: opt < %s -domtree -gvn -domtree -constmerge -disable-output
define i32 @test1() {
unreachable
diff --git a/libclamav/c++/llvm/test/Other/2007-04-24-eliminate-mostly-empty-blocks.ll b/libclamav/c++/llvm/test/Other/2007-04-24-eliminate-mostly-empty-blocks.ll
index 4ffcf96..c436e07 100644
--- a/libclamav/c++/llvm/test/Other/2007-04-24-eliminate-mostly-empty-blocks.ll
+++ b/libclamav/c++/llvm/test/Other/2007-04-24-eliminate-mostly-empty-blocks.ll
@@ -1,4 +1,4 @@
-;RUN: llvm-as < %s | opt -codegenprepare -disable-output
+;RUN: opt < %s -codegenprepare -disable-output
define void @foo() {
entry:
diff --git a/libclamav/c++/llvm/test/Other/2007-06-05-PassID.ll b/libclamav/c++/llvm/test/Other/2007-06-05-PassID.ll
index b6bba36..7a03544 100644
--- a/libclamav/c++/llvm/test/Other/2007-06-05-PassID.ll
+++ b/libclamav/c++/llvm/test/Other/2007-06-05-PassID.ll
@@ -1,4 +1,4 @@
-;RUN: llvm-as < %s | opt -analyze -dot-cfg-only -disable-output 2>/dev/null
+;RUN: opt < %s -analyze -dot-cfg-only -disable-output 2>/dev/null
;PR 1497
define void @foo() {
diff --git a/libclamav/c++/llvm/test/Other/2007-06-28-PassManager.ll b/libclamav/c++/llvm/test/Other/2007-06-28-PassManager.ll
index 5968d8c..f097f59 100644
--- a/libclamav/c++/llvm/test/Other/2007-06-28-PassManager.ll
+++ b/libclamav/c++/llvm/test/Other/2007-06-28-PassManager.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | opt -analyze -inline -disable-output
-; PR 1526
-; RUN: llvm-as < %s | opt -analyze -indvars -disable-output
-; PR 1539
+; RUN: opt < %s -analyze -inline -disable-output
+; PR1526
+; RUN: opt < %s -analyze -indvars -disable-output
+; PR1539
define i32 @test1() {
ret i32 0;
}
diff --git a/libclamav/c++/llvm/test/Other/2007-09-10-PassManager.ll b/libclamav/c++/llvm/test/Other/2007-09-10-PassManager.ll
index 863be33..ded15e5 100644
--- a/libclamav/c++/llvm/test/Other/2007-09-10-PassManager.ll
+++ b/libclamav/c++/llvm/test/Other/2007-09-10-PassManager.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -loop-unswitch -indvars -disable-output
+; RUN: opt < %s -loop-unswitch -indvars -disable-output
; Require SCEV before LCSSA.
define void @foo() {
entry:
diff --git a/libclamav/c++/llvm/test/Other/2008-02-14-PassManager.ll b/libclamav/c++/llvm/test/Other/2008-02-14-PassManager.ll
index 985e190..6b51edb 100644
--- a/libclamav/c++/llvm/test/Other/2008-02-14-PassManager.ll
+++ b/libclamav/c++/llvm/test/Other/2008-02-14-PassManager.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | opt -loop-unroll -loop-rotate -simplifycfg -disable-output
-; PR 2028
+; RUN: opt < %s -loop-unroll -loop-rotate -simplifycfg -disable-output
+; PR2028
define i32 @test1() {
ret i32 0;
}
diff --git a/libclamav/c++/llvm/test/Other/2008-03-19-PassManager.ll b/libclamav/c++/llvm/test/Other/2008-03-19-PassManager.ll
index 832465c..e208222 100644
--- a/libclamav/c++/llvm/test/Other/2008-03-19-PassManager.ll
+++ b/libclamav/c++/llvm/test/Other/2008-03-19-PassManager.ll
@@ -1,5 +1,5 @@
; PR 2034
-; RUN: llvm-as < %s | opt -anders-aa -instcombine -gvn -disable-output
+; RUN: opt < %s -anders-aa -instcombine -gvn -disable-output
%struct.FULL = type { i32, i32, [1000 x float*] }
define i32 @sgesl(%struct.FULL* %a, i32* %ipvt, float* %b, i32 %job) {
diff --git a/libclamav/c++/llvm/test/Other/2008-06-04-FieldSizeInPacked.ll b/libclamav/c++/llvm/test/Other/2008-06-04-FieldSizeInPacked.ll
index f718dd3..d90209f 100644
--- a/libclamav/c++/llvm/test/Other/2008-06-04-FieldSizeInPacked.ll
+++ b/libclamav/c++/llvm/test/Other/2008-06-04-FieldSizeInPacked.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep true
+; RUN: opt < %s -instcombine -S | grep true
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/libclamav/c++/llvm/test/Other/2008-08-14-PassManager.ll b/libclamav/c++/llvm/test/Other/2008-08-14-PassManager.ll
index 110f380..22a421d 100644
--- a/libclamav/c++/llvm/test/Other/2008-08-14-PassManager.ll
+++ b/libclamav/c++/llvm/test/Other/2008-08-14-PassManager.ll
@@ -1,5 +1,5 @@
-; RUN: llvm-as < %s | opt -loop-deletion -loop-index-split -disable-output
-; PR 2640
+; RUN: opt < %s -loop-deletion -loop-index-split -disable-output
+; PR2640
define i32 @test1() {
ret i32 0;
}
diff --git a/libclamav/c++/llvm/test/Other/2008-10-06-RemoveDeadPass.ll b/libclamav/c++/llvm/test/Other/2008-10-06-RemoveDeadPass.ll
index a82d1b6..7cec2c5 100644
--- a/libclamav/c++/llvm/test/Other/2008-10-06-RemoveDeadPass.ll
+++ b/libclamav/c++/llvm/test/Other/2008-10-06-RemoveDeadPass.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -inline -internalize -disable-output
+; RUN: opt < %s -inline -internalize -disable-output
define void @foo() nounwind {
ret void
}
diff --git a/libclamav/c++/llvm/test/Other/2009-03-31-CallGraph.ll b/libclamav/c++/llvm/test/Other/2009-03-31-CallGraph.ll
index 43578be..d6653ec 100644
--- a/libclamav/c++/llvm/test/Other/2009-03-31-CallGraph.ll
+++ b/libclamav/c++/llvm/test/Other/2009-03-31-CallGraph.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -inline -prune-eh -disable-output
+; RUN: opt < %s -inline -prune-eh -disable-output
define void @f2() {
invoke void @f6()
to label %ok1 unwind label %lpad1
diff --git a/libclamav/c++/llvm/test/Other/2009-06-05-no-implicit-float.ll b/libclamav/c++/llvm/test/Other/2009-06-05-no-implicit-float.ll
index 5addfe2..0d02e3c 100644
--- a/libclamav/c++/llvm/test/Other/2009-06-05-no-implicit-float.ll
+++ b/libclamav/c++/llvm/test/Other/2009-06-05-no-implicit-float.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -verify | llvm-dis | grep noimplicitfloat
+; RUN: opt < %s -verify -S | grep noimplicitfloat
define void @f() noimplicitfloat {
}
diff --git a/libclamav/c++/llvm/test/Other/2009-09-14-function-elements.ll b/libclamav/c++/llvm/test/Other/2009-09-14-function-elements.ll
new file mode 100644
index 0000000..883d76d
--- /dev/null
+++ b/libclamav/c++/llvm/test/Other/2009-09-14-function-elements.ll
@@ -0,0 +1,6 @@
+; RUN: not llvm-as %s -disable-output 2>/dev/null
+
+; Arrays and structures with function types (not function pointers) are illegal.
+
+ at foo = external global [4 x i32 (i32)]
+ at bar = external global { i32 (i32) }
diff --git a/libclamav/c++/llvm/test/Scripts/count b/libclamav/c++/llvm/test/Scripts/count
deleted file mode 100755
index 1c3d7e0..0000000
--- a/libclamav/c++/llvm/test/Scripts/count
+++ /dev/null
@@ -1,17 +0,0 @@
-#!/bin/sh
-#
-# Program: count
-#
-# Synopsis: Count the number of lines of input on stdin and test that it
-# matches the specified number.
-#
-# Syntax: count <number>
-
-set -e
-set -u
-input_lines=`wc -l`
-if [ "$input_lines" -ne "$1" ]; then
- echo "count: expected $1 lines and got ${input_lines}."
- exit 1
-fi
-exit 0
diff --git a/libclamav/c++/llvm/test/Scripts/not b/libclamav/c++/llvm/test/Scripts/not
deleted file mode 100755
index e3b1efe..0000000
--- a/libclamav/c++/llvm/test/Scripts/not
+++ /dev/null
@@ -1,12 +0,0 @@
-#!/bin/sh
-#
-# Program: not
-#
-# Synopsis: Inverse the output of the program specified on the command line
-#
-# Syntax: not command <arguments>
-
-if "$@"
-then exit 1
-else exit 0
-fi
diff --git a/libclamav/c++/llvm/test/Scripts/prcontext.tcl b/libclamav/c++/llvm/test/Scripts/prcontext.tcl
deleted file mode 100755
index 5ab0854..0000000
--- a/libclamav/c++/llvm/test/Scripts/prcontext.tcl
+++ /dev/null
@@ -1,36 +0,0 @@
-#!/usr/bin/tclsh
-#
-# Usage:
-# prcontext <pattern> <# lines of context>
-# (for platforms that don't have grep -C)
-
-
-#
-# Get the arguments
-#
-set pattern [lindex $argv 0]
-set num [lindex $argv 1]
-
-
-#
-# Get all of the lines in the file.
-#
-set lines [split [read stdin] \n]
-
-set index 0
-foreach line $lines {
- if { [regexp $pattern $line match matchline] } {
- if { [ expr [expr $index - $num] < 0 ] } {
- set bottom 0
- } else {
- set bottom [expr $index - $num]
- }
- set endLineNum [ expr [expr $index + $num] + 1]
- while {$bottom < $endLineNum} {
- set output [lindex $lines $bottom]
- puts $output
- set bottom [expr $bottom + 1]
- }
- }
- set index [expr $index + 1]
-}
\ No newline at end of file
diff --git a/libclamav/c++/llvm/test/Unit/lit.cfg b/libclamav/c++/llvm/test/Unit/lit.cfg
new file mode 100644
index 0000000..6fd3998
--- /dev/null
+++ b/libclamav/c++/llvm/test/Unit/lit.cfg
@@ -0,0 +1,65 @@
+# -*- Python -*-
+
+# Configuration file for the 'lit' test runner.
+
+import os
+
+# name: The name of this test suite.
+config.name = 'LLVM-Unit'
+
+# suffixes: A list of file extensions to treat as test files, this is actually
+# set by on_clone().
+config.suffixes = []
+
+# test_source_root: The root path where tests are located.
+# test_exec_root: The root path where tests should be run.
+llvm_obj_root = getattr(config, 'llvm_obj_root', None)
+if llvm_obj_root is not None:
+ config.test_exec_root = os.path.join(llvm_obj_root, 'unittests')
+ config.test_source_root = config.test_exec_root
+
+# testFormat: The test format to use to interpret tests.
+llvm_build_mode = getattr(config, 'llvm_build_mode', "Debug")
+config.test_format = lit.formats.GoogleTest(llvm_build_mode, 'Tests')
+
+###
+
+import os
+
+# Check that the object root is known.
+if config.test_exec_root is None:
+ # Otherwise, we haven't loaded the site specific configuration (the user is
+ # probably trying to run on a test file directly, and either the site
+ # configuration hasn't been created by the build system, or we are in an
+ # out-of-tree build situation).
+
+ # Try to detect the situation where we are using an out-of-tree build by
+ # looking for 'llvm-config'.
+ #
+ # FIXME: I debated (i.e., wrote and threw away) adding logic to
+ # automagically generate the lit.site.cfg if we are in some kind of fresh
+ # build situation. This means knowing how to invoke the build system
+ # though, and I decided it was too much magic.
+
+ llvm_config = lit.util.which('llvm-config', config.environment['PATH'])
+ if not llvm_config:
+ lit.fatal('No site specific configuration available!')
+
+ # Get the source and object roots.
+ llvm_src_root = lit.util.capture(['llvm-config', '--src-root']).strip()
+ llvm_obj_root = lit.util.capture(['llvm-config', '--obj-root']).strip()
+
+ # Validate that we got a tree which points to here.
+ this_src_root = os.path.join(os.path.dirname(__file__),'..','..')
+ if os.path.realpath(llvm_src_root) != os.path.realpath(this_src_root):
+ lit.fatal('No site specific configuration available!')
+
+ # Check that the site specific configuration exists.
+ site_cfg = os.path.join(llvm_obj_root, 'test', 'Unit', 'lit.site.cfg')
+ if not os.path.exists(site_cfg):
+ lit.fatal('No site specific configuration available!')
+
+ # Okay, that worked. Notify the user of the automagic, and reconfigure.
+ lit.note('using out-of-tree build at %r' % llvm_obj_root)
+ lit.load_config(config, site_cfg)
+ raise SystemExit
diff --git a/libclamav/c++/llvm/test/lib/llvm.exp b/libclamav/c++/llvm/test/lib/llvm.exp
index 3e2632f..2c1bef9 100644
--- a/libclamav/c++/llvm/test/lib/llvm.exp
+++ b/libclamav/c++/llvm/test/lib/llvm.exp
@@ -46,8 +46,8 @@ proc execOneLine { test PRS outcome lineno line } {
# This procedure performs variable substitutions on the RUN: lines of a test
# cases.
proc substitute { line test tmpFile } {
- global srcroot objroot srcdir objdir subdir target_triplet prcontext
- global llvmgcc llvmgxx llvmgcc_version llvmgccmajvers ocamlc
+ global srcroot objroot srcdir objdir subdir target_triplet
+ global llvmgcc llvmgxx llvmgcc_version llvmgccmajvers ocamlopt
global gccpath gxxpath compile_c compile_cxx link shlibext llvmlibsdir
global llvmdsymutil valgrind grep gas bugpoint_topts
set path [file join $srcdir $subdir]
@@ -57,8 +57,8 @@ proc substitute { line test tmpFile } {
#replace %% with _#MARKER#_ to make the replacement of %% more predictable
regsub -all {%%} $new_line {_#MARKER#_} new_line
- #replace %prcontext with prcontext.tcl (Must replace before %p)
- regsub -all {%prcontext} $new_line $prcontext new_line
+ #replace %llvmgcc_only with actual path to llvmgcc
+ regsub -all {%llvmgcc_only} $new_line "$llvmgcc" new_line
#replace %llvmgcc with actual path to llvmgcc
regsub -all {%llvmgcc} $new_line "$llvmgcc -emit-llvm -w" new_line
#replace %llvmgxx with actual path to llvmg++
@@ -71,8 +71,8 @@ proc substitute { line test tmpFile } {
regsub -all {%link} $new_line "$link" new_line
#replace %shlibext with shared library extension
regsub -all {%shlibext} $new_line "$shlibext" new_line
- #replace %ocamlc with ocaml compiler command
- regsub -all {%ocamlc} $new_line "$ocamlc" new_line
+ #replace %ocamlopt with ocaml compiler command
+ regsub -all {%ocamlopt} $new_line "$ocamlopt" new_line
#replace %llvmdsymutil with dsymutil command
regsub -all {%llvmdsymutil} $new_line "$llvmdsymutil" new_line
#replace %llvmlibsdir with configure library directory
@@ -85,6 +85,8 @@ proc substitute { line test tmpFile } {
regsub -all {%s} $new_line $test new_line
#replace %t with temp filenames
regsub -all {%t} $new_line $tmpFile new_line
+ #replace %abs_tmp with absolute temp filenames
+ regsub -all {%abs_tmp} $new_line [file join [pwd] $tmpFile] new_line
#replace _#MARKER#_ with %
regsub -all {_#MARKER#_} $new_line % new_line
@@ -298,3 +300,15 @@ proc llvm_supports_target { tgtName } {
}
return 0
}
+
+# This procedure provides an interface to check the BINDINGS_TO_BUILD makefile
+# variable to see if a particular binding has been configured to build.
+proc llvm_supports_binding { name } {
+ global llvm_bindings
+ foreach item [split $llvm_bindings] {
+ if { [regexp $name $item match] } {
+ return 1
+ }
+ }
+ return 0
+}
diff --git a/libclamav/c++/llvm/test/lit.cfg b/libclamav/c++/llvm/test/lit.cfg
new file mode 100644
index 0000000..7eac5c6
--- /dev/null
+++ b/libclamav/c++/llvm/test/lit.cfg
@@ -0,0 +1,155 @@
+# -*- Python -*-
+
+# Configuration file for the 'lit' test runner.
+
+import os
+
+# name: The name of this test suite.
+config.name = 'LLVM'
+
+# testFormat: The test format to use to interpret tests.
+config.test_format = lit.formats.TclTest()
+
+# suffixes: A list of file extensions to treat as test files, this is actually
+# set by on_clone().
+config.suffixes = []
+
+# test_source_root: The root path where tests are located.
+config.test_source_root = os.path.dirname(__file__)
+
+# test_exec_root: The root path where tests should be run.
+llvm_obj_root = getattr(config, 'llvm_obj_root', None)
+if llvm_obj_root is not None:
+ config.test_exec_root = os.path.join(llvm_obj_root, 'test')
+
+###
+
+import os
+
+# Check that the object root is known.
+if config.test_exec_root is None:
+ # Otherwise, we haven't loaded the site specific configuration (the user is
+ # probably trying to run on a test file directly, and either the site
+ # configuration hasn't been created by the build system, or we are in an
+ # out-of-tree build situation).
+
+ # Try to detect the situation where we are using an out-of-tree build by
+ # looking for 'llvm-config'.
+ #
+ # FIXME: I debated (i.e., wrote and threw away) adding logic to
+ # automagically generate the lit.site.cfg if we are in some kind of fresh
+ # build situation. This means knowing how to invoke the build system
+ # though, and I decided it was too much magic.
+
+ llvm_config = lit.util.which('llvm-config', config.environment['PATH'])
+ if not llvm_config:
+ lit.fatal('No site specific configuration available!')
+
+ # Get the source and object roots.
+ llvm_src_root = lit.util.capture(['llvm-config', '--src-root']).strip()
+ llvm_obj_root = lit.util.capture(['llvm-config', '--obj-root']).strip()
+
+ # Validate that we got a tree which points to here.
+ this_src_root = os.path.dirname(config.test_source_root)
+ if os.path.realpath(llvm_src_root) != os.path.realpath(this_src_root):
+ lit.fatal('No site specific configuration available!')
+
+ # Check that the site specific configuration exists.
+ site_cfg = os.path.join(llvm_obj_root, 'test', 'lit.site.cfg')
+ if not os.path.exists(site_cfg):
+ lit.fatal('No site specific configuration available!')
+
+ # Okay, that worked. Notify the user of the automagic, and reconfigure.
+ lit.note('using out-of-tree build at %r' % llvm_obj_root)
+ lit.load_config(config, site_cfg)
+ raise SystemExit
+
+###
+
+# Load site data from DejaGNU's site.exp.
+import re
+site_exp = {}
+# FIXME: Implement lit.site.cfg.
+for line in open(os.path.join(config.llvm_obj_root, 'test', 'site.exp')):
+ m = re.match('set ([^ ]+) "([^"]*)"', line)
+ if m:
+ site_exp[m.group(1)] = m.group(2)
+
+# Add substitutions.
+for sub in ['llvmgcc', 'llvmgxx', 'compile_cxx', 'compile_c',
+ 'link', 'shlibext', 'ocamlopt', 'llvmdsymutil', 'llvmlibsdir',
+ 'bugpoint_topts']:
+ if sub in ('llvmgcc', 'llvmgxx'):
+ config.substitutions.append(('%' + sub,
+ site_exp[sub] + ' -emit-llvm -w'))
+ else:
+ config.substitutions.append(('%' + sub, site_exp[sub]))
+
+excludes = []
+
+# Provide target_triple for use in XFAIL and XTARGET.
+config.target_triple = site_exp['target_triplet']
+
+# Provide llvm_supports_target for use in local configs.
+targets = set(site_exp["TARGETS_TO_BUILD"].split())
+def llvm_supports_target(name):
+ return name in targets
+
+langs = set(site_exp['llvmgcc_langs'].split(','))
+def llvm_gcc_supports(name):
+ return name in langs
+
+bindings = set(site_exp['llvm_bindings'].split(','))
+def llvm_supports_binding(name):
+ return name in langs
+
+# Provide on_clone hook for reading 'dg.exp'.
+import os
+simpleLibData = re.compile(r"""load_lib llvm.exp
+
+RunLLVMTests \[lsort \[glob -nocomplain \$srcdir/\$subdir/\*\.(.*)\]\]""",
+ re.MULTILINE)
+conditionalLibData = re.compile(r"""load_lib llvm.exp
+
+if.*\[ ?(llvm[^ ]*) ([^ ]*) ?\].*{
+ *RunLLVMTests \[lsort \[glob -nocomplain \$srcdir/\$subdir/\*\.(.*)\]\]
+\}""", re.MULTILINE)
+def on_clone(parent, cfg, for_path):
+ def addSuffixes(match):
+ if match[0] == '{' and match[-1] == '}':
+ cfg.suffixes = ['.' + s for s in match[1:-1].split(',')]
+ else:
+ cfg.suffixes = ['.' + match]
+
+ libPath = os.path.join(os.path.dirname(for_path),
+ 'dg.exp')
+ if not os.path.exists(libPath):
+ cfg.unsupported = True
+ return
+
+ # Reset unsupported, in case we inherited it.
+ cfg.unsupported = False
+ lib = open(libPath).read().strip()
+
+ # Check for a simple library.
+ m = simpleLibData.match(lib)
+ if m:
+ addSuffixes(m.group(1))
+ return
+
+ # Check for a conditional test set.
+ m = conditionalLibData.match(lib)
+ if m:
+ funcname,arg,match = m.groups()
+ addSuffixes(match)
+
+ func = globals().get(funcname)
+ if not func:
+ lit.error('unsupported predicate %r' % funcname)
+ elif not func(arg):
+ cfg.unsupported = True
+ return
+ # Otherwise, give up.
+ lit.error('unable to understand %r:\n%s' % (libPath, lib))
+
+config.on_clone = on_clone
diff --git a/libclamav/c++/llvm/test/lit.site.cfg.in b/libclamav/c++/llvm/test/lit.site.cfg.in
new file mode 100644
index 0000000..88699e3
--- /dev/null
+++ b/libclamav/c++/llvm/test/lit.site.cfg.in
@@ -0,0 +1,9 @@
+## Autogenerated by LLVM/Clang configuration.
+# Do not edit!
+config.llvm_src_root = "@LLVM_SOURCE_DIR@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
+config.llvm_tools_dir = "@LLVM_TOOLS_DIR@"
+config.llvmgcc_dir = "@LLVMGCCDIR@"
+
+# Let the main config do the real work.
+lit.load_config(config, "@LLVM_SOURCE_DIR@/test/lit.cfg")
diff --git a/libclamav/c++/llvm/test/site.exp.in b/libclamav/c++/llvm/test/site.exp.in
new file mode 100644
index 0000000..6a74ba8
--- /dev/null
+++ b/libclamav/c++/llvm/test/site.exp.in
@@ -0,0 +1,27 @@
+## Autogenerated by LLVM/Clang configuration.
+# Do not edit!
+set target_triplet "@target@"
+set TARGETS_TO_BUILD "@TARGETS_TO_BUILD@"
+set llvmgcc_langs "@LLVMGCC_LANGS@"
+set llvmgcc_version "@LLVMGCC_VERSION@"
+set llvmlibsdir "@LLVM_LIBS_DIR@"
+set llvm_bindings "@LLVM_BINDINGS@"
+set srcroot "@LLVM_SOURCE_DIR@"
+set objroot "@LLVM_BINARY_DIR@"
+set srcdir "@LLVM_SOURCE_DIR@"
+set objdir "@LLVM_BINARY_DIR@"
+set gccpath "@GCCPATH@"
+set gxxpath "@GXXPATH@"
+set compile_c "@TEST_COMPILE_C_CMD@"
+set compile_cxx "@TEST_COMPILE_CXX_CMD@"
+set link "@TEST_LINK_CMD@"
+set llvmgcc "@LLVMGCC@"
+set llvmgxx "@LLVMGXX@"
+set llvmgccmajvers "@LLVMGCCMAJVERS@"
+set bugpoint_topts "@BUGPOINT_TOPTS@"
+set shlibext "@SHLIBEXT@"
+set ocamlopt "@OCAMLOPT@"
+set valgrind "@VALGRIND@"
+set grep "@GREP@"
+set gas "@AS@"
+set llvmdsymutil "@DSYMUTIL@"
diff --git a/libclamav/c++/llvm/tools/llc/CMakeLists.txt b/libclamav/c++/llvm/tools/llc/CMakeLists.txt
index e98b5a2..683f298 100644
--- a/libclamav/c++/llvm/tools/llc/CMakeLists.txt
+++ b/libclamav/c++/llvm/tools/llc/CMakeLists.txt
@@ -1,4 +1,4 @@
-set(LLVM_LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} bitreader)
+set(LLVM_LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} bitreader asmparser)
add_llvm_tool(llc
llc.cpp
diff --git a/libclamav/c++/llvm/tools/llc/Makefile b/libclamav/c++/llvm/tools/llc/Makefile
index 8514040..7319aad 100644
--- a/libclamav/c++/llvm/tools/llc/Makefile
+++ b/libclamav/c++/llvm/tools/llc/Makefile
@@ -15,7 +15,7 @@ TOOLNAME = llc
# early so we can set up LINK_COMPONENTS before including Makefile.rules
include $(LEVEL)/Makefile.config
-LINK_COMPONENTS := $(TARGETS_TO_BUILD) bitreader
+LINK_COMPONENTS := $(TARGETS_TO_BUILD) bitreader asmparser
include $(LLVM_SRC_ROOT)/Makefile.rules
diff --git a/libclamav/c++/llvm/tools/llc/llc.cpp b/libclamav/c++/llvm/tools/llc/llc.cpp
index 6ff97f3..b94e5fb 100644
--- a/libclamav/c++/llvm/tools/llc/llc.cpp
+++ b/libclamav/c++/llvm/tools/llc/llc.cpp
@@ -20,7 +20,7 @@
#include "llvm/Pass.h"
#include "llvm/ADT/Triple.h"
#include "llvm/Analysis/Verifier.h"
-#include "llvm/Bitcode/ReaderWriter.h"
+#include "llvm/Support/IRReader.h"
#include "llvm/CodeGen/FileWriters.h"
#include "llvm/CodeGen/LinkAllAsmWriterComponents.h"
#include "llvm/CodeGen/LinkAllCodegenComponents.h"
@@ -119,7 +119,9 @@ GetFileNameRoot(const std::string &InputFilename) {
std::string outputFilename;
int Len = IFN.length();
if ((Len > 2) &&
- IFN[Len-3] == '.' && IFN[Len-2] == 'b' && IFN[Len-1] == 'c') {
+ IFN[Len-3] == '.' &&
+ ((IFN[Len-2] == 'b' && IFN[Len-1] == 'c') ||
+ (IFN[Len-2] == 'l' && IFN[Len-1] == 'l'))) {
outputFilename = std::string(IFN.begin(), IFN.end()-3); // s/.bc/.s/
} else {
outputFilename = IFN;
@@ -211,23 +213,19 @@ int main(int argc, char **argv) {
LLVMContext &Context = getGlobalContext();
llvm_shutdown_obj Y; // Call llvm_shutdown() on exit.
- // Initialize targets first.
+ // Initialize targets first, so that --version shows registered targets.
InitializeAllTargets();
InitializeAllAsmPrinters();
cl::ParseCommandLineOptions(argc, argv, "llvm system compiler\n");
// Load the module to be compiled...
- std::string ErrorMessage;
+ SMDiagnostic Err;
std::auto_ptr<Module> M;
- std::auto_ptr<MemoryBuffer> Buffer(
- MemoryBuffer::getFileOrSTDIN(InputFilename, &ErrorMessage));
- if (Buffer.get())
- M.reset(ParseBitcodeFile(Buffer.get(), Context, &ErrorMessage));
+ M.reset(ParseIRFile(InputFilename, Err, Context));
if (M.get() == 0) {
- errs() << argv[0] << ": bitcode didn't read correctly.\n";
- errs() << "Reason: " << ErrorMessage << "\n";
+ Err.Print(argv[0], errs());
return 1;
}
Module &mod = *M.get();
diff --git a/libclamav/c++/llvm/tools/llvm-as/llvm-as.cpp b/libclamav/c++/llvm/tools/llvm-as/llvm-as.cpp
index 9027cfc..d510297 100644
--- a/libclamav/c++/llvm/tools/llvm-as/llvm-as.cpp
+++ b/libclamav/c++/llvm/tools/llvm-as/llvm-as.cpp
@@ -94,7 +94,12 @@ int main(int argc, char **argv) {
OutputFilename += ".bc";
}
}
-
+
+ // Make sure that the Out file gets unlinked from the disk if we get a
+ // SIGINT.
+ if (OutputFilename != "-")
+ sys::RemoveFileOnSignal(sys::Path(OutputFilename));
+
std::string ErrorInfo;
std::auto_ptr<raw_ostream> Out
(new raw_fd_ostream(OutputFilename.c_str(), ErrorInfo,
@@ -103,12 +108,6 @@ int main(int argc, char **argv) {
errs() << ErrorInfo << '\n';
return 1;
}
-
-
- // Make sure that the Out file gets unlinked from the disk if we get a
- // SIGINT.
- if (OutputFilename != "-")
- sys::RemoveFileOnSignal(sys::Path(OutputFilename));
if (!DisableOutput)
if (Force || !CheckBitcodeOutputToConsole(*Out, true))
diff --git a/libclamav/c++/llvm/tools/llvm-config/CMakeLists.txt b/libclamav/c++/llvm/tools/llvm-config/CMakeLists.txt
index b029663..15df21f 100644
--- a/libclamav/c++/llvm/tools/llvm-config/CMakeLists.txt
+++ b/libclamav/c++/llvm/tools/llvm-config/CMakeLists.txt
@@ -8,6 +8,8 @@ endif( NOT PERL_FOUND )
set(PERL ${PERL_EXECUTABLE})
set(VERSION PACKAGE_VERSION)
set(PREFIX ${LLVM_BINARY_DIR}) # TODO: Root for `make install'.
+set(abs_top_srcdir ${LLVM_MAIN_SRC_DIR})
+set(abs_top_builddir ${LLVM_BINARY_DIR})
execute_process(COMMAND date
OUTPUT_VARIABLE LLVM_CONFIGTIME
OUTPUT_STRIP_TRAILING_WHITESPACE)
@@ -27,7 +29,7 @@ endif( IS_BIG_ENDIAN )
set(SHLIBEXT ${LTDL_SHLIB_EXT})
#EXEEXT already set.
set(OS "${CMAKE_SYSTEM}")
-set(ARCH "X86") # TODO: This gives "i686" in Linux: "${CMAKE_SYSTEM_PROCESSOR}")
+set(ARCH "${LLVM_NATIVE_ARCH}")
get_system_libs(LLVM_SYSTEM_LIBS_LIST)
foreach(l ${LLVM_SYSTEM_LIBS_LIST})
diff --git a/libclamav/c++/llvm/tools/llvm-config/llvm-config.in.in b/libclamav/c++/llvm/tools/llvm-config/llvm-config.in.in
index fd39042..7f93f16 100644
--- a/libclamav/c++/llvm/tools/llvm-config/llvm-config.in.in
+++ b/libclamav/c++/llvm/tools/llvm-config/llvm-config.in.in
@@ -26,17 +26,6 @@ my $PREFIX = q{@LLVM_PREFIX@};
my $LLVM_CONFIGTIME = q{@LLVM_CONFIGTIME@};
my $LLVM_SRC_ROOT = q{@abs_top_srcdir@};
my $LLVM_OBJ_ROOT = q{@abs_top_builddir@};
-my $LLVM_ON_WIN32 = q{@LLVM_ON_WIN32@};
-my $LLVM_ON_UNIX = q{@LLVM_ON_UNIX@};
-my $LLVMGCCDIR = q{@LLVMGCCDIR@};
-my $LLVMGCC = q{@LLVMGCC@};
-my $LLVMGXX = q{@LLVMGXX@};
-my $LLVMGCC_VERSION = q{@LLVMGCC_VERSION@};
-my $LLVMGCC_MAJVERS = q{@LLVMGCC_MAJVERS@};
-my $ENDIAN = q{@ENDIAN@};
-my $SHLIBEXT = q{@SHLIBEXT@};
-my $EXEEXT = q{@EXEEXT@};
-my $OS = q{@OS@};
my $ARCH = lc(q{@ARCH@});
my $TARGET_TRIPLE = q{@target@};
my $TARGETS_TO_BUILD = q{@TARGETS_TO_BUILD@};
diff --git a/libclamav/c++/llvm/tools/llvmc/doc/LLVMC-Reference.rst b/libclamav/c++/llvm/tools/llvmc/doc/LLVMC-Reference.rst
index 3014a3a..5d3b02a 100644
--- a/libclamav/c++/llvm/tools/llvmc/doc/LLVMC-Reference.rst
+++ b/libclamav/c++/llvm/tools/llvmc/doc/LLVMC-Reference.rst
@@ -458,17 +458,27 @@ use TableGen inheritance instead.
- ``empty`` - The opposite of ``not_empty``. Equivalent to ``(not (not_empty
X))``. Provided for convenience.
+ - ``single_input_file`` - Returns true if there was only one input file
+ provided on the command-line. Used without arguments:
+ ``(single_input_file)``.
+
+ - ``multiple_input_files`` - Equivalent to ``(not (single_input_file))`` (the
+ case of zero input files is considered an error).
+
- ``default`` - Always evaluates to true. Should always be the last
test in the ``case`` expression.
- - ``and`` - A standard logical combinator that returns true iff all
- of its arguments return true. Used like this: ``(and (test1),
- (test2), ... (testN))``. Nesting of ``and`` and ``or`` is allowed,
- but not encouraged.
+ - ``and`` - A standard binary logical combinator that returns true iff all of
+ its arguments return true. Used like this: ``(and (test1), (test2),
+ ... (testN))``. Nesting of ``and`` and ``or`` is allowed, but not
+ encouraged.
+
+ - ``or`` - A binary logical combinator that returns true iff any of its
+ arguments returns true. Example: ``(or (test1), (test2), ... (testN))``.
+
+ - ``not`` - Standard unary logical combinator that negates its
+ argument. Example: ``(not (or (test1), (test2), ... (testN)))``.
- - ``or`` - Another logical combinator that returns true only if any
- one of its arguments returns true. Example: ``(or (test1),
- (test2), ... (testN))``.
Writing a tool description
diff --git a/libclamav/c++/llvm/tools/llvmc/plugins/Base/Base.td.in b/libclamav/c++/llvm/tools/llvmc/plugins/Base/Base.td.in
index 757078a..4b964e3 100644
--- a/libclamav/c++/llvm/tools/llvmc/plugins/Base/Base.td.in
+++ b/libclamav/c++/llvm/tools/llvmc/plugins/Base/Base.td.in
@@ -70,6 +70,8 @@ class llvm_gcc_based <string cmd_prefix, string in_lang, string E_ext> : Tool<
!strconcat(cmd_prefix, " -c $INFILE -o $OUTFILE -emit-llvm"))),
(actions
(case
+ (and (multiple_input_files), (or (switch_on "S"), (switch_on "c"))),
+ (error "cannot specify -o with -c or -S with multiple files"),
(switch_on "E"), [(stop_compilation), (output_suffix E_ext)],
(and (switch_on "emit-llvm"), (switch_on "S")),
[(output_suffix "ll"), (stop_compilation)],
@@ -166,6 +168,7 @@ def CompilationGraph : CompilationGraph<[
Edge<"root", "llvm_gcc_m">,
Edge<"root", "llvm_gcc_mxx">,
Edge<"root", "llvm_as">,
+ Edge<"root", "llc">,
Edge<"llvm_gcc_c", "llc">,
Edge<"llvm_gcc_cpp", "llc">,
diff --git a/libclamav/c++/llvm/unittests/ADT/APFloatTest.cpp b/libclamav/c++/llvm/unittests/ADT/APFloatTest.cpp
index 7928d7e..92f020b 100644
--- a/libclamav/c++/llvm/unittests/ADT/APFloatTest.cpp
+++ b/libclamav/c++/llvm/unittests/ADT/APFloatTest.cpp
@@ -15,6 +15,12 @@
using namespace llvm;
+static double convertToDoubleFromString(const char *Str) {
+ llvm::APFloat F(0.0);
+ F.convertFromString(Str, llvm::APFloat::rmNearestTiesToEven);
+ return F.convertToDouble();
+}
+
namespace {
TEST(APFloatTest, Zero) {
@@ -303,6 +309,8 @@ TEST(APFloatTest, fromHexadecimalString) {
EXPECT_EQ(1.0625, APFloat(APFloat::IEEEdouble, "0x1.1p0").convertToDouble());
EXPECT_EQ(1.0, APFloat(APFloat::IEEEdouble, "0x1p0").convertToDouble());
+
+ EXPECT_EQ(2.71828, convertToDoubleFromString("2.71828"));
}
#ifdef GTEST_HAS_DEATH_TEST
diff --git a/libclamav/c++/llvm/unittests/ADT/APIntTest.cpp b/libclamav/c++/llvm/unittests/ADT/APIntTest.cpp
index 415f192..24a3d9b 100644
--- a/libclamav/c++/llvm/unittests/ADT/APIntTest.cpp
+++ b/libclamav/c++/llvm/unittests/ADT/APIntTest.cpp
@@ -8,7 +8,6 @@
//===----------------------------------------------------------------------===//
#include <ostream>
-#include "llvm/Support/raw_os_ostream.h"
#include "gtest/gtest.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/SmallString.h"
@@ -17,13 +16,6 @@ using namespace llvm;
namespace {
-// Support APInt output to an std::ostream.
-inline std::ostream &operator<<(std::ostream &OS, const APInt &Value) {
- raw_os_ostream RawOS(OS);
- RawOS << Value;
- return OS;
-}
-
// Test that APInt shift left works when bitwidth > 64 and shiftamt == 0
TEST(APIntTest, ShiftLeftByZero) {
APInt One = APInt::getNullValue(65) + 1;
@@ -183,11 +175,11 @@ TEST(APIntTest, fromString) {
EXPECT_EQ(APInt(32, 3), APInt(32, "+11", 2));
EXPECT_EQ(APInt(32, 4), APInt(32, "+100", 2));
- EXPECT_EQ(APInt(32, -0), APInt(32, "-0", 2));
- EXPECT_EQ(APInt(32, -1), APInt(32, "-1", 2));
- EXPECT_EQ(APInt(32, -2), APInt(32, "-10", 2));
- EXPECT_EQ(APInt(32, -3), APInt(32, "-11", 2));
- EXPECT_EQ(APInt(32, -4), APInt(32, "-100", 2));
+ EXPECT_EQ(APInt(32, uint64_t(-0LL)), APInt(32, "-0", 2));
+ EXPECT_EQ(APInt(32, uint64_t(-1LL)), APInt(32, "-1", 2));
+ EXPECT_EQ(APInt(32, uint64_t(-2LL)), APInt(32, "-10", 2));
+ EXPECT_EQ(APInt(32, uint64_t(-3LL)), APInt(32, "-11", 2));
+ EXPECT_EQ(APInt(32, uint64_t(-4LL)), APInt(32, "-100", 2));
EXPECT_EQ(APInt(32, 0), APInt(32, "0", 8));
@@ -204,12 +196,12 @@ TEST(APIntTest, fromString) {
EXPECT_EQ(APInt(32, +15), APInt(32, "+17", 8));
EXPECT_EQ(APInt(32, +16), APInt(32, "+20", 8));
- EXPECT_EQ(APInt(32, -0), APInt(32, "-0", 8));
- EXPECT_EQ(APInt(32, -1), APInt(32, "-1", 8));
- EXPECT_EQ(APInt(32, -7), APInt(32, "-7", 8));
- EXPECT_EQ(APInt(32, -8), APInt(32, "-10", 8));
- EXPECT_EQ(APInt(32, -15), APInt(32, "-17", 8));
- EXPECT_EQ(APInt(32, -16), APInt(32, "-20", 8));
+ EXPECT_EQ(APInt(32, uint64_t(-0LL)), APInt(32, "-0", 8));
+ EXPECT_EQ(APInt(32, uint64_t(-1LL)), APInt(32, "-1", 8));
+ EXPECT_EQ(APInt(32, uint64_t(-7LL)), APInt(32, "-7", 8));
+ EXPECT_EQ(APInt(32, uint64_t(-8LL)), APInt(32, "-10", 8));
+ EXPECT_EQ(APInt(32, uint64_t(-15LL)), APInt(32, "-17", 8));
+ EXPECT_EQ(APInt(32, uint64_t(-16LL)), APInt(32, "-20", 8));
EXPECT_EQ(APInt(32, 0), APInt(32, "0", 10));
@@ -219,12 +211,12 @@ TEST(APIntTest, fromString) {
EXPECT_EQ(APInt(32, 19), APInt(32, "19", 10));
EXPECT_EQ(APInt(32, 20), APInt(32, "20", 10));
- EXPECT_EQ(APInt(32, -0), APInt(32, "-0", 10));
- EXPECT_EQ(APInt(32, -1), APInt(32, "-1", 10));
- EXPECT_EQ(APInt(32, -9), APInt(32, "-9", 10));
- EXPECT_EQ(APInt(32, -10), APInt(32, "-10", 10));
- EXPECT_EQ(APInt(32, -19), APInt(32, "-19", 10));
- EXPECT_EQ(APInt(32, -20), APInt(32, "-20", 10));
+ EXPECT_EQ(APInt(32, uint64_t(-0LL)), APInt(32, "-0", 10));
+ EXPECT_EQ(APInt(32, uint64_t(-1LL)), APInt(32, "-1", 10));
+ EXPECT_EQ(APInt(32, uint64_t(-9LL)), APInt(32, "-9", 10));
+ EXPECT_EQ(APInt(32, uint64_t(-10LL)), APInt(32, "-10", 10));
+ EXPECT_EQ(APInt(32, uint64_t(-19LL)), APInt(32, "-19", 10));
+ EXPECT_EQ(APInt(32, uint64_t(-20LL)), APInt(32, "-20", 10));
EXPECT_EQ(APInt(32, 0), APInt(32, "0", 16));
@@ -234,12 +226,12 @@ TEST(APIntTest, fromString) {
EXPECT_EQ(APInt(32, 31), APInt(32, "1F", 16));
EXPECT_EQ(APInt(32, 32), APInt(32, "20", 16));
- EXPECT_EQ(APInt(32, -0), APInt(32, "-0", 16));
- EXPECT_EQ(APInt(32, -1), APInt(32, "-1", 16));
- EXPECT_EQ(APInt(32, -15), APInt(32, "-F", 16));
- EXPECT_EQ(APInt(32, -16), APInt(32, "-10", 16));
- EXPECT_EQ(APInt(32, -31), APInt(32, "-1F", 16));
- EXPECT_EQ(APInt(32, -32), APInt(32, "-20", 16));
+ EXPECT_EQ(APInt(32, uint64_t(-0LL)), APInt(32, "-0", 16));
+ EXPECT_EQ(APInt(32, uint64_t(-1LL)), APInt(32, "-1", 16));
+ EXPECT_EQ(APInt(32, uint64_t(-15LL)), APInt(32, "-F", 16));
+ EXPECT_EQ(APInt(32, uint64_t(-16LL)), APInt(32, "-10", 16));
+ EXPECT_EQ(APInt(32, uint64_t(-31LL)), APInt(32, "-1F", 16));
+ EXPECT_EQ(APInt(32, uint64_t(-32LL)), APInt(32, "-20", 16));
}
TEST(APIntTest, StringBitsNeeded2) {
diff --git a/libclamav/c++/llvm/unittests/ADT/StringRefTest.cpp b/libclamav/c++/llvm/unittests/ADT/StringRefTest.cpp
index 320633a..cdc476e 100644
--- a/libclamav/c++/llvm/unittests/ADT/StringRefTest.cpp
+++ b/libclamav/c++/llvm/unittests/ADT/StringRefTest.cpp
@@ -14,18 +14,29 @@ using namespace llvm;
namespace {
+std::ostream &operator<<(std::ostream &OS, const StringRef &S) {
+ OS << S;
+ return OS;
+}
+
+std::ostream &operator<<(std::ostream &OS,
+ const std::pair<StringRef, StringRef> &P) {
+ OS << "(" << P.first << ", " << P.second << ")";
+ return OS;
+}
+
TEST(StringRefTest, Construction) {
- EXPECT_TRUE(StringRef() == "");
- EXPECT_TRUE(StringRef("hello") == "hello");
- EXPECT_TRUE(StringRef("hello world", 5) == "hello");
- EXPECT_TRUE(StringRef(std::string("hello")) == "hello");
+ EXPECT_EQ("", StringRef());
+ EXPECT_EQ("hello", StringRef("hello"));
+ EXPECT_EQ("hello", StringRef("hello world", 5));
+ EXPECT_EQ("hello", StringRef(std::string("hello")));
}
TEST(StringRefTest, Iteration) {
StringRef S("hello");
const char *p = "hello";
for (const char *it = S.begin(), *ie = S.end(); it != ie; ++it, ++p)
- EXPECT_TRUE(*p == *it);
+ EXPECT_EQ(*it, *p);
}
TEST(StringRefTest, StringOps) {
@@ -41,7 +52,7 @@ TEST(StringRefTest, StringOps) {
}
TEST(StringRefTest, Operators) {
- EXPECT_TRUE(StringRef() == "");
+ EXPECT_EQ("", StringRef());
EXPECT_TRUE(StringRef("aab") < StringRef("aad"));
EXPECT_FALSE(StringRef("aab") < StringRef("aab"));
EXPECT_TRUE(StringRef("aab") <= StringRef("aab"));
@@ -50,58 +61,95 @@ TEST(StringRefTest, Operators) {
EXPECT_FALSE(StringRef("aab") > StringRef("aab"));
EXPECT_TRUE(StringRef("aab") >= StringRef("aab"));
EXPECT_FALSE(StringRef("aaa") >= StringRef("aab"));
- EXPECT_TRUE(StringRef("aab") == StringRef("aab"));
+ EXPECT_EQ(StringRef("aab"), StringRef("aab"));
EXPECT_FALSE(StringRef("aab") == StringRef("aac"));
EXPECT_FALSE(StringRef("aab") != StringRef("aab"));
EXPECT_TRUE(StringRef("aab") != StringRef("aac"));
EXPECT_EQ('a', StringRef("aab")[1]);
}
-TEST(StringRefTest, Utilities) {
+TEST(StringRefTest, Substr) {
StringRef Str("hello");
- EXPECT_TRUE(Str.substr(3) == "lo");
- EXPECT_TRUE(Str.substr(100) == "");
- EXPECT_TRUE(Str.substr(0, 100) == "hello");
- EXPECT_TRUE(Str.substr(4, 10) == "o");
-
- EXPECT_TRUE(Str.slice(2, 3) == "l");
- EXPECT_TRUE(Str.slice(1, 4) == "ell");
- EXPECT_TRUE(Str.slice(2, 100) == "llo");
- EXPECT_TRUE(Str.slice(2, 1) == "");
- EXPECT_TRUE(Str.slice(10, 20) == "");
-
- EXPECT_TRUE(Str.split('X') == std::make_pair(StringRef("hello"),
- StringRef("")));
- EXPECT_TRUE(Str.split('e') == std::make_pair(StringRef("h"),
- StringRef("llo")));
- EXPECT_TRUE(Str.split('h') == std::make_pair(StringRef(""),
- StringRef("ello")));
- EXPECT_TRUE(Str.split('o') == std::make_pair(StringRef("hell"),
- StringRef("")));
+ EXPECT_EQ("lo", Str.substr(3));
+ EXPECT_EQ("", Str.substr(100));
+ EXPECT_EQ("hello", Str.substr(0, 100));
+ EXPECT_EQ("o", Str.substr(4, 10));
+}
+
+TEST(StringRefTest, Slice) {
+ StringRef Str("hello");
+ EXPECT_EQ("l", Str.slice(2, 3));
+ EXPECT_EQ("ell", Str.slice(1, 4));
+ EXPECT_EQ("llo", Str.slice(2, 100));
+ EXPECT_EQ("", Str.slice(2, 1));
+ EXPECT_EQ("", Str.slice(10, 20));
+}
+
+TEST(StringRefTest, Split) {
+ StringRef Str("hello");
+ EXPECT_EQ(std::make_pair(StringRef("hello"), StringRef("")),
+ Str.split('X'));
+ EXPECT_EQ(std::make_pair(StringRef("h"), StringRef("llo")),
+ Str.split('e'));
+ EXPECT_EQ(std::make_pair(StringRef(""), StringRef("ello")),
+ Str.split('h'));
+ EXPECT_EQ(std::make_pair(StringRef("he"), StringRef("lo")),
+ Str.split('l'));
+ EXPECT_EQ(std::make_pair(StringRef("hell"), StringRef("")),
+ Str.split('o'));
+
+ EXPECT_EQ(std::make_pair(StringRef("hello"), StringRef("")),
+ Str.rsplit('X'));
+ EXPECT_EQ(std::make_pair(StringRef("h"), StringRef("llo")),
+ Str.rsplit('e'));
+ EXPECT_EQ(std::make_pair(StringRef(""), StringRef("ello")),
+ Str.rsplit('h'));
+ EXPECT_EQ(std::make_pair(StringRef("hel"), StringRef("o")),
+ Str.rsplit('l'));
+ EXPECT_EQ(std::make_pair(StringRef("hell"), StringRef("")),
+ Str.rsplit('o'));
+}
+TEST(StringRefTest, StartsWith) {
+ StringRef Str("hello");
EXPECT_TRUE(Str.startswith("he"));
EXPECT_FALSE(Str.startswith("helloworld"));
EXPECT_FALSE(Str.startswith("hi"));
+}
+TEST(StringRefTest, Find) {
+ StringRef Str("hello");
+ EXPECT_EQ(2U, Str.find('l'));
+ EXPECT_EQ(StringRef::npos, Str.find('z'));
+ EXPECT_EQ(StringRef::npos, Str.find("helloworld"));
+ EXPECT_EQ(0U, Str.find("hello"));
+ EXPECT_EQ(1U, Str.find("ello"));
+ EXPECT_EQ(StringRef::npos, Str.find("zz"));
+
+ EXPECT_EQ(3U, Str.rfind('l'));
+ EXPECT_EQ(StringRef::npos, Str.rfind('z'));
+ EXPECT_EQ(StringRef::npos, Str.rfind("helloworld"));
+ EXPECT_EQ(0U, Str.rfind("hello"));
+ EXPECT_EQ(1U, Str.rfind("ello"));
+ EXPECT_EQ(StringRef::npos, Str.rfind("zz"));
+}
+
+TEST(StringRefTest, Count) {
+ StringRef Str("hello");
+ EXPECT_EQ(2U, Str.count('l'));
+ EXPECT_EQ(1U, Str.count('o'));
+ EXPECT_EQ(0U, Str.count('z'));
+ EXPECT_EQ(0U, Str.count("helloworld"));
+ EXPECT_EQ(1U, Str.count("hello"));
+ EXPECT_EQ(1U, Str.count("ello"));
+ EXPECT_EQ(0U, Str.count("zz"));
+}
+
+TEST(StringRefTest, Misc) {
std::string Storage;
raw_string_ostream OS(Storage);
OS << StringRef("hello");
EXPECT_EQ("hello", OS.str());
-
- EXPECT_TRUE(Str.find('l') == 2);
- EXPECT_TRUE(Str.find('z') == StringRef::npos);
- EXPECT_TRUE(Str.find("helloworld") == StringRef::npos);
- EXPECT_TRUE(Str.find("hello") == 0);
- EXPECT_TRUE(Str.find("ello") == 1);
- EXPECT_TRUE(Str.find("zz") == StringRef::npos);
-
- EXPECT_TRUE(Str.count('l') == 2);
- EXPECT_TRUE(Str.count('o') == 1);
- EXPECT_TRUE(Str.count('z') == 0);
- EXPECT_TRUE(Str.count("helloworld") == 0);
- EXPECT_TRUE(Str.count("hello") == 1);
- EXPECT_TRUE(Str.count("ello") == 1);
- EXPECT_TRUE(Str.count("zz") == 0);
}
} // end anonymous namespace
diff --git a/libclamav/c++/llvm/unittests/Makefile b/libclamav/c++/llvm/unittests/Makefile
index b743838..9f377cd 100644
--- a/libclamav/c++/llvm/unittests/Makefile
+++ b/libclamav/c++/llvm/unittests/Makefile
@@ -9,14 +9,7 @@
LEVEL = ..
-include $(LEVEL)/Makefile.config
-
-LIBRARYNAME = UnitTestMain
-BUILD_ARCHIVE = 1
-CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include
-CPP.Flags += -Wno-variadic-macros
-
-PARALLEL_DIRS = ADT ExecutionEngine Support VMCore
+PARALLEL_DIRS = ADT ExecutionEngine Support Transforms VMCore
include $(LEVEL)/Makefile.common
diff --git a/libclamav/c++/llvm/unittests/Makefile.unittest b/libclamav/c++/llvm/unittests/Makefile.unittest
index 1c75e44..214a1e8 100644
--- a/libclamav/c++/llvm/unittests/Makefile.unittest
+++ b/libclamav/c++/llvm/unittests/Makefile.unittest
@@ -25,11 +25,13 @@ LIBS += -lGoogleTest -lUnitTestMain
$(LLVMUnitTestExe): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths)
$(Echo) Linking $(BuildMode) unit test $(TESTNAME) $(StripWarnMsg)
$(Verb) $(Link) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \
- $(LLVMLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB) $(LIBS)
+ $(LIBS) $(LLVMLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB)
$(Echo) ======= Finished Linking $(BuildMode) Unit test $(TESTNAME) \
$(StripWarnMsg)
all:: $(LLVMUnitTestExe)
+
+unitcheck:: $(LLVMUnitTestExe)
$(LLVMUnitTestExe)
endif
diff --git a/libclamav/c++/llvm/unittests/Support/CommandLineTest.cpp b/libclamav/c++/llvm/unittests/Support/CommandLineTest.cpp
new file mode 100644
index 0000000..72fa24a
--- /dev/null
+++ b/libclamav/c++/llvm/unittests/Support/CommandLineTest.cpp
@@ -0,0 +1,60 @@
+//===- llvm/unittest/Support/CommandLineTest.cpp - CommandLine tests ------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Config/config.h"
+
+#include "gtest/gtest.h"
+
+#include <string>
+#include <stdlib.h>
+
+using namespace llvm;
+
+namespace {
+
+class TempEnvVar {
+ public:
+ TempEnvVar(const char *name, const char *value)
+ : name(name) {
+ const char *old_value = getenv(name);
+ EXPECT_EQ(NULL, old_value) << old_value;
+#if HAVE_SETENV
+ setenv(name, value, true);
+#else
+# define SKIP_ENVIRONMENT_TESTS
+#endif
+ }
+
+ ~TempEnvVar() {
+#if HAVE_SETENV
+ // Assume setenv and unsetenv come together.
+ unsetenv(name);
+#endif
+ }
+
+ private:
+ const char *const name;
+};
+
+#ifndef SKIP_ENVIRONMENT_TESTS
+
+const char test_env_var[] = "LLVM_TEST_COMMAND_LINE_FLAGS";
+
+cl::opt<std::string> EnvironmentTestOption("env-test-opt");
+TEST(CommandLineTest, ParseEnvironment) {
+ TempEnvVar TEV(test_env_var, "-env-test-opt=hello");
+ EXPECT_EQ("", EnvironmentTestOption);
+ cl::ParseEnvironmentOptions("CommandLineTest", test_env_var);
+ EXPECT_EQ("hello", EnvironmentTestOption);
+}
+
+#endif // SKIP_ENVIRONMENT_TESTS
+
+} // anonymous namespace
diff --git a/libclamav/c++/llvm/unittests/Support/ConstantRangeTest.cpp b/libclamav/c++/llvm/unittests/Support/ConstantRangeTest.cpp
index 937b880..6b8d01d 100644
--- a/libclamav/c++/llvm/unittests/Support/ConstantRangeTest.cpp
+++ b/libclamav/c++/llvm/unittests/Support/ConstantRangeTest.cpp
@@ -8,7 +8,6 @@
//===----------------------------------------------------------------------===//
#include "llvm/Support/ConstantRange.h"
-#include "llvm/Support/raw_os_ostream.h"
#include "gtest/gtest.h"
@@ -16,13 +15,6 @@ using namespace llvm;
namespace {
-// Support APInt output to an std::ostream.
-inline std::ostream &operator<<(std::ostream &OS, const APInt &Value) {
- raw_os_ostream RawOS(OS);
- RawOS << Value;
- return OS;
-}
-
class ConstantRangeTest : public ::testing::Test {
protected:
static ConstantRange Full;
@@ -86,21 +78,21 @@ TEST_F(ConstantRangeTest, Basics) {
}
TEST_F(ConstantRangeTest, Equality) {
- EXPECT_TRUE(Full == Full);
- EXPECT_TRUE(Empty == Empty);
- EXPECT_TRUE(One == One);
- EXPECT_TRUE(Some == Some);
- EXPECT_TRUE(Wrap == Wrap);
- EXPECT_TRUE(Full != Empty);
- EXPECT_TRUE(Full != One);
- EXPECT_TRUE(Full != Some);
- EXPECT_TRUE(Full != Wrap);
- EXPECT_TRUE(Empty != One);
- EXPECT_TRUE(Empty != Some);
- EXPECT_TRUE(Empty != Wrap);
- EXPECT_TRUE(One != Some);
- EXPECT_TRUE(One != Wrap);
- EXPECT_TRUE(Some != Wrap);
+ EXPECT_EQ(Full, Full);
+ EXPECT_EQ(Empty, Empty);
+ EXPECT_EQ(One, One);
+ EXPECT_EQ(Some, Some);
+ EXPECT_EQ(Wrap, Wrap);
+ EXPECT_NE(Full, Empty);
+ EXPECT_NE(Full, One);
+ EXPECT_NE(Full, Some);
+ EXPECT_NE(Full, Wrap);
+ EXPECT_NE(Empty, One);
+ EXPECT_NE(Empty, Some);
+ EXPECT_NE(Empty, Wrap);
+ EXPECT_NE(One, Some);
+ EXPECT_NE(One, Wrap);
+ EXPECT_NE(Some, Wrap);
}
TEST_F(ConstantRangeTest, SingleElement) {
@@ -159,7 +151,7 @@ TEST_F(ConstantRangeTest, Trunc) {
ConstantRange TWrap = Wrap.truncate(10);
EXPECT_TRUE(TFull.isFullSet());
EXPECT_TRUE(TEmpty.isEmptySet());
- EXPECT_TRUE(TOne == ConstantRange(APInt(One.getLower()).trunc(10),
+ EXPECT_EQ(TOne, ConstantRange(APInt(One.getLower()).trunc(10),
APInt(One.getUpper()).trunc(10)));
EXPECT_TRUE(TSome.isFullSet());
}
@@ -170,14 +162,14 @@ TEST_F(ConstantRangeTest, ZExt) {
ConstantRange ZOne = One.zeroExtend(20);
ConstantRange ZSome = Some.zeroExtend(20);
ConstantRange ZWrap = Wrap.zeroExtend(20);
- EXPECT_TRUE(ZFull == ConstantRange(APInt(20, 0), APInt(20, 0x10000)));
+ EXPECT_EQ(ZFull, ConstantRange(APInt(20, 0), APInt(20, 0x10000)));
EXPECT_TRUE(ZEmpty.isEmptySet());
- EXPECT_TRUE(ZOne == ConstantRange(APInt(One.getLower()).zext(20),
- APInt(One.getUpper()).zext(20)));
- EXPECT_TRUE(ZSome == ConstantRange(APInt(Some.getLower()).zext(20),
- APInt(Some.getUpper()).zext(20)));
- EXPECT_TRUE(ZWrap == ConstantRange(APInt(Wrap.getLower()).zext(20),
- APInt(Wrap.getUpper()).zext(20)));
+ EXPECT_EQ(ZOne, ConstantRange(APInt(One.getLower()).zext(20),
+ APInt(One.getUpper()).zext(20)));
+ EXPECT_EQ(ZSome, ConstantRange(APInt(Some.getLower()).zext(20),
+ APInt(Some.getUpper()).zext(20)));
+ EXPECT_EQ(ZWrap, ConstantRange(APInt(Wrap.getLower()).zext(20),
+ APInt(Wrap.getUpper()).zext(20)));
}
TEST_F(ConstantRangeTest, SExt) {
@@ -186,31 +178,31 @@ TEST_F(ConstantRangeTest, SExt) {
ConstantRange SOne = One.signExtend(20);
ConstantRange SSome = Some.signExtend(20);
ConstantRange SWrap = Wrap.signExtend(20);
- EXPECT_TRUE(SFull == ConstantRange(APInt(20, (uint64_t)INT16_MIN, true),
- APInt(20, INT16_MAX + 1, true)));
+ EXPECT_EQ(SFull, ConstantRange(APInt(20, (uint64_t)INT16_MIN, true),
+ APInt(20, INT16_MAX + 1, true)));
EXPECT_TRUE(SEmpty.isEmptySet());
- EXPECT_TRUE(SOne == ConstantRange(APInt(One.getLower()).sext(20),
- APInt(One.getUpper()).sext(20)));
- EXPECT_TRUE(SSome == ConstantRange(APInt(Some.getLower()).sext(20),
- APInt(Some.getUpper()).sext(20)));
- EXPECT_TRUE(SWrap == ConstantRange(APInt(Wrap.getLower()).sext(20),
- APInt(Wrap.getUpper()).sext(20)));
+ EXPECT_EQ(SOne, ConstantRange(APInt(One.getLower()).sext(20),
+ APInt(One.getUpper()).sext(20)));
+ EXPECT_EQ(SSome, ConstantRange(APInt(Some.getLower()).sext(20),
+ APInt(Some.getUpper()).sext(20)));
+ EXPECT_EQ(SWrap, ConstantRange(APInt(Wrap.getLower()).sext(20),
+ APInt(Wrap.getUpper()).sext(20)));
}
TEST_F(ConstantRangeTest, IntersectWith) {
- EXPECT_TRUE(Empty.intersectWith(Full).isEmptySet());
- EXPECT_TRUE(Empty.intersectWith(Empty).isEmptySet());
- EXPECT_TRUE(Empty.intersectWith(One).isEmptySet());
- EXPECT_TRUE(Empty.intersectWith(Some).isEmptySet());
- EXPECT_TRUE(Empty.intersectWith(Wrap).isEmptySet());
- EXPECT_TRUE(Full.intersectWith(Full).isFullSet());
- EXPECT_TRUE(Some.intersectWith(Some) == Some);
- EXPECT_TRUE(Some.intersectWith(One) == One);
- EXPECT_TRUE(Full.intersectWith(One) == One);
- EXPECT_TRUE(Full.intersectWith(Some) == Some);
- EXPECT_TRUE(Some.intersectWith(Wrap).isEmptySet());
- EXPECT_TRUE(One.intersectWith(Wrap).isEmptySet());
- EXPECT_TRUE(One.intersectWith(Wrap) == Wrap.intersectWith(One));
+ EXPECT_EQ(Empty.intersectWith(Full), Empty);
+ EXPECT_EQ(Empty.intersectWith(Empty), Empty);
+ EXPECT_EQ(Empty.intersectWith(One), Empty);
+ EXPECT_EQ(Empty.intersectWith(Some), Empty);
+ EXPECT_EQ(Empty.intersectWith(Wrap), Empty);
+ EXPECT_EQ(Full.intersectWith(Full), Full);
+ EXPECT_EQ(Some.intersectWith(Some), Some);
+ EXPECT_EQ(Some.intersectWith(One), One);
+ EXPECT_EQ(Full.intersectWith(One), One);
+ EXPECT_EQ(Full.intersectWith(Some), Some);
+ EXPECT_EQ(Some.intersectWith(Wrap), Empty);
+ EXPECT_EQ(One.intersectWith(Wrap), Empty);
+ EXPECT_EQ(One.intersectWith(Wrap), Wrap.intersectWith(One));
// Klee generated testcase from PR4545.
// The intersection of i16 [4, 2) and [6, 5) is disjoint, looking like
@@ -221,139 +213,139 @@ TEST_F(ConstantRangeTest, IntersectWith) {
}
TEST_F(ConstantRangeTest, UnionWith) {
- EXPECT_TRUE(Wrap.unionWith(One) ==
- ConstantRange(APInt(16, 0xaaa), APInt(16, 0xb)));
- EXPECT_TRUE(One.unionWith(Wrap) == Wrap.unionWith(One));
- EXPECT_TRUE(Empty.unionWith(Empty).isEmptySet());
- EXPECT_TRUE(Full.unionWith(Full).isFullSet());
- EXPECT_TRUE(Some.unionWith(Wrap).isFullSet());
+ EXPECT_EQ(Wrap.unionWith(One),
+ ConstantRange(APInt(16, 0xaaa), APInt(16, 0xb)));
+ EXPECT_EQ(One.unionWith(Wrap), Wrap.unionWith(One));
+ EXPECT_EQ(Empty.unionWith(Empty), Empty);
+ EXPECT_EQ(Full.unionWith(Full), Full);
+ EXPECT_EQ(Some.unionWith(Wrap), Full);
// PR4545
- EXPECT_TRUE(ConstantRange(APInt(16, 14), APInt(16, 1)).unionWith(
- ConstantRange(APInt(16, 0), APInt(16, 8))) ==
- ConstantRange(APInt(16, 14), APInt(16, 8)));
- EXPECT_TRUE(ConstantRange(APInt(16, 6), APInt(16, 4)).unionWith(
- ConstantRange(APInt(16, 4), APInt(16, 0))) ==
+ EXPECT_EQ(ConstantRange(APInt(16, 14), APInt(16, 1)).unionWith(
+ ConstantRange(APInt(16, 0), APInt(16, 8))),
+ ConstantRange(APInt(16, 14), APInt(16, 8)));
+ EXPECT_EQ(ConstantRange(APInt(16, 6), APInt(16, 4)).unionWith(
+ ConstantRange(APInt(16, 4), APInt(16, 0))),
ConstantRange(16));
- EXPECT_TRUE(ConstantRange(APInt(16, 1), APInt(16, 0)).unionWith(
- ConstantRange(APInt(16, 2), APInt(16, 1))) ==
+ EXPECT_EQ(ConstantRange(APInt(16, 1), APInt(16, 0)).unionWith(
+ ConstantRange(APInt(16, 2), APInt(16, 1))),
ConstantRange(16));
}
TEST_F(ConstantRangeTest, SubtractAPInt) {
- EXPECT_TRUE(Full.subtract(APInt(16, 4)).isFullSet());
- EXPECT_TRUE(Empty.subtract(APInt(16, 4)).isEmptySet());
- EXPECT_TRUE(Some.subtract(APInt(16, 4)) ==
- ConstantRange(APInt(16, 0x6), APInt(16, 0xaa6)));
- EXPECT_TRUE(Wrap.subtract(APInt(16, 4)) ==
- ConstantRange(APInt(16, 0xaa6), APInt(16, 0x6)));
- EXPECT_TRUE(One.subtract(APInt(16, 4)) ==
- ConstantRange(APInt(16, 0x6)));
+ EXPECT_EQ(Full.subtract(APInt(16, 4)), Full);
+ EXPECT_EQ(Empty.subtract(APInt(16, 4)), Empty);
+ EXPECT_EQ(Some.subtract(APInt(16, 4)),
+ ConstantRange(APInt(16, 0x6), APInt(16, 0xaa6)));
+ EXPECT_EQ(Wrap.subtract(APInt(16, 4)),
+ ConstantRange(APInt(16, 0xaa6), APInt(16, 0x6)));
+ EXPECT_EQ(One.subtract(APInt(16, 4)),
+ ConstantRange(APInt(16, 0x6)));
}
TEST_F(ConstantRangeTest, Add) {
- EXPECT_TRUE(Full.add(APInt(16, 4)).isFullSet());
- EXPECT_TRUE(Full.add(Full) == Full);
- EXPECT_TRUE(Full.add(Empty) == Empty);
- EXPECT_TRUE(Full.add(One) == Full);
- EXPECT_TRUE(Full.add(Some) == Full);
- EXPECT_TRUE(Full.add(Wrap) == Full);
- EXPECT_TRUE(Empty.add(Empty) == Empty);
- EXPECT_TRUE(Empty.add(One) == Empty);
- EXPECT_TRUE(Empty.add(Some) == Empty);
- EXPECT_TRUE(Empty.add(Wrap) == Empty);
- EXPECT_TRUE(Empty.add(APInt(16, 4)).isEmptySet());
- EXPECT_TRUE(Some.add(APInt(16, 4)) ==
+ EXPECT_EQ(Full.add(APInt(16, 4)), Full);
+ EXPECT_EQ(Full.add(Full), Full);
+ EXPECT_EQ(Full.add(Empty), Empty);
+ EXPECT_EQ(Full.add(One), Full);
+ EXPECT_EQ(Full.add(Some), Full);
+ EXPECT_EQ(Full.add(Wrap), Full);
+ EXPECT_EQ(Empty.add(Empty), Empty);
+ EXPECT_EQ(Empty.add(One), Empty);
+ EXPECT_EQ(Empty.add(Some), Empty);
+ EXPECT_EQ(Empty.add(Wrap), Empty);
+ EXPECT_EQ(Empty.add(APInt(16, 4)), Empty);
+ EXPECT_EQ(Some.add(APInt(16, 4)),
ConstantRange(APInt(16, 0xe), APInt(16, 0xaae)));
- EXPECT_TRUE(Wrap.add(APInt(16, 4)) ==
+ EXPECT_EQ(Wrap.add(APInt(16, 4)),
ConstantRange(APInt(16, 0xaae), APInt(16, 0xe)));
- EXPECT_TRUE(One.add(APInt(16, 4)) ==
+ EXPECT_EQ(One.add(APInt(16, 4)),
ConstantRange(APInt(16, 0xe)));
}
TEST_F(ConstantRangeTest, Multiply) {
- EXPECT_TRUE(Full.multiply(Full) == Full);
- EXPECT_TRUE(Full.multiply(Empty) == Empty);
- EXPECT_TRUE(Full.multiply(One) == Full);
- EXPECT_TRUE(Full.multiply(Some) == Full);
- EXPECT_TRUE(Full.multiply(Wrap) == Full);
- EXPECT_TRUE(Empty.multiply(Empty) == Empty);
- EXPECT_TRUE(Empty.multiply(One) == Empty);
- EXPECT_TRUE(Empty.multiply(Some) == Empty);
- EXPECT_TRUE(Empty.multiply(Wrap) == Empty);
- EXPECT_TRUE(One.multiply(One) == ConstantRange(APInt(16, 0xa*0xa),
- APInt(16, 0xa*0xa + 1)));
- EXPECT_TRUE(One.multiply(Some) == ConstantRange(APInt(16, 0xa*0xa),
- APInt(16, 0xa*0xaa9 + 1)));
- EXPECT_TRUE(One.multiply(Wrap).isFullSet());
- EXPECT_TRUE(Some.multiply(Some).isFullSet());
- EXPECT_TRUE(Some.multiply(Wrap) == Full);
- EXPECT_TRUE(Wrap.multiply(Wrap) == Full);
+ EXPECT_EQ(Full.multiply(Full), Full);
+ EXPECT_EQ(Full.multiply(Empty), Empty);
+ EXPECT_EQ(Full.multiply(One), Full);
+ EXPECT_EQ(Full.multiply(Some), Full);
+ EXPECT_EQ(Full.multiply(Wrap), Full);
+ EXPECT_EQ(Empty.multiply(Empty), Empty);
+ EXPECT_EQ(Empty.multiply(One), Empty);
+ EXPECT_EQ(Empty.multiply(Some), Empty);
+ EXPECT_EQ(Empty.multiply(Wrap), Empty);
+ EXPECT_EQ(One.multiply(One), ConstantRange(APInt(16, 0xa*0xa),
+ APInt(16, 0xa*0xa + 1)));
+ EXPECT_EQ(One.multiply(Some), ConstantRange(APInt(16, 0xa*0xa),
+ APInt(16, 0xa*0xaa9 + 1)));
+ EXPECT_EQ(One.multiply(Wrap), Full);
+ EXPECT_EQ(Some.multiply(Some), Full);
+ EXPECT_EQ(Some.multiply(Wrap), Full);
+ EXPECT_EQ(Wrap.multiply(Wrap), Full);
// http://llvm.org/PR4545
- EXPECT_TRUE(ConstantRange(APInt(4, 1), APInt(4, 6)).multiply(
- ConstantRange(APInt(4, 6), APInt(4, 2))) ==
- ConstantRange(4, /*isFullSet=*/true));
+ EXPECT_EQ(ConstantRange(APInt(4, 1), APInt(4, 6)).multiply(
+ ConstantRange(APInt(4, 6), APInt(4, 2))),
+ ConstantRange(4, /*isFullSet=*/true));
}
TEST_F(ConstantRangeTest, UMax) {
- EXPECT_TRUE(Full.umax(Full).isFullSet());
- EXPECT_TRUE(Full.umax(Empty).isEmptySet());
- EXPECT_TRUE(Full.umax(Some) == ConstantRange(APInt(16, 0xa), APInt(16, 0)));
- EXPECT_TRUE(Full.umax(Wrap).isFullSet());
- EXPECT_TRUE(Full.umax(Some) == ConstantRange(APInt(16, 0xa), APInt(16, 0)));
- EXPECT_TRUE(Empty.umax(Empty) == Empty);
- EXPECT_TRUE(Empty.umax(Some) == Empty);
- EXPECT_TRUE(Empty.umax(Wrap) == Empty);
- EXPECT_TRUE(Empty.umax(One) == Empty);
- EXPECT_TRUE(Some.umax(Some) == Some);
- EXPECT_TRUE(Some.umax(Wrap) == ConstantRange(APInt(16, 0xa), APInt(16, 0)));
- EXPECT_TRUE(Some.umax(One) == Some);
+ EXPECT_EQ(Full.umax(Full), Full);
+ EXPECT_EQ(Full.umax(Empty), Empty);
+ EXPECT_EQ(Full.umax(Some), ConstantRange(APInt(16, 0xa), APInt(16, 0)));
+ EXPECT_EQ(Full.umax(Wrap), Full);
+ EXPECT_EQ(Full.umax(Some), ConstantRange(APInt(16, 0xa), APInt(16, 0)));
+ EXPECT_EQ(Empty.umax(Empty), Empty);
+ EXPECT_EQ(Empty.umax(Some), Empty);
+ EXPECT_EQ(Empty.umax(Wrap), Empty);
+ EXPECT_EQ(Empty.umax(One), Empty);
+ EXPECT_EQ(Some.umax(Some), Some);
+ EXPECT_EQ(Some.umax(Wrap), ConstantRange(APInt(16, 0xa), APInt(16, 0)));
+ EXPECT_EQ(Some.umax(One), Some);
// TODO: ConstantRange is currently over-conservative here.
- EXPECT_TRUE(Wrap.umax(Wrap) == Full);
- EXPECT_TRUE(Wrap.umax(One) == ConstantRange(APInt(16, 0xa), APInt(16, 0)));
- EXPECT_TRUE(One.umax(One) == One);
+ EXPECT_EQ(Wrap.umax(Wrap), Full);
+ EXPECT_EQ(Wrap.umax(One), ConstantRange(APInt(16, 0xa), APInt(16, 0)));
+ EXPECT_EQ(One.umax(One), One);
}
TEST_F(ConstantRangeTest, SMax) {
- EXPECT_TRUE(Full.smax(Full).isFullSet());
- EXPECT_TRUE(Full.smax(Empty).isEmptySet());
- EXPECT_TRUE(Full.smax(Some) == ConstantRange(APInt(16, 0xa),
- APInt::getSignedMinValue(16)));
- EXPECT_TRUE(Full.smax(Wrap).isFullSet());
- EXPECT_TRUE(Full.smax(One) == ConstantRange(APInt(16, 0xa),
- APInt::getSignedMinValue(16)));
- EXPECT_TRUE(Empty.smax(Empty) == Empty);
- EXPECT_TRUE(Empty.smax(Some) == Empty);
- EXPECT_TRUE(Empty.smax(Wrap) == Empty);
- EXPECT_TRUE(Empty.smax(One) == Empty);
- EXPECT_TRUE(Some.smax(Some) == Some);
- EXPECT_TRUE(Some.smax(Wrap) == ConstantRange(APInt(16, 0xa),
- APInt(16, (uint64_t)INT16_MIN)));
- EXPECT_TRUE(Some.smax(One) == Some);
- EXPECT_TRUE(Wrap.smax(One) == ConstantRange(APInt(16, 0xa),
- APInt(16, (uint64_t)INT16_MIN)));
- EXPECT_TRUE(One.smax(One) == One);
+ EXPECT_EQ(Full.smax(Full), Full);
+ EXPECT_EQ(Full.smax(Empty), Empty);
+ EXPECT_EQ(Full.smax(Some), ConstantRange(APInt(16, 0xa),
+ APInt::getSignedMinValue(16)));
+ EXPECT_EQ(Full.smax(Wrap), Full);
+ EXPECT_EQ(Full.smax(One), ConstantRange(APInt(16, 0xa),
+ APInt::getSignedMinValue(16)));
+ EXPECT_EQ(Empty.smax(Empty), Empty);
+ EXPECT_EQ(Empty.smax(Some), Empty);
+ EXPECT_EQ(Empty.smax(Wrap), Empty);
+ EXPECT_EQ(Empty.smax(One), Empty);
+ EXPECT_EQ(Some.smax(Some), Some);
+ EXPECT_EQ(Some.smax(Wrap), ConstantRange(APInt(16, 0xa),
+ APInt(16, (uint64_t)INT16_MIN)));
+ EXPECT_EQ(Some.smax(One), Some);
+ EXPECT_EQ(Wrap.smax(One), ConstantRange(APInt(16, 0xa),
+ APInt(16, (uint64_t)INT16_MIN)));
+ EXPECT_EQ(One.smax(One), One);
}
TEST_F(ConstantRangeTest, UDiv) {
- EXPECT_TRUE(Full.udiv(Full) == Full);
- EXPECT_TRUE(Full.udiv(Empty) == Empty);
- EXPECT_TRUE(Full.udiv(One) == ConstantRange(APInt(16, 0),
- APInt(16, 0xffff / 0xa + 1)));
- EXPECT_TRUE(Full.udiv(Some) == ConstantRange(APInt(16, 0),
- APInt(16, 0xffff / 0xa + 1)));
- EXPECT_TRUE(Full.udiv(Wrap) == Full);
- EXPECT_TRUE(Empty.udiv(Empty) == Empty);
- EXPECT_TRUE(Empty.udiv(One) == Empty);
- EXPECT_TRUE(Empty.udiv(Some) == Empty);
- EXPECT_TRUE(Empty.udiv(Wrap) == Empty);
- EXPECT_TRUE(One.udiv(One) == ConstantRange(APInt(16, 1)));
- EXPECT_TRUE(One.udiv(Some) == ConstantRange(APInt(16, 0), APInt(16, 2)));
- EXPECT_TRUE(One.udiv(Wrap) == ConstantRange(APInt(16, 0), APInt(16, 0xb)));
- EXPECT_TRUE(Some.udiv(Some) == ConstantRange(APInt(16, 0), APInt(16, 0x111)));
- EXPECT_TRUE(Some.udiv(Wrap) == ConstantRange(APInt(16, 0), APInt(16, 0xaaa)));
- EXPECT_TRUE(Wrap.udiv(Wrap) == Full);
+ EXPECT_EQ(Full.udiv(Full), Full);
+ EXPECT_EQ(Full.udiv(Empty), Empty);
+ EXPECT_EQ(Full.udiv(One), ConstantRange(APInt(16, 0),
+ APInt(16, 0xffff / 0xa + 1)));
+ EXPECT_EQ(Full.udiv(Some), ConstantRange(APInt(16, 0),
+ APInt(16, 0xffff / 0xa + 1)));
+ EXPECT_EQ(Full.udiv(Wrap), Full);
+ EXPECT_EQ(Empty.udiv(Empty), Empty);
+ EXPECT_EQ(Empty.udiv(One), Empty);
+ EXPECT_EQ(Empty.udiv(Some), Empty);
+ EXPECT_EQ(Empty.udiv(Wrap), Empty);
+ EXPECT_EQ(One.udiv(One), ConstantRange(APInt(16, 1)));
+ EXPECT_EQ(One.udiv(Some), ConstantRange(APInt(16, 0), APInt(16, 2)));
+ EXPECT_EQ(One.udiv(Wrap), ConstantRange(APInt(16, 0), APInt(16, 0xb)));
+ EXPECT_EQ(Some.udiv(Some), ConstantRange(APInt(16, 0), APInt(16, 0x111)));
+ EXPECT_EQ(Some.udiv(Wrap), ConstantRange(APInt(16, 0), APInt(16, 0xaaa)));
+ EXPECT_EQ(Wrap.udiv(Wrap), Full);
}
} // anonymous namespace
diff --git a/libclamav/c++/llvm/unittests/Support/RegexTest.cpp b/libclamav/c++/llvm/unittests/Support/RegexTest.cpp
index b323e28..44c7e55 100644
--- a/libclamav/c++/llvm/unittests/Support/RegexTest.cpp
+++ b/libclamav/c++/llvm/unittests/Support/RegexTest.cpp
@@ -9,6 +9,7 @@
#include "gtest/gtest.h"
#include "llvm/Support/Regex.h"
+#include "llvm/ADT/SmallVector.h"
#include <cstring>
using namespace llvm;
@@ -24,12 +25,12 @@ TEST_F(RegexTest, Basics) {
EXPECT_FALSE(r1.match("9a"));
SmallVector<StringRef, 1> Matches;
- Regex r2("[0-9]+", Regex::Sub);
+ Regex r2("[0-9]+");
EXPECT_TRUE(r2.match("aa216b", &Matches));
EXPECT_EQ(1u, Matches.size());
EXPECT_EQ("216", Matches[0].str());
- Regex r3("[0-9]+([a-f])?:([0-9]+)", Regex::Sub);
+ Regex r3("[0-9]+([a-f])?:([0-9]+)");
EXPECT_TRUE(r3.match("9a:513b", &Matches));
EXPECT_EQ(3u, Matches.size());
EXPECT_EQ("9a:513", Matches[0].str());
@@ -42,7 +43,7 @@ TEST_F(RegexTest, Basics) {
EXPECT_EQ("", Matches[1].str());
EXPECT_EQ("513", Matches[2].str());
- Regex r4("a[^b]+b", Regex::Sub);
+ Regex r4("a[^b]+b");
std::string String="axxb";
String[2] = '\0';
EXPECT_FALSE(r4.match("abb"));
@@ -54,7 +55,7 @@ TEST_F(RegexTest, Basics) {
std::string NulPattern="X[0-9]+X([a-f])?:([0-9]+)";
String="YX99a:513b";
NulPattern[7] = '\0';
- Regex r5(NulPattern, Regex::Sub);
+ Regex r5(NulPattern);
EXPECT_FALSE(r5.match(String));
EXPECT_FALSE(r5.match("X9"));
String[3]='\0';
diff --git a/libclamav/c++/llvm/unittests/Support/TypeBuilderTest.cpp b/libclamav/c++/llvm/unittests/Support/TypeBuilderTest.cpp
index bd9f5d6..fae8907 100644
--- a/libclamav/c++/llvm/unittests/Support/TypeBuilderTest.cpp
+++ b/libclamav/c++/llvm/unittests/Support/TypeBuilderTest.cpp
@@ -147,6 +147,18 @@ TEST(TypeBuilderTest, Functions) {
false>::get(getGlobalContext())));
}
+TEST(TypeBuilderTest, Context) {
+ // We used to cache TypeBuilder results in static local variables. This
+ // produced the same type for different contexts, which of course broke
+ // things.
+ LLVMContext context1;
+ EXPECT_EQ(&context1,
+ &(TypeBuilder<types::i<1>, true>::get(context1))->getContext());
+ LLVMContext context2;
+ EXPECT_EQ(&context2,
+ &(TypeBuilder<types::i<1>, true>::get(context2))->getContext());
+}
+
class MyType {
int a;
int *b;
diff --git a/libclamav/c++/llvm/unittests/Support/raw_ostream_test.cpp b/libclamav/c++/llvm/unittests/Support/raw_ostream_test.cpp
index 52639ba..bd2e95c 100644
--- a/libclamav/c++/llvm/unittests/Support/raw_ostream_test.cpp
+++ b/libclamav/c++/llvm/unittests/Support/raw_ostream_test.cpp
@@ -117,4 +117,14 @@ TEST(raw_ostreamTest, BufferEdge) {
EXPECT_EQ("1.20", printToString(format("%.2f", 1.2), 10));
}
+TEST(raw_ostreamTest, TinyBuffer) {
+ std::string Str;
+ raw_string_ostream OS(Str);
+ OS.SetBufferSize(1);
+ OS << "hello";
+ OS << 1;
+ OS << 'w' << 'o' << 'r' << 'l' << 'd';
+ EXPECT_EQ("hello1world", OS.str());
+}
+
}
diff --git a/libclamav/c++/llvm/unittests/TestMain.cpp b/libclamav/c++/llvm/unittests/TestMain.cpp
deleted file mode 100644
index 095076b..0000000
--- a/libclamav/c++/llvm/unittests/TestMain.cpp
+++ /dev/null
@@ -1,15 +0,0 @@
-//===--- unittests/TestMain.cpp - unittest driver -------------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "gtest/gtest.h"
-
-int main(int argc, char **argv) {
- testing::InitGoogleTest(&argc, argv);
- return RUN_ALL_TESTS();
-}
diff --git a/libclamav/c++/llvm/unittests/Transforms/Makefile b/libclamav/c++/llvm/unittests/Transforms/Makefile
new file mode 100644
index 0000000..599b18a
--- /dev/null
+++ b/libclamav/c++/llvm/unittests/Transforms/Makefile
@@ -0,0 +1,17 @@
+##===- unittests/Transforms/Makefile -----------------------*- Makefile -*-===##
+#
+# The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+
+LEVEL = ../..
+
+PARALLEL_DIRS = Utils
+
+include $(LEVEL)/Makefile.common
+
+clean::
+ $(Verb) $(RM) -f *Tests
diff --git a/libclamav/c++/llvm/unittests/Transforms/Utils/Cloning.cpp b/libclamav/c++/llvm/unittests/Transforms/Utils/Cloning.cpp
new file mode 100644
index 0000000..7c93f6f
--- /dev/null
+++ b/libclamav/c++/llvm/unittests/Transforms/Utils/Cloning.cpp
@@ -0,0 +1,87 @@
+//===- Cloning.cpp - Unit tests for the Cloner ----------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "gtest/gtest.h"
+#include "llvm/Argument.h"
+#include "llvm/Instructions.h"
+
+using namespace llvm;
+
+TEST(CloneInstruction, OverflowBits) {
+ LLVMContext context;
+ Value *V = new Argument(Type::getInt32Ty(context));
+
+ BinaryOperator *Add = BinaryOperator::Create(Instruction::Add, V, V);
+ BinaryOperator *Sub = BinaryOperator::Create(Instruction::Sub, V, V);
+ BinaryOperator *Mul = BinaryOperator::Create(Instruction::Mul, V, V);
+
+ EXPECT_FALSE(Add->clone()->hasNoUnsignedWrap());
+ EXPECT_FALSE(Add->clone()->hasNoSignedWrap());
+ EXPECT_FALSE(Sub->clone()->hasNoUnsignedWrap());
+ EXPECT_FALSE(Sub->clone()->hasNoSignedWrap());
+ EXPECT_FALSE(Mul->clone()->hasNoUnsignedWrap());
+ EXPECT_FALSE(Mul->clone()->hasNoSignedWrap());
+
+ Add->setHasNoUnsignedWrap();
+ Sub->setHasNoUnsignedWrap();
+ Mul->setHasNoUnsignedWrap();
+
+ EXPECT_TRUE(Add->clone()->hasNoUnsignedWrap());
+ EXPECT_FALSE(Add->clone()->hasNoSignedWrap());
+ EXPECT_TRUE(Sub->clone()->hasNoUnsignedWrap());
+ EXPECT_FALSE(Sub->clone()->hasNoSignedWrap());
+ EXPECT_TRUE(Mul->clone()->hasNoUnsignedWrap());
+ EXPECT_FALSE(Mul->clone()->hasNoSignedWrap());
+
+ Add->setHasNoSignedWrap();
+ Sub->setHasNoSignedWrap();
+ Mul->setHasNoSignedWrap();
+
+ EXPECT_TRUE(Add->clone()->hasNoUnsignedWrap());
+ EXPECT_TRUE(Add->clone()->hasNoSignedWrap());
+ EXPECT_TRUE(Sub->clone()->hasNoUnsignedWrap());
+ EXPECT_TRUE(Sub->clone()->hasNoSignedWrap());
+ EXPECT_TRUE(Mul->clone()->hasNoUnsignedWrap());
+ EXPECT_TRUE(Mul->clone()->hasNoSignedWrap());
+
+ Add->setHasNoUnsignedWrap(false);
+ Sub->setHasNoUnsignedWrap(false);
+ Mul->setHasNoUnsignedWrap(false);
+
+ EXPECT_FALSE(Add->clone()->hasNoUnsignedWrap());
+ EXPECT_TRUE(Add->clone()->hasNoSignedWrap());
+ EXPECT_FALSE(Sub->clone()->hasNoUnsignedWrap());
+ EXPECT_TRUE(Sub->clone()->hasNoSignedWrap());
+ EXPECT_FALSE(Mul->clone()->hasNoUnsignedWrap());
+ EXPECT_TRUE(Mul->clone()->hasNoSignedWrap());
+}
+
+TEST(CloneInstruction, Inbounds) {
+ LLVMContext context;
+ Value *V = new Argument(Type::getInt32Ty(context)->getPointerTo());
+ Constant *Z = Constant::getNullValue(Type::getInt32Ty(context));
+ std::vector<Value *> ops;
+ ops.push_back(Z);
+ GetElementPtrInst *GEP = GetElementPtrInst::Create(V, ops.begin(), ops.end());
+ EXPECT_FALSE(GEP->clone()->isInBounds());
+
+ GEP->setIsInBounds();
+ EXPECT_TRUE(GEP->clone()->isInBounds());
+}
+
+TEST(CloneInstruction, Exact) {
+ LLVMContext context;
+ Value *V = new Argument(Type::getInt32Ty(context));
+
+ BinaryOperator *SDiv = BinaryOperator::Create(Instruction::SDiv, V, V);
+ EXPECT_FALSE(SDiv->clone()->isExact());
+
+ SDiv->setIsExact(true);
+ EXPECT_TRUE(SDiv->clone()->isExact());
+}
diff --git a/libclamav/c++/llvm/unittests/Transforms/Utils/Makefile b/libclamav/c++/llvm/unittests/Transforms/Utils/Makefile
new file mode 100644
index 0000000..fdf4be0
--- /dev/null
+++ b/libclamav/c++/llvm/unittests/Transforms/Utils/Makefile
@@ -0,0 +1,15 @@
+##===- unittests/Transforms/Utils/Makefile -----------------*- Makefile -*-===##
+#
+# The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+
+LEVEL = ../../..
+TESTNAME = Utils
+LINK_COMPONENTS := core support transformutils
+
+include $(LEVEL)/Makefile.config
+include $(LLVM_SRC_ROOT)/unittests/Makefile.unittest
diff --git a/libclamav/c++/llvm/unittests/VMCore/MetadataTest.cpp b/libclamav/c++/llvm/unittests/VMCore/MetadataTest.cpp
index cdf5a6e..b92b068 100644
--- a/libclamav/c++/llvm/unittests/VMCore/MetadataTest.cpp
+++ b/libclamav/c++/llvm/unittests/VMCore/MetadataTest.cpp
@@ -85,7 +85,11 @@ TEST(MDNodeTest, Simple) {
MDNode *n2 = MDNode::get(Context, &c1, 1);
MDNode *n3 = MDNode::get(Context, &V[0], 3);
EXPECT_NE(n1, n2);
+#ifdef ENABLE_MDNODE_UNIQUING
EXPECT_EQ(n1, n3);
+#else
+ (void) n3;
+#endif
EXPECT_EQ(3u, n1->getNumElements());
EXPECT_EQ(s1, n1->getElement(0));
diff --git a/libclamav/c++/llvm/utils/FileCheck/FileCheck.cpp b/libclamav/c++/llvm/utils/FileCheck/FileCheck.cpp
index c092ded..b4d1f84 100644
--- a/libclamav/c++/llvm/utils/FileCheck/FileCheck.cpp
+++ b/libclamav/c++/llvm/utils/FileCheck/FileCheck.cpp
@@ -19,9 +19,12 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/PrettyStackTrace.h"
+#include "llvm/Support/Regex.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/System/Signals.h"
+#include "llvm/ADT/StringMap.h"
+#include <algorithm>
using namespace llvm;
static cl::opt<std::string>
@@ -39,10 +42,282 @@ static cl::opt<bool>
NoCanonicalizeWhiteSpace("strict-whitespace",
cl::desc("Do not treat all horizontal whitespace as equivalent"));
+//===----------------------------------------------------------------------===//
+// Pattern Handling Code.
+//===----------------------------------------------------------------------===//
+
+class Pattern {
+ SMLoc PatternLoc;
+
+ /// FixedStr - If non-empty, this pattern is a fixed string match with the
+ /// specified fixed string.
+ StringRef FixedStr;
+
+ /// RegEx - If non-empty, this is a regex pattern.
+ std::string RegExStr;
+
+ /// VariableUses - Entries in this vector map to uses of a variable in the
+ /// pattern, e.g. "foo[[bar]]baz". In this case, the RegExStr will contain
+ /// "foobaz" and we'll get an entry in this vector that tells us to insert the
+ /// value of bar at offset 3.
+ std::vector<std::pair<StringRef, unsigned> > VariableUses;
+
+ /// VariableDefs - Entries in this vector map to definitions of a variable in
+ /// the pattern, e.g. "foo[[bar:.*]]baz". In this case, the RegExStr will
+ /// contain "foo(.*)baz" and VariableDefs will contain the pair "bar",1. The
+ /// index indicates what parenthesized value captures the variable value.
+ std::vector<std::pair<StringRef, unsigned> > VariableDefs;
+
+public:
+
+ Pattern() { }
+
+ bool ParsePattern(StringRef PatternStr, SourceMgr &SM);
+
+ /// Match - Match the pattern string against the input buffer Buffer. This
+ /// returns the position that is matched or npos if there is no match. If
+ /// there is a match, the size of the matched string is returned in MatchLen.
+ ///
+ /// The VariableTable StringMap provides the current values of filecheck
+ /// variables and is updated if this match defines new values.
+ size_t Match(StringRef Buffer, size_t &MatchLen,
+ StringMap<StringRef> &VariableTable) const;
+
+private:
+ static void AddFixedStringToRegEx(StringRef FixedStr, std::string &TheStr);
+ bool AddRegExToRegEx(StringRef RegExStr, unsigned &CurParen, SourceMgr &SM);
+};
+
+
+bool Pattern::ParsePattern(StringRef PatternStr, SourceMgr &SM) {
+ PatternLoc = SMLoc::getFromPointer(PatternStr.data());
+
+ // Ignore trailing whitespace.
+ while (!PatternStr.empty() &&
+ (PatternStr.back() == ' ' || PatternStr.back() == '\t'))
+ PatternStr = PatternStr.substr(0, PatternStr.size()-1);
+
+ // Check that there is something on the line.
+ if (PatternStr.empty()) {
+ SM.PrintMessage(PatternLoc, "found empty check string with prefix '" +
+ CheckPrefix+":'", "error");
+ return true;
+ }
+
+ // Check to see if this is a fixed string, or if it has regex pieces.
+ if (PatternStr.size() < 2 ||
+ (PatternStr.find("{{") == StringRef::npos &&
+ PatternStr.find("[[") == StringRef::npos)) {
+ FixedStr = PatternStr;
+ return false;
+ }
+
+ // Paren value #0 is for the fully matched string. Any new parenthesized
+ // values add from their.
+ unsigned CurParen = 1;
+
+ // Otherwise, there is at least one regex piece. Build up the regex pattern
+ // by escaping scary characters in fixed strings, building up one big regex.
+ while (!PatternStr.empty()) {
+ // RegEx matches.
+ if (PatternStr.size() >= 2 &&
+ PatternStr[0] == '{' && PatternStr[1] == '{') {
+
+ // Otherwise, this is the start of a regex match. Scan for the }}.
+ size_t End = PatternStr.find("}}");
+ if (End == StringRef::npos) {
+ SM.PrintMessage(SMLoc::getFromPointer(PatternStr.data()),
+ "found start of regex string with no end '}}'", "error");
+ return true;
+ }
+
+ if (AddRegExToRegEx(PatternStr.substr(2, End-2), CurParen, SM))
+ return true;
+ PatternStr = PatternStr.substr(End+2);
+ continue;
+ }
+
+ // Named RegEx matches. These are of two forms: [[foo:.*]] which matches .*
+ // (or some other regex) and assigns it to the FileCheck variable 'foo'. The
+ // second form is [[foo]] which is a reference to foo. The variable name
+ // itself must be of the form "[a-zA-Z][0-9a-zA-Z]*", otherwise we reject
+ // it. This is to catch some common errors.
+ if (PatternStr.size() >= 2 &&
+ PatternStr[0] == '[' && PatternStr[1] == '[') {
+ // Verify that it is terminated properly.
+ size_t End = PatternStr.find("]]");
+ if (End == StringRef::npos) {
+ SM.PrintMessage(SMLoc::getFromPointer(PatternStr.data()),
+ "invalid named regex reference, no ]] found", "error");
+ return true;
+ }
+
+ StringRef MatchStr = PatternStr.substr(2, End-2);
+ PatternStr = PatternStr.substr(End+2);
+
+ // Get the regex name (e.g. "foo").
+ size_t NameEnd = MatchStr.find(':');
+ StringRef Name = MatchStr.substr(0, NameEnd);
+
+ if (Name.empty()) {
+ SM.PrintMessage(SMLoc::getFromPointer(Name.data()),
+ "invalid name in named regex: empty name", "error");
+ return true;
+ }
+
+ // Verify that the name is well formed.
+ for (unsigned i = 0, e = Name.size(); i != e; ++i)
+ if ((Name[i] < 'a' || Name[i] > 'z') &&
+ (Name[i] < 'A' || Name[i] > 'Z') &&
+ (Name[i] < '0' || Name[i] > '9')) {
+ SM.PrintMessage(SMLoc::getFromPointer(Name.data()+i),
+ "invalid name in named regex", "error");
+ return true;
+ }
+
+ // Name can't start with a digit.
+ if (isdigit(Name[0])) {
+ SM.PrintMessage(SMLoc::getFromPointer(Name.data()),
+ "invalid name in named regex", "error");
+ return true;
+ }
+
+ // Handle [[foo]].
+ if (NameEnd == StringRef::npos) {
+ VariableUses.push_back(std::make_pair(Name, RegExStr.size()));
+ continue;
+ }
+
+ // Handle [[foo:.*]].
+ VariableDefs.push_back(std::make_pair(Name, CurParen));
+ RegExStr += '(';
+ ++CurParen;
+
+ if (AddRegExToRegEx(MatchStr.substr(NameEnd+1), CurParen, SM))
+ return true;
+
+ RegExStr += ')';
+ }
+
+ // Handle fixed string matches.
+ // Find the end, which is the start of the next regex.
+ size_t FixedMatchEnd = PatternStr.find("{{");
+ FixedMatchEnd = std::min(FixedMatchEnd, PatternStr.find("[["));
+ AddFixedStringToRegEx(PatternStr.substr(0, FixedMatchEnd), RegExStr);
+ PatternStr = PatternStr.substr(FixedMatchEnd);
+ continue;
+ }
+
+ return false;
+}
+
+void Pattern::AddFixedStringToRegEx(StringRef FixedStr, std::string &TheStr) {
+ // Add the characters from FixedStr to the regex, escaping as needed. This
+ // avoids "leaning toothpicks" in common patterns.
+ for (unsigned i = 0, e = FixedStr.size(); i != e; ++i) {
+ switch (FixedStr[i]) {
+ // These are the special characters matched in "p_ere_exp".
+ case '(':
+ case ')':
+ case '^':
+ case '$':
+ case '|':
+ case '*':
+ case '+':
+ case '?':
+ case '.':
+ case '[':
+ case '\\':
+ case '{':
+ TheStr += '\\';
+ // FALL THROUGH.
+ default:
+ TheStr += FixedStr[i];
+ break;
+ }
+ }
+}
+
+bool Pattern::AddRegExToRegEx(StringRef RegexStr, unsigned &CurParen,
+ SourceMgr &SM) {
+ Regex R(RegexStr);
+ std::string Error;
+ if (!R.isValid(Error)) {
+ SM.PrintMessage(SMLoc::getFromPointer(RegexStr.data()),
+ "invalid regex: " + Error, "error");
+ return true;
+ }
+
+ RegExStr += RegexStr.str();
+ CurParen += R.getNumMatches();
+ return false;
+}
+
+/// Match - Match the pattern string against the input buffer Buffer. This
+/// returns the position that is matched or npos if there is no match. If
+/// there is a match, the size of the matched string is returned in MatchLen.
+size_t Pattern::Match(StringRef Buffer, size_t &MatchLen,
+ StringMap<StringRef> &VariableTable) const {
+ // If this is a fixed string pattern, just match it now.
+ if (!FixedStr.empty()) {
+ MatchLen = FixedStr.size();
+ return Buffer.find(FixedStr);
+ }
+
+ // Regex match.
+
+ // If there are variable uses, we need to create a temporary string with the
+ // actual value.
+ StringRef RegExToMatch = RegExStr;
+ std::string TmpStr;
+ if (!VariableUses.empty()) {
+ TmpStr = RegExStr;
+
+ unsigned InsertOffset = 0;
+ for (unsigned i = 0, e = VariableUses.size(); i != e; ++i) {
+ // Look up the value and escape it so that we can plop it into the regex.
+ std::string Value;
+ AddFixedStringToRegEx(VariableTable[VariableUses[i].first], Value);
+
+ // Plop it into the regex at the adjusted offset.
+ TmpStr.insert(TmpStr.begin()+VariableUses[i].second+InsertOffset,
+ Value.begin(), Value.end());
+ InsertOffset += Value.size();
+ }
+
+ // Match the newly constructed regex.
+ RegExToMatch = TmpStr;
+ }
+
+
+ SmallVector<StringRef, 4> MatchInfo;
+ if (!Regex(RegExToMatch, Regex::Newline).match(Buffer, &MatchInfo))
+ return StringRef::npos;
+
+ // Successful regex match.
+ assert(!MatchInfo.empty() && "Didn't get any match");
+ StringRef FullMatch = MatchInfo[0];
+
+ // If this defines any variables, remember their values.
+ for (unsigned i = 0, e = VariableDefs.size(); i != e; ++i) {
+ assert(VariableDefs[i].second < MatchInfo.size() &&
+ "Internal paren error");
+ VariableTable[VariableDefs[i].first] = MatchInfo[VariableDefs[i].second];
+ }
+
+ MatchLen = FullMatch.size();
+ return FullMatch.data()-Buffer.data();
+}
+
+
+//===----------------------------------------------------------------------===//
+// Check Strings.
+//===----------------------------------------------------------------------===//
+
/// CheckString - This is a check that we found in the input file.
struct CheckString {
- /// Str - The string to match.
- std::string Str;
+ /// Pat - The pattern to match.
+ Pattern Pat;
/// Loc - The location in the match file that the check string was specified.
SMLoc Loc;
@@ -51,40 +326,47 @@ struct CheckString {
/// to a CHECK: directive.
bool IsCheckNext;
- CheckString(const std::string &S, SMLoc L, bool isCheckNext)
- : Str(S), Loc(L), IsCheckNext(isCheckNext) {}
+ /// NotStrings - These are all of the strings that are disallowed from
+ /// occurring between this match string and the previous one (or start of
+ /// file).
+ std::vector<std::pair<SMLoc, Pattern> > NotStrings;
+
+ CheckString(const Pattern &P, SMLoc L, bool isCheckNext)
+ : Pat(P), Loc(L), IsCheckNext(isCheckNext) {}
};
-
-/// FindFixedStringInBuffer - This works like strstr, except for two things:
-/// 1) it handles 'nul' characters in memory buffers. 2) it returns the end of
-/// the memory buffer on match failure instead of null.
-static const char *FindFixedStringInBuffer(StringRef Str, const char *CurPtr,
- const MemoryBuffer &MB) {
- assert(!Str.empty() && "Can't find an empty string");
- const char *BufEnd = MB.getBufferEnd();
+/// CanonicalizeInputFile - Remove duplicate horizontal space from the specified
+/// memory buffer, free it, and return a new one.
+static MemoryBuffer *CanonicalizeInputFile(MemoryBuffer *MB) {
+ SmallVector<char, 16> NewFile;
+ NewFile.reserve(MB->getBufferSize());
- while (1) {
- // Scan for the first character in the match string.
- CurPtr = (char*)memchr(CurPtr, Str[0], BufEnd-CurPtr);
-
- // If we didn't find the first character of the string, then we failed to
- // match.
- if (CurPtr == 0) return BufEnd;
-
- // If the match string is one character, then we win.
- if (Str.size() == 1) return CurPtr;
-
- // Otherwise, verify that the rest of the string matches.
- if (Str.size() <= unsigned(BufEnd-CurPtr) &&
- memcmp(CurPtr+1, Str.data()+1, Str.size()-1) == 0)
- return CurPtr;
+ for (const char *Ptr = MB->getBufferStart(), *End = MB->getBufferEnd();
+ Ptr != End; ++Ptr) {
+ // If C is not a horizontal whitespace, skip it.
+ if (*Ptr != ' ' && *Ptr != '\t') {
+ NewFile.push_back(*Ptr);
+ continue;
+ }
- // If not, advance past this character and try again.
- ++CurPtr;
+ // Otherwise, add one space and advance over neighboring space.
+ NewFile.push_back(' ');
+ while (Ptr+1 != End &&
+ (Ptr[1] == ' ' || Ptr[1] == '\t'))
+ ++Ptr;
}
+
+ // Free the old buffer and return a new one.
+ MemoryBuffer *MB2 =
+ MemoryBuffer::getMemBufferCopy(NewFile.data(),
+ NewFile.data() + NewFile.size(),
+ MB->getBufferIdentifier());
+
+ delete MB;
+ return MB2;
}
+
/// ReadCheckFile - Read the check file, which specifies the sequence of
/// expected strings. The strings are added to the CheckStrings vector.
static bool ReadCheckFile(SourceMgr &SM,
@@ -98,59 +380,63 @@ static bool ReadCheckFile(SourceMgr &SM,
<< ErrorStr << '\n';
return true;
}
+
+ // If we want to canonicalize whitespace, strip excess whitespace from the
+ // buffer containing the CHECK lines.
+ if (!NoCanonicalizeWhiteSpace)
+ F = CanonicalizeInputFile(F);
+
SM.AddNewSourceBuffer(F, SMLoc());
// Find all instances of CheckPrefix followed by : in the file.
- const char *CurPtr = F->getBufferStart(), *BufferEnd = F->getBufferEnd();
+ StringRef Buffer = F->getBuffer();
+ std::vector<std::pair<SMLoc, Pattern> > NotMatches;
+
while (1) {
// See if Prefix occurs in the memory buffer.
- const char *Ptr = FindFixedStringInBuffer(CheckPrefix, CurPtr, *F);
+ Buffer = Buffer.substr(Buffer.find(CheckPrefix));
// If we didn't find a match, we're done.
- if (Ptr == BufferEnd)
+ if (Buffer.empty())
break;
- const char *CheckPrefixStart = Ptr;
+ const char *CheckPrefixStart = Buffer.data();
// When we find a check prefix, keep track of whether we find CHECK: or
// CHECK-NEXT:
- bool IsCheckNext;
+ bool IsCheckNext = false, IsCheckNot = false;
// Verify that the : is present after the prefix.
- if (Ptr[CheckPrefix.size()] == ':') {
- Ptr += CheckPrefix.size()+1;
- IsCheckNext = false;
- } else if (BufferEnd-Ptr > 6 &&
- memcmp(Ptr+CheckPrefix.size(), "-NEXT:", 6) == 0) {
- Ptr += CheckPrefix.size()+7;
+ if (Buffer[CheckPrefix.size()] == ':') {
+ Buffer = Buffer.substr(CheckPrefix.size()+1);
+ } else if (Buffer.size() > CheckPrefix.size()+6 &&
+ memcmp(Buffer.data()+CheckPrefix.size(), "-NEXT:", 6) == 0) {
+ Buffer = Buffer.substr(CheckPrefix.size()+7);
IsCheckNext = true;
+ } else if (Buffer.size() > CheckPrefix.size()+5 &&
+ memcmp(Buffer.data()+CheckPrefix.size(), "-NOT:", 5) == 0) {
+ Buffer = Buffer.substr(CheckPrefix.size()+6);
+ IsCheckNot = true;
} else {
- CurPtr = Ptr+1;
+ Buffer = Buffer.substr(1);
continue;
}
// Okay, we found the prefix, yay. Remember the rest of the line, but
// ignore leading and trailing whitespace.
- while (*Ptr == ' ' || *Ptr == '\t')
- ++Ptr;
+ Buffer = Buffer.substr(Buffer.find_first_not_of(" \t"));
// Scan ahead to the end of line.
- CurPtr = Ptr;
- while (CurPtr != BufferEnd && *CurPtr != '\n' && *CurPtr != '\r')
- ++CurPtr;
-
- // Ignore trailing whitespace.
- while (CurPtr[-1] == ' ' || CurPtr[-1] == '\t')
- --CurPtr;
-
- // Check that there is something on the line.
- if (Ptr >= CurPtr) {
- SM.PrintMessage(SMLoc::getFromPointer(CurPtr),
- "found empty check string with prefix '"+CheckPrefix+":'",
- "error");
+ size_t EOL = Buffer.find_first_of("\n\r");
+
+ // Parse the pattern.
+ Pattern P;
+ if (P.ParsePattern(Buffer.substr(0, EOL), SM))
return true;
- }
+
+ Buffer = Buffer.substr(EOL);
+
// Verify that CHECK-NEXT lines have at least one CHECK line before them.
if (IsCheckNext && CheckStrings.empty()) {
@@ -160,10 +446,19 @@ static bool ReadCheckFile(SourceMgr &SM,
return true;
}
+ // Handle CHECK-NOT.
+ if (IsCheckNot) {
+ NotMatches.push_back(std::make_pair(SMLoc::getFromPointer(Buffer.data()),
+ P));
+ continue;
+ }
+
+
// Okay, add the string we captured to the output vector and move on.
- CheckStrings.push_back(CheckString(std::string(Ptr, CurPtr),
- SMLoc::getFromPointer(Ptr),
+ CheckStrings.push_back(CheckString(P,
+ SMLoc::getFromPointer(Buffer.data()),
IsCheckNext));
+ std::swap(NotMatches, CheckStrings.back().NotStrings);
}
if (CheckStrings.empty()) {
@@ -172,100 +467,47 @@ static bool ReadCheckFile(SourceMgr &SM,
return true;
}
- return false;
-}
-
-// CanonicalizeCheckStrings - Replace all sequences of horizontal whitespace in
-// the check strings with a single space.
-static void CanonicalizeCheckStrings(std::vector<CheckString> &CheckStrings) {
- for (unsigned i = 0, e = CheckStrings.size(); i != e; ++i) {
- std::string &Str = CheckStrings[i].Str;
-
- for (unsigned C = 0; C != Str.size(); ++C) {
- // If C is not a horizontal whitespace, skip it.
- if (Str[C] != ' ' && Str[C] != '\t')
- continue;
-
- // Replace the character with space, then remove any other space
- // characters after it.
- Str[C] = ' ';
-
- while (C+1 != Str.size() &&
- (Str[C+1] == ' ' || Str[C+1] == '\t'))
- Str.erase(Str.begin()+C+1);
- }
- }
-}
-
-/// CanonicalizeInputFile - Remove duplicate horizontal space from the specified
-/// memory buffer, free it, and return a new one.
-static MemoryBuffer *CanonicalizeInputFile(MemoryBuffer *MB) {
- SmallVector<char, 16> NewFile;
- NewFile.reserve(MB->getBufferSize());
-
- for (const char *Ptr = MB->getBufferStart(), *End = MB->getBufferEnd();
- Ptr != End; ++Ptr) {
- // If C is not a horizontal whitespace, skip it.
- if (*Ptr != ' ' && *Ptr != '\t') {
- NewFile.push_back(*Ptr);
- continue;
- }
-
- // Otherwise, add one space and advance over neighboring space.
- NewFile.push_back(' ');
- while (Ptr+1 != End &&
- (Ptr[1] == ' ' || Ptr[1] == '\t'))
- ++Ptr;
+ if (!NotMatches.empty()) {
+ errs() << "error: '" << CheckPrefix
+ << "-NOT:' not supported after last check line.\n";
+ return true;
}
- // Free the old buffer and return a new one.
- MemoryBuffer *MB2 =
- MemoryBuffer::getMemBufferCopy(NewFile.data(),
- NewFile.data() + NewFile.size(),
- MB->getBufferIdentifier());
-
- delete MB;
- return MB2;
+ return false;
}
-
static void PrintCheckFailed(const SourceMgr &SM, const CheckString &CheckStr,
- const char *CurPtr, const char *BufferEnd) {
+ StringRef Buffer) {
// Otherwise, we have an error, emit an error message.
SM.PrintMessage(CheckStr.Loc, "expected string not found in input",
"error");
// Print the "scanning from here" line. If the current position is at the
// end of a line, advance to the start of the next line.
- const char *Scan = CurPtr;
- while (Scan != BufferEnd &&
- (*Scan == ' ' || *Scan == '\t'))
- ++Scan;
- if (*Scan == '\n' || *Scan == '\r')
- CurPtr = Scan+1;
-
+ Buffer = Buffer.substr(Buffer.find_first_not_of(" \t\n\r"));
- SM.PrintMessage(SMLoc::getFromPointer(CurPtr), "scanning from here",
+ SM.PrintMessage(SMLoc::getFromPointer(Buffer.data()), "scanning from here",
"note");
}
-static unsigned CountNumNewlinesBetween(const char *Start, const char *End) {
+/// CountNumNewlinesBetween - Count the number of newlines in the specified
+/// range.
+static unsigned CountNumNewlinesBetween(StringRef Range) {
unsigned NumNewLines = 0;
- for (; Start != End; ++Start) {
+ while (1) {
// Scan for newline.
- if (Start[0] != '\n' && Start[0] != '\r')
- continue;
+ Range = Range.substr(Range.find_first_of("\n\r"));
+ if (Range.empty()) return NumNewLines;
++NumNewLines;
// Handle \n\r and \r\n as a single newline.
- if (Start+1 != End &&
- (Start[0] == '\n' || Start[0] == '\r') &&
- (Start[0] != Start[1]))
- ++Start;
+ if (Range.size() > 1 &&
+ (Range[1] == '\n' || Range[1] == '\r') &&
+ (Range[0] != Range[1]))
+ Range = Range.substr(1);
+ Range = Range.substr(1);
}
-
- return NumNewLines;
}
int main(int argc, char **argv) {
@@ -280,10 +522,6 @@ int main(int argc, char **argv) {
if (ReadCheckFile(SM, CheckStrings))
return 2;
- // Remove duplicate spaces in the check strings if requested.
- if (!NoCanonicalizeWhiteSpace)
- CanonicalizeCheckStrings(CheckStrings);
-
// Open the file to check and add it to SourceMgr.
std::string ErrorStr;
MemoryBuffer *F =
@@ -300,35 +538,45 @@ int main(int argc, char **argv) {
SM.AddNewSourceBuffer(F, SMLoc());
+ /// VariableTable - This holds all the current filecheck variables.
+ StringMap<StringRef> VariableTable;
+
// Check that we have all of the expected strings, in order, in the input
// file.
- const char *CurPtr = F->getBufferStart(), *BufferEnd = F->getBufferEnd();
+ StringRef Buffer = F->getBuffer();
+
+ const char *LastMatch = Buffer.data();
- const char *LastMatch = 0;
for (unsigned StrNo = 0, e = CheckStrings.size(); StrNo != e; ++StrNo) {
const CheckString &CheckStr = CheckStrings[StrNo];
+ StringRef SearchFrom = Buffer;
+
// Find StrNo in the file.
- const char *Ptr = FindFixedStringInBuffer(CheckStr.Str, CurPtr, *F);
+ size_t MatchLen = 0;
+ Buffer = Buffer.substr(CheckStr.Pat.Match(Buffer, MatchLen, VariableTable));
// If we didn't find a match, reject the input.
- if (Ptr == BufferEnd) {
- PrintCheckFailed(SM, CheckStr, CurPtr, BufferEnd);
+ if (Buffer.empty()) {
+ PrintCheckFailed(SM, CheckStr, SearchFrom);
return 1;
}
-
+
+ StringRef SkippedRegion(LastMatch, Buffer.data()-LastMatch);
+
// If this check is a "CHECK-NEXT", verify that the previous match was on
// the previous line (i.e. that there is one newline between them).
if (CheckStr.IsCheckNext) {
// Count the number of newlines between the previous match and this one.
- assert(LastMatch && "CHECK-NEXT can't be the first check in a file");
+ assert(LastMatch != F->getBufferStart() &&
+ "CHECK-NEXT can't be the first check in a file");
- unsigned NumNewLines = CountNumNewlinesBetween(LastMatch, Ptr);
+ unsigned NumNewLines = CountNumNewlinesBetween(SkippedRegion);
if (NumNewLines == 0) {
SM.PrintMessage(CheckStr.Loc,
CheckPrefix+"-NEXT: is on the same line as previous match",
"error");
- SM.PrintMessage(SMLoc::getFromPointer(Ptr),
+ SM.PrintMessage(SMLoc::getFromPointer(Buffer.data()),
"'next' match was here", "note");
SM.PrintMessage(SMLoc::getFromPointer(LastMatch),
"previous match was here", "note");
@@ -340,18 +588,36 @@ int main(int argc, char **argv) {
CheckPrefix+
"-NEXT: is not on the line after the previous match",
"error");
- SM.PrintMessage(SMLoc::getFromPointer(Ptr),
+ SM.PrintMessage(SMLoc::getFromPointer(Buffer.data()),
"'next' match was here", "note");
SM.PrintMessage(SMLoc::getFromPointer(LastMatch),
"previous match was here", "note");
return 1;
}
}
+
+ // If this match had "not strings", verify that they don't exist in the
+ // skipped region.
+ for (unsigned ChunkNo = 0, e = CheckStr.NotStrings.size();
+ ChunkNo != e; ++ChunkNo) {
+ size_t MatchLen = 0;
+ size_t Pos = CheckStr.NotStrings[ChunkNo].second.Match(SkippedRegion,
+ MatchLen,
+ VariableTable);
+ if (Pos == StringRef::npos) continue;
+
+ SM.PrintMessage(SMLoc::getFromPointer(LastMatch+Pos),
+ CheckPrefix+"-NOT: string occurred!", "error");
+ SM.PrintMessage(CheckStr.NotStrings[ChunkNo].first,
+ CheckPrefix+"-NOT: pattern specified here", "note");
+ return 1;
+ }
+
- // Otherwise, everything is good. Remember this as the last match and move
- // on to the next one.
- LastMatch = Ptr;
- CurPtr = Ptr + CheckStr.Str.size();
+ // Otherwise, everything is good. Step over the matched text and remember
+ // the position after the match as the end of the last match.
+ Buffer = Buffer.substr(MatchLen);
+ LastMatch = Buffer.data();
}
return 0;
diff --git a/libclamav/c++/llvm/utils/Makefile b/libclamav/c++/llvm/utils/Makefile
index 80204b0..000705e 100644
--- a/libclamav/c++/llvm/utils/Makefile
+++ b/libclamav/c++/llvm/utils/Makefile
@@ -8,7 +8,7 @@
##===----------------------------------------------------------------------===##
LEVEL = ..
-PARALLEL_DIRS := TableGen fpcmp PerfectShuffle FileCheck FileUpdate unittest
+PARALLEL_DIRS := TableGen fpcmp PerfectShuffle FileCheck FileUpdate count not unittest
EXTRA_DIST := cgiplotNLT.pl check-each-file codegen-diff countloc.sh cvsupdate \
DSAclean.py DSAextract.py emacs findsym.pl GenLibDeps.pl \
diff --git a/libclamav/c++/llvm/utils/PerfectShuffle/PerfectShuffle.cpp b/libclamav/c++/llvm/utils/PerfectShuffle/PerfectShuffle.cpp
index 7a42d02..b94a7d3 100644
--- a/libclamav/c++/llvm/utils/PerfectShuffle/PerfectShuffle.cpp
+++ b/libclamav/c++/llvm/utils/PerfectShuffle/PerfectShuffle.cpp
@@ -545,27 +545,27 @@ vext<2> the_vext2("vext2", OP_VEXT2);
vext<3> the_vext3("vext3", OP_VEXT3);
struct vuzpl : public Operator {
- vuzpl() : Operator(0x1032, "vuzpl", OP_VUZPL, 2) {}
+ vuzpl() : Operator(0x0246, "vuzpl", OP_VUZPL, 2) {}
} the_vuzpl;
struct vuzpr : public Operator {
- vuzpr() : Operator(0x4602, "vuzpr", OP_VUZPR, 2) {}
+ vuzpr() : Operator(0x1357, "vuzpr", OP_VUZPR, 2) {}
} the_vuzpr;
struct vzipl : public Operator {
- vzipl() : Operator(0x6273, "vzipl", OP_VZIPL, 2) {}
+ vzipl() : Operator(0x0415, "vzipl", OP_VZIPL, 2) {}
} the_vzipl;
struct vzipr : public Operator {
- vzipr() : Operator(0x4051, "vzipr", OP_VZIPR, 2) {}
+ vzipr() : Operator(0x2637, "vzipr", OP_VZIPR, 2) {}
} the_vzipr;
struct vtrnl : public Operator {
- vtrnl() : Operator(0x5173, "vtrnl", OP_VTRNL, 2) {}
+ vtrnl() : Operator(0x0426, "vtrnl", OP_VTRNL, 2) {}
} the_vtrnl;
struct vtrnr : public Operator {
- vtrnr() : Operator(0x4062, "vtrnr", OP_VTRNR, 2) {}
+ vtrnr() : Operator(0x1537, "vtrnr", OP_VTRNR, 2) {}
} the_vtrnr;
#endif
diff --git a/libclamav/c++/llvm/utils/TableGen/AsmWriterEmitter.cpp b/libclamav/c++/llvm/utils/TableGen/AsmWriterEmitter.cpp
index 1e85ff9..84a647b 100644
--- a/libclamav/c++/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/libclamav/c++/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -15,14 +15,14 @@
#include "AsmWriterEmitter.h"
#include "CodeGenTarget.h"
#include "Record.h"
+#include "StringToOffsetTable.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include <algorithm>
-#include <sstream>
-#include <iostream>
using namespace llvm;
+
static bool isIdentChar(char C) {
return (C >= 'a' && C <= 'z') ||
(C >= 'A' && C <= 'Z') ||
@@ -322,11 +322,9 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, Record *AsmWriter) {
LastEmitted = VarEnd;
}
}
-
- Operands.push_back(
- AsmWriterOperand("EmitComments(*MI);\n",
- AsmWriterOperand::isLiteralStatementOperand));
- AddLiteralString("\\n");
+
+ Operands.push_back(AsmWriterOperand("return;",
+ AsmWriterOperand::isLiteralStatementOperand));
}
/// MatchesAllButOneOp - If this instruction is exactly identical to the
@@ -449,10 +447,6 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
Command = " " + Inst->Operands[0].getCode() + "\n";
- // If this is the last operand, emit a return.
- if (Inst->Operands.size() == 1)
- Command += " return;\n";
-
// Check to see if we already have 'Command' in UniqueOperandCommands.
// If not, add it.
bool FoundIt = false;
@@ -524,14 +518,6 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
// to UniqueOperandCommands and remember that it was consumed.
std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
- // If this is the last operand, emit a return after the code.
- if (FirstInst->Operands.size() == Op+1 &&
- // Don't early-out too soon. Other instructions in this
- // group may have more operands.
- FirstInst->Operands.size() == MaxSize) {
- Command += " return;\n";
- }
-
UniqueOperandCommands[CommandIdx] += Command;
InstOpsUsed[CommandIdx]++;
}
@@ -552,19 +538,16 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
}
-
-void AsmWriterEmitter::run(raw_ostream &O) {
- EmitSourceFileHeader("Assembly Writer Source Fragment", O);
-
+/// EmitPrintInstruction - Generate the code for the "printInstruction" method
+/// implementation.
+void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
CodeGenTarget Target;
Record *AsmWriter = Target.getAsmWriter();
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
-
+
O <<
"/// printInstruction - This method is automatically generated by tablegen\n"
- "/// from the instruction set description. This method returns true if the\n"
- "/// machine instruction was sufficiently described to print it, otherwise\n"
- "/// it returns false.\n"
+ "/// from the instruction set description.\n"
"void " << Target.getName() << ClassName
<< "::printInstruction(const MachineInstr *MI) {\n";
@@ -572,7 +555,8 @@ void AsmWriterEmitter::run(raw_ostream &O) {
for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
E = Target.inst_end(); I != E; ++I)
- if (!I->second.AsmString.empty())
+ if (!I->second.AsmString.empty() &&
+ I->second.TheDef->getName() != "PHI")
Instructions.push_back(AsmWriterInst(I->second, AsmWriter));
// Get the instruction numbering.
@@ -585,10 +569,7 @@ void AsmWriterEmitter::run(raw_ostream &O) {
CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
// Build an aggregate string, and build a table of offsets into it.
- std::map<std::string, unsigned> StringOffset;
- std::string AggregateString;
- AggregateString.push_back(0); // "\0"
- AggregateString.push_back(0); // "\0"
+ StringToOffsetTable StringTable;
/// OpcodeInfo - This encodes the index of the string to use for the first
/// chunk of the output as well as indices used for operand printing.
@@ -600,32 +581,28 @@ void AsmWriterEmitter::run(raw_ostream &O) {
unsigned Idx;
if (AWI == 0) {
// Something not handled by the asmwriter printer.
- Idx = 0;
+ Idx = ~0U;
} else if (AWI->Operands[0].OperandType !=
AsmWriterOperand::isLiteralTextOperand ||
AWI->Operands[0].Str.empty()) {
// Something handled by the asmwriter printer, but with no leading string.
- Idx = 1;
+ Idx = StringTable.GetOrAddStringOffset("");
} else {
- unsigned &Entry = StringOffset[AWI->Operands[0].Str];
- if (Entry == 0) {
- // Add the string to the aggregate if this is the first time found.
- MaxStringIdx = Entry = AggregateString.size();
- std::string Str = AWI->Operands[0].Str;
- UnescapeString(Str);
- AggregateString += Str;
- AggregateString += '\0';
- }
- Idx = Entry;
-
+ std::string Str = AWI->Operands[0].Str;
+ UnescapeString(Str);
+ Idx = StringTable.GetOrAddStringOffset(Str);
+ MaxStringIdx = std::max(MaxStringIdx, Idx);
+
// Nuke the string from the operand list. It is now handled!
AWI->Operands.erase(AWI->Operands.begin());
}
- OpcodeInfo.push_back(Idx);
+
+ // Bias offset by one since we want 0 as a sentinel.
+ OpcodeInfo.push_back(Idx+1);
}
// Figure out how many bits we used for the string index.
- unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+1);
+ unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
// To reduce code size, we compactify common instructions into a few bits
// in the opcode-indexed table.
@@ -633,17 +610,8 @@ void AsmWriterEmitter::run(raw_ostream &O) {
std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
- bool isFirst = true;
while (1) {
std::vector<std::string> UniqueOperandCommands;
-
- // For the first operand check, add a default value for instructions with
- // just opcode strings to use.
- if (isFirst) {
- UniqueOperandCommands.push_back(" return;\n");
- isFirst = false;
- }
-
std::vector<unsigned> InstIdxs;
std::vector<unsigned> NumInstOpsHandled;
FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
@@ -697,36 +665,9 @@ void AsmWriterEmitter::run(raw_ostream &O) {
O << " };\n\n";
// Emit the string itself.
- O << " const char *AsmStrs = \n \"";
- unsigned CharsPrinted = 0;
- EscapeString(AggregateString);
- for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
- if (CharsPrinted > 70) {
- O << "\"\n \"";
- CharsPrinted = 0;
- }
- O << AggregateString[i];
- ++CharsPrinted;
-
- // Print escape sequences all together.
- if (AggregateString[i] == '\\') {
- assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
- if (isdigit(AggregateString[i+1])) {
- assert(isdigit(AggregateString[i+2]) && isdigit(AggregateString[i+3]) &&
- "Expected 3 digit octal escape!");
- O << AggregateString[++i];
- O << AggregateString[++i];
- O << AggregateString[++i];
- CharsPrinted += 3;
- } else {
- O << AggregateString[++i];
- ++CharsPrinted;
- }
- }
- }
- O << "\";\n\n";
-
- O << " processDebugLoc(MI->getDebugLoc());\n\n";
+ O << " const char *AsmStrs = \n";
+ StringTable.EmitString(O);
+ O << ";\n\n";
O << "\n#ifndef NO_ASM_WRITER_BOILERPLATE\n";
@@ -740,6 +681,8 @@ void AsmWriterEmitter::run(raw_ostream &O) {
<< " } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {\n"
<< " printImplicitDef(MI);\n"
<< " return;\n"
+ << " } else if (MI->getOpcode() == TargetInstrInfo::KILL) {\n"
+ << " return;\n"
<< " }\n\n";
O << "\n#endif\n";
@@ -749,7 +692,7 @@ void AsmWriterEmitter::run(raw_ostream &O) {
O << " // Emit the opcode for the instruction.\n"
<< " unsigned Bits = OpInfo[MI->getOpcode()];\n"
<< " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
- << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ");\n\n";
+ << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
// Output the table driven operand information.
BitsLeft = 32-AsmStrBits;
@@ -805,6 +748,11 @@ void AsmWriterEmitter::run(raw_ostream &O) {
// elements in the vector.
std::reverse(Instructions.begin(), Instructions.end());
+
+ // Now that we've emitted all of the operand info that fit into 32 bits, emit
+ // information for those instructions that are left. This is a less dense
+ // encoding, but we expect the main 32-bit table to handle the majority of
+ // instructions.
if (!Instructions.empty()) {
// Find the opcode # of inline asm.
O << " switch (MI->getOpcode()) {\n";
@@ -818,3 +766,55 @@ void AsmWriterEmitter::run(raw_ostream &O) {
O << " return;\n";
O << "}\n";
}
+
+
+void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
+ CodeGenTarget Target;
+ Record *AsmWriter = Target.getAsmWriter();
+ std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
+ const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
+
+ StringToOffsetTable StringTable;
+ O <<
+ "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
+ "/// from the register set description. This returns the assembler name\n"
+ "/// for the specified register.\n"
+ "const char *" << Target.getName() << ClassName
+ << "::getRegisterName(unsigned RegNo) {\n"
+ << " assert(RegNo && RegNo < " << (Registers.size()+1)
+ << " && \"Invalid register number!\");\n"
+ << "\n"
+ << " static const unsigned RegAsmOffset[] = {";
+ for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
+ const CodeGenRegister &Reg = Registers[i];
+
+ std::string AsmName = Reg.TheDef->getValueAsString("AsmName");
+ if (AsmName.empty())
+ AsmName = Reg.getName();
+
+
+ if ((i % 14) == 0)
+ O << "\n ";
+
+ O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
+ }
+ O << "0\n"
+ << " };\n"
+ << "\n";
+
+ O << " const char *AsmStrs =\n";
+ StringTable.EmitString(O);
+ O << ";\n";
+
+ O << " return AsmStrs+RegAsmOffset[RegNo-1];\n"
+ << "}\n";
+}
+
+
+void AsmWriterEmitter::run(raw_ostream &O) {
+ EmitSourceFileHeader("Assembly Writer Source Fragment", O);
+
+ EmitPrintInstruction(O);
+ EmitGetRegisterName(O);
+}
+
diff --git a/libclamav/c++/llvm/utils/TableGen/AsmWriterEmitter.h b/libclamav/c++/llvm/utils/TableGen/AsmWriterEmitter.h
index 75e6996..7862caa 100644
--- a/libclamav/c++/llvm/utils/TableGen/AsmWriterEmitter.h
+++ b/libclamav/c++/llvm/utils/TableGen/AsmWriterEmitter.h
@@ -35,6 +35,9 @@ namespace llvm {
void run(raw_ostream &o);
private:
+ void EmitPrintInstruction(raw_ostream &o);
+ void EmitGetRegisterName(raw_ostream &o);
+
AsmWriterInst *getAsmWriterInstByID(unsigned ID) const {
assert(ID < NumberedInstructions.size());
std::map<const CodeGenInstruction*, AsmWriterInst*>::const_iterator I =
diff --git a/libclamav/c++/llvm/utils/TableGen/CodeEmitterGen.cpp b/libclamav/c++/llvm/utils/TableGen/CodeEmitterGen.cpp
index 6ab9c9b..7e6c769 100644
--- a/libclamav/c++/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/libclamav/c++/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -29,7 +29,7 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
R->getName() == "DBG_LABEL" ||
R->getName() == "EH_LABEL" ||
R->getName() == "GC_LABEL" ||
- R->getName() == "DECLARE" ||
+ R->getName() == "KILL" ||
R->getName() == "EXTRACT_SUBREG" ||
R->getName() == "INSERT_SUBREG" ||
R->getName() == "IMPLICIT_DEF" ||
@@ -106,7 +106,7 @@ void CodeEmitterGen::run(raw_ostream &o) {
R->getName() == "DBG_LABEL" ||
R->getName() == "EH_LABEL" ||
R->getName() == "GC_LABEL" ||
- R->getName() == "DECLARE" ||
+ R->getName() == "KILL" ||
R->getName() == "EXTRACT_SUBREG" ||
R->getName() == "INSERT_SUBREG" ||
R->getName() == "IMPLICIT_DEF" ||
@@ -144,7 +144,7 @@ void CodeEmitterGen::run(raw_ostream &o) {
InstName == "DBG_LABEL"||
InstName == "EH_LABEL"||
InstName == "GC_LABEL"||
- InstName == "DECLARE"||
+ InstName == "KILL"||
InstName == "EXTRACT_SUBREG" ||
InstName == "INSERT_SUBREG" ||
InstName == "IMPLICIT_DEF" ||
diff --git a/libclamav/c++/llvm/utils/TableGen/CodeGenInstruction.cpp b/libclamav/c++/llvm/utils/TableGen/CodeGenInstruction.cpp
index b7968a0..d421fd0 100644
--- a/libclamav/c++/llvm/utils/TableGen/CodeGenInstruction.cpp
+++ b/libclamav/c++/llvm/utils/TableGen/CodeGenInstruction.cpp
@@ -101,6 +101,8 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
mayHaveSideEffects = R->getValueAsBit("mayHaveSideEffects");
neverHasSideEffects = R->getValueAsBit("neverHasSideEffects");
isAsCheapAsAMove = R->getValueAsBit("isAsCheapAsAMove");
+ hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq");
+ hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq");
hasOptionalDef = false;
isVariadic = false;
diff --git a/libclamav/c++/llvm/utils/TableGen/CodeGenInstruction.h b/libclamav/c++/llvm/utils/TableGen/CodeGenInstruction.h
index f4afd5e..04506e9 100644
--- a/libclamav/c++/llvm/utils/TableGen/CodeGenInstruction.h
+++ b/libclamav/c++/llvm/utils/TableGen/CodeGenInstruction.h
@@ -106,6 +106,8 @@ namespace llvm {
bool mayHaveSideEffects;
bool neverHasSideEffects;
bool isAsCheapAsAMove;
+ bool hasExtraSrcRegAllocReq;
+ bool hasExtraDefRegAllocReq;
/// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar",
/// where $foo is a whole operand and $foo.bar refers to a suboperand.
diff --git a/libclamav/c++/llvm/utils/TableGen/CodeGenTarget.cpp b/libclamav/c++/llvm/utils/TableGen/CodeGenTarget.cpp
index a3ec8dc..0edca73 100644
--- a/libclamav/c++/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/libclamav/c++/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -308,9 +308,9 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
if (I == Instructions.end()) throw "Could not find 'GC_LABEL' instruction!";
const CodeGenInstruction *GC_LABEL = &I->second;
- I = getInstructions().find("DECLARE");
- if (I == Instructions.end()) throw "Could not find 'DECLARE' instruction!";
- const CodeGenInstruction *DECLARE = &I->second;
+ I = getInstructions().find("KILL");
+ if (I == Instructions.end()) throw "Could not find 'KILL' instruction!";
+ const CodeGenInstruction *KILL = &I->second;
I = getInstructions().find("EXTRACT_SUBREG");
if (I == Instructions.end())
@@ -343,7 +343,7 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
NumberedInstructions.push_back(DBG_LABEL);
NumberedInstructions.push_back(EH_LABEL);
NumberedInstructions.push_back(GC_LABEL);
- NumberedInstructions.push_back(DECLARE);
+ NumberedInstructions.push_back(KILL);
NumberedInstructions.push_back(EXTRACT_SUBREG);
NumberedInstructions.push_back(INSERT_SUBREG);
NumberedInstructions.push_back(IMPLICIT_DEF);
@@ -355,7 +355,7 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
&II->second != DBG_LABEL &&
&II->second != EH_LABEL &&
&II->second != GC_LABEL &&
- &II->second != DECLARE &&
+ &II->second != KILL &&
&II->second != EXTRACT_SUBREG &&
&II->second != INSERT_SUBREG &&
&II->second != IMPLICIT_DEF &&
diff --git a/libclamav/c++/llvm/utils/TableGen/DAGISelEmitter.cpp b/libclamav/c++/llvm/utils/TableGen/DAGISelEmitter.cpp
index 95df746..dcf64e4 100644
--- a/libclamav/c++/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/libclamav/c++/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -784,7 +784,7 @@ public:
EmitResultCode(TreePatternNode *N, std::vector<Record*> DstRegs,
bool InFlagDecled, bool ResNodeDecled,
bool LikeLeaf = false, bool isRoot = false) {
- // List of arguments of getTargetNode() or SelectNodeTo().
+ // List of arguments of getMachineNode() or SelectNodeTo().
std::vector<std::string> NodeOps;
// This is something selected from the pattern we matched.
if (!N->getName().empty()) {
@@ -1089,7 +1089,7 @@ public:
std::string Code = "Opc" + utostr(OpcNo);
if (!isRoot || (InputHasChain && !NodeHasChain))
- // For call to "getTargetNode()".
+ // For call to "getMachineNode()".
Code += ", N.getDebugLoc()";
emitOpcode(II.Namespace + "::" + II.TheDef->getName());
@@ -1135,24 +1135,18 @@ public:
emitCode("}");
}
- // Generate MemOperandSDNodes nodes for each memory accesses covered by
+ // Populate MemRefs with entries for each memory accesses covered by
// this pattern.
- if (II.mayLoad | II.mayStore) {
- std::vector<std::string>::const_iterator mi, mie;
- for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
- std::string LSIName = "LSI_" + *mi;
- emitCode("SDValue " + LSIName + " = "
- "CurDAG->getMemOperand(cast<MemSDNode>(" +
- *mi + ")->getMemOperand());");
- if (GenDebug) {
- emitCode("CurDAG->setSubgraphColor(" + LSIName +".getNode(), \"yellow\");");
- emitCode("CurDAG->setSubgraphColor(" + LSIName +".getNode(), \"black\");");
- }
- if (IsVariadic)
- emitCode("Ops" + utostr(OpsNo) + ".push_back(" + LSIName + ");");
- else
- AllOps.push_back(LSIName);
- }
+ if (isRoot && !LSI.empty()) {
+ std::string MemRefs = "MemRefs" + utostr(OpsNo);
+ emitCode("MachineSDNode::mmo_iterator " + MemRefs + " = "
+ "MF->allocateMemRefsArray(" + utostr(LSI.size()) + ");");
+ for (unsigned i = 0, e = LSI.size(); i != e; ++i)
+ emitCode(MemRefs + "[" + utostr(i) + "] = "
+ "cast<MemSDNode>(" + LSI[i] + ")->getMemOperand();");
+ After.push_back("cast<MachineSDNode>(ResNode)->setMemRefs(" +
+ MemRefs + ", " + MemRefs + " + " + utostr(LSI.size()) +
+ ");");
}
if (NodeHasChain) {
@@ -1303,7 +1297,7 @@ public:
// would leave users of the chain dangling.
//
if (!isRoot || (InputHasChain && !NodeHasChain)) {
- Code = "CurDAG->getTargetNode(" + Code;
+ Code = "CurDAG->getMachineNode(" + Code;
} else {
Code = "CurDAG->SelectNodeTo(N.getNode(), " + Code;
}
@@ -1776,7 +1770,7 @@ void DAGISelEmitter::EmitInstructionSelector(raw_ostream &OS) {
CallerCode += ", " + TargetOpcodes[j];
}
for (unsigned j = 0, e = TargetVTs.size(); j != e; ++j) {
- CalleeCode += ", EVT VT" + utostr(j);
+ CalleeCode += ", MVT::SimpleValueType VT" + utostr(j);
CallerCode += ", " + TargetVTs[j];
}
for (std::set<std::string>::iterator
@@ -1965,7 +1959,6 @@ void DAGISelEmitter::EmitInstructionSelector(raw_ostream &OS) {
<< " assert(!N.isMachineOpcode() && \"Node already selected!\");\n"
<< " break;\n"
<< " case ISD::EntryToken: // These nodes remain the same.\n"
- << " case ISD::MEMOPERAND:\n"
<< " case ISD::BasicBlock:\n"
<< " case ISD::Register:\n"
<< " case ISD::HANDLENODE:\n"
diff --git a/libclamav/c++/llvm/utils/TableGen/FastISelEmitter.cpp b/libclamav/c++/llvm/utils/TableGen/FastISelEmitter.cpp
index bf92a9a..277640d 100644
--- a/libclamav/c++/llvm/utils/TableGen/FastISelEmitter.cpp
+++ b/libclamav/c++/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -216,7 +216,6 @@ public:
explicit FastISelMap(std::string InstNS);
void CollectPatterns(CodeGenDAGPatterns &CGP);
- void PrintClass(raw_ostream &OS);
void PrintFunctionDefinitions(raw_ostream &OS);
};
diff --git a/libclamav/c++/llvm/utils/TableGen/InstrInfoEmitter.cpp b/libclamav/c++/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 533ff9f..3a104ea 100644
--- a/libclamav/c++/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/libclamav/c++/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -280,6 +280,8 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
if (Inst.isVariadic) OS << "|(1<<TID::Variadic)";
if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)";
if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)";
+ if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<TID::ExtraSrcRegAllocReq)";
+ if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<TID::ExtraDefRegAllocReq)";
OS << ", 0";
// Emit all of the target-specific flags...
@@ -339,7 +341,7 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
R->getName() != "DBG_LABEL" &&
R->getName() != "EH_LABEL" &&
R->getName() != "GC_LABEL" &&
- R->getName() != "DECLARE" &&
+ R->getName() != "KILL" &&
R->getName() != "EXTRACT_SUBREG" &&
R->getName() != "INSERT_SUBREG" &&
R->getName() != "IMPLICIT_DEF" &&
diff --git a/libclamav/c++/llvm/utils/TableGen/LLVMCConfigurationEmitter.cpp b/libclamav/c++/llvm/utils/TableGen/LLVMCConfigurationEmitter.cpp
index 6bade9b..f9a447a 100644
--- a/libclamav/c++/llvm/utils/TableGen/LLVMCConfigurationEmitter.cpp
+++ b/libclamav/c++/llvm/utils/TableGen/LLVMCConfigurationEmitter.cpp
@@ -39,10 +39,11 @@ typedef std::vector<std::string> StrVector;
//===----------------------------------------------------------------------===//
/// Constants
-// Indentation strings.
-const char * Indent1 = " ";
-const char * Indent2 = " ";
-const char * Indent3 = " ";
+// Indentation.
+unsigned TabWidth = 4;
+unsigned Indent1 = TabWidth*1;
+unsigned Indent2 = TabWidth*2;
+unsigned Indent3 = TabWidth*3;
// Default help string.
const char * DefaultHelpString = "NO HELP MESSAGE PROVIDED";
@@ -89,7 +90,7 @@ void checkNumberOfArguments (const DagInit* d, unsigned min_arguments) {
// isDagEmpty - is this DAG marked with an empty marker?
bool isDagEmpty (const DagInit* d) {
- return d->getOperator()->getAsString() == "empty";
+ return d->getOperator()->getAsString() == "empty_dag_marker";
}
// EscapeVariableName - Escape commas and other symbols not allowed
@@ -975,8 +976,22 @@ void CheckForSuperfluousOptions (const RecordVector& Edges,
}
}
-/// EmitCaseTest1Arg - Helper function used by
-/// EmitCaseConstructHandler.
+/// EmitCaseTest0Args - Helper function used by EmitCaseConstructHandler().
+bool EmitCaseTest0Args(const std::string& TestName, raw_ostream& O) {
+ if (TestName == "single_input_file") {
+ O << "InputFilenames.size() == 1";
+ return true;
+ }
+ else if (TestName == "multiple_input_files") {
+ O << "InputFilenames.size() > 1";
+ return true;
+ }
+
+ return false;
+}
+
+
+/// EmitCaseTest1Arg - Helper function used by EmitCaseConstructHandler().
bool EmitCaseTest1Arg(const std::string& TestName,
const DagInit& d,
const OptionDescriptions& OptDescs,
@@ -1020,11 +1035,10 @@ bool EmitCaseTest1Arg(const std::string& TestName,
return false;
}
-/// EmitCaseTest2Args - Helper function used by
-/// EmitCaseConstructHandler.
+/// EmitCaseTest2Args - Helper function used by EmitCaseConstructHandler().
bool EmitCaseTest2Args(const std::string& TestName,
const DagInit& d,
- const char* IndentLevel,
+ unsigned IndentLevel,
const OptionDescriptions& OptDescs,
raw_ostream& O) {
checkNumberOfArguments(&d, 2);
@@ -1042,8 +1056,9 @@ bool EmitCaseTest2Args(const std::string& TestName,
if (!OptDesc.isList())
throw OptName + ": incorrect option type - should be a list!";
const std::string& VarName = OptDesc.GenVariableName();
- O << "std::find(" << VarName << ".begin(),\n"
- << IndentLevel << Indent1 << VarName << ".end(), \""
+ O << "std::find(" << VarName << ".begin(),\n";
+ O.indent(IndentLevel + Indent1)
+ << VarName << ".end(), \""
<< OptArg << "\") != " << VarName << ".end()";
return true;
}
@@ -1053,29 +1068,42 @@ bool EmitCaseTest2Args(const std::string& TestName,
// Forward declaration.
// EmitLogicalOperationTest and EmitCaseTest are mutually recursive.
-void EmitCaseTest(const DagInit& d, const char* IndentLevel,
+void EmitCaseTest(const DagInit& d, unsigned IndentLevel,
const OptionDescriptions& OptDescs,
raw_ostream& O);
/// EmitLogicalOperationTest - Helper function used by
/// EmitCaseConstructHandler.
void EmitLogicalOperationTest(const DagInit& d, const char* LogicOp,
- const char* IndentLevel,
+ unsigned IndentLevel,
const OptionDescriptions& OptDescs,
raw_ostream& O) {
O << '(';
for (unsigned j = 0, NumArgs = d.getNumArgs(); j < NumArgs; ++j) {
const DagInit& InnerTest = InitPtrToDag(d.getArg(j));
EmitCaseTest(InnerTest, IndentLevel, OptDescs, O);
- if (j != NumArgs - 1)
- O << ")\n" << IndentLevel << Indent1 << ' ' << LogicOp << " (";
- else
+ if (j != NumArgs - 1) {
+ O << ")\n";
+ O.indent(IndentLevel + Indent1) << ' ' << LogicOp << " (";
+ }
+ else {
O << ')';
+ }
}
}
+void EmitLogicalNot(const DagInit& d, unsigned IndentLevel,
+ const OptionDescriptions& OptDescs, raw_ostream& O)
+{
+ checkNumberOfArguments(&d, 1);
+ const DagInit& InnerTest = InitPtrToDag(d.getArg(0));
+ O << "! (";
+ EmitCaseTest(InnerTest, IndentLevel, OptDescs, O);
+ O << ")";
+}
+
/// EmitCaseTest - Helper function used by EmitCaseConstructHandler.
-void EmitCaseTest(const DagInit& d, const char* IndentLevel,
+void EmitCaseTest(const DagInit& d, unsigned IndentLevel,
const OptionDescriptions& OptDescs,
raw_ostream& O) {
const std::string& TestName = d.getOperator()->getAsString();
@@ -1084,6 +1112,10 @@ void EmitCaseTest(const DagInit& d, const char* IndentLevel,
EmitLogicalOperationTest(d, "&&", IndentLevel, OptDescs, O);
else if (TestName == "or")
EmitLogicalOperationTest(d, "||", IndentLevel, OptDescs, O);
+ else if (TestName == "not")
+ EmitLogicalNot(d, IndentLevel, OptDescs, O);
+ else if (EmitCaseTest0Args(TestName, O))
+ return;
else if (EmitCaseTest1Arg(TestName, d, OptDescs, O))
return;
else if (EmitCaseTest2Args(TestName, d, IndentLevel, OptDescs, O))
@@ -1095,9 +1127,9 @@ void EmitCaseTest(const DagInit& d, const char* IndentLevel,
// Emit code that handles the 'case' construct.
// Takes a function object that should emit code for every case clause.
// Callback's type is
-// void F(Init* Statement, const char* IndentLevel, raw_ostream& O).
+// void F(Init* Statement, unsigned IndentLevel, raw_ostream& O).
template <typename F>
-void EmitCaseConstructHandler(const Init* Dag, const char* IndentLevel,
+void EmitCaseConstructHandler(const Init* Dag, unsigned IndentLevel,
F Callback, bool EmitElseIf,
const OptionDescriptions& OptDescs,
raw_ostream& O) {
@@ -1119,10 +1151,10 @@ void EmitCaseConstructHandler(const Init* Dag, const char* IndentLevel,
if (i+2 != numArgs)
throw std::string("The 'default' clause should be the last in the"
"'case' construct!");
- O << IndentLevel << "else {\n";
+ O.indent(IndentLevel) << "else {\n";
}
else {
- O << IndentLevel << ((i != 0 && EmitElseIf) ? "else if (" : "if (");
+ O.indent(IndentLevel) << ((i != 0 && EmitElseIf) ? "else if (" : "if (");
EmitCaseTest(Test, IndentLevel, OptDescs, O);
O << ") {\n";
}
@@ -1137,13 +1169,13 @@ void EmitCaseConstructHandler(const Init* Dag, const char* IndentLevel,
const DagInit* nd = dynamic_cast<DagInit*>(arg);
if (nd && (nd->getOperator()->getAsString() == "case")) {
// Handle the nested 'case'.
- EmitCaseConstructHandler(nd, (std::string(IndentLevel) + Indent1).c_str(),
+ EmitCaseConstructHandler(nd, (IndentLevel + Indent1),
Callback, EmitElseIf, OptDescs, O);
}
else {
- Callback(arg, (std::string(IndentLevel) + Indent1).c_str(), O);
+ Callback(arg, (IndentLevel + Indent1), O);
}
- O << IndentLevel << "}\n";
+ O.indent(IndentLevel) << "}\n";
}
}
@@ -1297,7 +1329,7 @@ StrVector::const_iterator SubstituteSpecialCommands
/// EmitCmdLineVecFill - Emit code that fills in the command line
/// vector. Helper function used by EmitGenerateActionMethod().
void EmitCmdLineVecFill(const Init* CmdLine, const std::string& ToolName,
- bool IsJoin, const char* IndentLevel,
+ bool IsJoin, unsigned IndentLevel,
raw_ostream& O) {
StrVector StrVec;
TokenizeCmdline(InitPtrToString(CmdLine), StrVec);
@@ -1323,16 +1355,18 @@ void EmitCmdLineVecFill(const Init* CmdLine, const std::string& ToolName,
for (; I != E; ++I) {
const std::string& cmd = *I;
assert(!cmd.empty());
- O << IndentLevel;
+ O.indent(IndentLevel);
if (cmd.at(0) == '$') {
if (cmd == "$INFILE") {
- if (IsJoin)
+ if (IsJoin) {
O << "for (PathVector::const_iterator B = inFiles.begin()"
- << ", E = inFiles.end();\n"
- << IndentLevel << "B != E; ++B)\n"
- << IndentLevel << Indent1 << "vec.push_back(B->str());\n";
- else
+ << ", E = inFiles.end();\n";
+ O.indent(IndentLevel) << "B != E; ++B)\n";
+ O.indent(IndentLevel + Indent1) << "vec.push_back(B->str());\n";
+ }
+ else {
O << "vec.push_back(inFile.str());\n";
+ }
}
else if (cmd == "$OUTFILE") {
O << "vec.push_back(out_file);\n";
@@ -1347,7 +1381,7 @@ void EmitCmdLineVecFill(const Init* CmdLine, const std::string& ToolName,
O << "vec.push_back(\"" << cmd << "\");\n";
}
}
- O << IndentLevel << "cmd = ";
+ O.indent(IndentLevel) << "cmd = ";
if (StrVec[0][0] == '$')
SubstituteSpecialCommands(StrVec.begin(), StrVec.end(), O);
@@ -1366,11 +1400,10 @@ class EmitCmdLineVecFillCallback {
EmitCmdLineVecFillCallback(bool J, const std::string& TN)
: IsJoin(J), ToolName(TN) {}
- void operator()(const Init* Statement, const char* IndentLevel,
+ void operator()(const Init* Statement, unsigned IndentLevel,
raw_ostream& O) const
{
- EmitCmdLineVecFill(Statement, ToolName, IsJoin,
- IndentLevel, O);
+ EmitCmdLineVecFill(Statement, ToolName, IsJoin, IndentLevel, O);
}
};
@@ -1378,53 +1411,56 @@ class EmitCmdLineVecFillCallback {
/// implement EmitActionHandler. Emits code for
/// handling the (forward) and (forward_as) option properties.
void EmitForwardOptionPropertyHandlingCode (const OptionDescription& D,
- const char* Indent,
+ unsigned IndentLevel,
const std::string& NewName,
raw_ostream& O) {
const std::string& Name = NewName.empty()
? ("-" + D.Name)
: NewName;
+ unsigned IndentLevel1 = IndentLevel + Indent1;
switch (D.Type) {
case OptionType::Switch:
- O << Indent << "vec.push_back(\"" << Name << "\");\n";
+ O.indent(IndentLevel) << "vec.push_back(\"" << Name << "\");\n";
break;
case OptionType::Parameter:
- O << Indent << "vec.push_back(\"" << Name << "\");\n";
- O << Indent << "vec.push_back(" << D.GenVariableName() << ");\n";
+ O.indent(IndentLevel) << "vec.push_back(\"" << Name << "\");\n";
+ O.indent(IndentLevel) << "vec.push_back(" << D.GenVariableName() << ");\n";
break;
case OptionType::Prefix:
- O << Indent << "vec.push_back(\"" << Name << "\" + "
- << D.GenVariableName() << ");\n";
+ O.indent(IndentLevel) << "vec.push_back(\"" << Name << "\" + "
+ << D.GenVariableName() << ");\n";
break;
case OptionType::PrefixList:
- O << Indent << "for (" << D.GenTypeDeclaration()
- << "::iterator B = " << D.GenVariableName() << ".begin(),\n"
- << Indent << "E = " << D.GenVariableName() << ".end(); B != E;) {\n"
- << Indent << Indent1 << "vec.push_back(\"" << Name << "\" + "
- << "*B);\n"
- << Indent << Indent1 << "++B;\n";
+ O.indent(IndentLevel)
+ << "for (" << D.GenTypeDeclaration()
+ << "::iterator B = " << D.GenVariableName() << ".begin(),\n";
+ O.indent(IndentLevel)
+ << "E = " << D.GenVariableName() << ".end(); B != E;) {\n";
+ O.indent(IndentLevel1) << "vec.push_back(\"" << Name << "\" + " << "*B);\n";
+ O.indent(IndentLevel1) << "++B;\n";
for (int i = 1, j = D.MultiVal; i < j; ++i) {
- O << Indent << Indent1 << "vec.push_back(*B);\n"
- << Indent << Indent1 << "++B;\n";
+ O.indent(IndentLevel1) << "vec.push_back(*B);\n";
+ O.indent(IndentLevel1) << "++B;\n";
}
- O << Indent << "}\n";
+ O.indent(IndentLevel) << "}\n";
break;
case OptionType::ParameterList:
- O << Indent << "for (" << D.GenTypeDeclaration()
- << "::iterator B = " << D.GenVariableName() << ".begin(),\n"
- << Indent << "E = " << D.GenVariableName()
- << ".end() ; B != E;) {\n"
- << Indent << Indent1 << "vec.push_back(\"" << Name << "\");\n";
+ O.indent(IndentLevel)
+ << "for (" << D.GenTypeDeclaration() << "::iterator B = "
+ << D.GenVariableName() << ".begin(),\n";
+ O.indent(IndentLevel) << "E = " << D.GenVariableName()
+ << ".end() ; B != E;) {\n";
+ O.indent(IndentLevel1) << "vec.push_back(\"" << Name << "\");\n";
for (int i = 0, j = D.MultiVal; i < j; ++i) {
- O << Indent << Indent1 << "vec.push_back(*B);\n"
- << Indent << Indent1 << "++B;\n";
+ O.indent(IndentLevel1) << "vec.push_back(*B);\n";
+ O.indent(IndentLevel1) << "++B;\n";
}
- O << Indent << "}\n";
+ O.indent(IndentLevel) << "}\n";
break;
case OptionType::Alias:
default:
@@ -1438,7 +1474,7 @@ void EmitForwardOptionPropertyHandlingCode (const OptionDescription& D,
class EmitActionHandler {
const OptionDescriptions& OptDescs;
- void processActionDag(const Init* Statement, const char* IndentLevel,
+ void processActionDag(const Init* Statement, unsigned IndentLevel,
raw_ostream& O) const
{
const DagInit& Dag = InitPtrToDag(Statement);
@@ -1452,10 +1488,10 @@ class EmitActionHandler {
for (StrVector::const_iterator B = Out.begin(), E = Out.end();
B != E; ++B)
- O << IndentLevel << "vec.push_back(\"" << *B << "\");\n";
+ O.indent(IndentLevel) << "vec.push_back(\"" << *B << "\");\n";
}
else if (ActionName == "error") {
- O << IndentLevel << "throw std::runtime_error(\"" <<
+ O.indent(IndentLevel) << "throw std::runtime_error(\"" <<
(Dag.getNumArgs() >= 1 ? InitPtrToString(Dag.getArg(0))
: "Unknown error!")
<< "\");\n";
@@ -1476,10 +1512,10 @@ class EmitActionHandler {
else if (ActionName == "output_suffix") {
checkNumberOfArguments(&Dag, 1);
const std::string& OutSuf = InitPtrToString(Dag.getArg(0));
- O << IndentLevel << "output_suffix = \"" << OutSuf << "\";\n";
+ O.indent(IndentLevel) << "output_suffix = \"" << OutSuf << "\";\n";
}
else if (ActionName == "stop_compilation") {
- O << IndentLevel << "stop_compilation = true;\n";
+ O.indent(IndentLevel) << "stop_compilation = true;\n";
}
else if (ActionName == "unpack_values") {
checkNumberOfArguments(&Dag, 1);
@@ -1490,15 +1526,17 @@ class EmitActionHandler {
throw std::string("Can't use unpack_values with multi-valued options!");
if (D.isList()) {
- O << IndentLevel << "for (" << D.GenTypeDeclaration()
- << "::iterator B = " << D.GenVariableName() << ".begin(),\n"
- << IndentLevel << "E = " << D.GenVariableName()
- << ".end(); B != E; ++B)\n"
- << IndentLevel << Indent1 << "llvm::SplitString(*B, vec, \",\");\n";
+ O.indent(IndentLevel)
+ << "for (" << D.GenTypeDeclaration()
+ << "::iterator B = " << D.GenVariableName() << ".begin(),\n";
+ O.indent(IndentLevel)
+ << "E = " << D.GenVariableName() << ".end(); B != E; ++B)\n";
+ O.indent(IndentLevel + Indent1)
+ << "llvm::SplitString(*B, vec, \",\");\n";
}
else if (D.isParameter()){
- O << Indent3 << "llvm::SplitString("
- << D.GenVariableName() << ", vec, \",\");\n";
+ O.indent(IndentLevel) << "llvm::SplitString("
+ << D.GenVariableName() << ", vec, \",\");\n";
}
else {
throw "Option '" + D.Name +
@@ -1513,7 +1551,7 @@ class EmitActionHandler {
EmitActionHandler(const OptionDescriptions& OD)
: OptDescs(OD) {}
- void operator()(const Init* Statement, const char* IndentLevel,
+ void operator()(const Init* Statement, unsigned IndentLevel,
raw_ostream& O) const
{
if (typeid(*Statement) == typeid(ListInit)) {
@@ -1534,29 +1572,31 @@ void EmitGenerateActionMethod (const ToolDescription& D,
const OptionDescriptions& OptDescs,
bool IsJoin, raw_ostream& O) {
if (IsJoin)
- O << Indent1 << "Action GenerateAction(const PathVector& inFiles,\n";
+ O.indent(Indent1) << "Action GenerateAction(const PathVector& inFiles,\n";
else
- O << Indent1 << "Action GenerateAction(const sys::Path& inFile,\n";
-
- O << Indent2 << "bool HasChildren,\n"
- << Indent2 << "const llvm::sys::Path& TempDir,\n"
- << Indent2 << "const InputLanguagesSet& InLangs,\n"
- << Indent2 << "const LanguageMap& LangMap) const\n"
- << Indent1 << "{\n"
- << Indent2 << "std::string cmd;\n"
- << Indent2 << "std::vector<std::string> vec;\n"
- << Indent2 << "bool stop_compilation = !HasChildren;\n"
- << Indent2 << "const char* output_suffix = \"" << D.OutputSuffix << "\";\n"
- << Indent2 << "std::string out_file;\n\n";
+ O.indent(Indent1) << "Action GenerateAction(const sys::Path& inFile,\n";
+
+ O.indent(Indent2) << "bool HasChildren,\n";
+ O.indent(Indent2) << "const llvm::sys::Path& TempDir,\n";
+ O.indent(Indent2) << "const InputLanguagesSet& InLangs,\n";
+ O.indent(Indent2) << "const LanguageMap& LangMap) const\n";
+ O.indent(Indent1) << "{\n";
+ O.indent(Indent2) << "std::string cmd;\n";
+ O.indent(Indent2) << "std::vector<std::string> vec;\n";
+ O.indent(Indent2) << "bool stop_compilation = !HasChildren;\n";
+ O.indent(Indent2) << "const char* output_suffix = \""
+ << D.OutputSuffix << "\";\n";
+ O.indent(Indent2) << "std::string out_file;\n\n";
// For every understood option, emit handling code.
if (D.Actions)
EmitCaseConstructHandler(D.Actions, Indent2, EmitActionHandler(OptDescs),
false, OptDescs, O);
- O << '\n' << Indent2
- << "out_file = OutFilename(" << (IsJoin ? "sys::Path(),\n" : "inFile,\n")
- << Indent3 << "TempDir, stop_compilation, output_suffix).str();\n\n";
+ O << '\n';
+ O.indent(Indent2)
+ << "out_file = OutFilename(" << (IsJoin ? "sys::Path(),\n" : "inFile,\n");
+ O.indent(Indent3) << "TempDir, stop_compilation, output_suffix).str();\n\n";
// cmd_line is either a string or a 'case' construct.
if (!D.CmdLine)
@@ -1570,14 +1610,15 @@ void EmitGenerateActionMethod (const ToolDescription& D,
// Handle the Sink property.
if (D.isSink()) {
- O << Indent2 << "if (!" << SinkOptionName << ".empty()) {\n"
- << Indent3 << "vec.insert(vec.end(), "
- << SinkOptionName << ".begin(), " << SinkOptionName << ".end());\n"
- << Indent2 << "}\n";
+ O.indent(Indent2) << "if (!" << SinkOptionName << ".empty()) {\n";
+ O.indent(Indent3) << "vec.insert(vec.end(), "
+ << SinkOptionName << ".begin(), " << SinkOptionName
+ << ".end());\n";
+ O.indent(Indent2) << "}\n";
}
- O << Indent2 << "return Action(cmd, vec, stop_compilation, out_file);\n"
- << Indent1 << "}\n\n";
+ O.indent(Indent2) << "return Action(cmd, vec, stop_compilation, out_file);\n";
+ O.indent(Indent1) << "}\n\n";
}
/// EmitGenerateActionMethods - Emit two GenerateAction() methods for
@@ -1585,18 +1626,20 @@ void EmitGenerateActionMethod (const ToolDescription& D,
void EmitGenerateActionMethods (const ToolDescription& ToolDesc,
const OptionDescriptions& OptDescs,
raw_ostream& O) {
- if (!ToolDesc.isJoin())
- O << Indent1 << "Action GenerateAction(const PathVector& inFiles,\n"
- << Indent2 << "bool HasChildren,\n"
- << Indent2 << "const llvm::sys::Path& TempDir,\n"
- << Indent2 << "const InputLanguagesSet& InLangs,\n"
- << Indent2 << "const LanguageMap& LangMap) const\n"
- << Indent1 << "{\n"
- << Indent2 << "throw std::runtime_error(\"" << ToolDesc.Name
- << " is not a Join tool!\");\n"
- << Indent1 << "}\n\n";
- else
+ if (!ToolDesc.isJoin()) {
+ O.indent(Indent1) << "Action GenerateAction(const PathVector& inFiles,\n";
+ O.indent(Indent2) << "bool HasChildren,\n";
+ O.indent(Indent2) << "const llvm::sys::Path& TempDir,\n";
+ O.indent(Indent2) << "const InputLanguagesSet& InLangs,\n";
+ O.indent(Indent2) << "const LanguageMap& LangMap) const\n";
+ O.indent(Indent1) << "{\n";
+ O.indent(Indent2) << "throw std::runtime_error(\"" << ToolDesc.Name
+ << " is not a Join tool!\");\n";
+ O.indent(Indent1) << "}\n\n";
+ }
+ else {
EmitGenerateActionMethod(ToolDesc, OptDescs, true, O);
+ }
EmitGenerateActionMethod(ToolDesc, OptDescs, false, O);
}
@@ -1604,34 +1647,34 @@ void EmitGenerateActionMethods (const ToolDescription& ToolDesc,
/// EmitInOutLanguageMethods - Emit the [Input,Output]Language()
/// methods for a given Tool class.
void EmitInOutLanguageMethods (const ToolDescription& D, raw_ostream& O) {
- O << Indent1 << "const char** InputLanguages() const {\n"
- << Indent2 << "return InputLanguages_;\n"
- << Indent1 << "}\n\n";
+ O.indent(Indent1) << "const char** InputLanguages() const {\n";
+ O.indent(Indent2) << "return InputLanguages_;\n";
+ O.indent(Indent1) << "}\n\n";
if (D.OutLanguage.empty())
throw "Tool " + D.Name + " has no 'out_language' property!";
- O << Indent1 << "const char* OutputLanguage() const {\n"
- << Indent2 << "return \"" << D.OutLanguage << "\";\n"
- << Indent1 << "}\n\n";
+ O.indent(Indent1) << "const char* OutputLanguage() const {\n";
+ O.indent(Indent2) << "return \"" << D.OutLanguage << "\";\n";
+ O.indent(Indent1) << "}\n\n";
}
/// EmitNameMethod - Emit the Name() method for a given Tool class.
void EmitNameMethod (const ToolDescription& D, raw_ostream& O) {
- O << Indent1 << "const char* Name() const {\n"
- << Indent2 << "return \"" << D.Name << "\";\n"
- << Indent1 << "}\n\n";
+ O.indent(Indent1) << "const char* Name() const {\n";
+ O.indent(Indent2) << "return \"" << D.Name << "\";\n";
+ O.indent(Indent1) << "}\n\n";
}
/// EmitIsJoinMethod - Emit the IsJoin() method for a given Tool
/// class.
void EmitIsJoinMethod (const ToolDescription& D, raw_ostream& O) {
- O << Indent1 << "bool IsJoin() const {\n";
+ O.indent(Indent1) << "bool IsJoin() const {\n";
if (D.isJoin())
- O << Indent2 << "return true;\n";
+ O.indent(Indent2) << "return true;\n";
else
- O << Indent2 << "return false;\n";
- O << Indent1 << "}\n\n";
+ O.indent(Indent2) << "return false;\n";
+ O.indent(Indent1) << "}\n\n";
}
/// EmitStaticMemberDefinitions - Emit static member definitions for a
@@ -1661,8 +1704,8 @@ void EmitToolClassDefinition (const ToolDescription& D,
else
O << "Tool";
- O << "{\nprivate:\n"
- << Indent1 << "static const char* InputLanguages_[];\n\n";
+ O << "{\nprivate:\n";
+ O.indent(Indent1) << "static const char* InputLanguages_[];\n\n";
O << "public:\n";
EmitNameMethod(D, O);
@@ -1792,9 +1835,9 @@ void EmitPopulateLanguageMap (const RecordKeeper& Records, raw_ostream& O)
const ListInit* Suffixes = LangToSuffixes->getValueAsListInit("suffixes");
for (unsigned i = 0; i < Suffixes->size(); ++i)
- O << Indent1 << "langMap[\""
- << InitPtrToString(Suffixes->getElement(i))
- << "\"] = \"" << Lang << "\";\n";
+ O.indent(Indent1) << "langMap[\""
+ << InitPtrToString(Suffixes->getElement(i))
+ << "\"] = \"" << Lang << "\";\n";
}
}
@@ -1803,21 +1846,22 @@ void EmitPopulateLanguageMap (const RecordKeeper& Records, raw_ostream& O)
/// IncDecWeight - Helper function passed to EmitCaseConstructHandler()
/// by EmitEdgeClass().
-void IncDecWeight (const Init* i, const char* IndentLevel,
+void IncDecWeight (const Init* i, unsigned IndentLevel,
raw_ostream& O) {
const DagInit& d = InitPtrToDag(i);
const std::string& OpName = d.getOperator()->getAsString();
if (OpName == "inc_weight") {
- O << IndentLevel << "ret += ";
+ O.indent(IndentLevel) << "ret += ";
}
else if (OpName == "dec_weight") {
- O << IndentLevel << "ret -= ";
+ O.indent(IndentLevel) << "ret -= ";
}
else if (OpName == "error") {
- O << IndentLevel << "throw std::runtime_error(\"" <<
- (d.getNumArgs() >= 1 ? InitPtrToString(d.getArg(0))
- : "Unknown error!")
+ O.indent(IndentLevel)
+ << "throw std::runtime_error(\"" <<
+ (d.getNumArgs() >= 1 ? InitPtrToString(d.getArg(0))
+ : "Unknown error!")
<< "\");\n";
return;
}
@@ -1840,19 +1884,20 @@ void EmitEdgeClass (unsigned N, const std::string& Target,
// Class constructor.
O << "class Edge" << N << ": public Edge {\n"
- << "public:\n"
- << Indent1 << "Edge" << N << "() : Edge(\"" << Target
- << "\") {}\n\n"
+ << "public:\n";
+ O.indent(Indent1) << "Edge" << N << "() : Edge(\"" << Target
+ << "\") {}\n\n";
// Function Weight().
- << Indent1 << "unsigned Weight(const InputLanguagesSet& InLangs) const {\n"
- << Indent2 << "unsigned ret = 0;\n";
+ O.indent(Indent1)
+ << "unsigned Weight(const InputLanguagesSet& InLangs) const {\n";
+ O.indent(Indent2) << "unsigned ret = 0;\n";
// Handle the 'case' construct.
EmitCaseConstructHandler(Case, Indent2, IncDecWeight, false, OptDescs, O);
- O << Indent2 << "return ret;\n"
- << Indent1 << "};\n\n};\n\n";
+ O.indent(Indent2) << "return ret;\n";
+ O.indent(Indent1) << "};\n\n};\n\n";
}
/// EmitEdgeClasses - Emit Edge* classes that represent graph edges.
@@ -1882,7 +1927,7 @@ void EmitPopulateCompilationGraph (const RecordVector& EdgeVector,
for (ToolDescriptions::const_iterator B = ToolDescs.begin(),
E = ToolDescs.end(); B != E; ++B)
- O << Indent1 << "G.insertNode(new " << (*B)->Name << "());\n";
+ O.indent(Indent1) << "G.insertNode(new " << (*B)->Name << "());\n";
O << '\n';
@@ -1896,7 +1941,7 @@ void EmitPopulateCompilationGraph (const RecordVector& EdgeVector,
const std::string& NodeB = Edge->getValueAsString("b");
DagInit* Weight = Edge->getValueAsDag("weight");
- O << Indent1 << "G.insertEdge(\"" << NodeA << "\", ";
+ O.indent(Indent1) << "G.insertEdge(\"" << NodeA << "\", ";
if (isDagEmpty(Weight))
O << "new SimpleEdge(\"" << NodeB << "\")";
@@ -1985,7 +2030,7 @@ void EmitHookDeclarations(const ToolDescriptions& ToolDescs, raw_ostream& O) {
O << "namespace hooks {\n";
for (StringMap<unsigned>::const_iterator B = HookNames.begin(),
E = HookNames.end(); B != E; ++B) {
- O << Indent1 << "std::string " << B->first() << "(";
+ O.indent(Indent1) << "std::string " << B->first() << "(";
for (unsigned i = 0, j = B->second; i < j; ++i) {
O << "const char* Arg" << i << (i+1 == j ? "" : ", ");
@@ -1998,22 +2043,23 @@ void EmitHookDeclarations(const ToolDescriptions& ToolDescs, raw_ostream& O) {
/// EmitRegisterPlugin - Emit code to register this plugin.
void EmitRegisterPlugin(int Priority, raw_ostream& O) {
- O << "struct Plugin : public llvmc::BasePlugin {\n\n"
- << Indent1 << "int Priority() const { return " << Priority << "; }\n\n"
- << Indent1 << "void PopulateLanguageMap(LanguageMap& langMap) const\n"
- << Indent1 << "{ PopulateLanguageMapLocal(langMap); }\n\n"
- << Indent1
- << "void PopulateCompilationGraph(CompilationGraph& graph) const\n"
- << Indent1 << "{ PopulateCompilationGraphLocal(graph); }\n"
- << "};\n\n"
-
- << "static llvmc::RegisterPlugin<Plugin> RP;\n\n";
+ O << "struct Plugin : public llvmc::BasePlugin {\n\n";
+ O.indent(Indent1) << "int Priority() const { return "
+ << Priority << "; }\n\n";
+ O.indent(Indent1) << "void PopulateLanguageMap(LanguageMap& langMap) const\n";
+ O.indent(Indent1) << "{ PopulateLanguageMapLocal(langMap); }\n\n";
+ O.indent(Indent1)
+ << "void PopulateCompilationGraph(CompilationGraph& graph) const\n";
+ O.indent(Indent1) << "{ PopulateCompilationGraphLocal(graph); }\n"
+ << "};\n\n"
+ << "static llvmc::RegisterPlugin<Plugin> RP;\n\n";
}
/// EmitIncludes - Emit necessary #include directives and some
/// additional declarations.
void EmitIncludes(raw_ostream& O) {
- O << "#include \"llvm/CompilerDriver/CompilationGraph.h\"\n"
+ O << "#include \"llvm/CompilerDriver/BuiltinOptions.h\"\n"
+ << "#include \"llvm/CompilerDriver/CompilationGraph.h\"\n"
<< "#include \"llvm/CompilerDriver/ForceLinkageMacros.h\"\n"
<< "#include \"llvm/CompilerDriver/Plugin.h\"\n"
<< "#include \"llvm/CompilerDriver/Tool.h\"\n\n"
diff --git a/libclamav/c++/llvm/utils/TableGen/Record.cpp b/libclamav/c++/llvm/utils/TableGen/Record.cpp
index d594c9a..a551166 100644
--- a/libclamav/c++/llvm/utils/TableGen/Record.cpp
+++ b/libclamav/c++/llvm/utils/TableGen/Record.cpp
@@ -1384,11 +1384,11 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const Record &R) {
/// getValueInit - Return the initializer for a value with the specified name,
/// or throw an exception if the field does not exist.
///
-Init *Record::getValueInit(const std::string &FieldName) const {
+Init *Record::getValueInit(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (R == 0 || R->getValue() == 0)
throw "Record `" + getName() + "' does not have a field named `" +
- FieldName + "'!\n";
+ FieldName.str() + "'!\n";
return R->getValue();
}
@@ -1397,15 +1397,15 @@ Init *Record::getValueInit(const std::string &FieldName) const {
/// value as a string, throwing an exception if the field does not exist or if
/// the value is not a string.
///
-std::string Record::getValueAsString(const std::string &FieldName) const {
+std::string Record::getValueAsString(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (R == 0 || R->getValue() == 0)
throw "Record `" + getName() + "' does not have a field named `" +
- FieldName + "'!\n";
+ FieldName.str() + "'!\n";
if (const StringInit *SI = dynamic_cast<const StringInit*>(R->getValue()))
return SI->getValue();
- throw "Record `" + getName() + "', field `" + FieldName +
+ throw "Record `" + getName() + "', field `" + FieldName.str() +
"' does not have a string initializer!";
}
@@ -1413,15 +1413,15 @@ std::string Record::getValueAsString(const std::string &FieldName) const {
/// its value as a BitsInit, throwing an exception if the field does not exist
/// or if the value is not the right type.
///
-BitsInit *Record::getValueAsBitsInit(const std::string &FieldName) const {
+BitsInit *Record::getValueAsBitsInit(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (R == 0 || R->getValue() == 0)
throw "Record `" + getName() + "' does not have a field named `" +
- FieldName + "'!\n";
+ FieldName.str() + "'!\n";
if (BitsInit *BI = dynamic_cast<BitsInit*>(R->getValue()))
return BI;
- throw "Record `" + getName() + "', field `" + FieldName +
+ throw "Record `" + getName() + "', field `" + FieldName.str() +
"' does not have a BitsInit initializer!";
}
@@ -1429,15 +1429,15 @@ BitsInit *Record::getValueAsBitsInit(const std::string &FieldName) const {
/// its value as a ListInit, throwing an exception if the field does not exist
/// or if the value is not the right type.
///
-ListInit *Record::getValueAsListInit(const std::string &FieldName) const {
+ListInit *Record::getValueAsListInit(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (R == 0 || R->getValue() == 0)
throw "Record `" + getName() + "' does not have a field named `" +
- FieldName + "'!\n";
+ FieldName.str() + "'!\n";
if (ListInit *LI = dynamic_cast<ListInit*>(R->getValue()))
return LI;
- throw "Record `" + getName() + "', field `" + FieldName +
+ throw "Record `" + getName() + "', field `" + FieldName.str() +
"' does not have a list initializer!";
}
@@ -1446,14 +1446,14 @@ ListInit *Record::getValueAsListInit(const std::string &FieldName) const {
/// not exist or if the value is not the right type.
///
std::vector<Record*>
-Record::getValueAsListOfDefs(const std::string &FieldName) const {
+Record::getValueAsListOfDefs(StringRef FieldName) const {
ListInit *List = getValueAsListInit(FieldName);
std::vector<Record*> Defs;
for (unsigned i = 0; i < List->getSize(); i++) {
if (DefInit *DI = dynamic_cast<DefInit*>(List->getElement(i))) {
Defs.push_back(DI->getDef());
} else {
- throw "Record `" + getName() + "', field `" + FieldName +
+ throw "Record `" + getName() + "', field `" + FieldName.str() +
"' list is not entirely DefInit!";
}
}
@@ -1464,15 +1464,15 @@ Record::getValueAsListOfDefs(const std::string &FieldName) const {
/// value as an int64_t, throwing an exception if the field does not exist or if
/// the value is not the right type.
///
-int64_t Record::getValueAsInt(const std::string &FieldName) const {
+int64_t Record::getValueAsInt(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (R == 0 || R->getValue() == 0)
throw "Record `" + getName() + "' does not have a field named `" +
- FieldName + "'!\n";
+ FieldName.str() + "'!\n";
if (IntInit *II = dynamic_cast<IntInit*>(R->getValue()))
return II->getValue();
- throw "Record `" + getName() + "', field `" + FieldName +
+ throw "Record `" + getName() + "', field `" + FieldName.str() +
"' does not have an int initializer!";
}
@@ -1481,14 +1481,14 @@ int64_t Record::getValueAsInt(const std::string &FieldName) const {
/// not exist or if the value is not the right type.
///
std::vector<int64_t>
-Record::getValueAsListOfInts(const std::string &FieldName) const {
+Record::getValueAsListOfInts(StringRef FieldName) const {
ListInit *List = getValueAsListInit(FieldName);
std::vector<int64_t> Ints;
for (unsigned i = 0; i < List->getSize(); i++) {
if (IntInit *II = dynamic_cast<IntInit*>(List->getElement(i))) {
Ints.push_back(II->getValue());
} else {
- throw "Record `" + getName() + "', field `" + FieldName +
+ throw "Record `" + getName() + "', field `" + FieldName.str() +
"' does not have a list of ints initializer!";
}
}
@@ -1499,15 +1499,15 @@ Record::getValueAsListOfInts(const std::string &FieldName) const {
/// value as a Record, throwing an exception if the field does not exist or if
/// the value is not the right type.
///
-Record *Record::getValueAsDef(const std::string &FieldName) const {
+Record *Record::getValueAsDef(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (R == 0 || R->getValue() == 0)
throw "Record `" + getName() + "' does not have a field named `" +
- FieldName + "'!\n";
+ FieldName.str() + "'!\n";
if (DefInit *DI = dynamic_cast<DefInit*>(R->getValue()))
return DI->getDef();
- throw "Record `" + getName() + "', field `" + FieldName +
+ throw "Record `" + getName() + "', field `" + FieldName.str() +
"' does not have a def initializer!";
}
@@ -1515,15 +1515,15 @@ Record *Record::getValueAsDef(const std::string &FieldName) const {
/// value as a bit, throwing an exception if the field does not exist or if
/// the value is not the right type.
///
-bool Record::getValueAsBit(const std::string &FieldName) const {
+bool Record::getValueAsBit(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (R == 0 || R->getValue() == 0)
throw "Record `" + getName() + "' does not have a field named `" +
- FieldName + "'!\n";
+ FieldName.str() + "'!\n";
if (BitInit *BI = dynamic_cast<BitInit*>(R->getValue()))
return BI->getValue();
- throw "Record `" + getName() + "', field `" + FieldName +
+ throw "Record `" + getName() + "', field `" + FieldName.str() +
"' does not have a bit initializer!";
}
@@ -1531,27 +1531,27 @@ bool Record::getValueAsBit(const std::string &FieldName) const {
/// value as an Dag, throwing an exception if the field does not exist or if
/// the value is not the right type.
///
-DagInit *Record::getValueAsDag(const std::string &FieldName) const {
+DagInit *Record::getValueAsDag(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (R == 0 || R->getValue() == 0)
throw "Record `" + getName() + "' does not have a field named `" +
- FieldName + "'!\n";
+ FieldName.str() + "'!\n";
if (DagInit *DI = dynamic_cast<DagInit*>(R->getValue()))
return DI;
- throw "Record `" + getName() + "', field `" + FieldName +
+ throw "Record `" + getName() + "', field `" + FieldName.str() +
"' does not have a dag initializer!";
}
-std::string Record::getValueAsCode(const std::string &FieldName) const {
+std::string Record::getValueAsCode(StringRef FieldName) const {
const RecordVal *R = getValue(FieldName);
if (R == 0 || R->getValue() == 0)
throw "Record `" + getName() + "' does not have a field named `" +
- FieldName + "'!\n";
+ FieldName.str() + "'!\n";
if (const CodeInit *CI = dynamic_cast<const CodeInit*>(R->getValue()))
return CI->getValue();
- throw "Record `" + getName() + "', field `" + FieldName +
+ throw "Record `" + getName() + "', field `" + FieldName.str() +
"' does not have a code initializer!";
}
diff --git a/libclamav/c++/llvm/utils/TableGen/Record.h b/libclamav/c++/llvm/utils/TableGen/Record.h
index 9415109..1b33743 100644
--- a/libclamav/c++/llvm/utils/TableGen/Record.h
+++ b/libclamav/c++/llvm/utils/TableGen/Record.h
@@ -1248,24 +1248,24 @@ public:
const std::vector<RecordVal> &getValues() const { return Values; }
const std::vector<Record*> &getSuperClasses() const { return SuperClasses; }
- bool isTemplateArg(const std::string &Name) const {
+ bool isTemplateArg(StringRef Name) const {
for (unsigned i = 0, e = TemplateArgs.size(); i != e; ++i)
if (TemplateArgs[i] == Name) return true;
return false;
}
- const RecordVal *getValue(const std::string &Name) const {
+ const RecordVal *getValue(StringRef Name) const {
for (unsigned i = 0, e = Values.size(); i != e; ++i)
if (Values[i].getName() == Name) return &Values[i];
return 0;
}
- RecordVal *getValue(const std::string &Name) {
+ RecordVal *getValue(StringRef Name) {
for (unsigned i = 0, e = Values.size(); i != e; ++i)
if (Values[i].getName() == Name) return &Values[i];
return 0;
}
- void addTemplateArg(const std::string &Name) {
+ void addTemplateArg(StringRef Name) {
assert(!isTemplateArg(Name) && "Template arg already defined!");
TemplateArgs.push_back(Name);
}
@@ -1275,7 +1275,7 @@ public:
Values.push_back(RV);
}
- void removeValue(const std::string &Name) {
+ void removeValue(StringRef Name) {
assert(getValue(Name) && "Cannot remove an entry that does not exist!");
for (unsigned i = 0, e = Values.size(); i != e; ++i)
if (Values[i].getName() == Name) {
@@ -1292,7 +1292,7 @@ public:
return false;
}
- bool isSubClassOf(const std::string &Name) const {
+ bool isSubClassOf(StringRef Name) const {
for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
if (SuperClasses[i]->getName() == Name)
return true;
@@ -1323,67 +1323,67 @@ public:
/// getValueInit - Return the initializer for a value with the specified name,
/// or throw an exception if the field does not exist.
///
- Init *getValueInit(const std::string &FieldName) const;
+ Init *getValueInit(StringRef FieldName) const;
/// getValueAsString - This method looks up the specified field and returns
/// its value as a string, throwing an exception if the field does not exist
/// or if the value is not a string.
///
- std::string getValueAsString(const std::string &FieldName) const;
+ std::string getValueAsString(StringRef FieldName) const;
/// getValueAsBitsInit - This method looks up the specified field and returns
/// its value as a BitsInit, throwing an exception if the field does not exist
/// or if the value is not the right type.
///
- BitsInit *getValueAsBitsInit(const std::string &FieldName) const;
+ BitsInit *getValueAsBitsInit(StringRef FieldName) const;
/// getValueAsListInit - This method looks up the specified field and returns
/// its value as a ListInit, throwing an exception if the field does not exist
/// or if the value is not the right type.
///
- ListInit *getValueAsListInit(const std::string &FieldName) const;
+ ListInit *getValueAsListInit(StringRef FieldName) const;
/// getValueAsListOfDefs - This method looks up the specified field and
/// returns its value as a vector of records, throwing an exception if the
/// field does not exist or if the value is not the right type.
///
- std::vector<Record*> getValueAsListOfDefs(const std::string &FieldName) const;
+ std::vector<Record*> getValueAsListOfDefs(StringRef FieldName) const;
/// getValueAsListOfInts - This method looks up the specified field and returns
/// its value as a vector of integers, throwing an exception if the field does
/// not exist or if the value is not the right type.
///
- std::vector<int64_t> getValueAsListOfInts(const std::string &FieldName) const;
+ std::vector<int64_t> getValueAsListOfInts(StringRef FieldName) const;
/// getValueAsDef - This method looks up the specified field and returns its
/// value as a Record, throwing an exception if the field does not exist or if
/// the value is not the right type.
///
- Record *getValueAsDef(const std::string &FieldName) const;
+ Record *getValueAsDef(StringRef FieldName) const;
/// getValueAsBit - This method looks up the specified field and returns its
/// value as a bit, throwing an exception if the field does not exist or if
/// the value is not the right type.
///
- bool getValueAsBit(const std::string &FieldName) const;
+ bool getValueAsBit(StringRef FieldName) const;
/// getValueAsInt - This method looks up the specified field and returns its
/// value as an int64_t, throwing an exception if the field does not exist or
/// if the value is not the right type.
///
- int64_t getValueAsInt(const std::string &FieldName) const;
+ int64_t getValueAsInt(StringRef FieldName) const;
/// getValueAsDag - This method looks up the specified field and returns its
/// value as an Dag, throwing an exception if the field does not exist or if
/// the value is not the right type.
///
- DagInit *getValueAsDag(const std::string &FieldName) const;
+ DagInit *getValueAsDag(StringRef FieldName) const;
/// getValueAsCode - This method looks up the specified field and returns
/// its value as the string data in a CodeInit, throwing an exception if the
/// field does not exist or if the value is not a code object.
///
- std::string getValueAsCode(const std::string &FieldName) const;
+ std::string getValueAsCode(StringRef FieldName) const;
};
raw_ostream &operator<<(raw_ostream &OS, const Record &R);
diff --git a/libclamav/c++/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/libclamav/c++/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index a9bb2a1..3c7b44a 100644
--- a/libclamav/c++/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/libclamav/c++/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -767,7 +767,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
}
OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
- OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n";
+ OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
@@ -775,11 +775,6 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
const CodeGenRegister &Reg = Registers[i];
OS << " { \"";
- if (!Reg.TheDef->getValueAsString("AsmName").empty())
- OS << Reg.TheDef->getValueAsString("AsmName");
- else
- OS << Reg.getName();
- OS << "\",\t\"";
OS << Reg.getName() << "\",\t";
if (RegisterAliases.count(Reg.TheDef))
OS << Reg.getName() << "_AliasSet,\t";
diff --git a/libclamav/c++/llvm/utils/TableGen/StringToOffsetTable.h b/libclamav/c++/llvm/utils/TableGen/StringToOffsetTable.h
new file mode 100644
index 0000000..d9d7cf4
--- /dev/null
+++ b/libclamav/c++/llvm/utils/TableGen/StringToOffsetTable.h
@@ -0,0 +1,76 @@
+//===- StringToOffsetTable.h - Emit a big concatenated string ---*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef TBLGEN_STRING_TO_OFFSET_TABLE_H
+#define TBLGEN_STRING_TO_OFFSET_TABLE_H
+
+#include "llvm/ADT/StringMap.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/ADT/StringExtras.h"
+
+namespace llvm {
+
+/// StringToOffsetTable - This class uniques a bunch of nul-terminated strings
+/// and keeps track of their offset in a massive contiguous string allocation.
+/// It can then output this string blob and use indexes into the string to
+/// reference each piece.
+class StringToOffsetTable {
+ StringMap<unsigned> StringOffset;
+ std::string AggregateString;
+public:
+
+ unsigned GetOrAddStringOffset(StringRef Str) {
+ unsigned &Entry = StringOffset[Str];
+ if (Entry == 0) {
+ // Add the string to the aggregate if this is the first time found.
+ Entry = AggregateString.size();
+ AggregateString.append(Str.begin(), Str.end());
+ AggregateString += '\0';
+ }
+
+ return Entry;
+ }
+
+ void EmitString(raw_ostream &O) {
+ O << " \"";
+ unsigned CharsPrinted = 0;
+ EscapeString(AggregateString);
+ for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
+ if (CharsPrinted > 70) {
+ O << "\"\n \"";
+ CharsPrinted = 0;
+ }
+ O << AggregateString[i];
+ ++CharsPrinted;
+
+ // Print escape sequences all together.
+ if (AggregateString[i] != '\\')
+ continue;
+
+ assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
+ if (isdigit(AggregateString[i+1])) {
+ assert(isdigit(AggregateString[i+2]) &&
+ isdigit(AggregateString[i+3]) &&
+ "Expected 3 digit octal escape!");
+ O << AggregateString[++i];
+ O << AggregateString[++i];
+ O << AggregateString[++i];
+ CharsPrinted += 3;
+ } else {
+ O << AggregateString[++i];
+ ++CharsPrinted;
+ }
+ }
+ O << "\"";
+ }
+};
+
+} // end namespace llvm
+
+#endif
diff --git a/libclamav/c++/llvm/utils/TableGen/SubtargetEmitter.cpp b/libclamav/c++/llvm/utils/TableGen/SubtargetEmitter.cpp
index 9760b17..c8cf234 100644
--- a/libclamav/c++/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/libclamav/c++/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -413,7 +413,7 @@ void SubtargetEmitter::EmitProcessorData(raw_ostream &OS,
// For each itinerary class
std::vector<InstrItinerary> &ItinList = *ProcListIter++;
- for (unsigned j = 0, M = ItinList.size(); j < M;) {
+ for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
InstrItinerary &Intinerary = ItinList[j];
// Emit in the form of
@@ -427,13 +427,11 @@ void SubtargetEmitter::EmitProcessorData(raw_ostream &OS,
Intinerary.LastOperandCycle << " }";
}
- // If more in list add comma
- if (++j < M) OS << ",";
-
- OS << " // " << (j - 1) << "\n";
+ OS << ", // " << j << "\n";
}
// End processor itinerary table
+ OS << " { ~0U, ~0U, ~0U, ~0U } // end marker\n";
OS << "};\n";
}
}
diff --git a/libclamav/c++/llvm/utils/buildit/build_llvm b/libclamav/c++/llvm/utils/buildit/build_llvm
index 1c2b480..91fbe15 100755
--- a/libclamav/c++/llvm/utils/buildit/build_llvm
+++ b/libclamav/c++/llvm/utils/buildit/build_llvm
@@ -56,9 +56,6 @@ DIR=`pwd`
DARWIN_VERS=`uname -r | sed 's/\..*//'`
echo DARWIN_VERS = $DARWIN_VERS
-# If the user has CC set in their environment unset it now
-unset CC
-
if [ "x$RC_ProjectName" = "xllvmCore_Embedded" ]; then
DT_HOME=$DEST_DIR/Developer/Platforms/iPhoneOS.platform/Developer/usr
DEST_ROOT="/Developer/Platforms/iPhoneOS.platform/Developer$DEST_ROOT"
@@ -90,6 +87,17 @@ ln -s $ORIG_SRC_DIR/* $SRC_DIR/ || exit 1
mkdir -p $DIR/obj-llvm || exit 1
cd $DIR/obj-llvm || exit 1
+# If the user has set CC or CXX, respect their wishes. If not,
+# compile with LLVM-GCC/LLVM-G++ if available; if LLVM is not
+# available, fall back to usual GCC/G++ default.
+savedPATH=$PATH ; PATH="$PATH:/Developer/usr/bin"
+XTMPCC=$(which llvm-gcc)
+if [ x$CC = x -a x$XTMPCC != x ] ; then export CC=$XTMPCC ; fi
+XTMPCC=$(which llvm-g++)
+if [ x$CXX = x -a x$XTMPCC != x ] ; then export CXX=$XTMPCC ; fi
+PATH=$savedPATH
+unset XTMPCC savedPATH
+
if [ \! -f Makefile.config ]; then
$SRC_DIR/configure --prefix=$DT_HOME/local \
--enable-targets=arm,x86,powerpc,cbe \
@@ -152,7 +160,7 @@ make $JOBS_FLAG $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$TARGETS" \
CXXFLAGS="-DLLVM_VERSION_INFO='\" Apple Build #$LLVM_VERSION\"'" \
VERBOSE=1
-if ! test $? == 0 ; then
+if [ $? != 0 ] ; then
echo "error: LLVM 'make' failed!"
exit 1
fi
diff --git a/libclamav/c++/llvm/utils/count/CMakeLists.txt b/libclamav/c++/llvm/utils/count/CMakeLists.txt
new file mode 100644
index 0000000..e124f61
--- /dev/null
+++ b/libclamav/c++/llvm/utils/count/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_executable(count
+ count.c
+ )
diff --git a/libclamav/c++/llvm/utils/count/Makefile b/libclamav/c++/llvm/utils/count/Makefile
new file mode 100644
index 0000000..8de076a
--- /dev/null
+++ b/libclamav/c++/llvm/utils/count/Makefile
@@ -0,0 +1,20 @@
+##===- utils/count/Makefile --------------------------------*- Makefile -*-===##
+#
+# The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+
+LEVEL = ../..
+TOOLNAME = count
+USEDLIBS =
+
+# This tool has no plugins, optimize startup time.
+TOOL_NO_EXPORTS = 1
+
+# Don't install this utility
+NO_INSTALL = 1
+
+include $(LEVEL)/Makefile.common
diff --git a/libclamav/c++/llvm/utils/count/count.c b/libclamav/c++/llvm/utils/count/count.c
new file mode 100644
index 0000000..a37e1e0
--- /dev/null
+++ b/libclamav/c++/llvm/utils/count/count.c
@@ -0,0 +1,48 @@
+/*===- count.c - The 'count' testing tool ---------------------------------===*\
+ *
+ * The LLVM Compiler Infrastructure
+ *
+ * This file is distributed under the University of Illinois Open Source
+ * License. See LICENSE.TXT for details.
+ *
+\*===----------------------------------------------------------------------===*/
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main(int argc, char **argv) {
+ unsigned Count, NumLines, NumRead;
+ char Buffer[4096], *End;
+
+ if (argc != 2) {
+ fprintf(stderr, "usage: %s <expected line count>\n", argv[0]);
+ return 2;
+ }
+
+ Count = strtol(argv[1], &End, 10);
+ if (*End != '\0' && End != argv[1]) {
+ fprintf(stderr, "%s: invalid count argument '%s'\n", argv[0], argv[1]);
+ return 2;
+ }
+
+ NumLines = 0;
+ while ((NumRead = fread(Buffer, 1, sizeof(Buffer), stdin))) {
+ unsigned i;
+
+ for (i = 0; i != NumRead; ++i)
+ if (Buffer[i] == '\n')
+ ++NumLines;
+ }
+
+ if (!feof(stdin)) {
+ fprintf(stderr, "%s: error reading stdin\n", argv[0]);
+ return 3;
+ }
+
+ if (Count != NumLines) {
+ fprintf(stderr, "Expected %d lines, got %d.\n", Count, NumLines);
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/libclamav/c++/llvm/utils/lit/LitConfig.py b/libclamav/c++/llvm/utils/lit/LitConfig.py
new file mode 100644
index 0000000..4fb0ccc
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/LitConfig.py
@@ -0,0 +1,71 @@
+class LitConfig:
+ """LitConfig - Configuration data for a 'lit' test runner instance, shared
+ across all tests.
+
+ The LitConfig object is also used to communicate with client configuration
+ files, it is always passed in as the global variable 'lit' so that
+ configuration files can access common functionality and internal components
+ easily.
+ """
+
+ # Provide access to built-in formats.
+ import LitFormats as formats
+
+ # Provide access to built-in utility functions.
+ import Util as util
+
+ def __init__(self, progname, path, quiet,
+ useValgrind, valgrindArgs,
+ useTclAsSh,
+ noExecute, debug, isWindows):
+ # The name of the test runner.
+ self.progname = progname
+ # The items to add to the PATH environment variable.
+ self.path = list(map(str, path))
+ self.quiet = bool(quiet)
+ self.useValgrind = bool(useValgrind)
+ self.valgrindArgs = list(valgrindArgs)
+ self.useTclAsSh = bool(useTclAsSh)
+ self.noExecute = noExecute
+ self.debug = debug
+ self.isWindows = bool(isWindows)
+
+ self.numErrors = 0
+ self.numWarnings = 0
+
+ def load_config(self, config, path):
+ """load_config(config, path) - Load a config object from an alternate
+ path."""
+ from TestingConfig import TestingConfig
+ return TestingConfig.frompath(path, config.parent, self,
+ mustExist = True,
+ config = config)
+
+ def _write_message(self, kind, message):
+ import inspect, os, sys
+
+ # Get the file/line where this message was generated.
+ f = inspect.currentframe()
+ # Step out of _write_message, and then out of wrapper.
+ f = f.f_back.f_back
+ file,line,_,_,_ = inspect.getframeinfo(f)
+ location = '%s:%d' % (os.path.basename(file), line)
+
+ print >>sys.stderr, '%s: %s: %s: %s' % (self.progname, location,
+ kind, message)
+
+ def note(self, message):
+ self._write_message('note', message)
+
+ def warning(self, message):
+ self._write_message('warning', message)
+ self.numWarnings += 1
+
+ def error(self, message):
+ self._write_message('error', message)
+ self.numErrors += 1
+
+ def fatal(self, message):
+ import sys
+ self._write_message('fatal', message)
+ sys.exit(2)
diff --git a/libclamav/c++/llvm/utils/lit/LitFormats.py b/libclamav/c++/llvm/utils/lit/LitFormats.py
new file mode 100644
index 0000000..9b8250d
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/LitFormats.py
@@ -0,0 +1,2 @@
+from TestFormats import GoogleTest, ShTest, TclTest, SyntaxCheckTest
+
diff --git a/libclamav/c++/llvm/utils/lit/ProgressBar.py b/libclamav/c++/llvm/utils/lit/ProgressBar.py
new file mode 100644
index 0000000..85c95f5
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/ProgressBar.py
@@ -0,0 +1,267 @@
+#!/usr/bin/env python
+
+# Source: http://code.activestate.com/recipes/475116/, with
+# modifications by Daniel Dunbar.
+
+import sys, re, time
+
+class TerminalController:
+ """
+ A class that can be used to portably generate formatted output to
+ a terminal.
+
+ `TerminalController` defines a set of instance variables whose
+ values are initialized to the control sequence necessary to
+ perform a given action. These can be simply included in normal
+ output to the terminal:
+
+ >>> term = TerminalController()
+ >>> print 'This is '+term.GREEN+'green'+term.NORMAL
+
+ Alternatively, the `render()` method can used, which replaces
+ '${action}' with the string required to perform 'action':
+
+ >>> term = TerminalController()
+ >>> print term.render('This is ${GREEN}green${NORMAL}')
+
+ If the terminal doesn't support a given action, then the value of
+ the corresponding instance variable will be set to ''. As a
+ result, the above code will still work on terminals that do not
+ support color, except that their output will not be colored.
+ Also, this means that you can test whether the terminal supports a
+ given action by simply testing the truth value of the
+ corresponding instance variable:
+
+ >>> term = TerminalController()
+ >>> if term.CLEAR_SCREEN:
+ ... print 'This terminal supports clearning the screen.'
+
+ Finally, if the width and height of the terminal are known, then
+ they will be stored in the `COLS` and `LINES` attributes.
+ """
+ # Cursor movement:
+ BOL = '' #: Move the cursor to the beginning of the line
+ UP = '' #: Move the cursor up one line
+ DOWN = '' #: Move the cursor down one line
+ LEFT = '' #: Move the cursor left one char
+ RIGHT = '' #: Move the cursor right one char
+
+ # Deletion:
+ CLEAR_SCREEN = '' #: Clear the screen and move to home position
+ CLEAR_EOL = '' #: Clear to the end of the line.
+ CLEAR_BOL = '' #: Clear to the beginning of the line.
+ CLEAR_EOS = '' #: Clear to the end of the screen
+
+ # Output modes:
+ BOLD = '' #: Turn on bold mode
+ BLINK = '' #: Turn on blink mode
+ DIM = '' #: Turn on half-bright mode
+ REVERSE = '' #: Turn on reverse-video mode
+ NORMAL = '' #: Turn off all modes
+
+ # Cursor display:
+ HIDE_CURSOR = '' #: Make the cursor invisible
+ SHOW_CURSOR = '' #: Make the cursor visible
+
+ # Terminal size:
+ COLS = None #: Width of the terminal (None for unknown)
+ LINES = None #: Height of the terminal (None for unknown)
+
+ # Foreground colors:
+ BLACK = BLUE = GREEN = CYAN = RED = MAGENTA = YELLOW = WHITE = ''
+
+ # Background colors:
+ BG_BLACK = BG_BLUE = BG_GREEN = BG_CYAN = ''
+ BG_RED = BG_MAGENTA = BG_YELLOW = BG_WHITE = ''
+
+ _STRING_CAPABILITIES = """
+ BOL=cr UP=cuu1 DOWN=cud1 LEFT=cub1 RIGHT=cuf1
+ CLEAR_SCREEN=clear CLEAR_EOL=el CLEAR_BOL=el1 CLEAR_EOS=ed BOLD=bold
+ BLINK=blink DIM=dim REVERSE=rev UNDERLINE=smul NORMAL=sgr0
+ HIDE_CURSOR=cinvis SHOW_CURSOR=cnorm""".split()
+ _COLORS = """BLACK BLUE GREEN CYAN RED MAGENTA YELLOW WHITE""".split()
+ _ANSICOLORS = "BLACK RED GREEN YELLOW BLUE MAGENTA CYAN WHITE".split()
+
+ def __init__(self, term_stream=sys.stdout):
+ """
+ Create a `TerminalController` and initialize its attributes
+ with appropriate values for the current terminal.
+ `term_stream` is the stream that will be used for terminal
+ output; if this stream is not a tty, then the terminal is
+ assumed to be a dumb terminal (i.e., have no capabilities).
+ """
+ # Curses isn't available on all platforms
+ try: import curses
+ except: return
+
+ # If the stream isn't a tty, then assume it has no capabilities.
+ if not term_stream.isatty(): return
+
+ # Check the terminal type. If we fail, then assume that the
+ # terminal has no capabilities.
+ try: curses.setupterm()
+ except: return
+
+ # Look up numeric capabilities.
+ self.COLS = curses.tigetnum('cols')
+ self.LINES = curses.tigetnum('lines')
+
+ # Look up string capabilities.
+ for capability in self._STRING_CAPABILITIES:
+ (attrib, cap_name) = capability.split('=')
+ setattr(self, attrib, self._tigetstr(cap_name) or '')
+
+ # Colors
+ set_fg = self._tigetstr('setf')
+ if set_fg:
+ for i,color in zip(range(len(self._COLORS)), self._COLORS):
+ setattr(self, color, curses.tparm(set_fg, i) or '')
+ set_fg_ansi = self._tigetstr('setaf')
+ if set_fg_ansi:
+ for i,color in zip(range(len(self._ANSICOLORS)), self._ANSICOLORS):
+ setattr(self, color, curses.tparm(set_fg_ansi, i) or '')
+ set_bg = self._tigetstr('setb')
+ if set_bg:
+ for i,color in zip(range(len(self._COLORS)), self._COLORS):
+ setattr(self, 'BG_'+color, curses.tparm(set_bg, i) or '')
+ set_bg_ansi = self._tigetstr('setab')
+ if set_bg_ansi:
+ for i,color in zip(range(len(self._ANSICOLORS)), self._ANSICOLORS):
+ setattr(self, 'BG_'+color, curses.tparm(set_bg_ansi, i) or '')
+
+ def _tigetstr(self, cap_name):
+ # String capabilities can include "delays" of the form "$<2>".
+ # For any modern terminal, we should be able to just ignore
+ # these, so strip them out.
+ import curses
+ cap = curses.tigetstr(cap_name) or ''
+ return re.sub(r'\$<\d+>[/*]?', '', cap)
+
+ def render(self, template):
+ """
+ Replace each $-substitutions in the given template string with
+ the corresponding terminal control string (if it's defined) or
+ '' (if it's not).
+ """
+ return re.sub(r'\$\$|\${\w+}', self._render_sub, template)
+
+ def _render_sub(self, match):
+ s = match.group()
+ if s == '$$': return s
+ else: return getattr(self, s[2:-1])
+
+#######################################################################
+# Example use case: progress bar
+#######################################################################
+
+class SimpleProgressBar:
+ """
+ A simple progress bar which doesn't need any terminal support.
+
+ This prints out a progress bar like:
+ 'Header: 0 .. 10.. 20.. ...'
+ """
+
+ def __init__(self, header):
+ self.header = header
+ self.atIndex = None
+
+ def update(self, percent, message):
+ if self.atIndex is None:
+ sys.stdout.write(self.header)
+ self.atIndex = 0
+
+ next = int(percent*50)
+ if next == self.atIndex:
+ return
+
+ for i in range(self.atIndex, next):
+ idx = i % 5
+ if idx == 0:
+ sys.stdout.write('%-2d' % (i*2))
+ elif idx == 1:
+ pass # Skip second char
+ elif idx < 4:
+ sys.stdout.write('.')
+ else:
+ sys.stdout.write(' ')
+ sys.stdout.flush()
+ self.atIndex = next
+
+ def clear(self):
+ if self.atIndex is not None:
+ sys.stdout.write('\n')
+ sys.stdout.flush()
+ self.atIndex = None
+
+class ProgressBar:
+ """
+ A 3-line progress bar, which looks like::
+
+ Header
+ 20% [===========----------------------------------]
+ progress message
+
+ The progress bar is colored, if the terminal supports color
+ output; and adjusts to the width of the terminal.
+ """
+ BAR = '%s${GREEN}[${BOLD}%s%s${NORMAL}${GREEN}]${NORMAL}%s\n'
+ HEADER = '${BOLD}${CYAN}%s${NORMAL}\n\n'
+
+ def __init__(self, term, header, useETA=True):
+ self.term = term
+ if not (self.term.CLEAR_EOL and self.term.UP and self.term.BOL):
+ raise ValueError("Terminal isn't capable enough -- you "
+ "should use a simpler progress dispaly.")
+ self.width = self.term.COLS or 75
+ self.bar = term.render(self.BAR)
+ self.header = self.term.render(self.HEADER % header.center(self.width))
+ self.cleared = 1 #: true if we haven't drawn the bar yet.
+ self.useETA = useETA
+ if self.useETA:
+ self.startTime = time.time()
+ self.update(0, '')
+
+ def update(self, percent, message):
+ if self.cleared:
+ sys.stdout.write(self.header)
+ self.cleared = 0
+ prefix = '%3d%% ' % (percent*100,)
+ suffix = ''
+ if self.useETA:
+ elapsed = time.time() - self.startTime
+ if percent > .0001 and elapsed > 1:
+ total = elapsed / percent
+ eta = int(total - elapsed)
+ h = eta//3600.
+ m = (eta//60) % 60
+ s = eta % 60
+ suffix = ' ETA: %02d:%02d:%02d'%(h,m,s)
+ barWidth = self.width - len(prefix) - len(suffix) - 2
+ n = int(barWidth*percent)
+ if len(message) < self.width:
+ message = message + ' '*(self.width - len(message))
+ else:
+ message = '... ' + message[-(self.width-4):]
+ sys.stdout.write(
+ self.term.BOL + self.term.UP + self.term.CLEAR_EOL +
+ (self.bar % (prefix, '='*n, '-'*(barWidth-n), suffix)) +
+ self.term.CLEAR_EOL + message)
+
+ def clear(self):
+ if not self.cleared:
+ sys.stdout.write(self.term.BOL + self.term.CLEAR_EOL +
+ self.term.UP + self.term.CLEAR_EOL +
+ self.term.UP + self.term.CLEAR_EOL)
+ self.cleared = 1
+
+def test():
+ import time
+ tc = TerminalController()
+ p = ProgressBar(tc, 'Tests')
+ for i in range(101):
+ p.update(i/100., str(i))
+ time.sleep(.3)
+
+if __name__=='__main__':
+ test()
diff --git a/libclamav/c++/llvm/utils/lit/ShCommands.py b/libclamav/c++/llvm/utils/lit/ShCommands.py
new file mode 100644
index 0000000..4550437
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/ShCommands.py
@@ -0,0 +1,85 @@
+class Command:
+ def __init__(self, args, redirects):
+ self.args = list(args)
+ self.redirects = list(redirects)
+
+ def __repr__(self):
+ return 'Command(%r, %r)' % (self.args, self.redirects)
+
+ def __cmp__(self, other):
+ if not isinstance(other, Command):
+ return -1
+
+ return cmp((self.args, self.redirects),
+ (other.args, other.redirects))
+
+ def toShell(self, file):
+ for arg in self.args:
+ if "'" not in arg:
+ quoted = "'%s'" % arg
+ elif '"' not in arg and '$' not in arg:
+ quoted = '"%s"' % arg
+ else:
+ raise NotImplementedError,'Unable to quote %r' % arg
+ print >>file, quoted,
+
+ # For debugging / validation.
+ import ShUtil
+ dequoted = list(ShUtil.ShLexer(quoted).lex())
+ if dequoted != [arg]:
+ raise NotImplementedError,'Unable to quote %r' % arg
+
+ for r in self.redirects:
+ if len(r[0]) == 1:
+ print >>file, "%s '%s'" % (r[0][0], r[1]),
+ else:
+ print >>file, "%s%s '%s'" % (r[0][1], r[0][0], r[1]),
+
+class Pipeline:
+ def __init__(self, commands, negate=False, pipe_err=False):
+ self.commands = commands
+ self.negate = negate
+ self.pipe_err = pipe_err
+
+ def __repr__(self):
+ return 'Pipeline(%r, %r, %r)' % (self.commands, self.negate,
+ self.pipe_err)
+
+ def __cmp__(self, other):
+ if not isinstance(other, Pipeline):
+ return -1
+
+ return cmp((self.commands, self.negate, self.pipe_err),
+ (other.commands, other.negate, self.pipe_err))
+
+ def toShell(self, file, pipefail=False):
+ if pipefail != self.pipe_err:
+ raise ValueError,'Inconsistent "pipefail" attribute!'
+ if self.negate:
+ print >>file, '!',
+ for cmd in self.commands:
+ cmd.toShell(file)
+ if cmd is not self.commands[-1]:
+ print >>file, '|\n ',
+
+class Seq:
+ def __init__(self, lhs, op, rhs):
+ assert op in (';', '&', '||', '&&')
+ self.op = op
+ self.lhs = lhs
+ self.rhs = rhs
+
+ def __repr__(self):
+ return 'Seq(%r, %r, %r)' % (self.lhs, self.op, self.rhs)
+
+ def __cmp__(self, other):
+ if not isinstance(other, Seq):
+ return -1
+
+ return cmp((self.lhs, self.op, self.rhs),
+ (other.lhs, other.op, other.rhs))
+
+ def toShell(self, file, pipefail=False):
+ self.lhs.toShell(file, pipefail)
+ print >>file, ' %s\n' % self.op
+ self.rhs.toShell(file, pipefail)
diff --git a/libclamav/c++/llvm/utils/lit/ShUtil.py b/libclamav/c++/llvm/utils/lit/ShUtil.py
new file mode 100644
index 0000000..c4bbb3d
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/ShUtil.py
@@ -0,0 +1,346 @@
+import itertools
+
+import Util
+from ShCommands import Command, Pipeline, Seq
+
+class ShLexer:
+ def __init__(self, data, win32Escapes = False):
+ self.data = data
+ self.pos = 0
+ self.end = len(data)
+ self.win32Escapes = win32Escapes
+
+ def eat(self):
+ c = self.data[self.pos]
+ self.pos += 1
+ return c
+
+ def look(self):
+ return self.data[self.pos]
+
+ def maybe_eat(self, c):
+ """
+ maybe_eat(c) - Consume the character c if it is the next character,
+ returning True if a character was consumed. """
+ if self.data[self.pos] == c:
+ self.pos += 1
+ return True
+ return False
+
+ def lex_arg_fast(self, c):
+ # Get the leading whitespace free section.
+ chunk = self.data[self.pos - 1:].split(None, 1)[0]
+
+ # If it has special characters, the fast path failed.
+ if ('|' in chunk or '&' in chunk or
+ '<' in chunk or '>' in chunk or
+ "'" in chunk or '"' in chunk or
+ '\\' in chunk):
+ return None
+
+ self.pos = self.pos - 1 + len(chunk)
+ return chunk
+
+ def lex_arg_slow(self, c):
+ if c in "'\"":
+ str = self.lex_arg_quoted(c)
+ else:
+ str = c
+ while self.pos != self.end:
+ c = self.look()
+ if c.isspace() or c in "|&":
+ break
+ elif c in '><':
+ # This is an annoying case; we treat '2>' as a single token so
+ # we don't have to track whitespace tokens.
+
+ # If the parse string isn't an integer, do the usual thing.
+ if not str.isdigit():
+ break
+
+ # Otherwise, lex the operator and convert to a redirection
+ # token.
+ num = int(str)
+ tok = self.lex_one_token()
+ assert isinstance(tok, tuple) and len(tok) == 1
+ return (tok[0], num)
+ elif c == '"':
+ self.eat()
+ str += self.lex_arg_quoted('"')
+ elif not self.win32Escapes and c == '\\':
+ # Outside of a string, '\\' escapes everything.
+ self.eat()
+ if self.pos == self.end:
+ Util.warning("escape at end of quoted argument in: %r" %
+ self.data)
+ return str
+ str += self.eat()
+ else:
+ str += self.eat()
+ return str
+
+ def lex_arg_quoted(self, delim):
+ str = ''
+ while self.pos != self.end:
+ c = self.eat()
+ if c == delim:
+ return str
+ elif c == '\\' and delim == '"':
+ # Inside a '"' quoted string, '\\' only escapes the quote
+ # character and backslash, otherwise it is preserved.
+ if self.pos == self.end:
+ Util.warning("escape at end of quoted argument in: %r" %
+ self.data)
+ return str
+ c = self.eat()
+ if c == '"': #
+ str += '"'
+ elif c == '\\':
+ str += '\\'
+ else:
+ str += '\\' + c
+ else:
+ str += c
+ Util.warning("missing quote character in %r" % self.data)
+ return str
+
+ def lex_arg_checked(self, c):
+ pos = self.pos
+ res = self.lex_arg_fast(c)
+ end = self.pos
+
+ self.pos = pos
+ reference = self.lex_arg_slow(c)
+ if res is not None:
+ if res != reference:
+ raise ValueError,"Fast path failure: %r != %r" % (res, reference)
+ if self.pos != end:
+ raise ValueError,"Fast path failure: %r != %r" % (self.pos, end)
+ return reference
+
+ def lex_arg(self, c):
+ return self.lex_arg_fast(c) or self.lex_arg_slow(c)
+
+ def lex_one_token(self):
+ """
+ lex_one_token - Lex a single 'sh' token. """
+
+ c = self.eat()
+ if c in ';!':
+ return (c,)
+ if c == '|':
+ if self.maybe_eat('|'):
+ return ('||',)
+ return (c,)
+ if c == '&':
+ if self.maybe_eat('&'):
+ return ('&&',)
+ if self.maybe_eat('>'):
+ return ('&>',)
+ return (c,)
+ if c == '>':
+ if self.maybe_eat('&'):
+ return ('>&',)
+ if self.maybe_eat('>'):
+ return ('>>',)
+ return (c,)
+ if c == '<':
+ if self.maybe_eat('&'):
+ return ('<&',)
+ if self.maybe_eat('>'):
+ return ('<<',)
+ return (c,)
+
+ return self.lex_arg(c)
+
+ def lex(self):
+ while self.pos != self.end:
+ if self.look().isspace():
+ self.eat()
+ else:
+ yield self.lex_one_token()
+
+###
+
+class ShParser:
+ def __init__(self, data, win32Escapes = False):
+ self.data = data
+ self.tokens = ShLexer(data, win32Escapes = win32Escapes).lex()
+
+ def lex(self):
+ try:
+ return self.tokens.next()
+ except StopIteration:
+ return None
+
+ def look(self):
+ next = self.lex()
+ if next is not None:
+ self.tokens = itertools.chain([next], self.tokens)
+ return next
+
+ def parse_command(self):
+ tok = self.lex()
+ if not tok:
+ raise ValueError,"empty command!"
+ if isinstance(tok, tuple):
+ raise ValueError,"syntax error near unexpected token %r" % tok[0]
+
+ args = [tok]
+ redirects = []
+ while 1:
+ tok = self.look()
+
+ # EOF?
+ if tok is None:
+ break
+
+ # If this is an argument, just add it to the current command.
+ if isinstance(tok, str):
+ args.append(self.lex())
+ continue
+
+ # Otherwise see if it is a terminator.
+ assert isinstance(tok, tuple)
+ if tok[0] in ('|',';','&','||','&&'):
+ break
+
+ # Otherwise it must be a redirection.
+ op = self.lex()
+ arg = self.lex()
+ if not arg:
+ raise ValueError,"syntax error near token %r" % op[0]
+ redirects.append((op, arg))
+
+ return Command(args, redirects)
+
+ def parse_pipeline(self):
+ negate = False
+ if self.look() == ('!',):
+ self.lex()
+ negate = True
+
+ commands = [self.parse_command()]
+ while self.look() == ('|',):
+ self.lex()
+ commands.append(self.parse_command())
+ return Pipeline(commands, negate)
+
+ def parse(self):
+ lhs = self.parse_pipeline()
+
+ while self.look():
+ operator = self.lex()
+ assert isinstance(operator, tuple) and len(operator) == 1
+
+ if not self.look():
+ raise ValueError, "missing argument to operator %r" % operator[0]
+
+ # FIXME: Operator precedence!!
+ lhs = Seq(lhs, operator[0], self.parse_pipeline())
+
+ return lhs
+
+###
+
+import unittest
+
+class TestShLexer(unittest.TestCase):
+ def lex(self, str, *args, **kwargs):
+ return list(ShLexer(str, *args, **kwargs).lex())
+
+ def test_basic(self):
+ self.assertEqual(self.lex('a|b>c&d<e'),
+ ['a', ('|',), 'b', ('>',), 'c', ('&',), 'd',
+ ('<',), 'e'])
+
+ def test_redirection_tokens(self):
+ self.assertEqual(self.lex('a2>c'),
+ ['a2', ('>',), 'c'])
+ self.assertEqual(self.lex('a 2>c'),
+ ['a', ('>',2), 'c'])
+
+ def test_quoting(self):
+ self.assertEqual(self.lex(""" 'a' """),
+ ['a'])
+ self.assertEqual(self.lex(""" "hello\\"world" """),
+ ['hello"world'])
+ self.assertEqual(self.lex(""" "hello\\'world" """),
+ ["hello\\'world"])
+ self.assertEqual(self.lex(""" "hello\\\\world" """),
+ ["hello\\world"])
+ self.assertEqual(self.lex(""" he"llo wo"rld """),
+ ["hello world"])
+ self.assertEqual(self.lex(""" a\\ b a\\\\b """),
+ ["a b", "a\\b"])
+ self.assertEqual(self.lex(""" "" "" """),
+ ["", ""])
+ self.assertEqual(self.lex(""" a\\ b """, win32Escapes = True),
+ ['a\\', 'b'])
+
+class TestShParse(unittest.TestCase):
+ def parse(self, str):
+ return ShParser(str).parse()
+
+ def test_basic(self):
+ self.assertEqual(self.parse('echo hello'),
+ Pipeline([Command(['echo', 'hello'], [])], False))
+ self.assertEqual(self.parse('echo ""'),
+ Pipeline([Command(['echo', ''], [])], False))
+
+ def test_redirection(self):
+ self.assertEqual(self.parse('echo hello > c'),
+ Pipeline([Command(['echo', 'hello'],
+ [((('>'),), 'c')])], False))
+ self.assertEqual(self.parse('echo hello > c >> d'),
+ Pipeline([Command(['echo', 'hello'], [(('>',), 'c'),
+ (('>>',), 'd')])], False))
+ self.assertEqual(self.parse('a 2>&1'),
+ Pipeline([Command(['a'], [(('>&',2), '1')])], False))
+
+ def test_pipeline(self):
+ self.assertEqual(self.parse('a | b'),
+ Pipeline([Command(['a'], []),
+ Command(['b'], [])],
+ False))
+
+ self.assertEqual(self.parse('a | b | c'),
+ Pipeline([Command(['a'], []),
+ Command(['b'], []),
+ Command(['c'], [])],
+ False))
+
+ self.assertEqual(self.parse('! a'),
+ Pipeline([Command(['a'], [])],
+ True))
+
+ def test_list(self):
+ self.assertEqual(self.parse('a ; b'),
+ Seq(Pipeline([Command(['a'], [])], False),
+ ';',
+ Pipeline([Command(['b'], [])], False)))
+
+ self.assertEqual(self.parse('a & b'),
+ Seq(Pipeline([Command(['a'], [])], False),
+ '&',
+ Pipeline([Command(['b'], [])], False)))
+
+ self.assertEqual(self.parse('a && b'),
+ Seq(Pipeline([Command(['a'], [])], False),
+ '&&',
+ Pipeline([Command(['b'], [])], False)))
+
+ self.assertEqual(self.parse('a || b'),
+ Seq(Pipeline([Command(['a'], [])], False),
+ '||',
+ Pipeline([Command(['b'], [])], False)))
+
+ self.assertEqual(self.parse('a && b || c'),
+ Seq(Seq(Pipeline([Command(['a'], [])], False),
+ '&&',
+ Pipeline([Command(['b'], [])], False)),
+ '||',
+ Pipeline([Command(['c'], [])], False)))
+
+if __name__ == '__main__':
+ unittest.main()
diff --git a/libclamav/c++/llvm/utils/lit/TODO b/libclamav/c++/llvm/utils/lit/TODO
new file mode 100644
index 0000000..4d00d2c
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/TODO
@@ -0,0 +1,19 @@
+ - Move temp directory name into local test config.
+
+ - Add --show-unsupported, don't show by default?
+
+ - Finish documentation.
+
+ - Optionally use multiprocessing.
+
+ - Support llvmc and ocaml tests.
+
+ - Support valgrind in all configs, and LLVM style valgrind.
+
+ - Provide test suite config for running unit tests.
+
+ - Support a timeout / ulimit.
+
+ - Support "disabling" tests? The advantage of making this distinct from XFAIL
+ is it makes it more obvious that it is a temporary measure (and lit can put
+ in a separate category).
diff --git a/libclamav/c++/llvm/utils/lit/TclUtil.py b/libclamav/c++/llvm/utils/lit/TclUtil.py
new file mode 100644
index 0000000..4a3f345
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/TclUtil.py
@@ -0,0 +1,322 @@
+import itertools
+
+from ShCommands import Command, Pipeline
+
+def tcl_preprocess(data):
+ # Tcl has a preprocessing step to replace escaped newlines.
+ i = data.find('\\\n')
+ if i == -1:
+ return data
+
+ # Replace '\\\n' and subsequent whitespace by a single space.
+ n = len(data)
+ str = data[:i]
+ i += 2
+ while i < n and data[i] in ' \t':
+ i += 1
+ return str + ' ' + data[i:]
+
+class TclLexer:
+ """TclLexer - Lex a string into "words", following the Tcl syntax."""
+
+ def __init__(self, data):
+ self.data = tcl_preprocess(data)
+ self.pos = 0
+ self.end = len(self.data)
+
+ def at_end(self):
+ return self.pos == self.end
+
+ def eat(self):
+ c = self.data[self.pos]
+ self.pos += 1
+ return c
+
+ def look(self):
+ return self.data[self.pos]
+
+ def maybe_eat(self, c):
+ """
+ maybe_eat(c) - Consume the character c if it is the next character,
+ returning True if a character was consumed. """
+ if self.data[self.pos] == c:
+ self.pos += 1
+ return True
+ return False
+
+ def escape(self, c):
+ if c == 'a':
+ return '\x07'
+ elif c == 'b':
+ return '\x08'
+ elif c == 'f':
+ return '\x0c'
+ elif c == 'n':
+ return '\n'
+ elif c == 'r':
+ return '\r'
+ elif c == 't':
+ return '\t'
+ elif c == 'v':
+ return '\x0b'
+ elif c in 'uxo':
+ raise ValueError,'Invalid quoted character %r' % c
+ else:
+ return c
+
+ def lex_braced(self):
+ # Lex until whitespace or end of string, the opening brace has already
+ # been consumed.
+
+ str = ''
+ while 1:
+ if self.at_end():
+ raise ValueError,"Unterminated '{' quoted word"
+
+ c = self.eat()
+ if c == '}':
+ break
+ elif c == '{':
+ str += '{' + self.lex_braced() + '}'
+ elif c == '\\' and self.look() in '{}':
+ str += self.eat()
+ else:
+ str += c
+
+ return str
+
+ def lex_quoted(self):
+ str = ''
+
+ while 1:
+ if self.at_end():
+ raise ValueError,"Unterminated '\"' quoted word"
+
+ c = self.eat()
+ if c == '"':
+ break
+ elif c == '\\':
+ if self.at_end():
+ raise ValueError,'Missing quoted character'
+
+ str += self.escape(self.eat())
+ else:
+ str += c
+
+ return str
+
+ def lex_unquoted(self, process_all=False):
+ # Lex until whitespace or end of string.
+ str = ''
+ while not self.at_end():
+ if not process_all:
+ if self.look().isspace() or self.look() == ';':
+ break
+
+ c = self.eat()
+ if c == '\\':
+ if self.at_end():
+ raise ValueError,'Missing quoted character'
+
+ str += self.escape(self.eat())
+ elif c == '[':
+ raise NotImplementedError, ('Command substitution is '
+ 'not supported')
+ elif c == '$' and not self.at_end() and (self.look().isalpha() or
+ self.look() == '{'):
+ raise NotImplementedError, ('Variable substitution is '
+ 'not supported')
+ else:
+ str += c
+
+ return str
+
+ def lex_one_token(self):
+ if self.maybe_eat('"'):
+ return self.lex_quoted()
+ elif self.maybe_eat('{'):
+ # Check for argument substitution.
+ if not self.maybe_eat('*'):
+ return self.lex_braced()
+
+ if not self.maybe_eat('}'):
+ return '*' + self.lex_braced()
+
+ if self.at_end() or self.look().isspace():
+ return '*'
+
+ raise NotImplementedError, "Argument substitution is unsupported"
+ else:
+ return self.lex_unquoted()
+
+ def lex(self):
+ while not self.at_end():
+ c = self.look()
+ if c in ' \t':
+ self.eat()
+ elif c in ';\n':
+ self.eat()
+ yield (';',)
+ else:
+ yield self.lex_one_token()
+
+class TclExecCommand:
+ kRedirectPrefixes1 = ('<', '>')
+ kRedirectPrefixes2 = ('<@', '<<', '2>', '>&', '>>', '>@')
+ kRedirectPrefixes3 = ('2>@', '2>>', '>>&', '>&@')
+ kRedirectPrefixes4 = ('2>@1',)
+
+ def __init__(self, args):
+ self.args = iter(args)
+
+ def lex(self):
+ try:
+ return self.args.next()
+ except StopIteration:
+ return None
+
+ def look(self):
+ next = self.lex()
+ if next is not None:
+ self.args = itertools.chain([next], self.args)
+ return next
+
+ def parse_redirect(self, tok, length):
+ if len(tok) == length:
+ arg = self.lex()
+ if arg is None:
+ raise ValueError,'Missing argument to %r redirection' % tok
+ else:
+ tok,arg = tok[:length],tok[length:]
+
+ if tok[0] == '2':
+ op = (tok[1:],2)
+ else:
+ op = (tok,)
+ return (op, arg)
+
+ def parse_pipeline(self):
+ if self.look() is None:
+ raise ValueError,"Expected at least one argument to exec"
+
+ commands = [Command([],[])]
+ while 1:
+ arg = self.lex()
+ if arg is None:
+ break
+ elif arg == '|':
+ commands.append(Command([],[]))
+ elif arg == '|&':
+ # Write this as a redirect of stderr; it must come first because
+ # stdout may have already been redirected.
+ commands[-1].redirects.insert(0, (('>&',2),'1'))
+ commands.append(Command([],[]))
+ elif arg[:4] in TclExecCommand.kRedirectPrefixes4:
+ commands[-1].redirects.append(self.parse_redirect(arg, 4))
+ elif arg[:3] in TclExecCommand.kRedirectPrefixes3:
+ commands[-1].redirects.append(self.parse_redirect(arg, 3))
+ elif arg[:2] in TclExecCommand.kRedirectPrefixes2:
+ commands[-1].redirects.append(self.parse_redirect(arg, 2))
+ elif arg[:1] in TclExecCommand.kRedirectPrefixes1:
+ commands[-1].redirects.append(self.parse_redirect(arg, 1))
+ else:
+ commands[-1].args.append(arg)
+
+ return Pipeline(commands, False, pipe_err=True)
+
+ def parse(self):
+ ignoreStderr = False
+ keepNewline = False
+
+ # Parse arguments.
+ while 1:
+ next = self.look()
+ if not isinstance(next, str) or next[0] != '-':
+ break
+
+ if next == '--':
+ self.lex()
+ break
+ elif next == '-ignorestderr':
+ ignoreStderr = True
+ elif next == '-keepnewline':
+ keepNewline = True
+ else:
+ raise ValueError,"Invalid exec argument %r" % next
+
+ return (ignoreStderr, keepNewline, self.parse_pipeline())
+
+###
+
+import unittest
+
+class TestTclLexer(unittest.TestCase):
+ def lex(self, str, *args, **kwargs):
+ return list(TclLexer(str, *args, **kwargs).lex())
+
+ def test_preprocess(self):
+ self.assertEqual(tcl_preprocess('a b'), 'a b')
+ self.assertEqual(tcl_preprocess('a\\\nb c'), 'a b c')
+
+ def test_unquoted(self):
+ self.assertEqual(self.lex('a b c'),
+ ['a', 'b', 'c'])
+ self.assertEqual(self.lex(r'a\nb\tc\ '),
+ ['a\nb\tc '])
+ self.assertEqual(self.lex(r'a \\\$b c $\\'),
+ ['a', r'\$b', 'c', '$\\'])
+
+ def test_braced(self):
+ self.assertEqual(self.lex('a {b c} {}'),
+ ['a', 'b c', ''])
+ self.assertEqual(self.lex(r'a {b {c\n}}'),
+ ['a', 'b {c\\n}'])
+ self.assertEqual(self.lex(r'a {b\{}'),
+ ['a', 'b{'])
+ self.assertEqual(self.lex(r'{*}'), ['*'])
+ self.assertEqual(self.lex(r'{*} a'), ['*', 'a'])
+ self.assertEqual(self.lex(r'{*} a'), ['*', 'a'])
+ self.assertEqual(self.lex('{a\\\n b}'),
+ ['a b'])
+
+ def test_quoted(self):
+ self.assertEqual(self.lex('a "b c"'),
+ ['a', 'b c'])
+
+ def test_terminators(self):
+ self.assertEqual(self.lex('a\nb'),
+ ['a', (';',), 'b'])
+ self.assertEqual(self.lex('a;b'),
+ ['a', (';',), 'b'])
+ self.assertEqual(self.lex('a ; b'),
+ ['a', (';',), 'b'])
+
+class TestTclExecCommand(unittest.TestCase):
+ def parse(self, str):
+ return TclExecCommand(list(TclLexer(str).lex())).parse()
+
+ def test_basic(self):
+ self.assertEqual(self.parse('echo hello'),
+ (False, False,
+ Pipeline([Command(['echo', 'hello'], [])],
+ False, True)))
+ self.assertEqual(self.parse('echo hello | grep hello'),
+ (False, False,
+ Pipeline([Command(['echo', 'hello'], []),
+ Command(['grep', 'hello'], [])],
+ False, True)))
+
+ def test_redirect(self):
+ self.assertEqual(self.parse('echo hello > a >b >>c 2> d |& e'),
+ (False, False,
+ Pipeline([Command(['echo', 'hello'],
+ [(('>&',2),'1'),
+ (('>',),'a'),
+ (('>',),'b'),
+ (('>>',),'c'),
+ (('>',2),'d')]),
+ Command(['e'], [])],
+ False, True)))
+
+if __name__ == '__main__':
+ unittest.main()
diff --git a/libclamav/c++/llvm/utils/lit/Test.py b/libclamav/c++/llvm/utils/lit/Test.py
new file mode 100644
index 0000000..d3f6274
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/Test.py
@@ -0,0 +1,71 @@
+import os
+
+# Test results.
+
+class TestResult:
+ def __init__(self, name, isFailure):
+ self.name = name
+ self.isFailure = isFailure
+
+PASS = TestResult('PASS', False)
+XFAIL = TestResult('XFAIL', False)
+FAIL = TestResult('FAIL', True)
+XPASS = TestResult('XPASS', True)
+UNRESOLVED = TestResult('UNRESOLVED', True)
+UNSUPPORTED = TestResult('UNSUPPORTED', False)
+
+# Test classes.
+
+class TestFormat:
+ """TestFormat - Test information provider."""
+
+ def __init__(self, name):
+ self.name = name
+
+class TestSuite:
+ """TestSuite - Information on a group of tests.
+
+ A test suite groups together a set of logically related tests.
+ """
+
+ def __init__(self, name, source_root, exec_root, config):
+ self.name = name
+ self.source_root = source_root
+ self.exec_root = exec_root
+ # The test suite configuration.
+ self.config = config
+
+ def getSourcePath(self, components):
+ return os.path.join(self.source_root, *components)
+
+ def getExecPath(self, components):
+ return os.path.join(self.exec_root, *components)
+
+class Test:
+ """Test - Information on a single test instance."""
+
+ def __init__(self, suite, path_in_suite, config):
+ self.suite = suite
+ self.path_in_suite = path_in_suite
+ self.config = config
+ # The test result code, once complete.
+ self.result = None
+ # Any additional output from the test, once complete.
+ self.output = None
+ # The wall time to execute this test, if timing and once complete.
+ self.elapsed = None
+
+ def setResult(self, result, output, elapsed):
+ assert self.result is None, "Test result already set!"
+ self.result = result
+ self.output = output
+ self.elapsed = elapsed
+
+ def getFullName(self):
+ return self.suite.config.name + '::' + '/'.join(self.path_in_suite)
+
+ def getSourcePath(self):
+ return self.suite.getSourcePath(self.path_in_suite)
+
+ def getExecPath(self):
+ return self.suite.getExecPath(self.path_in_suite)
diff --git a/libclamav/c++/llvm/utils/lit/TestFormats.py b/libclamav/c++/llvm/utils/lit/TestFormats.py
new file mode 100644
index 0000000..61bdb18
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/TestFormats.py
@@ -0,0 +1,144 @@
+import os
+
+import Test
+import TestRunner
+import Util
+
+class GoogleTest(object):
+ def __init__(self, test_sub_dir, test_suffix):
+ self.test_sub_dir = str(test_sub_dir)
+ self.test_suffix = str(test_suffix)
+
+ def getGTestTests(self, path):
+ """getGTestTests(path) - [name]
+
+ Return the tests available in gtest executable."""
+
+ lines = Util.capture([path, '--gtest_list_tests']).split('\n')
+ nested_tests = []
+ for ln in lines:
+ if not ln.strip():
+ continue
+
+ prefix = ''
+ index = 0
+ while ln[index*2:index*2+2] == ' ':
+ index += 1
+ while len(nested_tests) > index:
+ nested_tests.pop()
+
+ ln = ln[index*2:]
+ if ln.endswith('.'):
+ nested_tests.append(ln)
+ else:
+ yield ''.join(nested_tests) + ln
+
+ def getTestsInDirectory(self, testSuite, path_in_suite,
+ litConfig, localConfig):
+ source_path = testSuite.getSourcePath(path_in_suite)
+ for filename in os.listdir(source_path):
+ # Check for the one subdirectory (build directory) tests will be in.
+ if filename != self.test_sub_dir:
+ continue
+
+ filepath = os.path.join(source_path, filename)
+ for subfilename in os.listdir(filepath):
+ if subfilename.endswith(self.test_suffix):
+ execpath = os.path.join(filepath, subfilename)
+
+ # Discover the tests in this executable.
+ for name in self.getGTestTests(execpath):
+ testPath = path_in_suite + (filename, subfilename, name)
+ yield Test.Test(testSuite, testPath, localConfig)
+
+ def execute(self, test, litConfig):
+ testPath,testName = os.path.split(test.getSourcePath())
+
+ cmd = [testPath, '--gtest_filter=' + testName]
+ out, err, exitCode = TestRunner.executeCommand(cmd)
+
+ if not exitCode:
+ return Test.PASS,''
+
+ return Test.FAIL, out + err
+
+###
+
+class FileBasedTest(object):
+ def getTestsInDirectory(self, testSuite, path_in_suite,
+ litConfig, localConfig):
+ source_path = testSuite.getSourcePath(path_in_suite)
+ for filename in os.listdir(source_path):
+ filepath = os.path.join(source_path, filename)
+ if not os.path.isdir(filepath):
+ base,ext = os.path.splitext(filename)
+ if ext in localConfig.suffixes:
+ yield Test.Test(testSuite, path_in_suite + (filename,),
+ localConfig)
+
+class ShTest(FileBasedTest):
+ def __init__(self, execute_external = False, require_and_and = False):
+ self.execute_external = execute_external
+ self.require_and_and = require_and_and
+
+ def execute(self, test, litConfig):
+ return TestRunner.executeShTest(test, litConfig,
+ self.execute_external,
+ self.require_and_and)
+
+class TclTest(FileBasedTest):
+ def execute(self, test, litConfig):
+ return TestRunner.executeTclTest(test, litConfig)
+
+###
+
+import re
+import tempfile
+
+class SyntaxCheckTest:
+ # FIXME: Refactor into generic test for running some command on a directory
+ # of inputs.
+
+ def __init__(self, compiler, dir, recursive, pattern, extra_cxx_args=[]):
+ self.compiler = str(compiler)
+ self.dir = str(dir)
+ self.recursive = bool(recursive)
+ self.pattern = re.compile(pattern)
+ self.extra_cxx_args = list(extra_cxx_args)
+
+ def getTestsInDirectory(self, testSuite, path_in_suite,
+ litConfig, localConfig):
+ for dirname,subdirs,filenames in os.walk(self.dir):
+ if not self.recursive:
+ subdirs[:] = []
+
+ for filename in filenames:
+ if (not self.pattern.match(filename) or
+ filename in localConfig.excludes):
+ continue
+
+ path = os.path.join(dirname,filename)
+ suffix = path[len(self.dir):]
+ if suffix.startswith(os.sep):
+ suffix = suffix[1:]
+ test = Test.Test(testSuite,
+ path_in_suite + tuple(suffix.split(os.sep)),
+ localConfig)
+ # FIXME: Hack?
+ test.source_path = path
+ yield test
+
+ def execute(self, test, litConfig):
+ tmp = tempfile.NamedTemporaryFile(suffix='.cpp')
+ print >>tmp, '#include "%s"' % test.source_path
+ tmp.flush()
+
+ cmd = [self.compiler, '-x', 'c++', '-fsyntax-only', tmp.name]
+ cmd.extend(self.extra_cxx_args)
+ out, err, exitCode = TestRunner.executeCommand(cmd)
+
+ diags = out + err
+ if not exitCode and not diags.strip():
+ return Test.PASS,''
+
+ return Test.FAIL, diags
diff --git a/libclamav/c++/llvm/utils/lit/TestRunner.py b/libclamav/c++/llvm/utils/lit/TestRunner.py
new file mode 100644
index 0000000..7b549ac
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/TestRunner.py
@@ -0,0 +1,505 @@
+import os, signal, subprocess, sys
+import StringIO
+
+import ShUtil
+import Test
+import Util
+
+import platform
+import tempfile
+
+class InternalShellError(Exception):
+ def __init__(self, command, message):
+ self.command = command
+ self.message = message
+
+# Don't use close_fds on Windows.
+kUseCloseFDs = platform.system() != 'Windows'
+def executeCommand(command, cwd=None, env=None):
+ p = subprocess.Popen(command, cwd=cwd,
+ stdin=subprocess.PIPE,
+ stdout=subprocess.PIPE,
+ stderr=subprocess.PIPE,
+ env=env)
+ out,err = p.communicate()
+ exitCode = p.wait()
+
+ # Detect Ctrl-C in subprocess.
+ if exitCode == -signal.SIGINT:
+ raise KeyboardInterrupt
+
+ return out, err, exitCode
+
+def executeShCmd(cmd, cfg, cwd, results):
+ if isinstance(cmd, ShUtil.Seq):
+ if cmd.op == ';':
+ res = executeShCmd(cmd.lhs, cfg, cwd, results)
+ return executeShCmd(cmd.rhs, cfg, cwd, results)
+
+ if cmd.op == '&':
+ raise NotImplementedError,"unsupported test command: '&'"
+
+ if cmd.op == '||':
+ res = executeShCmd(cmd.lhs, cfg, cwd, results)
+ if res != 0:
+ res = executeShCmd(cmd.rhs, cfg, cwd, results)
+ return res
+ if cmd.op == '&&':
+ res = executeShCmd(cmd.lhs, cfg, cwd, results)
+ if res is None:
+ return res
+
+ if res == 0:
+ res = executeShCmd(cmd.rhs, cfg, cwd, results)
+ return res
+
+ raise ValueError,'Unknown shell command: %r' % cmd.op
+
+ assert isinstance(cmd, ShUtil.Pipeline)
+ procs = []
+ input = subprocess.PIPE
+ stderrTempFiles = []
+ # To avoid deadlock, we use a single stderr stream for piped
+ # output. This is null until we have seen some output using
+ # stderr.
+ for i,j in enumerate(cmd.commands):
+ redirects = [(0,), (1,), (2,)]
+ for r in j.redirects:
+ if r[0] == ('>',2):
+ redirects[2] = [r[1], 'w', None]
+ elif r[0] == ('>&',2) and r[1] in '012':
+ redirects[2] = redirects[int(r[1])]
+ elif r[0] == ('>&',) or r[0] == ('&>',):
+ redirects[1] = redirects[2] = [r[1], 'w', None]
+ elif r[0] == ('>',):
+ redirects[1] = [r[1], 'w', None]
+ elif r[0] == ('<',):
+ redirects[0] = [r[1], 'r', None]
+ else:
+ raise NotImplementedError,"Unsupported redirect: %r" % (r,)
+
+ final_redirects = []
+ for index,r in enumerate(redirects):
+ if r == (0,):
+ result = input
+ elif r == (1,):
+ if index == 0:
+ raise NotImplementedError,"Unsupported redirect for stdin"
+ elif index == 1:
+ result = subprocess.PIPE
+ else:
+ result = subprocess.STDOUT
+ elif r == (2,):
+ if index != 2:
+ raise NotImplementedError,"Unsupported redirect on stdout"
+ result = subprocess.PIPE
+ else:
+ if r[2] is None:
+ r[2] = open(r[0], r[1])
+ result = r[2]
+ final_redirects.append(result)
+
+ stdin, stdout, stderr = final_redirects
+
+ # If stderr wants to come from stdout, but stdout isn't a pipe, then put
+ # stderr on a pipe and treat it as stdout.
+ if (stderr == subprocess.STDOUT and stdout != subprocess.PIPE):
+ stderr = subprocess.PIPE
+ stderrIsStdout = True
+ else:
+ stderrIsStdout = False
+
+ # Don't allow stderr on a PIPE except for the last
+ # process, this could deadlock.
+ #
+ # FIXME: This is slow, but so is deadlock.
+ if stderr == subprocess.PIPE and j != cmd.commands[-1]:
+ stderr = tempfile.TemporaryFile(mode='w+b')
+ stderrTempFiles.append((i, stderr))
+
+ # Resolve the executable path ourselves.
+ args = list(j.args)
+ args[0] = Util.which(args[0], cfg.environment['PATH'])
+ if not args[0]:
+ raise InternalShellError(j, '%r: command not found' % j.args[0])
+
+ procs.append(subprocess.Popen(args, cwd=cwd,
+ stdin = stdin,
+ stdout = stdout,
+ stderr = stderr,
+ env = cfg.environment,
+ close_fds = kUseCloseFDs))
+
+ # Immediately close stdin for any process taking stdin from us.
+ if stdin == subprocess.PIPE:
+ procs[-1].stdin.close()
+ procs[-1].stdin = None
+
+ # Update the current stdin source.
+ if stdout == subprocess.PIPE:
+ input = procs[-1].stdout
+ elif stderrIsStdout:
+ input = procs[-1].stderr
+ else:
+ input = subprocess.PIPE
+
+ # FIXME: There is probably still deadlock potential here. Yawn.
+ procData = [None] * len(procs)
+ procData[-1] = procs[-1].communicate()
+
+ for i in range(len(procs) - 1):
+ if procs[i].stdout is not None:
+ out = procs[i].stdout.read()
+ else:
+ out = ''
+ if procs[i].stderr is not None:
+ err = procs[i].stderr.read()
+ else:
+ err = ''
+ procData[i] = (out,err)
+
+ # Read stderr out of the temp files.
+ for i,f in stderrTempFiles:
+ f.seek(0, 0)
+ procData[i] = (procData[i][0], f.read())
+
+ exitCode = None
+ for i,(out,err) in enumerate(procData):
+ res = procs[i].wait()
+ # Detect Ctrl-C in subprocess.
+ if res == -signal.SIGINT:
+ raise KeyboardInterrupt
+
+ results.append((cmd.commands[i], out, err, res))
+ if cmd.pipe_err:
+ # Python treats the exit code as a signed char.
+ if res < 0:
+ exitCode = min(exitCode, res)
+ else:
+ exitCode = max(exitCode, res)
+ else:
+ exitCode = res
+
+ if cmd.negate:
+ exitCode = not exitCode
+
+ return exitCode
+
+def executeScriptInternal(test, litConfig, tmpBase, commands, cwd):
+ ln = ' &&\n'.join(commands)
+ try:
+ cmd = ShUtil.ShParser(ln, litConfig.isWindows).parse()
+ except:
+ return (Test.FAIL, "shell parser error on: %r" % ln)
+
+ results = []
+ try:
+ exitCode = executeShCmd(cmd, test.config, cwd, results)
+ except InternalShellError,e:
+ out = ''
+ err = e.message
+ exitCode = 255
+
+ out = err = ''
+ for i,(cmd, cmd_out,cmd_err,res) in enumerate(results):
+ out += 'Command %d: %s\n' % (i, ' '.join('"%s"' % s for s in cmd.args))
+ out += 'Command %d Result: %r\n' % (i, res)
+ out += 'Command %d Output:\n%s\n\n' % (i, cmd_out)
+ out += 'Command %d Stderr:\n%s\n\n' % (i, cmd_err)
+
+ return out, err, exitCode
+
+def executeTclScriptInternal(test, litConfig, tmpBase, commands, cwd):
+ import TclUtil
+ cmds = []
+ for ln in commands:
+ # Given the unfortunate way LLVM's test are written, the line gets
+ # backslash substitution done twice.
+ ln = TclUtil.TclLexer(ln).lex_unquoted(process_all = True)
+
+ try:
+ tokens = list(TclUtil.TclLexer(ln).lex())
+ except:
+ return (Test.FAIL, "Tcl lexer error on: %r" % ln)
+
+ # Validate there are no control tokens.
+ for t in tokens:
+ if not isinstance(t, str):
+ return (Test.FAIL,
+ "Invalid test line: %r containing %r" % (ln, t))
+
+ try:
+ cmds.append(TclUtil.TclExecCommand(tokens).parse_pipeline())
+ except:
+ return (Test.FAIL, "Tcl 'exec' parse error on: %r" % ln)
+
+ cmd = cmds[0]
+ for c in cmds[1:]:
+ cmd = ShUtil.Seq(cmd, '&&', c)
+
+ if litConfig.useTclAsSh:
+ script = tmpBase + '.script'
+
+ # Write script file
+ f = open(script,'w')
+ print >>f, 'set -o pipefail'
+ cmd.toShell(f, pipefail = True)
+ f.close()
+
+ if 0:
+ print >>sys.stdout, cmd
+ print >>sys.stdout, open(script).read()
+ print >>sys.stdout
+ return '', '', 0
+
+ command = ['/bin/bash', script]
+ out,err,exitCode = executeCommand(command, cwd=cwd,
+ env=test.config.environment)
+
+ # Tcl commands fail on standard error output.
+ if err:
+ exitCode = 1
+ out = 'Command has output on stderr!\n\n' + out
+
+ return out,err,exitCode
+ else:
+ results = []
+ try:
+ exitCode = executeShCmd(cmd, test.config, cwd, results)
+ except InternalShellError,e:
+ results.append((e.command, '', e.message + '\n', 255))
+ exitCode = 255
+
+ out = err = ''
+
+ # Tcl commands fail on standard error output.
+ if [True for _,_,err,res in results if err]:
+ exitCode = 1
+ out += 'Command has output on stderr!\n\n'
+
+ for i,(cmd, cmd_out, cmd_err, res) in enumerate(results):
+ out += 'Command %d: %s\n' % (i, ' '.join('"%s"' % s for s in cmd.args))
+ out += 'Command %d Result: %r\n' % (i, res)
+ out += 'Command %d Output:\n%s\n\n' % (i, cmd_out)
+ out += 'Command %d Stderr:\n%s\n\n' % (i, cmd_err)
+
+ return out, err, exitCode
+
+def executeScript(test, litConfig, tmpBase, commands, cwd):
+ script = tmpBase + '.script'
+ if litConfig.isWindows:
+ script += '.bat'
+
+ # Write script file
+ f = open(script,'w')
+ if litConfig.isWindows:
+ f.write('\nif %ERRORLEVEL% NEQ 0 EXIT\n'.join(commands))
+ else:
+ f.write(' &&\n'.join(commands))
+ f.write('\n')
+ f.close()
+
+ if litConfig.isWindows:
+ command = ['cmd','/c', script]
+ else:
+ command = ['/bin/sh', script]
+ if litConfig.useValgrind:
+ # FIXME: Running valgrind on sh is overkill. We probably could just
+ # run on clang with no real loss.
+ valgrindArgs = ['valgrind', '-q',
+ '--tool=memcheck', '--trace-children=yes',
+ '--error-exitcode=123']
+ valgrindArgs.extend(litConfig.valgrindArgs)
+
+ command = valgrindArgs + command
+
+ return executeCommand(command, cwd=cwd, env=test.config.environment)
+
+def parseIntegratedTestScript(test, xfailHasColon, requireAndAnd):
+ """parseIntegratedTestScript - Scan an LLVM/Clang style integrated test
+ script and extract the lines to 'RUN' as well as 'XFAIL' and 'XTARGET'
+ information. The RUN lines also will have variable substitution performed.
+ """
+
+ # Get the temporary location, this is always relative to the test suite
+ # root, not test source root.
+ #
+ # FIXME: This should not be here?
+ sourcepath = test.getSourcePath()
+ execpath = test.getExecPath()
+ execdir,execbase = os.path.split(execpath)
+ tmpBase = os.path.join(execdir, 'Output', execbase)
+
+ # We use #_MARKER_# to hide %% while we do the other substitutions.
+ substitutions = [('%%', '#_MARKER_#')]
+ substitutions.extend(test.config.substitutions)
+ substitutions.extend([('%s', sourcepath),
+ ('%S', os.path.dirname(sourcepath)),
+ ('%p', os.path.dirname(sourcepath)),
+ ('%t', tmpBase + '.tmp'),
+ # FIXME: Remove this once we kill DejaGNU.
+ ('%abs_tmp', tmpBase + '.tmp'),
+ ('#_MARKER_#', '%')])
+
+ # Collect the test lines from the script.
+ script = []
+ xfails = []
+ xtargets = []
+ for ln in open(sourcepath):
+ if 'RUN:' in ln:
+ # Isolate the command to run.
+ index = ln.index('RUN:')
+ ln = ln[index+4:]
+
+ # Trim trailing whitespace.
+ ln = ln.rstrip()
+
+ # Collapse lines with trailing '\\'.
+ if script and script[-1][-1] == '\\':
+ script[-1] = script[-1][:-1] + ln
+ else:
+ script.append(ln)
+ elif xfailHasColon and 'XFAIL:' in ln:
+ items = ln[ln.index('XFAIL:') + 6:].split(',')
+ xfails.extend([s.strip() for s in items])
+ elif not xfailHasColon and 'XFAIL' in ln:
+ items = ln[ln.index('XFAIL') + 5:].split(',')
+ xfails.extend([s.strip() for s in items])
+ elif 'XTARGET:' in ln:
+ items = ln[ln.index('XTARGET:') + 8:].split(',')
+ xtargets.extend([s.strip() for s in items])
+ elif 'END.' in ln:
+ # Check for END. lines.
+ if ln[ln.index('END.'):].strip() == 'END.':
+ break
+
+ # Apply substitutions to the script.
+ def processLine(ln):
+ # Apply substitutions
+ for a,b in substitutions:
+ ln = ln.replace(a,b)
+
+ # Strip the trailing newline and any extra whitespace.
+ return ln.strip()
+ script = map(processLine, script)
+
+ # Verify the script contains a run line.
+ if not script:
+ return (Test.UNRESOLVED, "Test has no run line!")
+
+ if script[-1][-1] == '\\':
+ return (Test.UNRESOLVED, "Test has unterminated run lines (with '\\')")
+
+ # Validate interior lines for '&&', a lovely historical artifact.
+ if requireAndAnd:
+ for i in range(len(script) - 1):
+ ln = script[i]
+
+ if not ln.endswith('&&'):
+ return (Test.FAIL,
+ ("MISSING \'&&\': %s\n" +
+ "FOLLOWED BY : %s\n") % (ln, script[i + 1]))
+
+ # Strip off '&&'
+ script[i] = ln[:-2]
+
+ return script,xfails,xtargets,tmpBase,execdir
+
+def formatTestOutput(status, out, err, exitCode, script):
+ output = StringIO.StringIO()
+ print >>output, "Script:"
+ print >>output, "--"
+ print >>output, '\n'.join(script)
+ print >>output, "--"
+ print >>output, "Exit Code: %r" % exitCode
+ print >>output, "Command Output (stdout):"
+ print >>output, "--"
+ output.write(out)
+ print >>output, "--"
+ print >>output, "Command Output (stderr):"
+ print >>output, "--"
+ output.write(err)
+ print >>output, "--"
+ return (status, output.getvalue())
+
+def executeTclTest(test, litConfig):
+ if test.config.unsupported:
+ return (Test.UNSUPPORTED, 'Test is unsupported')
+
+ res = parseIntegratedTestScript(test, True, False)
+ if len(res) == 2:
+ return res
+
+ script, xfails, xtargets, tmpBase, execdir = res
+
+ if litConfig.noExecute:
+ return (Test.PASS, '')
+
+ # Create the output directory if it does not already exist.
+ Util.mkdir_p(os.path.dirname(tmpBase))
+
+ res = executeTclScriptInternal(test, litConfig, tmpBase, script, execdir)
+ if len(res) == 2:
+ return res
+
+ isXFail = False
+ for item in xfails:
+ if item == '*' or item in test.suite.config.target_triple:
+ isXFail = True
+ break
+
+ # If this is XFAIL, see if it is expected to pass on this target.
+ if isXFail:
+ for item in xtargets:
+ if item == '*' or item in test.suite.config.target_triple:
+ isXFail = False
+ break
+
+ out,err,exitCode = res
+ if isXFail:
+ ok = exitCode != 0
+ status = (Test.XPASS, Test.XFAIL)[ok]
+ else:
+ ok = exitCode == 0
+ status = (Test.FAIL, Test.PASS)[ok]
+
+ if ok:
+ return (status,'')
+
+ return formatTestOutput(status, out, err, exitCode, script)
+
+def executeShTest(test, litConfig, useExternalSh, requireAndAnd):
+ if test.config.unsupported:
+ return (Test.UNSUPPORTED, 'Test is unsupported')
+
+ res = parseIntegratedTestScript(test, False, requireAndAnd)
+ if len(res) == 2:
+ return res
+
+ script, xfails, xtargets, tmpBase, execdir = res
+
+ if litConfig.noExecute:
+ return (Test.PASS, '')
+
+ # Create the output directory if it does not already exist.
+ Util.mkdir_p(os.path.dirname(tmpBase))
+
+ if useExternalSh:
+ res = executeScript(test, litConfig, tmpBase, script, execdir)
+ else:
+ res = executeScriptInternal(test, litConfig, tmpBase, script, execdir)
+ if len(res) == 2:
+ return res
+
+ out,err,exitCode = res
+ if xfails:
+ ok = exitCode != 0
+ status = (Test.XPASS, Test.XFAIL)[ok]
+ else:
+ ok = exitCode == 0
+ status = (Test.FAIL, Test.PASS)[ok]
+
+ if ok:
+ return (status,'')
+
+ return formatTestOutput(status, out, err, exitCode, script)
diff --git a/libclamav/c++/llvm/utils/lit/TestingConfig.py b/libclamav/c++/llvm/utils/lit/TestingConfig.py
new file mode 100644
index 0000000..e4874d7
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/TestingConfig.py
@@ -0,0 +1,96 @@
+import os
+
+class TestingConfig:
+ """"
+ TestingConfig - Information on the tests inside a suite.
+ """
+
+ @staticmethod
+ def frompath(path, parent, litConfig, mustExist, config = None):
+ if config is None:
+ # Set the environment based on the command line arguments.
+ environment = {
+ 'PATH' : os.pathsep.join(litConfig.path +
+ [os.environ.get('PATH','')]),
+ 'SYSTEMROOT' : os.environ.get('SYSTEMROOT',''),
+ 'LLVM_DISABLE_CRT_DEBUG' : '1',
+ }
+
+ config = TestingConfig(parent,
+ name = '<unnamed>',
+ suffixes = set(),
+ test_format = None,
+ environment = environment,
+ substitutions = [],
+ unsupported = False,
+ on_clone = None,
+ test_exec_root = None,
+ test_source_root = None,
+ excludes = [])
+
+ if os.path.exists(path):
+ # FIXME: Improve detection and error reporting of errors in the
+ # config file.
+ f = open(path)
+ cfg_globals = dict(globals())
+ cfg_globals['config'] = config
+ cfg_globals['lit'] = litConfig
+ cfg_globals['__file__'] = path
+ try:
+ exec f in cfg_globals
+ except SystemExit,status:
+ # We allow normal system exit inside a config file to just
+ # return control without error.
+ if status.args:
+ raise
+ f.close()
+ elif mustExist:
+ litConfig.fatal('unable to load config from %r ' % path)
+
+ config.finish(litConfig)
+ return config
+
+ def __init__(self, parent, name, suffixes, test_format,
+ environment, substitutions, unsupported, on_clone,
+ test_exec_root, test_source_root, excludes):
+ self.parent = parent
+ self.name = str(name)
+ self.suffixes = set(suffixes)
+ self.test_format = test_format
+ self.environment = dict(environment)
+ self.substitutions = list(substitutions)
+ self.unsupported = unsupported
+ self.on_clone = on_clone
+ self.test_exec_root = test_exec_root
+ self.test_source_root = test_source_root
+ self.excludes = set(excludes)
+
+ def clone(self, path):
+ # FIXME: Chain implementations?
+ #
+ # FIXME: Allow extra parameters?
+ cfg = TestingConfig(self, self.name, self.suffixes, self.test_format,
+ self.environment, self.substitutions,
+ self.unsupported, self.on_clone,
+ self.test_exec_root, self.test_source_root,
+ self.excludes)
+ if cfg.on_clone:
+ cfg.on_clone(self, cfg, path)
+ return cfg
+
+ def finish(self, litConfig):
+ """finish() - Finish this config object, after loading is complete."""
+
+ self.name = str(self.name)
+ self.suffixes = set(self.suffixes)
+ self.environment = dict(self.environment)
+ self.substitutions = list(self.substitutions)
+ if self.test_exec_root is not None:
+ # FIXME: This should really only be suite in test suite config
+ # files. Should we distinguish them?
+ self.test_exec_root = str(self.test_exec_root)
+ if self.test_source_root is not None:
+ # FIXME: This should really only be suite in test suite config
+ # files. Should we distinguish them?
+ self.test_source_root = str(self.test_source_root)
+ self.excludes = set(self.excludes)
diff --git a/libclamav/c++/llvm/utils/lit/Util.py b/libclamav/c++/llvm/utils/lit/Util.py
new file mode 100644
index 0000000..e62a8ed
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/Util.py
@@ -0,0 +1,124 @@
+import os, sys
+
+def detectCPUs():
+ """
+ Detects the number of CPUs on a system. Cribbed from pp.
+ """
+ # Linux, Unix and MacOS:
+ if hasattr(os, "sysconf"):
+ if os.sysconf_names.has_key("SC_NPROCESSORS_ONLN"):
+ # Linux & Unix:
+ ncpus = os.sysconf("SC_NPROCESSORS_ONLN")
+ if isinstance(ncpus, int) and ncpus > 0:
+ return ncpus
+ else: # OSX:
+ return int(os.popen2("sysctl -n hw.ncpu")[1].read())
+ # Windows:
+ if os.environ.has_key("NUMBER_OF_PROCESSORS"):
+ ncpus = int(os.environ["NUMBER_OF_PROCESSORS"]);
+ if ncpus > 0:
+ return ncpus
+ return 1 # Default
+
+def mkdir_p(path):
+ """mkdir_p(path) - Make the "path" directory, if it does not exist; this
+ will also make directories for any missing parent directories."""
+ import errno
+
+ if not path or os.path.exists(path):
+ return
+
+ parent = os.path.dirname(path)
+ if parent != path:
+ mkdir_p(parent)
+
+ try:
+ os.mkdir(path)
+ except OSError,e:
+ # Ignore EEXIST, which may occur during a race condition.
+ if e.errno != errno.EEXIST:
+ raise
+
+def capture(args):
+ import subprocess
+ """capture(command) - Run the given command (or argv list) in a shell and
+ return the standard output."""
+ p = subprocess.Popen(args, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+ out,_ = p.communicate()
+ return out
+
+def which(command, paths = None):
+ """which(command, [paths]) - Look up the given command in the paths string
+ (or the PATH environment variable, if unspecified)."""
+
+ if paths is None:
+ paths = os.environ.get('PATH','')
+
+ # Check for absolute match first.
+ if os.path.exists(command):
+ return command
+
+ # Would be nice if Python had a lib function for this.
+ if not paths:
+ paths = os.defpath
+
+ # Get suffixes to search.
+ pathext = os.environ.get('PATHEXT', '').split(os.pathsep)
+
+ # Search the paths...
+ for path in paths.split(os.pathsep):
+ for ext in pathext:
+ p = os.path.join(path, command + ext)
+ if os.path.exists(p):
+ return p
+
+ return None
+
+def printHistogram(items, title = 'Items'):
+ import itertools, math
+
+ items.sort(key = lambda (_,v): v)
+
+ maxValue = max([v for _,v in items])
+
+ # Select first "nice" bar height that produces more than 10 bars.
+ power = int(math.ceil(math.log(maxValue, 10)))
+ for inc in itertools.cycle((5, 2, 2.5, 1)):
+ barH = inc * 10**power
+ N = int(math.ceil(maxValue / barH))
+ if N > 10:
+ break
+ elif inc == 1:
+ power -= 1
+
+ histo = [set() for i in range(N)]
+ for name,v in items:
+ bin = min(int(N * v/maxValue), N-1)
+ histo[bin].add(name)
+
+ barW = 40
+ hr = '-' * (barW + 34)
+ print '\nSlowest %s:' % title
+ print hr
+ for name,value in items[-20:]:
+ print '%.2fs: %s' % (value, name)
+ print '\n%s Times:' % title
+ print hr
+ pDigits = int(math.ceil(math.log(maxValue, 10)))
+ pfDigits = max(0, 3-pDigits)
+ if pfDigits:
+ pDigits += pfDigits + 1
+ cDigits = int(math.ceil(math.log(len(items), 10)))
+ print "[%s] :: [%s] :: [%s]" % ('Range'.center((pDigits+1)*2 + 3),
+ 'Percentage'.center(barW),
+ 'Count'.center(cDigits*2 + 1))
+ print hr
+ for i,row in enumerate(histo):
+ pct = float(len(row)) / len(items)
+ w = int(barW * pct)
+ print "[%*.*fs,%*.*fs)" % (pDigits, pfDigits, i*barH,
+ pDigits, pfDigits, (i+1)*barH),
+ print ":: [%s%s] :: [%*d/%*d]" % ('*'*w, ' '*(barW-w),
+ cDigits, len(row),
+ cDigits, len(items))
+
diff --git a/libclamav/c++/llvm/utils/lit/lit.py b/libclamav/c++/llvm/utils/lit/lit.py
new file mode 100755
index 0000000..5b24286
--- /dev/null
+++ b/libclamav/c++/llvm/utils/lit/lit.py
@@ -0,0 +1,531 @@
+#!/usr/bin/env python
+
+"""
+lit - LLVM Integrated Tester.
+
+See lit.pod for more information.
+"""
+
+import math, os, platform, random, re, sys, time, threading, traceback
+
+import ProgressBar
+import TestRunner
+import Util
+
+from TestingConfig import TestingConfig
+import LitConfig
+import Test
+
+# FIXME: Rename to 'config.lit', 'site.lit', and 'local.lit' ?
+kConfigName = 'lit.cfg'
+kSiteConfigName = 'lit.site.cfg'
+kLocalConfigName = 'lit.local.cfg'
+
+class TestingProgressDisplay:
+ def __init__(self, opts, numTests, progressBar=None):
+ self.opts = opts
+ self.numTests = numTests
+ self.current = None
+ self.lock = threading.Lock()
+ self.progressBar = progressBar
+ self.completed = 0
+
+ def update(self, test):
+ # Avoid locking overhead in quiet mode
+ if self.opts.quiet and not test.result.isFailure:
+ self.completed += 1
+ return
+
+ # Output lock.
+ self.lock.acquire()
+ try:
+ self.handleUpdate(test)
+ finally:
+ self.lock.release()
+
+ def finish(self):
+ if self.progressBar:
+ self.progressBar.clear()
+ elif self.opts.quiet:
+ pass
+ elif self.opts.succinct:
+ sys.stdout.write('\n')
+
+ def handleUpdate(self, test):
+ self.completed += 1
+ if self.progressBar:
+ self.progressBar.update(float(self.completed)/self.numTests,
+ test.getFullName())
+
+ if self.opts.succinct and not test.result.isFailure:
+ return
+
+ if self.progressBar:
+ self.progressBar.clear()
+
+ print '%s: %s (%d of %d)' % (test.result.name, test.getFullName(),
+ self.completed, self.numTests)
+
+ if test.result.isFailure and self.opts.showOutput:
+ print "%s TEST '%s' FAILED %s" % ('*'*20, test.getFullName(),
+ '*'*20)
+ print test.output
+ print "*" * 20
+
+ sys.stdout.flush()
+
+class TestProvider:
+ def __init__(self, tests, maxTime):
+ self.maxTime = maxTime
+ self.iter = iter(tests)
+ self.lock = threading.Lock()
+ self.startTime = time.time()
+
+ def get(self):
+ # Check if we have run out of time.
+ if self.maxTime is not None:
+ if time.time() - self.startTime > self.maxTime:
+ return None
+
+ # Otherwise take the next test.
+ self.lock.acquire()
+ try:
+ item = self.iter.next()
+ except StopIteration:
+ item = None
+ self.lock.release()
+ return item
+
+class Tester(threading.Thread):
+ def __init__(self, litConfig, provider, display):
+ threading.Thread.__init__(self)
+ self.litConfig = litConfig
+ self.provider = provider
+ self.display = display
+
+ def run(self):
+ while 1:
+ item = self.provider.get()
+ if item is None:
+ break
+ self.runTest(item)
+
+ def runTest(self, test):
+ result = None
+ startTime = time.time()
+ try:
+ result, output = test.config.test_format.execute(test,
+ self.litConfig)
+ except KeyboardInterrupt:
+ # This is a sad hack. Unfortunately subprocess goes
+ # bonkers with ctrl-c and we start forking merrily.
+ print '\nCtrl-C detected, goodbye.'
+ os.kill(0,9)
+ except:
+ if self.litConfig.debug:
+ raise
+ result = Test.UNRESOLVED
+ output = 'Exception during script execution:\n'
+ output += traceback.format_exc()
+ output += '\n'
+ elapsed = time.time() - startTime
+
+ test.setResult(result, output, elapsed)
+ self.display.update(test)
+
+def dirContainsTestSuite(path):
+ cfgpath = os.path.join(path, kSiteConfigName)
+ if os.path.exists(cfgpath):
+ return cfgpath
+ cfgpath = os.path.join(path, kConfigName)
+ if os.path.exists(cfgpath):
+ return cfgpath
+
+def getTestSuite(item, litConfig, cache):
+ """getTestSuite(item, litConfig, cache) -> (suite, relative_path)
+
+ Find the test suite containing @arg item.
+
+ @retval (None, ...) - Indicates no test suite contains @arg item.
+ @retval (suite, relative_path) - The suite that @arg item is in, and its
+ relative path inside that suite.
+ """
+ def search1(path):
+ # Check for a site config or a lit config.
+ cfgpath = dirContainsTestSuite(path)
+
+ # If we didn't find a config file, keep looking.
+ if not cfgpath:
+ parent,base = os.path.split(path)
+ if parent == path:
+ return (None, ())
+
+ ts, relative = search(parent)
+ return (ts, relative + (base,))
+
+ # We found a config file, load it.
+ if litConfig.debug:
+ litConfig.note('loading suite config %r' % cfgpath)
+
+ cfg = TestingConfig.frompath(cfgpath, None, litConfig, mustExist = True)
+ source_root = os.path.realpath(cfg.test_source_root or path)
+ exec_root = os.path.realpath(cfg.test_exec_root or path)
+ return Test.TestSuite(cfg.name, source_root, exec_root, cfg), ()
+
+ def search(path):
+ # Check for an already instantiated test suite.
+ res = cache.get(path)
+ if res is None:
+ cache[path] = res = search1(path)
+ return res
+
+ # Canonicalize the path.
+ item = os.path.realpath(item)
+
+ # Skip files and virtual components.
+ components = []
+ while not os.path.isdir(item):
+ parent,base = os.path.split(item)
+ if parent == item:
+ return (None, ())
+ components.append(base)
+ item = parent
+ components.reverse()
+
+ ts, relative = search(item)
+ return ts, tuple(relative + tuple(components))
+
+def getLocalConfig(ts, path_in_suite, litConfig, cache):
+ def search1(path_in_suite):
+ # Get the parent config.
+ if not path_in_suite:
+ parent = ts.config
+ else:
+ parent = search(path_in_suite[:-1])
+
+ # Load the local configuration.
+ source_path = ts.getSourcePath(path_in_suite)
+ cfgpath = os.path.join(source_path, kLocalConfigName)
+ if litConfig.debug:
+ litConfig.note('loading local config %r' % cfgpath)
+ return TestingConfig.frompath(cfgpath, parent, litConfig,
+ mustExist = False,
+ config = parent.clone(cfgpath))
+
+ def search(path_in_suite):
+ key = (ts, path_in_suite)
+ res = cache.get(key)
+ if res is None:
+ cache[key] = res = search1(path_in_suite)
+ return res
+
+ return search(path_in_suite)
+
+def getTests(path, litConfig, testSuiteCache, localConfigCache):
+ # Find the test suite for this input and its relative path.
+ ts,path_in_suite = getTestSuite(path, litConfig, testSuiteCache)
+ if ts is None:
+ litConfig.warning('unable to find test suite for %r' % path)
+ return ()
+
+ if litConfig.debug:
+ litConfig.note('resolved input %r to %r::%r' % (path, ts.name,
+ path_in_suite))
+
+ return getTestsInSuite(ts, path_in_suite, litConfig,
+ testSuiteCache, localConfigCache)
+
+def getTestsInSuite(ts, path_in_suite, litConfig,
+ testSuiteCache, localConfigCache):
+ # Check that the source path exists (errors here are reported by the
+ # caller).
+ source_path = ts.getSourcePath(path_in_suite)
+ if not os.path.exists(source_path):
+ return
+
+ # Check if the user named a test directly.
+ if not os.path.isdir(source_path):
+ lc = getLocalConfig(ts, path_in_suite[:-1], litConfig, localConfigCache)
+ yield Test.Test(ts, path_in_suite, lc)
+ return
+
+ # Otherwise we have a directory to search for tests, start by getting the
+ # local configuration.
+ lc = getLocalConfig(ts, path_in_suite, litConfig, localConfigCache)
+
+ # Search for tests.
+ for res in lc.test_format.getTestsInDirectory(ts, path_in_suite,
+ litConfig, lc):
+ yield res
+
+ # Search subdirectories.
+ for filename in os.listdir(source_path):
+ # FIXME: This doesn't belong here?
+ if filename in ('Output', '.svn') or filename in lc.excludes:
+ continue
+
+ # Ignore non-directories.
+ file_sourcepath = os.path.join(source_path, filename)
+ if not os.path.isdir(file_sourcepath):
+ continue
+
+ # Check for nested test suites, first in the execpath in case there is a
+ # site configuration and then in the source path.
+ file_execpath = ts.getExecPath(path_in_suite + (filename,))
+ if dirContainsTestSuite(file_execpath):
+ subiter = getTests(file_execpath, litConfig,
+ testSuiteCache, localConfigCache)
+ elif dirContainsTestSuite(file_sourcepath):
+ subiter = getTests(file_sourcepath, litConfig,
+ testSuiteCache, localConfigCache)
+ else:
+ # Otherwise, continue loading from inside this test suite.
+ subiter = getTestsInSuite(ts, path_in_suite + (filename,),
+ litConfig, testSuiteCache,
+ localConfigCache)
+
+ for res in subiter:
+ yield res
+
+def runTests(numThreads, litConfig, provider, display):
+ # If only using one testing thread, don't use threads at all; this lets us
+ # profile, among other things.
+ if numThreads == 1:
+ t = Tester(litConfig, provider, display)
+ t.run()
+ return
+
+ # Otherwise spin up the testing threads and wait for them to finish.
+ testers = [Tester(litConfig, provider, display)
+ for i in range(numThreads)]
+ for t in testers:
+ t.start()
+ try:
+ for t in testers:
+ t.join()
+ except KeyboardInterrupt:
+ sys.exit(2)
+
+def main():
+ global options
+ from optparse import OptionParser, OptionGroup
+ parser = OptionParser("usage: %prog [options] {file-or-path}")
+
+ parser.add_option("-j", "--threads", dest="numThreads", metavar="N",
+ help="Number of testing threads",
+ type=int, action="store", default=None)
+
+ group = OptionGroup(parser, "Output Format")
+ # FIXME: I find these names very confusing, although I like the
+ # functionality.
+ group.add_option("-q", "--quiet", dest="quiet",
+ help="Suppress no error output",
+ action="store_true", default=False)
+ group.add_option("-s", "--succinct", dest="succinct",
+ help="Reduce amount of output",
+ action="store_true", default=False)
+ group.add_option("-v", "--verbose", dest="showOutput",
+ help="Show all test output",
+ action="store_true", default=False)
+ group.add_option("", "--no-progress-bar", dest="useProgressBar",
+ help="Do not use curses based progress bar",
+ action="store_false", default=True)
+ parser.add_option_group(group)
+
+ group = OptionGroup(parser, "Test Execution")
+ group.add_option("", "--path", dest="path",
+ help="Additional paths to add to testing environment",
+ action="append", type=str, default=[])
+ group.add_option("", "--vg", dest="useValgrind",
+ help="Run tests under valgrind",
+ action="store_true", default=False)
+ group.add_option("", "--vg-arg", dest="valgrindArgs", metavar="ARG",
+ help="Specify an extra argument for valgrind",
+ type=str, action="append", default=[])
+ group.add_option("", "--time-tests", dest="timeTests",
+ help="Track elapsed wall time for each test",
+ action="store_true", default=False)
+ group.add_option("", "--no-execute", dest="noExecute",
+ help="Don't execute any tests (assume PASS)",
+ action="store_true", default=False)
+ parser.add_option_group(group)
+
+ group = OptionGroup(parser, "Test Selection")
+ group.add_option("", "--max-tests", dest="maxTests", metavar="N",
+ help="Maximum number of tests to run",
+ action="store", type=int, default=None)
+ group.add_option("", "--max-time", dest="maxTime", metavar="N",
+ help="Maximum time to spend testing (in seconds)",
+ action="store", type=float, default=None)
+ group.add_option("", "--shuffle", dest="shuffle",
+ help="Run tests in random order",
+ action="store_true", default=False)
+ parser.add_option_group(group)
+
+ group = OptionGroup(parser, "Debug and Experimental Options")
+ group.add_option("", "--debug", dest="debug",
+ help="Enable debugging (for 'lit' development)",
+ action="store_true", default=False)
+ group.add_option("", "--show-suites", dest="showSuites",
+ help="Show discovered test suites",
+ action="store_true", default=False)
+ group.add_option("", "--no-tcl-as-sh", dest="useTclAsSh",
+ help="Don't run Tcl scripts using 'sh'",
+ action="store_false", default=True)
+ parser.add_option_group(group)
+
+ (opts, args) = parser.parse_args()
+
+ if not args:
+ parser.error('No inputs specified')
+
+ if opts.numThreads is None:
+ opts.numThreads = Util.detectCPUs()
+
+ inputs = args
+
+ # Create the global config object.
+ litConfig = LitConfig.LitConfig(progname = os.path.basename(sys.argv[0]),
+ path = opts.path,
+ quiet = opts.quiet,
+ useValgrind = opts.useValgrind,
+ valgrindArgs = opts.valgrindArgs,
+ useTclAsSh = opts.useTclAsSh,
+ noExecute = opts.noExecute,
+ debug = opts.debug,
+ isWindows = (platform.system()=='Windows'))
+
+ # Load the tests from the inputs.
+ tests = []
+ testSuiteCache = {}
+ localConfigCache = {}
+ for input in inputs:
+ prev = len(tests)
+ tests.extend(getTests(input, litConfig,
+ testSuiteCache, localConfigCache))
+ if prev == len(tests):
+ litConfig.warning('input %r contained no tests' % input)
+
+ # If there were any errors during test discovery, exit now.
+ if litConfig.numErrors:
+ print >>sys.stderr, '%d errors, exiting.' % litConfig.numErrors
+ sys.exit(2)
+
+ if opts.showSuites:
+ suitesAndTests = dict([(ts,[])
+ for ts,_ in testSuiteCache.values()])
+ for t in tests:
+ suitesAndTests[t.suite].append(t)
+
+ print '-- Test Suites --'
+ suitesAndTests = suitesAndTests.items()
+ suitesAndTests.sort(key = lambda (ts,_): ts.name)
+ for ts,tests in suitesAndTests:
+ print ' %s - %d tests' %(ts.name, len(tests))
+ print ' Source Root: %s' % ts.source_root
+ print ' Exec Root : %s' % ts.exec_root
+
+ # Select and order the tests.
+ numTotalTests = len(tests)
+ if opts.shuffle:
+ random.shuffle(tests)
+ else:
+ tests.sort(key = lambda t: t.getFullName())
+ if opts.maxTests is not None:
+ tests = tests[:opts.maxTests]
+
+ extra = ''
+ if len(tests) != numTotalTests:
+ extra = ' of %d' % numTotalTests
+ header = '-- Testing: %d%s tests, %d threads --'%(len(tests),extra,
+ opts.numThreads)
+
+ progressBar = None
+ if not opts.quiet:
+ if opts.succinct and opts.useProgressBar:
+ try:
+ tc = ProgressBar.TerminalController()
+ progressBar = ProgressBar.ProgressBar(tc, header)
+ except ValueError:
+ print header
+ progressBar = ProgressBar.SimpleProgressBar('Testing: ')
+ else:
+ print header
+
+ # Don't create more threads than tests.
+ opts.numThreads = min(len(tests), opts.numThreads)
+
+ startTime = time.time()
+ display = TestingProgressDisplay(opts, len(tests), progressBar)
+ provider = TestProvider(tests, opts.maxTime)
+ runTests(opts.numThreads, litConfig, provider, display)
+ display.finish()
+
+ if not opts.quiet:
+ print 'Testing Time: %.2fs'%(time.time() - startTime)
+
+ # Update results for any tests which weren't run.
+ for t in tests:
+ if t.result is None:
+ t.setResult(Test.UNRESOLVED, '', 0.0)
+
+ # List test results organized by kind.
+ hasFailures = False
+ byCode = {}
+ for t in tests:
+ if t.result not in byCode:
+ byCode[t.result] = []
+ byCode[t.result].append(t)
+ if t.result.isFailure:
+ hasFailures = True
+
+ # FIXME: Show unresolved and (optionally) unsupported tests.
+ for title,code in (('Unexpected Passing Tests', Test.XPASS),
+ ('Failing Tests', Test.FAIL)):
+ elts = byCode.get(code)
+ if not elts:
+ continue
+ print '*'*20
+ print '%s (%d):' % (title, len(elts))
+ for t in elts:
+ print ' %s' % t.getFullName()
+ print
+
+ if opts.timeTests:
+ byTime = list(tests)
+ byTime.sort(key = lambda t: t.elapsed)
+ if byTime:
+ Util.printHistogram([(t.getFullName(), t.elapsed) for t in byTime],
+ title='Tests')
+
+ for name,code in (('Expected Passes ', Test.PASS),
+ ('Expected Failures ', Test.XFAIL),
+ ('Unsupported Tests ', Test.UNSUPPORTED),
+ ('Unresolved Tests ', Test.UNRESOLVED),
+ ('Unexpected Passes ', Test.XPASS),
+ ('Unexpected Failures', Test.FAIL),):
+ if opts.quiet and not code.isFailure:
+ continue
+ N = len(byCode.get(code,[]))
+ if N:
+ print ' %s: %d' % (name,N)
+
+ # If we encountered any additional errors, exit abnormally.
+ if litConfig.numErrors:
+ print >>sys.stderr, '\n%d error(s), exiting.' % litConfig.numErrors
+ sys.exit(2)
+
+ # Warn about warnings.
+ if litConfig.numWarnings:
+ print >>sys.stderr, '\n%d warning(s) in tests.' % litConfig.numWarnings
+
+ if hasFailures:
+ sys.exit(1)
+ sys.exit(0)
+
+if __name__=='__main__':
+ # Bump the GIL check interval, its more important to get any one thread to a
+ # blocking operation (hopefully exec) than to try and unblock other threads.
+ import sys
+ sys.setcheckinterval(1000)
+ main()
diff --git a/libclamav/c++/llvm/utils/not/CMakeLists.txt b/libclamav/c++/llvm/utils/not/CMakeLists.txt
new file mode 100644
index 0000000..407c82e
--- /dev/null
+++ b/libclamav/c++/llvm/utils/not/CMakeLists.txt
@@ -0,0 +1,11 @@
+add_executable(not
+ not.cpp
+ )
+
+target_link_libraries(not LLVMSystem)
+if( MINGW )
+ target_link_libraries(not imagehlp psapi)
+endif( MINGW )
+if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD )
+ target_link_libraries(not pthread)
+endif()
diff --git a/libclamav/c++/llvm/utils/not/Makefile b/libclamav/c++/llvm/utils/not/Makefile
new file mode 100644
index 0000000..fef4802
--- /dev/null
+++ b/libclamav/c++/llvm/utils/not/Makefile
@@ -0,0 +1,21 @@
+##===- utils/not/Makefile ----------------------------------*- Makefile -*-===##
+#
+# The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+
+LEVEL = ../..
+TOOLNAME = not
+USEDLIBS = LLVMSupport.a LLVMSystem.a
+
+# This tool has no plugins, optimize startup time.
+TOOL_NO_EXPORTS = 1
+
+# Don't install this utility
+NO_INSTALL = 1
+
+include $(LEVEL)/Makefile.common
+
diff --git a/libclamav/c++/llvm/utils/not/not.cpp b/libclamav/c++/llvm/utils/not/not.cpp
new file mode 100644
index 0000000..dd89b8f
--- /dev/null
+++ b/libclamav/c++/llvm/utils/not/not.cpp
@@ -0,0 +1,17 @@
+//===- not.cpp - The 'not' testing tool -----------------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/System/Path.h"
+#include "llvm/System/Program.h"
+using namespace llvm;
+
+int main(int argc, const char **argv) {
+ sys::Path Program = sys::Program::FindProgramByName(argv[1]);
+ return !sys::Program::ExecuteAndWait(Program, argv + 1);
+}
diff --git a/libclamav/c++/llvm/utils/unittest/Makefile b/libclamav/c++/llvm/utils/unittest/Makefile
index 2f3e601..6a09341 100644
--- a/libclamav/c++/llvm/utils/unittest/Makefile
+++ b/libclamav/c++/llvm/utils/unittest/Makefile
@@ -8,6 +8,6 @@
##===----------------------------------------------------------------------===##
LEVEL = ../..
-PARALLEL_DIRS = googletest
+PARALLEL_DIRS = googletest UnitTestMain
include $(LEVEL)/Makefile.common
diff --git a/libclamav/c++/llvm/utils/unittest/UnitTestMain/Makefile b/libclamav/c++/llvm/utils/unittest/UnitTestMain/Makefile
new file mode 100644
index 0000000..aadff21
--- /dev/null
+++ b/libclamav/c++/llvm/utils/unittest/UnitTestMain/Makefile
@@ -0,0 +1,21 @@
+##===- utils/unittest/UnitTestMain/Makefile ----------------*- Makefile -*-===##
+#
+# The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+
+LEVEL = ../../..
+
+include $(LEVEL)/Makefile.config
+NO_MISSING_FIELD_INITIALIZERS := $(shell $(CXX) -Wno-missing-field-initializers -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-missing-field-initializers)
+NO_VARIADIC_MACROS := $(shell $(CXX) -Wno-variadic-macros -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-variadic-macros)
+
+LIBRARYNAME = UnitTestMain
+BUILD_ARCHIVE = 1
+CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include
+CPP.Flags += $(NO_MISSING_FIELD_INITIALIZERS) $(NO_VARIADIC_MACROS)
+
+include $(LEVEL)/Makefile.common
diff --git a/libclamav/c++/llvm/utils/unittest/UnitTestMain/TestMain.cpp b/libclamav/c++/llvm/utils/unittest/UnitTestMain/TestMain.cpp
new file mode 100644
index 0000000..d97dca8
--- /dev/null
+++ b/libclamav/c++/llvm/utils/unittest/UnitTestMain/TestMain.cpp
@@ -0,0 +1,15 @@
+//===--- utils/unittest/UnitTestMain/TestMain.cpp - unittest driver -------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "gtest/gtest.h"
+
+int main(int argc, char **argv) {
+ testing::InitGoogleTest(&argc, argv);
+ return RUN_ALL_TESTS();
+}
diff --git a/libclamav/c++/llvm/utils/unittest/googletest/Makefile b/libclamav/c++/llvm/utils/unittest/googletest/Makefile
index 2e0bf72..29fe679 100644
--- a/libclamav/c++/llvm/utils/unittest/googletest/Makefile
+++ b/libclamav/c++/llvm/utils/unittest/googletest/Makefile
@@ -8,11 +8,11 @@
##===----------------------------------------------------------------------===##
LEVEL := ../../..
+
include $(LEVEL)/Makefile.config
NO_MISSING_FIELD_INITIALIZERS := $(shell $(CXX) -Wno-missing-field-initializers -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-missing-field-initializers)
NO_VARIADIC_MACROS := $(shell $(CXX) -Wno-variadic-macros -fsyntax-only -xc /dev/null 2>/dev/null && echo -Wno-variadic-macros)
-
LIBRARYNAME = GoogleTest
BUILD_ARCHIVE = 1
CPP.Flags += -I$(LLVM_SRC_ROOT)/utils/unittest/googletest/include
diff --git a/libclamav/c++/llvm/utils/unittest/googletest/README.LLVM b/libclamav/c++/llvm/utils/unittest/googletest/README.LLVM
index 2c673cc..e907a5e 100644
--- a/libclamav/c++/llvm/utils/unittest/googletest/README.LLVM
+++ b/libclamav/c++/llvm/utils/unittest/googletest/README.LLVM
@@ -24,3 +24,8 @@ $ perl -pi -e 's|^#include "src/|#include "gtest/internal/|' *.cc
$ rm -f gtest-all.cc gtest_main.cc
$ mv COPYING LICENSE.TXT
+
+
+Modified as follows:
+* To GTestStreamToHelper in include/gtest/internal/gtest-internal.h,
+ added the ability to stream with raw_os_ostream.
diff --git a/libclamav/c++/llvm/utils/unittest/googletest/include/gtest/internal/gtest-internal.h b/libclamav/c++/llvm/utils/unittest/googletest/include/gtest/internal/gtest-internal.h
index 37faaae..242ffea 100644
--- a/libclamav/c++/llvm/utils/unittest/googletest/include/gtest/internal/gtest-internal.h
+++ b/libclamav/c++/llvm/utils/unittest/googletest/include/gtest/internal/gtest-internal.h
@@ -56,6 +56,8 @@
#include <gtest/internal/gtest-filepath.h>
#include <gtest/internal/gtest-type-util.h>
+#include "llvm/Support/raw_os_ostream.h"
+
// Due to C++ preprocessor weirdness, we need double indirection to
// concatenate two tokens when one of them is __LINE__. Writing
//
@@ -92,9 +94,27 @@
// ::operator<<;" in the definition of Message's operator<<. That fix
// doesn't require a helper function, but unfortunately doesn't
// compile with MSVC.
+
+// LLVM INTERNAL CHANGE: To allow operator<< to work with both
+// std::ostreams and LLVM's raw_ostreams, we define a special
+// std::ostream with an implicit conversion to raw_ostream& and stream
+// to that. This causes the compiler to prefer std::ostream overloads
+// but still find raw_ostream& overloads.
+namespace llvm {
+class convertible_fwd_ostream : public std::ostream {
+ std::ostream& os_;
+ raw_os_ostream ros_;
+
+public:
+ convertible_fwd_ostream(std::ostream& os)
+ : std::ostream(os.rdbuf()), os_(os), ros_(*this) {}
+ operator raw_ostream&() { return ros_; }
+};
+}
template <typename T>
inline void GTestStreamToHelper(std::ostream* os, const T& val) {
- *os << val;
+ llvm::convertible_fwd_ostream cos(*os);
+ cos << val;
}
namespace testing {
diff --git a/libclamav/c++/llvm/utils/valgrind/x86_64-pc-linux-gnu_gcc-4.3.3.supp b/libclamav/c++/llvm/utils/valgrind/x86_64-pc-linux-gnu_gcc-4.3.3.supp
new file mode 100644
index 0000000..a86be6c
--- /dev/null
+++ b/libclamav/c++/llvm/utils/valgrind/x86_64-pc-linux-gnu_gcc-4.3.3.supp
@@ -0,0 +1,23 @@
+{
+ libstdcxx_overlapped_memcpy_in_stable_sort_1
+ Memcheck:Overlap
+ fun:memcpy
+ ...
+ fun:_ZSt11stable_sortIN9__gnu_cxx17__normal_iteratorIPSt4pairIPKN4llvm5ValueEjESt6vectorIS7_SaIS7_EEEEN12_GLOBAL__N_116CstSortPredicateEEvT_SF_T0_
+}
+
+{
+ libstdcxx_overlapped_memcpy_in_stable_sort_2
+ Memcheck:Overlap
+ fun:memcpy
+ ...
+ fun:_ZSt11stable_sortIN9__gnu_cxx17__normal_iteratorIPSt4pairIPKN4llvm5ValueEjESt6vectorIS7_SaIS7_EEEEN12_GLOBAL__N_116CstSortPredicateEEvT_SF_T0_
+}
+
+{
+ libstdcxx_overlapped_memcpy_in_stable_sort_3
+ Memcheck:Overlap
+ fun:memcpy
+ ...
+ fun:_ZSt11stable_sortIN9__gnu_cxx17__normal_iteratorIPSt4pairIPKN4llvm4TypeEjESt6vectorIS7_SaIS7_EEEEPFbRKS7_SE_EEvT_SH_T0_
+}
--
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