[Pkg-clamav-commits] [SCM] Debian repository for ClamAV branch, debian/unstable, updated. debian/0.95+dfsg-1-6156-g094ec9b
Török Edvin
edwin at clamav.net
Sun Apr 4 01:13:13 UTC 2010
The following commit has been merged in the debian/unstable branch:
commit 973f086a7d6277cc8aeaf4766640fbf0809992e1
Author: Török Edvin <edwin at clamav.net>
Date: Mon Dec 28 20:08:10 2009 +0200
Regenerate auto-generated files.
diff --git a/libclamav/c++/ARMGenAsmWriter.inc b/libclamav/c++/ARMGenAsmWriter.inc
index 0626d07..063f82d 100644
--- a/libclamav/c++/ARMGenAsmWriter.inc
+++ b/libclamav/c++/ARMGenAsmWriter.inc
@@ -1463,7 +1463,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
1522U, // tCBNZ
1528U, // tCBZ
1076986004U, // tCMN
- 1076986004U, // tCMNZ
+ 1076986004U, // tCMNz
1076986008U, // tCMPhir
1076986008U, // tCMPi8
1076986008U, // tCMPr
@@ -3133,7 +3133,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::tADDrr:
case ARM::tASRri:
case ARM::tCMN:
- case ARM::tCMNZ:
+ case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
case ARM::tCMPr:
@@ -3657,7 +3657,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2CLZ:
case ARM::t2MOVi16:
case ARM::tCMN:
- case ARM::tCMNZ:
+ case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
case ARM::tCMPr:
diff --git a/libclamav/c++/ARMGenCodeEmitter.inc b/libclamav/c++/ARMGenCodeEmitter.inc
index 121e782..c593b9e 100644
--- a/libclamav/c++/ARMGenCodeEmitter.inc
+++ b/libclamav/c++/ARMGenCodeEmitter.inc
@@ -1206,326 +1206,326 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4088791488U, // VZIPq16
4089053632U, // VZIPq32
4088529344U, // VZIPq8
- 0U, // t2ADCSri
- 0U, // t2ADCSrr
- 0U, // t2ADCSrs
- 0U, // t2ADCri
- 0U, // t2ADCrr
- 0U, // t2ADCrs
- 0U, // t2ADDSri
- 0U, // t2ADDSrr
- 0U, // t2ADDSrs
- 0U, // t2ADDrSPi
- 0U, // t2ADDrSPi12
- 0U, // t2ADDrSPs
- 0U, // t2ADDri
- 0U, // t2ADDri12
- 0U, // t2ADDrr
- 0U, // t2ADDrs
- 0U, // t2ANDri
- 0U, // t2ANDrr
- 0U, // t2ANDrs
- 0U, // t2ASRri
- 0U, // t2ASRrr
- 0U, // t2B
- 0U, // t2BFC
- 0U, // t2BICri
- 0U, // t2BICrr
- 0U, // t2BICrs
- 0U, // t2BR_JT
- 0U, // t2Bcc
- 0U, // t2CLZ
- 0U, // t2CMNri
- 0U, // t2CMNrr
- 0U, // t2CMNrs
- 0U, // t2CMNzri
- 0U, // t2CMNzrr
- 0U, // t2CMNzrs
- 0U, // t2CMPri
- 0U, // t2CMPrr
- 0U, // t2CMPrs
- 0U, // t2CMPzri
- 0U, // t2CMPzrr
- 0U, // t2CMPzrs
- 0U, // t2EORri
- 0U, // t2EORrr
- 0U, // t2EORrs
- 0U, // t2IT
- 0U, // t2Int_MemBarrierV7
- 0U, // t2Int_SyncBarrierV7
+ 4048551936U, // t2ADCSri
+ 3947888640U, // t2ADCSrr
+ 3947888640U, // t2ADCSrs
+ 4047503360U, // t2ADCri
+ 3946840064U, // t2ADCrr
+ 3946840064U, // t2ADCrs
+ 4044357632U, // t2ADDSri
+ 3943694336U, // t2ADDSrr
+ 3943694336U, // t2ADDSrs
+ 4044161024U, // t2ADDrSPi
+ 4060938240U, // t2ADDrSPi12
+ 3943497728U, // t2ADDrSPs
+ 4043309056U, // t2ADDri
+ 4060086272U, // t2ADDri12
+ 3942645760U, // t2ADDrr
+ 3942645760U, // t2ADDrs
+ 4026531840U, // t2ANDri
+ 3925868544U, // t2ANDrr
+ 3925868544U, // t2ANDrs
+ 3931045920U, // t2ASRri
+ 4198559744U, // t2ASRrr
+ 4026568704U, // t2B
+ 4084137984U, // t2BFC
+ 4028628992U, // t2BICri
+ 3927965696U, // t2BICrr
+ 3927965696U, // t2BICrs
+ 3931049728U, // t2BR_JT
+ 4026564608U, // t2Bcc
+ 4205899904U, // t2CLZ
+ 4044361472U, // t2CMNri
+ 3943698176U, // t2CMNrr
+ 3943698176U, // t2CMNrs
+ 4044361472U, // t2CMNzri
+ 3943698176U, // t2CMNzrr
+ 3943698176U, // t2CMNzrs
+ 4054847232U, // t2CMPri
+ 3954183936U, // t2CMPrr
+ 3954183936U, // t2CMPrs
+ 4054847232U, // t2CMPzri
+ 3954183936U, // t2CMPzrr
+ 3954183936U, // t2CMPzrs
+ 4034920448U, // t2EORri
+ 3934257152U, // t2EORrr
+ 3934257152U, // t2EORrs
+ 48896U, // t2IT
+ 4089417567U, // t2Int_MemBarrierV7
+ 4089417551U, // t2Int_SyncBarrierV7
0U, // t2Int_eh_sjlj_setjmp
- 0U, // t2LDM
- 0U, // t2LDM_RET
- 0U, // t2LDRB_POST
- 0U, // t2LDRB_PRE
- 0U, // t2LDRBi12
- 0U, // t2LDRBi8
- 0U, // t2LDRBpci
- 0U, // t2LDRBs
- 0U, // t2LDRDi8
- 0U, // t2LDRDpci
- 0U, // t2LDREX
- 0U, // t2LDREXB
- 0U, // t2LDREXD
- 0U, // t2LDREXH
- 0U, // t2LDRH_POST
- 0U, // t2LDRH_PRE
- 0U, // t2LDRHi12
- 0U, // t2LDRHi8
- 0U, // t2LDRHpci
- 0U, // t2LDRHs
- 0U, // t2LDRSB_POST
- 0U, // t2LDRSB_PRE
- 0U, // t2LDRSBi12
- 0U, // t2LDRSBi8
- 0U, // t2LDRSBpci
- 0U, // t2LDRSBs
- 0U, // t2LDRSH_POST
- 0U, // t2LDRSH_PRE
- 0U, // t2LDRSHi12
- 0U, // t2LDRSHi8
- 0U, // t2LDRSHpci
- 0U, // t2LDRSHs
- 0U, // t2LDR_POST
- 0U, // t2LDR_PRE
- 0U, // t2LDRi12
- 0U, // t2LDRi8
- 0U, // t2LDRpci
+ 3893362688U, // t2LDM
+ 3893362688U, // t2LDM_RET
+ 4161800448U, // t2LDRB_POST
+ 4161801472U, // t2LDRB_PRE
+ 4170186752U, // t2LDRBi12
+ 4161801216U, // t2LDRBi8
+ 4162781184U, // t2LDRBpci
+ 4161798144U, // t2LDRBs
+ 3914334208U, // t2LDRDi8
+ 3898540032U, // t2LDRDpci
+ 3897560832U, // t2LDREX
+ 3905949519U, // t2LDREXB
+ 3905945727U, // t2LDREXD
+ 3905949535U, // t2LDREXH
+ 4163897600U, // t2LDRH_POST
+ 4163898624U, // t2LDRH_PRE
+ 4172283904U, // t2LDRHi12
+ 4163898368U, // t2LDRHi8
+ 4164878336U, // t2LDRHpci
+ 4163895296U, // t2LDRHs
+ 4178577664U, // t2LDRSB_POST
+ 4178578688U, // t2LDRSB_PRE
+ 4186963968U, // t2LDRSBi12
+ 4178578432U, // t2LDRSBi8
+ 4179558400U, // t2LDRSBpci
+ 4178575360U, // t2LDRSBs
+ 4180674816U, // t2LDRSH_POST
+ 4180675840U, // t2LDRSH_PRE
+ 4189061120U, // t2LDRSHi12
+ 4180675584U, // t2LDRSHi8
+ 4181655552U, // t2LDRSHpci
+ 4180672512U, // t2LDRSHs
+ 4165994752U, // t2LDR_POST
+ 4165995776U, // t2LDR_PRE
+ 4174381056U, // t2LDRi12
+ 4165995520U, // t2LDRi8
+ 4166975488U, // t2LDRpci
0U, // t2LDRpci_pic
- 0U, // t2LDRs
- 0U, // t2LEApcrel
- 0U, // t2LEApcrelJT
- 0U, // t2LSLri
- 0U, // t2LSLrr
- 0U, // t2LSRri
- 0U, // t2LSRrr
- 0U, // t2MLA
- 0U, // t2MLS
- 0U, // t2MOVCCasr
- 0U, // t2MOVCCi
- 0U, // t2MOVCClsl
- 0U, // t2MOVCClsr
- 0U, // t2MOVCCr
- 0U, // t2MOVCCror
- 0U, // t2MOVTi16
- 0U, // t2MOVi
- 0U, // t2MOVi16
+ 4165992448U, // t2LDRs
+ 4061069312U, // t2LEApcrel
+ 4061069312U, // t2LEApcrelJT
+ 3931045888U, // t2LSLri
+ 4194365440U, // t2LSLrr
+ 3931045904U, // t2LSRri
+ 4196462592U, // t2LSRrr
+ 4211081216U, // t2MLA
+ 4211081232U, // t2MLS
+ 3931045920U, // t2MOVCCasr
+ 4031709184U, // t2MOVCCi
+ 3931045888U, // t2MOVCClsl
+ 3931045904U, // t2MOVCClsr
+ 3931045888U, // t2MOVCCr
+ 3931045936U, // t2MOVCCror
+ 4072669184U, // t2MOVTi16
+ 4031709184U, // t2MOVi
+ 4064280576U, // t2MOVi16
0U, // t2MOVi32imm
- 0U, // t2MOVr
- 0U, // t2MOVrx
- 0U, // t2MOVsra_flag
- 0U, // t2MOVsrl_flag
- 0U, // t2MUL
- 0U, // t2MVNi
- 0U, // t2MVNr
- 0U, // t2MVNs
- 0U, // t2ORNri
- 0U, // t2ORNrr
- 0U, // t2ORNrs
- 0U, // t2ORRri
- 0U, // t2ORRrr
- 0U, // t2ORRrs
- 0U, // t2PKHBT
- 0U, // t2PKHTB
- 0U, // t2REV
- 0U, // t2REV16
- 0U, // t2REVSH
- 0U, // t2RORri
- 0U, // t2RORrr
- 0U, // t2RSBSri
- 0U, // t2RSBSrs
- 0U, // t2RSBri
- 0U, // t2RSBrs
- 0U, // t2SBCSri
- 0U, // t2SBCSrr
- 0U, // t2SBCSrs
- 0U, // t2SBCri
- 0U, // t2SBCrr
- 0U, // t2SBCrs
- 0U, // t2SBFX
- 0U, // t2SMLABB
- 0U, // t2SMLABT
- 0U, // t2SMLAL
- 0U, // t2SMLATB
- 0U, // t2SMLATT
- 0U, // t2SMLAWB
- 0U, // t2SMLAWT
- 0U, // t2SMMLA
- 0U, // t2SMMLS
- 0U, // t2SMMUL
- 0U, // t2SMULBB
- 0U, // t2SMULBT
- 0U, // t2SMULL
- 0U, // t2SMULTB
- 0U, // t2SMULTT
- 0U, // t2SMULWB
- 0U, // t2SMULWT
- 0U, // t2STM
- 0U, // t2STRB_POST
- 0U, // t2STRB_PRE
- 0U, // t2STRBi12
- 0U, // t2STRBi8
- 0U, // t2STRBs
- 0U, // t2STRDi8
- 0U, // t2STREX
- 0U, // t2STREXB
- 0U, // t2STREXD
- 0U, // t2STREXH
- 0U, // t2STRH_POST
- 0U, // t2STRH_PRE
- 0U, // t2STRHi12
- 0U, // t2STRHi8
- 0U, // t2STRHs
- 0U, // t2STR_POST
- 0U, // t2STR_PRE
- 0U, // t2STRi12
- 0U, // t2STRi8
- 0U, // t2STRs
- 0U, // t2SUBSri
- 0U, // t2SUBSrr
- 0U, // t2SUBSrs
- 0U, // t2SUBrSPi
- 0U, // t2SUBrSPi12
+ 3931045888U, // t2MOVr
+ 3931045936U, // t2MOVrx
+ 3932094560U, // t2MOVsra_flag
+ 3932094544U, // t2MOVsrl_flag
+ 4211142656U, // t2MUL
+ 4033806336U, // t2MVNi
+ 3933143040U, // t2MVNr
+ 3933143040U, // t2MVNs
+ 4032823296U, // t2ORNri
+ 3932160000U, // t2ORNrr
+ 3932160000U, // t2ORNrs
+ 4030726144U, // t2ORRri
+ 3930062848U, // t2ORRrr
+ 3930062848U, // t2ORRrs
+ 3938451456U, // t2PKHBT
+ 3938451488U, // t2PKHTB
+ 4203802752U, // t2REV
+ 4203802768U, // t2REV16
+ 4203802800U, // t2REVSH
+ 3931045936U, // t2RORri
+ 4200656896U, // t2RORrr
+ 4056940544U, // t2RSBSri
+ 3956277248U, // t2RSBSrs
+ 4055891968U, // t2RSBri
+ 3955228672U, // t2RSBrs
+ 4050649088U, // t2SBCSri
+ 3949985792U, // t2SBCSrr
+ 3949985792U, // t2SBCSrs
+ 4049600512U, // t2SBCri
+ 3948937216U, // t2SBCrr
+ 3948937216U, // t2SBCrs
+ 4081057792U, // t2SBFX
+ 4212129792U, // t2SMLABB
+ 4212129808U, // t2SMLABT
+ 4223664128U, // t2SMLAL
+ 4212129824U, // t2SMLATB
+ 4212129840U, // t2SMLATT
+ 4214226944U, // t2SMLAWB
+ 4214226960U, // t2SMLAWT
+ 4216324096U, // t2SMMLA
+ 4217372672U, // t2SMMLS
+ 4216385536U, // t2SMMUL
+ 4212191232U, // t2SMULBB
+ 4212191248U, // t2SMULBT
+ 4219469824U, // t2SMULL
+ 4212191264U, // t2SMULTB
+ 4212191280U, // t2SMULTT
+ 4214288384U, // t2SMULWB
+ 4214288400U, // t2SMULWT
+ 3892314112U, // t2STM
+ 4160751872U, // t2STRB_POST
+ 4160752896U, // t2STRB_PRE
+ 4169138176U, // t2STRBi12
+ 4160752640U, // t2STRBi8
+ 4160749568U, // t2STRBs
+ 3913285632U, // t2STRDi8
+ 3896508416U, // t2STREX
+ 3904900928U, // t2STREXB
+ 3904897136U, // t2STREXD
+ 3904900944U, // t2STREXH
+ 4162849024U, // t2STRH_POST
+ 4162850048U, // t2STRH_PRE
+ 4171235328U, // t2STRHi12
+ 4162849792U, // t2STRHi8
+ 4162846720U, // t2STRHs
+ 4164946176U, // t2STR_POST
+ 4164947200U, // t2STR_PRE
+ 4173332480U, // t2STRi12
+ 4164946944U, // t2STRi8
+ 4164943872U, // t2STRs
+ 4054843392U, // t2SUBSri
+ 3954180096U, // t2SUBSrr
+ 3954180096U, // t2SUBSrs
+ 4054646784U, // t2SUBrSPi
+ 4071424000U, // t2SUBrSPi12
0U, // t2SUBrSPi12_
0U, // t2SUBrSPi_
- 0U, // t2SUBrSPs
+ 3953983488U, // t2SUBrSPs
0U, // t2SUBrSPs_
- 0U, // t2SUBri
- 0U, // t2SUBri12
- 0U, // t2SUBrr
- 0U, // t2SUBrs
- 0U, // t2SXTABrr
- 0U, // t2SXTABrr_rot
- 0U, // t2SXTAHrr
- 0U, // t2SXTAHrr_rot
- 0U, // t2SXTBr
- 0U, // t2SXTBr_rot
- 0U, // t2SXTHr
- 0U, // t2SXTHr_rot
- 0U, // t2TBB
- 0U, // t2TBH
- 0U, // t2TEQri
- 0U, // t2TEQrr
- 0U, // t2TEQrs
- 0U, // t2TPsoft
- 0U, // t2TSTri
- 0U, // t2TSTrr
- 0U, // t2TSTrs
- 0U, // t2UBFX
- 0U, // t2UMAAL
- 0U, // t2UMLAL
- 0U, // t2UMULL
- 0U, // t2UXTABrr
- 0U, // t2UXTABrr_rot
- 0U, // t2UXTAHrr
- 0U, // t2UXTAHrr_rot
- 0U, // t2UXTB16r
- 0U, // t2UXTB16r_rot
- 0U, // t2UXTBr
- 0U, // t2UXTBr_rot
- 0U, // t2UXTHr
- 0U, // t2UXTHr_rot
- 0U, // tADC
- 0U, // tADDhirr
- 0U, // tADDi3
- 0U, // tADDi8
- 0U, // tADDrPCi
- 0U, // tADDrSP
- 0U, // tADDrSPi
- 0U, // tADDrr
- 0U, // tADDspi
- 0U, // tADDspr
+ 4053794816U, // t2SUBri
+ 4070572032U, // t2SUBri12
+ 3953131520U, // t2SUBrr
+ 3953131520U, // t2SUBrs
+ 4198559872U, // t2SXTABrr
+ 4198559872U, // t2SXTABrr_rot
+ 4194365568U, // t2SXTAHrr
+ 4194365568U, // t2SXTAHrr_rot
+ 4199542912U, // t2SXTBr
+ 4199542912U, // t2SXTBr_rot
+ 4195348608U, // t2SXTHr
+ 4195348608U, // t2SXTHr_rot
+ 3906990080U, // t2TBB
+ 3906990096U, // t2TBH
+ 4035972864U, // t2TEQri
+ 3935309568U, // t2TEQrr
+ 3935309568U, // t2TEQrs
+ 4026585088U, // t2TPsoft
+ 4027584256U, // t2TSTri
+ 3926920960U, // t2TSTrr
+ 3926920960U, // t2TSTrs
+ 4089446400U, // t2UBFX
+ 4225761376U, // t2UMAAL
+ 4225761280U, // t2UMLAL
+ 4221566976U, // t2UMULL
+ 4199608448U, // t2UXTABrr
+ 4199608448U, // t2UXTABrr_rot
+ 4195414144U, // t2UXTAHrr
+ 4195414144U, // t2UXTAHrr_rot
+ 4198494336U, // t2UXTB16r
+ 4198494336U, // t2UXTB16r_rot
+ 4200591488U, // t2UXTBr
+ 4200591488U, // t2UXTBr_rot
+ 4196397184U, // t2UXTHr
+ 4196397184U, // t2UXTHr_rot
+ 16704U, // tADC
+ 17408U, // tADDhirr
+ 7168U, // tADDi3
+ 12288U, // tADDi8
+ 40960U, // tADDrPCi
+ 17512U, // tADDrSP
+ 43008U, // tADDrSPi
+ 6144U, // tADDrr
+ 45056U, // tADDspi
+ 17541U, // tADDspr
0U, // tADDspr_
0U, // tADJCALLSTACKDOWN
0U, // tADJCALLSTACKUP
- 0U, // tAND
+ 16384U, // tAND
0U, // tANDsp
- 0U, // tASRri
- 0U, // tASRrr
- 0U, // tB
- 0U, // tBIC
- 0U, // tBL
- 0U, // tBLXi
- 0U, // tBLXi_r9
- 0U, // tBLXr
- 0U, // tBLXr_r9
- 0U, // tBLr9
- 0U, // tBRIND
- 0U, // tBR_JTr
+ 4096U, // tASRri
+ 16640U, // tASRrr
+ 57344U, // tB
+ 17280U, // tBIC
+ 4026585088U, // tBL
+ 4026580992U, // tBLXi
+ 4026580992U, // tBLXi_r9
+ 18304U, // tBLXr
+ 18304U, // tBLXr_r9
+ 4026585088U, // tBLr9
+ 18055U, // tBRIND
+ 18055U, // tBR_JTr
0U, // tBX
- 0U, // tBX_RET
- 0U, // tBX_RET_vararg
+ 18288U, // tBX_RET
+ 18176U, // tBX_RET_vararg
0U, // tBXr9
- 0U, // tBcc
- 0U, // tBfar
- 0U, // tCBNZ
- 0U, // tCBZ
- 0U, // tCMN
- 0U, // tCMNZ
- 0U, // tCMPhir
- 0U, // tCMPi8
- 0U, // tCMPr
- 0U, // tCMPzhir
- 0U, // tCMPzi8
- 0U, // tCMPzr
- 0U, // tEOR
+ 53248U, // tBcc
+ 4026585088U, // tBfar
+ 47360U, // tCBNZ
+ 45312U, // tCBZ
+ 17088U, // tCMN
+ 17088U, // tCMNz
+ 17664U, // tCMPhir
+ 10240U, // tCMPi8
+ 17024U, // tCMPr
+ 17664U, // tCMPzhir
+ 10240U, // tCMPzi8
+ 17024U, // tCMPzr
+ 16448U, // tEOR
0U, // tInt_eh_sjlj_setjmp
- 0U, // tLDM
- 0U, // tLDR
- 0U, // tLDRB
- 0U, // tLDRH
- 0U, // tLDRSB
- 0U, // tLDRSH
- 0U, // tLDRcp
- 0U, // tLDRpci
+ 51200U, // tLDM
+ 22528U, // tLDR
+ 23552U, // tLDRB
+ 23040U, // tLDRH
+ 22016U, // tLDRSB
+ 24064U, // tLDRSH
+ 38912U, // tLDRcp
+ 18432U, // tLDRpci
0U, // tLDRpci_pic
- 0U, // tLDRspi
- 0U, // tLEApcrel
- 0U, // tLEApcrelJT
+ 38912U, // tLDRspi
+ 40960U, // tLEApcrel
+ 40960U, // tLEApcrelJT
0U, // tLSLri
- 0U, // tLSLrr
- 0U, // tLSRri
- 0U, // tLSRrr
- 0U, // tMOVCCi
- 0U, // tMOVCCr
+ 16512U, // tLSLrr
+ 2048U, // tLSRri
+ 16576U, // tLSRrr
+ 8192U, // tMOVCCi
+ 17920U, // tMOVCCr
0U, // tMOVCCr_pseudo
0U, // tMOVSr
- 0U, // tMOVgpr2gpr
- 0U, // tMOVgpr2tgpr
- 0U, // tMOVi8
- 0U, // tMOVr
- 0U, // tMOVtgpr2gpr
- 0U, // tMUL
- 0U, // tMVN
- 0U, // tORR
- 0U, // tPICADD
- 0U, // tPOP
- 0U, // tPOP_RET
- 0U, // tPUSH
- 0U, // tREV
- 0U, // tREV16
- 0U, // tREVSH
- 0U, // tROR
- 0U, // tRSB
- 0U, // tRestore
- 0U, // tSBC
- 0U, // tSTM
- 0U, // tSTR
- 0U, // tSTRB
- 0U, // tSTRH
- 0U, // tSTRspi
- 0U, // tSUBi3
- 0U, // tSUBi8
- 0U, // tSUBrr
- 0U, // tSUBspi
+ 18112U, // tMOVgpr2gpr
+ 17984U, // tMOVgpr2tgpr
+ 8192U, // tMOVi8
+ 17920U, // tMOVr
+ 18048U, // tMOVtgpr2gpr
+ 17216U, // tMUL
+ 17344U, // tMVN
+ 17152U, // tORR
+ 17528U, // tPICADD
+ 48128U, // tPOP
+ 48128U, // tPOP_RET
+ 46080U, // tPUSH
+ 47616U, // tREV
+ 47680U, // tREV16
+ 47808U, // tREVSH
+ 16832U, // tROR
+ 16960U, // tRSB
+ 38912U, // tRestore
+ 16768U, // tSBC
+ 49152U, // tSTM
+ 20480U, // tSTR
+ 21504U, // tSTRB
+ 20992U, // tSTRH
+ 36864U, // tSTRspi
+ 7680U, // tSUBi3
+ 14336U, // tSUBi8
+ 6656U, // tSUBrr
+ 45184U, // tSUBspi
0U, // tSUBspi_
- 0U, // tSXTB
- 0U, // tSXTH
- 0U, // tSpill
- 0U, // tTPsoft
- 0U, // tTST
- 0U, // tUXTB
- 0U, // tUXTH
+ 45632U, // tSXTB
+ 45568U, // tSXTH
+ 36864U, // tSpill
+ 4026585088U, // tTPsoft
+ 16896U, // tTST
+ 45760U, // tUXTB
+ 45696U, // tUXTH
0U
};
const unsigned opcode = MI.getOpcode();
@@ -2975,7 +2975,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::tCBNZ:
case ARM::tCBZ:
case ARM::tCMN:
- case ARM::tCMNZ:
+ case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
case ARM::tCMPr:
diff --git a/libclamav/c++/ARMGenDAGISel.inc b/libclamav/c++/ARMGenDAGISel.inc
index 8ffbed3..c03b62e 100644
--- a/libclamav/c++/ARMGenDAGISel.inc
+++ b/libclamav/c++/ARMGenDAGISel.inc
@@ -2651,7 +2651,7 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
SDValue N0 = N.getOperand(0);
// Pattern: (ARMcmpZ:isVoid tGPR:i32:$lhs, (sub:i32 0:i32, tGPR:i32:$rhs))
- // Emits: (tCMNZ:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tCMNz:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
// Pattern complexity = 11 cost = 1 size = 0
{
SDValue N1 = N.getOperand(1);
@@ -2663,7 +2663,7 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
if (CN1 == INT64_C(0)) {
SDValue N11 = N1.getOperand(1);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_10(N, ARM::tCMNZ);
+ SDNode *Result = Emit_10(N, ARM::tCMNz);
return Result;
}
}
@@ -2773,7 +2773,7 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
}
// Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, tGPR:i32:$rhs), tGPR:i32:$lhs)
- // Emits: (tCMNZ:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tCMNz:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
// Pattern complexity = 11 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
SDValue N0 = N.getOperand(0);
@@ -2786,7 +2786,7 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
SDValue N01 = N0.getOperand(1);
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_24(N, ARM::tCMNZ);
+ SDNode *Result = Emit_24(N, ARM::tCMNz);
return Result;
}
}
diff --git a/libclamav/c++/ARMGenInstrInfo.inc b/libclamav/c++/ARMGenInstrInfo.inc
index 9917512..d542084 100644
--- a/libclamav/c++/ARMGenInstrInfo.inc
+++ b/libclamav/c++/ARMGenInstrInfo.inc
@@ -11,15 +11,16 @@ namespace llvm {
static const unsigned ImplicitList1[] = { ARM::CPSR, 0 };
static const TargetRegisterClass* Barriers1[] = { &ARM::CCRRegClass, NULL };
static const unsigned ImplicitList2[] = { ARM::SP, 0 };
-static const TargetRegisterClass* Barriers2[] = { &ARM::CCRRegClass, &ARM::DPR_8RegClass, NULL };
+static const TargetRegisterClass* Barriers2[] = { &ARM::JustSPRegClass, NULL };
+static const TargetRegisterClass* Barriers3[] = { &ARM::CCRRegClass, &ARM::DPR_8RegClass, NULL };
static const unsigned ImplicitList3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::CPSR, ARM::FPSCR, 0 };
static const unsigned ImplicitList4[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R9, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::CPSR, ARM::FPSCR, 0 };
static const unsigned ImplicitList5[] = { ARM::FPSCR, 0 };
-static const TargetRegisterClass* Barriers3[] = { &ARM::DPRRegClass, &ARM::DPR_8RegClass, &ARM::DPR_VFP2RegClass, &ARM::tGPRRegClass, NULL };
+static const TargetRegisterClass* Barriers4[] = { &ARM::DPRRegClass, &ARM::DPR_8RegClass, &ARM::DPR_VFP2RegClass, &ARM::tGPRRegClass, NULL };
static const unsigned ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 0 };
static const unsigned ImplicitList7[] = { ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, 0 };
static const unsigned ImplicitList8[] = { ARM::LR, 0 };
-static const TargetRegisterClass* Barriers4[] = { &ARM::tGPRRegClass, NULL };
+static const TargetRegisterClass* Barriers5[] = { &ARM::tGPRRegClass, NULL };
static const unsigned ImplicitList9[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, 0 };
static const unsigned ImplicitList10[] = { ARM::R0, ARM::LR, 0 };
@@ -61,123 +62,125 @@ static const TargetOperandInfo OperandInfo36[] = { { ARM::GPRRegClassID, 0, 0 },
static const TargetOperandInfo OperandInfo37[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
static const TargetOperandInfo OperandInfo38[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo39[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo40[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo41[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo42[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo43[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo44[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo45[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo46[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo47[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo48[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo49[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo50[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo51[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo52[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo53[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo54[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo55[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo56[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo57[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo58[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo59[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo60[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo61[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo62[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo63[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo64[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo65[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo66[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo67[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo68[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo69[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo70[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo71[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo72[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo73[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo74[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo75[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo76[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo77[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((4 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo78[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo79[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo80[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo81[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo82[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo83[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo84[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo85[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo86[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo87[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo88[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo89[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo90[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo91[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo92[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo93[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo94[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo95[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo96[] = { { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo97[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo98[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo99[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo100[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo101[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo102[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo103[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo104[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo105[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo106[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo107[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo108[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo109[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo110[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo111[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo112[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo113[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo114[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo115[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo116[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo117[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo118[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo119[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo120[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo121[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo122[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo123[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo124[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo125[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo126[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo127[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo128[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo129[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo130[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo131[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo132[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo133[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo134[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo135[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo136[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo137[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo138[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo139[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo140[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo141[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo142[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo143[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo144[] = { { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo145[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo146[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo147[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo148[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo149[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo150[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo151[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo152[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo153[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo154[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo155[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo156[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo40[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo41[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo42[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo43[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo44[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo45[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo46[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo47[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo48[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo49[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo50[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo51[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo52[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo53[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo54[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo55[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo56[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo57[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo58[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo59[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo60[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo61[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo62[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo63[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo64[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo65[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo66[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo67[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo68[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo69[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo70[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo71[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo72[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo73[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo74[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo75[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo76[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo77[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo78[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo79[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((4 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo80[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo81[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo82[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo83[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo84[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo85[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo86[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo87[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo88[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo89[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo90[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo91[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo92[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo93[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo94[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo95[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo96[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo97[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo98[] = { { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo99[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo100[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo101[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo102[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo103[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo104[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo105[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo106[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo107[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo108[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo109[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo110[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo111[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo112[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo113[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo114[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo115[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo116[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo117[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo118[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo119[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo120[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo121[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo122[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo123[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo124[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo125[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo126[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo127[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo128[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo129[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo130[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo131[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo132[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo133[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo134[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo135[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo136[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo137[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo138[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo139[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo140[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo141[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo142[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo143[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo144[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo145[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo146[] = { { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo147[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo148[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo149[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo150[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo151[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::JustSPRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo152[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo153[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo154[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo155[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo156[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo157[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo158[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
static const TargetInstrDesc ARMInsts[] = {
{ 0, 0, 0, 128, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #0 = PHI
@@ -189,7 +192,7 @@ static const TargetInstrDesc ARMInsts[] = {
{ 6, 3, 1, 128, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #6 = EXTRACT_SUBREG
{ 7, 4, 1, 128, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo27 }, // Inst #7 = INSERT_SUBREG
{ 8, 1, 1, 128, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #8 = IMPLICIT_DEF
- { 9, 4, 1, 128, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo40 }, // Inst #9 = SUBREG_TO_REG
+ { 9, 4, 1, 128, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #9 = SUBREG_TO_REG
{ 10, 3, 1, 128, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #10 = COPY_TO_REGCLASS
{ 11, 3, 1, 88, "ADCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #11 = ADCSSri
{ 12, 3, 1, 89, "ADCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #12 = ADCSSrr
@@ -203,8 +206,8 @@ static const TargetInstrDesc ARMInsts[] = {
{ 20, 6, 1, 88, "ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #20 = ADDri
{ 21, 6, 1, 89, "ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #21 = ADDrr
{ 22, 8, 1, 91, "ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #22 = ADDrs
- { 23, 3, 0, 128, "ADJCALLSTACKDOWN", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo11 }, // Inst #23 = ADJCALLSTACKDOWN
- { 24, 4, 0, 128, "ADJCALLSTACKUP", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo12 }, // Inst #24 = ADJCALLSTACKUP
+ { 23, 3, 0, 128, "ADJCALLSTACKDOWN", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, Barriers2, OperandInfo11 }, // Inst #23 = ADJCALLSTACKDOWN
+ { 24, 4, 0, 128, "ADJCALLSTACKUP", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, Barriers2, OperandInfo12 }, // Inst #24 = ADJCALLSTACKUP
{ 25, 6, 1, 88, "ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #25 = ANDri
{ 26, 6, 1, 89, "ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #26 = ANDrr
{ 27, 8, 1, 91, "ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #27 = ANDrs
@@ -237,19 +240,19 @@ static const TargetInstrDesc ARMInsts[] = {
{ 54, 6, 1, 88, "BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #54 = BICri
{ 55, 6, 1, 89, "BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #55 = BICrr
{ 56, 8, 1, 91, "BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #56 = BICrs
- { 57, 1, 0, 0, "BL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #57 = BL
- { 58, 1, 0, 0, "BLX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #58 = BLX
- { 59, 1, 0, 0, "BLXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #59 = BLXr9
- { 60, 3, 0, 0, "BL_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo11 }, // Inst #60 = BL_pred
- { 61, 1, 0, 0, "BLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #61 = BLr9
- { 62, 3, 0, 0, "BLr9_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo11 }, // Inst #62 = BLr9_pred
+ { 57, 1, 0, 0, "BL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers3, OperandInfo14 }, // Inst #57 = BL
+ { 58, 1, 0, 0, "BLX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList3, Barriers3, OperandInfo16 }, // Inst #58 = BLX
+ { 59, 1, 0, 0, "BLXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList4, Barriers3, OperandInfo16 }, // Inst #59 = BLXr9
+ { 60, 3, 0, 0, "BL_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers3, OperandInfo11 }, // Inst #60 = BL_pred
+ { 61, 1, 0, 0, "BLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers3, OperandInfo14 }, // Inst #61 = BLr9
+ { 62, 3, 0, 0, "BLr9_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers3, OperandInfo11 }, // Inst #62 = BLr9_pred
{ 63, 1, 0, 0, "BRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #63 = BRIND
{ 64, 4, 0, 0, "BR_JTadd", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #64 = BR_JTadd
{ 65, 5, 0, 0, "BR_JTm", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo18 }, // Inst #65 = BR_JTm
{ 66, 3, 0, 0, "BR_JTr", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #66 = BR_JTr
- { 67, 1, 0, 0, "BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #67 = BX
+ { 67, 1, 0, 0, "BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers3, OperandInfo16 }, // Inst #67 = BX
{ 68, 2, 0, 0, "BX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #68 = BX_RET
- { 69, 1, 0, 0, "BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #69 = BXr9
+ { 69, 1, 0, 0, "BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers3, OperandInfo16 }, // Inst #69 = BXr9
{ 70, 3, 0, 0, "Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #70 = Bcc
{ 71, 4, 1, 125, "CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #71 = CLZ
{ 72, 4, 0, 97, "CMNri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #72 = CMNri
@@ -275,7 +278,7 @@ static const TargetInstrDesc ARMInsts[] = {
{ 92, 0, 0, 128, "Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #92 = Int_MemBarrierV7
{ 93, 1, 0, 128, "Int_SyncBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #93 = Int_SyncBarrierV6
{ 94, 0, 0, 128, "Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #94 = Int_SyncBarrierV7
- { 95, 1, 0, 128, "Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers3, OperandInfo16 }, // Inst #95 = Int_eh_sjlj_setjmp
+ { 95, 1, 0, 128, "Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers4, OperandInfo16 }, // Inst #95 = Int_eh_sjlj_setjmp
{ 96, 5, 0, 103, "LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #96 = LDM
{ 97, 5, 0, 0, "LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #97 = LDM_RET
{ 98, 6, 1, 104, "LDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #98 = LDR
@@ -375,10 +378,10 @@ static const TargetInstrDesc ARMInsts[] = {
{ 192, 7, 1, 122, "STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #192 = STRB_POST
{ 193, 7, 1, 122, "STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #193 = STRB_PRE
{ 194, 7, 0, 121, "STRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #194 = STRD
- { 195, 5, 1, 128, "STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #195 = STREX
- { 196, 5, 1, 128, "STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #196 = STREXB
- { 197, 6, 1, 128, "STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #197 = STREXD
- { 198, 5, 1, 128, "STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #198 = STREXH
+ { 195, 5, 1, 128, "STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #195 = STREX
+ { 196, 5, 1, 128, "STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #196 = STREXB
+ { 197, 6, 1, 128, "STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #197 = STREXD
+ { 198, 5, 1, 128, "STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #198 = STREXH
{ 199, 6, 0, 121, "STRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #199 = STRH
{ 200, 7, 1, 122, "STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #200 = STRH_POST
{ 201, 7, 1, 122, "STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #201 = STRH_PRE
@@ -419,968 +422,968 @@ static const TargetInstrDesc ARMInsts[] = {
{ 236, 5, 1, 126, "UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #236 = UXTBr_rot
{ 237, 4, 1, 125, "UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #237 = UXTHr
{ 238, 5, 1, 126, "UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #238 = UXTHr_rot
- { 239, 6, 1, 17, "VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #239 = VABALsv2i64
- { 240, 6, 1, 17, "VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #240 = VABALsv4i32
- { 241, 6, 1, 17, "VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #241 = VABALsv8i16
- { 242, 6, 1, 17, "VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #242 = VABALuv2i64
- { 243, 6, 1, 17, "VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #243 = VABALuv4i32
- { 244, 6, 1, 17, "VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #244 = VABALuv8i16
- { 245, 6, 1, 18, "VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #245 = VABAsv16i8
- { 246, 6, 1, 19, "VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #246 = VABAsv2i32
- { 247, 6, 1, 17, "VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #247 = VABAsv4i16
- { 248, 6, 1, 20, "VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #248 = VABAsv4i32
- { 249, 6, 1, 18, "VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #249 = VABAsv8i16
- { 250, 6, 1, 17, "VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #250 = VABAsv8i8
- { 251, 6, 1, 18, "VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #251 = VABAuv16i8
- { 252, 6, 1, 19, "VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #252 = VABAuv2i32
- { 253, 6, 1, 17, "VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #253 = VABAuv4i16
- { 254, 6, 1, 20, "VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #254 = VABAuv4i32
- { 255, 6, 1, 18, "VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #255 = VABAuv8i16
- { 256, 6, 1, 17, "VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #256 = VABAuv8i8
- { 257, 5, 1, 4, "VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #257 = VABDLsv2i64
- { 258, 5, 1, 4, "VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #258 = VABDLsv4i32
- { 259, 5, 1, 4, "VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #259 = VABDLsv8i16
- { 260, 5, 1, 4, "VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #260 = VABDLuv2i64
- { 261, 5, 1, 4, "VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #261 = VABDLuv4i32
- { 262, 5, 1, 4, "VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #262 = VABDLuv8i16
- { 263, 5, 1, 1, "VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #263 = VABDfd
- { 264, 5, 1, 2, "VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #264 = VABDfq
- { 265, 5, 1, 4, "VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #265 = VABDsv16i8
- { 266, 5, 1, 3, "VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #266 = VABDsv2i32
- { 267, 5, 1, 3, "VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #267 = VABDsv4i16
- { 268, 5, 1, 4, "VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #268 = VABDsv4i32
- { 269, 5, 1, 4, "VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #269 = VABDsv8i16
- { 270, 5, 1, 3, "VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #270 = VABDsv8i8
- { 271, 5, 1, 4, "VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #271 = VABDuv16i8
- { 272, 5, 1, 3, "VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #272 = VABDuv2i32
- { 273, 5, 1, 3, "VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #273 = VABDuv4i16
- { 274, 5, 1, 4, "VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #274 = VABDuv4i32
- { 275, 5, 1, 4, "VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #275 = VABDuv8i16
- { 276, 5, 1, 3, "VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #276 = VABDuv8i8
- { 277, 4, 1, 87, "VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #277 = VABSD
- { 278, 4, 1, 86, "VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #278 = VABSS
- { 279, 4, 1, 57, "VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #279 = VABSfd
- { 280, 4, 1, 57, "VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #280 = VABSfd_sfp
- { 281, 4, 1, 58, "VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #281 = VABSfq
- { 282, 4, 1, 60, "VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #282 = VABSv16i8
- { 283, 4, 1, 59, "VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #283 = VABSv2i32
- { 284, 4, 1, 59, "VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #284 = VABSv4i16
- { 285, 4, 1, 60, "VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #285 = VABSv4i32
- { 286, 4, 1, 60, "VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #286 = VABSv8i16
- { 287, 4, 1, 59, "VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #287 = VABSv8i8
- { 288, 5, 1, 1, "VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #288 = VACGEd
- { 289, 5, 1, 2, "VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #289 = VACGEq
- { 290, 5, 1, 1, "VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #290 = VACGTd
- { 291, 5, 1, 2, "VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #291 = VACGTq
- { 292, 5, 1, 62, "VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #292 = VADDD
- { 293, 5, 1, 3, "VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #293 = VADDHNv2i32
- { 294, 5, 1, 3, "VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #294 = VADDHNv4i16
- { 295, 5, 1, 3, "VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #295 = VADDHNv8i8
- { 296, 5, 1, 44, "VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #296 = VADDLsv2i64
- { 297, 5, 1, 44, "VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #297 = VADDLsv4i32
- { 298, 5, 1, 44, "VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #298 = VADDLsv8i16
- { 299, 5, 1, 44, "VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #299 = VADDLuv2i64
- { 300, 5, 1, 44, "VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #300 = VADDLuv4i32
- { 301, 5, 1, 44, "VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #301 = VADDLuv8i16
- { 302, 5, 1, 61, "VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #302 = VADDS
- { 303, 5, 1, 47, "VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #303 = VADDWsv2i64
- { 304, 5, 1, 47, "VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #304 = VADDWsv4i32
- { 305, 5, 1, 47, "VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #305 = VADDWsv8i16
- { 306, 5, 1, 47, "VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #306 = VADDWuv2i64
- { 307, 5, 1, 47, "VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #307 = VADDWuv4i32
- { 308, 5, 1, 47, "VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #308 = VADDWuv8i16
- { 309, 5, 1, 1, "VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #309 = VADDfd
- { 310, 5, 1, 1, "VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #310 = VADDfd_sfp
- { 311, 5, 1, 2, "VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #311 = VADDfq
- { 312, 5, 1, 6, "VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #312 = VADDv16i8
- { 313, 5, 1, 5, "VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #313 = VADDv1i64
- { 314, 5, 1, 5, "VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #314 = VADDv2i32
- { 315, 5, 1, 6, "VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #315 = VADDv2i64
- { 316, 5, 1, 5, "VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #316 = VADDv4i16
- { 317, 5, 1, 6, "VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #317 = VADDv4i32
- { 318, 5, 1, 6, "VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #318 = VADDv8i16
- { 319, 5, 1, 5, "VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #319 = VADDv8i8
- { 320, 5, 1, 5, "VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #320 = VANDd
- { 321, 5, 1, 6, "VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #321 = VANDq
- { 322, 5, 1, 5, "VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #322 = VBICd
- { 323, 5, 1, 6, "VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #323 = VBICq
- { 324, 6, 1, 7, "VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #324 = VBSLd
- { 325, 6, 1, 8, "VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #325 = VBSLq
- { 326, 5, 1, 1, "VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #326 = VCEQfd
- { 327, 5, 1, 2, "VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #327 = VCEQfq
- { 328, 5, 1, 4, "VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #328 = VCEQv16i8
- { 329, 5, 1, 3, "VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #329 = VCEQv2i32
- { 330, 5, 1, 3, "VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #330 = VCEQv4i16
- { 331, 5, 1, 4, "VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #331 = VCEQv4i32
- { 332, 5, 1, 4, "VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #332 = VCEQv8i16
- { 333, 5, 1, 3, "VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #333 = VCEQv8i8
- { 334, 5, 1, 1, "VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #334 = VCGEfd
- { 335, 5, 1, 2, "VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #335 = VCGEfq
- { 336, 5, 1, 4, "VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #336 = VCGEsv16i8
- { 337, 5, 1, 3, "VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #337 = VCGEsv2i32
- { 338, 5, 1, 3, "VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #338 = VCGEsv4i16
- { 339, 5, 1, 4, "VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #339 = VCGEsv4i32
- { 340, 5, 1, 4, "VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #340 = VCGEsv8i16
- { 341, 5, 1, 3, "VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #341 = VCGEsv8i8
- { 342, 5, 1, 4, "VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #342 = VCGEuv16i8
- { 343, 5, 1, 3, "VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #343 = VCGEuv2i32
- { 344, 5, 1, 3, "VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #344 = VCGEuv4i16
- { 345, 5, 1, 4, "VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #345 = VCGEuv4i32
- { 346, 5, 1, 4, "VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #346 = VCGEuv8i16
- { 347, 5, 1, 3, "VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #347 = VCGEuv8i8
- { 348, 5, 1, 1, "VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #348 = VCGTfd
- { 349, 5, 1, 2, "VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #349 = VCGTfq
- { 350, 5, 1, 4, "VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #350 = VCGTsv16i8
- { 351, 5, 1, 3, "VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #351 = VCGTsv2i32
- { 352, 5, 1, 3, "VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #352 = VCGTsv4i16
- { 353, 5, 1, 4, "VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #353 = VCGTsv4i32
- { 354, 5, 1, 4, "VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #354 = VCGTsv8i16
- { 355, 5, 1, 3, "VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #355 = VCGTsv8i8
- { 356, 5, 1, 4, "VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #356 = VCGTuv16i8
- { 357, 5, 1, 3, "VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #357 = VCGTuv2i32
- { 358, 5, 1, 3, "VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #358 = VCGTuv4i16
- { 359, 5, 1, 4, "VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #359 = VCGTuv4i32
- { 360, 5, 1, 4, "VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #360 = VCGTuv8i16
- { 361, 5, 1, 3, "VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #361 = VCGTuv8i8
- { 362, 4, 1, 8, "VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #362 = VCLSv16i8
- { 363, 4, 1, 7, "VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #363 = VCLSv2i32
- { 364, 4, 1, 7, "VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #364 = VCLSv4i16
- { 365, 4, 1, 8, "VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #365 = VCLSv4i32
- { 366, 4, 1, 8, "VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #366 = VCLSv8i16
- { 367, 4, 1, 7, "VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #367 = VCLSv8i8
- { 368, 4, 1, 8, "VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #368 = VCLZv16i8
- { 369, 4, 1, 7, "VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #369 = VCLZv2i32
- { 370, 4, 1, 7, "VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #370 = VCLZv4i16
- { 371, 4, 1, 8, "VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #371 = VCLZv4i32
- { 372, 4, 1, 8, "VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #372 = VCLZv8i16
- { 373, 4, 1, 7, "VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #373 = VCLZv8i8
- { 374, 4, 0, 64, "VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo47 }, // Inst #374 = VCMPED
- { 375, 4, 0, 63, "VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo48 }, // Inst #375 = VCMPES
- { 376, 3, 0, 64, "VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo55 }, // Inst #376 = VCMPEZD
- { 377, 3, 0, 63, "VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo56 }, // Inst #377 = VCMPEZS
- { 378, 4, 1, 7, "VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #378 = VCNTd
- { 379, 4, 1, 8, "VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #379 = VCNTq
- { 380, 4, 1, 66, "VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #380 = VCVTDS
- { 381, 4, 1, 69, "VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #381 = VCVTSD
- { 382, 4, 1, 57, "VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #382 = VCVTf2sd
- { 383, 4, 1, 57, "VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #383 = VCVTf2sd_sfp
- { 384, 4, 1, 58, "VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #384 = VCVTf2sq
- { 385, 4, 1, 57, "VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #385 = VCVTf2ud
- { 386, 4, 1, 57, "VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #386 = VCVTf2ud_sfp
- { 387, 4, 1, 58, "VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #387 = VCVTf2uq
- { 388, 5, 1, 57, "VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #388 = VCVTf2xsd
- { 389, 5, 1, 58, "VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #389 = VCVTf2xsq
- { 390, 5, 1, 57, "VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #390 = VCVTf2xud
- { 391, 5, 1, 58, "VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #391 = VCVTf2xuq
- { 392, 4, 1, 57, "VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #392 = VCVTs2fd
- { 393, 4, 1, 57, "VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #393 = VCVTs2fd_sfp
- { 394, 4, 1, 58, "VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #394 = VCVTs2fq
- { 395, 4, 1, 57, "VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #395 = VCVTu2fd
- { 396, 4, 1, 57, "VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #396 = VCVTu2fd_sfp
- { 397, 4, 1, 58, "VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #397 = VCVTu2fq
- { 398, 5, 1, 57, "VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #398 = VCVTxs2fd
- { 399, 5, 1, 58, "VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #399 = VCVTxs2fq
- { 400, 5, 1, 57, "VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #400 = VCVTxu2fd
- { 401, 5, 1, 58, "VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #401 = VCVTxu2fq
- { 402, 5, 1, 72, "VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #402 = VDIVD
- { 403, 5, 1, 71, "VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #403 = VDIVS
- { 404, 4, 1, 24, "VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo61 }, // Inst #404 = VDUP16d
- { 405, 4, 1, 24, "VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo62 }, // Inst #405 = VDUP16q
- { 406, 4, 1, 24, "VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo61 }, // Inst #406 = VDUP32d
- { 407, 4, 1, 24, "VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo62 }, // Inst #407 = VDUP32q
- { 408, 4, 1, 24, "VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo61 }, // Inst #408 = VDUP8d
- { 409, 4, 1, 24, "VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo62 }, // Inst #409 = VDUP8q
- { 410, 5, 1, 21, "VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #410 = VDUPLN16d
- { 411, 5, 1, 21, "VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #411 = VDUPLN16q
- { 412, 5, 1, 21, "VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #412 = VDUPLN32d
- { 413, 5, 1, 21, "VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #413 = VDUPLN32q
- { 414, 5, 1, 21, "VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #414 = VDUPLN8d
- { 415, 5, 1, 21, "VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #415 = VDUPLN8q
- { 416, 5, 1, 21, "VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #416 = VDUPLNfd
- { 417, 5, 1, 21, "VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #417 = VDUPLNfq
- { 418, 4, 1, 24, "VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo61 }, // Inst #418 = VDUPfd
- { 419, 4, 1, 21, "VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #419 = VDUPfdf
- { 420, 4, 1, 24, "VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo62 }, // Inst #420 = VDUPfq
- { 421, 4, 1, 21, "VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #421 = VDUPfqf
- { 422, 5, 1, 5, "VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #422 = VEORd
- { 423, 5, 1, 6, "VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #423 = VEORq
- { 424, 6, 1, 9, "VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #424 = VEXTd16
- { 425, 6, 1, 9, "VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #425 = VEXTd32
- { 426, 6, 1, 9, "VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #426 = VEXTd8
- { 427, 6, 1, 9, "VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #427 = VEXTdf
- { 428, 6, 1, 10, "VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #428 = VEXTq16
- { 429, 6, 1, 10, "VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #429 = VEXTq32
- { 430, 6, 1, 10, "VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #430 = VEXTq8
- { 431, 6, 1, 10, "VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #431 = VEXTqf
- { 432, 5, 1, 28, "VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo67 }, // Inst #432 = VGETLNi32
- { 433, 5, 1, 28, "VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo67 }, // Inst #433 = VGETLNs16
- { 434, 5, 1, 28, "VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo67 }, // Inst #434 = VGETLNs8
- { 435, 5, 1, 28, "VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo67 }, // Inst #435 = VGETLNu16
- { 436, 5, 1, 28, "VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo67 }, // Inst #436 = VGETLNu8
- { 437, 5, 1, 4, "VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #437 = VHADDsv16i8
- { 438, 5, 1, 3, "VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #438 = VHADDsv2i32
- { 439, 5, 1, 3, "VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #439 = VHADDsv4i16
- { 440, 5, 1, 4, "VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #440 = VHADDsv4i32
- { 441, 5, 1, 4, "VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #441 = VHADDsv8i16
- { 442, 5, 1, 3, "VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #442 = VHADDsv8i8
- { 443, 5, 1, 4, "VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #443 = VHADDuv16i8
- { 444, 5, 1, 3, "VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #444 = VHADDuv2i32
- { 445, 5, 1, 3, "VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #445 = VHADDuv4i16
- { 446, 5, 1, 4, "VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #446 = VHADDuv4i32
- { 447, 5, 1, 4, "VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #447 = VHADDuv8i16
- { 448, 5, 1, 3, "VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #448 = VHADDuv8i8
- { 449, 5, 1, 4, "VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #449 = VHSUBsv16i8
- { 450, 5, 1, 3, "VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #450 = VHSUBsv2i32
- { 451, 5, 1, 3, "VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #451 = VHSUBsv4i16
- { 452, 5, 1, 4, "VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #452 = VHSUBsv4i32
- { 453, 5, 1, 4, "VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #453 = VHSUBsv8i16
- { 454, 5, 1, 3, "VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #454 = VHSUBsv8i8
- { 455, 5, 1, 4, "VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #455 = VHSUBuv16i8
- { 456, 5, 1, 3, "VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #456 = VHSUBuv2i32
- { 457, 5, 1, 3, "VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #457 = VHSUBuv4i16
- { 458, 5, 1, 4, "VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #458 = VHSUBuv4i32
- { 459, 5, 1, 4, "VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #459 = VHSUBuv8i16
- { 460, 5, 1, 3, "VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #460 = VHSUBuv8i8
- { 461, 7, 1, 11, "VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #461 = VLD1d16
- { 462, 7, 1, 11, "VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #462 = VLD1d32
- { 463, 7, 1, 11, "VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #463 = VLD1d64
- { 464, 7, 1, 11, "VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #464 = VLD1d8
- { 465, 7, 1, 11, "VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #465 = VLD1df
- { 466, 7, 1, 11, "VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #466 = VLD1q16
- { 467, 7, 1, 11, "VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #467 = VLD1q32
- { 468, 7, 1, 11, "VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #468 = VLD1q64
- { 469, 7, 1, 11, "VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #469 = VLD1q8
- { 470, 7, 1, 11, "VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #470 = VLD1qf
- { 471, 11, 2, 12, "VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #471 = VLD2LNd16
- { 472, 11, 2, 12, "VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #472 = VLD2LNd32
- { 473, 11, 2, 12, "VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #473 = VLD2LNd8
- { 474, 11, 2, 12, "VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #474 = VLD2LNq16a
- { 475, 11, 2, 12, "VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #475 = VLD2LNq16b
- { 476, 11, 2, 12, "VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #476 = VLD2LNq32a
- { 477, 11, 2, 12, "VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #477 = VLD2LNq32b
- { 478, 8, 2, 12, "VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #478 = VLD2d16
- { 479, 8, 2, 12, "VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #479 = VLD2d32
- { 480, 8, 2, 11, "VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #480 = VLD2d64
- { 481, 8, 2, 12, "VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #481 = VLD2d8
- { 482, 10, 4, 12, "VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #482 = VLD2q16
- { 483, 10, 4, 12, "VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #483 = VLD2q32
- { 484, 10, 4, 12, "VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #484 = VLD2q8
- { 485, 13, 3, 13, "VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #485 = VLD3LNd16
- { 486, 13, 3, 13, "VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #486 = VLD3LNd32
- { 487, 13, 3, 13, "VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #487 = VLD3LNd8
- { 488, 13, 3, 13, "VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #488 = VLD3LNq16a
- { 489, 13, 3, 13, "VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #489 = VLD3LNq16b
- { 490, 13, 3, 13, "VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #490 = VLD3LNq32a
- { 491, 13, 3, 13, "VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #491 = VLD3LNq32b
- { 492, 9, 3, 13, "VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #492 = VLD3d16
- { 493, 9, 3, 13, "VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #493 = VLD3d32
- { 494, 9, 3, 11, "VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #494 = VLD3d64
- { 495, 9, 3, 13, "VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #495 = VLD3d8
- { 496, 10, 4, 13, "VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #496 = VLD3q16a
- { 497, 10, 4, 13, "VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #497 = VLD3q16b
- { 498, 10, 4, 13, "VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #498 = VLD3q32a
- { 499, 10, 4, 13, "VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #499 = VLD3q32b
- { 500, 10, 4, 13, "VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #500 = VLD3q8a
- { 501, 10, 4, 13, "VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #501 = VLD3q8b
- { 502, 15, 4, 14, "VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #502 = VLD4LNd16
- { 503, 15, 4, 14, "VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #503 = VLD4LNd32
- { 504, 15, 4, 14, "VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #504 = VLD4LNd8
- { 505, 15, 4, 14, "VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #505 = VLD4LNq16a
- { 506, 15, 4, 14, "VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #506 = VLD4LNq16b
- { 507, 15, 4, 14, "VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #507 = VLD4LNq32a
- { 508, 15, 4, 14, "VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #508 = VLD4LNq32b
- { 509, 10, 4, 14, "VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #509 = VLD4d16
- { 510, 10, 4, 14, "VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #510 = VLD4d32
- { 511, 10, 4, 11, "VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #511 = VLD4d64
- { 512, 10, 4, 14, "VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #512 = VLD4d8
- { 513, 11, 5, 14, "VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #513 = VLD4q16a
- { 514, 11, 5, 14, "VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #514 = VLD4q16b
- { 515, 11, 5, 14, "VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #515 = VLD4q32a
- { 516, 11, 5, 14, "VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #516 = VLD4q32b
- { 517, 11, 5, 14, "VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #517 = VLD4q8a
- { 518, 11, 5, 14, "VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #518 = VLD4q8b
+ { 239, 6, 1, 17, "VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #239 = VABALsv2i64
+ { 240, 6, 1, 17, "VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #240 = VABALsv4i32
+ { 241, 6, 1, 17, "VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #241 = VABALsv8i16
+ { 242, 6, 1, 17, "VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #242 = VABALuv2i64
+ { 243, 6, 1, 17, "VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #243 = VABALuv4i32
+ { 244, 6, 1, 17, "VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #244 = VABALuv8i16
+ { 245, 6, 1, 18, "VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #245 = VABAsv16i8
+ { 246, 6, 1, 19, "VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #246 = VABAsv2i32
+ { 247, 6, 1, 17, "VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #247 = VABAsv4i16
+ { 248, 6, 1, 20, "VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #248 = VABAsv4i32
+ { 249, 6, 1, 18, "VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #249 = VABAsv8i16
+ { 250, 6, 1, 17, "VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #250 = VABAsv8i8
+ { 251, 6, 1, 18, "VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #251 = VABAuv16i8
+ { 252, 6, 1, 19, "VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #252 = VABAuv2i32
+ { 253, 6, 1, 17, "VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #253 = VABAuv4i16
+ { 254, 6, 1, 20, "VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #254 = VABAuv4i32
+ { 255, 6, 1, 18, "VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #255 = VABAuv8i16
+ { 256, 6, 1, 17, "VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #256 = VABAuv8i8
+ { 257, 5, 1, 4, "VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #257 = VABDLsv2i64
+ { 258, 5, 1, 4, "VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #258 = VABDLsv4i32
+ { 259, 5, 1, 4, "VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #259 = VABDLsv8i16
+ { 260, 5, 1, 4, "VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #260 = VABDLuv2i64
+ { 261, 5, 1, 4, "VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #261 = VABDLuv4i32
+ { 262, 5, 1, 4, "VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #262 = VABDLuv8i16
+ { 263, 5, 1, 1, "VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #263 = VABDfd
+ { 264, 5, 1, 2, "VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #264 = VABDfq
+ { 265, 5, 1, 4, "VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #265 = VABDsv16i8
+ { 266, 5, 1, 3, "VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #266 = VABDsv2i32
+ { 267, 5, 1, 3, "VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #267 = VABDsv4i16
+ { 268, 5, 1, 4, "VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #268 = VABDsv4i32
+ { 269, 5, 1, 4, "VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #269 = VABDsv8i16
+ { 270, 5, 1, 3, "VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #270 = VABDsv8i8
+ { 271, 5, 1, 4, "VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #271 = VABDuv16i8
+ { 272, 5, 1, 3, "VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #272 = VABDuv2i32
+ { 273, 5, 1, 3, "VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #273 = VABDuv4i16
+ { 274, 5, 1, 4, "VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #274 = VABDuv4i32
+ { 275, 5, 1, 4, "VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #275 = VABDuv8i16
+ { 276, 5, 1, 3, "VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #276 = VABDuv8i8
+ { 277, 4, 1, 87, "VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #277 = VABSD
+ { 278, 4, 1, 86, "VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #278 = VABSS
+ { 279, 4, 1, 57, "VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #279 = VABSfd
+ { 280, 4, 1, 57, "VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #280 = VABSfd_sfp
+ { 281, 4, 1, 58, "VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #281 = VABSfq
+ { 282, 4, 1, 60, "VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #282 = VABSv16i8
+ { 283, 4, 1, 59, "VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #283 = VABSv2i32
+ { 284, 4, 1, 59, "VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #284 = VABSv4i16
+ { 285, 4, 1, 60, "VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #285 = VABSv4i32
+ { 286, 4, 1, 60, "VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #286 = VABSv8i16
+ { 287, 4, 1, 59, "VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #287 = VABSv8i8
+ { 288, 5, 1, 1, "VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #288 = VACGEd
+ { 289, 5, 1, 2, "VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #289 = VACGEq
+ { 290, 5, 1, 1, "VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #290 = VACGTd
+ { 291, 5, 1, 2, "VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #291 = VACGTq
+ { 292, 5, 1, 62, "VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #292 = VADDD
+ { 293, 5, 1, 3, "VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #293 = VADDHNv2i32
+ { 294, 5, 1, 3, "VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #294 = VADDHNv4i16
+ { 295, 5, 1, 3, "VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #295 = VADDHNv8i8
+ { 296, 5, 1, 44, "VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #296 = VADDLsv2i64
+ { 297, 5, 1, 44, "VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #297 = VADDLsv4i32
+ { 298, 5, 1, 44, "VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #298 = VADDLsv8i16
+ { 299, 5, 1, 44, "VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #299 = VADDLuv2i64
+ { 300, 5, 1, 44, "VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #300 = VADDLuv4i32
+ { 301, 5, 1, 44, "VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #301 = VADDLuv8i16
+ { 302, 5, 1, 61, "VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #302 = VADDS
+ { 303, 5, 1, 47, "VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #303 = VADDWsv2i64
+ { 304, 5, 1, 47, "VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #304 = VADDWsv4i32
+ { 305, 5, 1, 47, "VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #305 = VADDWsv8i16
+ { 306, 5, 1, 47, "VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #306 = VADDWuv2i64
+ { 307, 5, 1, 47, "VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #307 = VADDWuv4i32
+ { 308, 5, 1, 47, "VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #308 = VADDWuv8i16
+ { 309, 5, 1, 1, "VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #309 = VADDfd
+ { 310, 5, 1, 1, "VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #310 = VADDfd_sfp
+ { 311, 5, 1, 2, "VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #311 = VADDfq
+ { 312, 5, 1, 6, "VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #312 = VADDv16i8
+ { 313, 5, 1, 5, "VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #313 = VADDv1i64
+ { 314, 5, 1, 5, "VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #314 = VADDv2i32
+ { 315, 5, 1, 6, "VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #315 = VADDv2i64
+ { 316, 5, 1, 5, "VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #316 = VADDv4i16
+ { 317, 5, 1, 6, "VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #317 = VADDv4i32
+ { 318, 5, 1, 6, "VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #318 = VADDv8i16
+ { 319, 5, 1, 5, "VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #319 = VADDv8i8
+ { 320, 5, 1, 5, "VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #320 = VANDd
+ { 321, 5, 1, 6, "VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #321 = VANDq
+ { 322, 5, 1, 5, "VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #322 = VBICd
+ { 323, 5, 1, 6, "VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #323 = VBICq
+ { 324, 6, 1, 7, "VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #324 = VBSLd
+ { 325, 6, 1, 8, "VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #325 = VBSLq
+ { 326, 5, 1, 1, "VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #326 = VCEQfd
+ { 327, 5, 1, 2, "VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #327 = VCEQfq
+ { 328, 5, 1, 4, "VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #328 = VCEQv16i8
+ { 329, 5, 1, 3, "VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #329 = VCEQv2i32
+ { 330, 5, 1, 3, "VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #330 = VCEQv4i16
+ { 331, 5, 1, 4, "VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #331 = VCEQv4i32
+ { 332, 5, 1, 4, "VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #332 = VCEQv8i16
+ { 333, 5, 1, 3, "VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #333 = VCEQv8i8
+ { 334, 5, 1, 1, "VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #334 = VCGEfd
+ { 335, 5, 1, 2, "VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #335 = VCGEfq
+ { 336, 5, 1, 4, "VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #336 = VCGEsv16i8
+ { 337, 5, 1, 3, "VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #337 = VCGEsv2i32
+ { 338, 5, 1, 3, "VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #338 = VCGEsv4i16
+ { 339, 5, 1, 4, "VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #339 = VCGEsv4i32
+ { 340, 5, 1, 4, "VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #340 = VCGEsv8i16
+ { 341, 5, 1, 3, "VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #341 = VCGEsv8i8
+ { 342, 5, 1, 4, "VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #342 = VCGEuv16i8
+ { 343, 5, 1, 3, "VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #343 = VCGEuv2i32
+ { 344, 5, 1, 3, "VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #344 = VCGEuv4i16
+ { 345, 5, 1, 4, "VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #345 = VCGEuv4i32
+ { 346, 5, 1, 4, "VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #346 = VCGEuv8i16
+ { 347, 5, 1, 3, "VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #347 = VCGEuv8i8
+ { 348, 5, 1, 1, "VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #348 = VCGTfd
+ { 349, 5, 1, 2, "VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #349 = VCGTfq
+ { 350, 5, 1, 4, "VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #350 = VCGTsv16i8
+ { 351, 5, 1, 3, "VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #351 = VCGTsv2i32
+ { 352, 5, 1, 3, "VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #352 = VCGTsv4i16
+ { 353, 5, 1, 4, "VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #353 = VCGTsv4i32
+ { 354, 5, 1, 4, "VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #354 = VCGTsv8i16
+ { 355, 5, 1, 3, "VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #355 = VCGTsv8i8
+ { 356, 5, 1, 4, "VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #356 = VCGTuv16i8
+ { 357, 5, 1, 3, "VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #357 = VCGTuv2i32
+ { 358, 5, 1, 3, "VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #358 = VCGTuv4i16
+ { 359, 5, 1, 4, "VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #359 = VCGTuv4i32
+ { 360, 5, 1, 4, "VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #360 = VCGTuv8i16
+ { 361, 5, 1, 3, "VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #361 = VCGTuv8i8
+ { 362, 4, 1, 8, "VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #362 = VCLSv16i8
+ { 363, 4, 1, 7, "VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #363 = VCLSv2i32
+ { 364, 4, 1, 7, "VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #364 = VCLSv4i16
+ { 365, 4, 1, 8, "VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #365 = VCLSv4i32
+ { 366, 4, 1, 8, "VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #366 = VCLSv8i16
+ { 367, 4, 1, 7, "VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #367 = VCLSv8i8
+ { 368, 4, 1, 8, "VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #368 = VCLZv16i8
+ { 369, 4, 1, 7, "VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #369 = VCLZv2i32
+ { 370, 4, 1, 7, "VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #370 = VCLZv4i16
+ { 371, 4, 1, 8, "VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #371 = VCLZv4i32
+ { 372, 4, 1, 8, "VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #372 = VCLZv8i16
+ { 373, 4, 1, 7, "VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #373 = VCLZv8i8
+ { 374, 4, 0, 64, "VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo49 }, // Inst #374 = VCMPED
+ { 375, 4, 0, 63, "VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo50 }, // Inst #375 = VCMPES
+ { 376, 3, 0, 64, "VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo57 }, // Inst #376 = VCMPEZD
+ { 377, 3, 0, 63, "VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo58 }, // Inst #377 = VCMPEZS
+ { 378, 4, 1, 7, "VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #378 = VCNTd
+ { 379, 4, 1, 8, "VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #379 = VCNTq
+ { 380, 4, 1, 66, "VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #380 = VCVTDS
+ { 381, 4, 1, 69, "VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #381 = VCVTSD
+ { 382, 4, 1, 57, "VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #382 = VCVTf2sd
+ { 383, 4, 1, 57, "VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #383 = VCVTf2sd_sfp
+ { 384, 4, 1, 58, "VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #384 = VCVTf2sq
+ { 385, 4, 1, 57, "VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #385 = VCVTf2ud
+ { 386, 4, 1, 57, "VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #386 = VCVTf2ud_sfp
+ { 387, 4, 1, 58, "VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #387 = VCVTf2uq
+ { 388, 5, 1, 57, "VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #388 = VCVTf2xsd
+ { 389, 5, 1, 58, "VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #389 = VCVTf2xsq
+ { 390, 5, 1, 57, "VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #390 = VCVTf2xud
+ { 391, 5, 1, 58, "VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #391 = VCVTf2xuq
+ { 392, 4, 1, 57, "VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #392 = VCVTs2fd
+ { 393, 4, 1, 57, "VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #393 = VCVTs2fd_sfp
+ { 394, 4, 1, 58, "VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #394 = VCVTs2fq
+ { 395, 4, 1, 57, "VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #395 = VCVTu2fd
+ { 396, 4, 1, 57, "VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #396 = VCVTu2fd_sfp
+ { 397, 4, 1, 58, "VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #397 = VCVTu2fq
+ { 398, 5, 1, 57, "VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #398 = VCVTxs2fd
+ { 399, 5, 1, 58, "VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #399 = VCVTxs2fq
+ { 400, 5, 1, 57, "VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #400 = VCVTxu2fd
+ { 401, 5, 1, 58, "VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #401 = VCVTxu2fq
+ { 402, 5, 1, 72, "VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #402 = VDIVD
+ { 403, 5, 1, 71, "VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #403 = VDIVS
+ { 404, 4, 1, 24, "VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #404 = VDUP16d
+ { 405, 4, 1, 24, "VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #405 = VDUP16q
+ { 406, 4, 1, 24, "VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #406 = VDUP32d
+ { 407, 4, 1, 24, "VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #407 = VDUP32q
+ { 408, 4, 1, 24, "VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #408 = VDUP8d
+ { 409, 4, 1, 24, "VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #409 = VDUP8q
+ { 410, 5, 1, 21, "VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #410 = VDUPLN16d
+ { 411, 5, 1, 21, "VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #411 = VDUPLN16q
+ { 412, 5, 1, 21, "VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #412 = VDUPLN32d
+ { 413, 5, 1, 21, "VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #413 = VDUPLN32q
+ { 414, 5, 1, 21, "VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #414 = VDUPLN8d
+ { 415, 5, 1, 21, "VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #415 = VDUPLN8q
+ { 416, 5, 1, 21, "VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #416 = VDUPLNfd
+ { 417, 5, 1, 21, "VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #417 = VDUPLNfq
+ { 418, 4, 1, 24, "VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #418 = VDUPfd
+ { 419, 4, 1, 21, "VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #419 = VDUPfdf
+ { 420, 4, 1, 24, "VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #420 = VDUPfq
+ { 421, 4, 1, 21, "VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #421 = VDUPfqf
+ { 422, 5, 1, 5, "VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #422 = VEORd
+ { 423, 5, 1, 6, "VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #423 = VEORq
+ { 424, 6, 1, 9, "VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #424 = VEXTd16
+ { 425, 6, 1, 9, "VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #425 = VEXTd32
+ { 426, 6, 1, 9, "VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #426 = VEXTd8
+ { 427, 6, 1, 9, "VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #427 = VEXTdf
+ { 428, 6, 1, 10, "VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #428 = VEXTq16
+ { 429, 6, 1, 10, "VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #429 = VEXTq32
+ { 430, 6, 1, 10, "VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #430 = VEXTq8
+ { 431, 6, 1, 10, "VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #431 = VEXTqf
+ { 432, 5, 1, 28, "VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #432 = VGETLNi32
+ { 433, 5, 1, 28, "VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #433 = VGETLNs16
+ { 434, 5, 1, 28, "VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #434 = VGETLNs8
+ { 435, 5, 1, 28, "VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #435 = VGETLNu16
+ { 436, 5, 1, 28, "VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #436 = VGETLNu8
+ { 437, 5, 1, 4, "VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #437 = VHADDsv16i8
+ { 438, 5, 1, 3, "VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #438 = VHADDsv2i32
+ { 439, 5, 1, 3, "VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #439 = VHADDsv4i16
+ { 440, 5, 1, 4, "VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #440 = VHADDsv4i32
+ { 441, 5, 1, 4, "VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #441 = VHADDsv8i16
+ { 442, 5, 1, 3, "VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #442 = VHADDsv8i8
+ { 443, 5, 1, 4, "VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #443 = VHADDuv16i8
+ { 444, 5, 1, 3, "VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #444 = VHADDuv2i32
+ { 445, 5, 1, 3, "VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #445 = VHADDuv4i16
+ { 446, 5, 1, 4, "VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #446 = VHADDuv4i32
+ { 447, 5, 1, 4, "VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #447 = VHADDuv8i16
+ { 448, 5, 1, 3, "VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #448 = VHADDuv8i8
+ { 449, 5, 1, 4, "VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #449 = VHSUBsv16i8
+ { 450, 5, 1, 3, "VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #450 = VHSUBsv2i32
+ { 451, 5, 1, 3, "VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #451 = VHSUBsv4i16
+ { 452, 5, 1, 4, "VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #452 = VHSUBsv4i32
+ { 453, 5, 1, 4, "VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #453 = VHSUBsv8i16
+ { 454, 5, 1, 3, "VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #454 = VHSUBsv8i8
+ { 455, 5, 1, 4, "VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #455 = VHSUBuv16i8
+ { 456, 5, 1, 3, "VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #456 = VHSUBuv2i32
+ { 457, 5, 1, 3, "VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #457 = VHSUBuv4i16
+ { 458, 5, 1, 4, "VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #458 = VHSUBuv4i32
+ { 459, 5, 1, 4, "VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #459 = VHSUBuv8i16
+ { 460, 5, 1, 3, "VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #460 = VHSUBuv8i8
+ { 461, 7, 1, 11, "VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #461 = VLD1d16
+ { 462, 7, 1, 11, "VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #462 = VLD1d32
+ { 463, 7, 1, 11, "VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #463 = VLD1d64
+ { 464, 7, 1, 11, "VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #464 = VLD1d8
+ { 465, 7, 1, 11, "VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #465 = VLD1df
+ { 466, 7, 1, 11, "VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #466 = VLD1q16
+ { 467, 7, 1, 11, "VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #467 = VLD1q32
+ { 468, 7, 1, 11, "VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #468 = VLD1q64
+ { 469, 7, 1, 11, "VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #469 = VLD1q8
+ { 470, 7, 1, 11, "VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #470 = VLD1qf
+ { 471, 11, 2, 12, "VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #471 = VLD2LNd16
+ { 472, 11, 2, 12, "VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #472 = VLD2LNd32
+ { 473, 11, 2, 12, "VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #473 = VLD2LNd8
+ { 474, 11, 2, 12, "VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #474 = VLD2LNq16a
+ { 475, 11, 2, 12, "VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #475 = VLD2LNq16b
+ { 476, 11, 2, 12, "VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #476 = VLD2LNq32a
+ { 477, 11, 2, 12, "VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #477 = VLD2LNq32b
+ { 478, 8, 2, 12, "VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #478 = VLD2d16
+ { 479, 8, 2, 12, "VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #479 = VLD2d32
+ { 480, 8, 2, 11, "VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #480 = VLD2d64
+ { 481, 8, 2, 12, "VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #481 = VLD2d8
+ { 482, 10, 4, 12, "VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #482 = VLD2q16
+ { 483, 10, 4, 12, "VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #483 = VLD2q32
+ { 484, 10, 4, 12, "VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #484 = VLD2q8
+ { 485, 13, 3, 13, "VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #485 = VLD3LNd16
+ { 486, 13, 3, 13, "VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #486 = VLD3LNd32
+ { 487, 13, 3, 13, "VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #487 = VLD3LNd8
+ { 488, 13, 3, 13, "VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #488 = VLD3LNq16a
+ { 489, 13, 3, 13, "VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #489 = VLD3LNq16b
+ { 490, 13, 3, 13, "VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #490 = VLD3LNq32a
+ { 491, 13, 3, 13, "VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #491 = VLD3LNq32b
+ { 492, 9, 3, 13, "VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #492 = VLD3d16
+ { 493, 9, 3, 13, "VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #493 = VLD3d32
+ { 494, 9, 3, 11, "VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #494 = VLD3d64
+ { 495, 9, 3, 13, "VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #495 = VLD3d8
+ { 496, 10, 4, 13, "VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #496 = VLD3q16a
+ { 497, 10, 4, 13, "VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #497 = VLD3q16b
+ { 498, 10, 4, 13, "VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #498 = VLD3q32a
+ { 499, 10, 4, 13, "VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #499 = VLD3q32b
+ { 500, 10, 4, 13, "VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #500 = VLD3q8a
+ { 501, 10, 4, 13, "VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #501 = VLD3q8b
+ { 502, 15, 4, 14, "VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #502 = VLD4LNd16
+ { 503, 15, 4, 14, "VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #503 = VLD4LNd32
+ { 504, 15, 4, 14, "VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #504 = VLD4LNd8
+ { 505, 15, 4, 14, "VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #505 = VLD4LNq16a
+ { 506, 15, 4, 14, "VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #506 = VLD4LNq16b
+ { 507, 15, 4, 14, "VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #507 = VLD4LNq32a
+ { 508, 15, 4, 14, "VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #508 = VLD4LNq32b
+ { 509, 10, 4, 14, "VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #509 = VLD4d16
+ { 510, 10, 4, 14, "VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #510 = VLD4d32
+ { 511, 10, 4, 11, "VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #511 = VLD4d64
+ { 512, 10, 4, 14, "VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #512 = VLD4d8
+ { 513, 11, 5, 14, "VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #513 = VLD4q16a
+ { 514, 11, 5, 14, "VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #514 = VLD4q16b
+ { 515, 11, 5, 14, "VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #515 = VLD4q32a
+ { 516, 11, 5, 14, "VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #516 = VLD4q32b
+ { 517, 11, 5, 14, "VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #517 = VLD4q8a
+ { 518, 11, 5, 14, "VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #518 = VLD4q8b
{ 519, 5, 0, 75, "VLDMD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #519 = VLDMD
{ 520, 5, 0, 75, "VLDMS", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #520 = VLDMS
- { 521, 5, 1, 74, "VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #521 = VLDRD
- { 522, 5, 1, 75, "VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #522 = VLDRQ
- { 523, 5, 1, 73, "VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #523 = VLDRS
- { 524, 5, 1, 1, "VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #524 = VMAXfd
- { 525, 5, 1, 2, "VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #525 = VMAXfq
- { 526, 5, 1, 4, "VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #526 = VMAXsv16i8
- { 527, 5, 1, 3, "VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #527 = VMAXsv2i32
- { 528, 5, 1, 3, "VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #528 = VMAXsv4i16
- { 529, 5, 1, 4, "VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #529 = VMAXsv4i32
- { 530, 5, 1, 4, "VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #530 = VMAXsv8i16
- { 531, 5, 1, 3, "VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #531 = VMAXsv8i8
- { 532, 5, 1, 4, "VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #532 = VMAXuv16i8
- { 533, 5, 1, 3, "VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #533 = VMAXuv2i32
- { 534, 5, 1, 3, "VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #534 = VMAXuv4i16
- { 535, 5, 1, 4, "VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #535 = VMAXuv4i32
- { 536, 5, 1, 4, "VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #536 = VMAXuv8i16
- { 537, 5, 1, 3, "VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #537 = VMAXuv8i8
- { 538, 5, 1, 1, "VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #538 = VMINfd
- { 539, 5, 1, 2, "VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #539 = VMINfq
- { 540, 5, 1, 4, "VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #540 = VMINsv16i8
- { 541, 5, 1, 3, "VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #541 = VMINsv2i32
- { 542, 5, 1, 3, "VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #542 = VMINsv4i16
- { 543, 5, 1, 4, "VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #543 = VMINsv4i32
- { 544, 5, 1, 4, "VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #544 = VMINsv8i16
- { 545, 5, 1, 3, "VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #545 = VMINsv8i8
- { 546, 5, 1, 4, "VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #546 = VMINuv16i8
- { 547, 5, 1, 3, "VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #547 = VMINuv2i32
- { 548, 5, 1, 3, "VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #548 = VMINuv4i16
- { 549, 5, 1, 4, "VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #549 = VMINuv4i32
- { 550, 5, 1, 4, "VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #550 = VMINuv8i16
- { 551, 5, 1, 3, "VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #551 = VMINuv8i8
- { 552, 6, 1, 77, "VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #552 = VMLAD
- { 553, 7, 1, 19, "VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #553 = VMLALslsv2i32
- { 554, 7, 1, 17, "VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #554 = VMLALslsv4i16
- { 555, 7, 1, 19, "VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #555 = VMLALsluv2i32
- { 556, 7, 1, 17, "VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #556 = VMLALsluv4i16
- { 557, 6, 1, 17, "VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #557 = VMLALsv2i64
- { 558, 6, 1, 17, "VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #558 = VMLALsv4i32
- { 559, 6, 1, 17, "VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #559 = VMLALsv8i16
- { 560, 6, 1, 17, "VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #560 = VMLALuv2i64
- { 561, 6, 1, 17, "VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #561 = VMLALuv4i32
- { 562, 6, 1, 17, "VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #562 = VMLALuv8i16
- { 563, 6, 1, 76, "VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #563 = VMLAS
- { 564, 6, 1, 15, "VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #564 = VMLAfd
- { 565, 6, 1, 16, "VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #565 = VMLAfq
- { 566, 7, 1, 15, "VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #566 = VMLAslfd
- { 567, 7, 1, 16, "VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #567 = VMLAslfq
- { 568, 7, 1, 19, "VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #568 = VMLAslv2i32
- { 569, 7, 1, 17, "VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #569 = VMLAslv4i16
- { 570, 7, 1, 20, "VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #570 = VMLAslv4i32
- { 571, 7, 1, 18, "VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #571 = VMLAslv8i16
- { 572, 6, 1, 18, "VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #572 = VMLAv16i8
- { 573, 6, 1, 19, "VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #573 = VMLAv2i32
- { 574, 6, 1, 17, "VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #574 = VMLAv4i16
- { 575, 6, 1, 20, "VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #575 = VMLAv4i32
- { 576, 6, 1, 18, "VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #576 = VMLAv8i16
- { 577, 6, 1, 17, "VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #577 = VMLAv8i8
- { 578, 6, 1, 77, "VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #578 = VMLSD
- { 579, 7, 1, 19, "VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #579 = VMLSLslsv2i32
- { 580, 7, 1, 17, "VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #580 = VMLSLslsv4i16
- { 581, 7, 1, 19, "VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #581 = VMLSLsluv2i32
- { 582, 7, 1, 17, "VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #582 = VMLSLsluv4i16
- { 583, 6, 1, 17, "VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #583 = VMLSLsv2i64
- { 584, 6, 1, 17, "VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #584 = VMLSLsv4i32
- { 585, 6, 1, 17, "VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #585 = VMLSLsv8i16
- { 586, 6, 1, 17, "VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #586 = VMLSLuv2i64
- { 587, 6, 1, 17, "VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #587 = VMLSLuv4i32
- { 588, 6, 1, 17, "VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #588 = VMLSLuv8i16
- { 589, 6, 1, 76, "VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #589 = VMLSS
- { 590, 6, 1, 15, "VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #590 = VMLSfd
- { 591, 6, 1, 16, "VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #591 = VMLSfq
- { 592, 7, 1, 15, "VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #592 = VMLSslfd
- { 593, 7, 1, 16, "VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #593 = VMLSslfq
- { 594, 7, 1, 19, "VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #594 = VMLSslv2i32
- { 595, 7, 1, 17, "VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #595 = VMLSslv4i16
- { 596, 7, 1, 20, "VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #596 = VMLSslv4i32
- { 597, 7, 1, 18, "VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #597 = VMLSslv8i16
- { 598, 6, 1, 18, "VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #598 = VMLSv16i8
- { 599, 6, 1, 19, "VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #599 = VMLSv2i32
- { 600, 6, 1, 17, "VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #600 = VMLSv4i16
- { 601, 6, 1, 20, "VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #601 = VMLSv4i32
- { 602, 6, 1, 18, "VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #602 = VMLSv8i16
- { 603, 6, 1, 17, "VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #603 = VMLSv8i8
- { 604, 4, 1, 87, "VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #604 = VMOVD
- { 605, 5, 1, 23, "VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #605 = VMOVDRR
- { 606, 5, 1, 87, "VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #606 = VMOVDcc
- { 607, 4, 1, 21, "VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #607 = VMOVDneon
- { 608, 4, 1, 38, "VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #608 = VMOVLsv2i64
- { 609, 4, 1, 38, "VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #609 = VMOVLsv4i32
- { 610, 4, 1, 38, "VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #610 = VMOVLsv8i16
- { 611, 4, 1, 38, "VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #611 = VMOVLuv2i64
- { 612, 4, 1, 38, "VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #612 = VMOVLuv4i32
- { 613, 4, 1, 38, "VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #613 = VMOVLuv8i16
- { 614, 4, 1, 21, "VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #614 = VMOVNv2i32
- { 615, 4, 1, 21, "VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #615 = VMOVNv4i16
- { 616, 4, 1, 21, "VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #616 = VMOVNv8i8
- { 617, 4, 1, 21, "VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #617 = VMOVQ
- { 618, 5, 2, 22, "VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #618 = VMOVRRD
- { 619, 4, 1, 28, "VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #619 = VMOVRS
- { 620, 4, 1, 86, "VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #620 = VMOVS
- { 621, 4, 1, 24, "VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #621 = VMOVSR
- { 622, 5, 1, 86, "VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #622 = VMOVScc
- { 623, 4, 1, 26, "VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #623 = VMOVv16i8
+ { 521, 5, 1, 74, "VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #521 = VLDRD
+ { 522, 5, 1, 75, "VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #522 = VLDRQ
+ { 523, 5, 1, 73, "VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #523 = VLDRS
+ { 524, 5, 1, 1, "VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #524 = VMAXfd
+ { 525, 5, 1, 2, "VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #525 = VMAXfq
+ { 526, 5, 1, 4, "VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #526 = VMAXsv16i8
+ { 527, 5, 1, 3, "VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #527 = VMAXsv2i32
+ { 528, 5, 1, 3, "VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #528 = VMAXsv4i16
+ { 529, 5, 1, 4, "VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #529 = VMAXsv4i32
+ { 530, 5, 1, 4, "VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #530 = VMAXsv8i16
+ { 531, 5, 1, 3, "VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #531 = VMAXsv8i8
+ { 532, 5, 1, 4, "VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #532 = VMAXuv16i8
+ { 533, 5, 1, 3, "VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #533 = VMAXuv2i32
+ { 534, 5, 1, 3, "VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #534 = VMAXuv4i16
+ { 535, 5, 1, 4, "VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #535 = VMAXuv4i32
+ { 536, 5, 1, 4, "VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #536 = VMAXuv8i16
+ { 537, 5, 1, 3, "VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #537 = VMAXuv8i8
+ { 538, 5, 1, 1, "VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #538 = VMINfd
+ { 539, 5, 1, 2, "VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #539 = VMINfq
+ { 540, 5, 1, 4, "VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #540 = VMINsv16i8
+ { 541, 5, 1, 3, "VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #541 = VMINsv2i32
+ { 542, 5, 1, 3, "VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #542 = VMINsv4i16
+ { 543, 5, 1, 4, "VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #543 = VMINsv4i32
+ { 544, 5, 1, 4, "VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #544 = VMINsv8i16
+ { 545, 5, 1, 3, "VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #545 = VMINsv8i8
+ { 546, 5, 1, 4, "VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #546 = VMINuv16i8
+ { 547, 5, 1, 3, "VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #547 = VMINuv2i32
+ { 548, 5, 1, 3, "VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #548 = VMINuv4i16
+ { 549, 5, 1, 4, "VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #549 = VMINuv4i32
+ { 550, 5, 1, 4, "VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #550 = VMINuv8i16
+ { 551, 5, 1, 3, "VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #551 = VMINuv8i8
+ { 552, 6, 1, 77, "VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #552 = VMLAD
+ { 553, 7, 1, 19, "VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #553 = VMLALslsv2i32
+ { 554, 7, 1, 17, "VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #554 = VMLALslsv4i16
+ { 555, 7, 1, 19, "VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #555 = VMLALsluv2i32
+ { 556, 7, 1, 17, "VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #556 = VMLALsluv4i16
+ { 557, 6, 1, 17, "VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #557 = VMLALsv2i64
+ { 558, 6, 1, 17, "VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #558 = VMLALsv4i32
+ { 559, 6, 1, 17, "VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #559 = VMLALsv8i16
+ { 560, 6, 1, 17, "VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #560 = VMLALuv2i64
+ { 561, 6, 1, 17, "VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #561 = VMLALuv4i32
+ { 562, 6, 1, 17, "VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #562 = VMLALuv8i16
+ { 563, 6, 1, 76, "VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #563 = VMLAS
+ { 564, 6, 1, 15, "VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #564 = VMLAfd
+ { 565, 6, 1, 16, "VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #565 = VMLAfq
+ { 566, 7, 1, 15, "VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #566 = VMLAslfd
+ { 567, 7, 1, 16, "VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #567 = VMLAslfq
+ { 568, 7, 1, 19, "VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #568 = VMLAslv2i32
+ { 569, 7, 1, 17, "VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #569 = VMLAslv4i16
+ { 570, 7, 1, 20, "VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #570 = VMLAslv4i32
+ { 571, 7, 1, 18, "VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #571 = VMLAslv8i16
+ { 572, 6, 1, 18, "VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #572 = VMLAv16i8
+ { 573, 6, 1, 19, "VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #573 = VMLAv2i32
+ { 574, 6, 1, 17, "VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #574 = VMLAv4i16
+ { 575, 6, 1, 20, "VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #575 = VMLAv4i32
+ { 576, 6, 1, 18, "VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #576 = VMLAv8i16
+ { 577, 6, 1, 17, "VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #577 = VMLAv8i8
+ { 578, 6, 1, 77, "VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #578 = VMLSD
+ { 579, 7, 1, 19, "VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #579 = VMLSLslsv2i32
+ { 580, 7, 1, 17, "VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #580 = VMLSLslsv4i16
+ { 581, 7, 1, 19, "VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #581 = VMLSLsluv2i32
+ { 582, 7, 1, 17, "VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #582 = VMLSLsluv4i16
+ { 583, 6, 1, 17, "VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #583 = VMLSLsv2i64
+ { 584, 6, 1, 17, "VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #584 = VMLSLsv4i32
+ { 585, 6, 1, 17, "VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #585 = VMLSLsv8i16
+ { 586, 6, 1, 17, "VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #586 = VMLSLuv2i64
+ { 587, 6, 1, 17, "VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #587 = VMLSLuv4i32
+ { 588, 6, 1, 17, "VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #588 = VMLSLuv8i16
+ { 589, 6, 1, 76, "VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #589 = VMLSS
+ { 590, 6, 1, 15, "VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #590 = VMLSfd
+ { 591, 6, 1, 16, "VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #591 = VMLSfq
+ { 592, 7, 1, 15, "VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #592 = VMLSslfd
+ { 593, 7, 1, 16, "VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #593 = VMLSslfq
+ { 594, 7, 1, 19, "VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #594 = VMLSslv2i32
+ { 595, 7, 1, 17, "VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #595 = VMLSslv4i16
+ { 596, 7, 1, 20, "VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #596 = VMLSslv4i32
+ { 597, 7, 1, 18, "VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #597 = VMLSslv8i16
+ { 598, 6, 1, 18, "VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #598 = VMLSv16i8
+ { 599, 6, 1, 19, "VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #599 = VMLSv2i32
+ { 600, 6, 1, 17, "VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #600 = VMLSv4i16
+ { 601, 6, 1, 20, "VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #601 = VMLSv4i32
+ { 602, 6, 1, 18, "VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #602 = VMLSv8i16
+ { 603, 6, 1, 17, "VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #603 = VMLSv8i8
+ { 604, 4, 1, 87, "VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #604 = VMOVD
+ { 605, 5, 1, 23, "VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #605 = VMOVDRR
+ { 606, 5, 1, 87, "VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #606 = VMOVDcc
+ { 607, 4, 1, 21, "VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #607 = VMOVDneon
+ { 608, 4, 1, 38, "VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #608 = VMOVLsv2i64
+ { 609, 4, 1, 38, "VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #609 = VMOVLsv4i32
+ { 610, 4, 1, 38, "VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #610 = VMOVLsv8i16
+ { 611, 4, 1, 38, "VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #611 = VMOVLuv2i64
+ { 612, 4, 1, 38, "VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #612 = VMOVLuv4i32
+ { 613, 4, 1, 38, "VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #613 = VMOVLuv8i16
+ { 614, 4, 1, 21, "VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #614 = VMOVNv2i32
+ { 615, 4, 1, 21, "VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #615 = VMOVNv4i16
+ { 616, 4, 1, 21, "VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #616 = VMOVNv8i8
+ { 617, 4, 1, 21, "VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #617 = VMOVQ
+ { 618, 5, 2, 22, "VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #618 = VMOVRRD
+ { 619, 4, 1, 28, "VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #619 = VMOVRS
+ { 620, 4, 1, 86, "VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #620 = VMOVS
+ { 621, 4, 1, 24, "VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #621 = VMOVSR
+ { 622, 5, 1, 86, "VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #622 = VMOVScc
+ { 623, 4, 1, 26, "VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #623 = VMOVv16i8
{ 624, 4, 1, 26, "VMOVv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #624 = VMOVv1i64
{ 625, 4, 1, 26, "VMOVv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #625 = VMOVv2i32
- { 626, 4, 1, 26, "VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #626 = VMOVv2i64
+ { 626, 4, 1, 26, "VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #626 = VMOVv2i64
{ 627, 4, 1, 26, "VMOVv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #627 = VMOVv4i16
- { 628, 4, 1, 26, "VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #628 = VMOVv4i32
- { 629, 4, 1, 26, "VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #629 = VMOVv8i16
+ { 628, 4, 1, 26, "VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #628 = VMOVv4i32
+ { 629, 4, 1, 26, "VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #629 = VMOVv8i16
{ 630, 4, 1, 26, "VMOVv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #630 = VMOVv8i8
- { 631, 5, 1, 79, "VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #631 = VMULD
- { 632, 5, 1, 29, "VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #632 = VMULLp
- { 633, 6, 1, 29, "VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #633 = VMULLslsv2i32
- { 634, 6, 1, 29, "VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #634 = VMULLslsv4i16
- { 635, 6, 1, 29, "VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #635 = VMULLsluv2i32
- { 636, 6, 1, 29, "VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #636 = VMULLsluv4i16
- { 637, 5, 1, 29, "VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #637 = VMULLsv2i64
- { 638, 5, 1, 29, "VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #638 = VMULLsv4i32
- { 639, 5, 1, 29, "VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #639 = VMULLsv8i16
- { 640, 5, 1, 29, "VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #640 = VMULLuv2i64
- { 641, 5, 1, 29, "VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #641 = VMULLuv4i32
- { 642, 5, 1, 29, "VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #642 = VMULLuv8i16
- { 643, 5, 1, 78, "VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #643 = VMULS
- { 644, 5, 1, 1, "VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #644 = VMULfd
- { 645, 5, 1, 1, "VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #645 = VMULfd_sfp
- { 646, 5, 1, 2, "VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #646 = VMULfq
- { 647, 5, 1, 29, "VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #647 = VMULpd
- { 648, 5, 1, 30, "VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #648 = VMULpq
- { 649, 6, 1, 1, "VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #649 = VMULslfd
- { 650, 6, 1, 2, "VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #650 = VMULslfq
- { 651, 6, 1, 31, "VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #651 = VMULslv2i32
- { 652, 6, 1, 29, "VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #652 = VMULslv4i16
- { 653, 6, 1, 32, "VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #653 = VMULslv4i32
- { 654, 6, 1, 30, "VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #654 = VMULslv8i16
- { 655, 5, 1, 30, "VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #655 = VMULv16i8
- { 656, 5, 1, 31, "VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #656 = VMULv2i32
- { 657, 5, 1, 29, "VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #657 = VMULv4i16
- { 658, 5, 1, 32, "VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #658 = VMULv4i32
- { 659, 5, 1, 30, "VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #659 = VMULv8i16
- { 660, 5, 1, 29, "VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #660 = VMULv8i8
- { 661, 4, 1, 44, "VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #661 = VMVNd
- { 662, 4, 1, 44, "VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #662 = VMVNq
- { 663, 4, 1, 87, "VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #663 = VNEGD
- { 664, 5, 1, 87, "VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #664 = VNEGDcc
- { 665, 4, 1, 86, "VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #665 = VNEGS
- { 666, 5, 1, 86, "VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #666 = VNEGScc
- { 667, 4, 1, 57, "VNEGf32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #667 = VNEGf32d
- { 668, 4, 1, 57, "VNEGf32d_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #668 = VNEGf32d_sfp
- { 669, 4, 1, 58, "VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #669 = VNEGf32q
- { 670, 4, 1, 44, "VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #670 = VNEGs16d
- { 671, 4, 1, 44, "VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #671 = VNEGs16q
- { 672, 4, 1, 44, "VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #672 = VNEGs32d
- { 673, 4, 1, 44, "VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #673 = VNEGs32q
- { 674, 4, 1, 44, "VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #674 = VNEGs8d
- { 675, 4, 1, 44, "VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #675 = VNEGs8q
- { 676, 6, 1, 77, "VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #676 = VNMLAD
- { 677, 6, 1, 76, "VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #677 = VNMLAS
- { 678, 6, 1, 77, "VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #678 = VNMLSD
- { 679, 6, 1, 76, "VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #679 = VNMLSS
- { 680, 5, 1, 79, "VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #680 = VNMULD
- { 681, 5, 1, 78, "VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #681 = VNMULS
- { 682, 5, 1, 5, "VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #682 = VORNd
- { 683, 5, 1, 6, "VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #683 = VORNq
- { 684, 5, 1, 5, "VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #684 = VORRd
- { 685, 5, 1, 6, "VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #685 = VORRq
- { 686, 5, 1, 34, "VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #686 = VPADALsv16i8
- { 687, 5, 1, 33, "VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #687 = VPADALsv2i32
- { 688, 5, 1, 33, "VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #688 = VPADALsv4i16
- { 689, 5, 1, 34, "VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #689 = VPADALsv4i32
- { 690, 5, 1, 34, "VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #690 = VPADALsv8i16
- { 691, 5, 1, 33, "VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #691 = VPADALsv8i8
- { 692, 5, 1, 34, "VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #692 = VPADALuv16i8
- { 693, 5, 1, 33, "VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #693 = VPADALuv2i32
- { 694, 5, 1, 33, "VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #694 = VPADALuv4i16
- { 695, 5, 1, 34, "VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #695 = VPADALuv4i32
- { 696, 5, 1, 34, "VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #696 = VPADALuv8i16
- { 697, 5, 1, 33, "VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #697 = VPADALuv8i8
- { 698, 4, 1, 44, "VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #698 = VPADDLsv16i8
- { 699, 4, 1, 44, "VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #699 = VPADDLsv2i32
- { 700, 4, 1, 44, "VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #700 = VPADDLsv4i16
- { 701, 4, 1, 44, "VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #701 = VPADDLsv4i32
- { 702, 4, 1, 44, "VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #702 = VPADDLsv8i16
- { 703, 4, 1, 44, "VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #703 = VPADDLsv8i8
- { 704, 4, 1, 44, "VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #704 = VPADDLuv16i8
- { 705, 4, 1, 44, "VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #705 = VPADDLuv2i32
- { 706, 4, 1, 44, "VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #706 = VPADDLuv4i16
- { 707, 4, 1, 44, "VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #707 = VPADDLuv4i32
- { 708, 4, 1, 44, "VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #708 = VPADDLuv8i16
- { 709, 4, 1, 44, "VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #709 = VPADDLuv8i8
- { 710, 5, 1, 1, "VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #710 = VPADDf
- { 711, 5, 1, 5, "VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #711 = VPADDi16
- { 712, 5, 1, 5, "VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #712 = VPADDi32
- { 713, 5, 1, 5, "VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #713 = VPADDi8
- { 714, 5, 1, 3, "VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #714 = VPMAXf
- { 715, 5, 1, 3, "VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #715 = VPMAXs16
- { 716, 5, 1, 3, "VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #716 = VPMAXs32
- { 717, 5, 1, 3, "VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #717 = VPMAXs8
- { 718, 5, 1, 3, "VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #718 = VPMAXu16
- { 719, 5, 1, 3, "VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #719 = VPMAXu32
- { 720, 5, 1, 3, "VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #720 = VPMAXu8
- { 721, 5, 1, 3, "VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #721 = VPMINf
- { 722, 5, 1, 3, "VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #722 = VPMINs16
- { 723, 5, 1, 3, "VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #723 = VPMINs32
- { 724, 5, 1, 3, "VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #724 = VPMINs8
- { 725, 5, 1, 3, "VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #725 = VPMINu16
- { 726, 5, 1, 3, "VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #726 = VPMINu32
- { 727, 5, 1, 3, "VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #727 = VPMINu8
- { 728, 4, 1, 39, "VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #728 = VQABSv16i8
- { 729, 4, 1, 38, "VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #729 = VQABSv2i32
- { 730, 4, 1, 38, "VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #730 = VQABSv4i16
- { 731, 4, 1, 39, "VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #731 = VQABSv4i32
- { 732, 4, 1, 39, "VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #732 = VQABSv8i16
- { 733, 4, 1, 38, "VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #733 = VQABSv8i8
- { 734, 5, 1, 4, "VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #734 = VQADDsv16i8
- { 735, 5, 1, 3, "VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #735 = VQADDsv1i64
- { 736, 5, 1, 3, "VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #736 = VQADDsv2i32
- { 737, 5, 1, 4, "VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #737 = VQADDsv2i64
- { 738, 5, 1, 3, "VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #738 = VQADDsv4i16
- { 739, 5, 1, 4, "VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #739 = VQADDsv4i32
- { 740, 5, 1, 4, "VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #740 = VQADDsv8i16
- { 741, 5, 1, 3, "VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #741 = VQADDsv8i8
- { 742, 5, 1, 4, "VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #742 = VQADDuv16i8
- { 743, 5, 1, 3, "VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #743 = VQADDuv1i64
- { 744, 5, 1, 3, "VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #744 = VQADDuv2i32
- { 745, 5, 1, 4, "VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #745 = VQADDuv2i64
- { 746, 5, 1, 3, "VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #746 = VQADDuv4i16
- { 747, 5, 1, 4, "VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #747 = VQADDuv4i32
- { 748, 5, 1, 4, "VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #748 = VQADDuv8i16
- { 749, 5, 1, 3, "VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #749 = VQADDuv8i8
- { 750, 7, 1, 19, "VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #750 = VQDMLALslv2i32
- { 751, 7, 1, 17, "VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #751 = VQDMLALslv4i16
- { 752, 6, 1, 17, "VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #752 = VQDMLALv2i64
- { 753, 6, 1, 17, "VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #753 = VQDMLALv4i32
- { 754, 7, 1, 19, "VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #754 = VQDMLSLslv2i32
- { 755, 7, 1, 17, "VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #755 = VQDMLSLslv4i16
- { 756, 6, 1, 17, "VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #756 = VQDMLSLv2i64
- { 757, 6, 1, 17, "VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #757 = VQDMLSLv4i32
- { 758, 6, 1, 31, "VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #758 = VQDMULHslv2i32
- { 759, 6, 1, 29, "VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #759 = VQDMULHslv4i16
- { 760, 6, 1, 32, "VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #760 = VQDMULHslv4i32
- { 761, 6, 1, 30, "VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #761 = VQDMULHslv8i16
- { 762, 5, 1, 31, "VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #762 = VQDMULHv2i32
- { 763, 5, 1, 29, "VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #763 = VQDMULHv4i16
- { 764, 5, 1, 32, "VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #764 = VQDMULHv4i32
- { 765, 5, 1, 30, "VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #765 = VQDMULHv8i16
- { 766, 6, 1, 29, "VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #766 = VQDMULLslv2i32
- { 767, 6, 1, 29, "VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #767 = VQDMULLslv4i16
- { 768, 5, 1, 29, "VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #768 = VQDMULLv2i64
- { 769, 5, 1, 29, "VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #769 = VQDMULLv4i32
- { 770, 4, 1, 38, "VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #770 = VQMOVNsuv2i32
- { 771, 4, 1, 38, "VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #771 = VQMOVNsuv4i16
- { 772, 4, 1, 38, "VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #772 = VQMOVNsuv8i8
- { 773, 4, 1, 38, "VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #773 = VQMOVNsv2i32
- { 774, 4, 1, 38, "VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #774 = VQMOVNsv4i16
- { 775, 4, 1, 38, "VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #775 = VQMOVNsv8i8
- { 776, 4, 1, 38, "VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #776 = VQMOVNuv2i32
- { 777, 4, 1, 38, "VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #777 = VQMOVNuv4i16
- { 778, 4, 1, 38, "VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #778 = VQMOVNuv8i8
- { 779, 4, 1, 39, "VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #779 = VQNEGv16i8
- { 780, 4, 1, 38, "VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #780 = VQNEGv2i32
- { 781, 4, 1, 38, "VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #781 = VQNEGv4i16
- { 782, 4, 1, 39, "VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #782 = VQNEGv4i32
- { 783, 4, 1, 39, "VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #783 = VQNEGv8i16
- { 784, 4, 1, 38, "VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #784 = VQNEGv8i8
- { 785, 6, 1, 31, "VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #785 = VQRDMULHslv2i32
- { 786, 6, 1, 29, "VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #786 = VQRDMULHslv4i16
- { 787, 6, 1, 32, "VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #787 = VQRDMULHslv4i32
- { 788, 6, 1, 30, "VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #788 = VQRDMULHslv8i16
- { 789, 5, 1, 31, "VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #789 = VQRDMULHv2i32
- { 790, 5, 1, 29, "VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #790 = VQRDMULHv4i16
- { 791, 5, 1, 32, "VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #791 = VQRDMULHv4i32
- { 792, 5, 1, 30, "VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #792 = VQRDMULHv8i16
- { 793, 5, 1, 43, "VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #793 = VQRSHLsv16i8
- { 794, 5, 1, 42, "VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #794 = VQRSHLsv1i64
- { 795, 5, 1, 42, "VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #795 = VQRSHLsv2i32
- { 796, 5, 1, 43, "VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #796 = VQRSHLsv2i64
- { 797, 5, 1, 42, "VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #797 = VQRSHLsv4i16
- { 798, 5, 1, 43, "VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #798 = VQRSHLsv4i32
- { 799, 5, 1, 43, "VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #799 = VQRSHLsv8i16
- { 800, 5, 1, 42, "VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #800 = VQRSHLsv8i8
- { 801, 5, 1, 43, "VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #801 = VQRSHLuv16i8
- { 802, 5, 1, 42, "VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #802 = VQRSHLuv1i64
- { 803, 5, 1, 42, "VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #803 = VQRSHLuv2i32
- { 804, 5, 1, 43, "VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #804 = VQRSHLuv2i64
- { 805, 5, 1, 42, "VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #805 = VQRSHLuv4i16
- { 806, 5, 1, 43, "VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #806 = VQRSHLuv4i32
- { 807, 5, 1, 43, "VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #807 = VQRSHLuv8i16
- { 808, 5, 1, 42, "VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #808 = VQRSHLuv8i8
- { 809, 5, 1, 42, "VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #809 = VQRSHRNsv2i32
- { 810, 5, 1, 42, "VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #810 = VQRSHRNsv4i16
- { 811, 5, 1, 42, "VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #811 = VQRSHRNsv8i8
- { 812, 5, 1, 42, "VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #812 = VQRSHRNuv2i32
- { 813, 5, 1, 42, "VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #813 = VQRSHRNuv4i16
- { 814, 5, 1, 42, "VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #814 = VQRSHRNuv8i8
- { 815, 5, 1, 42, "VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #815 = VQRSHRUNv2i32
- { 816, 5, 1, 42, "VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #816 = VQRSHRUNv4i16
- { 817, 5, 1, 42, "VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #817 = VQRSHRUNv8i8
- { 818, 5, 1, 42, "VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #818 = VQSHLsiv16i8
- { 819, 5, 1, 42, "VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #819 = VQSHLsiv1i64
- { 820, 5, 1, 42, "VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #820 = VQSHLsiv2i32
- { 821, 5, 1, 42, "VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #821 = VQSHLsiv2i64
- { 822, 5, 1, 42, "VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #822 = VQSHLsiv4i16
- { 823, 5, 1, 42, "VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #823 = VQSHLsiv4i32
- { 824, 5, 1, 42, "VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #824 = VQSHLsiv8i16
- { 825, 5, 1, 42, "VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #825 = VQSHLsiv8i8
- { 826, 5, 1, 42, "VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #826 = VQSHLsuv16i8
- { 827, 5, 1, 42, "VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #827 = VQSHLsuv1i64
- { 828, 5, 1, 42, "VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #828 = VQSHLsuv2i32
- { 829, 5, 1, 42, "VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #829 = VQSHLsuv2i64
- { 830, 5, 1, 42, "VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #830 = VQSHLsuv4i16
- { 831, 5, 1, 42, "VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #831 = VQSHLsuv4i32
- { 832, 5, 1, 42, "VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #832 = VQSHLsuv8i16
- { 833, 5, 1, 42, "VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #833 = VQSHLsuv8i8
- { 834, 5, 1, 43, "VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #834 = VQSHLsv16i8
- { 835, 5, 1, 42, "VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #835 = VQSHLsv1i64
- { 836, 5, 1, 42, "VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #836 = VQSHLsv2i32
- { 837, 5, 1, 43, "VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #837 = VQSHLsv2i64
- { 838, 5, 1, 42, "VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #838 = VQSHLsv4i16
- { 839, 5, 1, 43, "VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #839 = VQSHLsv4i32
- { 840, 5, 1, 43, "VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #840 = VQSHLsv8i16
- { 841, 5, 1, 42, "VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #841 = VQSHLsv8i8
- { 842, 5, 1, 42, "VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #842 = VQSHLuiv16i8
- { 843, 5, 1, 42, "VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #843 = VQSHLuiv1i64
- { 844, 5, 1, 42, "VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #844 = VQSHLuiv2i32
- { 845, 5, 1, 42, "VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #845 = VQSHLuiv2i64
- { 846, 5, 1, 42, "VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #846 = VQSHLuiv4i16
- { 847, 5, 1, 42, "VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #847 = VQSHLuiv4i32
- { 848, 5, 1, 42, "VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #848 = VQSHLuiv8i16
- { 849, 5, 1, 42, "VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #849 = VQSHLuiv8i8
- { 850, 5, 1, 43, "VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #850 = VQSHLuv16i8
- { 851, 5, 1, 42, "VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #851 = VQSHLuv1i64
- { 852, 5, 1, 42, "VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #852 = VQSHLuv2i32
- { 853, 5, 1, 43, "VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #853 = VQSHLuv2i64
- { 854, 5, 1, 42, "VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #854 = VQSHLuv4i16
- { 855, 5, 1, 43, "VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #855 = VQSHLuv4i32
- { 856, 5, 1, 43, "VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #856 = VQSHLuv8i16
- { 857, 5, 1, 42, "VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #857 = VQSHLuv8i8
- { 858, 5, 1, 42, "VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #858 = VQSHRNsv2i32
- { 859, 5, 1, 42, "VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #859 = VQSHRNsv4i16
- { 860, 5, 1, 42, "VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #860 = VQSHRNsv8i8
- { 861, 5, 1, 42, "VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #861 = VQSHRNuv2i32
- { 862, 5, 1, 42, "VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #862 = VQSHRNuv4i16
- { 863, 5, 1, 42, "VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #863 = VQSHRNuv8i8
- { 864, 5, 1, 42, "VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #864 = VQSHRUNv2i32
- { 865, 5, 1, 42, "VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #865 = VQSHRUNv4i16
- { 866, 5, 1, 42, "VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #866 = VQSHRUNv8i8
- { 867, 5, 1, 4, "VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #867 = VQSUBsv16i8
- { 868, 5, 1, 3, "VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #868 = VQSUBsv1i64
- { 869, 5, 1, 3, "VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #869 = VQSUBsv2i32
- { 870, 5, 1, 4, "VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #870 = VQSUBsv2i64
- { 871, 5, 1, 3, "VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #871 = VQSUBsv4i16
- { 872, 5, 1, 4, "VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #872 = VQSUBsv4i32
- { 873, 5, 1, 4, "VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #873 = VQSUBsv8i16
- { 874, 5, 1, 3, "VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #874 = VQSUBsv8i8
- { 875, 5, 1, 4, "VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #875 = VQSUBuv16i8
- { 876, 5, 1, 3, "VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #876 = VQSUBuv1i64
- { 877, 5, 1, 3, "VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #877 = VQSUBuv2i32
- { 878, 5, 1, 4, "VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #878 = VQSUBuv2i64
- { 879, 5, 1, 3, "VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #879 = VQSUBuv4i16
- { 880, 5, 1, 4, "VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #880 = VQSUBuv4i32
- { 881, 5, 1, 4, "VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #881 = VQSUBuv8i16
- { 882, 5, 1, 3, "VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #882 = VQSUBuv8i8
- { 883, 5, 1, 3, "VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #883 = VRADDHNv2i32
- { 884, 5, 1, 3, "VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #884 = VRADDHNv4i16
- { 885, 5, 1, 3, "VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #885 = VRADDHNv8i8
- { 886, 4, 1, 57, "VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #886 = VRECPEd
- { 887, 4, 1, 57, "VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #887 = VRECPEfd
- { 888, 4, 1, 58, "VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #888 = VRECPEfq
- { 889, 4, 1, 58, "VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #889 = VRECPEq
- { 890, 5, 1, 40, "VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #890 = VRECPSfd
- { 891, 5, 1, 41, "VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #891 = VRECPSfq
- { 892, 4, 1, 21, "VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #892 = VREV16d8
- { 893, 4, 1, 21, "VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #893 = VREV16q8
- { 894, 4, 1, 21, "VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #894 = VREV32d16
- { 895, 4, 1, 21, "VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #895 = VREV32d8
- { 896, 4, 1, 21, "VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #896 = VREV32q16
- { 897, 4, 1, 21, "VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #897 = VREV32q8
- { 898, 4, 1, 21, "VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #898 = VREV64d16
- { 899, 4, 1, 21, "VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #899 = VREV64d32
- { 900, 4, 1, 21, "VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #900 = VREV64d8
- { 901, 4, 1, 21, "VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #901 = VREV64df
- { 902, 4, 1, 21, "VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #902 = VREV64q16
- { 903, 4, 1, 21, "VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #903 = VREV64q32
- { 904, 4, 1, 21, "VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #904 = VREV64q8
- { 905, 4, 1, 21, "VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #905 = VREV64qf
- { 906, 5, 1, 4, "VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #906 = VRHADDsv16i8
- { 907, 5, 1, 3, "VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #907 = VRHADDsv2i32
- { 908, 5, 1, 3, "VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #908 = VRHADDsv4i16
- { 909, 5, 1, 4, "VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #909 = VRHADDsv4i32
- { 910, 5, 1, 4, "VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #910 = VRHADDsv8i16
- { 911, 5, 1, 3, "VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #911 = VRHADDsv8i8
- { 912, 5, 1, 4, "VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #912 = VRHADDuv16i8
- { 913, 5, 1, 3, "VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #913 = VRHADDuv2i32
- { 914, 5, 1, 3, "VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #914 = VRHADDuv4i16
- { 915, 5, 1, 4, "VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #915 = VRHADDuv4i32
- { 916, 5, 1, 4, "VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #916 = VRHADDuv8i16
- { 917, 5, 1, 3, "VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #917 = VRHADDuv8i8
- { 918, 5, 1, 43, "VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #918 = VRSHLsv16i8
- { 919, 5, 1, 42, "VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #919 = VRSHLsv1i64
- { 920, 5, 1, 42, "VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #920 = VRSHLsv2i32
- { 921, 5, 1, 43, "VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #921 = VRSHLsv2i64
- { 922, 5, 1, 42, "VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #922 = VRSHLsv4i16
- { 923, 5, 1, 43, "VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #923 = VRSHLsv4i32
- { 924, 5, 1, 43, "VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #924 = VRSHLsv8i16
- { 925, 5, 1, 42, "VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #925 = VRSHLsv8i8
- { 926, 5, 1, 43, "VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #926 = VRSHLuv16i8
- { 927, 5, 1, 42, "VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #927 = VRSHLuv1i64
- { 928, 5, 1, 42, "VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #928 = VRSHLuv2i32
- { 929, 5, 1, 43, "VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #929 = VRSHLuv2i64
- { 930, 5, 1, 42, "VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #930 = VRSHLuv4i16
- { 931, 5, 1, 43, "VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #931 = VRSHLuv4i32
- { 932, 5, 1, 43, "VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #932 = VRSHLuv8i16
- { 933, 5, 1, 42, "VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #933 = VRSHLuv8i8
- { 934, 5, 1, 42, "VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #934 = VRSHRNv2i32
- { 935, 5, 1, 42, "VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #935 = VRSHRNv4i16
- { 936, 5, 1, 42, "VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #936 = VRSHRNv8i8
- { 937, 5, 1, 42, "VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #937 = VRSHRsv16i8
- { 938, 5, 1, 42, "VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #938 = VRSHRsv1i64
- { 939, 5, 1, 42, "VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #939 = VRSHRsv2i32
- { 940, 5, 1, 42, "VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #940 = VRSHRsv2i64
- { 941, 5, 1, 42, "VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #941 = VRSHRsv4i16
- { 942, 5, 1, 42, "VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #942 = VRSHRsv4i32
- { 943, 5, 1, 42, "VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #943 = VRSHRsv8i16
- { 944, 5, 1, 42, "VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #944 = VRSHRsv8i8
- { 945, 5, 1, 42, "VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #945 = VRSHRuv16i8
- { 946, 5, 1, 42, "VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #946 = VRSHRuv1i64
- { 947, 5, 1, 42, "VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #947 = VRSHRuv2i32
- { 948, 5, 1, 42, "VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #948 = VRSHRuv2i64
- { 949, 5, 1, 42, "VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #949 = VRSHRuv4i16
- { 950, 5, 1, 42, "VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #950 = VRSHRuv4i32
- { 951, 5, 1, 42, "VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #951 = VRSHRuv8i16
- { 952, 5, 1, 42, "VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #952 = VRSHRuv8i8
- { 953, 4, 1, 57, "VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #953 = VRSQRTEd
- { 954, 4, 1, 57, "VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #954 = VRSQRTEfd
- { 955, 4, 1, 58, "VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #955 = VRSQRTEfq
- { 956, 4, 1, 58, "VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #956 = VRSQRTEq
- { 957, 5, 1, 40, "VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #957 = VRSQRTSfd
- { 958, 5, 1, 41, "VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #958 = VRSQRTSfq
- { 959, 6, 1, 33, "VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #959 = VRSRAsv16i8
- { 960, 6, 1, 33, "VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #960 = VRSRAsv1i64
- { 961, 6, 1, 33, "VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #961 = VRSRAsv2i32
- { 962, 6, 1, 33, "VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #962 = VRSRAsv2i64
- { 963, 6, 1, 33, "VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #963 = VRSRAsv4i16
- { 964, 6, 1, 33, "VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #964 = VRSRAsv4i32
- { 965, 6, 1, 33, "VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #965 = VRSRAsv8i16
- { 966, 6, 1, 33, "VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #966 = VRSRAsv8i8
- { 967, 6, 1, 33, "VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #967 = VRSRAuv16i8
- { 968, 6, 1, 33, "VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #968 = VRSRAuv1i64
- { 969, 6, 1, 33, "VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #969 = VRSRAuv2i32
- { 970, 6, 1, 33, "VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #970 = VRSRAuv2i64
- { 971, 6, 1, 33, "VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #971 = VRSRAuv4i16
- { 972, 6, 1, 33, "VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #972 = VRSRAuv4i32
- { 973, 6, 1, 33, "VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #973 = VRSRAuv8i16
- { 974, 6, 1, 33, "VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #974 = VRSRAuv8i8
- { 975, 5, 1, 3, "VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #975 = VRSUBHNv2i32
- { 976, 5, 1, 3, "VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #976 = VRSUBHNv4i16
- { 977, 5, 1, 3, "VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #977 = VRSUBHNv8i8
- { 978, 6, 1, 25, "VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo107 }, // Inst #978 = VSETLNi16
- { 979, 6, 1, 25, "VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo107 }, // Inst #979 = VSETLNi32
- { 980, 6, 1, 25, "VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo107 }, // Inst #980 = VSETLNi8
- { 981, 5, 1, 44, "VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #981 = VSHLLi16
- { 982, 5, 1, 44, "VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #982 = VSHLLi32
- { 983, 5, 1, 44, "VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #983 = VSHLLi8
- { 984, 5, 1, 44, "VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #984 = VSHLLsv2i64
- { 985, 5, 1, 44, "VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #985 = VSHLLsv4i32
- { 986, 5, 1, 44, "VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #986 = VSHLLsv8i16
- { 987, 5, 1, 44, "VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #987 = VSHLLuv2i64
- { 988, 5, 1, 44, "VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #988 = VSHLLuv4i32
- { 989, 5, 1, 44, "VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #989 = VSHLLuv8i16
- { 990, 5, 1, 44, "VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #990 = VSHLiv16i8
- { 991, 5, 1, 44, "VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #991 = VSHLiv1i64
- { 992, 5, 1, 44, "VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #992 = VSHLiv2i32
- { 993, 5, 1, 44, "VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #993 = VSHLiv2i64
- { 994, 5, 1, 44, "VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #994 = VSHLiv4i16
- { 995, 5, 1, 44, "VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #995 = VSHLiv4i32
- { 996, 5, 1, 44, "VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #996 = VSHLiv8i16
- { 997, 5, 1, 44, "VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #997 = VSHLiv8i8
- { 998, 5, 1, 45, "VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #998 = VSHLsv16i8
- { 999, 5, 1, 44, "VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #999 = VSHLsv1i64
- { 1000, 5, 1, 44, "VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1000 = VSHLsv2i32
- { 1001, 5, 1, 45, "VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1001 = VSHLsv2i64
- { 1002, 5, 1, 44, "VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1002 = VSHLsv4i16
- { 1003, 5, 1, 45, "VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1003 = VSHLsv4i32
- { 1004, 5, 1, 45, "VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1004 = VSHLsv8i16
- { 1005, 5, 1, 44, "VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1005 = VSHLsv8i8
- { 1006, 5, 1, 45, "VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1006 = VSHLuv16i8
- { 1007, 5, 1, 44, "VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1007 = VSHLuv1i64
- { 1008, 5, 1, 44, "VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1008 = VSHLuv2i32
- { 1009, 5, 1, 45, "VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1009 = VSHLuv2i64
- { 1010, 5, 1, 44, "VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1010 = VSHLuv4i16
- { 1011, 5, 1, 45, "VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1011 = VSHLuv4i32
- { 1012, 5, 1, 45, "VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1012 = VSHLuv8i16
- { 1013, 5, 1, 44, "VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1013 = VSHLuv8i8
- { 1014, 5, 1, 44, "VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #1014 = VSHRNv2i32
- { 1015, 5, 1, 44, "VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #1015 = VSHRNv4i16
- { 1016, 5, 1, 44, "VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #1016 = VSHRNv8i8
- { 1017, 5, 1, 44, "VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1017 = VSHRsv16i8
- { 1018, 5, 1, 44, "VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1018 = VSHRsv1i64
- { 1019, 5, 1, 44, "VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1019 = VSHRsv2i32
- { 1020, 5, 1, 44, "VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1020 = VSHRsv2i64
- { 1021, 5, 1, 44, "VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1021 = VSHRsv4i16
- { 1022, 5, 1, 44, "VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1022 = VSHRsv4i32
- { 1023, 5, 1, 44, "VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1023 = VSHRsv8i16
- { 1024, 5, 1, 44, "VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1024 = VSHRsv8i8
- { 1025, 5, 1, 44, "VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1025 = VSHRuv16i8
- { 1026, 5, 1, 44, "VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1026 = VSHRuv1i64
- { 1027, 5, 1, 44, "VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1027 = VSHRuv2i32
- { 1028, 5, 1, 44, "VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1028 = VSHRuv2i64
- { 1029, 5, 1, 44, "VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1029 = VSHRuv4i16
- { 1030, 5, 1, 44, "VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1030 = VSHRuv4i32
- { 1031, 5, 1, 44, "VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1031 = VSHRuv8i16
- { 1032, 5, 1, 44, "VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1032 = VSHRuv8i8
- { 1033, 4, 1, 67, "VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #1033 = VSITOD
- { 1034, 4, 1, 68, "VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1034 = VSITOS
- { 1035, 6, 1, 45, "VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1035 = VSLIv16i8
- { 1036, 6, 1, 44, "VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1036 = VSLIv1i64
- { 1037, 6, 1, 44, "VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1037 = VSLIv2i32
- { 1038, 6, 1, 45, "VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1038 = VSLIv2i64
- { 1039, 6, 1, 44, "VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1039 = VSLIv4i16
- { 1040, 6, 1, 45, "VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1040 = VSLIv4i32
- { 1041, 6, 1, 45, "VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1041 = VSLIv8i16
- { 1042, 6, 1, 44, "VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1042 = VSLIv8i8
- { 1043, 4, 1, 81, "VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1043 = VSQRTD
- { 1044, 4, 1, 80, "VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1044 = VSQRTS
- { 1045, 6, 1, 33, "VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1045 = VSRAsv16i8
- { 1046, 6, 1, 33, "VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1046 = VSRAsv1i64
- { 1047, 6, 1, 33, "VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1047 = VSRAsv2i32
- { 1048, 6, 1, 33, "VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1048 = VSRAsv2i64
- { 1049, 6, 1, 33, "VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1049 = VSRAsv4i16
- { 1050, 6, 1, 33, "VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1050 = VSRAsv4i32
- { 1051, 6, 1, 33, "VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1051 = VSRAsv8i16
- { 1052, 6, 1, 33, "VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1052 = VSRAsv8i8
- { 1053, 6, 1, 33, "VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1053 = VSRAuv16i8
- { 1054, 6, 1, 33, "VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1054 = VSRAuv1i64
- { 1055, 6, 1, 33, "VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1055 = VSRAuv2i32
- { 1056, 6, 1, 33, "VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1056 = VSRAuv2i64
- { 1057, 6, 1, 33, "VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1057 = VSRAuv4i16
- { 1058, 6, 1, 33, "VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1058 = VSRAuv4i32
- { 1059, 6, 1, 33, "VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1059 = VSRAuv8i16
- { 1060, 6, 1, 33, "VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1060 = VSRAuv8i8
- { 1061, 6, 1, 45, "VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1061 = VSRIv16i8
- { 1062, 6, 1, 44, "VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1062 = VSRIv1i64
- { 1063, 6, 1, 44, "VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1063 = VSRIv2i32
- { 1064, 6, 1, 45, "VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1064 = VSRIv2i64
- { 1065, 6, 1, 44, "VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1065 = VSRIv4i16
- { 1066, 6, 1, 45, "VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1066 = VSRIv4i32
- { 1067, 6, 1, 45, "VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1067 = VSRIv8i16
- { 1068, 6, 1, 44, "VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1068 = VSRIv8i8
- { 1069, 7, 0, 46, "VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1069 = VST1d16
- { 1070, 7, 0, 46, "VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1070 = VST1d32
- { 1071, 7, 0, 46, "VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1071 = VST1d64
- { 1072, 7, 0, 46, "VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1072 = VST1d8
- { 1073, 7, 0, 46, "VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1073 = VST1df
- { 1074, 7, 0, 46, "VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1074 = VST1q16
- { 1075, 7, 0, 46, "VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1075 = VST1q32
- { 1076, 7, 0, 46, "VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1076 = VST1q64
- { 1077, 7, 0, 46, "VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1077 = VST1q8
- { 1078, 7, 0, 46, "VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1078 = VST1qf
- { 1079, 9, 0, 46, "VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1079 = VST2LNd16
- { 1080, 9, 0, 46, "VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1080 = VST2LNd32
- { 1081, 9, 0, 46, "VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1081 = VST2LNd8
- { 1082, 9, 0, 46, "VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1082 = VST2LNq16a
- { 1083, 9, 0, 46, "VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1083 = VST2LNq16b
- { 1084, 9, 0, 46, "VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1084 = VST2LNq32a
- { 1085, 9, 0, 46, "VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1085 = VST2LNq32b
- { 1086, 8, 0, 46, "VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1086 = VST2d16
- { 1087, 8, 0, 46, "VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1087 = VST2d32
- { 1088, 8, 0, 46, "VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1088 = VST2d64
- { 1089, 8, 0, 46, "VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1089 = VST2d8
- { 1090, 10, 0, 46, "VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1090 = VST2q16
- { 1091, 10, 0, 46, "VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1091 = VST2q32
- { 1092, 10, 0, 46, "VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1092 = VST2q8
- { 1093, 10, 0, 46, "VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1093 = VST3LNd16
- { 1094, 10, 0, 46, "VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1094 = VST3LNd32
- { 1095, 10, 0, 46, "VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1095 = VST3LNd8
- { 1096, 10, 0, 46, "VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1096 = VST3LNq16a
- { 1097, 10, 0, 46, "VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1097 = VST3LNq16b
- { 1098, 10, 0, 46, "VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1098 = VST3LNq32a
- { 1099, 10, 0, 46, "VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1099 = VST3LNq32b
- { 1100, 9, 0, 46, "VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1100 = VST3d16
- { 1101, 9, 0, 46, "VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1101 = VST3d32
- { 1102, 9, 0, 46, "VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1102 = VST3d64
- { 1103, 9, 0, 46, "VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1103 = VST3d8
- { 1104, 10, 1, 46, "VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1104 = VST3q16a
- { 1105, 10, 1, 46, "VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1105 = VST3q16b
- { 1106, 10, 1, 46, "VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1106 = VST3q32a
- { 1107, 10, 1, 46, "VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1107 = VST3q32b
- { 1108, 10, 1, 46, "VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1108 = VST3q8a
- { 1109, 10, 1, 46, "VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1109 = VST3q8b
- { 1110, 11, 0, 46, "VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1110 = VST4LNd16
- { 1111, 11, 0, 46, "VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1111 = VST4LNd32
- { 1112, 11, 0, 46, "VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1112 = VST4LNd8
- { 1113, 11, 0, 46, "VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1113 = VST4LNq16a
- { 1114, 11, 0, 46, "VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1114 = VST4LNq16b
- { 1115, 11, 0, 46, "VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1115 = VST4LNq32a
- { 1116, 11, 0, 46, "VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1116 = VST4LNq32b
- { 1117, 10, 0, 46, "VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1117 = VST4d16
- { 1118, 10, 0, 46, "VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1118 = VST4d32
- { 1119, 10, 0, 46, "VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1119 = VST4d64
- { 1120, 10, 0, 46, "VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1120 = VST4d8
- { 1121, 11, 1, 46, "VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1121 = VST4q16a
- { 1122, 11, 1, 46, "VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1122 = VST4q16b
- { 1123, 11, 1, 46, "VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1123 = VST4q32a
- { 1124, 11, 1, 46, "VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1124 = VST4q32b
- { 1125, 11, 1, 46, "VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1125 = VST4q8a
- { 1126, 11, 1, 46, "VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1126 = VST4q8b
+ { 631, 5, 1, 79, "VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #631 = VMULD
+ { 632, 5, 1, 29, "VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #632 = VMULLp
+ { 633, 6, 1, 29, "VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #633 = VMULLslsv2i32
+ { 634, 6, 1, 29, "VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #634 = VMULLslsv4i16
+ { 635, 6, 1, 29, "VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #635 = VMULLsluv2i32
+ { 636, 6, 1, 29, "VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #636 = VMULLsluv4i16
+ { 637, 5, 1, 29, "VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #637 = VMULLsv2i64
+ { 638, 5, 1, 29, "VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #638 = VMULLsv4i32
+ { 639, 5, 1, 29, "VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #639 = VMULLsv8i16
+ { 640, 5, 1, 29, "VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #640 = VMULLuv2i64
+ { 641, 5, 1, 29, "VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #641 = VMULLuv4i32
+ { 642, 5, 1, 29, "VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #642 = VMULLuv8i16
+ { 643, 5, 1, 78, "VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #643 = VMULS
+ { 644, 5, 1, 1, "VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #644 = VMULfd
+ { 645, 5, 1, 1, "VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #645 = VMULfd_sfp
+ { 646, 5, 1, 2, "VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #646 = VMULfq
+ { 647, 5, 1, 29, "VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #647 = VMULpd
+ { 648, 5, 1, 30, "VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #648 = VMULpq
+ { 649, 6, 1, 1, "VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #649 = VMULslfd
+ { 650, 6, 1, 2, "VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #650 = VMULslfq
+ { 651, 6, 1, 31, "VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #651 = VMULslv2i32
+ { 652, 6, 1, 29, "VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #652 = VMULslv4i16
+ { 653, 6, 1, 32, "VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #653 = VMULslv4i32
+ { 654, 6, 1, 30, "VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #654 = VMULslv8i16
+ { 655, 5, 1, 30, "VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #655 = VMULv16i8
+ { 656, 5, 1, 31, "VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #656 = VMULv2i32
+ { 657, 5, 1, 29, "VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #657 = VMULv4i16
+ { 658, 5, 1, 32, "VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #658 = VMULv4i32
+ { 659, 5, 1, 30, "VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #659 = VMULv8i16
+ { 660, 5, 1, 29, "VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #660 = VMULv8i8
+ { 661, 4, 1, 44, "VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #661 = VMVNd
+ { 662, 4, 1, 44, "VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #662 = VMVNq
+ { 663, 4, 1, 87, "VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #663 = VNEGD
+ { 664, 5, 1, 87, "VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #664 = VNEGDcc
+ { 665, 4, 1, 86, "VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #665 = VNEGS
+ { 666, 5, 1, 86, "VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #666 = VNEGScc
+ { 667, 4, 1, 57, "VNEGf32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #667 = VNEGf32d
+ { 668, 4, 1, 57, "VNEGf32d_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #668 = VNEGf32d_sfp
+ { 669, 4, 1, 58, "VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #669 = VNEGf32q
+ { 670, 4, 1, 44, "VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #670 = VNEGs16d
+ { 671, 4, 1, 44, "VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #671 = VNEGs16q
+ { 672, 4, 1, 44, "VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #672 = VNEGs32d
+ { 673, 4, 1, 44, "VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #673 = VNEGs32q
+ { 674, 4, 1, 44, "VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #674 = VNEGs8d
+ { 675, 4, 1, 44, "VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #675 = VNEGs8q
+ { 676, 6, 1, 77, "VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #676 = VNMLAD
+ { 677, 6, 1, 76, "VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #677 = VNMLAS
+ { 678, 6, 1, 77, "VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #678 = VNMLSD
+ { 679, 6, 1, 76, "VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #679 = VNMLSS
+ { 680, 5, 1, 79, "VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #680 = VNMULD
+ { 681, 5, 1, 78, "VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #681 = VNMULS
+ { 682, 5, 1, 5, "VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #682 = VORNd
+ { 683, 5, 1, 6, "VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #683 = VORNq
+ { 684, 5, 1, 5, "VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #684 = VORRd
+ { 685, 5, 1, 6, "VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #685 = VORRq
+ { 686, 5, 1, 34, "VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #686 = VPADALsv16i8
+ { 687, 5, 1, 33, "VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #687 = VPADALsv2i32
+ { 688, 5, 1, 33, "VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #688 = VPADALsv4i16
+ { 689, 5, 1, 34, "VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #689 = VPADALsv4i32
+ { 690, 5, 1, 34, "VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #690 = VPADALsv8i16
+ { 691, 5, 1, 33, "VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #691 = VPADALsv8i8
+ { 692, 5, 1, 34, "VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #692 = VPADALuv16i8
+ { 693, 5, 1, 33, "VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #693 = VPADALuv2i32
+ { 694, 5, 1, 33, "VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #694 = VPADALuv4i16
+ { 695, 5, 1, 34, "VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #695 = VPADALuv4i32
+ { 696, 5, 1, 34, "VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #696 = VPADALuv8i16
+ { 697, 5, 1, 33, "VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #697 = VPADALuv8i8
+ { 698, 4, 1, 44, "VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #698 = VPADDLsv16i8
+ { 699, 4, 1, 44, "VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #699 = VPADDLsv2i32
+ { 700, 4, 1, 44, "VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #700 = VPADDLsv4i16
+ { 701, 4, 1, 44, "VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #701 = VPADDLsv4i32
+ { 702, 4, 1, 44, "VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #702 = VPADDLsv8i16
+ { 703, 4, 1, 44, "VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #703 = VPADDLsv8i8
+ { 704, 4, 1, 44, "VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #704 = VPADDLuv16i8
+ { 705, 4, 1, 44, "VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #705 = VPADDLuv2i32
+ { 706, 4, 1, 44, "VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #706 = VPADDLuv4i16
+ { 707, 4, 1, 44, "VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #707 = VPADDLuv4i32
+ { 708, 4, 1, 44, "VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #708 = VPADDLuv8i16
+ { 709, 4, 1, 44, "VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #709 = VPADDLuv8i8
+ { 710, 5, 1, 1, "VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #710 = VPADDf
+ { 711, 5, 1, 5, "VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #711 = VPADDi16
+ { 712, 5, 1, 5, "VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #712 = VPADDi32
+ { 713, 5, 1, 5, "VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #713 = VPADDi8
+ { 714, 5, 1, 3, "VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #714 = VPMAXf
+ { 715, 5, 1, 3, "VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #715 = VPMAXs16
+ { 716, 5, 1, 3, "VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #716 = VPMAXs32
+ { 717, 5, 1, 3, "VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #717 = VPMAXs8
+ { 718, 5, 1, 3, "VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #718 = VPMAXu16
+ { 719, 5, 1, 3, "VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #719 = VPMAXu32
+ { 720, 5, 1, 3, "VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #720 = VPMAXu8
+ { 721, 5, 1, 3, "VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #721 = VPMINf
+ { 722, 5, 1, 3, "VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #722 = VPMINs16
+ { 723, 5, 1, 3, "VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #723 = VPMINs32
+ { 724, 5, 1, 3, "VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #724 = VPMINs8
+ { 725, 5, 1, 3, "VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #725 = VPMINu16
+ { 726, 5, 1, 3, "VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #726 = VPMINu32
+ { 727, 5, 1, 3, "VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #727 = VPMINu8
+ { 728, 4, 1, 39, "VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #728 = VQABSv16i8
+ { 729, 4, 1, 38, "VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #729 = VQABSv2i32
+ { 730, 4, 1, 38, "VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #730 = VQABSv4i16
+ { 731, 4, 1, 39, "VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #731 = VQABSv4i32
+ { 732, 4, 1, 39, "VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #732 = VQABSv8i16
+ { 733, 4, 1, 38, "VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #733 = VQABSv8i8
+ { 734, 5, 1, 4, "VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #734 = VQADDsv16i8
+ { 735, 5, 1, 3, "VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #735 = VQADDsv1i64
+ { 736, 5, 1, 3, "VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #736 = VQADDsv2i32
+ { 737, 5, 1, 4, "VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #737 = VQADDsv2i64
+ { 738, 5, 1, 3, "VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #738 = VQADDsv4i16
+ { 739, 5, 1, 4, "VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #739 = VQADDsv4i32
+ { 740, 5, 1, 4, "VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #740 = VQADDsv8i16
+ { 741, 5, 1, 3, "VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #741 = VQADDsv8i8
+ { 742, 5, 1, 4, "VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #742 = VQADDuv16i8
+ { 743, 5, 1, 3, "VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #743 = VQADDuv1i64
+ { 744, 5, 1, 3, "VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #744 = VQADDuv2i32
+ { 745, 5, 1, 4, "VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #745 = VQADDuv2i64
+ { 746, 5, 1, 3, "VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #746 = VQADDuv4i16
+ { 747, 5, 1, 4, "VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #747 = VQADDuv4i32
+ { 748, 5, 1, 4, "VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #748 = VQADDuv8i16
+ { 749, 5, 1, 3, "VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #749 = VQADDuv8i8
+ { 750, 7, 1, 19, "VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #750 = VQDMLALslv2i32
+ { 751, 7, 1, 17, "VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #751 = VQDMLALslv4i16
+ { 752, 6, 1, 17, "VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #752 = VQDMLALv2i64
+ { 753, 6, 1, 17, "VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #753 = VQDMLALv4i32
+ { 754, 7, 1, 19, "VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #754 = VQDMLSLslv2i32
+ { 755, 7, 1, 17, "VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #755 = VQDMLSLslv4i16
+ { 756, 6, 1, 17, "VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #756 = VQDMLSLv2i64
+ { 757, 6, 1, 17, "VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #757 = VQDMLSLv4i32
+ { 758, 6, 1, 31, "VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #758 = VQDMULHslv2i32
+ { 759, 6, 1, 29, "VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #759 = VQDMULHslv4i16
+ { 760, 6, 1, 32, "VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #760 = VQDMULHslv4i32
+ { 761, 6, 1, 30, "VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #761 = VQDMULHslv8i16
+ { 762, 5, 1, 31, "VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #762 = VQDMULHv2i32
+ { 763, 5, 1, 29, "VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #763 = VQDMULHv4i16
+ { 764, 5, 1, 32, "VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #764 = VQDMULHv4i32
+ { 765, 5, 1, 30, "VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #765 = VQDMULHv8i16
+ { 766, 6, 1, 29, "VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #766 = VQDMULLslv2i32
+ { 767, 6, 1, 29, "VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #767 = VQDMULLslv4i16
+ { 768, 5, 1, 29, "VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #768 = VQDMULLv2i64
+ { 769, 5, 1, 29, "VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #769 = VQDMULLv4i32
+ { 770, 4, 1, 38, "VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #770 = VQMOVNsuv2i32
+ { 771, 4, 1, 38, "VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #771 = VQMOVNsuv4i16
+ { 772, 4, 1, 38, "VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #772 = VQMOVNsuv8i8
+ { 773, 4, 1, 38, "VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #773 = VQMOVNsv2i32
+ { 774, 4, 1, 38, "VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #774 = VQMOVNsv4i16
+ { 775, 4, 1, 38, "VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #775 = VQMOVNsv8i8
+ { 776, 4, 1, 38, "VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #776 = VQMOVNuv2i32
+ { 777, 4, 1, 38, "VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #777 = VQMOVNuv4i16
+ { 778, 4, 1, 38, "VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #778 = VQMOVNuv8i8
+ { 779, 4, 1, 39, "VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #779 = VQNEGv16i8
+ { 780, 4, 1, 38, "VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #780 = VQNEGv2i32
+ { 781, 4, 1, 38, "VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #781 = VQNEGv4i16
+ { 782, 4, 1, 39, "VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #782 = VQNEGv4i32
+ { 783, 4, 1, 39, "VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #783 = VQNEGv8i16
+ { 784, 4, 1, 38, "VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #784 = VQNEGv8i8
+ { 785, 6, 1, 31, "VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #785 = VQRDMULHslv2i32
+ { 786, 6, 1, 29, "VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #786 = VQRDMULHslv4i16
+ { 787, 6, 1, 32, "VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #787 = VQRDMULHslv4i32
+ { 788, 6, 1, 30, "VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #788 = VQRDMULHslv8i16
+ { 789, 5, 1, 31, "VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #789 = VQRDMULHv2i32
+ { 790, 5, 1, 29, "VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #790 = VQRDMULHv4i16
+ { 791, 5, 1, 32, "VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #791 = VQRDMULHv4i32
+ { 792, 5, 1, 30, "VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #792 = VQRDMULHv8i16
+ { 793, 5, 1, 43, "VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #793 = VQRSHLsv16i8
+ { 794, 5, 1, 42, "VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #794 = VQRSHLsv1i64
+ { 795, 5, 1, 42, "VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #795 = VQRSHLsv2i32
+ { 796, 5, 1, 43, "VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #796 = VQRSHLsv2i64
+ { 797, 5, 1, 42, "VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #797 = VQRSHLsv4i16
+ { 798, 5, 1, 43, "VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #798 = VQRSHLsv4i32
+ { 799, 5, 1, 43, "VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #799 = VQRSHLsv8i16
+ { 800, 5, 1, 42, "VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #800 = VQRSHLsv8i8
+ { 801, 5, 1, 43, "VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #801 = VQRSHLuv16i8
+ { 802, 5, 1, 42, "VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #802 = VQRSHLuv1i64
+ { 803, 5, 1, 42, "VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #803 = VQRSHLuv2i32
+ { 804, 5, 1, 43, "VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #804 = VQRSHLuv2i64
+ { 805, 5, 1, 42, "VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #805 = VQRSHLuv4i16
+ { 806, 5, 1, 43, "VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #806 = VQRSHLuv4i32
+ { 807, 5, 1, 43, "VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #807 = VQRSHLuv8i16
+ { 808, 5, 1, 42, "VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #808 = VQRSHLuv8i8
+ { 809, 5, 1, 42, "VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #809 = VQRSHRNsv2i32
+ { 810, 5, 1, 42, "VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #810 = VQRSHRNsv4i16
+ { 811, 5, 1, 42, "VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #811 = VQRSHRNsv8i8
+ { 812, 5, 1, 42, "VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #812 = VQRSHRNuv2i32
+ { 813, 5, 1, 42, "VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #813 = VQRSHRNuv4i16
+ { 814, 5, 1, 42, "VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #814 = VQRSHRNuv8i8
+ { 815, 5, 1, 42, "VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #815 = VQRSHRUNv2i32
+ { 816, 5, 1, 42, "VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #816 = VQRSHRUNv4i16
+ { 817, 5, 1, 42, "VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #817 = VQRSHRUNv8i8
+ { 818, 5, 1, 42, "VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #818 = VQSHLsiv16i8
+ { 819, 5, 1, 42, "VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #819 = VQSHLsiv1i64
+ { 820, 5, 1, 42, "VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #820 = VQSHLsiv2i32
+ { 821, 5, 1, 42, "VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #821 = VQSHLsiv2i64
+ { 822, 5, 1, 42, "VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #822 = VQSHLsiv4i16
+ { 823, 5, 1, 42, "VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #823 = VQSHLsiv4i32
+ { 824, 5, 1, 42, "VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #824 = VQSHLsiv8i16
+ { 825, 5, 1, 42, "VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #825 = VQSHLsiv8i8
+ { 826, 5, 1, 42, "VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #826 = VQSHLsuv16i8
+ { 827, 5, 1, 42, "VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #827 = VQSHLsuv1i64
+ { 828, 5, 1, 42, "VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #828 = VQSHLsuv2i32
+ { 829, 5, 1, 42, "VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #829 = VQSHLsuv2i64
+ { 830, 5, 1, 42, "VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #830 = VQSHLsuv4i16
+ { 831, 5, 1, 42, "VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #831 = VQSHLsuv4i32
+ { 832, 5, 1, 42, "VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #832 = VQSHLsuv8i16
+ { 833, 5, 1, 42, "VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #833 = VQSHLsuv8i8
+ { 834, 5, 1, 43, "VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #834 = VQSHLsv16i8
+ { 835, 5, 1, 42, "VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #835 = VQSHLsv1i64
+ { 836, 5, 1, 42, "VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #836 = VQSHLsv2i32
+ { 837, 5, 1, 43, "VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #837 = VQSHLsv2i64
+ { 838, 5, 1, 42, "VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #838 = VQSHLsv4i16
+ { 839, 5, 1, 43, "VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #839 = VQSHLsv4i32
+ { 840, 5, 1, 43, "VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #840 = VQSHLsv8i16
+ { 841, 5, 1, 42, "VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #841 = VQSHLsv8i8
+ { 842, 5, 1, 42, "VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #842 = VQSHLuiv16i8
+ { 843, 5, 1, 42, "VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #843 = VQSHLuiv1i64
+ { 844, 5, 1, 42, "VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #844 = VQSHLuiv2i32
+ { 845, 5, 1, 42, "VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #845 = VQSHLuiv2i64
+ { 846, 5, 1, 42, "VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #846 = VQSHLuiv4i16
+ { 847, 5, 1, 42, "VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #847 = VQSHLuiv4i32
+ { 848, 5, 1, 42, "VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #848 = VQSHLuiv8i16
+ { 849, 5, 1, 42, "VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #849 = VQSHLuiv8i8
+ { 850, 5, 1, 43, "VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #850 = VQSHLuv16i8
+ { 851, 5, 1, 42, "VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #851 = VQSHLuv1i64
+ { 852, 5, 1, 42, "VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #852 = VQSHLuv2i32
+ { 853, 5, 1, 43, "VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #853 = VQSHLuv2i64
+ { 854, 5, 1, 42, "VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #854 = VQSHLuv4i16
+ { 855, 5, 1, 43, "VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #855 = VQSHLuv4i32
+ { 856, 5, 1, 43, "VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #856 = VQSHLuv8i16
+ { 857, 5, 1, 42, "VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #857 = VQSHLuv8i8
+ { 858, 5, 1, 42, "VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #858 = VQSHRNsv2i32
+ { 859, 5, 1, 42, "VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #859 = VQSHRNsv4i16
+ { 860, 5, 1, 42, "VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #860 = VQSHRNsv8i8
+ { 861, 5, 1, 42, "VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #861 = VQSHRNuv2i32
+ { 862, 5, 1, 42, "VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #862 = VQSHRNuv4i16
+ { 863, 5, 1, 42, "VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #863 = VQSHRNuv8i8
+ { 864, 5, 1, 42, "VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #864 = VQSHRUNv2i32
+ { 865, 5, 1, 42, "VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #865 = VQSHRUNv4i16
+ { 866, 5, 1, 42, "VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #866 = VQSHRUNv8i8
+ { 867, 5, 1, 4, "VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #867 = VQSUBsv16i8
+ { 868, 5, 1, 3, "VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #868 = VQSUBsv1i64
+ { 869, 5, 1, 3, "VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #869 = VQSUBsv2i32
+ { 870, 5, 1, 4, "VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #870 = VQSUBsv2i64
+ { 871, 5, 1, 3, "VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #871 = VQSUBsv4i16
+ { 872, 5, 1, 4, "VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #872 = VQSUBsv4i32
+ { 873, 5, 1, 4, "VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #873 = VQSUBsv8i16
+ { 874, 5, 1, 3, "VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #874 = VQSUBsv8i8
+ { 875, 5, 1, 4, "VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #875 = VQSUBuv16i8
+ { 876, 5, 1, 3, "VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #876 = VQSUBuv1i64
+ { 877, 5, 1, 3, "VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #877 = VQSUBuv2i32
+ { 878, 5, 1, 4, "VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #878 = VQSUBuv2i64
+ { 879, 5, 1, 3, "VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #879 = VQSUBuv4i16
+ { 880, 5, 1, 4, "VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #880 = VQSUBuv4i32
+ { 881, 5, 1, 4, "VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #881 = VQSUBuv8i16
+ { 882, 5, 1, 3, "VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #882 = VQSUBuv8i8
+ { 883, 5, 1, 3, "VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #883 = VRADDHNv2i32
+ { 884, 5, 1, 3, "VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #884 = VRADDHNv4i16
+ { 885, 5, 1, 3, "VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #885 = VRADDHNv8i8
+ { 886, 4, 1, 57, "VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #886 = VRECPEd
+ { 887, 4, 1, 57, "VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #887 = VRECPEfd
+ { 888, 4, 1, 58, "VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #888 = VRECPEfq
+ { 889, 4, 1, 58, "VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #889 = VRECPEq
+ { 890, 5, 1, 40, "VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #890 = VRECPSfd
+ { 891, 5, 1, 41, "VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #891 = VRECPSfq
+ { 892, 4, 1, 21, "VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #892 = VREV16d8
+ { 893, 4, 1, 21, "VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #893 = VREV16q8
+ { 894, 4, 1, 21, "VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #894 = VREV32d16
+ { 895, 4, 1, 21, "VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #895 = VREV32d8
+ { 896, 4, 1, 21, "VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #896 = VREV32q16
+ { 897, 4, 1, 21, "VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #897 = VREV32q8
+ { 898, 4, 1, 21, "VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #898 = VREV64d16
+ { 899, 4, 1, 21, "VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #899 = VREV64d32
+ { 900, 4, 1, 21, "VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #900 = VREV64d8
+ { 901, 4, 1, 21, "VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #901 = VREV64df
+ { 902, 4, 1, 21, "VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #902 = VREV64q16
+ { 903, 4, 1, 21, "VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #903 = VREV64q32
+ { 904, 4, 1, 21, "VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #904 = VREV64q8
+ { 905, 4, 1, 21, "VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #905 = VREV64qf
+ { 906, 5, 1, 4, "VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #906 = VRHADDsv16i8
+ { 907, 5, 1, 3, "VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #907 = VRHADDsv2i32
+ { 908, 5, 1, 3, "VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #908 = VRHADDsv4i16
+ { 909, 5, 1, 4, "VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #909 = VRHADDsv4i32
+ { 910, 5, 1, 4, "VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #910 = VRHADDsv8i16
+ { 911, 5, 1, 3, "VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #911 = VRHADDsv8i8
+ { 912, 5, 1, 4, "VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #912 = VRHADDuv16i8
+ { 913, 5, 1, 3, "VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #913 = VRHADDuv2i32
+ { 914, 5, 1, 3, "VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #914 = VRHADDuv4i16
+ { 915, 5, 1, 4, "VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #915 = VRHADDuv4i32
+ { 916, 5, 1, 4, "VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #916 = VRHADDuv8i16
+ { 917, 5, 1, 3, "VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #917 = VRHADDuv8i8
+ { 918, 5, 1, 43, "VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #918 = VRSHLsv16i8
+ { 919, 5, 1, 42, "VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #919 = VRSHLsv1i64
+ { 920, 5, 1, 42, "VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #920 = VRSHLsv2i32
+ { 921, 5, 1, 43, "VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #921 = VRSHLsv2i64
+ { 922, 5, 1, 42, "VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #922 = VRSHLsv4i16
+ { 923, 5, 1, 43, "VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #923 = VRSHLsv4i32
+ { 924, 5, 1, 43, "VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #924 = VRSHLsv8i16
+ { 925, 5, 1, 42, "VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #925 = VRSHLsv8i8
+ { 926, 5, 1, 43, "VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #926 = VRSHLuv16i8
+ { 927, 5, 1, 42, "VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #927 = VRSHLuv1i64
+ { 928, 5, 1, 42, "VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #928 = VRSHLuv2i32
+ { 929, 5, 1, 43, "VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #929 = VRSHLuv2i64
+ { 930, 5, 1, 42, "VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #930 = VRSHLuv4i16
+ { 931, 5, 1, 43, "VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #931 = VRSHLuv4i32
+ { 932, 5, 1, 43, "VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #932 = VRSHLuv8i16
+ { 933, 5, 1, 42, "VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #933 = VRSHLuv8i8
+ { 934, 5, 1, 42, "VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #934 = VRSHRNv2i32
+ { 935, 5, 1, 42, "VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #935 = VRSHRNv4i16
+ { 936, 5, 1, 42, "VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #936 = VRSHRNv8i8
+ { 937, 5, 1, 42, "VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #937 = VRSHRsv16i8
+ { 938, 5, 1, 42, "VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #938 = VRSHRsv1i64
+ { 939, 5, 1, 42, "VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #939 = VRSHRsv2i32
+ { 940, 5, 1, 42, "VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #940 = VRSHRsv2i64
+ { 941, 5, 1, 42, "VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #941 = VRSHRsv4i16
+ { 942, 5, 1, 42, "VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #942 = VRSHRsv4i32
+ { 943, 5, 1, 42, "VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #943 = VRSHRsv8i16
+ { 944, 5, 1, 42, "VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #944 = VRSHRsv8i8
+ { 945, 5, 1, 42, "VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #945 = VRSHRuv16i8
+ { 946, 5, 1, 42, "VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #946 = VRSHRuv1i64
+ { 947, 5, 1, 42, "VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #947 = VRSHRuv2i32
+ { 948, 5, 1, 42, "VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #948 = VRSHRuv2i64
+ { 949, 5, 1, 42, "VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #949 = VRSHRuv4i16
+ { 950, 5, 1, 42, "VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #950 = VRSHRuv4i32
+ { 951, 5, 1, 42, "VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #951 = VRSHRuv8i16
+ { 952, 5, 1, 42, "VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #952 = VRSHRuv8i8
+ { 953, 4, 1, 57, "VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #953 = VRSQRTEd
+ { 954, 4, 1, 57, "VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #954 = VRSQRTEfd
+ { 955, 4, 1, 58, "VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #955 = VRSQRTEfq
+ { 956, 4, 1, 58, "VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #956 = VRSQRTEq
+ { 957, 5, 1, 40, "VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #957 = VRSQRTSfd
+ { 958, 5, 1, 41, "VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #958 = VRSQRTSfq
+ { 959, 6, 1, 33, "VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #959 = VRSRAsv16i8
+ { 960, 6, 1, 33, "VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #960 = VRSRAsv1i64
+ { 961, 6, 1, 33, "VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #961 = VRSRAsv2i32
+ { 962, 6, 1, 33, "VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #962 = VRSRAsv2i64
+ { 963, 6, 1, 33, "VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #963 = VRSRAsv4i16
+ { 964, 6, 1, 33, "VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #964 = VRSRAsv4i32
+ { 965, 6, 1, 33, "VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #965 = VRSRAsv8i16
+ { 966, 6, 1, 33, "VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #966 = VRSRAsv8i8
+ { 967, 6, 1, 33, "VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #967 = VRSRAuv16i8
+ { 968, 6, 1, 33, "VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #968 = VRSRAuv1i64
+ { 969, 6, 1, 33, "VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #969 = VRSRAuv2i32
+ { 970, 6, 1, 33, "VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #970 = VRSRAuv2i64
+ { 971, 6, 1, 33, "VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #971 = VRSRAuv4i16
+ { 972, 6, 1, 33, "VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #972 = VRSRAuv4i32
+ { 973, 6, 1, 33, "VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #973 = VRSRAuv8i16
+ { 974, 6, 1, 33, "VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #974 = VRSRAuv8i8
+ { 975, 5, 1, 3, "VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #975 = VRSUBHNv2i32
+ { 976, 5, 1, 3, "VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #976 = VRSUBHNv4i16
+ { 977, 5, 1, 3, "VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #977 = VRSUBHNv8i8
+ { 978, 6, 1, 25, "VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #978 = VSETLNi16
+ { 979, 6, 1, 25, "VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #979 = VSETLNi32
+ { 980, 6, 1, 25, "VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #980 = VSETLNi8
+ { 981, 5, 1, 44, "VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #981 = VSHLLi16
+ { 982, 5, 1, 44, "VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #982 = VSHLLi32
+ { 983, 5, 1, 44, "VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #983 = VSHLLi8
+ { 984, 5, 1, 44, "VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #984 = VSHLLsv2i64
+ { 985, 5, 1, 44, "VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #985 = VSHLLsv4i32
+ { 986, 5, 1, 44, "VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #986 = VSHLLsv8i16
+ { 987, 5, 1, 44, "VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #987 = VSHLLuv2i64
+ { 988, 5, 1, 44, "VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #988 = VSHLLuv4i32
+ { 989, 5, 1, 44, "VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #989 = VSHLLuv8i16
+ { 990, 5, 1, 44, "VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #990 = VSHLiv16i8
+ { 991, 5, 1, 44, "VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #991 = VSHLiv1i64
+ { 992, 5, 1, 44, "VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #992 = VSHLiv2i32
+ { 993, 5, 1, 44, "VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #993 = VSHLiv2i64
+ { 994, 5, 1, 44, "VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #994 = VSHLiv4i16
+ { 995, 5, 1, 44, "VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #995 = VSHLiv4i32
+ { 996, 5, 1, 44, "VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #996 = VSHLiv8i16
+ { 997, 5, 1, 44, "VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #997 = VSHLiv8i8
+ { 998, 5, 1, 45, "VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #998 = VSHLsv16i8
+ { 999, 5, 1, 44, "VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #999 = VSHLsv1i64
+ { 1000, 5, 1, 44, "VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1000 = VSHLsv2i32
+ { 1001, 5, 1, 45, "VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1001 = VSHLsv2i64
+ { 1002, 5, 1, 44, "VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1002 = VSHLsv4i16
+ { 1003, 5, 1, 45, "VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1003 = VSHLsv4i32
+ { 1004, 5, 1, 45, "VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1004 = VSHLsv8i16
+ { 1005, 5, 1, 44, "VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1005 = VSHLsv8i8
+ { 1006, 5, 1, 45, "VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1006 = VSHLuv16i8
+ { 1007, 5, 1, 44, "VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1007 = VSHLuv1i64
+ { 1008, 5, 1, 44, "VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1008 = VSHLuv2i32
+ { 1009, 5, 1, 45, "VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1009 = VSHLuv2i64
+ { 1010, 5, 1, 44, "VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1010 = VSHLuv4i16
+ { 1011, 5, 1, 45, "VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1011 = VSHLuv4i32
+ { 1012, 5, 1, 45, "VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1012 = VSHLuv8i16
+ { 1013, 5, 1, 44, "VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1013 = VSHLuv8i8
+ { 1014, 5, 1, 44, "VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1014 = VSHRNv2i32
+ { 1015, 5, 1, 44, "VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1015 = VSHRNv4i16
+ { 1016, 5, 1, 44, "VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1016 = VSHRNv8i8
+ { 1017, 5, 1, 44, "VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1017 = VSHRsv16i8
+ { 1018, 5, 1, 44, "VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1018 = VSHRsv1i64
+ { 1019, 5, 1, 44, "VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1019 = VSHRsv2i32
+ { 1020, 5, 1, 44, "VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1020 = VSHRsv2i64
+ { 1021, 5, 1, 44, "VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1021 = VSHRsv4i16
+ { 1022, 5, 1, 44, "VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1022 = VSHRsv4i32
+ { 1023, 5, 1, 44, "VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1023 = VSHRsv8i16
+ { 1024, 5, 1, 44, "VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1024 = VSHRsv8i8
+ { 1025, 5, 1, 44, "VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1025 = VSHRuv16i8
+ { 1026, 5, 1, 44, "VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1026 = VSHRuv1i64
+ { 1027, 5, 1, 44, "VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1027 = VSHRuv2i32
+ { 1028, 5, 1, 44, "VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1028 = VSHRuv2i64
+ { 1029, 5, 1, 44, "VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1029 = VSHRuv4i16
+ { 1030, 5, 1, 44, "VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1030 = VSHRuv4i32
+ { 1031, 5, 1, 44, "VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1031 = VSHRuv8i16
+ { 1032, 5, 1, 44, "VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1032 = VSHRuv8i8
+ { 1033, 4, 1, 67, "VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1033 = VSITOD
+ { 1034, 4, 1, 68, "VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1034 = VSITOS
+ { 1035, 6, 1, 45, "VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1035 = VSLIv16i8
+ { 1036, 6, 1, 44, "VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1036 = VSLIv1i64
+ { 1037, 6, 1, 44, "VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1037 = VSLIv2i32
+ { 1038, 6, 1, 45, "VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1038 = VSLIv2i64
+ { 1039, 6, 1, 44, "VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1039 = VSLIv4i16
+ { 1040, 6, 1, 45, "VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1040 = VSLIv4i32
+ { 1041, 6, 1, 45, "VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1041 = VSLIv8i16
+ { 1042, 6, 1, 44, "VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1042 = VSLIv8i8
+ { 1043, 4, 1, 81, "VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #1043 = VSQRTD
+ { 1044, 4, 1, 80, "VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1044 = VSQRTS
+ { 1045, 6, 1, 33, "VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1045 = VSRAsv16i8
+ { 1046, 6, 1, 33, "VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1046 = VSRAsv1i64
+ { 1047, 6, 1, 33, "VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1047 = VSRAsv2i32
+ { 1048, 6, 1, 33, "VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1048 = VSRAsv2i64
+ { 1049, 6, 1, 33, "VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1049 = VSRAsv4i16
+ { 1050, 6, 1, 33, "VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1050 = VSRAsv4i32
+ { 1051, 6, 1, 33, "VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1051 = VSRAsv8i16
+ { 1052, 6, 1, 33, "VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1052 = VSRAsv8i8
+ { 1053, 6, 1, 33, "VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1053 = VSRAuv16i8
+ { 1054, 6, 1, 33, "VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1054 = VSRAuv1i64
+ { 1055, 6, 1, 33, "VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1055 = VSRAuv2i32
+ { 1056, 6, 1, 33, "VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1056 = VSRAuv2i64
+ { 1057, 6, 1, 33, "VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1057 = VSRAuv4i16
+ { 1058, 6, 1, 33, "VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1058 = VSRAuv4i32
+ { 1059, 6, 1, 33, "VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1059 = VSRAuv8i16
+ { 1060, 6, 1, 33, "VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1060 = VSRAuv8i8
+ { 1061, 6, 1, 45, "VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1061 = VSRIv16i8
+ { 1062, 6, 1, 44, "VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1062 = VSRIv1i64
+ { 1063, 6, 1, 44, "VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1063 = VSRIv2i32
+ { 1064, 6, 1, 45, "VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1064 = VSRIv2i64
+ { 1065, 6, 1, 44, "VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1065 = VSRIv4i16
+ { 1066, 6, 1, 45, "VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1066 = VSRIv4i32
+ { 1067, 6, 1, 45, "VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1067 = VSRIv8i16
+ { 1068, 6, 1, 44, "VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1068 = VSRIv8i8
+ { 1069, 7, 0, 46, "VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1069 = VST1d16
+ { 1070, 7, 0, 46, "VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1070 = VST1d32
+ { 1071, 7, 0, 46, "VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1071 = VST1d64
+ { 1072, 7, 0, 46, "VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1072 = VST1d8
+ { 1073, 7, 0, 46, "VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1073 = VST1df
+ { 1074, 7, 0, 46, "VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1074 = VST1q16
+ { 1075, 7, 0, 46, "VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1075 = VST1q32
+ { 1076, 7, 0, 46, "VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1076 = VST1q64
+ { 1077, 7, 0, 46, "VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1077 = VST1q8
+ { 1078, 7, 0, 46, "VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1078 = VST1qf
+ { 1079, 9, 0, 46, "VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1079 = VST2LNd16
+ { 1080, 9, 0, 46, "VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1080 = VST2LNd32
+ { 1081, 9, 0, 46, "VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1081 = VST2LNd8
+ { 1082, 9, 0, 46, "VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1082 = VST2LNq16a
+ { 1083, 9, 0, 46, "VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1083 = VST2LNq16b
+ { 1084, 9, 0, 46, "VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1084 = VST2LNq32a
+ { 1085, 9, 0, 46, "VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1085 = VST2LNq32b
+ { 1086, 8, 0, 46, "VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1086 = VST2d16
+ { 1087, 8, 0, 46, "VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1087 = VST2d32
+ { 1088, 8, 0, 46, "VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1088 = VST2d64
+ { 1089, 8, 0, 46, "VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1089 = VST2d8
+ { 1090, 10, 0, 46, "VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1090 = VST2q16
+ { 1091, 10, 0, 46, "VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1091 = VST2q32
+ { 1092, 10, 0, 46, "VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1092 = VST2q8
+ { 1093, 10, 0, 46, "VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1093 = VST3LNd16
+ { 1094, 10, 0, 46, "VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1094 = VST3LNd32
+ { 1095, 10, 0, 46, "VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1095 = VST3LNd8
+ { 1096, 10, 0, 46, "VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1096 = VST3LNq16a
+ { 1097, 10, 0, 46, "VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1097 = VST3LNq16b
+ { 1098, 10, 0, 46, "VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1098 = VST3LNq32a
+ { 1099, 10, 0, 46, "VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1099 = VST3LNq32b
+ { 1100, 9, 0, 46, "VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1100 = VST3d16
+ { 1101, 9, 0, 46, "VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1101 = VST3d32
+ { 1102, 9, 0, 46, "VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1102 = VST3d64
+ { 1103, 9, 0, 46, "VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1103 = VST3d8
+ { 1104, 10, 1, 46, "VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1104 = VST3q16a
+ { 1105, 10, 1, 46, "VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1105 = VST3q16b
+ { 1106, 10, 1, 46, "VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1106 = VST3q32a
+ { 1107, 10, 1, 46, "VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1107 = VST3q32b
+ { 1108, 10, 1, 46, "VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1108 = VST3q8a
+ { 1109, 10, 1, 46, "VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1109 = VST3q8b
+ { 1110, 11, 0, 46, "VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1110 = VST4LNd16
+ { 1111, 11, 0, 46, "VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1111 = VST4LNd32
+ { 1112, 11, 0, 46, "VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1112 = VST4LNd8
+ { 1113, 11, 0, 46, "VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1113 = VST4LNq16a
+ { 1114, 11, 0, 46, "VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1114 = VST4LNq16b
+ { 1115, 11, 0, 46, "VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1115 = VST4LNq32a
+ { 1116, 11, 0, 46, "VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1116 = VST4LNq32b
+ { 1117, 10, 0, 46, "VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1117 = VST4d16
+ { 1118, 10, 0, 46, "VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1118 = VST4d32
+ { 1119, 10, 0, 46, "VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1119 = VST4d64
+ { 1120, 10, 0, 46, "VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1120 = VST4d8
+ { 1121, 11, 1, 46, "VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1121 = VST4q16a
+ { 1122, 11, 1, 46, "VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1122 = VST4q16b
+ { 1123, 11, 1, 46, "VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1123 = VST4q32a
+ { 1124, 11, 1, 46, "VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1124 = VST4q32b
+ { 1125, 11, 1, 46, "VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1125 = VST4q8a
+ { 1126, 11, 1, 46, "VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1126 = VST4q8b
{ 1127, 5, 0, 85, "VSTMD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #1127 = VSTMD
{ 1128, 5, 0, 85, "VSTMS", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #1128 = VSTMS
- { 1129, 5, 0, 84, "VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1129 = VSTRD
- { 1130, 5, 0, 85, "VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #1130 = VSTRQ
- { 1131, 5, 0, 83, "VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #1131 = VSTRS
- { 1132, 5, 1, 62, "VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1132 = VSUBD
- { 1133, 5, 1, 3, "VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #1133 = VSUBHNv2i32
- { 1134, 5, 1, 3, "VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #1134 = VSUBHNv4i16
- { 1135, 5, 1, 3, "VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #1135 = VSUBHNv8i8
- { 1136, 5, 1, 44, "VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1136 = VSUBLsv2i64
- { 1137, 5, 1, 44, "VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1137 = VSUBLsv4i32
- { 1138, 5, 1, 44, "VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1138 = VSUBLsv8i16
- { 1139, 5, 1, 44, "VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1139 = VSUBLuv2i64
- { 1140, 5, 1, 44, "VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1140 = VSUBLuv4i32
- { 1141, 5, 1, 44, "VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1141 = VSUBLuv8i16
- { 1142, 5, 1, 61, "VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #1142 = VSUBS
- { 1143, 5, 1, 47, "VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1143 = VSUBWsv2i64
- { 1144, 5, 1, 47, "VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1144 = VSUBWsv4i32
- { 1145, 5, 1, 47, "VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1145 = VSUBWsv8i16
- { 1146, 5, 1, 47, "VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1146 = VSUBWuv2i64
- { 1147, 5, 1, 47, "VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1147 = VSUBWuv4i32
- { 1148, 5, 1, 47, "VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1148 = VSUBWuv8i16
- { 1149, 5, 1, 1, "VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1149 = VSUBfd
- { 1150, 5, 1, 1, "VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1150 = VSUBfd_sfp
- { 1151, 5, 1, 2, "VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1151 = VSUBfq
- { 1152, 5, 1, 48, "VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1152 = VSUBv16i8
- { 1153, 5, 1, 47, "VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1153 = VSUBv1i64
- { 1154, 5, 1, 47, "VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1154 = VSUBv2i32
- { 1155, 5, 1, 48, "VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1155 = VSUBv2i64
- { 1156, 5, 1, 47, "VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1156 = VSUBv4i16
- { 1157, 5, 1, 48, "VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1157 = VSUBv4i32
- { 1158, 5, 1, 48, "VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1158 = VSUBv8i16
- { 1159, 5, 1, 47, "VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1159 = VSUBv8i8
- { 1160, 5, 1, 49, "VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1160 = VTBL1
- { 1161, 6, 1, 50, "VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1161 = VTBL2
- { 1162, 7, 1, 51, "VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1162 = VTBL3
- { 1163, 8, 1, 52, "VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1163 = VTBL4
- { 1164, 6, 1, 53, "VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #1164 = VTBX1
- { 1165, 7, 1, 54, "VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1165 = VTBX2
- { 1166, 8, 1, 55, "VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1166 = VTBX3
- { 1167, 9, 1, 56, "VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1167 = VTBX4
- { 1168, 4, 1, 65, "VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1168 = VTOSIZD
- { 1169, 4, 1, 70, "VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1169 = VTOSIZS
- { 1170, 4, 1, 65, "VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1170 = VTOUIZD
- { 1171, 4, 1, 70, "VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1171 = VTOUIZS
- { 1172, 6, 2, 35, "VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1172 = VTRNd16
- { 1173, 6, 2, 35, "VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1173 = VTRNd32
- { 1174, 6, 2, 35, "VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1174 = VTRNd8
- { 1175, 6, 2, 36, "VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1175 = VTRNq16
- { 1176, 6, 2, 36, "VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1176 = VTRNq32
- { 1177, 6, 2, 36, "VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1177 = VTRNq8
- { 1178, 5, 1, 4, "VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1178 = VTSTv16i8
- { 1179, 5, 1, 3, "VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1179 = VTSTv2i32
- { 1180, 5, 1, 3, "VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1180 = VTSTv4i16
- { 1181, 5, 1, 4, "VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1181 = VTSTv4i32
- { 1182, 5, 1, 4, "VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1182 = VTSTv8i16
- { 1183, 5, 1, 3, "VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1183 = VTSTv8i8
- { 1184, 4, 1, 67, "VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #1184 = VUITOD
- { 1185, 4, 1, 68, "VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1185 = VUITOS
- { 1186, 6, 2, 35, "VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1186 = VUZPd16
- { 1187, 6, 2, 35, "VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1187 = VUZPd32
- { 1188, 6, 2, 35, "VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1188 = VUZPd8
- { 1189, 6, 2, 37, "VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1189 = VUZPq16
- { 1190, 6, 2, 37, "VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1190 = VUZPq32
- { 1191, 6, 2, 37, "VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1191 = VUZPq8
- { 1192, 6, 2, 35, "VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1192 = VZIPd16
- { 1193, 6, 2, 35, "VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1193 = VZIPd32
- { 1194, 6, 2, 35, "VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1194 = VZIPd8
- { 1195, 6, 2, 37, "VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1195 = VZIPq16
- { 1196, 6, 2, 37, "VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1196 = VZIPq32
- { 1197, 6, 2, 37, "VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1197 = VZIPq8
+ { 1129, 5, 0, 84, "VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #1129 = VSTRD
+ { 1130, 5, 0, 85, "VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1130 = VSTRQ
+ { 1131, 5, 0, 83, "VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #1131 = VSTRS
+ { 1132, 5, 1, 62, "VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1132 = VSUBD
+ { 1133, 5, 1, 3, "VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1133 = VSUBHNv2i32
+ { 1134, 5, 1, 3, "VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1134 = VSUBHNv4i16
+ { 1135, 5, 1, 3, "VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1135 = VSUBHNv8i8
+ { 1136, 5, 1, 44, "VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1136 = VSUBLsv2i64
+ { 1137, 5, 1, 44, "VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1137 = VSUBLsv4i32
+ { 1138, 5, 1, 44, "VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1138 = VSUBLsv8i16
+ { 1139, 5, 1, 44, "VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1139 = VSUBLuv2i64
+ { 1140, 5, 1, 44, "VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1140 = VSUBLuv4i32
+ { 1141, 5, 1, 44, "VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1141 = VSUBLuv8i16
+ { 1142, 5, 1, 61, "VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1142 = VSUBS
+ { 1143, 5, 1, 47, "VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1143 = VSUBWsv2i64
+ { 1144, 5, 1, 47, "VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1144 = VSUBWsv4i32
+ { 1145, 5, 1, 47, "VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1145 = VSUBWsv8i16
+ { 1146, 5, 1, 47, "VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1146 = VSUBWuv2i64
+ { 1147, 5, 1, 47, "VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1147 = VSUBWuv4i32
+ { 1148, 5, 1, 47, "VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1148 = VSUBWuv8i16
+ { 1149, 5, 1, 1, "VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1149 = VSUBfd
+ { 1150, 5, 1, 1, "VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1150 = VSUBfd_sfp
+ { 1151, 5, 1, 2, "VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1151 = VSUBfq
+ { 1152, 5, 1, 48, "VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1152 = VSUBv16i8
+ { 1153, 5, 1, 47, "VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1153 = VSUBv1i64
+ { 1154, 5, 1, 47, "VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1154 = VSUBv2i32
+ { 1155, 5, 1, 48, "VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1155 = VSUBv2i64
+ { 1156, 5, 1, 47, "VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1156 = VSUBv4i16
+ { 1157, 5, 1, 48, "VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1157 = VSUBv4i32
+ { 1158, 5, 1, 48, "VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1158 = VSUBv8i16
+ { 1159, 5, 1, 47, "VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1159 = VSUBv8i8
+ { 1160, 5, 1, 49, "VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1160 = VTBL1
+ { 1161, 6, 1, 50, "VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1161 = VTBL2
+ { 1162, 7, 1, 51, "VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1162 = VTBL3
+ { 1163, 8, 1, 52, "VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1163 = VTBL4
+ { 1164, 6, 1, 53, "VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1164 = VTBX1
+ { 1165, 7, 1, 54, "VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1165 = VTBX2
+ { 1166, 8, 1, 55, "VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1166 = VTBX3
+ { 1167, 9, 1, 56, "VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1167 = VTBX4
+ { 1168, 4, 1, 65, "VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1168 = VTOSIZD
+ { 1169, 4, 1, 70, "VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1169 = VTOSIZS
+ { 1170, 4, 1, 65, "VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1170 = VTOUIZD
+ { 1171, 4, 1, 70, "VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1171 = VTOUIZS
+ { 1172, 6, 2, 35, "VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1172 = VTRNd16
+ { 1173, 6, 2, 35, "VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1173 = VTRNd32
+ { 1174, 6, 2, 35, "VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1174 = VTRNd8
+ { 1175, 6, 2, 36, "VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1175 = VTRNq16
+ { 1176, 6, 2, 36, "VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1176 = VTRNq32
+ { 1177, 6, 2, 36, "VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1177 = VTRNq8
+ { 1178, 5, 1, 4, "VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1178 = VTSTv16i8
+ { 1179, 5, 1, 3, "VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1179 = VTSTv2i32
+ { 1180, 5, 1, 3, "VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1180 = VTSTv4i16
+ { 1181, 5, 1, 4, "VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1181 = VTSTv4i32
+ { 1182, 5, 1, 4, "VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1182 = VTSTv8i16
+ { 1183, 5, 1, 3, "VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1183 = VTSTv8i8
+ { 1184, 4, 1, 67, "VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1184 = VUITOD
+ { 1185, 4, 1, 68, "VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1185 = VUITOS
+ { 1186, 6, 2, 35, "VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1186 = VUZPd16
+ { 1187, 6, 2, 35, "VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1187 = VUZPd32
+ { 1188, 6, 2, 35, "VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1188 = VUZPd8
+ { 1189, 6, 2, 37, "VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1189 = VUZPq16
+ { 1190, 6, 2, 37, "VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1190 = VUZPq32
+ { 1191, 6, 2, 37, "VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1191 = VUZPq8
+ { 1192, 6, 2, 35, "VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1192 = VZIPd16
+ { 1193, 6, 2, 35, "VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1193 = VZIPd32
+ { 1194, 6, 2, 35, "VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1194 = VZIPd8
+ { 1195, 6, 2, 37, "VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1195 = VZIPq16
+ { 1196, 6, 2, 37, "VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1196 = VZIPq32
+ { 1197, 6, 2, 37, "VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1197 = VZIPq8
{ 1198, 3, 1, 88, "t2ADCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1198 = t2ADCSri
{ 1199, 3, 1, 89, "t2ADCSrr", 0|(1<<TID::Commutable), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1199 = t2ADCSrr
- { 1200, 4, 1, 90, "t2ADCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo126 }, // Inst #1200 = t2ADCSrs
+ { 1200, 4, 1, 90, "t2ADCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo128 }, // Inst #1200 = t2ADCSrs
{ 1201, 6, 1, 88, "t2ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1201 = t2ADCri
{ 1202, 6, 1, 89, "t2ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1202 = t2ADCrr
{ 1203, 7, 1, 90, "t2ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo37 }, // Inst #1203 = t2ADCrs
@@ -1422,14 +1425,14 @@ static const TargetInstrDesc ARMInsts[] = {
{ 1239, 6, 1, 88, "t2EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1239 = t2EORri
{ 1240, 6, 1, 89, "t2EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1240 = t2EORrr
{ 1241, 7, 1, 90, "t2EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1241 = t2EORrs
- { 1242, 2, 0, 92, "t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo127 }, // Inst #1242 = t2IT
+ { 1242, 2, 0, 92, "t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1242 = t2IT
{ 1243, 0, 0, 128, "t2Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1243 = t2Int_MemBarrierV7
{ 1244, 0, 0, 128, "t2Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1244 = t2Int_SyncBarrierV7
- { 1245, 1, 0, 128, "t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers3, OperandInfo16 }, // Inst #1245 = t2Int_eh_sjlj_setjmp
+ { 1245, 1, 0, 128, "t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers4, OperandInfo16 }, // Inst #1245 = t2Int_eh_sjlj_setjmp
{ 1246, 5, 0, 103, "t2LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1246 = t2LDM
{ 1247, 5, 0, 0, "t2LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1247 = t2LDM_RET
- { 1248, 6, 2, 102, "t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1248 = t2LDRB_POST
- { 1249, 6, 2, 102, "t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1249 = t2LDRB_PRE
+ { 1248, 6, 2, 102, "t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1248 = t2LDRB_POST
+ { 1249, 6, 2, 102, "t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1249 = t2LDRB_PRE
{ 1250, 5, 1, 101, "t2LDRBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1250 = t2LDRBi12
{ 1251, 5, 1, 101, "t2LDRBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1251 = t2LDRBi8
{ 1252, 4, 1, 101, "t2LDRBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1252 = t2LDRBpci
@@ -1440,26 +1443,26 @@ static const TargetInstrDesc ARMInsts[] = {
{ 1257, 4, 1, 128, "t2LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1257 = t2LDREXB
{ 1258, 5, 2, 128, "t2LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1258 = t2LDREXD
{ 1259, 4, 1, 128, "t2LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1259 = t2LDREXH
- { 1260, 6, 2, 102, "t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1260 = t2LDRH_POST
- { 1261, 6, 2, 102, "t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1261 = t2LDRH_PRE
+ { 1260, 6, 2, 102, "t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1260 = t2LDRH_POST
+ { 1261, 6, 2, 102, "t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1261 = t2LDRH_PRE
{ 1262, 5, 1, 101, "t2LDRHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1262 = t2LDRHi12
{ 1263, 5, 1, 101, "t2LDRHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1263 = t2LDRHi8
{ 1264, 4, 1, 101, "t2LDRHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1264 = t2LDRHpci
{ 1265, 6, 1, 104, "t2LDRHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1265 = t2LDRHs
- { 1266, 6, 2, 102, "t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1266 = t2LDRSB_POST
- { 1267, 6, 2, 102, "t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1267 = t2LDRSB_PRE
+ { 1266, 6, 2, 102, "t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1266 = t2LDRSB_POST
+ { 1267, 6, 2, 102, "t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1267 = t2LDRSB_PRE
{ 1268, 5, 1, 101, "t2LDRSBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1268 = t2LDRSBi12
{ 1269, 5, 1, 101, "t2LDRSBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1269 = t2LDRSBi8
{ 1270, 4, 1, 101, "t2LDRSBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1270 = t2LDRSBpci
{ 1271, 6, 1, 104, "t2LDRSBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1271 = t2LDRSBs
- { 1272, 6, 2, 102, "t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1272 = t2LDRSH_POST
- { 1273, 6, 2, 102, "t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1273 = t2LDRSH_PRE
+ { 1272, 6, 2, 102, "t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1272 = t2LDRSH_POST
+ { 1273, 6, 2, 102, "t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1273 = t2LDRSH_PRE
{ 1274, 5, 1, 101, "t2LDRSHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1274 = t2LDRSHi12
{ 1275, 5, 1, 101, "t2LDRSHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1275 = t2LDRSHi8
{ 1276, 4, 1, 101, "t2LDRSHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1276 = t2LDRSHpci
{ 1277, 6, 1, 104, "t2LDRSHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1277 = t2LDRSHs
- { 1278, 6, 2, 102, "t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1278 = t2LDR_POST
- { 1279, 6, 2, 102, "t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1279 = t2LDR_PRE
+ { 1278, 6, 2, 102, "t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1278 = t2LDR_POST
+ { 1279, 6, 2, 102, "t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1279 = t2LDR_PRE
{ 1280, 5, 1, 101, "t2LDRi12", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1280 = t2LDRi12
{ 1281, 5, 1, 101, "t2LDRi8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1281 = t2LDRi8
{ 1282, 4, 1, 101, "t2LDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1282 = t2LDRpci
@@ -1473,20 +1476,20 @@ static const TargetInstrDesc ARMInsts[] = {
{ 1290, 6, 1, 114, "t2LSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1290 = t2LSRrr
{ 1291, 6, 1, 109, "t2MLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1291 = t2MLA
{ 1292, 6, 1, 109, "t2MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1292 = t2MLS
- { 1293, 6, 1, 95, "t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1293 = t2MOVCCasr
+ { 1293, 6, 1, 95, "t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1293 = t2MOVCCasr
{ 1294, 5, 1, 93, "t2MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1294 = t2MOVCCi
- { 1295, 6, 1, 95, "t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1295 = t2MOVCClsl
- { 1296, 6, 1, 95, "t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1296 = t2MOVCClsr
+ { 1295, 6, 1, 95, "t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1295 = t2MOVCClsl
+ { 1296, 6, 1, 95, "t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1296 = t2MOVCClsr
{ 1297, 5, 1, 94, "t2MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1297 = t2MOVCCr
- { 1298, 6, 1, 95, "t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1298 = t2MOVCCror
+ { 1298, 6, 1, 95, "t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1298 = t2MOVCCror
{ 1299, 5, 1, 111, "t2MOVTi16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1299 = t2MOVTi16
{ 1300, 5, 1, 111, "t2MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1300 = t2MOVi
{ 1301, 4, 1, 111, "t2MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1301 = t2MOVi16
{ 1302, 4, 1, 111, "t2MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(2<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1302 = t2MOVi32imm
{ 1303, 5, 1, 112, "t2MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #1303 = t2MOVr
{ 1304, 5, 1, 113, "t2MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo36 }, // Inst #1304 = t2MOVrx
- { 1305, 2, 1, 113, "t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo130 }, // Inst #1305 = t2MOVsra_flag
- { 1306, 2, 1, 113, "t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo130 }, // Inst #1306 = t2MOVsrl_flag
+ { 1305, 2, 1, 113, "t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo132 }, // Inst #1305 = t2MOVsra_flag
+ { 1306, 2, 1, 113, "t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo132 }, // Inst #1306 = t2MOVsrl_flag
{ 1307, 5, 1, 116, "t2MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1307 = t2MUL
{ 1308, 5, 1, 111, "t2MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1308 = t2MVNi
{ 1309, 4, 1, 112, "t2MVNr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1309 = t2MVNr
@@ -1504,13 +1507,13 @@ static const TargetInstrDesc ARMInsts[] = {
{ 1321, 4, 1, 125, "t2REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1321 = t2REVSH
{ 1322, 6, 1, 113, "t2RORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1322 = t2RORri
{ 1323, 6, 1, 114, "t2RORrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1323 = t2RORrr
- { 1324, 4, 1, 88, "t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo131 }, // Inst #1324 = t2RSBSri
- { 1325, 5, 1, 90, "t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo132 }, // Inst #1325 = t2RSBSrs
+ { 1324, 4, 1, 88, "t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo133 }, // Inst #1324 = t2RSBSri
+ { 1325, 5, 1, 90, "t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo134 }, // Inst #1325 = t2RSBSrs
{ 1326, 5, 1, 88, "t2RSBri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1326 = t2RSBri
{ 1327, 6, 1, 90, "t2RSBrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1327 = t2RSBrs
{ 1328, 3, 1, 88, "t2SBCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1328 = t2SBCSri
{ 1329, 3, 1, 89, "t2SBCSrr", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1329 = t2SBCSrr
- { 1330, 4, 1, 90, "t2SBCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo126 }, // Inst #1330 = t2SBCSrs
+ { 1330, 4, 1, 90, "t2SBCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo128 }, // Inst #1330 = t2SBCSrs
{ 1331, 6, 1, 88, "t2SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1331 = t2SBCri
{ 1332, 6, 1, 89, "t2SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1332 = t2SBCrr
{ 1333, 7, 1, 90, "t2SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo37 }, // Inst #1333 = t2SBCrs
@@ -1533,23 +1536,23 @@ static const TargetInstrDesc ARMInsts[] = {
{ 1350, 5, 1, 115, "t2SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1350 = t2SMULWB
{ 1351, 5, 1, 115, "t2SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1351 = t2SMULWT
{ 1352, 5, 0, 120, "t2STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1352 = t2STM
- { 1353, 6, 1, 119, "t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1353 = t2STRB_POST
- { 1354, 6, 1, 119, "t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1354 = t2STRB_PRE
+ { 1353, 6, 1, 119, "t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1353 = t2STRB_POST
+ { 1354, 6, 1, 119, "t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1354 = t2STRB_PRE
{ 1355, 5, 0, 118, "t2STRBi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1355 = t2STRBi12
{ 1356, 5, 0, 118, "t2STRBi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1356 = t2STRBi8
{ 1357, 6, 0, 121, "t2STRBs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1357 = t2STRBs
{ 1358, 6, 0, 121, "t2STRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1358 = t2STRDi8
- { 1359, 5, 1, 128, "t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1359 = t2STREX
- { 1360, 5, 1, 128, "t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1360 = t2STREXB
- { 1361, 6, 1, 128, "t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1361 = t2STREXD
- { 1362, 5, 1, 128, "t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1362 = t2STREXH
- { 1363, 6, 1, 119, "t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1363 = t2STRH_POST
- { 1364, 6, 1, 119, "t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1364 = t2STRH_PRE
+ { 1359, 5, 1, 128, "t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1359 = t2STREX
+ { 1360, 5, 1, 128, "t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1360 = t2STREXB
+ { 1361, 6, 1, 128, "t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #1361 = t2STREXD
+ { 1362, 5, 1, 128, "t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1362 = t2STREXH
+ { 1363, 6, 1, 119, "t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1363 = t2STRH_POST
+ { 1364, 6, 1, 119, "t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1364 = t2STRH_PRE
{ 1365, 5, 0, 118, "t2STRHi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1365 = t2STRHi12
{ 1366, 5, 0, 118, "t2STRHi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1366 = t2STRHi8
{ 1367, 6, 0, 121, "t2STRHs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1367 = t2STRHs
- { 1368, 6, 1, 119, "t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1368 = t2STR_POST
- { 1369, 6, 1, 119, "t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1369 = t2STR_PRE
+ { 1368, 6, 1, 119, "t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1368 = t2STR_POST
+ { 1369, 6, 1, 119, "t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1369 = t2STR_PRE
{ 1370, 5, 0, 118, "t2STRi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1370 = t2STRi12
{ 1371, 5, 0, 118, "t2STRi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1371 = t2STRi8
{ 1372, 6, 0, 121, "t2STRs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1372 = t2STRs
@@ -1561,7 +1564,7 @@ static const TargetInstrDesc ARMInsts[] = {
{ 1378, 3, 1, 128, "t2SUBrSPi12_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1378 = t2SUBrSPi12_
{ 1379, 3, 1, 128, "t2SUBrSPi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1379 = t2SUBrSPi_
{ 1380, 7, 1, 90, "t2SUBrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1380 = t2SUBrSPs
- { 1381, 4, 1, 128, "t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo126 }, // Inst #1381 = t2SUBrSPs_
+ { 1381, 4, 1, 128, "t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo128 }, // Inst #1381 = t2SUBrSPs_
{ 1382, 6, 1, 88, "t2SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1382 = t2SUBri
{ 1383, 6, 1, 88, "t2SUBri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1383 = t2SUBri12
{ 1384, 6, 1, 89, "t2SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1384 = t2SUBrr
@@ -1597,106 +1600,106 @@ static const TargetInstrDesc ARMInsts[] = {
{ 1414, 5, 1, 126, "t2UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1414 = t2UXTBr_rot
{ 1415, 4, 1, 125, "t2UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1415 = t2UXTHr
{ 1416, 5, 1, 126, "t2UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1416 = t2UXTHr_rot
- { 1417, 6, 2, 89, "tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo134 }, // Inst #1417 = tADC
+ { 1417, 6, 2, 89, "tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo136 }, // Inst #1417 = tADC
{ 1418, 5, 1, 89, "tADDhirr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1418 = tADDhirr
- { 1419, 6, 2, 88, "tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1419 = tADDi3
- { 1420, 6, 2, 88, "tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1420 = tADDi8
- { 1421, 2, 1, 88, "tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1421 = tADDrPCi
- { 1422, 3, 1, 89, "tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1422 = tADDrSP
- { 1423, 3, 1, 88, "tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1423 = tADDrSPi
- { 1424, 6, 2, 89, "tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1424 = tADDrr
- { 1425, 3, 1, 88, "tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1425 = tADDspi
- { 1426, 3, 1, 89, "tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1426 = tADDspr
+ { 1419, 6, 2, 88, "tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1419 = tADDi3
+ { 1420, 6, 2, 88, "tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1420 = tADDi8
+ { 1421, 2, 1, 88, "tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1421 = tADDrPCi
+ { 1422, 3, 1, 89, "tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1422 = tADDrSP
+ { 1423, 3, 1, 88, "tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1423 = tADDrSPi
+ { 1424, 6, 2, 89, "tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo142 }, // Inst #1424 = tADDrr
+ { 1425, 3, 1, 88, "tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1425 = tADDspi
+ { 1426, 3, 1, 89, "tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1426 = tADDspr
{ 1427, 3, 1, 128, "tADDspr_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo3 }, // Inst #1427 = tADDspr_
- { 1428, 1, 0, 128, "tADJCALLSTACKDOWN", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo14 }, // Inst #1428 = tADJCALLSTACKDOWN
- { 1429, 2, 0, 128, "tADJCALLSTACKUP", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo127 }, // Inst #1429 = tADJCALLSTACKUP
- { 1430, 6, 2, 89, "tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1430 = tAND
- { 1431, 3, 1, 128, "tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo142 }, // Inst #1431 = tANDsp
- { 1432, 6, 2, 113, "tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1432 = tASRri
- { 1433, 6, 2, 114, "tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1433 = tASRrr
+ { 1428, 1, 0, 128, "tADJCALLSTACKDOWN", 0, 0|(1<<4), ImplicitList2, ImplicitList2, Barriers2, OperandInfo14 }, // Inst #1428 = tADJCALLSTACKDOWN
+ { 1429, 2, 0, 128, "tADJCALLSTACKUP", 0, 0|(1<<4), ImplicitList2, ImplicitList2, Barriers2, OperandInfo129 }, // Inst #1429 = tADJCALLSTACKUP
+ { 1430, 6, 2, 89, "tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1430 = tAND
+ { 1431, 3, 1, 128, "tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo144 }, // Inst #1431 = tANDsp
+ { 1432, 6, 2, 113, "tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1432 = tASRri
+ { 1433, 6, 2, 114, "tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1433 = tASRrr
{ 1434, 1, 0, 0, "tB", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1434 = tB
- { 1435, 6, 2, 89, "tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1435 = tBIC
- { 1436, 1, 0, 0, "tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1436 = tBL
- { 1437, 1, 0, 0, "tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1437 = tBLXi
- { 1438, 1, 0, 0, "tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1438 = tBLXi_r9
- { 1439, 1, 0, 0, "tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #1439 = tBLXr
- { 1440, 1, 0, 0, "tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #1440 = tBLXr_r9
- { 1441, 1, 0, 0, "tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1441 = tBLr9
+ { 1435, 6, 2, 89, "tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1435 = tBIC
+ { 1436, 1, 0, 0, "tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers3, OperandInfo14 }, // Inst #1436 = tBL
+ { 1437, 1, 0, 0, "tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers3, OperandInfo14 }, // Inst #1437 = tBLXi
+ { 1438, 1, 0, 0, "tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers3, OperandInfo14 }, // Inst #1438 = tBLXi_r9
+ { 1439, 1, 0, 0, "tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers3, OperandInfo16 }, // Inst #1439 = tBLXr
+ { 1440, 1, 0, 0, "tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers3, OperandInfo16 }, // Inst #1440 = tBLXr_r9
+ { 1441, 1, 0, 0, "tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers3, OperandInfo14 }, // Inst #1441 = tBLr9
{ 1442, 1, 0, 0, "tBRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #1442 = tBRIND
- { 1443, 3, 0, 0, "tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1443 = tBR_JTr
- { 1444, 1, 0, 0, "tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo144 }, // Inst #1444 = tBX
+ { 1443, 3, 0, 0, "tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1443 = tBR_JTr
+ { 1444, 1, 0, 0, "tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers3, OperandInfo146 }, // Inst #1444 = tBX
{ 1445, 0, 0, 0, "tBX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1445 = tBX_RET
- { 1446, 1, 0, 0, "tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo144 }, // Inst #1446 = tBX_RET_vararg
- { 1447, 1, 0, 0, "tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo144 }, // Inst #1447 = tBXr9
+ { 1446, 1, 0, 0, "tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo146 }, // Inst #1446 = tBX_RET_vararg
+ { 1447, 1, 0, 0, "tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers3, OperandInfo146 }, // Inst #1447 = tBXr9
{ 1448, 3, 0, 0, "tBcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1448 = tBcc
{ 1449, 1, 0, 0, "tBfar", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, ImplicitList8, NULL, OperandInfo14 }, // Inst #1449 = tBfar
- { 1450, 2, 0, 0, "tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1450 = tCBNZ
- { 1451, 2, 0, 0, "tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1451 = tCBZ
- { 1452, 4, 0, 98, "tCMN", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1452 = tCMN
- { 1453, 4, 0, 98, "tCMNZ", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1453 = tCMNZ
+ { 1450, 2, 0, 0, "tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1450 = tCBNZ
+ { 1451, 2, 0, 0, "tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1451 = tCBZ
+ { 1452, 4, 0, 98, "tCMN", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1452 = tCMN
+ { 1453, 4, 0, 98, "tCMNz", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1453 = tCMNz
{ 1454, 4, 0, 98, "tCMPhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1454 = tCMPhir
- { 1455, 4, 0, 97, "tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo146 }, // Inst #1455 = tCMPi8
- { 1456, 4, 0, 98, "tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1456 = tCMPr
+ { 1455, 4, 0, 97, "tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo148 }, // Inst #1455 = tCMPi8
+ { 1456, 4, 0, 98, "tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1456 = tCMPr
{ 1457, 4, 0, 98, "tCMPzhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1457 = tCMPzhir
- { 1458, 4, 0, 97, "tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo146 }, // Inst #1458 = tCMPzi8
- { 1459, 4, 0, 98, "tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1459 = tCMPzr
- { 1460, 6, 2, 89, "tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1460 = tEOR
- { 1461, 1, 0, 128, "tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers4, OperandInfo16 }, // Inst #1461 = tInt_eh_sjlj_setjmp
+ { 1458, 4, 0, 97, "tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo148 }, // Inst #1458 = tCMPzi8
+ { 1459, 4, 0, 98, "tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1459 = tCMPzr
+ { 1460, 6, 2, 89, "tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1460 = tEOR
+ { 1461, 1, 0, 128, "tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers5, OperandInfo16 }, // Inst #1461 = tInt_eh_sjlj_setjmp
{ 1462, 5, 0, 103, "tLDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1462 = tLDM
- { 1463, 6, 1, 104, "tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1463 = tLDR
- { 1464, 6, 1, 104, "tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1464 = tLDRB
- { 1465, 6, 1, 104, "tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1465 = tLDRH
- { 1466, 5, 1, 104, "tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1466 = tLDRSB
- { 1467, 5, 1, 104, "tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1467 = tLDRSH
- { 1468, 4, 1, 101, "tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo146 }, // Inst #1468 = tLDRcp
- { 1469, 4, 1, 101, "tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo146 }, // Inst #1469 = tLDRpci
+ { 1463, 6, 1, 104, "tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1463 = tLDR
+ { 1464, 6, 1, 104, "tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1464 = tLDRB
+ { 1465, 6, 1, 104, "tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1465 = tLDRH
+ { 1466, 5, 1, 104, "tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1466 = tLDRSB
+ { 1467, 5, 1, 104, "tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1467 = tLDRSH
+ { 1468, 4, 1, 101, "tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1468 = tLDRcp
+ { 1469, 4, 1, 101, "tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1469 = tLDRpci
{ 1470, 3, 1, 128, "tLDRpci_pic", 0|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1470 = tLDRpci_pic
- { 1471, 5, 1, 101, "tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1471 = tLDRspi
- { 1472, 4, 1, 88, "tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo146 }, // Inst #1472 = tLEApcrel
- { 1473, 5, 1, 88, "tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1473 = tLEApcrelJT
- { 1474, 6, 2, 113, "tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1474 = tLSLri
- { 1475, 6, 2, 114, "tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1475 = tLSLrr
- { 1476, 6, 2, 113, "tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1476 = tLSRri
- { 1477, 6, 2, 114, "tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1477 = tLSRrr
+ { 1471, 5, 1, 101, "tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1471 = tLDRspi
+ { 1472, 4, 1, 88, "tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1472 = tLEApcrel
+ { 1473, 5, 1, 88, "tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo152 }, // Inst #1473 = tLEApcrelJT
+ { 1474, 6, 2, 113, "tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1474 = tLSLri
+ { 1475, 6, 2, 114, "tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1475 = tLSLrr
+ { 1476, 6, 2, 113, "tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1476 = tLSRri
+ { 1477, 6, 2, 114, "tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1477 = tLSRrr
{ 1478, 5, 1, 93, "tMOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1478 = tMOVCCi
{ 1479, 5, 1, 94, "tMOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1479 = tMOVCCr
- { 1480, 5, 1, 128, "tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo148 }, // Inst #1480 = tMOVCCr_pseudo
- { 1481, 2, 1, 112, "tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo151 }, // Inst #1481 = tMOVSr
- { 1482, 2, 1, 112, "tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1482 = tMOVgpr2gpr
- { 1483, 2, 1, 112, "tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo152 }, // Inst #1483 = tMOVgpr2tgpr
- { 1484, 5, 2, 111, "tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo153 }, // Inst #1484 = tMOVi8
- { 1485, 2, 1, 112, "tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1485 = tMOVr
- { 1486, 2, 1, 112, "tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1486 = tMOVtgpr2gpr
- { 1487, 6, 2, 116, "tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1487 = tMUL
- { 1488, 5, 2, 112, "tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1488 = tMVN
- { 1489, 6, 2, 89, "tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1489 = tORR
- { 1490, 3, 1, 89, "tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1490 = tPICADD
- { 1491, 3, 0, 0, "tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo156 }, // Inst #1491 = tPOP
- { 1492, 3, 0, 0, "tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1492 = tPOP_RET
- { 1493, 3, 0, 0, "tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo156 }, // Inst #1493 = tPUSH
- { 1494, 4, 1, 125, "tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1494 = tREV
- { 1495, 4, 1, 125, "tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1495 = tREV16
- { 1496, 4, 1, 125, "tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1496 = tREVSH
- { 1497, 6, 2, 114, "tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1497 = tROR
- { 1498, 5, 2, 88, "tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1498 = tRSB
- { 1499, 5, 1, 101, "tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1499 = tRestore
- { 1500, 6, 2, 89, "tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo134 }, // Inst #1500 = tSBC
+ { 1480, 5, 1, 128, "tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo150 }, // Inst #1480 = tMOVCCr_pseudo
+ { 1481, 2, 1, 112, "tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo153 }, // Inst #1481 = tMOVSr
+ { 1482, 2, 1, 112, "tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo132 }, // Inst #1482 = tMOVgpr2gpr
+ { 1483, 2, 1, 112, "tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1483 = tMOVgpr2tgpr
+ { 1484, 5, 2, 111, "tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1484 = tMOVi8
+ { 1485, 2, 1, 112, "tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo153 }, // Inst #1485 = tMOVr
+ { 1486, 2, 1, 112, "tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1486 = tMOVtgpr2gpr
+ { 1487, 6, 2, 116, "tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1487 = tMUL
+ { 1488, 5, 2, 112, "tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1488 = tMVN
+ { 1489, 6, 2, 89, "tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1489 = tORR
+ { 1490, 3, 1, 89, "tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1490 = tPICADD
+ { 1491, 3, 0, 0, "tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, Barriers2, OperandInfo158 }, // Inst #1491 = tPOP
+ { 1492, 3, 0, 0, "tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1492 = tPOP_RET
+ { 1493, 3, 0, 0, "tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, Barriers2, OperandInfo158 }, // Inst #1493 = tPUSH
+ { 1494, 4, 1, 125, "tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1494 = tREV
+ { 1495, 4, 1, 125, "tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1495 = tREV16
+ { 1496, 4, 1, 125, "tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1496 = tREVSH
+ { 1497, 6, 2, 114, "tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1497 = tROR
+ { 1498, 5, 2, 88, "tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1498 = tRSB
+ { 1499, 5, 1, 101, "tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1499 = tRestore
+ { 1500, 6, 2, 89, "tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo136 }, // Inst #1500 = tSBC
{ 1501, 5, 0, 120, "tSTM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1501 = tSTM
- { 1502, 6, 0, 121, "tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1502 = tSTR
- { 1503, 6, 0, 121, "tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1503 = tSTRB
- { 1504, 6, 0, 121, "tSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1504 = tSTRH
- { 1505, 5, 0, 118, "tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1505 = tSTRspi
- { 1506, 6, 2, 88, "tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1506 = tSUBi3
- { 1507, 6, 2, 88, "tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1507 = tSUBi8
- { 1508, 6, 2, 89, "tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1508 = tSUBrr
- { 1509, 3, 1, 88, "tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1509 = tSUBspi
+ { 1502, 6, 0, 121, "tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1502 = tSTR
+ { 1503, 6, 0, 121, "tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1503 = tSTRB
+ { 1504, 6, 0, 121, "tSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1504 = tSTRH
+ { 1505, 5, 0, 118, "tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1505 = tSTRspi
+ { 1506, 6, 2, 88, "tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1506 = tSUBi3
+ { 1507, 6, 2, 88, "tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1507 = tSUBi8
+ { 1508, 6, 2, 89, "tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo142 }, // Inst #1508 = tSUBrr
+ { 1509, 3, 1, 88, "tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1509 = tSUBspi
{ 1510, 3, 1, 128, "tSUBspi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1510 = tSUBspi_
- { 1511, 4, 1, 125, "tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1511 = tSXTB
- { 1512, 4, 1, 125, "tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1512 = tSXTH
- { 1513, 5, 0, 118, "tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1513 = tSpill
+ { 1511, 4, 1, 125, "tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1511 = tSXTB
+ { 1512, 4, 1, 125, "tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1512 = tSXTH
+ { 1513, 5, 0, 118, "tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1513 = tSpill
{ 1514, 0, 0, 0, "tTPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList10, NULL, 0 }, // Inst #1514 = tTPsoft
- { 1515, 4, 0, 98, "tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1515 = tTST
- { 1516, 4, 1, 125, "tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1516 = tUXTB
- { 1517, 4, 1, 125, "tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1517 = tUXTH
+ { 1515, 4, 0, 98, "tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1515 = tTST
+ { 1516, 4, 1, 125, "tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1516 = tUXTB
+ { 1517, 4, 1, 125, "tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1517 = tUXTH
};
} // End llvm namespace
diff --git a/libclamav/c++/ARMGenInstrNames.inc b/libclamav/c++/ARMGenInstrNames.inc
index 7da3f63..2ab6a5a 100644
--- a/libclamav/c++/ARMGenInstrNames.inc
+++ b/libclamav/c++/ARMGenInstrNames.inc
@@ -1463,7 +1463,7 @@ namespace ARM {
tCBNZ = 1450,
tCBZ = 1451,
tCMN = 1452,
- tCMNZ = 1453,
+ tCMNz = 1453,
tCMPhir = 1454,
tCMPi8 = 1455,
tCMPr = 1456,
diff --git a/libclamav/c++/ARMGenRegisterInfo.h.inc b/libclamav/c++/ARMGenRegisterInfo.h.inc
index 1e26e88..3c40e2e 100644
--- a/libclamav/c++/ARMGenRegisterInfo.h.inc
+++ b/libclamav/c++/ARMGenRegisterInfo.h.inc
@@ -28,13 +28,14 @@ namespace ARM { // Register classes
DPR_8RegClassID = 3,
DPR_VFP2RegClassID = 4,
GPRRegClassID = 5,
- QPRRegClassID = 6,
- QPR_8RegClassID = 7,
- QPR_VFP2RegClassID = 8,
- SPRRegClassID = 9,
- SPR_8RegClassID = 10,
- SPR_INVALIDRegClassID = 11,
- tGPRRegClassID = 12
+ JustSPRegClassID = 6,
+ QPRRegClassID = 7,
+ QPR_8RegClassID = 8,
+ QPR_VFP2RegClassID = 9,
+ SPRRegClassID = 10,
+ SPR_8RegClassID = 11,
+ SPR_INVALIDRegClassID = 12,
+ tGPRRegClassID = 13
};
struct CCRClass : public TargetRegisterClass {
@@ -68,6 +69,13 @@ namespace ARM { // Register classes
};
extern GPRClass GPRRegClass;
static TargetRegisterClass * const GPRRegisterClass = &GPRRegClass;
+ struct JustSPClass : public TargetRegisterClass {
+ JustSPClass();
+
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern JustSPClass JustSPRegClass;
+ static TargetRegisterClass * const JustSPRegisterClass = &JustSPRegClass;
struct QPRClass : public TargetRegisterClass {
QPRClass();
};
diff --git a/libclamav/c++/ARMGenRegisterInfo.inc b/libclamav/c++/ARMGenRegisterInfo.inc
index c449225..8a52344 100644
--- a/libclamav/c++/ARMGenRegisterInfo.inc
+++ b/libclamav/c++/ARMGenRegisterInfo.inc
@@ -34,6 +34,11 @@ namespace { // Register classes...
ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R12, ARM::R11, ARM::LR, ARM::SP, ARM::PC,
};
+ // JustSP Register Class...
+ static const unsigned JustSP[] = {
+ ARM::SP,
+ };
+
// QPR Register Class...
static const unsigned QPR[] = {
ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15,
@@ -94,6 +99,11 @@ namespace { // Register classes...
MVT::i32, MVT::Other
};
+ // JustSPVTs Register Class Value Types...
+ static const EVT JustSPVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
// QPRVTs Register Class Value Types...
static const EVT QPRVTs[] = {
MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other
@@ -137,6 +147,7 @@ namespace ARM { // Register class instances
DPR_8Class DPR_8RegClass;
DPR_VFP2Class DPR_VFP2RegClass;
GPRClass GPRRegClass;
+ JustSPClass JustSPRegClass;
QPRClass QPRRegClass;
QPR_8Class QPR_8RegClass;
QPR_VFP2Class QPR_VFP2RegClass;
@@ -170,6 +181,11 @@ namespace ARM { // Register class instances
NULL
};
+ // JustSP Sub-register Classes...
+ static const TargetRegisterClass* const JustSPSubRegClasses[] = {
+ NULL
+ };
+
// QPR Sub-register Classes...
static const TargetRegisterClass* const QPRSubRegClasses[] = {
&ARM::SPR_INVALIDRegClass, &ARM::SPR_INVALIDRegClass, &ARM::SPR_INVALIDRegClass, &ARM::SPR_INVALIDRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, NULL
@@ -230,6 +246,11 @@ namespace ARM { // Register class instances
NULL
};
+ // JustSP Super-register Classes...
+ static const TargetRegisterClass* const JustSPSuperRegClasses[] = {
+ NULL
+ };
+
// QPR Super-register Classes...
static const TargetRegisterClass* const QPRSuperRegClasses[] = {
NULL
@@ -287,7 +308,12 @@ namespace ARM { // Register class instances
// GPR Register Class sub-classes...
static const TargetRegisterClass* const GPRSubclasses[] = {
- &ARM::tGPRRegClass, NULL
+ &ARM::JustSPRegClass, &ARM::tGPRRegClass, NULL
+ };
+
+ // JustSP Register Class sub-classes...
+ static const TargetRegisterClass* const JustSPSubclasses[] = {
+ NULL
};
// QPR Register Class sub-classes...
@@ -350,6 +376,11 @@ namespace ARM { // Register class instances
NULL
};
+ // JustSP Register Class super-classes...
+ static const TargetRegisterClass* const JustSPSuperclasses[] = {
+ &ARM::GPRRegClass, NULL
+ };
+
// QPR Register Class super-classes...
static const TargetRegisterClass* const QPRSuperclasses[] = {
NULL
@@ -527,6 +558,13 @@ DPR_VFP2Class::DPR_VFP2Class() : TargetRegisterClass(DPR_VFP2RegClassID, "DPR_V
GPRClass::GPRClass() : TargetRegisterClass(GPRRegClassID, "GPR", GPRVTs, GPRSubclasses, GPRSuperclasses, GPRSubRegClasses, GPRSuperRegClasses, 4, 4, 1, GPR, GPR + 16) {}
+ JustSPClass::iterator
+ JustSPClass::allocation_order_end(const MachineFunction &MF) const {
+ return allocation_order_begin(MF);
+ }
+
+JustSPClass::JustSPClass() : TargetRegisterClass(JustSPRegClassID, "JustSP", JustSPVTs, JustSPSubclasses, JustSPSuperclasses, JustSPSubRegClasses, JustSPSuperRegClasses, 4, 4, 1, JustSP, JustSP + 1) {}
+
QPRClass::QPRClass() : TargetRegisterClass(QPRRegClassID, "QPR", QPRVTs, QPRSubclasses, QPRSuperclasses, QPRSubRegClasses, QPRSuperRegClasses, 16, 16, 1, QPR, QPR + 16) {}
QPR_8Class::QPR_8Class() : TargetRegisterClass(QPR_8RegClassID, "QPR_8", QPR_8VTs, QPR_8Subclasses, QPR_8Superclasses, QPR_8SubRegClasses, QPR_8SuperRegClasses, 16, 16, 1, QPR_8, QPR_8 + 4) {}
@@ -570,6 +608,7 @@ namespace {
&ARM::DPR_8RegClass,
&ARM::DPR_VFP2RegClass,
&ARM::GPRRegClass,
+ &ARM::JustSPRegClass,
&ARM::QPRRegClass,
&ARM::QPR_8RegClass,
&ARM::QPR_VFP2RegClass,
@@ -3485,7 +3524,7 @@ unsigned ARMGenRegisterInfo::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) c
}
ARMGenRegisterInfo::ARMGenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)
- : TargetRegisterInfo(RegisterDescriptors, 100, RegisterClasses, RegisterClasses+12,
+ : TargetRegisterInfo(RegisterDescriptors, 100, RegisterClasses, RegisterClasses+13,
CallFrameSetupOpcode, CallFrameDestroyOpcode,
SubregHashTable, SubregHashTableSize,
SuperregHashTable, SuperregHashTableSize,
diff --git a/libclamav/c++/Makefile.in b/libclamav/c++/Makefile.in
index 0258c4b..5f6d029 100644
--- a/libclamav/c++/Makefile.in
+++ b/libclamav/c++/Makefile.in
@@ -295,9 +295,10 @@ am_libllvmjit_la_OBJECTS = AliasAnalysis.lo BasicAliasAnalysis.lo \
ConstantRange.lo Debug.lo Dwarf.lo ErrorHandling.lo \
FoldingSet.lo FormattedStream.lo GraphWriter.lo \
ManagedStatic.lo MemoryBuffer.lo PrettyStackTrace.lo \
- SmallPtrSet.lo SourceMgr.lo Statistic.lo StringExtras.lo \
- StringMap.lo StringPool.lo StringRef.lo TargetRegistry.lo \
- Timer.lo Triple.lo Twine.lo raw_ostream.lo SubtargetFeature.lo \
+ SmallPtrSet.lo SmallVector.lo SourceMgr.lo Statistic.lo \
+ StringExtras.lo StringMap.lo StringPool.lo StringRef.lo \
+ TargetRegistry.lo Timer.lo Triple.lo Twine.lo \
+ circular_raw_ostream.lo raw_ostream.lo SubtargetFeature.lo \
TargetData.lo TargetInstrInfo.lo TargetLoweringObjectFile.lo \
TargetMachine.lo TargetRegisterInfo.lo AsmWriter.lo \
Attributes.lo AutoUpgrade.lo BasicBlock.lo ConstantFold.lo \
@@ -351,11 +352,12 @@ am_libllvmsupport_la_OBJECTS = APFloat.lo APInt.lo APSInt.lo \
FoldingSet.lo FormattedStream.lo GraphWriter.lo IsInf.lo \
IsNAN.lo ManagedStatic.lo MemoryBuffer.lo MemoryObject.lo \
PluginLoader.lo PrettyStackTrace.lo Regex.lo \
- SlowOperationInformer.lo SmallPtrSet.lo SourceMgr.lo \
- Statistic.lo StringExtras.lo StringMap.lo StringPool.lo \
- StringRef.lo SystemUtils.lo TargetRegistry.lo Timer.lo \
- Triple.lo Twine.lo raw_os_ostream.lo raw_ostream.lo regcomp.lo \
- regerror.lo regexec.lo regfree.lo regstrlcpy.lo
+ SlowOperationInformer.lo SmallPtrSet.lo SmallVector.lo \
+ SourceMgr.lo Statistic.lo StringExtras.lo StringMap.lo \
+ StringPool.lo StringRef.lo SystemUtils.lo TargetRegistry.lo \
+ Timer.lo Triple.lo Twine.lo circular_raw_ostream.lo \
+ raw_os_ostream.lo raw_ostream.lo regcomp.lo regerror.lo \
+ regexec.lo regfree.lo regstrlcpy.lo
libllvmsupport_la_OBJECTS = $(am_libllvmsupport_la_OBJECTS)
libllvmsystem_la_DEPENDENCIES =
am_libllvmsystem_la_OBJECTS = Alarm.lo Atomic.lo Disassembler.lo \
@@ -530,7 +532,9 @@ am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
llvm/utils/TableGen/TGParser.cpp \
llvm/utils/TableGen/TGValueTypes.cpp \
llvm/utils/TableGen/TableGen.cpp \
- llvm/utils/TableGen/TableGenBackend.cpp
+ llvm/utils/TableGen/TableGenBackend.cpp \
+ llvm/utils/TableGen/X86DisassemblerTables.cpp \
+ llvm/utils/TableGen/X86RecognizableInstr.cpp
@MAINTAINER_MODE_TRUE at am_tblgen_OBJECTS = \
@MAINTAINER_MODE_TRUE@ tblgen-AsmMatcherEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-AsmWriterEmitter.$(OBJEXT) \
@@ -555,7 +559,9 @@ am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
@MAINTAINER_MODE_TRUE@ tblgen-TGParser.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-TGValueTypes.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-TableGen.$(OBJEXT) \
- at MAINTAINER_MODE_TRUE@ tblgen-TableGenBackend.$(OBJEXT)
+ at MAINTAINER_MODE_TRUE@ tblgen-TableGenBackend.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-X86DisassemblerTables.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-X86RecognizableInstr.$(OBJEXT)
tblgen_OBJECTS = $(am_tblgen_OBJECTS)
@MAINTAINER_MODE_TRUE at tblgen_DEPENDENCIES = libllvmsupport.la \
@MAINTAINER_MODE_TRUE@ libllvmsystem.la
@@ -874,6 +880,7 @@ libllvmsupport_la_SOURCES = \
llvm/lib/Support/Regex.cpp\
llvm/lib/Support/SlowOperationInformer.cpp\
llvm/lib/Support/SmallPtrSet.cpp\
+ llvm/lib/Support/SmallVector.cpp\
llvm/lib/Support/SourceMgr.cpp\
llvm/lib/Support/Statistic.cpp\
llvm/lib/Support/StringExtras.cpp\
@@ -885,6 +892,7 @@ libllvmsupport_la_SOURCES = \
llvm/lib/Support/Timer.cpp\
llvm/lib/Support/Triple.cpp\
llvm/lib/Support/Twine.cpp\
+ llvm/lib/Support/circular_raw_ostream.cpp\
llvm/lib/Support/raw_os_ostream.cpp\
llvm/lib/Support/raw_ostream.cpp\
llvm/lib/Support/regcomp.c\
@@ -921,7 +929,9 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TGParser.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TGValueTypes.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TableGen.cpp\
- at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TableGenBackend.cpp
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TableGenBackend.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/X86DisassemblerTables.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/X86RecognizableInstr.cpp
@MAINTAINER_MODE_TRUE at TBLGEN = $(top_builddir)/tblgen
@MAINTAINER_MODE_TRUE at TBLGEN_V = $(AM_V_GEN)$(TBLGEN)
@@ -1057,6 +1067,7 @@ libllvmjit_la_SOURCES = \
llvm/lib/Support/MemoryBuffer.cpp\
llvm/lib/Support/PrettyStackTrace.cpp\
llvm/lib/Support/SmallPtrSet.cpp\
+ llvm/lib/Support/SmallVector.cpp\
llvm/lib/Support/SourceMgr.cpp\
llvm/lib/Support/Statistic.cpp\
llvm/lib/Support/StringExtras.cpp\
@@ -1067,6 +1078,7 @@ libllvmjit_la_SOURCES = \
llvm/lib/Support/Timer.cpp\
llvm/lib/Support/Triple.cpp\
llvm/lib/Support/Twine.cpp\
+ llvm/lib/Support/circular_raw_ostream.cpp\
llvm/lib/Support/raw_ostream.cpp\
llvm/lib/Target/SubtargetFeature.cpp\
llvm/lib/Target/TargetData.cpp\
@@ -1776,6 +1788,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/SlotIndexes.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/SlowOperationInformer.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/SmallPtrSet.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/SmallVector.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/SourceMgr.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Spiller.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/StackProtector.Plo at am__quote@
@@ -1824,6 +1837,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Verifier.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/VirtRegMap.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/VirtRegRewriter.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/circular_raw_ostream.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/count-count.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libclamavcxx_la-bytecode2llvm.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libgoogletest_la-TestMain.Plo at am__quote@
@@ -1976,6 +1990,8 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-TGValueTypes.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-TableGen.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-TableGenBackend.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-X86DisassemblerTables.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-X86RecognizableInstr.Po at am__quote@
.c.o:
@am__fastdepCC_TRUE@ $(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
@@ -4017,6 +4033,14 @@ SmallPtrSet.lo: llvm/lib/Support/SmallPtrSet.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o SmallPtrSet.lo `test -f 'llvm/lib/Support/SmallPtrSet.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SmallPtrSet.cpp
+SmallVector.lo: llvm/lib/Support/SmallVector.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT SmallVector.lo -MD -MP -MF $(DEPDIR)/SmallVector.Tpo -c -o SmallVector.lo `test -f 'llvm/lib/Support/SmallVector.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SmallVector.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/SmallVector.Tpo $(DEPDIR)/SmallVector.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/SmallVector.cpp' object='SmallVector.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o SmallVector.lo `test -f 'llvm/lib/Support/SmallVector.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SmallVector.cpp
+
SourceMgr.lo: llvm/lib/Support/SourceMgr.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT SourceMgr.lo -MD -MP -MF $(DEPDIR)/SourceMgr.Tpo -c -o SourceMgr.lo `test -f 'llvm/lib/Support/SourceMgr.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SourceMgr.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/SourceMgr.Tpo $(DEPDIR)/SourceMgr.Plo
@@ -4097,6 +4121,14 @@ Twine.lo: llvm/lib/Support/Twine.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o Twine.lo `test -f 'llvm/lib/Support/Twine.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Twine.cpp
+circular_raw_ostream.lo: llvm/lib/Support/circular_raw_ostream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT circular_raw_ostream.lo -MD -MP -MF $(DEPDIR)/circular_raw_ostream.Tpo -c -o circular_raw_ostream.lo `test -f 'llvm/lib/Support/circular_raw_ostream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/circular_raw_ostream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/circular_raw_ostream.Tpo $(DEPDIR)/circular_raw_ostream.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/circular_raw_ostream.cpp' object='circular_raw_ostream.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o circular_raw_ostream.lo `test -f 'llvm/lib/Support/circular_raw_ostream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/circular_raw_ostream.cpp
+
raw_ostream.lo: llvm/lib/Support/raw_ostream.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT raw_ostream.lo -MD -MP -MF $(DEPDIR)/raw_ostream.Tpo -c -o raw_ostream.lo `test -f 'llvm/lib/Support/raw_ostream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/raw_ostream.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/raw_ostream.Tpo $(DEPDIR)/raw_ostream.Plo
@@ -5897,6 +5929,38 @@ tblgen-TableGenBackend.obj: llvm/utils/TableGen/TableGenBackend.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-TableGenBackend.obj `if test -f 'llvm/utils/TableGen/TableGenBackend.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/TableGenBackend.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/TableGenBackend.cpp'; fi`
+tblgen-X86DisassemblerTables.o: llvm/utils/TableGen/X86DisassemblerTables.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-X86DisassemblerTables.o -MD -MP -MF $(DEPDIR)/tblgen-X86DisassemblerTables.Tpo -c -o tblgen-X86DisassemblerTables.o `test -f 'llvm/utils/TableGen/X86DisassemblerTables.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/X86DisassemblerTables.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-X86DisassemblerTables.Tpo $(DEPDIR)/tblgen-X86DisassemblerTables.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/X86DisassemblerTables.cpp' object='tblgen-X86DisassemblerTables.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-X86DisassemblerTables.o `test -f 'llvm/utils/TableGen/X86DisassemblerTables.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/X86DisassemblerTables.cpp
+
+tblgen-X86DisassemblerTables.obj: llvm/utils/TableGen/X86DisassemblerTables.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-X86DisassemblerTables.obj -MD -MP -MF $(DEPDIR)/tblgen-X86DisassemblerTables.Tpo -c -o tblgen-X86DisassemblerTables.obj `if test -f 'llvm/utils/TableGen/X86DisassemblerTables.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/X86DisassemblerTables.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/X86DisassemblerTables.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-X86DisassemblerTables.Tpo $(DEPDIR)/tblgen-X86DisassemblerTables.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/X86DisassemblerTables.cpp' object='tblgen-X86DisassemblerTables.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-X86DisassemblerTables.obj `if test -f 'llvm/utils/TableGen/X86DisassemblerTables.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/X86DisassemblerTables.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/X86DisassemblerTables.cpp'; fi`
+
+tblgen-X86RecognizableInstr.o: llvm/utils/TableGen/X86RecognizableInstr.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-X86RecognizableInstr.o -MD -MP -MF $(DEPDIR)/tblgen-X86RecognizableInstr.Tpo -c -o tblgen-X86RecognizableInstr.o `test -f 'llvm/utils/TableGen/X86RecognizableInstr.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/X86RecognizableInstr.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-X86RecognizableInstr.Tpo $(DEPDIR)/tblgen-X86RecognizableInstr.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/X86RecognizableInstr.cpp' object='tblgen-X86RecognizableInstr.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-X86RecognizableInstr.o `test -f 'llvm/utils/TableGen/X86RecognizableInstr.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/X86RecognizableInstr.cpp
+
+tblgen-X86RecognizableInstr.obj: llvm/utils/TableGen/X86RecognizableInstr.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-X86RecognizableInstr.obj -MD -MP -MF $(DEPDIR)/tblgen-X86RecognizableInstr.Tpo -c -o tblgen-X86RecognizableInstr.obj `if test -f 'llvm/utils/TableGen/X86RecognizableInstr.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/X86RecognizableInstr.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/X86RecognizableInstr.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-X86RecognizableInstr.Tpo $(DEPDIR)/tblgen-X86RecognizableInstr.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/X86RecognizableInstr.cpp' object='tblgen-X86RecognizableInstr.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-X86RecognizableInstr.obj `if test -f 'llvm/utils/TableGen/X86RecognizableInstr.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/X86RecognizableInstr.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/X86RecognizableInstr.cpp'; fi`
+
.cpp.o:
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
diff --git a/libclamav/c++/PPCGenAsmWriter.inc b/libclamav/c++/PPCGenAsmWriter.inc
index 7dab0d0..c3c2d2d 100644
--- a/libclamav/c++/PPCGenAsmWriter.inc
+++ b/libclamav/c++/PPCGenAsmWriter.inc
@@ -189,345 +189,347 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
1573430U, // LDARX
2097725U, // LDU
1573442U, // LDX
+ 167772743U, // LDinto_toc
2359858U, // LDtoc
- 1049159U, // LFD
- 1311303U, // LFDU
- 1573452U, // LFDX
- 1049170U, // LFS
- 1311314U, // LFSU
- 1573463U, // LFSX
- 1049181U, // LHA
- 1049181U, // LHA8
- 1311330U, // LHAU
- 885346U, // LHAU8
- 1573480U, // LHAX
- 1573480U, // LHAX8
- 1573486U, // LHBRX
- 1049205U, // LHZ
- 1049205U, // LHZ8
- 1311354U, // LHZU
- 1311354U, // LHZU8
- 1573504U, // LHZX
- 1573504U, // LHZX8
- 2622086U, // LI
- 2622086U, // LI8
- 2884234U, // LIS
- 2884234U, // LIS8
- 1573519U, // LVEBX
- 1573526U, // LVEHX
- 1573533U, // LVEWX
- 1573540U, // LVSL
- 1573546U, // LVSR
- 1573552U, // LVX
- 1573557U, // LVXL
- 1835707U, // LWA
- 1573568U, // LWARX
- 1573575U, // LWAX
- 1573581U, // LWBRX
- 1049300U, // LWZ
- 1049300U, // LWZ8
- 1311449U, // LWZU
- 1311449U, // LWZU8
- 1573599U, // LWZX
- 1573599U, // LWZX8
- 33509U, // MCRF
- 150995691U, // MFCR
- 150995697U, // MFCTR
- 150995697U, // MFCTR8
- 150995704U, // MFFS
- 150995710U, // MFLR
- 150995710U, // MFLR8
- 3146475U, // MFOCRF
- 167772932U, // MFVRSAVE
- 150995723U, // MFVSCR
- 2684355347U, // MTCRF
- 150995738U, // MTCTR
- 150995738U, // MTCTR8
- 2952790817U, // MTFSB0
- 2952790825U, // MTFSB1
- 3393192753U, // MTFSF
- 150995768U, // MTLR
- 150995768U, // MTLR8
- 150995774U, // MTVRSAVE
- 150995786U, // MTVSCR
- 850U, // MULHD
- 857U, // MULHDU
- 865U, // MULHW
- 872U, // MULHWU
- 880U, // MULLD
- 4983U, // MULLI
- 894U, // MULLW
+ 1073742416U, // LDtoc_restore
+ 1049180U, // LFD
+ 1311324U, // LFDU
+ 1573473U, // LFDX
+ 1049191U, // LFS
+ 1311335U, // LFSU
+ 1573484U, // LFSX
+ 1049202U, // LHA
+ 1049202U, // LHA8
+ 1311351U, // LHAU
+ 885367U, // LHAU8
+ 1573501U, // LHAX
+ 1573501U, // LHAX8
+ 1573507U, // LHBRX
+ 1049226U, // LHZ
+ 1049226U, // LHZ8
+ 1311375U, // LHZU
+ 1311375U, // LHZU8
+ 1573525U, // LHZX
+ 1573525U, // LHZX8
+ 2622107U, // LI
+ 2622107U, // LI8
+ 2884255U, // LIS
+ 2884255U, // LIS8
+ 1573540U, // LVEBX
+ 1573547U, // LVEHX
+ 1573554U, // LVEWX
+ 1573561U, // LVSL
+ 1573567U, // LVSR
+ 1573573U, // LVX
+ 1573578U, // LVXL
+ 1835728U, // LWA
+ 1573589U, // LWARX
+ 1573596U, // LWAX
+ 1573602U, // LWBRX
+ 1049321U, // LWZ
+ 1049321U, // LWZ8
+ 1311470U, // LWZU
+ 1311470U, // LWZU8
+ 1573620U, // LWZX
+ 1573620U, // LWZX8
+ 33530U, // MCRF
+ 150995712U, // MFCR
+ 150995718U, // MFCTR
+ 150995718U, // MFCTR8
+ 150995725U, // MFFS
+ 150995731U, // MFLR
+ 150995731U, // MFLR8
+ 3146496U, // MFOCRF
+ 171967257U, // MFVRSAVE
+ 150995744U, // MFVSCR
+ 2684355368U, // MTCRF
+ 150995759U, // MTCTR
+ 150995759U, // MTCTR8
+ 2952790838U, // MTFSB0
+ 2952790846U, // MTFSB1
+ 3397387078U, // MTFSF
+ 150995789U, // MTLR
+ 150995789U, // MTLR8
+ 150995795U, // MTVRSAVE
+ 150995807U, // MTVSCR
+ 871U, // MULHD
+ 878U, // MULHDU
+ 886U, // MULHW
+ 893U, // MULHWU
+ 901U, // MULLD
+ 5004U, // MULLI
+ 915U, // MULLW
3489661036U, // MovePCtoLR
3489661036U, // MovePCtoLR8
- 901U, // NAND
- 901U, // NAND8
- 33675U, // NEG
- 33675U, // NEG8
- 1073742736U, // NOP
- 916U, // NOR
- 916U, // NOR8
- 921U, // OR
- 921U, // OR4To8
- 921U, // OR8
- 921U, // OR8To4
- 925U, // ORC
- 925U, // ORC8
- 13218U, // ORI
- 13218U, // ORI8
- 13223U, // ORIS
- 13223U, // ORIS8
- 941U, // RLDCL
- 17332U, // RLDICL
- 17340U, // RLDICR
- 3539908U, // RLDIMI
- 3572684U, // RLWIMI
- 21460U, // RLWINM
- 21468U, // RLWINMo
- 997U, // RLWNM
- 444596289U, // SELECT_CC_F4
- 444596289U, // SELECT_CC_F8
- 444596289U, // SELECT_CC_I4
- 444596289U, // SELECT_CC_I8
- 444596289U, // SELECT_CC_VRRC
- 1004U, // SLD
- 1009U, // SLW
- 448790593U, // SPILL_CR
- 1014U, // SRAD
- 17404U, // SRADI
- 1027U, // SRAW
- 21513U, // SRAWI
- 1040U, // SRD
- 1045U, // SRW
- 1049626U, // STB
- 1049626U, // STB8
- 3405775903U, // STBU
- 3405775903U, // STBU8
- 1573925U, // STBX
- 1573925U, // STBX8
- 1836075U, // STD
- 1573936U, // STDCX
- 3409970232U, // STDU
- 1573950U, // STDUX
- 1573957U, // STDX
- 1573957U, // STDX_32
- 1836075U, // STD_32
- 1049675U, // STFD
- 3405775953U, // STFDU
- 1573976U, // STFDX
- 1573983U, // STFIWX
- 1049703U, // STFS
- 3405775981U, // STFSU
- 1574004U, // STFSX
- 1049723U, // STH
- 1049723U, // STH8
- 1574016U, // STHBRX
- 3405776008U, // STHU
- 3405776008U, // STHU8
- 1574030U, // STHX
- 1574030U, // STHX8
- 1574036U, // STVEBX
- 1574044U, // STVEHX
- 1574052U, // STVEWX
- 1574060U, // STVX
- 1574066U, // STVXL
- 1049785U, // STW
- 1049785U, // STW8
- 1574078U, // STWBRX
- 1574086U, // STWCX
- 3405776078U, // STWU
- 3405776078U, // STWU8
- 1236U, // STWUX
- 1574107U, // STWX
- 1574107U, // STWX8
- 1249U, // SUBF
- 1249U, // SUBF8
- 1255U, // SUBFC
- 1255U, // SUBFC8
- 1262U, // SUBFE
- 1262U, // SUBFE8
- 5365U, // SUBFIC
- 5365U, // SUBFIC8
- 34045U, // SUBFME
- 34045U, // SUBFME8
- 34053U, // SUBFZE
- 34053U, // SUBFZE8
- 1073743117U, // SYNC
+ 922U, // NAND
+ 922U, // NAND8
+ 33696U, // NEG
+ 33696U, // NEG8
+ 1073742757U, // NOP
+ 937U, // NOR
+ 937U, // NOR8
+ 942U, // OR
+ 942U, // OR4To8
+ 942U, // OR8
+ 942U, // OR8To4
+ 946U, // ORC
+ 946U, // ORC8
+ 13239U, // ORI
+ 13239U, // ORI8
+ 13244U, // ORIS
+ 13244U, // ORIS8
+ 962U, // RLDCL
+ 17353U, // RLDICL
+ 17361U, // RLDICR
+ 3539929U, // RLDIMI
+ 3572705U, // RLWIMI
+ 21481U, // RLWINM
+ 21489U, // RLWINMo
+ 1018U, // RLWNM
+ 448790593U, // SELECT_CC_F4
+ 448790593U, // SELECT_CC_F8
+ 448790593U, // SELECT_CC_I4
+ 448790593U, // SELECT_CC_I8
+ 448790593U, // SELECT_CC_VRRC
+ 1025U, // SLD
+ 1030U, // SLW
+ 452984897U, // SPILL_CR
+ 1035U, // SRAD
+ 17425U, // SRADI
+ 1048U, // SRAW
+ 21534U, // SRAWI
+ 1061U, // SRD
+ 1066U, // SRW
+ 1049647U, // STB
+ 1049647U, // STB8
+ 3409970228U, // STBU
+ 3409970228U, // STBU8
+ 1573946U, // STBX
+ 1573946U, // STBX8
+ 1836096U, // STD
+ 1573957U, // STDCX
+ 3414164557U, // STDU
+ 1573971U, // STDUX
+ 1573978U, // STDX
+ 1573978U, // STDX_32
+ 1836096U, // STD_32
+ 1049696U, // STFD
+ 3409970278U, // STFDU
+ 1573997U, // STFDX
+ 1574004U, // STFIWX
+ 1049724U, // STFS
+ 3409970306U, // STFSU
+ 1574025U, // STFSX
+ 1049744U, // STH
+ 1049744U, // STH8
+ 1574037U, // STHBRX
+ 3409970333U, // STHU
+ 3409970333U, // STHU8
+ 1574051U, // STHX
+ 1574051U, // STHX8
+ 1574057U, // STVEBX
+ 1574065U, // STVEHX
+ 1574073U, // STVEWX
+ 1574081U, // STVX
+ 1574087U, // STVXL
+ 1049806U, // STW
+ 1049806U, // STW8
+ 1574099U, // STWBRX
+ 1574107U, // STWCX
+ 3409970403U, // STWU
+ 3409970403U, // STWU8
+ 1257U, // STWUX
+ 1574128U, // STWX
+ 1574128U, // STWX8
+ 1270U, // SUBF
+ 1270U, // SUBF8
+ 1276U, // SUBFC
+ 1276U, // SUBFC8
+ 1283U, // SUBFE
+ 1283U, // SUBFE8
+ 5386U, // SUBFIC
+ 5386U, // SUBFIC8
+ 34066U, // SUBFME
+ 34066U, // SUBFME8
+ 34074U, // SUBFZE
+ 34074U, // SUBFZE8
+ 1073743138U, // SYNC
1493172316U, // TAILB
1493172316U, // TAILB8
- 1761608978U, // TAILBA
- 1761608978U, // TAILBA8
+ 1761608999U, // TAILBA
+ 1761608999U, // TAILBA8
1073741921U, // TAILBCTR
1073741921U, // TAILBCTR8
- 1757447446U, // TCRETURNai
- 1757447459U, // TCRETURNai8
- 1489012017U, // TCRETURNdi
- 1489012030U, // TCRETURNdi8
- 146834764U, // TCRETURNri
- 146834777U, // TCRETURNri8
- 1073743207U, // TRAP
- 34156U, // UPDATE_VRSAVE
- 1403U, // VADDCUW
- 1412U, // VADDFP
- 1420U, // VADDSBS
- 1429U, // VADDSHS
- 1438U, // VADDSWS
- 1447U, // VADDUBM
- 1456U, // VADDUBS
- 1465U, // VADDUHM
- 1474U, // VADDUHS
- 1483U, // VADDUWM
- 1492U, // VADDUWS
- 1501U, // VAND
- 1507U, // VANDC
- 1514U, // VAVGSB
- 1522U, // VAVGSH
- 1530U, // VAVGSW
- 1538U, // VAVGUB
- 1546U, // VAVGUH
- 1554U, // VAVGUW
- 3606042U, // VCFSX
- 3606049U, // VCFUX
- 1576U, // VCMPBFP
- 1585U, // VCMPBFPo
- 1595U, // VCMPEQFP
- 1605U, // VCMPEQFPo
- 1616U, // VCMPEQUB
- 1626U, // VCMPEQUBo
- 1637U, // VCMPEQUH
- 1647U, // VCMPEQUHo
- 1658U, // VCMPEQUW
- 1668U, // VCMPEQUWo
- 1679U, // VCMPGEFP
- 1689U, // VCMPGEFPo
- 1700U, // VCMPGTFP
- 1710U, // VCMPGTFPo
- 1721U, // VCMPGTSB
- 1731U, // VCMPGTSBo
- 1742U, // VCMPGTSH
- 1752U, // VCMPGTSHo
- 1763U, // VCMPGTSW
- 1773U, // VCMPGTSWo
- 1784U, // VCMPGTUB
- 1794U, // VCMPGTUBo
- 1805U, // VCMPGTUH
- 1815U, // VCMPGTUHo
- 1826U, // VCMPGTUW
- 1836U, // VCMPGTUWo
- 3606327U, // VCTSXS
- 3606335U, // VCTUXS
- 34631U, // VEXPTEFP
- 34641U, // VLOGEFP
- 1882U, // VMADDFP
- 1891U, // VMAXFP
- 1899U, // VMAXSB
- 1907U, // VMAXSH
- 1915U, // VMAXSW
- 1923U, // VMAXUB
- 1931U, // VMAXUH
- 1939U, // VMAXUW
- 1947U, // VMHADDSHS
- 1958U, // VMHRADDSHS
- 1970U, // VMINFP
- 1978U, // VMINSB
- 1986U, // VMINSH
- 1994U, // VMINSW
- 2002U, // VMINUB
- 2010U, // VMINUH
- 2018U, // VMINUW
- 2026U, // VMLADDUHM
- 2037U, // VMRGHB
- 2045U, // VMRGHH
- 2053U, // VMRGHW
- 2061U, // VMRGLB
- 2069U, // VMRGLH
- 2077U, // VMRGLW
- 2085U, // VMSUMMBM
- 2095U, // VMSUMSHM
- 2105U, // VMSUMSHS
- 2115U, // VMSUMUBM
- 2125U, // VMSUMUHM
- 2135U, // VMSUMUHS
- 2145U, // VMULESB
- 2154U, // VMULESH
- 2163U, // VMULEUB
- 2172U, // VMULEUH
- 2181U, // VMULOSB
- 2190U, // VMULOSH
- 2199U, // VMULOUB
- 2208U, // VMULOUH
- 2217U, // VNMSUBFP
- 2227U, // VNOR
- 2233U, // VOR
- 2238U, // VPERM
- 2245U, // VPKPX
- 2252U, // VPKSHSS
- 2261U, // VPKSHUS
- 2270U, // VPKSWSS
- 2279U, // VPKSWUS
- 2288U, // VPKUHUM
- 2297U, // VPKUHUS
- 2306U, // VPKUWUM
- 2315U, // VPKUWUS
- 35092U, // VREFP
- 35099U, // VRFIM
- 35106U, // VRFIN
- 35113U, // VRFIP
- 35120U, // VRFIZ
- 2359U, // VRLB
- 2365U, // VRLH
- 2371U, // VRLW
- 35145U, // VRSQRTEFP
- 2388U, // VSEL
- 2394U, // VSL
- 2399U, // VSLB
- 2405U, // VSLDOI
- 2413U, // VSLH
- 2419U, // VSLO
- 2425U, // VSLW
- 3606911U, // VSPLTB
- 3606919U, // VSPLTH
- 3672463U, // VSPLTISB
- 3672473U, // VSPLTISH
- 3672483U, // VSPLTISW
- 3606957U, // VSPLTW
- 2485U, // VSR
- 2490U, // VSRAB
- 2497U, // VSRAH
- 2504U, // VSRAW
- 2511U, // VSRB
- 2517U, // VSRH
- 2523U, // VSRO
- 2529U, // VSRW
- 2535U, // VSUBCUW
- 2544U, // VSUBFP
- 2552U, // VSUBSBS
- 2561U, // VSUBSHS
- 2570U, // VSUBSWS
- 2579U, // VSUBUBM
- 2588U, // VSUBUBS
- 2597U, // VSUBUHM
- 2606U, // VSUBUHS
- 2615U, // VSUBUWM
- 2624U, // VSUBUWS
- 2633U, // VSUM2SWS
- 2643U, // VSUM4SBS
- 2653U, // VSUM4SHS
- 2663U, // VSUM4UBS
- 2673U, // VSUMSWS
- 35450U, // VUPKHPX
- 35459U, // VUPKHSB
- 35468U, // VUPKHSH
- 35477U, // VUPKLPX
- 35486U, // VUPKLSB
- 35495U, // VUPKLSH
- 2736U, // VXOR
- 527024U, // V_SET0
- 2742U, // XOR
- 2742U, // XOR8
- 15035U, // XORI
- 15035U, // XORI8
- 15041U, // XORIS
- 15041U, // XORIS8
+ 1757447467U, // TCRETURNai
+ 1757447480U, // TCRETURNai8
+ 1489012038U, // TCRETURNdi
+ 1489012051U, // TCRETURNdi8
+ 146834785U, // TCRETURNri
+ 146834798U, // TCRETURNri8
+ 1073743228U, // TRAP
+ 34177U, // UPDATE_VRSAVE
+ 1424U, // VADDCUW
+ 1433U, // VADDFP
+ 1441U, // VADDSBS
+ 1450U, // VADDSHS
+ 1459U, // VADDSWS
+ 1468U, // VADDUBM
+ 1477U, // VADDUBS
+ 1486U, // VADDUHM
+ 1495U, // VADDUHS
+ 1504U, // VADDUWM
+ 1513U, // VADDUWS
+ 1522U, // VAND
+ 1528U, // VANDC
+ 1535U, // VAVGSB
+ 1543U, // VAVGSH
+ 1551U, // VAVGSW
+ 1559U, // VAVGUB
+ 1567U, // VAVGUH
+ 1575U, // VAVGUW
+ 3606063U, // VCFSX
+ 3606070U, // VCFUX
+ 1597U, // VCMPBFP
+ 1606U, // VCMPBFPo
+ 1616U, // VCMPEQFP
+ 1626U, // VCMPEQFPo
+ 1637U, // VCMPEQUB
+ 1647U, // VCMPEQUBo
+ 1658U, // VCMPEQUH
+ 1668U, // VCMPEQUHo
+ 1679U, // VCMPEQUW
+ 1689U, // VCMPEQUWo
+ 1700U, // VCMPGEFP
+ 1710U, // VCMPGEFPo
+ 1721U, // VCMPGTFP
+ 1731U, // VCMPGTFPo
+ 1742U, // VCMPGTSB
+ 1752U, // VCMPGTSBo
+ 1763U, // VCMPGTSH
+ 1773U, // VCMPGTSHo
+ 1784U, // VCMPGTSW
+ 1794U, // VCMPGTSWo
+ 1805U, // VCMPGTUB
+ 1815U, // VCMPGTUBo
+ 1826U, // VCMPGTUH
+ 1836U, // VCMPGTUHo
+ 1847U, // VCMPGTUW
+ 1857U, // VCMPGTUWo
+ 3606348U, // VCTSXS
+ 3606356U, // VCTUXS
+ 34652U, // VEXPTEFP
+ 34662U, // VLOGEFP
+ 1903U, // VMADDFP
+ 1912U, // VMAXFP
+ 1920U, // VMAXSB
+ 1928U, // VMAXSH
+ 1936U, // VMAXSW
+ 1944U, // VMAXUB
+ 1952U, // VMAXUH
+ 1960U, // VMAXUW
+ 1968U, // VMHADDSHS
+ 1979U, // VMHRADDSHS
+ 1991U, // VMINFP
+ 1999U, // VMINSB
+ 2007U, // VMINSH
+ 2015U, // VMINSW
+ 2023U, // VMINUB
+ 2031U, // VMINUH
+ 2039U, // VMINUW
+ 2047U, // VMLADDUHM
+ 2058U, // VMRGHB
+ 2066U, // VMRGHH
+ 2074U, // VMRGHW
+ 2082U, // VMRGLB
+ 2090U, // VMRGLH
+ 2098U, // VMRGLW
+ 2106U, // VMSUMMBM
+ 2116U, // VMSUMSHM
+ 2126U, // VMSUMSHS
+ 2136U, // VMSUMUBM
+ 2146U, // VMSUMUHM
+ 2156U, // VMSUMUHS
+ 2166U, // VMULESB
+ 2175U, // VMULESH
+ 2184U, // VMULEUB
+ 2193U, // VMULEUH
+ 2202U, // VMULOSB
+ 2211U, // VMULOSH
+ 2220U, // VMULOUB
+ 2229U, // VMULOUH
+ 2238U, // VNMSUBFP
+ 2248U, // VNOR
+ 2254U, // VOR
+ 2259U, // VPERM
+ 2266U, // VPKPX
+ 2273U, // VPKSHSS
+ 2282U, // VPKSHUS
+ 2291U, // VPKSWSS
+ 2300U, // VPKSWUS
+ 2309U, // VPKUHUM
+ 2318U, // VPKUHUS
+ 2327U, // VPKUWUM
+ 2336U, // VPKUWUS
+ 35113U, // VREFP
+ 35120U, // VRFIM
+ 35127U, // VRFIN
+ 35134U, // VRFIP
+ 35141U, // VRFIZ
+ 2380U, // VRLB
+ 2386U, // VRLH
+ 2392U, // VRLW
+ 35166U, // VRSQRTEFP
+ 2409U, // VSEL
+ 2415U, // VSL
+ 2420U, // VSLB
+ 2426U, // VSLDOI
+ 2434U, // VSLH
+ 2440U, // VSLO
+ 2446U, // VSLW
+ 3606932U, // VSPLTB
+ 3606940U, // VSPLTH
+ 3672484U, // VSPLTISB
+ 3672494U, // VSPLTISH
+ 3672504U, // VSPLTISW
+ 3606978U, // VSPLTW
+ 2506U, // VSR
+ 2511U, // VSRAB
+ 2518U, // VSRAH
+ 2525U, // VSRAW
+ 2532U, // VSRB
+ 2538U, // VSRH
+ 2544U, // VSRO
+ 2550U, // VSRW
+ 2556U, // VSUBCUW
+ 2565U, // VSUBFP
+ 2573U, // VSUBSBS
+ 2582U, // VSUBSHS
+ 2591U, // VSUBSWS
+ 2600U, // VSUBUBM
+ 2609U, // VSUBUBS
+ 2618U, // VSUBUHM
+ 2627U, // VSUBUHS
+ 2636U, // VSUBUWM
+ 2645U, // VSUBUWS
+ 2654U, // VSUM2SWS
+ 2664U, // VSUM4SBS
+ 2674U, // VSUM4SHS
+ 2684U, // VSUM4UBS
+ 2694U, // VSUMSWS
+ 35471U, // VUPKHPX
+ 35480U, // VUPKHSB
+ 35489U, // VUPKHSH
+ 35498U, // VUPKLPX
+ 35507U, // VUPKLSB
+ 35516U, // VUPKLSH
+ 2757U, // VXOR
+ 527045U, // V_SET0
+ 2763U, // XOR
+ 2763U, // XOR8
+ 15056U, // XORI
+ 15056U, // XORI8
+ 15062U, // XORIS
+ 15062U, // XORIS8
0U
};
@@ -543,49 +545,50 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
"fdiv \000fdivs \000fmadd \000fmadds \000fmr \000fmsub \000fmsubs \000fm"
"ul \000fmuls \000fnabs \000fneg \000fnmadd \000fnmadds \000fnmsub \000f"
"nmsubs \000frsp \000fsel \000fsqrt \000fsqrts \000fsub \000fsubs \000la"
- " \000lbz \000lbzu \000lbzx \000ld \000ldarx \000ldu \000ldx \000lfd \000"
- "lfdx \000lfs \000lfsx \000lha \000lhau \000lhax \000lhbrx \000lhz \000l"
- "hzu \000lhzx \000li \000lis \000lvebx \000lvehx \000lvewx \000lvsl \000"
- "lvsr \000lvx \000lvxl \000lwa \000lwarx \000lwax \000lwbrx \000lwz \000"
- "lwzu \000lwzx \000mcrf \000mfcr \000mfctr \000mffs \000mflr \000mfspr \000"
- "mfvscr \000mtcrf \000mtctr \000mtfsb0 \000mtfsb1 \000mtfsf \000mtlr \000"
- "mtspr 256, \000mtvscr \000mulhd \000mulhdu \000mulhw \000mulhwu \000mul"
- "ld \000mulli \000mullw \000nand \000neg \000nop\000nor \000or \000orc \000"
- "ori \000oris \000rldcl \000rldicl \000rldicr \000rldimi \000rlwimi \000"
- "rlwinm \000rlwinm. \000rlwnm \000sld \000slw \000srad \000sradi \000sra"
- "w \000srawi \000srd \000srw \000stb \000stbu \000stbx \000std \000stdcx"
- ". \000stdu \000stdux \000stdx \000stfd \000stfdu \000stfdx \000stfiwx \000"
- "stfs \000stfsu \000stfsx \000sth \000sthbrx \000sthu \000sthx \000stveb"
- "x \000stvehx \000stvewx \000stvx \000stvxl \000stw \000stwbrx \000stwcx"
- ". \000stwu \000stwux \000stwx \000subf \000subfc \000subfe \000subfic \000"
- "subfme \000subfze \000sync\000ba \000#TC_RETURNa \000#TC_RETURNa8 \000#"
- "TC_RETURNd \000#TC_RETURNd8 \000#TC_RETURNr \000#TC_RETURNr8 \000trap\000"
- "UPDATE_VRSAVE \000vaddcuw \000vaddfp \000vaddsbs \000vaddshs \000vaddsw"
- "s \000vaddubm \000vaddubs \000vadduhm \000vadduhs \000vadduwm \000vaddu"
- "ws \000vand \000vandc \000vavgsb \000vavgsh \000vavgsw \000vavgub \000v"
- "avguh \000vavguw \000vcfsx \000vcfux \000vcmpbfp \000vcmpbfp. \000vcmpe"
- "qfp \000vcmpeqfp. \000vcmpequb \000vcmpequb. \000vcmpequh \000vcmpequh."
- " \000vcmpequw \000vcmpequw. \000vcmpgefp \000vcmpgefp. \000vcmpgtfp \000"
- "vcmpgtfp. \000vcmpgtsb \000vcmpgtsb. \000vcmpgtsh \000vcmpgtsh. \000vcm"
- "pgtsw \000vcmpgtsw. \000vcmpgtub \000vcmpgtub. \000vcmpgtuh \000vcmpgtu"
- "h. \000vcmpgtuw \000vcmpgtuw. \000vctsxs \000vctuxs \000vexptefp \000vl"
- "ogefp \000vmaddfp \000vmaxfp \000vmaxsb \000vmaxsh \000vmaxsw \000vmaxu"
- "b \000vmaxuh \000vmaxuw \000vmhaddshs \000vmhraddshs \000vminfp \000vmi"
- "nsb \000vminsh \000vminsw \000vminub \000vminuh \000vminuw \000vmladduh"
- "m \000vmrghb \000vmrghh \000vmrghw \000vmrglb \000vmrglh \000vmrglw \000"
- "vmsummbm \000vmsumshm \000vmsumshs \000vmsumubm \000vmsumuhm \000vmsumu"
- "hs \000vmulesb \000vmulesh \000vmuleub \000vmuleuh \000vmulosb \000vmul"
- "osh \000vmuloub \000vmulouh \000vnmsubfp \000vnor \000vor \000vperm \000"
- "vpkpx \000vpkshss \000vpkshus \000vpkswss \000vpkswus \000vpkuhum \000v"
- "pkuhus \000vpkuwum \000vpkuwus \000vrefp \000vrfim \000vrfin \000vrfip "
- "\000vrfiz \000vrlb \000vrlh \000vrlw \000vrsqrtefp \000vsel \000vsl \000"
- "vslb \000vsldoi \000vslh \000vslo \000vslw \000vspltb \000vsplth \000vs"
- "pltisb \000vspltish \000vspltisw \000vspltw \000vsr \000vsrab \000vsrah"
- " \000vsraw \000vsrb \000vsrh \000vsro \000vsrw \000vsubcuw \000vsubfp \000"
- "vsubsbs \000vsubshs \000vsubsws \000vsububm \000vsububs \000vsubuhm \000"
- "vsubuhs \000vsubuwm \000vsubuws \000vsum2sws \000vsum4sbs \000vsum4shs "
- "\000vsum4ubs \000vsumsws \000vupkhpx \000vupkhsb \000vupkhsh \000vupklp"
- "x \000vupklsb \000vupklsh \000vxor \000xor \000xori \000xoris \000";
+ " \000lbz \000lbzu \000lbzx \000ld \000ldarx \000ldu \000ldx \000ld 2, 8"
+ "(\000ld 2, 40(1)\000lfd \000lfdx \000lfs \000lfsx \000lha \000lhau \000"
+ "lhax \000lhbrx \000lhz \000lhzu \000lhzx \000li \000lis \000lvebx \000l"
+ "vehx \000lvewx \000lvsl \000lvsr \000lvx \000lvxl \000lwa \000lwarx \000"
+ "lwax \000lwbrx \000lwz \000lwzu \000lwzx \000mcrf \000mfcr \000mfctr \000"
+ "mffs \000mflr \000mfspr \000mfvscr \000mtcrf \000mtctr \000mtfsb0 \000m"
+ "tfsb1 \000mtfsf \000mtlr \000mtspr 256, \000mtvscr \000mulhd \000mulhdu"
+ " \000mulhw \000mulhwu \000mulld \000mulli \000mullw \000nand \000neg \000"
+ "nop\000nor \000or \000orc \000ori \000oris \000rldcl \000rldicl \000rld"
+ "icr \000rldimi \000rlwimi \000rlwinm \000rlwinm. \000rlwnm \000sld \000"
+ "slw \000srad \000sradi \000sraw \000srawi \000srd \000srw \000stb \000s"
+ "tbu \000stbx \000std \000stdcx. \000stdu \000stdux \000stdx \000stfd \000"
+ "stfdu \000stfdx \000stfiwx \000stfs \000stfsu \000stfsx \000sth \000sth"
+ "brx \000sthu \000sthx \000stvebx \000stvehx \000stvewx \000stvx \000stv"
+ "xl \000stw \000stwbrx \000stwcx. \000stwu \000stwux \000stwx \000subf \000"
+ "subfc \000subfe \000subfic \000subfme \000subfze \000sync\000ba \000#TC"
+ "_RETURNa \000#TC_RETURNa8 \000#TC_RETURNd \000#TC_RETURNd8 \000#TC_RETU"
+ "RNr \000#TC_RETURNr8 \000trap\000UPDATE_VRSAVE \000vaddcuw \000vaddfp \000"
+ "vaddsbs \000vaddshs \000vaddsws \000vaddubm \000vaddubs \000vadduhm \000"
+ "vadduhs \000vadduwm \000vadduws \000vand \000vandc \000vavgsb \000vavgs"
+ "h \000vavgsw \000vavgub \000vavguh \000vavguw \000vcfsx \000vcfux \000v"
+ "cmpbfp \000vcmpbfp. \000vcmpeqfp \000vcmpeqfp. \000vcmpequb \000vcmpequ"
+ "b. \000vcmpequh \000vcmpequh. \000vcmpequw \000vcmpequw. \000vcmpgefp \000"
+ "vcmpgefp. \000vcmpgtfp \000vcmpgtfp. \000vcmpgtsb \000vcmpgtsb. \000vcm"
+ "pgtsh \000vcmpgtsh. \000vcmpgtsw \000vcmpgtsw. \000vcmpgtub \000vcmpgtu"
+ "b. \000vcmpgtuh \000vcmpgtuh. \000vcmpgtuw \000vcmpgtuw. \000vctsxs \000"
+ "vctuxs \000vexptefp \000vlogefp \000vmaddfp \000vmaxfp \000vmaxsb \000v"
+ "maxsh \000vmaxsw \000vmaxub \000vmaxuh \000vmaxuw \000vmhaddshs \000vmh"
+ "raddshs \000vminfp \000vminsb \000vminsh \000vminsw \000vminub \000vmin"
+ "uh \000vminuw \000vmladduhm \000vmrghb \000vmrghh \000vmrghw \000vmrglb"
+ " \000vmrglh \000vmrglw \000vmsummbm \000vmsumshm \000vmsumshs \000vmsum"
+ "ubm \000vmsumuhm \000vmsumuhs \000vmulesb \000vmulesh \000vmuleub \000v"
+ "muleuh \000vmulosb \000vmulosh \000vmuloub \000vmulouh \000vnmsubfp \000"
+ "vnor \000vor \000vperm \000vpkpx \000vpkshss \000vpkshus \000vpkswss \000"
+ "vpkswus \000vpkuhum \000vpkuhus \000vpkuwum \000vpkuwus \000vrefp \000v"
+ "rfim \000vrfin \000vrfip \000vrfiz \000vrlb \000vrlh \000vrlw \000vrsqr"
+ "tefp \000vsel \000vsl \000vslb \000vsldoi \000vslh \000vslo \000vslw \000"
+ "vspltb \000vsplth \000vspltisb \000vspltish \000vspltisw \000vspltw \000"
+ "vsr \000vsrab \000vsrah \000vsraw \000vsrb \000vsrh \000vsro \000vsrw \000"
+ "vsubcuw \000vsubfp \000vsubsbs \000vsubshs \000vsubsws \000vsububm \000"
+ "vsububs \000vsubuhm \000vsubuhs \000vsubuwm \000vsubuws \000vsum2sws \000"
+ "vsum4sbs \000vsum4shs \000vsum4ubs \000vsumsws \000vupkhpx \000vupkhsb "
+ "\000vupkhsh \000vupklpx \000vupklsb \000vupklsh \000vxor \000xor \000xo"
+ "ri \000xoris \000";
#ifndef NO_ASM_WRITER_BOILERPLATE
@@ -634,7 +637,7 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
printPredicateOperand(MI, 0, "cc");
break;
case 4:
- // BCTR, BCTRL8_Darwin, BCTRL8_ELF, BCTRL_Darwin, BCTRL_SVR4, DSSALL, NOP...
+ // BCTR, BCTRL8_Darwin, BCTRL8_ELF, BCTRL_Darwin, BCTRL_SVR4, DSSALL, LDt...
return;
break;
case 5:
@@ -689,7 +692,7 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
}
- // Fragment 1 encoded into 6 bits for 46 unique commands.
+ // Fragment 1 encoded into 6 bits for 47 unique commands.
switch ((Bits >> 22) & 63) {
default: // unreachable.
case 0:
@@ -901,21 +904,26 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 40:
+ // LDinto_toc
+ O << ')';
+ return;
+ break;
+ case 41:
// MFVRSAVE
O << ", 256";
return;
break;
- case 41:
+ case 42:
// MTFSF
printOperand(MI, 2);
return;
break;
- case 42:
+ case 43:
// SELECT_CC_F4, SELECT_CC_F8, SELECT_CC_I4, SELECT_CC_I8, SELECT_CC_VRRC
O << " SELECT_CC PSEUDO!";
return;
break;
- case 43:
+ case 44:
// SPILL_CR
O << " SPILL_CR ";
printOperand(MI, 0);
@@ -923,7 +931,7 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
printMemRegImm(MI, 1);
return;
break;
- case 44:
+ case 45:
// STBU, STBU8, STFDU, STFSU, STHU, STHU8, STWU, STWU8
printSymbolLo(MI, 2);
O << '(';
@@ -931,7 +939,7 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
O << ')';
return;
break;
- case 45:
+ case 46:
// STDU
printS16X4ImmOperand(MI, 2);
O << '(';
diff --git a/libclamav/c++/PPCGenCodeEmitter.inc b/libclamav/c++/PPCGenCodeEmitter.inc
index 0c3fab2..597195f 100644
--- a/libclamav/c++/PPCGenCodeEmitter.inc
+++ b/libclamav/c++/PPCGenCodeEmitter.inc
@@ -187,7 +187,9 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
2080374952U, // LDARX
3892314113U, // LDU
2080374826U, // LDX
+ 3896508448U, // LDinto_toc
3892314112U, // LDtoc
+ 3896574112U, // LDtoc_restore
3355443200U, // LFD
3422552064U, // LFDU
2080375982U, // LFDX
@@ -533,33 +535,8 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
unsigned op = 0;
op = op; // suppress warning
switch (opcode) {
- case PPC::ADD4:
- case PPC::ADD8:
- case PPC::ADDC:
- case PPC::ADDC8:
- case PPC::ADDE:
- case PPC::ADDE8:
- case PPC::ADDI:
- case PPC::ADDI8:
- case PPC::ADDIC:
- case PPC::ADDIC8:
- case PPC::ADDICo:
- case PPC::ADDIS:
- case PPC::ADDIS8:
- case PPC::ADDME:
- case PPC::ADDME8:
- case PPC::ADDZE:
- case PPC::ADDZE8:
case PPC::ADJCALLSTACKDOWN:
case PPC::ADJCALLSTACKUP:
- case PPC::AND:
- case PPC::AND8:
- case PPC::ANDC:
- case PPC::ANDC8:
- case PPC::ANDISo:
- case PPC::ANDISo8:
- case PPC::ANDIo:
- case PPC::ANDIo8:
case PPC::ATOMIC_CMP_SWAP_I16:
case PPC::ATOMIC_CMP_SWAP_I32:
case PPC::ATOMIC_CMP_SWAP_I64:
@@ -592,35 +569,36 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::ATOMIC_SWAP_I32:
case PPC::ATOMIC_SWAP_I64:
case PPC::ATOMIC_SWAP_I8:
- case PPC::B:
- case PPC::BCC:
case PPC::BCTR:
case PPC::BCTRL8_Darwin:
case PPC::BCTRL8_ELF:
case PPC::BCTRL_Darwin:
case PPC::BCTRL_SVR4:
- case PPC::BL8_Darwin:
- case PPC::BL8_ELF:
- case PPC::BLA8_Darwin:
- case PPC::BLA8_ELF:
- case PPC::BLA_Darwin:
- case PPC::BLA_SVR4:
- case PPC::BLR:
- case PPC::BL_Darwin:
- case PPC::BL_SVR4:
- case PPC::CMPD:
- case PPC::CMPDI:
- case PPC::CMPLD:
- case PPC::CMPLDI:
- case PPC::CMPLW:
- case PPC::CMPLWI:
- case PPC::CMPW:
- case PPC::CMPWI:
- case PPC::CNTLZD:
- case PPC::CNTLZW:
- case PPC::CREQV:
- case PPC::CROR:
- case PPC::CRSET:
+ case PPC::DYNALLOC:
+ case PPC::DYNALLOC8:
+ case PPC::LDtoc_restore:
+ case PPC::MovePCtoLR:
+ case PPC::MovePCtoLR8:
+ case PPC::NOP:
+ case PPC::SELECT_CC_F4:
+ case PPC::SELECT_CC_F8:
+ case PPC::SELECT_CC_I4:
+ case PPC::SELECT_CC_I8:
+ case PPC::SELECT_CC_VRRC:
+ case PPC::SPILL_CR:
+ case PPC::SYNC:
+ case PPC::TAILBCTR:
+ case PPC::TAILBCTR8:
+ case PPC::TCRETURNai:
+ case PPC::TCRETURNai8:
+ case PPC::TCRETURNdi:
+ case PPC::TCRETURNdi8:
+ case PPC::TCRETURNri:
+ case PPC::TCRETURNri8:
+ case PPC::TRAP:
+ case PPC::UPDATE_VRSAVE: {
+ break;
+ }
case PPC::DCBA:
case PPC::DCBF:
case PPC::DCBI:
@@ -628,103 +606,504 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::DCBT:
case PPC::DCBTST:
case PPC::DCBZ:
- case PPC::DCBZL:
- case PPC::DIVD:
- case PPC::DIVDU:
- case PPC::DIVW:
- case PPC::DIVWU:
- case PPC::DSS:
- case PPC::DSSALL:
- case PPC::DST:
- case PPC::DST64:
- case PPC::DSTST:
- case PPC::DSTST64:
- case PPC::DSTSTT:
- case PPC::DSTSTT64:
- case PPC::DSTT:
- case PPC::DSTT64:
- case PPC::DYNALLOC:
- case PPC::DYNALLOC8:
- case PPC::EQV:
- case PPC::EQV8:
+ case PPC::DCBZL: {
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 16;
+ // op: B
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::SRADI: {
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 16;
+ // op: RS
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 21;
+ // op: SH
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ Value |= (op & 32U) >> 4;
+ break;
+ }
+ case PPC::CNTLZD:
+ case PPC::CNTLZW:
case PPC::EXTSB:
case PPC::EXTSB8:
case PPC::EXTSH:
case PPC::EXTSH8:
case PPC::EXTSW:
case PPC::EXTSW_32:
- case PPC::EXTSW_32_64:
- case PPC::FABSD:
- case PPC::FABSS:
+ case PPC::EXTSW_32_64: {
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 16;
+ // op: RST
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 21;
+ break;
+ }
+ case PPC::AND:
+ case PPC::AND8:
+ case PPC::ANDC:
+ case PPC::ANDC8:
+ case PPC::EQV:
+ case PPC::EQV8:
+ case PPC::NAND:
+ case PPC::NAND8:
+ case PPC::NOR:
+ case PPC::NOR8:
+ case PPC::OR:
+ case PPC::OR4To8:
+ case PPC::OR8:
+ case PPC::OR8To4:
+ case PPC::ORC:
+ case PPC::ORC8:
+ case PPC::SLD:
+ case PPC::SLW:
+ case PPC::SRAD:
+ case PPC::SRAW:
+ case PPC::SRAWI:
+ case PPC::SRD:
+ case PPC::SRW:
+ case PPC::XOR:
+ case PPC::XOR8: {
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 16;
+ // op: RST
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 21;
+ // op: B
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::ADDI:
+ case PPC::ADDI8:
+ case PPC::ADDIC:
+ case PPC::ADDIC8:
+ case PPC::ADDICo:
+ case PPC::ADDIS:
+ case PPC::ADDIS8:
+ case PPC::LA:
+ case PPC::MULLI:
+ case PPC::SUBFIC:
+ case PPC::SUBFIC8: {
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: B
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: C
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= op & 65535U;
+ break;
+ }
+ case PPC::LI:
+ case PPC::LI8:
+ case PPC::LIS:
+ case PPC::LIS8: {
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: B
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= op & 65535U;
+ break;
+ }
+ case PPC::LBZ:
+ case PPC::LBZ8:
+ case PPC::LFD:
+ case PPC::LFS:
+ case PPC::LHA:
+ case PPC::LHA8:
+ case PPC::LHZ:
+ case PPC::LHZ8:
+ case PPC::LWZ:
+ case PPC::LWZ8:
+ case PPC::STB:
+ case PPC::STB8:
+ case PPC::STFD:
+ case PPC::STFS:
+ case PPC::STH:
+ case PPC::STH8:
+ case PPC::STW:
+ case PPC::STW8: {
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: C
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= op & 65535U;
+ // op: B
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 16;
+ break;
+ }
+ case PPC::LBZU:
+ case PPC::LBZU8:
+ case PPC::LFDU:
+ case PPC::LFSU:
+ case PPC::LHAU:
+ case PPC::LHAU8:
+ case PPC::LHZU:
+ case PPC::LHZU8:
+ case PPC::LWZU:
+ case PPC::LWZU8: {
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: C
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= op & 65535U;
+ // op: B
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 16;
+ break;
+ }
+ case PPC::STBU:
+ case PPC::STBU8:
+ case PPC::STFDU:
+ case PPC::STFSU:
+ case PPC::STHU:
+ case PPC::STHU8:
+ case PPC::STWU:
+ case PPC::STWU8: {
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 21;
+ // op: C
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= op & 65535U;
+ // op: B
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 16;
+ break;
+ }
+ case PPC::ANDISo:
+ case PPC::ANDISo8:
+ case PPC::ANDIo:
+ case PPC::ANDIo8:
+ case PPC::ORI:
+ case PPC::ORI8:
+ case PPC::ORIS:
+ case PPC::ORIS8:
+ case PPC::XORI:
+ case PPC::XORI8:
+ case PPC::XORIS:
+ case PPC::XORIS8: {
+ // op: B
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 16;
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 21;
+ // op: C
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= op & 65535U;
+ break;
+ }
+ case PPC::MCRF: {
+ // op: BF
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 7U) << 23;
+ // op: BFA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 7U) << 18;
+ break;
+ }
+ case PPC::FCMPUD:
+ case PPC::FCMPUS: {
+ // op: BF
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 7U) << 23;
+ // op: FRA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: FRB
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::CMPDI:
+ case PPC::CMPLDI:
+ case PPC::CMPLWI:
+ case PPC::CMPWI: {
+ // op: BF
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 7U) << 23;
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: I
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= op & 65535U;
+ break;
+ }
+ case PPC::CMPD:
+ case PPC::CMPLD:
+ case PPC::CMPLW:
+ case PPC::CMPW: {
+ // op: BF
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 7U) << 23;
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: RB
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::BCC: {
+ // op: BIBO
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ Value |= (op & 96U) << 11;
+ // op: CR
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 7U) << 18;
+ // op: BD
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 16383U) << 2;
+ break;
+ }
+ case PPC::BLR: {
+ // op: BIBO
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 4U) << 23;
+ Value |= (op & 8U) << 21;
+ Value |= (op & 16U) << 19;
+ Value |= (op & 32U) << 17;
+ Value |= (op & 64U) << 15;
+ Value |= (op & 3U) << 16;
+ // op: CR
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 1U) << 20;
+ Value |= (op & 2U) << 18;
+ Value |= (op & 4U) << 16;
+ break;
+ }
+ case PPC::CREQV:
+ case PPC::CROR: {
+ // op: CRD
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: CRA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: CRB
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::CRSET: {
+ // op: CRD
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ Value |= (op & 31U) << 16;
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::MTFSF: {
+ // op: FM
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 255U) << 17;
+ // op: RT
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::MTFSB0:
+ case PPC::MTFSB1: {
+ // op: FM
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ break;
+ }
case PPC::FADD:
case PPC::FADDS:
case PPC::FADDrtz:
- case PPC::FCFID:
- case PPC::FCMPUD:
- case PPC::FCMPUS:
- case PPC::FCTIDZ:
- case PPC::FCTIWZ:
case PPC::FDIV:
case PPC::FDIVS:
+ case PPC::FSUB:
+ case PPC::FSUBS: {
+ // op: FRT
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: FRA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: FRB
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::FMUL:
+ case PPC::FMULS: {
+ // op: FRT
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: FRA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: FRC
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 6;
+ break;
+ }
case PPC::FMADD:
case PPC::FMADDS:
- case PPC::FMRD:
- case PPC::FMRS:
- case PPC::FMRSD:
case PPC::FMSUB:
case PPC::FMSUBS:
- case PPC::FMUL:
- case PPC::FMULS:
- case PPC::FNABSD:
- case PPC::FNABSS:
- case PPC::FNEGD:
- case PPC::FNEGS:
case PPC::FNMADD:
case PPC::FNMADDS:
case PPC::FNMSUB:
case PPC::FNMSUBS:
- case PPC::FRSP:
case PPC::FSELD:
- case PPC::FSELS:
- case PPC::FSQRT:
- case PPC::FSQRTS:
- case PPC::FSUB:
- case PPC::FSUBS:
- case PPC::LA:
- case PPC::LBZ:
- case PPC::LBZ8:
- case PPC::LBZU:
- case PPC::LBZU8:
+ case PPC::FSELS: {
+ // op: FRT
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: FRA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: FRC
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 6;
+ // op: FRB
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::MTCRF: {
+ // op: FXM
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 255U) << 12;
+ // op: ST
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 21;
+ break;
+ }
+ case PPC::B:
+ case PPC::BL8_Darwin:
+ case PPC::BL8_ELF:
+ case PPC::BLA8_Darwin:
+ case PPC::BLA8_ELF:
+ case PPC::BLA_Darwin:
+ case PPC::BLA_SVR4:
+ case PPC::BL_Darwin:
+ case PPC::BL_SVR4:
+ case PPC::TAILB:
+ case PPC::TAILB8:
+ case PPC::TAILBA:
+ case PPC::TAILBA8: {
+ // op: LI
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 16777215U) << 2;
+ break;
+ }
+ case PPC::LDinto_toc: {
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 16;
+ break;
+ }
+ case PPC::RLWINM:
+ case PPC::RLWINMo:
+ case PPC::RLWNM: {
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 16;
+ // op: RS
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 21;
+ // op: RB
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ // op: MB
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 6;
+ // op: ME
+ op = getMachineOpValue(MI, MI.getOperand(4));
+ Value |= (op & 31U) << 1;
+ break;
+ }
+ case PPC::RLDCL:
+ case PPC::RLDICL:
+ case PPC::RLDICR: {
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 16;
+ // op: RS
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 21;
+ // op: SH
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ Value |= (op & 32U) >> 4;
+ // op: MBE
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 6;
+ Value |= op & 32U;
+ break;
+ }
+ case PPC::RLWIMI: {
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 16;
+ // op: RS
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 21;
+ // op: RB
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 11;
+ // op: MB
+ op = getMachineOpValue(MI, MI.getOperand(4));
+ Value |= (op & 31U) << 6;
+ // op: ME
+ op = getMachineOpValue(MI, MI.getOperand(5));
+ Value |= (op & 31U) << 1;
+ break;
+ }
+ case PPC::RLDIMI: {
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 16;
+ // op: RS
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 21;
+ // op: SH
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 11;
+ Value |= (op & 32U) >> 4;
+ // op: MBE
+ op = getMachineOpValue(MI, MI.getOperand(4));
+ Value |= (op & 31U) << 6;
+ Value |= op & 32U;
+ break;
+ }
+ case PPC::MFFS: {
+ // op: RST
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ break;
+ }
case PPC::LBZX:
case PPC::LBZX8:
- case PPC::LD:
case PPC::LDARX:
- case PPC::LDU:
case PPC::LDX:
- case PPC::LDtoc:
- case PPC::LFD:
- case PPC::LFDU:
case PPC::LFDX:
- case PPC::LFS:
- case PPC::LFSU:
case PPC::LFSX:
- case PPC::LHA:
- case PPC::LHA8:
- case PPC::LHAU:
- case PPC::LHAU8:
case PPC::LHAX:
case PPC::LHAX8:
case PPC::LHBRX:
- case PPC::LHZ:
- case PPC::LHZ8:
- case PPC::LHZU:
- case PPC::LHZU8:
case PPC::LHZX:
case PPC::LHZX8:
- case PPC::LI:
- case PPC::LI8:
- case PPC::LIS:
- case PPC::LIS8:
case PPC::LVEBX:
case PPC::LVEHX:
case PPC::LVEWX:
@@ -732,109 +1111,21 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::LVSR:
case PPC::LVX:
case PPC::LVXL:
- case PPC::LWA:
case PPC::LWARX:
case PPC::LWAX:
case PPC::LWBRX:
- case PPC::LWZ:
- case PPC::LWZ8:
- case PPC::LWZU:
- case PPC::LWZU8:
case PPC::LWZX:
case PPC::LWZX8:
- case PPC::MCRF:
- case PPC::MFCR:
- case PPC::MFCTR:
- case PPC::MFCTR8:
- case PPC::MFFS:
- case PPC::MFLR:
- case PPC::MFLR8:
- case PPC::MFOCRF:
- case PPC::MFVRSAVE:
- case PPC::MFVSCR:
- case PPC::MTCRF:
- case PPC::MTCTR:
- case PPC::MTCTR8:
- case PPC::MTFSB0:
- case PPC::MTFSB1:
- case PPC::MTFSF:
- case PPC::MTLR:
- case PPC::MTLR8:
- case PPC::MTVRSAVE:
- case PPC::MTVSCR:
- case PPC::MULHD:
- case PPC::MULHDU:
- case PPC::MULHW:
- case PPC::MULHWU:
- case PPC::MULLD:
- case PPC::MULLI:
- case PPC::MULLW:
- case PPC::MovePCtoLR:
- case PPC::MovePCtoLR8:
- case PPC::NAND:
- case PPC::NAND8:
- case PPC::NEG:
- case PPC::NEG8:
- case PPC::NOP:
- case PPC::NOR:
- case PPC::NOR8:
- case PPC::OR:
- case PPC::OR4To8:
- case PPC::OR8:
- case PPC::OR8To4:
- case PPC::ORC:
- case PPC::ORC8:
- case PPC::ORI:
- case PPC::ORI8:
- case PPC::ORIS:
- case PPC::ORIS8:
- case PPC::RLDCL:
- case PPC::RLDICL:
- case PPC::RLDICR:
- case PPC::RLDIMI:
- case PPC::RLWIMI:
- case PPC::RLWINM:
- case PPC::RLWINMo:
- case PPC::RLWNM:
- case PPC::SELECT_CC_F4:
- case PPC::SELECT_CC_F8:
- case PPC::SELECT_CC_I4:
- case PPC::SELECT_CC_I8:
- case PPC::SELECT_CC_VRRC:
- case PPC::SLD:
- case PPC::SLW:
- case PPC::SPILL_CR:
- case PPC::SRAD:
- case PPC::SRADI:
- case PPC::SRAW:
- case PPC::SRAWI:
- case PPC::SRD:
- case PPC::SRW:
- case PPC::STB:
- case PPC::STB8:
- case PPC::STBU:
- case PPC::STBU8:
case PPC::STBX:
case PPC::STBX8:
- case PPC::STD:
case PPC::STDCX:
- case PPC::STDU:
case PPC::STDUX:
case PPC::STDX:
case PPC::STDX_32:
- case PPC::STD_32:
- case PPC::STFD:
- case PPC::STFDU:
case PPC::STFDX:
case PPC::STFIWX:
- case PPC::STFS:
- case PPC::STFSU:
case PPC::STFSX:
- case PPC::STH:
- case PPC::STH8:
case PPC::STHBRX:
- case PPC::STHU:
- case PPC::STHU8:
case PPC::STHX:
case PPC::STHX8:
case PPC::STVEBX:
@@ -842,42 +1133,208 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::STVEWX:
case PPC::STVX:
case PPC::STVXL:
- case PPC::STW:
- case PPC::STW8:
case PPC::STWBRX:
case PPC::STWCX:
- case PPC::STWU:
- case PPC::STWU8:
case PPC::STWUX:
case PPC::STWX:
- case PPC::STWX8:
+ case PPC::STWX8: {
+ // op: RST
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: B
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::FABSD:
+ case PPC::FABSS:
+ case PPC::FCFID:
+ case PPC::FCTIDZ:
+ case PPC::FCTIWZ:
+ case PPC::FMRD:
+ case PPC::FMRS:
+ case PPC::FMRSD:
+ case PPC::FNABSD:
+ case PPC::FNABSS:
+ case PPC::FNEGD:
+ case PPC::FNEGS:
+ case PPC::FRSP:
+ case PPC::FSQRT:
+ case PPC::FSQRTS: {
+ // op: RST
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: B
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::LD:
+ case PPC::LDtoc:
+ case PPC::LWA:
+ case PPC::STD:
+ case PPC::STD_32: {
+ // op: RST
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: DS
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 16383U) << 2;
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 16;
+ break;
+ }
+ case PPC::LDU: {
+ // op: RST
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: DS
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 16383U) << 2;
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 16;
+ break;
+ }
+ case PPC::STDU: {
+ // op: RST
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 21;
+ // op: DS
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 16383U) << 2;
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 16;
+ break;
+ }
+ case PPC::MFCR:
+ case PPC::MFCTR:
+ case PPC::MFCTR8:
+ case PPC::MFLR:
+ case PPC::MFLR8:
+ case PPC::MFVRSAVE:
+ case PPC::MTCTR:
+ case PPC::MTCTR8:
+ case PPC::MTLR:
+ case PPC::MTLR8:
+ case PPC::MTVRSAVE: {
+ // op: RT
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ break;
+ }
+ case PPC::ADDME:
+ case PPC::ADDME8:
+ case PPC::ADDZE:
+ case PPC::ADDZE8:
+ case PPC::NEG:
+ case PPC::NEG8:
+ case PPC::SUBFME:
+ case PPC::SUBFME8:
+ case PPC::SUBFZE:
+ case PPC::SUBFZE8: {
+ // op: RT
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ break;
+ }
+ case PPC::ADD4:
+ case PPC::ADD8:
+ case PPC::ADDC:
+ case PPC::ADDC8:
+ case PPC::ADDE:
+ case PPC::ADDE8:
+ case PPC::DIVD:
+ case PPC::DIVDU:
+ case PPC::DIVW:
+ case PPC::DIVWU:
+ case PPC::MULHD:
+ case PPC::MULHDU:
+ case PPC::MULHW:
+ case PPC::MULHWU:
+ case PPC::MULLD:
+ case PPC::MULLW:
case PPC::SUBF:
case PPC::SUBF8:
case PPC::SUBFC:
case PPC::SUBFC8:
case PPC::SUBFE:
- case PPC::SUBFE8:
- case PPC::SUBFIC:
- case PPC::SUBFIC8:
- case PPC::SUBFME:
- case PPC::SUBFME8:
- case PPC::SUBFZE:
- case PPC::SUBFZE8:
- case PPC::SYNC:
- case PPC::TAILB:
- case PPC::TAILB8:
- case PPC::TAILBA:
- case PPC::TAILBA8:
- case PPC::TAILBCTR:
- case PPC::TAILBCTR8:
- case PPC::TCRETURNai:
- case PPC::TCRETURNai8:
- case PPC::TCRETURNdi:
- case PPC::TCRETURNdi8:
- case PPC::TCRETURNri:
- case PPC::TCRETURNri8:
- case PPC::TRAP:
- case PPC::UPDATE_VRSAVE:
+ case PPC::SUBFE8: {
+ // op: RT
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: RA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: RB
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::MFOCRF: {
+ // op: ST
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: FXM
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 255U) << 12;
+ break;
+ }
+ case PPC::DSS:
+ case PPC::DSSALL:
+ case PPC::DST:
+ case PPC::DST64:
+ case PPC::DSTST:
+ case PPC::DSTST64:
+ case PPC::DSTSTT:
+ case PPC::DSTSTT64:
+ case PPC::DSTT:
+ case PPC::DSTT64: {
+ // op: T
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 1U) << 25;
+ // op: STRM
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 3U) << 21;
+ // op: A
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 16;
+ // op: B
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::MTVSCR: {
+ // op: VB
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::MFVSCR: {
+ // op: VD
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ break;
+ }
+ case PPC::VSPLTISB:
+ case PPC::VSPLTISH:
+ case PPC::VSPLTISW: {
+ // op: VD
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: IMM
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ break;
+ }
case PPC::VADDCUW:
case PPC::VADDFP:
case PPC::VADDSBS:
@@ -927,9 +1384,6 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::VCMPGTUWo:
case PPC::VCTSXS:
case PPC::VCTUXS:
- case PPC::VEXPTEFP:
- case PPC::VLOGEFP:
- case PPC::VMADDFP:
case PPC::VMAXFP:
case PPC::VMAXSB:
case PPC::VMAXSH:
@@ -937,8 +1391,6 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::VMAXUB:
case PPC::VMAXUH:
case PPC::VMAXUW:
- case PPC::VMHADDSHS:
- case PPC::VMHRADDSHS:
case PPC::VMINFP:
case PPC::VMINSB:
case PPC::VMINSH:
@@ -946,19 +1398,12 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::VMINUB:
case PPC::VMINUH:
case PPC::VMINUW:
- case PPC::VMLADDUHM:
case PPC::VMRGHB:
case PPC::VMRGHH:
case PPC::VMRGHW:
case PPC::VMRGLB:
case PPC::VMRGLH:
case PPC::VMRGLW:
- case PPC::VMSUMMBM:
- case PPC::VMSUMSHM:
- case PPC::VMSUMSHS:
- case PPC::VMSUMUBM:
- case PPC::VMSUMUHM:
- case PPC::VMSUMUHS:
case PPC::VMULESB:
case PPC::VMULESH:
case PPC::VMULEUB:
@@ -967,10 +1412,8 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::VMULOSH:
case PPC::VMULOUB:
case PPC::VMULOUH:
- case PPC::VNMSUBFP:
case PPC::VNOR:
case PPC::VOR:
- case PPC::VPERM:
case PPC::VPKPX:
case PPC::VPKSHSS:
case PPC::VPKSHUS:
@@ -980,27 +1423,16 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::VPKUHUS:
case PPC::VPKUWUM:
case PPC::VPKUWUS:
- case PPC::VREFP:
- case PPC::VRFIM:
- case PPC::VRFIN:
- case PPC::VRFIP:
- case PPC::VRFIZ:
case PPC::VRLB:
case PPC::VRLH:
case PPC::VRLW:
- case PPC::VRSQRTEFP:
- case PPC::VSEL:
case PPC::VSL:
case PPC::VSLB:
- case PPC::VSLDOI:
case PPC::VSLH:
case PPC::VSLO:
case PPC::VSLW:
case PPC::VSPLTB:
case PPC::VSPLTH:
- case PPC::VSPLTISB:
- case PPC::VSPLTISH:
- case PPC::VSPLTISW:
case PPC::VSPLTW:
case PPC::VSR:
case PPC::VSRAB:
@@ -1026,20 +1458,102 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::VSUM4SHS:
case PPC::VSUM4UBS:
case PPC::VSUMSWS:
+ case PPC::VXOR: {
+ // op: VD
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: VA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: VB
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::VSLDOI: {
+ // op: VD
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: VA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: VB
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ // op: SH
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 15U) << 6;
+ break;
+ }
+ case PPC::VMHADDSHS:
+ case PPC::VMHRADDSHS:
+ case PPC::VMLADDUHM:
+ case PPC::VMSUMMBM:
+ case PPC::VMSUMSHM:
+ case PPC::VMSUMSHS:
+ case PPC::VMSUMUBM:
+ case PPC::VMSUMUHM:
+ case PPC::VMSUMUHS:
+ case PPC::VPERM:
+ case PPC::VSEL: {
+ // op: VD
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: VA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: VB
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 11;
+ // op: VC
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 6;
+ break;
+ }
+ case PPC::VMADDFP:
+ case PPC::VNMSUBFP: {
+ // op: VD
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: VA
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 16;
+ // op: VC
+ op = getMachineOpValue(MI, MI.getOperand(2));
+ Value |= (op & 31U) << 6;
+ // op: VB
+ op = getMachineOpValue(MI, MI.getOperand(3));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::VEXPTEFP:
+ case PPC::VLOGEFP:
+ case PPC::VREFP:
+ case PPC::VRFIM:
+ case PPC::VRFIN:
+ case PPC::VRFIP:
+ case PPC::VRFIZ:
+ case PPC::VRSQRTEFP:
case PPC::VUPKHPX:
case PPC::VUPKHSB:
case PPC::VUPKHSH:
case PPC::VUPKLPX:
case PPC::VUPKLSB:
- case PPC::VUPKLSH:
- case PPC::VXOR:
- case PPC::V_SET0:
- case PPC::XOR:
- case PPC::XOR8:
- case PPC::XORI:
- case PPC::XORI8:
- case PPC::XORIS:
- case PPC::XORIS8: {
+ case PPC::VUPKLSH: {
+ // op: VD
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ // op: VB
+ op = getMachineOpValue(MI, MI.getOperand(1));
+ Value |= (op & 31U) << 11;
+ break;
+ }
+ case PPC::V_SET0: {
+ // op: VD
+ op = getMachineOpValue(MI, MI.getOperand(0));
+ Value |= (op & 31U) << 21;
+ Value |= (op & 31U) << 16;
+ Value |= (op & 31U) << 11;
break;
}
default:
diff --git a/libclamav/c++/PPCGenDAGISel.inc b/libclamav/c++/PPCGenDAGISel.inc
index f5fcdd3..371f730 100644
--- a/libclamav/c++/PPCGenDAGISel.inc
+++ b/libclamav/c++/PPCGenDAGISel.inc
@@ -7606,6 +7606,87 @@ SDNode *Select_PPCISD_LBRX_i32(const SDValue &N) {
return NULL;
}
+DISABLE_INLINE SDNode *Emit_100(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, Chain, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
+ Chain = SDValue(ResNode, 1);
+ InFlag = SDValue(ResNode, 2);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 2),
+ SDValue(N.getNode(), 1)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_PPCISD_LOAD_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (PPCload:i64 ixaddr:iPTR:$src)
+ // Emits: (LD:i64 ixaddr:iPTR:$src)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (SelectAddrImmShift(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == TLI.getPointerTy()) {
+ SDNode *Result = Emit_100(N, PPC::LD, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (PPCload:i64 xaddr:iPTR:$src)
+ // Emits: (LDX:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == TLI.getPointerTy()) {
+ SDNode *Result = Emit_100(N, PPC::LDX, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_101(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, N1, Chain, InFlag);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_PPCISD_LOAD_TOC(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_101(N, PPC::LDinto_toc);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
SDNode *Select_PPCISD_Lo_i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
@@ -7740,18 +7821,18 @@ SDNode *Select_PPCISD_Lo_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_100(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_102(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag);
SDValue InFlag(ResNode, 1);
ReplaceUses(SDValue(N.getNode(), 1), InFlag);
return ResNode;
}
SDNode *Select_PPCISD_MFFS_f64(const SDValue &N) {
- SDNode *Result = Emit_100(N, PPC::MFFS, MVT::f64);
+ SDNode *Result = Emit_102(N, PPC::MFFS, MVT::f64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_101(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
@@ -7782,7 +7863,7 @@ SDNode *Select_PPCISD_MTCTR(const SDValue &N) {
// Emits: (MTCTR:isVoid GPRC:i32:$rS)
// Pattern complexity = 3 cost = 1 size = 0
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_101(N, PPC::MTCTR);
+ SDNode *Result = Emit_103(N, PPC::MTCTR);
return Result;
}
@@ -7790,7 +7871,7 @@ SDNode *Select_PPCISD_MTCTR(const SDValue &N) {
// Emits: (MTCTR8:isVoid G8RC:i64:$rS)
// Pattern complexity = 3 cost = 1 size = 0
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_101(N, PPC::MTCTR8);
+ SDNode *Result = Emit_103(N, PPC::MTCTR8);
return Result;
}
@@ -7798,7 +7879,7 @@ SDNode *Select_PPCISD_MTCTR(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_102(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
SDValue InFlag = N.getOperand(1);
@@ -7811,7 +7892,7 @@ SDNode *Select_PPCISD_MTFSB0(const SDValue &N) {
SDValue N0 = N.getOperand(0);
if (N0.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_102(N, PPC::MTFSB0);
+ SDNode *Result = Emit_104(N, PPC::MTFSB0);
return Result;
}
@@ -7823,7 +7904,7 @@ SDNode *Select_PPCISD_MTFSB1(const SDValue &N) {
SDValue N0 = N.getOperand(0);
if (N0.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_102(N, PPC::MTFSB1);
+ SDNode *Result = Emit_104(N, PPC::MTFSB1);
return Result;
}
@@ -7831,7 +7912,7 @@ SDNode *Select_PPCISD_MTFSB1(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_105(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -7846,7 +7927,7 @@ SDNode *Select_PPCISD_MTFSF_f64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_103(N, PPC::MTFSF, MVT::f64);
+ SDNode *Result = Emit_105(N, PPC::MTFSF, MVT::f64);
return Result;
}
}
@@ -7855,7 +7936,7 @@ SDNode *Select_PPCISD_MTFSF_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_106(const SDValue &N, unsigned Opc0) {
SDValue InFlag = N.getOperand(0);
SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, InFlag);
InFlag = SDValue(ResNode, 0);
@@ -7863,11 +7944,11 @@ DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0) {
return ResNode;
}
SDNode *Select_PPCISD_NOP(const SDValue &N) {
- SDNode *Result = Emit_104(N, PPC::NOP);
+ SDNode *Result = Emit_106(N, PPC::NOP);
return Result;
}
-DISABLE_INLINE SDNode *Emit_105(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_107(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
SDValue Tmp0 = CurDAG->getTargetConstant(0x14ULL, MVT::i32);
@@ -7880,7 +7961,7 @@ DISABLE_INLINE SDNode *Emit_105(const SDValue &N, unsigned Opc0) {
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, HasInFlag ? 4 : 3);
}
SDNode *Select_PPCISD_RET_FLAG(const SDValue &N) {
- SDNode *Result = Emit_105(N, PPC::BLR);
+ SDNode *Result = Emit_107(N, PPC::BLR);
return Result;
}
@@ -7956,7 +8037,7 @@ SDNode *Select_PPCISD_SRL_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_106(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -7977,7 +8058,7 @@ SDNode *Select_PPCISD_STBRX(const SDValue &N) {
// Emits: (STHBRX:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 12 cost = 1 size = 0
if (cast<VTSDNode>(N3)->getVT() == MVT::i16) {
- SDNode *Result = Emit_106(N, PPC::STHBRX, CPTmpN2_0, CPTmpN2_1);
+ SDNode *Result = Emit_108(N, PPC::STHBRX, CPTmpN2_0, CPTmpN2_1);
return Result;
}
@@ -7985,7 +8066,7 @@ SDNode *Select_PPCISD_STBRX(const SDValue &N) {
// Emits: (STWBRX:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 12 cost = 1 size = 0
if (cast<VTSDNode>(N3)->getVT() == MVT::i32) {
- SDNode *Result = Emit_106(N, PPC::STWBRX, CPTmpN2_0, CPTmpN2_1);
+ SDNode *Result = Emit_108(N, PPC::STWBRX, CPTmpN2_0, CPTmpN2_1);
return Result;
}
}
@@ -7994,7 +8075,7 @@ SDNode *Select_PPCISD_STBRX(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_107(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+DISABLE_INLINE SDNode *Emit_109(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -8013,7 +8094,7 @@ SDNode *Select_PPCISD_STCX(const SDValue &N) {
// Emits: (STWCX:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 12 cost = 1 size = 0
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_107(N, PPC::STWCX, CPTmpN2_0, CPTmpN2_1);
+ SDNode *Result = Emit_109(N, PPC::STWCX, CPTmpN2_0, CPTmpN2_1);
return Result;
}
@@ -8021,7 +8102,7 @@ SDNode *Select_PPCISD_STCX(const SDValue &N) {
// Emits: (STDCX:isVoid G8RC:i64:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 12 cost = 1 size = 0
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_107(N, PPC::STDCX, CPTmpN2_0, CPTmpN2_1);
+ SDNode *Result = Emit_109(N, PPC::STDCX, CPTmpN2_0, CPTmpN2_1);
return Result;
}
}
@@ -8042,7 +8123,7 @@ SDNode *Select_PPCISD_STD_32(const SDValue &N) {
// Pattern complexity = 12 cost = 1 size = 0
if (SelectAddrImmShift(N, N2, CPTmpN2_0, CPTmpN2_1) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_107(N, PPC::STD_32, CPTmpN2_0, CPTmpN2_1);
+ SDNode *Result = Emit_109(N, PPC::STD_32, CPTmpN2_0, CPTmpN2_1);
return Result;
}
@@ -8051,7 +8132,7 @@ SDNode *Select_PPCISD_STD_32(const SDValue &N) {
// Pattern complexity = 12 cost = 1 size = 0
if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_107(N, PPC::STDX_32, CPTmpN2_0, CPTmpN2_1);
+ SDNode *Result = Emit_109(N, PPC::STDX_32, CPTmpN2_0, CPTmpN2_1);
return Result;
}
@@ -8066,7 +8147,7 @@ SDNode *Select_PPCISD_STFIWX(const SDValue &N) {
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_107(N, PPC::STFIWX, CPTmpN2_0, CPTmpN2_1);
+ SDNode *Result = Emit_109(N, PPC::STFIWX, CPTmpN2_0, CPTmpN2_1);
return Result;
}
@@ -8074,7 +8155,7 @@ SDNode *Select_PPCISD_STFIWX(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_110(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -8096,7 +8177,7 @@ DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, unsigned NumInp
Ops0.push_back(InFlag);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
}
-DISABLE_INLINE SDNode *Emit_109(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_111(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -8118,7 +8199,7 @@ DISABLE_INLINE SDNode *Emit_109(const SDValue &N, unsigned Opc0, unsigned NumInp
Ops0.push_back(InFlag);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
}
-DISABLE_INLINE SDNode *Emit_110(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_112(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -8150,7 +8231,7 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
// Emits: (TCRETURNai:isVoid (imm:i32):$func, (imm:i32):$offset)
// Pattern complexity = 9 cost = 1 size = 0
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_108(N, PPC::TCRETURNai, 2);
+ SDNode *Result = Emit_110(N, PPC::TCRETURNai, 2);
return Result;
}
@@ -8158,7 +8239,7 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
// Emits: (TCRETURNai8:isVoid (imm:i64):$func, (imm:i32):$offset)
// Pattern complexity = 9 cost = 1 size = 0
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_109(N, PPC::TCRETURNai8, 2);
+ SDNode *Result = Emit_111(N, PPC::TCRETURNai8, 2);
return Result;
}
}
@@ -8171,7 +8252,7 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_110(N, PPC::TCRETURNdi8, 2);
+ SDNode *Result = Emit_112(N, PPC::TCRETURNdi8, 2);
return Result;
}
}
@@ -8183,7 +8264,7 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_110(N, PPC::TCRETURNdi8, 2);
+ SDNode *Result = Emit_112(N, PPC::TCRETURNdi8, 2);
return Result;
}
}
@@ -8195,7 +8276,7 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_110(N, PPC::TCRETURNdi, 2);
+ SDNode *Result = Emit_112(N, PPC::TCRETURNdi, 2);
return Result;
}
}
@@ -8207,7 +8288,7 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_110(N, PPC::TCRETURNdi, 2);
+ SDNode *Result = Emit_112(N, PPC::TCRETURNdi, 2);
return Result;
}
}
@@ -8218,7 +8299,7 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
// Emits: (TCRETURNri8:isVoid CTRRC8:i64:$dst, (imm:i32):$imm)
// Pattern complexity = 6 cost = 1 size = 0
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_110(N, PPC::TCRETURNri8, 2);
+ SDNode *Result = Emit_112(N, PPC::TCRETURNri8, 2);
return Result;
}
@@ -8226,7 +8307,7 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
// Emits: (TCRETURNri:isVoid CTRRC:i32:$dst, (imm:i32):$imm)
// Pattern complexity = 6 cost = 1 size = 0
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_110(N, PPC::TCRETURNri, 2);
+ SDNode *Result = Emit_112(N, PPC::TCRETURNri, 2);
return Result;
}
}
@@ -8246,7 +8327,29 @@ SDNode *Select_PPCISD_TOC_ENTRY_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_111(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_113(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue InFlag = N.getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Chain, InFlag);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_PPCISD_TOC_RESTORE(const SDValue &N) {
+ SDNode *Result = Emit_113(N, PPC::LDtoc_restore);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_114(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -8264,7 +8367,7 @@ SDNode *Select_PPCISD_VCMP_v16i8(const SDValue &N) {
// Emits: (VCMPEQUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_111(N, PPC::VCMPEQUB, MVT::v16i8);
+ SDNode *Result = Emit_114(N, PPC::VCMPEQUB, MVT::v16i8);
return Result;
}
@@ -8272,7 +8375,7 @@ SDNode *Select_PPCISD_VCMP_v16i8(const SDValue &N) {
// Emits: (VCMPGTSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(774)) {
- SDNode *Result = Emit_111(N, PPC::VCMPGTSB, MVT::v16i8);
+ SDNode *Result = Emit_114(N, PPC::VCMPGTSB, MVT::v16i8);
return Result;
}
@@ -8280,7 +8383,7 @@ SDNode *Select_PPCISD_VCMP_v16i8(const SDValue &N) {
// Emits: (VCMPGTUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(518)) {
- SDNode *Result = Emit_111(N, PPC::VCMPGTUB, MVT::v16i8);
+ SDNode *Result = Emit_114(N, PPC::VCMPGTUB, MVT::v16i8);
return Result;
}
}
@@ -8301,7 +8404,7 @@ SDNode *Select_PPCISD_VCMP_v8i16(const SDValue &N) {
// Emits: (VCMPEQUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(70)) {
- SDNode *Result = Emit_111(N, PPC::VCMPEQUH, MVT::v8i16);
+ SDNode *Result = Emit_114(N, PPC::VCMPEQUH, MVT::v8i16);
return Result;
}
@@ -8309,7 +8412,7 @@ SDNode *Select_PPCISD_VCMP_v8i16(const SDValue &N) {
// Emits: (VCMPGTSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(838)) {
- SDNode *Result = Emit_111(N, PPC::VCMPGTSH, MVT::v8i16);
+ SDNode *Result = Emit_114(N, PPC::VCMPGTSH, MVT::v8i16);
return Result;
}
@@ -8317,7 +8420,7 @@ SDNode *Select_PPCISD_VCMP_v8i16(const SDValue &N) {
// Emits: (VCMPGTUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(582)) {
- SDNode *Result = Emit_111(N, PPC::VCMPGTUH, MVT::v8i16);
+ SDNode *Result = Emit_114(N, PPC::VCMPGTUH, MVT::v8i16);
return Result;
}
}
@@ -8338,7 +8441,7 @@ SDNode *Select_PPCISD_VCMP_v4i32(const SDValue &N) {
// Emits: (VCMPEQUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(134)) {
- SDNode *Result = Emit_111(N, PPC::VCMPEQUW, MVT::v4i32);
+ SDNode *Result = Emit_114(N, PPC::VCMPEQUW, MVT::v4i32);
return Result;
}
@@ -8346,7 +8449,7 @@ SDNode *Select_PPCISD_VCMP_v4i32(const SDValue &N) {
// Emits: (VCMPGTSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(902)) {
- SDNode *Result = Emit_111(N, PPC::VCMPGTSW, MVT::v4i32);
+ SDNode *Result = Emit_114(N, PPC::VCMPGTSW, MVT::v4i32);
return Result;
}
@@ -8354,7 +8457,7 @@ SDNode *Select_PPCISD_VCMP_v4i32(const SDValue &N) {
// Emits: (VCMPGTUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(646)) {
- SDNode *Result = Emit_111(N, PPC::VCMPGTUW, MVT::v4i32);
+ SDNode *Result = Emit_114(N, PPC::VCMPGTUW, MVT::v4i32);
return Result;
}
}
@@ -8375,7 +8478,7 @@ SDNode *Select_PPCISD_VCMP_v4f32(const SDValue &N) {
// Emits: (VCMPBFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(966)) {
- SDNode *Result = Emit_111(N, PPC::VCMPBFP, MVT::v4f32);
+ SDNode *Result = Emit_114(N, PPC::VCMPBFP, MVT::v4f32);
return Result;
}
@@ -8383,7 +8486,7 @@ SDNode *Select_PPCISD_VCMP_v4f32(const SDValue &N) {
// Emits: (VCMPEQFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(198)) {
- SDNode *Result = Emit_111(N, PPC::VCMPEQFP, MVT::v4f32);
+ SDNode *Result = Emit_114(N, PPC::VCMPEQFP, MVT::v4f32);
return Result;
}
@@ -8391,7 +8494,7 @@ SDNode *Select_PPCISD_VCMP_v4f32(const SDValue &N) {
// Emits: (VCMPGEFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(454)) {
- SDNode *Result = Emit_111(N, PPC::VCMPGEFP, MVT::v4f32);
+ SDNode *Result = Emit_114(N, PPC::VCMPGEFP, MVT::v4f32);
return Result;
}
@@ -8399,7 +8502,7 @@ SDNode *Select_PPCISD_VCMP_v4f32(const SDValue &N) {
// Emits: (VCMPGTFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(710)) {
- SDNode *Result = Emit_111(N, PPC::VCMPGTFP, MVT::v4f32);
+ SDNode *Result = Emit_114(N, PPC::VCMPGTFP, MVT::v4f32);
return Result;
}
}
@@ -8408,7 +8511,7 @@ SDNode *Select_PPCISD_VCMP_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_112(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_115(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -8429,7 +8532,7 @@ SDNode *Select_PPCISD_VCMPo_v16i8(const SDValue &N) {
// Emits: (VCMPEQUBo:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_112(N, PPC::VCMPEQUBo, MVT::v16i8);
+ SDNode *Result = Emit_115(N, PPC::VCMPEQUBo, MVT::v16i8);
return Result;
}
@@ -8437,7 +8540,7 @@ SDNode *Select_PPCISD_VCMPo_v16i8(const SDValue &N) {
// Emits: (VCMPGTSBo:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(774)) {
- SDNode *Result = Emit_112(N, PPC::VCMPGTSBo, MVT::v16i8);
+ SDNode *Result = Emit_115(N, PPC::VCMPGTSBo, MVT::v16i8);
return Result;
}
@@ -8445,7 +8548,7 @@ SDNode *Select_PPCISD_VCMPo_v16i8(const SDValue &N) {
// Emits: (VCMPGTUBo:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(518)) {
- SDNode *Result = Emit_112(N, PPC::VCMPGTUBo, MVT::v16i8);
+ SDNode *Result = Emit_115(N, PPC::VCMPGTUBo, MVT::v16i8);
return Result;
}
}
@@ -8466,7 +8569,7 @@ SDNode *Select_PPCISD_VCMPo_v8i16(const SDValue &N) {
// Emits: (VCMPEQUHo:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(70)) {
- SDNode *Result = Emit_112(N, PPC::VCMPEQUHo, MVT::v8i16);
+ SDNode *Result = Emit_115(N, PPC::VCMPEQUHo, MVT::v8i16);
return Result;
}
@@ -8474,7 +8577,7 @@ SDNode *Select_PPCISD_VCMPo_v8i16(const SDValue &N) {
// Emits: (VCMPGTSHo:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(838)) {
- SDNode *Result = Emit_112(N, PPC::VCMPGTSHo, MVT::v8i16);
+ SDNode *Result = Emit_115(N, PPC::VCMPGTSHo, MVT::v8i16);
return Result;
}
@@ -8482,7 +8585,7 @@ SDNode *Select_PPCISD_VCMPo_v8i16(const SDValue &N) {
// Emits: (VCMPGTUHo:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(582)) {
- SDNode *Result = Emit_112(N, PPC::VCMPGTUHo, MVT::v8i16);
+ SDNode *Result = Emit_115(N, PPC::VCMPGTUHo, MVT::v8i16);
return Result;
}
}
@@ -8503,7 +8606,7 @@ SDNode *Select_PPCISD_VCMPo_v4i32(const SDValue &N) {
// Emits: (VCMPEQUWo:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(134)) {
- SDNode *Result = Emit_112(N, PPC::VCMPEQUWo, MVT::v4i32);
+ SDNode *Result = Emit_115(N, PPC::VCMPEQUWo, MVT::v4i32);
return Result;
}
@@ -8511,7 +8614,7 @@ SDNode *Select_PPCISD_VCMPo_v4i32(const SDValue &N) {
// Emits: (VCMPGTSWo:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(902)) {
- SDNode *Result = Emit_112(N, PPC::VCMPGTSWo, MVT::v4i32);
+ SDNode *Result = Emit_115(N, PPC::VCMPGTSWo, MVT::v4i32);
return Result;
}
@@ -8519,7 +8622,7 @@ SDNode *Select_PPCISD_VCMPo_v4i32(const SDValue &N) {
// Emits: (VCMPGTUWo:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(646)) {
- SDNode *Result = Emit_112(N, PPC::VCMPGTUWo, MVT::v4i32);
+ SDNode *Result = Emit_115(N, PPC::VCMPGTUWo, MVT::v4i32);
return Result;
}
}
@@ -8540,7 +8643,7 @@ SDNode *Select_PPCISD_VCMPo_v4f32(const SDValue &N) {
// Emits: (VCMPBFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(966)) {
- SDNode *Result = Emit_112(N, PPC::VCMPBFPo, MVT::v4f32);
+ SDNode *Result = Emit_115(N, PPC::VCMPBFPo, MVT::v4f32);
return Result;
}
@@ -8548,7 +8651,7 @@ SDNode *Select_PPCISD_VCMPo_v4f32(const SDValue &N) {
// Emits: (VCMPEQFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(198)) {
- SDNode *Result = Emit_112(N, PPC::VCMPEQFPo, MVT::v4f32);
+ SDNode *Result = Emit_115(N, PPC::VCMPEQFPo, MVT::v4f32);
return Result;
}
@@ -8556,7 +8659,7 @@ SDNode *Select_PPCISD_VCMPo_v4f32(const SDValue &N) {
// Emits: (VCMPGEFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(454)) {
- SDNode *Result = Emit_112(N, PPC::VCMPGEFPo, MVT::v4f32);
+ SDNode *Result = Emit_115(N, PPC::VCMPGEFPo, MVT::v4f32);
return Result;
}
@@ -8564,7 +8667,7 @@ SDNode *Select_PPCISD_VCMPo_v4f32(const SDValue &N) {
// Emits: (VCMPGTFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(710)) {
- SDNode *Result = Emit_112(N, PPC::VCMPGTFPo, MVT::v4f32);
+ SDNode *Result = Emit_115(N, PPC::VCMPGTFPo, MVT::v4f32);
return Result;
}
}
@@ -9343,6 +9446,19 @@ SDNode *SelectCode(SDValue N) {
}
break;
}
+ case PPCISD::LOAD: {
+ switch (NVT) {
+ case MVT::i64:
+ return Select_PPCISD_LOAD_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::LOAD_TOC: {
+ return Select_PPCISD_LOAD_TOC(N);
+ break;
+ }
case PPCISD::Lo: {
switch (NVT) {
case MVT::i32:
@@ -9454,6 +9570,10 @@ SDNode *SelectCode(SDValue N) {
}
break;
}
+ case PPCISD::TOC_RESTORE: {
+ return Select_PPCISD_TOC_RESTORE(N);
+ break;
+ }
case PPCISD::VCMP: {
switch (NVT) {
case MVT::v16i8:
diff --git a/libclamav/c++/PPCGenInstrInfo.inc b/libclamav/c++/PPCGenInstrInfo.inc
index f608bff..80cd4ff 100644
--- a/libclamav/c++/PPCGenInstrInfo.inc
+++ b/libclamav/c++/PPCGenInstrInfo.inc
@@ -76,19 +76,19 @@ static const TargetOperandInfo OperandInfo44[] = { { PPC::GPRCRegClassID, 0, 0 }
static const TargetOperandInfo OperandInfo45[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
static const TargetOperandInfo OperandInfo46[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
static const TargetOperandInfo OperandInfo47[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
-static const TargetOperandInfo OperandInfo48[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo49[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
-static const TargetOperandInfo OperandInfo50[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
-static const TargetOperandInfo OperandInfo51[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
-static const TargetOperandInfo OperandInfo52[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
-static const TargetOperandInfo OperandInfo53[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
-static const TargetOperandInfo OperandInfo54[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
-static const TargetOperandInfo OperandInfo55[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo56[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo57[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
-static const TargetOperandInfo OperandInfo58[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo59[] = { { PPC::GPRCRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo60[] = { { PPC::G8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo48[] = { { PPC::G8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo49[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo50[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo51[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo52[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo53[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo54[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo55[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo56[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo57[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo58[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo59[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo60[] = { { PPC::GPRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo61[] = { { PPC::F8RCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo62[] = { { PPC::VRRCRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo63[] = { { 0, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
@@ -300,344 +300,346 @@ static const TargetInstrDesc PPCInsts[] = {
{ 176, 3, 1, 36, "LDARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo47 }, // Inst #176 = LDARX
{ 177, 4, 2, 35, "LDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #177 = LDU
{ 178, 3, 1, 35, "LDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #178 = LDX
- { 179, 3, 1, 35, "LDtoc", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 }, // Inst #179 = LDtoc
- { 180, 3, 1, 37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #180 = LFD
- { 181, 4, 2, 37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #181 = LFDU
- { 182, 3, 1, 38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #182 = LFDX
- { 183, 3, 1, 38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #183 = LFS
- { 184, 4, 2, 38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #184 = LFSU
- { 185, 3, 1, 38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #185 = LFSX
- { 186, 3, 1, 39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #186 = LHA
- { 187, 3, 1, 39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #187 = LHA8
- { 188, 4, 2, 33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #188 = LHAU
- { 189, 4, 2, 33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #189 = LHAU8
- { 190, 3, 1, 39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #190 = LHAX
- { 191, 3, 1, 39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #191 = LHAX8
- { 192, 3, 1, 33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #192 = LHBRX
- { 193, 3, 1, 33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #193 = LHZ
- { 194, 3, 1, 33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #194 = LHZ8
- { 195, 4, 2, 33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #195 = LHZU
- { 196, 4, 2, 33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #196 = LHZU8
- { 197, 3, 1, 33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #197 = LHZX
- { 198, 3, 1, 33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #198 = LHZX8
- { 199, 2, 1, 14, "LI", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #199 = LI
- { 200, 2, 1, 14, "LI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #200 = LI8
- { 201, 2, 1, 14, "LIS", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #201 = LIS
- { 202, 2, 1, 14, "LIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #202 = LIS8
- { 203, 3, 1, 33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #203 = LVEBX
- { 204, 3, 1, 33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #204 = LVEHX
- { 205, 3, 1, 33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #205 = LVEWX
- { 206, 3, 1, 33, "LVSL", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #206 = LVSL
- { 207, 3, 1, 33, "LVSR", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #207 = LVSR
- { 208, 3, 1, 33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #208 = LVX
- { 209, 3, 1, 33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #209 = LVXL
- { 210, 3, 1, 42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #210 = LWA
- { 211, 3, 1, 43, "LWARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo46 }, // Inst #211 = LWARX
- { 212, 3, 1, 39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #212 = LWAX
- { 213, 3, 1, 33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #213 = LWBRX
- { 214, 3, 1, 33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #214 = LWZ
- { 215, 3, 1, 33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #215 = LWZ8
- { 216, 4, 2, 33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #216 = LWZU
- { 217, 4, 2, 33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #217 = LWZU8
- { 218, 3, 1, 33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #218 = LWZX
- { 219, 3, 1, 33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #219 = LWZX8
- { 220, 2, 1, 2, "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #220 = MCRF
- { 221, 1, 1, 54, "MFCR", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #221 = MFCR
- { 222, 1, 1, 56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList4, NULL, NULL, OperandInfo59 }, // Inst #222 = MFCTR
- { 223, 1, 1, 56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList13, NULL, NULL, OperandInfo60 }, // Inst #223 = MFCTR8
- { 224, 1, 1, 15, "MFFS", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo61 }, // Inst #224 = MFFS
- { 225, 1, 1, 56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList14, NULL, NULL, OperandInfo59 }, // Inst #225 = MFLR
- { 226, 1, 1, 56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList15, NULL, NULL, OperandInfo60 }, // Inst #226 = MFLR8
- { 227, 2, 1, 54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #227 = MFOCRF
- { 228, 1, 1, 14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #228 = MFVRSAVE
- { 229, 1, 1, 33, "MFVSCR", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #229 = MFVSCR
- { 230, 2, 0, 3, "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo63 }, // Inst #230 = MTCRF
- { 231, 1, 0, 60, "MTCTR", 0, 0|1|(1<<3), NULL, ImplicitList4, Barriers4, OperandInfo59 }, // Inst #231 = MTCTR
- { 232, 1, 0, 60, "MTCTR8", 0, 0|1|(1<<3), NULL, ImplicitList13, Barriers5, OperandInfo60 }, // Inst #232 = MTCTR8
- { 233, 1, 0, 17, "MTFSB0", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #233 = MTFSB0
- { 234, 1, 0, 17, "MTFSB1", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #234 = MTFSB1
- { 235, 4, 1, 17, "MTFSF", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo64 }, // Inst #235 = MTFSF
- { 236, 1, 0, 60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList14, NULL, OperandInfo59 }, // Inst #236 = MTLR
- { 237, 1, 0, 60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList15, NULL, OperandInfo60 }, // Inst #237 = MTLR8
- { 238, 1, 0, 14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<1)|(1<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #238 = MTVRSAVE
- { 239, 1, 0, 33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #239 = MTVSCR
- { 240, 3, 1, 20, "MULHD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #240 = MULHD
- { 241, 3, 1, 21, "MULHDU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #241 = MULHDU
- { 242, 3, 1, 20, "MULHW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #242 = MULHW
- { 243, 3, 1, 21, "MULHWU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #243 = MULHWU
- { 244, 3, 1, 19, "MULLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #244 = MULLD
- { 245, 3, 1, 22, "MULLI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #245 = MULLI
- { 246, 3, 1, 20, "MULLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #246 = MULLW
- { 247, 1, 0, 52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList14, NULL, OperandInfo8 }, // Inst #247 = MovePCtoLR
- { 248, 1, 0, 52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList15, NULL, OperandInfo8 }, // Inst #248 = MovePCtoLR8
- { 249, 3, 1, 14, "NAND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #249 = NAND
- { 250, 3, 1, 14, "NAND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #250 = NAND8
- { 251, 2, 1, 14, "NEG", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #251 = NEG
- { 252, 2, 1, 14, "NEG8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #252 = NEG8
- { 253, 0, 0, 14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, 0 }, // Inst #253 = NOP
- { 254, 3, 1, 14, "NOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #254 = NOR
- { 255, 3, 1, 14, "NOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #255 = NOR8
- { 256, 3, 1, 14, "OR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #256 = OR
- { 257, 3, 1, 14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo65 }, // Inst #257 = OR4To8
- { 258, 3, 1, 14, "OR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #258 = OR8
- { 259, 3, 1, 14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo66 }, // Inst #259 = OR8To4
- { 260, 3, 1, 14, "ORC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #260 = ORC
- { 261, 3, 1, 14, "ORC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #261 = ORC8
- { 262, 3, 1, 14, "ORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #262 = ORI
- { 263, 3, 1, 14, "ORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #263 = ORI8
- { 264, 3, 1, 14, "ORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #264 = ORIS
- { 265, 3, 1, 14, "ORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #265 = ORIS8
- { 266, 4, 1, 25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 }, // Inst #266 = RLDCL
- { 267, 4, 1, 25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #267 = RLDICL
- { 268, 4, 1, 25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #268 = RLDICR
- { 269, 5, 1, 25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo69 }, // Inst #269 = RLDIMI
- { 270, 6, 1, 24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo70 }, // Inst #270 = RLWIMI
- { 271, 5, 1, 14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo71 }, // Inst #271 = RLWINM
- { 272, 5, 1, 14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, ImplicitList3, NULL, OperandInfo71 }, // Inst #272 = RLWINMo
- { 273, 5, 1, 14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo72 }, // Inst #273 = RLWNM
- { 274, 5, 1, 52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo73 }, // Inst #274 = SELECT_CC_F4
- { 275, 5, 1, 52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo74 }, // Inst #275 = SELECT_CC_F8
- { 276, 5, 1, 52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo75 }, // Inst #276 = SELECT_CC_I4
- { 277, 5, 1, 52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo76 }, // Inst #277 = SELECT_CC_I8
- { 278, 5, 1, 52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo77 }, // Inst #278 = SELECT_CC_VRRC
- { 279, 3, 1, 25, "SLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #279 = SLD
- { 280, 3, 1, 14, "SLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #280 = SLW
- { 281, 3, 0, 52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #281 = SPILL_CR
- { 282, 3, 1, 25, "SRAD", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #282 = SRAD
- { 283, 3, 1, 25, "SRADI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #283 = SRADI
- { 284, 3, 1, 26, "SRAW", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #284 = SRAW
- { 285, 3, 1, 26, "SRAWI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #285 = SRAWI
- { 286, 3, 1, 25, "SRD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #286 = SRD
- { 287, 3, 1, 14, "SRW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #287 = SRW
- { 288, 3, 0, 33, "STB", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #288 = STB
- { 289, 3, 0, 33, "STB8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #289 = STB8
- { 290, 4, 1, 33, "STBU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #290 = STBU
- { 291, 4, 1, 33, "STBU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #291 = STBU8
- { 292, 3, 0, 33, "STBX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #292 = STBX
- { 293, 3, 0, 33, "STBX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #293 = STBX8
- { 294, 3, 0, 46, "STD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #294 = STD
- { 295, 3, 0, 47, "STDCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo47 }, // Inst #295 = STDCX
- { 296, 4, 1, 46, "STDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #296 = STDU
- { 297, 3, 0, 46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #297 = STDUX
- { 298, 3, 0, 46, "STDX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #298 = STDX
- { 299, 3, 0, 46, "STDX_32", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #299 = STDX_32
- { 300, 3, 0, 46, "STD_32", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #300 = STD_32
- { 301, 3, 0, 51, "STFD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #301 = STFD
- { 302, 4, 1, 33, "STFDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo81 }, // Inst #302 = STFDU
- { 303, 3, 0, 51, "STFDX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #303 = STFDX
- { 304, 3, 0, 51, "STFIWX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #304 = STFIWX
- { 305, 3, 0, 51, "STFS", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #305 = STFS
- { 306, 4, 1, 33, "STFSU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo82 }, // Inst #306 = STFSU
- { 307, 3, 0, 51, "STFSX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #307 = STFSX
- { 308, 3, 0, 33, "STH", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #308 = STH
- { 309, 3, 0, 33, "STH8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #309 = STH8
- { 310, 3, 0, 33, "STHBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #310 = STHBRX
- { 311, 4, 1, 33, "STHU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #311 = STHU
- { 312, 4, 1, 33, "STHU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #312 = STHU8
- { 313, 3, 0, 33, "STHX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #313 = STHX
- { 314, 3, 0, 33, "STHX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #314 = STHX8
- { 315, 3, 0, 33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #315 = STVEBX
- { 316, 3, 0, 33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #316 = STVEHX
- { 317, 3, 0, 33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #317 = STVEWX
- { 318, 3, 0, 33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #318 = STVX
- { 319, 3, 0, 33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #319 = STVXL
- { 320, 3, 0, 33, "STW", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #320 = STW
- { 321, 3, 0, 33, "STW8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #321 = STW8
- { 322, 3, 0, 33, "STWBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #322 = STWBRX
- { 323, 3, 0, 49, "STWCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo46 }, // Inst #323 = STWCX
- { 324, 4, 1, 33, "STWU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #324 = STWU
- { 325, 4, 1, 33, "STWU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #325 = STWU8
- { 326, 3, 0, 33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #326 = STWUX
- { 327, 3, 0, 33, "STWX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #327 = STWX
- { 328, 3, 0, 33, "STWX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #328 = STWX8
- { 329, 3, 1, 14, "SUBF", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #329 = SUBF
- { 330, 3, 1, 14, "SUBF8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #330 = SUBF8
- { 331, 3, 1, 14, "SUBFC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #331 = SUBFC
- { 332, 3, 1, 14, "SUBFC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #332 = SUBFC8
- { 333, 3, 1, 14, "SUBFE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #333 = SUBFE
- { 334, 3, 1, 14, "SUBFE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #334 = SUBFE8
- { 335, 3, 1, 14, "SUBFIC", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #335 = SUBFIC
- { 336, 3, 1, 14, "SUBFIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #336 = SUBFIC8
- { 337, 2, 1, 14, "SUBFME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #337 = SUBFME
- { 338, 2, 1, 14, "SUBFME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #338 = SUBFME8
- { 339, 2, 1, 14, "SUBFZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #339 = SUBFZE
- { 340, 2, 1, 14, "SUBFZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #340 = SUBFZE8
- { 341, 0, 0, 50, "SYNC", 0|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #341 = SYNC
- { 342, 1, 0, 0, "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #342 = TAILB
- { 343, 1, 0, 0, "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #343 = TAILB8
- { 344, 1, 0, 0, "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #344 = TAILBA
- { 345, 1, 0, 0, "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #345 = TAILBA8
- { 346, 0, 0, 0, "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #346 = TAILBCTR
- { 347, 0, 0, 0, "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #347 = TAILBCTR8
- { 348, 2, 0, 52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #348 = TCRETURNai
- { 349, 2, 0, 52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #349 = TCRETURNai8
- { 350, 2, 0, 52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #350 = TCRETURNdi
- { 351, 2, 0, 52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #351 = TCRETURNdi8
- { 352, 2, 0, 52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo83 }, // Inst #352 = TCRETURNri
- { 353, 2, 0, 52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo84 }, // Inst #353 = TCRETURNri8
- { 354, 0, 0, 33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #354 = TRAP
- { 355, 2, 1, 52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo6 }, // Inst #355 = UPDATE_VRSAVE
- { 356, 3, 1, 67, "VADDCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #356 = VADDCUW
- { 357, 3, 1, 67, "VADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #357 = VADDFP
- { 358, 3, 1, 67, "VADDSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #358 = VADDSBS
- { 359, 3, 1, 67, "VADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #359 = VADDSHS
- { 360, 3, 1, 67, "VADDSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #360 = VADDSWS
- { 361, 3, 1, 70, "VADDUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #361 = VADDUBM
- { 362, 3, 1, 67, "VADDUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #362 = VADDUBS
- { 363, 3, 1, 70, "VADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #363 = VADDUHM
- { 364, 3, 1, 67, "VADDUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #364 = VADDUHS
- { 365, 3, 1, 70, "VADDUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #365 = VADDUWM
- { 366, 3, 1, 67, "VADDUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #366 = VADDUWS
- { 367, 3, 1, 67, "VAND", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #367 = VAND
- { 368, 3, 1, 67, "VANDC", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #368 = VANDC
- { 369, 3, 1, 67, "VAVGSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #369 = VAVGSB
- { 370, 3, 1, 67, "VAVGSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #370 = VAVGSH
- { 371, 3, 1, 67, "VAVGSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #371 = VAVGSW
- { 372, 3, 1, 67, "VAVGUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #372 = VAVGUB
- { 373, 3, 1, 67, "VAVGUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #373 = VAVGUH
- { 374, 3, 1, 67, "VAVGUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #374 = VAVGUW
- { 375, 3, 1, 67, "VCFSX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #375 = VCFSX
- { 376, 3, 1, 67, "VCFUX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #376 = VCFUX
- { 377, 3, 1, 68, "VCMPBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #377 = VCMPBFP
- { 378, 3, 1, 68, "VCMPBFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #378 = VCMPBFPo
- { 379, 3, 1, 68, "VCMPEQFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #379 = VCMPEQFP
- { 380, 3, 1, 68, "VCMPEQFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #380 = VCMPEQFPo
- { 381, 3, 1, 68, "VCMPEQUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #381 = VCMPEQUB
- { 382, 3, 1, 68, "VCMPEQUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #382 = VCMPEQUBo
- { 383, 3, 1, 68, "VCMPEQUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #383 = VCMPEQUH
- { 384, 3, 1, 68, "VCMPEQUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #384 = VCMPEQUHo
- { 385, 3, 1, 68, "VCMPEQUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #385 = VCMPEQUW
- { 386, 3, 1, 68, "VCMPEQUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #386 = VCMPEQUWo
- { 387, 3, 1, 68, "VCMPGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #387 = VCMPGEFP
- { 388, 3, 1, 68, "VCMPGEFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #388 = VCMPGEFPo
- { 389, 3, 1, 68, "VCMPGTFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #389 = VCMPGTFP
- { 390, 3, 1, 68, "VCMPGTFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #390 = VCMPGTFPo
- { 391, 3, 1, 68, "VCMPGTSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #391 = VCMPGTSB
- { 392, 3, 1, 68, "VCMPGTSBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #392 = VCMPGTSBo
- { 393, 3, 1, 68, "VCMPGTSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #393 = VCMPGTSH
- { 394, 3, 1, 68, "VCMPGTSHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #394 = VCMPGTSHo
- { 395, 3, 1, 68, "VCMPGTSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #395 = VCMPGTSW
- { 396, 3, 1, 68, "VCMPGTSWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #396 = VCMPGTSWo
- { 397, 3, 1, 68, "VCMPGTUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #397 = VCMPGTUB
- { 398, 3, 1, 68, "VCMPGTUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #398 = VCMPGTUBo
- { 399, 3, 1, 68, "VCMPGTUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #399 = VCMPGTUH
- { 400, 3, 1, 68, "VCMPGTUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #400 = VCMPGTUHo
- { 401, 3, 1, 68, "VCMPGTUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #401 = VCMPGTUW
- { 402, 3, 1, 68, "VCMPGTUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #402 = VCMPGTUWo
- { 403, 3, 1, 67, "VCTSXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #403 = VCTSXS
- { 404, 3, 1, 67, "VCTUXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #404 = VCTUXS
- { 405, 2, 1, 67, "VEXPTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #405 = VEXPTEFP
- { 406, 2, 1, 67, "VLOGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #406 = VLOGEFP
- { 407, 4, 1, 67, "VMADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #407 = VMADDFP
- { 408, 3, 1, 67, "VMAXFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #408 = VMAXFP
- { 409, 3, 1, 67, "VMAXSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #409 = VMAXSB
- { 410, 3, 1, 67, "VMAXSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #410 = VMAXSH
- { 411, 3, 1, 67, "VMAXSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #411 = VMAXSW
- { 412, 3, 1, 67, "VMAXUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #412 = VMAXUB
- { 413, 3, 1, 67, "VMAXUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #413 = VMAXUH
- { 414, 3, 1, 67, "VMAXUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #414 = VMAXUW
- { 415, 4, 1, 67, "VMHADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #415 = VMHADDSHS
- { 416, 4, 1, 67, "VMHRADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #416 = VMHRADDSHS
- { 417, 3, 1, 67, "VMINFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #417 = VMINFP
- { 418, 3, 1, 67, "VMINSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #418 = VMINSB
- { 419, 3, 1, 67, "VMINSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #419 = VMINSH
- { 420, 3, 1, 67, "VMINSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #420 = VMINSW
- { 421, 3, 1, 67, "VMINUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #421 = VMINUB
- { 422, 3, 1, 67, "VMINUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #422 = VMINUH
- { 423, 3, 1, 67, "VMINUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #423 = VMINUW
- { 424, 4, 1, 67, "VMLADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #424 = VMLADDUHM
- { 425, 3, 1, 67, "VMRGHB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #425 = VMRGHB
- { 426, 3, 1, 67, "VMRGHH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #426 = VMRGHH
- { 427, 3, 1, 67, "VMRGHW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #427 = VMRGHW
- { 428, 3, 1, 67, "VMRGLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #428 = VMRGLB
- { 429, 3, 1, 67, "VMRGLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #429 = VMRGLH
- { 430, 3, 1, 67, "VMRGLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #430 = VMRGLW
- { 431, 4, 1, 67, "VMSUMMBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #431 = VMSUMMBM
- { 432, 4, 1, 67, "VMSUMSHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #432 = VMSUMSHM
- { 433, 4, 1, 67, "VMSUMSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #433 = VMSUMSHS
- { 434, 4, 1, 67, "VMSUMUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #434 = VMSUMUBM
- { 435, 4, 1, 67, "VMSUMUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #435 = VMSUMUHM
- { 436, 4, 1, 67, "VMSUMUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #436 = VMSUMUHS
- { 437, 3, 1, 67, "VMULESB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #437 = VMULESB
- { 438, 3, 1, 67, "VMULESH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #438 = VMULESH
- { 439, 3, 1, 67, "VMULEUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #439 = VMULEUB
- { 440, 3, 1, 67, "VMULEUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #440 = VMULEUH
- { 441, 3, 1, 67, "VMULOSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #441 = VMULOSB
- { 442, 3, 1, 67, "VMULOSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #442 = VMULOSH
- { 443, 3, 1, 67, "VMULOUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #443 = VMULOUB
- { 444, 3, 1, 67, "VMULOUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #444 = VMULOUH
- { 445, 4, 1, 67, "VNMSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #445 = VNMSUBFP
- { 446, 3, 1, 67, "VNOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #446 = VNOR
- { 447, 3, 1, 67, "VOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #447 = VOR
- { 448, 4, 1, 67, "VPERM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #448 = VPERM
- { 449, 3, 1, 67, "VPKPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #449 = VPKPX
- { 450, 3, 1, 67, "VPKSHSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #450 = VPKSHSS
- { 451, 3, 1, 67, "VPKSHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #451 = VPKSHUS
- { 452, 3, 1, 67, "VPKSWSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #452 = VPKSWSS
- { 453, 3, 1, 67, "VPKSWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = VPKSWUS
- { 454, 3, 1, 67, "VPKUHUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #454 = VPKUHUM
- { 455, 3, 1, 67, "VPKUHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #455 = VPKUHUS
- { 456, 3, 1, 67, "VPKUWUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #456 = VPKUWUM
- { 457, 3, 1, 67, "VPKUWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #457 = VPKUWUS
- { 458, 2, 1, 67, "VREFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #458 = VREFP
- { 459, 2, 1, 67, "VRFIM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #459 = VRFIM
- { 460, 2, 1, 67, "VRFIN", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #460 = VRFIN
- { 461, 2, 1, 67, "VRFIP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #461 = VRFIP
- { 462, 2, 1, 67, "VRFIZ", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #462 = VRFIZ
- { 463, 3, 1, 67, "VRLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #463 = VRLB
- { 464, 3, 1, 67, "VRLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #464 = VRLH
- { 465, 3, 1, 67, "VRLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #465 = VRLW
- { 466, 2, 1, 67, "VRSQRTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #466 = VRSQRTEFP
- { 467, 4, 1, 67, "VSEL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #467 = VSEL
- { 468, 3, 1, 67, "VSL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #468 = VSL
- { 469, 3, 1, 67, "VSLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #469 = VSLB
- { 470, 4, 1, 67, "VSLDOI", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 }, // Inst #470 = VSLDOI
- { 471, 3, 1, 67, "VSLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #471 = VSLH
- { 472, 3, 1, 67, "VSLO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #472 = VSLO
- { 473, 3, 1, 67, "VSLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #473 = VSLW
- { 474, 3, 1, 71, "VSPLTB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #474 = VSPLTB
- { 475, 3, 1, 71, "VSPLTH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #475 = VSPLTH
- { 476, 2, 1, 71, "VSPLTISB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #476 = VSPLTISB
- { 477, 2, 1, 71, "VSPLTISH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #477 = VSPLTISH
- { 478, 2, 1, 71, "VSPLTISW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #478 = VSPLTISW
- { 479, 3, 1, 71, "VSPLTW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #479 = VSPLTW
- { 480, 3, 1, 67, "VSR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #480 = VSR
- { 481, 3, 1, 67, "VSRAB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #481 = VSRAB
- { 482, 3, 1, 67, "VSRAH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #482 = VSRAH
- { 483, 3, 1, 67, "VSRAW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #483 = VSRAW
- { 484, 3, 1, 67, "VSRB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #484 = VSRB
- { 485, 3, 1, 67, "VSRH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #485 = VSRH
- { 486, 3, 1, 67, "VSRO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #486 = VSRO
- { 487, 3, 1, 67, "VSRW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #487 = VSRW
- { 488, 3, 1, 67, "VSUBCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #488 = VSUBCUW
- { 489, 3, 1, 70, "VSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #489 = VSUBFP
- { 490, 3, 1, 67, "VSUBSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #490 = VSUBSBS
- { 491, 3, 1, 67, "VSUBSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #491 = VSUBSHS
- { 492, 3, 1, 67, "VSUBSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #492 = VSUBSWS
- { 493, 3, 1, 70, "VSUBUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #493 = VSUBUBM
- { 494, 3, 1, 67, "VSUBUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #494 = VSUBUBS
- { 495, 3, 1, 70, "VSUBUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #495 = VSUBUHM
- { 496, 3, 1, 67, "VSUBUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #496 = VSUBUHS
- { 497, 3, 1, 70, "VSUBUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #497 = VSUBUWM
- { 498, 3, 1, 67, "VSUBUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #498 = VSUBUWS
- { 499, 3, 1, 67, "VSUM2SWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #499 = VSUM2SWS
- { 500, 3, 1, 67, "VSUM4SBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #500 = VSUM4SBS
- { 501, 3, 1, 67, "VSUM4SHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #501 = VSUM4SHS
- { 502, 3, 1, 67, "VSUM4UBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #502 = VSUM4UBS
- { 503, 3, 1, 67, "VSUMSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #503 = VSUMSWS
- { 504, 2, 1, 67, "VUPKHPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #504 = VUPKHPX
- { 505, 2, 1, 67, "VUPKHSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #505 = VUPKHSB
- { 506, 2, 1, 67, "VUPKHSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #506 = VUPKHSH
- { 507, 2, 1, 67, "VUPKLPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #507 = VUPKLPX
- { 508, 2, 1, 67, "VUPKLSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #508 = VUPKLSB
- { 509, 2, 1, 67, "VUPKLSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #509 = VUPKLSH
- { 510, 3, 1, 67, "VXOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #510 = VXOR
- { 511, 1, 1, 67, "V_SET0", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo62 }, // Inst #511 = V_SET0
- { 512, 3, 1, 14, "XOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #512 = XOR
- { 513, 3, 1, 14, "XOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #513 = XOR8
- { 514, 3, 1, 14, "XORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #514 = XORI
- { 515, 3, 1, 14, "XORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #515 = XORI8
- { 516, 3, 1, 14, "XORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #516 = XORIS
- { 517, 3, 1, 14, "XORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #517 = XORIS8
+ { 179, 1, 0, 35, "LDinto_toc", 0|(1<<TID::FoldableAsLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 }, // Inst #179 = LDinto_toc
+ { 180, 3, 1, 35, "LDtoc", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #180 = LDtoc
+ { 181, 0, 0, 35, "LDtoc_restore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, 0 }, // Inst #181 = LDtoc_restore
+ { 182, 3, 1, 37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #182 = LFD
+ { 183, 4, 2, 37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #183 = LFDU
+ { 184, 3, 1, 38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #184 = LFDX
+ { 185, 3, 1, 38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #185 = LFS
+ { 186, 4, 2, 38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #186 = LFSU
+ { 187, 3, 1, 38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #187 = LFSX
+ { 188, 3, 1, 39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #188 = LHA
+ { 189, 3, 1, 39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #189 = LHA8
+ { 190, 4, 2, 33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #190 = LHAU
+ { 191, 4, 2, 33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #191 = LHAU8
+ { 192, 3, 1, 39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #192 = LHAX
+ { 193, 3, 1, 39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #193 = LHAX8
+ { 194, 3, 1, 33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #194 = LHBRX
+ { 195, 3, 1, 33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #195 = LHZ
+ { 196, 3, 1, 33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #196 = LHZ8
+ { 197, 4, 2, 33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #197 = LHZU
+ { 198, 4, 2, 33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #198 = LHZU8
+ { 199, 3, 1, 33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #199 = LHZX
+ { 200, 3, 1, 33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #200 = LHZX8
+ { 201, 2, 1, 14, "LI", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #201 = LI
+ { 202, 2, 1, 14, "LI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #202 = LI8
+ { 203, 2, 1, 14, "LIS", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #203 = LIS
+ { 204, 2, 1, 14, "LIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #204 = LIS8
+ { 205, 3, 1, 33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #205 = LVEBX
+ { 206, 3, 1, 33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #206 = LVEHX
+ { 207, 3, 1, 33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #207 = LVEWX
+ { 208, 3, 1, 33, "LVSL", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #208 = LVSL
+ { 209, 3, 1, 33, "LVSR", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #209 = LVSR
+ { 210, 3, 1, 33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #210 = LVX
+ { 211, 3, 1, 33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #211 = LVXL
+ { 212, 3, 1, 42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #212 = LWA
+ { 213, 3, 1, 43, "LWARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo46 }, // Inst #213 = LWARX
+ { 214, 3, 1, 39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #214 = LWAX
+ { 215, 3, 1, 33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #215 = LWBRX
+ { 216, 3, 1, 33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #216 = LWZ
+ { 217, 3, 1, 33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #217 = LWZ8
+ { 218, 4, 2, 33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #218 = LWZU
+ { 219, 4, 2, 33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #219 = LWZU8
+ { 220, 3, 1, 33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #220 = LWZX
+ { 221, 3, 1, 33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #221 = LWZX8
+ { 222, 2, 1, 2, "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #222 = MCRF
+ { 223, 1, 1, 54, "MFCR", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #223 = MFCR
+ { 224, 1, 1, 56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList4, NULL, NULL, OperandInfo60 }, // Inst #224 = MFCTR
+ { 225, 1, 1, 56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList13, NULL, NULL, OperandInfo48 }, // Inst #225 = MFCTR8
+ { 226, 1, 1, 15, "MFFS", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo61 }, // Inst #226 = MFFS
+ { 227, 1, 1, 56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList14, NULL, NULL, OperandInfo60 }, // Inst #227 = MFLR
+ { 228, 1, 1, 56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList15, NULL, NULL, OperandInfo48 }, // Inst #228 = MFLR8
+ { 229, 2, 1, 54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #229 = MFOCRF
+ { 230, 1, 1, 14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #230 = MFVRSAVE
+ { 231, 1, 1, 33, "MFVSCR", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #231 = MFVSCR
+ { 232, 2, 0, 3, "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo63 }, // Inst #232 = MTCRF
+ { 233, 1, 0, 60, "MTCTR", 0, 0|1|(1<<3), NULL, ImplicitList4, Barriers4, OperandInfo60 }, // Inst #233 = MTCTR
+ { 234, 1, 0, 60, "MTCTR8", 0, 0|1|(1<<3), NULL, ImplicitList13, Barriers5, OperandInfo48 }, // Inst #234 = MTCTR8
+ { 235, 1, 0, 17, "MTFSB0", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #235 = MTFSB0
+ { 236, 1, 0, 17, "MTFSB1", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #236 = MTFSB1
+ { 237, 4, 1, 17, "MTFSF", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo64 }, // Inst #237 = MTFSF
+ { 238, 1, 0, 60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList14, NULL, OperandInfo60 }, // Inst #238 = MTLR
+ { 239, 1, 0, 60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList15, NULL, OperandInfo48 }, // Inst #239 = MTLR8
+ { 240, 1, 0, 14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<1)|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #240 = MTVRSAVE
+ { 241, 1, 0, 33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #241 = MTVSCR
+ { 242, 3, 1, 20, "MULHD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #242 = MULHD
+ { 243, 3, 1, 21, "MULHDU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #243 = MULHDU
+ { 244, 3, 1, 20, "MULHW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #244 = MULHW
+ { 245, 3, 1, 21, "MULHWU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #245 = MULHWU
+ { 246, 3, 1, 19, "MULLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #246 = MULLD
+ { 247, 3, 1, 22, "MULLI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #247 = MULLI
+ { 248, 3, 1, 20, "MULLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #248 = MULLW
+ { 249, 1, 0, 52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList14, NULL, OperandInfo8 }, // Inst #249 = MovePCtoLR
+ { 250, 1, 0, 52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList15, NULL, OperandInfo8 }, // Inst #250 = MovePCtoLR8
+ { 251, 3, 1, 14, "NAND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #251 = NAND
+ { 252, 3, 1, 14, "NAND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #252 = NAND8
+ { 253, 2, 1, 14, "NEG", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #253 = NEG
+ { 254, 2, 1, 14, "NEG8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #254 = NEG8
+ { 255, 0, 0, 14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, 0 }, // Inst #255 = NOP
+ { 256, 3, 1, 14, "NOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #256 = NOR
+ { 257, 3, 1, 14, "NOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #257 = NOR8
+ { 258, 3, 1, 14, "OR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #258 = OR
+ { 259, 3, 1, 14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo65 }, // Inst #259 = OR4To8
+ { 260, 3, 1, 14, "OR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #260 = OR8
+ { 261, 3, 1, 14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo66 }, // Inst #261 = OR8To4
+ { 262, 3, 1, 14, "ORC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #262 = ORC
+ { 263, 3, 1, 14, "ORC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #263 = ORC8
+ { 264, 3, 1, 14, "ORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #264 = ORI
+ { 265, 3, 1, 14, "ORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #265 = ORI8
+ { 266, 3, 1, 14, "ORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #266 = ORIS
+ { 267, 3, 1, 14, "ORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #267 = ORIS8
+ { 268, 4, 1, 25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 }, // Inst #268 = RLDCL
+ { 269, 4, 1, 25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #269 = RLDICL
+ { 270, 4, 1, 25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #270 = RLDICR
+ { 271, 5, 1, 25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo69 }, // Inst #271 = RLDIMI
+ { 272, 6, 1, 24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo70 }, // Inst #272 = RLWIMI
+ { 273, 5, 1, 14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo71 }, // Inst #273 = RLWINM
+ { 274, 5, 1, 14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, ImplicitList3, NULL, OperandInfo71 }, // Inst #274 = RLWINMo
+ { 275, 5, 1, 14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo72 }, // Inst #275 = RLWNM
+ { 276, 5, 1, 52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo73 }, // Inst #276 = SELECT_CC_F4
+ { 277, 5, 1, 52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo74 }, // Inst #277 = SELECT_CC_F8
+ { 278, 5, 1, 52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo75 }, // Inst #278 = SELECT_CC_I4
+ { 279, 5, 1, 52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo76 }, // Inst #279 = SELECT_CC_I8
+ { 280, 5, 1, 52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo77 }, // Inst #280 = SELECT_CC_VRRC
+ { 281, 3, 1, 25, "SLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #281 = SLD
+ { 282, 3, 1, 14, "SLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #282 = SLW
+ { 283, 3, 0, 52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #283 = SPILL_CR
+ { 284, 3, 1, 25, "SRAD", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #284 = SRAD
+ { 285, 3, 1, 25, "SRADI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #285 = SRADI
+ { 286, 3, 1, 26, "SRAW", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #286 = SRAW
+ { 287, 3, 1, 26, "SRAWI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #287 = SRAWI
+ { 288, 3, 1, 25, "SRD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #288 = SRD
+ { 289, 3, 1, 14, "SRW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #289 = SRW
+ { 290, 3, 0, 33, "STB", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #290 = STB
+ { 291, 3, 0, 33, "STB8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #291 = STB8
+ { 292, 4, 1, 33, "STBU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #292 = STBU
+ { 293, 4, 1, 33, "STBU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #293 = STBU8
+ { 294, 3, 0, 33, "STBX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #294 = STBX
+ { 295, 3, 0, 33, "STBX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #295 = STBX8
+ { 296, 3, 0, 46, "STD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #296 = STD
+ { 297, 3, 0, 47, "STDCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo47 }, // Inst #297 = STDCX
+ { 298, 4, 1, 46, "STDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #298 = STDU
+ { 299, 3, 0, 46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #299 = STDUX
+ { 300, 3, 0, 46, "STDX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #300 = STDX
+ { 301, 3, 0, 46, "STDX_32", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #301 = STDX_32
+ { 302, 3, 0, 46, "STD_32", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #302 = STD_32
+ { 303, 3, 0, 51, "STFD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #303 = STFD
+ { 304, 4, 1, 33, "STFDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo81 }, // Inst #304 = STFDU
+ { 305, 3, 0, 51, "STFDX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #305 = STFDX
+ { 306, 3, 0, 51, "STFIWX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #306 = STFIWX
+ { 307, 3, 0, 51, "STFS", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #307 = STFS
+ { 308, 4, 1, 33, "STFSU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo82 }, // Inst #308 = STFSU
+ { 309, 3, 0, 51, "STFSX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #309 = STFSX
+ { 310, 3, 0, 33, "STH", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #310 = STH
+ { 311, 3, 0, 33, "STH8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #311 = STH8
+ { 312, 3, 0, 33, "STHBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #312 = STHBRX
+ { 313, 4, 1, 33, "STHU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #313 = STHU
+ { 314, 4, 1, 33, "STHU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #314 = STHU8
+ { 315, 3, 0, 33, "STHX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #315 = STHX
+ { 316, 3, 0, 33, "STHX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #316 = STHX8
+ { 317, 3, 0, 33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #317 = STVEBX
+ { 318, 3, 0, 33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #318 = STVEHX
+ { 319, 3, 0, 33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #319 = STVEWX
+ { 320, 3, 0, 33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #320 = STVX
+ { 321, 3, 0, 33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #321 = STVXL
+ { 322, 3, 0, 33, "STW", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #322 = STW
+ { 323, 3, 0, 33, "STW8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #323 = STW8
+ { 324, 3, 0, 33, "STWBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #324 = STWBRX
+ { 325, 3, 0, 49, "STWCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo46 }, // Inst #325 = STWCX
+ { 326, 4, 1, 33, "STWU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #326 = STWU
+ { 327, 4, 1, 33, "STWU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #327 = STWU8
+ { 328, 3, 0, 33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #328 = STWUX
+ { 329, 3, 0, 33, "STWX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #329 = STWX
+ { 330, 3, 0, 33, "STWX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #330 = STWX8
+ { 331, 3, 1, 14, "SUBF", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #331 = SUBF
+ { 332, 3, 1, 14, "SUBF8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #332 = SUBF8
+ { 333, 3, 1, 14, "SUBFC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #333 = SUBFC
+ { 334, 3, 1, 14, "SUBFC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #334 = SUBFC8
+ { 335, 3, 1, 14, "SUBFE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #335 = SUBFE
+ { 336, 3, 1, 14, "SUBFE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #336 = SUBFE8
+ { 337, 3, 1, 14, "SUBFIC", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #337 = SUBFIC
+ { 338, 3, 1, 14, "SUBFIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #338 = SUBFIC8
+ { 339, 2, 1, 14, "SUBFME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #339 = SUBFME
+ { 340, 2, 1, 14, "SUBFME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #340 = SUBFME8
+ { 341, 2, 1, 14, "SUBFZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #341 = SUBFZE
+ { 342, 2, 1, 14, "SUBFZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #342 = SUBFZE8
+ { 343, 0, 0, 50, "SYNC", 0|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #343 = SYNC
+ { 344, 1, 0, 0, "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #344 = TAILB
+ { 345, 1, 0, 0, "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #345 = TAILB8
+ { 346, 1, 0, 0, "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #346 = TAILBA
+ { 347, 1, 0, 0, "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #347 = TAILBA8
+ { 348, 0, 0, 0, "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #348 = TAILBCTR
+ { 349, 0, 0, 0, "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #349 = TAILBCTR8
+ { 350, 2, 0, 52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #350 = TCRETURNai
+ { 351, 2, 0, 52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #351 = TCRETURNai8
+ { 352, 2, 0, 52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #352 = TCRETURNdi
+ { 353, 2, 0, 52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #353 = TCRETURNdi8
+ { 354, 2, 0, 52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo83 }, // Inst #354 = TCRETURNri
+ { 355, 2, 0, 52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo84 }, // Inst #355 = TCRETURNri8
+ { 356, 0, 0, 33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #356 = TRAP
+ { 357, 2, 1, 52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo6 }, // Inst #357 = UPDATE_VRSAVE
+ { 358, 3, 1, 67, "VADDCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #358 = VADDCUW
+ { 359, 3, 1, 67, "VADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #359 = VADDFP
+ { 360, 3, 1, 67, "VADDSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #360 = VADDSBS
+ { 361, 3, 1, 67, "VADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #361 = VADDSHS
+ { 362, 3, 1, 67, "VADDSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #362 = VADDSWS
+ { 363, 3, 1, 70, "VADDUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #363 = VADDUBM
+ { 364, 3, 1, 67, "VADDUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #364 = VADDUBS
+ { 365, 3, 1, 70, "VADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #365 = VADDUHM
+ { 366, 3, 1, 67, "VADDUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #366 = VADDUHS
+ { 367, 3, 1, 70, "VADDUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #367 = VADDUWM
+ { 368, 3, 1, 67, "VADDUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #368 = VADDUWS
+ { 369, 3, 1, 67, "VAND", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #369 = VAND
+ { 370, 3, 1, 67, "VANDC", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #370 = VANDC
+ { 371, 3, 1, 67, "VAVGSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #371 = VAVGSB
+ { 372, 3, 1, 67, "VAVGSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #372 = VAVGSH
+ { 373, 3, 1, 67, "VAVGSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #373 = VAVGSW
+ { 374, 3, 1, 67, "VAVGUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #374 = VAVGUB
+ { 375, 3, 1, 67, "VAVGUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #375 = VAVGUH
+ { 376, 3, 1, 67, "VAVGUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #376 = VAVGUW
+ { 377, 3, 1, 67, "VCFSX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #377 = VCFSX
+ { 378, 3, 1, 67, "VCFUX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #378 = VCFUX
+ { 379, 3, 1, 68, "VCMPBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #379 = VCMPBFP
+ { 380, 3, 1, 68, "VCMPBFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #380 = VCMPBFPo
+ { 381, 3, 1, 68, "VCMPEQFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #381 = VCMPEQFP
+ { 382, 3, 1, 68, "VCMPEQFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #382 = VCMPEQFPo
+ { 383, 3, 1, 68, "VCMPEQUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #383 = VCMPEQUB
+ { 384, 3, 1, 68, "VCMPEQUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #384 = VCMPEQUBo
+ { 385, 3, 1, 68, "VCMPEQUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #385 = VCMPEQUH
+ { 386, 3, 1, 68, "VCMPEQUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #386 = VCMPEQUHo
+ { 387, 3, 1, 68, "VCMPEQUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #387 = VCMPEQUW
+ { 388, 3, 1, 68, "VCMPEQUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #388 = VCMPEQUWo
+ { 389, 3, 1, 68, "VCMPGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #389 = VCMPGEFP
+ { 390, 3, 1, 68, "VCMPGEFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #390 = VCMPGEFPo
+ { 391, 3, 1, 68, "VCMPGTFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #391 = VCMPGTFP
+ { 392, 3, 1, 68, "VCMPGTFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #392 = VCMPGTFPo
+ { 393, 3, 1, 68, "VCMPGTSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #393 = VCMPGTSB
+ { 394, 3, 1, 68, "VCMPGTSBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #394 = VCMPGTSBo
+ { 395, 3, 1, 68, "VCMPGTSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #395 = VCMPGTSH
+ { 396, 3, 1, 68, "VCMPGTSHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #396 = VCMPGTSHo
+ { 397, 3, 1, 68, "VCMPGTSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #397 = VCMPGTSW
+ { 398, 3, 1, 68, "VCMPGTSWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #398 = VCMPGTSWo
+ { 399, 3, 1, 68, "VCMPGTUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #399 = VCMPGTUB
+ { 400, 3, 1, 68, "VCMPGTUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #400 = VCMPGTUBo
+ { 401, 3, 1, 68, "VCMPGTUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #401 = VCMPGTUH
+ { 402, 3, 1, 68, "VCMPGTUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #402 = VCMPGTUHo
+ { 403, 3, 1, 68, "VCMPGTUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #403 = VCMPGTUW
+ { 404, 3, 1, 68, "VCMPGTUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #404 = VCMPGTUWo
+ { 405, 3, 1, 67, "VCTSXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #405 = VCTSXS
+ { 406, 3, 1, 67, "VCTUXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #406 = VCTUXS
+ { 407, 2, 1, 67, "VEXPTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #407 = VEXPTEFP
+ { 408, 2, 1, 67, "VLOGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #408 = VLOGEFP
+ { 409, 4, 1, 67, "VMADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #409 = VMADDFP
+ { 410, 3, 1, 67, "VMAXFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #410 = VMAXFP
+ { 411, 3, 1, 67, "VMAXSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #411 = VMAXSB
+ { 412, 3, 1, 67, "VMAXSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #412 = VMAXSH
+ { 413, 3, 1, 67, "VMAXSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #413 = VMAXSW
+ { 414, 3, 1, 67, "VMAXUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #414 = VMAXUB
+ { 415, 3, 1, 67, "VMAXUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #415 = VMAXUH
+ { 416, 3, 1, 67, "VMAXUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #416 = VMAXUW
+ { 417, 4, 1, 67, "VMHADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #417 = VMHADDSHS
+ { 418, 4, 1, 67, "VMHRADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #418 = VMHRADDSHS
+ { 419, 3, 1, 67, "VMINFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #419 = VMINFP
+ { 420, 3, 1, 67, "VMINSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #420 = VMINSB
+ { 421, 3, 1, 67, "VMINSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #421 = VMINSH
+ { 422, 3, 1, 67, "VMINSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #422 = VMINSW
+ { 423, 3, 1, 67, "VMINUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #423 = VMINUB
+ { 424, 3, 1, 67, "VMINUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #424 = VMINUH
+ { 425, 3, 1, 67, "VMINUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #425 = VMINUW
+ { 426, 4, 1, 67, "VMLADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #426 = VMLADDUHM
+ { 427, 3, 1, 67, "VMRGHB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #427 = VMRGHB
+ { 428, 3, 1, 67, "VMRGHH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #428 = VMRGHH
+ { 429, 3, 1, 67, "VMRGHW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #429 = VMRGHW
+ { 430, 3, 1, 67, "VMRGLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #430 = VMRGLB
+ { 431, 3, 1, 67, "VMRGLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #431 = VMRGLH
+ { 432, 3, 1, 67, "VMRGLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #432 = VMRGLW
+ { 433, 4, 1, 67, "VMSUMMBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #433 = VMSUMMBM
+ { 434, 4, 1, 67, "VMSUMSHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #434 = VMSUMSHM
+ { 435, 4, 1, 67, "VMSUMSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #435 = VMSUMSHS
+ { 436, 4, 1, 67, "VMSUMUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #436 = VMSUMUBM
+ { 437, 4, 1, 67, "VMSUMUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #437 = VMSUMUHM
+ { 438, 4, 1, 67, "VMSUMUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #438 = VMSUMUHS
+ { 439, 3, 1, 67, "VMULESB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #439 = VMULESB
+ { 440, 3, 1, 67, "VMULESH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #440 = VMULESH
+ { 441, 3, 1, 67, "VMULEUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #441 = VMULEUB
+ { 442, 3, 1, 67, "VMULEUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #442 = VMULEUH
+ { 443, 3, 1, 67, "VMULOSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #443 = VMULOSB
+ { 444, 3, 1, 67, "VMULOSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #444 = VMULOSH
+ { 445, 3, 1, 67, "VMULOUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #445 = VMULOUB
+ { 446, 3, 1, 67, "VMULOUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #446 = VMULOUH
+ { 447, 4, 1, 67, "VNMSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #447 = VNMSUBFP
+ { 448, 3, 1, 67, "VNOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #448 = VNOR
+ { 449, 3, 1, 67, "VOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #449 = VOR
+ { 450, 4, 1, 67, "VPERM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #450 = VPERM
+ { 451, 3, 1, 67, "VPKPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #451 = VPKPX
+ { 452, 3, 1, 67, "VPKSHSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #452 = VPKSHSS
+ { 453, 3, 1, 67, "VPKSHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = VPKSHUS
+ { 454, 3, 1, 67, "VPKSWSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #454 = VPKSWSS
+ { 455, 3, 1, 67, "VPKSWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #455 = VPKSWUS
+ { 456, 3, 1, 67, "VPKUHUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #456 = VPKUHUM
+ { 457, 3, 1, 67, "VPKUHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #457 = VPKUHUS
+ { 458, 3, 1, 67, "VPKUWUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #458 = VPKUWUM
+ { 459, 3, 1, 67, "VPKUWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #459 = VPKUWUS
+ { 460, 2, 1, 67, "VREFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #460 = VREFP
+ { 461, 2, 1, 67, "VRFIM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #461 = VRFIM
+ { 462, 2, 1, 67, "VRFIN", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #462 = VRFIN
+ { 463, 2, 1, 67, "VRFIP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #463 = VRFIP
+ { 464, 2, 1, 67, "VRFIZ", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #464 = VRFIZ
+ { 465, 3, 1, 67, "VRLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #465 = VRLB
+ { 466, 3, 1, 67, "VRLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #466 = VRLH
+ { 467, 3, 1, 67, "VRLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #467 = VRLW
+ { 468, 2, 1, 67, "VRSQRTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #468 = VRSQRTEFP
+ { 469, 4, 1, 67, "VSEL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #469 = VSEL
+ { 470, 3, 1, 67, "VSL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #470 = VSL
+ { 471, 3, 1, 67, "VSLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #471 = VSLB
+ { 472, 4, 1, 67, "VSLDOI", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 }, // Inst #472 = VSLDOI
+ { 473, 3, 1, 67, "VSLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #473 = VSLH
+ { 474, 3, 1, 67, "VSLO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #474 = VSLO
+ { 475, 3, 1, 67, "VSLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #475 = VSLW
+ { 476, 3, 1, 71, "VSPLTB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #476 = VSPLTB
+ { 477, 3, 1, 71, "VSPLTH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #477 = VSPLTH
+ { 478, 2, 1, 71, "VSPLTISB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #478 = VSPLTISB
+ { 479, 2, 1, 71, "VSPLTISH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #479 = VSPLTISH
+ { 480, 2, 1, 71, "VSPLTISW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #480 = VSPLTISW
+ { 481, 3, 1, 71, "VSPLTW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #481 = VSPLTW
+ { 482, 3, 1, 67, "VSR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #482 = VSR
+ { 483, 3, 1, 67, "VSRAB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #483 = VSRAB
+ { 484, 3, 1, 67, "VSRAH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #484 = VSRAH
+ { 485, 3, 1, 67, "VSRAW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #485 = VSRAW
+ { 486, 3, 1, 67, "VSRB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #486 = VSRB
+ { 487, 3, 1, 67, "VSRH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #487 = VSRH
+ { 488, 3, 1, 67, "VSRO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #488 = VSRO
+ { 489, 3, 1, 67, "VSRW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #489 = VSRW
+ { 490, 3, 1, 67, "VSUBCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #490 = VSUBCUW
+ { 491, 3, 1, 70, "VSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #491 = VSUBFP
+ { 492, 3, 1, 67, "VSUBSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #492 = VSUBSBS
+ { 493, 3, 1, 67, "VSUBSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #493 = VSUBSHS
+ { 494, 3, 1, 67, "VSUBSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #494 = VSUBSWS
+ { 495, 3, 1, 70, "VSUBUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #495 = VSUBUBM
+ { 496, 3, 1, 67, "VSUBUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #496 = VSUBUBS
+ { 497, 3, 1, 70, "VSUBUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #497 = VSUBUHM
+ { 498, 3, 1, 67, "VSUBUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #498 = VSUBUHS
+ { 499, 3, 1, 70, "VSUBUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #499 = VSUBUWM
+ { 500, 3, 1, 67, "VSUBUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #500 = VSUBUWS
+ { 501, 3, 1, 67, "VSUM2SWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #501 = VSUM2SWS
+ { 502, 3, 1, 67, "VSUM4SBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #502 = VSUM4SBS
+ { 503, 3, 1, 67, "VSUM4SHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #503 = VSUM4SHS
+ { 504, 3, 1, 67, "VSUM4UBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #504 = VSUM4UBS
+ { 505, 3, 1, 67, "VSUMSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #505 = VSUMSWS
+ { 506, 2, 1, 67, "VUPKHPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #506 = VUPKHPX
+ { 507, 2, 1, 67, "VUPKHSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #507 = VUPKHSB
+ { 508, 2, 1, 67, "VUPKHSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #508 = VUPKHSH
+ { 509, 2, 1, 67, "VUPKLPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #509 = VUPKLPX
+ { 510, 2, 1, 67, "VUPKLSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #510 = VUPKLSB
+ { 511, 2, 1, 67, "VUPKLSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #511 = VUPKLSH
+ { 512, 3, 1, 67, "VXOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #512 = VXOR
+ { 513, 1, 1, 67, "V_SET0", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo62 }, // Inst #513 = V_SET0
+ { 514, 3, 1, 14, "XOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #514 = XOR
+ { 515, 3, 1, 14, "XOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #515 = XOR8
+ { 516, 3, 1, 14, "XORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #516 = XORI
+ { 517, 3, 1, 14, "XORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #517 = XORI8
+ { 518, 3, 1, 14, "XORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #518 = XORIS
+ { 519, 3, 1, 14, "XORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #519 = XORIS8
};
} // End llvm namespace
diff --git a/libclamav/c++/PPCGenInstrNames.inc b/libclamav/c++/PPCGenInstrNames.inc
index 7cc9414..eb88431 100644
--- a/libclamav/c++/PPCGenInstrNames.inc
+++ b/libclamav/c++/PPCGenInstrNames.inc
@@ -189,346 +189,348 @@ namespace PPC {
LDARX = 176,
LDU = 177,
LDX = 178,
- LDtoc = 179,
- LFD = 180,
- LFDU = 181,
- LFDX = 182,
- LFS = 183,
- LFSU = 184,
- LFSX = 185,
- LHA = 186,
- LHA8 = 187,
- LHAU = 188,
- LHAU8 = 189,
- LHAX = 190,
- LHAX8 = 191,
- LHBRX = 192,
- LHZ = 193,
- LHZ8 = 194,
- LHZU = 195,
- LHZU8 = 196,
- LHZX = 197,
- LHZX8 = 198,
- LI = 199,
- LI8 = 200,
- LIS = 201,
- LIS8 = 202,
- LVEBX = 203,
- LVEHX = 204,
- LVEWX = 205,
- LVSL = 206,
- LVSR = 207,
- LVX = 208,
- LVXL = 209,
- LWA = 210,
- LWARX = 211,
- LWAX = 212,
- LWBRX = 213,
- LWZ = 214,
- LWZ8 = 215,
- LWZU = 216,
- LWZU8 = 217,
- LWZX = 218,
- LWZX8 = 219,
- MCRF = 220,
- MFCR = 221,
- MFCTR = 222,
- MFCTR8 = 223,
- MFFS = 224,
- MFLR = 225,
- MFLR8 = 226,
- MFOCRF = 227,
- MFVRSAVE = 228,
- MFVSCR = 229,
- MTCRF = 230,
- MTCTR = 231,
- MTCTR8 = 232,
- MTFSB0 = 233,
- MTFSB1 = 234,
- MTFSF = 235,
- MTLR = 236,
- MTLR8 = 237,
- MTVRSAVE = 238,
- MTVSCR = 239,
- MULHD = 240,
- MULHDU = 241,
- MULHW = 242,
- MULHWU = 243,
- MULLD = 244,
- MULLI = 245,
- MULLW = 246,
- MovePCtoLR = 247,
- MovePCtoLR8 = 248,
- NAND = 249,
- NAND8 = 250,
- NEG = 251,
- NEG8 = 252,
- NOP = 253,
- NOR = 254,
- NOR8 = 255,
- OR = 256,
- OR4To8 = 257,
- OR8 = 258,
- OR8To4 = 259,
- ORC = 260,
- ORC8 = 261,
- ORI = 262,
- ORI8 = 263,
- ORIS = 264,
- ORIS8 = 265,
- RLDCL = 266,
- RLDICL = 267,
- RLDICR = 268,
- RLDIMI = 269,
- RLWIMI = 270,
- RLWINM = 271,
- RLWINMo = 272,
- RLWNM = 273,
- SELECT_CC_F4 = 274,
- SELECT_CC_F8 = 275,
- SELECT_CC_I4 = 276,
- SELECT_CC_I8 = 277,
- SELECT_CC_VRRC = 278,
- SLD = 279,
- SLW = 280,
- SPILL_CR = 281,
- SRAD = 282,
- SRADI = 283,
- SRAW = 284,
- SRAWI = 285,
- SRD = 286,
- SRW = 287,
- STB = 288,
- STB8 = 289,
- STBU = 290,
- STBU8 = 291,
- STBX = 292,
- STBX8 = 293,
- STD = 294,
- STDCX = 295,
- STDU = 296,
- STDUX = 297,
- STDX = 298,
- STDX_32 = 299,
- STD_32 = 300,
- STFD = 301,
- STFDU = 302,
- STFDX = 303,
- STFIWX = 304,
- STFS = 305,
- STFSU = 306,
- STFSX = 307,
- STH = 308,
- STH8 = 309,
- STHBRX = 310,
- STHU = 311,
- STHU8 = 312,
- STHX = 313,
- STHX8 = 314,
- STVEBX = 315,
- STVEHX = 316,
- STVEWX = 317,
- STVX = 318,
- STVXL = 319,
- STW = 320,
- STW8 = 321,
- STWBRX = 322,
- STWCX = 323,
- STWU = 324,
- STWU8 = 325,
- STWUX = 326,
- STWX = 327,
- STWX8 = 328,
- SUBF = 329,
- SUBF8 = 330,
- SUBFC = 331,
- SUBFC8 = 332,
- SUBFE = 333,
- SUBFE8 = 334,
- SUBFIC = 335,
- SUBFIC8 = 336,
- SUBFME = 337,
- SUBFME8 = 338,
- SUBFZE = 339,
- SUBFZE8 = 340,
- SYNC = 341,
- TAILB = 342,
- TAILB8 = 343,
- TAILBA = 344,
- TAILBA8 = 345,
- TAILBCTR = 346,
- TAILBCTR8 = 347,
- TCRETURNai = 348,
- TCRETURNai8 = 349,
- TCRETURNdi = 350,
- TCRETURNdi8 = 351,
- TCRETURNri = 352,
- TCRETURNri8 = 353,
- TRAP = 354,
- UPDATE_VRSAVE = 355,
- VADDCUW = 356,
- VADDFP = 357,
- VADDSBS = 358,
- VADDSHS = 359,
- VADDSWS = 360,
- VADDUBM = 361,
- VADDUBS = 362,
- VADDUHM = 363,
- VADDUHS = 364,
- VADDUWM = 365,
- VADDUWS = 366,
- VAND = 367,
- VANDC = 368,
- VAVGSB = 369,
- VAVGSH = 370,
- VAVGSW = 371,
- VAVGUB = 372,
- VAVGUH = 373,
- VAVGUW = 374,
- VCFSX = 375,
- VCFUX = 376,
- VCMPBFP = 377,
- VCMPBFPo = 378,
- VCMPEQFP = 379,
- VCMPEQFPo = 380,
- VCMPEQUB = 381,
- VCMPEQUBo = 382,
- VCMPEQUH = 383,
- VCMPEQUHo = 384,
- VCMPEQUW = 385,
- VCMPEQUWo = 386,
- VCMPGEFP = 387,
- VCMPGEFPo = 388,
- VCMPGTFP = 389,
- VCMPGTFPo = 390,
- VCMPGTSB = 391,
- VCMPGTSBo = 392,
- VCMPGTSH = 393,
- VCMPGTSHo = 394,
- VCMPGTSW = 395,
- VCMPGTSWo = 396,
- VCMPGTUB = 397,
- VCMPGTUBo = 398,
- VCMPGTUH = 399,
- VCMPGTUHo = 400,
- VCMPGTUW = 401,
- VCMPGTUWo = 402,
- VCTSXS = 403,
- VCTUXS = 404,
- VEXPTEFP = 405,
- VLOGEFP = 406,
- VMADDFP = 407,
- VMAXFP = 408,
- VMAXSB = 409,
- VMAXSH = 410,
- VMAXSW = 411,
- VMAXUB = 412,
- VMAXUH = 413,
- VMAXUW = 414,
- VMHADDSHS = 415,
- VMHRADDSHS = 416,
- VMINFP = 417,
- VMINSB = 418,
- VMINSH = 419,
- VMINSW = 420,
- VMINUB = 421,
- VMINUH = 422,
- VMINUW = 423,
- VMLADDUHM = 424,
- VMRGHB = 425,
- VMRGHH = 426,
- VMRGHW = 427,
- VMRGLB = 428,
- VMRGLH = 429,
- VMRGLW = 430,
- VMSUMMBM = 431,
- VMSUMSHM = 432,
- VMSUMSHS = 433,
- VMSUMUBM = 434,
- VMSUMUHM = 435,
- VMSUMUHS = 436,
- VMULESB = 437,
- VMULESH = 438,
- VMULEUB = 439,
- VMULEUH = 440,
- VMULOSB = 441,
- VMULOSH = 442,
- VMULOUB = 443,
- VMULOUH = 444,
- VNMSUBFP = 445,
- VNOR = 446,
- VOR = 447,
- VPERM = 448,
- VPKPX = 449,
- VPKSHSS = 450,
- VPKSHUS = 451,
- VPKSWSS = 452,
- VPKSWUS = 453,
- VPKUHUM = 454,
- VPKUHUS = 455,
- VPKUWUM = 456,
- VPKUWUS = 457,
- VREFP = 458,
- VRFIM = 459,
- VRFIN = 460,
- VRFIP = 461,
- VRFIZ = 462,
- VRLB = 463,
- VRLH = 464,
- VRLW = 465,
- VRSQRTEFP = 466,
- VSEL = 467,
- VSL = 468,
- VSLB = 469,
- VSLDOI = 470,
- VSLH = 471,
- VSLO = 472,
- VSLW = 473,
- VSPLTB = 474,
- VSPLTH = 475,
- VSPLTISB = 476,
- VSPLTISH = 477,
- VSPLTISW = 478,
- VSPLTW = 479,
- VSR = 480,
- VSRAB = 481,
- VSRAH = 482,
- VSRAW = 483,
- VSRB = 484,
- VSRH = 485,
- VSRO = 486,
- VSRW = 487,
- VSUBCUW = 488,
- VSUBFP = 489,
- VSUBSBS = 490,
- VSUBSHS = 491,
- VSUBSWS = 492,
- VSUBUBM = 493,
- VSUBUBS = 494,
- VSUBUHM = 495,
- VSUBUHS = 496,
- VSUBUWM = 497,
- VSUBUWS = 498,
- VSUM2SWS = 499,
- VSUM4SBS = 500,
- VSUM4SHS = 501,
- VSUM4UBS = 502,
- VSUMSWS = 503,
- VUPKHPX = 504,
- VUPKHSB = 505,
- VUPKHSH = 506,
- VUPKLPX = 507,
- VUPKLSB = 508,
- VUPKLSH = 509,
- VXOR = 510,
- V_SET0 = 511,
- XOR = 512,
- XOR8 = 513,
- XORI = 514,
- XORI8 = 515,
- XORIS = 516,
- XORIS8 = 517,
- INSTRUCTION_LIST_END = 518
+ LDinto_toc = 179,
+ LDtoc = 180,
+ LDtoc_restore = 181,
+ LFD = 182,
+ LFDU = 183,
+ LFDX = 184,
+ LFS = 185,
+ LFSU = 186,
+ LFSX = 187,
+ LHA = 188,
+ LHA8 = 189,
+ LHAU = 190,
+ LHAU8 = 191,
+ LHAX = 192,
+ LHAX8 = 193,
+ LHBRX = 194,
+ LHZ = 195,
+ LHZ8 = 196,
+ LHZU = 197,
+ LHZU8 = 198,
+ LHZX = 199,
+ LHZX8 = 200,
+ LI = 201,
+ LI8 = 202,
+ LIS = 203,
+ LIS8 = 204,
+ LVEBX = 205,
+ LVEHX = 206,
+ LVEWX = 207,
+ LVSL = 208,
+ LVSR = 209,
+ LVX = 210,
+ LVXL = 211,
+ LWA = 212,
+ LWARX = 213,
+ LWAX = 214,
+ LWBRX = 215,
+ LWZ = 216,
+ LWZ8 = 217,
+ LWZU = 218,
+ LWZU8 = 219,
+ LWZX = 220,
+ LWZX8 = 221,
+ MCRF = 222,
+ MFCR = 223,
+ MFCTR = 224,
+ MFCTR8 = 225,
+ MFFS = 226,
+ MFLR = 227,
+ MFLR8 = 228,
+ MFOCRF = 229,
+ MFVRSAVE = 230,
+ MFVSCR = 231,
+ MTCRF = 232,
+ MTCTR = 233,
+ MTCTR8 = 234,
+ MTFSB0 = 235,
+ MTFSB1 = 236,
+ MTFSF = 237,
+ MTLR = 238,
+ MTLR8 = 239,
+ MTVRSAVE = 240,
+ MTVSCR = 241,
+ MULHD = 242,
+ MULHDU = 243,
+ MULHW = 244,
+ MULHWU = 245,
+ MULLD = 246,
+ MULLI = 247,
+ MULLW = 248,
+ MovePCtoLR = 249,
+ MovePCtoLR8 = 250,
+ NAND = 251,
+ NAND8 = 252,
+ NEG = 253,
+ NEG8 = 254,
+ NOP = 255,
+ NOR = 256,
+ NOR8 = 257,
+ OR = 258,
+ OR4To8 = 259,
+ OR8 = 260,
+ OR8To4 = 261,
+ ORC = 262,
+ ORC8 = 263,
+ ORI = 264,
+ ORI8 = 265,
+ ORIS = 266,
+ ORIS8 = 267,
+ RLDCL = 268,
+ RLDICL = 269,
+ RLDICR = 270,
+ RLDIMI = 271,
+ RLWIMI = 272,
+ RLWINM = 273,
+ RLWINMo = 274,
+ RLWNM = 275,
+ SELECT_CC_F4 = 276,
+ SELECT_CC_F8 = 277,
+ SELECT_CC_I4 = 278,
+ SELECT_CC_I8 = 279,
+ SELECT_CC_VRRC = 280,
+ SLD = 281,
+ SLW = 282,
+ SPILL_CR = 283,
+ SRAD = 284,
+ SRADI = 285,
+ SRAW = 286,
+ SRAWI = 287,
+ SRD = 288,
+ SRW = 289,
+ STB = 290,
+ STB8 = 291,
+ STBU = 292,
+ STBU8 = 293,
+ STBX = 294,
+ STBX8 = 295,
+ STD = 296,
+ STDCX = 297,
+ STDU = 298,
+ STDUX = 299,
+ STDX = 300,
+ STDX_32 = 301,
+ STD_32 = 302,
+ STFD = 303,
+ STFDU = 304,
+ STFDX = 305,
+ STFIWX = 306,
+ STFS = 307,
+ STFSU = 308,
+ STFSX = 309,
+ STH = 310,
+ STH8 = 311,
+ STHBRX = 312,
+ STHU = 313,
+ STHU8 = 314,
+ STHX = 315,
+ STHX8 = 316,
+ STVEBX = 317,
+ STVEHX = 318,
+ STVEWX = 319,
+ STVX = 320,
+ STVXL = 321,
+ STW = 322,
+ STW8 = 323,
+ STWBRX = 324,
+ STWCX = 325,
+ STWU = 326,
+ STWU8 = 327,
+ STWUX = 328,
+ STWX = 329,
+ STWX8 = 330,
+ SUBF = 331,
+ SUBF8 = 332,
+ SUBFC = 333,
+ SUBFC8 = 334,
+ SUBFE = 335,
+ SUBFE8 = 336,
+ SUBFIC = 337,
+ SUBFIC8 = 338,
+ SUBFME = 339,
+ SUBFME8 = 340,
+ SUBFZE = 341,
+ SUBFZE8 = 342,
+ SYNC = 343,
+ TAILB = 344,
+ TAILB8 = 345,
+ TAILBA = 346,
+ TAILBA8 = 347,
+ TAILBCTR = 348,
+ TAILBCTR8 = 349,
+ TCRETURNai = 350,
+ TCRETURNai8 = 351,
+ TCRETURNdi = 352,
+ TCRETURNdi8 = 353,
+ TCRETURNri = 354,
+ TCRETURNri8 = 355,
+ TRAP = 356,
+ UPDATE_VRSAVE = 357,
+ VADDCUW = 358,
+ VADDFP = 359,
+ VADDSBS = 360,
+ VADDSHS = 361,
+ VADDSWS = 362,
+ VADDUBM = 363,
+ VADDUBS = 364,
+ VADDUHM = 365,
+ VADDUHS = 366,
+ VADDUWM = 367,
+ VADDUWS = 368,
+ VAND = 369,
+ VANDC = 370,
+ VAVGSB = 371,
+ VAVGSH = 372,
+ VAVGSW = 373,
+ VAVGUB = 374,
+ VAVGUH = 375,
+ VAVGUW = 376,
+ VCFSX = 377,
+ VCFUX = 378,
+ VCMPBFP = 379,
+ VCMPBFPo = 380,
+ VCMPEQFP = 381,
+ VCMPEQFPo = 382,
+ VCMPEQUB = 383,
+ VCMPEQUBo = 384,
+ VCMPEQUH = 385,
+ VCMPEQUHo = 386,
+ VCMPEQUW = 387,
+ VCMPEQUWo = 388,
+ VCMPGEFP = 389,
+ VCMPGEFPo = 390,
+ VCMPGTFP = 391,
+ VCMPGTFPo = 392,
+ VCMPGTSB = 393,
+ VCMPGTSBo = 394,
+ VCMPGTSH = 395,
+ VCMPGTSHo = 396,
+ VCMPGTSW = 397,
+ VCMPGTSWo = 398,
+ VCMPGTUB = 399,
+ VCMPGTUBo = 400,
+ VCMPGTUH = 401,
+ VCMPGTUHo = 402,
+ VCMPGTUW = 403,
+ VCMPGTUWo = 404,
+ VCTSXS = 405,
+ VCTUXS = 406,
+ VEXPTEFP = 407,
+ VLOGEFP = 408,
+ VMADDFP = 409,
+ VMAXFP = 410,
+ VMAXSB = 411,
+ VMAXSH = 412,
+ VMAXSW = 413,
+ VMAXUB = 414,
+ VMAXUH = 415,
+ VMAXUW = 416,
+ VMHADDSHS = 417,
+ VMHRADDSHS = 418,
+ VMINFP = 419,
+ VMINSB = 420,
+ VMINSH = 421,
+ VMINSW = 422,
+ VMINUB = 423,
+ VMINUH = 424,
+ VMINUW = 425,
+ VMLADDUHM = 426,
+ VMRGHB = 427,
+ VMRGHH = 428,
+ VMRGHW = 429,
+ VMRGLB = 430,
+ VMRGLH = 431,
+ VMRGLW = 432,
+ VMSUMMBM = 433,
+ VMSUMSHM = 434,
+ VMSUMSHS = 435,
+ VMSUMUBM = 436,
+ VMSUMUHM = 437,
+ VMSUMUHS = 438,
+ VMULESB = 439,
+ VMULESH = 440,
+ VMULEUB = 441,
+ VMULEUH = 442,
+ VMULOSB = 443,
+ VMULOSH = 444,
+ VMULOUB = 445,
+ VMULOUH = 446,
+ VNMSUBFP = 447,
+ VNOR = 448,
+ VOR = 449,
+ VPERM = 450,
+ VPKPX = 451,
+ VPKSHSS = 452,
+ VPKSHUS = 453,
+ VPKSWSS = 454,
+ VPKSWUS = 455,
+ VPKUHUM = 456,
+ VPKUHUS = 457,
+ VPKUWUM = 458,
+ VPKUWUS = 459,
+ VREFP = 460,
+ VRFIM = 461,
+ VRFIN = 462,
+ VRFIP = 463,
+ VRFIZ = 464,
+ VRLB = 465,
+ VRLH = 466,
+ VRLW = 467,
+ VRSQRTEFP = 468,
+ VSEL = 469,
+ VSL = 470,
+ VSLB = 471,
+ VSLDOI = 472,
+ VSLH = 473,
+ VSLO = 474,
+ VSLW = 475,
+ VSPLTB = 476,
+ VSPLTH = 477,
+ VSPLTISB = 478,
+ VSPLTISH = 479,
+ VSPLTISW = 480,
+ VSPLTW = 481,
+ VSR = 482,
+ VSRAB = 483,
+ VSRAH = 484,
+ VSRAW = 485,
+ VSRB = 486,
+ VSRH = 487,
+ VSRO = 488,
+ VSRW = 489,
+ VSUBCUW = 490,
+ VSUBFP = 491,
+ VSUBSBS = 492,
+ VSUBSHS = 493,
+ VSUBSWS = 494,
+ VSUBUBM = 495,
+ VSUBUBS = 496,
+ VSUBUHM = 497,
+ VSUBUHS = 498,
+ VSUBUWM = 499,
+ VSUBUWS = 500,
+ VSUM2SWS = 501,
+ VSUM4SBS = 502,
+ VSUM4SHS = 503,
+ VSUM4UBS = 504,
+ VSUMSWS = 505,
+ VUPKHPX = 506,
+ VUPKHSB = 507,
+ VUPKHSH = 508,
+ VUPKLPX = 509,
+ VUPKLSB = 510,
+ VUPKLSH = 511,
+ VXOR = 512,
+ V_SET0 = 513,
+ XOR = 514,
+ XOR8 = 515,
+ XORI = 516,
+ XORI8 = 517,
+ XORIS = 518,
+ XORIS8 = 519,
+ INSTRUCTION_LIST_END = 520
};
}
} // End llvm namespace
diff --git a/libclamav/c++/X86GenAsmMatcher.inc b/libclamav/c++/X86GenAsmMatcher.inc
index f63d239..12be603 100644
--- a/libclamav/c++/X86GenAsmMatcher.inc
+++ b/libclamav/c++/X86GenAsmMatcher.inc
@@ -59,100 +59,126 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
case 'l': // 1 strings to match.
return 16; // "dl"
case 's': // 1 strings to match.
- return 17; // "ds"
+ return 25; // "ds"
case 'x': // 1 strings to match.
- return 18; // "dx"
+ return 26; // "dx"
}
break;
case 'e': // 1 strings to match.
if (Name[1] != 's')
break;
- return 27; // "es"
+ return 43; // "es"
case 'f': // 1 strings to match.
if (Name[1] != 's')
break;
- return 37; // "fs"
+ return 53; // "fs"
case 'g': // 1 strings to match.
if (Name[1] != 's')
break;
- return 38; // "gs"
+ return 54; // "gs"
case 'i': // 1 strings to match.
if (Name[1] != 'p')
break;
- return 39; // "ip"
+ return 55; // "ip"
case 'r': // 2 strings to match.
switch (Name[1]) {
default: break;
case '8': // 1 strings to match.
- return 72; // "r8"
+ return 88; // "r8"
case '9': // 1 strings to match.
- return 76; // "r9"
+ return 92; // "r9"
}
break;
case 's': // 3 strings to match.
switch (Name[1]) {
default: break;
case 'i': // 1 strings to match.
- return 89; // "si"
+ return 114; // "si"
case 'p': // 1 strings to match.
- return 91; // "sp"
+ return 116; // "sp"
case 's': // 1 strings to match.
- return 93; // "ss"
+ return 118; // "ss"
}
break;
}
break;
- case 3: // 49 strings to match.
+ case 3: // 57 strings to match.
switch (Name[0]) {
default: break;
case 'b': // 1 strings to match.
if (Name.substr(1,2) != "pl")
break;
return 7; // "bpl"
- case 'd': // 1 strings to match.
- if (Name.substr(1,2) != "il")
+ case 'd': // 9 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ if (Name[2] != 'l')
+ break;
+ return 15; // "dil"
+ case 'r': // 8 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 1 strings to match.
+ return 17; // "dr0"
+ case '1': // 1 strings to match.
+ return 18; // "dr1"
+ case '2': // 1 strings to match.
+ return 19; // "dr2"
+ case '3': // 1 strings to match.
+ return 20; // "dr3"
+ case '4': // 1 strings to match.
+ return 21; // "dr4"
+ case '5': // 1 strings to match.
+ return 22; // "dr5"
+ case '6': // 1 strings to match.
+ return 23; // "dr6"
+ case '7': // 1 strings to match.
+ return 24; // "dr7"
+ }
break;
- return 15; // "dil"
+ }
+ break;
case 'e': // 9 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 1 strings to match.
if (Name[2] != 'x')
break;
- return 19; // "eax"
+ return 27; // "eax"
case 'b': // 2 strings to match.
switch (Name[2]) {
default: break;
case 'p': // 1 strings to match.
- return 20; // "ebp"
+ return 28; // "ebp"
case 'x': // 1 strings to match.
- return 21; // "ebx"
+ return 29; // "ebx"
}
break;
case 'c': // 1 strings to match.
if (Name[2] != 'x')
break;
- return 22; // "ecx"
+ return 38; // "ecx"
case 'd': // 2 strings to match.
switch (Name[2]) {
default: break;
case 'i': // 1 strings to match.
- return 23; // "edi"
+ return 39; // "edi"
case 'x': // 1 strings to match.
- return 24; // "edx"
+ return 40; // "edx"
}
break;
case 'i': // 1 strings to match.
if (Name[2] != 'p')
break;
- return 26; // "eip"
+ return 42; // "eip"
case 's': // 2 strings to match.
switch (Name[2]) {
default: break;
case 'i': // 1 strings to match.
- return 28; // "esi"
+ return 44; // "esi"
case 'p': // 1 strings to match.
- return 29; // "esp"
+ return 45; // "esp"
}
break;
}
@@ -163,19 +189,19 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
switch (Name[2]) {
default: break;
case '0': // 1 strings to match.
- return 30; // "fp0"
+ return 46; // "fp0"
case '1': // 1 strings to match.
- return 31; // "fp1"
+ return 47; // "fp1"
case '2': // 1 strings to match.
- return 32; // "fp2"
+ return 48; // "fp2"
case '3': // 1 strings to match.
- return 33; // "fp3"
+ return 49; // "fp3"
case '4': // 1 strings to match.
- return 34; // "fp4"
+ return 50; // "fp4"
case '5': // 1 strings to match.
- return 35; // "fp5"
+ return 51; // "fp5"
case '6': // 1 strings to match.
- return 36; // "fp6"
+ return 52; // "fp6"
}
break;
case 'm': // 8 strings to match.
@@ -184,21 +210,21 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
switch (Name[2]) {
default: break;
case '0': // 1 strings to match.
- return 40; // "mm0"
+ return 56; // "mm0"
case '1': // 1 strings to match.
- return 41; // "mm1"
+ return 57; // "mm1"
case '2': // 1 strings to match.
- return 42; // "mm2"
+ return 58; // "mm2"
case '3': // 1 strings to match.
- return 43; // "mm3"
+ return 59; // "mm3"
case '4': // 1 strings to match.
- return 44; // "mm4"
+ return 60; // "mm4"
case '5': // 1 strings to match.
- return 45; // "mm5"
+ return 61; // "mm5"
case '6': // 1 strings to match.
- return 46; // "mm6"
+ return 62; // "mm6"
case '7': // 1 strings to match.
- return 47; // "mm7"
+ return 63; // "mm7"
}
break;
case 'r': // 21 strings to match.
@@ -208,78 +234,78 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
switch (Name[2]) {
default: break;
case '0': // 1 strings to match.
- return 48; // "r10"
+ return 64; // "r10"
case '1': // 1 strings to match.
- return 52; // "r11"
+ return 68; // "r11"
case '2': // 1 strings to match.
- return 56; // "r12"
+ return 72; // "r12"
case '3': // 1 strings to match.
- return 60; // "r13"
+ return 76; // "r13"
case '4': // 1 strings to match.
- return 64; // "r14"
+ return 80; // "r14"
case '5': // 1 strings to match.
- return 68; // "r15"
+ return 84; // "r15"
}
break;
case '8': // 3 strings to match.
switch (Name[2]) {
default: break;
case 'b': // 1 strings to match.
- return 73; // "r8b"
+ return 89; // "r8b"
case 'd': // 1 strings to match.
- return 74; // "r8d"
+ return 90; // "r8d"
case 'w': // 1 strings to match.
- return 75; // "r8w"
+ return 91; // "r8w"
}
break;
case '9': // 3 strings to match.
switch (Name[2]) {
default: break;
case 'b': // 1 strings to match.
- return 77; // "r9b"
+ return 93; // "r9b"
case 'd': // 1 strings to match.
- return 78; // "r9d"
+ return 94; // "r9d"
case 'w': // 1 strings to match.
- return 79; // "r9w"
+ return 95; // "r9w"
}
break;
case 'a': // 1 strings to match.
if (Name[2] != 'x')
break;
- return 80; // "rax"
+ return 96; // "rax"
case 'b': // 2 strings to match.
switch (Name[2]) {
default: break;
case 'p': // 1 strings to match.
- return 81; // "rbp"
+ return 97; // "rbp"
case 'x': // 1 strings to match.
- return 82; // "rbx"
+ return 98; // "rbx"
}
break;
case 'c': // 1 strings to match.
if (Name[2] != 'x')
break;
- return 83; // "rcx"
+ return 108; // "rcx"
case 'd': // 2 strings to match.
switch (Name[2]) {
default: break;
case 'i': // 1 strings to match.
- return 84; // "rdi"
+ return 109; // "rdi"
case 'x': // 1 strings to match.
- return 85; // "rdx"
+ return 110; // "rdx"
}
break;
case 'i': // 1 strings to match.
if (Name[2] != 'p')
break;
- return 86; // "rip"
+ return 111; // "rip"
case 's': // 2 strings to match.
switch (Name[2]) {
default: break;
case 'i': // 1 strings to match.
- return 87; // "rsi"
+ return 112; // "rsi"
case 'p': // 1 strings to match.
- return 88; // "rsp"
+ return 113; // "rsp"
}
break;
}
@@ -290,87 +316,138 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
case 'i': // 1 strings to match.
if (Name[2] != 'l')
break;
- return 90; // "sil"
+ return 115; // "sil"
case 'p': // 1 strings to match.
if (Name[2] != 'l')
break;
- return 92; // "spl"
+ return 117; // "spl"
}
break;
}
break;
- case 4: // 38 strings to match.
+ case 4: // 55 strings to match.
switch (Name[0]) {
default: break;
- case 'r': // 18 strings to match.
- if (Name[1] != '1')
+ case 'e': // 8 strings to match.
+ if (Name.substr(1,2) != "cr")
break;
- switch (Name[2]) {
+ switch (Name[3]) {
default: break;
- case '0': // 3 strings to match.
- switch (Name[3]) {
- default: break;
- case 'b': // 1 strings to match.
- return 49; // "r10b"
- case 'd': // 1 strings to match.
- return 50; // "r10d"
- case 'w': // 1 strings to match.
- return 51; // "r10w"
- }
- break;
- case '1': // 3 strings to match.
- switch (Name[3]) {
- default: break;
- case 'b': // 1 strings to match.
- return 53; // "r11b"
- case 'd': // 1 strings to match.
- return 54; // "r11d"
- case 'w': // 1 strings to match.
- return 55; // "r11w"
- }
- break;
- case '2': // 3 strings to match.
- switch (Name[3]) {
- default: break;
- case 'b': // 1 strings to match.
- return 57; // "r12b"
- case 'd': // 1 strings to match.
- return 58; // "r12d"
- case 'w': // 1 strings to match.
- return 59; // "r12w"
- }
- break;
- case '3': // 3 strings to match.
- switch (Name[3]) {
- default: break;
- case 'b': // 1 strings to match.
- return 61; // "r13b"
- case 'd': // 1 strings to match.
- return 62; // "r13d"
- case 'w': // 1 strings to match.
- return 63; // "r13w"
- }
- break;
- case '4': // 3 strings to match.
- switch (Name[3]) {
+ case '0': // 1 strings to match.
+ return 30; // "ecr0"
+ case '1': // 1 strings to match.
+ return 31; // "ecr1"
+ case '2': // 1 strings to match.
+ return 32; // "ecr2"
+ case '3': // 1 strings to match.
+ return 33; // "ecr3"
+ case '4': // 1 strings to match.
+ return 34; // "ecr4"
+ case '5': // 1 strings to match.
+ return 35; // "ecr5"
+ case '6': // 1 strings to match.
+ return 36; // "ecr6"
+ case '7': // 1 strings to match.
+ return 37; // "ecr7"
+ }
+ break;
+ case 'r': // 27 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '1': // 18 strings to match.
+ switch (Name[2]) {
default: break;
- case 'b': // 1 strings to match.
- return 65; // "r14b"
- case 'd': // 1 strings to match.
- return 66; // "r14d"
- case 'w': // 1 strings to match.
- return 67; // "r14w"
+ case '0': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 65; // "r10b"
+ case 'd': // 1 strings to match.
+ return 66; // "r10d"
+ case 'w': // 1 strings to match.
+ return 67; // "r10w"
+ }
+ break;
+ case '1': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 69; // "r11b"
+ case 'd': // 1 strings to match.
+ return 70; // "r11d"
+ case 'w': // 1 strings to match.
+ return 71; // "r11w"
+ }
+ break;
+ case '2': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 73; // "r12b"
+ case 'd': // 1 strings to match.
+ return 74; // "r12d"
+ case 'w': // 1 strings to match.
+ return 75; // "r12w"
+ }
+ break;
+ case '3': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 77; // "r13b"
+ case 'd': // 1 strings to match.
+ return 78; // "r13d"
+ case 'w': // 1 strings to match.
+ return 79; // "r13w"
+ }
+ break;
+ case '4': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 81; // "r14b"
+ case 'd': // 1 strings to match.
+ return 82; // "r14d"
+ case 'w': // 1 strings to match.
+ return 83; // "r14w"
+ }
+ break;
+ case '5': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 85; // "r15b"
+ case 'd': // 1 strings to match.
+ return 86; // "r15d"
+ case 'w': // 1 strings to match.
+ return 87; // "r15w"
+ }
+ break;
}
break;
- case '5': // 3 strings to match.
+ case 'c': // 9 strings to match.
+ if (Name[2] != 'r')
+ break;
switch (Name[3]) {
default: break;
- case 'b': // 1 strings to match.
- return 69; // "r15b"
- case 'd': // 1 strings to match.
- return 70; // "r15d"
- case 'w': // 1 strings to match.
- return 71; // "r15w"
+ case '0': // 1 strings to match.
+ return 99; // "rcr0"
+ case '1': // 1 strings to match.
+ return 100; // "rcr1"
+ case '2': // 1 strings to match.
+ return 101; // "rcr2"
+ case '3': // 1 strings to match.
+ return 102; // "rcr3"
+ case '4': // 1 strings to match.
+ return 103; // "rcr4"
+ case '5': // 1 strings to match.
+ return 104; // "rcr5"
+ case '6': // 1 strings to match.
+ return 105; // "rcr6"
+ case '7': // 1 strings to match.
+ return 106; // "rcr7"
+ case '8': // 1 strings to match.
+ return 107; // "rcr8"
}
break;
}
@@ -381,25 +458,25 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
switch (Name[3]) {
default: break;
case '0': // 1 strings to match.
- return 102; // "xmm0"
+ return 127; // "xmm0"
case '1': // 1 strings to match.
- return 103; // "xmm1"
+ return 128; // "xmm1"
case '2': // 1 strings to match.
- return 110; // "xmm2"
+ return 135; // "xmm2"
case '3': // 1 strings to match.
- return 111; // "xmm3"
+ return 136; // "xmm3"
case '4': // 1 strings to match.
- return 112; // "xmm4"
+ return 137; // "xmm4"
case '5': // 1 strings to match.
- return 113; // "xmm5"
+ return 138; // "xmm5"
case '6': // 1 strings to match.
- return 114; // "xmm6"
+ return 139; // "xmm6"
case '7': // 1 strings to match.
- return 115; // "xmm7"
+ return 140; // "xmm7"
case '8': // 1 strings to match.
- return 116; // "xmm8"
+ return 141; // "xmm8"
case '9': // 1 strings to match.
- return 117; // "xmm9"
+ return 142; // "xmm9"
}
break;
case 'y': // 10 strings to match.
@@ -408,25 +485,25 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
switch (Name[3]) {
default: break;
case '0': // 1 strings to match.
- return 118; // "ymm0"
+ return 143; // "ymm0"
case '1': // 1 strings to match.
- return 119; // "ymm1"
+ return 144; // "ymm1"
case '2': // 1 strings to match.
- return 126; // "ymm2"
+ return 151; // "ymm2"
case '3': // 1 strings to match.
- return 127; // "ymm3"
+ return 152; // "ymm3"
case '4': // 1 strings to match.
- return 128; // "ymm4"
+ return 153; // "ymm4"
case '5': // 1 strings to match.
- return 129; // "ymm5"
+ return 154; // "ymm5"
case '6': // 1 strings to match.
- return 130; // "ymm6"
+ return 155; // "ymm6"
case '7': // 1 strings to match.
- return 131; // "ymm7"
+ return 156; // "ymm7"
case '8': // 1 strings to match.
- return 132; // "ymm8"
+ return 157; // "ymm8"
case '9': // 1 strings to match.
- return 133; // "ymm9"
+ return 158; // "ymm9"
}
break;
}
@@ -437,7 +514,7 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
case 'f': // 1 strings to match.
if (Name.substr(1,4) != "lags")
break;
- return 25; // "flags"
+ return 41; // "flags"
case 's': // 8 strings to match.
if (Name.substr(1,2) != "t(")
break;
@@ -446,35 +523,35 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
case '0': // 1 strings to match.
if (Name[4] != ')')
break;
- return 94; // "st(0)"
+ return 119; // "st(0)"
case '1': // 1 strings to match.
if (Name[4] != ')')
break;
- return 95; // "st(1)"
+ return 120; // "st(1)"
case '2': // 1 strings to match.
if (Name[4] != ')')
break;
- return 96; // "st(2)"
+ return 121; // "st(2)"
case '3': // 1 strings to match.
if (Name[4] != ')')
break;
- return 97; // "st(3)"
+ return 122; // "st(3)"
case '4': // 1 strings to match.
if (Name[4] != ')')
break;
- return 98; // "st(4)"
+ return 123; // "st(4)"
case '5': // 1 strings to match.
if (Name[4] != ')')
break;
- return 99; // "st(5)"
+ return 124; // "st(5)"
case '6': // 1 strings to match.
if (Name[4] != ')')
break;
- return 100; // "st(6)"
+ return 125; // "st(6)"
case '7': // 1 strings to match.
if (Name[4] != ')')
break;
- return 101; // "st(7)"
+ return 126; // "st(7)"
}
break;
case 'x': // 6 strings to match.
@@ -483,17 +560,17 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
switch (Name[4]) {
default: break;
case '0': // 1 strings to match.
- return 104; // "xmm10"
+ return 129; // "xmm10"
case '1': // 1 strings to match.
- return 105; // "xmm11"
+ return 130; // "xmm11"
case '2': // 1 strings to match.
- return 106; // "xmm12"
+ return 131; // "xmm12"
case '3': // 1 strings to match.
- return 107; // "xmm13"
+ return 132; // "xmm13"
case '4': // 1 strings to match.
- return 108; // "xmm14"
+ return 133; // "xmm14"
case '5': // 1 strings to match.
- return 109; // "xmm15"
+ return 134; // "xmm15"
}
break;
case 'y': // 6 strings to match.
@@ -502,17 +579,17 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
switch (Name[4]) {
default: break;
case '0': // 1 strings to match.
- return 120; // "ymm10"
+ return 145; // "ymm10"
case '1': // 1 strings to match.
- return 121; // "ymm11"
+ return 146; // "ymm11"
case '2': // 1 strings to match.
- return 122; // "ymm12"
+ return 147; // "ymm12"
case '3': // 1 strings to match.
- return 123; // "ymm13"
+ return 148; // "ymm13"
case '4': // 1 strings to match.
- return 124; // "ymm14"
+ return 149; // "ymm14"
case '5': // 1 strings to match.
- return 125; // "ymm15"
+ return 150; // "ymm15"
}
break;
}
@@ -553,7 +630,8 @@ enum ConversionKind {
Convert_Reg1_2Imp,
Convert_Mem5_2ImpImpImpImpImp,
Convert_Mem5_2_ImpImpImpImpImpImm1_1,
- Convert_ImpMem5_2_Reg1_1,
+ Convert_ImpReg1_1_Reg1_2,
+ Convert_ImpReg1_1_Mem5_2,
Convert_Reg1_3_ImpReg1_2_ImmSExt81_1,
Convert_Reg1_3_ImpMem5_2_ImmSExt81_1,
Convert_Reg1_3_ImpReg1_2,
@@ -697,10 +775,15 @@ static bool ConvertToMCInst(ConversionKind Kind, MCInst &Inst, unsigned Opcode,
Inst.addOperand(MCOperand::CreateReg(0));
Operands[1].addImmOperands(Inst, 1);
break;
- case Convert_ImpMem5_2_Reg1_1:
+ case Convert_ImpReg1_1_Reg1_2:
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[1].addRegOperands(Inst, 1);
+ Operands[2].addRegOperands(Inst, 1);
+ break;
+ case Convert_ImpReg1_1_Mem5_2:
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[2].addMemOperands(Inst, 5);
Operands[1].addRegOperands(Inst, 1);
+ Operands[2].addMemOperands(Inst, 5);
break;
case Convert_Reg1_3_ImpReg1_2_ImmSExt81_1:
Operands[3].addRegOperands(Inst, 1);
@@ -829,30 +912,77 @@ enum MatchClassKind {
MCK_bsrw, // 'bsrw'
MCK_bswapl, // 'bswapl'
MCK_bswapq, // 'bswapq'
+ MCK_btcl, // 'btcl'
+ MCK_btcq, // 'btcq'
+ MCK_btcw, // 'btcw'
MCK_btl, // 'btl'
MCK_btq, // 'btq'
+ MCK_btrl, // 'btrl'
+ MCK_btrq, // 'btrq'
+ MCK_btrw, // 'btrw'
+ MCK_btsl, // 'btsl'
+ MCK_btsq, // 'btsq'
+ MCK_btsw, // 'btsw'
MCK_btw, // 'btw'
MCK_call, // 'call'
+ MCK_callq, // 'callq'
MCK_cbtw, // 'cbtw'
+ MCK_clc, // 'clc'
+ MCK_cld, // 'cld'
MCK_clflush, // 'clflush'
+ MCK_cli, // 'cli'
MCK_cltd, // 'cltd'
MCK_cltq, // 'cltq'
- MCK_cmova, // 'cmova'
- MCK_cmovae, // 'cmovae'
- MCK_cmovb, // 'cmovb'
- MCK_cmovbe, // 'cmovbe'
- MCK_cmove, // 'cmove'
- MCK_cmovg, // 'cmovg'
- MCK_cmovge, // 'cmovge'
- MCK_cmovl, // 'cmovl'
- MCK_cmovle, // 'cmovle'
- MCK_cmovne, // 'cmovne'
- MCK_cmovno, // 'cmovno'
- MCK_cmovnp, // 'cmovnp'
- MCK_cmovns, // 'cmovns'
- MCK_cmovo, // 'cmovo'
- MCK_cmovp, // 'cmovp'
- MCK_cmovs, // 'cmovs'
+ MCK_clts, // 'clts'
+ MCK_cmc, // 'cmc'
+ MCK_cmovael, // 'cmovael'
+ MCK_cmovaeq, // 'cmovaeq'
+ MCK_cmovaew, // 'cmovaew'
+ MCK_cmoval, // 'cmoval'
+ MCK_cmovaq, // 'cmovaq'
+ MCK_cmovaw, // 'cmovaw'
+ MCK_cmovbel, // 'cmovbel'
+ MCK_cmovbeq, // 'cmovbeq'
+ MCK_cmovbew, // 'cmovbew'
+ MCK_cmovbl, // 'cmovbl'
+ MCK_cmovbq, // 'cmovbq'
+ MCK_cmovbw, // 'cmovbw'
+ MCK_cmovel, // 'cmovel'
+ MCK_cmoveq, // 'cmoveq'
+ MCK_cmovew, // 'cmovew'
+ MCK_cmovgel, // 'cmovgel'
+ MCK_cmovgeq, // 'cmovgeq'
+ MCK_cmovgew, // 'cmovgew'
+ MCK_cmovgl, // 'cmovgl'
+ MCK_cmovgq, // 'cmovgq'
+ MCK_cmovgw, // 'cmovgw'
+ MCK_cmovlel, // 'cmovlel'
+ MCK_cmovleq, // 'cmovleq'
+ MCK_cmovlew, // 'cmovlew'
+ MCK_cmovll, // 'cmovll'
+ MCK_cmovlq, // 'cmovlq'
+ MCK_cmovlw, // 'cmovlw'
+ MCK_cmovnel, // 'cmovnel'
+ MCK_cmovneq, // 'cmovneq'
+ MCK_cmovnew, // 'cmovnew'
+ MCK_cmovnol, // 'cmovnol'
+ MCK_cmovnoq, // 'cmovnoq'
+ MCK_cmovnow, // 'cmovnow'
+ MCK_cmovnpl, // 'cmovnpl'
+ MCK_cmovnpq, // 'cmovnpq'
+ MCK_cmovnpw, // 'cmovnpw'
+ MCK_cmovnsl, // 'cmovnsl'
+ MCK_cmovnsq, // 'cmovnsq'
+ MCK_cmovnsw, // 'cmovnsw'
+ MCK_cmovol, // 'cmovol'
+ MCK_cmovoq, // 'cmovoq'
+ MCK_cmovow, // 'cmovow'
+ MCK_cmovpl, // 'cmovpl'
+ MCK_cmovpq, // 'cmovpq'
+ MCK_cmovpw, // 'cmovpw'
+ MCK_cmovsl, // 'cmovsl'
+ MCK_cmovsq, // 'cmovsq'
+ MCK_cmovsw, // 'cmovsw'
MCK_cmp, // 'cmp'
MCK_cmpb, // 'cmpb'
MCK_cmpl, // 'cmpl'
@@ -862,24 +992,38 @@ enum MatchClassKind {
MCK_cmpsq, // 'cmpsq'
MCK_cmpsw, // 'cmpsw'
MCK_cmpw, // 'cmpw'
+ MCK_cmpxchg16b, // 'cmpxchg16b'
+ MCK_cmpxchg8b, // 'cmpxchg8b'
+ MCK_cmpxchgb, // 'cmpxchgb'
+ MCK_cmpxchgl, // 'cmpxchgl'
+ MCK_cmpxchgq, // 'cmpxchgq'
+ MCK_cmpxchgw, // 'cmpxchgw'
MCK_comisd, // 'comisd'
+ MCK_comiss, // 'comiss'
+ MCK_cpuid, // 'cpuid'
MCK_cqto, // 'cqto'
MCK_crc32, // 'crc32'
MCK_cvtdq2pd, // 'cvtdq2pd'
MCK_cvtdq2ps, // 'cvtdq2ps'
MCK_cvtpd2dq, // 'cvtpd2dq'
MCK_cvtpd2pi, // 'cvtpd2pi'
+ MCK_cvtpd2ps, // 'cvtpd2ps'
MCK_cvtpi2pd, // 'cvtpi2pd'
MCK_cvtpi2ps, // 'cvtpi2ps'
MCK_cvtps2dq, // 'cvtps2dq'
+ MCK_cvtps2pd, // 'cvtps2pd'
MCK_cvtps2pi, // 'cvtps2pi'
+ MCK_cvtsd2siq, // 'cvtsd2siq'
MCK_cvtsd2ss, // 'cvtsd2ss'
MCK_cvtsi2sd, // 'cvtsi2sd'
MCK_cvtsi2sdq, // 'cvtsi2sdq'
MCK_cvtsi2ss, // 'cvtsi2ss'
MCK_cvtsi2ssq, // 'cvtsi2ssq'
MCK_cvtss2sd, // 'cvtss2sd'
+ MCK_cvtss2sil, // 'cvtss2sil'
+ MCK_cvtss2siq, // 'cvtss2siq'
MCK_cvttpd2pi, // 'cvttpd2pi'
+ MCK_cvttps2dq, // 'cvttps2dq'
MCK_cvttps2pi, // 'cvttps2pi'
MCK_cvttsd2si, // 'cvttsd2si'
MCK_cvttsd2siq, // 'cvttsd2siq'
@@ -904,6 +1048,7 @@ enum MatchClassKind {
MCK_emms, // 'emms'
MCK_enter, // 'enter'
MCK_extractps, // 'extractps'
+ MCK_f2xm1, // 'f2xm1'
MCK_fabs, // 'fabs'
MCK_fadd, // 'fadd'
MCK_faddl, // 'faddl'
@@ -921,8 +1066,16 @@ enum MatchClassKind {
MCK_fcmovnu, // 'fcmovnu'
MCK_fcmovu, // 'fcmovu'
MCK_fcom, // 'fcom'
+ MCK_fcomi, // 'fcomi'
+ MCK_fcomip, // 'fcomip'
+ MCK_fcoml, // 'fcoml'
+ MCK_fcomll, // 'fcomll'
MCK_fcomp, // 'fcomp'
+ MCK_fcompl, // 'fcompl'
+ MCK_fcompll, // 'fcompll'
+ MCK_fcompp, // 'fcompp'
MCK_fcos, // 'fcos'
+ MCK_fdecstp, // 'fdecstp'
MCK_fdiv, // 'fdiv'
MCK_fdivl, // 'fdivl'
MCK_fdivp, // 'fdivp'
@@ -932,6 +1085,7 @@ enum MatchClassKind {
MCK_fdivrs, // 'fdivrs'
MCK_fdivs, // 'fdivs'
MCK_femms, // 'femms'
+ MCK_ffree, // 'ffree'
MCK_fiaddl, // 'fiaddl'
MCK_fiadds, // 'fiadds'
MCK_ficoml, // 'ficoml'
@@ -947,6 +1101,7 @@ enum MatchClassKind {
MCK_filds, // 'filds'
MCK_fimull, // 'fimull'
MCK_fimuls, // 'fimuls'
+ MCK_fincstp, // 'fincstp'
MCK_fistl, // 'fistl'
MCK_fistpl, // 'fistpl'
MCK_fistpll, // 'fistpll'
@@ -964,6 +1119,11 @@ enum MatchClassKind {
MCK_fldcw, // 'fldcw'
MCK_fldenv, // 'fldenv'
MCK_fldl, // 'fldl'
+ MCK_fldl2e, // 'fldl2e'
+ MCK_fldl2t, // 'fldl2t'
+ MCK_fldlg2, // 'fldlg2'
+ MCK_fldln2, // 'fldln2'
+ MCK_fldpi, // 'fldpi'
MCK_flds, // 'flds'
MCK_fldt, // 'fldt'
MCK_fldz, // 'fldz'
@@ -971,21 +1131,30 @@ enum MatchClassKind {
MCK_fmull, // 'fmull'
MCK_fmulp, // 'fmulp'
MCK_fmuls, // 'fmuls'
+ MCK_fnclex, // 'fnclex'
+ MCK_fninit, // 'fninit'
+ MCK_fnop, // 'fnop'
+ MCK_fnsave, // 'fnsave'
MCK_fnstcw, // 'fnstcw'
+ MCK_fnstenv, // 'fnstenv'
MCK_fnstsw, // 'fnstsw'
+ MCK_fpatan, // 'fpatan'
+ MCK_fprem, // 'fprem'
+ MCK_fprem1, // 'fprem1'
+ MCK_fptan, // 'fptan'
+ MCK_frndint, // 'frndint'
MCK_frstor, // 'frstor'
- MCK_fsave, // 'fsave'
+ MCK_fscale, // 'fscale'
MCK_fsin, // 'fsin'
+ MCK_fsincos, // 'fsincos'
MCK_fsqrt, // 'fsqrt'
MCK_fst, // 'fst'
- MCK_fstenv, // 'fstenv'
MCK_fstl, // 'fstl'
MCK_fstp, // 'fstp'
MCK_fstpl, // 'fstpl'
MCK_fstps, // 'fstps'
MCK_fstpt, // 'fstpt'
MCK_fsts, // 'fsts'
- MCK_fstsw, // 'fstsw'
MCK_fsub, // 'fsub'
MCK_fsubl, // 'fsubl'
MCK_fsubp, // 'fsubp'
@@ -1000,9 +1169,16 @@ enum MatchClassKind {
MCK_fucomip, // 'fucomip'
MCK_fucomp, // 'fucomp'
MCK_fucompp, // 'fucompp'
+ MCK_fxam, // 'fxam'
MCK_fxch, // 'fxch'
+ MCK_fxrstor, // 'fxrstor'
+ MCK_fxsave, // 'fxsave'
+ MCK_fxtract, // 'fxtract'
+ MCK_fyl2x, // 'fyl2x'
+ MCK_fyl2xp1, // 'fyl2xp1'
MCK_haddpd, // 'haddpd'
MCK_haddps, // 'haddps'
+ MCK_hlt, // 'hlt'
MCK_hsubpd, // 'hsubpd'
MCK_hsubps, // 'hsubps'
MCK_idivb, // 'idivb'
@@ -1019,9 +1195,19 @@ enum MatchClassKind {
MCK_incq, // 'incq'
MCK_incw, // 'incw'
MCK_inl, // 'inl'
+ MCK_insb, // 'insb'
MCK_insertps, // 'insertps'
+ MCK_insl, // 'insl'
+ MCK_insw, // 'insw'
MCK_int, // 'int'
+ MCK_invd, // 'invd'
+ MCK_invept, // 'invept'
+ MCK_invlpg, // 'invlpg'
+ MCK_invvpid, // 'invvpid'
MCK_inw, // 'inw'
+ MCK_iretl, // 'iretl'
+ MCK_iretq, // 'iretq'
+ MCK_iretw, // 'iretw'
MCK_ja, // 'ja'
MCK_jae, // 'jae'
MCK_jb, // 'jb'
@@ -1051,22 +1237,43 @@ enum MatchClassKind {
MCK_lcallw, // 'lcallw'
MCK_lddqu, // 'lddqu'
MCK_ldmxcsr, // 'ldmxcsr'
+ MCK_ldsl, // 'ldsl'
+ MCK_ldsw, // 'ldsw'
MCK_leal, // 'leal'
MCK_leaq, // 'leaq'
MCK_leave, // 'leave'
MCK_leaw, // 'leaw'
+ MCK_lesl, // 'lesl'
+ MCK_lesw, // 'lesw'
MCK_lfence, // 'lfence'
+ MCK_lfsl, // 'lfsl'
+ MCK_lfsq, // 'lfsq'
+ MCK_lfsw, // 'lfsw'
+ MCK_lgdt, // 'lgdt'
+ MCK_lgsl, // 'lgsl'
+ MCK_lgsq, // 'lgsq'
+ MCK_lgsw, // 'lgsw'
+ MCK_lidt, // 'lidt'
MCK_ljmpl, // 'ljmpl'
MCK_ljmpq, // 'ljmpq'
MCK_ljmpw, // 'ljmpw'
+ MCK_lldtw, // 'lldtw'
+ MCK_lmsww, // 'lmsww'
MCK_lodsb, // 'lodsb'
- MCK_lodsd, // 'lodsd'
+ MCK_lodsl, // 'lodsl'
MCK_lodsq, // 'lodsq'
MCK_lodsw, // 'lodsw'
MCK_loop, // 'loop'
MCK_loope, // 'loope'
MCK_loopne, // 'loopne'
MCK_lret, // 'lret'
+ MCK_lsll, // 'lsll'
+ MCK_lslq, // 'lslq'
+ MCK_lslw, // 'lslw'
+ MCK_lssl, // 'lssl'
+ MCK_lssq, // 'lssq'
+ MCK_lssw, // 'lssw'
+ MCK_ltrw, // 'ltrw'
MCK_maskmovdqu, // 'maskmovdqu'
MCK_maskmovq, // 'maskmovq'
MCK_maxpd, // 'maxpd'
@@ -1107,6 +1314,7 @@ enum MatchClassKind {
MCK_movq2dq, // 'movq2dq'
MCK_movsbl, // 'movsbl'
MCK_movsbq, // 'movsbq'
+ MCK_movsbw, // 'movsbw'
MCK_movsd, // 'movsd'
MCK_movshdup, // 'movshdup'
MCK_movsldup, // 'movsldup'
@@ -1118,7 +1326,10 @@ enum MatchClassKind {
MCK_movups, // 'movups'
MCK_movw, // 'movw'
MCK_movzbl, // 'movzbl'
+ MCK_movzbq, // 'movzbq'
+ MCK_movzbw, // 'movzbw'
MCK_movzwl, // 'movzwl'
+ MCK_movzwq, // 'movzwq'
MCK_mpsadbw, // 'mpsadbw'
MCK_mulb, // 'mulb'
MCK_mull, // 'mull'
@@ -1135,6 +1346,7 @@ enum MatchClassKind {
MCK_negw, // 'negw'
MCK_nop, // 'nop'
MCK_nopl, // 'nopl'
+ MCK_nopw, // 'nopw'
MCK_notb, // 'notb'
MCK_notl, // 'notl'
MCK_notq, // 'notq'
@@ -1147,6 +1359,9 @@ enum MatchClassKind {
MCK_orw, // 'orw'
MCK_outb, // 'outb'
MCK_outl, // 'outl'
+ MCK_outsb, // 'outsb'
+ MCK_outsl, // 'outsl'
+ MCK_outsw, // 'outsw'
MCK_outw, // 'outw'
MCK_pabsb, // 'pabsb'
MCK_pabsd, // 'pabsd'
@@ -1232,7 +1447,12 @@ enum MatchClassKind {
MCK_pmulld, // 'pmulld'
MCK_pmullw, // 'pmullw'
MCK_pmuludq, // 'pmuludq'
- MCK_popf, // 'popf'
+ MCK_popcntl, // 'popcntl'
+ MCK_popcntq, // 'popcntq'
+ MCK_popcntw, // 'popcntw'
+ MCK_popfl, // 'popfl'
+ MCK_popfq, // 'popfq'
+ MCK_popfw, // 'popfw'
MCK_popl, // 'popl'
MCK_popq, // 'popq'
MCK_popw, // 'popw'
@@ -1278,7 +1498,9 @@ enum MatchClassKind {
MCK_punpckldq, // 'punpckldq'
MCK_punpcklqdq, // 'punpcklqdq'
MCK_punpcklwd, // 'punpcklwd'
- MCK_pushf, // 'pushf'
+ MCK_pushfl, // 'pushfl'
+ MCK_pushfq, // 'pushfq'
+ MCK_pushfw, // 'pushfw'
MCK_pushl, // 'pushl'
MCK_pushq, // 'pushq'
MCK_pushw, // 'pushw'
@@ -1293,6 +1515,8 @@ enum MatchClassKind {
MCK_rcrl, // 'rcrl'
MCK_rcrq, // 'rcrq'
MCK_rcrw, // 'rcrw'
+ MCK_rdmsr, // 'rdmsr'
+ MCK_rdpmc, // 'rdpmc'
MCK_rdtsc, // 'rdtsc'
MCK_rep_59_movsb, // 'rep;movsb'
MCK_rep_59_movsl, // 'rep;movsl'
@@ -1311,6 +1535,7 @@ enum MatchClassKind {
MCK_rorl, // 'rorl'
MCK_rorq, // 'rorq'
MCK_rorw, // 'rorw'
+ MCK_rsm, // 'rsm'
MCK_rsqrtps, // 'rsqrtps'
MCK_rsqrtss, // 'rsqrtss'
MCK_sahf, // 'sahf'
@@ -1344,6 +1569,7 @@ enum MatchClassKind {
MCK_setp, // 'setp'
MCK_sets, // 'sets'
MCK_sfence, // 'sfence'
+ MCK_sgdt, // 'sgdt'
MCK_shlb, // 'shlb'
MCK_shldl, // 'shldl'
MCK_shldq, // 'shldq'
@@ -1360,12 +1586,22 @@ enum MatchClassKind {
MCK_shrw, // 'shrw'
MCK_shufpd, // 'shufpd'
MCK_shufps, // 'shufps'
+ MCK_sidt, // 'sidt'
+ MCK_sldtq, // 'sldtq'
+ MCK_sldtw, // 'sldtw'
+ MCK_smswl, // 'smswl'
+ MCK_smswq, // 'smswq'
+ MCK_smsww, // 'smsww'
MCK_sqrtpd, // 'sqrtpd'
MCK_sqrtps, // 'sqrtps'
MCK_sqrtsd, // 'sqrtsd'
MCK_sqrtss, // 'sqrtss'
MCK_ss, // 'ss'
+ MCK_stc, // 'stc'
+ MCK_std, // 'std'
+ MCK_sti, // 'sti'
MCK_stmxcsr, // 'stmxcsr'
+ MCK_strw, // 'strw'
MCK_subb, // 'subb'
MCK_subl, // 'subl'
MCK_subpd, // 'subpd'
@@ -1374,6 +1610,7 @@ enum MatchClassKind {
MCK_subsd, // 'subsd'
MCK_subss, // 'subss'
MCK_subw, // 'subw'
+ MCK_swpgs, // 'swpgs'
MCK_syscall, // 'syscall'
MCK_sysenter, // 'sysenter'
MCK_sysexit, // 'sysexit'
@@ -1389,11 +1626,32 @@ enum MatchClassKind {
MCK_unpckhps, // 'unpckhps'
MCK_unpcklpd, // 'unpcklpd'
MCK_unpcklps, // 'unpcklps'
+ MCK_verr, // 'verr'
+ MCK_verw, // 'verw'
+ MCK_vmcall, // 'vmcall'
+ MCK_vmclear, // 'vmclear'
+ MCK_vmlaunch, // 'vmlaunch'
+ MCK_vmptrld, // 'vmptrld'
+ MCK_vmptrst, // 'vmptrst'
+ MCK_vmreadl, // 'vmreadl'
+ MCK_vmreadq, // 'vmreadq'
+ MCK_vmresume, // 'vmresume'
+ MCK_vmwritel, // 'vmwritel'
+ MCK_vmwriteq, // 'vmwriteq'
+ MCK_vmxoff, // 'vmxoff'
+ MCK_vmxon, // 'vmxon'
MCK_wait, // 'wait'
- MCK_xchg, // 'xchg'
+ MCK_wbinvd, // 'wbinvd'
+ MCK_wrmsr, // 'wrmsr'
+ MCK_xaddb, // 'xaddb'
+ MCK_xaddl, // 'xaddl'
+ MCK_xaddq, // 'xaddq'
+ MCK_xaddw, // 'xaddw'
MCK_xchgb, // 'xchgb'
MCK_xchgl, // 'xchgl'
+ MCK_xchgq, // 'xchgq'
MCK_xchgw, // 'xchgw'
+ MCK_xlatb, // 'xlatb'
MCK_xorb, // 'xorb'
MCK_xorl, // 'xorl'
MCK_xorpd, // 'xorpd'
@@ -1421,8 +1679,8 @@ enum MatchClassKind {
MCK_RAX, // register class 'RAX'
MCK_GR64_ABCD, // register class 'GR64_ABCD'
MCK_GR64_NOREX_NOSP, // register class 'GR64_NOREX_NOSP'
- MCK_GR64_NOREX, // register class 'GR64_NOREX'
MCK_GR64_NOSP, // register class 'GR64_NOSP'
+ MCK_GR64_NOREX, // register class 'GR64_NOREX'
MCK_GR64, // register class 'GR64'
MCK_VR64, // register class 'VR64'
MCK_RFP32, // register class 'RFP32,RFP64,RFP80'
@@ -1432,7 +1690,12 @@ enum MatchClassKind {
MCK_ST0, // register class 'ST0'
MCK_RST, // register class 'RST'
MCK_CCR, // register class 'CCR'
+ MCK_FS, // register class 'FS'
+ MCK_GS, // register class 'GS'
MCK_SEGMENT_REG, // register class 'SEGMENT_REG'
+ MCK_DEBUG_REG, // register class 'DEBUG_REG'
+ MCK_CONTROL_REG_32, // register class 'CONTROL_REG_32'
+ MCK_CONTROL_REG_64, // register class 'CONTROL_REG_64'
MCK_ImmSExt8, // user defined class 'ImmSExt8AsmOperand'
MCK_Imm, // user defined class 'ImmAsmOperand'
MCK_Mem, // user defined class 'X86MemAsmOperand'
@@ -1499,7 +1762,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 3: // 27 strings to match.
+ case 3: // 36 strings to match.
switch (Name[0]) {
default: break;
case 'b': // 3 strings to match.
@@ -1515,10 +1778,31 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_btw; // "btw"
}
break;
- case 'c': // 1 strings to match.
- if (Name.substr(1,2) != "mp")
+ case 'c': // 5 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'l': // 3 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ return MCK_clc; // "clc"
+ case 'd': // 1 strings to match.
+ return MCK_cld; // "cld"
+ case 'i': // 1 strings to match.
+ return MCK_cli; // "cli"
+ }
+ break;
+ case 'm': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ return MCK_cmc; // "cmc"
+ case 'p': // 1 strings to match.
+ return MCK_cmp; // "cmp"
+ }
break;
- return MCK_cmp; // "cmp"
+ }
+ break;
case 'f': // 2 strings to match.
switch (Name[1]) {
default: break;
@@ -1532,6 +1816,10 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_fst; // "fst"
}
break;
+ case 'h': // 1 strings to match.
+ if (Name.substr(1,2) != "lt")
+ break;
+ return MCK_hlt; // "hlt"
case 'i': // 4 strings to match.
if (Name[1] != 'n')
break;
@@ -1608,17 +1896,39 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(1,2) != "or")
break;
return MCK_por; // "por"
- case 'r': // 1 strings to match.
- if (Name.substr(1,2) != "et")
+ case 'r': // 2 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'e': // 1 strings to match.
+ if (Name[2] != 't')
+ break;
+ return MCK_ret; // "ret"
+ case 's': // 1 strings to match.
+ if (Name[2] != 'm')
+ break;
+ return MCK_rsm; // "rsm"
+ }
+ break;
+ case 's': // 3 strings to match.
+ if (Name[1] != 't')
break;
- return MCK_ret; // "ret"
+ switch (Name[2]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ return MCK_stc; // "stc"
+ case 'd': // 1 strings to match.
+ return MCK_std; // "std"
+ case 'i': // 1 strings to match.
+ return MCK_sti; // "sti"
+ }
+ break;
case 'u': // 1 strings to match.
if (Name.substr(1,2) != "d2")
break;
return MCK_ud2; // "ud2"
}
break;
- case 4: // 156 strings to match.
+ case 4: // 195 strings to match.
switch (Name[0]) {
default: break;
case 'a': // 12 strings to match.
@@ -1672,36 +1982,77 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'b': // 6 strings to match.
- if (Name[1] != 's')
- break;
- switch (Name[2]) {
+ case 'b': // 15 strings to match.
+ switch (Name[1]) {
default: break;
- case 'f': // 3 strings to match.
- switch (Name[3]) {
+ case 's': // 6 strings to match.
+ switch (Name[2]) {
default: break;
- case 'l': // 1 strings to match.
- return MCK_bsfl; // "bsfl"
- case 'q': // 1 strings to match.
- return MCK_bsfq; // "bsfq"
- case 'w': // 1 strings to match.
- return MCK_bsfw; // "bsfw"
+ case 'f': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_bsfl; // "bsfl"
+ case 'q': // 1 strings to match.
+ return MCK_bsfq; // "bsfq"
+ case 'w': // 1 strings to match.
+ return MCK_bsfw; // "bsfw"
+ }
+ break;
+ case 'r': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_bsrl; // "bsrl"
+ case 'q': // 1 strings to match.
+ return MCK_bsrq; // "bsrq"
+ case 'w': // 1 strings to match.
+ return MCK_bsrw; // "bsrw"
+ }
+ break;
}
break;
- case 'r': // 3 strings to match.
- switch (Name[3]) {
+ case 't': // 9 strings to match.
+ switch (Name[2]) {
default: break;
- case 'l': // 1 strings to match.
- return MCK_bsrl; // "bsrl"
- case 'q': // 1 strings to match.
- return MCK_bsrq; // "bsrq"
- case 'w': // 1 strings to match.
- return MCK_bsrw; // "bsrw"
+ case 'c': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_btcl; // "btcl"
+ case 'q': // 1 strings to match.
+ return MCK_btcq; // "btcq"
+ case 'w': // 1 strings to match.
+ return MCK_btcw; // "btcw"
+ }
+ break;
+ case 'r': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_btrl; // "btrl"
+ case 'q': // 1 strings to match.
+ return MCK_btrq; // "btrq"
+ case 'w': // 1 strings to match.
+ return MCK_btrw; // "btrw"
+ }
+ break;
+ case 's': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_btsl; // "btsl"
+ case 'q': // 1 strings to match.
+ return MCK_btsq; // "btsq"
+ case 'w': // 1 strings to match.
+ return MCK_btsw; // "btsw"
+ }
+ break;
}
break;
}
break;
- case 'c': // 11 strings to match.
+ case 'c': // 12 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 1 strings to match.
@@ -1712,7 +2063,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(2,2) != "tw")
break;
return MCK_cbtw; // "cbtw"
- case 'l': // 2 strings to match.
+ case 'l': // 3 strings to match.
if (Name[2] != 't')
break;
switch (Name[3]) {
@@ -1721,6 +2072,8 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_cltd; // "cltd"
case 'q': // 1 strings to match.
return MCK_cltq; // "cltq"
+ case 's': // 1 strings to match.
+ return MCK_clts; // "clts"
}
break;
case 'm': // 4 strings to match.
@@ -1805,7 +2158,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(1,3) != "mms")
break;
return MCK_emms; // "emms"
- case 'f': // 20 strings to match.
+ case 'f': // 22 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 2 strings to match.
@@ -1868,6 +2221,10 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(2,2) != "ul")
break;
return MCK_fmul; // "fmul"
+ case 'n': // 1 strings to match.
+ if (Name.substr(2,2) != "op")
+ break;
+ return MCK_fnop; // "fnop"
case 's': // 5 strings to match.
switch (Name[2]) {
default: break;
@@ -1896,25 +2253,54 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(2,2) != "st")
break;
return MCK_ftst; // "ftst"
- case 'x': // 1 strings to match.
- if (Name.substr(2,2) != "ch")
- break;
- return MCK_fxch; // "fxch"
+ case 'x': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name[3] != 'm')
+ break;
+ return MCK_fxam; // "fxam"
+ case 'c': // 1 strings to match.
+ if (Name[3] != 'h')
+ break;
+ return MCK_fxch; // "fxch"
+ }
+ break;
}
break;
- case 'i': // 4 strings to match.
- if (Name.substr(1,2) != "nc")
+ case 'i': // 8 strings to match.
+ if (Name[1] != 'n')
break;
- switch (Name[3]) {
+ switch (Name[2]) {
default: break;
- case 'b': // 1 strings to match.
- return MCK_incb; // "incb"
- case 'l': // 1 strings to match.
- return MCK_incl; // "incl"
- case 'q': // 1 strings to match.
- return MCK_incq; // "incq"
- case 'w': // 1 strings to match.
- return MCK_incw; // "incw"
+ case 'c': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_incb; // "incb"
+ case 'l': // 1 strings to match.
+ return MCK_incl; // "incl"
+ case 'q': // 1 strings to match.
+ return MCK_incq; // "incq"
+ case 'w': // 1 strings to match.
+ return MCK_incw; // "incw"
+ }
+ break;
+ case 's': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_insb; // "insb"
+ case 'l': // 1 strings to match.
+ return MCK_insl; // "insl"
+ case 'w': // 1 strings to match.
+ return MCK_insw; // "insw"
+ }
+ break;
+ case 'v': // 1 strings to match.
+ if (Name[3] != 'd')
+ break;
+ return MCK_invd; // "invd"
}
break;
case 'j': // 3 strings to match.
@@ -1937,7 +2323,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'l': // 9 strings to match.
+ case 'l': // 28 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 4 strings to match.
@@ -1960,19 +2346,79 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'e': // 3 strings to match.
- if (Name[2] != 'a')
+ case 'd': // 2 strings to match.
+ if (Name[2] != 's')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_ldsl; // "ldsl"
+ case 'w': // 1 strings to match.
+ return MCK_ldsw; // "ldsw"
+ }
+ break;
+ case 'e': // 5 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'a': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_leal; // "leal"
+ case 'q': // 1 strings to match.
+ return MCK_leaq; // "leaq"
+ case 'w': // 1 strings to match.
+ return MCK_leaw; // "leaw"
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_lesl; // "lesl"
+ case 'w': // 1 strings to match.
+ return MCK_lesw; // "lesw"
+ }
+ break;
+ }
+ break;
+ case 'f': // 3 strings to match.
+ if (Name[2] != 's')
break;
switch (Name[3]) {
default: break;
case 'l': // 1 strings to match.
- return MCK_leal; // "leal"
+ return MCK_lfsl; // "lfsl"
case 'q': // 1 strings to match.
- return MCK_leaq; // "leaq"
+ return MCK_lfsq; // "lfsq"
case 'w': // 1 strings to match.
- return MCK_leaw; // "leaw"
+ return MCK_lfsw; // "lfsw"
+ }
+ break;
+ case 'g': // 4 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[3] != 't')
+ break;
+ return MCK_lgdt; // "lgdt"
+ case 's': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_lgsl; // "lgsl"
+ case 'q': // 1 strings to match.
+ return MCK_lgsq; // "lgsq"
+ case 'w': // 1 strings to match.
+ return MCK_lgsw; // "lgsw"
+ }
+ break;
}
break;
+ case 'i': // 1 strings to match.
+ if (Name.substr(2,2) != "dt")
+ break;
+ return MCK_lidt; // "lidt"
case 'o': // 1 strings to match.
if (Name.substr(2,2) != "op")
break;
@@ -1981,6 +2427,37 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(2,2) != "et")
break;
return MCK_lret; // "lret"
+ case 's': // 6 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'l': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_lsll; // "lsll"
+ case 'q': // 1 strings to match.
+ return MCK_lslq; // "lslq"
+ case 'w': // 1 strings to match.
+ return MCK_lslw; // "lslw"
+ }
+ break;
+ case 's': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_lssl; // "lssl"
+ case 'q': // 1 strings to match.
+ return MCK_lssq; // "lssq"
+ case 'w': // 1 strings to match.
+ return MCK_lssw; // "lssw"
+ }
+ break;
+ }
+ break;
+ case 't': // 1 strings to match.
+ if (Name.substr(2,2) != "rw")
+ break;
+ return MCK_ltrw; // "ltrw"
}
break;
case 'm': // 9 strings to match.
@@ -2020,7 +2497,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'n': // 9 strings to match.
+ case 'n': // 10 strings to match.
switch (Name[1]) {
default: break;
case 'e': // 4 strings to match.
@@ -2038,13 +2515,18 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_negw; // "negw"
}
break;
- case 'o': // 5 strings to match.
+ case 'o': // 6 strings to match.
switch (Name[2]) {
default: break;
- case 'p': // 1 strings to match.
- if (Name[3] != 'l')
- break;
- return MCK_nopl; // "nopl"
+ case 'p': // 2 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_nopl; // "nopl"
+ case 'w': // 1 strings to match.
+ return MCK_nopw; // "nopw"
+ }
+ break;
case 't': // 4 strings to match.
switch (Name[3]) {
default: break;
@@ -2091,20 +2573,18 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'p': // 6 strings to match.
+ case 'p': // 5 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 1 strings to match.
if (Name.substr(2,2) != "nd")
break;
return MCK_pand; // "pand"
- case 'o': // 4 strings to match.
+ case 'o': // 3 strings to match.
if (Name[2] != 'p')
break;
switch (Name[3]) {
default: break;
- case 'f': // 1 strings to match.
- return MCK_popf; // "popf"
case 'l': // 1 strings to match.
return MCK_popl; // "popl"
case 'q': // 1 strings to match.
@@ -2186,7 +2666,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 's': // 29 strings to match.
+ case 's': // 32 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 5 strings to match.
@@ -2249,6 +2729,10 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_sets; // "sets"
}
break;
+ case 'g': // 1 strings to match.
+ if (Name.substr(2,2) != "dt")
+ break;
+ return MCK_sgdt; // "sgdt"
case 'h': // 8 strings to match.
switch (Name[2]) {
default: break;
@@ -2280,6 +2764,14 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
+ case 'i': // 1 strings to match.
+ if (Name.substr(2,2) != "dt")
+ break;
+ return MCK_sidt; // "sidt"
+ case 't': // 1 strings to match.
+ if (Name.substr(2,2) != "rw")
+ break;
+ return MCK_strw; // "strw"
case 'u': // 4 strings to match.
if (Name[2] != 'b')
break;
@@ -2297,37 +2789,39 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
+ case 'v': // 2 strings to match.
+ if (Name.substr(1,2) != "er")
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'r': // 1 strings to match.
+ return MCK_verr; // "verr"
+ case 'w': // 1 strings to match.
+ return MCK_verw; // "verw"
+ }
+ break;
case 'w': // 1 strings to match.
if (Name.substr(1,3) != "ait")
break;
return MCK_wait; // "wait"
- case 'x': // 5 strings to match.
- switch (Name[1]) {
- default: break;
- case 'c': // 1 strings to match.
- if (Name.substr(2,2) != "hg")
- break;
- return MCK_xchg; // "xchg"
- case 'o': // 4 strings to match.
- if (Name[2] != 'r')
- break;
- switch (Name[3]) {
- default: break;
- case 'b': // 1 strings to match.
- return MCK_xorb; // "xorb"
- case 'l': // 1 strings to match.
- return MCK_xorl; // "xorl"
- case 'q': // 1 strings to match.
- return MCK_xorq; // "xorq"
- case 'w': // 1 strings to match.
- return MCK_xorw; // "xorw"
- }
+ case 'x': // 4 strings to match.
+ if (Name.substr(1,2) != "or")
break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_xorb; // "xorb"
+ case 'l': // 1 strings to match.
+ return MCK_xorl; // "xorl"
+ case 'q': // 1 strings to match.
+ return MCK_xorq; // "xorq"
+ case 'w': // 1 strings to match.
+ return MCK_xorw; // "xorw"
}
break;
}
break;
- case 5: // 147 strings to match.
+ case 5: // 173 strings to match.
switch (Name[0]) {
default: break;
case 'a': // 6 strings to match.
@@ -2371,52 +2865,32 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'c': // 13 strings to match.
+ case 'c': // 7 strings to match.
switch (Name[1]) {
default: break;
- case 'm': // 12 strings to match.
- switch (Name[2]) {
- default: break;
- case 'o': // 8 strings to match.
- if (Name[3] != 'v')
- break;
- switch (Name[4]) {
- default: break;
- case 'a': // 1 strings to match.
- return MCK_cmova; // "cmova"
- case 'b': // 1 strings to match.
- return MCK_cmovb; // "cmovb"
- case 'e': // 1 strings to match.
- return MCK_cmove; // "cmove"
- case 'g': // 1 strings to match.
- return MCK_cmovg; // "cmovg"
- case 'l': // 1 strings to match.
- return MCK_cmovl; // "cmovl"
- case 'o': // 1 strings to match.
- return MCK_cmovo; // "cmovo"
- case 'p': // 1 strings to match.
- return MCK_cmovp; // "cmovp"
- case 's': // 1 strings to match.
- return MCK_cmovs; // "cmovs"
- }
+ case 'a': // 1 strings to match.
+ if (Name.substr(2,3) != "llq")
break;
- case 'p': // 4 strings to match.
- if (Name[3] != 's')
- break;
- switch (Name[4]) {
- default: break;
- case 'b': // 1 strings to match.
- return MCK_cmpsb; // "cmpsb"
- case 'l': // 1 strings to match.
- return MCK_cmpsl; // "cmpsl"
- case 'q': // 1 strings to match.
- return MCK_cmpsq; // "cmpsq"
- case 'w': // 1 strings to match.
- return MCK_cmpsw; // "cmpsw"
- }
+ return MCK_callq; // "callq"
+ case 'm': // 4 strings to match.
+ if (Name.substr(2,2) != "ps")
break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_cmpsb; // "cmpsb"
+ case 'l': // 1 strings to match.
+ return MCK_cmpsl; // "cmpsl"
+ case 'q': // 1 strings to match.
+ return MCK_cmpsq; // "cmpsq"
+ case 'w': // 1 strings to match.
+ return MCK_cmpsw; // "cmpsw"
}
break;
+ case 'p': // 1 strings to match.
+ if (Name.substr(2,3) != "uid")
+ break;
+ return MCK_cpuid; // "cpuid"
case 'r': // 1 strings to match.
if (Name.substr(2,3) != "c32")
break;
@@ -2452,9 +2926,13 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(1,4) != "nter")
break;
return MCK_enter; // "enter"
- case 'f': // 29 strings to match.
+ case 'f': // 35 strings to match.
switch (Name[1]) {
default: break;
+ case '2': // 1 strings to match.
+ if (Name.substr(2,3) != "xm1")
+ break;
+ return MCK_f2xm1; // "f2xm1"
case 'a': // 3 strings to match.
if (Name.substr(2,2) != "dd")
break;
@@ -2472,10 +2950,19 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(2,3) != "stp")
break;
return MCK_fbstp; // "fbstp"
- case 'c': // 1 strings to match.
- if (Name.substr(2,3) != "omp")
+ case 'c': // 3 strings to match.
+ if (Name.substr(2,2) != "om")
break;
- return MCK_fcomp; // "fcomp"
+ switch (Name[4]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ return MCK_fcomi; // "fcomi"
+ case 'l': // 1 strings to match.
+ return MCK_fcoml; // "fcoml"
+ case 'p': // 1 strings to match.
+ return MCK_fcomp; // "fcomp"
+ }
+ break;
case 'd': // 4 strings to match.
if (Name.substr(2,2) != "iv")
break;
@@ -2495,6 +2982,10 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(2,3) != "mms")
break;
return MCK_femms; // "femms"
+ case 'f': // 1 strings to match.
+ if (Name.substr(2,3) != "ree")
+ break;
+ return MCK_ffree; // "ffree"
case 'i': // 4 strings to match.
switch (Name[2]) {
default: break;
@@ -2522,10 +3013,21 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'l': // 1 strings to match.
- if (Name.substr(2,3) != "dcw")
+ case 'l': // 2 strings to match.
+ if (Name[2] != 'd')
break;
- return MCK_fldcw; // "fldcw"
+ switch (Name[3]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ if (Name[4] != 'w')
+ break;
+ return MCK_fldcw; // "fldcw"
+ case 'p': // 1 strings to match.
+ if (Name[4] != 'i')
+ break;
+ return MCK_fldpi; // "fldpi"
+ }
+ break;
case 'm': // 3 strings to match.
if (Name.substr(2,2) != "ul")
break;
@@ -2539,35 +3041,37 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_fmuls; // "fmuls"
}
break;
- case 's': // 10 strings to match.
+ case 'p': // 2 strings to match.
switch (Name[2]) {
default: break;
- case 'a': // 1 strings to match.
- if (Name.substr(3,2) != "ve")
+ case 'r': // 1 strings to match.
+ if (Name.substr(3,2) != "em")
+ break;
+ return MCK_fprem; // "fprem"
+ case 't': // 1 strings to match.
+ if (Name.substr(3,2) != "an")
break;
- return MCK_fsave; // "fsave"
+ return MCK_fptan; // "fptan"
+ }
+ break;
+ case 's': // 8 strings to match.
+ switch (Name[2]) {
+ default: break;
case 'q': // 1 strings to match.
if (Name.substr(3,2) != "rt")
break;
return MCK_fsqrt; // "fsqrt"
- case 't': // 4 strings to match.
- switch (Name[3]) {
- default: break;
- case 'p': // 3 strings to match.
- switch (Name[4]) {
- default: break;
- case 'l': // 1 strings to match.
- return MCK_fstpl; // "fstpl"
- case 's': // 1 strings to match.
- return MCK_fstps; // "fstps"
- case 't': // 1 strings to match.
- return MCK_fstpt; // "fstpt"
- }
+ case 't': // 3 strings to match.
+ if (Name[3] != 'p')
break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fstpl; // "fstpl"
case 's': // 1 strings to match.
- if (Name[4] != 'w')
- break;
- return MCK_fstsw; // "fstsw"
+ return MCK_fstps; // "fstps"
+ case 't': // 1 strings to match.
+ return MCK_fstpt; // "fstpt"
}
break;
case 'u': // 4 strings to match.
@@ -2591,9 +3095,13 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(2,3) != "com")
break;
return MCK_fucom; // "fucom"
+ case 'y': // 1 strings to match.
+ if (Name.substr(2,3) != "l2x")
+ break;
+ return MCK_fyl2x; // "fyl2x"
}
break;
- case 'i': // 8 strings to match.
+ case 'i': // 11 strings to match.
switch (Name[1]) {
default: break;
case 'd': // 4 strings to match.
@@ -2626,9 +3134,22 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_imulw; // "imulw"
}
break;
+ case 'r': // 3 strings to match.
+ if (Name.substr(2,2) != "et")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_iretl; // "iretl"
+ case 'q': // 1 strings to match.
+ return MCK_iretq; // "iretq"
+ case 'w': // 1 strings to match.
+ return MCK_iretw; // "iretw"
+ }
+ break;
}
break;
- case 'l': // 10 strings to match.
+ case 'l': // 12 strings to match.
switch (Name[1]) {
default: break;
case 'd': // 1 strings to match.
@@ -2652,6 +3173,14 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_ljmpw; // "ljmpw"
}
break;
+ case 'l': // 1 strings to match.
+ if (Name.substr(2,3) != "dtw")
+ break;
+ return MCK_lldtw; // "lldtw"
+ case 'm': // 1 strings to match.
+ if (Name.substr(2,3) != "sww")
+ break;
+ return MCK_lmsww; // "lmsww"
case 'o': // 5 strings to match.
switch (Name[2]) {
default: break;
@@ -2662,8 +3191,8 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
default: break;
case 'b': // 1 strings to match.
return MCK_lodsb; // "lodsb"
- case 'd': // 1 strings to match.
- return MCK_lodsd; // "lodsd"
+ case 'l': // 1 strings to match.
+ return MCK_lodsl; // "lodsl"
case 'q': // 1 strings to match.
return MCK_lodsq; // "lodsq"
case 'w': // 1 strings to match.
@@ -2773,7 +3302,20 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_mwait; // "mwait"
}
break;
- case 'p': // 27 strings to match.
+ case 'o': // 3 strings to match.
+ if (Name.substr(1,3) != "uts")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_outsb; // "outsb"
+ case 'l': // 1 strings to match.
+ return MCK_outsl; // "outsl"
+ case 'w': // 1 strings to match.
+ return MCK_outsw; // "outsw"
+ }
+ break;
+ case 'p': // 29 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 10 strings to match.
@@ -2824,6 +3366,19 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
+ case 'o': // 3 strings to match.
+ if (Name.substr(2,2) != "pf")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_popfl; // "popfl"
+ case 'q': // 1 strings to match.
+ return MCK_popfq; // "popfq"
+ case 'w': // 1 strings to match.
+ return MCK_popfw; // "popfw"
+ }
+ break;
case 's': // 12 strings to match.
switch (Name[2]) {
default: break;
@@ -2886,13 +3441,11 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(2,3) != "est")
break;
return MCK_ptest; // "ptest"
- case 'u': // 4 strings to match.
+ case 'u': // 3 strings to match.
if (Name.substr(2,2) != "sh")
break;
switch (Name[4]) {
default: break;
- case 'f': // 1 strings to match.
- return MCK_pushf; // "pushf"
case 'l': // 1 strings to match.
return MCK_pushl; // "pushl"
case 'q': // 1 strings to match.
@@ -2903,7 +3456,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'r': // 3 strings to match.
+ case 'r': // 5 strings to match.
switch (Name[1]) {
default: break;
case 'c': // 2 strings to match.
@@ -2921,13 +3474,26 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_rcpss; // "rcpss"
}
break;
- case 'd': // 1 strings to match.
- if (Name.substr(2,3) != "tsc")
- break;
- return MCK_rdtsc; // "rdtsc"
+ case 'd': // 3 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'm': // 1 strings to match.
+ if (Name.substr(3,2) != "sr")
+ break;
+ return MCK_rdmsr; // "rdmsr"
+ case 'p': // 1 strings to match.
+ if (Name.substr(3,2) != "mc")
+ break;
+ return MCK_rdpmc; // "rdpmc"
+ case 't': // 1 strings to match.
+ if (Name.substr(3,2) != "sc")
+ break;
+ return MCK_rdtsc; // "rdtsc"
+ }
+ break;
}
break;
- case 's': // 22 strings to match.
+ case 's': // 28 strings to match.
switch (Name[1]) {
default: break;
case 'c': // 4 strings to match.
@@ -3012,6 +3578,30 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
+ case 'l': // 2 strings to match.
+ if (Name.substr(2,2) != "dt")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'q': // 1 strings to match.
+ return MCK_sldtq; // "sldtq"
+ case 'w': // 1 strings to match.
+ return MCK_sldtw; // "sldtw"
+ }
+ break;
+ case 'm': // 3 strings to match.
+ if (Name.substr(2,2) != "sw")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_smswl; // "smswl"
+ case 'q': // 1 strings to match.
+ return MCK_smswq; // "smswq"
+ case 'w': // 1 strings to match.
+ return MCK_smsww; // "smsww"
+ }
+ break;
case 'u': // 4 strings to match.
if (Name[2] != 'b')
break;
@@ -3037,6 +3627,10 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
+ case 'w': // 1 strings to match.
+ if (Name.substr(2,3) != "pgs")
+ break;
+ return MCK_swpgs; // "swpgs"
}
break;
case 't': // 4 strings to match.
@@ -3054,10 +3648,33 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_testw; // "testw"
}
break;
- case 'x': // 5 strings to match.
+ case 'v': // 1 strings to match.
+ if (Name.substr(1,4) != "mxon")
+ break;
+ return MCK_vmxon; // "vmxon"
+ case 'w': // 1 strings to match.
+ if (Name.substr(1,4) != "rmsr")
+ break;
+ return MCK_wrmsr; // "wrmsr"
+ case 'x': // 11 strings to match.
switch (Name[1]) {
default: break;
- case 'c': // 3 strings to match.
+ case 'a': // 4 strings to match.
+ if (Name.substr(2,2) != "dd")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_xaddb; // "xaddb"
+ case 'l': // 1 strings to match.
+ return MCK_xaddl; // "xaddl"
+ case 'q': // 1 strings to match.
+ return MCK_xaddq; // "xaddq"
+ case 'w': // 1 strings to match.
+ return MCK_xaddw; // "xaddw"
+ }
+ break;
+ case 'c': // 4 strings to match.
if (Name.substr(2,2) != "hg")
break;
switch (Name[4]) {
@@ -3066,10 +3683,16 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_xchgb; // "xchgb"
case 'l': // 1 strings to match.
return MCK_xchgl; // "xchgl"
+ case 'q': // 1 strings to match.
+ return MCK_xchgq; // "xchgq"
case 'w': // 1 strings to match.
return MCK_xchgw; // "xchgw"
}
break;
+ case 'l': // 1 strings to match.
+ if (Name.substr(2,3) != "atb")
+ break;
+ return MCK_xlatb; // "xlatb"
case 'o': // 2 strings to match.
if (Name.substr(2,2) != "rp")
break;
@@ -3085,7 +3708,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 6: // 120 strings to match.
+ case 6: // 163 strings to match.
switch (Name[0]) {
default: break;
case 'a': // 2 strings to match.
@@ -3110,65 +3733,160 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_bswapq; // "bswapq"
}
break;
- case 'c': // 9 strings to match.
+ case 'c': // 26 strings to match.
switch (Name[1]) {
default: break;
- case 'm': // 8 strings to match.
+ case 'm': // 24 strings to match.
if (Name.substr(2,2) != "ov")
break;
switch (Name[4]) {
default: break;
- case 'a': // 1 strings to match.
- if (Name[5] != 'e')
- break;
- return MCK_cmovae; // "cmovae"
- case 'b': // 1 strings to match.
- if (Name[5] != 'e')
- break;
- return MCK_cmovbe; // "cmovbe"
- case 'g': // 1 strings to match.
- if (Name[5] != 'e')
- break;
- return MCK_cmovge; // "cmovge"
- case 'l': // 1 strings to match.
- if (Name[5] != 'e')
- break;
- return MCK_cmovle; // "cmovle"
- case 'n': // 4 strings to match.
+ case 'a': // 3 strings to match.
switch (Name[5]) {
default: break;
- case 'e': // 1 strings to match.
- return MCK_cmovne; // "cmovne"
- case 'o': // 1 strings to match.
- return MCK_cmovno; // "cmovno"
- case 'p': // 1 strings to match.
- return MCK_cmovnp; // "cmovnp"
- case 's': // 1 strings to match.
- return MCK_cmovns; // "cmovns"
+ case 'l': // 1 strings to match.
+ return MCK_cmoval; // "cmoval"
+ case 'q': // 1 strings to match.
+ return MCK_cmovaq; // "cmovaq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovaw; // "cmovaw"
+ }
+ break;
+ case 'b': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovbl; // "cmovbl"
+ case 'q': // 1 strings to match.
+ return MCK_cmovbq; // "cmovbq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovbw; // "cmovbw"
+ }
+ break;
+ case 'e': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovel; // "cmovel"
+ case 'q': // 1 strings to match.
+ return MCK_cmoveq; // "cmoveq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovew; // "cmovew"
+ }
+ break;
+ case 'g': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovgl; // "cmovgl"
+ case 'q': // 1 strings to match.
+ return MCK_cmovgq; // "cmovgq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovgw; // "cmovgw"
+ }
+ break;
+ case 'l': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovll; // "cmovll"
+ case 'q': // 1 strings to match.
+ return MCK_cmovlq; // "cmovlq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovlw; // "cmovlw"
+ }
+ break;
+ case 'o': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovol; // "cmovol"
+ case 'q': // 1 strings to match.
+ return MCK_cmovoq; // "cmovoq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovow; // "cmovow"
+ }
+ break;
+ case 'p': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovpl; // "cmovpl"
+ case 'q': // 1 strings to match.
+ return MCK_cmovpq; // "cmovpq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovpw; // "cmovpw"
+ }
+ break;
+ case 's': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovsl; // "cmovsl"
+ case 'q': // 1 strings to match.
+ return MCK_cmovsq; // "cmovsq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovsw; // "cmovsw"
}
break;
}
break;
- case 'o': // 1 strings to match.
- if (Name.substr(2,4) != "misd")
+ case 'o': // 2 strings to match.
+ if (Name.substr(2,3) != "mis")
break;
- return MCK_comisd; // "comisd"
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_comisd; // "comisd"
+ case 's': // 1 strings to match.
+ return MCK_comiss; // "comiss"
+ }
+ break;
}
break;
- case 'f': // 29 strings to match.
+ case 'f': // 43 strings to match.
switch (Name[1]) {
default: break;
- case 'c': // 3 strings to match.
- if (Name.substr(2,3) != "mov")
- break;
- switch (Name[5]) {
+ case 'c': // 7 strings to match.
+ switch (Name[2]) {
default: break;
- case 'b': // 1 strings to match.
- return MCK_fcmovb; // "fcmovb"
- case 'e': // 1 strings to match.
- return MCK_fcmove; // "fcmove"
- case 'u': // 1 strings to match.
- return MCK_fcmovu; // "fcmovu"
+ case 'm': // 3 strings to match.
+ if (Name.substr(3,2) != "ov")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_fcmovb; // "fcmovb"
+ case 'e': // 1 strings to match.
+ return MCK_fcmove; // "fcmove"
+ case 'u': // 1 strings to match.
+ return MCK_fcmovu; // "fcmovu"
+ }
+ break;
+ case 'o': // 4 strings to match.
+ if (Name[3] != 'm')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ if (Name[5] != 'p')
+ break;
+ return MCK_fcomip; // "fcomip"
+ case 'l': // 1 strings to match.
+ if (Name[5] != 'l')
+ break;
+ return MCK_fcomll; // "fcomll"
+ case 'p': // 2 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fcompl; // "fcompl"
+ case 'p': // 1 strings to match.
+ return MCK_fcompp; // "fcompp"
+ }
+ break;
+ }
+ break;
}
break;
case 'd': // 3 strings to match.
@@ -3264,23 +3982,85 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'l': // 1 strings to match.
- if (Name.substr(2,4) != "denv")
+ case 'l': // 5 strings to match.
+ if (Name[2] != 'd')
break;
- return MCK_fldenv; // "fldenv"
- case 'n': // 2 strings to match.
- if (Name.substr(2,2) != "st")
+ switch (Name[3]) {
+ default: break;
+ case 'e': // 1 strings to match.
+ if (Name.substr(4,2) != "nv")
+ break;
+ return MCK_fldenv; // "fldenv"
+ case 'l': // 4 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case '2': // 2 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'e': // 1 strings to match.
+ return MCK_fldl2e; // "fldl2e"
+ case 't': // 1 strings to match.
+ return MCK_fldl2t; // "fldl2t"
+ }
+ break;
+ case 'g': // 1 strings to match.
+ if (Name[5] != '2')
+ break;
+ return MCK_fldlg2; // "fldlg2"
+ case 'n': // 1 strings to match.
+ if (Name[5] != '2')
+ break;
+ return MCK_fldln2; // "fldln2"
+ }
break;
- switch (Name[4]) {
+ }
+ break;
+ case 'n': // 5 strings to match.
+ switch (Name[2]) {
default: break;
case 'c': // 1 strings to match.
- if (Name[5] != 'w')
+ if (Name.substr(3,3) != "lex")
break;
- return MCK_fnstcw; // "fnstcw"
- case 's': // 1 strings to match.
- if (Name[5] != 'w')
+ return MCK_fnclex; // "fnclex"
+ case 'i': // 1 strings to match.
+ if (Name.substr(3,3) != "nit")
+ break;
+ return MCK_fninit; // "fninit"
+ case 's': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name.substr(4,2) != "ve")
+ break;
+ return MCK_fnsave; // "fnsave"
+ case 't': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ if (Name[5] != 'w')
+ break;
+ return MCK_fnstcw; // "fnstcw"
+ case 's': // 1 strings to match.
+ if (Name[5] != 'w')
+ break;
+ return MCK_fnstsw; // "fnstsw"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'p': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name.substr(3,3) != "tan")
+ break;
+ return MCK_fpatan; // "fpatan"
+ case 'r': // 1 strings to match.
+ if (Name.substr(3,3) != "em1")
break;
- return MCK_fnstsw; // "fnstsw"
+ return MCK_fprem1; // "fprem1"
}
break;
case 'r': // 1 strings to match.
@@ -3290,10 +4070,10 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
case 's': // 4 strings to match.
switch (Name[2]) {
default: break;
- case 't': // 1 strings to match.
- if (Name.substr(3,3) != "env")
+ case 'c': // 1 strings to match.
+ if (Name.substr(3,3) != "ale")
break;
- return MCK_fstenv; // "fstenv"
+ return MCK_fscale; // "fscale"
case 'u': // 3 strings to match.
if (Name.substr(3,2) != "br")
break;
@@ -3320,6 +4100,10 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_fucomp; // "fucomp"
}
break;
+ case 'x': // 1 strings to match.
+ if (Name.substr(2,4) != "save")
+ break;
+ return MCK_fxsave; // "fxsave"
}
break;
case 'h': // 4 strings to match.
@@ -3349,6 +4133,21 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
+ case 'i': // 2 strings to match.
+ if (Name.substr(1,2) != "nv")
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'e': // 1 strings to match.
+ if (Name.substr(4,2) != "pt")
+ break;
+ return MCK_invept; // "invept"
+ case 'l': // 1 strings to match.
+ if (Name.substr(4,2) != "pg")
+ break;
+ return MCK_invlpg; // "invlpg"
+ }
+ break;
case 'l': // 5 strings to match.
switch (Name[1]) {
default: break;
@@ -3375,14 +4174,14 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_loopne; // "loopne"
}
break;
- case 'm': // 20 strings to match.
+ case 'm': // 24 strings to match.
switch (Name[1]) {
default: break;
case 'f': // 1 strings to match.
if (Name.substr(2,4) != "ence")
break;
return MCK_mfence; // "mfence"
- case 'o': // 19 strings to match.
+ case 'o': // 23 strings to match.
if (Name[2] != 'v')
break;
switch (Name[3]) {
@@ -3442,16 +4241,18 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_movntq; // "movntq"
}
break;
- case 's': // 5 strings to match.
+ case 's': // 6 strings to match.
switch (Name[4]) {
default: break;
- case 'b': // 2 strings to match.
+ case 'b': // 3 strings to match.
switch (Name[5]) {
default: break;
case 'l': // 1 strings to match.
return MCK_movsbl; // "movsbl"
case 'q': // 1 strings to match.
return MCK_movsbq; // "movsbq"
+ case 'w': // 1 strings to match.
+ return MCK_movsbw; // "movsbw"
}
break;
case 'l': // 1 strings to match.
@@ -3480,24 +4281,36 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_movups; // "movups"
}
break;
- case 'z': // 2 strings to match.
+ case 'z': // 5 strings to match.
switch (Name[4]) {
default: break;
- case 'b': // 1 strings to match.
- if (Name[5] != 'l')
- break;
- return MCK_movzbl; // "movzbl"
- case 'w': // 1 strings to match.
- if (Name[5] != 'l')
- break;
- return MCK_movzwl; // "movzwl"
+ case 'b': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_movzbl; // "movzbl"
+ case 'q': // 1 strings to match.
+ return MCK_movzbq; // "movzbq"
+ case 'w': // 1 strings to match.
+ return MCK_movzbw; // "movzbw"
+ }
+ break;
+ case 'w': // 2 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_movzwl; // "movzwl"
+ case 'q': // 1 strings to match.
+ return MCK_movzwq; // "movzwq"
+ }
+ break;
}
break;
}
break;
}
break;
- case 'p': // 41 strings to match.
+ case 'p': // 44 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 2 strings to match.
@@ -3709,6 +4522,19 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
+ case 'u': // 3 strings to match.
+ if (Name.substr(2,3) != "shf")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_pushfl; // "pushfl"
+ case 'q': // 1 strings to match.
+ return MCK_pushfq; // "pushfq"
+ case 'w': // 1 strings to match.
+ return MCK_pushfw; // "pushfw"
+ }
+ break;
}
break;
case 's': // 8 strings to match.
@@ -3760,9 +4586,28 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_sysret; // "sysret"
}
break;
+ case 'v': // 2 strings to match.
+ if (Name[1] != 'm')
+ break;
+ switch (Name[2]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ if (Name.substr(3,3) != "all")
+ break;
+ return MCK_vmcall; // "vmcall"
+ case 'x': // 1 strings to match.
+ if (Name.substr(3,3) != "off")
+ break;
+ return MCK_vmxoff; // "vmxoff"
+ }
+ break;
+ case 'w': // 1 strings to match.
+ if (Name.substr(1,5) != "binvd")
+ break;
+ return MCK_wbinvd; // "wbinvd"
}
break;
- case 7: // 58 strings to match.
+ case 7: // 100 strings to match.
switch (Name[0]) {
default: break;
case 'b': // 2 strings to match.
@@ -3776,36 +4621,162 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_blendps; // "blendps"
}
break;
- case 'c': // 1 strings to match.
- if (Name.substr(1,6) != "lflush")
- break;
- return MCK_clflush; // "clflush"
- case 'f': // 15 strings to match.
+ case 'c': // 25 strings to match.
switch (Name[1]) {
default: break;
- case 'c': // 4 strings to match.
- if (Name.substr(2,3) != "mov")
+ case 'l': // 1 strings to match.
+ if (Name.substr(2,5) != "flush")
break;
- switch (Name[5]) {
+ return MCK_clflush; // "clflush"
+ case 'm': // 24 strings to match.
+ if (Name.substr(2,2) != "ov")
+ break;
+ switch (Name[4]) {
default: break;
- case 'b': // 1 strings to match.
- if (Name[6] != 'e')
+ case 'a': // 3 strings to match.
+ if (Name[5] != 'e')
break;
- return MCK_fcmovbe; // "fcmovbe"
- case 'n': // 3 strings to match.
switch (Name[6]) {
default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovael; // "cmovael"
+ case 'q': // 1 strings to match.
+ return MCK_cmovaeq; // "cmovaeq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovaew; // "cmovaew"
+ }
+ break;
+ case 'b': // 3 strings to match.
+ if (Name[5] != 'e')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovbel; // "cmovbel"
+ case 'q': // 1 strings to match.
+ return MCK_cmovbeq; // "cmovbeq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovbew; // "cmovbew"
+ }
+ break;
+ case 'g': // 3 strings to match.
+ if (Name[5] != 'e')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovgel; // "cmovgel"
+ case 'q': // 1 strings to match.
+ return MCK_cmovgeq; // "cmovgeq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovgew; // "cmovgew"
+ }
+ break;
+ case 'l': // 3 strings to match.
+ if (Name[5] != 'e')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovlel; // "cmovlel"
+ case 'q': // 1 strings to match.
+ return MCK_cmovleq; // "cmovleq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovlew; // "cmovlew"
+ }
+ break;
+ case 'n': // 12 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'e': // 3 strings to match.
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovnel; // "cmovnel"
+ case 'q': // 1 strings to match.
+ return MCK_cmovneq; // "cmovneq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovnew; // "cmovnew"
+ }
+ break;
+ case 'o': // 3 strings to match.
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovnol; // "cmovnol"
+ case 'q': // 1 strings to match.
+ return MCK_cmovnoq; // "cmovnoq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovnow; // "cmovnow"
+ }
+ break;
+ case 'p': // 3 strings to match.
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovnpl; // "cmovnpl"
+ case 'q': // 1 strings to match.
+ return MCK_cmovnpq; // "cmovnpq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovnpw; // "cmovnpw"
+ }
+ break;
+ case 's': // 3 strings to match.
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cmovnsl; // "cmovnsl"
+ case 'q': // 1 strings to match.
+ return MCK_cmovnsq; // "cmovnsq"
+ case 'w': // 1 strings to match.
+ return MCK_cmovnsw; // "cmovnsw"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'f': // 24 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 5 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'm': // 4 strings to match.
+ if (Name.substr(3,2) != "ov")
+ break;
+ switch (Name[5]) {
+ default: break;
case 'b': // 1 strings to match.
- return MCK_fcmovnb; // "fcmovnb"
- case 'e': // 1 strings to match.
- return MCK_fcmovne; // "fcmovne"
- case 'u': // 1 strings to match.
- return MCK_fcmovnu; // "fcmovnu"
+ if (Name[6] != 'e')
+ break;
+ return MCK_fcmovbe; // "fcmovbe"
+ case 'n': // 3 strings to match.
+ switch (Name[6]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_fcmovnb; // "fcmovnb"
+ case 'e': // 1 strings to match.
+ return MCK_fcmovne; // "fcmovne"
+ case 'u': // 1 strings to match.
+ return MCK_fcmovnu; // "fcmovnu"
+ }
+ break;
}
break;
+ case 'o': // 1 strings to match.
+ if (Name.substr(3,4) != "mpll")
+ break;
+ return MCK_fcompll; // "fcompll"
}
break;
- case 'i': // 9 strings to match.
+ case 'd': // 1 strings to match.
+ if (Name.substr(2,5) != "ecstp")
+ break;
+ return MCK_fdecstp; // "fdecstp"
+ case 'i': // 10 strings to match.
switch (Name[2]) {
default: break;
case 'c': // 2 strings to match.
@@ -3830,6 +4801,10 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_fidivrs; // "fidivrs"
}
break;
+ case 'n': // 1 strings to match.
+ if (Name.substr(3,4) != "cstp")
+ break;
+ return MCK_fincstp; // "fincstp"
case 's': // 5 strings to match.
switch (Name[3]) {
default: break;
@@ -3868,6 +4843,18 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
+ case 'n': // 1 strings to match.
+ if (Name.substr(2,5) != "stenv")
+ break;
+ return MCK_fnstenv; // "fnstenv"
+ case 'r': // 1 strings to match.
+ if (Name.substr(2,5) != "ndint")
+ break;
+ return MCK_frndint; // "frndint"
+ case 's': // 1 strings to match.
+ if (Name.substr(2,5) != "incos")
+ break;
+ return MCK_fsincos; // "fsincos"
case 'u': // 2 strings to match.
if (Name.substr(2,3) != "com")
break;
@@ -3883,8 +4870,29 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_fucompp; // "fucompp"
}
break;
+ case 'x': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'r': // 1 strings to match.
+ if (Name.substr(3,4) != "stor")
+ break;
+ return MCK_fxrstor; // "fxrstor"
+ case 't': // 1 strings to match.
+ if (Name.substr(3,4) != "ract")
+ break;
+ return MCK_fxtract; // "fxtract"
+ }
+ break;
+ case 'y': // 1 strings to match.
+ if (Name.substr(2,5) != "l2xp1")
+ break;
+ return MCK_fyl2xp1; // "fyl2xp1"
}
break;
+ case 'i': // 1 strings to match.
+ if (Name.substr(1,6) != "nvvpid")
+ break;
+ return MCK_invvpid; // "invvpid"
case 'l': // 1 strings to match.
if (Name.substr(1,6) != "dmxcsr")
break;
@@ -3961,7 +4969,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_mpsadbw; // "mpsadbw"
}
break;
- case 'p': // 21 strings to match.
+ case 'p': // 24 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 3 strings to match.
@@ -4062,6 +5070,19 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
+ case 'o': // 3 strings to match.
+ if (Name.substr(2,4) != "pcnt")
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_popcntl; // "popcntl"
+ case 'q': // 1 strings to match.
+ return MCK_popcntq; // "popcntq"
+ case 'w': // 1 strings to match.
+ return MCK_popcntw; // "popcntw"
+ }
+ break;
case 's': // 4 strings to match.
switch (Name[2]) {
default: break;
@@ -4145,9 +5166,46 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_ucomiss; // "ucomiss"
}
break;
+ case 'v': // 5 strings to match.
+ if (Name[1] != 'm')
+ break;
+ switch (Name[2]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ if (Name.substr(3,4) != "lear")
+ break;
+ return MCK_vmclear; // "vmclear"
+ case 'p': // 2 strings to match.
+ if (Name.substr(3,2) != "tr")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ if (Name[6] != 'd')
+ break;
+ return MCK_vmptrld; // "vmptrld"
+ case 's': // 1 strings to match.
+ if (Name[6] != 't')
+ break;
+ return MCK_vmptrst; // "vmptrst"
+ }
+ break;
+ case 'r': // 2 strings to match.
+ if (Name.substr(3,3) != "ead")
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_vmreadl; // "vmreadl"
+ case 'q': // 1 strings to match.
+ return MCK_vmreadq; // "vmreadq"
+ }
+ break;
+ }
+ break;
}
break;
- case 8: // 49 strings to match.
+ case 8: // 59 strings to match.
switch (Name[0]) {
default: break;
case 'a': // 2 strings to match.
@@ -4172,90 +5230,120 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_blendvps; // "blendvps"
}
break;
- case 'c': // 12 strings to match.
- if (Name.substr(1,2) != "vt")
- break;
- switch (Name[3]) {
+ case 'c': // 18 strings to match.
+ switch (Name[1]) {
default: break;
- case 'd': // 2 strings to match.
- if (Name.substr(4,3) != "q2p")
+ case 'm': // 4 strings to match.
+ if (Name.substr(2,5) != "pxchg")
break;
switch (Name[7]) {
default: break;
- case 'd': // 1 strings to match.
- return MCK_cvtdq2pd; // "cvtdq2pd"
- case 's': // 1 strings to match.
- return MCK_cvtdq2ps; // "cvtdq2ps"
+ case 'b': // 1 strings to match.
+ return MCK_cmpxchgb; // "cmpxchgb"
+ case 'l': // 1 strings to match.
+ return MCK_cmpxchgl; // "cmpxchgl"
+ case 'q': // 1 strings to match.
+ return MCK_cmpxchgq; // "cmpxchgq"
+ case 'w': // 1 strings to match.
+ return MCK_cmpxchgw; // "cmpxchgw"
}
break;
- case 'p': // 6 strings to match.
- switch (Name[4]) {
+ case 'v': // 14 strings to match.
+ if (Name[2] != 't')
+ break;
+ switch (Name[3]) {
default: break;
case 'd': // 2 strings to match.
- if (Name[5] != '2')
- break;
- switch (Name[6]) {
- default: break;
- case 'd': // 1 strings to match.
- if (Name[7] != 'q')
- break;
- return MCK_cvtpd2dq; // "cvtpd2dq"
- case 'p': // 1 strings to match.
- if (Name[7] != 'i')
- break;
- return MCK_cvtpd2pi; // "cvtpd2pi"
- }
- break;
- case 'i': // 2 strings to match.
- if (Name.substr(5,2) != "2p")
+ if (Name.substr(4,3) != "q2p")
break;
switch (Name[7]) {
default: break;
case 'd': // 1 strings to match.
- return MCK_cvtpi2pd; // "cvtpi2pd"
+ return MCK_cvtdq2pd; // "cvtdq2pd"
case 's': // 1 strings to match.
- return MCK_cvtpi2ps; // "cvtpi2ps"
+ return MCK_cvtdq2ps; // "cvtdq2ps"
}
break;
- case 's': // 2 strings to match.
- if (Name[5] != '2')
- break;
- switch (Name[6]) {
+ case 'p': // 8 strings to match.
+ switch (Name[4]) {
default: break;
- case 'd': // 1 strings to match.
- if (Name[7] != 'q')
+ case 'd': // 3 strings to match.
+ if (Name[5] != '2')
break;
- return MCK_cvtps2dq; // "cvtps2dq"
- case 'p': // 1 strings to match.
- if (Name[7] != 'i')
+ switch (Name[6]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[7] != 'q')
+ break;
+ return MCK_cvtpd2dq; // "cvtpd2dq"
+ case 'p': // 2 strings to match.
+ switch (Name[7]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ return MCK_cvtpd2pi; // "cvtpd2pi"
+ case 's': // 1 strings to match.
+ return MCK_cvtpd2ps; // "cvtpd2ps"
+ }
break;
- return MCK_cvtps2pi; // "cvtps2pi"
- }
- break;
- }
- break;
- case 's': // 4 strings to match.
- switch (Name[4]) {
- default: break;
- case 'd': // 1 strings to match.
- if (Name.substr(5,3) != "2ss")
+ }
break;
- return MCK_cvtsd2ss; // "cvtsd2ss"
- case 'i': // 2 strings to match.
- if (Name.substr(5,2) != "2s")
+ case 'i': // 2 strings to match.
+ if (Name.substr(5,2) != "2p")
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_cvtpi2pd; // "cvtpi2pd"
+ case 's': // 1 strings to match.
+ return MCK_cvtpi2ps; // "cvtpi2ps"
+ }
break;
- switch (Name[7]) {
+ case 's': // 3 strings to match.
+ if (Name[5] != '2')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[7] != 'q')
+ break;
+ return MCK_cvtps2dq; // "cvtps2dq"
+ case 'p': // 2 strings to match.
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_cvtps2pd; // "cvtps2pd"
+ case 'i': // 1 strings to match.
+ return MCK_cvtps2pi; // "cvtps2pi"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 's': // 4 strings to match.
+ switch (Name[4]) {
default: break;
case 'd': // 1 strings to match.
- return MCK_cvtsi2sd; // "cvtsi2sd"
+ if (Name.substr(5,3) != "2ss")
+ break;
+ return MCK_cvtsd2ss; // "cvtsd2ss"
+ case 'i': // 2 strings to match.
+ if (Name.substr(5,2) != "2s")
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_cvtsi2sd; // "cvtsi2sd"
+ case 's': // 1 strings to match.
+ return MCK_cvtsi2ss; // "cvtsi2ss"
+ }
+ break;
case 's': // 1 strings to match.
- return MCK_cvtsi2ss; // "cvtsi2ss"
+ if (Name.substr(5,3) != "2sd")
+ break;
+ return MCK_cvtss2sd; // "cvtss2sd"
}
break;
- case 's': // 1 strings to match.
- if (Name.substr(5,3) != "2sd")
- break;
- return MCK_cvtss2sd; // "cvtss2sd"
}
break;
}
@@ -4482,58 +5570,124 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- }
- break;
- case 9: // 26 strings to match.
- switch (Name[0]) {
- default: break;
- case 'c': // 6 strings to match.
- if (Name.substr(1,2) != "vt")
+ case 'v': // 4 strings to match.
+ if (Name[1] != 'm')
break;
- switch (Name[3]) {
+ switch (Name[2]) {
default: break;
- case 's': // 2 strings to match.
- if (Name.substr(4,3) != "i2s")
+ case 'l': // 1 strings to match.
+ if (Name.substr(3,5) != "aunch")
+ break;
+ return MCK_vmlaunch; // "vmlaunch"
+ case 'r': // 1 strings to match.
+ if (Name.substr(3,5) != "esume")
+ break;
+ return MCK_vmresume; // "vmresume"
+ case 'w': // 2 strings to match.
+ if (Name.substr(3,4) != "rite")
break;
switch (Name[7]) {
default: break;
- case 'd': // 1 strings to match.
- if (Name[8] != 'q')
- break;
- return MCK_cvtsi2sdq; // "cvtsi2sdq"
- case 's': // 1 strings to match.
- if (Name[8] != 'q')
- break;
- return MCK_cvtsi2ssq; // "cvtsi2ssq"
+ case 'l': // 1 strings to match.
+ return MCK_vmwritel; // "vmwritel"
+ case 'q': // 1 strings to match.
+ return MCK_vmwriteq; // "vmwriteq"
}
break;
- case 't': // 4 strings to match.
- switch (Name[4]) {
+ }
+ break;
+ }
+ break;
+ case 9: // 31 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'c': // 11 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'm': // 1 strings to match.
+ if (Name.substr(2,7) != "pxchg8b")
+ break;
+ return MCK_cmpxchg8b; // "cmpxchg8b"
+ case 'v': // 10 strings to match.
+ if (Name[2] != 't')
+ break;
+ switch (Name[3]) {
default: break;
- case 'p': // 2 strings to match.
- switch (Name[5]) {
+ case 's': // 5 strings to match.
+ switch (Name[4]) {
default: break;
case 'd': // 1 strings to match.
- if (Name.substr(6,3) != "2pi")
+ if (Name.substr(5,4) != "2siq")
break;
- return MCK_cvttpd2pi; // "cvttpd2pi"
- case 's': // 1 strings to match.
- if (Name.substr(6,3) != "2pi")
+ return MCK_cvtsd2siq; // "cvtsd2siq"
+ case 'i': // 2 strings to match.
+ if (Name.substr(5,2) != "2s")
break;
- return MCK_cvttps2pi; // "cvttps2pi"
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[8] != 'q')
+ break;
+ return MCK_cvtsi2sdq; // "cvtsi2sdq"
+ case 's': // 1 strings to match.
+ if (Name[8] != 'q')
+ break;
+ return MCK_cvtsi2ssq; // "cvtsi2ssq"
+ }
+ break;
+ case 's': // 2 strings to match.
+ if (Name.substr(5,3) != "2si")
+ break;
+ switch (Name[8]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_cvtss2sil; // "cvtss2sil"
+ case 'q': // 1 strings to match.
+ return MCK_cvtss2siq; // "cvtss2siq"
+ }
+ break;
}
break;
- case 's': // 2 strings to match.
- switch (Name[5]) {
+ case 't': // 5 strings to match.
+ switch (Name[4]) {
default: break;
- case 'd': // 1 strings to match.
- if (Name.substr(6,3) != "2si")
- break;
- return MCK_cvttsd2si; // "cvttsd2si"
- case 's': // 1 strings to match.
- if (Name.substr(6,3) != "2si")
+ case 'p': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name.substr(6,3) != "2pi")
+ break;
+ return MCK_cvttpd2pi; // "cvttpd2pi"
+ case 's': // 2 strings to match.
+ if (Name[6] != '2')
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[8] != 'q')
+ break;
+ return MCK_cvttps2dq; // "cvttps2dq"
+ case 'p': // 1 strings to match.
+ if (Name[8] != 'i')
+ break;
+ return MCK_cvttps2pi; // "cvttps2pi"
+ }
break;
- return MCK_cvttss2si; // "cvttss2si"
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name.substr(6,3) != "2si")
+ break;
+ return MCK_cvttsd2si; // "cvttsd2si"
+ case 's': // 1 strings to match.
+ if (Name.substr(6,3) != "2si")
+ break;
+ return MCK_cvttss2si; // "cvttss2si"
+ }
+ break;
}
break;
}
@@ -4662,22 +5816,31 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 10: // 9 strings to match.
+ case 10: // 10 strings to match.
switch (Name[0]) {
default: break;
- case 'c': // 2 strings to match.
- if (Name.substr(1,4) != "vtts")
- break;
- switch (Name[5]) {
+ case 'c': // 3 strings to match.
+ switch (Name[1]) {
default: break;
- case 'd': // 1 strings to match.
- if (Name.substr(6,4) != "2siq")
+ case 'm': // 1 strings to match.
+ if (Name.substr(2,8) != "pxchg16b")
break;
- return MCK_cvttsd2siq; // "cvttsd2siq"
- case 's': // 1 strings to match.
- if (Name.substr(6,4) != "2siq")
+ return MCK_cmpxchg16b; // "cmpxchg16b"
+ case 'v': // 2 strings to match.
+ if (Name.substr(2,3) != "tts")
break;
- return MCK_cvttss2siq; // "cvttss2siq"
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name.substr(6,4) != "2siq")
+ break;
+ return MCK_cvttsd2siq; // "cvttsd2siq"
+ case 's': // 1 strings to match.
+ if (Name.substr(6,4) != "2siq")
+ break;
+ return MCK_cvttss2siq; // "cvttss2siq"
+ }
+ break;
}
break;
case 'm': // 1 strings to match.
@@ -4867,8 +6030,33 @@ static MatchClassKind ClassifyOperand(X86Operand &Operand) {
case X86::DS: return MCK_SEGMENT_REG;
case X86::SS: return MCK_SEGMENT_REG;
case X86::ES: return MCK_SEGMENT_REG;
- case X86::FS: return MCK_SEGMENT_REG;
- case X86::GS: return MCK_SEGMENT_REG;
+ case X86::FS: return MCK_FS;
+ case X86::GS: return MCK_GS;
+ case X86::DR0: return MCK_DEBUG_REG;
+ case X86::DR1: return MCK_DEBUG_REG;
+ case X86::DR2: return MCK_DEBUG_REG;
+ case X86::DR3: return MCK_DEBUG_REG;
+ case X86::DR4: return MCK_DEBUG_REG;
+ case X86::DR5: return MCK_DEBUG_REG;
+ case X86::DR6: return MCK_DEBUG_REG;
+ case X86::DR7: return MCK_DEBUG_REG;
+ case X86::ECR0: return MCK_CONTROL_REG_32;
+ case X86::ECR1: return MCK_CONTROL_REG_32;
+ case X86::ECR2: return MCK_CONTROL_REG_32;
+ case X86::ECR3: return MCK_CONTROL_REG_32;
+ case X86::ECR4: return MCK_CONTROL_REG_32;
+ case X86::ECR5: return MCK_CONTROL_REG_32;
+ case X86::ECR6: return MCK_CONTROL_REG_32;
+ case X86::ECR7: return MCK_CONTROL_REG_32;
+ case X86::RCR0: return MCK_CONTROL_REG_64;
+ case X86::RCR1: return MCK_CONTROL_REG_64;
+ case X86::RCR2: return MCK_CONTROL_REG_64;
+ case X86::RCR3: return MCK_CONTROL_REG_64;
+ case X86::RCR4: return MCK_CONTROL_REG_64;
+ case X86::RCR5: return MCK_CONTROL_REG_64;
+ case X86::RCR6: return MCK_CONTROL_REG_64;
+ case X86::RCR7: return MCK_CONTROL_REG_64;
+ case X86::RCR8: return MCK_CONTROL_REG_64;
}
}
@@ -5008,8 +6196,8 @@ static bool IsSubclass(MatchClassKind A, MatchClassKind B) {
default: return false;
case MCK_GR64_ABCD: return true;
case MCK_GR64_NOREX_NOSP: return true;
- case MCK_GR64_NOREX: return true;
case MCK_GR64_NOSP: return true;
+ case MCK_GR64_NOREX: return true;
case MCK_GR64: return true;
}
@@ -5017,23 +6205,23 @@ static bool IsSubclass(MatchClassKind A, MatchClassKind B) {
switch (B) {
default: return false;
case MCK_GR64_NOREX_NOSP: return true;
- case MCK_GR64_NOREX: return true;
case MCK_GR64_NOSP: return true;
+ case MCK_GR64_NOREX: return true;
case MCK_GR64: return true;
}
case MCK_GR64_NOREX_NOSP:
switch (B) {
default: return false;
- case MCK_GR64_NOREX: return true;
case MCK_GR64_NOSP: return true;
+ case MCK_GR64_NOREX: return true;
case MCK_GR64: return true;
}
- case MCK_GR64_NOREX:
+ case MCK_GR64_NOSP:
return B == MCK_GR64;
- case MCK_GR64_NOSP:
+ case MCK_GR64_NOREX:
return B == MCK_GR64;
case MCK_XMM0:
@@ -5042,6 +6230,12 @@ static bool IsSubclass(MatchClassKind A, MatchClassKind B) {
case MCK_ST0:
return B == MCK_RST;
+ case MCK_FS:
+ return B == MCK_SEGMENT_REG;
+
+ case MCK_GS:
+ return B == MCK_SEGMENT_REG;
+
case MCK_ImmSExt8:
return B == MCK_Imm;
}
@@ -5052,35 +6246,74 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
unsigned Opcode;
ConversionKind ConvertFn;
MatchClassKind Classes[5];
- } MatchTable[1775] = {
+ } MatchTable[2041] = {
{ X86::CBW, Convert, { MCK_cbtw } },
+ { X86::CLC, Convert, { MCK_clc } },
+ { X86::CLD, Convert, { MCK_cld } },
+ { X86::CLI, Convert, { MCK_cli } },
{ X86::CDQ, Convert, { MCK_cltd } },
{ X86::CDQE, Convert, { MCK_cltq } },
+ { X86::CLTS, Convert, { MCK_clts } },
+ { X86::CMC, Convert, { MCK_cmc } },
{ X86::CMPS8, Convert, { MCK_cmpsb } },
{ X86::CMPS32, Convert, { MCK_cmpsl } },
{ X86::CMPS64, Convert, { MCK_cmpsq } },
{ X86::CMPS16, Convert, { MCK_cmpsw } },
+ { X86::CPUID, Convert, { MCK_cpuid } },
{ X86::CQO, Convert, { MCK_cqto } },
{ X86::CWD, Convert, { MCK_cwtd } },
{ X86::CWDE, Convert, { MCK_cwtl } },
{ X86::MMX_EMMS, Convert, { MCK_emms } },
+ { X86::F2XM1, Convert, { MCK_f2xm1 } },
{ X86::ABS_F, Convert, { MCK_fabs } },
{ X86::CHS_F, Convert, { MCK_fchs } },
+ { X86::FCOMPP, Convert, { MCK_fcompp } },
{ X86::COS_F, Convert, { MCK_fcos } },
+ { X86::FDECSTP, Convert, { MCK_fdecstp } },
{ X86::MMX_FEMMS, Convert, { MCK_femms } },
+ { X86::FINCSTP, Convert, { MCK_fincstp } },
{ X86::LD_F1, Convert, { MCK_fld1 } },
+ { X86::FLDL2E, Convert, { MCK_fldl2e } },
+ { X86::FLDL2T, Convert, { MCK_fldl2t } },
+ { X86::FLDLG2, Convert, { MCK_fldlg2 } },
+ { X86::FLDLN2, Convert, { MCK_fldln2 } },
+ { X86::FLDPI, Convert, { MCK_fldpi } },
{ X86::LD_F0, Convert, { MCK_fldz } },
- { X86::FNSTSW8r, Convert, { MCK_fnstsw } },
+ { X86::FNCLEX, Convert, { MCK_fnclex } },
+ { X86::FNINIT, Convert, { MCK_fninit } },
+ { X86::FNOP, Convert, { MCK_fnop } },
+ { X86::FPATAN, Convert, { MCK_fpatan } },
+ { X86::FPREM, Convert, { MCK_fprem } },
+ { X86::FPREM1, Convert, { MCK_fprem1 } },
+ { X86::FPTAN, Convert, { MCK_fptan } },
+ { X86::FRNDINT, Convert, { MCK_frndint } },
+ { X86::FSCALE, Convert, { MCK_fscale } },
{ X86::SIN_F, Convert, { MCK_fsin } },
+ { X86::FSINCOS, Convert, { MCK_fsincos } },
{ X86::SQRT_F, Convert, { MCK_fsqrt } },
{ X86::TST_F, Convert, { MCK_ftst } },
{ X86::UCOM_FPPr, Convert, { MCK_fucompp } },
+ { X86::FXAM, Convert, { MCK_fxam } },
+ { X86::FXTRACT, Convert, { MCK_fxtract } },
+ { X86::FYL2X, Convert, { MCK_fyl2x } },
+ { X86::FYL2XP1, Convert, { MCK_fyl2xp1 } },
+ { X86::HLT, Convert, { MCK_hlt } },
+ { X86::IN8, Convert, { MCK_insb } },
+ { X86::IN32, Convert, { MCK_insl } },
+ { X86::IN16, Convert, { MCK_insw } },
+ { X86::INVD, Convert, { MCK_invd } },
+ { X86::INVEPT, Convert, { MCK_invept } },
+ { X86::INVLPG, Convert, { MCK_invlpg } },
+ { X86::INVVPID, Convert, { MCK_invvpid } },
+ { X86::IRET32, Convert, { MCK_iretl } },
+ { X86::IRET64, Convert, { MCK_iretq } },
+ { X86::IRET16, Convert, { MCK_iretw } },
{ X86::LAHF, Convert, { MCK_lahf } },
{ X86::LEAVE, Convert, { MCK_leave } },
{ X86::LEAVE64, Convert, { MCK_leave } },
{ X86::LFENCE, Convert, { MCK_lfence } },
{ X86::LODSB, Convert, { MCK_lodsb } },
- { X86::LODSD, Convert, { MCK_lodsd } },
+ { X86::LODSD, Convert, { MCK_lodsl } },
{ X86::LODSQ, Convert, { MCK_lodsq } },
{ X86::LODSW, Convert, { MCK_lodsw } },
{ X86::LRET, Convert, { MCK_lret } },
@@ -5088,10 +6321,17 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MONITOR, Convert, { MCK_monitor } },
{ X86::MWAIT, Convert, { MCK_mwait } },
{ X86::NOOP, Convert, { MCK_nop } },
- { X86::POPFD, Convert, { MCK_popf } },
- { X86::POPFQ, Convert, { MCK_popf } },
- { X86::PUSHFD, Convert, { MCK_pushf } },
- { X86::PUSHFQ, Convert, { MCK_pushf } },
+ { X86::OUTSB, Convert, { MCK_outsb } },
+ { X86::OUTSD, Convert, { MCK_outsl } },
+ { X86::OUTSW, Convert, { MCK_outsw } },
+ { X86::POPFD, Convert, { MCK_popfl } },
+ { X86::POPFQ, Convert, { MCK_popfq } },
+ { X86::POPF, Convert, { MCK_popfw } },
+ { X86::PUSHFD, Convert, { MCK_pushfl } },
+ { X86::PUSHFQ64, Convert, { MCK_pushfq } },
+ { X86::PUSHF, Convert, { MCK_pushfw } },
+ { X86::RDMSR, Convert, { MCK_rdmsr } },
+ { X86::RDPMC, Convert, { MCK_rdpmc } },
{ X86::RDTSC, Convert, { MCK_rdtsc } },
{ X86::REP_MOVSB, Convert, { MCK_rep_59_movsb } },
{ X86::REP_MOVSD, Convert, { MCK_rep_59_movsl } },
@@ -5103,35 +6343,49 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::REP_STOSW, Convert, { MCK_rep_59_stosw } },
{ X86::EH_RETURN64, ConvertImp, { MCK_ret } },
{ X86::RET, Convert, { MCK_ret } },
+ { X86::RSM, Convert, { MCK_rsm } },
{ X86::SAHF, Convert, { MCK_sahf } },
{ X86::SCAS8, Convert, { MCK_scasb } },
{ X86::SCAS32, Convert, { MCK_scasl } },
{ X86::SCAS64, Convert, { MCK_scasq } },
{ X86::SCAS16, Convert, { MCK_scasw } },
{ X86::SFENCE, Convert, { MCK_sfence } },
+ { X86::STC, Convert, { MCK_stc } },
+ { X86::STD, Convert, { MCK_std } },
+ { X86::STI, Convert, { MCK_sti } },
+ { X86::SWPGS, Convert, { MCK_swpgs } },
{ X86::SYSCALL, Convert, { MCK_syscall } },
{ X86::SYSENTER, Convert, { MCK_sysenter } },
- { X86::SYSEXIT, Convert, { MCK_sysexit } },
{ X86::SYSEXIT64, Convert, { MCK_sysexit } },
+ { X86::SYSEXIT, Convert, { MCK_sysexit } },
{ X86::SYSRET, Convert, { MCK_sysret } },
{ X86::TRAP, Convert, { MCK_ud2 } },
+ { X86::VMCALL, Convert, { MCK_vmcall } },
+ { X86::VMLAUNCH, Convert, { MCK_vmlaunch } },
+ { X86::VMRESUME, Convert, { MCK_vmresume } },
+ { X86::VMXOFF, Convert, { MCK_vmxoff } },
{ X86::WAIT, Convert, { MCK_wait } },
+ { X86::WBINVD, Convert, { MCK_wbinvd } },
+ { X86::WRMSR, Convert, { MCK_wrmsr } },
+ { X86::XLAT, Convert, { MCK_xlatb } },
{ X86::BSWAP32r, Convert_Reg1_1Imp, { MCK_bswapl, MCK_GR32 } },
{ X86::BSWAP64r, Convert_Reg1_1Imp, { MCK_bswapq, MCK_GR64 } },
- { X86::WINCALL64pcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
- { X86::CALL64pcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
{ X86::CALLpcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
+ { X86::WINCALL64pcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
+ { X86::CALL64pcrel32, Convert_Imm1_1, { MCK_callq, MCK_Imm } },
{ X86::CLFLUSH, Convert_Mem5_1, { MCK_clflush, MCK_Mem } },
+ { X86::CMPXCHG16B, Convert_Mem5_1, { MCK_cmpxchg16b, MCK_Mem } },
+ { X86::CMPXCHG8B, Convert_Mem5_1, { MCK_cmpxchg8b, MCK_Mem } },
{ X86::DEC8r, Convert_Reg1_1Imp, { MCK_decb, MCK_GR8 } },
{ X86::DEC8m, Convert_Mem5_1, { MCK_decb, MCK_Mem } },
{ X86::DEC32r, Convert_Reg1_1Imp, { MCK_decl, MCK_GR32 } },
{ X86::DEC64_32r, Convert_Reg1_1Imp, { MCK_decl, MCK_GR32 } },
- { X86::DEC64_32m, Convert_Mem5_1, { MCK_decl, MCK_Mem } },
{ X86::DEC32m, Convert_Mem5_1, { MCK_decl, MCK_Mem } },
+ { X86::DEC64_32m, Convert_Mem5_1, { MCK_decl, MCK_Mem } },
{ X86::DEC64r, Convert_Reg1_1Imp, { MCK_decq, MCK_GR64 } },
{ X86::DEC64m, Convert_Mem5_1, { MCK_decq, MCK_Mem } },
- { X86::DEC64_16r, Convert_Reg1_1Imp, { MCK_decw, MCK_GR16 } },
{ X86::DEC16r, Convert_Reg1_1Imp, { MCK_decw, MCK_GR16 } },
+ { X86::DEC64_16r, Convert_Reg1_1Imp, { MCK_decw, MCK_GR16 } },
{ X86::DEC64_16m, Convert_Mem5_1, { MCK_decw, MCK_Mem } },
{ X86::DEC16m, Convert_Mem5_1, { MCK_decw, MCK_Mem } },
{ X86::DIV8r, Convert_Reg1_1, { MCK_divb, MCK_GR8 } },
@@ -5148,10 +6402,12 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::ADD_F32m, Convert_Mem5_1, { MCK_fadds, MCK_Mem } },
{ X86::FBLDm, Convert_Mem5_1, { MCK_fbld, MCK_Mem } },
{ X86::FBSTPm, Convert_Mem5_1, { MCK_fbstp, MCK_Mem } },
- { X86::FCOM32m, Convert_Mem5_1, { MCK_fcom, MCK_Mem } },
- { X86::FCOM64m, Convert_Mem5_1, { MCK_fcom, MCK_Mem } },
- { X86::FCOMP32m, Convert_Mem5_1, { MCK_fcomp, MCK_Mem } },
- { X86::FCOMP64m, Convert_Mem5_1, { MCK_fcomp, MCK_Mem } },
+ { X86::COM_FST0r, Convert_Reg1_1, { MCK_fcom, MCK_RST } },
+ { X86::FCOM32m, Convert_Mem5_1, { MCK_fcoml, MCK_Mem } },
+ { X86::FCOM64m, Convert_Mem5_1, { MCK_fcomll, MCK_Mem } },
+ { X86::COMP_FST0r, Convert_Reg1_1, { MCK_fcomp, MCK_RST } },
+ { X86::FCOMP32m, Convert_Mem5_1, { MCK_fcompl, MCK_Mem } },
+ { X86::FCOMP64m, Convert_Mem5_1, { MCK_fcompll, MCK_Mem } },
{ X86::DIV_FST0r, Convert_Reg1_1, { MCK_fdiv, MCK_RST } },
{ X86::DIV_F64m, Convert_Mem5_1, { MCK_fdivl, MCK_Mem } },
{ X86::DIVR_FPrST0, Convert_Reg1_1, { MCK_fdivp, MCK_RST } },
@@ -5160,6 +6416,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::DIV_FPrST0, Convert_Reg1_1, { MCK_fdivrp, MCK_RST } },
{ X86::DIVR_F32m, Convert_Mem5_1, { MCK_fdivrs, MCK_Mem } },
{ X86::DIV_F32m, Convert_Mem5_1, { MCK_fdivs, MCK_Mem } },
+ { X86::FFREE, Convert_Reg1_1, { MCK_ffree, MCK_RST } },
{ X86::ADD_FI32m, Convert_Mem5_1, { MCK_fiaddl, MCK_Mem } },
{ X86::ADD_FI16m, Convert_Mem5_1, { MCK_fiadds, MCK_Mem } },
{ X86::FICOM32m, Convert_Mem5_1, { MCK_ficoml, MCK_Mem } },
@@ -5198,18 +6455,19 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MUL_F64m, Convert_Mem5_1, { MCK_fmull, MCK_Mem } },
{ X86::MUL_FPrST0, Convert_Reg1_1, { MCK_fmulp, MCK_RST } },
{ X86::MUL_F32m, Convert_Mem5_1, { MCK_fmuls, MCK_Mem } },
+ { X86::FSAVEm, Convert_Mem5_1, { MCK_fnsave, MCK_Mem } },
{ X86::FNSTCW16m, Convert_Mem5_1, { MCK_fnstcw, MCK_Mem } },
+ { X86::FSTENVm, Convert_Mem5_1, { MCK_fnstenv, MCK_Mem } },
+ { X86::FNSTSW8r, Convert, { MCK_fnstsw, MCK_AX } },
+ { X86::FNSTSWm, Convert_Mem5_1, { MCK_fnstsw, MCK_Mem } },
{ X86::FRSTORm, Convert_Mem5_1, { MCK_frstor, MCK_Mem } },
- { X86::FSAVEm, Convert_Mem5_1, { MCK_fsave, MCK_Mem } },
{ X86::ST_Frr, Convert_Reg1_1, { MCK_fst, MCK_RST } },
- { X86::FSTENVm, Convert_Mem5_1, { MCK_fstenv, MCK_Mem } },
{ X86::ST_F64m, Convert_Mem5_1, { MCK_fstl, MCK_Mem } },
{ X86::ST_FPrr, Convert_Reg1_1, { MCK_fstp, MCK_RST } },
{ X86::ST_FP64m, Convert_Mem5_1, { MCK_fstpl, MCK_Mem } },
{ X86::ST_FP32m, Convert_Mem5_1, { MCK_fstps, MCK_Mem } },
{ X86::ST_FP80m, Convert_Mem5_1, { MCK_fstpt, MCK_Mem } },
{ X86::ST_F32m, Convert_Mem5_1, { MCK_fsts, MCK_Mem } },
- { X86::FSTSWm, Convert_Mem5_1, { MCK_fstsw, MCK_Mem } },
{ X86::SUB_FST0r, Convert_Reg1_1, { MCK_fsub, MCK_RST } },
{ X86::SUB_F64m, Convert_Mem5_1, { MCK_fsubl, MCK_Mem } },
{ X86::SUBR_FPrST0, Convert_Reg1_1, { MCK_fsubp, MCK_RST } },
@@ -5221,6 +6479,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::UCOM_Fr, Convert_Reg1_1, { MCK_fucom, MCK_RST } },
{ X86::UCOM_FPr, Convert_Reg1_1, { MCK_fucomp, MCK_RST } },
{ X86::XCH_F, Convert_Reg1_1, { MCK_fxch, MCK_RST } },
+ { X86::FXRSTOR, Convert_Mem5_1, { MCK_fxrstor, MCK_Mem } },
+ { X86::FXSAVE, Convert_Mem5_1, { MCK_fxsave, MCK_Mem } },
{ X86::IDIV8r, Convert_Reg1_1, { MCK_idivb, MCK_GR8 } },
{ X86::IDIV8m, Convert_Mem5_1, { MCK_idivb, MCK_Mem } },
{ X86::IDIV32r, Convert_Reg1_1, { MCK_idivl, MCK_GR32 } },
@@ -5241,57 +6501,66 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::INC8m, Convert_Mem5_1, { MCK_incb, MCK_Mem } },
{ X86::INC64_32r, Convert_Reg1_1Imp, { MCK_incl, MCK_GR32 } },
{ X86::INC32r, Convert_Reg1_1Imp, { MCK_incl, MCK_GR32 } },
- { X86::INC32m, Convert_Mem5_1, { MCK_incl, MCK_Mem } },
{ X86::INC64_32m, Convert_Mem5_1, { MCK_incl, MCK_Mem } },
+ { X86::INC32m, Convert_Mem5_1, { MCK_incl, MCK_Mem } },
{ X86::INC64r, Convert_Reg1_1Imp, { MCK_incq, MCK_GR64 } },
{ X86::INC64m, Convert_Mem5_1, { MCK_incq, MCK_Mem } },
- { X86::INC16r, Convert_Reg1_1Imp, { MCK_incw, MCK_GR16 } },
{ X86::INC64_16r, Convert_Reg1_1Imp, { MCK_incw, MCK_GR16 } },
- { X86::INC16m, Convert_Mem5_1, { MCK_incw, MCK_Mem } },
+ { X86::INC16r, Convert_Reg1_1Imp, { MCK_incw, MCK_GR16 } },
{ X86::INC64_16m, Convert_Mem5_1, { MCK_incw, MCK_Mem } },
+ { X86::INC16m, Convert_Mem5_1, { MCK_incw, MCK_Mem } },
{ X86::INT3, Convert, { MCK_int, MCK_3 } },
{ X86::INT, Convert_Imm1_1, { MCK_int, MCK_Imm } },
- { X86::JA8, Convert_Imm1_1, { MCK_ja, MCK_Imm } },
{ X86::JA, Convert_Imm1_1, { MCK_ja, MCK_Imm } },
- { X86::JAE8, Convert_Imm1_1, { MCK_jae, MCK_Imm } },
+ { X86::JA8, Convert_Imm1_1, { MCK_ja, MCK_Imm } },
{ X86::JAE, Convert_Imm1_1, { MCK_jae, MCK_Imm } },
- { X86::JB8, Convert_Imm1_1, { MCK_jb, MCK_Imm } },
+ { X86::JAE8, Convert_Imm1_1, { MCK_jae, MCK_Imm } },
{ X86::JB, Convert_Imm1_1, { MCK_jb, MCK_Imm } },
- { X86::JBE, Convert_Imm1_1, { MCK_jbe, MCK_Imm } },
+ { X86::JB8, Convert_Imm1_1, { MCK_jb, MCK_Imm } },
{ X86::JBE8, Convert_Imm1_1, { MCK_jbe, MCK_Imm } },
+ { X86::JBE, Convert_Imm1_1, { MCK_jbe, MCK_Imm } },
{ X86::JCXZ8, Convert_Imm1_1, { MCK_jcxz, MCK_Imm } },
{ X86::JE, Convert_Imm1_1, { MCK_je, MCK_Imm } },
{ X86::JE8, Convert_Imm1_1, { MCK_je, MCK_Imm } },
{ X86::JG, Convert_Imm1_1, { MCK_jg, MCK_Imm } },
{ X86::JG8, Convert_Imm1_1, { MCK_jg, MCK_Imm } },
- { X86::JGE, Convert_Imm1_1, { MCK_jge, MCK_Imm } },
{ X86::JGE8, Convert_Imm1_1, { MCK_jge, MCK_Imm } },
- { X86::JL, Convert_Imm1_1, { MCK_jl, MCK_Imm } },
+ { X86::JGE, Convert_Imm1_1, { MCK_jge, MCK_Imm } },
{ X86::JL8, Convert_Imm1_1, { MCK_jl, MCK_Imm } },
- { X86::JLE, Convert_Imm1_1, { MCK_jle, MCK_Imm } },
+ { X86::JL, Convert_Imm1_1, { MCK_jl, MCK_Imm } },
{ X86::JLE8, Convert_Imm1_1, { MCK_jle, MCK_Imm } },
- { X86::TAILJMPd, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
+ { X86::JLE, Convert_Imm1_1, { MCK_jle, MCK_Imm } },
{ X86::JMP, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
{ X86::JMP8, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
+ { X86::TAILJMPd, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
+ { X86::JMP64pcrel32, Convert_Imm1_1, { MCK_jmpq, MCK_Imm } },
{ X86::JNE, Convert_Imm1_1, { MCK_jne, MCK_Imm } },
{ X86::JNE8, Convert_Imm1_1, { MCK_jne, MCK_Imm } },
{ X86::JNO, Convert_Imm1_1, { MCK_jno, MCK_Imm } },
{ X86::JNO8, Convert_Imm1_1, { MCK_jno, MCK_Imm } },
- { X86::JNP, Convert_Imm1_1, { MCK_jnp, MCK_Imm } },
{ X86::JNP8, Convert_Imm1_1, { MCK_jnp, MCK_Imm } },
- { X86::JNS, Convert_Imm1_1, { MCK_jns, MCK_Imm } },
+ { X86::JNP, Convert_Imm1_1, { MCK_jnp, MCK_Imm } },
{ X86::JNS8, Convert_Imm1_1, { MCK_jns, MCK_Imm } },
+ { X86::JNS, Convert_Imm1_1, { MCK_jns, MCK_Imm } },
{ X86::JO8, Convert_Imm1_1, { MCK_jo, MCK_Imm } },
{ X86::JO, Convert_Imm1_1, { MCK_jo, MCK_Imm } },
- { X86::JP8, Convert_Imm1_1, { MCK_jp, MCK_Imm } },
{ X86::JP, Convert_Imm1_1, { MCK_jp, MCK_Imm } },
- { X86::JS, Convert_Imm1_1, { MCK_js, MCK_Imm } },
+ { X86::JP8, Convert_Imm1_1, { MCK_jp, MCK_Imm } },
{ X86::JS8, Convert_Imm1_1, { MCK_js, MCK_Imm } },
+ { X86::JS, Convert_Imm1_1, { MCK_js, MCK_Imm } },
{ X86::LDMXCSR, Convert_Mem5_1, { MCK_ldmxcsr, MCK_Mem } },
+ { X86::LGDTm, Convert_Mem5_1, { MCK_lgdt, MCK_Mem } },
+ { X86::LIDTm, Convert_Mem5_1, { MCK_lidt, MCK_Mem } },
+ { X86::LLDT16r, Convert_Reg1_1, { MCK_lldtw, MCK_GR16 } },
+ { X86::LLDT16m, Convert_Mem5_1, { MCK_lldtw, MCK_Mem } },
+ { X86::LMSW16r, Convert_Reg1_1, { MCK_lmsww, MCK_GR16 } },
+ { X86::LMSW16m, Convert_Mem5_1, { MCK_lmsww, MCK_Mem } },
{ X86::LOOP, Convert_Imm1_1, { MCK_loop, MCK_Imm } },
{ X86::LOOPE, Convert_Imm1_1, { MCK_loope, MCK_Imm } },
{ X86::LOOPNE, Convert_Imm1_1, { MCK_loopne, MCK_Imm } },
{ X86::LRETI, Convert_Imm1_1, { MCK_lret, MCK_Imm } },
+ { X86::LTRr, Convert_Reg1_1, { MCK_ltrw, MCK_GR16 } },
+ { X86::LTRm, Convert_Mem5_1, { MCK_ltrw, MCK_Mem } },
{ X86::MUL8r, Convert_Reg1_1, { MCK_mulb, MCK_GR8 } },
{ X86::MUL8m, Convert_Mem5_1, { MCK_mulb, MCK_Mem } },
{ X86::MUL32r, Convert_Reg1_1, { MCK_mull, MCK_GR32 } },
@@ -5309,6 +6578,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::NEG16r, Convert_Reg1_1Imp, { MCK_negw, MCK_GR16 } },
{ X86::NEG16m, Convert_Mem5_1, { MCK_negw, MCK_Mem } },
{ X86::NOOPL, Convert_Mem5_1, { MCK_nopl, MCK_Mem } },
+ { X86::NOOPW, Convert_Mem5_1, { MCK_nopw, MCK_Mem } },
{ X86::NOT8r, Convert_Reg1_1Imp, { MCK_notb, MCK_GR8 } },
{ X86::NOT8m, Convert_Mem5_1, { MCK_notb, MCK_Mem } },
{ X86::NOT32r, Convert_Reg1_1Imp, { MCK_notl, MCK_GR32 } },
@@ -5317,14 +6587,20 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::NOT64m, Convert_Mem5_1, { MCK_notq, MCK_Mem } },
{ X86::NOT16r, Convert_Reg1_1Imp, { MCK_notw, MCK_GR16 } },
{ X86::NOT16m, Convert_Mem5_1, { MCK_notw, MCK_Mem } },
- { X86::POP32rmr, Convert_Reg1_1, { MCK_popl, MCK_GR32 } },
{ X86::POP32r, Convert_Reg1_1, { MCK_popl, MCK_GR32 } },
+ { X86::POP32rmr, Convert_Reg1_1, { MCK_popl, MCK_GR32 } },
+ { X86::POPFS32, Convert, { MCK_popl, MCK_FS } },
+ { X86::POPGS32, Convert, { MCK_popl, MCK_GS } },
{ X86::POP32rmm, Convert_Mem5_1, { MCK_popl, MCK_Mem } },
- { X86::POP64r, Convert_Reg1_1, { MCK_popq, MCK_GR64 } },
{ X86::POP64rmr, Convert_Reg1_1, { MCK_popq, MCK_GR64 } },
+ { X86::POP64r, Convert_Reg1_1, { MCK_popq, MCK_GR64 } },
+ { X86::POPFS64, Convert, { MCK_popq, MCK_FS } },
+ { X86::POPGS64, Convert, { MCK_popq, MCK_GS } },
{ X86::POP64rmm, Convert_Mem5_1, { MCK_popq, MCK_Mem } },
{ X86::POP16r, Convert_Reg1_1, { MCK_popw, MCK_GR16 } },
{ X86::POP16rmr, Convert_Reg1_1, { MCK_popw, MCK_GR16 } },
+ { X86::POPFS16, Convert, { MCK_popw, MCK_FS } },
+ { X86::POPGS16, Convert, { MCK_popw, MCK_GS } },
{ X86::POP16rmm, Convert_Mem5_1, { MCK_popw, MCK_Mem } },
{ X86::PREFETCHNTA, Convert_Mem5_1, { MCK_prefetchnta, MCK_Mem } },
{ X86::PREFETCHT0, Convert_Mem5_1, { MCK_prefetcht0, MCK_Mem } },
@@ -5332,18 +6608,24 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::PREFETCHT2, Convert_Mem5_1, { MCK_prefetcht2, MCK_Mem } },
{ X86::PUSH32r, Convert_Reg1_1, { MCK_pushl, MCK_GR32 } },
{ X86::PUSH32rmr, Convert_Reg1_1, { MCK_pushl, MCK_GR32 } },
- { X86::PUSH32i8, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
+ { X86::PUSHFS32, Convert, { MCK_pushl, MCK_FS } },
+ { X86::PUSHGS32, Convert, { MCK_pushl, MCK_GS } },
{ X86::PUSH32i32, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
+ { X86::PUSH32i8, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
{ X86::PUSH32i16, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
{ X86::PUSH32rmm, Convert_Mem5_1, { MCK_pushl, MCK_Mem } },
- { X86::PUSH64r, Convert_Reg1_1, { MCK_pushq, MCK_GR64 } },
{ X86::PUSH64rmr, Convert_Reg1_1, { MCK_pushq, MCK_GR64 } },
- { X86::PUSH64i16, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
- { X86::PUSH64i32, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
+ { X86::PUSH64r, Convert_Reg1_1, { MCK_pushq, MCK_GR64 } },
+ { X86::PUSHFS64, Convert, { MCK_pushq, MCK_FS } },
+ { X86::PUSHGS64, Convert, { MCK_pushq, MCK_GS } },
{ X86::PUSH64i8, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
+ { X86::PUSH64i32, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
+ { X86::PUSH64i16, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
{ X86::PUSH64rmm, Convert_Mem5_1, { MCK_pushq, MCK_Mem } },
- { X86::PUSH16rmr, Convert_Reg1_1, { MCK_pushw, MCK_GR16 } },
{ X86::PUSH16r, Convert_Reg1_1, { MCK_pushw, MCK_GR16 } },
+ { X86::PUSH16rmr, Convert_Reg1_1, { MCK_pushw, MCK_GR16 } },
+ { X86::PUSHFS16, Convert, { MCK_pushw, MCK_FS } },
+ { X86::PUSHGS16, Convert, { MCK_pushw, MCK_GS } },
{ X86::PUSH16rmm, Convert_Mem5_1, { MCK_pushw, MCK_Mem } },
{ X86::RETI, Convert_Imm1_1, { MCK_ret, MCK_Imm } },
{ X86::ROL8r1, Convert_Reg1_1Imp, { MCK_rolb, MCK_GR8 } },
@@ -5402,10 +6684,12 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SETPm, Convert_Mem5_1, { MCK_setp, MCK_Mem } },
{ X86::SETSr, Convert_Reg1_1, { MCK_sets, MCK_GR8 } },
{ X86::SETSm, Convert_Mem5_1, { MCK_sets, MCK_Mem } },
+ { X86::SGDTm, Convert_Mem5_1, { MCK_sgdt, MCK_Mem } },
{ X86::SHL8r1, Convert_Reg1_1Imp, { MCK_shlb, MCK_GR8 } },
{ X86::SHL8m1, Convert_Mem5_1, { MCK_shlb, MCK_Mem } },
{ X86::SHL32r1, Convert_Reg1_1Imp, { MCK_shll, MCK_GR32 } },
{ X86::SHL32m1, Convert_Mem5_1, { MCK_shll, MCK_Mem } },
+ { X86::SHL64r1, Convert_Reg1_1Imp, { MCK_shlq, MCK_GR64 } },
{ X86::SHL64m1, Convert_Mem5_1, { MCK_shlq, MCK_Mem } },
{ X86::SHL16r1, Convert_Reg1_1Imp, { MCK_shlw, MCK_GR16 } },
{ X86::SHL16m1, Convert_Mem5_1, { MCK_shlw, MCK_Mem } },
@@ -5414,17 +6698,37 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SHR32r1, Convert_Reg1_1Imp, { MCK_shrl, MCK_GR32 } },
{ X86::SHR32m1, Convert_Mem5_1, { MCK_shrl, MCK_Mem } },
{ X86::SHR64r1, Convert_Reg1_1Imp, { MCK_shrq, MCK_GR64 } },
- { X86::SHL64r1, Convert_Reg1_1Imp, { MCK_shrq, MCK_GR64 } },
{ X86::SHR64m1, Convert_Mem5_1, { MCK_shrq, MCK_Mem } },
{ X86::SHR16r1, Convert_Reg1_1Imp, { MCK_shrw, MCK_GR16 } },
{ X86::SHR16m1, Convert_Mem5_1, { MCK_shrw, MCK_Mem } },
+ { X86::SIDTm, Convert_Mem5_1, { MCK_sidt, MCK_Mem } },
+ { X86::SLDT64r, Convert_Reg1_1, { MCK_sldtq, MCK_GR64 } },
+ { X86::SLDT64m, Convert_Mem5_1, { MCK_sldtq, MCK_Mem } },
+ { X86::SLDT16r, Convert_Reg1_1, { MCK_sldtw, MCK_GR16 } },
+ { X86::SLDT16m, Convert_Mem5_1, { MCK_sldtw, MCK_Mem } },
+ { X86::SMSW32r, Convert_Reg1_1, { MCK_smswl, MCK_GR32 } },
+ { X86::SMSW64r, Convert_Reg1_1, { MCK_smswq, MCK_GR64 } },
+ { X86::SMSW16r, Convert_Reg1_1, { MCK_smsww, MCK_GR16 } },
+ { X86::SMSW16m, Convert_Mem5_1, { MCK_smsww, MCK_Mem } },
{ X86::STMXCSR, Convert_Mem5_1, { MCK_stmxcsr, MCK_Mem } },
+ { X86::STRr, Convert_Reg1_1, { MCK_strw, MCK_GR16 } },
+ { X86::STRm, Convert_Mem5_1, { MCK_strw, MCK_Mem } },
+ { X86::VERRr, Convert_Reg1_1, { MCK_verr, MCK_GR16 } },
+ { X86::VERRm, Convert_Mem5_1, { MCK_verr, MCK_Mem } },
+ { X86::VERWr, Convert_Reg1_1, { MCK_verw, MCK_GR16 } },
+ { X86::VERWm, Convert_Mem5_1, { MCK_verw, MCK_Mem } },
+ { X86::VMCLEARm, Convert_Mem5_1, { MCK_vmclear, MCK_Mem } },
+ { X86::VMPTRLDm, Convert_Mem5_1, { MCK_vmptrld, MCK_Mem } },
+ { X86::VMPTRSTm, Convert_Mem5_1, { MCK_vmptrst, MCK_Mem } },
+ { X86::VMXON, Convert_Mem5_1, { MCK_vmxon, MCK_Mem } },
{ X86::ADC8rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcb, MCK_GR8, MCK_GR8 } },
+ { X86::ADC8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_adcb, MCK_GR8, MCK_GR8 } },
{ X86::ADC8mr, Convert_Mem5_2_Reg1_1, { MCK_adcb, MCK_GR8, MCK_Mem } },
{ X86::ADC8i8, Convert_Imm1_1, { MCK_adcb, MCK_Imm, MCK_AL } },
{ X86::ADC8ri, Convert_Reg1_2_ImpImm1_1, { MCK_adcb, MCK_Imm, MCK_GR8 } },
{ X86::ADC8mi, Convert_Mem5_2_Imm1_1, { MCK_adcb, MCK_Imm, MCK_Mem } },
{ X86::ADC8rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcb, MCK_Mem, MCK_GR8 } },
+ { X86::ADC32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_adcl, MCK_GR32, MCK_GR32 } },
{ X86::ADC32rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcl, MCK_GR32, MCK_GR32 } },
{ X86::ADC32mr, Convert_Mem5_2_Reg1_1, { MCK_adcl, MCK_GR32, MCK_Mem } },
{ X86::ADC32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_adcl, MCK_ImmSExt8, MCK_GR32 } },
@@ -5433,6 +6737,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::ADC32ri, Convert_Reg1_2_ImpImm1_1, { MCK_adcl, MCK_Imm, MCK_GR32 } },
{ X86::ADC32mi, Convert_Mem5_2_Imm1_1, { MCK_adcl, MCK_Imm, MCK_Mem } },
{ X86::ADC32rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcl, MCK_Mem, MCK_GR32 } },
+ { X86::ADC64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_adcq, MCK_GR64, MCK_GR32 } },
{ X86::ADC64rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcq, MCK_GR64, MCK_GR64 } },
{ X86::ADC64mr, Convert_Mem5_2_Reg1_1, { MCK_adcq, MCK_GR64, MCK_Mem } },
{ X86::ADC64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_adcq, MCK_ImmSExt8, MCK_GR64 } },
@@ -5442,6 +6747,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::ADC64mi32, Convert_Mem5_2_Imm1_1, { MCK_adcq, MCK_Imm, MCK_Mem } },
{ X86::ADC64rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcq, MCK_Mem, MCK_GR64 } },
{ X86::ADC16rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcw, MCK_GR16, MCK_GR16 } },
+ { X86::ADC16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_adcw, MCK_GR16, MCK_GR16 } },
{ X86::ADC16mr, Convert_Mem5_2_Reg1_1, { MCK_adcw, MCK_GR16, MCK_Mem } },
{ X86::ADC16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_adcw, MCK_ImmSExt8, MCK_GR16 } },
{ X86::ADC16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_adcw, MCK_ImmSExt8, MCK_Mem } },
@@ -5496,11 +6802,13 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::ADD16mi, Convert_Mem5_2_Imm1_1, { MCK_addw, MCK_Imm, MCK_Mem } },
{ X86::ADD16rm, Convert_Reg1_2_ImpMem5_1, { MCK_addw, MCK_Mem, MCK_GR16 } },
{ X86::AND8rr, Convert_Reg1_2_ImpReg1_1, { MCK_andb, MCK_GR8, MCK_GR8 } },
+ { X86::AND8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_andb, MCK_GR8, MCK_GR8 } },
{ X86::AND8mr, Convert_Mem5_2_Reg1_1, { MCK_andb, MCK_GR8, MCK_Mem } },
{ X86::AND8i8, Convert_Imm1_1, { MCK_andb, MCK_Imm, MCK_AL } },
{ X86::AND8ri, Convert_Reg1_2_ImpImm1_1, { MCK_andb, MCK_Imm, MCK_GR8 } },
{ X86::AND8mi, Convert_Mem5_2_Imm1_1, { MCK_andb, MCK_Imm, MCK_Mem } },
{ X86::AND8rm, Convert_Reg1_2_ImpMem5_1, { MCK_andb, MCK_Mem, MCK_GR8 } },
+ { X86::AND32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_andl, MCK_GR32, MCK_GR32 } },
{ X86::AND32rr, Convert_Reg1_2_ImpReg1_1, { MCK_andl, MCK_GR32, MCK_GR32 } },
{ X86::AND32mr, Convert_Mem5_2_Reg1_1, { MCK_andl, MCK_GR32, MCK_Mem } },
{ X86::AND32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_andl, MCK_ImmSExt8, MCK_GR32 } },
@@ -5509,12 +6817,12 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::AND32ri, Convert_Reg1_2_ImpImm1_1, { MCK_andl, MCK_Imm, MCK_GR32 } },
{ X86::AND32mi, Convert_Mem5_2_Imm1_1, { MCK_andl, MCK_Imm, MCK_Mem } },
{ X86::AND32rm, Convert_Reg1_2_ImpMem5_1, { MCK_andl, MCK_Mem, MCK_GR32 } },
- { X86::ANDNPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnpd, MCK_FR32, MCK_FR32 } },
{ X86::FsANDNPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnpd, MCK_FR32, MCK_FR32 } },
+ { X86::ANDNPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnpd, MCK_FR32, MCK_FR32 } },
{ X86::FsANDNPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnpd, MCK_Mem, MCK_FR32 } },
{ X86::ANDNPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnpd, MCK_Mem, MCK_FR32 } },
- { X86::FsANDNPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnps, MCK_FR32, MCK_FR32 } },
{ X86::ANDNPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnps, MCK_FR32, MCK_FR32 } },
+ { X86::FsANDNPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnps, MCK_FR32, MCK_FR32 } },
{ X86::FsANDNPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnps, MCK_Mem, MCK_FR32 } },
{ X86::ANDNPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnps, MCK_Mem, MCK_FR32 } },
{ X86::FsANDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andpd, MCK_FR32, MCK_FR32 } },
@@ -5525,6 +6833,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::FsANDPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andps, MCK_FR32, MCK_FR32 } },
{ X86::ANDPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andps, MCK_Mem, MCK_FR32 } },
{ X86::FsANDPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andps, MCK_Mem, MCK_FR32 } },
+ { X86::AND64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_andq, MCK_GR64, MCK_GR64 } },
{ X86::AND64rr, Convert_Reg1_2_ImpReg1_1, { MCK_andq, MCK_GR64, MCK_GR64 } },
{ X86::AND64mr, Convert_Mem5_2_Reg1_1, { MCK_andq, MCK_GR64, MCK_Mem } },
{ X86::AND64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_andq, MCK_ImmSExt8, MCK_GR64 } },
@@ -5533,6 +6842,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::AND64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_andq, MCK_Imm, MCK_GR64 } },
{ X86::AND64mi32, Convert_Mem5_2_Imm1_1, { MCK_andq, MCK_Imm, MCK_Mem } },
{ X86::AND64rm, Convert_Reg1_2_ImpMem5_1, { MCK_andq, MCK_Mem, MCK_GR64 } },
+ { X86::AND16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_andw, MCK_GR16, MCK_GR16 } },
{ X86::AND16rr, Convert_Reg1_2_ImpReg1_1, { MCK_andw, MCK_GR16, MCK_GR16 } },
{ X86::AND16mr, Convert_Mem5_2_Reg1_1, { MCK_andw, MCK_GR16, MCK_Mem } },
{ X86::AND16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_andw, MCK_ImmSExt8, MCK_GR16 } },
@@ -5553,119 +6863,158 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::BSR64rm, Convert_Reg1_2_Mem5_1, { MCK_bsrq, MCK_Mem, MCK_GR64 } },
{ X86::BSR16rr, Convert_Reg1_2_Reg1_1, { MCK_bsrw, MCK_GR16, MCK_GR16 } },
{ X86::BSR16rm, Convert_Reg1_2_Mem5_1, { MCK_bsrw, MCK_Mem, MCK_GR16 } },
+ { X86::BTC32rr, Convert_Reg1_2_Reg1_1, { MCK_btcl, MCK_GR32, MCK_GR32 } },
+ { X86::BTC32mr, Convert_Mem5_2_Reg1_1, { MCK_btcl, MCK_GR32, MCK_Mem } },
+ { X86::BTC32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btcl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::BTC32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btcl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTC64rr, Convert_Reg1_2_Reg1_1, { MCK_btcq, MCK_GR64, MCK_GR64 } },
+ { X86::BTC64mr, Convert_Mem5_2_Reg1_1, { MCK_btcq, MCK_GR64, MCK_Mem } },
+ { X86::BTC64ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btcq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::BTC64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btcq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTC16rr, Convert_Reg1_2_Reg1_1, { MCK_btcw, MCK_GR16, MCK_GR16 } },
+ { X86::BTC16mr, Convert_Mem5_2_Reg1_1, { MCK_btcw, MCK_GR16, MCK_Mem } },
+ { X86::BTC16ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btcw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::BTC16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btcw, MCK_ImmSExt8, MCK_Mem } },
{ X86::BT32rr, Convert_Reg1_2_Reg1_1, { MCK_btl, MCK_GR32, MCK_GR32 } },
+ { X86::BT32mr, Convert_Mem5_2_Reg1_1, { MCK_btl, MCK_GR32, MCK_Mem } },
{ X86::BT32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btl, MCK_ImmSExt8, MCK_GR32 } },
{ X86::BT32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btl, MCK_ImmSExt8, MCK_Mem } },
{ X86::BT64rr, Convert_Reg1_2_Reg1_1, { MCK_btq, MCK_GR64, MCK_GR64 } },
+ { X86::BT64mr, Convert_Mem5_2_Reg1_1, { MCK_btq, MCK_GR64, MCK_Mem } },
{ X86::BT64ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btq, MCK_ImmSExt8, MCK_GR64 } },
{ X86::BT64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTR32rr, Convert_Reg1_2_Reg1_1, { MCK_btrl, MCK_GR32, MCK_GR32 } },
+ { X86::BTR32mr, Convert_Mem5_2_Reg1_1, { MCK_btrl, MCK_GR32, MCK_Mem } },
+ { X86::BTR32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btrl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::BTR32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btrl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTR64rr, Convert_Reg1_2_Reg1_1, { MCK_btrq, MCK_GR64, MCK_GR64 } },
+ { X86::BTR64mr, Convert_Mem5_2_Reg1_1, { MCK_btrq, MCK_GR64, MCK_Mem } },
+ { X86::BTR64ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btrq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::BTR64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btrq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTR16rr, Convert_Reg1_2_Reg1_1, { MCK_btrw, MCK_GR16, MCK_GR16 } },
+ { X86::BTR16mr, Convert_Mem5_2_Reg1_1, { MCK_btrw, MCK_GR16, MCK_Mem } },
+ { X86::BTR16ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btrw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::BTR16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btrw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTS32rr, Convert_Reg1_2_Reg1_1, { MCK_btsl, MCK_GR32, MCK_GR32 } },
+ { X86::BTS32mr, Convert_Mem5_2_Reg1_1, { MCK_btsl, MCK_GR32, MCK_Mem } },
+ { X86::BTS32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btsl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::BTS32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btsl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTS64rr, Convert_Reg1_2_Reg1_1, { MCK_btsq, MCK_GR64, MCK_GR64 } },
+ { X86::BTS64mr, Convert_Mem5_2_Reg1_1, { MCK_btsq, MCK_GR64, MCK_Mem } },
+ { X86::BTS64ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btsq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::BTS64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btsq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTS16rr, Convert_Reg1_2_Reg1_1, { MCK_btsw, MCK_GR16, MCK_GR16 } },
+ { X86::BTS16mr, Convert_Mem5_2_Reg1_1, { MCK_btsw, MCK_GR16, MCK_Mem } },
+ { X86::BTS16ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btsw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::BTS16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btsw, MCK_ImmSExt8, MCK_Mem } },
{ X86::BT16rr, Convert_Reg1_2_Reg1_1, { MCK_btw, MCK_GR16, MCK_GR16 } },
+ { X86::BT16mr, Convert_Mem5_2_Reg1_1, { MCK_btw, MCK_GR16, MCK_Mem } },
{ X86::BT16ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btw, MCK_ImmSExt8, MCK_GR16 } },
{ X86::BT16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btw, MCK_ImmSExt8, MCK_Mem } },
{ X86::CALL32r, Convert_Reg1_2, { MCK_call, MCK__STAR_, MCK_GR32 } },
- { X86::CALL64r, Convert_Reg1_2, { MCK_call, MCK__STAR_, MCK_GR64 } },
{ X86::WINCALL64r, Convert_Reg1_2, { MCK_call, MCK__STAR_, MCK_GR64 } },
- { X86::CALL64m, Convert_Mem5_2, { MCK_call, MCK__STAR_, MCK_Mem } },
- { X86::WINCALL64m, Convert_Mem5_2, { MCK_call, MCK__STAR_, MCK_Mem } },
{ X86::CALL32m, Convert_Mem5_2, { MCK_call, MCK__STAR_, MCK_Mem } },
- { X86::CMOVA16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmova, MCK_GR16, MCK_GR16 } },
- { X86::CMOVA32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmova, MCK_GR32, MCK_GR32 } },
- { X86::CMOVA64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmova, MCK_GR64, MCK_GR64 } },
- { X86::CMOVA16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmova, MCK_Mem, MCK_GR16 } },
- { X86::CMOVA32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmova, MCK_Mem, MCK_GR32 } },
- { X86::CMOVA64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmova, MCK_Mem, MCK_GR64 } },
- { X86::CMOVAE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovae, MCK_GR16, MCK_GR16 } },
- { X86::CMOVAE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovae, MCK_GR32, MCK_GR32 } },
- { X86::CMOVAE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovae, MCK_GR64, MCK_GR64 } },
- { X86::CMOVAE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovae, MCK_Mem, MCK_GR16 } },
- { X86::CMOVAE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovae, MCK_Mem, MCK_GR32 } },
- { X86::CMOVAE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovae, MCK_Mem, MCK_GR64 } },
- { X86::CMOVB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovb, MCK_GR16, MCK_GR16 } },
- { X86::CMOVB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovb, MCK_GR32, MCK_GR32 } },
- { X86::CMOVB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovb, MCK_GR64, MCK_GR64 } },
- { X86::CMOVB16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovb, MCK_Mem, MCK_GR16 } },
- { X86::CMOVB32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovb, MCK_Mem, MCK_GR32 } },
- { X86::CMOVB64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovb, MCK_Mem, MCK_GR64 } },
- { X86::CMOVBE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbe, MCK_GR16, MCK_GR16 } },
- { X86::CMOVBE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbe, MCK_GR32, MCK_GR32 } },
- { X86::CMOVBE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbe, MCK_GR64, MCK_GR64 } },
- { X86::CMOVBE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbe, MCK_Mem, MCK_GR16 } },
- { X86::CMOVBE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbe, MCK_Mem, MCK_GR32 } },
- { X86::CMOVBE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbe, MCK_Mem, MCK_GR64 } },
- { X86::CMOVE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmove, MCK_GR16, MCK_GR16 } },
- { X86::CMOVE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmove, MCK_GR32, MCK_GR32 } },
- { X86::CMOVE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmove, MCK_GR64, MCK_GR64 } },
- { X86::CMOVE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmove, MCK_Mem, MCK_GR16 } },
- { X86::CMOVE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmove, MCK_Mem, MCK_GR32 } },
- { X86::CMOVE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmove, MCK_Mem, MCK_GR64 } },
- { X86::CMOVG16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovg, MCK_GR16, MCK_GR16 } },
- { X86::CMOVG32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovg, MCK_GR32, MCK_GR32 } },
- { X86::CMOVG64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovg, MCK_GR64, MCK_GR64 } },
- { X86::CMOVG16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovg, MCK_Mem, MCK_GR16 } },
- { X86::CMOVG32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovg, MCK_Mem, MCK_GR32 } },
- { X86::CMOVG64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovg, MCK_Mem, MCK_GR64 } },
- { X86::CMOVGE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovge, MCK_GR16, MCK_GR16 } },
- { X86::CMOVGE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovge, MCK_GR32, MCK_GR32 } },
- { X86::CMOVGE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovge, MCK_GR64, MCK_GR64 } },
- { X86::CMOVGE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovge, MCK_Mem, MCK_GR16 } },
- { X86::CMOVGE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovge, MCK_Mem, MCK_GR32 } },
- { X86::CMOVGE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovge, MCK_Mem, MCK_GR64 } },
- { X86::CMOVL16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovl, MCK_GR16, MCK_GR16 } },
- { X86::CMOVL32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovl, MCK_GR32, MCK_GR32 } },
- { X86::CMOVL64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovl, MCK_GR64, MCK_GR64 } },
- { X86::CMOVL16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovl, MCK_Mem, MCK_GR16 } },
- { X86::CMOVL32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovl, MCK_Mem, MCK_GR32 } },
- { X86::CMOVL64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovl, MCK_Mem, MCK_GR64 } },
- { X86::CMOVLE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovle, MCK_GR16, MCK_GR16 } },
- { X86::CMOVLE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovle, MCK_GR32, MCK_GR32 } },
- { X86::CMOVLE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovle, MCK_GR64, MCK_GR64 } },
- { X86::CMOVLE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovle, MCK_Mem, MCK_GR16 } },
- { X86::CMOVLE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovle, MCK_Mem, MCK_GR32 } },
- { X86::CMOVLE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovle, MCK_Mem, MCK_GR64 } },
- { X86::CMOVNE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovne, MCK_GR16, MCK_GR16 } },
- { X86::CMOVNE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovne, MCK_GR32, MCK_GR32 } },
- { X86::CMOVNE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovne, MCK_GR64, MCK_GR64 } },
- { X86::CMOVNE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovne, MCK_Mem, MCK_GR16 } },
- { X86::CMOVNE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovne, MCK_Mem, MCK_GR32 } },
- { X86::CMOVNE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovne, MCK_Mem, MCK_GR64 } },
- { X86::CMOVNO16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovno, MCK_GR16, MCK_GR16 } },
- { X86::CMOVNO32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovno, MCK_GR32, MCK_GR32 } },
- { X86::CMOVNO64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovno, MCK_GR64, MCK_GR64 } },
- { X86::CMOVNO16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovno, MCK_Mem, MCK_GR16 } },
- { X86::CMOVNO32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovno, MCK_Mem, MCK_GR32 } },
- { X86::CMOVNO64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovno, MCK_Mem, MCK_GR64 } },
- { X86::CMOVNP16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnp, MCK_GR16, MCK_GR16 } },
- { X86::CMOVNP32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnp, MCK_GR32, MCK_GR32 } },
- { X86::CMOVNP64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnp, MCK_GR64, MCK_GR64 } },
- { X86::CMOVNP16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnp, MCK_Mem, MCK_GR16 } },
- { X86::CMOVNP32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnp, MCK_Mem, MCK_GR32 } },
- { X86::CMOVNP64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnp, MCK_Mem, MCK_GR64 } },
- { X86::CMOVNS16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovns, MCK_GR16, MCK_GR16 } },
- { X86::CMOVNS32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovns, MCK_GR32, MCK_GR32 } },
- { X86::CMOVNS64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovns, MCK_GR64, MCK_GR64 } },
- { X86::CMOVNS16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovns, MCK_Mem, MCK_GR16 } },
- { X86::CMOVNS32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovns, MCK_Mem, MCK_GR32 } },
- { X86::CMOVNS64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovns, MCK_Mem, MCK_GR64 } },
- { X86::CMOVO16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovo, MCK_GR16, MCK_GR16 } },
- { X86::CMOVO32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovo, MCK_GR32, MCK_GR32 } },
- { X86::CMOVO64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovo, MCK_GR64, MCK_GR64 } },
- { X86::CMOVO16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovo, MCK_Mem, MCK_GR16 } },
- { X86::CMOVO32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovo, MCK_Mem, MCK_GR32 } },
- { X86::CMOVO64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovo, MCK_Mem, MCK_GR64 } },
- { X86::CMOVP16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovp, MCK_GR16, MCK_GR16 } },
- { X86::CMOVP32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovp, MCK_GR32, MCK_GR32 } },
- { X86::CMOVP64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovp, MCK_GR64, MCK_GR64 } },
- { X86::CMOVP16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovp, MCK_Mem, MCK_GR16 } },
- { X86::CMOVP32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovp, MCK_Mem, MCK_GR32 } },
- { X86::CMOVP64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovp, MCK_Mem, MCK_GR64 } },
- { X86::CMOVS16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovs, MCK_GR16, MCK_GR16 } },
- { X86::CMOVS32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovs, MCK_GR32, MCK_GR32 } },
- { X86::CMOVS64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovs, MCK_GR64, MCK_GR64 } },
- { X86::CMOVS16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovs, MCK_Mem, MCK_GR16 } },
- { X86::CMOVS32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovs, MCK_Mem, MCK_GR32 } },
- { X86::CMOVS64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovs, MCK_Mem, MCK_GR64 } },
- { X86::CMP8mrmrr, Convert_Reg1_2_Reg1_1, { MCK_cmpb, MCK_GR8, MCK_GR8 } },
+ { X86::WINCALL64m, Convert_Mem5_2, { MCK_call, MCK__STAR_, MCK_Mem } },
+ { X86::CALL64r, Convert_Reg1_2, { MCK_callq, MCK__STAR_, MCK_GR64 } },
+ { X86::CALL64m, Convert_Mem5_2, { MCK_callq, MCK__STAR_, MCK_Mem } },
+ { X86::CMOVAE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovael, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVAE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovael, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVAE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovaeq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVAE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovaeq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVAE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovaew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVAE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovaew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVA32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmoval, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVA32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmoval, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVA64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovaq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVA64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovaq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVA16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovaw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVA16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovaw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVBE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbel, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVBE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbel, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVBE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbeq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVBE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbeq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVBE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVBE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVB32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVB64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVB16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovel, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovel, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmoveq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmoveq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVGE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgel, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVGE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgel, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVGE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgeq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVGE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgeq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVGE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVGE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVG32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVG32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVG64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVG64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVG16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVG16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVLE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovlel, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVLE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovlel, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVLE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovleq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVLE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovleq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVLE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovlew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVLE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovlew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVL32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovll, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVL32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovll, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVL64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovlq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVL64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovlq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVL16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovlw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVL16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovlw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnel, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnel, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovneq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovneq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNO32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnol, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNO32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnol, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNO64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnoq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNO64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnoq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNO16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnow, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNO16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnow, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNP32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnpl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNP32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnpl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNP64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnpq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNP64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnpq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNP16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnpw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNP16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnpw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNS32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnsl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNS32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnsl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNS64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnsq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNS64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnsq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNS16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnsw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNS16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnsw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVO32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovol, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVO32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovol, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVO64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovoq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVO64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovoq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVO16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovow, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVO16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovow, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVP32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovpl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVP32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovpl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVP64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovpq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVP64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovpq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVP16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovpw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVP16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovpw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVS32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovsl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVS32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovsl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVS64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovsq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVS64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovsq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVS16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovsw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVS16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovsw, MCK_Mem, MCK_GR16 } },
{ X86::CMP8rr, Convert_Reg1_2_Reg1_1, { MCK_cmpb, MCK_GR8, MCK_GR8 } },
+ { X86::CMP8mrmrr, Convert_Reg1_2_Reg1_1, { MCK_cmpb, MCK_GR8, MCK_GR8 } },
{ X86::CMP8mr, Convert_Mem5_2_Reg1_1, { MCK_cmpb, MCK_GR8, MCK_Mem } },
{ X86::CMP8i8, Convert_Imm1_1, { MCK_cmpb, MCK_Imm, MCK_AL } },
{ X86::CMP8ri, Convert_Reg1_2_Imm1_1, { MCK_cmpb, MCK_Imm, MCK_GR8 } },
@@ -5698,15 +7047,25 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::CMP16ri, Convert_Reg1_2_Imm1_1, { MCK_cmpw, MCK_Imm, MCK_GR16 } },
{ X86::CMP16mi, Convert_Mem5_2_Imm1_1, { MCK_cmpw, MCK_Imm, MCK_Mem } },
{ X86::CMP16rm, Convert_Reg1_2_Mem5_1, { MCK_cmpw, MCK_Mem, MCK_GR16 } },
+ { X86::CMPXCHG8rr, Convert_Reg1_2_Reg1_1, { MCK_cmpxchgb, MCK_GR8, MCK_GR8 } },
+ { X86::CMPXCHG8rm, Convert_Mem5_2_Reg1_1, { MCK_cmpxchgb, MCK_GR8, MCK_Mem } },
+ { X86::CMPXCHG32rr, Convert_Reg1_2_Reg1_1, { MCK_cmpxchgl, MCK_GR32, MCK_GR32 } },
+ { X86::CMPXCHG32rm, Convert_Mem5_2_Reg1_1, { MCK_cmpxchgl, MCK_GR32, MCK_Mem } },
+ { X86::CMPXCHG64rr, Convert_Reg1_2_Reg1_1, { MCK_cmpxchgq, MCK_GR64, MCK_GR64 } },
+ { X86::CMPXCHG64rm, Convert_Mem5_2_Reg1_1, { MCK_cmpxchgq, MCK_GR64, MCK_Mem } },
+ { X86::CMPXCHG16rr, Convert_Reg1_2_Reg1_1, { MCK_cmpxchgw, MCK_GR16, MCK_GR16 } },
+ { X86::CMPXCHG16rm, Convert_Mem5_2_Reg1_1, { MCK_cmpxchgw, MCK_GR16, MCK_Mem } },
{ X86::COMISDrr, Convert_Reg1_2_Reg1_1, { MCK_comisd, MCK_FR32, MCK_FR32 } },
{ X86::COMISDrm, Convert_Reg1_2_Mem5_1, { MCK_comisd, MCK_Mem, MCK_FR32 } },
+ { X86::COMISSrr, Convert_Reg1_2_Reg1_1, { MCK_comiss, MCK_FR32, MCK_FR32 } },
+ { X86::COMISSrm, Convert_Reg1_2_Mem5_1, { MCK_comiss, MCK_Mem, MCK_FR32 } },
{ X86::CRC32r8, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR8, MCK_GR32 } },
{ X86::CRC32r16, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR16, MCK_GR32 } },
{ X86::CRC32r32, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR32, MCK_GR32 } },
{ X86::CRC64r64, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR64, MCK_GR64 } },
- { X86::CRC32m8, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
- { X86::CRC32m32, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
{ X86::CRC32m16, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
+ { X86::CRC32m32, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
+ { X86::CRC32m8, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
{ X86::CRC64m64, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR64 } },
{ X86::CVTDQ2PDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtdq2pd, MCK_FR32, MCK_FR32 } },
{ X86::CVTDQ2PDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtdq2pd, MCK_Mem, MCK_FR32 } },
@@ -5716,14 +7075,20 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::CVTPD2DQrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpd2dq, MCK_Mem, MCK_FR32 } },
{ X86::MMX_CVTPD2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpd2pi, MCK_FR32, MCK_VR64 } },
{ X86::MMX_CVTPD2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpd2pi, MCK_Mem, MCK_VR64 } },
+ { X86::CVTPD2PSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpd2ps, MCK_FR32, MCK_FR32 } },
+ { X86::CVTPD2PSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpd2ps, MCK_Mem, MCK_FR32 } },
{ X86::MMX_CVTPI2PDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpi2pd, MCK_VR64, MCK_FR32 } },
{ X86::MMX_CVTPI2PDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpi2pd, MCK_Mem, MCK_FR32 } },
{ X86::MMX_CVTPI2PSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpi2ps, MCK_VR64, MCK_FR32 } },
{ X86::MMX_CVTPI2PSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpi2ps, MCK_Mem, MCK_FR32 } },
{ X86::CVTPS2DQrr, Convert_Reg1_2_Reg1_1, { MCK_cvtps2dq, MCK_FR32, MCK_FR32 } },
{ X86::CVTPS2DQrm, Convert_Reg1_2_Mem5_1, { MCK_cvtps2dq, MCK_Mem, MCK_FR32 } },
+ { X86::CVTPS2PDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtps2pd, MCK_FR32, MCK_FR32 } },
+ { X86::CVTPS2PDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtps2pd, MCK_Mem, MCK_FR32 } },
{ X86::MMX_CVTPS2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvtps2pi, MCK_FR32, MCK_VR64 } },
{ X86::MMX_CVTPS2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvtps2pi, MCK_Mem, MCK_VR64 } },
+ { X86::CVTSD2SI64rr, Convert_Reg1_2_Reg1_1, { MCK_cvtsd2siq, MCK_FR32, MCK_GR64 } },
+ { X86::CVTSD2SI64rm, Convert_Reg1_2_Mem5_1, { MCK_cvtsd2siq, MCK_Mem, MCK_GR64 } },
{ X86::CVTSD2SSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtsd2ss, MCK_FR32, MCK_FR32 } },
{ X86::CVTSD2SSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtsd2ss, MCK_Mem, MCK_FR32 } },
{ X86::CVTSI2SDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtsi2sd, MCK_GR32, MCK_FR32 } },
@@ -5736,8 +7101,14 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::CVTSI2SS64rm, Convert_Reg1_2_Mem5_1, { MCK_cvtsi2ssq, MCK_Mem, MCK_FR32 } },
{ X86::CVTSS2SDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtss2sd, MCK_FR32, MCK_FR32 } },
{ X86::CVTSS2SDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtss2sd, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSS2SIrr, Convert_Reg1_2_Reg1_1, { MCK_cvtss2sil, MCK_FR32, MCK_GR32 } },
+ { X86::CVTSS2SIrm, Convert_Reg1_2_Mem5_1, { MCK_cvtss2sil, MCK_Mem, MCK_GR32 } },
+ { X86::CVTSS2SI64rr, Convert_Reg1_2_Reg1_1, { MCK_cvtss2siq, MCK_FR32, MCK_GR64 } },
+ { X86::CVTSS2SI64rm, Convert_Reg1_2_Mem5_1, { MCK_cvtss2siq, MCK_Mem, MCK_GR64 } },
{ X86::MMX_CVTTPD2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvttpd2pi, MCK_FR32, MCK_VR64 } },
{ X86::MMX_CVTTPD2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvttpd2pi, MCK_Mem, MCK_VR64 } },
+ { X86::CVTTPS2DQrr, Convert_Reg1_2_Reg1_1, { MCK_cvttps2dq, MCK_FR32, MCK_FR32 } },
+ { X86::CVTTPS2DQrm, Convert_Reg1_2_Mem5_1, { MCK_cvttps2dq, MCK_Mem, MCK_FR32 } },
{ X86::MMX_CVTTPS2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvttps2pi, MCK_FR32, MCK_VR64 } },
{ X86::MMX_CVTTPS2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvttps2pi, MCK_Mem, MCK_VR64 } },
{ X86::CVTTSD2SIrr, Convert_Reg1_2_Reg1_1, { MCK_cvttsd2si, MCK_FR32, MCK_GR32 } },
@@ -5766,6 +7137,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::CMOVNE_F, Convert_Reg1_1, { MCK_fcmovne, MCK_RST, MCK_ST0 } },
{ X86::CMOVNP_F, Convert_Reg1_1, { MCK_fcmovnu, MCK_RST, MCK_ST0 } },
{ X86::CMOVP_F, Convert_Reg1_1, { MCK_fcmovu, MCK_RST, MCK_ST0 } },
+ { X86::COM_FIr, Convert_Reg1_1, { MCK_fcomi, MCK_RST, MCK_ST0 } },
+ { X86::COM_FIPr, Convert_Reg1_1, { MCK_fcomip, MCK_RST, MCK_ST0 } },
{ X86::DIVR_FrST0, Convert_Reg1_2, { MCK_fdiv, MCK_ST0, MCK_RST } },
{ X86::DIV_FrST0, Convert_Reg1_2, { MCK_fdivr, MCK_ST0, MCK_RST } },
{ X86::MUL_FrST0, Convert_Reg1_2, { MCK_fmul, MCK_ST0, MCK_RST } },
@@ -5794,8 +7167,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::IN16rr, Convert, { MCK_inw, MCK_DX, MCK_AX } },
{ X86::IN16ri, Convert_ImmSExt81_1, { MCK_inw, MCK_ImmSExt8, MCK_AX } },
{ X86::TAILJMPm, Convert_Mem5_2, { MCK_jmp, MCK__STAR_, MCK_Mem } },
- { X86::TAILJMPr, Convert_Reg1_2, { MCK_jmpl, MCK__STAR_, MCK_GR32 } },
{ X86::JMP32r, Convert_Reg1_2, { MCK_jmpl, MCK__STAR_, MCK_GR32 } },
+ { X86::TAILJMPr, Convert_Reg1_2, { MCK_jmpl, MCK__STAR_, MCK_GR32 } },
{ X86::JMP32m, Convert_Mem5_2, { MCK_jmpl, MCK__STAR_, MCK_Mem } },
{ X86::TAILJMPr64, Convert_Reg1_2, { MCK_jmpq, MCK__STAR_, MCK_GR64 } },
{ X86::JMP64r, Convert_Reg1_2, { MCK_jmpq, MCK__STAR_, MCK_GR64 } },
@@ -5812,19 +7185,38 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::FARCALL16m, Convert_Mem5_2, { MCK_lcallw, MCK__STAR_, MCK_Mem } },
{ X86::FARCALL16i, Convert_Imm1_1_Imm1_2, { MCK_lcallw, MCK_Imm, MCK_Imm } },
{ X86::LDDQUrm, Convert_Reg1_2_Mem5_1, { MCK_lddqu, MCK_Mem, MCK_FR32 } },
+ { X86::LDS32rm, Convert_Reg1_2_Mem5_1, { MCK_ldsl, MCK_Mem, MCK_GR32 } },
+ { X86::LDS16rm, Convert_Reg1_2_Mem5_1, { MCK_ldsw, MCK_Mem, MCK_GR16 } },
{ X86::LEA64_32r, Convert_Reg1_2_Mem4_1, { MCK_leal, MCK_Mem, MCK_GR32 } },
{ X86::LEA32r, Convert_Reg1_2_Mem4_1, { MCK_leal, MCK_Mem, MCK_GR32 } },
{ X86::LEA64r, Convert_Reg1_2_Mem4_1, { MCK_leaq, MCK_Mem, MCK_GR64 } },
{ X86::LEA16r, Convert_Reg1_2_Mem4_1, { MCK_leaw, MCK_Mem, MCK_GR16 } },
+ { X86::LES32rm, Convert_Reg1_2_Mem5_1, { MCK_lesl, MCK_Mem, MCK_GR32 } },
+ { X86::LES16rm, Convert_Reg1_2_Mem5_1, { MCK_lesw, MCK_Mem, MCK_GR16 } },
+ { X86::LFS32rm, Convert_Reg1_2_Mem5_1, { MCK_lfsl, MCK_Mem, MCK_GR32 } },
+ { X86::LFS64rm, Convert_Reg1_2_Mem5_1, { MCK_lfsq, MCK_Mem, MCK_GR64 } },
+ { X86::LFS16rm, Convert_Reg1_2_Mem5_1, { MCK_lfsw, MCK_Mem, MCK_GR16 } },
+ { X86::LGS32rm, Convert_Reg1_2_Mem5_1, { MCK_lgsl, MCK_Mem, MCK_GR32 } },
+ { X86::LGS64rm, Convert_Reg1_2_Mem5_1, { MCK_lgsq, MCK_Mem, MCK_GR64 } },
+ { X86::LGS16rm, Convert_Reg1_2_Mem5_1, { MCK_lgsw, MCK_Mem, MCK_GR16 } },
{ X86::FARJMP32m, Convert_Mem5_2, { MCK_ljmpl, MCK__STAR_, MCK_Mem } },
{ X86::FARJMP32i, Convert_Imm1_1_Imm1_2, { MCK_ljmpl, MCK_Imm, MCK_Imm } },
{ X86::FARJMP64, Convert_Mem5_2, { MCK_ljmpq, MCK__STAR_, MCK_Mem } },
{ X86::FARJMP16m, Convert_Mem5_2, { MCK_ljmpw, MCK__STAR_, MCK_Mem } },
{ X86::FARJMP16i, Convert_Imm1_1_Imm1_2, { MCK_ljmpw, MCK_Imm, MCK_Imm } },
- { X86::MASKMOVDQU, Convert_Reg1_2_Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
+ { X86::LSL32rr, Convert_Reg1_2_Reg1_1, { MCK_lsll, MCK_GR32, MCK_GR32 } },
+ { X86::LSL32rm, Convert_Reg1_2_Mem5_1, { MCK_lsll, MCK_Mem, MCK_GR32 } },
+ { X86::LSL64rr, Convert_Reg1_2_Reg1_1, { MCK_lslq, MCK_GR64, MCK_GR64 } },
+ { X86::LSL64rm, Convert_Reg1_2_Mem5_1, { MCK_lslq, MCK_Mem, MCK_GR64 } },
+ { X86::LSL16rr, Convert_Reg1_2_Reg1_1, { MCK_lslw, MCK_GR16, MCK_GR16 } },
+ { X86::LSL16rm, Convert_Reg1_2_Mem5_1, { MCK_lslw, MCK_Mem, MCK_GR16 } },
+ { X86::LSS32rm, Convert_Reg1_2_Mem5_1, { MCK_lssl, MCK_Mem, MCK_GR32 } },
+ { X86::LSS64rm, Convert_Reg1_2_Mem5_1, { MCK_lssq, MCK_Mem, MCK_GR64 } },
+ { X86::LSS16rm, Convert_Reg1_2_Mem5_1, { MCK_lssw, MCK_Mem, MCK_GR16 } },
{ X86::MASKMOVDQU64, Convert_Reg1_2_Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
- { X86::MMX_MASKMOVQ64, Convert_Reg1_2_Reg1_1, { MCK_maskmovq, MCK_VR64, MCK_VR64 } },
+ { X86::MASKMOVDQU, Convert_Reg1_2_Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
{ X86::MMX_MASKMOVQ, Convert_Reg1_2_Reg1_1, { MCK_maskmovq, MCK_VR64, MCK_VR64 } },
+ { X86::MMX_MASKMOVQ64, Convert_Reg1_2_Reg1_1, { MCK_maskmovq, MCK_VR64, MCK_VR64 } },
{ X86::MAXPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_maxpd, MCK_FR32, MCK_FR32 } },
{ X86::MAXPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_maxpd, MCK_Mem, MCK_FR32 } },
{ X86::MAXPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_maxps, MCK_FR32, MCK_FR32 } },
@@ -5855,6 +7247,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MOV8ao8, Convert_Imm1_2, { MCK_movb, MCK_AL, MCK_Imm } },
{ X86::MOV8rr_NOREX, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8_NOREX, MCK_GR8_NOREX } },
{ X86::MOV8mr_NOREX, Convert_Mem5_2_Reg1_1, { MCK_movb, MCK_GR8_NOREX, MCK_Mem } },
+ { X86::MOV8rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_GR8 } },
{ X86::MOV8rr, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_GR8 } },
{ X86::MOV8mr, Convert_Mem5_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_Mem } },
{ X86::MOV8o8a, Convert_Imm1_1, { MCK_movb, MCK_Imm, MCK_AL } },
@@ -5865,13 +7258,14 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MMX_MOVZDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_VR64 } },
{ X86::MMX_MOVD64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_VR64 } },
{ X86::MOVDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
- { X86::MOVDI2SSrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
{ X86::MOVZDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
+ { X86::MOVDI2SSrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
{ X86::MMX_MOVD64rrv164, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_VR64 } },
{ X86::MMX_MOVD64to64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_VR64 } },
{ X86::MOV64toSDrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
{ X86::MOV64toPQIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
{ X86::MOVZQI2PQIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
+ { X86::MMX_MOVD64grr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_VR64, MCK_GR32 } },
{ X86::MMX_MOVD64from64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_VR64, MCK_GR64 } },
{ X86::MMX_MOVD64mr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_VR64, MCK_Mem } },
{ X86::MOVSS2DIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR32 } },
@@ -5880,8 +7274,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MOVPQIto64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR64 } },
{ X86::MOVPDI2DImr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_Mem } },
{ X86::MOVSS2DImr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_Mem } },
- { X86::MMX_MOVZDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
{ X86::MMX_MOVD64rm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
+ { X86::MMX_MOVZDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
{ X86::MOVZDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
{ X86::MOVDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
{ X86::MOVDI2SSrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
@@ -5900,7 +7294,10 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MOVHPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_movhps, MCK_Mem, MCK_FR32 } },
{ X86::MOV32ao32, Convert_Imm1_2, { MCK_movl, MCK_EAX, MCK_Imm } },
{ X86::MOV32rr, Convert_Reg1_2_Reg1_1, { MCK_movl, MCK_GR32, MCK_GR32 } },
+ { X86::MOV32rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movl, MCK_GR32, MCK_GR32 } },
+ { X86::MOV32dr, Convert_Reg1_2_Reg1_1, { MCK_movl, MCK_GR32, MCK_DEBUG_REG } },
{ X86::MOV32mr, Convert_Mem5_2_Reg1_1, { MCK_movl, MCK_GR32, MCK_Mem } },
+ { X86::MOV32rd, Convert_Reg1_2_Reg1_1, { MCK_movl, MCK_DEBUG_REG, MCK_GR32 } },
{ X86::MOV32o32a, Convert_Imm1_1, { MCK_movl, MCK_Imm, MCK_EAX } },
{ X86::MOV32ri, Convert_Reg1_2_Imm1_1, { MCK_movl, MCK_Imm, MCK_GR32 } },
{ X86::MOV32mi, Convert_Mem5_2_Imm1_1, { MCK_movl, MCK_Imm, MCK_Mem } },
@@ -5918,58 +7315,73 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MOVNTPDmr, Convert_Mem5_2_Reg1_1, { MCK_movntpd, MCK_FR32, MCK_Mem } },
{ X86::MOVNTPSmr, Convert_Mem5_2_Reg1_1, { MCK_movntps, MCK_FR32, MCK_Mem } },
{ X86::MMX_MOVNTQmr, Convert_Mem5_2_Reg1_1, { MCK_movntq, MCK_VR64, MCK_Mem } },
+ { X86::MOV32cr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR32, MCK_CONTROL_REG_32 } },
+ { X86::MOV64ao64, Convert_Imm1_2, { MCK_movq, MCK_RAX, MCK_Imm } },
{ X86::MOV64ao8, Convert_Imm1_2, { MCK_movq, MCK_RAX, MCK_Imm } },
- { X86::MOV64ao32, Convert_Imm1_2, { MCK_movq, MCK_RAX, MCK_Imm } },
+ { X86::MOV64rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_GR64 } },
{ X86::MOV64rr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_GR64 } },
+ { X86::MOV64sr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_SEGMENT_REG } },
+ { X86::MOV64dr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_DEBUG_REG } },
+ { X86::MOV64cr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_CONTROL_REG_64 } },
{ X86::MOV64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_Mem } },
{ X86::MMX_MOVQ64rr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_VR64 } },
+ { X86::MMX_MOVQ64gmr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_Mem } },
{ X86::MMX_MOVQ64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_Mem } },
{ X86::MOVZPQILo2PQIrr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_FR32 } },
+ { X86::MOVQxrxr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLQ128mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
{ X86::MOVSDto64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
{ X86::MOVPQI2QImr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
- { X86::MOVLQ128mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
+ { X86::MOV64rs, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_SEGMENT_REG, MCK_GR64 } },
+ { X86::MOV64ms, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_SEGMENT_REG, MCK_Mem } },
+ { X86::MOV64rd, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_DEBUG_REG, MCK_GR64 } },
+ { X86::MOV32rc, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_CONTROL_REG_32, MCK_GR32 } },
+ { X86::MOV64rc, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_CONTROL_REG_64, MCK_GR64 } },
{ X86::MOV64o8a, Convert_Imm1_1, { MCK_movq, MCK_Imm, MCK_RAX } },
- { X86::MOV64o32a, Convert_Imm1_1, { MCK_movq, MCK_Imm, MCK_RAX } },
+ { X86::MOV64o64a, Convert_Imm1_1, { MCK_movq, MCK_Imm, MCK_RAX } },
{ X86::MOV64ri32, Convert_Reg1_2_Imm1_1, { MCK_movq, MCK_Imm, MCK_GR64 } },
{ X86::MOV64mi32, Convert_Mem5_2_Imm1_1, { MCK_movq, MCK_Imm, MCK_Mem } },
{ X86::MOV64rm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_GR64 } },
{ X86::MMX_MOVQ64rm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_VR64 } },
- { X86::MOV64toSDrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
{ X86::MOVQI2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
- { X86::MOVZQI2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
+ { X86::MOV64toSDrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
{ X86::MOVZPQILo2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
- { X86::MMX_MOVQ2DQrr, Convert_Reg1_2_Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
+ { X86::MOVZQI2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
+ { X86::MOV64sm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_SEGMENT_REG } },
{ X86::MMX_MOVQ2FR64rr, Convert_Reg1_2_Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
+ { X86::MMX_MOVQ2DQrr, Convert_Reg1_2_Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
{ X86::MOVSX32rr8, Convert_Reg1_2_Reg1_1, { MCK_movsbl, MCK_GR8, MCK_GR32 } },
{ X86::MOVSX32rm8, Convert_Reg1_2_Mem5_1, { MCK_movsbl, MCK_Mem, MCK_GR32 } },
{ X86::MOVSX64rr8, Convert_Reg1_2_Reg1_1, { MCK_movsbq, MCK_GR8, MCK_GR64 } },
{ X86::MOVSX64rm8, Convert_Reg1_2_Mem5_1, { MCK_movsbq, MCK_Mem, MCK_GR64 } },
+ { X86::MOVSX16rr8W, Convert_Reg1_2_Reg1_1, { MCK_movsbw, MCK_GR8, MCK_GR16 } },
+ { X86::MOVSX16rm8W, Convert_Reg1_2_Mem5_1, { MCK_movsbw, MCK_Mem, MCK_GR16 } },
{ X86::MOVSDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVPD2SDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVLSD2PDrr, Convert_Reg1_2_ImpReg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVLPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLSD2PDrr, Convert_Reg1_2_ImpReg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVSD2PDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVPD2SDmr, Convert_Mem5_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
+ { X86::MOVPD2SDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVSDmr, Convert_Mem5_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
- { X86::MOVSD2PDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
- { X86::MOVSDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVPD2SDmr, Convert_Mem5_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
{ X86::MOVZSD2PDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSD2PDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
{ X86::MOVSHDUPrr, Convert_Reg1_2_Reg1_1, { MCK_movshdup, MCK_FR32, MCK_FR32 } },
{ X86::MOVSHDUPrm, Convert_Reg1_2_Mem5_1, { MCK_movshdup, MCK_Mem, MCK_FR32 } },
{ X86::MOVSLDUPrr, Convert_Reg1_2_Reg1_1, { MCK_movsldup, MCK_FR32, MCK_FR32 } },
{ X86::MOVSLDUPrm, Convert_Reg1_2_Mem5_1, { MCK_movsldup, MCK_Mem, MCK_FR32 } },
{ X86::MOVSX64rr32, Convert_Reg1_2_Reg1_1, { MCK_movslq, MCK_GR32, MCK_GR64 } },
{ X86::MOVSX64rm32, Convert_Reg1_2_Mem5_1, { MCK_movslq, MCK_Mem, MCK_GR64 } },
+ { X86::MOVPS2SSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVSS2PSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVSSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVLPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVLSS2PSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVPS2SSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVSSmr, Convert_Mem5_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
+ { X86::MOVLPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVPS2SSmr, Convert_Mem5_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
+ { X86::MOVSSmr, Convert_Mem5_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
+ { X86::MOVZSS2PSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
{ X86::MOVSSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
{ X86::MOVSS2PSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
- { X86::MOVZSS2PSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
{ X86::MOVSX32rr16, Convert_Reg1_2_Reg1_1, { MCK_movswl, MCK_GR16, MCK_GR32 } },
{ X86::MOVSX32rm16, Convert_Reg1_2_Mem5_1, { MCK_movswl, MCK_Mem, MCK_GR32 } },
{ X86::MOVSX64rr16, Convert_Reg1_2_Reg1_1, { MCK_movswq, MCK_GR16, MCK_GR64 } },
@@ -5982,25 +7394,28 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MOVUPSrm, Convert_Reg1_2_Mem5_1, { MCK_movups, MCK_Mem, MCK_FR32 } },
{ X86::MOV16ao16, Convert_Imm1_2, { MCK_movw, MCK_AX, MCK_Imm } },
{ X86::MOV16rr, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_GR16, MCK_GR16 } },
+ { X86::MOV16rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_GR16, MCK_GR16 } },
{ X86::MOV16sr, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_GR16, MCK_SEGMENT_REG } },
{ X86::MOV16mr, Convert_Mem5_2_Reg1_1, { MCK_movw, MCK_GR16, MCK_Mem } },
- { X86::MOV64sr, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_GR64, MCK_SEGMENT_REG } },
{ X86::MOV16rs, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_GR16 } },
- { X86::MOV64rs, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_GR64 } },
{ X86::MOV16ms, Convert_Mem5_2_Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_Mem } },
- { X86::MOV64ms, Convert_Mem5_2_Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_Mem } },
{ X86::MOV16o16a, Convert_Imm1_1, { MCK_movw, MCK_Imm, MCK_AX } },
{ X86::MOV16ri, Convert_Reg1_2_Imm1_1, { MCK_movw, MCK_Imm, MCK_GR16 } },
{ X86::MOV16mi, Convert_Mem5_2_Imm1_1, { MCK_movw, MCK_Imm, MCK_Mem } },
{ X86::MOV16rm, Convert_Reg1_2_Mem5_1, { MCK_movw, MCK_Mem, MCK_GR16 } },
{ X86::MOV16sm, Convert_Reg1_2_Mem5_1, { MCK_movw, MCK_Mem, MCK_SEGMENT_REG } },
- { X86::MOV64sm, Convert_Reg1_2_Mem5_1, { MCK_movw, MCK_Mem, MCK_SEGMENT_REG } },
{ X86::MOVZX32_NOREXrr8, Convert_Reg1_2_Reg1_1, { MCK_movzbl, MCK_GR8, MCK_GR32_NOREX } },
{ X86::MOVZX32rr8, Convert_Reg1_2_Reg1_1, { MCK_movzbl, MCK_GR8, MCK_GR32 } },
{ X86::MOVZX32_NOREXrm8, Convert_Reg1_2_Mem5_1, { MCK_movzbl, MCK_Mem, MCK_GR32_NOREX } },
{ X86::MOVZX32rm8, Convert_Reg1_2_Mem5_1, { MCK_movzbl, MCK_Mem, MCK_GR32 } },
+ { X86::MOVZX64rr8_Q, Convert_Reg1_2_Reg1_1, { MCK_movzbq, MCK_GR8, MCK_GR64 } },
+ { X86::MOVZX64rm8_Q, Convert_Reg1_2_Mem5_1, { MCK_movzbq, MCK_Mem, MCK_GR64 } },
+ { X86::MOVZX16rr8W, Convert_Reg1_2_Reg1_1, { MCK_movzbw, MCK_GR8, MCK_GR16 } },
+ { X86::MOVZX16rm8W, Convert_Reg1_2_Mem5_1, { MCK_movzbw, MCK_Mem, MCK_GR16 } },
{ X86::MOVZX32rr16, Convert_Reg1_2_Reg1_1, { MCK_movzwl, MCK_GR16, MCK_GR32 } },
{ X86::MOVZX32rm16, Convert_Reg1_2_Mem5_1, { MCK_movzwl, MCK_Mem, MCK_GR32 } },
+ { X86::MOVZX64rr16_Q, Convert_Reg1_2_Reg1_1, { MCK_movzwq, MCK_GR16, MCK_GR64 } },
+ { X86::MOVZX64rm16_Q, Convert_Reg1_2_Mem5_1, { MCK_movzwq, MCK_Mem, MCK_GR64 } },
{ X86::MULPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulpd, MCK_FR32, MCK_FR32 } },
{ X86::MULPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulpd, MCK_Mem, MCK_FR32 } },
{ X86::MULPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulps, MCK_FR32, MCK_FR32 } },
@@ -6010,11 +7425,13 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MULSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulss, MCK_FR32, MCK_FR32 } },
{ X86::MULSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulss, MCK_Mem, MCK_FR32 } },
{ X86::OR8rr, Convert_Reg1_2_ImpReg1_1, { MCK_orb, MCK_GR8, MCK_GR8 } },
+ { X86::OR8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orb, MCK_GR8, MCK_GR8 } },
{ X86::OR8mr, Convert_Mem5_2_Reg1_1, { MCK_orb, MCK_GR8, MCK_Mem } },
{ X86::OR8i8, Convert_Imm1_1, { MCK_orb, MCK_Imm, MCK_AL } },
{ X86::OR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_orb, MCK_Imm, MCK_GR8 } },
{ X86::OR8mi, Convert_Mem5_2_Imm1_1, { MCK_orb, MCK_Imm, MCK_Mem } },
{ X86::OR8rm, Convert_Reg1_2_ImpMem5_1, { MCK_orb, MCK_Mem, MCK_GR8 } },
+ { X86::OR32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orl, MCK_GR32, MCK_GR32 } },
{ X86::OR32rr, Convert_Reg1_2_ImpReg1_1, { MCK_orl, MCK_GR32, MCK_GR32 } },
{ X86::OR32mr, Convert_Mem5_2_Reg1_1, { MCK_orl, MCK_GR32, MCK_Mem } },
{ X86::OR32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_orl, MCK_ImmSExt8, MCK_GR32 } },
@@ -6023,15 +7440,16 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::OR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_orl, MCK_Imm, MCK_GR32 } },
{ X86::OR32mi, Convert_Mem5_2_Imm1_1, { MCK_orl, MCK_Imm, MCK_Mem } },
{ X86::OR32rm, Convert_Reg1_2_ImpMem5_1, { MCK_orl, MCK_Mem, MCK_GR32 } },
- { X86::ORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
{ X86::FsORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
+ { X86::ORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
{ X86::FsORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_orpd, MCK_Mem, MCK_FR32 } },
{ X86::ORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_orpd, MCK_Mem, MCK_FR32 } },
- { X86::FsORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
{ X86::ORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
- { X86::FsORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
+ { X86::FsORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
{ X86::ORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
+ { X86::FsORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
{ X86::OR64rr, Convert_Reg1_2_ImpReg1_1, { MCK_orq, MCK_GR64, MCK_GR64 } },
+ { X86::OR64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orq, MCK_GR64, MCK_GR64 } },
{ X86::OR64mr, Convert_Mem5_2_Reg1_1, { MCK_orq, MCK_GR64, MCK_Mem } },
{ X86::OR64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_orq, MCK_ImmSExt8, MCK_GR64 } },
{ X86::OR64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_orq, MCK_ImmSExt8, MCK_Mem } },
@@ -6040,6 +7458,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::OR64mi32, Convert_Mem5_2_Imm1_1, { MCK_orq, MCK_Imm, MCK_Mem } },
{ X86::OR64rm, Convert_Reg1_2_ImpMem5_1, { MCK_orq, MCK_Mem, MCK_GR64 } },
{ X86::OR16rr, Convert_Reg1_2_ImpReg1_1, { MCK_orw, MCK_GR16, MCK_GR16 } },
+ { X86::OR16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orw, MCK_GR16, MCK_GR16 } },
{ X86::OR16mr, Convert_Mem5_2_Reg1_1, { MCK_orw, MCK_GR16, MCK_Mem } },
{ X86::OR16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_orw, MCK_ImmSExt8, MCK_GR16 } },
{ X86::OR16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_orw, MCK_ImmSExt8, MCK_Mem } },
@@ -6273,6 +7692,12 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::PMULUDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmuludq, MCK_FR32, MCK_FR32 } },
{ X86::MMX_PMULUDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmuludq, MCK_Mem, MCK_VR64 } },
{ X86::PMULUDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmuludq, MCK_Mem, MCK_FR32 } },
+ { X86::POPCNT32rr, Convert_Reg1_2_Reg1_1, { MCK_popcntl, MCK_GR32, MCK_GR32 } },
+ { X86::POPCNT32rm, Convert_Reg1_2_Mem5_1, { MCK_popcntl, MCK_Mem, MCK_GR32 } },
+ { X86::POPCNT64rr, Convert_Reg1_2_Reg1_1, { MCK_popcntq, MCK_GR64, MCK_GR64 } },
+ { X86::POPCNT64rm, Convert_Reg1_2_Mem5_1, { MCK_popcntq, MCK_Mem, MCK_GR64 } },
+ { X86::POPCNT16rr, Convert_Reg1_2_Reg1_1, { MCK_popcntw, MCK_GR16, MCK_GR16 } },
+ { X86::POPCNT16rm, Convert_Reg1_2_Mem5_1, { MCK_popcntw, MCK_Mem, MCK_GR16 } },
{ X86::MMX_PORrr, Convert_Reg1_2_ImpReg1_1, { MCK_por, MCK_VR64, MCK_VR64 } },
{ X86::PORrr, Convert_Reg1_2_ImpReg1_1, { MCK_por, MCK_FR32, MCK_FR32 } },
{ X86::MMX_PORrm, Convert_Reg1_2_ImpMem5_1, { MCK_por, MCK_Mem, MCK_VR64 } },
@@ -6517,6 +7942,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SAR16mCL, Convert_Mem5_2, { MCK_sarw, MCK_CL, MCK_Mem } },
{ X86::SAR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_sarw, MCK_Imm, MCK_GR16 } },
{ X86::SAR16mi, Convert_Mem5_2_Imm1_1, { MCK_sarw, MCK_Imm, MCK_Mem } },
+ { X86::SBB8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_sbbb, MCK_GR8, MCK_GR8 } },
{ X86::SBB8rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbb, MCK_GR8, MCK_GR8 } },
{ X86::SBB8mr, Convert_Mem5_2_Reg1_1, { MCK_sbbb, MCK_GR8, MCK_Mem } },
{ X86::SBB8i8, Convert_Imm1_1, { MCK_sbbb, MCK_Imm, MCK_AL } },
@@ -6524,6 +7950,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SBB8mi, Convert_Mem5_2_Imm1_1, { MCK_sbbb, MCK_Imm, MCK_Mem } },
{ X86::SBB8rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbb, MCK_Mem, MCK_GR8 } },
{ X86::SBB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbl, MCK_GR32, MCK_GR32 } },
+ { X86::SBB32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_sbbl, MCK_GR32, MCK_GR32 } },
{ X86::SBB32mr, Convert_Mem5_2_Reg1_1, { MCK_sbbl, MCK_GR32, MCK_Mem } },
{ X86::SBB32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_sbbl, MCK_ImmSExt8, MCK_GR32 } },
{ X86::SBB32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_sbbl, MCK_ImmSExt8, MCK_Mem } },
@@ -6532,6 +7959,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SBB32mi, Convert_Mem5_2_Imm1_1, { MCK_sbbl, MCK_Imm, MCK_Mem } },
{ X86::SBB32rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbl, MCK_Mem, MCK_GR32 } },
{ X86::SBB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbq, MCK_GR64, MCK_GR64 } },
+ { X86::SBB64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_sbbq, MCK_GR64, MCK_GR64 } },
{ X86::SBB64mr, Convert_Mem5_2_Reg1_1, { MCK_sbbq, MCK_GR64, MCK_Mem } },
{ X86::SBB64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_sbbq, MCK_ImmSExt8, MCK_GR64 } },
{ X86::SBB64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_sbbq, MCK_ImmSExt8, MCK_Mem } },
@@ -6539,6 +7967,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SBB64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_sbbq, MCK_Imm, MCK_GR64 } },
{ X86::SBB64mi32, Convert_Mem5_2_Imm1_1, { MCK_sbbq, MCK_Imm, MCK_Mem } },
{ X86::SBB64rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbq, MCK_Mem, MCK_GR64 } },
+ { X86::SBB16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_sbbw, MCK_GR16, MCK_GR16 } },
{ X86::SBB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbw, MCK_GR16, MCK_GR16 } },
{ X86::SBB16mr, Convert_Mem5_2_Reg1_1, { MCK_sbbw, MCK_GR16, MCK_Mem } },
{ X86::SBB16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_sbbw, MCK_ImmSExt8, MCK_GR16 } },
@@ -6588,12 +8017,14 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SQRTSSr, Convert_Reg1_2_Reg1_1, { MCK_sqrtss, MCK_FR32, MCK_FR32 } },
{ X86::SQRTSSm, Convert_Reg1_2_Mem5_1, { MCK_sqrtss, MCK_Mem, MCK_FR32 } },
{ X86::SUB8rr, Convert_Reg1_2_ImpReg1_1, { MCK_subb, MCK_GR8, MCK_GR8 } },
+ { X86::SUB8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_subb, MCK_GR8, MCK_GR8 } },
{ X86::SUB8mr, Convert_Mem5_2_Reg1_1, { MCK_subb, MCK_GR8, MCK_Mem } },
{ X86::SUB8i8, Convert_Imm1_1, { MCK_subb, MCK_Imm, MCK_AL } },
{ X86::SUB8ri, Convert_Reg1_2_ImpImm1_1, { MCK_subb, MCK_Imm, MCK_GR8 } },
{ X86::SUB8mi, Convert_Mem5_2_Imm1_1, { MCK_subb, MCK_Imm, MCK_Mem } },
{ X86::SUB8rm, Convert_Reg1_2_ImpMem5_1, { MCK_subb, MCK_Mem, MCK_GR8 } },
{ X86::SUB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_subl, MCK_GR32, MCK_GR32 } },
+ { X86::SUB32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_subl, MCK_GR32, MCK_GR32 } },
{ X86::SUB32mr, Convert_Mem5_2_Reg1_1, { MCK_subl, MCK_GR32, MCK_Mem } },
{ X86::SUB32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_subl, MCK_ImmSExt8, MCK_GR32 } },
{ X86::SUB32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_subl, MCK_ImmSExt8, MCK_Mem } },
@@ -6605,6 +8036,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SUBPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_subpd, MCK_Mem, MCK_FR32 } },
{ X86::SUBPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_subps, MCK_FR32, MCK_FR32 } },
{ X86::SUBPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_subps, MCK_Mem, MCK_FR32 } },
+ { X86::SUB64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_subq, MCK_GR64, MCK_GR64 } },
{ X86::SUB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_subq, MCK_GR64, MCK_GR64 } },
{ X86::SUB64mr, Convert_Mem5_2_Reg1_1, { MCK_subq, MCK_GR64, MCK_Mem } },
{ X86::SUB64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_subq, MCK_ImmSExt8, MCK_GR64 } },
@@ -6618,6 +8050,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SUBSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_subss, MCK_FR32, MCK_FR32 } },
{ X86::SUBSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_subss, MCK_Mem, MCK_FR32 } },
{ X86::SUB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_subw, MCK_GR16, MCK_GR16 } },
+ { X86::SUB16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_subw, MCK_GR16, MCK_GR16 } },
{ X86::SUB16mr, Convert_Mem5_2_Reg1_1, { MCK_subw, MCK_GR16, MCK_Mem } },
{ X86::SUB16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_subw, MCK_ImmSExt8, MCK_GR16 } },
{ X86::SUB16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_subw, MCK_ImmSExt8, MCK_Mem } },
@@ -6657,16 +8090,41 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::UNPCKLPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_unpcklpd, MCK_Mem, MCK_FR32 } },
{ X86::UNPCKLPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_unpcklps, MCK_FR32, MCK_FR32 } },
{ X86::UNPCKLPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_unpcklps, MCK_Mem, MCK_FR32 } },
- { X86::XCHG64rm, Convert_ImpMem5_2_Reg1_1, { MCK_xchg, MCK_GR64, MCK_Mem } },
- { X86::XCHG8rm, Convert_ImpMem5_2_Reg1_1, { MCK_xchgb, MCK_GR8, MCK_Mem } },
- { X86::XCHG32rm, Convert_ImpMem5_2_Reg1_1, { MCK_xchgl, MCK_GR32, MCK_Mem } },
- { X86::XCHG16rm, Convert_ImpMem5_2_Reg1_1, { MCK_xchgw, MCK_GR16, MCK_Mem } },
+ { X86::VMREAD32rr, Convert_Reg1_2_Reg1_1, { MCK_vmreadl, MCK_GR32, MCK_GR32 } },
+ { X86::VMREAD32rm, Convert_Mem5_2_Reg1_1, { MCK_vmreadl, MCK_GR32, MCK_Mem } },
+ { X86::VMREAD64rr, Convert_Reg1_2_Reg1_1, { MCK_vmreadq, MCK_GR64, MCK_GR64 } },
+ { X86::VMREAD64rm, Convert_Mem5_2_Reg1_1, { MCK_vmreadq, MCK_GR64, MCK_Mem } },
+ { X86::VMWRITE32rr, Convert_Reg1_2_Reg1_1, { MCK_vmwritel, MCK_GR32, MCK_GR32 } },
+ { X86::VMWRITE32rm, Convert_Reg1_2_Mem5_1, { MCK_vmwritel, MCK_Mem, MCK_GR32 } },
+ { X86::VMWRITE64rr, Convert_Reg1_2_Reg1_1, { MCK_vmwriteq, MCK_GR64, MCK_GR64 } },
+ { X86::VMWRITE64rm, Convert_Reg1_2_Mem5_1, { MCK_vmwriteq, MCK_Mem, MCK_GR64 } },
+ { X86::XADD8rr, Convert_Reg1_2_Reg1_1, { MCK_xaddb, MCK_GR8, MCK_GR8 } },
+ { X86::XADD8rm, Convert_Mem5_2_Reg1_1, { MCK_xaddb, MCK_GR8, MCK_Mem } },
+ { X86::XADD32rr, Convert_Reg1_2_Reg1_1, { MCK_xaddl, MCK_GR32, MCK_GR32 } },
+ { X86::XADD32rm, Convert_Mem5_2_Reg1_1, { MCK_xaddl, MCK_GR32, MCK_Mem } },
+ { X86::XADD64rr, Convert_Reg1_2_Reg1_1, { MCK_xaddq, MCK_GR64, MCK_GR64 } },
+ { X86::XADD64rm, Convert_Mem5_2_Reg1_1, { MCK_xaddq, MCK_GR64, MCK_Mem } },
+ { X86::XADD16rr, Convert_Reg1_2_Reg1_1, { MCK_xaddw, MCK_GR16, MCK_GR16 } },
+ { X86::XADD16rm, Convert_Mem5_2_Reg1_1, { MCK_xaddw, MCK_GR16, MCK_Mem } },
+ { X86::XCHG8rr, Convert_ImpReg1_1_Reg1_2, { MCK_xchgb, MCK_GR8, MCK_GR8 } },
+ { X86::XCHG8rm, Convert_ImpReg1_1_Mem5_2, { MCK_xchgb, MCK_GR8, MCK_Mem } },
+ { X86::XCHG32ar, Convert_Reg1_1, { MCK_xchgl, MCK_GR32, MCK_EAX } },
+ { X86::XCHG32rr, Convert_ImpReg1_1_Reg1_2, { MCK_xchgl, MCK_GR32, MCK_GR32 } },
+ { X86::XCHG32rm, Convert_ImpReg1_1_Mem5_2, { MCK_xchgl, MCK_GR32, MCK_Mem } },
+ { X86::XCHG64ar, Convert_Reg1_1, { MCK_xchgq, MCK_GR64, MCK_RAX } },
+ { X86::XCHG64rr, Convert_ImpReg1_1_Reg1_2, { MCK_xchgq, MCK_GR64, MCK_GR64 } },
+ { X86::XCHG64rm, Convert_ImpReg1_1_Mem5_2, { MCK_xchgq, MCK_GR64, MCK_Mem } },
+ { X86::XCHG16ar, Convert_Reg1_1, { MCK_xchgw, MCK_GR16, MCK_AX } },
+ { X86::XCHG16rr, Convert_ImpReg1_1_Reg1_2, { MCK_xchgw, MCK_GR16, MCK_GR16 } },
+ { X86::XCHG16rm, Convert_ImpReg1_1_Mem5_2, { MCK_xchgw, MCK_GR16, MCK_Mem } },
{ X86::XOR8rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorb, MCK_GR8, MCK_GR8 } },
+ { X86::XOR8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorb, MCK_GR8, MCK_GR8 } },
{ X86::XOR8mr, Convert_Mem5_2_Reg1_1, { MCK_xorb, MCK_GR8, MCK_Mem } },
{ X86::XOR8i8, Convert_Imm1_1, { MCK_xorb, MCK_Imm, MCK_AL } },
{ X86::XOR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_xorb, MCK_Imm, MCK_GR8 } },
{ X86::XOR8mi, Convert_Mem5_2_Imm1_1, { MCK_xorb, MCK_Imm, MCK_Mem } },
{ X86::XOR8rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorb, MCK_Mem, MCK_GR8 } },
+ { X86::XOR32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorl, MCK_GR32, MCK_GR32 } },
{ X86::XOR32rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorl, MCK_GR32, MCK_GR32 } },
{ X86::XOR32mr, Convert_Mem5_2_Reg1_1, { MCK_xorl, MCK_GR32, MCK_Mem } },
{ X86::XOR32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorl, MCK_ImmSExt8, MCK_GR32 } },
@@ -6684,6 +8142,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::FsXORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorps, MCK_Mem, MCK_FR32 } },
{ X86::XORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorps, MCK_Mem, MCK_FR32 } },
{ X86::XOR64rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorq, MCK_GR64, MCK_GR64 } },
+ { X86::XOR64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorq, MCK_GR64, MCK_GR64 } },
{ X86::XOR64mr, Convert_Mem5_2_Reg1_1, { MCK_xorq, MCK_GR64, MCK_Mem } },
{ X86::XOR64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorq, MCK_ImmSExt8, MCK_GR64 } },
{ X86::XOR64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_xorq, MCK_ImmSExt8, MCK_Mem } },
@@ -6692,6 +8151,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::XOR64mi32, Convert_Mem5_2_Imm1_1, { MCK_xorq, MCK_Imm, MCK_Mem } },
{ X86::XOR64rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorq, MCK_Mem, MCK_GR64 } },
{ X86::XOR16rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorw, MCK_GR16, MCK_GR16 } },
+ { X86::XOR16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorw, MCK_GR16, MCK_GR16 } },
{ X86::XOR16mr, Convert_Mem5_2_Reg1_1, { MCK_xorw, MCK_GR16, MCK_Mem } },
{ X86::XOR16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorw, MCK_ImmSExt8, MCK_GR16 } },
{ X86::XOR16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_xorw, MCK_ImmSExt8, MCK_Mem } },
@@ -6737,32 +8197,32 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::PBLENDVBrm0, Convert_Reg1_3_ImpMem5_2, { MCK_pblendvb, MCK_XMM0, MCK_Mem, MCK_FR32 } },
{ X86::PBLENDWrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pblendw, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
{ X86::PBLENDWrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pblendw, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRIZrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPESTRIrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPESTRIArr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIZrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPESTRISrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPESTRIOrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPESTRICrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIArr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIOrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRICrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPESTRIZrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPESTRIrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRIOrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPESTRIArm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRICrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPESTRM128rr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestrm, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPESTRM128rm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestrm, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRISrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPISTRIOrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPISTRICrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPISTRIArr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRICrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRIOrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRISrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPISTRIZrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPISTRIrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPISTRIZrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIOrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPISTRIrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRIArm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPISTRICrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRIOrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIArm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPISTRM128rr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistrm, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPISTRM128rm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistrm, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PEXTRBrr, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrb, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
@@ -6849,7 +8309,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
Classes[i] = InvalidMatchClass;
// Search the table.
- for (const MatchEntry *it = MatchTable, *ie = MatchTable + 1775; it != ie; ++it) {
+ for (const MatchEntry *it = MatchTable, *ie = MatchTable + 2041; it != ie; ++it) {
if (!IsSubclass(Classes[0], it->Classes[0]))
continue;
if (!IsSubclass(Classes[1], it->Classes[1]))
diff --git a/libclamav/c++/X86GenAsmWriter.inc b/libclamav/c++/X86GenAsmWriter.inc
index 4dad678..24fdc1d 100644
--- a/libclamav/c++/X86GenAsmWriter.inc
+++ b/libclamav/c++/X86GenAsmWriter.inc
@@ -29,82 +29,86 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
135266310U, // ADC16mi
135266310U, // ADC16mi8
135266310U, // ADC16mr
- 203423750U, // ADC16ri
- 203423750U, // ADC16ri8
- 270532614U, // ADC16rm
- 203423750U, // ADC16rr
+ 203456518U, // ADC16ri
+ 203456518U, // ADC16ri8
+ 270565382U, // ADC16rm
+ 203456518U, // ADC16rr
+ 203456518U, // ADC16rr_REV
70254604U, // ADC32i32
135331852U, // ADC32mi
135331852U, // ADC32mi8
135331852U, // ADC32mr
- 203423756U, // ADC32ri
- 203423756U, // ADC32ri8
- 337641484U, // ADC32rm
- 203423756U, // ADC32rr
+ 203456524U, // ADC32ri
+ 203456524U, // ADC32ri8
+ 337674252U, // ADC32rm
+ 203456524U, // ADC32rr
+ 203456524U, // ADC32rr_REV
71303186U, // ADC64i32
- 135397394U, // ADC64mi32
- 135397394U, // ADC64mi8
- 135397394U, // ADC64mr
- 203423762U, // ADC64ri32
- 203423762U, // ADC64ri8
- 404750354U, // ADC64rm
- 203423762U, // ADC64rr
+ 135364626U, // ADC64mi32
+ 135364626U, // ADC64mi8
+ 135364626U, // ADC64mr
+ 203456530U, // ADC64ri32
+ 203456530U, // ADC64ri8
+ 404783122U, // ADC64rm
+ 203456530U, // ADC64rr
+ 203456530U, // ADC64rr_REV
72351768U, // ADC8i8
- 135462936U, // ADC8mi
- 135462936U, // ADC8mr
- 203423768U, // ADC8ri
- 471859224U, // ADC8rm
- 203423768U, // ADC8rr
+ 135397400U, // ADC8mi
+ 135397400U, // ADC8mr
+ 203456536U, // ADC8ri
+ 471891992U, // ADC8rm
+ 203456536U, // ADC8rr
+ 203456536U, // ADC8rr_REV
67108894U, // ADD16i16
135266334U, // ADD16mi
135266334U, // ADD16mi8
135266334U, // ADD16mr
- 203423774U, // ADD16mrmrr
- 203423774U, // ADD16ri
- 203423774U, // ADD16ri8
- 270532638U, // ADD16rm
- 203423774U, // ADD16rr
+ 203456542U, // ADD16mrmrr
+ 203456542U, // ADD16ri
+ 203456542U, // ADD16ri8
+ 270565406U, // ADD16rm
+ 203456542U, // ADD16rr
70254628U, // ADD32i32
135331876U, // ADD32mi
135331876U, // ADD32mi8
135331876U, // ADD32mr
- 203423780U, // ADD32mrmrr
- 203423780U, // ADD32ri
- 203423780U, // ADD32ri8
- 337641508U, // ADD32rm
- 203423780U, // ADD32rr
+ 203456548U, // ADD32mrmrr
+ 203456548U, // ADD32ri
+ 203456548U, // ADD32ri8
+ 337674276U, // ADD32rm
+ 203456548U, // ADD32rr
71303210U, // ADD64i32
- 135397418U, // ADD64mi32
- 135397418U, // ADD64mi8
- 135397418U, // ADD64mr
- 203423780U, // ADD64mrmrr
- 203423786U, // ADD64ri32
- 203423786U, // ADD64ri8
- 404750378U, // ADD64rm
- 203423786U, // ADD64rr
+ 135364650U, // ADD64mi32
+ 135364650U, // ADD64mi8
+ 135364650U, // ADD64mr
+ 203456548U, // ADD64mrmrr
+ 203456554U, // ADD64ri32
+ 203456554U, // ADD64ri8
+ 404783146U, // ADD64rm
+ 203456554U, // ADD64rr
72351792U, // ADD8i8
- 135462960U, // ADD8mi
- 135462960U, // ADD8mr
- 203423792U, // ADD8mrmrr
- 203423792U, // ADD8ri
- 471859248U, // ADD8rm
- 203423792U, // ADD8rr
+ 135397424U, // ADD8mi
+ 135397424U, // ADD8mr
+ 203456560U, // ADD8mrmrr
+ 203456560U, // ADD8ri
+ 471892016U, // ADD8rm
+ 203456560U, // ADD8rr
536870966U, // ADDPDrm
- 203423798U, // ADDPDrr
+ 203456566U, // ADDPDrr
536870973U, // ADDPSrm
- 203423805U, // ADDPSrr
+ 203456573U, // ADDPSrr
603979844U, // ADDSDrm
603979844U, // ADDSDrm_Int
- 203423812U, // ADDSDrr
- 203423812U, // ADDSDrr_Int
+ 203456580U, // ADDSDrr
+ 203456580U, // ADDSDrr_Int
671088715U, // ADDSSrm
671088715U, // ADDSSrm_Int
- 203423819U, // ADDSSrr
- 203423819U, // ADDSSrr_Int
+ 203456587U, // ADDSSrr
+ 203456587U, // ADDSSrr_Int
536870994U, // ADDSUBPDrm
- 203423826U, // ADDSUBPDrr
+ 203456594U, // ADDSUBPDrr
536871004U, // ADDSUBPSrm
- 203423836U, // ADDSUBPSrr
+ 203456604U, // ADDSUBPSrr
738197606U, // ADD_F32m
805306477U, // ADD_F64m
872415348U, // ADD_FI16m
@@ -134,40 +138,44 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
135266497U, // AND16mi
135266497U, // AND16mi8
135266497U, // AND16mr
- 203423937U, // AND16ri
- 203423937U, // AND16ri8
- 270532801U, // AND16rm
- 203423937U, // AND16rr
+ 203456705U, // AND16ri
+ 203456705U, // AND16ri8
+ 270565569U, // AND16rm
+ 203456705U, // AND16rr
+ 203456705U, // AND16rr_REV
70254791U, // AND32i32
135332039U, // AND32mi
135332039U, // AND32mi8
135332039U, // AND32mr
- 203423943U, // AND32ri
- 203423943U, // AND32ri8
- 337641671U, // AND32rm
- 203423943U, // AND32rr
+ 203456711U, // AND32ri
+ 203456711U, // AND32ri8
+ 337674439U, // AND32rm
+ 203456711U, // AND32rr
+ 203456711U, // AND32rr_REV
71303373U, // AND64i32
- 135397581U, // AND64mi32
- 135397581U, // AND64mi8
- 135397581U, // AND64mr
- 203423949U, // AND64ri32
- 203423949U, // AND64ri8
- 404750541U, // AND64rm
- 203423949U, // AND64rr
+ 135364813U, // AND64mi32
+ 135364813U, // AND64mi8
+ 135364813U, // AND64mr
+ 203456717U, // AND64ri32
+ 203456717U, // AND64ri8
+ 404783309U, // AND64rm
+ 203456717U, // AND64rr
+ 203456717U, // AND64rr_REV
72351955U, // AND8i8
- 135463123U, // AND8mi
- 135463123U, // AND8mr
- 203423955U, // AND8ri
- 471859411U, // AND8rm
- 203423955U, // AND8rr
+ 135397587U, // AND8mi
+ 135397587U, // AND8mr
+ 203456723U, // AND8ri
+ 471892179U, // AND8rm
+ 203456723U, // AND8rr
+ 203456723U, // AND8rr_REV
536871129U, // ANDNPDrm
- 203423961U, // ANDNPDrr
+ 203456729U, // ANDNPDrr
536871137U, // ANDNPSrm
- 203423969U, // ANDNPSrr
+ 203456737U, // ANDNPSrr
536871145U, // ANDPDrm
- 203423977U, // ANDPDrr
+ 203456745U, // ANDPDrr
536871152U, // ANDPSrm
- 203423984U, // ANDPSrr
+ 203456752U, // ANDPSrr
247U, // ATOMADD6432
268U, // ATOMAND16
287U, // ATOMAND32
@@ -208,302 +216,375 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
1013973930U, // BLENDPSrmi
1073742762U, // BLENDPSrri
1140851635U, // BLENDVPDrm0
- 203424691U, // BLENDVPDrr0
+ 203457459U, // BLENDVPDrr0
1140851652U, // BLENDVPSrm0
- 203424708U, // BLENDVPSrr0
+ 203457476U, // BLENDVPSrr0
1207960533U, // BSF16rm
- 1281360853U, // BSF16rr
+ 1277199317U, // BSF16rr
1342178267U, // BSF32rm
- 1281360859U, // BSF32rr
+ 1277199323U, // BSF32rr
1409287137U, // BSF64rm
- 1281360865U, // BSF64rr
+ 1277199329U, // BSF64rr
1207960551U, // BSR16rm
- 1281360871U, // BSR16rr
+ 1277199335U, // BSR16rr
1342178285U, // BSR32rm
- 1281360877U, // BSR32rr
+ 1277199341U, // BSR32rr
1409287155U, // BSR64rm
- 1281360883U, // BSR64rr
+ 1277199347U, // BSR64rr
73401337U, // BSWAP32r
73401345U, // BSWAP64r
135267337U, // BT16mi8
- 1281360905U, // BT16ri8
- 1281360905U, // BT16rr
+ 135267337U, // BT16mr
+ 1277199369U, // BT16ri8
+ 1277199369U, // BT16rr
135332878U, // BT32mi8
- 1281360910U, // BT32ri8
- 1281360910U, // BT32rr
- 135398419U, // BT64mi8
- 1281360915U, // BT64ri8
- 1281360915U, // BT64rr
- 945816600U, // CALL32m
- 73401368U, // CALL32r
- 1476396056U, // CALL64m
- 1549796383U, // CALL64pcrel32
- 73401368U, // CALL64r
- 1549796383U, // CALLpcrel32
- 1061U, // CBW
- 1066U, // CDQ
- 1071U, // CDQE
- 1076U, // CHS_F
+ 135332878U, // BT32mr
+ 1277199374U, // BT32ri8
+ 1277199374U, // BT32rr
+ 135365651U, // BT64mi8
+ 135365651U, // BT64mr
+ 1277199379U, // BT64ri8
+ 1277199379U, // BT64rr
+ 135267352U, // BTC16mi8
+ 135267352U, // BTC16mr
+ 1277199384U, // BTC16ri8
+ 1277199384U, // BTC16rr
+ 135332894U, // BTC32mi8
+ 135332894U, // BTC32mr
+ 1277199390U, // BTC32ri8
+ 1277199390U, // BTC32rr
+ 135365668U, // BTC64mi8
+ 135365668U, // BTC64mr
+ 1277199396U, // BTC64ri8
+ 1277199396U, // BTC64rr
+ 135267370U, // BTR16mi8
+ 135267370U, // BTR16mr
+ 1277199402U, // BTR16ri8
+ 1277199402U, // BTR16rr
+ 135332912U, // BTR32mi8
+ 135332912U, // BTR32mr
+ 1277199408U, // BTR32ri8
+ 1277199408U, // BTR32rr
+ 135365686U, // BTR64mi8
+ 135365686U, // BTR64mr
+ 1277199414U, // BTR64ri8
+ 1277199414U, // BTR64rr
+ 135267388U, // BTS16mi8
+ 135267388U, // BTS16mr
+ 1277199420U, // BTS16ri8
+ 1277199420U, // BTS16rr
+ 135332930U, // BTS32mi8
+ 135332930U, // BTS32mr
+ 1277199426U, // BTS32ri8
+ 1277199426U, // BTS32rr
+ 135365704U, // BTS64mi8
+ 135365704U, // BTS64mr
+ 1277199432U, // BTS64ri8
+ 1277199432U, // BTS64rr
+ 945816654U, // CALL32m
+ 73401422U, // CALL32r
+ 1476396117U, // CALL64m
+ 1549796445U, // CALL64pcrel32
+ 73401429U, // CALL64r
+ 1549796452U, // CALLpcrel32
+ 1130U, // CBW
+ 1135U, // CDQ
+ 1140U, // CDQE
+ 1145U, // CHS_F
0U, // CHS_Fp32
0U, // CHS_Fp64
0U, // CHS_Fp80
- 1610613817U, // CLFLUSH
- 270533698U, // CMOVA16rm
- 203424834U, // CMOVA16rr
- 337642562U, // CMOVA32rm
- 203424834U, // CMOVA32rr
- 404751426U, // CMOVA64rm
- 203424834U, // CMOVA64rr
- 270533705U, // CMOVAE16rm
- 203424841U, // CMOVAE16rr
- 337642569U, // CMOVAE32rm
- 203424841U, // CMOVAE32rr
- 404751433U, // CMOVAE64rm
- 203424841U, // CMOVAE64rr
- 270533713U, // CMOVB16rm
- 203424849U, // CMOVB16rr
- 337642577U, // CMOVB32rm
- 203424849U, // CMOVB32rr
- 404751441U, // CMOVB64rm
- 203424849U, // CMOVB64rr
- 270533720U, // CMOVBE16rm
- 203424856U, // CMOVBE16rr
- 337642584U, // CMOVBE32rm
- 203424856U, // CMOVBE32rr
- 404751448U, // CMOVBE64rm
- 203424856U, // CMOVBE64rr
- 75498592U, // CMOVBE_F
+ 1150U, // CLC
+ 1154U, // CLD
+ 1610613894U, // CLFLUSH
+ 1167U, // CLI
+ 1171U, // CLTS
+ 1176U, // CMC
+ 270566556U, // CMOVA16rm
+ 203457692U, // CMOVA16rr
+ 337675428U, // CMOVA32rm
+ 203457700U, // CMOVA32rr
+ 404784300U, // CMOVA64rm
+ 203457708U, // CMOVA64rr
+ 270566580U, // CMOVAE16rm
+ 203457716U, // CMOVAE16rr
+ 337675453U, // CMOVAE32rm
+ 203457725U, // CMOVAE32rr
+ 404784326U, // CMOVAE64rm
+ 203457734U, // CMOVAE64rr
+ 270566607U, // CMOVB16rm
+ 203457743U, // CMOVB16rr
+ 337675479U, // CMOVB32rm
+ 203457751U, // CMOVB32rr
+ 404784351U, // CMOVB64rm
+ 203457759U, // CMOVB64rr
+ 270566631U, // CMOVBE16rm
+ 203457767U, // CMOVBE16rr
+ 337675504U, // CMOVBE32rm
+ 203457776U, // CMOVBE32rr
+ 404784377U, // CMOVBE64rm
+ 203457785U, // CMOVBE64rr
+ 75498754U, // CMOVBE_F
0U, // CMOVBE_Fp32
0U, // CMOVBE_Fp64
0U, // CMOVBE_Fp80
- 75498601U, // CMOVB_F
+ 75498763U, // CMOVB_F
0U, // CMOVB_Fp32
0U, // CMOVB_Fp64
0U, // CMOVB_Fp80
- 270533745U, // CMOVE16rm
- 203424881U, // CMOVE16rr
- 337642609U, // CMOVE32rm
- 203424881U, // CMOVE32rr
- 404751473U, // CMOVE64rm
- 203424881U, // CMOVE64rr
- 75498616U, // CMOVE_F
+ 270566675U, // CMOVE16rm
+ 203457811U, // CMOVE16rr
+ 337675547U, // CMOVE32rm
+ 203457819U, // CMOVE32rr
+ 404784419U, // CMOVE64rm
+ 203457827U, // CMOVE64rr
+ 75498795U, // CMOVE_F
0U, // CMOVE_Fp32
0U, // CMOVE_Fp64
0U, // CMOVE_Fp80
- 270533760U, // CMOVG16rm
- 203424896U, // CMOVG16rr
- 337642624U, // CMOVG32rm
- 203424896U, // CMOVG32rr
- 404751488U, // CMOVG64rm
- 203424896U, // CMOVG64rr
- 270533767U, // CMOVGE16rm
- 203424903U, // CMOVGE16rr
- 337642631U, // CMOVGE32rm
- 203424903U, // CMOVGE32rr
- 404751495U, // CMOVGE64rm
- 203424903U, // CMOVGE64rr
- 270533775U, // CMOVL16rm
- 203424911U, // CMOVL16rr
- 337642639U, // CMOVL32rm
- 203424911U, // CMOVL32rr
- 404751503U, // CMOVL64rm
- 203424911U, // CMOVL64rr
- 270533782U, // CMOVLE16rm
- 203424918U, // CMOVLE16rr
- 337642646U, // CMOVLE32rm
- 203424918U, // CMOVLE32rr
- 404751510U, // CMOVLE64rm
- 203424918U, // CMOVLE64rr
- 75498654U, // CMOVNBE_F
+ 270566707U, // CMOVG16rm
+ 203457843U, // CMOVG16rr
+ 337675579U, // CMOVG32rm
+ 203457851U, // CMOVG32rr
+ 404784451U, // CMOVG64rm
+ 203457859U, // CMOVG64rr
+ 270566731U, // CMOVGE16rm
+ 203457867U, // CMOVGE16rr
+ 337675604U, // CMOVGE32rm
+ 203457876U, // CMOVGE32rr
+ 404784477U, // CMOVGE64rm
+ 203457885U, // CMOVGE64rr
+ 270566758U, // CMOVL16rm
+ 203457894U, // CMOVL16rr
+ 337675630U, // CMOVL32rm
+ 203457902U, // CMOVL32rr
+ 404784502U, // CMOVL64rm
+ 203457910U, // CMOVL64rr
+ 270566782U, // CMOVLE16rm
+ 203457918U, // CMOVLE16rr
+ 337675655U, // CMOVLE32rm
+ 203457927U, // CMOVLE32rr
+ 404784528U, // CMOVLE64rm
+ 203457936U, // CMOVLE64rr
+ 75498905U, // CMOVNBE_F
0U, // CMOVNBE_Fp32
0U, // CMOVNBE_Fp64
0U, // CMOVNBE_Fp80
- 75498664U, // CMOVNB_F
+ 75498915U, // CMOVNB_F
0U, // CMOVNB_Fp32
0U, // CMOVNB_Fp64
0U, // CMOVNB_Fp80
- 270533809U, // CMOVNE16rm
- 203424945U, // CMOVNE16rr
- 337642673U, // CMOVNE32rm
- 203424945U, // CMOVNE32rr
- 404751537U, // CMOVNE64rm
- 203424945U, // CMOVNE64rr
- 75498681U, // CMOVNE_F
+ 270566828U, // CMOVNE16rm
+ 203457964U, // CMOVNE16rr
+ 337675701U, // CMOVNE32rm
+ 203457973U, // CMOVNE32rr
+ 404784574U, // CMOVNE64rm
+ 203457982U, // CMOVNE64rr
+ 75498951U, // CMOVNE_F
0U, // CMOVNE_Fp32
0U, // CMOVNE_Fp64
0U, // CMOVNE_Fp80
- 270533826U, // CMOVNO16rm
- 203424962U, // CMOVNO16rr
- 337642690U, // CMOVNO32rm
- 203424962U, // CMOVNO32rr
- 404751554U, // CMOVNO64rm
- 203424962U, // CMOVNO64rr
- 270533834U, // CMOVNP16rm
- 203424970U, // CMOVNP16rr
- 337642698U, // CMOVNP32rm
- 203424970U, // CMOVNP32rr
- 404751562U, // CMOVNP64rm
- 203424970U, // CMOVNP64rr
- 75498706U, // CMOVNP_F
+ 270566864U, // CMOVNO16rm
+ 203458000U, // CMOVNO16rr
+ 337675737U, // CMOVNO32rm
+ 203458009U, // CMOVNO32rr
+ 404784610U, // CMOVNO64rm
+ 203458018U, // CMOVNO64rr
+ 270566891U, // CMOVNP16rm
+ 203458027U, // CMOVNP16rr
+ 337675764U, // CMOVNP32rm
+ 203458036U, // CMOVNP32rr
+ 404784637U, // CMOVNP64rm
+ 203458045U, // CMOVNP64rr
+ 75499014U, // CMOVNP_F
0U, // CMOVNP_Fp32
0U, // CMOVNP_Fp64
0U, // CMOVNP_Fp80
- 270533851U, // CMOVNS16rm
- 203424987U, // CMOVNS16rr
- 337642715U, // CMOVNS32rm
- 203424987U, // CMOVNS32rr
- 404751579U, // CMOVNS64rm
- 203424987U, // CMOVNS64rr
- 270533859U, // CMOVO16rm
- 203424995U, // CMOVO16rr
- 337642723U, // CMOVO32rm
- 203424995U, // CMOVO32rr
- 404751587U, // CMOVO64rm
- 203424995U, // CMOVO64rr
- 270533866U, // CMOVP16rm
- 203425002U, // CMOVP16rr
- 337642730U, // CMOVP32rm
- 203425002U, // CMOVP32rr
- 404751594U, // CMOVP64rm
- 203425002U, // CMOVP64rr
- 75498737U, // CMOVP_F
+ 270566927U, // CMOVNS16rm
+ 203458063U, // CMOVNS16rr
+ 337675800U, // CMOVNS32rm
+ 203458072U, // CMOVNS32rr
+ 404784673U, // CMOVNS64rm
+ 203458081U, // CMOVNS64rr
+ 270566954U, // CMOVO16rm
+ 203458090U, // CMOVO16rr
+ 337675826U, // CMOVO32rm
+ 203458098U, // CMOVO32rr
+ 404784698U, // CMOVO64rm
+ 203458106U, // CMOVO64rr
+ 270566978U, // CMOVP16rm
+ 203458114U, // CMOVP16rr
+ 337675850U, // CMOVP32rm
+ 203458122U, // CMOVP32rr
+ 404784722U, // CMOVP64rm
+ 203458130U, // CMOVP64rr
+ 75499098U, // CMOVP_F
0U, // CMOVP_Fp32
0U, // CMOVP_Fp64
0U, // CMOVP_Fp80
- 270533882U, // CMOVS16rm
- 203425018U, // CMOVS16rr
- 337642746U, // CMOVS32rm
- 203425018U, // CMOVS32rr
- 404751610U, // CMOVS64rm
- 203425018U, // CMOVS64rr
- 1281U, // CMOV_FR32
- 1300U, // CMOV_FR64
- 1319U, // CMOV_GR8
- 1337U, // CMOV_V1I64
- 1357U, // CMOV_V2F64
- 1377U, // CMOV_V2I64
- 1397U, // CMOV_V4F32
- 67110281U, // CMP16i16
- 135267721U, // CMP16mi
- 135267721U, // CMP16mi8
- 135267721U, // CMP16mr
- 1281361289U, // CMP16mrmrr
- 1281361289U, // CMP16ri
- 1281361289U, // CMP16ri8
- 1207960969U, // CMP16rm
- 1281361289U, // CMP16rr
- 70256015U, // CMP32i32
- 135333263U, // CMP32mi
- 135333263U, // CMP32mi8
- 135333263U, // CMP32mr
- 1281361295U, // CMP32mrmrr
- 1281361295U, // CMP32ri
- 1281361295U, // CMP32ri8
- 1342178703U, // CMP32rm
- 1281361295U, // CMP32rr
- 71304597U, // CMP64i32
- 135398805U, // CMP64mi32
- 135398805U, // CMP64mi8
- 135398805U, // CMP64mr
- 1281361301U, // CMP64mrmrr
- 1281361301U, // CMP64ri32
- 1281361301U, // CMP64ri8
- 1409287573U, // CMP64rm
- 1281361301U, // CMP64rr
- 72353179U, // CMP8i8
- 135464347U, // CMP8mi
- 135464347U, // CMP8mr
- 1281361307U, // CMP8mrmrr
- 1281361307U, // CMP8ri
- 1684014491U, // CMP8rm
- 1281361307U, // CMP8rr
- 1754531233U, // CMPPDrmi
- 1821705633U, // CMPPDrri
- 1755579809U, // CMPPSrmi
- 1822754209U, // CMPPSrri
- 1445U, // CMPS16
- 1451U, // CMPS32
- 1457U, // CMPS64
- 1463U, // CMPS8
- 1756759457U, // CMPSDrm
- 1823802785U, // CMPSDrr
- 1757873569U, // CMPSSrm
- 1824851361U, // CMPSSrr
- 1879049661U, // COMISDrm
- 1281361341U, // COMISDrr
- 1477U, // COS_F
+ 270567011U, // CMOVS16rm
+ 203458147U, // CMOVS16rr
+ 337675883U, // CMOVS32rm
+ 203458155U, // CMOVS32rr
+ 404784755U, // CMOVS64rm
+ 203458163U, // CMOVS64rr
+ 1659U, // CMOV_FR32
+ 1678U, // CMOV_FR64
+ 1697U, // CMOV_GR8
+ 1715U, // CMOV_V1I64
+ 1735U, // CMOV_V2F64
+ 1755U, // CMOV_V2I64
+ 1775U, // CMOV_V4F32
+ 67110659U, // CMP16i16
+ 135268099U, // CMP16mi
+ 135268099U, // CMP16mi8
+ 135268099U, // CMP16mr
+ 1277200131U, // CMP16mrmrr
+ 1277200131U, // CMP16ri
+ 1277200131U, // CMP16ri8
+ 1207961347U, // CMP16rm
+ 1277200131U, // CMP16rr
+ 70256393U, // CMP32i32
+ 135333641U, // CMP32mi
+ 135333641U, // CMP32mi8
+ 135333641U, // CMP32mr
+ 1277200137U, // CMP32mrmrr
+ 1277200137U, // CMP32ri
+ 1277200137U, // CMP32ri8
+ 1342179081U, // CMP32rm
+ 1277200137U, // CMP32rr
+ 71304975U, // CMP64i32
+ 135366415U, // CMP64mi32
+ 135366415U, // CMP64mi8
+ 135366415U, // CMP64mr
+ 1277200143U, // CMP64mrmrr
+ 1277200143U, // CMP64ri32
+ 1277200143U, // CMP64ri8
+ 1409287951U, // CMP64rm
+ 1277200143U, // CMP64rr
+ 72353557U, // CMP8i8
+ 135399189U, // CMP8mi
+ 135399189U, // CMP8mr
+ 1277200149U, // CMP8mrmrr
+ 1277200149U, // CMP8ri
+ 1684014869U, // CMP8rm
+ 1277200149U, // CMP8rr
+ 1754433307U, // CMPPDrmi
+ 1821574939U, // CMPPDrri
+ 1755481883U, // CMPPSrmi
+ 1822623515U, // CMPPSrri
+ 1823U, // CMPS16
+ 1829U, // CMPS32
+ 1835U, // CMPS64
+ 1841U, // CMPS8
+ 1756595995U, // CMPSDrm
+ 1823672091U, // CMPSDrr
+ 1757677339U, // CMPSSrm
+ 1824720667U, // CMPSSrr
+ 1879050039U, // CMPXCHG16B
+ 135268163U, // CMPXCHG16rm
+ 1277200195U, // CMPXCHG16rr
+ 135333709U, // CMPXCHG32rm
+ 1277200205U, // CMPXCHG32rr
+ 135366487U, // CMPXCHG64rm
+ 1277200215U, // CMPXCHG64rr
+ 1476396897U, // CMPXCHG8B
+ 135399276U, // CMPXCHG8rm
+ 1277200236U, // CMPXCHG8rr
+ 1946158966U, // COMISDrm
+ 1277200246U, // COMISDrr
+ 1946158974U, // COMISSrm
+ 1277200254U, // COMISSrr
+ 73402246U, // COMP_FST0r
+ 75499405U, // COM_FIPr
+ 75499413U, // COM_FIr
+ 73402268U, // COM_FST0r
+ 1954U, // COS_F
0U, // COS_Fp32
0U, // COS_Fp64
0U, // COS_Fp80
- 1482U, // CQO
- 282592719U, // CRC32m16
- 349701583U, // CRC32m32
- 483919311U, // CRC32m8
- 215483855U, // CRC32r16
- 215483855U, // CRC32r32
- 215483855U, // CRC32r8
- 416810447U, // CRC64m64
- 215483855U, // CRC64r64
- 1879049687U, // CVTDQ2PDrm
- 1281361367U, // CVTDQ2PDrr
- 1879049697U, // CVTDQ2PSrm
- 1281361377U, // CVTDQ2PSrr
- 1879049707U, // CVTPD2DQrm
- 1281361387U, // CVTPD2DQrr
- 1879049717U, // CVTPS2DQrm
- 1281361397U, // CVTPS2DQrr
- 1946158591U, // CVTSD2SSrm
- 1281361407U, // CVTSD2SSrr
- 1409287689U, // CVTSI2SD64rm
- 1281361417U, // CVTSI2SD64rr
- 1342178836U, // CVTSI2SDrm
- 1281361428U, // CVTSI2SDrr
- 1409287710U, // CVTSI2SS64rm
- 1281361438U, // CVTSI2SS64rr
- 1342178857U, // CVTSI2SSrm
- 1281361449U, // CVTSI2SSrr
- 2013267507U, // CVTSS2SDrm
- 1281361459U, // CVTSS2SDrr
- 1946158653U, // CVTTSD2SI64rm
- 1281361469U, // CVTTSD2SI64rr
- 1946158665U, // CVTTSD2SIrm
- 1281361481U, // CVTTSD2SIrr
- 2013267540U, // CVTTSS2SI64rm
- 1281361492U, // CVTTSS2SI64rr
- 2013267552U, // CVTTSS2SIrm
- 1281361504U, // CVTTSS2SIrr
- 1643U, // CWD
- 1648U, // CWDE
- 872416885U, // DEC16m
- 73401973U, // DEC16r
- 945817211U, // DEC32m
- 73401979U, // DEC32r
- 872416885U, // DEC64_16m
- 73401973U, // DEC64_16r
- 945817211U, // DEC64_32m
- 73401979U, // DEC64_32r
- 1476396673U, // DEC64m
- 73401985U, // DEC64r
- 1610614407U, // DEC8m
- 73401991U, // DEC8r
- 872416909U, // DIV16m
- 73401997U, // DIV16r
- 945817235U, // DIV32m
- 73402003U, // DIV32r
- 1476396697U, // DIV64m
- 73402009U, // DIV64r
- 1610614431U, // DIV8m
- 73402015U, // DIV8r
- 536872613U, // DIVPDrm
- 203425445U, // DIVPDrr
- 536872620U, // DIVPSrm
- 203425452U, // DIVPSrr
- 738199219U, // DIVR_F32m
- 805308091U, // DIVR_F64m
- 872416963U, // DIVR_FI16m
- 945817292U, // DIVR_FI32m
- 73402069U, // DIVR_FPrST0
- 73402076U, // DIVR_FST0r
+ 1959U, // CPUID
+ 1965U, // CQO
+ 282101682U, // CRC32m16
+ 349210546U, // CRC32m32
+ 483428274U, // CRC32m8
+ 214992818U, // CRC32r16
+ 214992818U, // CRC32r32
+ 214992818U, // CRC32r8
+ 416319410U, // CRC64m64
+ 214992818U, // CRC64r64
+ 1946159034U, // CVTDQ2PDrm
+ 1277200314U, // CVTDQ2PDrr
+ 1946159044U, // CVTDQ2PSrm
+ 1277200324U, // CVTDQ2PSrr
+ 1946159054U, // CVTPD2DQrm
+ 1277200334U, // CVTPD2DQrr
+ 1946159064U, // CVTPD2PSrm
+ 1277200344U, // CVTPD2PSrr
+ 1946159074U, // CVTPS2DQrm
+ 1277200354U, // CVTPS2DQrr
+ 2013267948U, // CVTPS2PDrm
+ 1277200364U, // CVTPS2PDrr
+ 2013267958U, // CVTSD2SI64rm
+ 1277200374U, // CVTSD2SI64rr
+ 2013267969U, // CVTSD2SSrm
+ 1277200385U, // CVTSD2SSrr
+ 1409288203U, // CVTSI2SD64rm
+ 1277200395U, // CVTSI2SD64rr
+ 1342179350U, // CVTSI2SDrm
+ 1277200406U, // CVTSI2SDrr
+ 1409288224U, // CVTSI2SS64rm
+ 1277200416U, // CVTSI2SS64rr
+ 1342179371U, // CVTSI2SSrm
+ 1277200427U, // CVTSI2SSrr
+ 2080376885U, // CVTSS2SDrm
+ 1277200437U, // CVTSS2SDrr
+ 2080376895U, // CVTSS2SI64rm
+ 1277200447U, // CVTSS2SI64rr
+ 2080376906U, // CVTSS2SIrm
+ 1277200458U, // CVTSS2SIrr
+ 1946159189U, // CVTTPS2DQrm
+ 1277200469U, // CVTTPS2DQrr
+ 2013268064U, // CVTTSD2SI64rm
+ 1277200480U, // CVTTSD2SI64rr
+ 2013268076U, // CVTTSD2SIrm
+ 1277200492U, // CVTTSD2SIrr
+ 2080376951U, // CVTTSS2SI64rm
+ 1277200503U, // CVTTSS2SI64rr
+ 2080376963U, // CVTTSS2SIrm
+ 1277200515U, // CVTTSS2SIrr
+ 2190U, // CWD
+ 2195U, // CWDE
+ 872417432U, // DEC16m
+ 73402520U, // DEC16r
+ 945817758U, // DEC32m
+ 73402526U, // DEC32r
+ 872417432U, // DEC64_16m
+ 73402520U, // DEC64_16r
+ 945817758U, // DEC64_32m
+ 73402526U, // DEC64_32r
+ 1476397220U, // DEC64m
+ 73402532U, // DEC64r
+ 1610614954U, // DEC8m
+ 73402538U, // DEC8r
+ 872417456U, // DIV16m
+ 73402544U, // DIV16r
+ 945817782U, // DIV32m
+ 73402550U, // DIV32r
+ 1476397244U, // DIV64m
+ 73402556U, // DIV64r
+ 1610614978U, // DIV8m
+ 73402562U, // DIV8r
+ 536873160U, // DIVPDrm
+ 203458760U, // DIVPDrr
+ 536873167U, // DIVPSrm
+ 203458767U, // DIVPSrr
+ 738199766U, // DIVR_F32m
+ 805308638U, // DIVR_F64m
+ 872417510U, // DIVR_FI16m
+ 945817839U, // DIVR_FI32m
+ 73402616U, // DIVR_FPrST0
+ 73402623U, // DIVR_FST0r
0U, // DIVR_Fp32m
0U, // DIVR_Fp64m
0U, // DIVR_Fp64m32
@@ -515,21 +596,21 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIVR_FpI32m32
0U, // DIVR_FpI32m64
0U, // DIVR_FpI32m80
- 73402083U, // DIVR_FrST0
- 603981553U, // DIVSDrm
- 603981553U, // DIVSDrm_Int
- 203425521U, // DIVSDrr
- 203425521U, // DIVSDrr_Int
- 671090424U, // DIVSSrm
- 671090424U, // DIVSSrm_Int
- 203425528U, // DIVSSrr
- 203425528U, // DIVSSrr_Int
- 738199295U, // DIV_F32m
- 805308166U, // DIV_F64m
- 872417037U, // DIV_FI16m
- 945817365U, // DIV_FI32m
- 73402141U, // DIV_FPrST0
- 73402149U, // DIV_FST0r
+ 73402630U, // DIVR_FrST0
+ 603982100U, // DIVSDrm
+ 603982100U, // DIVSDrm_Int
+ 203458836U, // DIVSDrr
+ 203458836U, // DIVSDrr_Int
+ 671090971U, // DIVSSrm
+ 671090971U, // DIVSSrm_Int
+ 203458843U, // DIVSSrr
+ 203458843U, // DIVSSrr_Int
+ 738199842U, // DIV_F32m
+ 805308713U, // DIV_F64m
+ 872417584U, // DIV_FI16m
+ 945817912U, // DIV_FI32m
+ 73402688U, // DIV_FPrST0
+ 73402696U, // DIV_FST0r
0U, // DIV_Fp32
0U, // DIV_Fp32m
0U, // DIV_Fp64
@@ -544,56 +625,82 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIV_FpI32m32
0U, // DIV_FpI32m64
0U, // DIV_FpI32m80
- 73402155U, // DIV_FrST0
- 1013974842U, // DPPDrmi
- 1073743674U, // DPPDrri
- 1013974848U, // DPPSrmi
- 1073743680U, // DPPSrri
- 73402182U, // EH_RETURN
- 73402182U, // EH_RETURN64
- 68749149U, // ENTER
- 2095712100U, // EXTRACTPSmr
- 215680868U, // EXTRACTPSrr
- 68749167U, // FARCALL16i
- 2147485559U, // FARCALL16m
- 68749184U, // FARCALL32i
- 2147485576U, // FARCALL32m
- 2147485585U, // FARCALL64
- 68749210U, // FARJMP16i
- 2147485601U, // FARJMP16m
- 68749225U, // FARJMP32i
- 2147485616U, // FARJMP32m
- 2147485624U, // FARJMP64
- 738199488U, // FBLDm
- 738199494U, // FBSTPm
- 738199501U, // FCOM32m
- 805308365U, // FCOM64m
- 738199507U, // FCOMP32m
- 805308371U, // FCOMP64m
- 872417242U, // FICOM16m
- 945817570U, // FICOM32m
- 872417258U, // FICOMP16m
- 945817587U, // FICOMP32m
- 945817596U, // FISTTP32m
- 872417285U, // FLDCW16m
- 738199564U, // FLDENVm
- 872417300U, // FNSTCW16m
- 2076U, // FNSTSW8r
- 2083U, // FP32_TO_INT16_IN_MEM
- 2114U, // FP32_TO_INT32_IN_MEM
- 2145U, // FP32_TO_INT64_IN_MEM
- 2176U, // FP64_TO_INT16_IN_MEM
- 2207U, // FP64_TO_INT32_IN_MEM
- 2238U, // FP64_TO_INT64_IN_MEM
- 2269U, // FP80_TO_INT16_IN_MEM
- 2300U, // FP80_TO_INT32_IN_MEM
- 2331U, // FP80_TO_INT64_IN_MEM
- 2362U, // FP_REG_KILL
- 738199880U, // FRSTORm
- 738199888U, // FSAVEm
- 738199895U, // FSTENVm
- 738199903U, // FSTSWm
- 1342179686U, // FS_MOV32rm
+ 73402702U, // DIV_FrST0
+ 1013975389U, // DPPDrmi
+ 1073744221U, // DPPDrri
+ 1013975395U, // DPPSrmi
+ 1073744227U, // DPPSrri
+ 73402729U, // EH_RETURN
+ 73402729U, // EH_RETURN64
+ 68454784U, // ENTER
+ 2162493831U, // EXTRACTPSmr
+ 215320967U, // EXTRACTPSrr
+ 2450U, // F2XM1
+ 68454808U, // FARCALL16i
+ 2214594976U, // FARCALL16m
+ 68454825U, // FARCALL32i
+ 2214594993U, // FARCALL32m
+ 2214595002U, // FARCALL64
+ 68454851U, // FARJMP16i
+ 2214595018U, // FARJMP16m
+ 68454866U, // FARJMP32i
+ 2214595033U, // FARJMP32m
+ 2214595041U, // FARJMP64
+ 738200041U, // FBLDm
+ 738200047U, // FBSTPm
+ 738200054U, // FCOM32m
+ 805308925U, // FCOM64m
+ 738200069U, // FCOMP32m
+ 805308941U, // FCOMP64m
+ 2582U, // FCOMPP
+ 2589U, // FDECSTP
+ 73402917U, // FFREE
+ 872417836U, // FICOM16m
+ 945818164U, // FICOM32m
+ 872417852U, // FICOMP16m
+ 945818181U, // FICOMP32m
+ 2638U, // FINCSTP
+ 945818198U, // FISTTP32m
+ 872417887U, // FLDCW16m
+ 738200166U, // FLDENVm
+ 2670U, // FLDL2E
+ 2677U, // FLDL2T
+ 2684U, // FLDLG2
+ 2691U, // FLDLN2
+ 2698U, // FLDPI
+ 2704U, // FNCLEX
+ 2711U, // FNINIT
+ 2718U, // FNOP
+ 872417955U, // FNSTCW16m
+ 2731U, // FNSTSW8r
+ 738200246U, // FNSTSWm
+ 2750U, // FP32_TO_INT16_IN_MEM
+ 2781U, // FP32_TO_INT32_IN_MEM
+ 2812U, // FP32_TO_INT64_IN_MEM
+ 2843U, // FP64_TO_INT16_IN_MEM
+ 2874U, // FP64_TO_INT32_IN_MEM
+ 2905U, // FP64_TO_INT64_IN_MEM
+ 2936U, // FP80_TO_INT16_IN_MEM
+ 2967U, // FP80_TO_INT32_IN_MEM
+ 2998U, // FP80_TO_INT64_IN_MEM
+ 3029U, // FPATAN
+ 3036U, // FPREM
+ 3042U, // FPREM1
+ 3049U, // FPTAN
+ 3055U, // FP_REG_KILL
+ 3069U, // FRNDINT
+ 738200581U, // FRSTORm
+ 738200589U, // FSAVEm
+ 3093U, // FSCALE
+ 3100U, // FSINCOS
+ 738200612U, // FSTENVm
+ 1342180397U, // FS_MOV32rm
+ 3127U, // FXAM
+ 2214595644U, // FXRSTOR
+ 2214595653U, // FXSAVE
+ 3149U, // FXTRACT
+ 3157U, // FYL2X
+ 3163U, // FYL2XP1
0U, // FpGET_ST0_32
0U, // FpGET_ST0_64
0U, // FpGET_ST0_80
@@ -607,47 +714,48 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // FpSET_ST1_64
0U, // FpSET_ST1_80
536871129U, // FsANDNPDrm
- 203423961U, // FsANDNPDrr
+ 203456729U, // FsANDNPDrr
536871137U, // FsANDNPSrm
- 203423969U, // FsANDNPSrr
+ 203456737U, // FsANDNPSrr
536871145U, // FsANDPDrm
- 203423977U, // FsANDPDrr
+ 203456745U, // FsANDPDrr
536871152U, // FsANDPSrm
- 203423984U, // FsANDPSrr
- 68946288U, // FsFLD0SD
- 68946288U, // FsFLD0SS
- 1879050614U, // FsMOVAPDrm
- 1281362294U, // FsMOVAPDrr
- 1879050622U, // FsMOVAPSrm
- 1281362302U, // FsMOVAPSrr
- 536873350U, // FsORPDrm
- 203426182U, // FsORPDrr
- 536873356U, // FsORPSrm
- 203426188U, // FsORPSrr
- 536873362U, // FsXORPDrm
- 203426194U, // FsXORPDrr
- 536873369U, // FsXORPSrm
- 203426201U, // FsXORPSrr
- 1342179744U, // GS_MOV32rm
- 536873386U, // HADDPDrm
- 203426218U, // HADDPDrr
- 536873394U, // HADDPSrm
- 203426226U, // HADDPSrr
- 536873402U, // HSUBPDrm
- 203426234U, // HSUBPDrr
- 536873410U, // HSUBPSrm
- 203426242U, // HSUBPSrr
- 872417738U, // IDIV16m
- 73402826U, // IDIV16r
- 945818065U, // IDIV32m
- 73402833U, // IDIV32r
- 1476397528U, // IDIV64m
- 73402840U, // IDIV64r
- 1610615263U, // IDIV8m
- 73402847U, // IDIV8r
- 872417766U, // ILD_F16m
- 945818093U, // ILD_F32m
- 1476397556U, // ILD_F64m
+ 203456752U, // FsANDPSrr
+ 68553827U, // FsFLD0SD
+ 68553827U, // FsFLD0SS
+ 1946160233U, // FsMOVAPDrm
+ 1277201513U, // FsMOVAPDrr
+ 1946160241U, // FsMOVAPSrm
+ 1277201521U, // FsMOVAPSrr
+ 536874105U, // FsORPDrm
+ 203459705U, // FsORPDrr
+ 536874111U, // FsORPSrm
+ 203459711U, // FsORPSrr
+ 536874117U, // FsXORPDrm
+ 203459717U, // FsXORPDrr
+ 536874124U, // FsXORPSrm
+ 203459724U, // FsXORPSrr
+ 1342180499U, // GS_MOV32rm
+ 536874141U, // HADDPDrm
+ 203459741U, // HADDPDrr
+ 536874149U, // HADDPSrm
+ 203459749U, // HADDPSrr
+ 3245U, // HLT
+ 536874161U, // HSUBPDrm
+ 203459761U, // HSUBPDrr
+ 536874169U, // HSUBPSrm
+ 203459769U, // HSUBPSrr
+ 872418497U, // IDIV16m
+ 73403585U, // IDIV16r
+ 945818824U, // IDIV32m
+ 73403592U, // IDIV32r
+ 1476398287U, // IDIV64m
+ 73403599U, // IDIV64r
+ 1610616022U, // IDIV8m
+ 73403606U, // IDIV8r
+ 872418525U, // ILD_F16m
+ 945818852U, // ILD_F32m
+ 1476398315U, // ILD_F64m
0U, // ILD_Fp16m32
0U, // ILD_Fp16m64
0U, // ILD_Fp16m80
@@ -657,57 +765,67 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ILD_Fp64m32
0U, // ILD_Fp64m64
0U, // ILD_Fp64m80
- 872417788U, // IMUL16m
- 73402876U, // IMUL16r
- 270535164U, // IMUL16rm
- 2096826876U, // IMUL16rmi
- 2096826876U, // IMUL16rmi8
- 203426300U, // IMUL16rr
- 215681532U, // IMUL16rri
- 215681532U, // IMUL16rri8
- 945818115U, // IMUL32m
- 73402883U, // IMUL32r
- 337644035U, // IMUL32rm
- 2097875459U, // IMUL32rmi
- 2097875459U, // IMUL32rmi8
- 203426307U, // IMUL32rr
- 215681539U, // IMUL32rri
- 215681539U, // IMUL32rri8
- 1476397578U, // IMUL64m
- 73402890U, // IMUL64r
- 404752906U, // IMUL64rm
- 2098924042U, // IMUL64rmi32
- 2098924042U, // IMUL64rmi8
- 203426314U, // IMUL64rr
- 215681546U, // IMUL64rri32
- 215681546U, // IMUL64rri8
- 1610615313U, // IMUL8m
- 73402897U, // IMUL8r
- 67111448U, // IN16ri
- 2589U, // IN16rr
- 70257194U, // IN32ri
- 2607U, // IN32rr
- 72354365U, // IN8ri
- 2626U, // IN8rr
- 872417871U, // INC16m
- 73402959U, // INC16r
- 945818197U, // INC32m
- 73402965U, // INC32r
- 872417871U, // INC64_16m
- 73402959U, // INC64_16r
- 945818197U, // INC64_32m
- 73402965U, // INC64_32r
- 1476397659U, // INC64m
- 73402971U, // INC64r
- 1610615393U, // INC8m
- 73402977U, // INC8r
- 1025509991U, // INSERTPSrm
- 1073744487U, // INSERTPSrr
- 73402993U, // INT
- 2678U, // INT3
- 872417916U, // ISTT_FP16m
- 945817596U, // ISTT_FP32m
- 1476397701U, // ISTT_FP64m
+ 872418547U, // IMUL16m
+ 73403635U, // IMUL16r
+ 270568691U, // IMUL16rm
+ 2163215603U, // IMUL16rmi
+ 2163215603U, // IMUL16rmi8
+ 203459827U, // IMUL16rr
+ 215321843U, // IMUL16rri
+ 215321843U, // IMUL16rri8
+ 945818874U, // IMUL32m
+ 73403642U, // IMUL32r
+ 337677562U, // IMUL32rm
+ 2164264186U, // IMUL32rmi
+ 2164264186U, // IMUL32rmi8
+ 203459834U, // IMUL32rr
+ 215321850U, // IMUL32rri
+ 215321850U, // IMUL32rri8
+ 1476398337U, // IMUL64m
+ 73403649U, // IMUL64r
+ 404786433U, // IMUL64rm
+ 2165312769U, // IMUL64rmi32
+ 2165312769U, // IMUL64rmi8
+ 203459841U, // IMUL64rr
+ 215321857U, // IMUL64rri32
+ 215321857U, // IMUL64rri8
+ 1610616072U, // IMUL8m
+ 73403656U, // IMUL8r
+ 3343U, // IN16
+ 67112212U, // IN16ri
+ 3353U, // IN16rr
+ 3366U, // IN32
+ 70257963U, // IN32ri
+ 3376U, // IN32rr
+ 3390U, // IN8
+ 72355139U, // IN8ri
+ 3400U, // IN8rr
+ 872418645U, // INC16m
+ 73403733U, // INC16r
+ 945818971U, // INC32m
+ 73403739U, // INC32r
+ 872418645U, // INC64_16m
+ 73403733U, // INC64_16r
+ 945818971U, // INC64_32m
+ 73403739U, // INC64_32r
+ 1476398433U, // INC64m
+ 73403745U, // INC64r
+ 1610616167U, // INC8m
+ 73403751U, // INC8r
+ 1025510765U, // INSERTPSrm
+ 1073745261U, // INSERTPSrr
+ 73403767U, // INT
+ 3452U, // INT3
+ 3458U, // INVD
+ 3463U, // INVEPT
+ 3470U, // INVLPG
+ 3477U, // INVVPID
+ 3485U, // IRET16
+ 3491U, // IRET32
+ 3497U, // IRET64
+ 872418735U, // ISTT_FP16m
+ 945818198U, // ISTT_FP32m
+ 1476398520U, // ISTT_FP64m
0U, // ISTT_Fp16m32
0U, // ISTT_Fp16m64
0U, // ISTT_Fp16m80
@@ -717,11 +835,11 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ISTT_Fp64m32
0U, // ISTT_Fp64m64
0U, // ISTT_Fp64m80
- 872417935U, // IST_F16m
- 945818262U, // IST_F32m
- 872417949U, // IST_FP16m
- 945818277U, // IST_FP32m
- 1476397741U, // IST_FP64m
+ 872418754U, // IST_F16m
+ 945819081U, // IST_F32m
+ 872418768U, // IST_FP16m
+ 945819096U, // IST_FP32m
+ 1476398560U, // IST_FP64m
0U, // IST_Fp16m32
0U, // IST_Fp16m64
0U, // IST_Fp16m80
@@ -731,132 +849,135 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // IST_Fp64m32
0U, // IST_Fp64m64
0U, // IST_Fp64m80
- 1756759457U, // Int_CMPSDrm
- 1823802785U, // Int_CMPSDrr
- 1757873569U, // Int_CMPSSrm
- 1824851361U, // Int_CMPSSrr
- 1879049661U, // Int_COMISDrm
- 1281361341U, // Int_COMISDrr
- 1879050934U, // Int_COMISSrm
- 1281362614U, // Int_COMISSrr
- 1409287639U, // Int_CVTDQ2PDrm
- 1281361367U, // Int_CVTDQ2PDrr
- 2214594017U, // Int_CVTDQ2PSrm
- 1281361377U, // Int_CVTDQ2PSrr
- 1879049707U, // Int_CVTPD2DQrm
- 1281361387U, // Int_CVTPD2DQrr
- 1879050942U, // Int_CVTPD2PIrm
- 1281362622U, // Int_CVTPD2PIrr
- 1879050952U, // Int_CVTPD2PSrm
- 1281362632U, // Int_CVTPD2PSrr
- 1409288914U, // Int_CVTPI2PDrm
- 1281362642U, // Int_CVTPI2PDrr
- 404753116U, // Int_CVTPI2PSrm
- 203426524U, // Int_CVTPI2PSrr
- 1879049717U, // Int_CVTPS2DQrm
- 1281361397U, // Int_CVTPS2DQrr
- 1946159846U, // Int_CVTPS2PDrm
- 1281362662U, // Int_CVTPS2PDrr
- 1946159856U, // Int_CVTPS2PIrm
- 1281362672U, // Int_CVTPS2PIrr
- 1879051002U, // Int_CVTSD2SI64rm
- 1281362682U, // Int_CVTSD2SI64rr
- 1879051013U, // Int_CVTSD2SIrm
- 1281362693U, // Int_CVTSD2SIrr
- 603981311U, // Int_CVTSD2SSrm
- 203425279U, // Int_CVTSD2SSrr
- 404751881U, // Int_CVTSI2SD64rm
- 203425289U, // Int_CVTSI2SD64rr
- 337643028U, // Int_CVTSI2SDrm
- 203425300U, // Int_CVTSI2SDrr
- 404751902U, // Int_CVTSI2SS64rm
- 203425310U, // Int_CVTSI2SS64rr
- 337643049U, // Int_CVTSI2SSrm
- 203425321U, // Int_CVTSI2SSrr
- 671090227U, // Int_CVTSS2SDrm
- 203425331U, // Int_CVTSS2SDrr
- 2013268751U, // Int_CVTSS2SI64rm
- 1281362703U, // Int_CVTSS2SI64rr
- 2013268762U, // Int_CVTSS2SIrm
- 1281362714U, // Int_CVTSS2SIrr
- 1879051044U, // Int_CVTTPD2DQrm
- 1281362724U, // Int_CVTTPD2DQrr
- 1879051055U, // Int_CVTTPD2PIrm
- 1281362735U, // Int_CVTTPD2PIrr
- 1879051066U, // Int_CVTTPS2DQrm
- 1281362746U, // Int_CVTTPS2DQrr
- 1946159941U, // Int_CVTTPS2PIrm
- 1281362757U, // Int_CVTTPS2PIrr
- 1879049789U, // Int_CVTTSD2SI64rm
- 1281361469U, // Int_CVTTSD2SI64rr
- 1879049801U, // Int_CVTTSD2SIrm
- 1281361481U, // Int_CVTTSD2SIrr
- 2013267540U, // Int_CVTTSS2SI64rm
- 1281361492U, // Int_CVTTSS2SI64rr
- 2013267552U, // Int_CVTTSS2SIrm
- 1281361504U, // Int_CVTTSS2SIrr
- 1879051088U, // Int_UCOMISDrm
- 1281362768U, // Int_UCOMISDrr
- 1879051097U, // Int_UCOMISSrm
- 1281362777U, // Int_UCOMISSrr
- 1549798242U, // JA
- 1549798242U, // JA8
- 1549798246U, // JAE
- 1549798246U, // JAE8
- 1549798251U, // JB
- 1549798251U, // JB8
- 1549798255U, // JBE
- 1549798255U, // JBE8
- 1549798260U, // JCXZ8
- 1549798266U, // JE
- 1549798266U, // JE8
- 1549798270U, // JG
- 1549798270U, // JG8
- 1549798274U, // JGE
- 1549798274U, // JGE8
- 1549798279U, // JL
- 1549798279U, // JL8
- 1549798283U, // JLE
- 1549798283U, // JLE8
- 1549798288U, // JMP
- 945818517U, // JMP32m
- 73403285U, // JMP32r
- 1476397980U, // JMP64m
- 73403292U, // JMP64r
- 1549798288U, // JMP8
- 1549798307U, // JNE
- 1549798307U, // JNE8
- 1549798312U, // JNO
- 1549798312U, // JNO8
- 1549798317U, // JNP
- 1549798317U, // JNP8
- 1549798322U, // JNS
- 1549798322U, // JNS8
- 1549798327U, // JO
- 1549798327U, // JO8
- 1549798331U, // JP
- 1549798331U, // JP8
- 1549798335U, // JS
- 1549798335U, // JS8
- 3011U, // LAHF
- 1207962568U, // LAR16rm
- 1281362888U, // LAR16rr
- 1207962574U, // LAR32rm
- 1281362894U, // LAR32rr
- 1207962580U, // LAR64rm
- 1281362900U, // LAR64rr
- 135269338U, // LCMPXCHG16
- 135334890U, // LCMPXCHG32
- 154143738U, // LCMPXCHG64
- 135465994U, // LCMPXCHG8
- 945818650U, // LCMPXCHG8B
- 2214595627U, // LDDQUrm
- 945818674U, // LDMXCSR
- 3131U, // LD_F0
- 3136U, // LD_F1
- 738200645U, // LD_F32m
- 805309515U, // LD_F64m
- 2281704529U, // LD_F80m
+ 1756595995U, // Int_CMPSDrm
+ 1823672091U, // Int_CMPSDrr
+ 1757677339U, // Int_CMPSSrm
+ 1824720667U, // Int_CMPSSrr
+ 1946158966U, // Int_COMISDrm
+ 1277200246U, // Int_COMISDrr
+ 1946158974U, // Int_COMISSrm
+ 1277200254U, // Int_COMISSrr
+ 1409288122U, // Int_CVTDQ2PDrm
+ 1277200314U, // Int_CVTDQ2PDrr
+ 2281703364U, // Int_CVTDQ2PSrm
+ 1277200324U, // Int_CVTDQ2PSrr
+ 1946159054U, // Int_CVTPD2DQrm
+ 1277200334U, // Int_CVTPD2DQrr
+ 1946160617U, // Int_CVTPD2PIrm
+ 1277201897U, // Int_CVTPD2PIrr
+ 1946159064U, // Int_CVTPD2PSrm
+ 1277200344U, // Int_CVTPD2PSrr
+ 1409289715U, // Int_CVTPI2PDrm
+ 1277201907U, // Int_CVTPI2PDrr
+ 404786685U, // Int_CVTPI2PSrm
+ 203460093U, // Int_CVTPI2PSrr
+ 1946159074U, // Int_CVTPS2DQrm
+ 1277200354U, // Int_CVTPS2DQrr
+ 2013267948U, // Int_CVTPS2PDrm
+ 1277200364U, // Int_CVTPS2PDrr
+ 2013269511U, // Int_CVTPS2PIrm
+ 1277201927U, // Int_CVTPS2PIrr
+ 1946159094U, // Int_CVTSD2SI64rm
+ 1277200374U, // Int_CVTSD2SI64rr
+ 1946160657U, // Int_CVTSD2SIrm
+ 1277201937U, // Int_CVTSD2SIrr
+ 603981825U, // Int_CVTSD2SSrm
+ 203458561U, // Int_CVTSD2SSrr
+ 404785163U, // Int_CVTSI2SD64rm
+ 203458571U, // Int_CVTSI2SD64rr
+ 337676310U, // Int_CVTSI2SDrm
+ 203458582U, // Int_CVTSI2SDrr
+ 404785184U, // Int_CVTSI2SS64rm
+ 203458592U, // Int_CVTSI2SS64rr
+ 337676331U, // Int_CVTSI2SSrm
+ 203458603U, // Int_CVTSI2SSrr
+ 671090741U, // Int_CVTSS2SDrm
+ 203458613U, // Int_CVTSS2SDrr
+ 2080376895U, // Int_CVTSS2SI64rm
+ 1277200447U, // Int_CVTSS2SI64rr
+ 2080378395U, // Int_CVTSS2SIrm
+ 1277201947U, // Int_CVTSS2SIrr
+ 1946160677U, // Int_CVTTPD2DQrm
+ 1277201957U, // Int_CVTTPD2DQrr
+ 1946160688U, // Int_CVTTPD2PIrm
+ 1277201968U, // Int_CVTTPD2PIrr
+ 1946159189U, // Int_CVTTPS2DQrm
+ 1277200469U, // Int_CVTTPS2DQrr
+ 2013269563U, // Int_CVTTPS2PIrm
+ 1277201979U, // Int_CVTTPS2PIrr
+ 1946159200U, // Int_CVTTSD2SI64rm
+ 1277200480U, // Int_CVTTSD2SI64rr
+ 1946159212U, // Int_CVTTSD2SIrm
+ 1277200492U, // Int_CVTTSD2SIrr
+ 2080376951U, // Int_CVTTSS2SI64rm
+ 1277200503U, // Int_CVTTSS2SI64rr
+ 2080376963U, // Int_CVTTSS2SIrm
+ 1277200515U, // Int_CVTTSS2SIrr
+ 1946160710U, // Int_UCOMISDrm
+ 1277201990U, // Int_UCOMISDrr
+ 1946160719U, // Int_UCOMISSrm
+ 1277201999U, // Int_UCOMISSrr
+ 1549799000U, // JA
+ 1549799000U, // JA8
+ 1549799004U, // JAE
+ 1549799004U, // JAE8
+ 1549799009U, // JB
+ 1549799009U, // JB8
+ 1549799013U, // JBE
+ 1549799013U, // JBE8
+ 1549799018U, // JCXZ8
+ 1549799024U, // JE
+ 1549799024U, // JE8
+ 1549799028U, // JG
+ 1549799028U, // JG8
+ 1549799032U, // JGE
+ 1549799032U, // JGE8
+ 1549799037U, // JL
+ 1549799037U, // JL8
+ 1549799041U, // JLE
+ 1549799041U, // JLE8
+ 1549799046U, // JMP
+ 945819275U, // JMP32m
+ 73404043U, // JMP32r
+ 1476398738U, // JMP64m
+ 1549799065U, // JMP64pcrel32
+ 73404050U, // JMP64r
+ 1549799046U, // JMP8
+ 1549799071U, // JNE
+ 1549799071U, // JNE8
+ 1549799076U, // JNO
+ 1549799076U, // JNO8
+ 1549799081U, // JNP
+ 1549799081U, // JNP8
+ 1549799086U, // JNS
+ 1549799086U, // JNS8
+ 1549799091U, // JO
+ 1549799091U, // JO8
+ 1549799095U, // JP
+ 1549799095U, // JP8
+ 1549799099U, // JS
+ 1549799099U, // JS8
+ 3775U, // LAHF
+ 1207963332U, // LAR16rm
+ 1277202116U, // LAR16rr
+ 1207963338U, // LAR32rm
+ 1277202122U, // LAR32rr
+ 1207963344U, // LAR64rm
+ 1277202128U, // LAR64rr
+ 135270102U, // LCMPXCHG16
+ 135335654U, // LCMPXCHG32
+ 154144502U, // LCMPXCHG64
+ 135401222U, // LCMPXCHG8
+ 945819414U, // LCMPXCHG8B
+ 2281705255U, // LDDQUrm
+ 945819438U, // LDMXCSR
+ 2348814135U, // LDS16rm
+ 2348814141U, // LDS32rm
+ 3907U, // LD_F0
+ 3912U, // LD_F1
+ 738201421U, // LD_F32m
+ 805310291U, // LD_F64m
+ 2415923033U, // LD_F80m
0U, // LD_Fp032
0U, // LD_Fp064
0U, // LD_Fp080
@@ -869,414 +990,461 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // LD_Fp64m
0U, // LD_Fp64m80
0U, // LD_Fp80m
- 73403479U, // LD_Frr
- 2348813404U, // LEA16r
- 2348813410U, // LEA32r
- 2415922274U, // LEA64_32r
- 2483031144U, // LEA64r
- 3182U, // LEAVE
- 3182U, // LEAVE64
- 3188U, // LFENCE
- 135269499U, // LOCK_ADD16mi
- 135269499U, // LOCK_ADD16mi8
- 135269499U, // LOCK_ADD16mr
- 135335047U, // LOCK_ADD32mi
- 135335047U, // LOCK_ADD32mi8
- 135335047U, // LOCK_ADD32mr
- 135400595U, // LOCK_ADD64mi32
- 135400595U, // LOCK_ADD64mi8
- 135400595U, // LOCK_ADD64mr
- 135466143U, // LOCK_ADD8mi
- 135466143U, // LOCK_ADD8mr
- 872418475U, // LOCK_DEC16m
- 945818807U, // LOCK_DEC32m
- 1476398275U, // LOCK_DEC64m
- 1610616015U, // LOCK_DEC8m
- 872418523U, // LOCK_INC16m
- 945818855U, // LOCK_INC32m
- 1476398323U, // LOCK_INC64m
- 1610616063U, // LOCK_INC8m
- 135269643U, // LOCK_SUB16mi
- 135269643U, // LOCK_SUB16mi8
- 135269643U, // LOCK_SUB16mr
- 135335191U, // LOCK_SUB32mi
- 135335191U, // LOCK_SUB32mi8
- 135335191U, // LOCK_SUB32mr
- 135400739U, // LOCK_SUB64mi32
- 135400739U, // LOCK_SUB64mi8
- 135400739U, // LOCK_SUB64mr
- 135466287U, // LOCK_SUB8mi
- 135466287U, // LOCK_SUB8mr
- 3387U, // LODSB
- 3393U, // LODSD
- 3399U, // LODSQ
- 3405U, // LODSW
- 1549798739U, // LOOP
- 1549798745U, // LOOPE
- 1549798752U, // LOOPNE
- 3432U, // LRET
- 73403757U, // LRETI
- 2096631155U, // LXADD16
- 2097679744U, // LXADD32
- 2098728333U, // LXADD64
- 2101349785U, // LXADD8
- 1281363366U, // MASKMOVDQU
- 1281363366U, // MASKMOVDQU64
- 536874418U, // MAXPDrm
- 536874418U, // MAXPDrm_Int
- 203427250U, // MAXPDrr
- 203427250U, // MAXPDrr_Int
- 536874425U, // MAXPSrm
- 536874425U, // MAXPSrm_Int
- 203427257U, // MAXPSrr
- 203427257U, // MAXPSrr_Int
- 603983296U, // MAXSDrm
- 603983296U, // MAXSDrm_Int
- 203427264U, // MAXSDrr
- 203427264U, // MAXSDrr_Int
- 671092167U, // MAXSSrm
- 671092167U, // MAXSSrm_Int
- 203427271U, // MAXSSrr
- 203427271U, // MAXSSrr_Int
- 3534U, // MFENCE
- 536874453U, // MINPDrm
- 536874453U, // MINPDrm_Int
- 203427285U, // MINPDrr
- 203427285U, // MINPDrr_Int
- 536874460U, // MINPSrm
- 536874460U, // MINPSrm_Int
- 203427292U, // MINPSrr
- 203427292U, // MINPSrr_Int
- 603983331U, // MINSDrm
- 603983331U, // MINSDrm_Int
- 203427299U, // MINSDrr
- 203427299U, // MINSDrr_Int
- 671092202U, // MINSSrm
- 671092202U, // MINSSrm_Int
- 203427306U, // MINSSrr
- 203427306U, // MINSSrr_Int
- 1879050942U, // MMX_CVTPD2PIrm
- 1281362622U, // MMX_CVTPD2PIrr
- 1409288914U, // MMX_CVTPI2PDrm
- 1281362642U, // MMX_CVTPI2PDrr
- 1409288924U, // MMX_CVTPI2PSrm
- 1281362652U, // MMX_CVTPI2PSrr
- 1946159856U, // MMX_CVTPS2PIrm
- 1281362672U, // MMX_CVTPS2PIrr
- 1879051055U, // MMX_CVTTPD2PIrm
- 1281362735U, // MMX_CVTTPD2PIrr
- 1946159941U, // MMX_CVTTPS2PIrm
- 1281362757U, // MMX_CVTTPS2PIrr
- 3569U, // MMX_EMMS
- 3574U, // MMX_FEMMS
- 1281363452U, // MMX_MASKMOVQ
- 1281363452U, // MMX_MASKMOVQ64
- 1281363462U, // MMX_MOVD64from64rr
- 135335430U, // MMX_MOVD64mr
- 1342180870U, // MMX_MOVD64rm
- 1281363462U, // MMX_MOVD64rr
- 1281363462U, // MMX_MOVD64rrv164
- 1281363462U, // MMX_MOVD64to64rr
- 1281363468U, // MMX_MOVDQ2Qrr
- 135400981U, // MMX_MOVNTQmr
- 1281363485U, // MMX_MOVQ2DQrr
- 1281363485U, // MMX_MOVQ2FR64rr
- 135400998U, // MMX_MOVQ64mr
- 1409289766U, // MMX_MOVQ64rm
- 1281363494U, // MMX_MOVQ64rr
- 1342180870U, // MMX_MOVZDI2PDIrm
- 1281363462U, // MMX_MOVZDI2PDIrr
- 404753964U, // MMX_PACKSSDWrm
- 203427372U, // MMX_PACKSSDWrr
- 404753974U, // MMX_PACKSSWBrm
- 203427382U, // MMX_PACKSSWBrr
- 404753984U, // MMX_PACKUSWBrm
- 203427392U, // MMX_PACKUSWBrr
- 404753994U, // MMX_PADDBrm
- 203427402U, // MMX_PADDBrr
- 404754001U, // MMX_PADDDrm
- 203427409U, // MMX_PADDDrr
- 404754008U, // MMX_PADDQrm
- 203427416U, // MMX_PADDQrr
- 404754015U, // MMX_PADDSBrm
- 203427423U, // MMX_PADDSBrr
- 404754023U, // MMX_PADDSWrm
- 203427431U, // MMX_PADDSWrr
- 404754031U, // MMX_PADDUSBrm
- 203427439U, // MMX_PADDUSBrr
- 404754040U, // MMX_PADDUSWrm
- 203427448U, // MMX_PADDUSWrr
- 404754049U, // MMX_PADDWrm
- 203427457U, // MMX_PADDWrr
- 404754056U, // MMX_PANDNrm
- 203427464U, // MMX_PANDNrr
- 404754063U, // MMX_PANDrm
- 203427471U, // MMX_PANDrr
- 404754069U, // MMX_PAVGBrm
- 203427477U, // MMX_PAVGBrr
- 404754076U, // MMX_PAVGWrm
- 203427484U, // MMX_PAVGWrr
- 404754083U, // MMX_PCMPEQBrm
- 203427491U, // MMX_PCMPEQBrr
- 404754092U, // MMX_PCMPEQDrm
- 203427500U, // MMX_PCMPEQDrr
- 404754101U, // MMX_PCMPEQWrm
- 203427509U, // MMX_PCMPEQWrr
- 404754110U, // MMX_PCMPGTBrm
- 203427518U, // MMX_PCMPGTBrr
- 404754119U, // MMX_PCMPGTDrm
- 203427527U, // MMX_PCMPGTDrr
- 404754128U, // MMX_PCMPGTWrm
- 203427536U, // MMX_PCMPGTWrr
- 215682777U, // MMX_PEXTRWri
- 1028656865U, // MMX_PINSRWrmi
- 1073745633U, // MMX_PINSRWrri
- 404754153U, // MMX_PMADDWDrm
- 203427561U, // MMX_PMADDWDrr
- 404754162U, // MMX_PMAXSWrm
- 203427570U, // MMX_PMAXSWrr
- 404754170U, // MMX_PMAXUBrm
- 203427578U, // MMX_PMAXUBrr
- 404754178U, // MMX_PMINSWrm
- 203427586U, // MMX_PMINSWrr
- 404754186U, // MMX_PMINUBrm
- 203427594U, // MMX_PMINUBrr
- 1281363730U, // MMX_PMOVMSKBrr
- 404754204U, // MMX_PMULHUWrm
- 203427612U, // MMX_PMULHUWrr
- 404754213U, // MMX_PMULHWrm
- 203427621U, // MMX_PMULHWrr
- 404754221U, // MMX_PMULLWrm
- 203427629U, // MMX_PMULLWrr
- 404754229U, // MMX_PMULUDQrm
- 203427637U, // MMX_PMULUDQrr
- 404754238U, // MMX_PORrm
- 203427646U, // MMX_PORrr
- 404754243U, // MMX_PSADBWrm
- 203427651U, // MMX_PSADBWrr
- 2098925387U, // MMX_PSHUFWmi
- 215682891U, // MMX_PSHUFWri
- 203427667U, // MMX_PSLLDri
- 404754259U, // MMX_PSLLDrm
- 203427667U, // MMX_PSLLDrr
- 203427674U, // MMX_PSLLQri
- 404754266U, // MMX_PSLLQrm
- 203427674U, // MMX_PSLLQrr
- 203427681U, // MMX_PSLLWri
- 404754273U, // MMX_PSLLWrm
- 203427681U, // MMX_PSLLWrr
- 203427688U, // MMX_PSRADri
- 404754280U, // MMX_PSRADrm
- 203427688U, // MMX_PSRADrr
- 203427695U, // MMX_PSRAWri
- 404754287U, // MMX_PSRAWrm
- 203427695U, // MMX_PSRAWrr
- 203427702U, // MMX_PSRLDri
- 404754294U, // MMX_PSRLDrm
- 203427702U, // MMX_PSRLDrr
- 203427709U, // MMX_PSRLQri
- 404754301U, // MMX_PSRLQrm
- 203427709U, // MMX_PSRLQrr
- 203427716U, // MMX_PSRLWri
- 404754308U, // MMX_PSRLWrm
- 203427716U, // MMX_PSRLWrr
- 404754315U, // MMX_PSUBBrm
- 203427723U, // MMX_PSUBBrr
- 404754322U, // MMX_PSUBDrm
- 203427730U, // MMX_PSUBDrr
- 404754329U, // MMX_PSUBQrm
- 203427737U, // MMX_PSUBQrr
- 404754336U, // MMX_PSUBSBrm
- 203427744U, // MMX_PSUBSBrr
- 404754344U, // MMX_PSUBSWrm
- 203427752U, // MMX_PSUBSWrr
- 404754352U, // MMX_PSUBUSBrm
- 203427760U, // MMX_PSUBUSBrr
- 404754361U, // MMX_PSUBUSWrm
- 203427769U, // MMX_PSUBUSWrr
- 404754370U, // MMX_PSUBWrm
- 203427778U, // MMX_PSUBWrr
- 404754377U, // MMX_PUNPCKHBWrm
- 203427785U, // MMX_PUNPCKHBWrr
- 404754388U, // MMX_PUNPCKHDQrm
- 203427796U, // MMX_PUNPCKHDQrr
- 404754399U, // MMX_PUNPCKHWDrm
- 203427807U, // MMX_PUNPCKHWDrr
- 404754410U, // MMX_PUNPCKLBWrm
- 203427818U, // MMX_PUNPCKLBWrr
- 404754421U, // MMX_PUNPCKLDQrm
- 203427829U, // MMX_PUNPCKLDQrr
- 404754432U, // MMX_PUNPCKLWDrm
- 203427840U, // MMX_PUNPCKLWDrr
- 404752752U, // MMX_PXORrm
- 203426160U, // MMX_PXORrr
- 68946288U, // MMX_V_SET0
- 68947628U, // MMX_V_SETALLONES
- 4107U, // MONITOR
- 73404435U, // MOV16ao16
- 135270430U, // MOV16mi
- 135270430U, // MOV16mr
- 135270430U, // MOV16ms
- 67112990U, // MOV16o16a
- 0U, // MOV16r0
- 1281363998U, // MOV16ri
- 1207963678U, // MOV16rm
- 1281363998U, // MOV16rr
- 1281363998U, // MOV16rs
- 1207963678U, // MOV16sm
- 1281363998U, // MOV16sr
- 73404452U, // MOV32ao32
- 135335984U, // MOV32mi
- 135335984U, // MOV32mr
- 70258736U, // MOV32o32a
- 68948022U, // MOV32r0
- 1281364016U, // MOV32ri
- 1342181424U, // MOV32rm
- 1281364016U, // MOV32rr
- 1409290300U, // MOV64FSrm
- 1409290310U, // MOV64GSrm
- 73404496U, // MOV64ao32
- 73404496U, // MOV64ao8
- 135400998U, // MOV64mi32
- 135400998U, // MOV64mr
- 135401502U, // MOV64ms
- 71306790U, // MOV64o32a
- 71306790U, // MOV64o8a
- 1281364060U, // MOV64ri
- 1281363494U, // MOV64ri32
+ 73404255U, // LD_Frr
+ 2483031908U, // LEA16r
+ 2483031914U, // LEA32r
+ 2550140778U, // LEA64_32r
+ 2617249648U, // LEA64r
+ 3958U, // LEAVE
+ 3958U, // LEAVE64
+ 2348814204U, // LES16rm
+ 2348814210U, // LES32rm
+ 3976U, // LFENCE
+ 2348814223U, // LFS16rm
+ 2348814229U, // LFS32rm
+ 2348814235U, // LFS64rm
+ 2214596513U, // LGDTm
+ 2348814247U, // LGS16rm
+ 2348814253U, // LGS32rm
+ 2348814259U, // LGS64rm
+ 2214596537U, // LIDTm
+ 872419263U, // LLDT16m
+ 73404351U, // LLDT16r
+ 872419270U, // LMSW16m
+ 73404358U, // LMSW16r
+ 135270349U, // LOCK_ADD16mi
+ 135270349U, // LOCK_ADD16mi8
+ 135270349U, // LOCK_ADD16mr
+ 135335897U, // LOCK_ADD32mi
+ 135335897U, // LOCK_ADD32mi8
+ 135335897U, // LOCK_ADD32mr
+ 135368677U, // LOCK_ADD64mi32
+ 135368677U, // LOCK_ADD64mi8
+ 135368677U, // LOCK_ADD64mr
+ 135401457U, // LOCK_ADD8mi
+ 135401457U, // LOCK_ADD8mr
+ 872419325U, // LOCK_DEC16m
+ 945819657U, // LOCK_DEC32m
+ 1476399125U, // LOCK_DEC64m
+ 1610616865U, // LOCK_DEC8m
+ 872419373U, // LOCK_INC16m
+ 945819705U, // LOCK_INC32m
+ 1476399173U, // LOCK_INC64m
+ 1610616913U, // LOCK_INC8m
+ 135270493U, // LOCK_SUB16mi
+ 135270493U, // LOCK_SUB16mi8
+ 135270493U, // LOCK_SUB16mr
+ 135336041U, // LOCK_SUB32mi
+ 135336041U, // LOCK_SUB32mi8
+ 135336041U, // LOCK_SUB32mr
+ 135368821U, // LOCK_SUB64mi32
+ 135368821U, // LOCK_SUB64mi8
+ 135368821U, // LOCK_SUB64mr
+ 135401601U, // LOCK_SUB8mi
+ 135401601U, // LOCK_SUB8mr
+ 4237U, // LODSB
+ 4243U, // LODSD
+ 4249U, // LODSQ
+ 4255U, // LODSW
+ 1549799589U, // LOOP
+ 1549799595U, // LOOPE
+ 1549799602U, // LOOPNE
+ 4282U, // LRET
+ 73404607U, // LRETI
+ 1207963845U, // LSL16rm
+ 1277202629U, // LSL16rr
+ 1342181579U, // LSL32rm
+ 1277202635U, // LSL32rr
+ 1409290449U, // LSL64rm
+ 1277202641U, // LSL64rr
+ 2348814551U, // LSS16rm
+ 2348814557U, // LSS32rm
+ 2348814563U, // LSS64rm
+ 872419561U, // LTRm
+ 73404649U, // LTRr
+ 1296077039U, // LXADD16
+ 1297125628U, // LXADD32
+ 1298174217U, // LXADD64
+ 1299222805U, // LXADD8
+ 1277202722U, // MASKMOVDQU
+ 1277202722U, // MASKMOVDQU64
+ 536875310U, // MAXPDrm
+ 536875310U, // MAXPDrm_Int
+ 203460910U, // MAXPDrr
+ 203460910U, // MAXPDrr_Int
+ 536875317U, // MAXPSrm
+ 536875317U, // MAXPSrm_Int
+ 203460917U, // MAXPSrr
+ 203460917U, // MAXPSrr_Int
+ 603984188U, // MAXSDrm
+ 603984188U, // MAXSDrm_Int
+ 203460924U, // MAXSDrr
+ 203460924U, // MAXSDrr_Int
+ 671093059U, // MAXSSrm
+ 671093059U, // MAXSSrm_Int
+ 203460931U, // MAXSSrr
+ 203460931U, // MAXSSrr_Int
+ 4426U, // MFENCE
+ 536875345U, // MINPDrm
+ 536875345U, // MINPDrm_Int
+ 203460945U, // MINPDrr
+ 203460945U, // MINPDrr_Int
+ 536875352U, // MINPSrm
+ 536875352U, // MINPSrm_Int
+ 203460952U, // MINPSrr
+ 203460952U, // MINPSrr_Int
+ 603984223U, // MINSDrm
+ 603984223U, // MINSDrm_Int
+ 203460959U, // MINSDrr
+ 203460959U, // MINSDrr_Int
+ 671093094U, // MINSSrm
+ 671093094U, // MINSSrm_Int
+ 203460966U, // MINSSrr
+ 203460966U, // MINSSrr_Int
+ 1946160617U, // MMX_CVTPD2PIrm
+ 1277201897U, // MMX_CVTPD2PIrr
+ 1409289715U, // MMX_CVTPI2PDrm
+ 1277201907U, // MMX_CVTPI2PDrr
+ 1409289725U, // MMX_CVTPI2PSrm
+ 1277201917U, // MMX_CVTPI2PSrr
+ 2013269511U, // MMX_CVTPS2PIrm
+ 1277201927U, // MMX_CVTPS2PIrr
+ 1946160688U, // MMX_CVTTPD2PIrm
+ 1277201968U, // MMX_CVTTPD2PIrr
+ 2013269563U, // MMX_CVTTPS2PIrm
+ 1277201979U, // MMX_CVTTPS2PIrr
+ 4461U, // MMX_EMMS
+ 4466U, // MMX_FEMMS
+ 1277202808U, // MMX_MASKMOVQ
+ 1277202808U, // MMX_MASKMOVQ64
+ 1277202818U, // MMX_MOVD64from64rr
+ 1277202818U, // MMX_MOVD64grr
+ 135336322U, // MMX_MOVD64mr
+ 1342181762U, // MMX_MOVD64rm
+ 1277202818U, // MMX_MOVD64rr
+ 1277202818U, // MMX_MOVD64rrv164
+ 1277202818U, // MMX_MOVD64to64rr
+ 1277202824U, // MMX_MOVDQ2Qrr
+ 135369105U, // MMX_MOVNTQmr
+ 1277202841U, // MMX_MOVQ2DQrr
+ 1277202841U, // MMX_MOVQ2FR64rr
+ 135369122U, // MMX_MOVQ64gmr
+ 135369122U, // MMX_MOVQ64mr
+ 1409290658U, // MMX_MOVQ64rm
+ 1277202850U, // MMX_MOVQ64rr
+ 1342181762U, // MMX_MOVZDI2PDIrm
+ 1277202818U, // MMX_MOVZDI2PDIrr
+ 404787624U, // MMX_PACKSSDWrm
+ 203461032U, // MMX_PACKSSDWrr
+ 404787634U, // MMX_PACKSSWBrm
+ 203461042U, // MMX_PACKSSWBrr
+ 404787644U, // MMX_PACKUSWBrm
+ 203461052U, // MMX_PACKUSWBrr
+ 404787654U, // MMX_PADDBrm
+ 203461062U, // MMX_PADDBrr
+ 404787661U, // MMX_PADDDrm
+ 203461069U, // MMX_PADDDrr
+ 404787668U, // MMX_PADDQrm
+ 203461076U, // MMX_PADDQrr
+ 404787675U, // MMX_PADDSBrm
+ 203461083U, // MMX_PADDSBrr
+ 404787683U, // MMX_PADDSWrm
+ 203461091U, // MMX_PADDSWrr
+ 404787691U, // MMX_PADDUSBrm
+ 203461099U, // MMX_PADDUSBrr
+ 404787700U, // MMX_PADDUSWrm
+ 203461108U, // MMX_PADDUSWrr
+ 404787709U, // MMX_PADDWrm
+ 203461117U, // MMX_PADDWrr
+ 404787716U, // MMX_PANDNrm
+ 203461124U, // MMX_PANDNrr
+ 404787723U, // MMX_PANDrm
+ 203461131U, // MMX_PANDrr
+ 404787729U, // MMX_PAVGBrm
+ 203461137U, // MMX_PAVGBrr
+ 404787736U, // MMX_PAVGWrm
+ 203461144U, // MMX_PAVGWrr
+ 404787743U, // MMX_PCMPEQBrm
+ 203461151U, // MMX_PCMPEQBrr
+ 404787752U, // MMX_PCMPEQDrm
+ 203461160U, // MMX_PCMPEQDrr
+ 404787761U, // MMX_PCMPEQWrm
+ 203461169U, // MMX_PCMPEQWrr
+ 404787770U, // MMX_PCMPGTBrm
+ 203461178U, // MMX_PCMPGTBrr
+ 404787779U, // MMX_PCMPGTDrm
+ 203461187U, // MMX_PCMPGTDrr
+ 404787788U, // MMX_PCMPGTWrm
+ 203461196U, // MMX_PCMPGTWrr
+ 215323221U, // MMX_PEXTRWri
+ 1027969629U, // MMX_PINSRWrmi
+ 1073746525U, // MMX_PINSRWrri
+ 404787813U, // MMX_PMADDWDrm
+ 203461221U, // MMX_PMADDWDrr
+ 404787822U, // MMX_PMAXSWrm
+ 203461230U, // MMX_PMAXSWrr
+ 404787830U, // MMX_PMAXUBrm
+ 203461238U, // MMX_PMAXUBrr
+ 404787838U, // MMX_PMINSWrm
+ 203461246U, // MMX_PMINSWrr
+ 404787846U, // MMX_PMINUBrm
+ 203461254U, // MMX_PMINUBrr
+ 1277203086U, // MMX_PMOVMSKBrr
+ 404787864U, // MMX_PMULHUWrm
+ 203461272U, // MMX_PMULHUWrr
+ 404787873U, // MMX_PMULHWrm
+ 203461281U, // MMX_PMULHWrr
+ 404787881U, // MMX_PMULLWrm
+ 203461289U, // MMX_PMULLWrr
+ 404787889U, // MMX_PMULUDQrm
+ 203461297U, // MMX_PMULUDQrr
+ 404787898U, // MMX_PORrm
+ 203461306U, // MMX_PORrr
+ 404787903U, // MMX_PSADBWrm
+ 203461311U, // MMX_PSADBWrr
+ 2165314247U, // MMX_PSHUFWmi
+ 215323335U, // MMX_PSHUFWri
+ 203461327U, // MMX_PSLLDri
+ 404787919U, // MMX_PSLLDrm
+ 203461327U, // MMX_PSLLDrr
+ 203461334U, // MMX_PSLLQri
+ 404787926U, // MMX_PSLLQrm
+ 203461334U, // MMX_PSLLQrr
+ 203461341U, // MMX_PSLLWri
+ 404787933U, // MMX_PSLLWrm
+ 203461341U, // MMX_PSLLWrr
+ 203461348U, // MMX_PSRADri
+ 404787940U, // MMX_PSRADrm
+ 203461348U, // MMX_PSRADrr
+ 203461355U, // MMX_PSRAWri
+ 404787947U, // MMX_PSRAWrm
+ 203461355U, // MMX_PSRAWrr
+ 203461362U, // MMX_PSRLDri
+ 404787954U, // MMX_PSRLDrm
+ 203461362U, // MMX_PSRLDrr
+ 203461369U, // MMX_PSRLQri
+ 404787961U, // MMX_PSRLQrm
+ 203461369U, // MMX_PSRLQrr
+ 203461376U, // MMX_PSRLWri
+ 404787968U, // MMX_PSRLWrm
+ 203461376U, // MMX_PSRLWrr
+ 404787975U, // MMX_PSUBBrm
+ 203461383U, // MMX_PSUBBrr
+ 404787982U, // MMX_PSUBDrm
+ 203461390U, // MMX_PSUBDrr
+ 404787989U, // MMX_PSUBQrm
+ 203461397U, // MMX_PSUBQrr
+ 404787996U, // MMX_PSUBSBrm
+ 203461404U, // MMX_PSUBSBrr
+ 404788004U, // MMX_PSUBSWrm
+ 203461412U, // MMX_PSUBSWrr
+ 404788012U, // MMX_PSUBUSBrm
+ 203461420U, // MMX_PSUBUSBrr
+ 404788021U, // MMX_PSUBUSWrm
+ 203461429U, // MMX_PSUBUSWrr
+ 404788030U, // MMX_PSUBWrm
+ 203461438U, // MMX_PSUBWrr
+ 404788037U, // MMX_PUNPCKHBWrm
+ 203461445U, // MMX_PUNPCKHBWrr
+ 404788048U, // MMX_PUNPCKHDQrm
+ 203461456U, // MMX_PUNPCKHDQrr
+ 404788059U, // MMX_PUNPCKHWDrm
+ 203461467U, // MMX_PUNPCKHWDrr
+ 404788070U, // MMX_PUNPCKLBWrm
+ 203461478U, // MMX_PUNPCKLBWrr
+ 404788081U, // MMX_PUNPCKLDQrm
+ 203461489U, // MMX_PUNPCKLDQrr
+ 404788092U, // MMX_PUNPCKLWDrm
+ 203461500U, // MMX_PUNPCKLWDrr
+ 404786275U, // MMX_PXORrm
+ 203459683U, // MMX_PXORrr
+ 68553827U, // MMX_V_SET0
+ 68555304U, // MMX_V_SETALLONES
+ 4999U, // MONITOR
+ 1549800335U, // MOV16ao16
+ 135271322U, // MOV16mi
+ 135271322U, // MOV16mr
+ 135271322U, // MOV16ms
+ 1543508890U, // MOV16o16a
+ 1277203354U, // MOV16ri
+ 1207964570U, // MOV16rm
+ 1277203354U, // MOV16rr
+ 1277203354U, // MOV16rr_REV
+ 1277203354U, // MOV16rs
+ 1207964570U, // MOV16sm
+ 1277203354U, // MOV16sr
+ 1549800352U, // MOV32ao32
+ 1277202850U, // MOV32cr
+ 1277203372U, // MOV32dr
+ 135336876U, // MOV32mi
+ 135336876U, // MOV32mr
+ 1546654636U, // MOV32o32a
+ 68555698U, // MOV32r0
+ 1277202850U, // MOV32rc
+ 1277203372U, // MOV32rd
+ 1277203372U, // MOV32ri
+ 1342182316U, // MOV32rm
+ 1277203372U, // MOV32rr
+ 1277203372U, // MOV32rr_REV
+ 1409291192U, // MOV64FSrm
+ 1409291202U, // MOV64GSrm
+ 1549800396U, // MOV64ao64
+ 1549800396U, // MOV64ao8
+ 1277202850U, // MOV64cr
+ 1277202850U, // MOV64dr
+ 135369122U, // MOV64mi32
+ 135369122U, // MOV64mr
+ 135369122U, // MOV64ms
+ 1547702690U, // MOV64o64a
+ 1547702690U, // MOV64o8a
+ 1277202850U, // MOV64rc
+ 1277202850U, // MOV64rd
+ 1277203416U, // MOV64ri
+ 1277202850U, // MOV64ri32
0U, // MOV64ri64i32
- 1409289766U, // MOV64rm
- 1281363494U, // MOV64rr
- 1281363998U, // MOV64rs
- 1409290270U, // MOV64sm
- 1281363998U, // MOV64sr
- 1281363462U, // MOV64toPQIrr
- 1409289766U, // MOV64toSDrm
- 1281363462U, // MOV64toSDrr
- 73404517U, // MOV8ao8
- 135467120U, // MOV8mi
- 135467120U, // MOV8mr
- 135483504U, // MOV8mr_NOREX
- 72355952U, // MOV8o8a
- 68948086U, // MOV8r0
- 1281364080U, // MOV8ri
- 1684017264U, // MOV8rm
- 1700794480U, // MOV8rm_NOREX
- 1281364080U, // MOV8rr
- 1298141296U, // MOV8rr_NOREX
- 136120694U, // MOVAPDmr
- 1879050614U, // MOVAPDrm
- 1281362294U, // MOVAPDrr
- 136120702U, // MOVAPSmr
- 1879050622U, // MOVAPSrm
- 1281362302U, // MOVAPSrr
- 1946161276U, // MOVDDUPrm
- 1281364092U, // MOVDDUPrr
- 1342180870U, // MOVDI2PDIrm
- 1281363462U, // MOVDI2PDIrr
- 1342180870U, // MOVDI2SSrm
- 1281363462U, // MOVDI2SSrr
- 136188037U, // MOVDQAmr
- 2214596741U, // MOVDQArm
- 1281364101U, // MOVDQArr
- 136188045U, // MOVDQUmr
- 136188045U, // MOVDQUmr_Int
- 2214596749U, // MOVDQUrm
- 2214596749U, // MOVDQUrm_Int
- 203427989U, // MOVHLPSrr
- 136253598U, // MOVHPDmr
- 603984030U, // MOVHPDrm
- 136253606U, // MOVHPSmr
- 603984038U, // MOVHPSrm
- 203428014U, // MOVLHPSrr
- 136253623U, // MOVLPDmr
- 603984055U, // MOVLPDrm
- 203428031U, // MOVLPDrr
- 136253638U, // MOVLPSmr
- 603984070U, // MOVLPSrm
- 203428046U, // MOVLPSrr
- 135400998U, // MOVLQ128mr
- 203428031U, // MOVLSD2PDrr
- 203428046U, // MOVLSS2PSrr
- 1281364181U, // MOVMSKPDrr
- 1281364191U, // MOVMSKPSrr
- 2214596841U, // MOVNTDQArm
- 136122611U, // MOVNTDQmr
- 135336188U, // MOVNTImr
- 136188164U, // MOVNTPDmr
- 136188173U, // MOVNTPSmr
+ 1409290658U, // MOV64rm
+ 1277202850U, // MOV64rr
+ 1277202850U, // MOV64rr_REV
+ 1277202850U, // MOV64rs
+ 1409290658U, // MOV64sm
+ 1277202850U, // MOV64sr
+ 1277202818U, // MOV64toPQIrr
+ 1409290658U, // MOV64toSDrm
+ 1277202818U, // MOV64toSDrr
+ 1549800417U, // MOV8ao8
+ 135402476U, // MOV8mi
+ 135402476U, // MOV8mr
+ 135402476U, // MOV8mr_NOREX
+ 1548751852U, // MOV8o8a
+ 68555762U, // MOV8r0
+ 1277203436U, // MOV8ri
+ 1684018156U, // MOV8rm
+ 1702892524U, // MOV8rm_NOREX
+ 1277203436U, // MOV8rr
+ 1277596652U, // MOV8rr_NOREX
+ 1277203436U, // MOV8rr_REV
+ 135728233U, // MOVAPDmr
+ 1946160233U, // MOVAPDrm
+ 1277201513U, // MOVAPDrr
+ 135728241U, // MOVAPSmr
+ 1946160241U, // MOVAPSrm
+ 1277201521U, // MOVAPSrr
+ 2013271032U, // MOVDDUPrm
+ 1277203448U, // MOVDDUPrr
+ 1342181762U, // MOVDI2PDIrm
+ 1277202818U, // MOVDI2PDIrr
+ 1342181762U, // MOVDI2SSrm
+ 1277202818U, // MOVDI2SSrr
+ 135762945U, // MOVDQAmr
+ 2281706497U, // MOVDQArm
+ 1277203457U, // MOVDQArr
+ 135762953U, // MOVDQUmr
+ 135762953U, // MOVDQUmr_Int
+ 2281706505U, // MOVDQUrm
+ 2281706505U, // MOVDQUrm_Int
+ 203461649U, // MOVHLPSrr
+ 135795738U, // MOVHPDmr
+ 603984922U, // MOVHPDrm
+ 135795746U, // MOVHPSmr
+ 603984930U, // MOVHPSrm
+ 203461674U, // MOVLHPSrr
+ 135795763U, // MOVLPDmr
+ 603984947U, // MOVLPDrm
+ 203461691U, // MOVLPDrr
+ 135795778U, // MOVLPSmr
+ 603984962U, // MOVLPSrm
+ 203461706U, // MOVLPSrr
+ 135369122U, // MOVLQ128mr
+ 203461691U, // MOVLSD2PDrr
+ 203461706U, // MOVLSS2PSrr
+ 1277203537U, // MOVMSKPDrr
+ 1277203547U, // MOVMSKPSrr
+ 2281706597U, // MOVNTDQArm
+ 135730287U, // MOVNTDQmr
+ 135337080U, // MOVNTImr
+ 135763072U, // MOVNTPDmr
+ 135763081U, // MOVNTPSmr
0U, // MOVPC32r
- 136253631U, // MOVPD2SDmr
- 1281364159U, // MOVPD2SDrr
- 135335430U, // MOVPDI2DImr
- 1281363462U, // MOVPDI2DIrr
- 135400998U, // MOVPQI2QImr
- 1281363462U, // MOVPQIto64rr
- 135925966U, // MOVPS2SSmr
- 1281364174U, // MOVPS2SSrr
- 1409289766U, // MOVQI2PQIrm
- 1946161343U, // MOVSD2PDrm
- 1281364159U, // MOVSD2PDrr
- 136253631U, // MOVSDmr
- 1946161343U, // MOVSDrm
- 1281364159U, // MOVSDrr
- 135400998U, // MOVSDto64mr
- 1281363462U, // MOVSDto64rr
- 1879052566U, // MOVSHDUPrm
- 1281364246U, // MOVSHDUPrr
- 1879052576U, // MOVSLDUPrm
- 1281364256U, // MOVSLDUPrr
- 135335430U, // MOVSS2DImr
- 1281363462U, // MOVSS2DIrr
- 2013270222U, // MOVSS2PSrm
- 1281364174U, // MOVSS2PSrr
- 135925966U, // MOVSSmr
- 2013270222U, // MOVSSrm
- 1281364174U, // MOVSSrr
+ 135795771U, // MOVPD2SDmr
+ 1277203515U, // MOVPD2SDrr
+ 135336322U, // MOVPDI2DImr
+ 1277202818U, // MOVPDI2DIrr
+ 135369122U, // MOVPQI2QImr
+ 1277202818U, // MOVPQIto64rr
+ 135599178U, // MOVPS2SSmr
+ 1277203530U, // MOVPS2SSrr
+ 1409290658U, // MOVQI2PQIrm
+ 1277202850U, // MOVQxrxr
+ 2013271099U, // MOVSD2PDrm
+ 1277203515U, // MOVSD2PDrr
+ 135795771U, // MOVSDmr
+ 2013271099U, // MOVSDrm
+ 1277203515U, // MOVSDrr
+ 135369122U, // MOVSDto64mr
+ 1277202818U, // MOVSDto64rr
+ 1946162322U, // MOVSHDUPrm
+ 1277203602U, // MOVSHDUPrr
+ 1946162332U, // MOVSLDUPrm
+ 1277203612U, // MOVSLDUPrr
+ 135336322U, // MOVSS2DImr
+ 1277202818U, // MOVSS2DIrr
+ 2080379978U, // MOVSS2PSrm
+ 1277203530U, // MOVSS2PSrr
+ 135599178U, // MOVSSmr
+ 2080379978U, // MOVSSrm
+ 1277203530U, // MOVSSrr
0U, // MOVSX16rm8
+ 1684018342U, // MOVSX16rm8W
0U, // MOVSX16rr8
- 1207963946U, // MOVSX32rm16
- 1684017458U, // MOVSX32rm8
- 1281364266U, // MOVSX32rr16
- 1281364274U, // MOVSX32rr8
- 1207963962U, // MOVSX64rm16
- 1342181698U, // MOVSX64rm32
- 1684017482U, // MOVSX64rm8
- 1281364282U, // MOVSX64rr16
- 1281364290U, // MOVSX64rr32
- 1281364298U, // MOVSX64rr8
- 136122706U, // MOVUPDmr
- 136122706U, // MOVUPDmr_Int
- 1879052626U, // MOVUPDrm
- 1879052626U, // MOVUPDrm_Int
- 1281364306U, // MOVUPDrr
- 136122714U, // MOVUPSmr
- 136122714U, // MOVUPSmr_Int
- 1879052634U, // MOVUPSrm
- 1879052634U, // MOVUPSrm_Int
- 1281364314U, // MOVUPSrr
- 1342180870U, // MOVZDI2PDIrm
- 1281363462U, // MOVZDI2PDIrr
- 2214596134U, // MOVZPQILo2PQIrm
- 1281363494U, // MOVZPQILo2PQIrr
- 1409289766U, // MOVZQI2PQIrm
- 1281363462U, // MOVZQI2PQIrr
- 1946161343U, // MOVZSD2PDrm
- 2013270222U, // MOVZSS2PSrm
+ 1277203622U, // MOVSX16rr8W
+ 1207964846U, // MOVSX32rm16
+ 1684018358U, // MOVSX32rm8
+ 1277203630U, // MOVSX32rr16
+ 1277203638U, // MOVSX32rr8
+ 1207964862U, // MOVSX64rm16
+ 1342182598U, // MOVSX64rm32
+ 1684018382U, // MOVSX64rm8
+ 1277203646U, // MOVSX64rr16
+ 1277203654U, // MOVSX64rr32
+ 1277203662U, // MOVSX64rr8
+ 135730390U, // MOVUPDmr
+ 135730390U, // MOVUPDmr_Int
+ 1946162390U, // MOVUPDrm
+ 1946162390U, // MOVUPDrm_Int
+ 1277203670U, // MOVUPDrr
+ 135730398U, // MOVUPSmr
+ 135730398U, // MOVUPSmr_Int
+ 1946162398U, // MOVUPSrm
+ 1946162398U, // MOVUPSrm_Int
+ 1277203678U, // MOVUPSrr
+ 1342181762U, // MOVZDI2PDIrm
+ 1277202818U, // MOVZDI2PDIrr
+ 2281705890U, // MOVZPQILo2PQIrm
+ 1277202850U, // MOVZPQILo2PQIrr
+ 1409290658U, // MOVZQI2PQIrm
+ 1277202818U, // MOVZQI2PQIrr
+ 2013271099U, // MOVZSD2PDrm
+ 2080379978U, // MOVZSS2PSrm
0U, // MOVZX16rm8
+ 1684018406U, // MOVZX16rm8W
0U, // MOVZX16rr8
- 1700794722U, // MOVZX32_NOREXrm8
- 1298141538U, // MOVZX32_NOREXrr8
- 1207964010U, // MOVZX32rm16
- 1684017506U, // MOVZX32rm8
- 1281364330U, // MOVZX32rr16
- 1281364322U, // MOVZX32rr8
+ 1277203686U, // MOVZX16rr8W
+ 1702892782U, // MOVZX32_NOREXrm8
+ 1277596910U, // MOVZX32_NOREXrr8
+ 1207964918U, // MOVZX32rm16
+ 1684018414U, // MOVZX32rm8
+ 1277203702U, // MOVZX32rr16
+ 1277203694U, // MOVZX32rr8
0U, // MOVZX64rm16
+ 1207964926U, // MOVZX64rm16_Q
0U, // MOVZX64rm32
0U, // MOVZX64rm8
+ 1684018438U, // MOVZX64rm8_Q
0U, // MOVZX64rr16
+ 1277203710U, // MOVZX64rr16_Q
0U, // MOVZX64rr32
0U, // MOVZX64rr8
+ 1277203718U, // MOVZX64rr8_Q
0U, // MOV_Fp3232
0U, // MOV_Fp3264
0U, // MOV_Fp3280
@@ -1286,34 +1454,34 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MOV_Fp8032
0U, // MOV_Fp8064
0U, // MOV_Fp8080
- 1013977458U, // MPSADBWrmi
- 1073746290U, // MPSADBWrri
- 872419707U, // MUL16m
- 73404795U, // MUL16r
- 945820033U, // MUL32m
- 73404801U, // MUL32r
- 1476399495U, // MUL64m
- 73404807U, // MUL64r
- 1610617229U, // MUL8m
- 73404813U, // MUL8r
- 536875411U, // MULPDrm
- 203428243U, // MULPDrr
- 536875418U, // MULPSrm
- 203428250U, // MULPSrr
- 603984289U, // MULSDrm
- 603984289U, // MULSDrm_Int
- 203428257U, // MULSDrr
- 203428257U, // MULSDrr_Int
- 671093160U, // MULSSrm
- 671093160U, // MULSSrm_Int
- 203428264U, // MULSSrr
- 203428264U, // MULSSrr_Int
- 738202031U, // MUL_F32m
- 805310902U, // MUL_F64m
- 872419773U, // MUL_FI16m
- 945820101U, // MUL_FI32m
- 73404877U, // MUL_FPrST0
- 73404884U, // MUL_FST0r
+ 1013978382U, // MPSADBWrmi
+ 1073747214U, // MPSADBWrri
+ 872420631U, // MUL16m
+ 73405719U, // MUL16r
+ 945820957U, // MUL32m
+ 73405725U, // MUL32r
+ 1476400419U, // MUL64m
+ 73405731U, // MUL64r
+ 1610618153U, // MUL8m
+ 73405737U, // MUL8r
+ 536876335U, // MULPDrm
+ 203461935U, // MULPDrr
+ 536876342U, // MULPSrm
+ 203461942U, // MULPSrr
+ 603985213U, // MULSDrm
+ 603985213U, // MULSDrm_Int
+ 203461949U, // MULSDrr
+ 203461949U, // MULSDrr_Int
+ 671094084U, // MULSSrm
+ 671094084U, // MULSSrm_Int
+ 203461956U, // MULSSrr
+ 203461956U, // MULSSrr_Int
+ 738202955U, // MUL_F32m
+ 805311826U, // MUL_F64m
+ 872420697U, // MUL_FI16m
+ 945821025U, // MUL_FI32m
+ 73405801U, // MUL_FPrST0
+ 73405808U, // MUL_FST0r
0U, // MUL_Fp32
0U, // MUL_Fp32m
0U, // MUL_Fp64
@@ -1328,735 +1496,785 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MUL_FpI32m32
0U, // MUL_FpI32m64
0U, // MUL_FpI32m80
- 73404890U, // MUL_FrST0
- 4584U, // MWAIT
- 872419822U, // NEG16m
- 73404910U, // NEG16r
- 945820148U, // NEG32m
- 73404916U, // NEG32r
- 1476399610U, // NEG64m
- 73404922U, // NEG64r
- 1610617344U, // NEG8m
- 73404928U, // NEG8r
- 4614U, // NOOP
- 945820170U, // NOOPL
- 872419856U, // NOT16m
- 73404944U, // NOT16r
- 945820182U, // NOT32m
- 73404950U, // NOT32r
- 1476399644U, // NOT64m
- 73404956U, // NOT64r
- 1610617378U, // NOT8m
- 73404962U, // NOT8r
- 67113512U, // OR16i16
- 135270952U, // OR16mi
- 135270952U, // OR16mi8
- 135270952U, // OR16mr
- 203428392U, // OR16ri
- 203428392U, // OR16ri8
- 270537256U, // OR16rm
- 203428392U, // OR16rr
- 70259245U, // OR32i32
- 135336493U, // OR32mi
- 135336493U, // OR32mi8
- 135336493U, // OR32mr
- 203428397U, // OR32ri
- 203428397U, // OR32ri8
- 337646125U, // OR32rm
- 203428397U, // OR32rr
- 71307826U, // OR64i32
- 135402034U, // OR64mi32
- 135402034U, // OR64mi8
- 135402034U, // OR64mr
- 203428402U, // OR64ri32
- 203428402U, // OR64ri8
- 404754994U, // OR64rm
- 203428402U, // OR64rr
- 72356407U, // OR8i8
- 135467575U, // OR8mi
- 135467575U, // OR8mr
- 203428407U, // OR8ri
- 471863863U, // OR8rm
- 203428407U, // OR8rr
- 536873350U, // ORPDrm
- 203426182U, // ORPDrr
- 536873356U, // ORPSrm
- 203426188U, // ORPSrr
- 73404988U, // OUT16ir
- 4679U, // OUT16rr
- 73405013U, // OUT32ir
- 4705U, // OUT32rr
- 73405040U, // OUT8ir
- 4731U, // OUT8rr
- 2214597257U, // PABSBrm128
- 1409290889U, // PABSBrm64
- 1281364617U, // PABSBrr128
- 1281364617U, // PABSBrr64
- 2214597264U, // PABSDrm128
- 1409290896U, // PABSDrm64
- 1281364624U, // PABSDrr128
- 1281364624U, // PABSDrr64
- 2214597271U, // PABSWrm128
- 1409290903U, // PABSWrm64
- 1281364631U, // PABSWrr128
- 1281364631U, // PABSWrr64
- 1140854316U, // PACKSSDWrm
- 203427372U, // PACKSSDWrr
- 1140854326U, // PACKSSWBrm
- 203427382U, // PACKSSWBrr
- 1140855454U, // PACKUSDWrm
- 203428510U, // PACKUSDWrr
- 1140854336U, // PACKUSWBrm
- 203427392U, // PACKUSWBrr
- 1140854346U, // PADDBrm
- 203427402U, // PADDBrr
- 1140854353U, // PADDDrm
- 203427409U, // PADDDrr
- 1140854360U, // PADDQrm
- 203427416U, // PADDQrr
- 1140854367U, // PADDSBrm
- 203427423U, // PADDSBrr
- 1140854375U, // PADDSWrm
- 203427431U, // PADDSWrr
- 1140854383U, // PADDUSBrm
- 203427439U, // PADDUSBrr
- 1140854392U, // PADDUSWrm
- 203427448U, // PADDUSWrr
- 1140854401U, // PADDWrm
- 203427457U, // PADDWrr
- 1013977768U, // PALIGNR128rm
- 1073746600U, // PALIGNR128rr
- 1030754984U, // PALIGNR64rm
- 1073746600U, // PALIGNR64rr
- 1140854408U, // PANDNrm
- 203427464U, // PANDNrr
- 1140854415U, // PANDrm
- 203427471U, // PANDrr
- 1140854421U, // PAVGBrm
- 203427477U, // PAVGBrr
- 1140854428U, // PAVGWrm
- 203427484U, // PAVGWrr
- 1140855473U, // PBLENDVBrm0
- 203428529U, // PBLENDVBrr0
- 1013977794U, // PBLENDWrmi
- 1073746626U, // PBLENDWrri
- 1140854435U, // PCMPEQBrm
- 203427491U, // PCMPEQBrr
- 1140854444U, // PCMPEQDrm
- 203427500U, // PCMPEQDrr
- 1140855499U, // PCMPEQQrm
- 203428555U, // PCMPEQQrr
- 1140854453U, // PCMPEQWrm
- 203427509U, // PCMPEQWrr
- 2105545428U, // PCMPESTRIArm
- 215683796U, // PCMPESTRIArr
- 2105545428U, // PCMPESTRICrm
- 215683796U, // PCMPESTRICrr
- 2105545428U, // PCMPESTRIOrm
- 215683796U, // PCMPESTRIOrr
- 2105545428U, // PCMPESTRISrm
- 215683796U, // PCMPESTRISrr
- 2105545428U, // PCMPESTRIZrm
- 215683796U, // PCMPESTRIZrr
- 2105545428U, // PCMPESTRIrm
- 215683796U, // PCMPESTRIrr
- 4831U, // PCMPESTRM128MEM
- 4855U, // PCMPESTRM128REG
- 2105545487U, // PCMPESTRM128rm
- 215683855U, // PCMPESTRM128rr
- 1140854462U, // PCMPGTBrm
- 203427518U, // PCMPGTBrr
- 1140854471U, // PCMPGTDrm
- 203427527U, // PCMPGTDrr
- 1140855578U, // PCMPGTQrm
- 203428634U, // PCMPGTQrr
- 1140854480U, // PCMPGTWrm
- 203427536U, // PCMPGTWrr
- 2105545507U, // PCMPISTRIArm
- 215683875U, // PCMPISTRIArr
- 2105545507U, // PCMPISTRICrm
- 215683875U, // PCMPISTRICrr
- 2105545507U, // PCMPISTRIOrm
- 215683875U, // PCMPISTRIOrr
- 2105545507U, // PCMPISTRISrm
- 215683875U, // PCMPISTRISrr
- 2105545507U, // PCMPISTRIZrm
- 215683875U, // PCMPISTRIZrr
- 2105545507U, // PCMPISTRIrm
- 215683875U, // PCMPISTRIrr
- 4910U, // PCMPISTRM128MEM
- 4934U, // PCMPISTRM128REG
- 2105545566U, // PCMPISTRM128rm
- 215683934U, // PCMPISTRM128rr
- 2095256425U, // PEXTRBmr
- 215683945U, // PEXTRBrr
- 2095125361U, // PEXTRDmr
- 215683953U, // PEXTRDrr
- 2095190905U, // PEXTRQmr
- 215683961U, // PEXTRQrr
- 2095058649U, // PEXTRWmr
- 215682777U, // PEXTRWri
- 1140855681U, // PHADDDrm128
- 404755329U, // PHADDDrm64
- 203428737U, // PHADDDrr128
- 203428737U, // PHADDDrr64
- 1140855689U, // PHADDSWrm128
- 404755337U, // PHADDSWrm64
- 203428745U, // PHADDSWrr128
- 203428745U, // PHADDSWrr64
- 1140855698U, // PHADDWrm128
- 404755346U, // PHADDWrm64
- 203428754U, // PHADDWrr128
- 203428754U, // PHADDWrr64
- 2214597530U, // PHMINPOSUWrm128
- 1281364890U, // PHMINPOSUWrr128
- 1140855718U, // PHSUBDrm128
- 404755366U, // PHSUBDrm64
- 203428774U, // PHSUBDrr128
- 203428774U, // PHSUBDrr64
- 1140855726U, // PHSUBSWrm128
- 404755374U, // PHSUBSWrm64
- 203428782U, // PHSUBSWrr128
- 203428782U, // PHSUBSWrr64
- 1140855735U, // PHSUBWrm128
- 404755383U, // PHSUBWrm64
- 203428791U, // PHSUBWrr128
- 203428791U, // PHSUBWrr64
- 1032852415U, // PINSRBrm
- 1073746879U, // PINSRBrr
- 1033900999U, // PINSRDrm
- 1073746887U, // PINSRDrr
- 1030755279U, // PINSRQrm
- 1073746895U, // PINSRQrr
- 1028656865U, // PINSRWrmi
- 1073745633U, // PINSRWrri
- 1140855767U, // PMADDUBSWrm128
- 404755415U, // PMADDUBSWrm64
- 203428823U, // PMADDUBSWrr128
- 203428823U, // PMADDUBSWrr64
- 1140854505U, // PMADDWDrm
- 203427561U, // PMADDWDrr
- 1140855778U, // PMAXSBrm
- 203428834U, // PMAXSBrr
- 1140855786U, // PMAXSDrm
- 203428842U, // PMAXSDrr
- 1140854514U, // PMAXSWrm
- 203427570U, // PMAXSWrr
- 1140854522U, // PMAXUBrm
- 203427578U, // PMAXUBrr
- 1140855794U, // PMAXUDrm
- 203428850U, // PMAXUDrr
- 1140855802U, // PMAXUWrm
- 203428858U, // PMAXUWrr
- 1140855810U, // PMINSBrm
- 203428866U, // PMINSBrr
- 1140855818U, // PMINSDrm
- 203428874U, // PMINSDrr
- 1140854530U, // PMINSWrm
- 203427586U, // PMINSWrr
- 1140854538U, // PMINUBrm
- 203427594U, // PMINUBrr
- 1140855826U, // PMINUDrm
- 203428882U, // PMINUDrr
- 1140855834U, // PMINUWrm
- 203428890U, // PMINUWrr
- 1281363730U, // PMOVMSKBrr
- 1342182434U, // PMOVSXBDrm
- 1281365026U, // PMOVSXBDrr
- 1207964716U, // PMOVSXBQrm
- 1281365036U, // PMOVSXBQrr
- 1409291318U, // PMOVSXBWrm
- 1281365046U, // PMOVSXBWrr
- 1409291328U, // PMOVSXDQrm
- 1281365056U, // PMOVSXDQrr
- 1409291338U, // PMOVSXWDrm
- 1281365066U, // PMOVSXWDrr
- 1342182484U, // PMOVSXWQrm
- 1281365076U, // PMOVSXWQrr
- 1342182494U, // PMOVZXBDrm
- 1281365086U, // PMOVZXBDrr
- 1207964776U, // PMOVZXBQrm
- 1281365096U, // PMOVZXBQrr
- 1409291378U, // PMOVZXBWrm
- 1281365106U, // PMOVZXBWrr
- 1409291388U, // PMOVZXDQrm
- 1281365116U, // PMOVZXDQrr
- 1409291398U, // PMOVZXWDrm
- 1281365126U, // PMOVZXWDrr
- 1342182544U, // PMOVZXWQrm
- 1281365136U, // PMOVZXWQrr
- 1140855962U, // PMULDQrm
- 203429018U, // PMULDQrr
- 1140855970U, // PMULHRSWrm128
- 404755618U, // PMULHRSWrm64
- 203429026U, // PMULHRSWrr128
- 203429026U, // PMULHRSWrr64
- 1140854556U, // PMULHUWrm
- 203427612U, // PMULHUWrr
- 1140854565U, // PMULHWrm
- 203427621U, // PMULHWrr
- 1140855980U, // PMULLDrm
- 1140855980U, // PMULLDrm_int
- 203429036U, // PMULLDrr
- 203429036U, // PMULLDrr_int
- 1140854573U, // PMULLWrm
- 203427629U, // PMULLWrr
- 1140854581U, // PMULUDQrm
- 203427637U, // PMULUDQrr
- 73405620U, // POP16r
- 872420532U, // POP16rmm
- 73405620U, // POP16rmr
- 73405626U, // POP32r
- 945820858U, // POP32rmm
- 73405626U, // POP32rmr
- 73405632U, // POP64r
- 1476400320U, // POP64rmm
- 73405632U, // POP64rmr
- 5318U, // POPFD
- 5318U, // POPFQ
- 1140854590U, // PORrm
- 203427646U, // PORrr
- 1610618059U, // PREFETCHNTA
- 1610618072U, // PREFETCHT0
- 1610618084U, // PREFETCHT1
- 1610618096U, // PREFETCHT2
- 1140854595U, // PSADBWrm
- 203427651U, // PSADBWrr
- 1140856060U, // PSHUFBrm128
- 404755708U, // PSHUFBrm64
- 203429116U, // PSHUFBrr128
- 203429116U, // PSHUFBrr64
- 2105545988U, // PSHUFDmi
- 215684356U, // PSHUFDri
- 2105545996U, // PSHUFHWmi
- 215684364U, // PSHUFHWri
- 2105546005U, // PSHUFLWmi
- 215684373U, // PSHUFLWri
- 1140856094U, // PSIGNBrm128
- 404755742U, // PSIGNBrm64
- 203429150U, // PSIGNBrr128
- 203429150U, // PSIGNBrr64
- 1140856102U, // PSIGNDrm128
- 404755750U, // PSIGNDrm64
- 203429158U, // PSIGNDrr128
- 203429158U, // PSIGNDrr64
- 1140856110U, // PSIGNWrm128
- 404755758U, // PSIGNWrm64
- 203429166U, // PSIGNWrr128
- 203429166U, // PSIGNWrr64
- 203429174U, // PSLLDQri
- 203427667U, // PSLLDri
- 1140854611U, // PSLLDrm
- 203427667U, // PSLLDrr
- 203427674U, // PSLLQri
- 1140854618U, // PSLLQrm
- 203427674U, // PSLLQrr
- 203427681U, // PSLLWri
- 1140854625U, // PSLLWrm
- 203427681U, // PSLLWrr
- 203427688U, // PSRADri
- 1140854632U, // PSRADrm
- 203427688U, // PSRADrr
- 203427695U, // PSRAWri
- 1140854639U, // PSRAWrm
- 203427695U, // PSRAWrr
- 203429182U, // PSRLDQri
- 203427702U, // PSRLDri
- 1140854646U, // PSRLDrm
- 203427702U, // PSRLDrr
- 203427709U, // PSRLQri
- 1140854653U, // PSRLQrm
- 203427709U, // PSRLQrr
- 203427716U, // PSRLWri
- 1140854660U, // PSRLWrm
- 203427716U, // PSRLWrr
- 1140854667U, // PSUBBrm
- 203427723U, // PSUBBrr
- 1140854674U, // PSUBDrm
- 203427730U, // PSUBDrr
- 1140854681U, // PSUBQrm
- 203427737U, // PSUBQrr
- 1140854688U, // PSUBSBrm
- 203427744U, // PSUBSBrr
- 1140854696U, // PSUBSWrm
- 203427752U, // PSUBSWrr
- 1140854704U, // PSUBUSBrm
- 203427760U, // PSUBUSBrr
- 1140854713U, // PSUBUSWrm
- 203427769U, // PSUBUSWrr
- 1140854722U, // PSUBWrm
- 203427778U, // PSUBWrr
- 2214597958U, // PTESTrm
- 1281365318U, // PTESTrr
- 1140854729U, // PUNPCKHBWrm
- 203427785U, // PUNPCKHBWrr
- 1140854740U, // PUNPCKHDQrm
- 203427796U, // PUNPCKHDQrr
- 1140856142U, // PUNPCKHQDQrm
- 203429198U, // PUNPCKHQDQrr
- 1140854751U, // PUNPCKHWDrm
- 203427807U, // PUNPCKHWDrr
- 1140854762U, // PUNPCKLBWrm
- 203427818U, // PUNPCKLBWrr
- 1140854773U, // PUNPCKLDQrm
- 203427829U, // PUNPCKLDQrr
- 1140856154U, // PUNPCKLQDQrm
- 203429210U, // PUNPCKLQDQrr
- 1140854784U, // PUNPCKLWDrm
- 203427840U, // PUNPCKLWDrr
- 73405798U, // PUSH16r
- 872420710U, // PUSH16rmm
- 73405798U, // PUSH16rmr
- 73405805U, // PUSH32i16
- 73405805U, // PUSH32i32
- 73405805U, // PUSH32i8
- 73405805U, // PUSH32r
- 945821037U, // PUSH32rmm
- 73405805U, // PUSH32rmr
- 73405812U, // PUSH64i16
- 73405812U, // PUSH64i32
- 73405812U, // PUSH64i8
- 73405812U, // PUSH64r
- 1476400500U, // PUSH64rmm
- 73405812U, // PUSH64rmr
- 5499U, // PUSHFD
- 5499U, // PUSHFQ
- 1140853104U, // PXORrm
- 203426160U, // PXORrr
- 872420737U, // RCL16m1
- 872420746U, // RCL16mCL
- 2578453909U, // RCL16mi
- 73405825U, // RCL16r1
- 73405834U, // RCL16rCL
- 203429269U, // RCL16ri
- 945821083U, // RCL32m1
- 945821092U, // RCL32mCL
- 2579502511U, // RCL32mi
- 73405851U, // RCL32r1
- 73405860U, // RCL32rCL
- 203429295U, // RCL32ri
- 1476400565U, // RCL64m1
- 1476400574U, // RCL64mCL
- 2580551113U, // RCL64mi
- 73405877U, // RCL64r1
- 73405886U, // RCL64rCL
- 203429321U, // RCL64ri
- 1610618319U, // RCL8m1
- 1610618328U, // RCL8mCL
- 2581599715U, // RCL8mi
- 73405903U, // RCL8r1
- 73405912U, // RCL8rCL
- 203429347U, // RCL8ri
- 1879053801U, // RCPPSm
- 1879053801U, // RCPPSm_Int
- 1281365481U, // RCPPSr
- 1281365481U, // RCPPSr_Int
- 2013271536U, // RCPSSm
- 2013271536U, // RCPSSm_Int
- 1281365488U, // RCPSSr
- 1281365488U, // RCPSSr_Int
- 872420855U, // RCR16m1
- 872420864U, // RCR16mCL
- 2578454027U, // RCR16mi
- 73405943U, // RCR16r1
- 73405952U, // RCR16rCL
- 203429387U, // RCR16ri
- 945821201U, // RCR32m1
- 945821210U, // RCR32mCL
- 2579502629U, // RCR32mi
- 73405969U, // RCR32r1
- 73405978U, // RCR32rCL
- 203429413U, // RCR32ri
- 1476400683U, // RCR64m1
- 1476400692U, // RCR64mCL
- 2580551231U, // RCR64mi
- 73405995U, // RCR64r1
- 73406004U, // RCR64rCL
- 203429439U, // RCR64ri
- 1610618437U, // RCR8m1
- 1610618446U, // RCR8mCL
- 2581599833U, // RCR8mi
- 73406021U, // RCR8r1
- 73406030U, // RCR8rCL
- 203429465U, // RCR8ri
- 5727U, // RDTSC
- 5733U, // REP_MOVSB
- 5743U, // REP_MOVSD
- 5753U, // REP_MOVSQ
- 5763U, // REP_MOVSW
- 5773U, // REP_STOSB
- 5783U, // REP_STOSD
- 5793U, // REP_STOSQ
- 5803U, // REP_STOSW
- 5813U, // RET
- 73406137U, // RETI
- 872421054U, // ROL16m1
- 872421060U, // ROL16mCL
- 135272126U, // ROL16mi
- 73406142U, // ROL16r1
- 73406148U, // ROL16rCL
- 203429566U, // ROL16ri
- 945821391U, // ROL32m1
- 945821397U, // ROL32mCL
- 135337679U, // ROL32mi
- 73406159U, // ROL32r1
- 73406165U, // ROL32rCL
- 203429583U, // ROL32ri
- 1476400864U, // ROL64m1
- 1476400870U, // ROL64mCL
- 135403232U, // ROL64mi
- 73406176U, // ROL64r1
- 73406182U, // ROL64rCL
- 203429600U, // ROL64ri
- 1610618609U, // ROL8m1
- 1610618615U, // ROL8mCL
- 135468785U, // ROL8mi
- 73406193U, // ROL8r1
- 73406199U, // ROL8rCL
- 203429617U, // ROL8ri
- 872421122U, // ROR16m1
- 872421128U, // ROR16mCL
- 135272194U, // ROR16mi
- 73406210U, // ROR16r1
- 73406216U, // ROR16rCL
- 203429634U, // ROR16ri
- 945821459U, // ROR32m1
- 945821465U, // ROR32mCL
- 135337747U, // ROR32mi
- 73406227U, // ROR32r1
- 73406233U, // ROR32rCL
- 203429651U, // ROR32ri
- 1476400932U, // ROR64m1
- 1476400938U, // ROR64mCL
- 135403300U, // ROR64mi
- 73406244U, // ROR64r1
- 73406250U, // ROR64rCL
- 203429668U, // ROR64ri
- 1610618677U, // ROR8m1
- 1610618683U, // ROR8mCL
- 135468853U, // ROR8mi
- 73406261U, // ROR8r1
- 73406267U, // ROR8rCL
- 203429685U, // ROR8ri
- 2112886598U, // ROUNDPDm_Int
- 215684934U, // ROUNDPDr_Int
- 2112886607U, // ROUNDPSm_Int
- 215684943U, // ROUNDPSr_Int
- 1040193368U, // ROUNDSDm_Int
- 1073747800U, // ROUNDSDr_Int
- 1025513313U, // ROUNDSSm_Int
- 1073747809U, // ROUNDSSr_Int
- 1879054186U, // RSQRTPSm
- 1879054186U, // RSQRTPSm_Int
- 1281365866U, // RSQRTPSr
- 1281365866U, // RSQRTPSr_Int
- 2013271923U, // RSQRTSSm
- 2013271923U, // RSQRTSSm_Int
- 1281365875U, // RSQRTSSr
- 1281365875U, // RSQRTSSr_Int
- 6012U, // SAHF
- 872421249U, // SAR16m1
- 872421255U, // SAR16mCL
- 135272321U, // SAR16mi
- 73406337U, // SAR16r1
- 73406343U, // SAR16rCL
- 203429761U, // SAR16ri
- 945821586U, // SAR32m1
- 945821592U, // SAR32mCL
- 135337874U, // SAR32mi
- 73406354U, // SAR32r1
- 73406360U, // SAR32rCL
- 203429778U, // SAR32ri
- 1476401059U, // SAR64m1
- 1476401065U, // SAR64mCL
- 135403427U, // SAR64mi
- 73406371U, // SAR64r1
- 73406377U, // SAR64rCL
- 203429795U, // SAR64ri
- 1610618804U, // SAR8m1
- 1610618810U, // SAR8mCL
- 135468980U, // SAR8mi
- 73406388U, // SAR8r1
- 73406394U, // SAR8rCL
- 203429812U, // SAR8ri
- 67114949U, // SBB16i16
- 135272389U, // SBB16mi
- 135272389U, // SBB16mi8
- 135272389U, // SBB16mr
- 203429829U, // SBB16ri
- 203429829U, // SBB16ri8
- 270538693U, // SBB16rm
- 203429829U, // SBB16rr
- 70260683U, // SBB32i32
- 135337931U, // SBB32mi
- 135337931U, // SBB32mi8
- 135337931U, // SBB32mr
- 203429835U, // SBB32ri
- 203429835U, // SBB32ri8
- 337647563U, // SBB32rm
- 203429835U, // SBB32rr
- 71309265U, // SBB64i32
- 135403473U, // SBB64mi32
- 135403473U, // SBB64mi8
- 135403473U, // SBB64mr
- 203429841U, // SBB64ri32
- 203429841U, // SBB64ri8
- 404756433U, // SBB64rm
- 203429841U, // SBB64rr
- 72357847U, // SBB8i8
- 135469015U, // SBB8mi
- 135469015U, // SBB8mr
- 203429847U, // SBB8ri
- 471865303U, // SBB8rm
- 203429847U, // SBB8rr
- 6109U, // SCAS16
- 6115U, // SCAS32
- 6121U, // SCAS64
- 6127U, // SCAS8
- 1610618869U, // SETAEm
- 73406453U, // SETAEr
- 1610618876U, // SETAm
- 73406460U, // SETAr
- 1610618882U, // SETBEm
- 73406466U, // SETBEr
- 68949957U, // SETB_C16r
- 68949963U, // SETB_C32r
- 68949969U, // SETB_C64r
- 68949975U, // SETB_C8r
- 1610618889U, // SETBm
- 73406473U, // SETBr
- 1610618895U, // SETEm
- 73406479U, // SETEr
- 1610618901U, // SETGEm
- 73406485U, // SETGEr
- 1610618908U, // SETGm
- 73406492U, // SETGr
- 1610618914U, // SETLEm
- 73406498U, // SETLEr
- 1610618921U, // SETLm
- 73406505U, // SETLr
- 1610618927U, // SETNEm
- 73406511U, // SETNEr
- 1610618934U, // SETNOm
- 73406518U, // SETNOr
- 1610618941U, // SETNPm
- 73406525U, // SETNPr
- 1610618948U, // SETNSm
- 73406532U, // SETNSr
- 1610618955U, // SETOm
- 73406539U, // SETOr
- 1610618961U, // SETPm
- 73406545U, // SETPr
- 1610618967U, // SETSm
- 73406551U, // SETSr
- 6237U, // SFENCE
- 872421476U, // SHL16m1
- 872421482U, // SHL16mCL
- 135272548U, // SHL16mi
- 73406564U, // SHL16r1
- 73406570U, // SHL16rCL
- 203429988U, // SHL16ri
- 945821813U, // SHL32m1
- 945821819U, // SHL32mCL
- 135338101U, // SHL32mi
- 73406581U, // SHL32r1
- 73406587U, // SHL32rCL
- 203430005U, // SHL32ri
- 1476401286U, // SHL64m1
- 1476401292U, // SHL64mCL
- 135403654U, // SHL64mi
- 73406615U, // SHL64r1
- 73406604U, // SHL64rCL
- 203430022U, // SHL64ri
- 1610619037U, // SHL8m1
- 1610619043U, // SHL8mCL
- 135469213U, // SHL8mi
- 73406621U, // SHL8r1
- 73406627U, // SHL8rCL
- 203430045U, // SHL8ri
- 135272622U, // SHLD16mrCL
- 2095061178U, // SHLD16mri8
- 203430062U, // SHLD16rrCL
- 1073748154U, // SHLD16rri8
- 135338177U, // SHLD32mrCL
- 2095126733U, // SHLD32mri8
- 203430081U, // SHLD32rrCL
- 1073748173U, // SHLD32rri8
- 135403732U, // SHLD64mrCL
- 2095192288U, // SHLD64mri8
- 203430100U, // SHLD64rrCL
- 1073748192U, // SHLD64rri8
- 872421607U, // SHR16m1
- 872421613U, // SHR16mCL
- 135272679U, // SHR16mi
- 73406695U, // SHR16r1
- 73406701U, // SHR16rCL
- 203430119U, // SHR16ri
- 945821944U, // SHR32m1
- 945821950U, // SHR32mCL
- 135338232U, // SHR32mi
- 73406712U, // SHR32r1
- 73406718U, // SHR32rCL
- 203430136U, // SHR32ri
- 1476401303U, // SHR64m1
- 1476401417U, // SHR64mCL
- 135403671U, // SHR64mi
- 73406615U, // SHR64r1
- 73406729U, // SHR64rCL
- 203430039U, // SHR64ri
- 1610619156U, // SHR8m1
- 1610619162U, // SHR8mCL
- 135469332U, // SHR8mi
- 73406740U, // SHR8r1
- 73406746U, // SHR8rCL
- 203430164U, // SHR8ri
- 135272741U, // SHRD16mrCL
- 2095061297U, // SHRD16mri8
- 203430181U, // SHRD16rrCL
- 1073748273U, // SHRD16rri8
- 135338296U, // SHRD32mrCL
- 2095126852U, // SHRD32mri8
- 203430200U, // SHRD32rrCL
- 1073748292U, // SHRD32rri8
- 135403851U, // SHRD64mrCL
- 2095192407U, // SHRD64mri8
- 203430219U, // SHRD64rrCL
- 1073748311U, // SHRD64rri8
- 1041242462U, // SHUFPDrmi
- 1073748318U, // SHUFPDrri
- 1041242470U, // SHUFPSrmi
- 1073748326U, // SHUFPSrri
- 6510U, // SIN_F
+ 73405814U, // MUL_FrST0
+ 5508U, // MWAIT
+ 872420746U, // NEG16m
+ 73405834U, // NEG16r
+ 945821072U, // NEG32m
+ 73405840U, // NEG32r
+ 1476400534U, // NEG64m
+ 73405846U, // NEG64r
+ 1610618268U, // NEG8m
+ 73405852U, // NEG8r
+ 5538U, // NOOP
+ 945821094U, // NOOPL
+ 872420780U, // NOOPW
+ 872420786U, // NOT16m
+ 73405874U, // NOT16r
+ 945821112U, // NOT32m
+ 73405880U, // NOT32r
+ 1476400574U, // NOT64m
+ 73405886U, // NOT64r
+ 1610618308U, // NOT8m
+ 73405892U, // NOT8r
+ 67114442U, // OR16i16
+ 135271882U, // OR16mi
+ 135271882U, // OR16mi8
+ 135271882U, // OR16mr
+ 203462090U, // OR16ri
+ 203462090U, // OR16ri8
+ 270570954U, // OR16rm
+ 203462090U, // OR16rr
+ 203462090U, // OR16rr_REV
+ 70260175U, // OR32i32
+ 135337423U, // OR32mi
+ 135337423U, // OR32mi8
+ 135337423U, // OR32mr
+ 203462095U, // OR32ri
+ 203462095U, // OR32ri8
+ 337679823U, // OR32rm
+ 203462095U, // OR32rr
+ 203462095U, // OR32rr_REV
+ 71308756U, // OR64i32
+ 135370196U, // OR64mi32
+ 135370196U, // OR64mi8
+ 135370196U, // OR64mr
+ 203462100U, // OR64ri32
+ 203462100U, // OR64ri8
+ 404788692U, // OR64rm
+ 203462100U, // OR64rr
+ 203462100U, // OR64rr_REV
+ 72357337U, // OR8i8
+ 135402969U, // OR8mi
+ 135402969U, // OR8mr
+ 203462105U, // OR8ri
+ 471897561U, // OR8rm
+ 203462105U, // OR8rr
+ 203462105U, // OR8rr_REV
+ 536874105U, // ORPDrm
+ 203459705U, // ORPDrr
+ 536874111U, // ORPSrm
+ 203459711U, // ORPSrr
+ 73405918U, // OUT16ir
+ 5609U, // OUT16rr
+ 73405943U, // OUT32ir
+ 5635U, // OUT32rr
+ 73405970U, // OUT8ir
+ 5661U, // OUT8rr
+ 5675U, // OUTSB
+ 5681U, // OUTSD
+ 5687U, // OUTSW
+ 2281707069U, // PABSBrm128
+ 1409291837U, // PABSBrm64
+ 1277204029U, // PABSBrr128
+ 1277204029U, // PABSBrr64
+ 2281707076U, // PABSDrm128
+ 1409291844U, // PABSDrm64
+ 1277204036U, // PABSDrr128
+ 1277204036U, // PABSDrr64
+ 2281707083U, // PABSWrm128
+ 1409291851U, // PABSWrm64
+ 1277204043U, // PABSWrr128
+ 1277204043U, // PABSWrr64
+ 1140855208U, // PACKSSDWrm
+ 203461032U, // PACKSSDWrr
+ 1140855218U, // PACKSSWBrm
+ 203461042U, // PACKSSWBrr
+ 1140856402U, // PACKUSDWrm
+ 203462226U, // PACKUSDWrr
+ 1140855228U, // PACKUSWBrm
+ 203461052U, // PACKUSWBrr
+ 1140855238U, // PADDBrm
+ 203461062U, // PADDBrr
+ 1140855245U, // PADDDrm
+ 203461069U, // PADDDrr
+ 1140855252U, // PADDQrm
+ 203461076U, // PADDQrr
+ 1140855259U, // PADDSBrm
+ 203461083U, // PADDSBrr
+ 1140855267U, // PADDSWrm
+ 203461091U, // PADDSWrr
+ 1140855275U, // PADDUSBrm
+ 203461099U, // PADDUSBrr
+ 1140855284U, // PADDUSWrm
+ 203461108U, // PADDUSWrr
+ 1140855293U, // PADDWrm
+ 203461117U, // PADDWrr
+ 1013978716U, // PALIGNR128rm
+ 1073747548U, // PALIGNR128rr
+ 1030067804U, // PALIGNR64rm
+ 1073747548U, // PALIGNR64rr
+ 1140855300U, // PANDNrm
+ 203461124U, // PANDNrr
+ 1140855307U, // PANDrm
+ 203461131U, // PANDrr
+ 1140855313U, // PAVGBrm
+ 203461137U, // PAVGBrr
+ 1140855320U, // PAVGWrm
+ 203461144U, // PAVGWrr
+ 1140856421U, // PBLENDVBrm0
+ 203462245U, // PBLENDVBrr0
+ 1013978742U, // PBLENDWrmi
+ 1073747574U, // PBLENDWrri
+ 1140855327U, // PCMPEQBrm
+ 203461151U, // PCMPEQBrr
+ 1140855336U, // PCMPEQDrm
+ 203461160U, // PCMPEQDrr
+ 1140856447U, // PCMPEQQrm
+ 203462271U, // PCMPEQQrr
+ 1140855345U, // PCMPEQWrm
+ 203461169U, // PCMPEQWrr
+ 2173703816U, // PCMPESTRIArm
+ 215324296U, // PCMPESTRIArr
+ 2173703816U, // PCMPESTRICrm
+ 215324296U, // PCMPESTRICrr
+ 2173703816U, // PCMPESTRIOrm
+ 215324296U, // PCMPESTRIOrr
+ 2173703816U, // PCMPESTRISrm
+ 215324296U, // PCMPESTRISrr
+ 2173703816U, // PCMPESTRIZrm
+ 215324296U, // PCMPESTRIZrr
+ 2173703816U, // PCMPESTRIrm
+ 215324296U, // PCMPESTRIrr
+ 5779U, // PCMPESTRM128MEM
+ 5803U, // PCMPESTRM128REG
+ 2173703875U, // PCMPESTRM128rm
+ 215324355U, // PCMPESTRM128rr
+ 1140855354U, // PCMPGTBrm
+ 203461178U, // PCMPGTBrr
+ 1140855363U, // PCMPGTDrm
+ 203461187U, // PCMPGTDrr
+ 1140856526U, // PCMPGTQrm
+ 203462350U, // PCMPGTQrr
+ 1140855372U, // PCMPGTWrm
+ 203461196U, // PCMPGTWrr
+ 2173703895U, // PCMPISTRIArm
+ 215324375U, // PCMPISTRIArr
+ 2173703895U, // PCMPISTRICrm
+ 215324375U, // PCMPISTRICrr
+ 2173703895U, // PCMPISTRIOrm
+ 215324375U, // PCMPISTRIOrr
+ 2173703895U, // PCMPISTRISrm
+ 215324375U, // PCMPISTRISrr
+ 2173703895U, // PCMPISTRIZrm
+ 215324375U, // PCMPISTRIZrr
+ 2173703895U, // PCMPISTRIrm
+ 215324375U, // PCMPISTRIrr
+ 5858U, // PCMPISTRM128MEM
+ 5882U, // PCMPISTRM128REG
+ 2173703954U, // PCMPISTRM128rm
+ 215324434U, // PCMPISTRM128rr
+ 2162300701U, // PEXTRBmr
+ 215324445U, // PEXTRBrr
+ 2162235173U, // PEXTRDmr
+ 215324453U, // PEXTRDrr
+ 2162267949U, // PEXTRQmr
+ 215324461U, // PEXTRQrr
+ 2162168405U, // PEXTRWmr
+ 215323221U, // PEXTRWri
+ 1140856629U, // PHADDDrm128
+ 404789045U, // PHADDDrm64
+ 203462453U, // PHADDDrr128
+ 203462453U, // PHADDDrr64
+ 1140856637U, // PHADDSWrm128
+ 404789053U, // PHADDSWrm64
+ 203462461U, // PHADDSWrr128
+ 203462461U, // PHADDSWrr64
+ 1140856646U, // PHADDWrm128
+ 404789062U, // PHADDWrm64
+ 203462470U, // PHADDWrr128
+ 203462470U, // PHADDWrr64
+ 2281707342U, // PHMINPOSUWrm128
+ 1277204302U, // PHMINPOSUWrr128
+ 1140856666U, // PHSUBDrm128
+ 404789082U, // PHSUBDrm64
+ 203462490U, // PHSUBDrr128
+ 203462490U, // PHSUBDrr64
+ 1140856674U, // PHSUBSWrm128
+ 404789090U, // PHSUBSWrm64
+ 203462498U, // PHSUBSWrr128
+ 203462498U, // PHSUBSWrr64
+ 1140856683U, // PHSUBWrm128
+ 404789099U, // PHSUBWrm64
+ 203462507U, // PHSUBWrr128
+ 203462507U, // PHSUBWrr64
+ 1031116659U, // PINSRBrm
+ 1073747827U, // PINSRBrr
+ 1029019515U, // PINSRDrm
+ 1073747835U, // PINSRDrr
+ 1030068099U, // PINSRQrm
+ 1073747843U, // PINSRQrr
+ 1027969629U, // PINSRWrmi
+ 1073746525U, // PINSRWrri
+ 1140856715U, // PMADDUBSWrm128
+ 404789131U, // PMADDUBSWrm64
+ 203462539U, // PMADDUBSWrr128
+ 203462539U, // PMADDUBSWrr64
+ 1140855397U, // PMADDWDrm
+ 203461221U, // PMADDWDrr
+ 1140856726U, // PMAXSBrm
+ 203462550U, // PMAXSBrr
+ 1140856734U, // PMAXSDrm
+ 203462558U, // PMAXSDrr
+ 1140855406U, // PMAXSWrm
+ 203461230U, // PMAXSWrr
+ 1140855414U, // PMAXUBrm
+ 203461238U, // PMAXUBrr
+ 1140856742U, // PMAXUDrm
+ 203462566U, // PMAXUDrr
+ 1140856750U, // PMAXUWrm
+ 203462574U, // PMAXUWrr
+ 1140856758U, // PMINSBrm
+ 203462582U, // PMINSBrr
+ 1140856766U, // PMINSDrm
+ 203462590U, // PMINSDrr
+ 1140855422U, // PMINSWrm
+ 203461246U, // PMINSWrr
+ 1140855430U, // PMINUBrm
+ 203461254U, // PMINUBrr
+ 1140856774U, // PMINUDrm
+ 203462598U, // PMINUDrr
+ 1140856782U, // PMINUWrm
+ 203462606U, // PMINUWrr
+ 1277203086U, // PMOVMSKBrr
+ 1342183382U, // PMOVSXBDrm
+ 1277204438U, // PMOVSXBDrr
+ 1207965664U, // PMOVSXBQrm
+ 1277204448U, // PMOVSXBQrr
+ 1409292266U, // PMOVSXBWrm
+ 1277204458U, // PMOVSXBWrr
+ 1409292276U, // PMOVSXDQrm
+ 1277204468U, // PMOVSXDQrr
+ 1409292286U, // PMOVSXWDrm
+ 1277204478U, // PMOVSXWDrr
+ 1342183432U, // PMOVSXWQrm
+ 1277204488U, // PMOVSXWQrr
+ 1342183442U, // PMOVZXBDrm
+ 1277204498U, // PMOVZXBDrr
+ 1207965724U, // PMOVZXBQrm
+ 1277204508U, // PMOVZXBQrr
+ 1409292326U, // PMOVZXBWrm
+ 1277204518U, // PMOVZXBWrr
+ 1409292336U, // PMOVZXDQrm
+ 1277204528U, // PMOVZXDQrr
+ 1409292346U, // PMOVZXWDrm
+ 1277204538U, // PMOVZXWDrr
+ 1342183492U, // PMOVZXWQrm
+ 1277204548U, // PMOVZXWQrr
+ 1140856910U, // PMULDQrm
+ 203462734U, // PMULDQrr
+ 1140856918U, // PMULHRSWrm128
+ 404789334U, // PMULHRSWrm64
+ 203462742U, // PMULHRSWrr128
+ 203462742U, // PMULHRSWrr64
+ 1140855448U, // PMULHUWrm
+ 203461272U, // PMULHUWrr
+ 1140855457U, // PMULHWrm
+ 203461281U, // PMULHWrr
+ 1140856928U, // PMULLDrm
+ 1140856928U, // PMULLDrm_int
+ 203462752U, // PMULLDrr
+ 203462752U, // PMULLDrr_int
+ 1140855465U, // PMULLWrm
+ 203461289U, // PMULLWrr
+ 1140855473U, // PMULUDQrm
+ 203461297U, // PMULUDQrr
+ 73406568U, // POP16r
+ 872421480U, // POP16rmm
+ 73406568U, // POP16rmr
+ 73406574U, // POP32r
+ 945821806U, // POP32rmm
+ 73406574U, // POP32rmr
+ 73406580U, // POP64r
+ 1476401268U, // POP64rmm
+ 73406580U, // POP64rmr
+ 1207965818U, // POPCNT16rm
+ 1277204602U, // POPCNT16rr
+ 1342183555U, // POPCNT32rm
+ 1277204611U, // POPCNT32rr
+ 1409292428U, // POPCNT64rm
+ 1277204620U, // POPCNT64rr
+ 6293U, // POPF
+ 6299U, // POPFD
+ 6305U, // POPFQ
+ 6311U, // POPFS16
+ 6320U, // POPFS32
+ 6329U, // POPFS64
+ 6338U, // POPGS16
+ 6347U, // POPGS32
+ 6356U, // POPGS64
+ 1140855482U, // PORrm
+ 203461306U, // PORrr
+ 1610619101U, // PREFETCHNTA
+ 1610619114U, // PREFETCHT0
+ 1610619126U, // PREFETCHT1
+ 1610619138U, // PREFETCHT2
+ 1140855487U, // PSADBWrm
+ 203461311U, // PSADBWrr
+ 1140857102U, // PSHUFBrm128
+ 404789518U, // PSHUFBrm64
+ 203462926U, // PSHUFBrr128
+ 203462926U, // PSHUFBrr64
+ 2173704470U, // PSHUFDmi
+ 215324950U, // PSHUFDri
+ 2173704478U, // PSHUFHWmi
+ 215324958U, // PSHUFHWri
+ 2173704487U, // PSHUFLWmi
+ 215324967U, // PSHUFLWri
+ 1140857136U, // PSIGNBrm128
+ 404789552U, // PSIGNBrm64
+ 203462960U, // PSIGNBrr128
+ 203462960U, // PSIGNBrr64
+ 1140857144U, // PSIGNDrm128
+ 404789560U, // PSIGNDrm64
+ 203462968U, // PSIGNDrr128
+ 203462968U, // PSIGNDrr64
+ 1140857152U, // PSIGNWrm128
+ 404789568U, // PSIGNWrm64
+ 203462976U, // PSIGNWrr128
+ 203462976U, // PSIGNWrr64
+ 203462984U, // PSLLDQri
+ 203461327U, // PSLLDri
+ 1140855503U, // PSLLDrm
+ 203461327U, // PSLLDrr
+ 203461334U, // PSLLQri
+ 1140855510U, // PSLLQrm
+ 203461334U, // PSLLQrr
+ 203461341U, // PSLLWri
+ 1140855517U, // PSLLWrm
+ 203461341U, // PSLLWrr
+ 203461348U, // PSRADri
+ 1140855524U, // PSRADrm
+ 203461348U, // PSRADrr
+ 203461355U, // PSRAWri
+ 1140855531U, // PSRAWrm
+ 203461355U, // PSRAWrr
+ 203462992U, // PSRLDQri
+ 203461362U, // PSRLDri
+ 1140855538U, // PSRLDrm
+ 203461362U, // PSRLDrr
+ 203461369U, // PSRLQri
+ 1140855545U, // PSRLQrm
+ 203461369U, // PSRLQrr
+ 203461376U, // PSRLWri
+ 1140855552U, // PSRLWrm
+ 203461376U, // PSRLWrr
+ 1140855559U, // PSUBBrm
+ 203461383U, // PSUBBrr
+ 1140855566U, // PSUBDrm
+ 203461390U, // PSUBDrr
+ 1140855573U, // PSUBQrm
+ 203461397U, // PSUBQrr
+ 1140855580U, // PSUBSBrm
+ 203461404U, // PSUBSBrr
+ 1140855588U, // PSUBSWrm
+ 203461412U, // PSUBSWrr
+ 1140855596U, // PSUBUSBrm
+ 203461420U, // PSUBUSBrr
+ 1140855605U, // PSUBUSWrm
+ 203461429U, // PSUBUSWrr
+ 1140855614U, // PSUBWrm
+ 203461438U, // PSUBWrr
+ 2281707864U, // PTESTrm
+ 1277204824U, // PTESTrr
+ 1140855621U, // PUNPCKHBWrm
+ 203461445U, // PUNPCKHBWrr
+ 1140855632U, // PUNPCKHDQrm
+ 203461456U, // PUNPCKHDQrr
+ 1140857184U, // PUNPCKHQDQrm
+ 203463008U, // PUNPCKHQDQrr
+ 1140855643U, // PUNPCKHWDrm
+ 203461467U, // PUNPCKHWDrr
+ 1140855654U, // PUNPCKLBWrm
+ 203461478U, // PUNPCKLBWrr
+ 1140855665U, // PUNPCKLDQrm
+ 203461489U, // PUNPCKLDQrr
+ 1140857196U, // PUNPCKLQDQrm
+ 203463020U, // PUNPCKLQDQrr
+ 1140855676U, // PUNPCKLWDrm
+ 203461500U, // PUNPCKLWDrr
+ 73406840U, // PUSH16r
+ 872421752U, // PUSH16rmm
+ 73406840U, // PUSH16rmr
+ 73406847U, // PUSH32i16
+ 73406847U, // PUSH32i32
+ 73406847U, // PUSH32i8
+ 73406847U, // PUSH32r
+ 945822079U, // PUSH32rmm
+ 73406847U, // PUSH32rmr
+ 73406854U, // PUSH64i16
+ 73406854U, // PUSH64i32
+ 73406854U, // PUSH64i8
+ 73406854U, // PUSH64r
+ 1476401542U, // PUSH64rmm
+ 73406854U, // PUSH64rmr
+ 6541U, // PUSHF
+ 6548U, // PUSHFD
+ 6555U, // PUSHFQ64
+ 6562U, // PUSHFS16
+ 6572U, // PUSHFS32
+ 6582U, // PUSHFS64
+ 6592U, // PUSHGS16
+ 6602U, // PUSHGS32
+ 6612U, // PUSHGS64
+ 1140853859U, // PXORrm
+ 203459683U, // PXORrr
+ 872421854U, // RCL16m1
+ 872421863U, // RCL16mCL
+ 2711624178U, // RCL16mi
+ 73406942U, // RCL16r1
+ 73406951U, // RCL16rCL
+ 203463154U, // RCL16ri
+ 945822200U, // RCL32m1
+ 945822209U, // RCL32mCL
+ 2712672780U, // RCL32mi
+ 73406968U, // RCL32r1
+ 73406977U, // RCL32rCL
+ 203463180U, // RCL32ri
+ 1476401682U, // RCL64m1
+ 1476401691U, // RCL64mCL
+ 2713721382U, // RCL64mi
+ 73406994U, // RCL64r1
+ 73407003U, // RCL64rCL
+ 203463206U, // RCL64ri
+ 1610619436U, // RCL8m1
+ 1610619445U, // RCL8mCL
+ 2714769984U, // RCL8mi
+ 73407020U, // RCL8r1
+ 73407029U, // RCL8rCL
+ 203463232U, // RCL8ri
+ 1946163782U, // RCPPSm
+ 1946163782U, // RCPPSm_Int
+ 1277205062U, // RCPPSr
+ 1277205062U, // RCPPSr_Int
+ 2080381517U, // RCPSSm
+ 2080381517U, // RCPSSm_Int
+ 1277205069U, // RCPSSr
+ 1277205069U, // RCPSSr_Int
+ 872421972U, // RCR16m1
+ 872421981U, // RCR16mCL
+ 2711624296U, // RCR16mi
+ 73407060U, // RCR16r1
+ 73407069U, // RCR16rCL
+ 203463272U, // RCR16ri
+ 945822318U, // RCR32m1
+ 945822327U, // RCR32mCL
+ 2712672898U, // RCR32mi
+ 73407086U, // RCR32r1
+ 73407095U, // RCR32rCL
+ 203463298U, // RCR32ri
+ 1476401800U, // RCR64m1
+ 1476401809U, // RCR64mCL
+ 2713721500U, // RCR64mi
+ 73407112U, // RCR64r1
+ 73407121U, // RCR64rCL
+ 203463324U, // RCR64ri
+ 1610619554U, // RCR8m1
+ 1610619563U, // RCR8mCL
+ 2714770102U, // RCR8mi
+ 73407138U, // RCR8r1
+ 73407147U, // RCR8rCL
+ 203463350U, // RCR8ri
+ 6844U, // RDMSR
+ 6850U, // RDPMC
+ 6856U, // RDTSC
+ 6862U, // REP_MOVSB
+ 6872U, // REP_MOVSD
+ 6882U, // REP_MOVSQ
+ 6892U, // REP_MOVSW
+ 6902U, // REP_STOSB
+ 6912U, // REP_STOSD
+ 6922U, // REP_STOSQ
+ 6932U, // REP_STOSW
+ 6942U, // RET
+ 73407266U, // RETI
+ 872422183U, // ROL16m1
+ 872422189U, // ROL16mCL
+ 135273255U, // ROL16mi
+ 73407271U, // ROL16r1
+ 73407277U, // ROL16rCL
+ 203463463U, // ROL16ri
+ 945822520U, // ROL32m1
+ 945822526U, // ROL32mCL
+ 135338808U, // ROL32mi
+ 73407288U, // ROL32r1
+ 73407294U, // ROL32rCL
+ 203463480U, // ROL32ri
+ 1476401993U, // ROL64m1
+ 1476401999U, // ROL64mCL
+ 135371593U, // ROL64mi
+ 73407305U, // ROL64r1
+ 73407311U, // ROL64rCL
+ 203463497U, // ROL64ri
+ 1610619738U, // ROL8m1
+ 1610619744U, // ROL8mCL
+ 135404378U, // ROL8mi
+ 73407322U, // ROL8r1
+ 73407328U, // ROL8rCL
+ 203463514U, // ROL8ri
+ 872422251U, // ROR16m1
+ 872422257U, // ROR16mCL
+ 135273323U, // ROR16mi
+ 73407339U, // ROR16r1
+ 73407345U, // ROR16rCL
+ 203463531U, // ROR16ri
+ 945822588U, // ROR32m1
+ 945822594U, // ROR32mCL
+ 135338876U, // ROR32mi
+ 73407356U, // ROR32r1
+ 73407362U, // ROR32rCL
+ 203463548U, // ROR32ri
+ 1476402061U, // ROR64m1
+ 1476402067U, // ROR64mCL
+ 135371661U, // ROR64mi
+ 73407373U, // ROR64r1
+ 73407379U, // ROR64rCL
+ 203463565U, // ROR64ri
+ 1610619806U, // ROR8m1
+ 1610619812U, // ROR8mCL
+ 135404446U, // ROR8mi
+ 73407390U, // ROR8r1
+ 73407396U, // ROR8rCL
+ 203463582U, // ROR8ri
+ 2178948015U, // ROUNDPDm_Int
+ 215325615U, // ROUNDPDr_Int
+ 2178948024U, // ROUNDPSm_Int
+ 215325624U, // ROUNDPSr_Int
+ 1039145921U, // ROUNDSDm_Int
+ 1073748929U, // ROUNDSDr_Int
+ 1025514442U, // ROUNDSSm_Int
+ 1073748938U, // ROUNDSSr_Int
+ 7123U, // RSM
+ 1946164183U, // RSQRTPSm
+ 1946164183U, // RSQRTPSm_Int
+ 1277205463U, // RSQRTPSr
+ 1277205463U, // RSQRTPSr_Int
+ 2080381920U, // RSQRTSSm
+ 2080381920U, // RSQRTSSm_Int
+ 1277205472U, // RSQRTSSr
+ 1277205472U, // RSQRTSSr_Int
+ 7145U, // SAHF
+ 872422382U, // SAR16m1
+ 872422388U, // SAR16mCL
+ 135273454U, // SAR16mi
+ 73407470U, // SAR16r1
+ 73407476U, // SAR16rCL
+ 203463662U, // SAR16ri
+ 945822719U, // SAR32m1
+ 945822725U, // SAR32mCL
+ 135339007U, // SAR32mi
+ 73407487U, // SAR32r1
+ 73407493U, // SAR32rCL
+ 203463679U, // SAR32ri
+ 1476402192U, // SAR64m1
+ 1476402198U, // SAR64mCL
+ 135371792U, // SAR64mi
+ 73407504U, // SAR64r1
+ 73407510U, // SAR64rCL
+ 203463696U, // SAR64ri
+ 1610619937U, // SAR8m1
+ 1610619943U, // SAR8mCL
+ 135404577U, // SAR8mi
+ 73407521U, // SAR8r1
+ 73407527U, // SAR8rCL
+ 203463713U, // SAR8ri
+ 67116082U, // SBB16i16
+ 135273522U, // SBB16mi
+ 135273522U, // SBB16mi8
+ 135273522U, // SBB16mr
+ 203463730U, // SBB16ri
+ 203463730U, // SBB16ri8
+ 270572594U, // SBB16rm
+ 203463730U, // SBB16rr
+ 203463730U, // SBB16rr_REV
+ 70261816U, // SBB32i32
+ 135339064U, // SBB32mi
+ 135339064U, // SBB32mi8
+ 135339064U, // SBB32mr
+ 203463736U, // SBB32ri
+ 203463736U, // SBB32ri8
+ 337681464U, // SBB32rm
+ 203463736U, // SBB32rr
+ 203463736U, // SBB32rr_REV
+ 71310398U, // SBB64i32
+ 135371838U, // SBB64mi32
+ 135371838U, // SBB64mi8
+ 135371838U, // SBB64mr
+ 203463742U, // SBB64ri32
+ 203463742U, // SBB64ri8
+ 404790334U, // SBB64rm
+ 203463742U, // SBB64rr
+ 203463742U, // SBB64rr_REV
+ 72358980U, // SBB8i8
+ 135404612U, // SBB8mi
+ 135404612U, // SBB8mr
+ 203463748U, // SBB8ri
+ 471899204U, // SBB8rm
+ 203463748U, // SBB8rr
+ 203463748U, // SBB8rr_REV
+ 7242U, // SCAS16
+ 7248U, // SCAS32
+ 7254U, // SCAS64
+ 7260U, // SCAS8
+ 1610620002U, // SETAEm
+ 73407586U, // SETAEr
+ 1610620009U, // SETAm
+ 73407593U, // SETAr
+ 1610620015U, // SETBEm
+ 73407599U, // SETBEr
+ 68557874U, // SETB_C16r
+ 68557880U, // SETB_C32r
+ 68557886U, // SETB_C64r
+ 68557892U, // SETB_C8r
+ 1610620022U, // SETBm
+ 73407606U, // SETBr
+ 1610620028U, // SETEm
+ 73407612U, // SETEr
+ 1610620034U, // SETGEm
+ 73407618U, // SETGEr
+ 1610620041U, // SETGm
+ 73407625U, // SETGr
+ 1610620047U, // SETLEm
+ 73407631U, // SETLEr
+ 1610620054U, // SETLm
+ 73407638U, // SETLr
+ 1610620060U, // SETNEm
+ 73407644U, // SETNEr
+ 1610620067U, // SETNOm
+ 73407651U, // SETNOr
+ 1610620074U, // SETNPm
+ 73407658U, // SETNPr
+ 1610620081U, // SETNSm
+ 73407665U, // SETNSr
+ 1610620088U, // SETOm
+ 73407672U, // SETOr
+ 1610620094U, // SETPm
+ 73407678U, // SETPr
+ 1610620100U, // SETSm
+ 73407684U, // SETSr
+ 7370U, // SFENCE
+ 2214599889U, // SGDTm
+ 872422615U, // SHL16m1
+ 872422621U, // SHL16mCL
+ 135273687U, // SHL16mi
+ 73407703U, // SHL16r1
+ 73407709U, // SHL16rCL
+ 203463895U, // SHL16ri
+ 945822952U, // SHL32m1
+ 945822958U, // SHL32mCL
+ 135339240U, // SHL32mi
+ 73407720U, // SHL32r1
+ 73407726U, // SHL32rCL
+ 203463912U, // SHL32ri
+ 1476402425U, // SHL64m1
+ 1476402431U, // SHL64mCL
+ 135372025U, // SHL64mi
+ 73407737U, // SHL64r1
+ 73407743U, // SHL64rCL
+ 203463929U, // SHL64ri
+ 1610620170U, // SHL8m1
+ 1610620176U, // SHL8mCL
+ 135404810U, // SHL8mi
+ 73407754U, // SHL8r1
+ 73407760U, // SHL8rCL
+ 203463946U, // SHL8ri
+ 135273755U, // SHLD16mrCL
+ 2162171175U, // SHLD16mri8
+ 203463963U, // SHLD16rrCL
+ 1073749287U, // SHLD16rri8
+ 135339310U, // SHLD32mrCL
+ 2162236730U, // SHLD32mri8
+ 203463982U, // SHLD32rrCL
+ 1073749306U, // SHLD32rri8
+ 135372097U, // SHLD64mrCL
+ 2162269517U, // SHLD64mri8
+ 203464001U, // SHLD64rrCL
+ 1073749325U, // SHLD64rri8
+ 872422740U, // SHR16m1
+ 872422746U, // SHR16mCL
+ 135273812U, // SHR16mi
+ 73407828U, // SHR16r1
+ 73407834U, // SHR16rCL
+ 203464020U, // SHR16ri
+ 945823077U, // SHR32m1
+ 945823083U, // SHR32mCL
+ 135339365U, // SHR32mi
+ 73407845U, // SHR32r1
+ 73407851U, // SHR32rCL
+ 203464037U, // SHR32ri
+ 1476402550U, // SHR64m1
+ 1476402556U, // SHR64mCL
+ 135372150U, // SHR64mi
+ 73407862U, // SHR64r1
+ 73407868U, // SHR64rCL
+ 203464054U, // SHR64ri
+ 1610620295U, // SHR8m1
+ 1610620301U, // SHR8mCL
+ 135404935U, // SHR8mi
+ 73407879U, // SHR8r1
+ 73407885U, // SHR8rCL
+ 203464071U, // SHR8ri
+ 135273880U, // SHRD16mrCL
+ 2162171300U, // SHRD16mri8
+ 203464088U, // SHRD16rrCL
+ 1073749412U, // SHRD16rri8
+ 135339435U, // SHRD32mrCL
+ 2162236855U, // SHRD32mri8
+ 203464107U, // SHRD32rrCL
+ 1073749431U, // SHRD32rri8
+ 135372222U, // SHRD64mrCL
+ 2162269642U, // SHRD64mri8
+ 203464126U, // SHRD64rrCL
+ 1073749450U, // SHRD64rri8
+ 1040195025U, // SHUFPDrmi
+ 1073749457U, // SHUFPDrri
+ 1040195033U, // SHUFPSrmi
+ 1073749465U, // SHUFPSrri
+ 2214600161U, // SIDTm
+ 7655U, // SIN_F
0U, // SIN_Fp32
0U, // SIN_Fp64
0U, // SIN_Fp80
- 1879054707U, // SQRTPDm
- 1879054707U, // SQRTPDm_Int
- 1281366387U, // SQRTPDr
- 1281366387U, // SQRTPDr_Int
- 1879054715U, // SQRTPSm
- 1879054715U, // SQRTPSm_Int
- 1281366395U, // SQRTPSr
- 1281366395U, // SQRTPSr_Int
- 1946163587U, // SQRTSDm
- 1946163587U, // SQRTSDm_Int
- 1281366403U, // SQRTSDr
- 1281366403U, // SQRTSDr_Int
- 2013272459U, // SQRTSSm
- 2013272459U, // SQRTSSm_Int
- 1281366411U, // SQRTSSr
- 1281366411U, // SQRTSSr_Int
- 6547U, // SQRT_F
+ 872422892U, // SLDT16m
+ 73407980U, // SLDT16r
+ 872422899U, // SLDT64m
+ 73407987U, // SLDT64r
+ 872422906U, // SMSW16m
+ 73407994U, // SMSW16r
+ 73408001U, // SMSW32r
+ 73408008U, // SMSW64r
+ 1946164751U, // SQRTPDm
+ 1946164751U, // SQRTPDm_Int
+ 1277206031U, // SQRTPDr
+ 1277206031U, // SQRTPDr_Int
+ 1946164759U, // SQRTPSm
+ 1946164759U, // SQRTPSm_Int
+ 1277206039U, // SQRTPSr
+ 1277206039U, // SQRTPSr_Int
+ 2013273631U, // SQRTSDm
+ 2013273631U, // SQRTSDm_Int
+ 1277206047U, // SQRTSDr
+ 1277206047U, // SQRTSDr_Int
+ 2080382503U, // SQRTSSm
+ 2080382503U, // SQRTSSm_Int
+ 1277206055U, // SQRTSSr
+ 1277206055U, // SQRTSSr_Int
+ 7727U, // SQRT_F
0U, // SQRT_Fp32
0U, // SQRT_Fp64
0U, // SQRT_Fp80
- 945822105U, // STMXCSR
- 738204066U, // ST_F32m
- 805312936U, // ST_F64m
- 738204078U, // ST_FP32m
- 805312949U, // ST_FP64m
- 2281707964U, // ST_FP80m
- 73406915U, // ST_FPrr
+ 7733U, // STC
+ 7737U, // STD
+ 7741U, // STI
+ 945823297U, // STMXCSR
+ 872422986U, // STRm
+ 73408074U, // STRr
+ 738205264U, // ST_F32m
+ 805314134U, // ST_F64m
+ 738205276U, // ST_FP32m
+ 805314147U, // ST_FP64m
+ 2415926890U, // ST_FP80m
+ 73408113U, // ST_FPrr
0U, // ST_Fp32m
0U, // ST_Fp64m
0U, // ST_Fp64m32
@@ -2068,47 +2286,51 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ST_FpP80m
0U, // ST_FpP80m32
0U, // ST_FpP80m64
- 73406921U, // ST_Frr
- 67115470U, // SUB16i16
- 135272910U, // SUB16mi
- 135272910U, // SUB16mi8
- 135272910U, // SUB16mr
- 203430350U, // SUB16ri
- 203430350U, // SUB16ri8
- 270539214U, // SUB16rm
- 203430350U, // SUB16rr
- 70261204U, // SUB32i32
- 135338452U, // SUB32mi
- 135338452U, // SUB32mi8
- 135338452U, // SUB32mr
- 203430356U, // SUB32ri
- 203430356U, // SUB32ri8
- 337648084U, // SUB32rm
- 203430356U, // SUB32rr
- 71309786U, // SUB64i32
- 135403994U, // SUB64mi32
- 135403994U, // SUB64mi8
- 135403994U, // SUB64mr
- 203430362U, // SUB64ri32
- 203430362U, // SUB64ri8
- 404756954U, // SUB64rm
- 203430362U, // SUB64rr
- 72358368U, // SUB8i8
- 135469536U, // SUB8mi
- 135469536U, // SUB8mr
- 203430368U, // SUB8ri
- 471865824U, // SUB8rm
- 203430368U, // SUB8rr
- 536877542U, // SUBPDrm
- 203430374U, // SUBPDrr
- 536877549U, // SUBPSrm
- 203430381U, // SUBPSrr
- 738204148U, // SUBR_F32m
- 805313020U, // SUBR_F64m
- 872421892U, // SUBR_FI16m
- 945822221U, // SUBR_FI32m
- 73406998U, // SUBR_FPrST0
- 73407005U, // SUBR_FST0r
+ 73408119U, // ST_Frr
+ 67116668U, // SUB16i16
+ 135274108U, // SUB16mi
+ 135274108U, // SUB16mi8
+ 135274108U, // SUB16mr
+ 203464316U, // SUB16ri
+ 203464316U, // SUB16ri8
+ 270573180U, // SUB16rm
+ 203464316U, // SUB16rr
+ 203464316U, // SUB16rr_REV
+ 70262402U, // SUB32i32
+ 135339650U, // SUB32mi
+ 135339650U, // SUB32mi8
+ 135339650U, // SUB32mr
+ 203464322U, // SUB32ri
+ 203464322U, // SUB32ri8
+ 337682050U, // SUB32rm
+ 203464322U, // SUB32rr
+ 203464322U, // SUB32rr_REV
+ 71310984U, // SUB64i32
+ 135372424U, // SUB64mi32
+ 135372424U, // SUB64mi8
+ 135372424U, // SUB64mr
+ 203464328U, // SUB64ri32
+ 203464328U, // SUB64ri8
+ 404790920U, // SUB64rm
+ 203464328U, // SUB64rr
+ 203464328U, // SUB64rr_REV
+ 72359566U, // SUB8i8
+ 135405198U, // SUB8mi
+ 135405198U, // SUB8mr
+ 203464334U, // SUB8ri
+ 471899790U, // SUB8rm
+ 203464334U, // SUB8rr
+ 203464334U, // SUB8rr_REV
+ 536878740U, // SUBPDrm
+ 203464340U, // SUBPDrr
+ 536878747U, // SUBPSrm
+ 203464347U, // SUBPSrr
+ 738205346U, // SUBR_F32m
+ 805314218U, // SUBR_F64m
+ 872423090U, // SUBR_FI16m
+ 945823419U, // SUBR_FI32m
+ 73408196U, // SUBR_FPrST0
+ 73408203U, // SUBR_FST0r
0U, // SUBR_Fp32m
0U, // SUBR_Fp64m
0U, // SUBR_Fp64m32
@@ -2120,21 +2342,21 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUBR_FpI32m32
0U, // SUBR_FpI32m64
0U, // SUBR_FpI32m80
- 73407012U, // SUBR_FrST0
- 603986482U, // SUBSDrm
- 603986482U, // SUBSDrm_Int
- 203430450U, // SUBSDrr
- 203430450U, // SUBSDrr_Int
- 671095353U, // SUBSSrm
- 671095353U, // SUBSSrm_Int
- 203430457U, // SUBSSrr
- 203430457U, // SUBSSrr_Int
- 738204224U, // SUB_F32m
- 805313095U, // SUB_F64m
- 872421966U, // SUB_FI16m
- 945822294U, // SUB_FI32m
- 73407070U, // SUB_FPrST0
- 73407078U, // SUB_FST0r
+ 73408210U, // SUBR_FrST0
+ 603987680U, // SUBSDrm
+ 603987680U, // SUBSDrm_Int
+ 203464416U, // SUBSDrr
+ 203464416U, // SUBSDrr_Int
+ 671096551U, // SUBSSrm
+ 671096551U, // SUBSSrm_Int
+ 203464423U, // SUBSSrr
+ 203464423U, // SUBSSrr_Int
+ 738205422U, // SUB_F32m
+ 805314293U, // SUB_F64m
+ 872423164U, // SUB_FI16m
+ 945823492U, // SUB_FI32m
+ 73408268U, // SUB_FPrST0
+ 73408276U, // SUB_FST0r
0U, // SUB_Fp32
0U, // SUB_Fp32m
0U, // SUB_Fp64
@@ -2149,116 +2371,159 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUB_FpI32m32
0U, // SUB_FpI32m64
0U, // SUB_FpI32m80
- 73407084U, // SUB_FrST0
- 6779U, // SYSCALL
- 6787U, // SYSENTER
- 6796U, // SYSEXIT
- 6796U, // SYSEXIT64
- 6804U, // SYSRET
- 1579158416U, // TAILJMPd
- 975182491U, // TAILJMPm
- 102763413U, // TAILJMPr
- 102763420U, // TAILJMPr64
- 103815841U, // TCRETURNdi
- 103815841U, // TCRETURNdi64
- 103815841U, // TCRETURNri
- 103815841U, // TCRETURNri64
- 67115693U, // TEST16i16
- 135273133U, // TEST16mi
- 1281366701U, // TEST16ri
- 1207966381U, // TEST16rm
- 1281366701U, // TEST16rr
- 70261428U, // TEST32i32
- 135338676U, // TEST32mi
- 1281366708U, // TEST32ri
- 1342184116U, // TEST32rm
- 1281366708U, // TEST32rr
- 71310011U, // TEST64i32
- 135404219U, // TEST64mi32
- 1281366715U, // TEST64ri32
- 1409292987U, // TEST64rm
- 1281366715U, // TEST64rr
- 72358594U, // TEST8i8
- 135469762U, // TEST8mi
- 1281366722U, // TEST8ri
- 1684019906U, // TEST8rm
- 1281366722U, // TEST8rr
- 2617248866U, // TLS_addr32
- 2684361417U, // TLS_addr64
- 6875U, // TRAP
- 6879U, // TST_F
+ 73408282U, // SUB_FrST0
+ 7977U, // SWPGS
+ 7983U, // SYSCALL
+ 7991U, // SYSENTER
+ 8000U, // SYSEXIT
+ 8000U, // SYSEXIT64
+ 8008U, // SYSRET
+ 1578110598U, // TAILJMPd
+ 974135119U, // TAILJMPm
+ 101715595U, // TAILJMPr
+ 101715602U, // TAILJMPr64
+ 102768469U, // TCRETURNdi
+ 102768469U, // TCRETURNdi64
+ 102768469U, // TCRETURNri
+ 102768469U, // TCRETURNri64
+ 67116897U, // TEST16i16
+ 135274337U, // TEST16mi
+ 1277206369U, // TEST16ri
+ 1207967585U, // TEST16rm
+ 1277206369U, // TEST16rr
+ 70262632U, // TEST32i32
+ 135339880U, // TEST32mi
+ 1277206376U, // TEST32ri
+ 1342185320U, // TEST32rm
+ 1277206376U, // TEST32rr
+ 71311215U, // TEST64i32
+ 135372655U, // TEST64mi32
+ 1277206383U, // TEST64ri32
+ 1409294191U, // TEST64rm
+ 1277206383U, // TEST64rr
+ 72359798U, // TEST8i8
+ 135405430U, // TEST8mi
+ 1277206390U, // TEST8ri
+ 1684021110U, // TEST8rm
+ 1277206390U, // TEST8rr
+ 2751467370U, // TLS_addr32
+ 2818580349U, // TLS_addr64
+ 8079U, // TRAP
+ 8083U, // TST_F
0U, // TST_Fp32
0U, // TST_Fp64
0U, // TST_Fp80
- 1946159952U, // UCOMISDrm
- 1281362768U, // UCOMISDrr
- 2013268825U, // UCOMISSrm
- 1281362777U, // UCOMISSrr
- 75504356U, // UCOM_FIPr
- 75504365U, // UCOM_FIr
- 6901U, // UCOM_FPPr
- 73407229U, // UCOM_FPr
+ 2013269574U, // UCOMISDrm
+ 1277201990U, // UCOMISDrr
+ 2080378447U, // UCOMISSrm
+ 1277201999U, // UCOMISSrr
+ 75505560U, // UCOM_FIPr
+ 75505569U, // UCOM_FIr
+ 8105U, // UCOM_FPPr
+ 73408433U, // UCOM_FPr
0U, // UCOM_FpIr32
0U, // UCOM_FpIr64
0U, // UCOM_FpIr80
0U, // UCOM_Fpr32
0U, // UCOM_Fpr64
0U, // UCOM_Fpr80
- 73407237U, // UCOM_Fr
- 536877836U, // UNPCKHPDrm
- 203430668U, // UNPCKHPDrr
- 536877846U, // UNPCKHPSrm
- 203430678U, // UNPCKHPSrr
- 536877856U, // UNPCKLPDrm
- 203430688U, // UNPCKLPDrr
- 536877866U, // UNPCKLPSrm
- 203430698U, // UNPCKLPSrr
- 68786996U, // VASTART_SAVE_XMM_REGS
- 68946329U, // V_SET0
- 68947628U, // V_SETALLONES
- 6988U, // WAIT
- 1476396056U, // WINCALL64m
- 1549796383U, // WINCALL64pcrel32
- 73401368U, // WINCALL64r
- 2096634705U, // XCHG16rm
- 2097683288U, // XCHG32rm
- 2098731871U, // XCHG64rm
- 2101353317U, // XCHG8rm
- 73407340U, // XCH_F
- 67115890U, // XOR16i16
- 135273330U, // XOR16mi
- 135273330U, // XOR16mi8
- 135273330U, // XOR16mr
- 203430770U, // XOR16ri
- 203430770U, // XOR16ri8
- 270539634U, // XOR16rm
- 203430770U, // XOR16rr
- 70258742U, // XOR32i32
- 135335990U, // XOR32mi
- 135335990U, // XOR32mi8
- 135335990U, // XOR32mr
- 203427894U, // XOR32ri
- 203427894U, // XOR32ri8
- 337645622U, // XOR32rm
- 203427894U, // XOR32rr
- 71310200U, // XOR64i32
- 135404408U, // XOR64mi32
- 135404408U, // XOR64mi8
- 135404408U, // XOR64mr
- 203430776U, // XOR64ri32
- 203430776U, // XOR64ri8
- 404757368U, // XOR64rm
- 203430776U, // XOR64rr
- 72355958U, // XOR8i8
- 135467126U, // XOR8mi
- 135467126U, // XOR8mr
- 203427958U, // XOR8ri
- 471863414U, // XOR8rm
- 203427958U, // XOR8rr
- 536873362U, // XORPDrm
- 203426194U, // XORPDrr
- 536873369U, // XORPSrm
- 203426201U, // XORPSrr
+ 73408441U, // UCOM_Fr
+ 536879040U, // UNPCKHPDrm
+ 203464640U, // UNPCKHPDrr
+ 536879050U, // UNPCKHPSrm
+ 203464650U, // UNPCKHPSrr
+ 536879060U, // UNPCKLPDrm
+ 203464660U, // UNPCKLPDrr
+ 536879070U, // UNPCKLPSrm
+ 203464670U, // UNPCKLPSrr
+ 68460520U, // VASTART_SAVE_XMM_REGS
+ 872423424U, // VERRm
+ 73408512U, // VERRr
+ 872423430U, // VERWm
+ 73408518U, // VERWr
+ 8204U, // VMCALL
+ 1476403219U, // VMCLEARm
+ 8220U, // VMLAUNCH
+ 1476403237U, // VMPTRLDm
+ 1476403246U, // VMPTRSTm
+ 135340087U, // VMREAD32rm
+ 1277206583U, // VMREAD32rr
+ 135372864U, // VMREAD64rm
+ 1277206592U, // VMREAD64rr
+ 8265U, // VMRESUME
+ 1342185554U, // VMWRITE32rm
+ 1277206610U, // VMWRITE32rr
+ 1409294428U, // VMWRITE64rm
+ 1277206620U, // VMWRITE64rr
+ 8294U, // VMXOFF
+ 1476403309U, // VMXON
+ 68553868U, // V_SET0
+ 68555304U, // V_SETALLONES
+ 8308U, // WAIT
+ 8313U, // WBINVD
+ 1476396110U, // WINCALL64m
+ 1549796452U, // WINCALL64pcrel32
+ 73401422U, // WINCALL64r
+ 8320U, // WRMSR
+ 135274630U, // XADD16rm
+ 1277206662U, // XADD16rr
+ 135340173U, // XADD32rm
+ 1277206669U, // XADD32rr
+ 135372948U, // XADD64rm
+ 1277206676U, // XADD64rr
+ 135405723U, // XADD8rm
+ 1277206683U, // XADD8rr
+ 67117218U, // XCHG16ar
+ 1296081058U, // XCHG16rm
+ 1311776930U, // XCHG16rr
+ 70262953U, // XCHG32ar
+ 1297129641U, // XCHG32rm
+ 1311776937U, // XCHG32rr
+ 71311536U, // XCHG64ar
+ 1298178224U, // XCHG64rm
+ 1311776944U, // XCHG64rr
+ 1299226807U, // XCHG8rm
+ 1311776951U, // XCHG8rr
+ 73408702U, // XCH_F
+ 8388U, // XLAT
+ 67117258U, // XOR16i16
+ 135274698U, // XOR16mi
+ 135274698U, // XOR16mi8
+ 135274698U, // XOR16mr
+ 203464906U, // XOR16ri
+ 203464906U, // XOR16ri8
+ 270573770U, // XOR16rm
+ 203464906U, // XOR16rr
+ 203464906U, // XOR16rr_REV
+ 70259634U, // XOR32i32
+ 135336882U, // XOR32mi
+ 135336882U, // XOR32mi8
+ 135336882U, // XOR32mr
+ 203461554U, // XOR32ri
+ 203461554U, // XOR32ri8
+ 337679282U, // XOR32rm
+ 203461554U, // XOR32rr
+ 203461554U, // XOR32rr_REV
+ 71311568U, // XOR64i32
+ 135373008U, // XOR64mi32
+ 135373008U, // XOR64mi8
+ 135373008U, // XOR64mr
+ 203464912U, // XOR64ri32
+ 203464912U, // XOR64ri8
+ 404791504U, // XOR64rm
+ 203464912U, // XOR64rr
+ 203464912U, // XOR64rr_REV
+ 72356850U, // XOR8i8
+ 135402482U, // XOR8mi
+ 135402482U, // XOR8mr
+ 203461618U, // XOR8ri
+ 471897074U, // XOR8rm
+ 203461618U, // XOR8rr
+ 203461618U, // XOR8rr_REV
+ 536874117U, // XORPDrm
+ 203459717U, // XORPDrr
+ 536874124U, // XORPSrm
+ 203459724U, // XORPSrr
0U
};
@@ -2281,129 +2546,158 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
"OMXOR32 PSEUDO!\000#ATOMXOR64 PSEUDO!\000#ATOMXOR6432 PSEUDO!\000#ATOMX"
"OR8 PSEUDO!\000blendpd\t\000blendps\t\000blendvpd\t%xmm0, \000blendvps\t"
"%xmm0, \000bsfw\t\000bsfl\t\000bsfq\t\000bsrw\t\000bsrl\t\000bsrq\t\000"
- "bswapl\t\000bswapq\t\000btw\t\000btl\t\000btq\t\000call\t*\000call\t\000"
- "cbtw\000cltd\000cltq\000fchs\000clflush\t\000cmova\t\000cmovae\t\000cmo"
- "vb\t\000cmovbe\t\000fcmovbe\t\000fcmovb\t\000cmove\t\000fcmove\t\000cmo"
- "vg\t\000cmovge\t\000cmovl\t\000cmovle\t\000fcmovnbe\t\000fcmovnb\t\000c"
- "movne\t\000fcmovne\t\000cmovno\t\000cmovnp\t\000fcmovnu\t\000cmovns\t\000"
- "cmovo\t\000cmovp\t\000fcmovu\t \000cmovs\t\000#CMOV_FR32 PSEUDO!\000#CM"
- "OV_FR64 PSEUDO!\000#CMOV_GR8 PSEUDO!\000#CMOV_V1I64 PSEUDO!\000#CMOV_V2"
- "F64 PSEUDO!\000#CMOV_V2I64 PSEUDO!\000#CMOV_V4F32 PSEUDO!\000cmpw\t\000"
- "cmpl\t\000cmpq\t\000cmpb\t\000cmp\000cmpsw\000cmpsl\000cmpsq\000cmpsb\000"
- "comisd\t\000fcos\000cqto\000crc32 \t\000cvtdq2pd\t\000cvtdq2ps\t\000cvt"
- "pd2dq\t\000cvtps2dq\t\000cvtsd2ss\t\000cvtsi2sdq\t\000cvtsi2sd\t\000cvt"
- "si2ssq\t\000cvtsi2ss\t\000cvtss2sd\t\000cvttsd2siq\t\000cvttsd2si\t\000"
- "cvttss2siq\t\000cvttss2si\t\000cwtd\000cwtl\000decw\t\000decl\t\000decq"
- "\t\000decb\t\000divw\t\000divl\t\000divq\t\000divb\t\000divpd\t\000divp"
- "s\t\000fdivrs\t\000fdivrl\t\000fidivrs\t\000fidivrl\t\000fdivp\t\000fdi"
- "vr\t\000fdiv\t%st(0), \000divsd\t\000divss\t\000fdivs\t\000fdivl\t\000f"
- "idivs\t\000fidivl\t\000fdivrp\t\000fdiv\t\000fdivr\t%st(0), \000dppd\t\000"
- "dpps\t\000ret\t#eh_return, addr: \000enter\t\000extractps\t\000lcallw\t"
- "\000lcallw\t*\000lcalll\t\000lcalll\t*\000lcallq\t*\000ljmpw\t\000ljmpw"
- "\t*\000ljmpl\t\000ljmpl\t*\000ljmpq\t*\000fbld\t\000fbstp\t\000fcom\t\000"
- "fcomp\t\000ficomw\t\000ficoml\t\000ficompw\t\000ficompl\t\000fisttpl\t\000"
- "fldcw\t\000fldenv\t\000fnstcw\t\000fnstsw\000##FP32_TO_INT16_IN_MEM PSE"
- "UDO!\000##FP32_TO_INT32_IN_MEM PSEUDO!\000##FP32_TO_INT64_IN_MEM PSEUDO"
- "!\000##FP64_TO_INT16_IN_MEM PSEUDO!\000##FP64_TO_INT32_IN_MEM PSEUDO!\000"
- "##FP64_TO_INT64_IN_MEM PSEUDO!\000##FP80_TO_INT16_IN_MEM PSEUDO!\000##F"
- "P80_TO_INT32_IN_MEM PSEUDO!\000##FP80_TO_INT64_IN_MEM PSEUDO!\000##FP_R"
- "EG_KILL\000frstor\t\000fsave\t\000fstenv\t\000fstsw\t\000movl\t%fs:\000"
- "pxor\t\000movapd\t\000movaps\t\000orpd\t\000orps\t\000xorpd\t\000xorps\t"
- "\000movl\t%gs:\000haddpd\t\000haddps\t\000hsubpd\t\000hsubps\t\000idivw"
- "\t\000idivl\t\000idivq\t\000idivb\t\000filds\t\000fildl\t\000fildll\t\000"
- "imulw\t\000imull\t\000imulq\t\000imulb\t\000inw\t\000inw\t%dx, %ax\000i"
- "nl\t\000inl\t%dx, %eax\000inb\t\000inb\t%dx, %al\000incw\t\000incl\t\000"
- "incq\t\000incb\t\000insertps\t\000int\t\000int\t3\000fisttps\t\000fistt"
- "pll\t\000fists\t\000fistl\t\000fistps\t\000fistpl\t\000fistpll\t\000com"
- "iss\t\000cvtpd2pi\t\000cvtpd2ps\t\000cvtpi2pd\t\000cvtpi2ps\t\000cvtps2"
- "pd\t\000cvtps2pi\t\000cvtsd2siq\t\000cvtsd2si\t\000cvtss2siq\t\000cvtss"
- "2si\t\000cvttpd2dq\t\000cvttpd2pi\t\000cvttps2dq\t\000cvttps2pi\t\000uc"
- "omisd\t\000ucomiss\t\000ja\t\000jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t"
- "\000jg\t\000jge\t\000jl\t\000jle\t\000jmp\t\000jmpl\t*\000jmpq\t*\000jn"
- "e\t\000jno\t\000jnp\t\000jns\t\000jo\t\000jp\t\000js\t\000lahf\000larw\t"
- "\000larl\t\000larq\t\000lock\n\tcmpxchgw\t\000lock\n\tcmpxchgl\t\000loc"
- "k\n\tcmpxchgq\t\000lock\n\tcmpxchgb\t\000lock\n\tcmpxchg8b\t\000lddqu\t"
- "\000ldmxcsr\t\000fldz\000fld1\000flds\t\000fldl\t\000fldt\t\000fld\t\000"
- "leaw\t\000leal\t\000leaq\t\000leave\000lfence\000lock\n\taddw\t\000lock"
- "\n\taddl\t\000lock\n\taddq\t\000lock\n\taddb\t\000lock\n\tdecw\t\000loc"
- "k\n\tdecl\t\000lock\n\tdecq\t\000lock\n\tdecb\t\000lock\n\tincw\t\000lo"
- "ck\n\tincl\t\000lock\n\tincq\t\000lock\n\tincb\t\000lock\n\tsubw\t\000l"
- "ock\n\tsubl\t\000lock\n\tsubq\t\000lock\n\tsubb\t\000lodsb\000lodsd\000"
- "lodsq\000lodsw\000loop\t\000loope\t\000loopne\t\000lret\000lret\t\000lo"
- "ck\n\txaddw\t\000lock\n\txaddl\t\000lock\n\txadd\t\000lock\n\txaddb\t\000"
- "maskmovdqu\t\000maxpd\t\000maxps\t\000maxsd\t\000maxss\t\000mfence\000m"
- "inpd\t\000minps\t\000minsd\t\000minss\t\000emms\000femms\000maskmovq\t\000"
- "movd\t\000movdq2q\t\000movntq\t\000movq2dq\t\000movq\t\000packssdw\t\000"
- "packsswb\t\000packuswb\t\000paddb\t\000paddd\t\000paddq\t\000paddsb\t\000"
- "paddsw\t\000paddusb\t\000paddusw\t\000paddw\t\000pandn\t\000pand\t\000p"
- "avgb\t\000pavgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000"
- "pcmpgtd\t\000pcmpgtw\t\000pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t"
- "\000pmaxub\t\000pminsw\t\000pminub\t\000pmovmskb\t\000pmulhuw\t\000pmul"
- "hw\t\000pmullw\t\000pmuludq\t\000por\t\000psadbw\t\000pshufw\t\000pslld"
- "\t\000psllq\t\000psllw\t\000psrad\t\000psraw\t\000psrld\t\000psrlq\t\000"
- "psrlw\t\000psubb\t\000psubd\t\000psubq\t\000psubsb\t\000psubsw\t\000psu"
- "busb\t\000psubusw\t\000psubw\t\000punpckhbw\t\000punpckhdq\t\000punpckh"
- "wd\t\000punpcklbw\t\000punpckldq\t\000punpcklwd\t\000monitor\000movw\t%"
- "ax, \000movw\t\000movl\t%eax, \000movl\t\000xorl\t\000movq\t%fs:\000mov"
- "q\t%gs:\000movq\t%rax, \000movabsq\t\000movb\t%al, \000movb\t\000xorb\t"
- "\000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000movhp"
- "s\t\000movlhps\t\000movlpd\t\000movsd\t\000movlps\t\000movss\t\000movms"
- "kpd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t"
- "\000movntps\t\000movshdup\t\000movsldup\t\000movswl\t\000movsbl\t\000mo"
- "vswq\t\000movslq\t\000movsbq\t\000movupd\t\000movups\t\000movzbl\t\000m"
- "ovzwl\t\000mpsadbw\t\000mulw\t\000mull\t\000mulq\t\000mulb\t\000mulpd\t"
- "\000mulps\t\000mulsd\t\000mulss\t\000fmuls\t\000fmull\t\000fimuls\t\000"
- "fimull\t\000fmulp\t\000fmul\t\000fmul\t%st(0), \000mwait\000negw\t\000n"
- "egl\t\000negq\t\000negb\t\000nop\000nopl\t\000notw\t\000notl\t\000notq\t"
- "\000notb\t\000orw\t\000orl\t\000orq\t\000orb\t\000outw\t%ax, \000outw\t"
- "%ax, %dx\000outl\t%eax, \000outl\t%eax, %dx\000outb\t%al, \000outb\t%al"
- ", %dx\000pabsb\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t\000pb"
- "lendvb\t%xmm0, \000pblendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM1"
- "28rm PSEUDO!\000#PCMPESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000"
- "pcmpistri\t\000#PCMPISTRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pc"
- "mpistrm\t\000pextrb\t\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000"
- "phaddw\t\000phminposuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb"
- "\t\000pinsrd\t\000pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pm"
- "axud\t\000pmaxuw\t\000pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000p"
- "movsxbd\t\000pmovsxbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pm"
- "ovsxwq\t\000pmovzxbd\t\000pmovzxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmo"
- "vzxwd\t\000pmovzxwq\t\000pmuldq\t\000pmulhrsw\t\000pmulld\t\000popw\t\000"
- "popl\t\000popq\t\000popf\000prefetchnta\t\000prefetcht0\t\000prefetcht1"
- "\t\000prefetcht2\t\000pshufb\t\000pshufd\t\000pshufhw\t\000pshuflw\t\000"
- "psignb\t\000psignd\t\000psignw\t\000pslldq\t\000psrldq\t\000ptest \t\000"
- "punpckhqdq\t\000punpcklqdq\t\000pushw\t\000pushl\t\000pushq\t\000pushf\000"
- "rclw\t1, \000rclw\t%cl, \000rclw\t\000rcll\t1, \000rcll\t%cl, \000rcll\t"
- "\000rclq\t1, \000rclq\t%cl, \000rclq\t\000rclb\t1, \000rclb\t%cl, \000r"
- "clb\t\000rcpps\t\000rcpss\t\000rcrw\t1, \000rcrw\t%cl, \000rcrw\t\000rc"
- "rl\t1, \000rcrl\t%cl, \000rcrl\t\000rcrq\t1, \000rcrq\t%cl, \000rcrq\t\000"
- "rcrb\t1, \000rcrb\t%cl, \000rcrb\t\000rdtsc\000rep;movsb\000rep;movsl\000"
- "rep;movsq\000rep;movsw\000rep;stosb\000rep;stosl\000rep;stosq\000rep;st"
- "osw\000ret\000ret\t\000rolw\t\000rolw\t%cl, \000roll\t\000roll\t%cl, \000"
- "rolq\t\000rolq\t%cl, \000rolb\t\000rolb\t%cl, \000rorw\t\000rorw\t%cl, "
- "\000rorl\t\000rorl\t%cl, \000rorq\t\000rorq\t%cl, \000rorb\t\000rorb\t%"
- "cl, \000roundpd\t\000roundps\t\000roundsd\t\000roundss\t\000rsqrtps\t\000"
- "rsqrtss\t\000sahf\000sarw\t\000sarw\t%cl, \000sarl\t\000sarl\t%cl, \000"
- "sarq\t\000sarq\t%cl, \000sarb\t\000sarb\t%cl, \000sbbw\t\000sbbl\t\000s"
- "bbq\t\000sbbb\t\000scasw\000scasl\000scasq\000scasb\000setae\t\000seta\t"
- "\000setbe\t\000setb\t\000sete\t\000setge\t\000setg\t\000setle\t\000setl"
- "\t\000setne\t\000setno\t\000setnp\t\000setns\t\000seto\t\000setp\t\000s"
- "ets\t\000sfence\000shlw\t\000shlw\t%cl, \000shll\t\000shll\t%cl, \000sh"
- "lq\t\000shlq\t%cl, \000shrq\t\000shlb\t\000shlb\t%cl, \000shldw\t%cl, \000"
- "shldw\t\000shldl\t%cl, \000shldl\t\000shldq\t%cl, \000shldq\t\000shrw\t"
- "\000shrw\t%cl, \000shrl\t\000shrl\t%cl, \000shrq\t%cl, \000shrb\t\000sh"
- "rb\t%cl, \000shrdw\t%cl, \000shrdw\t\000shrdl\t%cl, \000shrdl\t\000shrd"
- "q\t%cl, \000shrdq\t\000shufpd\t\000shufps\t\000fsin\000sqrtpd\t\000sqrt"
- "ps\t\000sqrtsd\t\000sqrtss\t\000fsqrt\000stmxcsr\t\000fsts\t\000fstl\t\000"
+ "bswapl\t\000bswapq\t\000btw\t\000btl\t\000btq\t\000btcw\t\000btcl\t\000"
+ "btcq\t\000btrw\t\000btrl\t\000btrq\t\000btsw\t\000btsl\t\000btsq\t\000c"
+ "all\t*\000callq\t*\000callq\t\000call\t\000cbtw\000cltd\000cltq\000fchs"
+ "\000clc\000cld\000clflush\t\000cli\000clts\000cmc\000cmovaw\t\000cmoval"
+ "\t\000cmovaq\t\000cmovaew\t\000cmovael\t\000cmovaeq\t\000cmovbw\t\000cm"
+ "ovbl\t\000cmovbq\t\000cmovbew\t\000cmovbel\t\000cmovbeq\t\000fcmovbe\t\000"
+ "fcmovb\t\000cmovew\t\000cmovel\t\000cmoveq\t\000fcmove\t\000cmovgw\t\000"
+ "cmovgl\t\000cmovgq\t\000cmovgew\t\000cmovgel\t\000cmovgeq\t\000cmovlw\t"
+ "\000cmovll\t\000cmovlq\t\000cmovlew\t\000cmovlel\t\000cmovleq\t\000fcmo"
+ "vnbe\t\000fcmovnb\t\000cmovnew\t\000cmovnel\t\000cmovneq\t\000fcmovne\t"
+ "\000cmovnow\t\000cmovnol\t\000cmovnoq\t\000cmovnpw\t\000cmovnpl\t\000cm"
+ "ovnpq\t\000fcmovnu\t\000cmovnsw\t\000cmovnsl\t\000cmovnsq\t\000cmovow\t"
+ "\000cmovol\t\000cmovoq\t\000cmovpw\t\000cmovpl\t\000cmovpq\t\000fcmovu\t"
+ " \000cmovsw\t\000cmovsl\t\000cmovsq\t\000#CMOV_FR32 PSEUDO!\000#CMOV_FR"
+ "64 PSEUDO!\000#CMOV_GR8 PSEUDO!\000#CMOV_V1I64 PSEUDO!\000#CMOV_V2F64 P"
+ "SEUDO!\000#CMOV_V2I64 PSEUDO!\000#CMOV_V4F32 PSEUDO!\000cmpw\t\000cmpl\t"
+ "\000cmpq\t\000cmpb\t\000cmp\000cmpsw\000cmpsl\000cmpsq\000cmpsb\000cmpx"
+ "chg16b\t\000cmpxchgw\t\000cmpxchgl\t\000cmpxchgq\t\000cmpxchg8b\t\000cm"
+ "pxchgb\t\000comisd\t\000comiss\t\000fcomp\t\000fcomip\t\000fcomi\t\000f"
+ "com\t\000fcos\000cpuid\000cqto\000crc32 \t\000cvtdq2pd\t\000cvtdq2ps\t\000"
+ "cvtpd2dq\t\000cvtpd2ps\t\000cvtps2dq\t\000cvtps2pd\t\000cvtsd2siq\t\000"
+ "cvtsd2ss\t\000cvtsi2sdq\t\000cvtsi2sd\t\000cvtsi2ssq\t\000cvtsi2ss\t\000"
+ "cvtss2sd\t\000cvtss2siq\t\000cvtss2sil\t\000cvttps2dq\t\000cvttsd2siq\t"
+ "\000cvttsd2si\t\000cvttss2siq\t\000cvttss2si\t\000cwtd\000cwtl\000decw\t"
+ "\000decl\t\000decq\t\000decb\t\000divw\t\000divl\t\000divq\t\000divb\t\000"
+ "divpd\t\000divps\t\000fdivrs\t\000fdivrl\t\000fidivrs\t\000fidivrl\t\000"
+ "fdivp\t\000fdivr\t\000fdiv\t%st(0), \000divsd\t\000divss\t\000fdivs\t\000"
+ "fdivl\t\000fidivs\t\000fidivl\t\000fdivrp\t\000fdiv\t\000fdivr\t%st(0),"
+ " \000dppd\t\000dpps\t\000ret\t#eh_return, addr: \000enter\t\000extractp"
+ "s\t\000f2xm1\000lcallw\t\000lcallw\t*\000lcalll\t\000lcalll\t*\000lcall"
+ "q\t*\000ljmpw\t\000ljmpw\t*\000ljmpl\t\000ljmpl\t*\000ljmpq\t*\000fbld\t"
+ "\000fbstp\t\000fcoml\t\000fcomll\t\000fcompl\t\000fcompll\t\000fcompp\000"
+ "fdecstp\000ffree\t\000ficomw\t\000ficoml\t\000ficompw\t\000ficompl\t\000"
+ "fincstp\000fisttpl\t\000fldcw\t\000fldenv\t\000fldl2e\000fldl2t\000fldl"
+ "g2\000fldln2\000fldpi\000fnclex\000fninit\000fnop\000fnstcw\t\000fnstsw"
+ " %ax\000fnstsw\t\000##FP32_TO_INT16_IN_MEM PSEUDO!\000##FP32_TO_INT32_I"
+ "N_MEM PSEUDO!\000##FP32_TO_INT64_IN_MEM PSEUDO!\000##FP64_TO_INT16_IN_M"
+ "EM PSEUDO!\000##FP64_TO_INT32_IN_MEM PSEUDO!\000##FP64_TO_INT64_IN_MEM "
+ "PSEUDO!\000##FP80_TO_INT16_IN_MEM PSEUDO!\000##FP80_TO_INT32_IN_MEM PSE"
+ "UDO!\000##FP80_TO_INT64_IN_MEM PSEUDO!\000fpatan\000fprem\000fprem1\000"
+ "fptan\000##FP_REG_KILL\000frndint\000frstor\t\000fnsave\t\000fscale\000"
+ "fsincos\000fnstenv\t\000movl\t%fs:\000fxam\000fxrstor\t\000fxsave\t\000"
+ "fxtract\000fyl2x\000fyl2xp1\000pxor\t\000movapd\t\000movaps\t\000orpd\t"
+ "\000orps\t\000xorpd\t\000xorps\t\000movl\t%gs:\000haddpd\t\000haddps\t\000"
+ "hlt\000hsubpd\t\000hsubps\t\000idivw\t\000idivl\t\000idivq\t\000idivb\t"
+ "\000filds\t\000fildl\t\000fildll\t\000imulw\t\000imull\t\000imulq\t\000"
+ "imulb\t\000insw\000inw\t\000inw\t%dx, %ax\000insl\000inl\t\000inl\t%dx,"
+ " %eax\000insb\000inb\t\000inb\t%dx, %al\000incw\t\000incl\t\000incq\t\000"
+ "incb\t\000insertps\t\000int\t\000int\t3\000invd\000invept\000invlpg\000"
+ "invvpid\000iretw\000iretl\000iretq\000fisttps\t\000fisttpll\t\000fists\t"
+ "\000fistl\t\000fistps\t\000fistpl\t\000fistpll\t\000cvtpd2pi\t\000cvtpi"
+ "2pd\t\000cvtpi2ps\t\000cvtps2pi\t\000cvtsd2si\t\000cvtss2si\t\000cvttpd"
+ "2dq\t\000cvttpd2pi\t\000cvttps2pi\t\000ucomisd\t\000ucomiss\t\000ja\t\000"
+ "jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t\000jg\t\000jge\t\000jl\t\000jl"
+ "e\t\000jmp\t\000jmpl\t*\000jmpq\t*\000jmpq\t\000jne\t\000jno\t\000jnp\t"
+ "\000jns\t\000jo\t\000jp\t\000js\t\000lahf\000larw\t\000larl\t\000larq\t"
+ "\000lock\n\tcmpxchgw\t\000lock\n\tcmpxchgl\t\000lock\n\tcmpxchgq\t\000l"
+ "ock\n\tcmpxchgb\t\000lock\n\tcmpxchg8b\t\000lddqu\t\000ldmxcsr\t\000lds"
+ "w\t\000ldsl\t\000fldz\000fld1\000flds\t\000fldl\t\000fldt\t\000fld\t\000"
+ "leaw\t\000leal\t\000leaq\t\000leave\000lesw\t\000lesl\t\000lfence\000lf"
+ "sw\t\000lfsl\t\000lfsq\t\000lgdt\t\000lgsw\t\000lgsl\t\000lgsq\t\000lid"
+ "t\t\000lldtw\t\000lmsww\t\000lock\n\taddw\t\000lock\n\taddl\t\000lock\n"
+ "\taddq\t\000lock\n\taddb\t\000lock\n\tdecw\t\000lock\n\tdecl\t\000lock\n"
+ "\tdecq\t\000lock\n\tdecb\t\000lock\n\tincw\t\000lock\n\tincl\t\000lock\n"
+ "\tincq\t\000lock\n\tincb\t\000lock\n\tsubw\t\000lock\n\tsubl\t\000lock\n"
+ "\tsubq\t\000lock\n\tsubb\t\000lodsb\000lodsl\000lodsq\000lodsw\000loop\t"
+ "\000loope\t\000loopne\t\000lret\000lret\t\000lslw\t\000lsll\t\000lslq\t"
+ "\000lssw\t\000lssl\t\000lssq\t\000ltrw\t\000lock\n\txaddw\t\000lock\n\t"
+ "xaddl\t\000lock\n\txadd\t\000lock\n\txaddb\t\000maskmovdqu\t\000maxpd\t"
+ "\000maxps\t\000maxsd\t\000maxss\t\000mfence\000minpd\t\000minps\t\000mi"
+ "nsd\t\000minss\t\000emms\000femms\000maskmovq\t\000movd\t\000movdq2q\t\000"
+ "movntq\t\000movq2dq\t\000movq\t\000packssdw\t\000packsswb\t\000packuswb"
+ "\t\000paddb\t\000paddd\t\000paddq\t\000paddsb\t\000paddsw\t\000paddusb\t"
+ "\000paddusw\t\000paddw\t\000pandn\t\000pand\t\000pavgb\t\000pavgw\t\000"
+ "pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000pcmpgtd\t\000pcmpgt"
+ "w\t\000pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t\000pmaxub\t\000pmi"
+ "nsw\t\000pminub\t\000pmovmskb\t\000pmulhuw\t\000pmulhw\t\000pmullw\t\000"
+ "pmuludq\t\000por\t\000psadbw\t\000pshufw\t\000pslld\t\000psllq\t\000psl"
+ "lw\t\000psrad\t\000psraw\t\000psrld\t\000psrlq\t\000psrlw\t\000psubb\t\000"
+ "psubd\t\000psubq\t\000psubsb\t\000psubsw\t\000psubusb\t\000psubusw\t\000"
+ "psubw\t\000punpckhbw\t\000punpckhdq\t\000punpckhwd\t\000punpcklbw\t\000"
+ "punpckldq\t\000punpcklwd\t\000monitor\000movw\t%ax, \000movw\t\000movl\t"
+ "%eax, \000movl\t\000xorl\t\000movq\t%fs:\000movq\t%gs:\000movq\t%rax, \000"
+ "movabsq\t\000movb\t%al, \000movb\t\000xorb\t\000movddup\t\000movdqa\t\000"
+ "movdqu\t\000movhlps\t\000movhpd\t\000movhps\t\000movlhps\t\000movlpd\t\000"
+ "movsd\t\000movlps\t\000movss\t\000movmskpd\t\000movmskps\t\000movntdqa\t"
+ "\000movntdq\t\000movnti\t\000movntpd\t\000movntps\t\000movshdup\t\000mo"
+ "vsldup\t\000movsbw\t\000movswl\t\000movsbl\t\000movswq\t\000movslq\t\000"
+ "movsbq\t\000movupd\t\000movups\t\000movzbw\t\000movzbl\t\000movzwl\t\000"
+ "movzwq\t\000movzbq\t\000mpsadbw\t\000mulw\t\000mull\t\000mulq\t\000mulb"
+ "\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmuls\t\000fmull\t\000"
+ "fimuls\t\000fimull\t\000fmulp\t\000fmul\t\000fmul\t%st(0), \000mwait\000"
+ "negw\t\000negl\t\000negq\t\000negb\t\000nop\000nopl\t\000nopw\t\000notw"
+ "\t\000notl\t\000notq\t\000notb\t\000orw\t\000orl\t\000orq\t\000orb\t\000"
+ "outw\t%ax, \000outw\t%ax, %dx\000outl\t%eax, \000outl\t%eax, %dx\000out"
+ "b\t%al, \000outb\t%al, %dx\000outsb\000outsl\000outsw\000pabsb\t\000pab"
+ "sd\t\000pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t%xmm0, \000pble"
+ "ndw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PCMPES"
+ "TRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCMPIST"
+ "RM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb\t\000"
+ "pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000phminposuw"
+ "\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000pins"
+ "rq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t\000"
+ "pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000pmovsxbd\t\000pmovsxbq\t"
+ "\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzxbd\t\000"
+ "pmovzxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmovzxwd\t\000pmovzxwq\t\000p"
+ "muldq\t\000pmulhrsw\t\000pmulld\t\000popw\t\000popl\t\000popq\t\000popc"
+ "ntw\t\000popcntl\t\000popcntq\t\000popfw\000popfl\000popfq\000popw\t%fs"
+ "\000popl\t%fs\000popq\t%fs\000popw\t%gs\000popl\t%gs\000popq\t%gs\000pr"
+ "efetchnta\t\000prefetcht0\t\000prefetcht1\t\000prefetcht2\t\000pshufb\t"
+ "\000pshufd\t\000pshufhw\t\000pshuflw\t\000psignb\t\000psignd\t\000psign"
+ "w\t\000pslldq\t\000psrldq\t\000ptest \t\000punpckhqdq\t\000punpcklqdq\t"
+ "\000pushw\t\000pushl\t\000pushq\t\000pushfw\000pushfl\000pushfq\000push"
+ "w\t%fs\000pushl\t%fs\000pushq\t%fs\000pushw\t%gs\000pushl\t%gs\000pushq"
+ "\t%gs\000rclw\t1, \000rclw\t%cl, \000rclw\t\000rcll\t1, \000rcll\t%cl, "
+ "\000rcll\t\000rclq\t1, \000rclq\t%cl, \000rclq\t\000rclb\t1, \000rclb\t"
+ "%cl, \000rclb\t\000rcpps\t\000rcpss\t\000rcrw\t1, \000rcrw\t%cl, \000rc"
+ "rw\t\000rcrl\t1, \000rcrl\t%cl, \000rcrl\t\000rcrq\t1, \000rcrq\t%cl, \000"
+ "rcrq\t\000rcrb\t1, \000rcrb\t%cl, \000rcrb\t\000rdmsr\000rdpmc\000rdtsc"
+ "\000rep;movsb\000rep;movsl\000rep;movsq\000rep;movsw\000rep;stosb\000re"
+ "p;stosl\000rep;stosq\000rep;stosw\000ret\000ret\t\000rolw\t\000rolw\t%c"
+ "l, \000roll\t\000roll\t%cl, \000rolq\t\000rolq\t%cl, \000rolb\t\000rolb"
+ "\t%cl, \000rorw\t\000rorw\t%cl, \000rorl\t\000rorl\t%cl, \000rorq\t\000"
+ "rorq\t%cl, \000rorb\t\000rorb\t%cl, \000roundpd\t\000roundps\t\000round"
+ "sd\t\000roundss\t\000rsm\000rsqrtps\t\000rsqrtss\t\000sahf\000sarw\t\000"
+ "sarw\t%cl, \000sarl\t\000sarl\t%cl, \000sarq\t\000sarq\t%cl, \000sarb\t"
+ "\000sarb\t%cl, \000sbbw\t\000sbbl\t\000sbbq\t\000sbbb\t\000scasw\000sca"
+ "sl\000scasq\000scasb\000setae\t\000seta\t\000setbe\t\000setb\t\000sete\t"
+ "\000setge\t\000setg\t\000setle\t\000setl\t\000setne\t\000setno\t\000set"
+ "np\t\000setns\t\000seto\t\000setp\t\000sets\t\000sfence\000sgdt\t\000sh"
+ "lw\t\000shlw\t%cl, \000shll\t\000shll\t%cl, \000shlq\t\000shlq\t%cl, \000"
+ "shlb\t\000shlb\t%cl, \000shldw\t%cl, \000shldw\t\000shldl\t%cl, \000shl"
+ "dl\t\000shldq\t%cl, \000shldq\t\000shrw\t\000shrw\t%cl, \000shrl\t\000s"
+ "hrl\t%cl, \000shrq\t\000shrq\t%cl, \000shrb\t\000shrb\t%cl, \000shrdw\t"
+ "%cl, \000shrdw\t\000shrdl\t%cl, \000shrdl\t\000shrdq\t%cl, \000shrdq\t\000"
+ "shufpd\t\000shufps\t\000sidt\t\000fsin\000sldtw\t\000sldtq\t\000smsww\t"
+ "\000smswl\t\000smswq\t\000sqrtpd\t\000sqrtps\t\000sqrtsd\t\000sqrtss\t\000"
+ "fsqrt\000stc\000std\000sti\000stmxcsr\t\000strw\t\000fsts\t\000fstl\t\000"
"fstps\t\000fstpl\t\000fstpt\t\000fstp\t\000fst\t\000subw\t\000subl\t\000"
"subq\t\000subb\t\000subpd\t\000subps\t\000fsubrs\t\000fsubrl\t\000fisub"
"rs\t\000fisubrl\t\000fsubp\t\000fsubr\t\000fsub\t%st(0), \000subsd\t\000"
"subss\t\000fsubs\t\000fsubl\t\000fisubs\t\000fisubl\t\000fsubrp\t\000fs"
- "ub\t\000fsubr\t%st(0), \000syscall\000sysenter\000sysexit\000sysret\000"
- "jmp\t*\000#TC_RETURN \000testw\t\000testl\t\000testq\t\000testb\t\000.b"
- "yte\t0x66; leaq\t\000ud2\000ftst\000fucomip\t\000fucomi\t\000fucompp\000"
- "fucomp\t\000fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t\000unpckl"
- "ps\t\000#VASTART_SAVE_XMM_REGS \000wait\000xchgw\t\000xchgl\t\000xchg\t"
- "\000xchgb\t\000fxch\t\000xorw\t\000xorq\t\000";
+ "ub\t\000fsubr\t%st(0), \000swpgs\000syscall\000sysenter\000sysexit\000s"
+ "ysret\000jmp\t*\000#TC_RETURN \000testw\t\000testl\t\000testq\t\000test"
+ "b\t\000.byte\t0x66; leaq\t\000ud2\000ftst\000fucomip\t\000fucomi\t\000f"
+ "ucompp\000fucomp\t\000fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t"
+ "\000unpcklps\t\000#VASTART_SAVE_XMM_REGS \000verr\t\000verw\t\000vmcall"
+ "\000vmclear\t\000vmlaunch\000vmptrld\t\000vmptrst\t\000vmreadl\t\000vmr"
+ "eadq\t\000vmresume\000vmwritel\t\000vmwriteq\t\000vmxoff\000vmxon\t\000"
+ "wait\000wbinvd\000wrmsr\000xaddw\t\000xaddl\t\000xaddq\t\000xaddb\t\000"
+ "xchgw\t\000xchgl\t\000xchgq\t\000xchgb\t\000fxch\t\000xlatb\000xorw\t\000"
+ "xorq\t\000";
#ifndef NO_ASM_WRITER_BOILERPLATE
@@ -2428,10 +2722,10 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
// Emit the opcode for the instruction.
unsigned Bits = OpInfo[MI->getOpcode()];
assert(Bits != 0 && "Cannot print this instruction.");
- O << AsmStrs+(Bits & 8191)-1;
+ O << AsmStrs+(Bits & 16383)-1;
- // Fragment 0 encoded into 6 bits for 41 unique commands.
+ // Fragment 0 encoded into 6 bits for 43 unique commands.
switch ((Bits >> 26) & 63) {
default: // unreachable.
case 0:
@@ -2447,7 +2741,7 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 5);
break;
case 3:
- // ADC16ri, ADC16ri8, ADC16rr, ADC32ri, ADC32ri8, ADC32rr, ADC64ri32, ADC...
+ // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A...
printOperand(MI, 2);
O << ", ";
break;
@@ -2533,7 +2827,7 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 18:
- // BSF16rm, BSR16rm, CMP16rm, LAR16rm, LAR32rm, LAR64rm, MOV16rm, MOV16sm...
+ // BSF16rm, BSR16rm, CMP16rm, LAR16rm, LAR32rm, LAR64rm, LSL16rm, MOV16rm...
printi16mem(MI, 1);
O << ", ";
printOperand(MI, 0);
@@ -2543,7 +2837,6 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
// BSF16rr, BSF32rr, BSF64rr, BSR16rr, BSR32rr, BSR64rr, BT16ri8, BT16rr,...
printOperand(MI, 1);
O << ", ";
- printOperand(MI, 0);
break;
case 20:
// BSF32rm, BSR32rm, CMP32rm, CVTSI2SDrm, CVTSI2SSrm, FS_MOV32rm, GS_MOV3...
@@ -2560,7 +2853,7 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 22:
- // CALL64m, DEC64m, DIV64m, IDIV64m, ILD_F64m, IMUL64m, INC64m, ISTT_FP64...
+ // CALL64m, CMPXCHG8B, DEC64m, DIV64m, IDIV64m, ILD_F64m, IMUL64m, INC64m...
printi64mem(MI, 0);
return;
break;
@@ -2574,7 +2867,7 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 25:
- // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX32rm8, MOVSX64rm8, MOVZX32_NOREXrm8...
+ // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8W, MOVSX32rm8, MOVSX64rm8, MOV...
printi8mem(MI, 1);
O << ", ";
printOperand(MI, 0);
@@ -2588,81 +2881,93 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
printSSECC(MI, 3);
break;
case 28:
- // COMISDrm, CVTDQ2PDrm, CVTDQ2PSrm, CVTPD2DQrm, CVTPS2DQrm, FsMOVAPDrm, ...
+ // CMPXCHG16B
+ printi128mem(MI, 0);
+ return;
+ break;
+ case 29:
+ // COMISDrm, COMISSrm, CVTDQ2PDrm, CVTDQ2PSrm, CVTPD2DQrm, CVTPD2PSrm, CV...
printf128mem(MI, 1);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 29:
- // CVTSD2SSrm, CVTTSD2SI64rm, CVTTSD2SIrm, Int_CVTPS2PDrm, Int_CVTPS2PIrm...
+ case 30:
+ // CVTPS2PDrm, CVTSD2SI64rm, CVTSD2SSrm, CVTTSD2SI64rm, CVTTSD2SIrm, Int_...
printf64mem(MI, 1);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 30:
- // CVTSS2SDrm, CVTTSS2SI64rm, CVTTSS2SIrm, Int_CVTSS2SI64rm, Int_CVTSS2SI...
+ case 31:
+ // CVTSS2SDrm, CVTSS2SI64rm, CVTSS2SIrm, CVTTSS2SI64rm, CVTTSS2SIrm, Int_...
printf32mem(MI, 1);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 31:
+ case 32:
// EXTRACTPSmr, IMUL16rmi, IMUL16rmi8, IMUL32rmi, IMUL32rmi8, IMUL64rmi32...
printOperand(MI, 6);
O << ", ";
break;
- case 32:
- // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64
+ case 33:
+ // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, FXR...
printopaquemem(MI, 0);
return;
break;
- case 33:
+ case 34:
// Int_CVTDQ2PSrm, LDDQUrm, MOVDQArm, MOVDQUrm, MOVDQUrm_Int, MOVNTDQArm,...
printi128mem(MI, 1);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 34:
+ case 35:
+ // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm...
+ printopaquemem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 36:
// LD_F80m, ST_FP80m
printf80mem(MI, 0);
return;
break;
- case 35:
+ case 37:
// LEA16r, LEA32r
printlea32mem(MI, 1);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 36:
+ case 38:
// LEA64_32r
printlea64_32mem(MI, 1);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 37:
+ case 39:
// LEA64r
printlea64mem(MI, 1);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 38:
+ case 40:
// RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi
printOperand(MI, 10);
O << ", ";
break;
- case 39:
+ case 41:
// TLS_addr32
printlea32mem(MI, 0);
O << ", %eax; call\t___tls_get_addr at PLT";
return;
break;
- case 40:
+ case 42:
// TLS_addr64
printlea64mem(MI, 0);
O << "(%rip), %rdi; .word\t0x6666; rex64; call\t__tls_get_addr at PLT";
@@ -2684,9 +2989,8 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
O << ", ";
break;
case 2:
- // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32...
+ // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, A...
printOperand(MI, 0);
- return;
break;
case 3:
// ADC32i32, ADD32i32, AND32i32, CMP32i32, IN32ri, MOV32o32a, OR32i32, SB...
@@ -2694,7 +2998,7 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 4:
- // ADC64i32, ADD64i32, AND64i32, CMP64i32, MOV64o32a, MOV64o8a, OR64i32, ...
+ // ADC64i32, ADD64i32, AND64i32, CMP64i32, MOV64o64a, MOV64o8a, OR64i32, ...
O << ", %rax";
return;
break;
@@ -2704,7 +3008,7 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 6:
- // ADD_FI32m, ADD_FPrST0, ADD_FST0r, ADD_FrST0, BSF16rr, BSF32rr, BSF64rr...
+ // ADD_FI32m, ADD_FPrST0, ADD_FST0r, ADD_FrST0, BSWAP32r, BSWAP64r, CALL3...
return;
break;
case 7:
@@ -2745,16 +3049,25 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
O << ", ";
break;
case 15:
- // IMUL16rmi, IMUL16rmi8, LXADD16, XCHG16rm
+ // IMUL16rmi, IMUL16rmi8
printi16mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
break;
case 16:
- // IMUL32rmi, IMUL32rmi8, LXADD32, XCHG32rm
+ // IMUL32rmi, IMUL32rmi8
printi32mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
break;
case 17:
- // IMUL64rmi32, IMUL64rmi8, LXADD64, MMX_PSHUFWmi, XCHG64rm
+ // IMUL64rmi32, IMUL64rmi8, MMX_PSHUFWmi
printi64mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
break;
case 18:
// INSERTPSrm, ROUNDSSm_Int
@@ -2770,107 +3083,95 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 20:
- // LXADD8, XCHG8rm
- printi8mem(MI, 1);
- return;
+ // LXADD16, MMX_PINSRWrmi, PINSRWrmi, XCHG16rm
+ printi16mem(MI, 2);
break;
case 21:
- // MMX_PINSRWrmi, PINSRWrmi
- printi16mem(MI, 2);
- O << ", ";
- printOperand(MI, 0);
- return;
+ // LXADD32, PINSRDrm, XCHG32rm
+ printi32mem(MI, 2);
break;
case 22:
- // MOV8rm_NOREX, MOV8rr_NOREX, MOVZX32_NOREXrm8, MOVZX32_NOREXrr8
- O << " # NOREX";
- return;
+ // LXADD64, PALIGNR64rm, PINSRQrm, XCHG64rm
+ printi64mem(MI, 2);
break;
case 23:
- // PALIGNR64rm, PINSRQrm
- printi64mem(MI, 2);
- O << ", ";
- printOperand(MI, 0);
- return;
+ // LXADD8, PINSRBrm, XCHG8rm
+ printi8mem(MI, 2);
break;
case 24:
- // PCMPESTRIArm, PCMPESTRICrm, PCMPESTRIOrm, PCMPESTRISrm, PCMPESTRIZrm, ...
- printi128mem(MI, 1);
- O << ", ";
- printOperand(MI, 0);
+ // MOV8rm_NOREX, MOVZX32_NOREXrm8
+ O << " # NOREX";
return;
break;
case 25:
- // PINSRBrm
- printi8mem(MI, 2);
+ // PCMPESTRIArm, PCMPESTRICrm, PCMPESTRIOrm, PCMPESTRISrm, PCMPESTRIZrm, ...
+ printi128mem(MI, 1);
O << ", ";
printOperand(MI, 0);
return;
break;
case 26:
- // PINSRDrm
- printi32mem(MI, 2);
- O << ", ";
- printOperand(MI, 0);
- return;
- break;
- case 27:
// RCL16mi, RCR16mi
printi16mem(MI, 0);
return;
break;
- case 28:
+ case 27:
// RCL32mi, RCR32mi
printi32mem(MI, 0);
return;
break;
- case 29:
+ case 28:
// RCL64mi, RCR64mi
printi64mem(MI, 0);
return;
break;
- case 30:
+ case 29:
// RCL8mi, RCR8mi
printi8mem(MI, 0);
return;
break;
- case 31:
+ case 30:
// ROUNDPDm_Int, ROUNDPSm_Int
printf128mem(MI, 1);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 32:
+ case 31:
// ROUNDSDm_Int
printf64mem(MI, 2);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 33:
+ case 32:
// SHUFPDrmi, SHUFPSrmi
printf128mem(MI, 2);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 34:
+ case 33:
// TAILJMPd, TAILJMPm, TAILJMPr, TAILJMPr64
O << " # TAILCALL";
return;
break;
- case 35:
+ case 34:
// TCRETURNdi, TCRETURNdi64, TCRETURNri, TCRETURNri64
O << ' ';
printOperand(MI, 1);
return;
break;
+ case 35:
+ // XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr
+ printOperand(MI, 2);
+ return;
+ break;
}
- // Fragment 2 encoded into 4 bits for 16 unique commands.
- switch ((Bits >> 16) & 15) {
+ // Fragment 2 encoded into 5 bits for 17 unique commands.
+ switch ((Bits >> 15) & 31) {
default: // unreachable.
case 0:
// ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16...
@@ -2878,51 +3179,51 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 1:
+ // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, A...
+ return;
+ break;
+ case 2:
// ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, AND32mi, AND32...
printi32mem(MI, 0);
return;
break;
- case 2:
+ case 3:
// ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,...
printi64mem(MI, 0);
return;
break;
- case 3:
- // ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CMP8mi, CMP8mr, LCMPXC...
+ case 4:
+ // ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CMP8mi, CMP8mr, CMPXCH...
printi8mem(MI, 0);
break;
- case 4:
+ case 5:
// CMPPDrmi, CMPPSrmi
printf128mem(MI, 2);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 5:
+ case 6:
// CMPPDrri, CMPPSrri, CMPSDrr, CMPSSrr, Int_CMPSDrr, Int_CMPSSrr
printOperand(MI, 2);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 6:
+ case 7:
// CMPSDrm, Int_CMPSDrm
printf64mem(MI, 2);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 7:
+ case 8:
// CMPSSrm, Int_CMPSSrm
printf32mem(MI, 2);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 8:
- // CRC32m16, CRC32m32, CRC32m8, CRC32r16, CRC32r32, CRC32r8, CRC64m64, CR...
- return;
- break;
case 9:
// ENTER, FARCALL16i, FARCALL32i, FARJMP16i, FARJMP32i, VASTART_SAVE_XMM_...
printOperand(MI, 1);
@@ -2933,7 +3234,7 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 11:
- // EXTRACTPSrr, IMUL16rmi, IMUL16rmi8, IMUL16rri, IMUL16rri8, IMUL32rmi, ...
+ // EXTRACTPSrr, IMUL16rri, IMUL16rri8, IMUL32rri, IMUL32rri8, IMUL64rri32...
O << ", ";
printOperand(MI, 0);
return;
@@ -2944,43 +3245,78 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 13:
+ // MOV8rr_NOREX, MOVZX32_NOREXrr8
+ O << " # NOREX";
+ return;
+ break;
+ case 14:
// MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVUPDmr, MOVUPDmr_Int, MOVUPSmr, MOVUP...
printf128mem(MI, 0);
return;
break;
- case 14:
+ case 15:
// MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr, MOVNTPSmr
printi128mem(MI, 0);
return;
break;
- case 15:
+ case 16:
// MOVHPDmr, MOVHPSmr, MOVLPDmr, MOVLPSmr, MOVPD2SDmr, MOVSDmr
printf64mem(MI, 0);
return;
break;
}
-
- // Fragment 3 encoded into 2 bits for 3 unique commands.
- switch ((Bits >> 14) & 3) {
- default: // unreachable.
- case 0:
- // ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CMP8mi, CMP8mr, ENTER,...
- return;
- break;
- case 1:
- // MOV8mr_NOREX
+ switch (MI->getOpcode()) {
+ case X86::ADC8mi:
+ case X86::ADC8mr:
+ case X86::ADD8mi:
+ case X86::ADD8mr:
+ case X86::AND8mi:
+ case X86::AND8mr:
+ case X86::CMP8mi:
+ case X86::CMP8mr:
+ case X86::CMPXCHG8rm:
+ case X86::ENTER:
+ case X86::FARCALL16i:
+ case X86::FARCALL32i:
+ case X86::FARJMP16i:
+ case X86::FARJMP32i:
+ case X86::LCMPXCHG8:
+ case X86::LOCK_ADD8mi:
+ case X86::LOCK_ADD8mr:
+ case X86::LOCK_SUB8mi:
+ case X86::LOCK_SUB8mr:
+ case X86::MOV8mi:
+ case X86::MOV8mr:
+ case X86::OR8mi:
+ case X86::OR8mr:
+ case X86::PEXTRBmr:
+ case X86::ROL8mi:
+ case X86::ROR8mi:
+ case X86::SAR8mi:
+ case X86::SBB8mi:
+ case X86::SBB8mr:
+ case X86::SHL8mi:
+ case X86::SHR8mi:
+ case X86::SUB8mi:
+ case X86::SUB8mr:
+ case X86::TEST8mi:
+ case X86::XADD8rm:
+ case X86::XOR8mi:
+ case X86::XOR8mr:
+ return;
+ break;
+ case X86::MOV8mr_NOREX:
O << " # NOREX";
return;
break;
- case 2:
- // VASTART_SAVE_XMM_REGS
+ case X86::VASTART_SAVE_XMM_REGS:
O << ", ";
printOperand(MI, 2);
return;
break;
}
-
+ return;
}
@@ -2988,35 +3324,40 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
/// from the register set description. This returns the assembler name
/// for the specified register.
const char *X86ATTInstPrinter::getRegisterName(unsigned RegNo) {
- assert(RegNo && RegNo < 134 && "Invalid register number!");
+ assert(RegNo && RegNo < 159 && "Invalid register number!");
static const unsigned RegAsmOffset[] = {
0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37, 40,
- 43, 47, 50, 53, 56, 60, 64, 68, 72, 76, 80, 86, 90, 93,
- 97, 101, 105, 109, 113, 117, 121, 125, 129, 132, 135, 138, 142, 146,
- 150, 154, 158, 162, 166, 170, 174, 179, 184, 189, 193, 198, 203, 208,
- 212, 217, 222, 227, 231, 236, 241, 246, 250, 255, 260, 265, 269, 274,
- 279, 284, 287, 291, 295, 299, 302, 306, 310, 314, 318, 322, 326, 330,
- 334, 338, 342, 346, 350, 353, 357, 360, 364, 367, 373, 379, 385, 391,
- 397, 403, 409, 415, 420, 425, 431, 437, 443, 449, 455, 461, 466, 471,
- 476, 481, 486, 491, 496, 501, 506, 511, 517, 523, 529, 535, 541, 547,
- 552, 557, 562, 567, 572, 577, 582, 0
+ 43, 47, 50, 54, 58, 62, 66, 70, 74, 78, 82, 85, 88, 92,
+ 96, 100, 105, 110, 115, 120, 125, 130, 135, 140, 144, 148, 152, 158,
+ 162, 165, 169, 173, 177, 181, 185, 189, 193, 197, 201, 204, 207, 210,
+ 214, 218, 222, 226, 230, 234, 238, 242, 246, 251, 256, 261, 265, 270,
+ 275, 280, 284, 289, 294, 299, 303, 308, 313, 318, 322, 327, 332, 337,
+ 341, 346, 351, 356, 359, 363, 367, 371, 374, 378, 382, 386, 390, 394,
+ 398, 403, 408, 413, 418, 423, 428, 433, 438, 443, 447, 451, 455, 459,
+ 463, 467, 470, 474, 477, 481, 484, 490, 496, 502, 508, 514, 520, 526,
+ 532, 537, 542, 548, 554, 560, 566, 572, 578, 583, 588, 593, 598, 603,
+ 608, 613, 618, 623, 628, 634, 640, 646, 652, 658, 664, 669, 674, 679,
+ 684, 689, 694, 699, 0
};
const char *AsmStrs =
"ah\000al\000ax\000bh\000bl\000bp\000bpl\000bx\000ch\000cl\000cs\000cx\000"
- "dh\000di\000dil\000dl\000ds\000dx\000eax\000ebp\000ebx\000ecx\000edi\000"
- "edx\000flags\000eip\000es\000esi\000esp\000fp0\000fp1\000fp2\000fp3\000"
- "fp4\000fp5\000fp6\000fs\000gs\000ip\000mm0\000mm1\000mm2\000mm3\000mm4\000"
- "mm5\000mm6\000mm7\000r10\000r10b\000r10d\000r10w\000r11\000r11b\000r11d"
- "\000r11w\000r12\000r12b\000r12d\000r12w\000r13\000r13b\000r13d\000r13w\000"
- "r14\000r14b\000r14d\000r14w\000r15\000r15b\000r15d\000r15w\000r8\000r8b"
- "\000r8d\000r8w\000r9\000r9b\000r9d\000r9w\000rax\000rbp\000rbx\000rcx\000"
- "rdi\000rdx\000rip\000rsi\000rsp\000si\000sil\000sp\000spl\000ss\000st(0"
- ")\000st(1)\000st(2)\000st(3)\000st(4)\000st(5)\000st(6)\000st(7)\000xmm"
- "0\000xmm1\000xmm10\000xmm11\000xmm12\000xmm13\000xmm14\000xmm15\000xmm2"
- "\000xmm3\000xmm4\000xmm5\000xmm6\000xmm7\000xmm8\000xmm9\000ymm0\000ymm"
- "1\000ymm10\000ymm11\000ymm12\000ymm13\000ymm14\000ymm15\000ymm2\000ymm3"
- "\000ymm4\000ymm5\000ymm6\000ymm7\000ymm8\000ymm9\000";
+ "dh\000di\000dil\000dl\000dr0\000dr1\000dr2\000dr3\000dr4\000dr5\000dr6\000"
+ "dr7\000ds\000dx\000eax\000ebp\000ebx\000ecr0\000ecr1\000ecr2\000ecr3\000"
+ "ecr4\000ecr5\000ecr6\000ecr7\000ecx\000edi\000edx\000flags\000eip\000es"
+ "\000esi\000esp\000fp0\000fp1\000fp2\000fp3\000fp4\000fp5\000fp6\000fs\000"
+ "gs\000ip\000mm0\000mm1\000mm2\000mm3\000mm4\000mm5\000mm6\000mm7\000r10"
+ "\000r10b\000r10d\000r10w\000r11\000r11b\000r11d\000r11w\000r12\000r12b\000"
+ "r12d\000r12w\000r13\000r13b\000r13d\000r13w\000r14\000r14b\000r14d\000r"
+ "14w\000r15\000r15b\000r15d\000r15w\000r8\000r8b\000r8d\000r8w\000r9\000"
+ "r9b\000r9d\000r9w\000rax\000rbp\000rbx\000rcr0\000rcr1\000rcr2\000rcr3\000"
+ "rcr4\000rcr5\000rcr6\000rcr7\000rcr8\000rcx\000rdi\000rdx\000rip\000rsi"
+ "\000rsp\000si\000sil\000sp\000spl\000ss\000st(0)\000st(1)\000st(2)\000s"
+ "t(3)\000st(4)\000st(5)\000st(6)\000st(7)\000xmm0\000xmm1\000xmm10\000xm"
+ "m11\000xmm12\000xmm13\000xmm14\000xmm15\000xmm2\000xmm3\000xmm4\000xmm5"
+ "\000xmm6\000xmm7\000xmm8\000xmm9\000ymm0\000ymm1\000ymm10\000ymm11\000y"
+ "mm12\000ymm13\000ymm14\000ymm15\000ymm2\000ymm3\000ymm4\000ymm5\000ymm6"
+ "\000ymm7\000ymm8\000ymm9\000";
return AsmStrs+RegAsmOffset[RegNo-1];
}
diff --git a/libclamav/c++/X86GenAsmWriter1.inc b/libclamav/c++/X86GenAsmWriter1.inc
index 9113f72..6c71a8e 100644
--- a/libclamav/c++/X86GenAsmWriter1.inc
+++ b/libclamav/c++/X86GenAsmWriter1.inc
@@ -33,6 +33,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
138543120U, // ADC16ri8
138674192U, // ADC16rm
138543120U, // ADC16rr
+ 138543120U, // ADC16rr_REV
134217749U, // ADC32i32
406847504U, // ADC32mi
406847504U, // ADC32mi8
@@ -41,6 +42,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
138543120U, // ADC32ri8
138805264U, // ADC32rm
138543120U, // ADC32rr
+ 138543120U, // ADC32rr_REV
134217760U, // ADC64i32
541065232U, // ADC64mi32
541065232U, // ADC64mi8
@@ -49,12 +51,14 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
138543120U, // ADC64ri8
138936336U, // ADC64rm
138543120U, // ADC64rr
+ 138543120U, // ADC64rr_REV
134217771U, // ADC8i8
675282960U, // ADC8mi
675282960U, // ADC8mr
138543120U, // ADC8ri
139067408U, // ADC8rm
138543120U, // ADC8rr
+ 138543120U, // ADC8rr_REV
134217781U, // ADD16i16
272629823U, // ADD16mi
272629823U, // ADD16mi8
@@ -138,6 +142,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
138543316U, // AND16ri8
138674388U, // AND16rm
138543316U, // AND16rr
+ 138543316U, // AND16rr_REV
134217945U, // AND32i32
406847700U, // AND32mi
406847700U, // AND32mi8
@@ -146,6 +151,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
138543316U, // AND32ri8
138805460U, // AND32rm
138543316U, // AND32rr
+ 138543316U, // AND32rr_REV
134217956U, // AND64i32
541065428U, // AND64mi32
541065428U, // AND64mi8
@@ -154,12 +160,14 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
138543316U, // AND64ri8
138936532U, // AND64rm
138543316U, // AND64rr
+ 138543316U, // AND64rr_REV
134217967U, // AND8i8
675283156U, // AND8mi
675283156U, // AND8mr
138543316U, // AND8ri
139067604U, // AND8rm
138543316U, // AND8rr
+ 138543316U, // AND8rr_REV
139198713U, // ANDNPDrm
138543353U, // ANDNPDrr
139198721U, // ANDNPSrm
@@ -226,284 +234,357 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
134218737U, // BSWAP32r
134218737U, // BSWAP64r
272630776U, // BT16mi8
+ 272630776U, // BT16mr
139854840U, // BT16ri8
139854840U, // BT16rr
406848504U, // BT32mi8
+ 406848504U, // BT32mr
139854840U, // BT32ri8
139854840U, // BT32rr
541066232U, // BT64mi8
+ 541066232U, // BT64mr
139854840U, // BT64ri8
139854840U, // BT64rr
- 402654204U, // CALL32m
- 134218748U, // CALL32r
- 536871932U, // CALL64m
- 1073742844U, // CALL64pcrel32
- 134218748U, // CALL64r
- 1073742844U, // CALLpcrel32
- 1026U, // CBW
- 1030U, // CDQ
- 1034U, // CDQE
- 1039U, // CHS_F
+ 272630780U, // BTC16mi8
+ 272630780U, // BTC16mr
+ 139854844U, // BTC16ri8
+ 139854844U, // BTC16rr
+ 406848508U, // BTC32mi8
+ 406848508U, // BTC32mr
+ 139854844U, // BTC32ri8
+ 139854844U, // BTC32rr
+ 541066236U, // BTC64mi8
+ 541066236U, // BTC64mr
+ 139854844U, // BTC64ri8
+ 139854844U, // BTC64rr
+ 272630785U, // BTR16mi8
+ 272630785U, // BTR16mr
+ 139854849U, // BTR16ri8
+ 139854849U, // BTR16rr
+ 406848513U, // BTR32mi8
+ 406848513U, // BTR32mr
+ 139854849U, // BTR32ri8
+ 139854849U, // BTR32rr
+ 541066241U, // BTR64mi8
+ 541066241U, // BTR64mr
+ 139854849U, // BTR64ri8
+ 139854849U, // BTR64rr
+ 272630790U, // BTS16mi8
+ 272630790U, // BTS16mr
+ 139854854U, // BTS16ri8
+ 139854854U, // BTS16rr
+ 406848518U, // BTS32mi8
+ 406848518U, // BTS32mr
+ 139854854U, // BTS32ri8
+ 139854854U, // BTS32rr
+ 541066246U, // BTS64mi8
+ 541066246U, // BTS64mr
+ 139854854U, // BTS64ri8
+ 139854854U, // BTS64rr
+ 402654219U, // CALL32m
+ 134218763U, // CALL32r
+ 536871947U, // CALL64m
+ 1073742859U, // CALL64pcrel32
+ 134218763U, // CALL64r
+ 1073742859U, // CALLpcrel32
+ 1041U, // CBW
+ 1045U, // CDQ
+ 1049U, // CDQE
+ 1054U, // CHS_F
0U, // CHS_Fp32
0U, // CHS_Fp64
0U, // CHS_Fp80
- 671089684U, // CLFLUSH
- 138675229U, // CMOVA16rm
- 138544157U, // CMOVA16rr
- 138806301U, // CMOVA32rm
- 138544157U, // CMOVA32rr
- 138937373U, // CMOVA64rm
- 138544157U, // CMOVA64rr
- 138675236U, // CMOVAE16rm
- 138544164U, // CMOVAE16rr
- 138806308U, // CMOVAE32rm
- 138544164U, // CMOVAE32rr
- 138937380U, // CMOVAE64rm
- 138544164U, // CMOVAE64rr
- 138675244U, // CMOVB16rm
- 138544172U, // CMOVB16rr
- 138806316U, // CMOVB32rm
- 138544172U, // CMOVB32rr
- 138937388U, // CMOVB64rm
- 138544172U, // CMOVB64rr
- 138675251U, // CMOVBE16rm
- 138544179U, // CMOVBE16rr
- 138806323U, // CMOVBE32rm
- 138544179U, // CMOVBE32rr
- 138937395U, // CMOVBE64rm
- 138544179U, // CMOVBE64rr
- 134218811U, // CMOVBE_F
+ 1059U, // CLC
+ 1063U, // CLD
+ 671089707U, // CLFLUSH
+ 1076U, // CLI
+ 1080U, // CLTS
+ 1085U, // CMC
+ 138675265U, // CMOVA16rm
+ 138544193U, // CMOVA16rr
+ 138806337U, // CMOVA32rm
+ 138544193U, // CMOVA32rr
+ 138937409U, // CMOVA64rm
+ 138544193U, // CMOVA64rr
+ 138675272U, // CMOVAE16rm
+ 138544200U, // CMOVAE16rr
+ 138806344U, // CMOVAE32rm
+ 138544200U, // CMOVAE32rr
+ 138937416U, // CMOVAE64rm
+ 138544200U, // CMOVAE64rr
+ 138675280U, // CMOVB16rm
+ 138544208U, // CMOVB16rr
+ 138806352U, // CMOVB32rm
+ 138544208U, // CMOVB32rr
+ 138937424U, // CMOVB64rm
+ 138544208U, // CMOVB64rr
+ 138675287U, // CMOVBE16rm
+ 138544215U, // CMOVBE16rr
+ 138806359U, // CMOVBE32rm
+ 138544215U, // CMOVBE32rr
+ 138937431U, // CMOVBE64rm
+ 138544215U, // CMOVBE64rr
+ 134218847U, // CMOVBE_F
0U, // CMOVBE_Fp32
0U, // CMOVBE_Fp64
0U, // CMOVBE_Fp80
- 134218828U, // CMOVB_F
+ 134218864U, // CMOVB_F
0U, // CMOVB_Fp32
0U, // CMOVB_Fp64
0U, // CMOVB_Fp80
- 138675292U, // CMOVE16rm
- 138544220U, // CMOVE16rr
- 138806364U, // CMOVE32rm
- 138544220U, // CMOVE32rr
- 138937436U, // CMOVE64rm
- 138544220U, // CMOVE64rr
- 134218851U, // CMOVE_F
+ 138675328U, // CMOVE16rm
+ 138544256U, // CMOVE16rr
+ 138806400U, // CMOVE32rm
+ 138544256U, // CMOVE32rr
+ 138937472U, // CMOVE64rm
+ 138544256U, // CMOVE64rr
+ 134218887U, // CMOVE_F
0U, // CMOVE_Fp32
0U, // CMOVE_Fp64
0U, // CMOVE_Fp80
- 138675315U, // CMOVG16rm
- 138544243U, // CMOVG16rr
- 138806387U, // CMOVG32rm
- 138544243U, // CMOVG32rr
- 138937459U, // CMOVG64rm
- 138544243U, // CMOVG64rr
- 138675322U, // CMOVGE16rm
- 138544250U, // CMOVGE16rr
- 138806394U, // CMOVGE32rm
- 138544250U, // CMOVGE32rr
- 138937466U, // CMOVGE64rm
- 138544250U, // CMOVGE64rr
- 138675330U, // CMOVL16rm
- 138544258U, // CMOVL16rr
- 138806402U, // CMOVL32rm
- 138544258U, // CMOVL32rr
- 138937474U, // CMOVL64rm
- 138544258U, // CMOVL64rr
- 138675337U, // CMOVLE16rm
- 138544265U, // CMOVLE16rr
- 138806409U, // CMOVLE32rm
- 138544265U, // CMOVLE32rr
- 138937481U, // CMOVLE64rm
- 138544265U, // CMOVLE64rr
- 134218897U, // CMOVNBE_F
+ 138675351U, // CMOVG16rm
+ 138544279U, // CMOVG16rr
+ 138806423U, // CMOVG32rm
+ 138544279U, // CMOVG32rr
+ 138937495U, // CMOVG64rm
+ 138544279U, // CMOVG64rr
+ 138675358U, // CMOVGE16rm
+ 138544286U, // CMOVGE16rr
+ 138806430U, // CMOVGE32rm
+ 138544286U, // CMOVGE32rr
+ 138937502U, // CMOVGE64rm
+ 138544286U, // CMOVGE64rr
+ 138675366U, // CMOVL16rm
+ 138544294U, // CMOVL16rr
+ 138806438U, // CMOVL32rm
+ 138544294U, // CMOVL32rr
+ 138937510U, // CMOVL64rm
+ 138544294U, // CMOVL64rr
+ 138675373U, // CMOVLE16rm
+ 138544301U, // CMOVLE16rr
+ 138806445U, // CMOVLE32rm
+ 138544301U, // CMOVLE32rr
+ 138937517U, // CMOVLE64rm
+ 138544301U, // CMOVLE64rr
+ 134218933U, // CMOVNBE_F
0U, // CMOVNBE_Fp32
0U, // CMOVNBE_Fp64
0U, // CMOVNBE_Fp80
- 134218915U, // CMOVNB_F
+ 134218951U, // CMOVNB_F
0U, // CMOVNB_Fp32
0U, // CMOVNB_Fp64
0U, // CMOVNB_Fp80
- 138675380U, // CMOVNE16rm
- 138544308U, // CMOVNE16rr
- 138806452U, // CMOVNE32rm
- 138544308U, // CMOVNE32rr
- 138937524U, // CMOVNE64rm
- 138544308U, // CMOVNE64rr
- 134218940U, // CMOVNE_F
+ 138675416U, // CMOVNE16rm
+ 138544344U, // CMOVNE16rr
+ 138806488U, // CMOVNE32rm
+ 138544344U, // CMOVNE32rr
+ 138937560U, // CMOVNE64rm
+ 138544344U, // CMOVNE64rr
+ 134218976U, // CMOVNE_F
0U, // CMOVNE_Fp32
0U, // CMOVNE_Fp64
0U, // CMOVNE_Fp80
- 138675405U, // CMOVNO16rm
- 138544333U, // CMOVNO16rr
- 138806477U, // CMOVNO32rm
- 138544333U, // CMOVNO32rr
- 138937549U, // CMOVNO64rm
- 138544333U, // CMOVNO64rr
- 138675413U, // CMOVNP16rm
- 138544341U, // CMOVNP16rr
- 138806485U, // CMOVNP32rm
- 138544341U, // CMOVNP32rr
- 138937557U, // CMOVNP64rm
- 138544341U, // CMOVNP64rr
- 134218973U, // CMOVNP_F
+ 138675441U, // CMOVNO16rm
+ 138544369U, // CMOVNO16rr
+ 138806513U, // CMOVNO32rm
+ 138544369U, // CMOVNO32rr
+ 138937585U, // CMOVNO64rm
+ 138544369U, // CMOVNO64rr
+ 138675449U, // CMOVNP16rm
+ 138544377U, // CMOVNP16rr
+ 138806521U, // CMOVNP32rm
+ 138544377U, // CMOVNP32rr
+ 138937593U, // CMOVNP64rm
+ 138544377U, // CMOVNP64rr
+ 134219009U, // CMOVNP_F
0U, // CMOVNP_Fp32
0U, // CMOVNP_Fp64
0U, // CMOVNP_Fp80
- 138675438U, // CMOVNS16rm
- 138544366U, // CMOVNS16rr
- 138806510U, // CMOVNS32rm
- 138544366U, // CMOVNS32rr
- 138937582U, // CMOVNS64rm
- 138544366U, // CMOVNS64rr
- 138675446U, // CMOVO16rm
- 138544374U, // CMOVO16rr
- 138806518U, // CMOVO32rm
- 138544374U, // CMOVO32rr
- 138937590U, // CMOVO64rm
- 138544374U, // CMOVO64rr
- 138675453U, // CMOVP16rm
- 138544381U, // CMOVP16rr
- 138806525U, // CMOVP32rm
- 138544381U, // CMOVP32rr
- 138937597U, // CMOVP64rm
- 138544381U, // CMOVP64rr
- 134219012U, // CMOVP_F
+ 138675474U, // CMOVNS16rm
+ 138544402U, // CMOVNS16rr
+ 138806546U, // CMOVNS32rm
+ 138544402U, // CMOVNS32rr
+ 138937618U, // CMOVNS64rm
+ 138544402U, // CMOVNS64rr
+ 138675482U, // CMOVO16rm
+ 138544410U, // CMOVO16rr
+ 138806554U, // CMOVO32rm
+ 138544410U, // CMOVO32rr
+ 138937626U, // CMOVO64rm
+ 138544410U, // CMOVO64rr
+ 138675489U, // CMOVP16rm
+ 138544417U, // CMOVP16rr
+ 138806561U, // CMOVP32rm
+ 138544417U, // CMOVP32rr
+ 138937633U, // CMOVP64rm
+ 138544417U, // CMOVP64rr
+ 134219048U, // CMOVP_F
0U, // CMOVP_Fp32
0U, // CMOVP_Fp64
0U, // CMOVP_Fp80
- 138675477U, // CMOVS16rm
- 138544405U, // CMOVS16rr
- 138806549U, // CMOVS32rm
- 138544405U, // CMOVS32rr
- 138937621U, // CMOVS64rm
- 138544405U, // CMOVS64rr
- 1308U, // CMOV_FR32
- 1327U, // CMOV_FR64
- 1346U, // CMOV_GR8
- 1364U, // CMOV_V1I64
- 1384U, // CMOV_V2F64
- 1404U, // CMOV_V2I64
- 1424U, // CMOV_V4F32
- 134219172U, // CMP16i16
- 272631214U, // CMP16mi
- 272631214U, // CMP16mi8
- 272631214U, // CMP16mr
- 139855278U, // CMP16mrmrr
- 139855278U, // CMP16ri
- 139855278U, // CMP16ri8
- 139724206U, // CMP16rm
- 139855278U, // CMP16rr
- 134219187U, // CMP32i32
- 406848942U, // CMP32mi
- 406848942U, // CMP32mi8
- 406848942U, // CMP32mr
- 139855278U, // CMP32mrmrr
- 139855278U, // CMP32ri
- 139855278U, // CMP32ri8
- 139986350U, // CMP32rm
- 139855278U, // CMP32rr
- 134219198U, // CMP64i32
- 541066670U, // CMP64mi32
- 541066670U, // CMP64mi8
- 541066670U, // CMP64mr
- 139855278U, // CMP64mrmrr
- 139855278U, // CMP64ri32
- 139855278U, // CMP64ri8
- 140117422U, // CMP64rm
- 139855278U, // CMP64rr
- 134219209U, // CMP8i8
- 675284398U, // CMP8mi
- 675284398U, // CMP8mr
- 139855278U, // CMP8mrmrr
- 139855278U, // CMP8ri
- 140248494U, // CMP8rm
- 139855278U, // CMP8rr
- 1221330387U, // CMPPDrmi
- 1354892755U, // CMPPDrri
- 1225524691U, // CMPPSrmi
- 1359087059U, // CMPPSrri
- 1495U, // CMPS16
- 1495U, // CMPS32
- 1495U, // CMPS64
- 1495U, // CMPS8
- 1229850067U, // CMPSDrm
- 1363281363U, // CMPSDrr
- 1234175443U, // CMPSSrm
- 1367475667U, // CMPSSrr
- 140379612U, // COMISDrm
- 139855324U, // COMISDrr
- 1508U, // COS_F
+ 138675513U, // CMOVS16rm
+ 138544441U, // CMOVS16rr
+ 138806585U, // CMOVS32rm
+ 138544441U, // CMOVS32rr
+ 138937657U, // CMOVS64rm
+ 138544441U, // CMOVS64rr
+ 1344U, // CMOV_FR32
+ 1363U, // CMOV_FR64
+ 1382U, // CMOV_GR8
+ 1400U, // CMOV_V1I64
+ 1420U, // CMOV_V2F64
+ 1440U, // CMOV_V2I64
+ 1460U, // CMOV_V4F32
+ 134219208U, // CMP16i16
+ 272631250U, // CMP16mi
+ 272631250U, // CMP16mi8
+ 272631250U, // CMP16mr
+ 139855314U, // CMP16mrmrr
+ 139855314U, // CMP16ri
+ 139855314U, // CMP16ri8
+ 139724242U, // CMP16rm
+ 139855314U, // CMP16rr
+ 134219223U, // CMP32i32
+ 406848978U, // CMP32mi
+ 406848978U, // CMP32mi8
+ 406848978U, // CMP32mr
+ 139855314U, // CMP32mrmrr
+ 139855314U, // CMP32ri
+ 139855314U, // CMP32ri8
+ 139986386U, // CMP32rm
+ 139855314U, // CMP32rr
+ 134219234U, // CMP64i32
+ 541066706U, // CMP64mi32
+ 541066706U, // CMP64mi8
+ 541066706U, // CMP64mr
+ 139855314U, // CMP64mrmrr
+ 139855314U, // CMP64ri32
+ 139855314U, // CMP64ri8
+ 140117458U, // CMP64rm
+ 139855314U, // CMP64rr
+ 134219245U, // CMP8i8
+ 675284434U, // CMP8mi
+ 675284434U, // CMP8mr
+ 139855314U, // CMP8mrmrr
+ 139855314U, // CMP8ri
+ 140248530U, // CMP8rm
+ 139855314U, // CMP8rr
+ 1221330423U, // CMPPDrmi
+ 1354892791U, // CMPPDrri
+ 1225524727U, // CMPPSrmi
+ 1359087095U, // CMPPSrri
+ 1531U, // CMPS16
+ 1531U, // CMPS32
+ 1531U, // CMPS64
+ 1531U, // CMPS8
+ 1229850103U, // CMPSDrm
+ 1363281399U, // CMPSDrr
+ 1234175479U, // CMPSSrm
+ 1367475703U, // CMPSSrr
+ 1476396544U, // CMPXCHG16B
+ 272631308U, // CMPXCHG16rm
+ 139855372U, // CMPXCHG16rr
+ 406849036U, // CMPXCHG32rm
+ 139855372U, // CMPXCHG32rr
+ 541066764U, // CMPXCHG64rm
+ 139855372U, // CMPXCHG64rr
+ 536872469U, // CMPXCHG8B
+ 675284492U, // CMPXCHG8rm
+ 139855372U, // CMPXCHG8rr
+ 140379680U, // COMISDrm
+ 139855392U, // COMISDrr
+ 140379688U, // COMISSrm
+ 139855400U, // COMISSrr
+ 134219312U, // COMP_FST0r
+ 134219319U, // COM_FIPr
+ 134219335U, // COM_FIr
+ 134219350U, // COM_FST0r
+ 1628U, // COS_F
0U, // COS_Fp32
0U, // COS_Fp64
0U, // COS_Fp80
- 1513U, // CQO
- 1505756653U, // CRC32m16
- 1509950957U, // CRC32m32
- 1514145261U, // CRC32m8
- 1518339565U, // CRC32r16
- 1518339565U, // CRC32r32
- 1518339565U, // CRC32r8
- 1522533869U, // CRC64m64
- 1518339565U, // CRC64r64
- 140379637U, // CVTDQ2PDrm
- 139855349U, // CVTDQ2PDrr
- 140379647U, // CVTDQ2PSrm
- 139855359U, // CVTDQ2PSrr
- 140379657U, // CVTPD2DQrm
- 139855369U, // CVTPD2DQrr
- 140379667U, // CVTPS2DQrm
- 139855379U, // CVTPS2DQrr
- 140510749U, // CVTSD2SSrm
- 139855389U, // CVTSD2SSrr
- 140117543U, // CVTSI2SD64rm
- 139855399U, // CVTSI2SD64rr
- 139986471U, // CVTSI2SDrm
- 139855399U, // CVTSI2SDrr
- 140117553U, // CVTSI2SS64rm
- 139855409U, // CVTSI2SS64rr
- 139986481U, // CVTSI2SSrm
- 139855409U, // CVTSI2SSrr
- 140641851U, // CVTSS2SDrm
- 139855419U, // CVTSS2SDrr
- 140510789U, // CVTTSD2SI64rm
- 139855429U, // CVTTSD2SI64rr
- 140510789U, // CVTTSD2SIrm
- 139855429U, // CVTTSD2SIrr
- 140641872U, // CVTTSS2SI64rm
- 139855440U, // CVTTSS2SI64rr
- 140641872U, // CVTTSS2SIrm
- 139855440U, // CVTTSS2SIrr
- 1627U, // CWD
- 1631U, // CWDE
- 268437092U, // DEC16m
- 134219364U, // DEC16r
- 402654820U, // DEC32m
- 134219364U, // DEC32r
- 268437092U, // DEC64_16m
- 134219364U, // DEC64_16r
- 402654820U, // DEC64_32m
- 134219364U, // DEC64_32r
- 536872548U, // DEC64m
- 134219364U, // DEC64r
- 671090276U, // DEC8m
- 134219364U, // DEC8r
- 268437097U, // DIV16m
- 134219369U, // DIV16r
- 402654825U, // DIV32m
- 134219369U, // DIV32r
- 536872553U, // DIV64m
- 134219369U, // DIV64r
- 671090281U, // DIV8m
- 134219369U, // DIV8r
- 139200110U, // DIVPDrm
- 138544750U, // DIVPDrr
- 139200117U, // DIVPSrm
- 138544757U, // DIVPSrr
- 805308028U, // DIVR_F32m
- 939525756U, // DIVR_F64m
- 268437123U, // DIVR_FI16m
- 402654851U, // DIVR_FI32m
- 134219403U, // DIVR_FPrST0
- 134219388U, // DIVR_FST0r
+ 1633U, // CPUID
+ 1639U, // CQO
+ 1639974507U, // CRC32m16
+ 1644168811U, // CRC32m32
+ 1648363115U, // CRC32m8
+ 1652557419U, // CRC32r16
+ 1652557419U, // CRC32r32
+ 1652557419U, // CRC32r8
+ 1656751723U, // CRC64m64
+ 1652557419U, // CRC64r64
+ 140379763U, // CVTDQ2PDrm
+ 139855475U, // CVTDQ2PDrr
+ 140379773U, // CVTDQ2PSrm
+ 139855485U, // CVTDQ2PSrr
+ 140379783U, // CVTPD2DQrm
+ 139855495U, // CVTPD2DQrr
+ 140379793U, // CVTPD2PSrm
+ 139855505U, // CVTPD2PSrr
+ 140379803U, // CVTPS2DQrm
+ 139855515U, // CVTPS2DQrr
+ 140510885U, // CVTPS2PDrm
+ 139855525U, // CVTPS2PDrr
+ 140510895U, // CVTSD2SI64rm
+ 139855535U, // CVTSD2SI64rr
+ 140510905U, // CVTSD2SSrm
+ 139855545U, // CVTSD2SSrr
+ 140117699U, // CVTSI2SD64rm
+ 139855555U, // CVTSI2SD64rr
+ 139986627U, // CVTSI2SDrm
+ 139855555U, // CVTSI2SDrr
+ 140117709U, // CVTSI2SS64rm
+ 139855565U, // CVTSI2SS64rr
+ 139986637U, // CVTSI2SSrm
+ 139855565U, // CVTSI2SSrr
+ 140642007U, // CVTSS2SDrm
+ 139855575U, // CVTSS2SDrr
+ 140642017U, // CVTSS2SI64rm
+ 139855585U, // CVTSS2SI64rr
+ 140642017U, // CVTSS2SIrm
+ 139855585U, // CVTSS2SIrr
+ 140379883U, // CVTTPS2DQrm
+ 139855595U, // CVTTPS2DQrr
+ 140510966U, // CVTTSD2SI64rm
+ 139855606U, // CVTTSD2SI64rr
+ 140510966U, // CVTTSD2SIrm
+ 139855606U, // CVTTSD2SIrr
+ 140642049U, // CVTTSS2SI64rm
+ 139855617U, // CVTTSS2SI64rr
+ 140642049U, // CVTTSS2SIrm
+ 139855617U, // CVTTSS2SIrr
+ 1804U, // CWD
+ 1808U, // CWDE
+ 268437269U, // DEC16m
+ 134219541U, // DEC16r
+ 402654997U, // DEC32m
+ 134219541U, // DEC32r
+ 268437269U, // DEC64_16m
+ 134219541U, // DEC64_16r
+ 402654997U, // DEC64_32m
+ 134219541U, // DEC64_32r
+ 536872725U, // DEC64m
+ 134219541U, // DEC64r
+ 671090453U, // DEC8m
+ 134219541U, // DEC8r
+ 268437274U, // DIV16m
+ 134219546U, // DIV16r
+ 402655002U, // DIV32m
+ 134219546U, // DIV32r
+ 536872730U, // DIV64m
+ 134219546U, // DIV64r
+ 671090458U, // DIV8m
+ 134219546U, // DIV8r
+ 139200287U, // DIVPDrm
+ 138544927U, // DIVPDrr
+ 139200294U, // DIVPSrm
+ 138544934U, // DIVPSrr
+ 805308205U, // DIVR_F32m
+ 939525933U, // DIVR_F64m
+ 268437300U, // DIVR_FI16m
+ 402655028U, // DIVR_FI32m
+ 134219580U, // DIVR_FPrST0
+ 134219565U, // DIVR_FST0r
0U, // DIVR_Fp32m
0U, // DIVR_Fp64m
0U, // DIVR_Fp64m32
@@ -515,21 +596,21 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIVR_FpI32m32
0U, // DIVR_FpI32m64
0U, // DIVR_FpI32m80
- 142607996U, // DIVR_FrST0
- 139331219U, // DIVSDrm
- 139331219U, // DIVSDrm_Int
- 138544787U, // DIVSDrr
- 138544787U, // DIVSDrr_Int
- 139462298U, // DIVSSrm
- 139462298U, // DIVSSrm_Int
- 138544794U, // DIVSSrr
- 138544794U, // DIVSSrr_Int
- 805308065U, // DIV_F32m
- 939525793U, // DIV_F64m
- 268437159U, // DIV_FI16m
- 402654887U, // DIV_FI32m
- 134219438U, // DIV_FPrST0
- 134219425U, // DIV_FST0r
+ 142608173U, // DIVR_FrST0
+ 139331396U, // DIVSDrm
+ 139331396U, // DIVSDrm_Int
+ 138544964U, // DIVSDrr
+ 138544964U, // DIVSDrr_Int
+ 139462475U, // DIVSSrm
+ 139462475U, // DIVSSrm_Int
+ 138544971U, // DIVSSrr
+ 138544971U, // DIVSSrr_Int
+ 805308242U, // DIV_F32m
+ 939525970U, // DIV_F64m
+ 268437336U, // DIV_FI16m
+ 402655064U, // DIV_FI32m
+ 134219615U, // DIV_FPrST0
+ 134219602U, // DIV_FST0r
0U, // DIV_Fp32
0U, // DIV_Fp32m
0U, // DIV_Fp64
@@ -544,56 +625,82 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIV_FpI32m32
0U, // DIV_FpI32m64
0U, // DIV_FpI32m80
- 142608033U, // DIV_FrST0
- 139609781U, // DPPDrmi
- 138561205U, // DPPDrri
- 139609787U, // DPPSrmi
- 138561211U, // DPPSrri
- 134219457U, // EH_RETURN
- 134219457U, // EH_RETURN64
- 139855576U, // ENTER
- 809518815U, // EXTRACTPSmr
- 139871967U, // EXTRACTPSrr
- 139855594U, // FARCALL16i
- 1610614506U, // FARCALL16m
- 139855594U, // FARCALL32i
- 1610614506U, // FARCALL32m
- 1610614506U, // FARCALL64
- 139855601U, // FARJMP16i
- 1610614513U, // FARJMP16m
- 139855601U, // FARJMP32i
- 1610614513U, // FARJMP32m
- 1610614513U, // FARJMP64
- 805308151U, // FBLDm
- 805308157U, // FBSTPm
- 805308164U, // FCOM32m
- 939525892U, // FCOM64m
- 805308170U, // FCOMP32m
- 939525898U, // FCOMP64m
- 268437265U, // FICOM16m
- 402654993U, // FICOM32m
- 268437272U, // FICOMP16m
- 402655000U, // FICOMP32m
- 402655008U, // FISTTP32m
- 268437288U, // FLDCW16m
- 805308207U, // FLDENVm
- 268437303U, // FNSTCW16m
- 1855U, // FNSTSW8r
- 1862U, // FP32_TO_INT16_IN_MEM
- 1893U, // FP32_TO_INT32_IN_MEM
- 1924U, // FP32_TO_INT64_IN_MEM
- 1955U, // FP64_TO_INT16_IN_MEM
- 1986U, // FP64_TO_INT32_IN_MEM
- 2017U, // FP64_TO_INT64_IN_MEM
- 2048U, // FP80_TO_INT16_IN_MEM
- 2079U, // FP80_TO_INT32_IN_MEM
- 2110U, // FP80_TO_INT64_IN_MEM
- 2141U, // FP_REG_KILL
- 805308523U, // FRSTORm
- 805308531U, // FSAVEm
- 805308538U, // FSTENVm
- 805308546U, // FSTSWm
- 1795164297U, // FS_MOV32rm
+ 142608210U, // DIV_FrST0
+ 139609958U, // DPPDrmi
+ 138561382U, // DPPDrri
+ 139609964U, // DPPSrmi
+ 138561388U, // DPPSrri
+ 134219634U, // EH_RETURN
+ 134219634U, // EH_RETURN64
+ 139855753U, // ENTER
+ 809518992U, // EXTRACTPSmr
+ 139872144U, // EXTRACTPSrr
+ 1947U, // F2XM1
+ 139855777U, // FARCALL16i
+ 1744832417U, // FARCALL16m
+ 139855777U, // FARCALL32i
+ 1744832417U, // FARCALL32m
+ 1744832417U, // FARCALL64
+ 139855784U, // FARJMP16i
+ 1744832424U, // FARJMP16m
+ 139855784U, // FARJMP32i
+ 1744832424U, // FARJMP32m
+ 1744832424U, // FARJMP64
+ 805308334U, // FBLDm
+ 805308340U, // FBSTPm
+ 805307990U, // FCOM32m
+ 939525718U, // FCOM64m
+ 805307952U, // FCOMP32m
+ 939525680U, // FCOMP64m
+ 1979U, // FCOMPP
+ 1986U, // FDECSTP
+ 134219722U, // FFREE
+ 268437457U, // FICOM16m
+ 402655185U, // FICOM32m
+ 268437464U, // FICOMP16m
+ 402655192U, // FICOMP32m
+ 2016U, // FINCSTP
+ 402655208U, // FISTTP32m
+ 268437488U, // FLDCW16m
+ 805308407U, // FLDENVm
+ 2047U, // FLDL2E
+ 2054U, // FLDL2T
+ 2061U, // FLDLG2
+ 2068U, // FLDLN2
+ 2075U, // FLDPI
+ 2081U, // FNCLEX
+ 2088U, // FNINIT
+ 2095U, // FNOP
+ 268437556U, // FNSTCW16m
+ 2108U, // FNSTSW8r
+ 805308487U, // FNSTSWm
+ 2127U, // FP32_TO_INT16_IN_MEM
+ 2158U, // FP32_TO_INT32_IN_MEM
+ 2189U, // FP32_TO_INT64_IN_MEM
+ 2220U, // FP64_TO_INT16_IN_MEM
+ 2251U, // FP64_TO_INT32_IN_MEM
+ 2282U, // FP64_TO_INT64_IN_MEM
+ 2313U, // FP80_TO_INT16_IN_MEM
+ 2344U, // FP80_TO_INT32_IN_MEM
+ 2375U, // FP80_TO_INT64_IN_MEM
+ 2406U, // FPATAN
+ 2413U, // FPREM
+ 2419U, // FPREM1
+ 2426U, // FPTAN
+ 2432U, // FP_REG_KILL
+ 2446U, // FRNDINT
+ 805308822U, // FRSTORm
+ 805308830U, // FSAVEm
+ 2470U, // FSCALE
+ 2477U, // FSINCOS
+ 805308853U, // FSTENVm
+ 1879050686U, // FS_MOV32rm
+ 2504U, // FXAM
+ 1744832973U, // FXRSTOR
+ 1744832982U, // FXSAVE
+ 2526U, // FXTRACT
+ 2534U, // FYL2X
+ 2540U, // FYL2XP1
0U, // FpGET_ST0_32
0U, // FpGET_ST0_64
0U, // FpGET_ST0_80
@@ -614,40 +721,41 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
138543369U, // FsANDPDrr
139198736U, // FsANDPSrm
138543376U, // FsANDPSrr
- 140773523U, // FsFLD0SD
- 140773523U, // FsFLD0SS
- 140380313U, // FsMOVAPDrm
- 139856025U, // FsMOVAPDrr
- 140380321U, // FsMOVAPSrm
- 139856033U, // FsMOVAPSrr
- 139200681U, // FsORPDrm
- 138545321U, // FsORPDrr
- 139200687U, // FsORPSrm
- 138545327U, // FsORPSrr
- 139200693U, // FsXORPDrm
- 138545333U, // FsXORPDrr
- 139200700U, // FsXORPSrm
- 138545340U, // FsXORPSrr
- 1795164355U, // GS_MOV32rm
- 139200717U, // HADDPDrm
- 138545357U, // HADDPDrr
- 139200725U, // HADDPSrm
- 138545365U, // HADDPSrr
- 139200733U, // HSUBPDrm
- 138545373U, // HSUBPDrr
- 139200741U, // HSUBPSrm
- 138545381U, // HSUBPSrr
- 268437741U, // IDIV16m
- 134220013U, // IDIV16r
- 402655469U, // IDIV32m
- 134220013U, // IDIV32r
- 536873197U, // IDIV64m
- 134220013U, // IDIV64r
- 671090925U, // IDIV8m
- 134220013U, // IDIV8r
- 268437747U, // ILD_F16m
- 402655475U, // ILD_F32m
- 536873203U, // ILD_F64m
+ 140773876U, // FsFLD0SD
+ 140773876U, // FsFLD0SS
+ 140380666U, // FsMOVAPDrm
+ 139856378U, // FsMOVAPDrr
+ 140380674U, // FsMOVAPSrm
+ 139856386U, // FsMOVAPSrr
+ 139201034U, // FsORPDrm
+ 138545674U, // FsORPDrr
+ 139201040U, // FsORPSrm
+ 138545680U, // FsORPSrr
+ 139201046U, // FsXORPDrm
+ 138545686U, // FsXORPDrr
+ 139201053U, // FsXORPSrm
+ 138545693U, // FsXORPSrr
+ 1879050788U, // GS_MOV32rm
+ 139201070U, // HADDPDrm
+ 138545710U, // HADDPDrr
+ 139201078U, // HADDPSrm
+ 138545718U, // HADDPSrr
+ 2622U, // HLT
+ 139201090U, // HSUBPDrm
+ 138545730U, // HSUBPDrr
+ 139201098U, // HSUBPSrm
+ 138545738U, // HSUBPSrr
+ 268438098U, // IDIV16m
+ 134220370U, // IDIV16r
+ 402655826U, // IDIV32m
+ 134220370U, // IDIV32r
+ 536873554U, // IDIV64m
+ 134220370U, // IDIV64r
+ 671091282U, // IDIV8m
+ 134220370U, // IDIV8r
+ 268438104U, // ILD_F16m
+ 402655832U, // ILD_F32m
+ 536873560U, // ILD_F64m
0U, // ILD_Fp16m32
0U, // ILD_Fp16m64
0U, // ILD_Fp16m80
@@ -657,57 +765,67 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ILD_Fp64m32
0U, // ILD_Fp64m64
0U, // ILD_Fp64m80
- 268437753U, // IMUL16m
- 134220025U, // IMUL16r
- 138676473U, // IMUL16rm
- 139741433U, // IMUL16rmi
- 139741433U, // IMUL16rmi8
- 138545401U, // IMUL16rr
- 139872505U, // IMUL16rri
- 139872505U, // IMUL16rri8
- 402655481U, // IMUL32m
- 134220025U, // IMUL32r
- 138807545U, // IMUL32rm
- 140003577U, // IMUL32rmi
- 140003577U, // IMUL32rmi8
- 138545401U, // IMUL32rr
- 139872505U, // IMUL32rri
- 139872505U, // IMUL32rri8
- 536873209U, // IMUL64m
- 134220025U, // IMUL64r
- 138938617U, // IMUL64rm
- 140134649U, // IMUL64rmi32
- 140134649U, // IMUL64rmi8
- 138545401U, // IMUL64rr
- 139872505U, // IMUL64rri32
- 139872505U, // IMUL64rri8
- 671090937U, // IMUL8m
- 134220025U, // IMUL8r
- 134220031U, // IN16ri
- 2312U, // IN16rr
- 134220052U, // IN32ri
- 2334U, // IN32rr
- 134220075U, // IN8ri
- 2356U, // IN8rr
- 268437824U, // INC16m
- 134220096U, // INC16r
- 402655552U, // INC32m
- 134220096U, // INC32r
- 268437824U, // INC64_16m
- 134220096U, // INC64_16r
- 402655552U, // INC64_32m
- 134220096U, // INC64_32r
- 536873280U, // INC64m
- 134220096U, // INC64r
- 671091008U, // INC8m
- 134220096U, // INC8r
- 139479365U, // INSERTPSrm
- 138561861U, // INSERTPSrr
- 134220111U, // INT
- 2388U, // INT3
- 268437280U, // ISTT_FP16m
- 402655008U, // ISTT_FP32m
- 536872736U, // ISTT_FP64m
+ 268438110U, // IMUL16m
+ 134220382U, // IMUL16r
+ 138676830U, // IMUL16rm
+ 139741790U, // IMUL16rmi
+ 139741790U, // IMUL16rmi8
+ 138545758U, // IMUL16rr
+ 139872862U, // IMUL16rri
+ 139872862U, // IMUL16rri8
+ 402655838U, // IMUL32m
+ 134220382U, // IMUL32r
+ 138807902U, // IMUL32rm
+ 140003934U, // IMUL32rmi
+ 140003934U, // IMUL32rmi8
+ 138545758U, // IMUL32rr
+ 139872862U, // IMUL32rri
+ 139872862U, // IMUL32rri8
+ 536873566U, // IMUL64m
+ 134220382U, // IMUL64r
+ 138938974U, // IMUL64rm
+ 140135006U, // IMUL64rmi32
+ 140135006U, // IMUL64rmi8
+ 138545758U, // IMUL64rr
+ 139872862U, // IMUL64rri32
+ 139872862U, // IMUL64rri8
+ 671091294U, // IMUL8m
+ 134220382U, // IMUL8r
+ 2660U, // IN16
+ 134220392U, // IN16ri
+ 2673U, // IN16rr
+ 2660U, // IN32
+ 134220413U, // IN32ri
+ 2695U, // IN32rr
+ 2660U, // IN8
+ 134220436U, // IN8ri
+ 2717U, // IN8rr
+ 268438185U, // INC16m
+ 134220457U, // INC16r
+ 402655913U, // INC32m
+ 134220457U, // INC32r
+ 268438185U, // INC64_16m
+ 134220457U, // INC64_16r
+ 402655913U, // INC64_32m
+ 134220457U, // INC64_32r
+ 536873641U, // INC64m
+ 134220457U, // INC64r
+ 671091369U, // INC8m
+ 134220457U, // INC8r
+ 139479726U, // INSERTPSrm
+ 138562222U, // INSERTPSrr
+ 134220472U, // INT
+ 2749U, // INT3
+ 2755U, // INVD
+ 2760U, // INVEPT
+ 2767U, // INVLPG
+ 2774U, // INVVPID
+ 2782U, // IRET16
+ 2782U, // IRET32
+ 2782U, // IRET64
+ 268437480U, // ISTT_FP16m
+ 402655208U, // ISTT_FP32m
+ 536872936U, // ISTT_FP64m
0U, // ISTT_Fp16m32
0U, // ISTT_Fp16m64
0U, // ISTT_Fp16m80
@@ -717,11 +835,11 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ISTT_Fp64m32
0U, // ISTT_Fp64m64
0U, // ISTT_Fp64m80
- 268437850U, // IST_F16m
- 402655578U, // IST_F32m
- 268437856U, // IST_FP16m
- 402655584U, // IST_FP32m
- 536873312U, // IST_FP64m
+ 268438243U, // IST_F16m
+ 402655971U, // IST_F32m
+ 268438249U, // IST_FP16m
+ 402655977U, // IST_FP32m
+ 536873705U, // IST_FP64m
0U, // IST_Fp16m32
0U, // IST_Fp16m64
0U, // IST_Fp16m80
@@ -731,132 +849,135 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // IST_Fp64m32
0U, // IST_Fp64m64
0U, // IST_Fp64m80
- 1229850067U, // Int_CMPSDrm
- 1363281363U, // Int_CMPSDrr
- 1234175443U, // Int_CMPSSrm
- 1367475667U, // Int_CMPSSrr
- 140379612U, // Int_COMISDrm
- 139855324U, // Int_COMISDrr
- 140380519U, // Int_COMISSrm
- 139856231U, // Int_COMISSrr
- 140117493U, // Int_CVTDQ2PDrm
- 139855349U, // Int_CVTDQ2PDrr
- 140903935U, // Int_CVTDQ2PSrm
- 139855359U, // Int_CVTDQ2PSrr
- 140379657U, // Int_CVTPD2DQrm
- 139855369U, // Int_CVTPD2DQrr
- 140380527U, // Int_CVTPD2PIrm
- 139856239U, // Int_CVTPD2PIrr
- 140380537U, // Int_CVTPD2PSrm
- 139856249U, // Int_CVTPD2PSrr
- 140118403U, // Int_CVTPI2PDrm
- 139856259U, // Int_CVTPI2PDrr
- 138938765U, // Int_CVTPI2PSrm
- 138545549U, // Int_CVTPI2PSrr
- 140379667U, // Int_CVTPS2DQrm
- 139855379U, // Int_CVTPS2DQrr
- 140511639U, // Int_CVTPS2PDrm
- 139856279U, // Int_CVTPS2PDrr
- 140511649U, // Int_CVTPS2PIrm
- 139856289U, // Int_CVTPS2PIrr
- 140380587U, // Int_CVTSD2SI64rm
- 139856299U, // Int_CVTSD2SI64rr
- 140380587U, // Int_CVTSD2SIrm
- 139856299U, // Int_CVTSD2SIrr
- 139331101U, // Int_CVTSD2SSrm
- 138544669U, // Int_CVTSD2SSrr
- 138937895U, // Int_CVTSI2SD64rm
- 138544679U, // Int_CVTSI2SD64rr
- 138806823U, // Int_CVTSI2SDrm
- 138544679U, // Int_CVTSI2SDrr
- 138937905U, // Int_CVTSI2SS64rm
- 138544689U, // Int_CVTSI2SS64rr
- 138806833U, // Int_CVTSI2SSrm
- 138544689U, // Int_CVTSI2SSrr
- 139462203U, // Int_CVTSS2SDrm
- 138544699U, // Int_CVTSS2SDrr
- 140642741U, // Int_CVTSS2SI64rm
- 139856309U, // Int_CVTSS2SI64rr
- 140642741U, // Int_CVTSS2SIrm
- 139856309U, // Int_CVTSS2SIrr
- 140380607U, // Int_CVTTPD2DQrm
- 139856319U, // Int_CVTTPD2DQrr
- 140380618U, // Int_CVTTPD2PIrm
- 139856330U, // Int_CVTTPD2PIrr
- 140380629U, // Int_CVTTPS2DQrm
- 139856341U, // Int_CVTTPS2DQrr
- 140511712U, // Int_CVTTPS2PIrm
- 139856352U, // Int_CVTTPS2PIrr
- 140379717U, // Int_CVTTSD2SI64rm
- 139855429U, // Int_CVTTSD2SI64rr
- 140379717U, // Int_CVTTSD2SIrm
- 139855429U, // Int_CVTTSD2SIrr
- 140641872U, // Int_CVTTSS2SI64rm
- 139855440U, // Int_CVTTSS2SI64rr
- 140641872U, // Int_CVTTSS2SIrm
- 139855440U, // Int_CVTTSS2SIrr
- 140380651U, // Int_UCOMISDrm
- 139856363U, // Int_UCOMISDrr
- 140380660U, // Int_UCOMISSrm
- 139856372U, // Int_UCOMISSrr
- 1073744381U, // JA
- 1073744381U, // JA8
- 1073744385U, // JAE
- 1073744385U, // JAE8
- 1073744390U, // JB
- 1073744390U, // JB8
- 1073744394U, // JBE
- 1073744394U, // JBE8
- 1073744399U, // JCXZ8
- 1073744405U, // JE
- 1073744405U, // JE8
- 1073744409U, // JG
- 1073744409U, // JG8
- 1073744413U, // JGE
- 1073744413U, // JGE8
- 1073744418U, // JL
- 1073744418U, // JL8
- 1073744422U, // JLE
- 1073744422U, // JLE8
- 1073744427U, // JMP
- 402655787U, // JMP32m
- 134220331U, // JMP32r
- 536873515U, // JMP64m
- 134220331U, // JMP64r
- 1073744427U, // JMP8
- 1073744432U, // JNE
- 1073744432U, // JNE8
- 1073744437U, // JNO
- 1073744437U, // JNO8
- 1073744442U, // JNP
- 1073744442U, // JNP8
- 1073744447U, // JNS
- 1073744447U, // JNS8
- 1073744452U, // JO
- 1073744452U, // JO8
- 1073744456U, // JP
- 1073744456U, // JP8
- 1073744460U, // JS
- 1073744460U, // JS8
- 2640U, // LAHF
- 139725397U, // LAR16rm
- 139856469U, // LAR16rr
- 139725397U, // LAR32rm
- 139856469U, // LAR32rr
- 139725397U, // LAR64rm
- 139856469U, // LAR64rr
- 272632410U, // LCMPXCHG16
- 406850138U, // LCMPXCHG32
- 1879050857U, // LCMPXCHG64
- 675285594U, // LCMPXCHG8
- 402655865U, // LCMPXCHG8B
- 140905098U, // LDDQUrm
- 402655889U, // LDMXCSR
- 2714U, // LD_F0
- 2719U, // LD_F1
- 805309092U, // LD_F32m
- 939526820U, // LD_F64m
- 2013268644U, // LD_F80m
+ 1229850103U, // Int_CMPSDrm
+ 1363281399U, // Int_CMPSDrr
+ 1234175479U, // Int_CMPSSrm
+ 1367475703U, // Int_CMPSSrr
+ 140379680U, // Int_COMISDrm
+ 139855392U, // Int_COMISDrr
+ 140379688U, // Int_COMISSrm
+ 139855400U, // Int_COMISSrr
+ 140117619U, // Int_CVTDQ2PDrm
+ 139855475U, // Int_CVTDQ2PDrr
+ 140904061U, // Int_CVTDQ2PSrm
+ 139855485U, // Int_CVTDQ2PSrr
+ 140379783U, // Int_CVTPD2DQrm
+ 139855495U, // Int_CVTPD2DQrr
+ 140380912U, // Int_CVTPD2PIrm
+ 139856624U, // Int_CVTPD2PIrr
+ 140379793U, // Int_CVTPD2PSrm
+ 139855505U, // Int_CVTPD2PSrr
+ 140118778U, // Int_CVTPI2PDrm
+ 139856634U, // Int_CVTPI2PDrr
+ 138939140U, // Int_CVTPI2PSrm
+ 138545924U, // Int_CVTPI2PSrr
+ 140379803U, // Int_CVTPS2DQrm
+ 139855515U, // Int_CVTPS2DQrr
+ 140510885U, // Int_CVTPS2PDrm
+ 139855525U, // Int_CVTPS2PDrr
+ 140512014U, // Int_CVTPS2PIrm
+ 139856654U, // Int_CVTPS2PIrr
+ 140379823U, // Int_CVTSD2SI64rm
+ 139855535U, // Int_CVTSD2SI64rr
+ 140379823U, // Int_CVTSD2SIrm
+ 139855535U, // Int_CVTSD2SIrr
+ 139331257U, // Int_CVTSD2SSrm
+ 138544825U, // Int_CVTSD2SSrr
+ 138938051U, // Int_CVTSI2SD64rm
+ 138544835U, // Int_CVTSI2SD64rr
+ 138806979U, // Int_CVTSI2SDrm
+ 138544835U, // Int_CVTSI2SDrr
+ 138938061U, // Int_CVTSI2SS64rm
+ 138544845U, // Int_CVTSI2SS64rr
+ 138806989U, // Int_CVTSI2SSrm
+ 138544845U, // Int_CVTSI2SSrr
+ 139462359U, // Int_CVTSS2SDrm
+ 138544855U, // Int_CVTSS2SDrr
+ 140642017U, // Int_CVTSS2SI64rm
+ 139855585U, // Int_CVTSS2SI64rr
+ 140642017U, // Int_CVTSS2SIrm
+ 139855585U, // Int_CVTSS2SIrr
+ 140380952U, // Int_CVTTPD2DQrm
+ 139856664U, // Int_CVTTPD2DQrr
+ 140380963U, // Int_CVTTPD2PIrm
+ 139856675U, // Int_CVTTPD2PIrr
+ 140379883U, // Int_CVTTPS2DQrm
+ 139855595U, // Int_CVTTPS2DQrr
+ 140512046U, // Int_CVTTPS2PIrm
+ 139856686U, // Int_CVTTPS2PIrr
+ 140379894U, // Int_CVTTSD2SI64rm
+ 139855606U, // Int_CVTTSD2SI64rr
+ 140379894U, // Int_CVTTSD2SIrm
+ 139855606U, // Int_CVTTSD2SIrr
+ 140642049U, // Int_CVTTSS2SI64rm
+ 139855617U, // Int_CVTTSS2SI64rr
+ 140642049U, // Int_CVTTSS2SIrm
+ 139855617U, // Int_CVTTSS2SIrr
+ 140380985U, // Int_UCOMISDrm
+ 139856697U, // Int_UCOMISDrr
+ 140380994U, // Int_UCOMISSrm
+ 139856706U, // Int_UCOMISSrr
+ 1073744715U, // JA
+ 1073744715U, // JA8
+ 1073744719U, // JAE
+ 1073744719U, // JAE8
+ 1073744724U, // JB
+ 1073744724U, // JB8
+ 1073744728U, // JBE
+ 1073744728U, // JBE8
+ 1073744733U, // JCXZ8
+ 1073744739U, // JE
+ 1073744739U, // JE8
+ 1073744743U, // JG
+ 1073744743U, // JG8
+ 1073744747U, // JGE
+ 1073744747U, // JGE8
+ 1073744752U, // JL
+ 1073744752U, // JL8
+ 1073744756U, // JLE
+ 1073744756U, // JLE8
+ 1073744761U, // JMP
+ 402656121U, // JMP32m
+ 134220665U, // JMP32r
+ 536873849U, // JMP64m
+ 1073744761U, // JMP64pcrel32
+ 134220665U, // JMP64r
+ 1073744761U, // JMP8
+ 1073744766U, // JNE
+ 1073744766U, // JNE8
+ 1073744771U, // JNO
+ 1073744771U, // JNO8
+ 1073744776U, // JNP
+ 1073744776U, // JNP8
+ 1073744781U, // JNS
+ 1073744781U, // JNS8
+ 1073744786U, // JO
+ 1073744786U, // JO8
+ 1073744790U, // JP
+ 1073744790U, // JP8
+ 1073744794U, // JS
+ 1073744794U, // JS8
+ 2974U, // LAHF
+ 139725731U, // LAR16rm
+ 139856803U, // LAR16rr
+ 139725731U, // LAR32rm
+ 139856803U, // LAR32rr
+ 139725731U, // LAR64rm
+ 139856803U, // LAR64rr
+ 272632744U, // LCMPXCHG16
+ 406850472U, // LCMPXCHG32
+ 2013268919U, // LCMPXCHG64
+ 675285928U, // LCMPXCHG8
+ 402656199U, // LCMPXCHG8B
+ 140905432U, // LDDQUrm
+ 402656223U, // LDMXCSR
+ 141036520U, // LDS16rm
+ 141036520U, // LDS32rm
+ 3053U, // LD_F0
+ 3058U, // LD_F1
+ 805309431U, // LD_F32m
+ 939527159U, // LD_F64m
+ 2147486711U, // LD_F80m
0U, // LD_Fp032
0U, // LD_Fp064
0U, // LD_Fp080
@@ -869,414 +990,461 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // LD_Fp64m
0U, // LD_Fp64m80
0U, // LD_Fp80m
- 134220452U, // LD_Frr
- 141036201U, // LEA16r
- 141036201U, // LEA32r
- 141167273U, // LEA64_32r
- 141298345U, // LEA64r
- 2734U, // LEAVE
- 2734U, // LEAVE64
- 2740U, // LFENCE
- 272632507U, // LOCK_ADD16mi
- 272632507U, // LOCK_ADD16mi8
- 272632507U, // LOCK_ADD16mr
- 406850235U, // LOCK_ADD32mi
- 406850235U, // LOCK_ADD32mi8
- 406850235U, // LOCK_ADD32mr
- 541067963U, // LOCK_ADD64mi32
- 541067963U, // LOCK_ADD64mi8
- 541067963U, // LOCK_ADD64mr
- 675285691U, // LOCK_ADD8mi
- 675285691U, // LOCK_ADD8mr
- 268438214U, // LOCK_DEC16m
- 402655942U, // LOCK_DEC32m
- 536873670U, // LOCK_DEC64m
- 671091398U, // LOCK_DEC8m
- 268438225U, // LOCK_INC16m
- 402655953U, // LOCK_INC32m
- 536873681U, // LOCK_INC64m
- 671091409U, // LOCK_INC8m
- 272632540U, // LOCK_SUB16mi
- 272632540U, // LOCK_SUB16mi8
- 272632540U, // LOCK_SUB16mr
- 406850268U, // LOCK_SUB32mi
- 406850268U, // LOCK_SUB32mi8
- 406850268U, // LOCK_SUB32mr
- 541067996U, // LOCK_SUB64mi32
- 541067996U, // LOCK_SUB64mi8
- 541067996U, // LOCK_SUB64mr
- 675285724U, // LOCK_SUB8mi
- 675285724U, // LOCK_SUB8mr
- 2791U, // LODSB
- 2797U, // LODSD
- 2803U, // LODSQ
- 2809U, // LODSW
- 1073744639U, // LOOP
- 1073744645U, // LOOPE
- 1073744652U, // LOOPNE
- 2836U, // LRET
- 134220569U, // LRETI
- 2147486495U, // LXADD16
- 1799359263U, // LXADD32
- 2281704223U, // LXADD64
- 2415921951U, // LXADD8
- 139856683U, // MASKMOVDQU
- 139856683U, // MASKMOVDQU64
- 139201335U, // MAXPDrm
- 139201335U, // MAXPDrm_Int
- 138545975U, // MAXPDrr
- 138545975U, // MAXPDrr_Int
- 139201342U, // MAXPSrm
- 139201342U, // MAXPSrm_Int
- 138545982U, // MAXPSrr
- 138545982U, // MAXPSrr_Int
- 139332421U, // MAXSDrm
- 139332421U, // MAXSDrm_Int
- 138545989U, // MAXSDrr
- 138545989U, // MAXSDrr_Int
- 139463500U, // MAXSSrm
- 139463500U, // MAXSSrm_Int
- 138545996U, // MAXSSrr
- 138545996U, // MAXSSrr_Int
- 2899U, // MFENCE
- 139201370U, // MINPDrm
- 139201370U, // MINPDrm_Int
- 138546010U, // MINPDrr
- 138546010U, // MINPDrr_Int
- 139201377U, // MINPSrm
- 139201377U, // MINPSrm_Int
- 138546017U, // MINPSrr
- 138546017U, // MINPSrr_Int
- 139332456U, // MINSDrm
- 139332456U, // MINSDrm_Int
- 138546024U, // MINSDrr
- 138546024U, // MINSDrr_Int
- 139463535U, // MINSSrm
- 139463535U, // MINSSrm_Int
- 138546031U, // MINSSrr
- 138546031U, // MINSSrr_Int
- 140380527U, // MMX_CVTPD2PIrm
- 139856239U, // MMX_CVTPD2PIrr
- 140118403U, // MMX_CVTPI2PDrm
- 139856259U, // MMX_CVTPI2PDrr
- 140118413U, // MMX_CVTPI2PSrm
- 139856269U, // MMX_CVTPI2PSrr
- 140511649U, // MMX_CVTPS2PIrm
- 139856289U, // MMX_CVTPS2PIrr
- 140380618U, // MMX_CVTTPD2PIrm
- 139856330U, // MMX_CVTTPD2PIrr
- 140511712U, // MMX_CVTTPS2PIrm
- 139856352U, // MMX_CVTTPS2PIrr
- 2934U, // MMX_EMMS
- 2939U, // MMX_FEMMS
- 139856769U, // MMX_MASKMOVQ
- 139856769U, // MMX_MASKMOVQ64
- 139856779U, // MMX_MOVD64from64rr
- 406850443U, // MMX_MOVD64mr
- 139987851U, // MMX_MOVD64rm
- 139856779U, // MMX_MOVD64rr
- 139856779U, // MMX_MOVD64rrv164
- 139856779U, // MMX_MOVD64to64rr
- 139856785U, // MMX_MOVDQ2Qrr
- 541068186U, // MMX_MOVNTQmr
- 139856802U, // MMX_MOVQ2DQrr
- 139856802U, // MMX_MOVQ2FR64rr
- 541068203U, // MMX_MOVQ64mr
- 140118955U, // MMX_MOVQ64rm
- 139856811U, // MMX_MOVQ64rr
- 139987851U, // MMX_MOVZDI2PDIrm
- 139856779U, // MMX_MOVZDI2PDIrr
- 138939313U, // MMX_PACKSSDWrm
- 138546097U, // MMX_PACKSSDWrr
- 138939323U, // MMX_PACKSSWBrm
- 138546107U, // MMX_PACKSSWBrr
- 138939333U, // MMX_PACKUSWBrm
- 138546117U, // MMX_PACKUSWBrr
- 138939343U, // MMX_PADDBrm
- 138546127U, // MMX_PADDBrr
- 138939350U, // MMX_PADDDrm
- 138546134U, // MMX_PADDDrr
- 138939357U, // MMX_PADDQrm
- 138546141U, // MMX_PADDQrr
- 138939364U, // MMX_PADDSBrm
- 138546148U, // MMX_PADDSBrr
- 138939372U, // MMX_PADDSWrm
- 138546156U, // MMX_PADDSWrr
- 138939380U, // MMX_PADDUSBrm
- 138546164U, // MMX_PADDUSBrr
- 138939389U, // MMX_PADDUSWrm
- 138546173U, // MMX_PADDUSWrr
- 138939398U, // MMX_PADDWrm
- 138546182U, // MMX_PADDWrr
- 138939405U, // MMX_PANDNrm
- 138546189U, // MMX_PANDNrr
- 138939412U, // MMX_PANDrm
- 138546196U, // MMX_PANDrr
- 138939418U, // MMX_PAVGBrm
- 138546202U, // MMX_PAVGBrr
- 138939425U, // MMX_PAVGWrm
- 138546209U, // MMX_PAVGWrr
- 138939432U, // MMX_PCMPEQBrm
- 138546216U, // MMX_PCMPEQBrr
- 138939441U, // MMX_PCMPEQDrm
- 138546225U, // MMX_PCMPEQDrr
- 138939450U, // MMX_PCMPEQWrm
- 138546234U, // MMX_PCMPEQWrr
- 138939459U, // MMX_PCMPGTBrm
- 138546243U, // MMX_PCMPGTBrr
- 138939468U, // MMX_PCMPGTDrm
- 138546252U, // MMX_PCMPGTDrr
- 138939477U, // MMX_PCMPGTWrm
- 138546261U, // MMX_PCMPGTWrr
- 139873374U, // MMX_PEXTRWri
- 138693734U, // MMX_PINSRWrmi
- 138562662U, // MMX_PINSRWrri
- 138939502U, // MMX_PMADDWDrm
- 138546286U, // MMX_PMADDWDrr
- 138939511U, // MMX_PMAXSWrm
- 138546295U, // MMX_PMAXSWrr
- 138939519U, // MMX_PMAXUBrm
- 138546303U, // MMX_PMAXUBrr
- 138939527U, // MMX_PMINSWrm
- 138546311U, // MMX_PMINSWrr
- 138939535U, // MMX_PMINUBrm
- 138546319U, // MMX_PMINUBrr
- 139857047U, // MMX_PMOVMSKBrr
- 138939553U, // MMX_PMULHUWrm
- 138546337U, // MMX_PMULHUWrr
- 138939562U, // MMX_PMULHWrm
- 138546346U, // MMX_PMULHWrr
- 138939570U, // MMX_PMULLWrm
- 138546354U, // MMX_PMULLWrr
- 138939578U, // MMX_PMULUDQrm
- 138546362U, // MMX_PMULUDQrr
- 138939587U, // MMX_PORrm
- 138546371U, // MMX_PORrr
- 138939592U, // MMX_PSADBWrm
- 138546376U, // MMX_PSADBWrr
- 140135632U, // MMX_PSHUFWmi
- 139873488U, // MMX_PSHUFWri
- 138546392U, // MMX_PSLLDri
- 138939608U, // MMX_PSLLDrm
- 138546392U, // MMX_PSLLDrr
- 138546399U, // MMX_PSLLQri
- 138939615U, // MMX_PSLLQrm
- 138546399U, // MMX_PSLLQrr
- 138546406U, // MMX_PSLLWri
- 138939622U, // MMX_PSLLWrm
- 138546406U, // MMX_PSLLWrr
- 138546413U, // MMX_PSRADri
- 138939629U, // MMX_PSRADrm
- 138546413U, // MMX_PSRADrr
- 138546420U, // MMX_PSRAWri
- 138939636U, // MMX_PSRAWrm
- 138546420U, // MMX_PSRAWrr
- 138546427U, // MMX_PSRLDri
- 138939643U, // MMX_PSRLDrm
- 138546427U, // MMX_PSRLDrr
- 138546434U, // MMX_PSRLQri
- 138939650U, // MMX_PSRLQrm
- 138546434U, // MMX_PSRLQrr
- 138546441U, // MMX_PSRLWri
- 138939657U, // MMX_PSRLWrm
- 138546441U, // MMX_PSRLWrr
- 138939664U, // MMX_PSUBBrm
- 138546448U, // MMX_PSUBBrr
- 138939671U, // MMX_PSUBDrm
- 138546455U, // MMX_PSUBDrr
- 138939678U, // MMX_PSUBQrm
- 138546462U, // MMX_PSUBQrr
- 138939685U, // MMX_PSUBSBrm
- 138546469U, // MMX_PSUBSBrr
- 138939693U, // MMX_PSUBSWrm
- 138546477U, // MMX_PSUBSWrr
- 138939701U, // MMX_PSUBUSBrm
- 138546485U, // MMX_PSUBUSBrr
- 138939710U, // MMX_PSUBUSWrm
- 138546494U, // MMX_PSUBUSWrr
- 138939719U, // MMX_PSUBWrm
- 138546503U, // MMX_PSUBWrr
- 138939726U, // MMX_PUNPCKHBWrm
- 138546510U, // MMX_PUNPCKHBWrr
- 138939737U, // MMX_PUNPCKHDQrm
- 138546521U, // MMX_PUNPCKHDQrr
- 138939748U, // MMX_PUNPCKHWDrm
- 138546532U, // MMX_PUNPCKHWDrr
- 138939759U, // MMX_PUNPCKLBWrm
- 138546543U, // MMX_PUNPCKLBWrr
- 138939770U, // MMX_PUNPCKLDQrm
- 138546554U, // MMX_PUNPCKLDQrr
- 138939781U, // MMX_PUNPCKLWDrm
- 138546565U, // MMX_PUNPCKLWDrr
- 138938515U, // MMX_PXORrm
- 138545299U, // MMX_PXORrr
- 140773523U, // MMX_V_SET0
- 140774449U, // MMX_V_SETALLONES
- 3472U, // MONITOR
- 192941464U, // MOV16ao16
- 272633240U, // MOV16mi
- 272633240U, // MOV16mr
- 272633240U, // MOV16ms
- 134221213U, // MOV16o16a
- 0U, // MOV16r0
- 139857304U, // MOV16ri
- 139726232U, // MOV16rm
- 139857304U, // MOV16rr
- 139857304U, // MOV16rs
- 139726232U, // MOV16sm
- 139857304U, // MOV16sr
- 197135768U, // MOV32ao32
- 406850968U, // MOV32mi
- 406850968U, // MOV32mr
- 134221223U, // MOV32o32a
- 140774834U, // MOV32r0
- 139857304U, // MOV32ri
- 139988376U, // MOV32rm
- 139857304U, // MOV32rr
- 2550140343U, // MOV64FSrm
- 2550140353U, // MOV64GSrm
- 201330072U, // MOV64ao32
- 201330072U, // MOV64ao8
- 541068696U, // MOV64mi32
- 541068696U, // MOV64mr
- 541068696U, // MOV64ms
- 134221259U, // MOV64o32a
- 134221259U, // MOV64o8a
- 139857366U, // MOV64ri
- 139857304U, // MOV64ri32
+ 134220791U, // LD_Frr
+ 141167612U, // LEA16r
+ 141167612U, // LEA32r
+ 141298684U, // LEA64_32r
+ 141429756U, // LEA64r
+ 3073U, // LEAVE
+ 3073U, // LEAVE64
+ 141036551U, // LES16rm
+ 141036551U, // LES32rm
+ 3084U, // LFENCE
+ 141036563U, // LFS16rm
+ 141036563U, // LFS32rm
+ 141036563U, // LFS64rm
+ 1744833560U, // LGDTm
+ 141036574U, // LGS16rm
+ 141036574U, // LGS32rm
+ 141036574U, // LGS64rm
+ 1744833571U, // LIDTm
+ 268438569U, // LLDT16m
+ 134220841U, // LLDT16r
+ 268438575U, // LMSW16m
+ 134220847U, // LMSW16r
+ 272632885U, // LOCK_ADD16mi
+ 272632885U, // LOCK_ADD16mi8
+ 272632885U, // LOCK_ADD16mr
+ 406850613U, // LOCK_ADD32mi
+ 406850613U, // LOCK_ADD32mi8
+ 406850613U, // LOCK_ADD32mr
+ 541068341U, // LOCK_ADD64mi32
+ 541068341U, // LOCK_ADD64mi8
+ 541068341U, // LOCK_ADD64mr
+ 675286069U, // LOCK_ADD8mi
+ 675286069U, // LOCK_ADD8mr
+ 268438592U, // LOCK_DEC16m
+ 402656320U, // LOCK_DEC32m
+ 536874048U, // LOCK_DEC64m
+ 671091776U, // LOCK_DEC8m
+ 268438603U, // LOCK_INC16m
+ 402656331U, // LOCK_INC32m
+ 536874059U, // LOCK_INC64m
+ 671091787U, // LOCK_INC8m
+ 272632918U, // LOCK_SUB16mi
+ 272632918U, // LOCK_SUB16mi8
+ 272632918U, // LOCK_SUB16mr
+ 406850646U, // LOCK_SUB32mi
+ 406850646U, // LOCK_SUB32mi8
+ 406850646U, // LOCK_SUB32mr
+ 541068374U, // LOCK_SUB64mi32
+ 541068374U, // LOCK_SUB64mi8
+ 541068374U, // LOCK_SUB64mr
+ 675286102U, // LOCK_SUB8mi
+ 675286102U, // LOCK_SUB8mr
+ 3169U, // LODSB
+ 3175U, // LODSD
+ 3181U, // LODSQ
+ 3187U, // LODSW
+ 1073745017U, // LOOP
+ 1073745023U, // LOOPE
+ 1073745030U, // LOOPNE
+ 3214U, // LRET
+ 134220947U, // LRETI
+ 139725977U, // LSL16rm
+ 139857049U, // LSL16rr
+ 139988121U, // LSL32rm
+ 139857049U, // LSL32rr
+ 140119193U, // LSL64rm
+ 139857049U, // LSL64rr
+ 141036702U, // LSS16rm
+ 141036702U, // LSS32rm
+ 141036702U, // LSS64rm
+ 3235U, // LTRm
+ 3235U, // LTRr
+ 2281704616U, // LXADD16
+ 2415922344U, // LXADD32
+ 1656753320U, // LXADD64
+ 2550140072U, // LXADD8
+ 139857076U, // MASKMOVDQU
+ 139857076U, // MASKMOVDQU64
+ 139201728U, // MAXPDrm
+ 139201728U, // MAXPDrm_Int
+ 138546368U, // MAXPDrr
+ 138546368U, // MAXPDrr_Int
+ 139201735U, // MAXPSrm
+ 139201735U, // MAXPSrm_Int
+ 138546375U, // MAXPSrr
+ 138546375U, // MAXPSrr_Int
+ 139332814U, // MAXSDrm
+ 139332814U, // MAXSDrm_Int
+ 138546382U, // MAXSDrr
+ 138546382U, // MAXSDrr_Int
+ 139463893U, // MAXSSrm
+ 139463893U, // MAXSSrm_Int
+ 138546389U, // MAXSSrr
+ 138546389U, // MAXSSrr_Int
+ 3292U, // MFENCE
+ 139201763U, // MINPDrm
+ 139201763U, // MINPDrm_Int
+ 138546403U, // MINPDrr
+ 138546403U, // MINPDrr_Int
+ 139201770U, // MINPSrm
+ 139201770U, // MINPSrm_Int
+ 138546410U, // MINPSrr
+ 138546410U, // MINPSrr_Int
+ 139332849U, // MINSDrm
+ 139332849U, // MINSDrm_Int
+ 138546417U, // MINSDrr
+ 138546417U, // MINSDrr_Int
+ 139463928U, // MINSSrm
+ 139463928U, // MINSSrm_Int
+ 138546424U, // MINSSrr
+ 138546424U, // MINSSrr_Int
+ 140380912U, // MMX_CVTPD2PIrm
+ 139856624U, // MMX_CVTPD2PIrr
+ 140118778U, // MMX_CVTPI2PDrm
+ 139856634U, // MMX_CVTPI2PDrr
+ 140118788U, // MMX_CVTPI2PSrm
+ 139856644U, // MMX_CVTPI2PSrr
+ 140512014U, // MMX_CVTPS2PIrm
+ 139856654U, // MMX_CVTPS2PIrr
+ 140380963U, // MMX_CVTTPD2PIrm
+ 139856675U, // MMX_CVTTPD2PIrr
+ 140512046U, // MMX_CVTTPS2PIrm
+ 139856686U, // MMX_CVTTPS2PIrr
+ 3327U, // MMX_EMMS
+ 3332U, // MMX_FEMMS
+ 139857162U, // MMX_MASKMOVQ
+ 139857162U, // MMX_MASKMOVQ64
+ 139857172U, // MMX_MOVD64from64rr
+ 139857172U, // MMX_MOVD64grr
+ 406850836U, // MMX_MOVD64mr
+ 139988244U, // MMX_MOVD64rm
+ 139857172U, // MMX_MOVD64rr
+ 139857172U, // MMX_MOVD64rrv164
+ 139857172U, // MMX_MOVD64to64rr
+ 139857178U, // MMX_MOVDQ2Qrr
+ 541068579U, // MMX_MOVNTQmr
+ 139857195U, // MMX_MOVQ2DQrr
+ 139857195U, // MMX_MOVQ2FR64rr
+ 541068596U, // MMX_MOVQ64gmr
+ 541068596U, // MMX_MOVQ64mr
+ 140119348U, // MMX_MOVQ64rm
+ 139857204U, // MMX_MOVQ64rr
+ 139988244U, // MMX_MOVZDI2PDIrm
+ 139857172U, // MMX_MOVZDI2PDIrr
+ 138939706U, // MMX_PACKSSDWrm
+ 138546490U, // MMX_PACKSSDWrr
+ 138939716U, // MMX_PACKSSWBrm
+ 138546500U, // MMX_PACKSSWBrr
+ 138939726U, // MMX_PACKUSWBrm
+ 138546510U, // MMX_PACKUSWBrr
+ 138939736U, // MMX_PADDBrm
+ 138546520U, // MMX_PADDBrr
+ 138939743U, // MMX_PADDDrm
+ 138546527U, // MMX_PADDDrr
+ 138939750U, // MMX_PADDQrm
+ 138546534U, // MMX_PADDQrr
+ 138939757U, // MMX_PADDSBrm
+ 138546541U, // MMX_PADDSBrr
+ 138939765U, // MMX_PADDSWrm
+ 138546549U, // MMX_PADDSWrr
+ 138939773U, // MMX_PADDUSBrm
+ 138546557U, // MMX_PADDUSBrr
+ 138939782U, // MMX_PADDUSWrm
+ 138546566U, // MMX_PADDUSWrr
+ 138939791U, // MMX_PADDWrm
+ 138546575U, // MMX_PADDWrr
+ 138939798U, // MMX_PANDNrm
+ 138546582U, // MMX_PANDNrr
+ 138939805U, // MMX_PANDrm
+ 138546589U, // MMX_PANDrr
+ 138939811U, // MMX_PAVGBrm
+ 138546595U, // MMX_PAVGBrr
+ 138939818U, // MMX_PAVGWrm
+ 138546602U, // MMX_PAVGWrr
+ 138939825U, // MMX_PCMPEQBrm
+ 138546609U, // MMX_PCMPEQBrr
+ 138939834U, // MMX_PCMPEQDrm
+ 138546618U, // MMX_PCMPEQDrr
+ 138939843U, // MMX_PCMPEQWrm
+ 138546627U, // MMX_PCMPEQWrr
+ 138939852U, // MMX_PCMPGTBrm
+ 138546636U, // MMX_PCMPGTBrr
+ 138939861U, // MMX_PCMPGTDrm
+ 138546645U, // MMX_PCMPGTDrr
+ 138939870U, // MMX_PCMPGTWrm
+ 138546654U, // MMX_PCMPGTWrr
+ 139873767U, // MMX_PEXTRWri
+ 138694127U, // MMX_PINSRWrmi
+ 138563055U, // MMX_PINSRWrri
+ 138939895U, // MMX_PMADDWDrm
+ 138546679U, // MMX_PMADDWDrr
+ 138939904U, // MMX_PMAXSWrm
+ 138546688U, // MMX_PMAXSWrr
+ 138939912U, // MMX_PMAXUBrm
+ 138546696U, // MMX_PMAXUBrr
+ 138939920U, // MMX_PMINSWrm
+ 138546704U, // MMX_PMINSWrr
+ 138939928U, // MMX_PMINUBrm
+ 138546712U, // MMX_PMINUBrr
+ 139857440U, // MMX_PMOVMSKBrr
+ 138939946U, // MMX_PMULHUWrm
+ 138546730U, // MMX_PMULHUWrr
+ 138939955U, // MMX_PMULHWrm
+ 138546739U, // MMX_PMULHWrr
+ 138939963U, // MMX_PMULLWrm
+ 138546747U, // MMX_PMULLWrr
+ 138939971U, // MMX_PMULUDQrm
+ 138546755U, // MMX_PMULUDQrr
+ 138939980U, // MMX_PORrm
+ 138546764U, // MMX_PORrr
+ 138939985U, // MMX_PSADBWrm
+ 138546769U, // MMX_PSADBWrr
+ 140136025U, // MMX_PSHUFWmi
+ 139873881U, // MMX_PSHUFWri
+ 138546785U, // MMX_PSLLDri
+ 138940001U, // MMX_PSLLDrm
+ 138546785U, // MMX_PSLLDrr
+ 138546792U, // MMX_PSLLQri
+ 138940008U, // MMX_PSLLQrm
+ 138546792U, // MMX_PSLLQrr
+ 138546799U, // MMX_PSLLWri
+ 138940015U, // MMX_PSLLWrm
+ 138546799U, // MMX_PSLLWrr
+ 138546806U, // MMX_PSRADri
+ 138940022U, // MMX_PSRADrm
+ 138546806U, // MMX_PSRADrr
+ 138546813U, // MMX_PSRAWri
+ 138940029U, // MMX_PSRAWrm
+ 138546813U, // MMX_PSRAWrr
+ 138546820U, // MMX_PSRLDri
+ 138940036U, // MMX_PSRLDrm
+ 138546820U, // MMX_PSRLDrr
+ 138546827U, // MMX_PSRLQri
+ 138940043U, // MMX_PSRLQrm
+ 138546827U, // MMX_PSRLQrr
+ 138546834U, // MMX_PSRLWri
+ 138940050U, // MMX_PSRLWrm
+ 138546834U, // MMX_PSRLWrr
+ 138940057U, // MMX_PSUBBrm
+ 138546841U, // MMX_PSUBBrr
+ 138940064U, // MMX_PSUBDrm
+ 138546848U, // MMX_PSUBDrr
+ 138940071U, // MMX_PSUBQrm
+ 138546855U, // MMX_PSUBQrr
+ 138940078U, // MMX_PSUBSBrm
+ 138546862U, // MMX_PSUBSBrr
+ 138940086U, // MMX_PSUBSWrm
+ 138546870U, // MMX_PSUBSWrr
+ 138940094U, // MMX_PSUBUSBrm
+ 138546878U, // MMX_PSUBUSBrr
+ 138940103U, // MMX_PSUBUSWrm
+ 138546887U, // MMX_PSUBUSWrr
+ 138940112U, // MMX_PSUBWrm
+ 138546896U, // MMX_PSUBWrr
+ 138940119U, // MMX_PUNPCKHBWrm
+ 138546903U, // MMX_PUNPCKHBWrr
+ 138940130U, // MMX_PUNPCKHDQrm
+ 138546914U, // MMX_PUNPCKHDQrr
+ 138940141U, // MMX_PUNPCKHWDrm
+ 138546925U, // MMX_PUNPCKHWDrr
+ 138940152U, // MMX_PUNPCKLBWrm
+ 138546936U, // MMX_PUNPCKLBWrr
+ 138940163U, // MMX_PUNPCKLDQrm
+ 138546947U, // MMX_PUNPCKLDQrr
+ 138940174U, // MMX_PUNPCKLWDrm
+ 138546958U, // MMX_PUNPCKLWDrr
+ 138938868U, // MMX_PXORrm
+ 138545652U, // MMX_PXORrr
+ 140773876U, // MMX_V_SET0
+ 140774842U, // MMX_V_SETALLONES
+ 3865U, // MONITOR
+ 1124077345U, // MOV16ao16
+ 272633633U, // MOV16mi
+ 272633633U, // MOV16mr
+ 272633633U, // MOV16ms
+ 1073745702U, // MOV16o16a
+ 139857697U, // MOV16ri
+ 139726625U, // MOV16rm
+ 139857697U, // MOV16rr
+ 139857697U, // MOV16rr_REV
+ 139857697U, // MOV16rs
+ 139726625U, // MOV16sm
+ 139857697U, // MOV16sr
+ 1128271649U, // MOV32ao32
+ 139857697U, // MOV32cr
+ 139857697U, // MOV32dr
+ 406851361U, // MOV32mi
+ 406851361U, // MOV32mr
+ 1073745712U, // MOV32o32a
+ 140775227U, // MOV32r0
+ 139857697U, // MOV32rc
+ 139857697U, // MOV32rd
+ 139857697U, // MOV32ri
+ 139988769U, // MOV32rm
+ 139857697U, // MOV32rr
+ 139857697U, // MOV32rr_REV
+ 2684358464U, // MOV64FSrm
+ 2684358474U, // MOV64GSrm
+ 1132465953U, // MOV64ao64
+ 1132465953U, // MOV64ao8
+ 139857697U, // MOV64cr
+ 139857697U, // MOV64dr
+ 541069089U, // MOV64mi32
+ 541069089U, // MOV64mr
+ 541069089U, // MOV64ms
+ 1073745748U, // MOV64o64a
+ 1073745748U, // MOV64o8a
+ 139857697U, // MOV64rc
+ 139857697U, // MOV64rd
+ 139857759U, // MOV64ri
+ 139857697U, // MOV64ri32
0U, // MOV64ri64i32
- 140119448U, // MOV64rm
- 139857304U, // MOV64rr
- 139857304U, // MOV64rs
- 140119448U, // MOV64sm
- 139857304U, // MOV64sr
- 139856811U, // MOV64toPQIrr
- 140118955U, // MOV64toSDrm
- 139856811U, // MOV64toSDrr
- 205524376U, // MOV8ao8
- 675286424U, // MOV8mi
- 675286424U, // MOV8mr
- 675335576U, // MOV8mr_NOREX
- 134221278U, // MOV8o8a
- 140774834U, // MOV8r0
- 139857304U, // MOV8ri
- 140250520U, // MOV8rm
- 140299672U, // MOV8rm_NOREX
- 139857304U, // MOV8rr
- 139906456U, // MOV8rr_NOREX
- 2684356761U, // MOVAPDmr
- 140380313U, // MOVAPDrm
- 139856025U, // MOVAPDrr
- 2684356769U, // MOVAPSmr
- 140380321U, // MOVAPSrm
- 139856033U, // MOVAPSrr
- 140512744U, // MOVDDUPrm
- 139857384U, // MOVDDUPrr
- 139987851U, // MOVDI2PDIrm
- 139856779U, // MOVDI2PDIrr
- 139987851U, // MOVDI2SSrm
- 139856779U, // MOVDI2SSrr
- 2818575857U, // MOVDQAmr
- 140905969U, // MOVDQArm
- 139857393U, // MOVDQArr
- 2818575865U, // MOVDQUmr
- 2818575865U, // MOVDQUmr_Int
- 140905977U, // MOVDQUrm
- 140905977U, // MOVDQUrm_Int
- 138546689U, // MOVHLPSrr
- 943721994U, // MOVHPDmr
- 139333130U, // MOVHPDrm
- 943722002U, // MOVHPSmr
- 139333138U, // MOVHPSrm
- 138546714U, // MOVLHPSrr
- 943722019U, // MOVLPDmr
- 139333155U, // MOVLPDrm
- 138546731U, // MOVLPDrr
- 943722034U, // MOVLPSmr
- 139333170U, // MOVLPSrm
- 138546746U, // MOVLPSrr
- 541068203U, // MOVLQ128mr
- 138546731U, // MOVLSD2PDrr
- 138546746U, // MOVLSS2PSrr
- 139857473U, // MOVMSKPDrr
- 139857483U, // MOVMSKPSrr
- 140906069U, // MOVNTDQArm
- 2684358239U, // MOVNTDQmr
- 406851176U, // MOVNTImr
- 2818575984U, // MOVNTPDmr
- 2818575993U, // MOVNTPSmr
+ 140119841U, // MOV64rm
+ 139857697U, // MOV64rr
+ 139857697U, // MOV64rr_REV
+ 139857697U, // MOV64rs
+ 140119841U, // MOV64sm
+ 139857697U, // MOV64sr
+ 139857204U, // MOV64toPQIrr
+ 140119348U, // MOV64toSDrm
+ 139857204U, // MOV64toSDrr
+ 1136660257U, // MOV8ao8
+ 675286817U, // MOV8mi
+ 675286817U, // MOV8mr
+ 675335969U, // MOV8mr_NOREX
+ 1073745767U, // MOV8o8a
+ 140775227U, // MOV8r0
+ 139857697U, // MOV8ri
+ 140250913U, // MOV8rm
+ 140300065U, // MOV8rm_NOREX
+ 139857697U, // MOV8rr
+ 139906849U, // MOV8rr_NOREX
+ 139857697U, // MOV8rr_REV
+ 2818574842U, // MOVAPDmr
+ 140380666U, // MOVAPDrm
+ 139856378U, // MOVAPDrr
+ 2818574850U, // MOVAPSmr
+ 140380674U, // MOVAPSrm
+ 139856386U, // MOVAPSrr
+ 140513137U, // MOVDDUPrm
+ 139857777U, // MOVDDUPrr
+ 139988244U, // MOVDI2PDIrm
+ 139857172U, // MOVDI2PDIrr
+ 139988244U, // MOVDI2SSrm
+ 139857172U, // MOVDI2SSrr
+ 1480593274U, // MOVDQAmr
+ 140906362U, // MOVDQArm
+ 139857786U, // MOVDQArr
+ 1480593282U, // MOVDQUmr
+ 1480593282U, // MOVDQUmr_Int
+ 140906370U, // MOVDQUrm
+ 140906370U, // MOVDQUrm_Int
+ 138547082U, // MOVHLPSrr
+ 943722387U, // MOVHPDmr
+ 139333523U, // MOVHPDrm
+ 943722395U, // MOVHPSmr
+ 139333531U, // MOVHPSrm
+ 138547107U, // MOVLHPSrr
+ 943722412U, // MOVLPDmr
+ 139333548U, // MOVLPDrm
+ 138547124U, // MOVLPDrr
+ 943722427U, // MOVLPSmr
+ 139333563U, // MOVLPSrm
+ 138547139U, // MOVLPSrr
+ 541068596U, // MOVLQ128mr
+ 138547124U, // MOVLSD2PDrr
+ 138547139U, // MOVLSS2PSrr
+ 139857866U, // MOVMSKPDrr
+ 139857876U, // MOVMSKPSrr
+ 140906462U, // MOVNTDQArm
+ 2818576360U, // MOVNTDQmr
+ 406851569U, // MOVNTImr
+ 1480593401U, // MOVNTPDmr
+ 1480593410U, // MOVNTPSmr
0U, // MOVPC32r
- 943722027U, // MOVPD2SDmr
- 139857451U, // MOVPD2SDrr
- 406850443U, // MOVPDI2DImr
- 139856779U, // MOVPDI2DIrr
- 541068203U, // MOVPQI2QImr
- 139856811U, // MOVPQIto64rr
- 809504314U, // MOVPS2SSmr
- 139857466U, // MOVPS2SSrr
- 140118955U, // MOVQI2PQIrm
- 140512811U, // MOVSD2PDrm
- 139857451U, // MOVSD2PDrr
- 943722027U, // MOVSDmr
- 140512811U, // MOVSDrm
- 139857451U, // MOVSDrr
- 541068203U, // MOVSDto64mr
- 139856811U, // MOVSDto64rr
- 140381826U, // MOVSHDUPrm
- 139857538U, // MOVSHDUPrr
- 140381836U, // MOVSLDUPrm
- 139857548U, // MOVSLDUPrr
- 406850443U, // MOVSS2DImr
- 139856779U, // MOVSS2DIrr
- 140643898U, // MOVSS2PSrm
- 139857466U, // MOVSS2PSrr
- 809504314U, // MOVSSmr
- 140643898U, // MOVSSrm
- 139857466U, // MOVSSrr
+ 943722420U, // MOVPD2SDmr
+ 139857844U, // MOVPD2SDrr
+ 406850836U, // MOVPDI2DImr
+ 139857172U, // MOVPDI2DIrr
+ 541068596U, // MOVPQI2QImr
+ 139857204U, // MOVPQIto64rr
+ 809504707U, // MOVPS2SSmr
+ 139857859U, // MOVPS2SSrr
+ 140119348U, // MOVQI2PQIrm
+ 139857204U, // MOVQxrxr
+ 140513204U, // MOVSD2PDrm
+ 139857844U, // MOVSD2PDrr
+ 943722420U, // MOVSDmr
+ 140513204U, // MOVSDrm
+ 139857844U, // MOVSDrr
+ 541068596U, // MOVSDto64mr
+ 139857204U, // MOVSDto64rr
+ 140382219U, // MOVSHDUPrm
+ 139857931U, // MOVSHDUPrr
+ 140382229U, // MOVSLDUPrm
+ 139857941U, // MOVSLDUPrr
+ 406850836U, // MOVSS2DImr
+ 139857172U, // MOVSS2DIrr
+ 140644291U, // MOVSS2PSrm
+ 139857859U, // MOVSS2PSrr
+ 809504707U, // MOVSSmr
+ 140644291U, // MOVSSrm
+ 139857859U, // MOVSSrr
0U, // MOVSX16rm8
+ 140251167U, // MOVSX16rm8W
0U, // MOVSX16rr8
- 139726486U, // MOVSX32rm16
- 140250774U, // MOVSX32rm8
- 139857558U, // MOVSX32rr16
- 139857558U, // MOVSX32rr8
- 139726486U, // MOVSX64rm16
- 139988637U, // MOVSX64rm32
- 140250774U, // MOVSX64rm8
- 139857558U, // MOVSX64rr16
- 139857565U, // MOVSX64rr32
- 139857558U, // MOVSX64rr8
- 2684358309U, // MOVUPDmr
- 2684358309U, // MOVUPDmr_Int
- 140381861U, // MOVUPDrm
- 140381861U, // MOVUPDrm_Int
- 139857573U, // MOVUPDrr
- 2684358317U, // MOVUPSmr
- 2684358317U, // MOVUPSmr_Int
- 140381869U, // MOVUPSrm
- 140381869U, // MOVUPSrm_Int
- 139857581U, // MOVUPSrr
- 139987851U, // MOVZDI2PDIrm
- 139856779U, // MOVZDI2PDIrr
- 140905387U, // MOVZPQILo2PQIrm
- 139856811U, // MOVZPQILo2PQIrr
- 140118955U, // MOVZQI2PQIrm
- 139856811U, // MOVZQI2PQIrr
- 140512811U, // MOVZSD2PDrm
- 140643898U, // MOVZSS2PSrm
+ 139857951U, // MOVSX16rr8W
+ 139726879U, // MOVSX32rm16
+ 140251167U, // MOVSX32rm8
+ 139857951U, // MOVSX32rr16
+ 139857951U, // MOVSX32rr8
+ 139726879U, // MOVSX64rm16
+ 139989030U, // MOVSX64rm32
+ 140251167U, // MOVSX64rm8
+ 139857951U, // MOVSX64rr16
+ 139857958U, // MOVSX64rr32
+ 139857951U, // MOVSX64rr8
+ 2818576430U, // MOVUPDmr
+ 2818576430U, // MOVUPDmr_Int
+ 140382254U, // MOVUPDrm
+ 140382254U, // MOVUPDrm_Int
+ 139857966U, // MOVUPDrr
+ 2818576438U, // MOVUPSmr
+ 2818576438U, // MOVUPSmr_Int
+ 140382262U, // MOVUPSrm
+ 140382262U, // MOVUPSrm_Int
+ 139857974U, // MOVUPSrr
+ 139988244U, // MOVZDI2PDIrm
+ 139857172U, // MOVZDI2PDIrr
+ 140905780U, // MOVZPQILo2PQIrm
+ 139857204U, // MOVZPQILo2PQIrr
+ 140119348U, // MOVZQI2PQIrm
+ 139857204U, // MOVZQI2PQIrr
+ 140513204U, // MOVZSD2PDrm
+ 140644291U, // MOVZSS2PSrm
0U, // MOVZX16rm8
+ 140251198U, // MOVZX16rm8W
0U, // MOVZX16rr8
- 140299957U, // MOVZX32_NOREXrm8
- 139906741U, // MOVZX32_NOREXrr8
- 139726517U, // MOVZX32rm16
- 140250805U, // MOVZX32rm8
- 139857589U, // MOVZX32rr16
- 139857589U, // MOVZX32rr8
+ 139857982U, // MOVZX16rr8W
+ 140300350U, // MOVZX32_NOREXrm8
+ 139907134U, // MOVZX32_NOREXrr8
+ 139726910U, // MOVZX32rm16
+ 140251198U, // MOVZX32rm8
+ 139857982U, // MOVZX32rr16
+ 139857982U, // MOVZX32rr8
0U, // MOVZX64rm16
+ 139726910U, // MOVZX64rm16_Q
0U, // MOVZX64rm32
0U, // MOVZX64rm8
+ 140251198U, // MOVZX64rm8_Q
0U, // MOVZX64rr16
+ 139857982U, // MOVZX64rr16_Q
0U, // MOVZX64rr32
0U, // MOVZX64rr8
+ 139857982U, // MOVZX64rr8_Q
0U, // MOV_Fp3232
0U, // MOV_Fp3264
0U, // MOV_Fp3280
@@ -1286,34 +1454,34 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MOV_Fp8032
0U, // MOV_Fp8064
0U, // MOV_Fp8080
- 139611836U, // MPSADBWrmi
- 138563260U, // MPSADBWrri
- 268439237U, // MUL16m
- 134221509U, // MUL16r
- 402656965U, // MUL32m
- 134221509U, // MUL32r
- 536874693U, // MUL64m
- 134221509U, // MUL64r
- 671092421U, // MUL8m
- 134221509U, // MUL8r
- 139202250U, // MULPDrm
- 138546890U, // MULPDrr
- 139202257U, // MULPSrm
- 138546897U, // MULPSrr
- 139333336U, // MULSDrm
- 139333336U, // MULSDrm_Int
- 138546904U, // MULSDrr
- 138546904U, // MULSDrr_Int
- 139464415U, // MULSSrm
- 139464415U, // MULSSrm_Int
- 138546911U, // MULSSrr
- 138546911U, // MULSSrr_Int
- 805310182U, // MUL_F32m
- 939527910U, // MUL_F64m
- 268439276U, // MUL_FI16m
- 402657004U, // MUL_FI32m
- 134221555U, // MUL_FPrST0
- 134221542U, // MUL_FST0r
+ 139612229U, // MPSADBWrmi
+ 138563653U, // MPSADBWrri
+ 268439630U, // MUL16m
+ 134221902U, // MUL16r
+ 402657358U, // MUL32m
+ 134221902U, // MUL32r
+ 536875086U, // MUL64m
+ 134221902U, // MUL64r
+ 671092814U, // MUL8m
+ 134221902U, // MUL8r
+ 139202643U, // MULPDrm
+ 138547283U, // MULPDrr
+ 139202650U, // MULPSrm
+ 138547290U, // MULPSrr
+ 139333729U, // MULSDrm
+ 139333729U, // MULSDrm_Int
+ 138547297U, // MULSDrr
+ 138547297U, // MULSDrr_Int
+ 139464808U, // MULSSrm
+ 139464808U, // MULSSrm_Int
+ 138547304U, // MULSSrr
+ 138547304U, // MULSSrr_Int
+ 805310575U, // MUL_F32m
+ 939528303U, // MUL_F64m
+ 268439669U, // MUL_FI16m
+ 402657397U, // MUL_FI32m
+ 134221948U, // MUL_FPrST0
+ 134221935U, // MUL_FST0r
0U, // MUL_Fp32
0U, // MUL_Fp32m
0U, // MUL_Fp64
@@ -1328,735 +1496,785 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MUL_FpI32m32
0U, // MUL_FpI32m64
0U, // MUL_FpI32m80
- 142610150U, // MUL_FrST0
- 3834U, // MWAIT
- 268439296U, // NEG16m
- 134221568U, // NEG16r
- 402657024U, // NEG32m
- 134221568U, // NEG32r
- 536874752U, // NEG64m
- 134221568U, // NEG64r
- 671092480U, // NEG8m
- 134221568U, // NEG8r
- 3845U, // NOOP
- 402657033U, // NOOPL
- 268439311U, // NOT16m
- 134221583U, // NOT16r
- 402657039U, // NOT32m
- 134221583U, // NOT32r
- 536874767U, // NOT64m
- 134221583U, // NOT64r
- 671092495U, // NOT8m
- 134221583U, // NOT8r
- 134221588U, // OR16i16
- 272633629U, // OR16mi
- 272633629U, // OR16mi8
- 272633629U, // OR16mr
- 138546973U, // OR16ri
- 138546973U, // OR16ri8
- 138678045U, // OR16rm
- 138546973U, // OR16rr
- 134221601U, // OR32i32
- 406851357U, // OR32mi
- 406851357U, // OR32mi8
- 406851357U, // OR32mr
- 138546973U, // OR32ri
- 138546973U, // OR32ri8
- 138809117U, // OR32rm
- 138546973U, // OR32rr
- 134221611U, // OR64i32
- 541069085U, // OR64mi32
- 541069085U, // OR64mi8
- 541069085U, // OR64mr
- 138546973U, // OR64ri32
- 138546973U, // OR64ri8
- 138940189U, // OR64rm
- 138546973U, // OR64rr
- 134221621U, // OR8i8
- 675286813U, // OR8mi
- 675286813U, // OR8mr
- 138546973U, // OR8ri
- 139071261U, // OR8rm
- 138546973U, // OR8rr
- 139200681U, // ORPDrm
- 138545321U, // ORPDrr
- 139200687U, // ORPSrm
- 138545327U, // ORPSrr
- 209719102U, // OUT16ir
- 3907U, // OUT16rr
- 213913406U, // OUT32ir
- 3920U, // OUT32rr
- 218107710U, // OUT8ir
- 3934U, // OUT8rr
- 140906347U, // PABSBrm128
- 140119915U, // PABSBrm64
- 139857771U, // PABSBrr128
- 139857771U, // PABSBrr64
- 140906354U, // PABSDrm128
- 140119922U, // PABSDrm64
- 139857778U, // PABSDrr128
- 139857778U, // PABSDrr64
- 140906361U, // PABSWrm128
- 140119929U, // PABSWrm64
- 139857785U, // PABSWrr128
- 139857785U, // PABSWrr64
- 139594673U, // PACKSSDWrm
- 138546097U, // PACKSSDWrr
- 139594683U, // PACKSSWBrm
- 138546107U, // PACKSSWBrr
- 139595648U, // PACKUSDWrm
- 138547072U, // PACKUSDWrr
- 139594693U, // PACKUSWBrm
- 138546117U, // PACKUSWBrr
- 139594703U, // PADDBrm
- 138546127U, // PADDBrr
- 139594710U, // PADDDrm
- 138546134U, // PADDDrr
- 139594717U, // PADDQrm
- 138546141U, // PADDQrr
- 139594724U, // PADDSBrm
- 138546148U, // PADDSBrr
- 139594732U, // PADDSWrm
- 138546156U, // PADDSWrr
- 139594740U, // PADDUSBrm
- 138546164U, // PADDUSBrr
- 139594749U, // PADDUSWrm
- 138546173U, // PADDUSWrr
- 139594758U, // PADDWrm
- 138546182U, // PADDWrr
- 139612042U, // PALIGNR128rm
- 138563466U, // PALIGNR128rr
- 138956682U, // PALIGNR64rm
- 138563466U, // PALIGNR64rr
- 139594765U, // PANDNrm
- 138546189U, // PANDNrr
- 139594772U, // PANDrm
- 138546196U, // PANDrr
- 139594778U, // PAVGBrm
- 138546202U, // PAVGBrr
- 139594785U, // PAVGWrm
- 138546209U, // PAVGWrr
- 139628435U, // PBLENDVBrm0
- 138579859U, // PBLENDVBrr0
- 139612061U, // PBLENDWrmi
- 138563485U, // PBLENDWrri
- 139594792U, // PCMPEQBrm
- 138546216U, // PCMPEQBrr
- 139594801U, // PCMPEQDrm
- 138546225U, // PCMPEQDrr
- 139595686U, // PCMPEQQrm
- 138547110U, // PCMPEQQrr
- 139594810U, // PCMPEQWrm
- 138546234U, // PCMPEQWrr
- 140922799U, // PCMPESTRIArm
- 139874223U, // PCMPESTRIArr
- 140922799U, // PCMPESTRICrm
- 139874223U, // PCMPESTRICrr
- 140922799U, // PCMPESTRIOrm
- 139874223U, // PCMPESTRIOrr
- 140922799U, // PCMPESTRISrm
- 139874223U, // PCMPESTRISrr
- 140922799U, // PCMPESTRIZrm
- 139874223U, // PCMPESTRIZrr
- 140922799U, // PCMPESTRIrm
- 139874223U, // PCMPESTRIrr
- 4026U, // PCMPESTRM128MEM
- 4050U, // PCMPESTRM128REG
- 140922858U, // PCMPESTRM128rm
- 139874282U, // PCMPESTRM128rr
- 139594819U, // PCMPGTBrm
- 138546243U, // PCMPGTBrr
- 139594828U, // PCMPGTDrm
- 138546252U, // PCMPGTDrr
- 139595765U, // PCMPGTQrm
- 138547189U, // PCMPGTQrr
- 139594837U, // PCMPGTWrm
- 138546261U, // PCMPGTWrr
- 140922878U, // PCMPISTRIArm
- 139874302U, // PCMPISTRIArr
- 140922878U, // PCMPISTRICrm
- 139874302U, // PCMPISTRICrr
- 140922878U, // PCMPISTRIOrm
- 139874302U, // PCMPISTRIOrr
- 140922878U, // PCMPISTRISrm
- 139874302U, // PCMPISTRISrr
- 140922878U, // PCMPISTRIZrm
- 139874302U, // PCMPISTRIZrr
- 140922878U, // PCMPISTRIrm
- 139874302U, // PCMPISTRIrr
- 4105U, // PCMPISTRM128MEM
- 4129U, // PCMPISTRM128REG
- 140922937U, // PCMPISTRM128rm
- 139874361U, // PCMPISTRM128rr
- 675303492U, // PEXTRBmr
- 139874372U, // PEXTRBrr
- 406868044U, // PEXTRDmr
- 139874380U, // PEXTRDrr
- 541085780U, // PEXTRQmr
- 139874388U, // PEXTRQrr
- 272649310U, // PEXTRWmr
- 139873374U, // PEXTRWri
- 139595868U, // PHADDDrm128
- 138940508U, // PHADDDrm64
- 138547292U, // PHADDDrr128
- 138547292U, // PHADDDrr64
- 139595876U, // PHADDSWrm128
- 138940516U, // PHADDSWrm64
- 138547300U, // PHADDSWrr128
- 138547300U, // PHADDSWrr64
- 139595885U, // PHADDWrm128
- 138940525U, // PHADDWrm64
- 138547309U, // PHADDWrr128
- 138547309U, // PHADDWrr64
- 140906613U, // PHMINPOSUWrm128
- 139858037U, // PHMINPOSUWrr128
- 139595905U, // PHSUBDrm128
- 138940545U, // PHSUBDrm64
- 138547329U, // PHSUBDrr128
- 138547329U, // PHSUBDrr64
- 139595913U, // PHSUBSWrm128
- 138940553U, // PHSUBSWrm64
- 138547337U, // PHSUBSWrr128
- 138547337U, // PHSUBSWrr64
- 139595922U, // PHSUBWrm128
- 138940562U, // PHSUBWrm64
- 138547346U, // PHSUBWrr128
- 138547346U, // PHSUBWrr64
- 139088026U, // PINSRBrm
- 138563738U, // PINSRBrr
- 138825890U, // PINSRDrm
- 138563746U, // PINSRDrr
- 138956970U, // PINSRQrm
- 138563754U, // PINSRQrr
- 138693734U, // PINSRWrmi
- 138562662U, // PINSRWrri
- 139595954U, // PMADDUBSWrm128
- 138940594U, // PMADDUBSWrm64
- 138547378U, // PMADDUBSWrr128
- 138547378U, // PMADDUBSWrr64
- 139594862U, // PMADDWDrm
- 138546286U, // PMADDWDrr
- 139595965U, // PMAXSBrm
- 138547389U, // PMAXSBrr
- 139595973U, // PMAXSDrm
- 138547397U, // PMAXSDrr
- 139594871U, // PMAXSWrm
- 138546295U, // PMAXSWrr
- 139594879U, // PMAXUBrm
- 138546303U, // PMAXUBrr
- 139595981U, // PMAXUDrm
- 138547405U, // PMAXUDrr
- 139595989U, // PMAXUWrm
- 138547413U, // PMAXUWrr
- 139595997U, // PMINSBrm
- 138547421U, // PMINSBrr
- 139596005U, // PMINSDrm
- 138547429U, // PMINSDrr
- 139594887U, // PMINSWrm
- 138546311U, // PMINSWrr
- 139594895U, // PMINUBrm
- 138546319U, // PMINUBrr
- 139596013U, // PMINUDrm
- 138547437U, // PMINUDrr
- 139596021U, // PMINUWrm
- 138547445U, // PMINUWrr
- 139857047U, // PMOVMSKBrr
- 139989245U, // PMOVSXBDrm
- 139858173U, // PMOVSXBDrr
- 139727111U, // PMOVSXBQrm
- 139858183U, // PMOVSXBQrr
- 140120337U, // PMOVSXBWrm
- 139858193U, // PMOVSXBWrr
- 140120347U, // PMOVSXDQrm
- 139858203U, // PMOVSXDQrr
- 140120357U, // PMOVSXWDrm
- 139858213U, // PMOVSXWDrr
- 139989295U, // PMOVSXWQrm
- 139858223U, // PMOVSXWQrr
- 139989305U, // PMOVZXBDrm
- 139858233U, // PMOVZXBDrr
- 139727171U, // PMOVZXBQrm
- 139858243U, // PMOVZXBQrr
- 140120397U, // PMOVZXBWrm
- 139858253U, // PMOVZXBWrr
- 140120407U, // PMOVZXDQrm
- 139858263U, // PMOVZXDQrr
- 140120417U, // PMOVZXWDrm
- 139858273U, // PMOVZXWDrr
- 139989355U, // PMOVZXWQrm
- 139858283U, // PMOVZXWQrr
- 139596149U, // PMULDQrm
- 138547573U, // PMULDQrr
- 139596157U, // PMULHRSWrm128
- 138940797U, // PMULHRSWrm64
- 138547581U, // PMULHRSWrr128
- 138547581U, // PMULHRSWrr64
- 139594913U, // PMULHUWrm
- 138546337U, // PMULHUWrr
- 139594922U, // PMULHWrm
- 138546346U, // PMULHWrr
- 139596167U, // PMULLDrm
- 139596167U, // PMULLDrm_int
- 138547591U, // PMULLDrr
- 138547591U, // PMULLDrr_int
- 139594930U, // PMULLWrm
- 138546354U, // PMULLWrr
- 139594938U, // PMULUDQrm
- 138546362U, // PMULUDQrr
- 134222223U, // POP16r
- 268439951U, // POP16rmm
- 134222223U, // POP16rmr
- 134222223U, // POP32r
- 402657679U, // POP32rmm
- 134222223U, // POP32rmr
- 134222223U, // POP64r
- 536875407U, // POP64rmm
- 134222223U, // POP64rmr
- 4500U, // POPFD
- 4500U, // POPFQ
- 139594947U, // PORrm
- 138546371U, // PORrr
- 671093145U, // PREFETCHNTA
- 671093158U, // PREFETCHT0
- 671093170U, // PREFETCHT1
- 671093182U, // PREFETCHT2
- 139594952U, // PSADBWrm
- 138546376U, // PSADBWrr
- 139596234U, // PSHUFBrm128
- 138940874U, // PSHUFBrm64
- 138547658U, // PSHUFBrr128
- 138547658U, // PSHUFBrr64
- 140923346U, // PSHUFDmi
- 139874770U, // PSHUFDri
- 140923354U, // PSHUFHWmi
- 139874778U, // PSHUFHWri
- 140923363U, // PSHUFLWmi
- 139874787U, // PSHUFLWri
- 139596268U, // PSIGNBrm128
- 138940908U, // PSIGNBrm64
- 138547692U, // PSIGNBrr128
- 138547692U, // PSIGNBrr64
- 139596276U, // PSIGNDrm128
- 138940916U, // PSIGNDrm64
- 138547700U, // PSIGNDrr128
- 138547700U, // PSIGNDrr64
- 139596284U, // PSIGNWrm128
- 138940924U, // PSIGNWrm64
- 138547708U, // PSIGNWrr128
- 138547708U, // PSIGNWrr64
- 138547716U, // PSLLDQri
- 138546392U, // PSLLDri
- 139594968U, // PSLLDrm
- 138546392U, // PSLLDrr
- 138546399U, // PSLLQri
- 139594975U, // PSLLQrm
- 138546399U, // PSLLQrr
- 138546406U, // PSLLWri
- 139594982U, // PSLLWrm
- 138546406U, // PSLLWrr
- 138546413U, // PSRADri
- 139594989U, // PSRADrm
- 138546413U, // PSRADrr
- 138546420U, // PSRAWri
- 139594996U, // PSRAWrm
- 138546420U, // PSRAWrr
- 138547724U, // PSRLDQri
- 138546427U, // PSRLDri
- 139595003U, // PSRLDrm
- 138546427U, // PSRLDrr
- 138546434U, // PSRLQri
- 139595010U, // PSRLQrm
- 138546434U, // PSRLQrr
- 138546441U, // PSRLWri
- 139595017U, // PSRLWrm
- 138546441U, // PSRLWrr
- 139595024U, // PSUBBrm
- 138546448U, // PSUBBrr
- 139595031U, // PSUBDrm
- 138546455U, // PSUBDrr
- 139595038U, // PSUBQrm
- 138546462U, // PSUBQrr
- 139595045U, // PSUBSBrm
- 138546469U, // PSUBSBrr
- 139595053U, // PSUBSWrm
- 138546477U, // PSUBSWrr
- 139595061U, // PSUBUSBrm
- 138546485U, // PSUBUSBrr
- 139595070U, // PSUBUSWrm
- 138546494U, // PSUBUSWrr
- 139595079U, // PSUBWrm
- 138546503U, // PSUBWrr
- 140907028U, // PTESTrm
- 139858452U, // PTESTrr
- 139595086U, // PUNPCKHBWrm
- 138546510U, // PUNPCKHBWrr
- 139595097U, // PUNPCKHDQrm
- 138546521U, // PUNPCKHDQrr
- 139596316U, // PUNPCKHQDQrm
- 138547740U, // PUNPCKHQDQrr
- 139595108U, // PUNPCKHWDrm
- 138546532U, // PUNPCKHWDrr
- 139595119U, // PUNPCKLBWrm
- 138546543U, // PUNPCKLBWrr
- 139595130U, // PUNPCKLDQrm
- 138546554U, // PUNPCKLDQrr
- 139596328U, // PUNPCKLQDQrm
- 138547752U, // PUNPCKLQDQrr
- 139595141U, // PUNPCKLWDrm
- 138546565U, // PUNPCKLWDrr
- 134222388U, // PUSH16r
- 268440116U, // PUSH16rmm
- 134222388U, // PUSH16rmr
- 134222388U, // PUSH32i16
- 134222388U, // PUSH32i32
- 134222388U, // PUSH32i8
- 134222388U, // PUSH32r
- 402657844U, // PUSH32rmm
- 134222388U, // PUSH32rmr
- 134222388U, // PUSH64i16
- 134222388U, // PUSH64i32
- 134222388U, // PUSH64i8
- 134222388U, // PUSH64r
- 536875572U, // PUSH64rmm
- 134222388U, // PUSH64rmr
- 4666U, // PUSHFD
- 4666U, // PUSHFQ
- 139593875U, // PXORrm
- 138545299U, // PXORrr
- 356520512U, // RCL16m1
- 360714816U, // RCL16mCL
- 275649088U, // RCL16mi
- 222302784U, // RCL16r1
- 226497088U, // RCL16rCL
- 138547776U, // RCL16ri
- 490738240U, // RCL32m1
- 494932544U, // RCL32mCL
- 409866816U, // RCL32mi
- 222302784U, // RCL32r1
- 226497088U, // RCL32rCL
- 138547776U, // RCL32ri
- 624955968U, // RCL64m1
- 629150272U, // RCL64mCL
- 544084544U, // RCL64mi
- 222302784U, // RCL64r1
- 226497088U, // RCL64rCL
- 138547776U, // RCL64ri
- 759173696U, // RCL8m1
- 763368000U, // RCL8mCL
- 678302272U, // RCL8mi
- 222302784U, // RCL8r1
- 226497088U, // RCL8rCL
- 138547776U, // RCL8ri
- 140382789U, // RCPPSm
- 140382789U, // RCPPSm_Int
- 139858501U, // RCPPSr
- 139858501U, // RCPPSr_Int
- 140644940U, // RCPSSm
- 140644940U, // RCPSSm_Int
- 139858508U, // RCPSSr
- 139858508U, // RCPSSr_Int
- 356520531U, // RCR16m1
- 360714835U, // RCR16mCL
- 275649107U, // RCR16mi
- 222302803U, // RCR16r1
- 226497107U, // RCR16rCL
- 138547795U, // RCR16ri
- 490738259U, // RCR32m1
- 494932563U, // RCR32mCL
- 409866835U, // RCR32mi
- 222302803U, // RCR32r1
- 226497107U, // RCR32rCL
- 138547795U, // RCR32ri
- 624955987U, // RCR64m1
- 629150291U, // RCR64mCL
- 544084563U, // RCR64mi
- 222302803U, // RCR64r1
- 226497107U, // RCR64rCL
- 138547795U, // RCR64ri
- 759173715U, // RCR8m1
- 763368019U, // RCR8mCL
- 678302291U, // RCR8mi
- 222302803U, // RCR8r1
- 226497107U, // RCR8rCL
- 138547795U, // RCR8ri
- 4696U, // RDTSC
- 4702U, // REP_MOVSB
- 4712U, // REP_MOVSD
- 4722U, // REP_MOVSQ
- 4732U, // REP_MOVSW
- 4742U, // REP_STOSB
- 4752U, // REP_STOSD
- 4762U, // REP_STOSQ
- 4772U, // REP_STOSW
- 4782U, // RET
- 134222514U, // RETI
- 268440247U, // ROL16m1
- 360714935U, // ROL16mCL
- 272634551U, // ROL16mi
- 134222519U, // ROL16r1
- 226497207U, // ROL16rCL
- 138547895U, // ROL16ri
- 402657975U, // ROL32m1
- 494932663U, // ROL32mCL
- 406852279U, // ROL32mi
- 134222519U, // ROL32r1
- 226497207U, // ROL32rCL
- 138547895U, // ROL32ri
- 536875703U, // ROL64m1
- 633344695U, // ROL64mCL
- 541070007U, // ROL64mi
- 134222519U, // ROL64r1
- 230691511U, // ROL64rCL
- 138547895U, // ROL64ri
- 671093431U, // ROL8m1
- 763368119U, // ROL8mCL
- 675287735U, // ROL8mi
- 134222519U, // ROL8r1
- 226497207U, // ROL8rCL
- 138547895U, // ROL8ri
- 268440252U, // ROR16m1
- 360714940U, // ROR16mCL
- 272634556U, // ROR16mi
- 134222524U, // ROR16r1
- 226497212U, // ROR16rCL
- 138547900U, // ROR16ri
- 402657980U, // ROR32m1
- 494932668U, // ROR32mCL
- 406852284U, // ROR32mi
- 134222524U, // ROR32r1
- 226497212U, // ROR32rCL
- 138547900U, // ROR32ri
- 536875708U, // ROR64m1
- 633344700U, // ROR64mCL
- 541070012U, // ROR64mi
- 134222524U, // ROR64r1
- 230691516U, // ROR64rCL
- 138547900U, // ROR64ri
- 671093436U, // ROR8m1
- 763368124U, // ROR8mCL
- 675287740U, // ROR8mi
- 134222524U, // ROR8r1
- 226497212U, // ROR8rCL
- 138547900U, // ROR8ri
- 140399297U, // ROUNDPDm_Int
- 139875009U, // ROUNDPDr_Int
- 140399306U, // ROUNDPSm_Int
- 139875018U, // ROUNDPSr_Int
- 139350739U, // ROUNDSDm_Int
- 138564307U, // ROUNDSDr_Int
- 139481820U, // ROUNDSSm_Int
- 138564316U, // ROUNDSSr_Int
- 140382949U, // RSQRTPSm
- 140382949U, // RSQRTPSm_Int
- 139858661U, // RSQRTPSr
- 139858661U, // RSQRTPSr_Int
- 140645102U, // RSQRTSSm
- 140645102U, // RSQRTSSm_Int
- 139858670U, // RSQRTSSr
- 139858670U, // RSQRTSSr_Int
- 4855U, // SAHF
- 268440316U, // SAR16m1
- 360715004U, // SAR16mCL
- 272634620U, // SAR16mi
- 134222588U, // SAR16r1
- 226497276U, // SAR16rCL
- 138547964U, // SAR16ri
- 402658044U, // SAR32m1
- 494932732U, // SAR32mCL
- 406852348U, // SAR32mi
- 134222588U, // SAR32r1
- 226497276U, // SAR32rCL
- 138547964U, // SAR32ri
- 536875772U, // SAR64m1
- 633344764U, // SAR64mCL
- 541070076U, // SAR64mi
- 134222588U, // SAR64r1
- 230691580U, // SAR64rCL
- 138547964U, // SAR64ri
- 671093500U, // SAR8m1
- 763368188U, // SAR8mCL
- 675287804U, // SAR8mi
- 134222588U, // SAR8r1
- 226497276U, // SAR8rCL
- 138547964U, // SAR8ri
- 134222593U, // SBB16i16
- 272634635U, // SBB16mi
- 272634635U, // SBB16mi8
- 272634635U, // SBB16mr
- 138547979U, // SBB16ri
- 138547979U, // SBB16ri8
- 138679051U, // SBB16rm
- 138547979U, // SBB16rr
- 134222608U, // SBB32i32
- 406852363U, // SBB32mi
- 406852363U, // SBB32mi8
- 406852363U, // SBB32mr
- 138547979U, // SBB32ri
- 138547979U, // SBB32ri8
- 138810123U, // SBB32rm
- 138547979U, // SBB32rr
- 134222619U, // SBB64i32
- 541070091U, // SBB64mi32
- 541070091U, // SBB64mi8
- 541070091U, // SBB64mr
- 138547979U, // SBB64ri32
- 138547979U, // SBB64ri8
- 138941195U, // SBB64rm
- 138547979U, // SBB64rr
- 134222630U, // SBB8i8
- 675287819U, // SBB8mi
- 675287819U, // SBB8mr
- 138547979U, // SBB8ri
- 139072267U, // SBB8rm
- 138547979U, // SBB8rr
- 4912U, // SCAS16
- 4912U, // SCAS32
- 4912U, // SCAS64
- 4912U, // SCAS8
- 671093557U, // SETAEm
- 134222645U, // SETAEr
- 671093564U, // SETAm
- 134222652U, // SETAr
- 671093570U, // SETBEm
- 134222658U, // SETBEr
- 140776203U, // SETB_C16r
- 140776203U, // SETB_C32r
- 140776203U, // SETB_C64r
- 140776203U, // SETB_C8r
- 671093577U, // SETBm
- 134222665U, // SETBr
- 671093583U, // SETEm
- 134222671U, // SETEr
- 671093589U, // SETGEm
- 134222677U, // SETGEr
- 671093596U, // SETGm
- 134222684U, // SETGr
- 671093602U, // SETLEm
- 134222690U, // SETLEr
- 671093609U, // SETLm
- 134222697U, // SETLr
- 671093615U, // SETNEm
- 134222703U, // SETNEr
- 671093622U, // SETNOm
- 134222710U, // SETNOr
- 671093629U, // SETNPm
- 134222717U, // SETNPr
- 671093636U, // SETNSm
- 134222724U, // SETNSr
- 671093643U, // SETOm
- 134222731U, // SETOr
- 671093649U, // SETPm
- 134222737U, // SETPr
- 671093655U, // SETSm
- 134222743U, // SETSr
- 5021U, // SFENCE
- 268440484U, // SHL16m1
- 360715172U, // SHL16mCL
- 272634788U, // SHL16mi
- 134222756U, // SHL16r1
- 226497444U, // SHL16rCL
- 138548132U, // SHL16ri
- 402658212U, // SHL32m1
- 494932900U, // SHL32mCL
- 406852516U, // SHL32mi
- 134222756U, // SHL32r1
- 226497444U, // SHL32rCL
- 138548132U, // SHL32ri
- 536875940U, // SHL64m1
- 633344932U, // SHL64mCL
- 541070244U, // SHL64mi
- 134222761U, // SHL64r1
- 230691748U, // SHL64rCL
- 138548132U, // SHL64ri
- 671093668U, // SHL8m1
- 763368356U, // SHL8mCL
- 675287972U, // SHL8mi
- 134222756U, // SHL8r1
- 226497444U, // SHL8rCL
- 138548132U, // SHL8ri
- 272700334U, // SHLD16mrCL
- 272651182U, // SHLD16mri8
- 138613678U, // SHLD16rrCL
- 138564526U, // SHLD16rri8
- 406918062U, // SHLD32mrCL
- 406868910U, // SHLD32mri8
- 138613678U, // SHLD32rrCL
- 138564526U, // SHLD32rri8
- 541152174U, // SHLD64mrCL
- 541086638U, // SHLD64mri8
- 138630062U, // SHLD64rrCL
- 138564526U, // SHLD64rri8
- 268440489U, // SHR16m1
- 360715177U, // SHR16mCL
- 272634793U, // SHR16mi
- 134222761U, // SHR16r1
- 226497449U, // SHR16rCL
- 138548137U, // SHR16ri
- 402658217U, // SHR32m1
- 494932905U, // SHR32mCL
- 406852521U, // SHR32mi
- 134222761U, // SHR32r1
- 226497449U, // SHR32rCL
- 138548137U, // SHR32ri
- 536875945U, // SHR64m1
- 633344937U, // SHR64mCL
- 541070249U, // SHR64mi
- 134222761U, // SHR64r1
- 230691753U, // SHR64rCL
- 138548137U, // SHR64ri
- 671093673U, // SHR8m1
- 763368361U, // SHR8mCL
- 675287977U, // SHR8mi
- 134222761U, // SHR8r1
- 226497449U, // SHR8rCL
- 138548137U, // SHR8ri
- 272700340U, // SHRD16mrCL
- 272651188U, // SHRD16mri8
- 138613684U, // SHRD16rrCL
- 138564532U, // SHRD16rri8
- 406918068U, // SHRD32mrCL
- 406868916U, // SHRD32mri8
- 138613684U, // SHRD32rrCL
- 138564532U, // SHRD32rri8
- 541152180U, // SHRD64mrCL
- 541086644U, // SHRD64mri8
- 138630068U, // SHRD64rrCL
- 138564532U, // SHRD64rri8
- 139219898U, // SHUFPDrmi
- 138564538U, // SHUFPDrri
- 139219906U, // SHUFPSrmi
- 138564546U, // SHUFPSrri
- 5066U, // SIN_F
+ 142610543U, // MUL_FrST0
+ 4227U, // MWAIT
+ 268439689U, // NEG16m
+ 134221961U, // NEG16r
+ 402657417U, // NEG32m
+ 134221961U, // NEG32r
+ 536875145U, // NEG64m
+ 134221961U, // NEG64r
+ 671092873U, // NEG8m
+ 134221961U, // NEG8r
+ 4238U, // NOOP
+ 402657426U, // NOOPL
+ 268439698U, // NOOPW
+ 268439703U, // NOT16m
+ 134221975U, // NOT16r
+ 402657431U, // NOT32m
+ 134221975U, // NOT32r
+ 536875159U, // NOT64m
+ 134221975U, // NOT64r
+ 671092887U, // NOT8m
+ 134221975U, // NOT8r
+ 134221980U, // OR16i16
+ 272634021U, // OR16mi
+ 272634021U, // OR16mi8
+ 272634021U, // OR16mr
+ 138547365U, // OR16ri
+ 138547365U, // OR16ri8
+ 138678437U, // OR16rm
+ 138547365U, // OR16rr
+ 138547365U, // OR16rr_REV
+ 134221993U, // OR32i32
+ 406851749U, // OR32mi
+ 406851749U, // OR32mi8
+ 406851749U, // OR32mr
+ 138547365U, // OR32ri
+ 138547365U, // OR32ri8
+ 138809509U, // OR32rm
+ 138547365U, // OR32rr
+ 138547365U, // OR32rr_REV
+ 134222003U, // OR64i32
+ 541069477U, // OR64mi32
+ 541069477U, // OR64mi8
+ 541069477U, // OR64mr
+ 138547365U, // OR64ri32
+ 138547365U, // OR64ri8
+ 138940581U, // OR64rm
+ 138547365U, // OR64rr
+ 138547365U, // OR64rr_REV
+ 134222013U, // OR8i8
+ 675287205U, // OR8mi
+ 675287205U, // OR8mr
+ 138547365U, // OR8ri
+ 139071653U, // OR8rm
+ 138547365U, // OR8rr
+ 138547365U, // OR8rr_REV
+ 139201034U, // ORPDrm
+ 138545674U, // ORPDrr
+ 139201040U, // ORPSrm
+ 138545680U, // ORPSrr
+ 201330886U, // OUT16ir
+ 4299U, // OUT16rr
+ 205525190U, // OUT32ir
+ 4312U, // OUT32rr
+ 209719494U, // OUT8ir
+ 4326U, // OUT8rr
+ 4339U, // OUTSB
+ 4345U, // OUTSD
+ 4351U, // OUTSW
+ 140906757U, // PABSBrm128
+ 140120325U, // PABSBrm64
+ 139858181U, // PABSBrr128
+ 139858181U, // PABSBrr64
+ 140906764U, // PABSDrm128
+ 140120332U, // PABSDrm64
+ 139858188U, // PABSDrr128
+ 139858188U, // PABSDrr64
+ 140906771U, // PABSWrm128
+ 140120339U, // PABSWrm64
+ 139858195U, // PABSWrr128
+ 139858195U, // PABSWrr64
+ 139595066U, // PACKSSDWrm
+ 138546490U, // PACKSSDWrr
+ 139595076U, // PACKSSWBrm
+ 138546500U, // PACKSSWBrr
+ 139596058U, // PACKUSDWrm
+ 138547482U, // PACKUSDWrr
+ 139595086U, // PACKUSWBrm
+ 138546510U, // PACKUSWBrr
+ 139595096U, // PADDBrm
+ 138546520U, // PADDBrr
+ 139595103U, // PADDDrm
+ 138546527U, // PADDDrr
+ 139595110U, // PADDQrm
+ 138546534U, // PADDQrr
+ 139595117U, // PADDSBrm
+ 138546541U, // PADDSBrr
+ 139595125U, // PADDSWrm
+ 138546549U, // PADDSWrr
+ 139595133U, // PADDUSBrm
+ 138546557U, // PADDUSBrr
+ 139595142U, // PADDUSWrm
+ 138546566U, // PADDUSWrr
+ 139595151U, // PADDWrm
+ 138546575U, // PADDWrr
+ 139612452U, // PALIGNR128rm
+ 138563876U, // PALIGNR128rr
+ 138957092U, // PALIGNR64rm
+ 138563876U, // PALIGNR64rr
+ 139595158U, // PANDNrm
+ 138546582U, // PANDNrr
+ 139595165U, // PANDrm
+ 138546589U, // PANDrr
+ 139595171U, // PAVGBrm
+ 138546595U, // PAVGBrr
+ 139595178U, // PAVGWrm
+ 138546602U, // PAVGWrr
+ 139628845U, // PBLENDVBrm0
+ 138580269U, // PBLENDVBrr0
+ 139612471U, // PBLENDWrmi
+ 138563895U, // PBLENDWrri
+ 139595185U, // PCMPEQBrm
+ 138546609U, // PCMPEQBrr
+ 139595194U, // PCMPEQDrm
+ 138546618U, // PCMPEQDrr
+ 139596096U, // PCMPEQQrm
+ 138547520U, // PCMPEQQrr
+ 139595203U, // PCMPEQWrm
+ 138546627U, // PCMPEQWrr
+ 140923209U, // PCMPESTRIArm
+ 139874633U, // PCMPESTRIArr
+ 140923209U, // PCMPESTRICrm
+ 139874633U, // PCMPESTRICrr
+ 140923209U, // PCMPESTRIOrm
+ 139874633U, // PCMPESTRIOrr
+ 140923209U, // PCMPESTRISrm
+ 139874633U, // PCMPESTRISrr
+ 140923209U, // PCMPESTRIZrm
+ 139874633U, // PCMPESTRIZrr
+ 140923209U, // PCMPESTRIrm
+ 139874633U, // PCMPESTRIrr
+ 4436U, // PCMPESTRM128MEM
+ 4460U, // PCMPESTRM128REG
+ 140923268U, // PCMPESTRM128rm
+ 139874692U, // PCMPESTRM128rr
+ 139595212U, // PCMPGTBrm
+ 138546636U, // PCMPGTBrr
+ 139595221U, // PCMPGTDrm
+ 138546645U, // PCMPGTDrr
+ 139596175U, // PCMPGTQrm
+ 138547599U, // PCMPGTQrr
+ 139595230U, // PCMPGTWrm
+ 138546654U, // PCMPGTWrr
+ 140923288U, // PCMPISTRIArm
+ 139874712U, // PCMPISTRIArr
+ 140923288U, // PCMPISTRICrm
+ 139874712U, // PCMPISTRICrr
+ 140923288U, // PCMPISTRIOrm
+ 139874712U, // PCMPISTRIOrr
+ 140923288U, // PCMPISTRISrm
+ 139874712U, // PCMPISTRISrr
+ 140923288U, // PCMPISTRIZrm
+ 139874712U, // PCMPISTRIZrr
+ 140923288U, // PCMPISTRIrm
+ 139874712U, // PCMPISTRIrr
+ 4515U, // PCMPISTRM128MEM
+ 4539U, // PCMPISTRM128REG
+ 140923347U, // PCMPISTRM128rm
+ 139874771U, // PCMPISTRM128rr
+ 675303902U, // PEXTRBmr
+ 139874782U, // PEXTRBrr
+ 406868454U, // PEXTRDmr
+ 139874790U, // PEXTRDrr
+ 541086190U, // PEXTRQmr
+ 139874798U, // PEXTRQrr
+ 272649703U, // PEXTRWmr
+ 139873767U, // PEXTRWri
+ 139596278U, // PHADDDrm128
+ 138940918U, // PHADDDrm64
+ 138547702U, // PHADDDrr128
+ 138547702U, // PHADDDrr64
+ 139596286U, // PHADDSWrm128
+ 138940926U, // PHADDSWrm64
+ 138547710U, // PHADDSWrr128
+ 138547710U, // PHADDSWrr64
+ 139596295U, // PHADDWrm128
+ 138940935U, // PHADDWrm64
+ 138547719U, // PHADDWrr128
+ 138547719U, // PHADDWrr64
+ 140907023U, // PHMINPOSUWrm128
+ 139858447U, // PHMINPOSUWrr128
+ 139596315U, // PHSUBDrm128
+ 138940955U, // PHSUBDrm64
+ 138547739U, // PHSUBDrr128
+ 138547739U, // PHSUBDrr64
+ 139596323U, // PHSUBSWrm128
+ 138940963U, // PHSUBSWrm64
+ 138547747U, // PHSUBSWrr128
+ 138547747U, // PHSUBSWrr64
+ 139596332U, // PHSUBWrm128
+ 138940972U, // PHSUBWrm64
+ 138547756U, // PHSUBWrr128
+ 138547756U, // PHSUBWrr64
+ 139088436U, // PINSRBrm
+ 138564148U, // PINSRBrr
+ 138826300U, // PINSRDrm
+ 138564156U, // PINSRDrr
+ 138957380U, // PINSRQrm
+ 138564164U, // PINSRQrr
+ 138694127U, // PINSRWrmi
+ 138563055U, // PINSRWrri
+ 139596364U, // PMADDUBSWrm128
+ 138941004U, // PMADDUBSWrm64
+ 138547788U, // PMADDUBSWrr128
+ 138547788U, // PMADDUBSWrr64
+ 139595255U, // PMADDWDrm
+ 138546679U, // PMADDWDrr
+ 139596375U, // PMAXSBrm
+ 138547799U, // PMAXSBrr
+ 139596383U, // PMAXSDrm
+ 138547807U, // PMAXSDrr
+ 139595264U, // PMAXSWrm
+ 138546688U, // PMAXSWrr
+ 139595272U, // PMAXUBrm
+ 138546696U, // PMAXUBrr
+ 139596391U, // PMAXUDrm
+ 138547815U, // PMAXUDrr
+ 139596399U, // PMAXUWrm
+ 138547823U, // PMAXUWrr
+ 139596407U, // PMINSBrm
+ 138547831U, // PMINSBrr
+ 139596415U, // PMINSDrm
+ 138547839U, // PMINSDrr
+ 139595280U, // PMINSWrm
+ 138546704U, // PMINSWrr
+ 139595288U, // PMINUBrm
+ 138546712U, // PMINUBrr
+ 139596423U, // PMINUDrm
+ 138547847U, // PMINUDrr
+ 139596431U, // PMINUWrm
+ 138547855U, // PMINUWrr
+ 139857440U, // PMOVMSKBrr
+ 139989655U, // PMOVSXBDrm
+ 139858583U, // PMOVSXBDrr
+ 139727521U, // PMOVSXBQrm
+ 139858593U, // PMOVSXBQrr
+ 140120747U, // PMOVSXBWrm
+ 139858603U, // PMOVSXBWrr
+ 140120757U, // PMOVSXDQrm
+ 139858613U, // PMOVSXDQrr
+ 140120767U, // PMOVSXWDrm
+ 139858623U, // PMOVSXWDrr
+ 139989705U, // PMOVSXWQrm
+ 139858633U, // PMOVSXWQrr
+ 139989715U, // PMOVZXBDrm
+ 139858643U, // PMOVZXBDrr
+ 139727581U, // PMOVZXBQrm
+ 139858653U, // PMOVZXBQrr
+ 140120807U, // PMOVZXBWrm
+ 139858663U, // PMOVZXBWrr
+ 140120817U, // PMOVZXDQrm
+ 139858673U, // PMOVZXDQrr
+ 140120827U, // PMOVZXWDrm
+ 139858683U, // PMOVZXWDrr
+ 139989765U, // PMOVZXWQrm
+ 139858693U, // PMOVZXWQrr
+ 139596559U, // PMULDQrm
+ 138547983U, // PMULDQrr
+ 139596567U, // PMULHRSWrm128
+ 138941207U, // PMULHRSWrm64
+ 138547991U, // PMULHRSWrr128
+ 138547991U, // PMULHRSWrr64
+ 139595306U, // PMULHUWrm
+ 138546730U, // PMULHUWrr
+ 139595315U, // PMULHWrm
+ 138546739U, // PMULHWrr
+ 139596577U, // PMULLDrm
+ 139596577U, // PMULLDrm_int
+ 138548001U, // PMULLDrr
+ 138548001U, // PMULLDrr_int
+ 139595323U, // PMULLWrm
+ 138546747U, // PMULLWrr
+ 139595331U, // PMULUDQrm
+ 138546755U, // PMULUDQrr
+ 134222633U, // POP16r
+ 268440361U, // POP16rmm
+ 134222633U, // POP16rmr
+ 134222633U, // POP32r
+ 402658089U, // POP32rmm
+ 134222633U, // POP32rmr
+ 134222633U, // POP64r
+ 536875817U, // POP64rmm
+ 134222633U, // POP64rmr
+ 139727662U, // POPCNT16rm
+ 139858734U, // POPCNT16rr
+ 139989806U, // POPCNT32rm
+ 139858734U, // POPCNT32rr
+ 140120878U, // POPCNT64rm
+ 139858734U, // POPCNT64rr
+ 4918U, // POPF
+ 4918U, // POPFD
+ 4918U, // POPFQ
+ 4923U, // POPFS16
+ 4923U, // POPFS32
+ 4923U, // POPFS64
+ 4931U, // POPGS16
+ 4931U, // POPGS32
+ 4931U, // POPGS64
+ 139595340U, // PORrm
+ 138546764U, // PORrr
+ 671093579U, // PREFETCHNTA
+ 671093592U, // PREFETCHT0
+ 671093604U, // PREFETCHT1
+ 671093616U, // PREFETCHT2
+ 139595345U, // PSADBWrm
+ 138546769U, // PSADBWrr
+ 139596668U, // PSHUFBrm128
+ 138941308U, // PSHUFBrm64
+ 138548092U, // PSHUFBrr128
+ 138548092U, // PSHUFBrr64
+ 140923780U, // PSHUFDmi
+ 139875204U, // PSHUFDri
+ 140923788U, // PSHUFHWmi
+ 139875212U, // PSHUFHWri
+ 140923797U, // PSHUFLWmi
+ 139875221U, // PSHUFLWri
+ 139596702U, // PSIGNBrm128
+ 138941342U, // PSIGNBrm64
+ 138548126U, // PSIGNBrr128
+ 138548126U, // PSIGNBrr64
+ 139596710U, // PSIGNDrm128
+ 138941350U, // PSIGNDrm64
+ 138548134U, // PSIGNDrr128
+ 138548134U, // PSIGNDrr64
+ 139596718U, // PSIGNWrm128
+ 138941358U, // PSIGNWrm64
+ 138548142U, // PSIGNWrr128
+ 138548142U, // PSIGNWrr64
+ 138548150U, // PSLLDQri
+ 138546785U, // PSLLDri
+ 139595361U, // PSLLDrm
+ 138546785U, // PSLLDrr
+ 138546792U, // PSLLQri
+ 139595368U, // PSLLQrm
+ 138546792U, // PSLLQrr
+ 138546799U, // PSLLWri
+ 139595375U, // PSLLWrm
+ 138546799U, // PSLLWrr
+ 138546806U, // PSRADri
+ 139595382U, // PSRADrm
+ 138546806U, // PSRADrr
+ 138546813U, // PSRAWri
+ 139595389U, // PSRAWrm
+ 138546813U, // PSRAWrr
+ 138548158U, // PSRLDQri
+ 138546820U, // PSRLDri
+ 139595396U, // PSRLDrm
+ 138546820U, // PSRLDrr
+ 138546827U, // PSRLQri
+ 139595403U, // PSRLQrm
+ 138546827U, // PSRLQrr
+ 138546834U, // PSRLWri
+ 139595410U, // PSRLWrm
+ 138546834U, // PSRLWrr
+ 139595417U, // PSUBBrm
+ 138546841U, // PSUBBrr
+ 139595424U, // PSUBDrm
+ 138546848U, // PSUBDrr
+ 139595431U, // PSUBQrm
+ 138546855U, // PSUBQrr
+ 139595438U, // PSUBSBrm
+ 138546862U, // PSUBSBrr
+ 139595446U, // PSUBSWrm
+ 138546870U, // PSUBSWrr
+ 139595454U, // PSUBUSBrm
+ 138546878U, // PSUBUSBrr
+ 139595463U, // PSUBUSWrm
+ 138546887U, // PSUBUSWrr
+ 139595472U, // PSUBWrm
+ 138546896U, // PSUBWrr
+ 140907462U, // PTESTrm
+ 139858886U, // PTESTrr
+ 139595479U, // PUNPCKHBWrm
+ 138546903U, // PUNPCKHBWrr
+ 139595490U, // PUNPCKHDQrm
+ 138546914U, // PUNPCKHDQrr
+ 139596750U, // PUNPCKHQDQrm
+ 138548174U, // PUNPCKHQDQrr
+ 139595501U, // PUNPCKHWDrm
+ 138546925U, // PUNPCKHWDrr
+ 139595512U, // PUNPCKLBWrm
+ 138546936U, // PUNPCKLBWrr
+ 139595523U, // PUNPCKLDQrm
+ 138546947U, // PUNPCKLDQrr
+ 139596762U, // PUNPCKLQDQrm
+ 138548186U, // PUNPCKLQDQrr
+ 139595534U, // PUNPCKLWDrm
+ 138546958U, // PUNPCKLWDrr
+ 134222822U, // PUSH16r
+ 268440550U, // PUSH16rmm
+ 134222822U, // PUSH16rmr
+ 134222822U, // PUSH32i16
+ 134222822U, // PUSH32i32
+ 134222822U, // PUSH32i8
+ 134222822U, // PUSH32r
+ 402658278U, // PUSH32rmm
+ 134222822U, // PUSH32rmr
+ 134222822U, // PUSH64i16
+ 134222822U, // PUSH64i32
+ 134222822U, // PUSH64i8
+ 134222822U, // PUSH64r
+ 536876006U, // PUSH64rmm
+ 134222822U, // PUSH64rmr
+ 5100U, // PUSHF
+ 5100U, // PUSHFD
+ 5100U, // PUSHFQ64
+ 5106U, // PUSHFS16
+ 5106U, // PUSHFS32
+ 5106U, // PUSHFS64
+ 5115U, // PUSHGS16
+ 5115U, // PUSHGS32
+ 5115U, // PUSHGS64
+ 139594228U, // PXORrm
+ 138545652U, // PXORrr
+ 348132356U, // RCL16m1
+ 352326660U, // RCL16mCL
+ 275780612U, // RCL16mi
+ 213914628U, // RCL16r1
+ 218108932U, // RCL16rCL
+ 138548228U, // RCL16ri
+ 482350084U, // RCL32m1
+ 486544388U, // RCL32mCL
+ 409998340U, // RCL32mi
+ 213914628U, // RCL32r1
+ 218108932U, // RCL32rCL
+ 138548228U, // RCL32ri
+ 616567812U, // RCL64m1
+ 620762116U, // RCL64mCL
+ 544216068U, // RCL64mi
+ 213914628U, // RCL64r1
+ 218108932U, // RCL64rCL
+ 138548228U, // RCL64ri
+ 750785540U, // RCL8m1
+ 754979844U, // RCL8mCL
+ 678433796U, // RCL8mi
+ 213914628U, // RCL8r1
+ 218108932U, // RCL8rCL
+ 138548228U, // RCL8ri
+ 140383241U, // RCPPSm
+ 140383241U, // RCPPSm_Int
+ 139858953U, // RCPPSr
+ 139858953U, // RCPPSr_Int
+ 140645392U, // RCPSSm
+ 140645392U, // RCPSSm_Int
+ 139858960U, // RCPSSr
+ 139858960U, // RCPSSr_Int
+ 348132375U, // RCR16m1
+ 352326679U, // RCR16mCL
+ 275780631U, // RCR16mi
+ 213914647U, // RCR16r1
+ 218108951U, // RCR16rCL
+ 138548247U, // RCR16ri
+ 482350103U, // RCR32m1
+ 486544407U, // RCR32mCL
+ 409998359U, // RCR32mi
+ 213914647U, // RCR32r1
+ 218108951U, // RCR32rCL
+ 138548247U, // RCR32ri
+ 616567831U, // RCR64m1
+ 620762135U, // RCR64mCL
+ 544216087U, // RCR64mi
+ 213914647U, // RCR64r1
+ 218108951U, // RCR64rCL
+ 138548247U, // RCR64ri
+ 750785559U, // RCR8m1
+ 754979863U, // RCR8mCL
+ 678433815U, // RCR8mi
+ 213914647U, // RCR8r1
+ 218108951U, // RCR8rCL
+ 138548247U, // RCR8ri
+ 5148U, // RDMSR
+ 5154U, // RDPMC
+ 5160U, // RDTSC
+ 5166U, // REP_MOVSB
+ 5176U, // REP_MOVSD
+ 5186U, // REP_MOVSQ
+ 5196U, // REP_MOVSW
+ 5206U, // REP_STOSB
+ 5216U, // REP_STOSD
+ 5226U, // REP_STOSQ
+ 5236U, // REP_STOSW
+ 5246U, // RET
+ 134222978U, // RETI
+ 268440711U, // ROL16m1
+ 352326791U, // ROL16mCL
+ 272635015U, // ROL16mi
+ 134222983U, // ROL16r1
+ 218109063U, // ROL16rCL
+ 138548359U, // ROL16ri
+ 402658439U, // ROL32m1
+ 486544519U, // ROL32mCL
+ 406852743U, // ROL32mi
+ 134222983U, // ROL32r1
+ 218109063U, // ROL32rCL
+ 138548359U, // ROL32ri
+ 536876167U, // ROL64m1
+ 624956551U, // ROL64mCL
+ 541070471U, // ROL64mi
+ 134222983U, // ROL64r1
+ 222303367U, // ROL64rCL
+ 138548359U, // ROL64ri
+ 671093895U, // ROL8m1
+ 754979975U, // ROL8mCL
+ 675288199U, // ROL8mi
+ 134222983U, // ROL8r1
+ 218109063U, // ROL8rCL
+ 138548359U, // ROL8ri
+ 268440716U, // ROR16m1
+ 352326796U, // ROR16mCL
+ 272635020U, // ROR16mi
+ 134222988U, // ROR16r1
+ 218109068U, // ROR16rCL
+ 138548364U, // ROR16ri
+ 402658444U, // ROR32m1
+ 486544524U, // ROR32mCL
+ 406852748U, // ROR32mi
+ 134222988U, // ROR32r1
+ 218109068U, // ROR32rCL
+ 138548364U, // ROR32ri
+ 536876172U, // ROR64m1
+ 624956556U, // ROR64mCL
+ 541070476U, // ROR64mi
+ 134222988U, // ROR64r1
+ 222303372U, // ROR64rCL
+ 138548364U, // ROR64ri
+ 671093900U, // ROR8m1
+ 754979980U, // ROR8mCL
+ 675288204U, // ROR8mi
+ 134222988U, // ROR8r1
+ 218109068U, // ROR8rCL
+ 138548364U, // ROR8ri
+ 140399761U, // ROUNDPDm_Int
+ 139875473U, // ROUNDPDr_Int
+ 140399770U, // ROUNDPSm_Int
+ 139875482U, // ROUNDPSr_Int
+ 139351203U, // ROUNDSDm_Int
+ 138564771U, // ROUNDSDr_Int
+ 139482284U, // ROUNDSSm_Int
+ 138564780U, // ROUNDSSr_Int
+ 5301U, // RSM
+ 140383417U, // RSQRTPSm
+ 140383417U, // RSQRTPSm_Int
+ 139859129U, // RSQRTPSr
+ 139859129U, // RSQRTPSr_Int
+ 140645570U, // RSQRTSSm
+ 140645570U, // RSQRTSSm_Int
+ 139859138U, // RSQRTSSr
+ 139859138U, // RSQRTSSr_Int
+ 5323U, // SAHF
+ 268440784U, // SAR16m1
+ 352326864U, // SAR16mCL
+ 272635088U, // SAR16mi
+ 134223056U, // SAR16r1
+ 218109136U, // SAR16rCL
+ 138548432U, // SAR16ri
+ 402658512U, // SAR32m1
+ 486544592U, // SAR32mCL
+ 406852816U, // SAR32mi
+ 134223056U, // SAR32r1
+ 218109136U, // SAR32rCL
+ 138548432U, // SAR32ri
+ 536876240U, // SAR64m1
+ 624956624U, // SAR64mCL
+ 541070544U, // SAR64mi
+ 134223056U, // SAR64r1
+ 222303440U, // SAR64rCL
+ 138548432U, // SAR64ri
+ 671093968U, // SAR8m1
+ 754980048U, // SAR8mCL
+ 675288272U, // SAR8mi
+ 134223056U, // SAR8r1
+ 218109136U, // SAR8rCL
+ 138548432U, // SAR8ri
+ 134223061U, // SBB16i16
+ 272635103U, // SBB16mi
+ 272635103U, // SBB16mi8
+ 272635103U, // SBB16mr
+ 138548447U, // SBB16ri
+ 138548447U, // SBB16ri8
+ 138679519U, // SBB16rm
+ 138548447U, // SBB16rr
+ 138548447U, // SBB16rr_REV
+ 134223076U, // SBB32i32
+ 406852831U, // SBB32mi
+ 406852831U, // SBB32mi8
+ 406852831U, // SBB32mr
+ 138548447U, // SBB32ri
+ 138548447U, // SBB32ri8
+ 138810591U, // SBB32rm
+ 138548447U, // SBB32rr
+ 138548447U, // SBB32rr_REV
+ 134223087U, // SBB64i32
+ 541070559U, // SBB64mi32
+ 541070559U, // SBB64mi8
+ 541070559U, // SBB64mr
+ 138548447U, // SBB64ri32
+ 138548447U, // SBB64ri8
+ 138941663U, // SBB64rm
+ 138548447U, // SBB64rr
+ 138548447U, // SBB64rr_REV
+ 134223098U, // SBB8i8
+ 675288287U, // SBB8mi
+ 675288287U, // SBB8mr
+ 138548447U, // SBB8ri
+ 139072735U, // SBB8rm
+ 138548447U, // SBB8rr
+ 138548447U, // SBB8rr_REV
+ 5380U, // SCAS16
+ 5380U, // SCAS32
+ 5380U, // SCAS64
+ 5380U, // SCAS8
+ 671094025U, // SETAEm
+ 134223113U, // SETAEr
+ 671094032U, // SETAm
+ 134223120U, // SETAr
+ 671094038U, // SETBEm
+ 134223126U, // SETBEr
+ 140776671U, // SETB_C16r
+ 140776671U, // SETB_C32r
+ 140776671U, // SETB_C64r
+ 140776671U, // SETB_C8r
+ 671094045U, // SETBm
+ 134223133U, // SETBr
+ 671094051U, // SETEm
+ 134223139U, // SETEr
+ 671094057U, // SETGEm
+ 134223145U, // SETGEr
+ 671094064U, // SETGm
+ 134223152U, // SETGr
+ 671094070U, // SETLEm
+ 134223158U, // SETLEr
+ 671094077U, // SETLm
+ 134223165U, // SETLr
+ 671094083U, // SETNEm
+ 134223171U, // SETNEr
+ 671094090U, // SETNOm
+ 134223178U, // SETNOr
+ 671094097U, // SETNPm
+ 134223185U, // SETNPr
+ 671094104U, // SETNSm
+ 134223192U, // SETNSr
+ 671094111U, // SETOm
+ 134223199U, // SETOr
+ 671094117U, // SETPm
+ 134223205U, // SETPr
+ 671094123U, // SETSm
+ 134223211U, // SETSr
+ 5489U, // SFENCE
+ 1744835960U, // SGDTm
+ 268440958U, // SHL16m1
+ 352327038U, // SHL16mCL
+ 272635262U, // SHL16mi
+ 134223230U, // SHL16r1
+ 218109310U, // SHL16rCL
+ 138548606U, // SHL16ri
+ 402658686U, // SHL32m1
+ 486544766U, // SHL32mCL
+ 406852990U, // SHL32mi
+ 134223230U, // SHL32r1
+ 218109310U, // SHL32rCL
+ 138548606U, // SHL32ri
+ 536876414U, // SHL64m1
+ 624956798U, // SHL64mCL
+ 541070718U, // SHL64mi
+ 134223230U, // SHL64r1
+ 222303614U, // SHL64rCL
+ 138548606U, // SHL64ri
+ 671094142U, // SHL8m1
+ 754980222U, // SHL8mCL
+ 675288446U, // SHL8mi
+ 134223230U, // SHL8r1
+ 218109310U, // SHL8rCL
+ 138548606U, // SHL8ri
+ 272700803U, // SHLD16mrCL
+ 272651651U, // SHLD16mri8
+ 138614147U, // SHLD16rrCL
+ 138564995U, // SHLD16rri8
+ 406918531U, // SHLD32mrCL
+ 406869379U, // SHLD32mri8
+ 138614147U, // SHLD32rrCL
+ 138564995U, // SHLD32rri8
+ 541152643U, // SHLD64mrCL
+ 541087107U, // SHLD64mri8
+ 138630531U, // SHLD64rrCL
+ 138564995U, // SHLD64rri8
+ 268440969U, // SHR16m1
+ 352327049U, // SHR16mCL
+ 272635273U, // SHR16mi
+ 134223241U, // SHR16r1
+ 218109321U, // SHR16rCL
+ 138548617U, // SHR16ri
+ 402658697U, // SHR32m1
+ 486544777U, // SHR32mCL
+ 406853001U, // SHR32mi
+ 134223241U, // SHR32r1
+ 218109321U, // SHR32rCL
+ 138548617U, // SHR32ri
+ 536876425U, // SHR64m1
+ 624956809U, // SHR64mCL
+ 541070729U, // SHR64mi
+ 134223241U, // SHR64r1
+ 222303625U, // SHR64rCL
+ 138548617U, // SHR64ri
+ 671094153U, // SHR8m1
+ 754980233U, // SHR8mCL
+ 675288457U, // SHR8mi
+ 134223241U, // SHR8r1
+ 218109321U, // SHR8rCL
+ 138548617U, // SHR8ri
+ 272700814U, // SHRD16mrCL
+ 272651662U, // SHRD16mri8
+ 138614158U, // SHRD16rrCL
+ 138565006U, // SHRD16rri8
+ 406918542U, // SHRD32mrCL
+ 406869390U, // SHRD32mri8
+ 138614158U, // SHRD32rrCL
+ 138565006U, // SHRD32rri8
+ 541152654U, // SHRD64mrCL
+ 541087118U, // SHRD64mri8
+ 138630542U, // SHRD64rrCL
+ 138565006U, // SHRD64rri8
+ 139220372U, // SHUFPDrmi
+ 138565012U, // SHUFPDrri
+ 139220380U, // SHUFPSrmi
+ 138565020U, // SHUFPSrri
+ 1744836004U, // SIDTm
+ 5546U, // SIN_F
0U, // SIN_Fp32
0U, // SIN_Fp64
0U, // SIN_Fp80
- 140383183U, // SQRTPDm
- 140383183U, // SQRTPDm_Int
- 139858895U, // SQRTPDr
- 139858895U, // SQRTPDr_Int
- 140383191U, // SQRTPSm
- 140383191U, // SQRTPSm_Int
- 139858903U, // SQRTPSr
- 139858903U, // SQRTPSr_Int
- 140514271U, // SQRTSDm
- 140514271U, // SQRTSDm_Int
- 139858911U, // SQRTSDr
- 139858911U, // SQRTSDr_Int
- 140645351U, // SQRTSSm
- 140645351U, // SQRTSSm_Int
- 139858919U, // SQRTSSr
- 139858919U, // SQRTSSr_Int
- 5103U, // SQRT_F
+ 268441007U, // SLDT16m
+ 134223279U, // SLDT16r
+ 268441007U, // SLDT64m
+ 134223279U, // SLDT64r
+ 268441013U, // SMSW16m
+ 134223285U, // SMSW16r
+ 134223285U, // SMSW32r
+ 134223285U, // SMSW64r
+ 140383675U, // SQRTPDm
+ 140383675U, // SQRTPDm_Int
+ 139859387U, // SQRTPDr
+ 139859387U, // SQRTPDr_Int
+ 140383683U, // SQRTPSm
+ 140383683U, // SQRTPSm_Int
+ 139859395U, // SQRTPSr
+ 139859395U, // SQRTPSr_Int
+ 140514763U, // SQRTSDm
+ 140514763U, // SQRTSDm_Int
+ 139859403U, // SQRTSDr
+ 139859403U, // SQRTSDr_Int
+ 140645843U, // SQRTSSm
+ 140645843U, // SQRTSSm_Int
+ 139859411U, // SQRTSSr
+ 139859411U, // SQRTSSr_Int
+ 5595U, // SQRT_F
0U, // SQRT_Fp32
0U, // SQRT_Fp64
0U, // SQRT_Fp80
- 402658293U, // STMXCSR
- 805311486U, // ST_F32m
- 939529214U, // ST_F64m
- 805311491U, // ST_FP32m
- 939529219U, // ST_FP64m
- 2013271043U, // ST_FP80m
- 134222851U, // ST_FPrr
+ 5601U, // STC
+ 5605U, // STD
+ 5609U, // STI
+ 402658797U, // STMXCSR
+ 5622U, // STRm
+ 5622U, // STRr
+ 805311995U, // ST_F32m
+ 939529723U, // ST_F64m
+ 805312000U, // ST_FP32m
+ 939529728U, // ST_FP64m
+ 2147489280U, // ST_FP80m
+ 134223360U, // ST_FPrr
0U, // ST_Fp32m
0U, // ST_Fp64m
0U, // ST_Fp64m32
@@ -2068,47 +2286,51 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ST_FpP80m
0U, // ST_FpP80m32
0U, // ST_FpP80m64
- 134222846U, // ST_Frr
- 134222857U, // SUB16i16
- 272634899U, // SUB16mi
- 272634899U, // SUB16mi8
- 272634899U, // SUB16mr
- 138548243U, // SUB16ri
- 138548243U, // SUB16ri8
- 138679315U, // SUB16rm
- 138548243U, // SUB16rr
- 134222872U, // SUB32i32
- 406852627U, // SUB32mi
- 406852627U, // SUB32mi8
- 406852627U, // SUB32mr
- 138548243U, // SUB32ri
- 138548243U, // SUB32ri8
- 138810387U, // SUB32rm
- 138548243U, // SUB32rr
- 134222883U, // SUB64i32
- 541070355U, // SUB64mi32
- 541070355U, // SUB64mi8
- 541070355U, // SUB64mr
- 138548243U, // SUB64ri32
- 138548243U, // SUB64ri8
- 138941459U, // SUB64rm
- 138548243U, // SUB64rr
- 134222894U, // SUB8i8
- 675288083U, // SUB8mi
- 675288083U, // SUB8mr
- 138548243U, // SUB8ri
- 139072531U, // SUB8rm
- 138548243U, // SUB8rr
- 139203640U, // SUBPDrm
- 138548280U, // SUBPDrr
- 139203647U, // SUBPSrm
- 138548287U, // SUBPSrr
- 805311558U, // SUBR_F32m
- 939529286U, // SUBR_F64m
- 268440653U, // SUBR_FI16m
- 402658381U, // SUBR_FI32m
- 134222933U, // SUBR_FPrST0
- 134222918U, // SUBR_FST0r
+ 134223355U, // ST_Frr
+ 134223366U, // SUB16i16
+ 272635408U, // SUB16mi
+ 272635408U, // SUB16mi8
+ 272635408U, // SUB16mr
+ 138548752U, // SUB16ri
+ 138548752U, // SUB16ri8
+ 138679824U, // SUB16rm
+ 138548752U, // SUB16rr
+ 138548752U, // SUB16rr_REV
+ 134223381U, // SUB32i32
+ 406853136U, // SUB32mi
+ 406853136U, // SUB32mi8
+ 406853136U, // SUB32mr
+ 138548752U, // SUB32ri
+ 138548752U, // SUB32ri8
+ 138810896U, // SUB32rm
+ 138548752U, // SUB32rr
+ 138548752U, // SUB32rr_REV
+ 134223392U, // SUB64i32
+ 541070864U, // SUB64mi32
+ 541070864U, // SUB64mi8
+ 541070864U, // SUB64mr
+ 138548752U, // SUB64ri32
+ 138548752U, // SUB64ri8
+ 138941968U, // SUB64rm
+ 138548752U, // SUB64rr
+ 138548752U, // SUB64rr_REV
+ 134223403U, // SUB8i8
+ 675288592U, // SUB8mi
+ 675288592U, // SUB8mr
+ 138548752U, // SUB8ri
+ 139073040U, // SUB8rm
+ 138548752U, // SUB8rr
+ 138548752U, // SUB8rr_REV
+ 139204149U, // SUBPDrm
+ 138548789U, // SUBPDrr
+ 139204156U, // SUBPSrm
+ 138548796U, // SUBPSrr
+ 805312067U, // SUBR_F32m
+ 939529795U, // SUBR_F64m
+ 268441162U, // SUBR_FI16m
+ 402658890U, // SUBR_FI32m
+ 134223442U, // SUBR_FPrST0
+ 134223427U, // SUBR_FST0r
0U, // SUBR_Fp32m
0U, // SUBR_Fp64m
0U, // SUBR_Fp64m32
@@ -2120,21 +2342,21 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUBR_FpI32m32
0U, // SUBR_FpI32m64
0U, // SUBR_FpI32m80
- 142611526U, // SUBR_FrST0
- 139334749U, // SUBSDrm
- 139334749U, // SUBSDrm_Int
- 138548317U, // SUBSDrr
- 138548317U, // SUBSDrr_Int
- 139465828U, // SUBSSrm
- 139465828U, // SUBSSrm_Int
- 138548324U, // SUBSSrr
- 138548324U, // SUBSSrr_Int
- 805311595U, // SUB_F32m
- 939529323U, // SUB_F64m
- 268440689U, // SUB_FI16m
- 402658417U, // SUB_FI32m
- 134222968U, // SUB_FPrST0
- 134222955U, // SUB_FST0r
+ 142612035U, // SUBR_FrST0
+ 139335258U, // SUBSDrm
+ 139335258U, // SUBSDrm_Int
+ 138548826U, // SUBSDrr
+ 138548826U, // SUBSDrr_Int
+ 139466337U, // SUBSSrm
+ 139466337U, // SUBSSrm_Int
+ 138548833U, // SUBSSrr
+ 138548833U, // SUBSSrr_Int
+ 805312104U, // SUB_F32m
+ 939529832U, // SUB_F64m
+ 268441198U, // SUB_FI16m
+ 402658926U, // SUB_FI32m
+ 134223477U, // SUB_FPrST0
+ 134223464U, // SUB_FST0r
0U, // SUB_Fp32
0U, // SUB_Fp32m
0U, // SUB_Fp64
@@ -2149,116 +2371,159 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUB_FpI32m32
0U, // SUB_FpI32m64
0U, // SUB_FpI32m80
- 142611563U, // SUB_FrST0
- 5247U, // SYSCALL
- 5255U, // SYSENTER
- 5264U, // SYSEXIT
- 5264U, // SYSEXIT64
- 5272U, // SYSRET
- 1174407723U, // TAILJMPd
- 503319083U, // TAILJMPm
- 234883627U, // TAILJMPr
- 234883627U, // TAILJMPr64
- 239080607U, // TCRETURNdi
- 239080607U, // TCRETURNdi64
- 239080607U, // TCRETURNri
- 239080607U, // TCRETURNri64
- 134223019U, // TEST16i16
- 272635062U, // TEST16mi
- 139859126U, // TEST16ri
- 139728054U, // TEST16rm
- 139859126U, // TEST16rr
- 134223036U, // TEST32i32
- 406852790U, // TEST32mi
- 139859126U, // TEST32ri
- 139990198U, // TEST32rm
- 139859126U, // TEST32rr
- 134223048U, // TEST64i32
- 541070518U, // TEST64mi32
- 139859126U, // TEST64ri32
- 140121270U, // TEST64rm
- 139859126U, // TEST64rr
- 134223060U, // TEST8i8
- 675288246U, // TEST8mi
- 139859126U, // TEST8ri
- 140252342U, // TEST8rm
- 139859126U, // TEST8rr
- 2952795359U, // TLS_addr32
- 3087013093U, // TLS_addr64
- 5367U, // TRAP
- 5371U, // TST_F
+ 142612072U, // SUB_FrST0
+ 5756U, // SWPGS
+ 5762U, // SYSCALL
+ 5770U, // SYSENTER
+ 5779U, // SYSEXIT
+ 5779U, // SYSEXIT64
+ 5787U, // SYSRET
+ 1166019449U, // TAILJMPd
+ 494930809U, // TAILJMPm
+ 226495353U, // TAILJMPr
+ 226495353U, // TAILJMPr64
+ 230692514U, // TCRETURNdi
+ 230692514U, // TCRETURNdi64
+ 230692514U, // TCRETURNri
+ 230692514U, // TCRETURNri64
+ 134223534U, // TEST16i16
+ 272635577U, // TEST16mi
+ 139859641U, // TEST16ri
+ 139728569U, // TEST16rm
+ 139859641U, // TEST16rr
+ 134223551U, // TEST32i32
+ 406853305U, // TEST32mi
+ 139859641U, // TEST32ri
+ 139990713U, // TEST32rm
+ 139859641U, // TEST32rr
+ 134223563U, // TEST64i32
+ 541071033U, // TEST64mi32
+ 139859641U, // TEST64ri32
+ 140121785U, // TEST64rm
+ 139859641U, // TEST64rr
+ 134223575U, // TEST8i8
+ 675288761U, // TEST8mi
+ 139859641U, // TEST8ri
+ 140252857U, // TEST8rm
+ 139859641U, // TEST8rr
+ 2952795874U, // TLS_addr32
+ 3087013608U, // TLS_addr64
+ 5882U, // TRAP
+ 5886U, // TST_F
0U, // TST_Fp32
0U, // TST_Fp64
0U, // TST_Fp80
- 140511723U, // UCOMISDrm
- 139856363U, // UCOMISDrr
- 140642804U, // UCOMISSrm
- 139856372U, // UCOMISSrr
- 134223104U, // UCOM_FIPr
- 134223121U, // UCOM_FIr
- 5409U, // UCOM_FPPr
- 134223145U, // UCOM_FPr
+ 140512057U, // UCOMISDrm
+ 139856697U, // UCOMISDrr
+ 140643138U, // UCOMISSrm
+ 139856706U, // UCOMISSrr
+ 134223619U, // UCOM_FIPr
+ 134223636U, // UCOM_FIr
+ 5924U, // UCOM_FPPr
+ 134223660U, // UCOM_FPr
0U, // UCOM_FpIr32
0U, // UCOM_FpIr64
0U, // UCOM_FpIr80
0U, // UCOM_Fpr32
0U, // UCOM_Fpr64
0U, // UCOM_Fpr80
- 134223153U, // UCOM_Fr
- 139203896U, // UNPCKHPDrm
- 138548536U, // UNPCKHPDrr
- 139203906U, // UNPCKHPSrm
- 138548546U, // UNPCKHPSrr
- 139203916U, // UNPCKLPDrm
- 138548556U, // UNPCKLPDrr
- 139203926U, // UNPCKLPSrm
- 138548566U, // UNPCKLPSrr
- 139875680U, // VASTART_SAVE_XMM_REGS
- 140773564U, // V_SET0
- 140774449U, // V_SETALLONES
- 5496U, // WAIT
- 536871932U, // WINCALL64m
- 1073742844U, // WINCALL64pcrel32
- 134218748U, // WINCALL64r
- 2147489149U, // XCHG16rm
- 1799361917U, // XCHG32rm
- 2281706877U, // XCHG64rm
- 2415924605U, // XCHG8rm
- 134223235U, // XCH_F
- 134223241U, // XOR16i16
- 272633266U, // XOR16mi
- 272633266U, // XOR16mi8
- 272633266U, // XOR16mr
- 138546610U, // XOR16ri
- 138546610U, // XOR16ri8
- 138677682U, // XOR16rm
- 138546610U, // XOR16rr
- 134223251U, // XOR32i32
- 406850994U, // XOR32mi
- 406850994U, // XOR32mi8
- 406850994U, // XOR32mr
- 138546610U, // XOR32ri
- 138546610U, // XOR32ri8
- 138808754U, // XOR32rm
- 138546610U, // XOR32rr
- 134223262U, // XOR64i32
- 541068722U, // XOR64mi32
- 541068722U, // XOR64mi8
- 541068722U, // XOR64mr
- 138546610U, // XOR64ri32
- 138546610U, // XOR64ri8
- 138939826U, // XOR64rm
- 138546610U, // XOR64rr
- 134223273U, // XOR8i8
- 675286450U, // XOR8mi
- 675286450U, // XOR8mr
- 138546610U, // XOR8ri
- 139070898U, // XOR8rm
- 138546610U, // XOR8rr
- 139200693U, // XORPDrm
- 138545333U, // XORPDrr
- 139200700U, // XORPSrm
- 138545340U, // XORPSrr
+ 134223668U, // UCOM_Fr
+ 139204411U, // UNPCKHPDrm
+ 138549051U, // UNPCKHPDrr
+ 139204421U, // UNPCKHPSrm
+ 138549061U, // UNPCKHPSrr
+ 139204431U, // UNPCKLPDrm
+ 138549071U, // UNPCKLPDrr
+ 139204441U, // UNPCKLPSrm
+ 138549081U, // UNPCKLPSrr
+ 139876195U, // VASTART_SAVE_XMM_REGS
+ 268441467U, // VERRm
+ 134223739U, // VERRr
+ 268441473U, // VERWm
+ 134223745U, // VERWr
+ 6023U, // VMCALL
+ 536876942U, // VMCLEARm
+ 6039U, // VMLAUNCH
+ 536876960U, // VMPTRLDm
+ 536876969U, // VMPTRSTm
+ 406853554U, // VMREAD32rm
+ 139859890U, // VMREAD32rr
+ 541071282U, // VMREAD64rm
+ 139859890U, // VMREAD64rr
+ 6074U, // VMRESUME
+ 139990979U, // VMWRITE32rm
+ 139859907U, // VMWRITE32rr
+ 140122051U, // VMWRITE64rm
+ 139859907U, // VMWRITE64rr
+ 6092U, // VMXOFF
+ 6099U, // VMXON
+ 140773917U, // V_SET0
+ 140774842U, // V_SETALLONES
+ 6106U, // WAIT
+ 6111U, // WBINVD
+ 536871947U, // WINCALL64m
+ 1073742859U, // WINCALL64pcrel32
+ 134218763U, // WINCALL64r
+ 6118U, // WRMSR
+ 272635884U, // XADD16rm
+ 139859948U, // XADD16rr
+ 406853612U, // XADD32rm
+ 139859948U, // XADD32rr
+ 541071340U, // XADD64rm
+ 139859948U, // XADD64rr
+ 675289068U, // XADD8rm
+ 139859948U, // XADD8rr
+ 134223858U, // XCHG16ar
+ 2281707517U, // XCHG16rm
+ 3221231613U, // XCHG16rr
+ 134223875U, // XCHG32ar
+ 2415925245U, // XCHG32rm
+ 3221231613U, // XCHG32rr
+ 134223887U, // XCHG64ar
+ 3355449341U, // XCHG64rm
+ 3221231613U, // XCHG64rr
+ 2550142973U, // XCHG8rm
+ 3221231613U, // XCHG8rr
+ 134223899U, // XCH_F
+ 6177U, // XLAT
+ 134223911U, // XOR16i16
+ 272633659U, // XOR16mi
+ 272633659U, // XOR16mi8
+ 272633659U, // XOR16mr
+ 138547003U, // XOR16ri
+ 138547003U, // XOR16ri8
+ 138678075U, // XOR16rm
+ 138547003U, // XOR16rr
+ 138547003U, // XOR16rr_REV
+ 134223921U, // XOR32i32
+ 406851387U, // XOR32mi
+ 406851387U, // XOR32mi8
+ 406851387U, // XOR32mr
+ 138547003U, // XOR32ri
+ 138547003U, // XOR32ri8
+ 138809147U, // XOR32rm
+ 138547003U, // XOR32rr
+ 138547003U, // XOR32rr_REV
+ 134223932U, // XOR64i32
+ 541069115U, // XOR64mi32
+ 541069115U, // XOR64mi8
+ 541069115U, // XOR64mr
+ 138547003U, // XOR64ri32
+ 138547003U, // XOR64ri8
+ 138940219U, // XOR64rm
+ 138547003U, // XOR64rr
+ 138547003U, // XOR64rr_REV
+ 134223943U, // XOR8i8
+ 675286843U, // XOR8mi
+ 675286843U, // XOR8mr
+ 138547003U, // XOR8ri
+ 139071291U, // XOR8rm
+ 138547003U, // XOR8rr
+ 138547003U, // XOR8rr_REV
+ 139201046U, // XORPDrm
+ 138545686U, // XORPDrr
+ 139201053U, // XORPSrm
+ 138545693U, // XORPSrr
0U
};
@@ -2280,98 +2545,112 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
"DO!\000#ATOMUMIN16 PSEUDO!\000#ATOMUMIN32 PSEUDO!\000#ATOMUMIN64 PSEUDO"
"!\000#ATOMXOR16 PSEUDO!\000#ATOMXOR32 PSEUDO!\000#ATOMXOR64 PSEUDO!\000"
"#ATOMXOR6432 PSEUDO!\000#ATOMXOR8 PSEUDO!\000blendpd\t\000blendps\t\000"
- "blendvpd\t\000blendvps\t\000bsf\t\000bsr\t\000bswap\t\000bt\t\000call\t"
- "\000cbw\000cdq\000cdqe\000fchs\000clflush\t\000cmova\t\000cmovae\t\000c"
- "movb\t\000cmovbe\t\000fcmovbe\t%ST(0), \000fcmovb\t%ST(0), \000cmove\t\000"
- "fcmove\t%ST(0), \000cmovg\t\000cmovge\t\000cmovl\t\000cmovle\t\000fcmov"
- "nbe\t%ST(0), \000fcmovnb\t%ST(0), \000cmovne\t\000fcmovne\t%ST(0), \000"
- "cmovno\t\000cmovnp\t\000fcmovnu\t%ST(0), \000cmovns\t\000cmovo\t\000cmo"
- "vp\t\000fcmovu\t %ST(0), \000cmovs\t\000#CMOV_FR32 PSEUDO!\000#CMOV_FR6"
- "4 PSEUDO!\000#CMOV_GR8 PSEUDO!\000#CMOV_V1I64 PSEUDO!\000#CMOV_V2F64 PS"
- "EUDO!\000#CMOV_V2I64 PSEUDO!\000#CMOV_V4F32 PSEUDO!\000cmp\t%ax, \000cm"
- "p\t\000cmp\t%eax, \000cmp\t%rax, \000cmp\t%al, \000cmp\000cmps\000comis"
- "d\t\000fcos\000cqo\000crc32 \t\000cvtdq2pd\t\000cvtdq2ps\t\000cvtpd2dq\t"
- "\000cvtps2dq\t\000cvtsd2ss\t\000cvtsi2sd\t\000cvtsi2ss\t\000cvtss2sd\t\000"
- "cvttsd2si\t\000cvttss2si\t\000cwd\000cwde\000dec\t\000div\t\000divpd\t\000"
- "divps\t\000fdivr\t\000fidivr\t\000fdivrp\t\000divsd\t\000divss\t\000fdi"
- "v\t\000fidiv\t\000fdivp\t\000dppd\t\000dpps\t\000ret\t#eh_return, addr:"
- " \000enter\t\000extractps\t\000lcall\t\000ljmp\t\000fbld\t\000fbstp\t\000"
- "fcom\t\000fcomp\t\000ficom\t\000ficomp\t\000fisttp\t\000fldcw\t\000flde"
- "nv\t\000fnstcw\t\000fnstsw\000##FP32_TO_INT16_IN_MEM PSEUDO!\000##FP32_"
- "TO_INT32_IN_MEM PSEUDO!\000##FP32_TO_INT64_IN_MEM PSEUDO!\000##FP64_TO_"
- "INT16_IN_MEM PSEUDO!\000##FP64_TO_INT32_IN_MEM PSEUDO!\000##FP64_TO_INT"
- "64_IN_MEM PSEUDO!\000##FP80_TO_INT16_IN_MEM PSEUDO!\000##FP80_TO_INT32_"
- "IN_MEM PSEUDO!\000##FP80_TO_INT64_IN_MEM PSEUDO!\000##FP_REG_KILL\000fr"
- "stor\t\000fsave\t\000fstenv\t\000fstsw\t\000movl\t%fs:\000pxor\t\000mov"
- "apd\t\000movaps\t\000orpd\t\000orps\t\000xorpd\t\000xorps\t\000movl\t%g"
- "s:\000haddpd\t\000haddps\t\000hsubpd\t\000hsubps\t\000idiv\t\000fild\t\000"
- "imul\t\000in\t%AX, \000in\t%AX, %DX\000in\t%EAX, \000in\t%EAX, %DX\000i"
- "n\t%AL, \000in\t%AL, %DX\000inc\t\000insertps\t\000int\t\000int\t3\000f"
- "ist\t\000fistp\t\000comiss\t\000cvtpd2pi\t\000cvtpd2ps\t\000cvtpi2pd\t\000"
- "cvtpi2ps\t\000cvtps2pd\t\000cvtps2pi\t\000cvtsd2si\t\000cvtss2si\t\000c"
- "vttpd2dq\t\000cvttpd2pi\t\000cvttps2dq\t\000cvttps2pi\t\000ucomisd\t\000"
- "ucomiss\t\000ja\t\000jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t\000jg\t\000"
- "jge\t\000jl\t\000jle\t\000jmp\t\000jne\t\000jno\t\000jnp\t\000jns\t\000"
- "jo\t\000jp\t\000js\t\000lahf\000lar\t\000lock\n\tcmpxchg\t\000lock\n\tc"
- "mpxchgq\t\000lock\n\tcmpxchg8b\t\000lddqu\t\000ldmxcsr\t\000fldz\000fld"
- "1\000fld\t\000lea\t\000leave\000lfence\000lock\n\tadd\t\000lock\n\tdec\t"
- "\000lock\n\tinc\t\000lock\n\tsub\t\000lodsb\000lodsd\000lodsq\000lodsw\000"
- "loop\t\000loope\t\000loopne\t\000lret\000lret\t\000lock\n\txadd\t\000ma"
- "skmovdqu\t\000maxpd\t\000maxps\t\000maxsd\t\000maxss\t\000mfence\000min"
- "pd\t\000minps\t\000minsd\t\000minss\t\000emms\000femms\000maskmovq\t\000"
- "movd\t\000movdq2q\t\000movntq\t\000movq2dq\t\000movq\t\000packssdw\t\000"
- "packsswb\t\000packuswb\t\000paddb\t\000paddd\t\000paddq\t\000paddsb\t\000"
- "paddsw\t\000paddusb\t\000paddusw\t\000paddw\t\000pandn\t\000pand\t\000p"
- "avgb\t\000pavgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000"
- "pcmpgtd\t\000pcmpgtw\t\000pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t"
- "\000pmaxub\t\000pminsw\t\000pminub\t\000pmovmskb\t\000pmulhuw\t\000pmul"
- "hw\t\000pmullw\t\000pmuludq\t\000por\t\000psadbw\t\000pshufw\t\000pslld"
- "\t\000psllq\t\000psllw\t\000psrad\t\000psraw\t\000psrld\t\000psrlq\t\000"
- "psrlw\t\000psubb\t\000psubd\t\000psubq\t\000psubsb\t\000psubsw\t\000psu"
- "busb\t\000psubusw\t\000psubw\t\000punpckhbw\t\000punpckhdq\t\000punpckh"
- "wd\t\000punpcklbw\t\000punpckldq\t\000punpcklwd\t\000monitor\000mov\t\000"
- "mov\t%ax, \000mov\t%eax, \000xor\t\000movq\t%fs:\000movq\t%gs:\000mov\t"
- "%rax, \000movabs\t\000mov\t%al, \000movddup\t\000movdqa\t\000movdqu\t\000"
- "movhlps\t\000movhpd\t\000movhps\t\000movlhps\t\000movlpd\t\000movsd\t\000"
- "movlps\t\000movss\t\000movmskpd\t\000movmskps\t\000movntdqa\t\000movntd"
- "q\t\000movnti\t\000movntpd\t\000movntps\t\000movshdup\t\000movsldup\t\000"
- "movsx\t\000movsxd\t\000movupd\t\000movups\t\000movzx\t\000mpsadbw\t\000"
- "mul\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmul\t\000fimul\t\000"
- "fmulp\t\000mwait\000neg\t\000nop\000nopl\t\000not\t\000or\t%ax, \000or\t"
- "\000or\t%eax, \000or\t%rax, \000or\t%al, \000out\t\000out\t%DX, %AX\000"
- "out\t%DX, %EAX\000out\t%DX, %AL\000pabsb\t\000pabsd\t\000pabsw\t\000pac"
- "kusdw\t\000palignr\t\000pblendvb\t\000pblendw\t\000pcmpeqq\t\000pcmpest"
- "ri\t\000#PCMPESTRM128rm PSEUDO!\000#PCMPESTRM128rr PSEUDO!\000pcmpestrm"
- "\t\000pcmpgtq\t\000pcmpistri\t\000#PCMPISTRM128rm PSEUDO!\000#PCMPISTRM"
- "128rr PSEUDO!\000pcmpistrm\t\000pextrb\t\000pextrd\t\000pextrq\t\000pha"
- "ddd\t\000phaddsw\t\000phaddw\t\000phminposuw\t\000phsubd\t\000phsubsw\t"
- "\000phsubw\t\000pinsrb\t\000pinsrd\t\000pinsrq\t\000pmaddubsw\t\000pmax"
- "sb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t\000pminsb\t\000pminsd\t\000pmi"
- "nud\t\000pminuw\t\000pmovsxbd\t\000pmovsxbq\t\000pmovsxbw\t\000pmovsxdq"
- "\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzxbd\t\000pmovzxbq\t\000pmovzxbw\t"
- "\000pmovzxdq\t\000pmovzxwd\t\000pmovzxwq\t\000pmuldq\t\000pmulhrsw\t\000"
- "pmulld\t\000pop\t\000popf\000prefetchnta\t\000prefetcht0\t\000prefetcht"
- "1\t\000prefetcht2\t\000pshufb\t\000pshufd\t\000pshufhw\t\000pshuflw\t\000"
- "psignb\t\000psignd\t\000psignw\t\000pslldq\t\000psrldq\t\000ptest \t\000"
- "punpckhqdq\t\000punpcklqdq\t\000push\t\000pushf\000rcl\t\000rcpps\t\000"
- "rcpss\t\000rcr\t\000rdtsc\000rep movsb\000rep movsd\000rep movsq\000rep"
- " movsw\000rep stosb\000rep stosd\000rep stosq\000rep stosw\000ret\000re"
- "t\t\000rol\t\000ror\t\000roundpd\t\000roundps\t\000roundsd\t\000roundss"
- "\t\000rsqrtps\t\000rsqrtss\t\000sahf\000sar\t\000sbb\t%ax, \000sbb\t\000"
- "sbb\t%eax, \000sbb\t%rax, \000sbb\t%al, \000scas\000setae\t\000seta\t\000"
- "setbe\t\000setb\t\000sete\t\000setge\t\000setg\t\000setle\t\000setl\t\000"
- "setne\t\000setno\t\000setnp\t\000setns\t\000seto\t\000setp\t\000sets\t\000"
- "sfence\000shl\t\000shr\t\000shld\t\000shrd\t\000shufpd\t\000shufps\t\000"
- "fsin\000sqrtpd\t\000sqrtps\t\000sqrtsd\t\000sqrtss\t\000fsqrt\000stmxcs"
- "r\t\000fst\t\000fstp\t\000sub\t%ax, \000sub\t\000sub\t%eax, \000sub\t%r"
- "ax, \000sub\t%al, \000subpd\t\000subps\t\000fsubr\t\000fisubr\t\000fsub"
- "rp\t\000subsd\t\000subss\t\000fsub\t\000fisub\t\000fsubp\t\000syscall\000"
- "sysenter\000sysexit\000sysret\000#TC_RETURN \000test\t%ax, \000test\t\000"
- "test\t%eax, \000test\t%rax, \000test\t%al, \000leal\t\000.byte\t0x66; l"
- "eaq\t\000ud2\000ftst\000fucomip\t%ST(0), \000fucomi\t%ST(0), \000fucomp"
- "p\000fucomp\t\000fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t\000u"
- "npcklps\t\000#VASTART_SAVE_XMM_REGS \000wait\000xchg\t\000fxch\t\000xor"
- "\t%ax, \000xor\t%eax, \000xor\t%rax, \000xor\t%al, \000";
+ "blendvpd\t\000blendvps\t\000bsf\t\000bsr\t\000bswap\t\000bt\t\000btc\t\000"
+ "btr\t\000bts\t\000call\t\000cbw\000cdq\000cdqe\000fchs\000clc\000cld\000"
+ "clflush\t\000cli\000clts\000cmc\000cmova\t\000cmovae\t\000cmovb\t\000cm"
+ "ovbe\t\000fcmovbe\t%ST(0), \000fcmovb\t%ST(0), \000cmove\t\000fcmove\t%"
+ "ST(0), \000cmovg\t\000cmovge\t\000cmovl\t\000cmovle\t\000fcmovnbe\t%ST("
+ "0), \000fcmovnb\t%ST(0), \000cmovne\t\000fcmovne\t%ST(0), \000cmovno\t\000"
+ "cmovnp\t\000fcmovnu\t%ST(0), \000cmovns\t\000cmovo\t\000cmovp\t\000fcmo"
+ "vu\t %ST(0), \000cmovs\t\000#CMOV_FR32 PSEUDO!\000#CMOV_FR64 PSEUDO!\000"
+ "#CMOV_GR8 PSEUDO!\000#CMOV_V1I64 PSEUDO!\000#CMOV_V2F64 PSEUDO!\000#CMO"
+ "V_V2I64 PSEUDO!\000#CMOV_V4F32 PSEUDO!\000cmp\t%ax, \000cmp\t\000cmp\t%"
+ "eax, \000cmp\t%rax, \000cmp\t%al, \000cmp\000cmps\000cmpxchg16b\t\000cm"
+ "pxchg\t\000cmpxchg8b\t\000comisd\t\000comiss\t\000fcomp\t\000fcomip\t%S"
+ "T(0), \000fcomi\t%ST(0), \000fcom\t\000fcos\000cpuid\000cqo\000crc32 \t"
+ "\000cvtdq2pd\t\000cvtdq2ps\t\000cvtpd2dq\t\000cvtpd2ps\t\000cvtps2dq\t\000"
+ "cvtps2pd\t\000cvtsd2si\t\000cvtsd2ss\t\000cvtsi2sd\t\000cvtsi2ss\t\000c"
+ "vtss2sd\t\000cvtss2si\t\000cvttps2dq\t\000cvttsd2si\t\000cvttss2si\t\000"
+ "cwd\000cwde\000dec\t\000div\t\000divpd\t\000divps\t\000fdivr\t\000fidiv"
+ "r\t\000fdivrp\t\000divsd\t\000divss\t\000fdiv\t\000fidiv\t\000fdivp\t\000"
+ "dppd\t\000dpps\t\000ret\t#eh_return, addr: \000enter\t\000extractps\t\000"
+ "f2xm1\000lcall\t\000ljmp\t\000fbld\t\000fbstp\t\000fcompp\000fdecstp\000"
+ "ffree\t\000ficom\t\000ficomp\t\000fincstp\000fisttp\t\000fldcw\t\000fld"
+ "env\t\000fldl2e\000fldl2t\000fldlg2\000fldln2\000fldpi\000fnclex\000fni"
+ "nit\000fnop\000fnstcw\t\000fnstsw %ax\000fnstsw\t\000##FP32_TO_INT16_IN"
+ "_MEM PSEUDO!\000##FP32_TO_INT32_IN_MEM PSEUDO!\000##FP32_TO_INT64_IN_ME"
+ "M PSEUDO!\000##FP64_TO_INT16_IN_MEM PSEUDO!\000##FP64_TO_INT32_IN_MEM P"
+ "SEUDO!\000##FP64_TO_INT64_IN_MEM PSEUDO!\000##FP80_TO_INT16_IN_MEM PSEU"
+ "DO!\000##FP80_TO_INT32_IN_MEM PSEUDO!\000##FP80_TO_INT64_IN_MEM PSEUDO!"
+ "\000fpatan\000fprem\000fprem1\000fptan\000##FP_REG_KILL\000frndint\000f"
+ "rstor\t\000fnsave\t\000fscale\000fsincos\000fnstenv\t\000movl\t%fs:\000"
+ "fxam\000fxrstor\t\000fxsave\t\000fxtract\000fyl2x\000fyl2xp1\000pxor\t\000"
+ "movapd\t\000movaps\t\000orpd\t\000orps\t\000xorpd\t\000xorps\t\000movl\t"
+ "%gs:\000haddpd\t\000haddps\t\000hlt\000hsubpd\t\000hsubps\t\000idiv\t\000"
+ "fild\t\000imul\t\000ins\000in\t%AX, \000in\t%AX, %DX\000in\t%EAX, \000i"
+ "n\t%EAX, %DX\000in\t%AL, \000in\t%AL, %DX\000inc\t\000insertps\t\000int"
+ "\t\000int\t3\000invd\000invept\000invlpg\000invvpid\000iret\000fist\t\000"
+ "fistp\t\000cvtpd2pi\t\000cvtpi2pd\t\000cvtpi2ps\t\000cvtps2pi\t\000cvtt"
+ "pd2dq\t\000cvttpd2pi\t\000cvttps2pi\t\000ucomisd\t\000ucomiss\t\000ja\t"
+ "\000jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t\000jg\t\000jge\t\000jl\t\000"
+ "jle\t\000jmp\t\000jne\t\000jno\t\000jnp\t\000jns\t\000jo\t\000jp\t\000j"
+ "s\t\000lahf\000lar\t\000lock\n\tcmpxchg\t\000lock\n\tcmpxchgq\t\000lock"
+ "\n\tcmpxchg8b\t\000lddqu\t\000ldmxcsr\t\000lds\t\000fldz\000fld1\000fld"
+ "\t\000lea\t\000leave\000les\t\000lfence\000lfs\t\000lgdt\t\000lgs\t\000"
+ "lidt\t\000lldt\t\000lmsw\t\000lock\n\tadd\t\000lock\n\tdec\t\000lock\n\t"
+ "inc\t\000lock\n\tsub\t\000lodsb\000lodsd\000lodsq\000lodsw\000loop\t\000"
+ "loope\t\000loopne\t\000lret\000lret\t\000lsl\t\000lss\t\000ltr\t\000loc"
+ "k\n\txadd\t\000maskmovdqu\t\000maxpd\t\000maxps\t\000maxsd\t\000maxss\t"
+ "\000mfence\000minpd\t\000minps\t\000minsd\t\000minss\t\000emms\000femms"
+ "\000maskmovq\t\000movd\t\000movdq2q\t\000movntq\t\000movq2dq\t\000movq\t"
+ "\000packssdw\t\000packsswb\t\000packuswb\t\000paddb\t\000paddd\t\000pad"
+ "dq\t\000paddsb\t\000paddsw\t\000paddusb\t\000paddusw\t\000paddw\t\000pa"
+ "ndn\t\000pand\t\000pavgb\t\000pavgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmp"
+ "eqw\t\000pcmpgtb\t\000pcmpgtd\t\000pcmpgtw\t\000pextrw\t\000pinsrw\t\000"
+ "pmaddwd\t\000pmaxsw\t\000pmaxub\t\000pminsw\t\000pminub\t\000pmovmskb\t"
+ "\000pmulhuw\t\000pmulhw\t\000pmullw\t\000pmuludq\t\000por\t\000psadbw\t"
+ "\000pshufw\t\000pslld\t\000psllq\t\000psllw\t\000psrad\t\000psraw\t\000"
+ "psrld\t\000psrlq\t\000psrlw\t\000psubb\t\000psubd\t\000psubq\t\000psubs"
+ "b\t\000psubsw\t\000psubusb\t\000psubusw\t\000psubw\t\000punpckhbw\t\000"
+ "punpckhdq\t\000punpckhwd\t\000punpcklbw\t\000punpckldq\t\000punpcklwd\t"
+ "\000monitor\000mov\t\000mov\t%ax, \000mov\t%eax, \000xor\t\000movq\t%fs"
+ ":\000movq\t%gs:\000mov\t%rax, \000movabs\t\000mov\t%al, \000movddup\t\000"
+ "movdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000movhps\t\000movlhps\t\000"
+ "movlpd\t\000movsd\t\000movlps\t\000movss\t\000movmskpd\t\000movmskps\t\000"
+ "movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t\000movntps\t\000movshd"
+ "up\t\000movsldup\t\000movsx\t\000movsxd\t\000movupd\t\000movups\t\000mo"
+ "vzx\t\000mpsadbw\t\000mul\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t"
+ "\000fmul\t\000fimul\t\000fmulp\t\000mwait\000neg\t\000nop\000nop\t\000n"
+ "ot\t\000or\t%ax, \000or\t\000or\t%eax, \000or\t%rax, \000or\t%al, \000o"
+ "ut\t\000out\t%DX, %AX\000out\t%DX, %EAX\000out\t%DX, %AL\000outsb\000ou"
+ "tsd\000outsw\000pabsb\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t"
+ "\000pblendvb\t\000pblendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM12"
+ "8rm PSEUDO!\000#PCMPESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000p"
+ "cmpistri\t\000#PCMPISTRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcm"
+ "pistrm\t\000pextrb\t\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000"
+ "phaddw\t\000phminposuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb"
+ "\t\000pinsrd\t\000pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pm"
+ "axud\t\000pmaxuw\t\000pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000p"
+ "movsxbd\t\000pmovsxbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pm"
+ "ovsxwq\t\000pmovzxbd\t\000pmovzxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmo"
+ "vzxwd\t\000pmovzxwq\t\000pmuldq\t\000pmulhrsw\t\000pmulld\t\000pop\t\000"
+ "popcnt\t\000popf\000pop\t%fs\000pop\t%gs\000prefetchnta\t\000prefetcht0"
+ "\t\000prefetcht1\t\000prefetcht2\t\000pshufb\t\000pshufd\t\000pshufhw\t"
+ "\000pshuflw\t\000psignb\t\000psignd\t\000psignw\t\000pslldq\t\000psrldq"
+ "\t\000ptest \t\000punpckhqdq\t\000punpcklqdq\t\000push\t\000pushf\000pu"
+ "sh\t%fs\000push\t%gs\000rcl\t\000rcpps\t\000rcpss\t\000rcr\t\000rdmsr\000"
+ "rdpmc\000rdtsc\000rep movsb\000rep movsd\000rep movsq\000rep movsw\000r"
+ "ep stosb\000rep stosd\000rep stosq\000rep stosw\000ret\000ret\t\000rol\t"
+ "\000ror\t\000roundpd\t\000roundps\t\000roundsd\t\000roundss\t\000rsm\000"
+ "rsqrtps\t\000rsqrtss\t\000sahf\000sar\t\000sbb\t%ax, \000sbb\t\000sbb\t"
+ "%eax, \000sbb\t%rax, \000sbb\t%al, \000scas\000setae\t\000seta\t\000set"
+ "be\t\000setb\t\000sete\t\000setge\t\000setg\t\000setle\t\000setl\t\000s"
+ "etne\t\000setno\t\000setnp\t\000setns\t\000seto\t\000setp\t\000sets\t\000"
+ "sfence\000sgdt\t\000shl\t\000shld\t\000shr\t\000shrd\t\000shufpd\t\000s"
+ "hufps\t\000sidt\t\000fsin\000sldt\t\000smsw\t\000sqrtpd\t\000sqrtps\t\000"
+ "sqrtsd\t\000sqrtss\t\000fsqrt\000stc\000std\000sti\000stmxcsr\t\000str\t"
+ "\000fst\t\000fstp\t\000sub\t%ax, \000sub\t\000sub\t%eax, \000sub\t%rax,"
+ " \000sub\t%al, \000subpd\t\000subps\t\000fsubr\t\000fisubr\t\000fsubrp\t"
+ "\000subsd\t\000subss\t\000fsub\t\000fisub\t\000fsubp\t\000swpgs\000sysc"
+ "all\000sysenter\000sysexit\000sysret\000#TC_RETURN \000test\t%ax, \000t"
+ "est\t\000test\t%eax, \000test\t%rax, \000test\t%al, \000leal\t\000.byte"
+ "\t0x66; leaq\t\000ud2\000ftst\000fucomip\t%ST(0), \000fucomi\t%ST(0), \000"
+ "fucompp\000fucomp\t\000fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t"
+ "\000unpcklps\t\000#VASTART_SAVE_XMM_REGS \000verr\t\000verw\t\000vmcall"
+ "\000vmclear\t\000vmlaunch\000vmptrld\t\000vmptrst\t\000vmread\t\000vmre"
+ "sume\000vmwrite\t\000vmxoff\000vmxon\t\000wait\000wbinvd\000wrmsr\000xa"
+ "dd\t\000xchg\t%ax, \000xchg\t\000xchg\t%eax, \000xchg\t%rax, \000fxch\t"
+ "\000xlatb\000xor\t%ax, \000xor\t%eax, \000xor\t%rax, \000xor\t%al, \000";
#ifndef NO_ASM_WRITER_BOILERPLATE
@@ -2399,7 +2678,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
O << AsmStrs+(Bits & 8191)-1;
- // Fragment 0 encoded into 5 bits for 24 unique commands.
+ // Fragment 0 encoded into 5 bits for 26 unique commands.
switch ((Bits >> 27) & 31) {
default: // unreachable.
case 0:
@@ -2407,7 +2686,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 1:
- // ADC16i16, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32i32, ADC32ri, ADC3...
+ // ADC16i16, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16rr_REV, ADC32i32, ...
printOperand(MI, 0);
break;
case 2:
@@ -2447,74 +2726,73 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
printSSECC(MI, 3);
break;
case 11:
+ // CMPXCHG16B, MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr, MOVNTPSmr
+ printi128mem(MI, 0);
+ break;
+ case 12:
// CRC32m16, CRC32m32, CRC32m8, CRC32r16, CRC32r32, CRC32r8, CRC64m64, CR...
printOperand(MI, 1);
O << ", ";
break;
- case 12:
- // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64
+ case 13:
+ // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, FXR...
printopaquemem(MI, 0);
return;
break;
- case 13:
- // FS_MOV32rm, GS_MOV32rm, LXADD32, XCHG32rm
+ case 14:
+ // FS_MOV32rm, GS_MOV32rm
printi32mem(MI, 1);
O << ", ";
+ printOperand(MI, 0);
+ return;
break;
- case 14:
+ case 15:
// LCMPXCHG64
printOperand(MI, 5);
O << ',';
printi64mem(MI, 0);
return;
break;
- case 15:
+ case 16:
// LD_F80m, ST_FP80m
printf80mem(MI, 0);
return;
break;
- case 16:
+ case 17:
// LXADD16, XCHG16rm
- printi16mem(MI, 1);
+ printi16mem(MI, 2);
O << ", ";
- printOperand(MI, 6);
+ printOperand(MI, 1);
return;
break;
- case 17:
- // LXADD64, XCHG64rm
- printOperand(MI, 6);
+ case 18:
+ // LXADD32, XCHG32rm
+ printi32mem(MI, 2);
O << ", ";
- printi64mem(MI, 1);
+ printOperand(MI, 1);
return;
break;
- case 18:
+ case 19:
// LXADD8, XCHG8rm
- printi8mem(MI, 1);
+ printi8mem(MI, 2);
O << ", ";
- printOperand(MI, 6);
+ printOperand(MI, 1);
return;
break;
- case 19:
+ case 20:
// MOV64FSrm, MOV64GSrm
printi64mem(MI, 1);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 20:
+ case 21:
// MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVUPDmr, MOVUPDmr_Int, MOVUPSmr, MOVUP...
printf128mem(MI, 0);
O << ", ";
printOperand(MI, 5);
return;
break;
- case 21:
- // MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr, MOVNTPSmr
- printi128mem(MI, 0);
- O << ", ";
- printOperand(MI, 5);
- return;
- break;
case 22:
// TLS_addr32
printlea32mem(MI, 0);
@@ -2527,10 +2805,24 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
O << "(%rip), %rdi; .word\t0x6666; rex64; call\t__tls_get_addr at PLT";
return;
break;
+ case 24:
+ // XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr
+ printOperand(MI, 2);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 25:
+ // XCHG64rm
+ printi64mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
}
- // Fragment 1 encoded into 5 bits for 26 unique commands.
+ // Fragment 1 encoded into 5 bits for 24 unique commands.
switch ((Bits >> 22) & 31) {
default: // unreachable.
case 0:
@@ -2538,7 +2830,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 1:
- // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32...
+ // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16...
O << ", ";
break;
case 2:
@@ -2591,76 +2883,66 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 11:
- // CRC64m64
+ // CRC64m64, LXADD64
printi64mem(MI, 2);
return;
break;
case 12:
- // FS_MOV32rm, GS_MOV32rm
- printOperand(MI, 0);
- return;
- break;
- case 13:
- // LXADD32, XCHG32rm
- printOperand(MI, 6);
- return;
- break;
- case 14:
// MOV16ao16
O << ", %ax";
return;
break;
- case 15:
+ case 13:
// MOV32ao32
O << ", %eax";
return;
break;
- case 16:
- // MOV64ao32, MOV64ao8
+ case 14:
+ // MOV64ao64, MOV64ao8
O << ", %rax";
return;
break;
- case 17:
+ case 15:
// MOV8ao8
O << ", %al";
return;
break;
- case 18:
+ case 16:
// OUT16ir
O << ", %AX";
return;
break;
- case 19:
+ case 17:
// OUT32ir
O << ", %EAX";
return;
break;
- case 20:
+ case 18:
// OUT8ir
O << ", %AL";
return;
break;
- case 21:
+ case 19:
// RCL16m1, RCL16r1, RCL32m1, RCL32r1, RCL64m1, RCL64r1, RCL8m1, RCL8r1, ...
O << ", 1";
return;
break;
- case 22:
+ case 20:
// RCL16mCL, RCL16rCL, RCL32mCL, RCL32rCL, RCL64mCL, RCL64rCL, RCL8mCL, R...
O << ", CL";
return;
break;
- case 23:
+ case 21:
// ROL64mCL, ROL64rCL, ROR64mCL, ROR64rCL, SAR64mCL, SAR64rCL, SHL64mCL, ...
O << ", %CL";
return;
break;
- case 24:
+ case 22:
// TAILJMPd, TAILJMPm, TAILJMPr, TAILJMPr64
O << " # TAILCALL";
return;
break;
- case 25:
+ case 23:
// TCRETURNdi, TCRETURNdi64, TCRETURNri, TCRETURNri64
O << ' ';
printOperand(MI, 1);
@@ -2669,7 +2951,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
}
- // Fragment 2 encoded into 5 bits for 24 unique commands.
+ // Fragment 2 encoded into 5 bits for 25 unique commands.
switch ((Bits >> 17) & 31) {
default: // unreachable.
case 0:
@@ -2677,7 +2959,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 5);
break;
case 1:
- // ADC16ri, ADC16ri8, ADC16rr, ADC32ri, ADC32ri8, ADC32rr, ADC64ri32, ADC...
+ // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A...
printOperand(MI, 2);
break;
case 2:
@@ -2729,20 +3011,20 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
printi64mem(MI, 1);
break;
case 14:
- // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX32rm8, MOVSX64rm8, MOVZX32_NOREXrm8...
+ // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8W, MOVSX32rm8, MOVSX64rm8, MOV...
printi8mem(MI, 1);
break;
case 15:
- // COMISDrm, CVTDQ2PDrm, CVTDQ2PSrm, CVTPD2DQrm, CVTPS2DQrm, FsMOVAPDrm, ...
+ // COMISDrm, COMISSrm, CVTDQ2PDrm, CVTDQ2PSrm, CVTPD2DQrm, CVTPD2PSrm, CV...
printf128mem(MI, 1);
break;
case 16:
- // CVTSD2SSrm, CVTTSD2SI64rm, CVTTSD2SIrm, Int_CVTPS2PDrm, Int_CVTPS2PIrm...
+ // CVTPS2PDrm, CVTSD2SI64rm, CVTSD2SSrm, CVTTSD2SI64rm, CVTTSD2SIrm, Int_...
printf64mem(MI, 1);
return;
break;
case 17:
- // CVTSS2SDrm, CVTTSS2SI64rm, CVTTSS2SIrm, Int_CVTSS2SI64rm, Int_CVTSS2SI...
+ // CVTSS2SDrm, CVTSS2SI64rm, CVTSS2SIrm, CVTTSS2SI64rm, CVTTSS2SIrm, Int_...
printf32mem(MI, 1);
return;
break;
@@ -2756,21 +3038,26 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
printi128mem(MI, 1);
break;
case 20:
+ // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm...
+ printopaquemem(MI, 1);
+ return;
+ break;
+ case 21:
// LEA16r, LEA32r
printlea32mem(MI, 1);
return;
break;
- case 21:
+ case 22:
// LEA64_32r
printlea64_32mem(MI, 1);
return;
break;
- case 22:
+ case 23:
// LEA64r
printlea64mem(MI, 1);
return;
break;
- case 23:
+ case 24:
// RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi
printOperand(MI, 10);
return;
@@ -2782,7 +3069,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
switch ((Bits >> 14) & 7) {
default: // unreachable.
case 0:
- // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32...
+ // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16...
return;
break;
case 1:
@@ -3049,35 +3336,40 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
/// from the register set description. This returns the assembler name
/// for the specified register.
const char *X86IntelInstPrinter::getRegisterName(unsigned RegNo) {
- assert(RegNo && RegNo < 134 && "Invalid register number!");
+ assert(RegNo && RegNo < 159 && "Invalid register number!");
static const unsigned RegAsmOffset[] = {
0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37, 40,
- 43, 47, 50, 53, 56, 60, 64, 68, 72, 76, 80, 86, 90, 93,
- 97, 101, 105, 109, 113, 117, 121, 125, 129, 132, 135, 138, 142, 146,
- 150, 154, 158, 162, 166, 170, 174, 179, 184, 189, 193, 198, 203, 208,
- 212, 217, 222, 227, 231, 236, 241, 246, 250, 255, 260, 265, 269, 274,
- 279, 284, 287, 291, 295, 299, 302, 306, 310, 314, 318, 322, 326, 330,
- 334, 338, 342, 346, 350, 353, 357, 360, 364, 367, 373, 379, 385, 391,
- 397, 403, 409, 415, 420, 425, 431, 437, 443, 449, 455, 461, 466, 471,
- 476, 481, 486, 491, 496, 501, 506, 511, 517, 523, 529, 535, 541, 547,
- 552, 557, 562, 567, 572, 577, 582, 0
+ 43, 47, 50, 54, 58, 62, 66, 70, 74, 78, 82, 85, 88, 92,
+ 96, 100, 105, 110, 115, 120, 125, 130, 135, 140, 144, 148, 152, 158,
+ 162, 165, 169, 173, 177, 181, 185, 189, 193, 197, 201, 204, 207, 210,
+ 214, 218, 222, 226, 230, 234, 238, 242, 246, 251, 256, 261, 265, 270,
+ 275, 280, 284, 289, 294, 299, 303, 308, 313, 318, 322, 327, 332, 337,
+ 341, 346, 351, 356, 359, 363, 367, 371, 374, 378, 382, 386, 390, 394,
+ 398, 403, 408, 413, 418, 423, 428, 433, 438, 443, 447, 451, 455, 459,
+ 463, 467, 470, 474, 477, 481, 484, 490, 496, 502, 508, 514, 520, 526,
+ 532, 537, 542, 548, 554, 560, 566, 572, 578, 583, 588, 593, 598, 603,
+ 608, 613, 618, 623, 628, 634, 640, 646, 652, 658, 664, 669, 674, 679,
+ 684, 689, 694, 699, 0
};
const char *AsmStrs =
"ah\000al\000ax\000bh\000bl\000bp\000bpl\000bx\000ch\000cl\000cs\000cx\000"
- "dh\000di\000dil\000dl\000ds\000dx\000eax\000ebp\000ebx\000ecx\000edi\000"
- "edx\000flags\000eip\000es\000esi\000esp\000fp0\000fp1\000fp2\000fp3\000"
- "fp4\000fp5\000fp6\000fs\000gs\000ip\000mm0\000mm1\000mm2\000mm3\000mm4\000"
- "mm5\000mm6\000mm7\000r10\000r10b\000r10d\000r10w\000r11\000r11b\000r11d"
- "\000r11w\000r12\000r12b\000r12d\000r12w\000r13\000r13b\000r13d\000r13w\000"
- "r14\000r14b\000r14d\000r14w\000r15\000r15b\000r15d\000r15w\000r8\000r8b"
- "\000r8d\000r8w\000r9\000r9b\000r9d\000r9w\000rax\000rbp\000rbx\000rcx\000"
- "rdi\000rdx\000rip\000rsi\000rsp\000si\000sil\000sp\000spl\000ss\000st(0"
- ")\000st(1)\000st(2)\000st(3)\000st(4)\000st(5)\000st(6)\000st(7)\000xmm"
- "0\000xmm1\000xmm10\000xmm11\000xmm12\000xmm13\000xmm14\000xmm15\000xmm2"
- "\000xmm3\000xmm4\000xmm5\000xmm6\000xmm7\000xmm8\000xmm9\000ymm0\000ymm"
- "1\000ymm10\000ymm11\000ymm12\000ymm13\000ymm14\000ymm15\000ymm2\000ymm3"
- "\000ymm4\000ymm5\000ymm6\000ymm7\000ymm8\000ymm9\000";
+ "dh\000di\000dil\000dl\000dr0\000dr1\000dr2\000dr3\000dr4\000dr5\000dr6\000"
+ "dr7\000ds\000dx\000eax\000ebp\000ebx\000ecr0\000ecr1\000ecr2\000ecr3\000"
+ "ecr4\000ecr5\000ecr6\000ecr7\000ecx\000edi\000edx\000flags\000eip\000es"
+ "\000esi\000esp\000fp0\000fp1\000fp2\000fp3\000fp4\000fp5\000fp6\000fs\000"
+ "gs\000ip\000mm0\000mm1\000mm2\000mm3\000mm4\000mm5\000mm6\000mm7\000r10"
+ "\000r10b\000r10d\000r10w\000r11\000r11b\000r11d\000r11w\000r12\000r12b\000"
+ "r12d\000r12w\000r13\000r13b\000r13d\000r13w\000r14\000r14b\000r14d\000r"
+ "14w\000r15\000r15b\000r15d\000r15w\000r8\000r8b\000r8d\000r8w\000r9\000"
+ "r9b\000r9d\000r9w\000rax\000rbp\000rbx\000rcr0\000rcr1\000rcr2\000rcr3\000"
+ "rcr4\000rcr5\000rcr6\000rcr7\000rcr8\000rcx\000rdi\000rdx\000rip\000rsi"
+ "\000rsp\000si\000sil\000sp\000spl\000ss\000st(0)\000st(1)\000st(2)\000s"
+ "t(3)\000st(4)\000st(5)\000st(6)\000st(7)\000xmm0\000xmm1\000xmm10\000xm"
+ "m11\000xmm12\000xmm13\000xmm14\000xmm15\000xmm2\000xmm3\000xmm4\000xmm5"
+ "\000xmm6\000xmm7\000xmm8\000xmm9\000ymm0\000ymm1\000ymm10\000ymm11\000y"
+ "mm12\000ymm13\000ymm14\000ymm15\000ymm2\000ymm3\000ymm4\000ymm5\000ymm6"
+ "\000ymm7\000ymm8\000ymm9\000";
return AsmStrs+RegAsmOffset[RegNo-1];
}
diff --git a/libclamav/c++/X86GenDAGISel.inc b/libclamav/c++/X86GenDAGISel.inc
index d3b1b43..541f420 100644
--- a/libclamav/c++/X86GenDAGISel.inc
+++ b/libclamav/c++/X86GenDAGISel.inc
@@ -6074,8 +6074,11 @@ SDNode *Select_ISD_ANY_EXTEND_i16(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_72(N, X86::SETB_C16r, MVT::i16);
- return Result;
+ SDValue N01 = N0.getOperand(1);
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_72(N, X86::SETB_C16r, MVT::i16);
+ return Result;
+ }
}
}
}
@@ -6158,8 +6161,11 @@ SDNode *Select_ISD_ANY_EXTEND_i32(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_72(N, X86::SETB_C32r, MVT::i32);
- return Result;
+ SDValue N01 = N0.getOperand(1);
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_72(N, X86::SETB_C32r, MVT::i32);
+ return Result;
+ }
}
}
}
@@ -6234,8 +6240,11 @@ SDNode *Select_ISD_ANY_EXTEND_i64(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_72(N, X86::SETB_C64r, MVT::i64);
- return Result;
+ SDValue N01 = N0.getOperand(1);
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_72(N, X86::SETB_C64r, MVT::i64);
+ return Result;
+ }
}
}
}
@@ -6274,7 +6283,7 @@ DISABLE_INLINE SDNode *Emit_76(const SDValue &N, unsigned Opc0, MVT::SimpleValue
SDValue N2 = N.getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, N2, Chain };
+ SDValue Ops0[] = { N2, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
@@ -6355,6 +6364,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i64(const SDValue &N) {
return NULL;
}
+DISABLE_INLINE SDNode *Emit_77(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, N2, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
SDNode *Select_ISD_ATOMIC_LOAD_AND_i8(const SDValue &N) {
SDValue Chain = N.getOperand(0);
if (Predicate_atomic_load_and_8(N.getNode())) {
@@ -6365,7 +6385,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i8(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6384,7 +6404,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6403,7 +6423,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6422,7 +6442,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6441,7 +6461,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_MAX_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6460,7 +6480,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_MAX_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6479,7 +6499,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_MAX_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6498,7 +6518,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_MIN_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6517,7 +6537,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_MIN_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6536,7 +6556,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_MIN_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6555,7 +6575,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i8(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMNAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMNAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6574,7 +6594,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMNAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMNAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6593,7 +6613,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMNAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMNAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6612,7 +6632,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMNAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMNAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6631,7 +6651,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i8(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6650,7 +6670,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6669,7 +6689,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6688,7 +6708,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6707,7 +6727,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMUMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMUMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6726,7 +6746,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMUMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMUMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6745,7 +6765,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMUMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMUMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6764,7 +6784,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMUMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMUMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6783,7 +6803,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMUMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMUMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6802,7 +6822,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMUMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMUMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6821,7 +6841,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i8(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMXOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMXOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6840,7 +6860,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMXOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMXOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6859,7 +6879,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMXOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMXOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6878,7 +6898,7 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::ATOMXOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::ATOMXOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -7034,7 +7054,7 @@ SDNode *Select_ISD_BIT_CONVERT_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_77(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_78(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -7067,7 +7087,7 @@ SDNode *Select_ISD_BIT_CONVERT_f32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_77(N, X86::MOVDI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MOVDI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -7111,7 +7131,7 @@ SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_77(N, X86::MOV64toSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MOV64toSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -7166,12 +7186,12 @@ SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_78(const SDValue &N) {
+DISABLE_INLINE SDNode *Emit_79(const SDValue &N) {
SDValue N0 = N.getOperand(0);
ReplaceUses(N, N0);
return NULL;
}
-DISABLE_INLINE SDNode *Emit_79(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_80(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -7192,7 +7212,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64 &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_79(N, X86::MMX_MOVDQ2Qrr, MVT::v8i8);
+ SDNode *Result = Emit_80(N, X86::MMX_MOVDQ2Qrr, MVT::v8i8);
return Result;
}
}
@@ -7202,7 +7222,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
// Emits: VR64:v8i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7210,7 +7230,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
// Emits: VR64:v8i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7218,7 +7238,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
// Emits: VR64:v8i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7226,7 +7246,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
// Emits: VR64:v8i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7250,7 +7270,7 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
// Emits: VR128:v16i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7258,7 +7278,7 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
// Emits: VR128:v16i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7266,7 +7286,7 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
// Emits: VR128:v16i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7274,7 +7294,7 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
// Emits: VR128:v16i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7282,7 +7302,7 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
// Emits: VR128:v16i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
}
@@ -7306,7 +7326,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64 &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_79(N, X86::MMX_MOVDQ2Qrr, MVT::v4i16);
+ SDNode *Result = Emit_80(N, X86::MMX_MOVDQ2Qrr, MVT::v4i16);
return Result;
}
}
@@ -7316,7 +7336,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
// Emits: VR64:v4i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7324,7 +7344,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
// Emits: VR64:v4i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7332,7 +7352,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
// Emits: VR64:v4i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7340,7 +7360,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
// Emits: VR64:v4i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7364,7 +7384,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
// Emits: VR128:v8i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7372,7 +7392,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
// Emits: VR128:v8i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7380,7 +7400,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
// Emits: VR128:v8i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7388,7 +7408,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
// Emits: VR128:v8i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7396,7 +7416,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
// Emits: VR128:v8i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
}
@@ -7405,7 +7425,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_80(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0101_0, SDValue &CPTmpN0101_1, SDValue &CPTmpN0101_2, SDValue &CPTmpN0101_3, SDValue &CPTmpN0101_4) {
+DISABLE_INLINE SDNode *Emit_81(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0101_0, SDValue &CPTmpN0101_1, SDValue &CPTmpN0101_2, SDValue &CPTmpN0101_3, SDValue &CPTmpN0101_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -7451,7 +7471,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
if (SelectAddr(N, N0101, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4) &&
N0.getValueType() == MVT::v2i32 &&
N010.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_80(N, X86::MMX_PUNPCKLDQrm, MVT::v2i32, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4);
+ SDNode *Result = Emit_81(N, X86::MMX_PUNPCKLDQrm, MVT::v2i32, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4);
return Result;
}
}
@@ -7474,7 +7494,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64 &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_79(N, X86::MMX_MOVDQ2Qrr, MVT::v2i32);
+ SDNode *Result = Emit_80(N, X86::MMX_MOVDQ2Qrr, MVT::v2i32);
return Result;
}
}
@@ -7484,7 +7504,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
// Emits: VR64:v2i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7492,7 +7512,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
// Emits: VR64:v2i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7500,7 +7520,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
// Emits: VR64:v2i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7508,7 +7528,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
// Emits: VR64:v2i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7532,7 +7552,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
// Emits: VR128:v4i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7540,7 +7560,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
// Emits: VR128:v4i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7548,7 +7568,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
// Emits: VR128:v4i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7556,7 +7576,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
// Emits: VR128:v4i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7564,7 +7584,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
// Emits: VR128:v4i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
}
@@ -7589,7 +7609,7 @@ SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64 &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_79(N, X86::MMX_MOVDQ2Qrr, MVT::v1i64);
+ SDNode *Result = Emit_80(N, X86::MMX_MOVDQ2Qrr, MVT::v1i64);
return Result;
}
}
@@ -7601,7 +7621,7 @@ SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
// Emits: VR64:v1i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7609,7 +7629,7 @@ SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
// Emits: VR64:v1i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7617,7 +7637,7 @@ SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
// Emits: VR64:v1i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7625,7 +7645,7 @@ SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
// Emits: VR64:v1i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7649,7 +7669,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
// Emits: VR128:v2i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7657,7 +7677,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
// Emits: VR128:v2i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7665,7 +7685,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
// Emits: VR128:v2i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7673,7 +7693,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
// Emits: VR128:v2i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7681,7 +7701,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
// Emits: VR128:v2i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
}
@@ -7697,7 +7717,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
// Emits: VR64:v2f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7705,7 +7725,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
// Emits: VR64:v2f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7713,7 +7733,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
// Emits: VR64:v2f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7721,7 +7741,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
// Emits: VR64:v2f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7745,7 +7765,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
// Emits: VR128:v4f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7753,7 +7773,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
// Emits: VR128:v4f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7761,7 +7781,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
// Emits: VR128:v4f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7769,7 +7789,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
// Emits: VR128:v4f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7777,7 +7797,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
// Emits: VR128:v4f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
}
@@ -7794,7 +7814,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
// Emits: VR128:v2f64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7802,7 +7822,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
// Emits: VR128:v2f64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7810,7 +7830,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
// Emits: VR128:v2f64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7818,7 +7838,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
// Emits: VR128:v2f64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
@@ -7826,7 +7846,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
// Emits: VR128:v2f64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_78(N);
+ SDNode *Result = Emit_79(N);
return Result;
}
}
@@ -7835,7 +7855,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_81(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_82(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, N1, Chain);
@@ -7844,7 +7864,7 @@ SDNode *Select_ISD_BR(const SDValue &N) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::BasicBlock) {
- SDNode *Result = Emit_81(N, X86::JMP);
+ SDNode *Result = Emit_82(N, X86::JMP);
return Result;
}
@@ -7852,7 +7872,7 @@ SDNode *Select_ISD_BR(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_82(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_83(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -7902,7 +7922,7 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_82(N, X86::JMP32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_83(N, X86::JMP32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -7920,7 +7940,7 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_82(N, X86::JMP64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_83(N, X86::JMP64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -7931,7 +7951,7 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
// Emits: (JMP32r:isVoid GR32:i32:$dst)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_81(N, X86::JMP32r);
+ SDNode *Result = Emit_82(N, X86::JMP32r);
return Result;
}
@@ -7939,7 +7959,7 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
// Emits: (JMP64r:isVoid GR64:i64:$dst)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_81(N, X86::JMP64r);
+ SDNode *Result = Emit_82(N, X86::JMP64r);
return Result;
}
@@ -7957,13 +7977,13 @@ SDNode *Select_ISD_BSWAP_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_83(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_84(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0);
}
SDNode *Select_ISD_BUILD_VECTOR_v8i8(const SDValue &N) {
if ((Subtarget->hasMMX()) &&
Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::MMX_V_SET0, MVT::v8i8);
+ SDNode *Result = Emit_84(N, X86::MMX_V_SET0, MVT::v8i8);
return Result;
}
@@ -7974,7 +7994,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v8i8(const SDValue &N) {
SDNode *Select_ISD_BUILD_VECTOR_v16i8(const SDValue &N) {
if ((Subtarget->hasSSE1()) &&
Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v16i8);
+ SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v16i8);
return Result;
}
@@ -7985,7 +8005,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v16i8(const SDValue &N) {
SDNode *Select_ISD_BUILD_VECTOR_v4i16(const SDValue &N) {
if ((Subtarget->hasMMX()) &&
Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::MMX_V_SET0, MVT::v4i16);
+ SDNode *Result = Emit_84(N, X86::MMX_V_SET0, MVT::v4i16);
return Result;
}
@@ -7996,7 +8016,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v4i16(const SDValue &N) {
SDNode *Select_ISD_BUILD_VECTOR_v8i16(const SDValue &N) {
if ((Subtarget->hasSSE1()) &&
Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v8i16);
+ SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v8i16);
return Result;
}
@@ -8011,7 +8031,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v2i32(const SDValue &N) {
// Emits: (MMX_V_SET0:v2i32)
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::MMX_V_SET0, MVT::v2i32);
+ SDNode *Result = Emit_84(N, X86::MMX_V_SET0, MVT::v2i32);
return Result;
}
@@ -8019,7 +8039,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v2i32(const SDValue &N) {
// Emits: (MMX_V_SETALLONES:v2i32)
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_immAllOnesV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::MMX_V_SETALLONES, MVT::v2i32);
+ SDNode *Result = Emit_84(N, X86::MMX_V_SETALLONES, MVT::v2i32);
return Result;
}
}
@@ -8035,7 +8055,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
// Pattern complexity = 4 cost = 1 size = 3
if ((Subtarget->hasSSE1()) &&
Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v4i32);
+ SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v4i32);
return Result;
}
@@ -8044,7 +8064,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
// Pattern complexity = 4 cost = 1 size = 3
if ((Subtarget->hasSSE2()) &&
Predicate_immAllOnesV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::V_SETALLONES, MVT::v4i32);
+ SDNode *Result = Emit_84(N, X86::V_SETALLONES, MVT::v4i32);
return Result;
}
@@ -8055,7 +8075,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
SDNode *Select_ISD_BUILD_VECTOR_v1i64(const SDValue &N) {
if ((Subtarget->hasMMX()) &&
Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::MMX_V_SET0, MVT::v1i64);
+ SDNode *Result = Emit_84(N, X86::MMX_V_SET0, MVT::v1i64);
return Result;
}
@@ -8066,7 +8086,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v1i64(const SDValue &N) {
SDNode *Select_ISD_BUILD_VECTOR_v2i64(const SDValue &N) {
if ((Subtarget->hasSSE1()) &&
Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v2i64);
+ SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v2i64);
return Result;
}
@@ -8077,7 +8097,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v2i64(const SDValue &N) {
SDNode *Select_ISD_BUILD_VECTOR_v4f32(const SDValue &N) {
if ((Subtarget->hasSSE1()) &&
Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v4f32);
+ SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v4f32);
return Result;
}
@@ -8088,7 +8108,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v4f32(const SDValue &N) {
SDNode *Select_ISD_BUILD_VECTOR_v2f64(const SDValue &N) {
if ((Subtarget->hasSSE1()) &&
Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v2f64);
+ SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v2f64);
return Result;
}
@@ -8096,7 +8116,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_84(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_85(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -8131,7 +8151,7 @@ SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
if (N1.getOpcode() == ISD::TargetConstant) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_84(N, X86::ADJCALLSTACKUP32);
+ SDNode *Result = Emit_85(N, X86::ADJCALLSTACKUP32);
return Result;
}
}
@@ -8146,7 +8166,7 @@ SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
if (N1.getOpcode() == ISD::TargetConstant) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_84(N, X86::ADJCALLSTACKUP64);
+ SDNode *Result = Emit_85(N, X86::ADJCALLSTACKUP64);
return Result;
}
}
@@ -8156,7 +8176,7 @@ SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_85(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_86(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, N1, Chain);
@@ -8182,7 +8202,7 @@ SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_85(N, X86::ADJCALLSTACKDOWN32);
+ SDNode *Result = Emit_86(N, X86::ADJCALLSTACKDOWN32);
return Result;
}
}
@@ -8194,7 +8214,7 @@ SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_85(N, X86::ADJCALLSTACKDOWN64);
+ SDNode *Result = Emit_86(N, X86::ADJCALLSTACKDOWN64);
return Result;
}
}
@@ -8203,7 +8223,7 @@ SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_86(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_87(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i8);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
}
@@ -8213,39 +8233,44 @@ SDNode *Select_ISD_Constant_i8(const SDValue &N) {
// Emits: (MOV8r0:i8)
// Pattern complexity = 5 cost = 1 size = 3
if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_83(N, X86::MOV8r0, MVT::i8);
+ SDNode *Result = Emit_84(N, X86::MOV8r0, MVT::i8);
return Result;
}
// Pattern: (imm:i8):$src
// Emits: (MOV8ri:i8 (imm:i8):$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_86(N, X86::MOV8ri, MVT::i8);
+ SDNode *Result = Emit_87(N, X86::MOV8ri, MVT::i8);
return Result;
}
-DISABLE_INLINE SDNode *Emit_87(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_88(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i16);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
}
+DISABLE_INLINE SDNode *Emit_89(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, Tmp1);
+}
SDNode *Select_ISD_Constant_i16(const SDValue &N) {
// Pattern: 0:i16
- // Emits: (MOV16r0:i16)
- // Pattern complexity = 5 cost = 1 size = 3
+ // Emits: (EXTRACT_SUBREG:i16 (MOV32r0:i32), 3:i32)
+ // Pattern complexity = 6 cost = 2 size = 3
if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_83(N, X86::MOV16r0, MVT::i16);
+ SDNode *Result = Emit_89(N, X86::MOV32r0, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i16);
return Result;
}
// Pattern: (imm:i16):$src
// Emits: (MOV16ri:i16 (imm:i16):$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_87(N, X86::MOV16ri, MVT::i16);
+ SDNode *Result = Emit_88(N, X86::MOV16ri, MVT::i16);
return Result;
}
-DISABLE_INLINE SDNode *Emit_88(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_90(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
}
@@ -8255,22 +8280,22 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
// Emits: (MOV32r0:i32)
// Pattern complexity = 5 cost = 1 size = 3
if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_83(N, X86::MOV32r0, MVT::i32);
+ SDNode *Result = Emit_84(N, X86::MOV32r0, MVT::i32);
return Result;
}
// Pattern: (imm:i32):$src
// Emits: (MOV32ri:i32 (imm:i32):$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_88(N, X86::MOV32ri, MVT::i32);
+ SDNode *Result = Emit_90(N, X86::MOV32ri, MVT::i32);
return Result;
}
-DISABLE_INLINE SDNode *Emit_89(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_91(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i64);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
}
-DISABLE_INLINE SDNode *Emit_90(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_92(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
SDValue Tmp1(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
SDValue Tmp2 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
@@ -8282,7 +8307,7 @@ SDNode *Select_ISD_Constant_i64(const SDValue &N) {
// Emits: (SUBREG_TO_REG:i64 0:i64, (MOV32r0:i32), 4:i32)
// Pattern complexity = 6 cost = 2 size = 3
if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_90(N, X86::MOV32r0, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_92(N, X86::MOV32r0, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i64);
return Result;
}
@@ -8290,7 +8315,7 @@ SDNode *Select_ISD_Constant_i64(const SDValue &N) {
// Emits: (MOV64ri64i32:i64 (imm:i64):$src)
// Pattern complexity = 5 cost = 1 size = 3
if (Predicate_i64immZExt32(N.getNode())) {
- SDNode *Result = Emit_89(N, X86::MOV64ri64i32, MVT::i64);
+ SDNode *Result = Emit_91(N, X86::MOV64ri64i32, MVT::i64);
return Result;
}
@@ -8298,18 +8323,18 @@ SDNode *Select_ISD_Constant_i64(const SDValue &N) {
// Emits: (MOV64ri32:i64 (imm:i64):$src)
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_i64immSExt32(N.getNode())) {
- SDNode *Result = Emit_89(N, X86::MOV64ri32, MVT::i64);
+ SDNode *Result = Emit_91(N, X86::MOV64ri32, MVT::i64);
return Result;
}
// Pattern: (imm:i64):$src
// Emits: (MOV64ri:i64 (imm:i64):$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_89(N, X86::MOV64ri, MVT::i64);
+ SDNode *Result = Emit_91(N, X86::MOV64ri, MVT::i64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_91(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_93(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0);
}
@@ -8320,7 +8345,7 @@ SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
// Emits: (LD_Fp032:f32)
// Pattern complexity = 4 cost = 1 size = 0
if (Predicate_fpimm0(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::LD_Fp032, MVT::f32);
+ SDNode *Result = Emit_84(N, X86::LD_Fp032, MVT::f32);
return Result;
}
@@ -8328,7 +8353,7 @@ SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
// Emits: (LD_Fp132:f32)
// Pattern complexity = 4 cost = 1 size = 0
if (Predicate_fpimm1(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::LD_Fp132, MVT::f32);
+ SDNode *Result = Emit_84(N, X86::LD_Fp132, MVT::f32);
return Result;
}
}
@@ -8338,7 +8363,7 @@ SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
// Pattern complexity = 4 cost = 1 size = 3
if ((Subtarget->hasSSE1()) &&
Predicate_fp32imm0(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::FsFLD0SS, MVT::f32);
+ SDNode *Result = Emit_84(N, X86::FsFLD0SS, MVT::f32);
return Result;
}
if ((!Subtarget->hasSSE1())) {
@@ -8347,7 +8372,7 @@ SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
// Emits: (CHS_Fp32:f32 (LD_Fp032:f32))
// Pattern complexity = 4 cost = 2 size = 0
if (Predicate_fpimmneg0(N.getNode())) {
- SDNode *Result = Emit_91(N, X86::LD_Fp032, X86::CHS_Fp32, MVT::f32, MVT::f32);
+ SDNode *Result = Emit_93(N, X86::LD_Fp032, X86::CHS_Fp32, MVT::f32, MVT::f32);
return Result;
}
@@ -8355,7 +8380,7 @@ SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
// Emits: (CHS_Fp32:f32 (LD_Fp132:f32))
// Pattern complexity = 4 cost = 2 size = 0
if (Predicate_fpimmneg1(N.getNode())) {
- SDNode *Result = Emit_91(N, X86::LD_Fp132, X86::CHS_Fp32, MVT::f32, MVT::f32);
+ SDNode *Result = Emit_93(N, X86::LD_Fp132, X86::CHS_Fp32, MVT::f32, MVT::f32);
return Result;
}
}
@@ -8371,7 +8396,7 @@ SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
// Emits: (LD_Fp064:f64)
// Pattern complexity = 4 cost = 1 size = 0
if (Predicate_fpimm0(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::LD_Fp064, MVT::f64);
+ SDNode *Result = Emit_84(N, X86::LD_Fp064, MVT::f64);
return Result;
}
@@ -8379,7 +8404,7 @@ SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
// Emits: (LD_Fp164:f64)
// Pattern complexity = 4 cost = 1 size = 0
if (Predicate_fpimm1(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::LD_Fp164, MVT::f64);
+ SDNode *Result = Emit_84(N, X86::LD_Fp164, MVT::f64);
return Result;
}
}
@@ -8389,7 +8414,7 @@ SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
// Pattern complexity = 4 cost = 1 size = 3
if ((Subtarget->hasSSE2()) &&
Predicate_fpimm0(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::FsFLD0SD, MVT::f64);
+ SDNode *Result = Emit_84(N, X86::FsFLD0SD, MVT::f64);
return Result;
}
if ((!Subtarget->hasSSE2())) {
@@ -8398,7 +8423,7 @@ SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
// Emits: (CHS_Fp64:f64 (LD_Fp064:f64))
// Pattern complexity = 4 cost = 2 size = 0
if (Predicate_fpimmneg0(N.getNode())) {
- SDNode *Result = Emit_91(N, X86::LD_Fp064, X86::CHS_Fp64, MVT::f64, MVT::f64);
+ SDNode *Result = Emit_93(N, X86::LD_Fp064, X86::CHS_Fp64, MVT::f64, MVT::f64);
return Result;
}
@@ -8406,7 +8431,7 @@ SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
// Emits: (CHS_Fp64:f64 (LD_Fp164:f64))
// Pattern complexity = 4 cost = 2 size = 0
if (Predicate_fpimmneg1(N.getNode())) {
- SDNode *Result = Emit_91(N, X86::LD_Fp164, X86::CHS_Fp64, MVT::f64, MVT::f64);
+ SDNode *Result = Emit_93(N, X86::LD_Fp164, X86::CHS_Fp64, MVT::f64, MVT::f64);
return Result;
}
}
@@ -8421,7 +8446,7 @@ SDNode *Select_ISD_ConstantFP_f80(const SDValue &N) {
// Emits: (LD_Fp080:f80)
// Pattern complexity = 4 cost = 1 size = 0
if (Predicate_fpimm0(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::LD_Fp080, MVT::f80);
+ SDNode *Result = Emit_84(N, X86::LD_Fp080, MVT::f80);
return Result;
}
@@ -8429,7 +8454,7 @@ SDNode *Select_ISD_ConstantFP_f80(const SDValue &N) {
// Emits: (LD_Fp180:f80)
// Pattern complexity = 4 cost = 1 size = 0
if (Predicate_fpimm1(N.getNode())) {
- SDNode *Result = Emit_83(N, X86::LD_Fp180, MVT::f80);
+ SDNode *Result = Emit_84(N, X86::LD_Fp180, MVT::f80);
return Result;
}
@@ -8437,7 +8462,7 @@ SDNode *Select_ISD_ConstantFP_f80(const SDValue &N) {
// Emits: (CHS_Fp80:f80 (LD_Fp080:f80))
// Pattern complexity = 4 cost = 2 size = 0
if (Predicate_fpimmneg0(N.getNode())) {
- SDNode *Result = Emit_91(N, X86::LD_Fp080, X86::CHS_Fp80, MVT::f80, MVT::f80);
+ SDNode *Result = Emit_93(N, X86::LD_Fp080, X86::CHS_Fp80, MVT::f80, MVT::f80);
return Result;
}
@@ -8445,7 +8470,7 @@ SDNode *Select_ISD_ConstantFP_f80(const SDValue &N) {
// Emits: (CHS_Fp80:f80 (LD_Fp180:f80))
// Pattern complexity = 4 cost = 2 size = 0
if (Predicate_fpimmneg1(N.getNode())) {
- SDNode *Result = Emit_91(N, X86::LD_Fp180, X86::CHS_Fp80, MVT::f80, MVT::f80);
+ SDNode *Result = Emit_93(N, X86::LD_Fp180, X86::CHS_Fp80, MVT::f80, MVT::f80);
return Result;
}
@@ -8453,18 +8478,18 @@ SDNode *Select_ISD_ConstantFP_f80(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_92(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_94(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0);
}
-DISABLE_INLINE SDNode *Emit_93(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_95(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_94(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_96(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N1 = N.getOperand(1);
@@ -8484,7 +8509,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
if (N1.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32 &&
N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_94(N, X86::EXTRACTPSrr, MVT::i32);
+ SDNode *Result = Emit_96(N, X86::EXTRACTPSrr, MVT::i32);
return Result;
}
}
@@ -8501,7 +8526,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_92(N, X86::MOVPDI2DIrr, MVT::i32);
+ SDNode *Result = Emit_94(N, X86::MOVPDI2DIrr, MVT::i32);
return Result;
}
}
@@ -8515,7 +8540,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_93(N, X86::PEXTRDrr, MVT::i32);
+ SDNode *Result = Emit_95(N, X86::PEXTRDrr, MVT::i32);
return Result;
}
}
@@ -8537,7 +8562,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i64(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_92(N, X86::MOVPQIto64rr, MVT::i64);
+ SDNode *Result = Emit_94(N, X86::MOVPQIto64rr, MVT::i64);
return Result;
}
}
@@ -8551,7 +8576,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_93(N, X86::PEXTRQrr, MVT::i64);
+ SDNode *Result = Emit_95(N, X86::PEXTRQrr, MVT::i64);
return Result;
}
}
@@ -8569,7 +8594,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_92(N, X86::MOVPS2SSrr, MVT::f32);
+ SDNode *Result = Emit_94(N, X86::MOVPS2SSrr, MVT::f32);
return Result;
}
}
@@ -8588,7 +8613,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_92(N, X86::MOVPD2SDrr, MVT::f64);
+ SDNode *Result = Emit_94(N, X86::MOVPD2SDrr, MVT::f64);
return Result;
}
}
@@ -8623,7 +8648,7 @@ SDNode *Select_ISD_FABS_f80(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_95(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_97(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -8634,7 +8659,7 @@ DISABLE_INLINE SDNode *Emit_95(const SDValue &N, unsigned Opc0, MVT::SimpleValue
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_96(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_98(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -8770,7 +8795,7 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
// Emits: (ADD_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -8778,7 +8803,7 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
// Emits: (ADD_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -8801,7 +8826,7 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
// Emits: (ADD_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -8809,7 +8834,7 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
// Emits: (ADD_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -8998,7 +9023,7 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Emits: (ADD_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -9006,7 +9031,7 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Emits: (ADD_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -9029,7 +9054,7 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Emits: (ADD_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -9037,7 +9062,7 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Emits: (ADD_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -9170,7 +9195,7 @@ SDNode *Select_ISD_FADD_f80(const SDValue &N) {
// Emits: (ADD_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -9178,7 +9203,7 @@ SDNode *Select_ISD_FADD_f80(const SDValue &N) {
// Emits: (ADD_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -9201,7 +9226,7 @@ SDNode *Select_ISD_FADD_f80(const SDValue &N) {
// Emits: (ADD_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -9209,7 +9234,7 @@ SDNode *Select_ISD_FADD_f80(const SDValue &N) {
// Emits: (ADD_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -9465,7 +9490,7 @@ SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
// Emits: (DIV_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::DIV_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIV_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -9473,7 +9498,7 @@ SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
// Emits: (DIV_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::DIV_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIV_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -9481,7 +9506,7 @@ SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
// Emits: (DIVR_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::DIVR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIVR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -9489,7 +9514,7 @@ SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
// Emits: (DIVR_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::DIVR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIVR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -9644,7 +9669,7 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
// Emits: (DIV_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::DIV_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIV_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -9652,7 +9677,7 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
// Emits: (DIV_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::DIV_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIV_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -9660,7 +9685,7 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
// Emits: (DIVR_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::DIVR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIVR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -9668,7 +9693,7 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
// Emits: (DIVR_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::DIVR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIVR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -9789,7 +9814,7 @@ SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
// Emits: (DIV_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::DIV_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIV_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -9797,7 +9822,7 @@ SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
// Emits: (DIV_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::DIV_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIV_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -9805,7 +9830,7 @@ SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
// Emits: (DIVR_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::DIVR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIVR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -9813,7 +9838,7 @@ SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
// Emits: (DIVR_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::DIVR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::DIVR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -10036,7 +10061,7 @@ SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
// Emits: (MUL_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -10044,7 +10069,7 @@ SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
// Emits: (MUL_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -10067,7 +10092,7 @@ SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
// Emits: (MUL_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -10075,7 +10100,7 @@ SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
// Emits: (MUL_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10264,7 +10289,7 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
// Emits: (MUL_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -10272,7 +10297,7 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
// Emits: (MUL_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -10295,7 +10320,7 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
// Emits: (MUL_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -10303,7 +10328,7 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
// Emits: (MUL_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10436,7 +10461,7 @@ SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
// Emits: (MUL_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -10444,7 +10469,7 @@ SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
// Emits: (MUL_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -10467,7 +10492,7 @@ SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
// Emits: (MUL_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -10475,7 +10500,7 @@ SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
// Emits: (MUL_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_98(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10670,7 +10695,7 @@ SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_77(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10737,7 +10762,7 @@ SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
// Emits: (CVTSD2SSrm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ (Subtarget->hasSSE2()) && (OptForSize)) {
SDValue N0 = N.getOperand(0);
if (N0.getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -10753,7 +10778,7 @@ SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_77(N, X86::CVTSD2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::CVTSD2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10829,7 +10854,7 @@ SDNode *Select_ISD_FP_TO_SINT_i32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_77(N, X86::CVTTSS2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::CVTTSS2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10855,7 +10880,7 @@ SDNode *Select_ISD_FP_TO_SINT_i32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_77(N, X86::CVTTSD2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::CVTTSD2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10911,7 +10936,7 @@ SDNode *Select_ISD_FP_TO_SINT_i64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_77(N, X86::CVTTSD2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::CVTTSD2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10937,7 +10962,7 @@ SDNode *Select_ISD_FP_TO_SINT_i64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_77(N, X86::CVTTSS2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::CVTTSS2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -11028,7 +11053,7 @@ SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
// Emits: (SQRTSSm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
+ (Subtarget->hasSSE1()) && (OptForSize)) {
SDValue N0 = N.getOperand(0);
if (N0.getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -11042,7 +11067,7 @@ SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::SQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::SQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -11089,7 +11114,7 @@ SDNode *Select_ISD_FSQRT_f64(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::SQRTSDm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::SQRTSDm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -11142,7 +11167,7 @@ SDNode *Select_ISD_FSQRT_v4f32(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::SQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::SQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -11182,7 +11207,7 @@ SDNode *Select_ISD_FSQRT_v2f64(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::SQRTPDm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::SQRTPDm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -11284,7 +11309,7 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
// Emits: (SUB_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::SUB_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUB_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -11292,7 +11317,7 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
// Emits: (SUB_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::SUB_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUB_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -11300,7 +11325,7 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
// Emits: (SUBR_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::SUBR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUBR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -11308,7 +11333,7 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
// Emits: (SUBR_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::SUBR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUBR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -11463,7 +11488,7 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Emits: (SUB_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::SUB_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUB_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -11471,7 +11496,7 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Emits: (SUB_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::SUB_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUB_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -11479,7 +11504,7 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Emits: (SUBR_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::SUBR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUBR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -11487,7 +11512,7 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Emits: (SUBR_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::SUBR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUBR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -11608,7 +11633,7 @@ SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
// Emits: (SUB_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::SUB_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUB_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -11616,7 +11641,7 @@ SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
// Emits: (SUB_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::SUB_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUB_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -11624,7 +11649,7 @@ SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
// Emits: (SUBR_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_95(N, X86::SUBR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUBR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -11632,7 +11657,7 @@ SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
// Emits: (SUBR_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_95(N, X86::SUBR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_97(N, X86::SUBR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -11778,14 +11803,14 @@ SDNode *Select_ISD_FrameIndex_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_97(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_99(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_98(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_100(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -11824,7 +11849,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(const SDValue &N) {
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_98(N, X86::PINSRDrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_100(N, X86::PINSRDrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -11840,7 +11865,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_97(N, X86::PINSRDrr, MVT::v4i32);
+ SDNode *Result = Emit_99(N, X86::PINSRDrr, MVT::v4i32);
return Result;
}
}
@@ -11874,7 +11899,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i64(const SDValue &N) {
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_98(N, X86::PINSRQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_100(N, X86::PINSRQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -11890,7 +11915,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_97(N, X86::PINSRQrr, MVT::v2i64);
+ SDNode *Result = Emit_99(N, X86::PINSRQrr, MVT::v2i64);
return Result;
}
}
@@ -11899,7 +11924,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_99(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_101(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -11907,19 +11932,19 @@ DISABLE_INLINE SDNode *Emit_99(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N3, Chain };
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
}
-DISABLE_INLINE SDNode *Emit_100(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_102(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
}
-DISABLE_INLINE SDNode *Emit_101(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain };
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
}
-DISABLE_INLINE SDNode *Emit_102(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -11932,7 +11957,7 @@ DISABLE_INLINE SDNode *Emit_102(const SDValue &N, unsigned Opc0) {
SDValue Ops0[] = { N2, N3, Chain, InFlag };
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_105(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -11945,7 +11970,7 @@ DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0) {
SDValue Ops0[] = { N2, N3, Chain, InFlag };
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_106(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -11963,7 +11988,7 @@ DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0) {
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain, InFlag);
}
-DISABLE_INLINE SDNode *Emit_105(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_107(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -11996,7 +12021,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_99(N, X86::MOVUPSmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_101(N, X86::MOVUPSmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12012,7 +12037,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_99(N, X86::MOVNTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_101(N, X86::MOVNTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12028,7 +12053,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::LDMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_103(N, X86::LDMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12044,7 +12069,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::STMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_103(N, X86::STMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12068,7 +12093,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_99(N, X86::MOVUPDmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_101(N, X86::MOVUPDmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12084,7 +12109,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_99(N, X86::MOVDQUmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_101(N, X86::MOVDQUmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12100,7 +12125,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_99(N, X86::MOVNTPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_101(N, X86::MOVNTPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12116,7 +12141,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_99(N, X86::MOVNTDQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_101(N, X86::MOVNTDQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12132,7 +12157,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_99(N, X86::MOVNTImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_101(N, X86::MOVNTImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12148,7 +12173,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::CLFLUSH, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_103(N, X86::CLFLUSH, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12164,7 +12189,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_99(N, X86::MOVLQ128mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_101(N, X86::MOVLQ128mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12188,7 +12213,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_99(N, X86::MMX_MOVNTQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_101(N, X86::MMX_MOVNTQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -12205,7 +12230,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(714)) {
- SDNode *Result = Emit_100(N, X86::SFENCE);
+ SDNode *Result = Emit_102(N, X86::SFENCE);
return Result;
}
}
@@ -12225,7 +12250,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
// Emits: (MASKMOVDQU:isVoid VR128:v16i8:$src, VR128:v16i8:$mask)
// Pattern complexity = 8 cost = 1 size = 3
if (N4.getValueType() == MVT::i32) {
- SDNode *Result = Emit_102(N, X86::MASKMOVDQU);
+ SDNode *Result = Emit_104(N, X86::MASKMOVDQU);
return Result;
}
@@ -12233,7 +12258,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
// Emits: (MASKMOVDQU64:isVoid VR128:v16i8:$src, VR128:v16i8:$mask)
// Pattern complexity = 8 cost = 1 size = 3
if (N4.getValueType() == MVT::i64) {
- SDNode *Result = Emit_103(N, X86::MASKMOVDQU64);
+ SDNode *Result = Emit_105(N, X86::MASKMOVDQU64);
return Result;
}
}
@@ -12242,7 +12267,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
// Emits: (LFENCE:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(529)) {
- SDNode *Result = Emit_100(N, X86::LFENCE);
+ SDNode *Result = Emit_102(N, X86::LFENCE);
return Result;
}
@@ -12250,7 +12275,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
// Emits: (MFENCE:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(535)) {
- SDNode *Result = Emit_100(N, X86::MFENCE);
+ SDNode *Result = Emit_102(N, X86::MFENCE);
return Result;
}
}
@@ -12270,7 +12295,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue N3 = N.getOperand(3);
SDValue N4 = N.getOperand(4);
if (N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_104(N, X86::MONITOR);
+ SDNode *Result = Emit_106(N, X86::MONITOR);
return Result;
}
}
@@ -12279,7 +12304,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
// Emits: (MWAIT:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(612)) {
- SDNode *Result = Emit_105(N, X86::MWAIT);
+ SDNode *Result = Emit_107(N, X86::MWAIT);
return Result;
}
}
@@ -12295,7 +12320,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
// Emits: (MMX_EMMS:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(453)) {
- SDNode *Result = Emit_100(N, X86::MMX_EMMS);
+ SDNode *Result = Emit_102(N, X86::MMX_EMMS);
return Result;
}
@@ -12303,7 +12328,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
// Emits: (MMX_FEMMS:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(454)) {
- SDNode *Result = Emit_100(N, X86::MMX_FEMMS);
+ SDNode *Result = Emit_102(N, X86::MMX_FEMMS);
return Result;
}
@@ -12315,7 +12340,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue N3 = N.getOperand(3);
SDValue N4 = N.getOperand(4);
if (N4.getValueType() == MVT::i32) {
- SDNode *Result = Emit_102(N, X86::MMX_MASKMOVQ);
+ SDNode *Result = Emit_104(N, X86::MMX_MASKMOVQ);
return Result;
}
}
@@ -12336,7 +12361,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
SDValue N3 = N.getOperand(3);
SDValue N4 = N.getOperand(4);
if (N4.getValueType() == MVT::i64) {
- SDNode *Result = Emit_103(N, X86::MMX_MASKMOVQ64);
+ SDNode *Result = Emit_105(N, X86::MMX_MASKMOVQ64);
return Result;
}
}
@@ -12347,12 +12372,12 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_106(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1);
}
-DISABLE_INLINE SDNode *Emit_107(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_109(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -12365,7 +12390,7 @@ DISABLE_INLINE SDNode *Emit_107(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+DISABLE_INLINE SDNode *Emit_110(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -12379,13 +12404,13 @@ DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_109(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_111(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2);
}
-DISABLE_INLINE SDNode *Emit_110(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_112(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -12393,7 +12418,7 @@ DISABLE_INLINE SDNode *Emit_110(const SDValue &N, unsigned Opc0) {
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::i32, N1, N2, Tmp4);
}
-DISABLE_INLINE SDNode *Emit_111(const SDValue &N, unsigned Opc0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+DISABLE_INLINE SDNode *Emit_113(const SDValue &N, unsigned Opc0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -12409,7 +12434,7 @@ DISABLE_INLINE SDNode *Emit_111(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 2));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_112(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_114(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -12428,7 +12453,7 @@ DISABLE_INLINE SDNode *Emit_112(const SDValue &N, unsigned Opc0) {
SDValue Ops0[] = { N1, N3, Tmp4, InFlag };
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::i32, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_113(const SDValue &N, unsigned Opc0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
+DISABLE_INLINE SDNode *Emit_115(const SDValue &N, unsigned Opc0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -12482,7 +12507,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRIrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_113(N, X86::PCMPISTRIrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12511,7 +12536,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRIArm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_113(N, X86::PCMPISTRIArm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12540,7 +12565,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRICrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_113(N, X86::PCMPISTRICrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12569,7 +12594,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRIOrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_113(N, X86::PCMPISTRIOrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12598,7 +12623,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRISrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_113(N, X86::PCMPISTRISrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12627,7 +12652,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRIZrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_113(N, X86::PCMPISTRIZrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12658,7 +12683,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRIrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDNode *Result = Emit_115(N, X86::PCMPESTRIrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12689,7 +12714,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRIArm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDNode *Result = Emit_115(N, X86::PCMPESTRIArm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12720,7 +12745,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRICrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDNode *Result = Emit_115(N, X86::PCMPESTRICrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12751,7 +12776,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRIOrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDNode *Result = Emit_115(N, X86::PCMPESTRIOrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12782,7 +12807,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRISrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDNode *Result = Emit_115(N, X86::PCMPESTRISrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12813,7 +12838,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRIZrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDNode *Result = Emit_115(N, X86::PCMPESTRIZrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12846,7 +12871,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -12871,7 +12896,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -12903,7 +12928,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -12928,7 +12953,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -12961,7 +12986,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::CRC32m8, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::CRC32m8, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12987,7 +13012,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::CRC32m16, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::CRC32m16, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -13013,7 +13038,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::CRC32m32, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::CRC32m32, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -13036,7 +13061,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_110(N, X86::PCMPISTRIrr);
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIrr);
return Result;
}
}
@@ -13049,7 +13074,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_110(N, X86::PCMPISTRIArr);
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIArr);
return Result;
}
}
@@ -13062,7 +13087,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_110(N, X86::PCMPISTRICrr);
+ SDNode *Result = Emit_112(N, X86::PCMPISTRICrr);
return Result;
}
}
@@ -13075,7 +13100,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_110(N, X86::PCMPISTRIOrr);
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIOrr);
return Result;
}
}
@@ -13088,7 +13113,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_110(N, X86::PCMPISTRISrr);
+ SDNode *Result = Emit_112(N, X86::PCMPISTRISrr);
return Result;
}
}
@@ -13101,7 +13126,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_110(N, X86::PCMPISTRIZrr);
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIZrr);
return Result;
}
}
@@ -13116,7 +13141,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPESTRIrr);
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIrr);
return Result;
}
}
@@ -13131,7 +13156,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPESTRIArr);
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIArr);
return Result;
}
}
@@ -13146,7 +13171,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPESTRICrr);
+ SDNode *Result = Emit_114(N, X86::PCMPESTRICrr);
return Result;
}
}
@@ -13161,7 +13186,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPESTRIOrr);
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIOrr);
return Result;
}
}
@@ -13176,7 +13201,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPESTRISrr);
+ SDNode *Result = Emit_114(N, X86::PCMPESTRISrr);
return Result;
}
}
@@ -13191,7 +13216,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPESTRIZrr);
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIZrr);
return Result;
}
}
@@ -13207,7 +13232,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
// Emits: (Int_CVTSS2SIrr:i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(694)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTSS2SIrr, MVT::i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTSS2SIrr, MVT::i32);
return Result;
}
@@ -13215,7 +13240,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
// Emits: (Int_CVTTSS2SIrr:i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(698)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTTSS2SIrr, MVT::i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SIrr, MVT::i32);
return Result;
}
@@ -13223,7 +13248,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
// Emits: (MOVMSKPSrr:i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(707)) {
- SDNode *Result = Emit_106(N, X86::MOVMSKPSrr, MVT::i32);
+ SDNode *Result = Emit_108(N, X86::MOVMSKPSrr, MVT::i32);
return Result;
}
}
@@ -13238,7 +13263,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
// Emits: (MOVMSKPDrr:i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(538)) {
- SDNode *Result = Emit_106(N, X86::MOVMSKPDrr, MVT::i32);
+ SDNode *Result = Emit_108(N, X86::MOVMSKPDrr, MVT::i32);
return Result;
}
@@ -13246,7 +13271,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
// Emits: (Int_CVTSD2SIrr:i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(518)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTSD2SIrr, MVT::i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTSD2SIrr, MVT::i32);
return Result;
}
@@ -13254,7 +13279,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
// Emits: (Int_CVTTSD2SIrr:i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(526)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTTSD2SIrr, MVT::i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SIrr, MVT::i32);
return Result;
}
@@ -13262,7 +13287,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
// Emits: (PMOVMSKBrr:i32 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(563)) {
- SDNode *Result = Emit_106(N, X86::PMOVMSKBrr, MVT::i32);
+ SDNode *Result = Emit_108(N, X86::PMOVMSKBrr, MVT::i32);
return Result;
}
}
@@ -13277,7 +13302,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
// Emits: (CRC32r8:i32 GR32:i32:$src1, GR8:i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(663)) {
- SDNode *Result = Emit_109(N, X86::CRC32r8, MVT::i32);
+ SDNode *Result = Emit_111(N, X86::CRC32r8, MVT::i32);
return Result;
}
@@ -13285,7 +13310,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
// Emits: (CRC32r16:i32 GR32:i32:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(660)) {
- SDNode *Result = Emit_109(N, X86::CRC32r16, MVT::i32);
+ SDNode *Result = Emit_111(N, X86::CRC32r16, MVT::i32);
return Result;
}
@@ -13293,7 +13318,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
// Emits: (CRC32r32:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(661)) {
- SDNode *Result = Emit_109(N, X86::CRC32r32, MVT::i32);
+ SDNode *Result = Emit_111(N, X86::CRC32r32, MVT::i32);
return Result;
}
}
@@ -13308,7 +13333,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(477)) {
- SDNode *Result = Emit_106(N, X86::MMX_PMOVMSKBrr, MVT::i32);
+ SDNode *Result = Emit_108(N, X86::MMX_PMOVMSKBrr, MVT::i32);
return Result;
}
}
@@ -13344,7 +13369,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -13369,7 +13394,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -13401,7 +13426,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -13426,7 +13451,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -13459,7 +13484,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::CRC64m64, MVT::i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::CRC64m64, MVT::i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -13478,7 +13503,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
// Emits: (Int_CVTSD2SI64rr:i64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(519)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTSD2SI64rr, MVT::i64);
+ SDNode *Result = Emit_108(N, X86::Int_CVTSD2SI64rr, MVT::i64);
return Result;
}
@@ -13486,7 +13511,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
// Emits: (Int_CVTTSD2SI64rr:i64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(527)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTTSD2SI64rr, MVT::i64);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SI64rr, MVT::i64);
return Result;
}
}
@@ -13501,7 +13526,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
// Emits: (Int_CVTSS2SI64rr:i64 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(695)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTSS2SI64rr, MVT::i64);
+ SDNode *Result = Emit_108(N, X86::Int_CVTSS2SI64rr, MVT::i64);
return Result;
}
@@ -13509,7 +13534,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
// Emits: (Int_CVTTSS2SI64rr:i64 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(699)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTTSS2SI64rr, MVT::i64);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SI64rr, MVT::i64);
return Result;
}
}
@@ -13524,7 +13549,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(662)) {
- SDNode *Result = Emit_109(N, X86::CRC64r64, MVT::i64);
+ SDNode *Result = Emit_111(N, X86::CRC64r64, MVT::i64);
return Result;
}
}
@@ -13534,7 +13559,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_114(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_116(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -13548,7 +13573,7 @@ DISABLE_INLINE SDNode *Emit_114(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_115(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
+DISABLE_INLINE SDNode *Emit_117(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -13563,7 +13588,7 @@ DISABLE_INLINE SDNode *Emit_115(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_116(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_118(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -13609,7 +13634,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_114(N, X86::PABSBrm64, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_116(N, X86::PABSBrm64, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -13641,7 +13666,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_115(N, X86::PSHUFBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSHUFBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13673,7 +13698,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_115(N, X86::PSIGNBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSIGNBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13711,7 +13736,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13742,7 +13767,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13773,7 +13798,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSUBSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSUBSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13804,7 +13829,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSUBUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSUBUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13835,7 +13860,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13866,7 +13891,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13897,7 +13922,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13928,7 +13953,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13959,7 +13984,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PCMPGTBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PCMPGTBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13990,7 +14015,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PACKSSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PACKSSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14021,7 +14046,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PACKUSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PACKUSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14052,7 +14077,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14084,7 +14109,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14116,7 +14141,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14148,7 +14173,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14180,7 +14205,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14201,7 +14226,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (PABSBrr64:v8i8 VR64:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(726)) {
- SDNode *Result = Emit_106(N, X86::PABSBrr64, MVT::v8i8);
+ SDNode *Result = Emit_108(N, X86::PABSBrr64, MVT::v8i8);
return Result;
}
@@ -14209,7 +14234,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (PSHUFBrr64:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(750)) {
- SDNode *Result = Emit_109(N, X86::PSHUFBrr64, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::PSHUFBrr64, MVT::v8i8);
return Result;
}
@@ -14217,7 +14242,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (PSIGNBrr64:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(752)) {
- SDNode *Result = Emit_109(N, X86::PSIGNBrr64, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::PSIGNBrr64, MVT::v8i8);
return Result;
}
}
@@ -14232,7 +14257,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (MMX_PADDSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(460)) {
- SDNode *Result = Emit_109(N, X86::MMX_PADDSBrr, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::MMX_PADDSBrr, MVT::v8i8);
return Result;
}
@@ -14240,7 +14265,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (MMX_PADDUSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(462)) {
- SDNode *Result = Emit_109(N, X86::MMX_PADDUSBrr, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::MMX_PADDUSBrr, MVT::v8i8);
return Result;
}
@@ -14248,7 +14273,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (MMX_PSUBSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(498)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSUBSBrr, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::MMX_PSUBSBrr, MVT::v8i8);
return Result;
}
@@ -14256,7 +14281,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (MMX_PSUBUSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(500)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSUBUSBrr, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::MMX_PSUBUSBrr, MVT::v8i8);
return Result;
}
@@ -14264,7 +14289,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (MMX_PAVGBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(464)) {
- SDNode *Result = Emit_109(N, X86::MMX_PAVGBrr, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::MMX_PAVGBrr, MVT::v8i8);
return Result;
}
@@ -14272,7 +14297,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (MMX_PMINUBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(476)) {
- SDNode *Result = Emit_109(N, X86::MMX_PMINUBrr, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::MMX_PMINUBrr, MVT::v8i8);
return Result;
}
@@ -14280,7 +14305,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (MMX_PMAXUBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(474)) {
- SDNode *Result = Emit_109(N, X86::MMX_PMAXUBrr, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::MMX_PMAXUBrr, MVT::v8i8);
return Result;
}
@@ -14288,7 +14313,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (MMX_PCMPEQBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(466)) {
- SDNode *Result = Emit_109(N, X86::MMX_PCMPEQBrr, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::MMX_PCMPEQBrr, MVT::v8i8);
return Result;
}
@@ -14296,7 +14321,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (MMX_PCMPGTBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(469)) {
- SDNode *Result = Emit_109(N, X86::MMX_PCMPGTBrr, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::MMX_PCMPGTBrr, MVT::v8i8);
return Result;
}
@@ -14304,7 +14329,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (MMX_PACKSSWBrr:v8i8 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(458)) {
- SDNode *Result = Emit_109(N, X86::MMX_PACKSSWBrr, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::MMX_PACKSSWBrr, MVT::v8i8);
return Result;
}
@@ -14312,7 +14337,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (MMX_PACKUSWBrr:v8i8 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(459)) {
- SDNode *Result = Emit_109(N, X86::MMX_PACKUSWBrr, MVT::v8i8);
+ SDNode *Result = Emit_111(N, X86::MMX_PACKUSWBrr, MVT::v8i8);
return Result;
}
}
@@ -14322,7 +14347,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_117(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_119(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -14330,7 +14355,7 @@ DISABLE_INLINE SDNode *Emit_117(const SDValue &N, unsigned Opc0, MVT::SimpleValu
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, Tmp4);
}
-DISABLE_INLINE SDNode *Emit_118(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
+DISABLE_INLINE SDNode *Emit_120(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -14347,7 +14372,7 @@ DISABLE_INLINE SDNode *Emit_118(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_119(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_121(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -14359,7 +14384,7 @@ DISABLE_INLINE SDNode *Emit_119(const SDValue &N, unsigned Opc0, MVT::SimpleValu
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, InFlag);
}
-DISABLE_INLINE SDNode *Emit_120(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
+DISABLE_INLINE SDNode *Emit_122(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -14379,7 +14404,7 @@ DISABLE_INLINE SDNode *Emit_120(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_121(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_123(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -14387,7 +14412,7 @@ DISABLE_INLINE SDNode *Emit_121(const SDValue &N, unsigned Opc0, MVT::SimpleValu
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, Tmp4);
}
-DISABLE_INLINE SDNode *Emit_122(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+DISABLE_INLINE SDNode *Emit_124(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -14403,7 +14428,7 @@ DISABLE_INLINE SDNode *Emit_122(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_123(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_125(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -14422,7 +14447,7 @@ DISABLE_INLINE SDNode *Emit_123(const SDValue &N, unsigned Opc0, MVT::SimpleValu
SDValue Ops0[] = { N1, N3, Tmp4, InFlag };
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_124(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
+DISABLE_INLINE SDNode *Emit_126(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -14447,7 +14472,7 @@ DISABLE_INLINE SDNode *Emit_124(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N3.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_125(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_127(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -14499,7 +14524,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_120(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14532,7 +14557,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_125(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_127(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14572,7 +14597,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PADDSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PADDSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14604,7 +14629,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14636,7 +14661,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSUBSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSUBSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14668,7 +14693,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSUBUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSUBUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14700,7 +14725,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PAVGBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PAVGBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14732,7 +14757,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PMINUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMINUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14764,7 +14789,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14796,7 +14821,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14828,7 +14853,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PCMPGTBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PCMPGTBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14860,7 +14885,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PACKSSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PACKSSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14892,7 +14917,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PACKUSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PACKUSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14930,7 +14955,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_114(N, X86::PABSBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_116(N, X86::PABSBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14962,7 +14987,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14994,7 +15019,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PSIGNBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSIGNBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15033,7 +15058,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PMINSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMINSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15065,7 +15090,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15098,7 +15123,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
SDValue N3 = N.getOperand(3);
if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_120(N, X86::PBLENDVBrm0, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_122(N, X86::PBLENDVBrm0, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15138,7 +15163,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PADDSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15171,7 +15196,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15204,7 +15229,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PAVGBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PAVGBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15237,7 +15262,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMINUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMINUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15270,7 +15295,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15310,7 +15335,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMINSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15343,7 +15368,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15380,7 +15405,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_122(N, X86::PCMPISTRM128MEM, MVT::v16i8, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_124(N, X86::PCMPISTRM128MEM, MVT::v16i8, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -15411,7 +15436,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_124(N, X86::PCMPESTRM128MEM, MVT::v16i8, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDNode *Result = Emit_126(N, X86::PCMPESTRM128MEM, MVT::v16i8, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -15435,7 +15460,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_117(N, X86::MPSADBWrri, MVT::v16i8);
+ SDNode *Result = Emit_119(N, X86::MPSADBWrri, MVT::v16i8);
return Result;
}
}
@@ -15455,7 +15480,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_121(N, X86::PCMPISTRM128REG, MVT::v16i8);
+ SDNode *Result = Emit_123(N, X86::PCMPISTRM128REG, MVT::v16i8);
return Result;
}
}
@@ -15470,7 +15495,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue N4 = N.getOperand(4);
SDValue N5 = N.getOperand(5);
if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::PCMPESTRM128REG, MVT::v16i8);
+ SDNode *Result = Emit_125(N, X86::PCMPESTRM128REG, MVT::v16i8);
return Result;
}
}
@@ -15486,7 +15511,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PADDSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(546)) {
- SDNode *Result = Emit_109(N, X86::PADDSBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PADDSBrr, MVT::v16i8);
return Result;
}
@@ -15494,7 +15519,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PADDUSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(548)) {
- SDNode *Result = Emit_109(N, X86::PADDUSBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PADDUSBrr, MVT::v16i8);
return Result;
}
@@ -15502,7 +15527,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PSUBSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(588)) {
- SDNode *Result = Emit_109(N, X86::PSUBSBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PSUBSBrr, MVT::v16i8);
return Result;
}
@@ -15510,7 +15535,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PSUBUSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(590)) {
- SDNode *Result = Emit_109(N, X86::PSUBUSBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PSUBUSBrr, MVT::v16i8);
return Result;
}
@@ -15518,7 +15543,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PAVGBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(550)) {
- SDNode *Result = Emit_109(N, X86::PAVGBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PAVGBrr, MVT::v16i8);
return Result;
}
@@ -15526,7 +15551,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PMINUBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(562)) {
- SDNode *Result = Emit_109(N, X86::PMINUBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PMINUBrr, MVT::v16i8);
return Result;
}
@@ -15534,7 +15559,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PMAXUBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(560)) {
- SDNode *Result = Emit_109(N, X86::PMAXUBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PMAXUBrr, MVT::v16i8);
return Result;
}
@@ -15542,7 +15567,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PCMPEQBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(552)) {
- SDNode *Result = Emit_109(N, X86::PCMPEQBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PCMPEQBrr, MVT::v16i8);
return Result;
}
@@ -15550,7 +15575,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PCMPGTBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(555)) {
- SDNode *Result = Emit_109(N, X86::PCMPGTBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PCMPGTBrr, MVT::v16i8);
return Result;
}
@@ -15558,7 +15583,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PACKSSWBrr:v16i8 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(544)) {
- SDNode *Result = Emit_109(N, X86::PACKSSWBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PACKSSWBrr, MVT::v16i8);
return Result;
}
@@ -15566,7 +15591,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PACKUSWBrr:v16i8 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(545)) {
- SDNode *Result = Emit_109(N, X86::PACKUSWBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PACKUSWBrr, MVT::v16i8);
return Result;
}
}
@@ -15581,7 +15606,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PABSBrr128:v16i8 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(727)) {
- SDNode *Result = Emit_106(N, X86::PABSBrr128, MVT::v16i8);
+ SDNode *Result = Emit_108(N, X86::PABSBrr128, MVT::v16i8);
return Result;
}
@@ -15589,7 +15614,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PSHUFBrr128:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(751)) {
- SDNode *Result = Emit_109(N, X86::PSHUFBrr128, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PSHUFBrr128, MVT::v16i8);
return Result;
}
@@ -15597,7 +15622,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PSIGNBrr128:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(753)) {
- SDNode *Result = Emit_109(N, X86::PSIGNBrr128, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PSIGNBrr128, MVT::v16i8);
return Result;
}
}
@@ -15612,7 +15637,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PMINSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(635)) {
- SDNode *Result = Emit_109(N, X86::PMINSBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PMINSBrr, MVT::v16i8);
return Result;
}
@@ -15620,7 +15645,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PMAXSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(631)) {
- SDNode *Result = Emit_109(N, X86::PMAXSBrr, MVT::v16i8);
+ SDNode *Result = Emit_111(N, X86::PMAXSBrr, MVT::v16i8);
return Result;
}
@@ -15628,7 +15653,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (PBLENDVBrr0:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(624)) {
- SDNode *Result = Emit_119(N, X86::PBLENDVBrr0, MVT::v16i8);
+ SDNode *Result = Emit_121(N, X86::PBLENDVBrr0, MVT::v16i8);
return Result;
}
}
@@ -15638,7 +15663,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_126(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_128(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -15676,7 +15701,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_114(N, X86::PABSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_116(N, X86::PABSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15708,7 +15733,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_115(N, X86::PHADDWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHADDWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15740,7 +15765,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_115(N, X86::PHADDSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHADDSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15772,7 +15797,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_115(N, X86::PHSUBWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHSUBWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15804,7 +15829,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_115(N, X86::PHSUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHSUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15836,7 +15861,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_115(N, X86::PMADDUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMADDUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15868,7 +15893,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_115(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15900,7 +15925,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_115(N, X86::PSIGNWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSIGNWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15938,7 +15963,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15969,7 +15994,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16000,7 +16025,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSUBSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSUBSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16031,7 +16056,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSUBUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSUBUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16062,7 +16087,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16093,7 +16118,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16124,7 +16149,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16155,7 +16180,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16186,7 +16211,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16217,7 +16242,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16248,7 +16273,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSRLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSRLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16279,7 +16304,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSLLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSLLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16310,7 +16335,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSRAWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSRAWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16341,7 +16366,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16372,7 +16397,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PCMPGTWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PCMPGTWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16403,7 +16428,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PACKSSDWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PACKSSDWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16442,7 +16467,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16481,7 +16506,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16513,7 +16538,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16545,7 +16570,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16577,7 +16602,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16609,7 +16634,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16641,7 +16666,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16673,7 +16698,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16705,7 +16730,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16729,7 +16754,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::MMX_PSRLWri, MVT::v4i16);
+ SDNode *Result = Emit_128(N, X86::MMX_PSRLWri, MVT::v4i16);
return Result;
}
}
@@ -16741,7 +16766,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::MMX_PSLLWri, MVT::v4i16);
+ SDNode *Result = Emit_128(N, X86::MMX_PSLLWri, MVT::v4i16);
return Result;
}
}
@@ -16753,7 +16778,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::MMX_PSRAWri, MVT::v4i16);
+ SDNode *Result = Emit_128(N, X86::MMX_PSRAWri, MVT::v4i16);
return Result;
}
}
@@ -16769,7 +16794,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (PABSWrr64:v4i16 VR64:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(730)) {
- SDNode *Result = Emit_106(N, X86::PABSWrr64, MVT::v4i16);
+ SDNode *Result = Emit_108(N, X86::PABSWrr64, MVT::v4i16);
return Result;
}
@@ -16777,7 +16802,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (PHADDWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(738)) {
- SDNode *Result = Emit_109(N, X86::PHADDWrr64, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::PHADDWrr64, MVT::v4i16);
return Result;
}
@@ -16785,7 +16810,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (PHADDSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(736)) {
- SDNode *Result = Emit_109(N, X86::PHADDSWrr64, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::PHADDSWrr64, MVT::v4i16);
return Result;
}
@@ -16793,7 +16818,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (PHSUBWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(744)) {
- SDNode *Result = Emit_109(N, X86::PHSUBWrr64, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::PHSUBWrr64, MVT::v4i16);
return Result;
}
@@ -16801,7 +16826,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (PHSUBSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(742)) {
- SDNode *Result = Emit_109(N, X86::PHSUBSWrr64, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::PHSUBSWrr64, MVT::v4i16);
return Result;
}
@@ -16809,7 +16834,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (PMADDUBSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(746)) {
- SDNode *Result = Emit_109(N, X86::PMADDUBSWrr64, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::PMADDUBSWrr64, MVT::v4i16);
return Result;
}
@@ -16817,7 +16842,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (PMULHRSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(748)) {
- SDNode *Result = Emit_109(N, X86::PMULHRSWrr64, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::PMULHRSWrr64, MVT::v4i16);
return Result;
}
@@ -16825,7 +16850,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (PSIGNWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(756)) {
- SDNode *Result = Emit_109(N, X86::PSIGNWrr64, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::PSIGNWrr64, MVT::v4i16);
return Result;
}
}
@@ -16840,7 +16865,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PADDSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(461)) {
- SDNode *Result = Emit_109(N, X86::MMX_PADDSWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PADDSWrr, MVT::v4i16);
return Result;
}
@@ -16848,7 +16873,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PADDUSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(463)) {
- SDNode *Result = Emit_109(N, X86::MMX_PADDUSWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PADDUSWrr, MVT::v4i16);
return Result;
}
@@ -16856,7 +16881,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PSUBSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(499)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSUBSWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PSUBSWrr, MVT::v4i16);
return Result;
}
@@ -16864,7 +16889,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PSUBUSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(501)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSUBUSWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PSUBUSWrr, MVT::v4i16);
return Result;
}
@@ -16872,7 +16897,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PMULHWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(478)) {
- SDNode *Result = Emit_109(N, X86::MMX_PMULHWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PMULHWrr, MVT::v4i16);
return Result;
}
@@ -16880,7 +16905,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PMULHUWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(479)) {
- SDNode *Result = Emit_109(N, X86::MMX_PMULHUWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PMULHUWrr, MVT::v4i16);
return Result;
}
@@ -16888,7 +16913,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PAVGWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(465)) {
- SDNode *Result = Emit_109(N, X86::MMX_PAVGWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PAVGWrr, MVT::v4i16);
return Result;
}
@@ -16896,7 +16921,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PMINSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(475)) {
- SDNode *Result = Emit_109(N, X86::MMX_PMINSWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PMINSWrr, MVT::v4i16);
return Result;
}
@@ -16904,7 +16929,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PMAXSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(473)) {
- SDNode *Result = Emit_109(N, X86::MMX_PMAXSWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PMAXSWrr, MVT::v4i16);
return Result;
}
@@ -16912,7 +16937,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PSADBWrr:v4i16 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(481)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSADBWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PSADBWrr, MVT::v4i16);
return Result;
}
@@ -16920,7 +16945,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PSRLWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(494)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSRLWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PSRLWrr, MVT::v4i16);
return Result;
}
@@ -16928,7 +16953,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PSLLWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(484)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSLLWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PSLLWrr, MVT::v4i16);
return Result;
}
@@ -16936,7 +16961,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PSRAWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(489)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSRAWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PSRAWrr, MVT::v4i16);
return Result;
}
@@ -16944,7 +16969,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PCMPEQWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(468)) {
- SDNode *Result = Emit_109(N, X86::MMX_PCMPEQWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PCMPEQWrr, MVT::v4i16);
return Result;
}
@@ -16952,7 +16977,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PCMPGTWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(471)) {
- SDNode *Result = Emit_109(N, X86::MMX_PCMPGTWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PCMPGTWrr, MVT::v4i16);
return Result;
}
@@ -16960,7 +16985,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (MMX_PACKSSDWrr:v4i16 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(457)) {
- SDNode *Result = Emit_109(N, X86::MMX_PACKSSDWrr, MVT::v4i16);
+ SDNode *Result = Emit_111(N, X86::MMX_PACKSSDWrr, MVT::v4i16);
return Result;
}
}
@@ -16970,7 +16995,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_127(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+DISABLE_INLINE SDNode *Emit_129(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -16985,7 +17010,7 @@ DISABLE_INLINE SDNode *Emit_127(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N100.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_128(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10001_0, SDValue &CPTmpN10001_1, SDValue &CPTmpN10001_2, SDValue &CPTmpN10001_3, SDValue &CPTmpN10001_4) {
+DISABLE_INLINE SDNode *Emit_130(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10001_0, SDValue &CPTmpN10001_1, SDValue &CPTmpN10001_2, SDValue &CPTmpN10001_3, SDValue &CPTmpN10001_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -17001,7 +17026,7 @@ DISABLE_INLINE SDNode *Emit_128(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N1000.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_129(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_131(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -17050,7 +17075,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -17090,7 +17115,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -17126,7 +17151,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::PBLENDWrmi, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_120(N, X86::PBLENDWrmi, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17162,7 +17187,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_127(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -17198,7 +17223,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_127(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -17238,7 +17263,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PADDSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PADDSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17270,7 +17295,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17302,7 +17327,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSUBSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSUBSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17334,7 +17359,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSUBUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSUBUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17366,7 +17391,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17398,7 +17423,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PMULHWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMULHWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17430,7 +17455,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PAVGWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PAVGWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17462,7 +17487,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PMINSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMINSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17494,7 +17519,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17526,7 +17551,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSLLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSLLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17558,7 +17583,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSRLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSRLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17590,7 +17615,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSRAWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSRAWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17622,7 +17647,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17654,7 +17679,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PCMPGTWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PCMPGTWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17686,7 +17711,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PACKSSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PACKSSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17724,7 +17749,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_114(N, X86::PABSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_116(N, X86::PABSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -17756,7 +17781,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_115(N, X86::PHADDWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHADDWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17788,7 +17813,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_115(N, X86::PHSUBWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHSUBWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17820,7 +17845,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_115(N, X86::PHSUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHSUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17852,7 +17877,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PMADDUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMADDUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17884,7 +17909,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_115(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17916,7 +17941,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_115(N, X86::PSIGNWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSIGNWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17954,7 +17979,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_114(N, X86::PHMINPOSUWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_116(N, X86::PHMINPOSUWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -17986,7 +18011,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PACKUSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PACKUSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18018,7 +18043,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PMINUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMINUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18050,7 +18075,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18089,7 +18114,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PADDSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18122,7 +18147,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18155,7 +18180,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18188,7 +18213,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMULHWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMULHWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18221,7 +18246,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PAVGWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PAVGWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18254,7 +18279,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMINSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMINSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18287,7 +18312,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18327,7 +18352,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18367,7 +18392,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMINUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18400,7 +18425,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18429,7 +18454,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_131(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18456,7 +18481,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_131(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18478,7 +18503,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::PSLLWri, MVT::v8i16);
+ SDNode *Result = Emit_128(N, X86::PSLLWri, MVT::v8i16);
return Result;
}
}
@@ -18490,7 +18515,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::PSRLWri, MVT::v8i16);
+ SDNode *Result = Emit_128(N, X86::PSRLWri, MVT::v8i16);
return Result;
}
}
@@ -18502,7 +18527,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::PSRAWri, MVT::v8i16);
+ SDNode *Result = Emit_128(N, X86::PSRAWri, MVT::v8i16);
return Result;
}
}
@@ -18522,7 +18547,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_117(N, X86::PBLENDWrri, MVT::v8i16);
+ SDNode *Result = Emit_119(N, X86::PBLENDWrri, MVT::v8i16);
return Result;
}
}
@@ -18538,7 +18563,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PADDSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(547)) {
- SDNode *Result = Emit_109(N, X86::PADDSWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PADDSWrr, MVT::v8i16);
return Result;
}
@@ -18546,7 +18571,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PADDUSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(549)) {
- SDNode *Result = Emit_109(N, X86::PADDUSWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PADDUSWrr, MVT::v8i16);
return Result;
}
@@ -18554,7 +18579,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PSUBSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(589)) {
- SDNode *Result = Emit_109(N, X86::PSUBSWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PSUBSWrr, MVT::v8i16);
return Result;
}
@@ -18562,7 +18587,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PSUBUSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(591)) {
- SDNode *Result = Emit_109(N, X86::PSUBUSWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PSUBUSWrr, MVT::v8i16);
return Result;
}
@@ -18570,7 +18595,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PMULHUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(565)) {
- SDNode *Result = Emit_109(N, X86::PMULHUWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PMULHUWrr, MVT::v8i16);
return Result;
}
@@ -18578,7 +18603,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PMULHWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(564)) {
- SDNode *Result = Emit_109(N, X86::PMULHWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PMULHWrr, MVT::v8i16);
return Result;
}
@@ -18586,7 +18611,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PAVGWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(551)) {
- SDNode *Result = Emit_109(N, X86::PAVGWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PAVGWrr, MVT::v8i16);
return Result;
}
@@ -18594,7 +18619,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PMINSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(561)) {
- SDNode *Result = Emit_109(N, X86::PMINSWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PMINSWrr, MVT::v8i16);
return Result;
}
@@ -18602,7 +18627,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PMAXSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(559)) {
- SDNode *Result = Emit_109(N, X86::PMAXSWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PMAXSWrr, MVT::v8i16);
return Result;
}
@@ -18610,7 +18635,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PSLLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(572)) {
- SDNode *Result = Emit_109(N, X86::PSLLWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PSLLWrr, MVT::v8i16);
return Result;
}
@@ -18618,7 +18643,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PSRLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(584)) {
- SDNode *Result = Emit_109(N, X86::PSRLWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PSRLWrr, MVT::v8i16);
return Result;
}
@@ -18626,7 +18651,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PSRAWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(577)) {
- SDNode *Result = Emit_109(N, X86::PSRAWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PSRAWrr, MVT::v8i16);
return Result;
}
@@ -18634,7 +18659,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PCMPEQWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(554)) {
- SDNode *Result = Emit_109(N, X86::PCMPEQWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PCMPEQWrr, MVT::v8i16);
return Result;
}
@@ -18642,7 +18667,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PCMPGTWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(557)) {
- SDNode *Result = Emit_109(N, X86::PCMPGTWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PCMPGTWrr, MVT::v8i16);
return Result;
}
@@ -18650,7 +18675,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PACKSSDWrr:v8i16 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(543)) {
- SDNode *Result = Emit_109(N, X86::PACKSSDWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PACKSSDWrr, MVT::v8i16);
return Result;
}
}
@@ -18665,7 +18690,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PABSWrr128:v8i16 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(731)) {
- SDNode *Result = Emit_106(N, X86::PABSWrr128, MVT::v8i16);
+ SDNode *Result = Emit_108(N, X86::PABSWrr128, MVT::v8i16);
return Result;
}
@@ -18673,7 +18698,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PHADDWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(739)) {
- SDNode *Result = Emit_109(N, X86::PHADDWrr128, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PHADDWrr128, MVT::v8i16);
return Result;
}
@@ -18681,7 +18706,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PHSUBWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(745)) {
- SDNode *Result = Emit_109(N, X86::PHSUBWrr128, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PHSUBWrr128, MVT::v8i16);
return Result;
}
@@ -18689,7 +18714,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PHSUBSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(743)) {
- SDNode *Result = Emit_109(N, X86::PHSUBSWrr128, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PHSUBSWrr128, MVT::v8i16);
return Result;
}
@@ -18697,7 +18722,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PMADDUBSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(747)) {
- SDNode *Result = Emit_109(N, X86::PMADDUBSWrr128, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PMADDUBSWrr128, MVT::v8i16);
return Result;
}
@@ -18705,7 +18730,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PMULHRSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(749)) {
- SDNode *Result = Emit_109(N, X86::PMULHRSWrr128, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PMULHRSWrr128, MVT::v8i16);
return Result;
}
@@ -18713,7 +18738,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PSIGNWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(757)) {
- SDNode *Result = Emit_109(N, X86::PSIGNWrr128, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PSIGNWrr128, MVT::v8i16);
return Result;
}
}
@@ -18728,7 +18753,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PHMINPOSUWrr128:v8i16 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(630)) {
- SDNode *Result = Emit_106(N, X86::PHMINPOSUWrr128, MVT::v8i16);
+ SDNode *Result = Emit_108(N, X86::PHMINPOSUWrr128, MVT::v8i16);
return Result;
}
@@ -18736,7 +18761,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PACKUSDWrr:v8i16 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(623)) {
- SDNode *Result = Emit_109(N, X86::PACKUSDWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PACKUSDWrr, MVT::v8i16);
return Result;
}
@@ -18744,7 +18769,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PMINUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(638)) {
- SDNode *Result = Emit_109(N, X86::PMINUWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PMINUWrr, MVT::v8i16);
return Result;
}
@@ -18752,7 +18777,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PMAXUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(634)) {
- SDNode *Result = Emit_109(N, X86::PMAXUWrr, MVT::v8i16);
+ SDNode *Result = Emit_111(N, X86::PMAXUWrr, MVT::v8i16);
return Result;
}
@@ -18760,7 +18785,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PMOVSXBWrr:v8i16 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(641)) {
- SDNode *Result = Emit_106(N, X86::PMOVSXBWrr, MVT::v8i16);
+ SDNode *Result = Emit_108(N, X86::PMOVSXBWrr, MVT::v8i16);
return Result;
}
@@ -18768,7 +18793,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (PMOVZXBWrr:v8i16 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(647)) {
- SDNode *Result = Emit_106(N, X86::PMOVZXBWrr, MVT::v8i16);
+ SDNode *Result = Emit_108(N, X86::PMOVZXBWrr, MVT::v8i16);
return Result;
}
}
@@ -18809,7 +18834,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_114(N, X86::PABSDrm64, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_116(N, X86::PABSDrm64, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18841,7 +18866,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_115(N, X86::PHADDDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHADDDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18873,7 +18898,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_115(N, X86::PHSUBDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHSUBDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18905,7 +18930,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_115(N, X86::PSIGNDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSIGNDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18943,7 +18968,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18974,7 +18999,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19005,7 +19030,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSRLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSRLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19036,7 +19061,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSLLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSLLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19067,7 +19092,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSRADrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSRADrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19098,7 +19123,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19129,7 +19154,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PCMPGTDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PCMPGTDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19160,7 +19185,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -19192,7 +19217,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -19226,7 +19251,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -19251,7 +19276,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -19284,7 +19309,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -19310,7 +19335,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -19332,7 +19357,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::MMX_PSRLDri, MVT::v2i32);
+ SDNode *Result = Emit_128(N, X86::MMX_PSRLDri, MVT::v2i32);
return Result;
}
}
@@ -19344,7 +19369,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::MMX_PSLLDri, MVT::v2i32);
+ SDNode *Result = Emit_128(N, X86::MMX_PSLLDri, MVT::v2i32);
return Result;
}
}
@@ -19356,7 +19381,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::MMX_PSRADri, MVT::v2i32);
+ SDNode *Result = Emit_128(N, X86::MMX_PSRADri, MVT::v2i32);
return Result;
}
}
@@ -19372,7 +19397,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (Int_CVTPS2PIrr:v2i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(691)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTPS2PIrr, MVT::v2i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPS2PIrr, MVT::v2i32);
return Result;
}
@@ -19380,7 +19405,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (Int_CVTTPS2PIrr:v2i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(697)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTTPS2PIrr, MVT::v2i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPS2PIrr, MVT::v2i32);
return Result;
}
}
@@ -19395,7 +19420,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (Int_CVTPD2PIrr:v2i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(688)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTPD2PIrr, MVT::v2i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPD2PIrr, MVT::v2i32);
return Result;
}
@@ -19403,7 +19428,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (Int_CVTTPD2PIrr:v2i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(696)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTTPD2PIrr, MVT::v2i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPD2PIrr, MVT::v2i32);
return Result;
}
}
@@ -19418,7 +19443,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (PABSDrr64:v2i32 VR64:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(728)) {
- SDNode *Result = Emit_106(N, X86::PABSDrr64, MVT::v2i32);
+ SDNode *Result = Emit_108(N, X86::PABSDrr64, MVT::v2i32);
return Result;
}
@@ -19426,7 +19451,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (PHADDDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(734)) {
- SDNode *Result = Emit_109(N, X86::PHADDDrr64, MVT::v2i32);
+ SDNode *Result = Emit_111(N, X86::PHADDDrr64, MVT::v2i32);
return Result;
}
@@ -19434,7 +19459,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (PHSUBDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(740)) {
- SDNode *Result = Emit_109(N, X86::PHSUBDrr64, MVT::v2i32);
+ SDNode *Result = Emit_111(N, X86::PHSUBDrr64, MVT::v2i32);
return Result;
}
@@ -19442,7 +19467,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (PSIGNDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(754)) {
- SDNode *Result = Emit_109(N, X86::PSIGNDrr64, MVT::v2i32);
+ SDNode *Result = Emit_111(N, X86::PSIGNDrr64, MVT::v2i32);
return Result;
}
}
@@ -19457,7 +19482,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (MMX_PMULUDQrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(480)) {
- SDNode *Result = Emit_109(N, X86::MMX_PMULUDQrr, MVT::v2i32);
+ SDNode *Result = Emit_111(N, X86::MMX_PMULUDQrr, MVT::v2i32);
return Result;
}
@@ -19465,7 +19490,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (MMX_PMADDWDrr:v2i32 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(472)) {
- SDNode *Result = Emit_109(N, X86::MMX_PMADDWDrr, MVT::v2i32);
+ SDNode *Result = Emit_111(N, X86::MMX_PMADDWDrr, MVT::v2i32);
return Result;
}
@@ -19473,7 +19498,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (MMX_PSRLDrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(492)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSRLDrr, MVT::v2i32);
+ SDNode *Result = Emit_111(N, X86::MMX_PSRLDrr, MVT::v2i32);
return Result;
}
@@ -19481,7 +19506,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (MMX_PSLLDrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(482)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSLLDrr, MVT::v2i32);
+ SDNode *Result = Emit_111(N, X86::MMX_PSLLDrr, MVT::v2i32);
return Result;
}
@@ -19489,7 +19514,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (MMX_PSRADrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(488)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSRADrr, MVT::v2i32);
+ SDNode *Result = Emit_111(N, X86::MMX_PSRADrr, MVT::v2i32);
return Result;
}
@@ -19497,7 +19522,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (MMX_PCMPEQDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(467)) {
- SDNode *Result = Emit_109(N, X86::MMX_PCMPEQDrr, MVT::v2i32);
+ SDNode *Result = Emit_111(N, X86::MMX_PCMPEQDrr, MVT::v2i32);
return Result;
}
@@ -19505,7 +19530,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (MMX_PCMPGTDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(470)) {
- SDNode *Result = Emit_109(N, X86::MMX_PCMPGTDrr, MVT::v2i32);
+ SDNode *Result = Emit_111(N, X86::MMX_PCMPGTDrr, MVT::v2i32);
return Result;
}
}
@@ -19515,7 +19540,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_130(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_132(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -19567,7 +19592,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -19607,7 +19632,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -19646,7 +19671,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -19685,7 +19710,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -19722,7 +19747,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_127(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -19758,7 +19783,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_127(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -19793,7 +19818,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_127(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -19828,7 +19853,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_127(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -19868,7 +19893,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19900,7 +19925,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSLLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSLLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19932,7 +19957,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSRLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSRLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19964,7 +19989,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSRADrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSRADrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19996,7 +20021,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20028,7 +20053,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PCMPGTDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PCMPGTDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20066,7 +20091,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_114(N, X86::PABSDrm128, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_116(N, X86::PABSDrm128, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20098,7 +20123,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_115(N, X86::PHADDDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHADDDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20130,7 +20155,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_115(N, X86::PHADDSWrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHADDSWrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20162,7 +20187,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_115(N, X86::PHSUBDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PHSUBDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20194,7 +20219,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_115(N, X86::PSIGNDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSIGNDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20233,7 +20258,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PMINSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMINSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20265,7 +20290,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PMINUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMINUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20297,7 +20322,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20329,7 +20354,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20368,7 +20393,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20408,7 +20433,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMINSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20441,7 +20466,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMINUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20474,7 +20499,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20507,7 +20532,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20536,7 +20561,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_131(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20563,7 +20588,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_131(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20596,7 +20621,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -20622,7 +20647,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -20648,7 +20673,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -20674,7 +20699,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -20709,7 +20734,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -20733,7 +20758,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_130(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_132(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -20755,7 +20780,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::PSLLDri, MVT::v4i32);
+ SDNode *Result = Emit_128(N, X86::PSLLDri, MVT::v4i32);
return Result;
}
}
@@ -20767,7 +20792,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::PSRLDri, MVT::v4i32);
+ SDNode *Result = Emit_128(N, X86::PSRLDri, MVT::v4i32);
return Result;
}
}
@@ -20779,7 +20804,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::PSRADri, MVT::v4i32);
+ SDNode *Result = Emit_128(N, X86::PSRADri, MVT::v4i32);
return Result;
}
}
@@ -20788,7 +20813,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (Int_CVTPS2DQrr:v4i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(516)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTPS2DQrr, MVT::v4i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPS2DQrr, MVT::v4i32);
return Result;
}
@@ -20796,7 +20821,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (Int_CVTTPS2DQrr:v4i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(525)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTTPS2DQrr, MVT::v4i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPS2DQrr, MVT::v4i32);
return Result;
}
@@ -20804,7 +20829,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (Int_CVTPD2DQrr:v4i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(514)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTPD2DQrr, MVT::v4i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPD2DQrr, MVT::v4i32);
return Result;
}
@@ -20812,7 +20837,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (Int_CVTTPD2DQrr:v4i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(524)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTTPD2DQrr, MVT::v4i32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPD2DQrr, MVT::v4i32);
return Result;
}
@@ -20820,7 +20845,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PMADDWDrr:v4i32 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(558)) {
- SDNode *Result = Emit_109(N, X86::PMADDWDrr, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PMADDWDrr, MVT::v4i32);
return Result;
}
@@ -20828,7 +20853,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PSLLDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(568)) {
- SDNode *Result = Emit_109(N, X86::PSLLDrr, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PSLLDrr, MVT::v4i32);
return Result;
}
@@ -20836,7 +20861,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PSRLDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(580)) {
- SDNode *Result = Emit_109(N, X86::PSRLDrr, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PSRLDrr, MVT::v4i32);
return Result;
}
@@ -20844,7 +20869,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PSRADrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(576)) {
- SDNode *Result = Emit_109(N, X86::PSRADrr, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PSRADrr, MVT::v4i32);
return Result;
}
@@ -20852,7 +20877,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PCMPEQDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(553)) {
- SDNode *Result = Emit_109(N, X86::PCMPEQDrr, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PCMPEQDrr, MVT::v4i32);
return Result;
}
@@ -20860,7 +20885,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PCMPGTDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(556)) {
- SDNode *Result = Emit_109(N, X86::PCMPGTDrr, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PCMPGTDrr, MVT::v4i32);
return Result;
}
}
@@ -20875,7 +20900,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PABSDrr128:v4i32 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(729)) {
- SDNode *Result = Emit_106(N, X86::PABSDrr128, MVT::v4i32);
+ SDNode *Result = Emit_108(N, X86::PABSDrr128, MVT::v4i32);
return Result;
}
@@ -20883,7 +20908,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PHADDDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(735)) {
- SDNode *Result = Emit_109(N, X86::PHADDDrr128, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PHADDDrr128, MVT::v4i32);
return Result;
}
@@ -20891,7 +20916,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PHADDSWrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(737)) {
- SDNode *Result = Emit_109(N, X86::PHADDSWrr128, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PHADDSWrr128, MVT::v4i32);
return Result;
}
@@ -20899,7 +20924,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PHSUBDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(741)) {
- SDNode *Result = Emit_109(N, X86::PHSUBDrr128, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PHSUBDrr128, MVT::v4i32);
return Result;
}
@@ -20907,7 +20932,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PSIGNDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(755)) {
- SDNode *Result = Emit_109(N, X86::PSIGNDrr128, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PSIGNDrr128, MVT::v4i32);
return Result;
}
}
@@ -20922,7 +20947,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PMINSDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(636)) {
- SDNode *Result = Emit_109(N, X86::PMINSDrr, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PMINSDrr, MVT::v4i32);
return Result;
}
@@ -20930,7 +20955,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PMINUDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(637)) {
- SDNode *Result = Emit_109(N, X86::PMINUDrr, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PMINUDrr, MVT::v4i32);
return Result;
}
@@ -20938,7 +20963,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PMAXSDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(632)) {
- SDNode *Result = Emit_109(N, X86::PMAXSDrr, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PMAXSDrr, MVT::v4i32);
return Result;
}
@@ -20946,7 +20971,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PMAXUDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(633)) {
- SDNode *Result = Emit_109(N, X86::PMAXUDrr, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PMAXUDrr, MVT::v4i32);
return Result;
}
@@ -20954,7 +20979,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PMULLDrr_int:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(652)) {
- SDNode *Result = Emit_109(N, X86::PMULLDrr_int, MVT::v4i32);
+ SDNode *Result = Emit_111(N, X86::PMULLDrr_int, MVT::v4i32);
return Result;
}
@@ -20962,7 +20987,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PMOVSXWDrr:v4i32 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(643)) {
- SDNode *Result = Emit_106(N, X86::PMOVSXWDrr, MVT::v4i32);
+ SDNode *Result = Emit_108(N, X86::PMOVSXWDrr, MVT::v4i32);
return Result;
}
@@ -20970,7 +20995,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PMOVZXWDrr:v4i32 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(649)) {
- SDNode *Result = Emit_106(N, X86::PMOVZXWDrr, MVT::v4i32);
+ SDNode *Result = Emit_108(N, X86::PMOVZXWDrr, MVT::v4i32);
return Result;
}
@@ -20978,7 +21003,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PMOVSXBDrr:v4i32 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(639)) {
- SDNode *Result = Emit_106(N, X86::PMOVSXBDrr, MVT::v4i32);
+ SDNode *Result = Emit_108(N, X86::PMOVSXBDrr, MVT::v4i32);
return Result;
}
@@ -20986,7 +21011,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (PMOVZXBDrr:v4i32 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(645)) {
- SDNode *Result = Emit_106(N, X86::PMOVZXBDrr, MVT::v4i32);
+ SDNode *Result = Emit_108(N, X86::PMOVZXBDrr, MVT::v4i32);
return Result;
}
}
@@ -20996,7 +21021,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_131(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_133(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -21005,7 +21030,7 @@ DISABLE_INLINE SDNode *Emit_131(const SDValue &N, unsigned Opc0, MVT::SimpleValu
SDValue Tmp5 = Transform_BYTE_imm(Tmp4.getNode());
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, Tmp5);
}
-DISABLE_INLINE SDNode *Emit_132(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+DISABLE_INLINE SDNode *Emit_134(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -21053,7 +21078,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSRLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSRLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21084,7 +21109,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_115(N, X86::MMX_PSLLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSLLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21121,7 +21146,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_132(N, X86::PALIGNR64rm, MVT::v1i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_134(N, X86::PALIGNR64rm, MVT::v1i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -21144,7 +21169,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::MMX_PSRLQri, MVT::v1i64);
+ SDNode *Result = Emit_128(N, X86::MMX_PSRLQri, MVT::v1i64);
return Result;
}
}
@@ -21156,7 +21181,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::MMX_PSLLQri, MVT::v1i64);
+ SDNode *Result = Emit_128(N, X86::MMX_PSLLQri, MVT::v1i64);
return Result;
}
}
@@ -21176,7 +21201,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_131(N, X86::PALIGNR64rr, MVT::v1i64);
+ SDNode *Result = Emit_133(N, X86::PALIGNR64rr, MVT::v1i64);
return Result;
}
}
@@ -21192,7 +21217,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (MMX_PSRLQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(493)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSRLQrr, MVT::v1i64);
+ SDNode *Result = Emit_111(N, X86::MMX_PSRLQrr, MVT::v1i64);
return Result;
}
@@ -21200,7 +21225,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (MMX_PSLLQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(483)) {
- SDNode *Result = Emit_109(N, X86::MMX_PSLLQrr, MVT::v1i64);
+ SDNode *Result = Emit_111(N, X86::MMX_PSLLQrr, MVT::v1i64);
return Result;
}
}
@@ -21210,7 +21235,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_133(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_135(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -21256,7 +21281,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21296,7 +21321,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21335,7 +21360,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21374,7 +21399,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21413,7 +21438,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21452,7 +21477,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_130(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21489,7 +21514,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_127(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21525,7 +21550,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_127(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21560,7 +21585,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_127(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21595,7 +21620,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_127(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21630,7 +21655,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_127(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21665,7 +21690,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_127(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21705,7 +21730,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21737,7 +21762,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSADBWrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSADBWrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21769,7 +21794,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSLLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSLLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21801,7 +21826,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::PSRLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PSRLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21840,7 +21865,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21872,7 +21897,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PMULDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PMULDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21911,7 +21936,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PCMPGTQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_117(N, X86::PCMPGTQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21948,7 +21973,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_132(N, X86::PALIGNR128rm, MVT::v2i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_134(N, X86::PALIGNR128rm, MVT::v2i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -21987,7 +22012,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22020,7 +22045,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSADBWrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PSADBWrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22060,7 +22085,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22093,7 +22118,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N2 = N.getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMULDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_118(N, X86::PMULDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22122,7 +22147,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_131(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22149,7 +22174,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_131(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22171,7 +22196,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::PSLLQri, MVT::v2i64);
+ SDNode *Result = Emit_128(N, X86::PSLLQri, MVT::v2i64);
return Result;
}
}
@@ -22183,7 +22208,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::PSRLQri, MVT::v2i64);
+ SDNode *Result = Emit_128(N, X86::PSRLQri, MVT::v2i64);
return Result;
}
}
@@ -22195,7 +22220,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_133(N, X86::PSLLDQri, MVT::v2i64);
+ SDNode *Result = Emit_135(N, X86::PSLLDQri, MVT::v2i64);
return Result;
}
}
@@ -22207,7 +22232,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_133(N, X86::PSRLDQri, MVT::v2i64);
+ SDNode *Result = Emit_135(N, X86::PSRLDQri, MVT::v2i64);
return Result;
}
}
@@ -22219,7 +22244,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::PSLLDQri, MVT::v2i64);
+ SDNode *Result = Emit_128(N, X86::PSLLDQri, MVT::v2i64);
return Result;
}
}
@@ -22231,7 +22256,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::PSRLDQri, MVT::v2i64);
+ SDNode *Result = Emit_128(N, X86::PSRLDQri, MVT::v2i64);
return Result;
}
}
@@ -22251,7 +22276,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_131(N, X86::PALIGNR128rr, MVT::v2i64);
+ SDNode *Result = Emit_133(N, X86::PALIGNR128rr, MVT::v2i64);
return Result;
}
}
@@ -22267,7 +22292,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PMULUDQrr:v2i64 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(566)) {
- SDNode *Result = Emit_109(N, X86::PMULUDQrr, MVT::v2i64);
+ SDNode *Result = Emit_111(N, X86::PMULUDQrr, MVT::v2i64);
return Result;
}
@@ -22275,7 +22300,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PSADBWrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(567)) {
- SDNode *Result = Emit_109(N, X86::PSADBWrr, MVT::v2i64);
+ SDNode *Result = Emit_111(N, X86::PSADBWrr, MVT::v2i64);
return Result;
}
@@ -22283,7 +22308,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PSLLQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(571)) {
- SDNode *Result = Emit_109(N, X86::PSLLQrr, MVT::v2i64);
+ SDNode *Result = Emit_111(N, X86::PSLLQrr, MVT::v2i64);
return Result;
}
@@ -22291,7 +22316,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PSRLQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(583)) {
- SDNode *Result = Emit_109(N, X86::PSRLQrr, MVT::v2i64);
+ SDNode *Result = Emit_111(N, X86::PSRLQrr, MVT::v2i64);
return Result;
}
}
@@ -22306,7 +22331,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PCMPEQQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(626)) {
- SDNode *Result = Emit_109(N, X86::PCMPEQQrr, MVT::v2i64);
+ SDNode *Result = Emit_111(N, X86::PCMPEQQrr, MVT::v2i64);
return Result;
}
@@ -22314,7 +22339,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PMULDQrr:v2i64 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(651)) {
- SDNode *Result = Emit_109(N, X86::PMULDQrr, MVT::v2i64);
+ SDNode *Result = Emit_111(N, X86::PMULDQrr, MVT::v2i64);
return Result;
}
@@ -22322,7 +22347,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PMOVSXDQrr:v2i64 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(642)) {
- SDNode *Result = Emit_106(N, X86::PMOVSXDQrr, MVT::v2i64);
+ SDNode *Result = Emit_108(N, X86::PMOVSXDQrr, MVT::v2i64);
return Result;
}
@@ -22330,7 +22355,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PMOVZXDQrr:v2i64 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(648)) {
- SDNode *Result = Emit_106(N, X86::PMOVZXDQrr, MVT::v2i64);
+ SDNode *Result = Emit_108(N, X86::PMOVZXDQrr, MVT::v2i64);
return Result;
}
@@ -22338,7 +22363,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PMOVSXWQrr:v2i64 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(644)) {
- SDNode *Result = Emit_106(N, X86::PMOVSXWQrr, MVT::v2i64);
+ SDNode *Result = Emit_108(N, X86::PMOVSXWQrr, MVT::v2i64);
return Result;
}
@@ -22346,7 +22371,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PMOVZXWQrr:v2i64 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(650)) {
- SDNode *Result = Emit_106(N, X86::PMOVZXWQrr, MVT::v2i64);
+ SDNode *Result = Emit_108(N, X86::PMOVZXWQrr, MVT::v2i64);
return Result;
}
@@ -22354,7 +22379,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PMOVSXBQrr:v2i64 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(640)) {
- SDNode *Result = Emit_106(N, X86::PMOVSXBQrr, MVT::v2i64);
+ SDNode *Result = Emit_108(N, X86::PMOVSXBQrr, MVT::v2i64);
return Result;
}
@@ -22362,7 +22387,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (PMOVZXBQrr:v2i64 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(646)) {
- SDNode *Result = Emit_106(N, X86::PMOVZXBQrr, MVT::v2i64);
+ SDNode *Result = Emit_108(N, X86::PMOVZXBQrr, MVT::v2i64);
return Result;
}
}
@@ -22377,7 +22402,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(671)) {
- SDNode *Result = Emit_109(N, X86::PCMPGTQrr, MVT::v2i64);
+ SDNode *Result = Emit_111(N, X86::PCMPGTQrr, MVT::v2i64);
return Result;
}
}
@@ -22387,7 +22412,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_134(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
+DISABLE_INLINE SDNode *Emit_136(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -22396,7 +22421,7 @@ DISABLE_INLINE SDNode *Emit_134(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(CPInChain.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_135(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4, SDValue &Chain1) {
+DISABLE_INLINE SDNode *Emit_137(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4, SDValue &Chain1) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1 };
@@ -22404,7 +22429,7 @@ DISABLE_INLINE SDNode *Emit_135(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(CPInChain.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_136(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_138(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -22419,7 +22444,7 @@ DISABLE_INLINE SDNode *Emit_136(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_137(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
+DISABLE_INLINE SDNode *Emit_139(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -22464,7 +22489,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::BLENDPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_120(N, X86::BLENDPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -22500,7 +22525,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::DPPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_120(N, X86::DPPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -22533,7 +22558,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_125(N, X86::DPPSrmi, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_127(N, X86::DPPSrmi, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22570,7 +22595,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_122(N, X86::Int_CMPSSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_124(N, X86::Int_CMPSSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -22600,7 +22625,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_122(N, X86::CMPPSrmi, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_124(N, X86::CMPPSrmi, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -22638,7 +22663,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_114(N, X86::Int_CVTDQ2PSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_116(N, X86::Int_CVTDQ2PSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22674,7 +22699,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_136(N, X86::ROUNDPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_138(N, X86::ROUNDPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -22707,7 +22732,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
SDValue N3 = N.getOperand(3);
if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_120(N, X86::BLENDVPSrm0, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_122(N, X86::BLENDVPSrm0, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -22743,7 +22768,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSI2SS64rm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::Int_CVTSI2SS64rm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -22769,7 +22794,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPI2PSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::Int_CVTPI2PSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -22795,7 +22820,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSI2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::Int_CVTSI2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -22822,7 +22847,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::MAXPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::MAXPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -22849,7 +22874,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::MINPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::MINPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -22875,7 +22900,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::SQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::SQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -22901,7 +22926,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::RSQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::RSQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -22927,7 +22952,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::RCPPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::RCPPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -22960,7 +22985,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPD2PSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTPD2PSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -22986,7 +23011,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSD2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::Int_CVTSD2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -23020,7 +23045,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::ADDSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::ADDSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -23047,7 +23072,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::HADDPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::HADDPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -23074,7 +23099,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::HSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::HSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -23104,7 +23129,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_137(N, X86::ROUNDSSm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_139(N, X86::ROUNDSSm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -23131,7 +23156,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::ADDSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::ADDSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -23150,7 +23175,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::MULSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::MULSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -23169,7 +23194,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::SUBSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::SUBSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -23188,7 +23213,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::DIVSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::DIVSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -23207,7 +23232,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::MAXSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::MAXSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -23226,7 +23251,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::MINSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::MINSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -23244,7 +23269,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPInChain;
SDValue Chain1;
if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_135(N, X86::SQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ SDNode *Result = Emit_137(N, X86::SQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
return Result;
}
}
@@ -23262,7 +23287,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPInChain;
SDValue Chain1;
if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_135(N, X86::RSQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ SDNode *Result = Emit_137(N, X86::RSQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
return Result;
}
}
@@ -23280,7 +23305,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPInChain;
SDValue Chain1;
if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_135(N, X86::RCPSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ SDNode *Result = Emit_137(N, X86::RCPSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
return Result;
}
}
@@ -23301,7 +23326,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_121(N, X86::Int_CMPSSrr, MVT::v4f32);
+ SDNode *Result = Emit_123(N, X86::Int_CMPSSrr, MVT::v4f32);
return Result;
}
}
@@ -23314,7 +23339,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_121(N, X86::CMPPSrri, MVT::v4f32);
+ SDNode *Result = Emit_123(N, X86::CMPPSrri, MVT::v4f32);
return Result;
}
}
@@ -23333,7 +23358,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::ROUNDPSr_Int, MVT::v4f32);
+ SDNode *Result = Emit_128(N, X86::ROUNDPSr_Int, MVT::v4f32);
return Result;
}
}
@@ -23346,7 +23371,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_117(N, X86::ROUNDSSr_Int, MVT::v4f32);
+ SDNode *Result = Emit_119(N, X86::ROUNDSSr_Int, MVT::v4f32);
return Result;
}
}
@@ -23359,7 +23384,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_117(N, X86::BLENDPSrri, MVT::v4f32);
+ SDNode *Result = Emit_119(N, X86::BLENDPSrri, MVT::v4f32);
return Result;
}
}
@@ -23372,7 +23397,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_117(N, X86::DPPSrri, MVT::v4f32);
+ SDNode *Result = Emit_119(N, X86::DPPSrri, MVT::v4f32);
return Result;
}
}
@@ -23392,7 +23417,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_117(N, X86::INSERTPSrr, MVT::v4f32);
+ SDNode *Result = Emit_119(N, X86::INSERTPSrr, MVT::v4f32);
return Result;
}
}
@@ -23408,7 +23433,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (Int_CVTSI2SS64rr:v4f32 VR128:v4f32:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(693)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SS64rr, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::Int_CVTSI2SS64rr, MVT::v4f32);
return Result;
}
@@ -23416,7 +23441,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (Int_CVTPI2PSrr:v4f32 VR128:v4f32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(690)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTPI2PSrr, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::Int_CVTPI2PSrr, MVT::v4f32);
return Result;
}
@@ -23424,7 +23449,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (Int_CVTSI2SSrr:v4f32 VR128:v4f32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(692)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SSrr, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::Int_CVTSI2SSrr, MVT::v4f32);
return Result;
}
@@ -23432,7 +23457,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (ADDSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(679)) {
- SDNode *Result = Emit_109(N, X86::ADDSSrr_Int, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::ADDSSrr_Int, MVT::v4f32);
return Result;
}
@@ -23440,7 +23465,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (MULSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(709)) {
- SDNode *Result = Emit_109(N, X86::MULSSrr_Int, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::MULSSrr_Int, MVT::v4f32);
return Result;
}
@@ -23448,7 +23473,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (SUBSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(719)) {
- SDNode *Result = Emit_109(N, X86::SUBSSrr_Int, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::SUBSSrr_Int, MVT::v4f32);
return Result;
}
@@ -23456,7 +23481,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (DIVSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(700)) {
- SDNode *Result = Emit_109(N, X86::DIVSSrr_Int, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::DIVSSrr_Int, MVT::v4f32);
return Result;
}
@@ -23464,7 +23489,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (MAXSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(704)) {
- SDNode *Result = Emit_109(N, X86::MAXSSrr_Int, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::MAXSSrr_Int, MVT::v4f32);
return Result;
}
@@ -23472,7 +23497,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (MAXPSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(703)) {
- SDNode *Result = Emit_109(N, X86::MAXPSrr_Int, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::MAXPSrr_Int, MVT::v4f32);
return Result;
}
@@ -23480,7 +23505,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (MINSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(706)) {
- SDNode *Result = Emit_109(N, X86::MINSSrr_Int, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::MINSSrr_Int, MVT::v4f32);
return Result;
}
@@ -23488,7 +23513,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (MINPSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(705)) {
- SDNode *Result = Emit_109(N, X86::MINPSrr_Int, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::MINPSrr_Int, MVT::v4f32);
return Result;
}
@@ -23496,7 +23521,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (SQRTSSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(716)) {
- SDNode *Result = Emit_106(N, X86::SQRTSSr_Int, MVT::v4f32);
+ SDNode *Result = Emit_108(N, X86::SQRTSSr_Int, MVT::v4f32);
return Result;
}
@@ -23504,7 +23529,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (SQRTPSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(715)) {
- SDNode *Result = Emit_106(N, X86::SQRTPSr_Int, MVT::v4f32);
+ SDNode *Result = Emit_108(N, X86::SQRTPSr_Int, MVT::v4f32);
return Result;
}
@@ -23512,7 +23537,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (RSQRTSSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(713)) {
- SDNode *Result = Emit_106(N, X86::RSQRTSSr_Int, MVT::v4f32);
+ SDNode *Result = Emit_108(N, X86::RSQRTSSr_Int, MVT::v4f32);
return Result;
}
@@ -23520,7 +23545,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (RSQRTPSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(712)) {
- SDNode *Result = Emit_106(N, X86::RSQRTPSr_Int, MVT::v4f32);
+ SDNode *Result = Emit_108(N, X86::RSQRTPSr_Int, MVT::v4f32);
return Result;
}
@@ -23528,7 +23553,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (RCPSSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(711)) {
- SDNode *Result = Emit_106(N, X86::RCPSSr_Int, MVT::v4f32);
+ SDNode *Result = Emit_108(N, X86::RCPSSr_Int, MVT::v4f32);
return Result;
}
@@ -23536,7 +23561,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (RCPPSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(710)) {
- SDNode *Result = Emit_106(N, X86::RCPPSr_Int, MVT::v4f32);
+ SDNode *Result = Emit_108(N, X86::RCPPSr_Int, MVT::v4f32);
return Result;
}
}
@@ -23551,7 +23576,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (Int_CVTDQ2PSrr:v4f32 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(513)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTDQ2PSrr, MVT::v4f32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTDQ2PSrr, MVT::v4f32);
return Result;
}
@@ -23559,7 +23584,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (Int_CVTPD2PSrr:v4f32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(515)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTPD2PSrr, MVT::v4f32);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPD2PSrr, MVT::v4f32);
return Result;
}
@@ -23567,7 +23592,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (Int_CVTSD2SSrr:v4f32 VR128:v4f32:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(520)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSD2SSrr, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::Int_CVTSD2SSrr, MVT::v4f32);
return Result;
}
}
@@ -23582,7 +23607,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (ADDSUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(605)) {
- SDNode *Result = Emit_109(N, X86::ADDSUBPSrr, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::ADDSUBPSrr, MVT::v4f32);
return Result;
}
@@ -23590,7 +23615,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (HADDPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(607)) {
- SDNode *Result = Emit_109(N, X86::HADDPSrr, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::HADDPSrr, MVT::v4f32);
return Result;
}
@@ -23598,7 +23623,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (HSUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(609)) {
- SDNode *Result = Emit_109(N, X86::HSUBPSrr, MVT::v4f32);
+ SDNode *Result = Emit_111(N, X86::HSUBPSrr, MVT::v4f32);
return Result;
}
}
@@ -23613,7 +23638,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(616)) {
- SDNode *Result = Emit_119(N, X86::BLENDVPSrr0, MVT::v4f32);
+ SDNode *Result = Emit_121(N, X86::BLENDVPSrr0, MVT::v4f32);
return Result;
}
}
@@ -23657,7 +23682,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::BLENDPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_120(N, X86::BLENDPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -23693,7 +23718,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::DPPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_120(N, X86::DPPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -23726,7 +23751,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_125(N, X86::DPPDrmi, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_127(N, X86::DPPDrmi, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -23763,7 +23788,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_122(N, X86::Int_CMPSDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_124(N, X86::Int_CMPSDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -23794,7 +23819,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_114(N, X86::Int_CVTDQ2PDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_116(N, X86::Int_CVTDQ2PDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -23824,7 +23849,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_122(N, X86::CMPPDrmi, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_124(N, X86::CMPPDrmi, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -23860,7 +23885,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_136(N, X86::ROUNDPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_138(N, X86::ROUNDPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -23893,7 +23918,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
SDValue N3 = N.getOperand(3);
if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_120(N, X86::BLENDVPDrm0, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_122(N, X86::BLENDVPDrm0, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -23929,7 +23954,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSI2SD64rm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::Int_CVTSI2SD64rm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -23954,7 +23979,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPI2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTPI2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -23981,7 +24006,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::MAXPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::MAXPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -24008,7 +24033,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::MINPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::MINPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -24033,7 +24058,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPS2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTPS2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -24059,7 +24084,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSI2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::Int_CVTSI2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -24085,7 +24110,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSS2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::Int_CVTSS2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -24111,7 +24136,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_107(N, X86::SQRTPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_109(N, X86::SQRTPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -24145,7 +24170,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::ADDSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::ADDSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -24172,7 +24197,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::HADDPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::HADDPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -24199,7 +24224,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_108(N, X86::HSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_110(N, X86::HSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -24229,7 +24254,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_137(N, X86::ROUNDSDm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_139(N, X86::ROUNDSDm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -24256,7 +24281,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::ADDSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::ADDSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -24275,7 +24300,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::MULSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::MULSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -24294,7 +24319,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::SUBSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::SUBSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -24313,7 +24338,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::DIVSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::DIVSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -24332,7 +24357,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::MAXSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::MAXSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -24351,7 +24376,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPInChain;
SDValue Chain2;
if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_134(N, X86::MINSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ SDNode *Result = Emit_136(N, X86::MINSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -24369,7 +24394,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPInChain;
SDValue Chain1;
if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_135(N, X86::SQRTSDm_Int, MVT::v2f64, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ SDNode *Result = Emit_137(N, X86::SQRTSDm_Int, MVT::v2f64, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
return Result;
}
}
@@ -24390,7 +24415,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_121(N, X86::Int_CMPSDrr, MVT::v2f64);
+ SDNode *Result = Emit_123(N, X86::Int_CMPSDrr, MVT::v2f64);
return Result;
}
}
@@ -24403,7 +24428,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_121(N, X86::CMPPDrri, MVT::v2f64);
+ SDNode *Result = Emit_123(N, X86::CMPPDrri, MVT::v2f64);
return Result;
}
}
@@ -24422,7 +24447,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::ROUNDPDr_Int, MVT::v2f64);
+ SDNode *Result = Emit_128(N, X86::ROUNDPDr_Int, MVT::v2f64);
return Result;
}
}
@@ -24435,7 +24460,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_117(N, X86::ROUNDSDr_Int, MVT::v2f64);
+ SDNode *Result = Emit_119(N, X86::ROUNDSDr_Int, MVT::v2f64);
return Result;
}
}
@@ -24448,7 +24473,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_117(N, X86::BLENDPDrri, MVT::v2f64);
+ SDNode *Result = Emit_119(N, X86::BLENDPDrri, MVT::v2f64);
return Result;
}
}
@@ -24461,7 +24486,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue N2 = N.getOperand(2);
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_117(N, X86::DPPDrri, MVT::v2f64);
+ SDNode *Result = Emit_119(N, X86::DPPDrri, MVT::v2f64);
return Result;
}
}
@@ -24477,7 +24502,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (Int_CVTSI2SD64rr:v2f64 VR128:v2f64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(522)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SD64rr, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::Int_CVTSI2SD64rr, MVT::v2f64);
return Result;
}
@@ -24485,7 +24510,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (Int_CVTPI2PDrr:v2f64 VR64:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(689)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTPI2PDrr, MVT::v2f64);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPI2PDrr, MVT::v2f64);
return Result;
}
@@ -24493,7 +24518,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (ADDSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(502)) {
- SDNode *Result = Emit_109(N, X86::ADDSDrr_Int, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::ADDSDrr_Int, MVT::v2f64);
return Result;
}
@@ -24501,7 +24526,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (MULSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(542)) {
- SDNode *Result = Emit_109(N, X86::MULSDrr_Int, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::MULSDrr_Int, MVT::v2f64);
return Result;
}
@@ -24509,7 +24534,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (SUBSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(597)) {
- SDNode *Result = Emit_109(N, X86::SUBSDrr_Int, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::SUBSDrr_Int, MVT::v2f64);
return Result;
}
@@ -24517,7 +24542,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (DIVSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(528)) {
- SDNode *Result = Emit_109(N, X86::DIVSDrr_Int, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::DIVSDrr_Int, MVT::v2f64);
return Result;
}
@@ -24525,7 +24550,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (MAXSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(534)) {
- SDNode *Result = Emit_109(N, X86::MAXSDrr_Int, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::MAXSDrr_Int, MVT::v2f64);
return Result;
}
@@ -24533,7 +24558,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (MAXPDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(533)) {
- SDNode *Result = Emit_109(N, X86::MAXPDrr_Int, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::MAXPDrr_Int, MVT::v2f64);
return Result;
}
@@ -24541,7 +24566,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (MINSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(537)) {
- SDNode *Result = Emit_109(N, X86::MINSDrr_Int, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::MINSDrr_Int, MVT::v2f64);
return Result;
}
@@ -24549,7 +24574,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (MINPDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(536)) {
- SDNode *Result = Emit_109(N, X86::MINPDrr_Int, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::MINPDrr_Int, MVT::v2f64);
return Result;
}
@@ -24557,7 +24582,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (Int_CVTDQ2PDrr:v2f64 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(512)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTDQ2PDrr, MVT::v2f64);
+ SDNode *Result = Emit_108(N, X86::Int_CVTDQ2PDrr, MVT::v2f64);
return Result;
}
@@ -24565,7 +24590,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (Int_CVTPS2PDrr:v2f64 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(517)) {
- SDNode *Result = Emit_106(N, X86::Int_CVTPS2PDrr, MVT::v2f64);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPS2PDrr, MVT::v2f64);
return Result;
}
@@ -24573,7 +24598,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (Int_CVTSI2SDrr:v2f64 VR128:v2f64:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(521)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SDrr, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::Int_CVTSI2SDrr, MVT::v2f64);
return Result;
}
@@ -24581,7 +24606,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (Int_CVTSS2SDrr:v2f64 VR128:v2f64:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(523)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSS2SDrr, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::Int_CVTSS2SDrr, MVT::v2f64);
return Result;
}
@@ -24589,7 +24614,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (SQRTSDr_Int:v2f64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(593)) {
- SDNode *Result = Emit_106(N, X86::SQRTSDr_Int, MVT::v2f64);
+ SDNode *Result = Emit_108(N, X86::SQRTSDr_Int, MVT::v2f64);
return Result;
}
@@ -24597,7 +24622,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (SQRTPDr_Int:v2f64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(592)) {
- SDNode *Result = Emit_106(N, X86::SQRTPDr_Int, MVT::v2f64);
+ SDNode *Result = Emit_108(N, X86::SQRTPDr_Int, MVT::v2f64);
return Result;
}
}
@@ -24612,7 +24637,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (ADDSUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(604)) {
- SDNode *Result = Emit_109(N, X86::ADDSUBPDrr, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::ADDSUBPDrr, MVT::v2f64);
return Result;
}
@@ -24620,7 +24645,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (HADDPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(606)) {
- SDNode *Result = Emit_109(N, X86::HADDPDrr, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::HADDPDrr, MVT::v2f64);
return Result;
}
@@ -24628,7 +24653,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
// Emits: (HSUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(608)) {
- SDNode *Result = Emit_109(N, X86::HSUBPDrr, MVT::v2f64);
+ SDNode *Result = Emit_111(N, X86::HSUBPDrr, MVT::v2f64);
return Result;
}
}
@@ -24643,7 +24668,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(615)) {
- SDNode *Result = Emit_119(N, X86::BLENDVPDrr0, MVT::v2f64);
+ SDNode *Result = Emit_121(N, X86::BLENDVPDrr0, MVT::v2f64);
return Result;
}
}
@@ -24653,7 +24678,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_138(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_140(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -24679,7 +24704,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_138(N, X86::MOVDQUrm_Int, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_140(N, X86::MOVDQUrm_Int, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -24703,7 +24728,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_138(N, X86::LDDQUrm, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_140(N, X86::LDDQUrm, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -24729,7 +24754,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_138(N, X86::MOVNTDQArm, MVT::v2i64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_140(N, X86::MOVNTDQArm, MVT::v2i64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -24755,7 +24780,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_138(N, X86::MOVUPSrm_Int, MVT::v4f32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_140(N, X86::MOVUPSrm_Int, MVT::v4f32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -24781,7 +24806,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_138(N, X86::MOVUPDrm_Int, MVT::v2f64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_140(N, X86::MOVUPDrm_Int, MVT::v2f64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -24792,7 +24817,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_139(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_141(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
@@ -24818,7 +24843,7 @@ SDNode *Select_ISD_LOAD_i8(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24835,7 +24860,7 @@ SDNode *Select_ISD_LOAD_i8(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24852,7 +24877,7 @@ SDNode *Select_ISD_LOAD_i8(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24877,7 +24902,7 @@ SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOV16rm, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOV16rm, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24894,7 +24919,7 @@ SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVSX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVSX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24911,7 +24936,7 @@ SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24927,7 +24952,7 @@ SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24945,7 +24970,7 @@ SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24961,7 +24986,7 @@ SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24988,7 +25013,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::GS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::GS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25004,7 +25029,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::FS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::FS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25021,7 +25046,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25038,7 +25063,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVSX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVSX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25054,7 +25079,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25072,7 +25097,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25088,7 +25113,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25104,7 +25129,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25122,7 +25147,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25138,7 +25163,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25154,7 +25179,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25172,7 +25197,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25189,7 +25214,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25206,7 +25231,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25216,7 +25241,7 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_140(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_142(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
@@ -25247,7 +25272,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOV64GSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOV64GSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25263,7 +25288,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOV64FSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOV64FSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25278,7 +25303,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOV64rm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOV64rm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25295,7 +25320,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVSX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVSX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25311,7 +25336,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25327,7 +25352,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVSX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVSX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25345,7 +25370,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25361,7 +25386,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25377,7 +25402,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25393,7 +25418,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25411,7 +25436,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25427,7 +25452,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25443,7 +25468,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25461,7 +25486,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25478,7 +25503,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25495,7 +25520,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25511,7 +25536,7 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOV32rm, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_142(N, X86::MOV32rm, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25539,7 +25564,7 @@ SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25560,7 +25585,7 @@ SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVSSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVSSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25576,7 +25601,7 @@ SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::FsMOVAPSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::FsMOVAPSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25587,6 +25612,19 @@ SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
return NULL;
}
+DISABLE_INLINE SDNode *Emit_143(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
+ SDValue Tmp1(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
+ Chain = SDValue(Tmp1.getNode(), 1);
+ MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
+ MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDNode *ResNode = CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp1);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
+ ReplaceUses(SDValue(N.getNode(), 1), Chain);
+ return ResNode;
+}
SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
if ((!Subtarget->hasSSE2())) {
SDValue Chain = N.getOperand(0);
@@ -25604,7 +25642,7 @@ SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25621,65 +25659,93 @@ SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::LD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::LD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
}
}
+
+ // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>
+ // Emits: (MOVSDrm:f64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode()) &&
+ Predicate_loadf64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_141(N, X86::MOVSDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
- // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>
- // Emits: (MOVSDrm:f64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_load(N.getNode()) &&
- Predicate_loadf64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVSDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
+ // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
+ // Emits: (CVTSS2SDrm:f64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if ((Subtarget->hasSSE2()) && (OptForSize)) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_extload(N.getNode()) &&
+ Predicate_extloadf32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_141(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
}
+ }
+ }
- // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
- // Emits: (CVTSS2SDrm:f64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extload(N.getNode()) &&
- Predicate_extloadf32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
+ // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
+ // Emits: (FsMOVAPDrm:f64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode()) &&
+ Predicate_alignedload(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_141(N, X86::FsMOVAPDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
}
+ }
+ }
- // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
- // Emits: (FsMOVAPDrm:f64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_load(N.getNode()) &&
- Predicate_alignedload(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::FsMOVAPDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
+ // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
+ // Emits: (CVTSS2SDrr:f64 (MOVSSrm:f32 addr:iPTR:$src))
+ // Pattern complexity = 22 cost = 2 size = 6
+ if ((Subtarget->hasSSE2()) && (!OptForSize)) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_extload(N.getNode()) &&
+ Predicate_extloadf32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_143(N, X86::MOVSSrm, X86::CVTSS2SDrr, MVT::f32, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
}
}
}
@@ -25704,7 +25770,7 @@ SDNode *Select_ISD_LOAD_f80(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25721,7 +25787,7 @@ SDNode *Select_ISD_LOAD_f80(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::LD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::LD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25737,7 +25803,7 @@ SDNode *Select_ISD_LOAD_f80(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::LD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::LD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25765,7 +25831,7 @@ SDNode *Select_ISD_LOAD_v4i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVAPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVAPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25780,7 +25846,7 @@ SDNode *Select_ISD_LOAD_v4i32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVUPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVUPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25802,7 +25868,7 @@ SDNode *Select_ISD_LOAD_v1i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MMX_MOVQ64rm, MVT::v1i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MMX_MOVQ64rm, MVT::v1i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25829,7 +25895,7 @@ SDNode *Select_ISD_LOAD_v2i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVAPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVAPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25844,7 +25910,7 @@ SDNode *Select_ISD_LOAD_v2i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVUPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVUPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25871,7 +25937,7 @@ SDNode *Select_ISD_LOAD_v4f32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVAPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVAPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25886,7 +25952,7 @@ SDNode *Select_ISD_LOAD_v4f32(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVUPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVUPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25913,7 +25979,7 @@ SDNode *Select_ISD_LOAD_v2f64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVAPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVAPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25928,7 +25994,7 @@ SDNode *Select_ISD_LOAD_v2f64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_139(N, X86::MOVUPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOVUPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25938,7 +26004,7 @@ SDNode *Select_ISD_LOAD_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_141(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_144(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -25980,7 +26046,7 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
int64_t CN9 = Tmp8->getSExtValue();
if (CN9 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_141(N, X86::SFENCE);
+ SDNode *Result = Emit_144(N, X86::SFENCE);
return Result;
}
}
@@ -26017,7 +26083,7 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
int64_t CN9 = Tmp8->getSExtValue();
if (CN9 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_141(N, X86::LFENCE);
+ SDNode *Result = Emit_144(N, X86::LFENCE);
return Result;
}
}
@@ -26047,7 +26113,7 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
// Pattern complexity = 20 cost = 1 size = 3
if (CN1 == INT64_C(0) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_141(N, X86::NOOP);
+ SDNode *Result = Emit_144(N, X86::NOOP);
return Result;
}
@@ -26056,7 +26122,7 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
// Pattern complexity = 20 cost = 1 size = 3
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_141(N, X86::MFENCE);
+ SDNode *Result = Emit_144(N, X86::MFENCE);
return Result;
}
}
@@ -26069,7 +26135,7 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_142(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_145(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
@@ -26079,7 +26145,7 @@ DISABLE_INLINE SDNode *Emit_142(const SDValue &N, unsigned Opc0) {
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i8, MVT::i32, N1, InFlag);
}
-DISABLE_INLINE SDNode *Emit_143(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_146(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -26118,7 +26184,7 @@ SDNode *Select_ISD_MUL_i8(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_143(N, X86::MUL8m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_146(N, X86::MUL8m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -26128,11 +26194,11 @@ SDNode *Select_ISD_MUL_i8(const SDValue &N) {
// Pattern: (mul:i8 AL:i8, GR8:i8:$src)
// Emits: (MUL8r:isVoid GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_142(N, X86::MUL8r);
+ SDNode *Result = Emit_145(N, X86::MUL8r);
return Result;
}
-DISABLE_INLINE SDNode *Emit_144(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_147(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -26169,14 +26235,14 @@ SDNode *Select_ISD_MUL_i16(const SDValue &N) {
// Emits: (IMUL16rmi8:i16 addr:iPTR:$src1, (imm:i16):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_144(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_147(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (mul:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16):$src2)
// Emits: (IMUL16rmi:i16 addr:iPTR:$src1, (imm:i16):$src2)
// Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_144(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_147(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -26258,7 +26324,7 @@ SDNode *Select_ISD_MUL_i16(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_145(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_148(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -26295,14 +26361,14 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Emits: (IMUL32rmi8:i32 addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_145(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_148(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (mul:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$src2)
// Emits: (IMUL32rmi:i32 addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_145(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_148(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -26412,7 +26478,7 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_146(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_149(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -26449,7 +26515,7 @@ SDNode *Select_ISD_MUL_i64(const SDValue &N) {
// Emits: (IMUL64rmi8:i64 addr:iPTR:$src1, (imm:i64):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_146(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_149(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -26457,7 +26523,7 @@ SDNode *Select_ISD_MUL_i64(const SDValue &N) {
// Emits: (IMUL64rmi32:i64 addr:iPTR:$src1, (imm:i64):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_146(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_149(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -26852,7 +26918,7 @@ SDNode *Select_ISD_OR_i8(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_147(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_150(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -26868,7 +26934,7 @@ DISABLE_INLINE SDNode *Emit_147(const SDValue &N, unsigned Opc0, MVT::SimpleValu
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
}
-DISABLE_INLINE SDNode *Emit_148(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_151(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -26886,7 +26952,7 @@ DISABLE_INLINE SDNode *Emit_148(const SDValue &N, unsigned Opc0, MVT::SimpleValu
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
}
-DISABLE_INLINE SDNode *Emit_149(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_152(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -26896,7 +26962,7 @@ DISABLE_INLINE SDNode *Emit_149(const SDValue &N, unsigned Opc0, MVT::SimpleValu
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_150(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_153(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -26912,7 +26978,7 @@ DISABLE_INLINE SDNode *Emit_150(const SDValue &N, unsigned Opc0, MVT::SimpleValu
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, InFlag);
}
-DISABLE_INLINE SDNode *Emit_151(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_154(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -26930,7 +26996,7 @@ DISABLE_INLINE SDNode *Emit_151(const SDValue &N, unsigned Opc0, MVT::SimpleValu
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, InFlag);
}
-DISABLE_INLINE SDNode *Emit_152(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_155(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -27020,7 +27086,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
N010.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_148(N, X86::SHRD16rrCL, MVT::i16);
+ SDNode *Result = Emit_151(N, X86::SHRD16rrCL, MVT::i16);
return Result;
}
}
@@ -27058,7 +27124,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
N010.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_148(N, X86::SHLD16rrCL, MVT::i16);
+ SDNode *Result = Emit_151(N, X86::SHLD16rrCL, MVT::i16);
return Result;
}
}
@@ -27089,7 +27155,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
N010.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_151(N, X86::SHRD16rrCL, MVT::i16);
+ SDNode *Result = Emit_154(N, X86::SHRD16rrCL, MVT::i16);
return Result;
}
}
@@ -27126,7 +27192,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
N010.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_151(N, X86::SHLD16rrCL, MVT::i16);
+ SDNode *Result = Emit_154(N, X86::SHLD16rrCL, MVT::i16);
return Result;
}
}
@@ -27153,7 +27219,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
if (N01 == N111 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_147(N, X86::SHRD16rrCL, MVT::i16);
+ SDNode *Result = Emit_150(N, X86::SHRD16rrCL, MVT::i16);
return Result;
}
}
@@ -27183,7 +27249,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
if (N01 == N111 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_147(N, X86::SHLD16rrCL, MVT::i16);
+ SDNode *Result = Emit_150(N, X86::SHLD16rrCL, MVT::i16);
return Result;
}
}
@@ -27209,7 +27275,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
if (N011 == N11 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHRD16rrCL, MVT::i16);
+ SDNode *Result = Emit_153(N, X86::SHRD16rrCL, MVT::i16);
return Result;
}
}
@@ -27238,7 +27304,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
if (N011 == N11 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHLD16rrCL, MVT::i16);
+ SDNode *Result = Emit_153(N, X86::SHLD16rrCL, MVT::i16);
return Result;
}
}
@@ -27264,7 +27330,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_149(N, X86::SHRD16rri8, MVT::i16);
+ SDNode *Result = Emit_152(N, X86::SHRD16rri8, MVT::i16);
return Result;
}
}
@@ -27288,7 +27354,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_149(N, X86::SHLD16rri8, MVT::i16);
+ SDNode *Result = Emit_152(N, X86::SHLD16rri8, MVT::i16);
return Result;
}
}
@@ -27312,7 +27378,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHRD16rri8, MVT::i16);
+ SDNode *Result = Emit_155(N, X86::SHRD16rri8, MVT::i16);
return Result;
}
}
@@ -27336,7 +27402,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHLD16rri8, MVT::i16);
+ SDNode *Result = Emit_155(N, X86::SHLD16rri8, MVT::i16);
return Result;
}
}
@@ -27371,7 +27437,7 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_153(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_156(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -27389,7 +27455,7 @@ DISABLE_INLINE SDNode *Emit_153(const SDValue &N, unsigned Opc0, MVT::SimpleValu
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
}
-DISABLE_INLINE SDNode *Emit_154(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_157(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -27487,7 +27553,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
N010.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_153(N, X86::SHRD32rrCL, MVT::i32);
+ SDNode *Result = Emit_156(N, X86::SHRD32rrCL, MVT::i32);
return Result;
}
}
@@ -27525,7 +27591,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
N010.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_153(N, X86::SHLD32rrCL, MVT::i32);
+ SDNode *Result = Emit_156(N, X86::SHLD32rrCL, MVT::i32);
return Result;
}
}
@@ -27556,7 +27622,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
N010.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_154(N, X86::SHRD32rrCL, MVT::i32);
+ SDNode *Result = Emit_157(N, X86::SHRD32rrCL, MVT::i32);
return Result;
}
}
@@ -27593,7 +27659,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
N010.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_154(N, X86::SHLD32rrCL, MVT::i32);
+ SDNode *Result = Emit_157(N, X86::SHLD32rrCL, MVT::i32);
return Result;
}
}
@@ -27620,7 +27686,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
if (N01 == N111 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_147(N, X86::SHRD32rrCL, MVT::i32);
+ SDNode *Result = Emit_150(N, X86::SHRD32rrCL, MVT::i32);
return Result;
}
}
@@ -27650,7 +27716,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
if (N01 == N111 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_147(N, X86::SHLD32rrCL, MVT::i32);
+ SDNode *Result = Emit_150(N, X86::SHLD32rrCL, MVT::i32);
return Result;
}
}
@@ -27676,7 +27742,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
if (N011 == N11 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHRD32rrCL, MVT::i32);
+ SDNode *Result = Emit_153(N, X86::SHRD32rrCL, MVT::i32);
return Result;
}
}
@@ -27705,7 +27771,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
if (N011 == N11 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHLD32rrCL, MVT::i32);
+ SDNode *Result = Emit_153(N, X86::SHLD32rrCL, MVT::i32);
return Result;
}
}
@@ -27731,7 +27797,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_149(N, X86::SHRD32rri8, MVT::i32);
+ SDNode *Result = Emit_152(N, X86::SHRD32rri8, MVT::i32);
return Result;
}
}
@@ -27755,7 +27821,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_149(N, X86::SHLD32rri8, MVT::i32);
+ SDNode *Result = Emit_152(N, X86::SHLD32rri8, MVT::i32);
return Result;
}
}
@@ -27779,7 +27845,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHRD32rri8, MVT::i32);
+ SDNode *Result = Emit_155(N, X86::SHRD32rri8, MVT::i32);
return Result;
}
}
@@ -27803,7 +27869,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHLD32rri8, MVT::i32);
+ SDNode *Result = Emit_155(N, X86::SHLD32rri8, MVT::i32);
return Result;
}
}
@@ -27866,7 +27932,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_155(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_158(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -27884,7 +27950,7 @@ DISABLE_INLINE SDNode *Emit_155(const SDValue &N, unsigned Opc0, MVT::SimpleValu
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
}
-DISABLE_INLINE SDNode *Emit_156(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_159(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -27982,7 +28048,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
N010.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_155(N, X86::SHRD64rrCL, MVT::i64);
+ SDNode *Result = Emit_158(N, X86::SHRD64rrCL, MVT::i64);
return Result;
}
}
@@ -28020,7 +28086,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
N010.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_155(N, X86::SHLD64rrCL, MVT::i64);
+ SDNode *Result = Emit_158(N, X86::SHLD64rrCL, MVT::i64);
return Result;
}
}
@@ -28051,7 +28117,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
N010.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_156(N, X86::SHRD64rrCL, MVT::i64);
+ SDNode *Result = Emit_159(N, X86::SHRD64rrCL, MVT::i64);
return Result;
}
}
@@ -28088,7 +28154,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
N010.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_156(N, X86::SHLD64rrCL, MVT::i64);
+ SDNode *Result = Emit_159(N, X86::SHLD64rrCL, MVT::i64);
return Result;
}
}
@@ -28115,7 +28181,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
if (N01 == N111 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_147(N, X86::SHRD64rrCL, MVT::i64);
+ SDNode *Result = Emit_150(N, X86::SHRD64rrCL, MVT::i64);
return Result;
}
}
@@ -28145,7 +28211,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
if (N01 == N111 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_147(N, X86::SHLD64rrCL, MVT::i64);
+ SDNode *Result = Emit_150(N, X86::SHLD64rrCL, MVT::i64);
return Result;
}
}
@@ -28171,7 +28237,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
if (N011 == N11 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHRD64rrCL, MVT::i64);
+ SDNode *Result = Emit_153(N, X86::SHRD64rrCL, MVT::i64);
return Result;
}
}
@@ -28200,7 +28266,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
if (N011 == N11 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHLD64rrCL, MVT::i64);
+ SDNode *Result = Emit_153(N, X86::SHLD64rrCL, MVT::i64);
return Result;
}
}
@@ -28226,7 +28292,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_149(N, X86::SHRD64rri8, MVT::i64);
+ SDNode *Result = Emit_152(N, X86::SHRD64rri8, MVT::i64);
return Result;
}
}
@@ -28250,7 +28316,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_149(N, X86::SHLD64rri8, MVT::i64);
+ SDNode *Result = Emit_152(N, X86::SHLD64rri8, MVT::i64);
return Result;
}
}
@@ -28274,7 +28340,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHRD64rri8, MVT::i64);
+ SDNode *Result = Emit_155(N, X86::SHRD64rri8, MVT::i64);
return Result;
}
}
@@ -28298,7 +28364,7 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
if (N11.getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHLD64rri8, MVT::i64);
+ SDNode *Result = Emit_155(N, X86::SHLD64rri8, MVT::i64);
return Result;
}
}
@@ -28632,7 +28698,7 @@ SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_157(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_160(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -28662,7 +28728,7 @@ SDNode *Select_ISD_PREFETCH(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (CN1 == INT64_C(3) &&
N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_157(N, X86::PREFETCHT0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_160(N, X86::PREFETCHT0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -28671,7 +28737,7 @@ SDNode *Select_ISD_PREFETCH(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (CN1 == INT64_C(2) &&
N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_157(N, X86::PREFETCHT1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_160(N, X86::PREFETCHT1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -28680,7 +28746,7 @@ SDNode *Select_ISD_PREFETCH(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (CN1 == INT64_C(1) &&
N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_157(N, X86::PREFETCHT2, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_160(N, X86::PREFETCHT2, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -28689,7 +28755,7 @@ SDNode *Select_ISD_PREFETCH(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (CN1 == INT64_C(0) &&
N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_157(N, X86::PREFETCHNTA, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_160(N, X86::PREFETCHNTA, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -28701,7 +28767,7 @@ SDNode *Select_ISD_PREFETCH(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_158(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_161(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
@@ -28711,7 +28777,7 @@ DISABLE_INLINE SDNode *Emit_158(const SDValue &N, unsigned Opc0, MVT::SimpleValu
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, InFlag);
}
-DISABLE_INLINE SDNode *Emit_159(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_162(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
@@ -28730,7 +28796,7 @@ SDNode *Select_ISD_ROTL_i8(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::ROL8r1, MVT::i8);
+ SDNode *Result = Emit_94(N, X86::ROL8r1, MVT::i8);
return Result;
}
}
@@ -28741,7 +28807,7 @@ SDNode *Select_ISD_ROTL_i8(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROL8ri, MVT::i8);
+ SDNode *Result = Emit_162(N, X86::ROL8ri, MVT::i8);
return Result;
}
@@ -28749,7 +28815,7 @@ SDNode *Select_ISD_ROTL_i8(const SDValue &N) {
// Emits: (ROL8rCL:i8 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROL8rCL, MVT::i8);
+ SDNode *Result = Emit_161(N, X86::ROL8rCL, MVT::i8);
return Result;
}
@@ -28770,7 +28836,7 @@ SDNode *Select_ISD_ROTL_i16(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::ROL16r1, MVT::i16);
+ SDNode *Result = Emit_94(N, X86::ROL16r1, MVT::i16);
return Result;
}
}
@@ -28781,7 +28847,7 @@ SDNode *Select_ISD_ROTL_i16(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROL16ri, MVT::i16);
+ SDNode *Result = Emit_162(N, X86::ROL16ri, MVT::i16);
return Result;
}
@@ -28789,7 +28855,7 @@ SDNode *Select_ISD_ROTL_i16(const SDValue &N) {
// Emits: (ROL16rCL:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROL16rCL, MVT::i16);
+ SDNode *Result = Emit_161(N, X86::ROL16rCL, MVT::i16);
return Result;
}
@@ -28810,7 +28876,7 @@ SDNode *Select_ISD_ROTL_i32(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::ROL32r1, MVT::i32);
+ SDNode *Result = Emit_94(N, X86::ROL32r1, MVT::i32);
return Result;
}
}
@@ -28821,7 +28887,7 @@ SDNode *Select_ISD_ROTL_i32(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROL32ri, MVT::i32);
+ SDNode *Result = Emit_162(N, X86::ROL32ri, MVT::i32);
return Result;
}
@@ -28829,7 +28895,7 @@ SDNode *Select_ISD_ROTL_i32(const SDValue &N) {
// Emits: (ROL32rCL:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROL32rCL, MVT::i32);
+ SDNode *Result = Emit_161(N, X86::ROL32rCL, MVT::i32);
return Result;
}
@@ -28850,7 +28916,7 @@ SDNode *Select_ISD_ROTL_i64(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::ROL64r1, MVT::i64);
+ SDNode *Result = Emit_94(N, X86::ROL64r1, MVT::i64);
return Result;
}
}
@@ -28861,7 +28927,7 @@ SDNode *Select_ISD_ROTL_i64(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROL64ri, MVT::i64);
+ SDNode *Result = Emit_162(N, X86::ROL64ri, MVT::i64);
return Result;
}
@@ -28869,7 +28935,7 @@ SDNode *Select_ISD_ROTL_i64(const SDValue &N) {
// Emits: (ROL64rCL:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROL64rCL, MVT::i64);
+ SDNode *Result = Emit_161(N, X86::ROL64rCL, MVT::i64);
return Result;
}
@@ -28890,7 +28956,7 @@ SDNode *Select_ISD_ROTR_i8(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::ROR8r1, MVT::i8);
+ SDNode *Result = Emit_94(N, X86::ROR8r1, MVT::i8);
return Result;
}
}
@@ -28901,7 +28967,7 @@ SDNode *Select_ISD_ROTR_i8(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROR8ri, MVT::i8);
+ SDNode *Result = Emit_162(N, X86::ROR8ri, MVT::i8);
return Result;
}
@@ -28909,7 +28975,7 @@ SDNode *Select_ISD_ROTR_i8(const SDValue &N) {
// Emits: (ROR8rCL:i8 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROR8rCL, MVT::i8);
+ SDNode *Result = Emit_161(N, X86::ROR8rCL, MVT::i8);
return Result;
}
@@ -28930,7 +28996,7 @@ SDNode *Select_ISD_ROTR_i16(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::ROR16r1, MVT::i16);
+ SDNode *Result = Emit_94(N, X86::ROR16r1, MVT::i16);
return Result;
}
}
@@ -28941,7 +29007,7 @@ SDNode *Select_ISD_ROTR_i16(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROR16ri, MVT::i16);
+ SDNode *Result = Emit_162(N, X86::ROR16ri, MVT::i16);
return Result;
}
@@ -28949,7 +29015,7 @@ SDNode *Select_ISD_ROTR_i16(const SDValue &N) {
// Emits: (ROR16rCL:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROR16rCL, MVT::i16);
+ SDNode *Result = Emit_161(N, X86::ROR16rCL, MVT::i16);
return Result;
}
@@ -28970,7 +29036,7 @@ SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::ROR32r1, MVT::i32);
+ SDNode *Result = Emit_94(N, X86::ROR32r1, MVT::i32);
return Result;
}
}
@@ -28981,7 +29047,7 @@ SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROR32ri, MVT::i32);
+ SDNode *Result = Emit_162(N, X86::ROR32ri, MVT::i32);
return Result;
}
@@ -28989,7 +29055,7 @@ SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
// Emits: (ROR32rCL:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROR32rCL, MVT::i32);
+ SDNode *Result = Emit_161(N, X86::ROR32rCL, MVT::i32);
return Result;
}
@@ -29010,7 +29076,7 @@ SDNode *Select_ISD_ROTR_i64(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::ROR64r1, MVT::i64);
+ SDNode *Result = Emit_94(N, X86::ROR64r1, MVT::i64);
return Result;
}
}
@@ -29021,7 +29087,7 @@ SDNode *Select_ISD_ROTR_i64(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROR64ri, MVT::i64);
+ SDNode *Result = Emit_162(N, X86::ROR64ri, MVT::i64);
return Result;
}
@@ -29029,7 +29095,7 @@ SDNode *Select_ISD_ROTR_i64(const SDValue &N) {
// Emits: (ROR64rCL:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROR64rCL, MVT::i64);
+ SDNode *Result = Emit_161(N, X86::ROR64rCL, MVT::i64);
return Result;
}
@@ -29058,7 +29124,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_77(N, X86::MMX_MOVD64rm, MVT::v2i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MMX_MOVD64rm, MVT::v2i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29101,7 +29167,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_77(N, X86::MOVDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MOVDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29136,7 +29202,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v1i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_160(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_163(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00);
@@ -29163,7 +29229,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_77(N, X86::MOVQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MOVQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29179,7 +29245,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
// Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
// Pattern complexity = 6 cost = 1 size = 3
if (N00.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ SDNode *Result = Emit_163(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
return Result;
}
@@ -29187,7 +29253,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
// Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
// Pattern complexity = 6 cost = 1 size = 3
if (N00.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ SDNode *Result = Emit_163(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
return Result;
}
@@ -29195,7 +29261,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
// Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
// Pattern complexity = 6 cost = 1 size = 3
if (N00.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ SDNode *Result = Emit_163(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
return Result;
}
@@ -29203,7 +29269,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
// Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
// Pattern complexity = 6 cost = 1 size = 3
if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ SDNode *Result = Emit_163(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
return Result;
}
}
@@ -29247,7 +29313,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_77(N, X86::MOVSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MOVSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29291,7 +29357,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_77(N, X86::MOVSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MOVSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29313,12 +29379,12 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_161(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_164(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N0);
}
-DISABLE_INLINE SDNode *Emit_162(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_165(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -29344,7 +29410,7 @@ SDNode *Select_ISD_SHL_i8(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL8rCL, MVT::i8);
+ SDNode *Result = Emit_165(N, X86::SHL8rCL, MVT::i8);
return Result;
}
}
@@ -29358,7 +29424,7 @@ SDNode *Select_ISD_SHL_i8(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ADD8rr, MVT::i8);
+ SDNode *Result = Emit_164(N, X86::ADD8rr, MVT::i8);
return Result;
}
}
@@ -29369,7 +29435,7 @@ SDNode *Select_ISD_SHL_i8(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHL8ri, MVT::i8);
+ SDNode *Result = Emit_162(N, X86::SHL8ri, MVT::i8);
return Result;
}
@@ -29377,7 +29443,7 @@ SDNode *Select_ISD_SHL_i8(const SDValue &N) {
// Emits: (SHL8rCL:i8 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHL8rCL, MVT::i8);
+ SDNode *Result = Emit_161(N, X86::SHL8rCL, MVT::i8);
return Result;
}
@@ -29399,7 +29465,7 @@ SDNode *Select_ISD_SHL_i16(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL16rCL, MVT::i16);
+ SDNode *Result = Emit_165(N, X86::SHL16rCL, MVT::i16);
return Result;
}
}
@@ -29413,7 +29479,7 @@ SDNode *Select_ISD_SHL_i16(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ADD16rr, MVT::i16);
+ SDNode *Result = Emit_164(N, X86::ADD16rr, MVT::i16);
return Result;
}
}
@@ -29424,7 +29490,7 @@ SDNode *Select_ISD_SHL_i16(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHL16ri, MVT::i16);
+ SDNode *Result = Emit_162(N, X86::SHL16ri, MVT::i16);
return Result;
}
@@ -29432,7 +29498,7 @@ SDNode *Select_ISD_SHL_i16(const SDValue &N) {
// Emits: (SHL16rCL:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHL16rCL, MVT::i16);
+ SDNode *Result = Emit_161(N, X86::SHL16rCL, MVT::i16);
return Result;
}
@@ -29482,7 +29548,7 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL32rCL, MVT::i32);
+ SDNode *Result = Emit_165(N, X86::SHL32rCL, MVT::i32);
return Result;
}
}
@@ -29496,7 +29562,7 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ADD32rr, MVT::i32);
+ SDNode *Result = Emit_164(N, X86::ADD32rr, MVT::i32);
return Result;
}
}
@@ -29507,7 +29573,7 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHL32ri, MVT::i32);
+ SDNode *Result = Emit_162(N, X86::SHL32ri, MVT::i32);
return Result;
}
@@ -29515,7 +29581,7 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
// Emits: (SHL32rCL:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHL32rCL, MVT::i32);
+ SDNode *Result = Emit_161(N, X86::SHL32rCL, MVT::i32);
return Result;
}
@@ -29551,7 +29617,7 @@ SDNode *Select_ISD_SHL_i64(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(63)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL64rCL, MVT::i64);
+ SDNode *Result = Emit_165(N, X86::SHL64rCL, MVT::i64);
return Result;
}
}
@@ -29565,7 +29631,7 @@ SDNode *Select_ISD_SHL_i64(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ADD64rr, MVT::i64);
+ SDNode *Result = Emit_164(N, X86::ADD64rr, MVT::i64);
return Result;
}
}
@@ -29576,7 +29642,7 @@ SDNode *Select_ISD_SHL_i64(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHL64ri, MVT::i64);
+ SDNode *Result = Emit_162(N, X86::SHL64ri, MVT::i64);
return Result;
}
@@ -29584,7 +29650,7 @@ SDNode *Select_ISD_SHL_i64(const SDValue &N) {
// Emits: (SHL64rCL:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHL64rCL, MVT::i64);
+ SDNode *Result = Emit_161(N, X86::SHL64rCL, MVT::i64);
return Result;
}
@@ -29657,7 +29723,7 @@ SDNode *Select_ISD_SIGN_EXTEND_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_163(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+DISABLE_INLINE SDNode *Emit_166(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
@@ -29666,7 +29732,7 @@ DISABLE_INLINE SDNode *Emit_163(const SDValue &N, unsigned Opc0, unsigned Opc1,
SDValue Tmp4(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp2, Tmp3), 0);
return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp4);
}
-DISABLE_INLINE SDNode *Emit_164(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_167(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
@@ -29682,7 +29748,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i16(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i8, MVT::i16);
+ SDNode *Result = Emit_167(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i8, MVT::i16);
return Result;
}
}
@@ -29694,7 +29760,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i16(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_163(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i16, MVT::i8, MVT::i16);
+ SDNode *Result = Emit_166(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i16, MVT::i8, MVT::i16);
return Result;
}
}
@@ -29703,14 +29769,14 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_165(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_168(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_166(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+DISABLE_INLINE SDNode *Emit_169(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
@@ -29728,7 +29794,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
- SDNode *Result = Emit_165(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr16, MVT::i16, MVT::i32);
+ SDNode *Result = Emit_168(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr16, MVT::i16, MVT::i32);
return Result;
}
}
@@ -29740,7 +29806,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_167(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i8, MVT::i32);
return Result;
}
}
@@ -29752,7 +29818,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_166(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i32, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_169(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i32, MVT::i8, MVT::i32);
return Result;
}
}
@@ -29761,7 +29827,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_167(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_170(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
@@ -29776,7 +29842,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(const SDValue &N) {
// Emits: (MOVSX64rr32:i64 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32))
// Pattern complexity = 3 cost = 2 size = 3
if (cast<VTSDNode>(N1)->getVT() == MVT::i32) {
- SDNode *Result = Emit_167(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr32, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_170(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr32, MVT::i32, MVT::i64);
return Result;
}
@@ -29784,7 +29850,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(const SDValue &N) {
// Emits: (MOVSX64rr16:i64 (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
// Pattern complexity = 3 cost = 2 size = 3
if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
- SDNode *Result = Emit_165(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr16, MVT::i16, MVT::i64);
+ SDNode *Result = Emit_168(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr16, MVT::i16, MVT::i64);
return Result;
}
@@ -29792,7 +29858,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(const SDValue &N) {
// Emits: (MOVSX64rr8:i64 (EXTRACT_SUBREG:i8 GR64:i64:$src, 1:i32))
// Pattern complexity = 3 cost = 2 size = 3
if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr8, MVT::i8, MVT::i64);
+ SDNode *Result = Emit_167(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr8, MVT::i8, MVT::i64);
return Result;
}
@@ -29822,7 +29888,7 @@ SDNode *Select_ISD_SINT_TO_FP_f32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_77(N, X86::CVTSI2SS64rm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::CVTSI2SS64rm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29839,7 +29905,7 @@ SDNode *Select_ISD_SINT_TO_FP_f32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_77(N, X86::CVTSI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::CVTSI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29892,7 +29958,7 @@ SDNode *Select_ISD_SINT_TO_FP_f64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_77(N, X86::CVTSI2SD64rm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::CVTSI2SD64rm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29909,7 +29975,7 @@ SDNode *Select_ISD_SINT_TO_FP_f64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_77(N, X86::CVTSI2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::CVTSI2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29980,7 +30046,7 @@ SDNode *Select_ISD_SRA_i8(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR8rCL, MVT::i8);
+ SDNode *Result = Emit_165(N, X86::SAR8rCL, MVT::i8);
return Result;
}
}
@@ -29994,7 +30060,7 @@ SDNode *Select_ISD_SRA_i8(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::SAR8r1, MVT::i8);
+ SDNode *Result = Emit_94(N, X86::SAR8r1, MVT::i8);
return Result;
}
}
@@ -30005,7 +30071,7 @@ SDNode *Select_ISD_SRA_i8(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SAR8ri, MVT::i8);
+ SDNode *Result = Emit_162(N, X86::SAR8ri, MVT::i8);
return Result;
}
@@ -30013,7 +30079,7 @@ SDNode *Select_ISD_SRA_i8(const SDValue &N) {
// Emits: (SAR8rCL:i8 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SAR8rCL, MVT::i8);
+ SDNode *Result = Emit_161(N, X86::SAR8rCL, MVT::i8);
return Result;
}
@@ -30035,7 +30101,7 @@ SDNode *Select_ISD_SRA_i16(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR16rCL, MVT::i16);
+ SDNode *Result = Emit_165(N, X86::SAR16rCL, MVT::i16);
return Result;
}
}
@@ -30049,7 +30115,7 @@ SDNode *Select_ISD_SRA_i16(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::SAR16r1, MVT::i16);
+ SDNode *Result = Emit_94(N, X86::SAR16r1, MVT::i16);
return Result;
}
}
@@ -30060,7 +30126,7 @@ SDNode *Select_ISD_SRA_i16(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SAR16ri, MVT::i16);
+ SDNode *Result = Emit_162(N, X86::SAR16ri, MVT::i16);
return Result;
}
@@ -30068,7 +30134,7 @@ SDNode *Select_ISD_SRA_i16(const SDValue &N) {
// Emits: (SAR16rCL:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SAR16rCL, MVT::i16);
+ SDNode *Result = Emit_161(N, X86::SAR16rCL, MVT::i16);
return Result;
}
@@ -30090,7 +30156,7 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR32rCL, MVT::i32);
+ SDNode *Result = Emit_165(N, X86::SAR32rCL, MVT::i32);
return Result;
}
}
@@ -30104,7 +30170,7 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::SAR32r1, MVT::i32);
+ SDNode *Result = Emit_94(N, X86::SAR32r1, MVT::i32);
return Result;
}
}
@@ -30115,7 +30181,7 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SAR32ri, MVT::i32);
+ SDNode *Result = Emit_162(N, X86::SAR32ri, MVT::i32);
return Result;
}
@@ -30123,7 +30189,7 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (SAR32rCL:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SAR32rCL, MVT::i32);
+ SDNode *Result = Emit_161(N, X86::SAR32rCL, MVT::i32);
return Result;
}
@@ -30145,7 +30211,7 @@ SDNode *Select_ISD_SRA_i64(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(63)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR64rCL, MVT::i64);
+ SDNode *Result = Emit_165(N, X86::SAR64rCL, MVT::i64);
return Result;
}
}
@@ -30159,7 +30225,7 @@ SDNode *Select_ISD_SRA_i64(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::SAR64r1, MVT::i64);
+ SDNode *Result = Emit_94(N, X86::SAR64r1, MVT::i64);
return Result;
}
}
@@ -30170,7 +30236,7 @@ SDNode *Select_ISD_SRA_i64(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SAR64ri, MVT::i64);
+ SDNode *Result = Emit_162(N, X86::SAR64ri, MVT::i64);
return Result;
}
@@ -30178,7 +30244,7 @@ SDNode *Select_ISD_SRA_i64(const SDValue &N) {
// Emits: (SAR64rCL:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SAR64rCL, MVT::i64);
+ SDNode *Result = Emit_161(N, X86::SAR64rCL, MVT::i64);
return Result;
}
@@ -30200,7 +30266,7 @@ SDNode *Select_ISD_SRL_i8(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR8rCL, MVT::i8);
+ SDNode *Result = Emit_165(N, X86::SHR8rCL, MVT::i8);
return Result;
}
}
@@ -30214,7 +30280,7 @@ SDNode *Select_ISD_SRL_i8(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::SHR8r1, MVT::i8);
+ SDNode *Result = Emit_94(N, X86::SHR8r1, MVT::i8);
return Result;
}
}
@@ -30225,7 +30291,7 @@ SDNode *Select_ISD_SRL_i8(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHR8ri, MVT::i8);
+ SDNode *Result = Emit_162(N, X86::SHR8ri, MVT::i8);
return Result;
}
@@ -30233,7 +30299,7 @@ SDNode *Select_ISD_SRL_i8(const SDValue &N) {
// Emits: (SHR8rCL:i8 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHR8rCL, MVT::i8);
+ SDNode *Result = Emit_161(N, X86::SHR8rCL, MVT::i8);
return Result;
}
@@ -30241,7 +30307,7 @@ SDNode *Select_ISD_SRL_i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_168(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
+DISABLE_INLINE SDNode *Emit_171(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
@@ -30267,7 +30333,7 @@ SDNode *Select_ISD_SRL_i16(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR16rCL, MVT::i16);
+ SDNode *Result = Emit_165(N, X86::SHR16rCL, MVT::i16);
return Result;
}
}
@@ -30285,7 +30351,7 @@ SDNode *Select_ISD_SRL_i16(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_168(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
+ SDNode *Result = Emit_171(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
return Result;
}
}
@@ -30303,7 +30369,7 @@ SDNode *Select_ISD_SRL_i16(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_168(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
+ SDNode *Result = Emit_171(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
return Result;
}
}
@@ -30320,7 +30386,7 @@ SDNode *Select_ISD_SRL_i16(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::SHR16r1, MVT::i16);
+ SDNode *Result = Emit_94(N, X86::SHR16r1, MVT::i16);
return Result;
}
}
@@ -30331,7 +30397,7 @@ SDNode *Select_ISD_SRL_i16(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHR16ri, MVT::i16);
+ SDNode *Result = Emit_162(N, X86::SHR16ri, MVT::i16);
return Result;
}
@@ -30339,7 +30405,7 @@ SDNode *Select_ISD_SRL_i16(const SDValue &N) {
// Emits: (SHR16rCL:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHR16rCL, MVT::i16);
+ SDNode *Result = Emit_161(N, X86::SHR16rCL, MVT::i16);
return Result;
}
@@ -30361,7 +30427,7 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR32rCL, MVT::i32);
+ SDNode *Result = Emit_165(N, X86::SHR32rCL, MVT::i32);
return Result;
}
}
@@ -30375,7 +30441,7 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::SHR32r1, MVT::i32);
+ SDNode *Result = Emit_94(N, X86::SHR32r1, MVT::i32);
return Result;
}
}
@@ -30386,7 +30452,7 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHR32ri, MVT::i32);
+ SDNode *Result = Emit_162(N, X86::SHR32ri, MVT::i32);
return Result;
}
@@ -30394,7 +30460,7 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
// Emits: (SHR32rCL:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHR32rCL, MVT::i32);
+ SDNode *Result = Emit_161(N, X86::SHR32rCL, MVT::i32);
return Result;
}
@@ -30416,7 +30482,7 @@ SDNode *Select_ISD_SRL_i64(const SDValue &N) {
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(63)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR64rCL, MVT::i64);
+ SDNode *Result = Emit_165(N, X86::SHR64rCL, MVT::i64);
return Result;
}
}
@@ -30430,7 +30496,7 @@ SDNode *Select_ISD_SRL_i64(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_92(N, X86::SHR64r1, MVT::i64);
+ SDNode *Result = Emit_94(N, X86::SHR64r1, MVT::i64);
return Result;
}
}
@@ -30441,7 +30507,7 @@ SDNode *Select_ISD_SRL_i64(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHR64ri, MVT::i64);
+ SDNode *Result = Emit_162(N, X86::SHR64ri, MVT::i64);
return Result;
}
@@ -30449,7 +30515,7 @@ SDNode *Select_ISD_SRL_i64(const SDValue &N) {
// Emits: (SHR64rCL:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHR64rCL, MVT::i64);
+ SDNode *Result = Emit_161(N, X86::SHR64rCL, MVT::i64);
return Result;
}
@@ -30457,7 +30523,7 @@ SDNode *Select_ISD_SRL_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_169(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_172(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -30469,7 +30535,7 @@ DISABLE_INLINE SDNode *Emit_169(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_170(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_173(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -30481,7 +30547,7 @@ DISABLE_INLINE SDNode *Emit_170(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_171(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_174(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -30493,7 +30559,7 @@ DISABLE_INLINE SDNode *Emit_171(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_172(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_175(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -30504,7 +30570,7 @@ DISABLE_INLINE SDNode *Emit_172(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_173(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
+DISABLE_INLINE SDNode *Emit_176(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30536,7 +30602,7 @@ DISABLE_INLINE SDNode *Emit_173(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_174(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_177(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30568,7 +30634,7 @@ DISABLE_INLINE SDNode *Emit_174(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_175(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_178(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30600,7 +30666,7 @@ DISABLE_INLINE SDNode *Emit_175(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_176(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_179(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30632,7 +30698,7 @@ DISABLE_INLINE SDNode *Emit_176(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_177(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_180(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30665,7 +30731,7 @@ DISABLE_INLINE SDNode *Emit_177(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_178(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_181(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30698,7 +30764,7 @@ DISABLE_INLINE SDNode *Emit_178(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_179(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_182(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30731,7 +30797,7 @@ DISABLE_INLINE SDNode *Emit_179(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_180(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_183(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30767,7 +30833,7 @@ DISABLE_INLINE SDNode *Emit_180(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_181(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_184(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30800,7 +30866,7 @@ DISABLE_INLINE SDNode *Emit_181(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_182(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_185(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30837,7 +30903,7 @@ DISABLE_INLINE SDNode *Emit_182(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_183(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_186(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30871,7 +30937,7 @@ DISABLE_INLINE SDNode *Emit_183(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_184(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_187(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30907,7 +30973,7 @@ DISABLE_INLINE SDNode *Emit_184(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_185(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_188(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30944,7 +31010,7 @@ DISABLE_INLINE SDNode *Emit_185(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_186(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_189(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -30981,7 +31047,7 @@ DISABLE_INLINE SDNode *Emit_186(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_187(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_190(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31018,7 +31084,7 @@ DISABLE_INLINE SDNode *Emit_187(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_188(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_191(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31035,7 +31101,7 @@ DISABLE_INLINE SDNode *Emit_188(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_189(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_192(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -31047,7 +31113,7 @@ DISABLE_INLINE SDNode *Emit_189(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_190(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_193(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31080,7 +31146,7 @@ DISABLE_INLINE SDNode *Emit_190(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_191(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_194(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31117,7 +31183,7 @@ DISABLE_INLINE SDNode *Emit_191(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_192(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_195(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31129,7 +31195,7 @@ DISABLE_INLINE SDNode *Emit_192(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_193(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_196(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31143,7 +31209,7 @@ DISABLE_INLINE SDNode *Emit_193(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_194(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_197(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31157,7 +31223,7 @@ DISABLE_INLINE SDNode *Emit_194(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_195(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_198(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31173,7 +31239,7 @@ DISABLE_INLINE SDNode *Emit_195(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_196(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_199(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31186,7 +31252,7 @@ DISABLE_INLINE SDNode *Emit_196(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_197(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_200(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31201,7 +31267,7 @@ DISABLE_INLINE SDNode *Emit_197(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_198(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_201(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31216,7 +31282,7 @@ DISABLE_INLINE SDNode *Emit_198(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_199(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_202(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31249,7 +31315,7 @@ DISABLE_INLINE SDNode *Emit_199(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_200(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_203(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31282,7 +31348,7 @@ DISABLE_INLINE SDNode *Emit_200(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_201(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_204(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31320,7 +31386,7 @@ DISABLE_INLINE SDNode *Emit_201(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_202(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+DISABLE_INLINE SDNode *Emit_205(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31362,7 +31428,7 @@ DISABLE_INLINE SDNode *Emit_202(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_203(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+DISABLE_INLINE SDNode *Emit_206(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31406,7 +31472,7 @@ DISABLE_INLINE SDNode *Emit_203(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_204(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+DISABLE_INLINE SDNode *Emit_207(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31443,7 +31509,7 @@ DISABLE_INLINE SDNode *Emit_204(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_205(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+DISABLE_INLINE SDNode *Emit_208(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31487,7 +31553,7 @@ DISABLE_INLINE SDNode *Emit_205(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_206(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_209(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31518,7 +31584,7 @@ DISABLE_INLINE SDNode *Emit_206(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_207(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_210(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -31531,7 +31597,7 @@ DISABLE_INLINE SDNode *Emit_207(const SDValue &N, unsigned Opc0, unsigned Opc1,
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_208(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_211(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31564,7 +31630,7 @@ DISABLE_INLINE SDNode *Emit_208(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_209(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_212(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31597,7 +31663,7 @@ DISABLE_INLINE SDNode *Emit_209(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_210(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_213(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31615,7 +31681,7 @@ DISABLE_INLINE SDNode *Emit_210(const SDValue &N, unsigned Opc0, unsigned Opc1,
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_211(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_214(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31633,7 +31699,7 @@ DISABLE_INLINE SDNode *Emit_211(const SDValue &N, unsigned Opc0, unsigned Opc1,
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_212(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_215(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31651,7 +31717,7 @@ DISABLE_INLINE SDNode *Emit_212(const SDValue &N, unsigned Opc0, unsigned Opc1,
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_213(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+DISABLE_INLINE SDNode *Emit_216(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31695,7 +31761,7 @@ DISABLE_INLINE SDNode *Emit_213(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_214(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_217(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31727,7 +31793,7 @@ DISABLE_INLINE SDNode *Emit_214(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_215(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+DISABLE_INLINE SDNode *Emit_218(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31760,7 +31826,7 @@ DISABLE_INLINE SDNode *Emit_215(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_216(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_219(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31776,7 +31842,7 @@ DISABLE_INLINE SDNode *Emit_216(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_217(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
+DISABLE_INLINE SDNode *Emit_220(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31808,7 +31874,7 @@ DISABLE_INLINE SDNode *Emit_217(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_218(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
+DISABLE_INLINE SDNode *Emit_221(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31844,7 +31910,7 @@ DISABLE_INLINE SDNode *Emit_218(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_219(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+DISABLE_INLINE SDNode *Emit_222(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31886,7 +31952,7 @@ DISABLE_INLINE SDNode *Emit_219(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_220(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+DISABLE_INLINE SDNode *Emit_223(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31930,7 +31996,7 @@ DISABLE_INLINE SDNode *Emit_220(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_221(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+DISABLE_INLINE SDNode *Emit_224(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -31967,7 +32033,7 @@ DISABLE_INLINE SDNode *Emit_221(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_222(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+DISABLE_INLINE SDNode *Emit_225(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -32011,7 +32077,7 @@ DISABLE_INLINE SDNode *Emit_222(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_223(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+DISABLE_INLINE SDNode *Emit_226(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -32111,7 +32177,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i32 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_203(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_206(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32170,7 +32236,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i32 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_203(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_206(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32229,7 +32295,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i16 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_205(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_208(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32288,7 +32354,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i16 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_205(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_208(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32348,7 +32414,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i64 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_213(N, X86::SHRD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_216(N, X86::SHRD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32408,7 +32474,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i64 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_213(N, X86::SHLD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_216(N, X86::SHLD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32466,7 +32532,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i32 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_220(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_223(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -32525,7 +32591,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i32 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_220(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_223(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -32584,7 +32650,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i16 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_222(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_225(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -32643,7 +32709,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i16 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_222(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_225(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -32703,7 +32769,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i64 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_223(N, X86::SHRD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_226(N, X86::SHRD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -32764,7 +32830,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1010.getValueType() == MVT::i64 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_223(N, X86::SHLD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_226(N, X86::SHLD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -32816,7 +32882,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_205(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32868,7 +32934,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_205(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32919,7 +32985,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_205(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32970,7 +33036,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_205(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33022,7 +33088,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHRD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_205(N, X86::SHRD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33074,7 +33140,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHLD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_205(N, X86::SHLD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33124,7 +33190,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_219(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_222(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33175,7 +33241,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_219(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_222(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33226,7 +33292,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_219(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_222(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33277,7 +33343,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_219(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_222(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33329,7 +33395,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_219(N, X86::SHRD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_222(N, X86::SHRD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33381,7 +33447,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_219(N, X86::SHLD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_222(N, X86::SHLD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33429,7 +33495,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHRD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_207(N, X86::SHRD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33475,7 +33541,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHLD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_207(N, X86::SHLD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33521,7 +33587,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHRD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_207(N, X86::SHRD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33567,7 +33633,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHLD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_207(N, X86::SHLD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33614,7 +33680,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHRD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_207(N, X86::SHRD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33661,7 +33727,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHLD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_207(N, X86::SHLD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33707,7 +33773,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_221(N, X86::SHRD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_224(N, X86::SHRD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33753,7 +33819,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_221(N, X86::SHLD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_224(N, X86::SHLD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33799,7 +33865,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_221(N, X86::SHRD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_224(N, X86::SHRD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33845,7 +33911,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_221(N, X86::SHLD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_224(N, X86::SHLD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33892,7 +33958,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_221(N, X86::SHRD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_224(N, X86::SHRD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33939,7 +34005,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_221(N, X86::SHLD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_224(N, X86::SHLD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33984,7 +34050,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34014,7 +34080,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34044,7 +34110,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34087,7 +34153,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34117,7 +34183,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34147,7 +34213,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34190,7 +34256,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34220,7 +34286,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34250,7 +34316,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34293,7 +34359,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34335,7 +34401,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34377,7 +34443,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_204(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34416,7 +34482,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_173(N, X86::NEG8m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_176(N, X86::NEG8m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -34436,7 +34502,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_173(N, X86::NEG16m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_176(N, X86::NEG16m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -34456,7 +34522,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_173(N, X86::NEG32m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_176(N, X86::NEG32m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -34496,7 +34562,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_175(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34541,7 +34607,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34568,7 +34634,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34615,7 +34681,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_175(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34660,7 +34726,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34687,7 +34753,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34734,7 +34800,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_173(N, X86::NEG64m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_176(N, X86::NEG64m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -34773,7 +34839,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_175(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34785,7 +34851,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_175(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34830,7 +34896,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34857,7 +34923,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34884,7 +34950,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34911,7 +34977,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34959,7 +35025,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SHL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34987,7 +35053,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SHL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35015,7 +35081,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SHL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35056,7 +35122,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SHR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35084,7 +35150,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SHR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35112,7 +35178,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SHR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35153,7 +35219,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SAR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35181,7 +35247,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SAR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35209,7 +35275,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SAR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35250,7 +35316,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::ROL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35278,7 +35344,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::ROL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35306,7 +35372,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::ROL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35347,7 +35413,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::ROR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35375,7 +35441,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::ROR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35403,7 +35469,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::ROR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35444,7 +35510,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SHL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35484,7 +35550,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SHR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35524,7 +35590,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SAR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35564,7 +35630,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::ROL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35604,7 +35670,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::ROR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35642,7 +35708,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_199(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_202(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35669,7 +35735,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_200(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_203(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35697,7 +35763,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_208(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_211(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35709,7 +35775,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_209(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_212(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35747,7 +35813,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::NOT8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::NOT8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35771,7 +35837,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_174(N, X86::NOT16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::NOT16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35795,7 +35861,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_174(N, X86::NOT32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::NOT32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35831,7 +35897,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35843,7 +35909,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35879,7 +35945,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35891,7 +35957,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35927,7 +35993,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35939,7 +36005,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35975,7 +36041,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35987,7 +36053,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36023,7 +36089,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::ADC16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_189(N, X86::ADC16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36035,7 +36101,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::ADC32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::ADC32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36071,7 +36137,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36083,7 +36149,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36119,7 +36185,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::SBB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_189(N, X86::SBB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36131,7 +36197,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::SBB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::SBB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36167,7 +36233,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36179,7 +36245,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36216,14 +36282,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
// Pattern complexity = 51 cost = 1 size = 3
{
- SDNode *Result = Emit_191(N, X86::ADC64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_194(N, X86::ADC64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
// Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADC64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
// Pattern complexity = 51 cost = 1 size = 3
- SDNode *Result = Emit_191(N, X86::ADC64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_194(N, X86::ADC64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36258,7 +36324,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36270,7 +36336,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36306,7 +36372,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_191(N, X86::SBB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_194(N, X86::SBB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36318,7 +36384,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_191(N, X86::SBB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_194(N, X86::SBB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36355,7 +36421,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_174(N, X86::NOT64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::NOT64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36391,7 +36457,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36415,7 +36481,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36452,7 +36518,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36476,7 +36542,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36513,7 +36579,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36537,7 +36603,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36573,7 +36639,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36597,7 +36663,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36633,7 +36699,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36657,7 +36723,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36693,7 +36759,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36717,7 +36783,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36753,7 +36819,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36777,7 +36843,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36813,7 +36879,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36837,7 +36903,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36874,7 +36940,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36886,7 +36952,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36923,7 +36989,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36935,7 +37001,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36972,7 +37038,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36984,7 +37050,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37021,7 +37087,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37033,7 +37099,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37070,7 +37136,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37082,7 +37148,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_193(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37128,7 +37194,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N1001 == N2 &&
N1.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_215(N, X86::MOVLPSmr, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_218(N, X86::MOVLPSmr, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -37170,7 +37236,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37193,7 +37259,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37216,7 +37282,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37252,7 +37318,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37275,7 +37341,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37298,7 +37364,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37334,7 +37400,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37357,7 +37423,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37380,7 +37446,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37417,7 +37483,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SHL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37441,7 +37507,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SHL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37465,7 +37531,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SHL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37502,7 +37568,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SHR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37526,7 +37592,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SHR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37550,7 +37616,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SHR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37587,7 +37653,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SAR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37611,7 +37677,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SAR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37635,7 +37701,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SAR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37672,7 +37738,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ROL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37696,7 +37762,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ROL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37720,7 +37786,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ROL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37757,7 +37823,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ROR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37781,7 +37847,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ROR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37805,7 +37871,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ROR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37842,7 +37908,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHLD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_186(N, X86::SHLD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37878,7 +37944,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHRD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_186(N, X86::SHRD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37914,7 +37980,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHLD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_186(N, X86::SHLD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37950,7 +38016,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHRD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_186(N, X86::SHRD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37985,7 +38051,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38008,7 +38074,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38031,7 +38097,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38067,7 +38133,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::ADC8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_188(N, X86::ADC8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38090,7 +38156,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::ADC16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_189(N, X86::ADC16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38113,7 +38179,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::ADC32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::ADC32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38149,7 +38215,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38172,7 +38238,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38195,7 +38261,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38231,7 +38297,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::SBB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_188(N, X86::SBB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38254,7 +38320,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::SBB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_189(N, X86::SBB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38277,7 +38343,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::SBB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::SBB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38314,7 +38380,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SHL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38350,7 +38416,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SHR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38386,7 +38452,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SAR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38422,7 +38488,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ROL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38458,7 +38524,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ROR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38495,7 +38561,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHLD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_186(N, X86::SHLD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38532,7 +38598,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHRD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_186(N, X86::SHRD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38567,7 +38633,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38590,7 +38656,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38613,7 +38679,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38649,7 +38715,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38672,7 +38738,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38695,7 +38761,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38731,7 +38797,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38754,7 +38820,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38777,7 +38843,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38813,7 +38879,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38836,7 +38902,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38859,7 +38925,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38895,7 +38961,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38918,7 +38984,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38941,7 +39007,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38983,7 +39049,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_214(N, X86::MOVLPSmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_217(N, X86::MOVLPSmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39023,7 +39089,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
// Pattern complexity = 48 cost = 1 size = 3
if (N1.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_214(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_217(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39031,7 +39097,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
// Pattern complexity = 48 cost = 1 size = 3
if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_214(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_217(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39072,7 +39138,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N10.getValueType() == MVT::i8) {
- SDNode *Result = Emit_206(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39105,7 +39171,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N10.getValueType() == MVT::i8) {
- SDNode *Result = Emit_206(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39144,7 +39210,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39176,7 +39242,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39208,7 +39274,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39240,7 +39306,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39279,7 +39345,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39311,7 +39377,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39343,7 +39409,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39375,7 +39441,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39414,7 +39480,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N10.getValueType() == MVT::i64) {
- SDNode *Result = Emit_206(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39447,7 +39513,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N10.getValueType() == MVT::i64) {
- SDNode *Result = Emit_206(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39479,7 +39545,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39487,7 +39553,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39495,7 +39561,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39528,7 +39594,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39536,7 +39602,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39544,7 +39610,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39577,7 +39643,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39585,7 +39651,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39593,7 +39659,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39628,7 +39694,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39650,7 +39716,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39672,7 +39738,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39707,7 +39773,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39729,7 +39795,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39751,7 +39817,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39786,7 +39852,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39808,7 +39874,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39830,7 +39896,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39865,7 +39931,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::ROL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39887,7 +39953,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::ROL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39909,7 +39975,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::ROL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39944,7 +40010,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::ROR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39966,7 +40032,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::ROR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39988,7 +40054,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::ROR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40023,7 +40089,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHLD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_185(N, X86::SHLD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40057,7 +40123,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHRD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_185(N, X86::SHRD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40091,7 +40157,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHLD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_185(N, X86::SHLD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40125,7 +40191,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHRD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_185(N, X86::SHRD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40157,7 +40223,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40165,7 +40231,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40173,7 +40239,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40206,7 +40272,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::ADC8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::ADC8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40214,7 +40280,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_184(N, X86::ADC16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::ADC16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40222,7 +40288,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, X86::ADC32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::ADC32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40255,7 +40321,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40263,7 +40329,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40271,7 +40337,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40304,7 +40370,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SBB8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SBB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::SBB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40312,7 +40378,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SBB16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_184(N, X86::SBB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::SBB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40320,7 +40386,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SBB32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, X86::SBB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::SBB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40353,7 +40419,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40385,7 +40451,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_184(N, X86::ADC64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::ADC64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40417,7 +40483,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40449,7 +40515,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_184(N, X86::SBB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::SBB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40483,7 +40549,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40517,7 +40583,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40551,7 +40617,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40585,7 +40651,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::ROL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40619,7 +40685,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::ROR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40654,7 +40720,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHLD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_185(N, X86::SHLD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40689,7 +40755,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHRD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_185(N, X86::SHRD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40721,7 +40787,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40753,7 +40819,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40785,7 +40851,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40818,7 +40884,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40839,7 +40905,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40860,7 +40926,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40894,7 +40960,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40915,7 +40981,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40936,7 +41002,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40970,7 +41036,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40991,7 +41057,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41012,7 +41078,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41046,7 +41112,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41067,7 +41133,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41088,7 +41154,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41122,7 +41188,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41143,7 +41209,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41164,7 +41230,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41198,7 +41264,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41231,7 +41297,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41264,7 +41330,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41297,7 +41363,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41330,7 +41396,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41362,7 +41428,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_217(N, X86::AND8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::AND8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41370,7 +41436,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_217(N, X86::AND16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::AND16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41378,7 +41444,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_217(N, X86::AND32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::AND32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41411,7 +41477,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_217(N, X86::OR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::OR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41419,7 +41485,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_217(N, X86::OR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::OR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41427,7 +41493,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_217(N, X86::OR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::OR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41460,7 +41526,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_217(N, X86::XOR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::XOR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41468,7 +41534,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_217(N, X86::XOR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::XOR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41476,7 +41542,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_217(N, X86::XOR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::XOR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41509,7 +41575,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_217(N, X86::ADD8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::ADD8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41517,7 +41583,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_217(N, X86::ADD16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::ADD16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41525,7 +41591,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_217(N, X86::ADD32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::ADD32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41558,7 +41624,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_218(N, X86::ADC8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_221(N, X86::ADC8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41566,7 +41632,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_218(N, X86::ADC16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_221(N, X86::ADC16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41574,7 +41640,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_218(N, X86::ADC32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_221(N, X86::ADC32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41607,7 +41673,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_217(N, X86::ADD64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::ADD64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41639,7 +41705,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_218(N, X86::ADC64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_221(N, X86::ADC64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41671,7 +41737,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_217(N, X86::AND64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::AND64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41703,7 +41769,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_217(N, X86::OR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::OR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41735,7 +41801,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_217(N, X86::XOR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_220(N, X86::XOR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41777,7 +41843,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::f64 &&
N10.getValueType() == MVT::v2f64 &&
N1000.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_195(N, X86::MOVHPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_198(N, X86::MOVHPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -41818,7 +41884,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f64 &&
N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_197(N, X86::MOVHPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_200(N, X86::MOVHPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -41858,7 +41924,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i8 &&
N10.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_210(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i64, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_213(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i64, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -41897,7 +41963,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 35 cost = 3 size = 3
if (N10.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_211(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i32, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_214(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i32, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -41906,7 +41972,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 35 cost = 3 size = 3
if (N10.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_212(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i16, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_215(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i16, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -41944,7 +42010,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N10.getValueType() == MVT::i32 &&
N100.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_216(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_219(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -41981,7 +42047,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::f64 &&
N10.getValueType() == MVT::v2f64 &&
N100.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_194(N, X86::MOVLPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_197(N, X86::MOVLPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42015,7 +42081,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_198(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_201(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42046,7 +42112,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42063,7 +42129,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETNEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETNEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42080,7 +42146,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETLm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETLm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42097,7 +42163,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETGEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETGEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42114,7 +42180,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETLEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETLEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42131,7 +42197,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETGm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETGm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42148,7 +42214,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETBm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETBm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42165,7 +42231,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETAEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETAEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42182,7 +42248,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETBEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETBEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42199,7 +42265,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETAm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETAm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42216,7 +42282,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42233,7 +42299,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETNSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETNSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42250,7 +42316,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42267,7 +42333,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETNPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETNPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42284,7 +42350,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42301,7 +42367,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETNOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_191(N, X86::SETNOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42334,7 +42400,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f32 &&
N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_196(N, X86::MOVPS2SSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_199(N, X86::MOVPS2SSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42367,7 +42433,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 30 cost = 1 size = 3
if (N1.getValueType() == MVT::f64 &&
N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_196(N, X86::MOVLPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_199(N, X86::MOVLPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42376,7 +42442,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 30 cost = 1 size = 3
if (N1.getValueType() == MVT::i64 &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_196(N, X86::MOVPQI2QImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_199(N, X86::MOVPQI2QImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42385,7 +42451,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 30 cost = 1 size = 3
if (N1.getValueType() == MVT::f64 &&
N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_196(N, X86::MOVPD2SDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_199(N, X86::MOVPD2SDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42394,7 +42460,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 30 cost = 1 size = 3
if (N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_196(N, X86::MOVPDI2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_199(N, X86::MOVPDI2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42425,7 +42491,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 28 cost = 1 size = 3
if (N1.getValueType() == MVT::i64 &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_193(N, X86::PEXTRQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_196(N, X86::PEXTRQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42434,7 +42500,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 28 cost = 1 size = 3
if (N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_193(N, X86::PEXTRDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_196(N, X86::PEXTRDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42462,7 +42528,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_195(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42479,7 +42545,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_195(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42496,7 +42562,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_195(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42513,7 +42579,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_195(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42530,7 +42596,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_195(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42557,7 +42623,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_195(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42574,7 +42640,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_195(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42591,7 +42657,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_195(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42610,7 +42676,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_189(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42626,7 +42692,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_169(N, X86::MOV8mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOV8mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42634,7 +42700,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_173(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42642,7 +42708,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_171(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_174(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42669,7 +42735,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i64 &&
N10.getValueType() == MVT::f64) {
- SDNode *Result = Emit_192(N, X86::MOVSDto64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_195(N, X86::MOVSDto64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42678,7 +42744,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::f32) {
- SDNode *Result = Emit_192(N, X86::MOVSS2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_195(N, X86::MOVSS2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42704,7 +42770,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_173(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42712,7 +42778,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_173(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42736,7 +42802,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_172(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42759,7 +42825,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_172(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42777,7 +42843,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_172(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42801,7 +42867,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_172(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42819,7 +42885,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_172(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42838,7 +42904,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ST_FpP80m:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 22 cost = 1 size = 0
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_172(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42846,7 +42912,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_172(N, X86::MOV8mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOV8mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42854,7 +42920,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_172(N, X86::MOV16mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOV16mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42862,7 +42928,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_172(N, X86::MOV32mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOV32mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42870,7 +42936,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_172(N, X86::MOV64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOV64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42895,7 +42961,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_172(N, X86::MOVSSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVSSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42913,7 +42979,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42930,7 +42996,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42953,7 +43019,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_172(N, X86::MOVSDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVSDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42971,7 +43037,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_172(N, X86::MOVAPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVAPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42988,7 +43054,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_172(N, X86::MOVUPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVUPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -43010,7 +43076,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -43033,7 +43099,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43041,7 +43107,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43049,7 +43115,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43057,7 +43123,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -43075,7 +43141,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43083,7 +43149,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43091,7 +43157,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43099,7 +43165,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -43121,7 +43187,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43129,7 +43195,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43137,7 +43203,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43145,7 +43211,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43153,7 +43219,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -43173,7 +43239,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mr:isVoid addr:iPTR:$dst, (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32))
// Pattern complexity = 22 cost = 2 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_207(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43181,7 +43247,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mr:isVoid addr:iPTR:$dst, (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
// Pattern complexity = 22 cost = 2 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_207(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -43192,7 +43258,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_224(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_227(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N1);
@@ -43235,7 +43301,7 @@ SDNode *Select_ISD_SUB_i8(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_224(N, X86::NEG8r, MVT::i8);
+ SDNode *Result = Emit_227(N, X86::NEG8r, MVT::i8);
return Result;
}
}
@@ -43296,7 +43362,7 @@ SDNode *Select_ISD_SUB_i16(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_224(N, X86::NEG16r, MVT::i16);
+ SDNode *Result = Emit_227(N, X86::NEG16r, MVT::i16);
return Result;
}
}
@@ -43393,7 +43459,7 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_224(N, X86::NEG32r, MVT::i32);
+ SDNode *Result = Emit_227(N, X86::NEG32r, MVT::i32);
return Result;
}
}
@@ -43476,7 +43542,7 @@ SDNode *Select_ISD_SUB_i64(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_224(N, X86::NEG64r, MVT::i64);
+ SDNode *Result = Emit_227(N, X86::NEG64r, MVT::i64);
return Result;
}
}
@@ -44200,30 +44266,30 @@ SDNode *Select_ISD_SUBE_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_225(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_228(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
}
SDNode *Select_ISD_TRAP(const SDValue &N) {
- SDNode *Result = Emit_225(N, X86::TRAP);
+ SDNode *Result = Emit_228(N, X86::TRAP);
return Result;
}
-DISABLE_INLINE SDNode *Emit_226(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_229(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N.getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_227(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_230(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N.getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_228(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_231(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -44232,7 +44298,7 @@ DISABLE_INLINE SDNode *Emit_228(const SDValue &N, unsigned Opc0, unsigned Opc1,
SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp4, Tmp5);
}
-DISABLE_INLINE SDNode *Emit_229(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_232(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -44241,7 +44307,7 @@ DISABLE_INLINE SDNode *Emit_229(const SDValue &N, unsigned Opc0, unsigned Opc1,
SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp4, Tmp5);
}
-DISABLE_INLINE SDNode *Emit_230(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_233(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
@@ -44263,7 +44329,7 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
// Pattern complexity = 12 cost = 2 size = 0
if (N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_228(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
+ SDNode *Result = Emit_231(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
return Result;
}
@@ -44272,7 +44338,7 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
// Pattern complexity = 12 cost = 2 size = 0
if (N0.getValueType() == MVT::i32 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_229(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
+ SDNode *Result = Emit_232(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
return Result;
}
}
@@ -44286,7 +44352,7 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
{
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_230(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ SDNode *Result = Emit_233(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
return Result;
}
}
@@ -44297,7 +44363,7 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:i8 GR32:i32:$src, 1:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_230(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ SDNode *Result = Emit_233(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
return Result;
}
@@ -44305,7 +44371,7 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:i8 GR16:i16:$src, 1:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_230(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ SDNode *Result = Emit_233(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
return Result;
}
}
@@ -44316,7 +44382,7 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 1:i32)
// Pattern complexity = 3 cost = 2 size = 0
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_226(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
+ SDNode *Result = Emit_229(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
return Result;
}
@@ -44324,7 +44390,7 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 1:i32)
// Pattern complexity = 3 cost = 2 size = 0
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_227(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
+ SDNode *Result = Emit_230(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
return Result;
}
}
@@ -44333,7 +44399,7 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_231(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_234(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
@@ -44345,7 +44411,7 @@ SDNode *Select_ISD_TRUNCATE_i16(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_231(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
+ SDNode *Result = Emit_234(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
return Result;
}
@@ -44353,7 +44419,7 @@ SDNode *Select_ISD_TRUNCATE_i16(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_231(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
+ SDNode *Result = Emit_234(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
return Result;
}
@@ -44361,7 +44427,7 @@ SDNode *Select_ISD_TRUNCATE_i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_232(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_235(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
@@ -44369,7 +44435,7 @@ DISABLE_INLINE SDNode *Emit_232(const SDValue &N, unsigned Opc0, MVT::SimpleValu
SDNode *Select_ISD_TRUNCATE_i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_232(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32);
+ SDNode *Result = Emit_235(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32);
return Result;
}
@@ -44451,7 +44517,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLBWrr, MVT::v8i8);
+ SDNode *Result = Emit_164(N, X86::MMX_PUNPCKLBWrr, MVT::v8i8);
return Result;
}
}
@@ -44463,7 +44529,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHBWrr, MVT::v8i8);
+ SDNode *Result = Emit_164(N, X86::MMX_PUNPCKHBWrr, MVT::v8i8);
return Result;
}
}
@@ -44490,7 +44556,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_233(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_236(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp3 = Transform_SHUFFLE_get_palign_imm(N.getNode());
@@ -44573,7 +44639,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKLBWrr, MVT::v16i8);
+ SDNode *Result = Emit_164(N, X86::PUNPCKLBWrr, MVT::v16i8);
return Result;
}
}
@@ -44585,7 +44651,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKHBWrr, MVT::v16i8);
+ SDNode *Result = Emit_164(N, X86::PUNPCKHBWrr, MVT::v16i8);
return Result;
}
}
@@ -44596,7 +44662,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->hasSSSE3()) &&
Predicate_palign(N.getNode())) {
- SDNode *Result = Emit_233(N, X86::PALIGNR128rr, MVT::v16i8);
+ SDNode *Result = Emit_236(N, X86::PALIGNR128rr, MVT::v16i8);
return Result;
}
if ((Subtarget->hasSSE2())) {
@@ -44622,13 +44688,13 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_234(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_237(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp2 = Transform_MMX_SHUFFLE_get_shuf_imm(N.getNode());
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_235(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_238(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Chain00 = N00.getOperand(0);
@@ -44671,7 +44737,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_235(N, X86::MMX_PSHUFWmi, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_238(N, X86::MMX_PSHUFWmi, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -44750,7 +44816,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLWDrr, MVT::v4i16);
+ SDNode *Result = Emit_164(N, X86::MMX_PUNPCKLWDrr, MVT::v4i16);
return Result;
}
}
@@ -44762,7 +44828,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHWDrr, MVT::v4i16);
+ SDNode *Result = Emit_164(N, X86::MMX_PUNPCKHWDrr, MVT::v4i16);
return Result;
}
}
@@ -44775,7 +44841,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_234(N, X86::MMX_PSHUFWri, MVT::v4i16);
+ SDNode *Result = Emit_237(N, X86::MMX_PSHUFWri, MVT::v4i16);
return Result;
}
}
@@ -44801,13 +44867,13 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_236(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_239(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp2 = Transform_SHUFFLE_get_pshufhw_imm(N.getNode());
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_237(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_240(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Chain00 = N00.getOperand(0);
@@ -44822,13 +44888,13 @@ DISABLE_INLINE SDNode *Emit_237(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_238(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_241(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp2 = Transform_SHUFFLE_get_pshuflw_imm(N.getNode());
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_239(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_242(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Chain00 = N00.getOperand(0);
@@ -44872,7 +44938,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_237(N, X86::PSHUFHWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_240(N, X86::PSHUFHWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -44906,7 +44972,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_239(N, X86::PSHUFLWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_242(N, X86::PSHUFLWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -44988,7 +45054,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKLWDrr, MVT::v8i16);
+ SDNode *Result = Emit_164(N, X86::PUNPCKLWDrr, MVT::v8i16);
return Result;
}
}
@@ -45000,7 +45066,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKHWDrr, MVT::v8i16);
+ SDNode *Result = Emit_164(N, X86::PUNPCKHWDrr, MVT::v8i16);
return Result;
}
}
@@ -45011,7 +45077,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->hasSSSE3()) &&
Predicate_palign(N.getNode())) {
- SDNode *Result = Emit_233(N, X86::PALIGNR128rr, MVT::v8i16);
+ SDNode *Result = Emit_236(N, X86::PALIGNR128rr, MVT::v8i16);
return Result;
}
if ((Subtarget->hasSSE2())) {
@@ -45023,7 +45089,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_236(N, X86::PSHUFHWri, MVT::v8i16);
+ SDNode *Result = Emit_239(N, X86::PSHUFHWri, MVT::v8i16);
return Result;
}
}
@@ -45035,7 +45101,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_238(N, X86::PSHUFLWri, MVT::v8i16);
+ SDNode *Result = Emit_241(N, X86::PSHUFLWri, MVT::v8i16);
return Result;
}
}
@@ -45135,7 +45201,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLDQrr, MVT::v2i32);
+ SDNode *Result = Emit_164(N, X86::MMX_PUNPCKLDQrr, MVT::v2i32);
return Result;
}
}
@@ -45147,7 +45213,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHDQrr, MVT::v2i32);
+ SDNode *Result = Emit_164(N, X86::MMX_PUNPCKHDQrr, MVT::v2i32);
return Result;
}
}
@@ -45174,13 +45240,13 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_240(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_243(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp2 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_241(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_244(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Chain00 = N00.getOperand(0);
@@ -45195,7 +45261,7 @@ DISABLE_INLINE SDNode *Emit_241(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_242(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_245(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Chain00 = N00.getOperand(0);
@@ -45209,13 +45275,13 @@ DISABLE_INLINE SDNode *Emit_242(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_243(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_246(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_244(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_247(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -45259,7 +45325,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_242(N, X86::MOVSHDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_245(N, X86::MOVSHDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -45293,7 +45359,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_242(N, X86::MOVSLDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_245(N, X86::MOVSLDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -45355,7 +45421,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_241(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_244(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -45391,7 +45457,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_242(N, X86::MOVDDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_245(N, X86::MOVDDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -45426,7 +45492,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_241(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_244(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -45523,7 +45589,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_244(N, X86::SHUFPSrmi, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_247(N, X86::SHUFPSrmi, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -45540,7 +45606,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MOVHLPSrr, MVT::v4i32);
+ SDNode *Result = Emit_164(N, X86::MOVHLPSrr, MVT::v4i32);
return Result;
}
}
@@ -45569,7 +45635,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_92(N, X86::MOVSHDUPrr, MVT::v4i32);
+ SDNode *Result = Emit_94(N, X86::MOVSHDUPrr, MVT::v4i32);
return Result;
}
}
@@ -45581,7 +45647,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_92(N, X86::MOVSLDUPrr, MVT::v4i32);
+ SDNode *Result = Emit_94(N, X86::MOVSLDUPrr, MVT::v4i32);
return Result;
}
}
@@ -45595,7 +45661,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4i32);
+ SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4i32);
return Result;
}
}
@@ -45607,7 +45673,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4i32);
+ SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4i32);
return Result;
}
}
@@ -45637,7 +45703,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKLDQrr, MVT::v4i32);
+ SDNode *Result = Emit_164(N, X86::PUNPCKLDQrr, MVT::v4i32);
return Result;
}
}
@@ -45649,7 +45715,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKHDQrr, MVT::v4i32);
+ SDNode *Result = Emit_164(N, X86::PUNPCKHDQrr, MVT::v4i32);
return Result;
}
}
@@ -45661,7 +45727,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4i32);
+ SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4i32);
return Result;
}
}
@@ -45672,7 +45738,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->hasSSSE3()) &&
Predicate_palign(N.getNode())) {
- SDNode *Result = Emit_233(N, X86::PALIGNR128rr, MVT::v4i32);
+ SDNode *Result = Emit_236(N, X86::PALIGNR128rr, MVT::v4i32);
return Result;
}
if ((Subtarget->hasSSE2())) {
@@ -45697,7 +45763,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Emits: (SHUFPSrri:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_shufp(N.getNode())) {
- SDNode *Result = Emit_243(N, X86::SHUFPSrri, MVT::v4i32);
+ SDNode *Result = Emit_246(N, X86::SHUFPSrri, MVT::v4i32);
return Result;
}
}
@@ -45706,14 +45772,14 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_245(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_248(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
SDValue N100 = N10.getOperand(0);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N100);
}
-DISABLE_INLINE SDNode *Emit_246(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_249(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -45726,7 +45792,7 @@ DISABLE_INLINE SDNode *Emit_246(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_247(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_250(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
@@ -45784,7 +45850,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_246(N, X86::MOVDDUPrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_249(N, X86::MOVDDUPrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -45801,7 +45867,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MOVLHPSrr, MVT::v2i64);
+ SDNode *Result = Emit_164(N, X86::MOVLHPSrr, MVT::v2i64);
return Result;
}
}
@@ -45879,7 +45945,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKLQDQrr, MVT::v2i64);
+ SDNode *Result = Emit_164(N, X86::PUNPCKLQDQrr, MVT::v2i64);
return Result;
}
}
@@ -45891,7 +45957,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKHQDQrr, MVT::v2i64);
+ SDNode *Result = Emit_164(N, X86::PUNPCKHQDQrr, MVT::v2i64);
return Result;
}
}
@@ -45910,7 +45976,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
SDValue N100 = N10.getOperand(0);
if (N10.getValueType() == MVT::i64 &&
N100.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_245(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ SDNode *Result = Emit_248(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
return Result;
}
}
@@ -45925,7 +45991,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_247(N, X86::SHUFPDrri, MVT::v2i64);
+ SDNode *Result = Emit_250(N, X86::SHUFPDrri, MVT::v2i64);
return Result;
}
}
@@ -45950,7 +46016,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Emits: (SHUFPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_shufp(N.getNode())) {
- SDNode *Result = Emit_243(N, X86::SHUFPDrri, MVT::v2i64);
+ SDNode *Result = Emit_246(N, X86::SHUFPDrri, MVT::v2i64);
return Result;
}
}
@@ -45959,7 +46025,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_248(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+DISABLE_INLINE SDNode *Emit_251(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -45974,7 +46040,7 @@ DISABLE_INLINE SDNode *Emit_248(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N100.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_249(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_252(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -45988,7 +46054,7 @@ DISABLE_INLINE SDNode *Emit_249(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_250(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_253(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
@@ -46026,7 +46092,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2f64 &&
N100.getValueType() == MVT::f64) {
- SDNode *Result = Emit_248(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_251(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -46063,7 +46129,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2f64 &&
N100.getValueType() == MVT::f64) {
- SDNode *Result = Emit_248(N, X86::MOVHPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_251(N, X86::MOVHPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -46125,7 +46191,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_242(N, X86::MOVDDUPrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_245(N, X86::MOVDDUPrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -46212,7 +46278,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_246(N, X86::MOVSHDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_249(N, X86::MOVSHDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -46241,7 +46307,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_246(N, X86::MOVSLDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_249(N, X86::MOVSLDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -46259,7 +46325,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MOVLHPSrr, MVT::v4f32);
+ SDNode *Result = Emit_164(N, X86::MOVLHPSrr, MVT::v4f32);
return Result;
}
}
@@ -46271,7 +46337,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MOVHLPSrr, MVT::v4f32);
+ SDNode *Result = Emit_164(N, X86::MOVHLPSrr, MVT::v4f32);
return Result;
}
}
@@ -46298,7 +46364,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_249(N, X86::SHUFPSrmi, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_252(N, X86::SHUFPSrmi, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -46331,7 +46397,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4f32);
+ SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4f32);
return Result;
}
}
@@ -46343,7 +46409,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4f32);
+ SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4f32);
return Result;
}
}
@@ -46375,7 +46441,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::UNPCKLPSrr, MVT::v4f32);
+ SDNode *Result = Emit_164(N, X86::UNPCKLPSrr, MVT::v4f32);
return Result;
}
}
@@ -46387,7 +46453,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::UNPCKHPSrr, MVT::v4f32);
+ SDNode *Result = Emit_164(N, X86::UNPCKHPSrr, MVT::v4f32);
return Result;
}
}
@@ -46417,7 +46483,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4f32);
+ SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4f32);
return Result;
}
}
@@ -46427,7 +46493,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->hasSSSE3()) &&
Predicate_palign(N.getNode())) {
- SDNode *Result = Emit_233(N, X86::PALIGNR128rr, MVT::v4f32);
+ SDNode *Result = Emit_236(N, X86::PALIGNR128rr, MVT::v4f32);
return Result;
}
if ((Subtarget->hasSSE3())) {
@@ -46439,7 +46505,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_92(N, X86::MOVSHDUPrr, MVT::v4f32);
+ SDNode *Result = Emit_94(N, X86::MOVSHDUPrr, MVT::v4f32);
return Result;
}
}
@@ -46451,7 +46517,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_92(N, X86::MOVSLDUPrr, MVT::v4f32);
+ SDNode *Result = Emit_94(N, X86::MOVSLDUPrr, MVT::v4f32);
return Result;
}
}
@@ -46465,7 +46531,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_247(N, X86::SHUFPSrri, MVT::v4f32);
+ SDNode *Result = Emit_250(N, X86::SHUFPSrri, MVT::v4f32);
return Result;
}
}
@@ -46474,7 +46540,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Emits: (SHUFPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2):$src3))
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_shufp(N.getNode())) {
- SDNode *Result = Emit_243(N, X86::SHUFPSrri, MVT::v4f32);
+ SDNode *Result = Emit_246(N, X86::SHUFPSrri, MVT::v4f32);
return Result;
}
@@ -46482,7 +46548,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Emits: (SHUFPSrri:v4f32 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_movlp(N.getNode())) {
- SDNode *Result = Emit_250(N, X86::SHUFPSrri, MVT::v4f32);
+ SDNode *Result = Emit_253(N, X86::SHUFPSrri, MVT::v4f32);
return Result;
}
}
@@ -46491,7 +46557,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_251(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
+DISABLE_INLINE SDNode *Emit_254(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N000 = N00.getOperand(0);
@@ -46685,7 +46751,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
if (N1.getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64 &&
N000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_251(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
+ SDNode *Result = Emit_254(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
return Result;
}
}
@@ -46713,7 +46779,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_246(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_249(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -46743,7 +46809,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_242(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_245(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -46773,7 +46839,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_249(N, X86::SHUFPDrmi, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_252(N, X86::SHUFPDrmi, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -46790,7 +46856,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
SDValue N0 = N.getOperand(0);
if (N0.getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllZerosV_bc(N0.getNode())) {
- SDNode *Result = Emit_106(N, X86::MOVZPQILo2PQIrr, MVT::v2f64);
+ SDNode *Result = Emit_108(N, X86::MOVZPQILo2PQIrr, MVT::v2f64);
return Result;
}
}
@@ -46809,7 +46875,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::UNPCKLPDrr, MVT::v2f64);
+ SDNode *Result = Emit_164(N, X86::UNPCKLPDrr, MVT::v2f64);
return Result;
}
}
@@ -46822,7 +46888,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::UNPCKHPDrr, MVT::v2f64);
+ SDNode *Result = Emit_164(N, X86::UNPCKHPDrr, MVT::v2f64);
return Result;
}
}
@@ -46851,7 +46917,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_92(N, X86::MOVDDUPrr, MVT::v2f64);
+ SDNode *Result = Emit_94(N, X86::MOVDDUPrr, MVT::v2f64);
return Result;
}
}
@@ -46864,7 +46930,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_247(N, X86::SHUFPDrri, MVT::v2f64);
+ SDNode *Result = Emit_250(N, X86::SHUFPDrri, MVT::v2f64);
return Result;
}
}
@@ -46873,7 +46939,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Emits: (SHUFPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2):$src3))
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_shufp(N.getNode())) {
- SDNode *Result = Emit_243(N, X86::SHUFPDrri, MVT::v2f64);
+ SDNode *Result = Emit_246(N, X86::SHUFPDrri, MVT::v2f64);
return Result;
}
}
@@ -46942,7 +47008,7 @@ SDNode *Select_ISD_XOR_i8(const SDValue &N) {
// Emits: (NOT8r:i8 GR8:i8:$src)
// Pattern complexity = 22 cost = 1 size = 2
if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_92(N, X86::NOT8r, MVT::i8);
+ SDNode *Result = Emit_94(N, X86::NOT8r, MVT::i8);
return Result;
}
@@ -47021,7 +47087,7 @@ SDNode *Select_ISD_XOR_i16(const SDValue &N) {
// Emits: (NOT16r:i16 GR16:i16:$src)
// Pattern complexity = 22 cost = 1 size = 2
if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_92(N, X86::NOT16r, MVT::i16);
+ SDNode *Result = Emit_94(N, X86::NOT16r, MVT::i16);
return Result;
}
@@ -47108,7 +47174,7 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
// Emits: (NOT32r:i32 GR32:i32:$src)
// Pattern complexity = 22 cost = 1 size = 2
if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_92(N, X86::NOT32r, MVT::i32);
+ SDNode *Result = Emit_94(N, X86::NOT32r, MVT::i32);
return Result;
}
@@ -47195,7 +47261,7 @@ SDNode *Select_ISD_XOR_i64(const SDValue &N) {
// Emits: (NOT64r:i64 GR64:i64:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_92(N, X86::NOT64r, MVT::i64);
+ SDNode *Result = Emit_94(N, X86::NOT64r, MVT::i64);
return Result;
}
@@ -47509,25 +47575,6 @@ SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
SDNode *Select_ISD_ZERO_EXTEND_i16(const SDValue &N) {
SDValue N0 = N.getOperand(0);
-
- // Pattern: (zext:i16 (X86setcc_c:i8 2:i8, EFLAGS:i32))
- // Emits: (SETB_C16r:i16)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_72(N, X86::SETB_C16r, MVT::i16);
- return Result;
- }
- }
- }
-
- // Pattern: (zext:i16 GR8:i8:$src)
- // Emits: (MOVZX16rr8:i16 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
SDNode *Result = Emit_71(N, X86::MOVZX16rr8, MVT::i16);
return Result;
@@ -47584,21 +47631,6 @@ SDNode *Select_ISD_ZERO_EXTEND_i32(const SDValue &N) {
}
SDValue N0 = N.getOperand(0);
- // Pattern: (zext:i32 (X86setcc_c:i8 2:i8, EFLAGS:i32))
- // Emits: (SETB_C32r:i32)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_72(N, X86::SETB_C32r, MVT::i32);
- return Result;
- }
- }
- }
-
// Pattern: (zext:i32 GR8:i8:$src)
// Emits: (MOVZX32rr8:i32 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
@@ -47641,21 +47673,6 @@ SDNode *Select_ISD_ZERO_EXTEND_i64(const SDValue &N) {
}
}
- // Pattern: (zext:i64 (X86setcc_c:i8 2:i8, EFLAGS:i32))
- // Emits: (SETB_C64r:i64)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_72(N, X86::SETB_C64r, MVT::i64);
- return Result;
- }
- }
- }
-
// Pattern: (zext:i64 GR32:i32<<P:Predicate_def32>>:$src)
// Emits: (SUBREG_TO_REG:i64 0:i64, GR32:i32:$src, 4:i32)
// Pattern complexity = 4 cost = 1 size = 0
@@ -48125,7 +48142,7 @@ SDNode *Select_X86ISD_AND_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_252(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_255(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -48149,7 +48166,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_252(N, X86::JE);
+ SDNode *Result = Emit_255(N, X86::JE);
return Result;
}
@@ -48157,7 +48174,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JNE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_252(N, X86::JNE);
+ SDNode *Result = Emit_255(N, X86::JNE);
return Result;
}
@@ -48165,7 +48182,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JL:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_252(N, X86::JL);
+ SDNode *Result = Emit_255(N, X86::JL);
return Result;
}
@@ -48173,7 +48190,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JLE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_252(N, X86::JLE);
+ SDNode *Result = Emit_255(N, X86::JLE);
return Result;
}
@@ -48181,7 +48198,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JG:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_252(N, X86::JG);
+ SDNode *Result = Emit_255(N, X86::JG);
return Result;
}
@@ -48189,7 +48206,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JGE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_252(N, X86::JGE);
+ SDNode *Result = Emit_255(N, X86::JGE);
return Result;
}
@@ -48197,7 +48214,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JB:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_252(N, X86::JB);
+ SDNode *Result = Emit_255(N, X86::JB);
return Result;
}
@@ -48205,7 +48222,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JBE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_252(N, X86::JBE);
+ SDNode *Result = Emit_255(N, X86::JBE);
return Result;
}
@@ -48213,7 +48230,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JA:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_252(N, X86::JA);
+ SDNode *Result = Emit_255(N, X86::JA);
return Result;
}
@@ -48221,7 +48238,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JAE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_252(N, X86::JAE);
+ SDNode *Result = Emit_255(N, X86::JAE);
return Result;
}
@@ -48229,7 +48246,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JS:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_252(N, X86::JS);
+ SDNode *Result = Emit_255(N, X86::JS);
return Result;
}
@@ -48237,7 +48254,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JNS:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_252(N, X86::JNS);
+ SDNode *Result = Emit_255(N, X86::JNS);
return Result;
}
@@ -48245,7 +48262,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JP:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_252(N, X86::JP);
+ SDNode *Result = Emit_255(N, X86::JP);
return Result;
}
@@ -48253,7 +48270,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JNP:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_252(N, X86::JNP);
+ SDNode *Result = Emit_255(N, X86::JNP);
return Result;
}
@@ -48261,7 +48278,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JO:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_252(N, X86::JO);
+ SDNode *Result = Emit_255(N, X86::JO);
return Result;
}
@@ -48269,7 +48286,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JNO:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_252(N, X86::JNO);
+ SDNode *Result = Emit_255(N, X86::JNO);
return Result;
}
}
@@ -48279,11 +48296,11 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_253(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_256(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0);
}
-DISABLE_INLINE SDNode *Emit_254(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_257(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -48314,7 +48331,7 @@ SDNode *Select_X86ISD_BSF_i16(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_254(N, X86::BSF16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_257(N, X86::BSF16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48324,7 +48341,7 @@ SDNode *Select_X86ISD_BSF_i16(const SDValue &N) {
// Pattern: (X86bsf:i16 GR16:i16:$src)
// Emits: (BSF16rr:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_253(N, X86::BSF16rr, MVT::i16);
+ SDNode *Result = Emit_256(N, X86::BSF16rr, MVT::i16);
return Result;
}
@@ -48347,7 +48364,7 @@ SDNode *Select_X86ISD_BSF_i32(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_254(N, X86::BSF32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_257(N, X86::BSF32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48357,7 +48374,7 @@ SDNode *Select_X86ISD_BSF_i32(const SDValue &N) {
// Pattern: (X86bsf:i32 GR32:i32:$src)
// Emits: (BSF32rr:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_253(N, X86::BSF32rr, MVT::i32);
+ SDNode *Result = Emit_256(N, X86::BSF32rr, MVT::i32);
return Result;
}
@@ -48381,7 +48398,7 @@ SDNode *Select_X86ISD_BSF_i64(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_254(N, X86::BSF64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_257(N, X86::BSF64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48391,7 +48408,7 @@ SDNode *Select_X86ISD_BSF_i64(const SDValue &N) {
// Pattern: (X86bsf:i64 GR64:i64:$src)
// Emits: (BSF64rr:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_253(N, X86::BSF64rr, MVT::i64);
+ SDNode *Result = Emit_256(N, X86::BSF64rr, MVT::i64);
return Result;
}
@@ -48414,7 +48431,7 @@ SDNode *Select_X86ISD_BSR_i16(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_254(N, X86::BSR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_257(N, X86::BSR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48424,7 +48441,7 @@ SDNode *Select_X86ISD_BSR_i16(const SDValue &N) {
// Pattern: (X86bsr:i16 GR16:i16:$src)
// Emits: (BSR16rr:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_253(N, X86::BSR16rr, MVT::i16);
+ SDNode *Result = Emit_256(N, X86::BSR16rr, MVT::i16);
return Result;
}
@@ -48447,7 +48464,7 @@ SDNode *Select_X86ISD_BSR_i32(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_254(N, X86::BSR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_257(N, X86::BSR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48457,7 +48474,7 @@ SDNode *Select_X86ISD_BSR_i32(const SDValue &N) {
// Pattern: (X86bsr:i32 GR32:i32:$src)
// Emits: (BSR32rr:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_253(N, X86::BSR32rr, MVT::i32);
+ SDNode *Result = Emit_256(N, X86::BSR32rr, MVT::i32);
return Result;
}
@@ -48481,7 +48498,7 @@ SDNode *Select_X86ISD_BSR_i64(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_254(N, X86::BSR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_257(N, X86::BSR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48491,28 +48508,28 @@ SDNode *Select_X86ISD_BSR_i64(const SDValue &N) {
// Pattern: (X86bsr:i64 GR64:i64:$src)
// Emits: (BSR64rr:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_253(N, X86::BSR64rr, MVT::i64);
+ SDNode *Result = Emit_256(N, X86::BSR64rr, MVT::i64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_255(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_258(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, N1);
}
-DISABLE_INLINE SDNode *Emit_256(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_259(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_257(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_260(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_258(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_261(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -48526,7 +48543,7 @@ DISABLE_INLINE SDNode *Emit_258(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_259(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_262(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -48540,13 +48557,13 @@ DISABLE_INLINE SDNode *Emit_259(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_260(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_263(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_261(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_264(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -48584,7 +48601,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
if (N1.getOpcode() == ISD::Constant &&
Predicate_i16immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_258(N, X86::BT16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_261(N, X86::BT16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48605,7 +48622,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
if (N1.getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_259(N, X86::BT32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_262(N, X86::BT32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48627,7 +48644,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
if (N1.getOpcode() == ISD::Constant &&
Predicate_i64immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_261(N, X86::BT64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_264(N, X86::BT64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48644,7 +48661,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i16immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_256(N, X86::BT16ri8);
+ SDNode *Result = Emit_259(N, X86::BT16ri8);
return Result;
}
@@ -48653,7 +48670,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i32immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_257(N, X86::BT32ri8);
+ SDNode *Result = Emit_260(N, X86::BT32ri8);
return Result;
}
@@ -48662,7 +48679,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::BT64ri8);
+ SDNode *Result = Emit_263(N, X86::BT64ri8);
return Result;
}
}
@@ -48671,7 +48688,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Emits: (BT16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_255(N, X86::BT16rr);
+ SDNode *Result = Emit_258(N, X86::BT16rr);
return Result;
}
@@ -48679,7 +48696,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Emits: (BT32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_255(N, X86::BT32rr);
+ SDNode *Result = Emit_258(N, X86::BT32rr);
return Result;
}
@@ -48687,7 +48704,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Emits: (BT64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_255(N, X86::BT64rr);
+ SDNode *Result = Emit_258(N, X86::BT64rr);
return Result;
}
@@ -48695,7 +48712,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_262(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_265(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
@@ -48725,7 +48742,7 @@ DISABLE_INLINE SDNode *Emit_262(const SDValue &N, unsigned Opc0, unsigned NumInp
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_263(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_266(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4, unsigned NumInputRootOps) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -48772,7 +48789,7 @@ DISABLE_INLINE SDNode *Emit_263(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_264(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_267(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
@@ -48826,7 +48843,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_263(N, X86::CALL32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ SDNode *Result = Emit_266(N, X86::CALL32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
return Result;
}
}
@@ -48855,7 +48872,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_263(N, X86::CALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ SDNode *Result = Emit_266(N, X86::CALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
return Result;
}
}
@@ -48884,7 +48901,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_263(N, X86::WINCALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ SDNode *Result = Emit_266(N, X86::WINCALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
return Result;
}
}
@@ -48899,7 +48916,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_262(N, X86::CALL64pcrel32, 1);
+ SDNode *Result = Emit_265(N, X86::CALL64pcrel32, 1);
return Result;
}
@@ -48908,7 +48925,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_262(N, X86::CALL64pcrel32, 1);
+ SDNode *Result = Emit_265(N, X86::CALL64pcrel32, 1);
return Result;
}
}
@@ -48921,7 +48938,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_262(N, X86::WINCALL64pcrel32, 1);
+ SDNode *Result = Emit_265(N, X86::WINCALL64pcrel32, 1);
return Result;
}
@@ -48930,7 +48947,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_262(N, X86::WINCALL64pcrel32, 1);
+ SDNode *Result = Emit_265(N, X86::WINCALL64pcrel32, 1);
return Result;
}
}
@@ -48943,7 +48960,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, X86::CALLpcrel32, 1);
+ SDNode *Result = Emit_265(N, X86::CALLpcrel32, 1);
return Result;
}
@@ -48952,7 +48969,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, X86::CALLpcrel32, 1);
+ SDNode *Result = Emit_265(N, X86::CALLpcrel32, 1);
return Result;
}
}
@@ -48965,7 +48982,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_264(N, X86::CALLpcrel32, 1);
+ SDNode *Result = Emit_267(N, X86::CALLpcrel32, 1);
return Result;
}
}
@@ -48977,7 +48994,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, X86::CALL32r, 1);
+ SDNode *Result = Emit_265(N, X86::CALL32r, 1);
return Result;
}
}
@@ -48989,7 +49006,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_262(N, X86::CALL64r, 1);
+ SDNode *Result = Emit_265(N, X86::CALL64r, 1);
return Result;
}
}
@@ -49001,7 +49018,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_262(N, X86::WINCALL64r, 1);
+ SDNode *Result = Emit_265(N, X86::WINCALL64r, 1);
return Result;
}
}
@@ -49010,7 +49027,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_265(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_268(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -49029,7 +49046,7 @@ SDNode *Select_X86ISD_CMOV_i8(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_265(N, X86::CMOV_GR8, MVT::i8);
+ SDNode *Result = Emit_268(N, X86::CMOV_GR8, MVT::i8);
return Result;
}
@@ -49037,7 +49054,7 @@ SDNode *Select_X86ISD_CMOV_i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_266(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_269(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -49049,7 +49066,7 @@ DISABLE_INLINE SDNode *Emit_266(const SDValue &N, unsigned Opc0, MVT::SimpleValu
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, InFlag);
}
-DISABLE_INLINE SDNode *Emit_267(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_270(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -49068,7 +49085,7 @@ DISABLE_INLINE SDNode *Emit_267(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_268(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_271(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -49114,7 +49131,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_267(N, X86::CMOVB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49122,7 +49139,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVAE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_267(N, X86::CMOVAE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVAE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49130,7 +49147,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_267(N, X86::CMOVE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49138,7 +49155,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_267(N, X86::CMOVNE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49146,7 +49163,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVBE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_267(N, X86::CMOVBE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVBE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49154,7 +49171,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVA16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_267(N, X86::CMOVA16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVA16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49162,7 +49179,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_267(N, X86::CMOVL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49170,7 +49187,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVGE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_267(N, X86::CMOVGE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVGE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49178,7 +49195,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVLE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_267(N, X86::CMOVLE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVLE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49186,7 +49203,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVG16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_267(N, X86::CMOVG16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVG16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49194,7 +49211,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_267(N, X86::CMOVS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49202,7 +49219,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_267(N, X86::CMOVNS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49210,7 +49227,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_267(N, X86::CMOVP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49218,7 +49235,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_267(N, X86::CMOVNP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49226,7 +49243,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_267(N, X86::CMOVO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49234,7 +49251,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_267(N, X86::CMOVNO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -49265,7 +49282,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVL16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_268(N, X86::CMOVL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49273,7 +49290,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVG16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_268(N, X86::CMOVG16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVG16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49281,7 +49298,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVLE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_268(N, X86::CMOVLE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVLE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49289,7 +49306,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_268(N, X86::CMOVNP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49297,7 +49314,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_268(N, X86::CMOVP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49305,7 +49322,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_268(N, X86::CMOVNS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49313,7 +49330,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_268(N, X86::CMOVS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49321,7 +49338,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_268(N, X86::CMOVNO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49329,7 +49346,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_268(N, X86::CMOVO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49337,7 +49354,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVAE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_268(N, X86::CMOVAE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVAE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49345,7 +49362,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVB16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_268(N, X86::CMOVB16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVB16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49353,7 +49370,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_268(N, X86::CMOVNE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49361,7 +49378,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_268(N, X86::CMOVE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49369,7 +49386,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVA16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_268(N, X86::CMOVA16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVA16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49377,7 +49394,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVBE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_268(N, X86::CMOVBE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVBE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49385,7 +49402,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVGE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_268(N, X86::CMOVGE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVGE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -49404,7 +49421,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVB16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVB16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVB16rr, MVT::i16);
return Result;
}
@@ -49412,7 +49429,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVAE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVAE16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVAE16rr, MVT::i16);
return Result;
}
@@ -49420,7 +49437,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVE16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVE16rr, MVT::i16);
return Result;
}
@@ -49428,7 +49445,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVNE16rr, MVT::i16);
return Result;
}
@@ -49436,7 +49453,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVBE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVBE16rr, MVT::i16);
return Result;
}
@@ -49444,7 +49461,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVA16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVA16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVA16rr, MVT::i16);
return Result;
}
@@ -49452,7 +49469,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVL16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_266(N, X86::CMOVL16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVL16rr, MVT::i16);
return Result;
}
@@ -49460,7 +49477,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVGE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_266(N, X86::CMOVGE16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVGE16rr, MVT::i16);
return Result;
}
@@ -49468,7 +49485,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVLE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_266(N, X86::CMOVLE16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVLE16rr, MVT::i16);
return Result;
}
@@ -49476,7 +49493,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVG16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_266(N, X86::CMOVG16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVG16rr, MVT::i16);
return Result;
}
@@ -49484,7 +49501,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVS16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_266(N, X86::CMOVS16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVS16rr, MVT::i16);
return Result;
}
@@ -49492,7 +49509,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNS16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_266(N, X86::CMOVNS16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVNS16rr, MVT::i16);
return Result;
}
@@ -49500,7 +49517,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVP16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVP16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVP16rr, MVT::i16);
return Result;
}
@@ -49508,7 +49525,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNP16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVNP16rr, MVT::i16);
return Result;
}
@@ -49516,7 +49533,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVO16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_266(N, X86::CMOVO16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVO16rr, MVT::i16);
return Result;
}
@@ -49524,7 +49541,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNO16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_266(N, X86::CMOVNO16rr, MVT::i16);
+ SDNode *Result = Emit_269(N, X86::CMOVNO16rr, MVT::i16);
return Result;
}
}
@@ -49560,7 +49577,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_267(N, X86::CMOVB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49568,7 +49585,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVAE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_267(N, X86::CMOVAE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVAE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49576,7 +49593,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_267(N, X86::CMOVE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49584,7 +49601,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_267(N, X86::CMOVNE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49592,7 +49609,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVBE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_267(N, X86::CMOVBE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVBE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49600,7 +49617,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVA32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_267(N, X86::CMOVA32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVA32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49608,7 +49625,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_267(N, X86::CMOVL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49616,7 +49633,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVGE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_267(N, X86::CMOVGE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVGE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49624,7 +49641,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVLE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_267(N, X86::CMOVLE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVLE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49632,7 +49649,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVG32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_267(N, X86::CMOVG32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVG32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49640,7 +49657,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_267(N, X86::CMOVS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49648,7 +49665,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_267(N, X86::CMOVNS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49656,7 +49673,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_267(N, X86::CMOVP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49664,7 +49681,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_267(N, X86::CMOVNP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49672,7 +49689,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_267(N, X86::CMOVO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49680,7 +49697,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_267(N, X86::CMOVNO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -49707,11 +49724,19 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVGE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_271(N, X86::CMOVGE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
// Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 6:i8, EFLAGS:i32)
// Emits: (CMOVL32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_268(N, X86::CMOVL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49719,7 +49744,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVG32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_268(N, X86::CMOVG32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVG32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49727,7 +49752,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVLE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_268(N, X86::CMOVLE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVLE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49735,7 +49760,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_268(N, X86::CMOVNP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49743,7 +49768,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_268(N, X86::CMOVP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49751,7 +49776,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_268(N, X86::CMOVNS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49759,7 +49784,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_268(N, X86::CMOVS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49767,7 +49792,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_268(N, X86::CMOVNO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49775,7 +49800,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_268(N, X86::CMOVO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49783,7 +49808,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVAE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_268(N, X86::CMOVAE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVAE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49791,7 +49816,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVB32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_268(N, X86::CMOVB32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVB32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49799,7 +49824,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_268(N, X86::CMOVNE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49807,7 +49832,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_268(N, X86::CMOVE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49815,7 +49840,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVA32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_268(N, X86::CMOVA32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVA32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49823,15 +49848,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVBE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_268(N, X86::CMOVBE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 7:i8, EFLAGS:i32)
- // Emits: (CMOVGE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_268(N, X86::CMOVGE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVBE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -49850,7 +49867,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVB32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVB32rr, MVT::i32);
return Result;
}
@@ -49858,7 +49875,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVAE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVAE32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVAE32rr, MVT::i32);
return Result;
}
@@ -49866,7 +49883,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVE32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVE32rr, MVT::i32);
return Result;
}
@@ -49874,7 +49891,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVNE32rr, MVT::i32);
return Result;
}
@@ -49882,7 +49899,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVBE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVBE32rr, MVT::i32);
return Result;
}
@@ -49890,7 +49907,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVA32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVA32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVA32rr, MVT::i32);
return Result;
}
@@ -49898,7 +49915,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVL32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_266(N, X86::CMOVL32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVL32rr, MVT::i32);
return Result;
}
@@ -49906,7 +49923,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVGE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_266(N, X86::CMOVGE32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVGE32rr, MVT::i32);
return Result;
}
@@ -49914,7 +49931,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVLE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_266(N, X86::CMOVLE32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVLE32rr, MVT::i32);
return Result;
}
@@ -49922,7 +49939,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVG32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_266(N, X86::CMOVG32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVG32rr, MVT::i32);
return Result;
}
@@ -49930,7 +49947,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVS32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_266(N, X86::CMOVS32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVS32rr, MVT::i32);
return Result;
}
@@ -49938,7 +49955,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNS32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_266(N, X86::CMOVNS32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVNS32rr, MVT::i32);
return Result;
}
@@ -49946,7 +49963,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVP32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVP32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVP32rr, MVT::i32);
return Result;
}
@@ -49954,7 +49971,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNP32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVNP32rr, MVT::i32);
return Result;
}
@@ -49962,7 +49979,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVO32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_266(N, X86::CMOVO32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVO32rr, MVT::i32);
return Result;
}
@@ -49970,7 +49987,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNO32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_266(N, X86::CMOVNO32rr, MVT::i32);
+ SDNode *Result = Emit_269(N, X86::CMOVNO32rr, MVT::i32);
return Result;
}
}
@@ -50007,7 +50024,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_267(N, X86::CMOVB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50015,7 +50032,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVAE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_267(N, X86::CMOVAE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVAE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50023,7 +50040,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_267(N, X86::CMOVE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50031,7 +50048,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_267(N, X86::CMOVNE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50039,7 +50056,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVBE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_267(N, X86::CMOVBE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVBE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50047,7 +50064,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVA64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_267(N, X86::CMOVA64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVA64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50055,7 +50072,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_267(N, X86::CMOVL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50063,7 +50080,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVGE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_267(N, X86::CMOVGE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVGE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50071,7 +50088,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVLE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_267(N, X86::CMOVLE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVLE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50079,7 +50096,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVG64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_267(N, X86::CMOVG64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVG64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50087,7 +50104,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_267(N, X86::CMOVS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50095,7 +50112,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_267(N, X86::CMOVNS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50103,7 +50120,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_267(N, X86::CMOVP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50111,7 +50128,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_267(N, X86::CMOVNP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50119,7 +50136,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_267(N, X86::CMOVO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50127,7 +50144,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_267(N, X86::CMOVNO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_270(N, X86::CMOVNO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -50159,7 +50176,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVAE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_268(N, X86::CMOVAE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVAE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50167,7 +50184,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVB64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_268(N, X86::CMOVB64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVB64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50175,7 +50192,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_268(N, X86::CMOVNE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50183,7 +50200,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_268(N, X86::CMOVE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50191,7 +50208,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVA64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_268(N, X86::CMOVA64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVA64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50199,7 +50216,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVBE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_268(N, X86::CMOVBE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVBE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50207,7 +50224,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVGE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_268(N, X86::CMOVGE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVGE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50215,7 +50232,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVL64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_268(N, X86::CMOVL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50223,7 +50240,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVG64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_268(N, X86::CMOVG64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVG64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50231,7 +50248,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVLE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_268(N, X86::CMOVLE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVLE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50239,7 +50256,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_268(N, X86::CMOVNP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50247,7 +50264,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_268(N, X86::CMOVP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50255,7 +50272,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_268(N, X86::CMOVNS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50263,7 +50280,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_268(N, X86::CMOVS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50271,7 +50288,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_268(N, X86::CMOVNO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVNO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50279,7 +50296,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_268(N, X86::CMOVO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_271(N, X86::CMOVO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -50298,7 +50315,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVB64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVB64rr, MVT::i64);
return Result;
}
@@ -50306,7 +50323,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVAE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVAE64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVAE64rr, MVT::i64);
return Result;
}
@@ -50314,7 +50331,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVE64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVE64rr, MVT::i64);
return Result;
}
@@ -50322,7 +50339,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVNE64rr, MVT::i64);
return Result;
}
@@ -50330,7 +50347,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVBE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVBE64rr, MVT::i64);
return Result;
}
@@ -50338,7 +50355,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVA64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVA64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVA64rr, MVT::i64);
return Result;
}
@@ -50346,7 +50363,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVL64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_266(N, X86::CMOVL64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVL64rr, MVT::i64);
return Result;
}
@@ -50354,7 +50371,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVGE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_266(N, X86::CMOVGE64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVGE64rr, MVT::i64);
return Result;
}
@@ -50362,7 +50379,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVLE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_266(N, X86::CMOVLE64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVLE64rr, MVT::i64);
return Result;
}
@@ -50370,7 +50387,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVG64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_266(N, X86::CMOVG64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVG64rr, MVT::i64);
return Result;
}
@@ -50378,7 +50395,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVS64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_266(N, X86::CMOVS64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVS64rr, MVT::i64);
return Result;
}
@@ -50386,7 +50403,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNS64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_266(N, X86::CMOVNS64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVNS64rr, MVT::i64);
return Result;
}
@@ -50394,7 +50411,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVP64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVP64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVP64rr, MVT::i64);
return Result;
}
@@ -50402,7 +50419,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNP64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVNP64rr, MVT::i64);
return Result;
}
@@ -50410,7 +50427,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVO64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_266(N, X86::CMOVO64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVO64rr, MVT::i64);
return Result;
}
@@ -50418,7 +50435,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNO64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_266(N, X86::CMOVNO64rr, MVT::i64);
+ SDNode *Result = Emit_269(N, X86::CMOVNO64rr, MVT::i64);
return Result;
}
}
@@ -50440,7 +50457,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVB_Fp32, MVT::f32);
+ SDNode *Result = Emit_269(N, X86::CMOVB_Fp32, MVT::f32);
return Result;
}
@@ -50448,7 +50465,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVBE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE_Fp32, MVT::f32);
+ SDNode *Result = Emit_269(N, X86::CMOVBE_Fp32, MVT::f32);
return Result;
}
@@ -50456,7 +50473,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVE_Fp32, MVT::f32);
+ SDNode *Result = Emit_269(N, X86::CMOVE_Fp32, MVT::f32);
return Result;
}
@@ -50464,7 +50481,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVP_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVP_Fp32, MVT::f32);
+ SDNode *Result = Emit_269(N, X86::CMOVP_Fp32, MVT::f32);
return Result;
}
@@ -50472,7 +50489,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVNB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVNB_Fp32, MVT::f32);
+ SDNode *Result = Emit_269(N, X86::CMOVNB_Fp32, MVT::f32);
return Result;
}
@@ -50480,7 +50497,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVNBE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVNBE_Fp32, MVT::f32);
+ SDNode *Result = Emit_269(N, X86::CMOVNBE_Fp32, MVT::f32);
return Result;
}
@@ -50488,7 +50505,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVNE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE_Fp32, MVT::f32);
+ SDNode *Result = Emit_269(N, X86::CMOVNE_Fp32, MVT::f32);
return Result;
}
@@ -50496,7 +50513,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVNP_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP_Fp32, MVT::f32);
+ SDNode *Result = Emit_269(N, X86::CMOVNP_Fp32, MVT::f32);
return Result;
}
}
@@ -50509,7 +50526,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_265(N, X86::CMOV_FR32, MVT::f32);
+ SDNode *Result = Emit_268(N, X86::CMOV_FR32, MVT::f32);
return Result;
}
@@ -50530,7 +50547,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVB_Fp64, MVT::f64);
+ SDNode *Result = Emit_269(N, X86::CMOVB_Fp64, MVT::f64);
return Result;
}
@@ -50538,7 +50555,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVBE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE_Fp64, MVT::f64);
+ SDNode *Result = Emit_269(N, X86::CMOVBE_Fp64, MVT::f64);
return Result;
}
@@ -50546,7 +50563,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVE_Fp64, MVT::f64);
+ SDNode *Result = Emit_269(N, X86::CMOVE_Fp64, MVT::f64);
return Result;
}
@@ -50554,7 +50571,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVP_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVP_Fp64, MVT::f64);
+ SDNode *Result = Emit_269(N, X86::CMOVP_Fp64, MVT::f64);
return Result;
}
@@ -50562,7 +50579,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVNB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVNB_Fp64, MVT::f64);
+ SDNode *Result = Emit_269(N, X86::CMOVNB_Fp64, MVT::f64);
return Result;
}
@@ -50570,7 +50587,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVNBE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVNBE_Fp64, MVT::f64);
+ SDNode *Result = Emit_269(N, X86::CMOVNBE_Fp64, MVT::f64);
return Result;
}
@@ -50578,7 +50595,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVNE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE_Fp64, MVT::f64);
+ SDNode *Result = Emit_269(N, X86::CMOVNE_Fp64, MVT::f64);
return Result;
}
@@ -50586,7 +50603,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVNP_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP_Fp64, MVT::f64);
+ SDNode *Result = Emit_269(N, X86::CMOVNP_Fp64, MVT::f64);
return Result;
}
}
@@ -50599,7 +50616,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_265(N, X86::CMOV_FR64, MVT::f64);
+ SDNode *Result = Emit_268(N, X86::CMOV_FR64, MVT::f64);
return Result;
}
@@ -50619,7 +50636,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVB_Fp80, MVT::f80);
+ SDNode *Result = Emit_269(N, X86::CMOVB_Fp80, MVT::f80);
return Result;
}
@@ -50627,7 +50644,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVBE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE_Fp80, MVT::f80);
+ SDNode *Result = Emit_269(N, X86::CMOVBE_Fp80, MVT::f80);
return Result;
}
@@ -50635,7 +50652,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVE_Fp80, MVT::f80);
+ SDNode *Result = Emit_269(N, X86::CMOVE_Fp80, MVT::f80);
return Result;
}
@@ -50643,7 +50660,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVP_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVP_Fp80, MVT::f80);
+ SDNode *Result = Emit_269(N, X86::CMOVP_Fp80, MVT::f80);
return Result;
}
@@ -50651,7 +50668,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVNB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVNB_Fp80, MVT::f80);
+ SDNode *Result = Emit_269(N, X86::CMOVNB_Fp80, MVT::f80);
return Result;
}
@@ -50659,7 +50676,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVNBE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVNBE_Fp80, MVT::f80);
+ SDNode *Result = Emit_269(N, X86::CMOVNBE_Fp80, MVT::f80);
return Result;
}
@@ -50667,7 +50684,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVNE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE_Fp80, MVT::f80);
+ SDNode *Result = Emit_269(N, X86::CMOVNE_Fp80, MVT::f80);
return Result;
}
@@ -50675,7 +50692,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVNP_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP_Fp80, MVT::f80);
+ SDNode *Result = Emit_269(N, X86::CMOVNP_Fp80, MVT::f80);
return Result;
}
}
@@ -50689,7 +50706,7 @@ SDNode *Select_X86ISD_CMOV_v1i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_265(N, X86::CMOV_V1I64, MVT::v1i64);
+ SDNode *Result = Emit_268(N, X86::CMOV_V1I64, MVT::v1i64);
return Result;
}
@@ -50702,7 +50719,7 @@ SDNode *Select_X86ISD_CMOV_v2i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_265(N, X86::CMOV_V2I64, MVT::v2i64);
+ SDNode *Result = Emit_268(N, X86::CMOV_V2I64, MVT::v2i64);
return Result;
}
@@ -50715,7 +50732,7 @@ SDNode *Select_X86ISD_CMOV_v4f32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_265(N, X86::CMOV_V4F32, MVT::v4f32);
+ SDNode *Result = Emit_268(N, X86::CMOV_V4F32, MVT::v4f32);
return Result;
}
@@ -50728,7 +50745,7 @@ SDNode *Select_X86ISD_CMOV_v2f64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_265(N, X86::CMOV_V2F64, MVT::v2f64);
+ SDNode *Result = Emit_268(N, X86::CMOV_V2F64, MVT::v2f64);
return Result;
}
@@ -50736,14 +50753,14 @@ SDNode *Select_X86ISD_CMOV_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_269(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_272(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
SDValue N1 = N.getOperand(1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, N01);
}
-DISABLE_INLINE SDNode *Emit_270(const SDValue &N, unsigned Opc0, SDValue &CPTmpN011_0, SDValue &CPTmpN011_1, SDValue &CPTmpN011_2, SDValue &CPTmpN011_3, SDValue &CPTmpN011_4) {
+DISABLE_INLINE SDNode *Emit_273(const SDValue &N, unsigned Opc0, SDValue &CPTmpN011_0, SDValue &CPTmpN011_1, SDValue &CPTmpN011_2, SDValue &CPTmpN011_3, SDValue &CPTmpN011_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -50758,7 +50775,7 @@ DISABLE_INLINE SDNode *Emit_270(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(SDValue(N01.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_271(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_274(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -50766,7 +50783,7 @@ DISABLE_INLINE SDNode *Emit_271(const SDValue &N, unsigned Opc0) {
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_272(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_275(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -50774,7 +50791,7 @@ DISABLE_INLINE SDNode *Emit_272(const SDValue &N, unsigned Opc0) {
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i16);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_273(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_276(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -50782,7 +50799,7 @@ DISABLE_INLINE SDNode *Emit_273(const SDValue &N, unsigned Opc0) {
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_274(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_277(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Chain00 = N00.getOperand(0);
@@ -50798,7 +50815,7 @@ DISABLE_INLINE SDNode *Emit_274(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_275(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_278(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Chain00 = N00.getOperand(0);
@@ -50814,7 +50831,7 @@ DISABLE_INLINE SDNode *Emit_275(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_276(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_279(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Chain00 = N00.getOperand(0);
@@ -50830,7 +50847,7 @@ DISABLE_INLINE SDNode *Emit_276(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_277(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_280(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -50843,7 +50860,7 @@ DISABLE_INLINE SDNode *Emit_277(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_278(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_281(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -50856,13 +50873,13 @@ DISABLE_INLINE SDNode *Emit_278(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_279(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_282(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_280(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_283(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N.getOperand(0);
SDValue Chain0 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -50876,7 +50893,7 @@ DISABLE_INLINE SDNode *Emit_280(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_281(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_284(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
@@ -50884,7 +50901,7 @@ DISABLE_INLINE SDNode *Emit_281(const SDValue &N, unsigned Opc0) {
SDValue Tmp3 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i64);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_282(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_285(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Chain00 = N00.getOperand(0);
@@ -50900,12 +50917,12 @@ DISABLE_INLINE SDNode *Emit_282(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_283(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_286(const SDValue &N, unsigned Opc0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, N0);
}
-DISABLE_INLINE SDNode *Emit_284(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_287(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Chain00 = N00.getOperand(0);
@@ -50954,7 +50971,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_282(N, X86::TEST64mi32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_285(N, X86::TEST64mi32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -50981,7 +50998,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_274(N, X86::TEST8mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_277(N, X86::TEST8mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51009,7 +51026,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_275(N, X86::TEST16mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_278(N, X86::TEST16mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51036,7 +51053,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_276(N, X86::TEST32mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_279(N, X86::TEST32mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51071,7 +51088,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_270(N, X86::TEST8rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ SDNode *Result = Emit_273(N, X86::TEST8rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
@@ -51095,7 +51112,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_270(N, X86::TEST16rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ SDNode *Result = Emit_273(N, X86::TEST16rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
@@ -51119,7 +51136,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, X86::TEST32rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ SDNode *Result = Emit_273(N, X86::TEST32rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
@@ -51144,7 +51161,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_270(N, X86::TEST64rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ SDNode *Result = Emit_273(N, X86::TEST64rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
@@ -51178,7 +51195,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_284(N, X86::TEST8rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_287(N, X86::TEST8rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51203,7 +51220,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_284(N, X86::TEST16rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_287(N, X86::TEST16rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51228,7 +51245,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_284(N, X86::TEST32rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_287(N, X86::TEST32rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51254,7 +51271,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_284(N, X86::TEST64rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_287(N, X86::TEST64rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51284,7 +51301,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
if (N1.getOpcode() == ISD::Constant &&
Predicate_i16immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_258(N, X86::CMP16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_261(N, X86::CMP16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51305,7 +51322,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
if (N1.getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_259(N, X86::CMP32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_262(N, X86::CMP32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51327,7 +51344,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_261(N, X86::CMP64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_264(N, X86::CMP64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -51336,7 +51353,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt32(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_261(N, X86::CMP64mi32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_264(N, X86::CMP64mi32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51357,7 +51374,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_280(N, X86::CMP8mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_283(N, X86::CMP8mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51378,7 +51395,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_258(N, X86::CMP16mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_261(N, X86::CMP16mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51398,7 +51415,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_259(N, X86::CMP32mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_262(N, X86::CMP32mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51418,7 +51435,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_277(N, X86::CMP8mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_280(N, X86::CMP8mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51437,7 +51454,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_277(N, X86::CMP16mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_280(N, X86::CMP16mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51456,7 +51473,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_277(N, X86::CMP32mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_280(N, X86::CMP32mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51484,7 +51501,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_278(N, X86::CMP8rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_281(N, X86::CMP8rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51501,7 +51518,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_278(N, X86::CMP16rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_281(N, X86::CMP16rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51518,7 +51535,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_278(N, X86::CMP32rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_281(N, X86::CMP32rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51545,7 +51562,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_277(N, X86::CMP64mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_280(N, X86::CMP64mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51571,7 +51588,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_278(N, X86::CMP64rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_281(N, X86::CMP64rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51599,7 +51616,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_278(N, X86::UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_281(N, X86::UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51627,7 +51644,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_278(N, X86::UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_281(N, X86::UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51651,7 +51668,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST8ri:isVoid GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 15 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_271(N, X86::TEST8ri);
+ SDNode *Result = Emit_274(N, X86::TEST8ri);
return Result;
}
@@ -51659,7 +51676,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST16ri:isVoid GR16:i16:$src1, (imm:i16):$src2)
// Pattern complexity = 15 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_272(N, X86::TEST16ri);
+ SDNode *Result = Emit_275(N, X86::TEST16ri);
return Result;
}
@@ -51667,7 +51684,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST32ri:isVoid GR32:i32:$src1, (imm:i32):$src2)
// Pattern complexity = 15 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_273(N, X86::TEST32ri);
+ SDNode *Result = Emit_276(N, X86::TEST32ri);
return Result;
}
}
@@ -51689,7 +51706,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_281(N, X86::TEST64ri32);
+ SDNode *Result = Emit_284(N, X86::TEST64ri32);
return Result;
}
}
@@ -51708,7 +51725,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST8rr:isVoid GR8:i8:$src1, GR8:i8:$src2)
// Pattern complexity = 12 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_269(N, X86::TEST8rr);
+ SDNode *Result = Emit_272(N, X86::TEST8rr);
return Result;
}
@@ -51716,7 +51733,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 12 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_269(N, X86::TEST16rr);
+ SDNode *Result = Emit_272(N, X86::TEST16rr);
return Result;
}
@@ -51724,7 +51741,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 12 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, X86::TEST32rr);
+ SDNode *Result = Emit_272(N, X86::TEST32rr);
return Result;
}
}
@@ -51742,7 +51759,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_269(N, X86::TEST64rr);
+ SDNode *Result = Emit_272(N, X86::TEST64rr);
return Result;
}
}
@@ -51758,7 +51775,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST64rr:isVoid GR64:i64:$src1, GR64:i64:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_283(N, X86::TEST64rr);
+ SDNode *Result = Emit_286(N, X86::TEST64rr);
return Result;
}
@@ -51766,7 +51783,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST8rr:isVoid GR8:i8:$src1, GR8:i8:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_283(N, X86::TEST8rr);
+ SDNode *Result = Emit_286(N, X86::TEST8rr);
return Result;
}
@@ -51774,7 +51791,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST16rr:isVoid GR16:i16:$src1, GR16:i16:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_283(N, X86::TEST16rr);
+ SDNode *Result = Emit_286(N, X86::TEST16rr);
return Result;
}
@@ -51782,7 +51799,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST32rr:isVoid GR32:i32:$src1, GR32:i32:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_283(N, X86::TEST32rr);
+ SDNode *Result = Emit_286(N, X86::TEST32rr);
return Result;
}
}
@@ -51795,7 +51812,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i16immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_256(N, X86::CMP16ri8);
+ SDNode *Result = Emit_259(N, X86::CMP16ri8);
return Result;
}
@@ -51804,7 +51821,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i32immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_257(N, X86::CMP32ri8);
+ SDNode *Result = Emit_260(N, X86::CMP32ri8);
return Result;
}
@@ -51813,7 +51830,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::CMP64ri8);
+ SDNode *Result = Emit_263(N, X86::CMP64ri8);
return Result;
}
@@ -51822,7 +51839,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i64immSExt32(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::CMP64ri32);
+ SDNode *Result = Emit_263(N, X86::CMP64ri32);
return Result;
}
@@ -51830,7 +51847,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP8ri:isVoid GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_279(N, X86::CMP8ri);
+ SDNode *Result = Emit_282(N, X86::CMP8ri);
return Result;
}
@@ -51838,7 +51855,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP16ri:isVoid GR16:i16:$src1, (imm:i16):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_256(N, X86::CMP16ri);
+ SDNode *Result = Emit_259(N, X86::CMP16ri);
return Result;
}
@@ -51846,7 +51863,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP32ri:isVoid GR32:i32:$src1, (imm:i32):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_257(N, X86::CMP32ri);
+ SDNode *Result = Emit_260(N, X86::CMP32ri);
return Result;
}
}
@@ -51859,7 +51876,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_255(N, X86::UCOM_FpIr32);
+ SDNode *Result = Emit_258(N, X86::UCOM_FpIr32);
return Result;
}
}
@@ -51871,7 +51888,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_255(N, X86::UCOM_FpIr64);
+ SDNode *Result = Emit_258(N, X86::UCOM_FpIr64);
return Result;
}
}
@@ -51883,7 +51900,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (UCOM_FpIr80:isVoid RFP80:f80:$lhs, RFP80:f80:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::f80) {
- SDNode *Result = Emit_255(N, X86::UCOM_FpIr80);
+ SDNode *Result = Emit_258(N, X86::UCOM_FpIr80);
return Result;
}
@@ -51891,7 +51908,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP8rr:isVoid GR8:i8:$src1, GR8:i8:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_255(N, X86::CMP8rr);
+ SDNode *Result = Emit_258(N, X86::CMP8rr);
return Result;
}
@@ -51899,7 +51916,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_255(N, X86::CMP16rr);
+ SDNode *Result = Emit_258(N, X86::CMP16rr);
return Result;
}
@@ -51907,7 +51924,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_255(N, X86::CMP32rr);
+ SDNode *Result = Emit_258(N, X86::CMP32rr);
return Result;
}
@@ -51915,7 +51932,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_255(N, X86::CMP64rr);
+ SDNode *Result = Emit_258(N, X86::CMP64rr);
return Result;
}
}
@@ -51927,7 +51944,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_255(N, X86::UCOMISSrr);
+ SDNode *Result = Emit_258(N, X86::UCOMISSrr);
return Result;
}
}
@@ -51939,7 +51956,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_255(N, X86::UCOMISDrr);
+ SDNode *Result = Emit_258(N, X86::UCOMISDrr);
return Result;
}
}
@@ -51948,14 +51965,14 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_285(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_288(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i8);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_286(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_289(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain1 = N1.getOperand(0);
@@ -51995,7 +52012,7 @@ SDNode *Select_X86ISD_CMPPD_v2i64(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_286(N, X86::CMPPDrmi, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_289(N, X86::CMPPDrmi, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -52011,7 +52028,7 @@ SDNode *Select_X86ISD_CMPPD_v2i64(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_285(N, X86::CMPPDrri, MVT::v2i64);
+ SDNode *Result = Emit_288(N, X86::CMPPDrri, MVT::v2i64);
return Result;
}
@@ -52044,7 +52061,7 @@ SDNode *Select_X86ISD_CMPPS_v4i32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_286(N, X86::CMPPSrmi, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_289(N, X86::CMPPSrmi, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -52060,7 +52077,7 @@ SDNode *Select_X86ISD_CMPPS_v4i32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_285(N, X86::CMPPSrri, MVT::v4i32);
+ SDNode *Result = Emit_288(N, X86::CMPPSrri, MVT::v4i32);
return Result;
}
@@ -52091,7 +52108,7 @@ SDNode *Select_X86ISD_COMI(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_278(N, X86::Int_COMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_281(N, X86::Int_COMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -52118,7 +52135,7 @@ SDNode *Select_X86ISD_COMI(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_278(N, X86::Int_COMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_281(N, X86::Int_COMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -52133,7 +52150,7 @@ SDNode *Select_X86ISD_COMI(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_255(N, X86::Int_COMISSrr);
+ SDNode *Result = Emit_258(N, X86::Int_COMISSrr);
return Result;
}
}
@@ -52145,7 +52162,7 @@ SDNode *Select_X86ISD_COMI(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_255(N, X86::Int_COMISDrr);
+ SDNode *Result = Emit_258(N, X86::Int_COMISDrr);
return Result;
}
}
@@ -52157,7 +52174,7 @@ SDNode *Select_X86ISD_COMI(const SDValue &N) {
SDNode *Select_X86ISD_DEC_i8(const SDValue &N) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_253(N, X86::DEC8r, MVT::i8);
+ SDNode *Result = Emit_256(N, X86::DEC8r, MVT::i8);
return Result;
}
@@ -52173,7 +52190,7 @@ SDNode *Select_X86ISD_DEC_i16(const SDValue &N) {
if ((!Subtarget->is64Bit())) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_253(N, X86::DEC16r, MVT::i16);
+ SDNode *Result = Emit_256(N, X86::DEC16r, MVT::i16);
return Result;
}
}
@@ -52184,7 +52201,7 @@ SDNode *Select_X86ISD_DEC_i16(const SDValue &N) {
if ((Subtarget->is64Bit())) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_253(N, X86::DEC64_16r, MVT::i16);
+ SDNode *Result = Emit_256(N, X86::DEC64_16r, MVT::i16);
return Result;
}
}
@@ -52201,7 +52218,7 @@ SDNode *Select_X86ISD_DEC_i32(const SDValue &N) {
if ((!Subtarget->is64Bit())) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_253(N, X86::DEC32r, MVT::i32);
+ SDNode *Result = Emit_256(N, X86::DEC32r, MVT::i32);
return Result;
}
}
@@ -52212,7 +52229,7 @@ SDNode *Select_X86ISD_DEC_i32(const SDValue &N) {
if ((Subtarget->is64Bit())) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_253(N, X86::DEC64_32r, MVT::i32);
+ SDNode *Result = Emit_256(N, X86::DEC64_32r, MVT::i32);
return Result;
}
}
@@ -52224,7 +52241,7 @@ SDNode *Select_X86ISD_DEC_i32(const SDValue &N) {
SDNode *Select_X86ISD_DEC_i64(const SDValue &N) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_253(N, X86::DEC64r, MVT::i64);
+ SDNode *Result = Emit_256(N, X86::DEC64r, MVT::i64);
return Result;
}
@@ -52240,7 +52257,7 @@ SDNode *Select_X86ISD_EH_RETURN(const SDValue &N) {
// Emits: (EH_RETURN:isVoid GR32:i32:$addr)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_81(N, X86::EH_RETURN);
+ SDNode *Result = Emit_82(N, X86::EH_RETURN);
return Result;
}
@@ -52248,7 +52265,7 @@ SDNode *Select_X86ISD_EH_RETURN(const SDValue &N) {
// Emits: (EH_RETURN64:isVoid GR64:i64:$addr)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_81(N, X86::EH_RETURN64);
+ SDNode *Result = Emit_82(N, X86::EH_RETURN64);
return Result;
}
@@ -52390,7 +52407,7 @@ SDNode *Select_X86ISD_FAND_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_287(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_290(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -52413,7 +52430,7 @@ SDNode *Select_X86ISD_FILD_f32(const SDValue &N) {
// Emits: (ILD_Fp16m32:f32 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2)->getVT() == MVT::i16) {
- SDNode *Result = Emit_287(N, X86::ILD_Fp16m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::ILD_Fp16m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52421,7 +52438,7 @@ SDNode *Select_X86ISD_FILD_f32(const SDValue &N) {
// Emits: (ILD_Fp32m32:f32 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2)->getVT() == MVT::i32) {
- SDNode *Result = Emit_287(N, X86::ILD_Fp32m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::ILD_Fp32m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52429,7 +52446,7 @@ SDNode *Select_X86ISD_FILD_f32(const SDValue &N) {
// Emits: (ILD_Fp64m32:f32 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
- SDNode *Result = Emit_287(N, X86::ILD_Fp64m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::ILD_Fp64m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52455,7 +52472,7 @@ SDNode *Select_X86ISD_FILD_f64(const SDValue &N) {
// Emits: (ILD_Fp16m64:f64 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2)->getVT() == MVT::i16) {
- SDNode *Result = Emit_287(N, X86::ILD_Fp16m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::ILD_Fp16m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52463,7 +52480,7 @@ SDNode *Select_X86ISD_FILD_f64(const SDValue &N) {
// Emits: (ILD_Fp32m64:f64 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2)->getVT() == MVT::i32) {
- SDNode *Result = Emit_287(N, X86::ILD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::ILD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52471,7 +52488,7 @@ SDNode *Select_X86ISD_FILD_f64(const SDValue &N) {
// Emits: (ILD_Fp64m64:f64 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
- SDNode *Result = Emit_287(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52496,7 +52513,7 @@ SDNode *Select_X86ISD_FILD_f80(const SDValue &N) {
// Emits: (ILD_Fp16m80:f80 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2)->getVT() == MVT::i16) {
- SDNode *Result = Emit_287(N, X86::ILD_Fp16m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::ILD_Fp16m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52504,7 +52521,7 @@ SDNode *Select_X86ISD_FILD_f80(const SDValue &N) {
// Emits: (ILD_Fp32m80:f80 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2)->getVT() == MVT::i32) {
- SDNode *Result = Emit_287(N, X86::ILD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::ILD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52512,7 +52529,7 @@ SDNode *Select_X86ISD_FILD_f80(const SDValue &N) {
// Emits: (ILD_Fp64m80:f80 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
- SDNode *Result = Emit_287(N, X86::ILD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::ILD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52521,7 +52538,7 @@ SDNode *Select_X86ISD_FILD_f80(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_288(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_291(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -52551,7 +52568,7 @@ SDNode *Select_X86ISD_FILD_FLAG_f64(const SDValue &N) {
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
SDValue N2 = N.getOperand(2);
if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
- SDNode *Result = Emit_288(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_291(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52571,7 +52588,7 @@ SDNode *Select_X86ISD_FLD_f32(const SDValue &N) {
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
SDValue N2 = N.getOperand(2);
if (cast<VTSDNode>(N2)->getVT() == MVT::f32) {
- SDNode *Result = Emit_287(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52591,7 +52608,7 @@ SDNode *Select_X86ISD_FLD_f64(const SDValue &N) {
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
SDValue N2 = N.getOperand(2);
if (cast<VTSDNode>(N2)->getVT() == MVT::f64) {
- SDNode *Result = Emit_287(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52611,7 +52628,7 @@ SDNode *Select_X86ISD_FLD_f80(const SDValue &N) {
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
SDValue N2 = N.getOperand(2);
if (cast<VTSDNode>(N2)->getVT() == MVT::f80) {
- SDNode *Result = Emit_287(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_290(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52952,7 +52969,7 @@ SDNode *Select_X86ISD_FMIN_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_289(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_292(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
@@ -52967,7 +52984,7 @@ SDNode *Select_X86ISD_FNSTCW16m(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_289(N, X86::FNSTCW16m, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_292(N, X86::FNSTCW16m, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -53109,7 +53126,7 @@ SDNode *Select_X86ISD_FOR_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_290(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_293(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -53132,7 +53149,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp16m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_290(N, X86::ISTT_Fp16m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::ISTT_Fp16m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53140,7 +53157,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp16m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_290(N, X86::ISTT_Fp16m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::ISTT_Fp16m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53148,7 +53165,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp16m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_290(N, X86::ISTT_Fp16m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::ISTT_Fp16m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53167,7 +53184,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (FP32_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_290(N, X86::FP32_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::FP32_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53175,7 +53192,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (FP64_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_290(N, X86::FP64_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::FP64_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53183,7 +53200,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (FP80_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_290(N, X86::FP80_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::FP80_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53208,7 +53225,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp32m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_290(N, X86::ISTT_Fp32m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::ISTT_Fp32m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53216,7 +53233,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp32m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_290(N, X86::ISTT_Fp32m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::ISTT_Fp32m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53224,7 +53241,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp32m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_290(N, X86::ISTT_Fp32m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::ISTT_Fp32m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53243,7 +53260,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (FP32_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_290(N, X86::FP32_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::FP32_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53251,7 +53268,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (FP64_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_290(N, X86::FP64_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::FP64_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53259,7 +53276,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (FP80_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_290(N, X86::FP80_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::FP80_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53284,7 +53301,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp64m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_290(N, X86::ISTT_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::ISTT_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53292,7 +53309,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp64m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_290(N, X86::ISTT_Fp64m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::ISTT_Fp64m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53300,7 +53317,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp64m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_290(N, X86::ISTT_Fp64m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::ISTT_Fp64m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53319,7 +53336,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (FP32_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_290(N, X86::FP32_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::FP32_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53327,7 +53344,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (FP64_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_290(N, X86::FP64_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::FP64_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53335,7 +53352,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (FP80_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_290(N, X86::FP80_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_293(N, X86::FP80_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53350,7 +53367,7 @@ SDNode *Select_X86ISD_FRCP_f32(const SDValue &N) {
// Emits: (RCPSSm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
+ (Subtarget->hasSSE1()) && (OptForSize)) {
SDValue N0 = N.getOperand(0);
if (N0.getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -53364,7 +53381,7 @@ SDNode *Select_X86ISD_FRCP_f32(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::RCPSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::RCPSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -53404,7 +53421,7 @@ SDNode *Select_X86ISD_FRCP_v4f32(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::RCPPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::RCPPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -53429,7 +53446,7 @@ SDNode *Select_X86ISD_FRSQRT_f32(const SDValue &N) {
// Emits: (RSQRTSSm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
+ (Subtarget->hasSSE1()) && (OptForSize)) {
SDValue N0 = N.getOperand(0);
if (N0.getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -53443,7 +53460,7 @@ SDNode *Select_X86ISD_FRSQRT_f32(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::RSQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::RSQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -53483,7 +53500,7 @@ SDNode *Select_X86ISD_FRSQRT_v4f32(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::RSQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::RSQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -53502,7 +53519,7 @@ SDNode *Select_X86ISD_FRSQRT_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_291(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_294(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
@@ -53516,7 +53533,7 @@ SDNode *Select_X86ISD_FSRL_v2f64(const SDValue &N) {
if (N1.getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N1.getNode()) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_291(N, X86::PSRLDQri, MVT::v2f64);
+ SDNode *Result = Emit_294(N, X86::PSRLDQri, MVT::v2f64);
return Result;
}
}
@@ -53525,7 +53542,7 @@ SDNode *Select_X86ISD_FSRL_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_292(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_295(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -53551,7 +53568,7 @@ SDNode *Select_X86ISD_FST(const SDValue &N) {
// Emits: (ST_Fp32m:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_292(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_295(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53559,7 +53576,7 @@ SDNode *Select_X86ISD_FST(const SDValue &N) {
// Emits: (ST_Fp64m32:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_292(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_295(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53569,7 +53586,7 @@ SDNode *Select_X86ISD_FST(const SDValue &N) {
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N3)->getVT() == MVT::f64 &&
N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_292(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_295(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53578,7 +53595,7 @@ SDNode *Select_X86ISD_FST(const SDValue &N) {
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N3)->getVT() == MVT::f32 &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_292(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_295(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53587,7 +53604,7 @@ SDNode *Select_X86ISD_FST(const SDValue &N) {
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N3)->getVT() == MVT::f64 &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_292(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_295(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53596,7 +53613,7 @@ SDNode *Select_X86ISD_FST(const SDValue &N) {
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N3)->getVT() == MVT::f80 &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_292(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_295(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53742,7 +53759,7 @@ SDNode *Select_X86ISD_FXOR_f64(const SDValue &N) {
SDNode *Select_X86ISD_INC_i8(const SDValue &N) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_253(N, X86::INC8r, MVT::i8);
+ SDNode *Result = Emit_256(N, X86::INC8r, MVT::i8);
return Result;
}
@@ -53758,7 +53775,7 @@ SDNode *Select_X86ISD_INC_i16(const SDValue &N) {
if ((!Subtarget->is64Bit())) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_253(N, X86::INC16r, MVT::i16);
+ SDNode *Result = Emit_256(N, X86::INC16r, MVT::i16);
return Result;
}
}
@@ -53769,7 +53786,7 @@ SDNode *Select_X86ISD_INC_i16(const SDValue &N) {
if ((Subtarget->is64Bit())) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_253(N, X86::INC64_16r, MVT::i16);
+ SDNode *Result = Emit_256(N, X86::INC64_16r, MVT::i16);
return Result;
}
}
@@ -53786,7 +53803,7 @@ SDNode *Select_X86ISD_INC_i32(const SDValue &N) {
if ((!Subtarget->is64Bit())) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_253(N, X86::INC32r, MVT::i32);
+ SDNode *Result = Emit_256(N, X86::INC32r, MVT::i32);
return Result;
}
}
@@ -53797,7 +53814,7 @@ SDNode *Select_X86ISD_INC_i32(const SDValue &N) {
if ((Subtarget->is64Bit())) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_253(N, X86::INC64_32r, MVT::i32);
+ SDNode *Result = Emit_256(N, X86::INC64_32r, MVT::i32);
return Result;
}
}
@@ -53809,7 +53826,7 @@ SDNode *Select_X86ISD_INC_i32(const SDValue &N) {
SDNode *Select_X86ISD_INC_i64(const SDValue &N) {
SDValue N0 = N.getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_253(N, X86::INC64r, MVT::i64);
+ SDNode *Result = Emit_256(N, X86::INC64r, MVT::i64);
return Result;
}
@@ -53817,7 +53834,7 @@ SDNode *Select_X86ISD_INC_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_293(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_296(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -53862,7 +53879,7 @@ SDNode *Select_X86ISD_INSERTPS_v4f32(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::f32) {
- SDNode *Result = Emit_293(N, X86::INSERTPSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_296(N, X86::INSERTPSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -53879,7 +53896,7 @@ SDNode *Select_X86ISD_INSERTPS_v4f32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_97(N, X86::INSERTPSrr, MVT::v4f32);
+ SDNode *Result = Emit_99(N, X86::INSERTPSrr, MVT::v4f32);
return Result;
}
}
@@ -53888,7 +53905,7 @@ SDNode *Select_X86ISD_INSERTPS_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_294(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_297(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue InFlag = N.getOperand(2);
@@ -53916,7 +53933,7 @@ SDNode *Select_X86ISD_LCMPXCHG8_DAG(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_294(N, X86::LCMPXCHG8B, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_297(N, X86::LCMPXCHG8B, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -53924,7 +53941,7 @@ SDNode *Select_X86ISD_LCMPXCHG8_DAG(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_295(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_298(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -53965,7 +53982,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(const SDValue &N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(4) &&
N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_295(N, X86::LCMPXCHG32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_298(N, X86::LCMPXCHG32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -53974,7 +53991,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(const SDValue &N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(2) &&
N2.getValueType() == MVT::i16) {
- SDNode *Result = Emit_295(N, X86::LCMPXCHG16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_298(N, X86::LCMPXCHG16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -53983,7 +54000,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(const SDValue &N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(1) &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_295(N, X86::LCMPXCHG8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_298(N, X86::LCMPXCHG8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -53992,7 +54009,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(const SDValue &N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(8) &&
N2.getValueType() == MVT::i64) {
- SDNode *Result = Emit_295(N, X86::LCMPXCHG64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_298(N, X86::LCMPXCHG64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -54993,7 +55010,7 @@ SDNode *Select_X86ISD_PEXTRB_i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_93(N, X86::PEXTRBrr, MVT::i32);
+ SDNode *Result = Emit_95(N, X86::PEXTRBrr, MVT::i32);
return Result;
}
}
@@ -55002,7 +55019,7 @@ SDNode *Select_X86ISD_PEXTRB_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_296(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_299(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
@@ -55018,7 +55035,7 @@ SDNode *Select_X86ISD_PEXTRW_i32(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_93(N, X86::PEXTRWri, MVT::i32);
+ SDNode *Result = Emit_95(N, X86::PEXTRWri, MVT::i32);
return Result;
}
}
@@ -55032,7 +55049,7 @@ SDNode *Select_X86ISD_PEXTRW_i32(const SDValue &N) {
if (N1.getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i16 &&
N1.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_296(N, X86::MMX_PEXTRWri, MVT::i32);
+ SDNode *Result = Emit_299(N, X86::MMX_PEXTRWri, MVT::i32);
return Result;
}
}
@@ -55066,7 +55083,7 @@ SDNode *Select_X86ISD_PINSRB_v16i8(const SDValue &N) {
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_98(N, X86::PINSRBrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_100(N, X86::PINSRBrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -55082,7 +55099,7 @@ SDNode *Select_X86ISD_PINSRB_v16i8(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_97(N, X86::PINSRBrr, MVT::v16i8);
+ SDNode *Result = Emit_99(N, X86::PINSRBrr, MVT::v16i8);
return Result;
}
}
@@ -55091,14 +55108,14 @@ SDNode *Select_X86ISD_PINSRB_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_297(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_300(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i16);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_298(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_301(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N10 = N1.getOperand(0);
@@ -55145,7 +55162,7 @@ SDNode *Select_X86ISD_PINSRW_v4i16(const SDValue &N) {
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::i16 &&
N2.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_298(N, X86::MMX_PINSRWrmi, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_301(N, X86::MMX_PINSRWrmi, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -55165,7 +55182,7 @@ SDNode *Select_X86ISD_PINSRW_v4i16(const SDValue &N) {
N0.getValueType() == MVT::v4i16 &&
N1.getValueType() == MVT::i32 &&
N2.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_297(N, X86::MMX_PINSRWrri, MVT::v4i16);
+ SDNode *Result = Emit_300(N, X86::MMX_PINSRWrri, MVT::v4i16);
return Result;
}
}
@@ -55199,7 +55216,7 @@ SDNode *Select_X86ISD_PINSRW_v8i16(const SDValue &N) {
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_98(N, X86::PINSRWrmi, MVT::v8i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_100(N, X86::PINSRWrmi, MVT::v8i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -55215,7 +55232,7 @@ SDNode *Select_X86ISD_PINSRW_v8i16(const SDValue &N) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_97(N, X86::PINSRWrri, MVT::v8i16);
+ SDNode *Result = Emit_99(N, X86::PINSRWrri, MVT::v8i16);
return Result;
}
}
@@ -55293,7 +55310,7 @@ SDNode *Select_X86ISD_PTEST(const SDValue &N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_278(N, X86::PTESTrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_281(N, X86::PTESTrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -55304,7 +55321,7 @@ SDNode *Select_X86ISD_PTEST(const SDValue &N) {
// Emits: (PTESTrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDNode *Result = Emit_255(N, X86::PTESTrr);
+ SDNode *Result = Emit_258(N, X86::PTESTrr);
return Result;
}
@@ -55312,7 +55329,7 @@ SDNode *Select_X86ISD_PTEST(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_299(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_302(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Chain);
Chain = SDValue(ResNode, 0);
@@ -55329,11 +55346,11 @@ DISABLE_INLINE SDNode *Emit_299(const SDValue &N, unsigned Opc0) {
return ResNode;
}
SDNode *Select_X86ISD_RDTSC_DAG(const SDValue &N) {
- SDNode *Result = Emit_299(N, X86::RDTSC);
+ SDNode *Result = Emit_302(N, X86::RDTSC);
return Result;
}
-DISABLE_INLINE SDNode *Emit_300(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_303(const SDValue &N, unsigned Opc0) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue InFlag = N.getOperand(2);
@@ -55359,7 +55376,7 @@ SDNode *Select_X86ISD_REP_MOVS(const SDValue &N) {
// Emits: (REP_MOVSB:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_300(N, X86::REP_MOVSB);
+ SDNode *Result = Emit_303(N, X86::REP_MOVSB);
return Result;
}
@@ -55367,7 +55384,7 @@ SDNode *Select_X86ISD_REP_MOVS(const SDValue &N) {
// Emits: (REP_MOVSW:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
- SDNode *Result = Emit_300(N, X86::REP_MOVSW);
+ SDNode *Result = Emit_303(N, X86::REP_MOVSW);
return Result;
}
@@ -55375,7 +55392,7 @@ SDNode *Select_X86ISD_REP_MOVS(const SDValue &N) {
// Emits: (REP_MOVSD:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1)->getVT() == MVT::i32) {
- SDNode *Result = Emit_300(N, X86::REP_MOVSD);
+ SDNode *Result = Emit_303(N, X86::REP_MOVSD);
return Result;
}
@@ -55383,7 +55400,7 @@ SDNode *Select_X86ISD_REP_MOVS(const SDValue &N) {
// Emits: (REP_MOVSQ:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1)->getVT() == MVT::i64) {
- SDNode *Result = Emit_300(N, X86::REP_MOVSQ);
+ SDNode *Result = Emit_303(N, X86::REP_MOVSQ);
return Result;
}
@@ -55399,7 +55416,7 @@ SDNode *Select_X86ISD_REP_STOS(const SDValue &N) {
// Emits: (REP_STOSB:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_300(N, X86::REP_STOSB);
+ SDNode *Result = Emit_303(N, X86::REP_STOSB);
return Result;
}
@@ -55407,7 +55424,7 @@ SDNode *Select_X86ISD_REP_STOS(const SDValue &N) {
// Emits: (REP_STOSW:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
- SDNode *Result = Emit_300(N, X86::REP_STOSW);
+ SDNode *Result = Emit_303(N, X86::REP_STOSW);
return Result;
}
@@ -55415,7 +55432,7 @@ SDNode *Select_X86ISD_REP_STOS(const SDValue &N) {
// Emits: (REP_STOSD:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1)->getVT() == MVT::i32) {
- SDNode *Result = Emit_300(N, X86::REP_STOSD);
+ SDNode *Result = Emit_303(N, X86::REP_STOSD);
return Result;
}
@@ -55423,7 +55440,7 @@ SDNode *Select_X86ISD_REP_STOS(const SDValue &N) {
// Emits: (REP_STOSQ:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1)->getVT() == MVT::i64) {
- SDNode *Result = Emit_300(N, X86::REP_STOSQ);
+ SDNode *Result = Emit_303(N, X86::REP_STOSQ);
return Result;
}
@@ -55431,7 +55448,7 @@ SDNode *Select_X86ISD_REP_STOS(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_301(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_304(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
@@ -55448,7 +55465,7 @@ DISABLE_INLINE SDNode *Emit_301(const SDValue &N, unsigned Opc0, unsigned NumInp
Ops0.push_back(InFlag);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
}
-DISABLE_INLINE SDNode *Emit_302(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_305(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
@@ -55478,7 +55495,7 @@ SDNode *Select_X86ISD_RET_FLAG(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_301(N, X86::RET, 1);
+ SDNode *Result = Emit_304(N, X86::RET, 1);
return Result;
}
}
@@ -55488,7 +55505,7 @@ SDNode *Select_X86ISD_RET_FLAG(const SDValue &N) {
// Emits: (RETI:isVoid (timm:i16):$amt)
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_302(N, X86::RETI, 1);
+ SDNode *Result = Emit_305(N, X86::RETI, 1);
return Result;
}
@@ -55496,7 +55513,7 @@ SDNode *Select_X86ISD_RET_FLAG(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_303(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_306(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
@@ -55516,7 +55533,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_303(N, X86::SETEr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETEr, MVT::i8);
return Result;
}
@@ -55524,7 +55541,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETNEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_303(N, X86::SETNEr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETNEr, MVT::i8);
return Result;
}
@@ -55532,7 +55549,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETLr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_303(N, X86::SETLr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETLr, MVT::i8);
return Result;
}
@@ -55540,7 +55557,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETGEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_303(N, X86::SETGEr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETGEr, MVT::i8);
return Result;
}
@@ -55548,7 +55565,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETLEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_303(N, X86::SETLEr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETLEr, MVT::i8);
return Result;
}
@@ -55556,7 +55573,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETGr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_303(N, X86::SETGr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETGr, MVT::i8);
return Result;
}
@@ -55564,7 +55581,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETBr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_303(N, X86::SETBr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETBr, MVT::i8);
return Result;
}
@@ -55572,7 +55589,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETAEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_303(N, X86::SETAEr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETAEr, MVT::i8);
return Result;
}
@@ -55580,7 +55597,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETBEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_303(N, X86::SETBEr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETBEr, MVT::i8);
return Result;
}
@@ -55588,7 +55605,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETAr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_303(N, X86::SETAr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETAr, MVT::i8);
return Result;
}
@@ -55596,7 +55613,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETSr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_303(N, X86::SETSr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETSr, MVT::i8);
return Result;
}
@@ -55604,7 +55621,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETNSr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_303(N, X86::SETNSr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETNSr, MVT::i8);
return Result;
}
@@ -55612,7 +55629,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETPr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_303(N, X86::SETPr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETPr, MVT::i8);
return Result;
}
@@ -55620,7 +55637,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETNPr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_303(N, X86::SETNPr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETNPr, MVT::i8);
return Result;
}
@@ -55628,7 +55645,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETOr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_303(N, X86::SETOr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETOr, MVT::i8);
return Result;
}
@@ -55636,7 +55653,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETNOr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_303(N, X86::SETNOr, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETNOr, MVT::i8);
return Result;
}
}
@@ -55651,7 +55668,22 @@ SDNode *Select_X86ISD_SETCC_CARRY_i8(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_303(N, X86::SETB_C8r, MVT::i8);
+ SDNode *Result = Emit_306(N, X86::SETB_C8r, MVT::i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_SETCC_CARRY_i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_306(N, X86::SETB_C16r, MVT::i16);
return Result;
}
}
@@ -55660,7 +55692,37 @@ SDNode *Select_X86ISD_SETCC_CARRY_i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_304(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+SDNode *Select_X86ISD_SETCC_CARRY_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_306(N, X86::SETB_C32r, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_SETCC_CARRY_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_306(N, X86::SETB_C64r, MVT::i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_307(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -55681,7 +55743,7 @@ SDNode *Select_X86ISD_SHLD_i16(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_285(N, X86::SHLD16rri8, MVT::i16);
+ SDNode *Result = Emit_288(N, X86::SHLD16rri8, MVT::i16);
return Result;
}
@@ -55689,7 +55751,7 @@ SDNode *Select_X86ISD_SHLD_i16(const SDValue &N) {
// Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHLD16rrCL, MVT::i16);
+ SDNode *Result = Emit_307(N, X86::SHLD16rrCL, MVT::i16);
return Result;
}
@@ -55707,7 +55769,7 @@ SDNode *Select_X86ISD_SHLD_i32(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_285(N, X86::SHLD32rri8, MVT::i32);
+ SDNode *Result = Emit_288(N, X86::SHLD32rri8, MVT::i32);
return Result;
}
@@ -55715,7 +55777,7 @@ SDNode *Select_X86ISD_SHLD_i32(const SDValue &N) {
// Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHLD32rrCL, MVT::i32);
+ SDNode *Result = Emit_307(N, X86::SHLD32rrCL, MVT::i32);
return Result;
}
@@ -55733,7 +55795,7 @@ SDNode *Select_X86ISD_SHLD_i64(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_285(N, X86::SHLD64rri8, MVT::i64);
+ SDNode *Result = Emit_288(N, X86::SHLD64rri8, MVT::i64);
return Result;
}
@@ -55741,7 +55803,7 @@ SDNode *Select_X86ISD_SHLD_i64(const SDValue &N) {
// Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHLD64rrCL, MVT::i64);
+ SDNode *Result = Emit_307(N, X86::SHLD64rrCL, MVT::i64);
return Result;
}
@@ -55759,7 +55821,7 @@ SDNode *Select_X86ISD_SHRD_i16(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_285(N, X86::SHRD16rri8, MVT::i16);
+ SDNode *Result = Emit_288(N, X86::SHRD16rri8, MVT::i16);
return Result;
}
@@ -55767,7 +55829,7 @@ SDNode *Select_X86ISD_SHRD_i16(const SDValue &N) {
// Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHRD16rrCL, MVT::i16);
+ SDNode *Result = Emit_307(N, X86::SHRD16rrCL, MVT::i16);
return Result;
}
@@ -55785,7 +55847,7 @@ SDNode *Select_X86ISD_SHRD_i32(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_285(N, X86::SHRD32rri8, MVT::i32);
+ SDNode *Result = Emit_288(N, X86::SHRD32rri8, MVT::i32);
return Result;
}
@@ -55793,7 +55855,7 @@ SDNode *Select_X86ISD_SHRD_i32(const SDValue &N) {
// Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHRD32rrCL, MVT::i32);
+ SDNode *Result = Emit_307(N, X86::SHRD32rrCL, MVT::i32);
return Result;
}
@@ -55811,7 +55873,7 @@ SDNode *Select_X86ISD_SHRD_i64(const SDValue &N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_285(N, X86::SHRD64rri8, MVT::i64);
+ SDNode *Result = Emit_288(N, X86::SHRD64rri8, MVT::i64);
return Result;
}
@@ -55819,7 +55881,7 @@ SDNode *Select_X86ISD_SHRD_i64(const SDValue &N) {
// Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHRD64rrCL, MVT::i64);
+ SDNode *Result = Emit_307(N, X86::SHRD64rrCL, MVT::i64);
return Result;
}
@@ -55827,7 +55889,7 @@ SDNode *Select_X86ISD_SHRD_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_305(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_308(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, N0);
@@ -55855,14 +55917,14 @@ SDNode *Select_X86ISD_SMUL_i16(const SDValue &N) {
// Emits: (IMUL16rmi8:i16 addr:iPTR:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_144(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_147(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (X86smul_flag:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2)
// Emits: (IMUL16rmi:i16 addr:iPTR:$src1, (imm:i16):$src2)
// Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_144(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_147(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -55904,7 +55966,7 @@ SDNode *Select_X86ISD_SMUL_i16(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_305(N, X86::ADD16rr, MVT::i16);
+ SDNode *Result = Emit_308(N, X86::ADD16rr, MVT::i16);
return Result;
}
}
@@ -55957,14 +56019,14 @@ SDNode *Select_X86ISD_SMUL_i32(const SDValue &N) {
// Emits: (IMUL32rmi8:i32 addr:iPTR:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_145(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_148(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (X86smul_flag:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2)
// Emits: (IMUL32rmi:i32 addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_145(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_148(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -56006,7 +56068,7 @@ SDNode *Select_X86ISD_SMUL_i32(const SDValue &N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_305(N, X86::ADD32rr, MVT::i32);
+ SDNode *Result = Emit_308(N, X86::ADD32rr, MVT::i32);
return Result;
}
}
@@ -56060,7 +56122,7 @@ SDNode *Select_X86ISD_SMUL_i64(const SDValue &N) {
// Emits: (IMUL64rmi8:i64 addr:iPTR:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_146(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_149(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -56068,7 +56130,7 @@ SDNode *Select_X86ISD_SMUL_i64(const SDValue &N) {
// Emits: (IMUL64rmi32:i64 addr:iPTR:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_146(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_149(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -56346,7 +56408,7 @@ SDNode *Select_X86ISD_SUB_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_306(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_309(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -56378,7 +56440,7 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_306(N, X86::TCRETURNdi64, 2);
+ SDNode *Result = Emit_309(N, X86::TCRETURNdi64, 2);
return Result;
}
}
@@ -56390,7 +56452,7 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_306(N, X86::TCRETURNdi64, 2);
+ SDNode *Result = Emit_309(N, X86::TCRETURNdi64, 2);
return Result;
}
}
@@ -56402,7 +56464,7 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, X86::TCRETURNdi, 2);
+ SDNode *Result = Emit_309(N, X86::TCRETURNdi, 2);
return Result;
}
}
@@ -56414,7 +56476,7 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
SDValue N2 = N.getOperand(2);
if (N2.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, X86::TCRETURNdi, 2);
+ SDNode *Result = Emit_309(N, X86::TCRETURNdi, 2);
return Result;
}
}
@@ -56425,7 +56487,7 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
// Emits: (TCRETURNri64:isVoid GR64:i64:$dst, (imm:i32):$off)
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_306(N, X86::TCRETURNri64, 2);
+ SDNode *Result = Emit_309(N, X86::TCRETURNri64, 2);
return Result;
}
@@ -56433,7 +56495,7 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
// Emits: (TCRETURNri:isVoid GR32:i32:$dst, (imm:i32):$off)
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, X86::TCRETURNri, 2);
+ SDNode *Result = Emit_309(N, X86::TCRETURNri, 2);
return Result;
}
}
@@ -56442,7 +56504,7 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_307(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3) {
+DISABLE_INLINE SDNode *Emit_310(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
@@ -56479,7 +56541,7 @@ SDNode *Select_X86ISD_TLSADDR(const SDValue &N) {
SDValue CPTmpN1_3;
if (SelectTLSADDRAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_307(N, X86::TLS_addr32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
+ SDNode *Result = Emit_310(N, X86::TLS_addr32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
return Result;
}
}
@@ -56496,7 +56558,7 @@ SDNode *Select_X86ISD_TLSADDR(const SDValue &N) {
SDValue CPTmpN1_3;
if (SelectTLSADDRAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_307(N, X86::TLS_addr64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
+ SDNode *Result = Emit_310(N, X86::TLS_addr64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
return Result;
}
}
@@ -56528,7 +56590,7 @@ SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_278(N, X86::Int_UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_281(N, X86::Int_UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -56555,7 +56617,7 @@ SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_278(N, X86::Int_UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_281(N, X86::Int_UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -56570,7 +56632,7 @@ SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_255(N, X86::Int_UCOMISSrr);
+ SDNode *Result = Emit_258(N, X86::Int_UCOMISSrr);
return Result;
}
}
@@ -56582,7 +56644,7 @@ SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_255(N, X86::Int_UCOMISDrr);
+ SDNode *Result = Emit_258(N, X86::Int_UCOMISDrr);
return Result;
}
}
@@ -56591,7 +56653,7 @@ SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_308(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_311(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
@@ -56615,7 +56677,7 @@ SDNode *Select_X86ISD_VASTART_SAVE_XMM_REGS(const SDValue &N) {
if (N2.getOpcode() == ISD::Constant) {
SDValue N3 = N.getOperand(3);
if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_308(N, X86::VASTART_SAVE_XMM_REGS, 3);
+ SDNode *Result = Emit_311(N, X86::VASTART_SAVE_XMM_REGS, 3);
return Result;
}
}
@@ -56629,7 +56691,7 @@ SDNode *Select_X86ISD_VSHL_v1i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::MMX_PSLLQri, MVT::v1i64);
+ SDNode *Result = Emit_95(N, X86::MMX_PSLLQri, MVT::v1i64);
return Result;
}
@@ -56643,7 +56705,7 @@ SDNode *Select_X86ISD_VSHL_v2i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_291(N, X86::PSLLDQri, MVT::v2i64);
+ SDNode *Result = Emit_294(N, X86::PSLLDQri, MVT::v2i64);
return Result;
}
}
@@ -56657,7 +56719,7 @@ SDNode *Select_X86ISD_VSRL_v1i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::MMX_PSRLQri, MVT::v1i64);
+ SDNode *Result = Emit_95(N, X86::MMX_PSRLQri, MVT::v1i64);
return Result;
}
@@ -56671,7 +56733,7 @@ SDNode *Select_X86ISD_VSRL_v2i64(const SDValue &N) {
SDValue N1 = N.getOperand(1);
if (N1.getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_291(N, X86::PSRLDQri, MVT::v2i64);
+ SDNode *Result = Emit_294(N, X86::PSRLDQri, MVT::v2i64);
return Result;
}
}
@@ -56680,7 +56742,7 @@ SDNode *Select_X86ISD_VSRL_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_309(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_312(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N.getOperand(0);
SDValue N1 = N.getOperand(1);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
@@ -56695,7 +56757,7 @@ SDNode *Select_X86ISD_VZEXT_LOAD_v2i64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_309(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_312(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -56712,7 +56774,7 @@ SDNode *Select_X86ISD_VZEXT_LOAD_v2f64(const SDValue &N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_309(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_312(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -56720,7 +56782,7 @@ SDNode *Select_X86ISD_VZEXT_LOAD_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_310(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_313(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Chain00 = N00.getOperand(0);
@@ -56733,7 +56795,7 @@ DISABLE_INLINE SDNode *Emit_310(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_311(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_314(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N.getOperand(0);
SDValue Tmp1(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, N0, Tmp1);
@@ -56763,7 +56825,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_310(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_313(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -56792,7 +56854,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_310(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_313(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -56808,7 +56870,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(const SDValue &N) {
if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
SDValue N00 = N0.getOperand(0);
if (N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_160(N, X86::MMX_MOVZDI2PDIrr, MVT::v2i32);
+ SDNode *Result = Emit_163(N, X86::MMX_MOVZDI2PDIrr, MVT::v2i32);
return Result;
}
}
@@ -56817,11 +56879,11 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(const SDValue &N) {
// Pattern: (X86vzmovl:v2i32 VR64:v2i32:$src)
// Emits: (MMX_PUNPCKLDQrr:v2i32 VR64:v8i8:$src, (MMX_V_SET0:v8i8))
// Pattern complexity = 18 cost = 2 size = 6
- SDNode *Result = Emit_311(N, X86::MMX_V_SET0, X86::MMX_PUNPCKLDQrr, MVT::v8i8, MVT::v2i32);
+ SDNode *Result = Emit_314(N, X86::MMX_V_SET0, X86::MMX_PUNPCKLDQrr, MVT::v8i8, MVT::v2i32);
return Result;
}
-DISABLE_INLINE SDNode *Emit_312(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_315(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N.getOperand(0);
SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, N0);
@@ -56851,7 +56913,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_313(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -56880,7 +56942,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
// Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if (N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_313(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
@@ -56888,7 +56950,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
// Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_313(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -56911,7 +56973,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -56926,7 +56988,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
SDValue N00 = N0.getOperand(0);
if (N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_160(N, X86::MOVZDI2PDIrr, MVT::v4i32);
+ SDNode *Result = Emit_163(N, X86::MOVZDI2PDIrr, MVT::v4i32);
return Result;
}
}
@@ -56936,7 +56998,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
// Emits: (MOVLPSrr:v4i32 (V_SET0:v16i8), VR128:v16i8:$src)
// Pattern complexity = 18 cost = 2 size = 6
if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4i32);
+ SDNode *Result = Emit_315(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4i32);
return Result;
}
@@ -56970,7 +57032,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::i64) {
- SDNode *Result = Emit_310(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_313(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57000,7 +57062,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
// Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if (N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_310(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_313(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
@@ -57008,7 +57070,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
// Emits: (MOVZPQILo2PQIrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if (N00.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_310(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_313(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57034,7 +57096,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -57057,7 +57119,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -57073,7 +57135,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
SDValue N00 = N0.getOperand(0);
if (N00.getValueType() == MVT::i64) {
- SDNode *Result = Emit_160(N, X86::MOVZQI2PQIrr, MVT::v2i64);
+ SDNode *Result = Emit_163(N, X86::MOVZQI2PQIrr, MVT::v2i64);
return Result;
}
}
@@ -57090,7 +57152,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_313(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_316(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N.getOperand(0);
SDValue N00 = N0.getOperand(0);
SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
@@ -57122,7 +57184,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::f32) {
- SDNode *Result = Emit_310(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_313(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57146,7 +57208,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -57162,7 +57224,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(const SDValue &N) {
if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
SDValue N00 = N0.getOperand(0);
if (N00.getValueType() == MVT::f32) {
- SDNode *Result = Emit_313(N, X86::V_SET0, X86::MOVLSS2PSrr, MVT::v16i8, MVT::v4f32);
+ SDNode *Result = Emit_316(N, X86::V_SET0, X86::MOVLSS2PSrr, MVT::v16i8, MVT::v4f32);
return Result;
}
}
@@ -57171,7 +57233,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(const SDValue &N) {
// Pattern: (X86vzmovl:v4f32 VR128:v4f32:$src)
// Emits: (MOVLPSrr:v4f32 (V_SET0:v16i8), VR128:v16i8:$src)
// Pattern complexity = 18 cost = 2 size = 6
- SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4f32);
+ SDNode *Result = Emit_315(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4f32);
return Result;
}
@@ -57205,7 +57267,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_310(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_313(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57234,7 +57296,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_310(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_313(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57256,7 +57318,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_77(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_78(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -57272,7 +57334,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
SDValue N00 = N0.getOperand(0);
if (N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_313(N, X86::V_SET0, X86::MOVLSD2PDrr, MVT::v16i8, MVT::v2f64);
+ SDNode *Result = Emit_316(N, X86::V_SET0, X86::MOVLSD2PDrr, MVT::v16i8, MVT::v2f64);
return Result;
}
}
@@ -59217,6 +59279,12 @@ SDNode *SelectCode(SDValue N) {
switch (NVT) {
case MVT::i8:
return Select_X86ISD_SETCC_CARRY_i8(N);
+ case MVT::i16:
+ return Select_X86ISD_SETCC_CARRY_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_SETCC_CARRY_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_SETCC_CARRY_i64(N);
default:
break;
}
diff --git a/libclamav/c++/X86GenInstrInfo.inc b/libclamav/c++/X86GenInstrInfo.inc
index ee4f15c..52fe191 100644
--- a/libclamav/c++/X86GenInstrInfo.inc
+++ b/libclamav/c++/X86GenInstrInfo.inc
@@ -83,185 +83,194 @@ static const TargetOperandInfo OperandInfo15[] = { { 0, 0|(1<<TOI::LookupPtrRegC
static const TargetOperandInfo OperandInfo16[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo17[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo18[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo19[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo20[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo21[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo22[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo23[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo24[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR128RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo25[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo26[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo27[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo28[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo29[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo30[] = { { X86::RSTRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo31[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo32[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo33[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo34[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo35[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo36[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo37[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo38[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, };
-static const TargetOperandInfo OperandInfo39[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
-static const TargetOperandInfo OperandInfo40[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
-static const TargetOperandInfo OperandInfo41[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
-static const TargetOperandInfo OperandInfo42[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
-static const TargetOperandInfo OperandInfo43[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo44[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo45[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo46[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo47[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo48[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo49[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo50[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo51[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
-static const TargetOperandInfo OperandInfo52[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
-static const TargetOperandInfo OperandInfo53[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo54[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo55[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo56[] = { { X86::GR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo57[] = { { X86::GR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo58[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo59[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo60[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP80RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo61[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo62[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo63[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo64[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo65[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo66[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo67[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo68[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo69[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo70[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo71[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo72[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo73[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo74[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo75[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo76[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo77[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo78[] = { { X86::FR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo79[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo80[] = { { X86::FR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo81[] = { { X86::FR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo82[] = { { X86::FR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo83[] = { { X86::FR32RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo84[] = { { X86::FR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo85[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo86[] = { { X86::GR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo87[] = { { X86::GR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo19[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo20[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo21[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo22[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo23[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo24[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo25[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo26[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo27[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo28[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo29[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo30[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo31[] = { { X86::RSTRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo32[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo33[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo34[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo35[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo36[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo37[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo38[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo39[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo40[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo41[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo42[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo43[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo44[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo45[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo46[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo47[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo48[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo49[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo50[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo51[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo52[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo53[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo54[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo55[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo56[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo57[] = { { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo58[] = { { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo59[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo60[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo61[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo62[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo63[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo64[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo65[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo66[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo67[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo68[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo69[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo70[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo71[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo72[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo73[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo74[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo75[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo76[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo77[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo78[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo79[] = { { X86::GR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo80[] = { { X86::FR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo81[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo82[] = { { X86::FR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo83[] = { { X86::FR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo84[] = { { X86::FR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo85[] = { { X86::FR32RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo86[] = { { X86::FR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo87[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo88[] = { { X86::GR64RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo89[] = { { X86::GR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo90[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
-static const TargetOperandInfo OperandInfo91[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
-static const TargetOperandInfo OperandInfo92[] = { { X86::GR16RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo93[] = { { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo94[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo95[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo96[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo97[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo98[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo99[] = { { X86::RFP32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo100[] = { { X86::RFP64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo101[] = { { X86::RFP80RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo102[] = { { X86::FR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo103[] = { { X86::FR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo104[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo105[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo106[] = { { X86::RFP32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo107[] = { { X86::RFP64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo108[] = { { X86::RFP80RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo109[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo110[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo111[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo112[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo113[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo114[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo115[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo116[] = { { X86::VR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo117[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo118[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo119[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo120[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo121[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo122[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo123[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo124[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo125[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo126[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo127[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo128[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo129[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo130[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo131[] = { { X86::VR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo132[] = { { X86::VR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo133[] = { { X86::FR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo134[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo135[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo136[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo137[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo138[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo139[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo140[] = { { X86::VR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo141[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo142[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo143[] = { { X86::VR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo144[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo145[] = { { X86::GR16RegClassID, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo146[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo147[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo148[] = { { X86::GR64RegClassID, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo149[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo150[] = { { X86::VR128RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo151[] = { { X86::GR64_NOREXRegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8_NOREXRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo152[] = { { X86::GR8_NOREXRegClassID, 0, 0 }, { X86::GR64_NOREXRegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo153[] = { { X86::GR8_NOREXRegClassID, 0, 0 }, { X86::GR8_NOREXRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo154[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo155[] = { { X86::VR128RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo156[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo157[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo158[] = { { X86::FR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo159[] = { { X86::FR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo160[] = { { X86::VR128RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo161[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo162[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo163[] = { { X86::VR128RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo164[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo165[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo166[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo167[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo168[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo169[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo170[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo171[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo172[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo173[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo174[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo175[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo176[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo177[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo178[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo179[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo180[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo181[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo182[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo183[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo184[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo185[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo186[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo187[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo188[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo189[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo190[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo191[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo192[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo193[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo194[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo195[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo196[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo197[] = { { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo90[] = { { X86::GR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo91[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo92[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo93[] = { { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo94[] = { { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo95[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo96[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo97[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo98[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo99[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo100[] = { { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo101[] = { { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo102[] = { { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo103[] = { { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo104[] = { { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo105[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo106[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo107[] = { { X86::RFP32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo108[] = { { X86::RFP64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo109[] = { { X86::RFP80RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo110[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo111[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo112[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo113[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo114[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo115[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo116[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo117[] = { { X86::VR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo118[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo119[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo120[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo121[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo122[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo123[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo124[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo125[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo126[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo127[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo128[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo129[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo130[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo131[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo132[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo133[] = { { X86::VR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo134[] = { { X86::VR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo135[] = { { X86::FR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo136[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo137[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo138[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo139[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo140[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo141[] = { { X86::VR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo142[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo143[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo144[] = { { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo145[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo146[] = { { X86::GR16RegClassID, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo147[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo148[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo149[] = { { X86::CONTROL_REG_32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo150[] = { { X86::DEBUG_REGRegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo151[] = { { X86::GR32RegClassID, 0, 0 }, { X86::CONTROL_REG_32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo152[] = { { X86::GR32RegClassID, 0, 0 }, { X86::DEBUG_REGRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo153[] = { { X86::CONTROL_REG_64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo154[] = { { X86::DEBUG_REGRegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo155[] = { { X86::GR64RegClassID, 0, 0 }, { X86::CONTROL_REG_64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo156[] = { { X86::GR64RegClassID, 0, 0 }, { X86::DEBUG_REGRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo157[] = { { X86::GR64RegClassID, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo158[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo159[] = { { X86::VR128RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo160[] = { { X86::GR64_NOREXRegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8_NOREXRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo161[] = { { X86::GR8_NOREXRegClassID, 0, 0 }, { X86::GR64_NOREXRegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo162[] = { { X86::GR8_NOREXRegClassID, 0, 0 }, { X86::GR8_NOREXRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo163[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo164[] = { { X86::VR128RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo165[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo166[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo167[] = { { X86::FR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo168[] = { { X86::FR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo169[] = { { X86::VR128RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo170[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo171[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo172[] = { { X86::VR128RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo173[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo174[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo175[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo176[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo177[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo178[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo179[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo180[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo181[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo182[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo183[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo184[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo185[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo186[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo187[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo188[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo189[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo190[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo191[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo192[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo193[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo194[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo195[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo196[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo197[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo198[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo199[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo200[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo201[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo202[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo203[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo204[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo205[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo206[] = { { X86::VR128RegClassID, 0, 0 }, };
static const TargetInstrDesc X86Insts[] = {
{ 0, 0, 0, 0, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #0 = PHI
@@ -270,11 +279,11 @@ static const TargetInstrDesc X86Insts[] = {
{ 3, 1, 0, 0, "EH_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #3 = EH_LABEL
{ 4, 1, 0, 0, "GC_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #4 = GC_LABEL
{ 5, 0, 0, 0, "KILL", 0|(1<<TID::Variadic), 0, NULL, NULL, NULL, 0 }, // Inst #5 = KILL
- { 6, 3, 1, 0, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo75 }, // Inst #6 = EXTRACT_SUBREG
- { 7, 4, 1, 0, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo115 }, // Inst #7 = INSERT_SUBREG
+ { 6, 3, 1, 0, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo76 }, // Inst #6 = EXTRACT_SUBREG
+ { 7, 4, 1, 0, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo116 }, // Inst #7 = INSERT_SUBREG
{ 8, 1, 1, 0, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #8 = IMPLICIT_DEF
- { 9, 4, 1, 0, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo193 }, // Inst #9 = SUBREG_TO_REG
- { 10, 3, 1, 0, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo75 }, // Inst #10 = COPY_TO_REGCLASS
+ { 9, 4, 1, 0, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo202 }, // Inst #9 = SUBREG_TO_REG
+ { 10, 3, 1, 0, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo76 }, // Inst #10 = COPY_TO_REGCLASS
{ 11, 0, 0, 0, "ABS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(225<<24), NULL, NULL, NULL, 0 }, // Inst #11 = ABS_F
{ 12, 2, 1, 0, "ABS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #12 = ABS_Fp32
{ 13, 2, 1, 0, "ABS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #13 = ABS_Fp64
@@ -287,2231 +296,2496 @@ static const TargetInstrDesc X86Insts[] = {
{ 20, 3, 1, 0, "ADC16ri8", 0, 0|18|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #20 = ADC16ri8
{ 21, 7, 1, 0, "ADC16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #21 = ADC16rm
{ 22, 3, 1, 0, "ADC16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #22 = ADC16rr
- { 23, 1, 0, 0, "ADC32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #23 = ADC32i32
- { 24, 6, 0, 0, "ADC32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #24 = ADC32mi
- { 25, 6, 0, 0, "ADC32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #25 = ADC32mi8
- { 26, 6, 0, 0, "ADC32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #26 = ADC32mr
- { 27, 3, 1, 0, "ADC32ri", 0, 0|18|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #27 = ADC32ri
- { 28, 3, 1, 0, "ADC32ri8", 0, 0|18|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #28 = ADC32ri8
- { 29, 7, 1, 0, "ADC32rm", 0|(1<<TID::MayLoad), 0|6|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #29 = ADC32rm
- { 30, 3, 1, 0, "ADC32rr", 0|(1<<TID::Commutable), 0|3|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #30 = ADC32rr
- { 31, 1, 0, 0, "ADC64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #31 = ADC64i32
- { 32, 6, 0, 0, "ADC64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #32 = ADC64mi32
- { 33, 6, 0, 0, "ADC64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #33 = ADC64mi8
- { 34, 6, 0, 0, "ADC64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #34 = ADC64mr
- { 35, 3, 1, 0, "ADC64ri32", 0, 0|18|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #35 = ADC64ri32
- { 36, 3, 1, 0, "ADC64ri8", 0, 0|18|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #36 = ADC64ri8
- { 37, 7, 1, 0, "ADC64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #37 = ADC64rm
- { 38, 3, 1, 0, "ADC64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #38 = ADC64rr
- { 39, 1, 0, 0, "ADC8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(20<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #39 = ADC8i8
- { 40, 6, 0, 0, "ADC8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #40 = ADC8mi
- { 41, 6, 0, 0, "ADC8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #41 = ADC8mr
- { 42, 3, 1, 0, "ADC8ri", 0, 0|18|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #42 = ADC8ri
- { 43, 7, 1, 0, "ADC8rm", 0|(1<<TID::MayLoad), 0|6|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #43 = ADC8rm
- { 44, 3, 1, 0, "ADC8rr", 0|(1<<TID::Commutable), 0|3|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #44 = ADC8rr
- { 45, 1, 0, 0, "ADD16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #45 = ADD16i16
- { 46, 6, 0, 0, "ADD16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #46 = ADD16mi
- { 47, 6, 0, 0, "ADD16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #47 = ADD16mi8
- { 48, 6, 0, 0, "ADD16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #48 = ADD16mr
- { 49, 3, 1, 0, "ADD16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #49 = ADD16mrmrr
- { 50, 3, 1, 0, "ADD16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #50 = ADD16ri
- { 51, 3, 1, 0, "ADD16ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #51 = ADD16ri8
- { 52, 7, 1, 0, "ADD16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #52 = ADD16rm
- { 53, 3, 1, 0, "ADD16rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #53 = ADD16rr
- { 54, 1, 0, 0, "ADD32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #54 = ADD32i32
- { 55, 6, 0, 0, "ADD32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #55 = ADD32mi
- { 56, 6, 0, 0, "ADD32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #56 = ADD32mi8
- { 57, 6, 0, 0, "ADD32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #57 = ADD32mr
- { 58, 3, 1, 0, "ADD32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #58 = ADD32mrmrr
- { 59, 3, 1, 0, "ADD32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #59 = ADD32ri
- { 60, 3, 1, 0, "ADD32ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #60 = ADD32ri8
- { 61, 7, 1, 0, "ADD32rm", 0|(1<<TID::MayLoad), 0|6|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #61 = ADD32rm
- { 62, 3, 1, 0, "ADD32rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #62 = ADD32rr
- { 63, 1, 0, 0, "ADD64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #63 = ADD64i32
- { 64, 6, 0, 0, "ADD64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #64 = ADD64mi32
- { 65, 6, 0, 0, "ADD64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #65 = ADD64mi8
- { 66, 6, 0, 0, "ADD64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #66 = ADD64mr
- { 67, 3, 1, 0, "ADD64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #67 = ADD64mrmrr
- { 68, 3, 1, 0, "ADD64ri32", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #68 = ADD64ri32
- { 69, 3, 1, 0, "ADD64ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #69 = ADD64ri8
- { 70, 7, 1, 0, "ADD64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #70 = ADD64rm
- { 71, 3, 1, 0, "ADD64rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #71 = ADD64rr
- { 72, 1, 0, 0, "ADD8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(4<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #72 = ADD8i8
- { 73, 6, 0, 0, "ADD8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #73 = ADD8mi
- { 74, 6, 0, 0, "ADD8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4, NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #74 = ADD8mr
- { 75, 3, 1, 0, "ADD8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #75 = ADD8mrmrr
- { 76, 3, 1, 0, "ADD8ri", 0, 0|16|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #76 = ADD8ri
- { 77, 7, 1, 0, "ADD8rm", 0|(1<<TID::MayLoad), 0|6|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #77 = ADD8rm
- { 78, 3, 1, 0, "ADD8rr", 0|(1<<TID::Commutable), 0|3, NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #78 = ADD8rr
- { 79, 7, 1, 0, "ADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #79 = ADDPDrm
- { 80, 3, 1, 0, "ADDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #80 = ADDPDrr
- { 81, 7, 1, 0, "ADDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #81 = ADDPSrm
- { 82, 3, 1, 0, "ADDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #82 = ADDPSrr
- { 83, 7, 1, 0, "ADDSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #83 = ADDSDrm
- { 84, 7, 1, 0, "ADDSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #84 = ADDSDrm_Int
- { 85, 3, 1, 0, "ADDSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #85 = ADDSDrr
- { 86, 3, 1, 0, "ADDSDrr_Int", 0, 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #86 = ADDSDrr_Int
- { 87, 7, 1, 0, "ADDSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #87 = ADDSSrm
- { 88, 7, 1, 0, "ADDSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #88 = ADDSSrm_Int
- { 89, 3, 1, 0, "ADDSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #89 = ADDSSrr
- { 90, 3, 1, 0, "ADDSSrr_Int", 0, 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #90 = ADDSSrr_Int
- { 91, 7, 1, 0, "ADDSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #91 = ADDSUBPDrm
- { 92, 3, 1, 0, "ADDSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #92 = ADDSUBPDrr
- { 93, 7, 1, 0, "ADDSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #93 = ADDSUBPSrm
- { 94, 3, 1, 0, "ADDSUBPSrr", 0, 0|5|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #94 = ADDSUBPSrr
- { 95, 5, 0, 0, "ADD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #95 = ADD_F32m
- { 96, 5, 0, 0, "ADD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #96 = ADD_F64m
- { 97, 5, 0, 0, "ADD_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #97 = ADD_FI16m
- { 98, 5, 0, 0, "ADD_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #98 = ADD_FI32m
- { 99, 1, 0, 0, "ADD_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #99 = ADD_FPrST0
- { 100, 1, 0, 0, "ADD_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #100 = ADD_FST0r
- { 101, 3, 1, 0, "ADD_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo31 }, // Inst #101 = ADD_Fp32
- { 102, 7, 1, 0, "ADD_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #102 = ADD_Fp32m
- { 103, 3, 1, 0, "ADD_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #103 = ADD_Fp64
- { 104, 7, 1, 0, "ADD_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #104 = ADD_Fp64m
- { 105, 7, 1, 0, "ADD_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #105 = ADD_Fp64m32
- { 106, 3, 1, 0, "ADD_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #106 = ADD_Fp80
- { 107, 7, 1, 0, "ADD_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #107 = ADD_Fp80m32
- { 108, 7, 1, 0, "ADD_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #108 = ADD_Fp80m64
- { 109, 7, 1, 0, "ADD_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #109 = ADD_FpI16m32
- { 110, 7, 1, 0, "ADD_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #110 = ADD_FpI16m64
- { 111, 7, 1, 0, "ADD_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #111 = ADD_FpI16m80
- { 112, 7, 1, 0, "ADD_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #112 = ADD_FpI32m32
- { 113, 7, 1, 0, "ADD_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #113 = ADD_FpI32m64
- { 114, 7, 1, 0, "ADD_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #114 = ADD_FpI32m80
- { 115, 1, 0, 0, "ADD_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #115 = ADD_FrST0
- { 116, 1, 0, 0, "ADJCALLSTACKDOWN32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo5 }, // Inst #116 = ADJCALLSTACKDOWN32
- { 117, 1, 0, 0, "ADJCALLSTACKDOWN64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo5 }, // Inst #117 = ADJCALLSTACKDOWN64
- { 118, 2, 0, 0, "ADJCALLSTACKUP32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo37 }, // Inst #118 = ADJCALLSTACKUP32
- { 119, 2, 0, 0, "ADJCALLSTACKUP64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo37 }, // Inst #119 = ADJCALLSTACKUP64
- { 120, 1, 0, 0, "AND16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #120 = AND16i16
- { 121, 6, 0, 0, "AND16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #121 = AND16mi
- { 122, 6, 0, 0, "AND16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #122 = AND16mi8
- { 123, 6, 0, 0, "AND16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #123 = AND16mr
- { 124, 3, 1, 0, "AND16ri", 0, 0|20|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #124 = AND16ri
- { 125, 3, 1, 0, "AND16ri8", 0, 0|20|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #125 = AND16ri8
- { 126, 7, 1, 0, "AND16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #126 = AND16rm
- { 127, 3, 1, 0, "AND16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #127 = AND16rr
- { 128, 1, 0, 0, "AND32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #128 = AND32i32
- { 129, 6, 0, 0, "AND32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #129 = AND32mi
- { 130, 6, 0, 0, "AND32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #130 = AND32mi8
- { 131, 6, 0, 0, "AND32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #131 = AND32mr
- { 132, 3, 1, 0, "AND32ri", 0, 0|20|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #132 = AND32ri
- { 133, 3, 1, 0, "AND32ri8", 0, 0|20|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #133 = AND32ri8
- { 134, 7, 1, 0, "AND32rm", 0|(1<<TID::MayLoad), 0|6|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #134 = AND32rm
- { 135, 3, 1, 0, "AND32rr", 0|(1<<TID::Commutable), 0|3|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #135 = AND32rr
- { 136, 1, 0, 0, "AND64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #136 = AND64i32
- { 137, 6, 0, 0, "AND64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #137 = AND64mi32
- { 138, 6, 0, 0, "AND64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #138 = AND64mi8
- { 139, 6, 0, 0, "AND64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #139 = AND64mr
- { 140, 3, 1, 0, "AND64ri32", 0, 0|20|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #140 = AND64ri32
- { 141, 3, 1, 0, "AND64ri8", 0, 0|20|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #141 = AND64ri8
- { 142, 7, 1, 0, "AND64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #142 = AND64rm
- { 143, 3, 1, 0, "AND64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #143 = AND64rr
- { 144, 1, 0, 0, "AND8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(36<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #144 = AND8i8
- { 145, 6, 0, 0, "AND8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #145 = AND8mi
- { 146, 6, 0, 0, "AND8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #146 = AND8mr
- { 147, 3, 1, 0, "AND8ri", 0, 0|20|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #147 = AND8ri
- { 148, 7, 1, 0, "AND8rm", 0|(1<<TID::MayLoad), 0|6|(34<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #148 = AND8rm
- { 149, 3, 1, 0, "AND8rr", 0|(1<<TID::Commutable), 0|3|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #149 = AND8rr
- { 150, 7, 1, 0, "ANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #150 = ANDNPDrm
- { 151, 3, 1, 0, "ANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #151 = ANDNPDrr
- { 152, 7, 1, 0, "ANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #152 = ANDNPSrm
- { 153, 3, 1, 0, "ANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #153 = ANDNPSrr
- { 154, 7, 1, 0, "ANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #154 = ANDPDrm
- { 155, 3, 1, 0, "ANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #155 = ANDPDrr
- { 156, 7, 1, 0, "ANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #156 = ANDPSrm
- { 157, 3, 1, 0, "ANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #157 = ANDPSrr
- { 158, 9, 2, 0, "ATOMADD6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #158 = ATOMADD6432
- { 159, 7, 1, 0, "ATOMAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #159 = ATOMAND16
- { 160, 7, 1, 0, "ATOMAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #160 = ATOMAND32
- { 161, 7, 1, 0, "ATOMAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #161 = ATOMAND64
- { 162, 9, 2, 0, "ATOMAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #162 = ATOMAND6432
- { 163, 7, 1, 0, "ATOMAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #163 = ATOMAND8
- { 164, 7, 1, 0, "ATOMMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #164 = ATOMMAX16
- { 165, 7, 1, 0, "ATOMMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #165 = ATOMMAX32
- { 166, 7, 1, 0, "ATOMMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #166 = ATOMMAX64
- { 167, 7, 1, 0, "ATOMMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #167 = ATOMMIN16
- { 168, 7, 1, 0, "ATOMMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #168 = ATOMMIN32
- { 169, 7, 1, 0, "ATOMMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #169 = ATOMMIN64
- { 170, 7, 1, 0, "ATOMNAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #170 = ATOMNAND16
- { 171, 7, 1, 0, "ATOMNAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #171 = ATOMNAND32
- { 172, 7, 1, 0, "ATOMNAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #172 = ATOMNAND64
- { 173, 9, 2, 0, "ATOMNAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #173 = ATOMNAND6432
- { 174, 7, 1, 0, "ATOMNAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #174 = ATOMNAND8
- { 175, 7, 1, 0, "ATOMOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #175 = ATOMOR16
- { 176, 7, 1, 0, "ATOMOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #176 = ATOMOR32
- { 177, 7, 1, 0, "ATOMOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #177 = ATOMOR64
- { 178, 9, 2, 0, "ATOMOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #178 = ATOMOR6432
- { 179, 7, 1, 0, "ATOMOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #179 = ATOMOR8
- { 180, 9, 2, 0, "ATOMSUB6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #180 = ATOMSUB6432
- { 181, 9, 2, 0, "ATOMSWAP6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #181 = ATOMSWAP6432
- { 182, 7, 1, 0, "ATOMUMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #182 = ATOMUMAX16
- { 183, 7, 1, 0, "ATOMUMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #183 = ATOMUMAX32
- { 184, 7, 1, 0, "ATOMUMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #184 = ATOMUMAX64
- { 185, 7, 1, 0, "ATOMUMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #185 = ATOMUMIN16
- { 186, 7, 1, 0, "ATOMUMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #186 = ATOMUMIN32
- { 187, 7, 1, 0, "ATOMUMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #187 = ATOMUMIN64
- { 188, 7, 1, 0, "ATOMXOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #188 = ATOMXOR16
- { 189, 7, 1, 0, "ATOMXOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #189 = ATOMXOR32
- { 190, 7, 1, 0, "ATOMXOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #190 = ATOMXOR64
- { 191, 9, 2, 0, "ATOMXOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #191 = ATOMXOR6432
- { 192, 7, 1, 0, "ATOMXOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #192 = ATOMXOR8
- { 193, 8, 1, 0, "BLENDPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #193 = BLENDPDrmi
- { 194, 4, 1, 0, "BLENDPDrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #194 = BLENDPDrri
- { 195, 8, 1, 0, "BLENDPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #195 = BLENDPSrmi
- { 196, 4, 1, 0, "BLENDPSrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #196 = BLENDPSrri
- { 197, 7, 1, 0, "BLENDVPDrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo23 }, // Inst #197 = BLENDVPDrm0
- { 198, 3, 1, 0, "BLENDVPDrr0", 0, 0|5|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #198 = BLENDVPDrr0
- { 199, 7, 1, 0, "BLENDVPSrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo23 }, // Inst #199 = BLENDVPSrm0
- { 200, 3, 1, 0, "BLENDVPSrr0", 0, 0|5|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #200 = BLENDVPSrr0
- { 201, 6, 1, 0, "BSF16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo45 }, // Inst #201 = BSF16rm
- { 202, 2, 1, 0, "BSF16rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #202 = BSF16rr
- { 203, 6, 1, 0, "BSF32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #203 = BSF32rm
- { 204, 2, 1, 0, "BSF32rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #204 = BSF32rr
- { 205, 6, 1, 0, "BSF64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #205 = BSF64rm
- { 206, 2, 1, 0, "BSF64rr", 0, 0|5|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #206 = BSF64rr
- { 207, 6, 1, 0, "BSR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo45 }, // Inst #207 = BSR16rm
- { 208, 2, 1, 0, "BSR16rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #208 = BSR16rr
- { 209, 6, 1, 0, "BSR32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #209 = BSR32rm
- { 210, 2, 1, 0, "BSR32rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #210 = BSR32rr
- { 211, 6, 1, 0, "BSR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #211 = BSR64rm
- { 212, 2, 1, 0, "BSR64rr", 0, 0|5|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #212 = BSR64rr
- { 213, 2, 1, 0, "BSWAP32r", 0, 0|2|(1<<8)|(200<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #213 = BSWAP32r
- { 214, 2, 1, 0, "BSWAP64r", 0, 0|2|(1<<8)|(1<<12)|(200<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #214 = BSWAP64r
- { 215, 6, 0, 0, "BT16mi8", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #215 = BT16mi8
- { 216, 2, 0, 0, "BT16ri8", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #216 = BT16ri8
- { 217, 2, 0, 0, "BT16rr", 0, 0|3|(1<<6)|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #217 = BT16rr
- { 218, 6, 0, 0, "BT32mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #218 = BT32mi8
- { 219, 2, 0, 0, "BT32ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #219 = BT32ri8
- { 220, 2, 0, 0, "BT32rr", 0, 0|3|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #220 = BT32rr
- { 221, 6, 0, 0, "BT64mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #221 = BT64mi8
- { 222, 2, 0, 0, "BT64ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #222 = BT64ri8
- { 223, 2, 0, 0, "BT64rr", 0, 0|3|(1<<8)|(1<<12)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #223 = BT64rr
- { 224, 5, 0, 0, "CALL32m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo29 }, // Inst #224 = CALL32m
- { 225, 1, 0, 0, "CALL32r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo56 }, // Inst #225 = CALL32r
- { 226, 5, 0, 0, "CALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo29 }, // Inst #226 = CALL64m
- { 227, 1, 0, 0, "CALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo5 }, // Inst #227 = CALL64pcrel32
- { 228, 1, 0, 0, "CALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo57 }, // Inst #228 = CALL64r
- { 229, 1, 0, 0, "CALLpcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo5 }, // Inst #229 = CALLpcrel32
- { 230, 0, 0, 0, "CBW", 0, 0|1|(1<<6)|(152<<24), ImplicitList11, ImplicitList12, NULL, 0 }, // Inst #230 = CBW
- { 231, 0, 0, 0, "CDQ", 0, 0|1|(153<<24), ImplicitList13, ImplicitList14, Barriers5, 0 }, // Inst #231 = CDQ
- { 232, 0, 0, 0, "CDQE", 0, 0|1|(1<<12)|(152<<24), ImplicitList13, ImplicitList15, NULL, 0 }, // Inst #232 = CDQE
- { 233, 0, 0, 0, "CHS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(224<<24), NULL, NULL, NULL, 0 }, // Inst #233 = CHS_F
- { 234, 2, 1, 0, "CHS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #234 = CHS_Fp32
- { 235, 2, 1, 0, "CHS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #235 = CHS_Fp64
- { 236, 2, 1, 0, "CHS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #236 = CHS_Fp80
- { 237, 5, 0, 0, "CLFLUSH", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #237 = CLFLUSH
- { 238, 7, 1, 0, "CMOVA16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #238 = CMOVA16rm
- { 239, 3, 1, 0, "CMOVA16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #239 = CMOVA16rr
- { 240, 7, 1, 0, "CMOVA32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #240 = CMOVA32rm
- { 241, 3, 1, 0, "CMOVA32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #241 = CMOVA32rr
- { 242, 7, 1, 0, "CMOVA64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #242 = CMOVA64rm
- { 243, 3, 1, 0, "CMOVA64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #243 = CMOVA64rr
- { 244, 7, 1, 0, "CMOVAE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #244 = CMOVAE16rm
- { 245, 3, 1, 0, "CMOVAE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #245 = CMOVAE16rr
- { 246, 7, 1, 0, "CMOVAE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #246 = CMOVAE32rm
- { 247, 3, 1, 0, "CMOVAE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #247 = CMOVAE32rr
- { 248, 7, 1, 0, "CMOVAE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #248 = CMOVAE64rm
- { 249, 3, 1, 0, "CMOVAE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #249 = CMOVAE64rr
- { 250, 7, 1, 0, "CMOVB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #250 = CMOVB16rm
- { 251, 3, 1, 0, "CMOVB16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #251 = CMOVB16rr
- { 252, 7, 1, 0, "CMOVB32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #252 = CMOVB32rm
- { 253, 3, 1, 0, "CMOVB32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #253 = CMOVB32rr
- { 254, 7, 1, 0, "CMOVB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #254 = CMOVB64rm
- { 255, 3, 1, 0, "CMOVB64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #255 = CMOVB64rr
- { 256, 7, 1, 0, "CMOVBE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #256 = CMOVBE16rm
- { 257, 3, 1, 0, "CMOVBE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #257 = CMOVBE16rr
- { 258, 7, 1, 0, "CMOVBE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #258 = CMOVBE32rm
- { 259, 3, 1, 0, "CMOVBE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #259 = CMOVBE32rr
- { 260, 7, 1, 0, "CMOVBE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #260 = CMOVBE64rm
- { 261, 3, 1, 0, "CMOVBE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #261 = CMOVBE64rr
- { 262, 1, 1, 0, "CMOVBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(208<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #262 = CMOVBE_F
- { 263, 3, 1, 0, "CMOVBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #263 = CMOVBE_Fp32
- { 264, 3, 1, 0, "CMOVBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #264 = CMOVBE_Fp64
- { 265, 3, 1, 0, "CMOVBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #265 = CMOVBE_Fp80
- { 266, 1, 1, 0, "CMOVB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #266 = CMOVB_F
- { 267, 3, 1, 0, "CMOVB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #267 = CMOVB_Fp32
- { 268, 3, 1, 0, "CMOVB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #268 = CMOVB_Fp64
- { 269, 3, 1, 0, "CMOVB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #269 = CMOVB_Fp80
- { 270, 7, 1, 0, "CMOVE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #270 = CMOVE16rm
- { 271, 3, 1, 0, "CMOVE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #271 = CMOVE16rr
- { 272, 7, 1, 0, "CMOVE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #272 = CMOVE32rm
- { 273, 3, 1, 0, "CMOVE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #273 = CMOVE32rr
- { 274, 7, 1, 0, "CMOVE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #274 = CMOVE64rm
- { 275, 3, 1, 0, "CMOVE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #275 = CMOVE64rr
- { 276, 1, 1, 0, "CMOVE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #276 = CMOVE_F
- { 277, 3, 1, 0, "CMOVE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #277 = CMOVE_Fp32
- { 278, 3, 1, 0, "CMOVE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #278 = CMOVE_Fp64
- { 279, 3, 1, 0, "CMOVE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #279 = CMOVE_Fp80
- { 280, 7, 1, 0, "CMOVG16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #280 = CMOVG16rm
- { 281, 3, 1, 0, "CMOVG16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #281 = CMOVG16rr
- { 282, 7, 1, 0, "CMOVG32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #282 = CMOVG32rm
- { 283, 3, 1, 0, "CMOVG32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #283 = CMOVG32rr
- { 284, 7, 1, 0, "CMOVG64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #284 = CMOVG64rm
- { 285, 3, 1, 0, "CMOVG64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #285 = CMOVG64rr
- { 286, 7, 1, 0, "CMOVGE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #286 = CMOVGE16rm
- { 287, 3, 1, 0, "CMOVGE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #287 = CMOVGE16rr
- { 288, 7, 1, 0, "CMOVGE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #288 = CMOVGE32rm
- { 289, 3, 1, 0, "CMOVGE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #289 = CMOVGE32rr
- { 290, 7, 1, 0, "CMOVGE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #290 = CMOVGE64rm
- { 291, 3, 1, 0, "CMOVGE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #291 = CMOVGE64rr
- { 292, 7, 1, 0, "CMOVL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #292 = CMOVL16rm
- { 293, 3, 1, 0, "CMOVL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #293 = CMOVL16rr
- { 294, 7, 1, 0, "CMOVL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #294 = CMOVL32rm
- { 295, 3, 1, 0, "CMOVL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #295 = CMOVL32rr
- { 296, 7, 1, 0, "CMOVL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #296 = CMOVL64rm
- { 297, 3, 1, 0, "CMOVL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #297 = CMOVL64rr
- { 298, 7, 1, 0, "CMOVLE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #298 = CMOVLE16rm
- { 299, 3, 1, 0, "CMOVLE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #299 = CMOVLE16rr
- { 300, 7, 1, 0, "CMOVLE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #300 = CMOVLE32rm
- { 301, 3, 1, 0, "CMOVLE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #301 = CMOVLE32rr
- { 302, 7, 1, 0, "CMOVLE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #302 = CMOVLE64rm
- { 303, 3, 1, 0, "CMOVLE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #303 = CMOVLE64rr
- { 304, 1, 1, 0, "CMOVNBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(208<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #304 = CMOVNBE_F
- { 305, 3, 1, 0, "CMOVNBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #305 = CMOVNBE_Fp32
- { 306, 3, 1, 0, "CMOVNBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #306 = CMOVNBE_Fp64
- { 307, 3, 1, 0, "CMOVNBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #307 = CMOVNBE_Fp80
- { 308, 1, 1, 0, "CMOVNB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #308 = CMOVNB_F
- { 309, 3, 1, 0, "CMOVNB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #309 = CMOVNB_Fp32
- { 310, 3, 1, 0, "CMOVNB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #310 = CMOVNB_Fp64
- { 311, 3, 1, 0, "CMOVNB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #311 = CMOVNB_Fp80
- { 312, 7, 1, 0, "CMOVNE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #312 = CMOVNE16rm
- { 313, 3, 1, 0, "CMOVNE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #313 = CMOVNE16rr
- { 314, 7, 1, 0, "CMOVNE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #314 = CMOVNE32rm
- { 315, 3, 1, 0, "CMOVNE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #315 = CMOVNE32rr
- { 316, 7, 1, 0, "CMOVNE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #316 = CMOVNE64rm
- { 317, 3, 1, 0, "CMOVNE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #317 = CMOVNE64rr
- { 318, 1, 1, 0, "CMOVNE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #318 = CMOVNE_F
- { 319, 3, 1, 0, "CMOVNE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #319 = CMOVNE_Fp32
- { 320, 3, 1, 0, "CMOVNE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #320 = CMOVNE_Fp64
- { 321, 3, 1, 0, "CMOVNE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #321 = CMOVNE_Fp80
- { 322, 7, 1, 0, "CMOVNO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #322 = CMOVNO16rm
- { 323, 3, 1, 0, "CMOVNO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #323 = CMOVNO16rr
- { 324, 7, 1, 0, "CMOVNO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #324 = CMOVNO32rm
- { 325, 3, 1, 0, "CMOVNO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #325 = CMOVNO32rr
- { 326, 7, 1, 0, "CMOVNO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #326 = CMOVNO64rm
- { 327, 3, 1, 0, "CMOVNO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #327 = CMOVNO64rr
- { 328, 7, 1, 0, "CMOVNP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #328 = CMOVNP16rm
- { 329, 3, 1, 0, "CMOVNP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #329 = CMOVNP16rr
- { 330, 7, 1, 0, "CMOVNP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #330 = CMOVNP32rm
- { 331, 3, 1, 0, "CMOVNP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #331 = CMOVNP32rr
- { 332, 7, 1, 0, "CMOVNP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #332 = CMOVNP64rm
- { 333, 3, 1, 0, "CMOVNP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #333 = CMOVNP64rr
- { 334, 1, 1, 0, "CMOVNP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #334 = CMOVNP_F
- { 335, 3, 1, 0, "CMOVNP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #335 = CMOVNP_Fp32
- { 336, 3, 1, 0, "CMOVNP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #336 = CMOVNP_Fp64
- { 337, 3, 1, 0, "CMOVNP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #337 = CMOVNP_Fp80
- { 338, 7, 1, 0, "CMOVNS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #338 = CMOVNS16rm
- { 339, 3, 1, 0, "CMOVNS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #339 = CMOVNS16rr
- { 340, 7, 1, 0, "CMOVNS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #340 = CMOVNS32rm
- { 341, 3, 1, 0, "CMOVNS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #341 = CMOVNS32rr
- { 342, 7, 1, 0, "CMOVNS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #342 = CMOVNS64rm
- { 343, 3, 1, 0, "CMOVNS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #343 = CMOVNS64rr
- { 344, 7, 1, 0, "CMOVO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #344 = CMOVO16rm
- { 345, 3, 1, 0, "CMOVO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #345 = CMOVO16rr
- { 346, 7, 1, 0, "CMOVO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #346 = CMOVO32rm
- { 347, 3, 1, 0, "CMOVO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #347 = CMOVO32rr
- { 348, 7, 1, 0, "CMOVO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #348 = CMOVO64rm
- { 349, 3, 1, 0, "CMOVO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #349 = CMOVO64rr
- { 350, 7, 1, 0, "CMOVP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #350 = CMOVP16rm
- { 351, 3, 1, 0, "CMOVP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #351 = CMOVP16rr
- { 352, 7, 1, 0, "CMOVP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #352 = CMOVP32rm
- { 353, 3, 1, 0, "CMOVP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #353 = CMOVP32rr
- { 354, 7, 1, 0, "CMOVP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #354 = CMOVP64rm
- { 355, 3, 1, 0, "CMOVP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #355 = CMOVP64rr
- { 356, 1, 1, 0, "CMOVP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #356 = CMOVP_F
- { 357, 3, 1, 0, "CMOVP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #357 = CMOVP_Fp32
- { 358, 3, 1, 0, "CMOVP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #358 = CMOVP_Fp64
- { 359, 3, 1, 0, "CMOVP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #359 = CMOVP_Fp80
- { 360, 7, 1, 0, "CMOVS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #360 = CMOVS16rm
- { 361, 3, 1, 0, "CMOVS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #361 = CMOVS16rr
- { 362, 7, 1, 0, "CMOVS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #362 = CMOVS32rm
- { 363, 3, 1, 0, "CMOVS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #363 = CMOVS32rr
- { 364, 7, 1, 0, "CMOVS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #364 = CMOVS64rm
- { 365, 3, 1, 0, "CMOVS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #365 = CMOVS64rr
- { 366, 4, 1, 0, "CMOV_FR32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #366 = CMOV_FR32
- { 367, 4, 1, 0, "CMOV_FR64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo62 }, // Inst #367 = CMOV_FR64
- { 368, 4, 1, 0, "CMOV_GR8", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, ImplicitList1, Barriers1, OperandInfo63 }, // Inst #368 = CMOV_GR8
- { 369, 4, 1, 0, "CMOV_V1I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo64 }, // Inst #369 = CMOV_V1I64
- { 370, 4, 1, 0, "CMOV_V2F64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo65 }, // Inst #370 = CMOV_V2F64
- { 371, 4, 1, 0, "CMOV_V2I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo65 }, // Inst #371 = CMOV_V2I64
- { 372, 4, 1, 0, "CMOV_V4F32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo65 }, // Inst #372 = CMOV_V4F32
- { 373, 1, 0, 0, "CMP16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #373 = CMP16i16
- { 374, 6, 0, 0, "CMP16mi", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #374 = CMP16mi
- { 375, 6, 0, 0, "CMP16mi8", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #375 = CMP16mi8
- { 376, 6, 0, 0, "CMP16mr", 0|(1<<TID::MayLoad), 0|4|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #376 = CMP16mr
- { 377, 2, 0, 0, "CMP16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #377 = CMP16mrmrr
- { 378, 2, 0, 0, "CMP16ri", 0, 0|23|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #378 = CMP16ri
- { 379, 2, 0, 0, "CMP16ri8", 0, 0|23|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #379 = CMP16ri8
- { 380, 6, 0, 0, "CMP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo45 }, // Inst #380 = CMP16rm
- { 381, 2, 0, 0, "CMP16rr", 0, 0|3|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #381 = CMP16rr
- { 382, 1, 0, 0, "CMP32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #382 = CMP32i32
- { 383, 6, 0, 0, "CMP32mi", 0|(1<<TID::MayLoad), 0|31|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #383 = CMP32mi
- { 384, 6, 0, 0, "CMP32mi8", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #384 = CMP32mi8
- { 385, 6, 0, 0, "CMP32mr", 0|(1<<TID::MayLoad), 0|4|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #385 = CMP32mr
- { 386, 2, 0, 0, "CMP32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #386 = CMP32mrmrr
- { 387, 2, 0, 0, "CMP32ri", 0, 0|23|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #387 = CMP32ri
- { 388, 2, 0, 0, "CMP32ri8", 0, 0|23|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #388 = CMP32ri8
- { 389, 6, 0, 0, "CMP32rm", 0|(1<<TID::MayLoad), 0|6|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #389 = CMP32rm
- { 390, 2, 0, 0, "CMP32rr", 0, 0|3|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #390 = CMP32rr
- { 391, 1, 0, 0, "CMP64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #391 = CMP64i32
- { 392, 6, 0, 0, "CMP64mi32", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #392 = CMP64mi32
- { 393, 6, 0, 0, "CMP64mi8", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #393 = CMP64mi8
- { 394, 6, 0, 0, "CMP64mr", 0|(1<<TID::MayLoad), 0|4|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #394 = CMP64mr
- { 395, 2, 0, 0, "CMP64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #395 = CMP64mrmrr
- { 396, 2, 0, 0, "CMP64ri32", 0, 0|23|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #396 = CMP64ri32
- { 397, 2, 0, 0, "CMP64ri8", 0, 0|23|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #397 = CMP64ri8
- { 398, 6, 0, 0, "CMP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #398 = CMP64rm
- { 399, 2, 0, 0, "CMP64rr", 0, 0|3|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #399 = CMP64rr
- { 400, 1, 0, 0, "CMP8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(60<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #400 = CMP8i8
- { 401, 6, 0, 0, "CMP8mi", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #401 = CMP8mi
- { 402, 6, 0, 0, "CMP8mr", 0|(1<<TID::MayLoad), 0|4|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #402 = CMP8mr
- { 403, 2, 0, 0, "CMP8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #403 = CMP8mrmrr
- { 404, 2, 0, 0, "CMP8ri", 0, 0|23|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #404 = CMP8ri
- { 405, 6, 0, 0, "CMP8rm", 0|(1<<TID::MayLoad), 0|6|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #405 = CMP8rm
- { 406, 2, 0, 0, "CMP8rr", 0, 0|3|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #406 = CMP8rr
- { 407, 8, 1, 0, "CMPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #407 = CMPPDrmi
- { 408, 4, 1, 0, "CMPPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #408 = CMPPDrri
- { 409, 8, 1, 0, "CMPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #409 = CMPPSrmi
- { 410, 4, 1, 0, "CMPPSrri", 0, 0|5|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #410 = CMPPSrri
- { 411, 0, 0, 0, "CMPS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #411 = CMPS16
- { 412, 0, 0, 0, "CMPS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(167<<24), NULL, NULL, NULL, 0 }, // Inst #412 = CMPS32
- { 413, 0, 0, 0, "CMPS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #413 = CMPS64
- { 414, 0, 0, 0, "CMPS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(166<<24), NULL, NULL, NULL, 0 }, // Inst #414 = CMPS8
- { 415, 8, 1, 0, "CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo69 }, // Inst #415 = CMPSDrm
- { 416, 4, 1, 0, "CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo70 }, // Inst #416 = CMPSDrr
- { 417, 8, 1, 0, "CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo71 }, // Inst #417 = CMPSSrm
- { 418, 4, 1, 0, "CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo72 }, // Inst #418 = CMPSSrr
- { 419, 6, 0, 0, "COMISDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #419 = COMISDrm
- { 420, 2, 0, 0, "COMISDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #420 = COMISDrr
- { 421, 0, 0, 0, "COS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(255<<24), NULL, NULL, NULL, 0 }, // Inst #421 = COS_F
- { 422, 2, 1, 0, "COS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #422 = COS_Fp32
- { 423, 2, 1, 0, "COS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #423 = COS_Fp64
- { 424, 2, 1, 0, "COS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #424 = COS_Fp80
- { 425, 0, 0, 0, "CQO", 0, 0|1|(1<<12)|(153<<24), ImplicitList15, ImplicitList16, NULL, 0 }, // Inst #425 = CQO
- { 426, 7, 1, 0, "CRC32m16", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #426 = CRC32m16
- { 427, 7, 1, 0, "CRC32m32", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #427 = CRC32m32
- { 428, 7, 1, 0, "CRC32m8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #428 = CRC32m8
- { 429, 3, 1, 0, "CRC32r16", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo76 }, // Inst #429 = CRC32r16
- { 430, 3, 1, 0, "CRC32r32", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #430 = CRC32r32
- { 431, 3, 1, 0, "CRC32r8", 0, 0|5|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo77 }, // Inst #431 = CRC32r8
- { 432, 7, 1, 0, "CRC64m64", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #432 = CRC64m64
- { 433, 3, 1, 0, "CRC64r64", 0, 0|5|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #433 = CRC64r64
- { 434, 6, 1, 0, "CVTDQ2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #434 = CVTDQ2PDrm
- { 435, 2, 1, 0, "CVTDQ2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #435 = CVTDQ2PDrr
- { 436, 6, 1, 0, "CVTDQ2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #436 = CVTDQ2PSrm
- { 437, 2, 1, 0, "CVTDQ2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #437 = CVTDQ2PSrr
- { 438, 6, 1, 0, "CVTPD2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #438 = CVTPD2DQrm
- { 439, 2, 1, 0, "CVTPD2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #439 = CVTPD2DQrr
- { 440, 6, 1, 0, "CVTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #440 = CVTPS2DQrm
- { 441, 2, 1, 0, "CVTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #441 = CVTPS2DQrr
- { 442, 6, 1, 0, "CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #442 = CVTSD2SSrm
- { 443, 2, 1, 0, "CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #443 = CVTSD2SSrr
- { 444, 6, 1, 0, "CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #444 = CVTSI2SD64rm
- { 445, 2, 1, 0, "CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo81 }, // Inst #445 = CVTSI2SD64rr
- { 446, 6, 1, 0, "CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #446 = CVTSI2SDrm
- { 447, 2, 1, 0, "CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #447 = CVTSI2SDrr
- { 448, 6, 1, 0, "CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #448 = CVTSI2SS64rm
- { 449, 2, 1, 0, "CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #449 = CVTSI2SS64rr
- { 450, 6, 1, 0, "CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #450 = CVTSI2SSrm
- { 451, 2, 1, 0, "CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo84 }, // Inst #451 = CVTSI2SSrr
- { 452, 6, 1, 0, "CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #452 = CVTSS2SDrm
- { 453, 2, 1, 0, "CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = CVTSS2SDrr
- { 454, 6, 1, 0, "CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #454 = CVTTSD2SI64rm
- { 455, 2, 1, 0, "CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #455 = CVTTSD2SI64rr
- { 456, 6, 1, 0, "CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #456 = CVTTSD2SIrm
- { 457, 2, 1, 0, "CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo87 }, // Inst #457 = CVTTSD2SIrr
- { 458, 6, 1, 0, "CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #458 = CVTTSS2SI64rm
- { 459, 2, 1, 0, "CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #459 = CVTTSS2SI64rr
- { 460, 6, 1, 0, "CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #460 = CVTTSS2SIrm
- { 461, 2, 1, 0, "CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #461 = CVTTSS2SIrr
- { 462, 0, 0, 0, "CWD", 0, 0|1|(1<<6)|(153<<24), ImplicitList12, ImplicitList17, NULL, 0 }, // Inst #462 = CWD
- { 463, 0, 0, 0, "CWDE", 0, 0|1|(152<<24), ImplicitList12, ImplicitList13, NULL, 0 }, // Inst #463 = CWDE
- { 464, 5, 0, 0, "DEC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #464 = DEC16m
- { 465, 2, 1, 0, "DEC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #465 = DEC16r
- { 466, 5, 0, 0, "DEC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #466 = DEC32m
- { 467, 2, 1, 0, "DEC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #467 = DEC32r
- { 468, 5, 0, 0, "DEC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #468 = DEC64_16m
- { 469, 2, 1, 0, "DEC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #469 = DEC64_16r
- { 470, 5, 0, 0, "DEC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #470 = DEC64_32m
- { 471, 2, 1, 0, "DEC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #471 = DEC64_32r
- { 472, 5, 0, 0, "DEC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #472 = DEC64m
- { 473, 2, 1, 0, "DEC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #473 = DEC64r
- { 474, 5, 0, 0, "DEC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #474 = DEC8m
- { 475, 2, 1, 0, "DEC8r", 0, 0|17|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #475 = DEC8r
- { 476, 5, 0, 0, "DIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo29 }, // Inst #476 = DIV16m
- { 477, 1, 0, 0, "DIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo92 }, // Inst #477 = DIV16r
- { 478, 5, 0, 0, "DIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo29 }, // Inst #478 = DIV32m
- { 479, 1, 0, 0, "DIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo56 }, // Inst #479 = DIV32r
- { 480, 5, 0, 0, "DIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo29 }, // Inst #480 = DIV64m
- { 481, 1, 0, 0, "DIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo57 }, // Inst #481 = DIV64r
- { 482, 5, 0, 0, "DIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo29 }, // Inst #482 = DIV8m
- { 483, 1, 0, 0, "DIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #483 = DIV8r
- { 484, 7, 1, 0, "DIVPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #484 = DIVPDrm
- { 485, 3, 1, 0, "DIVPDrr", 0, 0|5|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #485 = DIVPDrr
- { 486, 7, 1, 0, "DIVPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #486 = DIVPSrm
- { 487, 3, 1, 0, "DIVPSrr", 0, 0|5|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #487 = DIVPSrr
- { 488, 5, 0, 0, "DIVR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #488 = DIVR_F32m
- { 489, 5, 0, 0, "DIVR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #489 = DIVR_F64m
- { 490, 5, 0, 0, "DIVR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #490 = DIVR_FI16m
- { 491, 5, 0, 0, "DIVR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #491 = DIVR_FI32m
- { 492, 1, 0, 0, "DIVR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(240<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #492 = DIVR_FPrST0
- { 493, 1, 0, 0, "DIVR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(248<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #493 = DIVR_FST0r
- { 494, 7, 1, 0, "DIVR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #494 = DIVR_Fp32m
- { 495, 7, 1, 0, "DIVR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #495 = DIVR_Fp64m
- { 496, 7, 1, 0, "DIVR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #496 = DIVR_Fp64m32
- { 497, 7, 1, 0, "DIVR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #497 = DIVR_Fp80m32
- { 498, 7, 1, 0, "DIVR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #498 = DIVR_Fp80m64
- { 499, 7, 1, 0, "DIVR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #499 = DIVR_FpI16m32
- { 500, 7, 1, 0, "DIVR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #500 = DIVR_FpI16m64
- { 501, 7, 1, 0, "DIVR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #501 = DIVR_FpI16m80
- { 502, 7, 1, 0, "DIVR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #502 = DIVR_FpI32m32
- { 503, 7, 1, 0, "DIVR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #503 = DIVR_FpI32m64
- { 504, 7, 1, 0, "DIVR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #504 = DIVR_FpI32m80
- { 505, 1, 0, 0, "DIVR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(240<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #505 = DIVR_FrST0
- { 506, 7, 1, 0, "DIVSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #506 = DIVSDrm
- { 507, 7, 1, 0, "DIVSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #507 = DIVSDrm_Int
- { 508, 3, 1, 0, "DIVSDrr", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #508 = DIVSDrr
- { 509, 3, 1, 0, "DIVSDrr_Int", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #509 = DIVSDrr_Int
- { 510, 7, 1, 0, "DIVSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #510 = DIVSSrm
- { 511, 7, 1, 0, "DIVSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #511 = DIVSSrm_Int
- { 512, 3, 1, 0, "DIVSSrr", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #512 = DIVSSrr
- { 513, 3, 1, 0, "DIVSSrr_Int", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #513 = DIVSSrr_Int
- { 514, 5, 0, 0, "DIV_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #514 = DIV_F32m
- { 515, 5, 0, 0, "DIV_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #515 = DIV_F64m
- { 516, 5, 0, 0, "DIV_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #516 = DIV_FI16m
- { 517, 5, 0, 0, "DIV_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #517 = DIV_FI32m
- { 518, 1, 0, 0, "DIV_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(248<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #518 = DIV_FPrST0
- { 519, 1, 0, 0, "DIV_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(240<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #519 = DIV_FST0r
- { 520, 3, 1, 0, "DIV_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo31 }, // Inst #520 = DIV_Fp32
- { 521, 7, 1, 0, "DIV_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #521 = DIV_Fp32m
- { 522, 3, 1, 0, "DIV_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #522 = DIV_Fp64
- { 523, 7, 1, 0, "DIV_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #523 = DIV_Fp64m
- { 524, 7, 1, 0, "DIV_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #524 = DIV_Fp64m32
- { 525, 3, 1, 0, "DIV_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #525 = DIV_Fp80
- { 526, 7, 1, 0, "DIV_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #526 = DIV_Fp80m32
- { 527, 7, 1, 0, "DIV_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #527 = DIV_Fp80m64
- { 528, 7, 1, 0, "DIV_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #528 = DIV_FpI16m32
- { 529, 7, 1, 0, "DIV_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #529 = DIV_FpI16m64
- { 530, 7, 1, 0, "DIV_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #530 = DIV_FpI16m80
- { 531, 7, 1, 0, "DIV_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #531 = DIV_FpI32m32
- { 532, 7, 1, 0, "DIV_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #532 = DIV_FpI32m64
- { 533, 7, 1, 0, "DIV_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #533 = DIV_FpI32m80
- { 534, 1, 0, 0, "DIV_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(248<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #534 = DIV_FrST0
- { 535, 8, 1, 0, "DPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #535 = DPPDrmi
- { 536, 4, 1, 0, "DPPDrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #536 = DPPDrri
- { 537, 8, 1, 0, "DPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #537 = DPPSrmi
- { 538, 4, 1, 0, "DPPSrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #538 = DPPSrri
- { 539, 1, 0, 0, "EH_RETURN", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #539 = EH_RETURN
- { 540, 1, 0, 0, "EH_RETURN64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #540 = EH_RETURN64
- { 541, 2, 0, 0, "ENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(200<<24), NULL, NULL, NULL, OperandInfo37 }, // Inst #541 = ENTER
- { 542, 7, 0, 0, "EXTRACTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo94 }, // Inst #542 = EXTRACTPSmr
- { 543, 3, 1, 0, "EXTRACTPSrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #543 = EXTRACTPSrr
- { 544, 2, 0, 0, "FARCALL16i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo37 }, // Inst #544 = FARCALL16i
- { 545, 5, 0, 0, "FARCALL16m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo29 }, // Inst #545 = FARCALL16m
- { 546, 2, 0, 0, "FARCALL32i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo37 }, // Inst #546 = FARCALL32i
- { 547, 5, 0, 0, "FARCALL32m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo29 }, // Inst #547 = FARCALL32m
- { 548, 5, 0, 0, "FARCALL64", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo29 }, // Inst #548 = FARCALL64
- { 549, 2, 0, 0, "FARJMP16i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(234<<24), NULL, NULL, NULL, OperandInfo37 }, // Inst #549 = FARJMP16i
- { 550, 5, 0, 0, "FARJMP16m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #550 = FARJMP16m
- { 551, 2, 0, 0, "FARJMP32i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(234<<24), NULL, NULL, NULL, OperandInfo37 }, // Inst #551 = FARJMP32i
- { 552, 5, 0, 0, "FARJMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #552 = FARJMP32m
- { 553, 5, 0, 0, "FARJMP64", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #553 = FARJMP64
- { 554, 5, 0, 0, "FBLDm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #554 = FBLDm
- { 555, 5, 1, 0, "FBSTPm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #555 = FBSTPm
- { 556, 5, 0, 0, "FCOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #556 = FCOM32m
- { 557, 5, 0, 0, "FCOM64m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #557 = FCOM64m
- { 558, 5, 0, 0, "FCOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #558 = FCOMP32m
- { 559, 5, 0, 0, "FCOMP64m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #559 = FCOMP64m
- { 560, 5, 0, 0, "FICOM16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #560 = FICOM16m
- { 561, 5, 0, 0, "FICOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #561 = FICOM32m
- { 562, 5, 0, 0, "FICOMP16m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #562 = FICOMP16m
- { 563, 5, 0, 0, "FICOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #563 = FICOMP32m
- { 564, 5, 1, 0, "FISTTP32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #564 = FISTTP32m
- { 565, 5, 0, 0, "FLDCW16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #565 = FLDCW16m
- { 566, 5, 0, 0, "FLDENVm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #566 = FLDENVm
- { 567, 5, 0, 0, "FNSTCW16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #567 = FNSTCW16m
- { 568, 0, 0, 0, "FNSTSW8r", 0|(1<<TID::UnmodeledSideEffects), 0|1|(10<<8)|(224<<24), NULL, ImplicitList12, NULL, 0 }, // Inst #568 = FNSTSW8r
- { 569, 6, 0, 0, "FP32_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo96 }, // Inst #569 = FP32_TO_INT16_IN_MEM
- { 570, 6, 0, 0, "FP32_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo96 }, // Inst #570 = FP32_TO_INT32_IN_MEM
- { 571, 6, 0, 0, "FP32_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo96 }, // Inst #571 = FP32_TO_INT64_IN_MEM
- { 572, 6, 0, 0, "FP64_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #572 = FP64_TO_INT16_IN_MEM
- { 573, 6, 0, 0, "FP64_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #573 = FP64_TO_INT32_IN_MEM
- { 574, 6, 0, 0, "FP64_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #574 = FP64_TO_INT64_IN_MEM
- { 575, 6, 0, 0, "FP80_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #575 = FP80_TO_INT16_IN_MEM
- { 576, 6, 0, 0, "FP80_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #576 = FP80_TO_INT32_IN_MEM
- { 577, 6, 0, 0, "FP80_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #577 = FP80_TO_INT64_IN_MEM
- { 578, 0, 0, 0, "FP_REG_KILL", 0|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0, NULL, ImplicitList22, Barriers7, 0 }, // Inst #578 = FP_REG_KILL
- { 579, 5, 1, 0, "FRSTORm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #579 = FRSTORm
- { 580, 5, 1, 0, "FSAVEm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #580 = FSAVEm
- { 581, 5, 1, 0, "FSTENVm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #581 = FSTENVm
- { 582, 5, 1, 0, "FSTSWm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #582 = FSTSWm
- { 583, 6, 1, 0, "FS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #583 = FS_MOV32rm
- { 584, 1, 1, 0, "FpGET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #584 = FpGET_ST0_32
- { 585, 1, 1, 0, "FpGET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #585 = FpGET_ST0_64
- { 586, 1, 1, 0, "FpGET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #586 = FpGET_ST0_80
- { 587, 1, 1, 0, "FpGET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #587 = FpGET_ST1_32
- { 588, 1, 1, 0, "FpGET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #588 = FpGET_ST1_64
- { 589, 1, 1, 0, "FpGET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #589 = FpGET_ST1_80
- { 590, 1, 0, 0, "FpSET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo99 }, // Inst #590 = FpSET_ST0_32
- { 591, 1, 0, 0, "FpSET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo100 }, // Inst #591 = FpSET_ST0_64
- { 592, 1, 0, 0, "FpSET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo101 }, // Inst #592 = FpSET_ST0_80
- { 593, 1, 0, 0, "FpSET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo99 }, // Inst #593 = FpSET_ST1_32
- { 594, 1, 0, 0, "FpSET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo100 }, // Inst #594 = FpSET_ST1_64
- { 595, 1, 0, 0, "FpSET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo101 }, // Inst #595 = FpSET_ST1_80
- { 596, 7, 1, 0, "FsANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #596 = FsANDNPDrm
- { 597, 3, 1, 0, "FsANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #597 = FsANDNPDrr
- { 598, 7, 1, 0, "FsANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #598 = FsANDNPSrm
- { 599, 3, 1, 0, "FsANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #599 = FsANDNPSrr
- { 600, 7, 1, 0, "FsANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #600 = FsANDPDrm
- { 601, 3, 1, 0, "FsANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #601 = FsANDPDrr
- { 602, 7, 1, 0, "FsANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #602 = FsANDPSrm
- { 603, 3, 1, 0, "FsANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #603 = FsANDPSrr
- { 604, 1, 1, 0, "FsFLD0SD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo102 }, // Inst #604 = FsFLD0SD
- { 605, 1, 1, 0, "FsFLD0SS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo103 }, // Inst #605 = FsFLD0SS
- { 606, 6, 1, 0, "FsMOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #606 = FsMOVAPDrm
- { 607, 2, 1, 0, "FsMOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #607 = FsMOVAPDrr
- { 608, 6, 1, 0, "FsMOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #608 = FsMOVAPSrm
- { 609, 2, 1, 0, "FsMOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #609 = FsMOVAPSrr
- { 610, 7, 1, 0, "FsORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #610 = FsORPDrm
- { 611, 3, 1, 0, "FsORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #611 = FsORPDrr
- { 612, 7, 1, 0, "FsORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #612 = FsORPSrm
- { 613, 3, 1, 0, "FsORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #613 = FsORPSrr
- { 614, 7, 1, 0, "FsXORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #614 = FsXORPDrm
- { 615, 3, 1, 0, "FsXORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #615 = FsXORPDrr
- { 616, 7, 1, 0, "FsXORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #616 = FsXORPSrm
- { 617, 3, 1, 0, "FsXORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #617 = FsXORPSrr
- { 618, 6, 1, 0, "GS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #618 = GS_MOV32rm
- { 619, 7, 1, 0, "HADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #619 = HADDPDrm
- { 620, 3, 1, 0, "HADDPDrr", 0, 0|5|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #620 = HADDPDrr
- { 621, 7, 1, 0, "HADDPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #621 = HADDPSrm
- { 622, 3, 1, 0, "HADDPSrr", 0, 0|5|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #622 = HADDPSrr
- { 623, 7, 1, 0, "HSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #623 = HSUBPDrm
- { 624, 3, 1, 0, "HSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #624 = HSUBPDrr
- { 625, 7, 1, 0, "HSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #625 = HSUBPSrm
- { 626, 3, 1, 0, "HSUBPSrr", 0, 0|5|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #626 = HSUBPSrr
- { 627, 5, 0, 0, "IDIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo29 }, // Inst #627 = IDIV16m
- { 628, 1, 0, 0, "IDIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo92 }, // Inst #628 = IDIV16r
- { 629, 5, 0, 0, "IDIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo29 }, // Inst #629 = IDIV32m
- { 630, 1, 0, 0, "IDIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo56 }, // Inst #630 = IDIV32r
- { 631, 5, 0, 0, "IDIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo29 }, // Inst #631 = IDIV64m
- { 632, 1, 0, 0, "IDIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo57 }, // Inst #632 = IDIV64r
- { 633, 5, 0, 0, "IDIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo29 }, // Inst #633 = IDIV8m
- { 634, 1, 0, 0, "IDIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #634 = IDIV8r
- { 635, 5, 0, 0, "ILD_F16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #635 = ILD_F16m
- { 636, 5, 0, 0, "ILD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #636 = ILD_F32m
- { 637, 5, 0, 0, "ILD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #637 = ILD_F64m
- { 638, 6, 1, 0, "ILD_Fp16m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo106 }, // Inst #638 = ILD_Fp16m32
- { 639, 6, 1, 0, "ILD_Fp16m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #639 = ILD_Fp16m64
- { 640, 6, 1, 0, "ILD_Fp16m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #640 = ILD_Fp16m80
- { 641, 6, 1, 0, "ILD_Fp32m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo106 }, // Inst #641 = ILD_Fp32m32
- { 642, 6, 1, 0, "ILD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #642 = ILD_Fp32m64
- { 643, 6, 1, 0, "ILD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #643 = ILD_Fp32m80
- { 644, 6, 1, 0, "ILD_Fp64m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo106 }, // Inst #644 = ILD_Fp64m32
- { 645, 6, 1, 0, "ILD_Fp64m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #645 = ILD_Fp64m64
- { 646, 6, 1, 0, "ILD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #646 = ILD_Fp64m80
- { 647, 5, 0, 0, "IMUL16m", 0|(1<<TID::MayLoad), 0|29|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo29 }, // Inst #647 = IMUL16m
- { 648, 1, 0, 0, "IMUL16r", 0, 0|21|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo92 }, // Inst #648 = IMUL16r
- { 649, 7, 1, 0, "IMUL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #649 = IMUL16rm
- { 650, 7, 1, 0, "IMUL16rmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo109 }, // Inst #650 = IMUL16rmi
- { 651, 7, 1, 0, "IMUL16rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo109 }, // Inst #651 = IMUL16rmi8
- { 652, 3, 1, 0, "IMUL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #652 = IMUL16rr
- { 653, 3, 1, 0, "IMUL16rri", 0, 0|5|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #653 = IMUL16rri
- { 654, 3, 1, 0, "IMUL16rri8", 0, 0|5|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #654 = IMUL16rri8
- { 655, 5, 0, 0, "IMUL32m", 0|(1<<TID::MayLoad), 0|29|(247<<24), ImplicitList13, ImplicitList14, Barriers5, OperandInfo29 }, // Inst #655 = IMUL32m
- { 656, 1, 0, 0, "IMUL32r", 0, 0|21|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo56 }, // Inst #656 = IMUL32r
- { 657, 7, 1, 0, "IMUL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #657 = IMUL32rm
- { 658, 7, 1, 0, "IMUL32rmi", 0|(1<<TID::MayLoad), 0|6|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #658 = IMUL32rmi
- { 659, 7, 1, 0, "IMUL32rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #659 = IMUL32rmi8
- { 660, 3, 1, 0, "IMUL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #660 = IMUL32rr
- { 661, 3, 1, 0, "IMUL32rri", 0, 0|5|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #661 = IMUL32rri
- { 662, 3, 1, 0, "IMUL32rri8", 0, 0|5|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #662 = IMUL32rri8
- { 663, 5, 0, 0, "IMUL64m", 0|(1<<TID::MayLoad), 0|29|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo29 }, // Inst #663 = IMUL64m
- { 664, 1, 0, 0, "IMUL64r", 0, 0|21|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo57 }, // Inst #664 = IMUL64r
- { 665, 7, 1, 0, "IMUL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #665 = IMUL64rm
- { 666, 7, 1, 0, "IMUL64rmi32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #666 = IMUL64rmi32
- { 667, 7, 1, 0, "IMUL64rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #667 = IMUL64rmi8
- { 668, 3, 1, 0, "IMUL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #668 = IMUL64rr
- { 669, 3, 1, 0, "IMUL64rri32", 0, 0|5|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #669 = IMUL64rri32
- { 670, 3, 1, 0, "IMUL64rri8", 0, 0|5|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #670 = IMUL64rri8
- { 671, 5, 0, 0, "IMUL8m", 0|(1<<TID::MayLoad), 0|29|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo29 }, // Inst #671 = IMUL8m
- { 672, 1, 0, 0, "IMUL8r", 0, 0|21|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #672 = IMUL8r
- { 673, 1, 0, 0, "IN16ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(229<<24), NULL, ImplicitList12, NULL, OperandInfo5 }, // Inst #673 = IN16ri
- { 674, 0, 0, 0, "IN16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(237<<24), ImplicitList25, ImplicitList12, NULL, 0 }, // Inst #674 = IN16rr
- { 675, 1, 0, 0, "IN32ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(229<<24), NULL, ImplicitList13, NULL, OperandInfo5 }, // Inst #675 = IN32ri
- { 676, 0, 0, 0, "IN32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(237<<24), ImplicitList25, ImplicitList13, NULL, 0 }, // Inst #676 = IN32rr
- { 677, 1, 0, 0, "IN8ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(228<<24), NULL, ImplicitList11, NULL, OperandInfo5 }, // Inst #677 = IN8ri
- { 678, 0, 0, 0, "IN8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(236<<24), ImplicitList25, ImplicitList11, NULL, 0 }, // Inst #678 = IN8rr
- { 679, 5, 0, 0, "INC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #679 = INC16m
- { 680, 2, 1, 0, "INC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #680 = INC16r
- { 681, 5, 0, 0, "INC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #681 = INC32m
- { 682, 2, 1, 0, "INC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #682 = INC32r
- { 683, 5, 0, 0, "INC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #683 = INC64_16m
- { 684, 2, 1, 0, "INC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #684 = INC64_16r
- { 685, 5, 0, 0, "INC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #685 = INC64_32m
- { 686, 2, 1, 0, "INC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #686 = INC64_32r
- { 687, 5, 0, 0, "INC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #687 = INC64m
- { 688, 2, 1, 0, "INC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #688 = INC64r
- { 689, 5, 0, 0, "INC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #689 = INC8m
- { 690, 2, 1, 0, "INC8r", 0, 0|16|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #690 = INC8r
- { 691, 8, 1, 0, "INSERTPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #691 = INSERTPSrm
- { 692, 4, 1, 0, "INSERTPSrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #692 = INSERTPSrr
- { 693, 1, 0, 0, "INT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(205<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #693 = INT
- { 694, 0, 0, 0, "INT3", 0|(1<<TID::UnmodeledSideEffects), 0|1|(204<<24), NULL, NULL, NULL, 0 }, // Inst #694 = INT3
- { 695, 5, 0, 0, "ISTT_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #695 = ISTT_FP16m
- { 696, 5, 0, 0, "ISTT_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #696 = ISTT_FP32m
- { 697, 5, 0, 0, "ISTT_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #697 = ISTT_FP64m
- { 698, 6, 0, 0, "ISTT_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #698 = ISTT_Fp16m32
- { 699, 6, 0, 0, "ISTT_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #699 = ISTT_Fp16m64
- { 700, 6, 0, 0, "ISTT_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #700 = ISTT_Fp16m80
- { 701, 6, 0, 0, "ISTT_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #701 = ISTT_Fp32m32
- { 702, 6, 0, 0, "ISTT_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #702 = ISTT_Fp32m64
- { 703, 6, 0, 0, "ISTT_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #703 = ISTT_Fp32m80
- { 704, 6, 0, 0, "ISTT_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #704 = ISTT_Fp64m32
- { 705, 6, 0, 0, "ISTT_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #705 = ISTT_Fp64m64
- { 706, 6, 0, 0, "ISTT_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #706 = ISTT_Fp64m80
- { 707, 5, 0, 0, "IST_F16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #707 = IST_F16m
- { 708, 5, 0, 0, "IST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #708 = IST_F32m
- { 709, 5, 0, 0, "IST_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #709 = IST_FP16m
- { 710, 5, 0, 0, "IST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #710 = IST_FP32m
- { 711, 5, 0, 0, "IST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #711 = IST_FP64m
- { 712, 6, 0, 0, "IST_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #712 = IST_Fp16m32
- { 713, 6, 0, 0, "IST_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #713 = IST_Fp16m64
- { 714, 6, 0, 0, "IST_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #714 = IST_Fp16m80
- { 715, 6, 0, 0, "IST_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #715 = IST_Fp32m32
- { 716, 6, 0, 0, "IST_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #716 = IST_Fp32m64
- { 717, 6, 0, 0, "IST_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #717 = IST_Fp32m80
- { 718, 6, 0, 0, "IST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #718 = IST_Fp64m32
- { 719, 6, 0, 0, "IST_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #719 = IST_Fp64m64
- { 720, 6, 0, 0, "IST_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #720 = IST_Fp64m80
- { 721, 8, 1, 0, "Int_CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #721 = Int_CMPSDrm
- { 722, 4, 1, 0, "Int_CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #722 = Int_CMPSDrr
- { 723, 8, 1, 0, "Int_CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #723 = Int_CMPSSrm
- { 724, 4, 1, 0, "Int_CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #724 = Int_CMPSSrr
- { 725, 6, 0, 0, "Int_COMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo73 }, // Inst #725 = Int_COMISDrm
- { 726, 2, 0, 0, "Int_COMISDrr", 0, 0|5|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #726 = Int_COMISDrr
- { 727, 6, 0, 0, "Int_COMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo73 }, // Inst #727 = Int_COMISSrm
- { 728, 2, 0, 0, "Int_COMISSrr", 0, 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #728 = Int_COMISSrr
- { 729, 6, 1, 0, "Int_CVTDQ2PDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #729 = Int_CVTDQ2PDrm
- { 730, 2, 1, 0, "Int_CVTDQ2PDrr", 0, 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #730 = Int_CVTDQ2PDrr
- { 731, 6, 1, 0, "Int_CVTDQ2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #731 = Int_CVTDQ2PSrm
- { 732, 2, 1, 0, "Int_CVTDQ2PSrr", 0, 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #732 = Int_CVTDQ2PSrr
- { 733, 6, 1, 0, "Int_CVTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #733 = Int_CVTPD2DQrm
- { 734, 2, 1, 0, "Int_CVTPD2DQrr", 0, 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #734 = Int_CVTPD2DQrr
- { 735, 6, 1, 0, "Int_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #735 = Int_CVTPD2PIrm
- { 736, 2, 1, 0, "Int_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #736 = Int_CVTPD2PIrr
- { 737, 6, 1, 0, "Int_CVTPD2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #737 = Int_CVTPD2PSrm
- { 738, 2, 1, 0, "Int_CVTPD2PSrr", 0, 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #738 = Int_CVTPD2PSrr
- { 739, 6, 1, 0, "Int_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #739 = Int_CVTPI2PDrm
- { 740, 2, 1, 0, "Int_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #740 = Int_CVTPI2PDrr
- { 741, 7, 1, 0, "Int_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #741 = Int_CVTPI2PSrm
- { 742, 3, 1, 0, "Int_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #742 = Int_CVTPI2PSrr
- { 743, 6, 1, 0, "Int_CVTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #743 = Int_CVTPS2DQrm
- { 744, 2, 1, 0, "Int_CVTPS2DQrr", 0, 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #744 = Int_CVTPS2DQrr
- { 745, 6, 1, 0, "Int_CVTPS2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #745 = Int_CVTPS2PDrm
- { 746, 2, 1, 0, "Int_CVTPS2PDrr", 0, 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #746 = Int_CVTPS2PDrr
- { 747, 6, 1, 0, "Int_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #747 = Int_CVTPS2PIrm
- { 748, 2, 1, 0, "Int_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #748 = Int_CVTPS2PIrr
- { 749, 6, 1, 0, "Int_CVTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #749 = Int_CVTSD2SI64rm
- { 750, 2, 1, 0, "Int_CVTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #750 = Int_CVTSD2SI64rr
- { 751, 6, 1, 0, "Int_CVTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #751 = Int_CVTSD2SIrm
- { 752, 2, 1, 0, "Int_CVTSD2SIrr", 0, 0|5|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #752 = Int_CVTSD2SIrr
- { 753, 7, 1, 0, "Int_CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #753 = Int_CVTSD2SSrm
- { 754, 3, 1, 0, "Int_CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #754 = Int_CVTSD2SSrr
- { 755, 7, 1, 0, "Int_CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #755 = Int_CVTSI2SD64rm
- { 756, 3, 1, 0, "Int_CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #756 = Int_CVTSI2SD64rr
- { 757, 7, 1, 0, "Int_CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #757 = Int_CVTSI2SDrm
- { 758, 3, 1, 0, "Int_CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #758 = Int_CVTSI2SDrr
- { 759, 7, 1, 0, "Int_CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #759 = Int_CVTSI2SS64rm
- { 760, 3, 1, 0, "Int_CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #760 = Int_CVTSI2SS64rr
- { 761, 7, 1, 0, "Int_CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #761 = Int_CVTSI2SSrm
- { 762, 3, 1, 0, "Int_CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #762 = Int_CVTSI2SSrr
- { 763, 7, 1, 0, "Int_CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #763 = Int_CVTSS2SDrm
- { 764, 3, 1, 0, "Int_CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #764 = Int_CVTSS2SDrr
- { 765, 6, 1, 0, "Int_CVTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #765 = Int_CVTSS2SI64rm
- { 766, 2, 1, 0, "Int_CVTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #766 = Int_CVTSS2SI64rr
- { 767, 6, 1, 0, "Int_CVTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #767 = Int_CVTSS2SIrm
- { 768, 2, 1, 0, "Int_CVTSS2SIrr", 0, 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #768 = Int_CVTSS2SIrr
- { 769, 6, 1, 0, "Int_CVTTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #769 = Int_CVTTPD2DQrm
- { 770, 2, 1, 0, "Int_CVTTPD2DQrr", 0, 0|5|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #770 = Int_CVTTPD2DQrr
- { 771, 6, 1, 0, "Int_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #771 = Int_CVTTPD2PIrm
- { 772, 2, 1, 0, "Int_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #772 = Int_CVTTPD2PIrr
- { 773, 6, 1, 0, "Int_CVTTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #773 = Int_CVTTPS2DQrm
- { 774, 2, 1, 0, "Int_CVTTPS2DQrr", 0, 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #774 = Int_CVTTPS2DQrr
- { 775, 6, 1, 0, "Int_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #775 = Int_CVTTPS2PIrm
- { 776, 2, 1, 0, "Int_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #776 = Int_CVTTPS2PIrr
- { 777, 6, 1, 0, "Int_CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #777 = Int_CVTTSD2SI64rm
- { 778, 2, 1, 0, "Int_CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #778 = Int_CVTTSD2SI64rr
- { 779, 6, 1, 0, "Int_CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #779 = Int_CVTTSD2SIrm
- { 780, 2, 1, 0, "Int_CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #780 = Int_CVTTSD2SIrr
- { 781, 6, 1, 0, "Int_CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #781 = Int_CVTTSS2SI64rm
- { 782, 2, 1, 0, "Int_CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #782 = Int_CVTTSS2SI64rr
- { 783, 6, 1, 0, "Int_CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #783 = Int_CVTTSS2SIrm
- { 784, 2, 1, 0, "Int_CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #784 = Int_CVTTSS2SIrr
- { 785, 6, 0, 0, "Int_UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo73 }, // Inst #785 = Int_UCOMISDrm
- { 786, 2, 0, 0, "Int_UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #786 = Int_UCOMISDrr
- { 787, 6, 0, 0, "Int_UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo73 }, // Inst #787 = Int_UCOMISSrm
- { 788, 2, 0, 0, "Int_UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #788 = Int_UCOMISSrr
- { 789, 1, 0, 0, "JA", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(135<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #789 = JA
- { 790, 1, 0, 0, "JA8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(119<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #790 = JA8
- { 791, 1, 0, 0, "JAE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(131<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #791 = JAE
- { 792, 1, 0, 0, "JAE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(115<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #792 = JAE8
- { 793, 1, 0, 0, "JB", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(130<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #793 = JB
- { 794, 1, 0, 0, "JB8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(114<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #794 = JB8
- { 795, 1, 0, 0, "JBE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(134<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #795 = JBE
- { 796, 1, 0, 0, "JBE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(118<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #796 = JBE8
- { 797, 1, 0, 0, "JCXZ8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(227<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #797 = JCXZ8
- { 798, 1, 0, 0, "JE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(132<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #798 = JE
- { 799, 1, 0, 0, "JE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(116<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #799 = JE8
- { 800, 1, 0, 0, "JG", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(143<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #800 = JG
- { 801, 1, 0, 0, "JG8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(127<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #801 = JG8
- { 802, 1, 0, 0, "JGE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(141<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #802 = JGE
- { 803, 1, 0, 0, "JGE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(125<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #803 = JGE8
- { 804, 1, 0, 0, "JL", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(140<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #804 = JL
- { 805, 1, 0, 0, "JL8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(124<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #805 = JL8
- { 806, 1, 0, 0, "JLE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(142<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #806 = JLE
- { 807, 1, 0, 0, "JLE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(126<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #807 = JLE8
- { 808, 1, 0, 0, "JMP", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #808 = JMP
- { 809, 5, 0, 0, "JMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #809 = JMP32m
- { 810, 1, 0, 0, "JMP32r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #810 = JMP32r
- { 811, 5, 0, 0, "JMP64m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #811 = JMP64m
- { 812, 1, 0, 0, "JMP64r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #812 = JMP64r
- { 813, 1, 0, 0, "JMP8", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(235<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #813 = JMP8
- { 814, 1, 0, 0, "JNE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(133<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #814 = JNE
- { 815, 1, 0, 0, "JNE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(117<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #815 = JNE8
- { 816, 1, 0, 0, "JNO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(129<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #816 = JNO
- { 817, 1, 0, 0, "JNO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(113<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #817 = JNO8
- { 818, 1, 0, 0, "JNP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(139<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #818 = JNP
- { 819, 1, 0, 0, "JNP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(123<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #819 = JNP8
- { 820, 1, 0, 0, "JNS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(137<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #820 = JNS
- { 821, 1, 0, 0, "JNS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(121<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #821 = JNS8
- { 822, 1, 0, 0, "JO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(128<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #822 = JO
- { 823, 1, 0, 0, "JO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(112<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #823 = JO8
- { 824, 1, 0, 0, "JP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(138<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #824 = JP
- { 825, 1, 0, 0, "JP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(122<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #825 = JP8
- { 826, 1, 0, 0, "JS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(136<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #826 = JS
- { 827, 1, 0, 0, "JS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(120<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #827 = JS8
- { 828, 0, 0, 0, "LAHF", 0, 0|1|(159<<24), ImplicitList1, ImplicitList26, NULL, 0 }, // Inst #828 = LAHF
- { 829, 6, 1, 0, "LAR16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #829 = LAR16rm
- { 830, 2, 1, 0, "LAR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #830 = LAR16rr
- { 831, 6, 1, 0, "LAR32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #831 = LAR32rm
- { 832, 2, 1, 0, "LAR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #832 = LAR32rr
- { 833, 6, 1, 0, "LAR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #833 = LAR64rm
- { 834, 2, 1, 0, "LAR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #834 = LAR64rr
- { 835, 6, 0, 0, "LCMPXCHG16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<19)|(177<<24), ImplicitList12, ImplicitList27, Barriers1, OperandInfo7 }, // Inst #835 = LCMPXCHG16
- { 836, 6, 0, 0, "LCMPXCHG32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(177<<24), ImplicitList13, ImplicitList28, Barriers1, OperandInfo11 }, // Inst #836 = LCMPXCHG32
- { 837, 6, 0, 0, "LCMPXCHG64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<19)|(177<<24), ImplicitList15, ImplicitList29, Barriers1, OperandInfo15 }, // Inst #837 = LCMPXCHG64
- { 838, 6, 0, 0, "LCMPXCHG8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(176<<24), ImplicitList11, ImplicitList30, Barriers1, OperandInfo19 }, // Inst #838 = LCMPXCHG8
- { 839, 5, 0, 0, "LCMPXCHG8B", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(1<<19)|(199<<24), ImplicitList6, ImplicitList19, Barriers6, OperandInfo29 }, // Inst #839 = LCMPXCHG8B
- { 840, 6, 1, 0, "LDDQUrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(240<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #840 = LDDQUrm
- { 841, 5, 0, 0, "LDMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #841 = LDMXCSR
- { 842, 0, 0, 0, "LD_F0", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(238<<24), NULL, NULL, NULL, 0 }, // Inst #842 = LD_F0
- { 843, 0, 0, 0, "LD_F1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(232<<24), NULL, NULL, NULL, 0 }, // Inst #843 = LD_F1
- { 844, 5, 0, 0, "LD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #844 = LD_F32m
- { 845, 5, 0, 0, "LD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #845 = LD_F64m
- { 846, 5, 0, 0, "LD_F80m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #846 = LD_F80m
- { 847, 1, 1, 0, "LD_Fp032", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #847 = LD_Fp032
- { 848, 1, 1, 0, "LD_Fp064", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #848 = LD_Fp064
- { 849, 1, 1, 0, "LD_Fp080", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #849 = LD_Fp080
- { 850, 1, 1, 0, "LD_Fp132", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #850 = LD_Fp132
- { 851, 1, 1, 0, "LD_Fp164", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #851 = LD_Fp164
- { 852, 1, 1, 0, "LD_Fp180", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #852 = LD_Fp180
- { 853, 6, 1, 0, "LD_Fp32m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo106 }, // Inst #853 = LD_Fp32m
- { 854, 6, 1, 0, "LD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #854 = LD_Fp32m64
- { 855, 6, 1, 0, "LD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #855 = LD_Fp32m80
- { 856, 6, 1, 0, "LD_Fp64m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #856 = LD_Fp64m
- { 857, 6, 1, 0, "LD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #857 = LD_Fp64m80
- { 858, 6, 1, 0, "LD_Fp80m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #858 = LD_Fp80m
- { 859, 1, 0, 0, "LD_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #859 = LD_Frr
- { 860, 5, 1, 0, "LEA16r", 0, 0|6|(1<<6)|(141<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #860 = LEA16r
- { 861, 5, 1, 0, "LEA32r", 0|(1<<TID::Rematerializable), 0|6|(141<<24), NULL, NULL, NULL, OperandInfo126 }, // Inst #861 = LEA32r
- { 862, 5, 1, 0, "LEA64_32r", 0, 0|6|(141<<24), NULL, NULL, NULL, OperandInfo126 }, // Inst #862 = LEA64_32r
- { 863, 5, 1, 0, "LEA64r", 0|(1<<TID::Rematerializable), 0|6|(1<<12)|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #863 = LEA64r
- { 864, 0, 0, 0, "LEAVE", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList31, ImplicitList31, NULL, 0 }, // Inst #864 = LEAVE
- { 865, 0, 0, 0, "LEAVE64", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList32, ImplicitList32, NULL, 0 }, // Inst #865 = LEAVE64
- { 866, 0, 0, 0, "LFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #866 = LFENCE
- { 867, 6, 0, 0, "LOCK_ADD16mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #867 = LOCK_ADD16mi
- { 868, 6, 0, 0, "LOCK_ADD16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #868 = LOCK_ADD16mi8
- { 869, 6, 0, 0, "LOCK_ADD16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #869 = LOCK_ADD16mr
- { 870, 6, 0, 0, "LOCK_ADD32mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #870 = LOCK_ADD32mi
- { 871, 6, 0, 0, "LOCK_ADD32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #871 = LOCK_ADD32mi8
- { 872, 6, 0, 0, "LOCK_ADD32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #872 = LOCK_ADD32mr
- { 873, 6, 0, 0, "LOCK_ADD64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #873 = LOCK_ADD64mi32
- { 874, 6, 0, 0, "LOCK_ADD64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #874 = LOCK_ADD64mi8
- { 875, 6, 0, 0, "LOCK_ADD64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #875 = LOCK_ADD64mr
- { 876, 6, 0, 0, "LOCK_ADD8mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #876 = LOCK_ADD8mi
- { 877, 6, 0, 0, "LOCK_ADD8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #877 = LOCK_ADD8mr
- { 878, 5, 0, 0, "LOCK_DEC16m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #878 = LOCK_DEC16m
- { 879, 5, 0, 0, "LOCK_DEC32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #879 = LOCK_DEC32m
- { 880, 5, 0, 0, "LOCK_DEC64m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #880 = LOCK_DEC64m
- { 881, 5, 0, 0, "LOCK_DEC8m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #881 = LOCK_DEC8m
- { 882, 5, 0, 0, "LOCK_INC16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #882 = LOCK_INC16m
- { 883, 5, 0, 0, "LOCK_INC32m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #883 = LOCK_INC32m
- { 884, 5, 0, 0, "LOCK_INC64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #884 = LOCK_INC64m
- { 885, 5, 0, 0, "LOCK_INC8m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #885 = LOCK_INC8m
- { 886, 6, 0, 0, "LOCK_SUB16mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #886 = LOCK_SUB16mi
- { 887, 6, 0, 0, "LOCK_SUB16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #887 = LOCK_SUB16mi8
- { 888, 6, 0, 0, "LOCK_SUB16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #888 = LOCK_SUB16mr
- { 889, 6, 0, 0, "LOCK_SUB32mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #889 = LOCK_SUB32mi
- { 890, 6, 0, 0, "LOCK_SUB32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #890 = LOCK_SUB32mi8
- { 891, 6, 0, 0, "LOCK_SUB32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #891 = LOCK_SUB32mr
- { 892, 6, 0, 0, "LOCK_SUB64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #892 = LOCK_SUB64mi32
- { 893, 6, 0, 0, "LOCK_SUB64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #893 = LOCK_SUB64mi8
- { 894, 6, 0, 0, "LOCK_SUB64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #894 = LOCK_SUB64mr
- { 895, 6, 0, 0, "LOCK_SUB8mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #895 = LOCK_SUB8mi
- { 896, 6, 0, 0, "LOCK_SUB8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #896 = LOCK_SUB8mr
- { 897, 0, 0, 0, "LODSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(172<<24), NULL, NULL, NULL, 0 }, // Inst #897 = LODSB
- { 898, 0, 0, 0, "LODSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(173<<24), NULL, NULL, NULL, 0 }, // Inst #898 = LODSD
- { 899, 0, 0, 0, "LODSQ", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #899 = LODSQ
- { 900, 0, 0, 0, "LODSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #900 = LODSW
- { 901, 1, 1, 0, "LOOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(226<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #901 = LOOP
- { 902, 1, 1, 0, "LOOPE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(225<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #902 = LOOPE
- { 903, 1, 1, 0, "LOOPNE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(224<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #903 = LOOPNE
- { 904, 0, 0, 0, "LRET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(7<<16)|(203<<24), NULL, NULL, NULL, 0 }, // Inst #904 = LRET
- { 905, 1, 0, 0, "LRETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(7<<16)|(202<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #905 = LRETI
- { 906, 7, 1, 0, "LXADD16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #906 = LXADD16
- { 907, 7, 1, 0, "LXADD32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #907 = LXADD32
- { 908, 7, 1, 0, "LXADD64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<12)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #908 = LXADD64
- { 909, 7, 1, 0, "LXADD8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #909 = LXADD8
- { 910, 2, 0, 0, "MASKMOVDQU", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList33, NULL, NULL, OperandInfo74 }, // Inst #910 = MASKMOVDQU
- { 911, 2, 0, 0, "MASKMOVDQU64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo74 }, // Inst #911 = MASKMOVDQU64
- { 912, 7, 1, 0, "MAXPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #912 = MAXPDrm
- { 913, 7, 1, 0, "MAXPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #913 = MAXPDrm_Int
- { 914, 3, 1, 0, "MAXPDrr", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #914 = MAXPDrr
- { 915, 3, 1, 0, "MAXPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #915 = MAXPDrr_Int
- { 916, 7, 1, 0, "MAXPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #916 = MAXPSrm
- { 917, 7, 1, 0, "MAXPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #917 = MAXPSrm_Int
- { 918, 3, 1, 0, "MAXPSrr", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #918 = MAXPSrr
- { 919, 3, 1, 0, "MAXPSrr_Int", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #919 = MAXPSrr_Int
- { 920, 7, 1, 0, "MAXSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #920 = MAXSDrm
- { 921, 7, 1, 0, "MAXSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #921 = MAXSDrm_Int
- { 922, 3, 1, 0, "MAXSDrr", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #922 = MAXSDrr
- { 923, 3, 1, 0, "MAXSDrr_Int", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #923 = MAXSDrr_Int
- { 924, 7, 1, 0, "MAXSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #924 = MAXSSrm
- { 925, 7, 1, 0, "MAXSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #925 = MAXSSrm_Int
- { 926, 3, 1, 0, "MAXSSrr", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #926 = MAXSSrr
- { 927, 3, 1, 0, "MAXSSrr_Int", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #927 = MAXSSrr_Int
- { 928, 0, 0, 0, "MFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #928 = MFENCE
- { 929, 7, 1, 0, "MINPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #929 = MINPDrm
- { 930, 7, 1, 0, "MINPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #930 = MINPDrm_Int
- { 931, 3, 1, 0, "MINPDrr", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #931 = MINPDrr
- { 932, 3, 1, 0, "MINPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #932 = MINPDrr_Int
- { 933, 7, 1, 0, "MINPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #933 = MINPSrm
- { 934, 7, 1, 0, "MINPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #934 = MINPSrm_Int
- { 935, 3, 1, 0, "MINPSrr", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #935 = MINPSrr
- { 936, 3, 1, 0, "MINPSrr_Int", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #936 = MINPSrr_Int
- { 937, 7, 1, 0, "MINSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #937 = MINSDrm
- { 938, 7, 1, 0, "MINSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #938 = MINSDrm_Int
- { 939, 3, 1, 0, "MINSDrr", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #939 = MINSDrr
- { 940, 3, 1, 0, "MINSDrr_Int", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #940 = MINSDrr_Int
- { 941, 7, 1, 0, "MINSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #941 = MINSSrm
- { 942, 7, 1, 0, "MINSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #942 = MINSSrm_Int
- { 943, 3, 1, 0, "MINSSrr", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #943 = MINSSrr
- { 944, 3, 1, 0, "MINSSrr_Int", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #944 = MINSSrr_Int
- { 945, 6, 1, 0, "MMX_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #945 = MMX_CVTPD2PIrm
- { 946, 2, 1, 0, "MMX_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #946 = MMX_CVTPD2PIrr
- { 947, 6, 1, 0, "MMX_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #947 = MMX_CVTPI2PDrm
- { 948, 2, 1, 0, "MMX_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #948 = MMX_CVTPI2PDrr
- { 949, 6, 1, 0, "MMX_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #949 = MMX_CVTPI2PSrm
- { 950, 2, 1, 0, "MMX_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #950 = MMX_CVTPI2PSrr
- { 951, 6, 1, 0, "MMX_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #951 = MMX_CVTPS2PIrm
- { 952, 2, 1, 0, "MMX_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #952 = MMX_CVTPS2PIrr
- { 953, 6, 1, 0, "MMX_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #953 = MMX_CVTTPD2PIrm
- { 954, 2, 1, 0, "MMX_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #954 = MMX_CVTTPD2PIrr
- { 955, 6, 1, 0, "MMX_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #955 = MMX_CVTTPS2PIrm
- { 956, 2, 1, 0, "MMX_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #956 = MMX_CVTTPS2PIrr
- { 957, 0, 0, 0, "MMX_EMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(119<<24), NULL, NULL, NULL, 0 }, // Inst #957 = MMX_EMMS
- { 958, 0, 0, 0, "MMX_FEMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(14<<24), NULL, NULL, NULL, 0 }, // Inst #958 = MMX_FEMMS
- { 959, 2, 0, 0, "MMX_MASKMOVQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList33, NULL, NULL, OperandInfo128 }, // Inst #959 = MMX_MASKMOVQ
- { 960, 2, 0, 0, "MMX_MASKMOVQ64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo128 }, // Inst #960 = MMX_MASKMOVQ64
- { 961, 2, 1, 0, "MMX_MOVD64from64rr", 0, 0|3|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #961 = MMX_MOVD64from64rr
- { 962, 6, 0, 0, "MMX_MOVD64mr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #962 = MMX_MOVD64mr
- { 963, 6, 1, 0, "MMX_MOVD64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #963 = MMX_MOVD64rm
- { 964, 2, 1, 0, "MMX_MOVD64rr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #964 = MMX_MOVD64rr
- { 965, 2, 1, 0, "MMX_MOVD64rrv164", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #965 = MMX_MOVD64rrv164
- { 966, 2, 1, 0, "MMX_MOVD64to64rr", 0, 0|5|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #966 = MMX_MOVD64to64rr
- { 967, 2, 1, 0, "MMX_MOVDQ2Qrr", 0, 0|5|(11<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #967 = MMX_MOVDQ2Qrr
- { 968, 6, 0, 0, "MMX_MOVNTQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #968 = MMX_MOVNTQmr
- { 969, 2, 1, 0, "MMX_MOVQ2DQrr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #969 = MMX_MOVQ2DQrr
- { 970, 2, 1, 0, "MMX_MOVQ2FR64rr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #970 = MMX_MOVQ2FR64rr
- { 971, 6, 0, 0, "MMX_MOVQ64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #971 = MMX_MOVQ64mr
- { 972, 6, 1, 0, "MMX_MOVQ64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #972 = MMX_MOVQ64rm
- { 973, 2, 1, 0, "MMX_MOVQ64rr", 0, 0|5|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #973 = MMX_MOVQ64rr
- { 974, 6, 1, 0, "MMX_MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #974 = MMX_MOVZDI2PDIrm
- { 975, 2, 1, 0, "MMX_MOVZDI2PDIrr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #975 = MMX_MOVZDI2PDIrr
- { 976, 7, 1, 0, "MMX_PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #976 = MMX_PACKSSDWrm
- { 977, 3, 1, 0, "MMX_PACKSSDWrr", 0, 0|5|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #977 = MMX_PACKSSDWrr
- { 978, 7, 1, 0, "MMX_PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #978 = MMX_PACKSSWBrm
- { 979, 3, 1, 0, "MMX_PACKSSWBrr", 0, 0|5|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #979 = MMX_PACKSSWBrr
- { 980, 7, 1, 0, "MMX_PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #980 = MMX_PACKUSWBrm
- { 981, 3, 1, 0, "MMX_PACKUSWBrr", 0, 0|5|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #981 = MMX_PACKUSWBrr
- { 982, 7, 1, 0, "MMX_PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #982 = MMX_PADDBrm
- { 983, 3, 1, 0, "MMX_PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #983 = MMX_PADDBrr
- { 984, 7, 1, 0, "MMX_PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #984 = MMX_PADDDrm
- { 985, 3, 1, 0, "MMX_PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #985 = MMX_PADDDrr
- { 986, 7, 1, 0, "MMX_PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #986 = MMX_PADDQrm
- { 987, 3, 1, 0, "MMX_PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #987 = MMX_PADDQrr
- { 988, 7, 1, 0, "MMX_PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #988 = MMX_PADDSBrm
- { 989, 3, 1, 0, "MMX_PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #989 = MMX_PADDSBrr
- { 990, 7, 1, 0, "MMX_PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #990 = MMX_PADDSWrm
- { 991, 3, 1, 0, "MMX_PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #991 = MMX_PADDSWrr
- { 992, 7, 1, 0, "MMX_PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #992 = MMX_PADDUSBrm
- { 993, 3, 1, 0, "MMX_PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #993 = MMX_PADDUSBrr
- { 994, 7, 1, 0, "MMX_PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #994 = MMX_PADDUSWrm
- { 995, 3, 1, 0, "MMX_PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #995 = MMX_PADDUSWrr
- { 996, 7, 1, 0, "MMX_PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #996 = MMX_PADDWrm
- { 997, 3, 1, 0, "MMX_PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #997 = MMX_PADDWrr
- { 998, 7, 1, 0, "MMX_PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #998 = MMX_PANDNrm
- { 999, 3, 1, 0, "MMX_PANDNrr", 0, 0|5|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #999 = MMX_PANDNrr
- { 1000, 7, 1, 0, "MMX_PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1000 = MMX_PANDrm
- { 1001, 3, 1, 0, "MMX_PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1001 = MMX_PANDrr
- { 1002, 7, 1, 0, "MMX_PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1002 = MMX_PAVGBrm
- { 1003, 3, 1, 0, "MMX_PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1003 = MMX_PAVGBrr
- { 1004, 7, 1, 0, "MMX_PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1004 = MMX_PAVGWrm
- { 1005, 3, 1, 0, "MMX_PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1005 = MMX_PAVGWrr
- { 1006, 7, 1, 0, "MMX_PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1006 = MMX_PCMPEQBrm
- { 1007, 3, 1, 0, "MMX_PCMPEQBrr", 0, 0|5|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1007 = MMX_PCMPEQBrr
- { 1008, 7, 1, 0, "MMX_PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1008 = MMX_PCMPEQDrm
- { 1009, 3, 1, 0, "MMX_PCMPEQDrr", 0, 0|5|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1009 = MMX_PCMPEQDrr
- { 1010, 7, 1, 0, "MMX_PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1010 = MMX_PCMPEQWrm
- { 1011, 3, 1, 0, "MMX_PCMPEQWrr", 0, 0|5|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1011 = MMX_PCMPEQWrr
- { 1012, 7, 1, 0, "MMX_PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1012 = MMX_PCMPGTBrm
- { 1013, 3, 1, 0, "MMX_PCMPGTBrr", 0, 0|5|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1013 = MMX_PCMPGTBrr
- { 1014, 7, 1, 0, "MMX_PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1014 = MMX_PCMPGTDrm
- { 1015, 3, 1, 0, "MMX_PCMPGTDrr", 0, 0|5|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1015 = MMX_PCMPGTDrr
- { 1016, 7, 1, 0, "MMX_PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1016 = MMX_PCMPGTWrm
- { 1017, 3, 1, 0, "MMX_PCMPGTWrr", 0, 0|5|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1017 = MMX_PCMPGTWrr
- { 1018, 3, 1, 0, "MMX_PEXTRWri", 0, 0|5|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1018 = MMX_PEXTRWri
- { 1019, 8, 1, 0, "MMX_PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1019 = MMX_PINSRWrmi
- { 1020, 4, 1, 0, "MMX_PINSRWrri", 0, 0|5|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo138 }, // Inst #1020 = MMX_PINSRWrri
- { 1021, 7, 1, 0, "MMX_PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1021 = MMX_PMADDWDrm
- { 1022, 3, 1, 0, "MMX_PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1022 = MMX_PMADDWDrr
- { 1023, 7, 1, 0, "MMX_PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1023 = MMX_PMAXSWrm
- { 1024, 3, 1, 0, "MMX_PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1024 = MMX_PMAXSWrr
- { 1025, 7, 1, 0, "MMX_PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1025 = MMX_PMAXUBrm
- { 1026, 3, 1, 0, "MMX_PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1026 = MMX_PMAXUBrr
- { 1027, 7, 1, 0, "MMX_PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1027 = MMX_PMINSWrm
- { 1028, 3, 1, 0, "MMX_PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1028 = MMX_PMINSWrr
- { 1029, 7, 1, 0, "MMX_PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1029 = MMX_PMINUBrm
- { 1030, 3, 1, 0, "MMX_PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1030 = MMX_PMINUBrr
- { 1031, 2, 1, 0, "MMX_PMOVMSKBrr", 0, 0|5|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1031 = MMX_PMOVMSKBrr
- { 1032, 7, 1, 0, "MMX_PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1032 = MMX_PMULHUWrm
- { 1033, 3, 1, 0, "MMX_PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1033 = MMX_PMULHUWrr
- { 1034, 7, 1, 0, "MMX_PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1034 = MMX_PMULHWrm
- { 1035, 3, 1, 0, "MMX_PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1035 = MMX_PMULHWrr
- { 1036, 7, 1, 0, "MMX_PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1036 = MMX_PMULLWrm
- { 1037, 3, 1, 0, "MMX_PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1037 = MMX_PMULLWrr
- { 1038, 7, 1, 0, "MMX_PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1038 = MMX_PMULUDQrm
- { 1039, 3, 1, 0, "MMX_PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1039 = MMX_PMULUDQrr
- { 1040, 7, 1, 0, "MMX_PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1040 = MMX_PORrm
- { 1041, 3, 1, 0, "MMX_PORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1041 = MMX_PORrr
- { 1042, 7, 1, 0, "MMX_PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1042 = MMX_PSADBWrm
- { 1043, 3, 1, 0, "MMX_PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1043 = MMX_PSADBWrr
- { 1044, 7, 1, 0, "MMX_PSHUFWmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo140 }, // Inst #1044 = MMX_PSHUFWmi
- { 1045, 3, 1, 0, "MMX_PSHUFWri", 0, 0|5|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo141 }, // Inst #1045 = MMX_PSHUFWri
- { 1046, 3, 1, 0, "MMX_PSLLDri", 0, 0|22|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1046 = MMX_PSLLDri
- { 1047, 7, 1, 0, "MMX_PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1047 = MMX_PSLLDrm
- { 1048, 3, 1, 0, "MMX_PSLLDrr", 0, 0|5|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1048 = MMX_PSLLDrr
- { 1049, 3, 1, 0, "MMX_PSLLQri", 0, 0|22|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1049 = MMX_PSLLQri
- { 1050, 7, 1, 0, "MMX_PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1050 = MMX_PSLLQrm
- { 1051, 3, 1, 0, "MMX_PSLLQrr", 0, 0|5|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1051 = MMX_PSLLQrr
- { 1052, 3, 1, 0, "MMX_PSLLWri", 0, 0|22|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1052 = MMX_PSLLWri
- { 1053, 7, 1, 0, "MMX_PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1053 = MMX_PSLLWrm
- { 1054, 3, 1, 0, "MMX_PSLLWrr", 0, 0|5|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1054 = MMX_PSLLWrr
- { 1055, 3, 1, 0, "MMX_PSRADri", 0, 0|20|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1055 = MMX_PSRADri
- { 1056, 7, 1, 0, "MMX_PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1056 = MMX_PSRADrm
- { 1057, 3, 1, 0, "MMX_PSRADrr", 0, 0|5|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1057 = MMX_PSRADrr
- { 1058, 3, 1, 0, "MMX_PSRAWri", 0, 0|20|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1058 = MMX_PSRAWri
- { 1059, 7, 1, 0, "MMX_PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1059 = MMX_PSRAWrm
- { 1060, 3, 1, 0, "MMX_PSRAWrr", 0, 0|5|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1060 = MMX_PSRAWrr
- { 1061, 3, 1, 0, "MMX_PSRLDri", 0, 0|18|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1061 = MMX_PSRLDri
- { 1062, 7, 1, 0, "MMX_PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1062 = MMX_PSRLDrm
- { 1063, 3, 1, 0, "MMX_PSRLDrr", 0, 0|5|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1063 = MMX_PSRLDrr
- { 1064, 3, 1, 0, "MMX_PSRLQri", 0, 0|18|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1064 = MMX_PSRLQri
- { 1065, 7, 1, 0, "MMX_PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1065 = MMX_PSRLQrm
- { 1066, 3, 1, 0, "MMX_PSRLQrr", 0, 0|5|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1066 = MMX_PSRLQrr
- { 1067, 3, 1, 0, "MMX_PSRLWri", 0, 0|18|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1067 = MMX_PSRLWri
- { 1068, 7, 1, 0, "MMX_PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1068 = MMX_PSRLWrm
- { 1069, 3, 1, 0, "MMX_PSRLWrr", 0, 0|5|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1069 = MMX_PSRLWrr
- { 1070, 7, 1, 0, "MMX_PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1070 = MMX_PSUBBrm
- { 1071, 3, 1, 0, "MMX_PSUBBrr", 0, 0|5|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1071 = MMX_PSUBBrr
- { 1072, 7, 1, 0, "MMX_PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1072 = MMX_PSUBDrm
- { 1073, 3, 1, 0, "MMX_PSUBDrr", 0, 0|5|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1073 = MMX_PSUBDrr
- { 1074, 7, 1, 0, "MMX_PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1074 = MMX_PSUBQrm
- { 1075, 3, 1, 0, "MMX_PSUBQrr", 0, 0|5|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1075 = MMX_PSUBQrr
- { 1076, 7, 1, 0, "MMX_PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1076 = MMX_PSUBSBrm
- { 1077, 3, 1, 0, "MMX_PSUBSBrr", 0, 0|5|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1077 = MMX_PSUBSBrr
- { 1078, 7, 1, 0, "MMX_PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1078 = MMX_PSUBSWrm
- { 1079, 3, 1, 0, "MMX_PSUBSWrr", 0, 0|5|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1079 = MMX_PSUBSWrr
- { 1080, 7, 1, 0, "MMX_PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1080 = MMX_PSUBUSBrm
- { 1081, 3, 1, 0, "MMX_PSUBUSBrr", 0, 0|5|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1081 = MMX_PSUBUSBrr
- { 1082, 7, 1, 0, "MMX_PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1082 = MMX_PSUBUSWrm
- { 1083, 3, 1, 0, "MMX_PSUBUSWrr", 0, 0|5|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1083 = MMX_PSUBUSWrr
- { 1084, 7, 1, 0, "MMX_PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1084 = MMX_PSUBWrm
- { 1085, 3, 1, 0, "MMX_PSUBWrr", 0, 0|5|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1085 = MMX_PSUBWrr
- { 1086, 7, 1, 0, "MMX_PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1086 = MMX_PUNPCKHBWrm
- { 1087, 3, 1, 0, "MMX_PUNPCKHBWrr", 0, 0|5|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1087 = MMX_PUNPCKHBWrr
- { 1088, 7, 1, 0, "MMX_PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1088 = MMX_PUNPCKHDQrm
- { 1089, 3, 1, 0, "MMX_PUNPCKHDQrr", 0, 0|5|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1089 = MMX_PUNPCKHDQrr
- { 1090, 7, 1, 0, "MMX_PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1090 = MMX_PUNPCKHWDrm
- { 1091, 3, 1, 0, "MMX_PUNPCKHWDrr", 0, 0|5|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1091 = MMX_PUNPCKHWDrr
- { 1092, 7, 1, 0, "MMX_PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1092 = MMX_PUNPCKLBWrm
- { 1093, 3, 1, 0, "MMX_PUNPCKLBWrr", 0, 0|5|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1093 = MMX_PUNPCKLBWrr
- { 1094, 7, 1, 0, "MMX_PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1094 = MMX_PUNPCKLDQrm
- { 1095, 3, 1, 0, "MMX_PUNPCKLDQrr", 0, 0|5|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1095 = MMX_PUNPCKLDQrr
- { 1096, 7, 1, 0, "MMX_PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1096 = MMX_PUNPCKLWDrm
- { 1097, 3, 1, 0, "MMX_PUNPCKLWDrr", 0, 0|5|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1097 = MMX_PUNPCKLWDrr
- { 1098, 7, 1, 0, "MMX_PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1098 = MMX_PXORrm
- { 1099, 3, 1, 0, "MMX_PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1099 = MMX_PXORrr
- { 1100, 1, 1, 0, "MMX_V_SET0", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1100 = MMX_V_SET0
- { 1101, 1, 1, 0, "MMX_V_SETALLONES", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1101 = MMX_V_SETALLONES
- { 1102, 0, 0, 0, "MONITOR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1102 = MONITOR
- { 1103, 1, 1, 0, "MOV16ao16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1103 = MOV16ao16
- { 1104, 6, 0, 0, "MOV16mi", 0|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1104 = MOV16mi
- { 1105, 6, 0, 0, "MOV16mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #1105 = MOV16mr
- { 1106, 6, 1, 0, "MOV16ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(140<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1106 = MOV16ms
- { 1107, 1, 0, 0, "MOV16o16a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1107 = MOV16o16a
- { 1108, 1, 1, 0, "MOV16r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1108 = MOV16r0
- { 1109, 2, 1, 0, "MOV16ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<6)|(2<<13)|(184<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1109 = MOV16ri
- { 1110, 6, 1, 0, "MOV16rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1110 = MOV16rm
- { 1111, 2, 1, 0, "MOV16rr", 0, 0|3|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1111 = MOV16rr
- { 1112, 2, 1, 0, "MOV16rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1112 = MOV16rs
- { 1113, 6, 1, 0, "MOV16sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(142<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1113 = MOV16sm
- { 1114, 2, 1, 0, "MOV16sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1114 = MOV16sr
- { 1115, 1, 1, 0, "MOV32ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1115 = MOV32ao32
- { 1116, 6, 0, 0, "MOV32mi", 0|(1<<TID::MayStore), 0|24|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1116 = MOV32mi
- { 1117, 6, 0, 0, "MOV32mr", 0|(1<<TID::MayStore), 0|4|(137<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1117 = MOV32mr
- { 1118, 1, 0, 0, "MOV32o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1118 = MOV32o32a
- { 1119, 1, 1, 0, "MOV32r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #1119 = MOV32r0
- { 1120, 2, 1, 0, "MOV32ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo54 }, // Inst #1120 = MOV32ri
- { 1121, 6, 1, 0, "MOV32rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1121 = MOV32rm
- { 1122, 2, 1, 0, "MOV32rr", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1122 = MOV32rr
- { 1123, 6, 1, 0, "MOV64FSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1123 = MOV64FSrm
- { 1124, 6, 1, 0, "MOV64GSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1124 = MOV64GSrm
- { 1125, 1, 1, 0, "MOV64ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1125 = MOV64ao32
- { 1126, 1, 1, 0, "MOV64ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1126 = MOV64ao8
- { 1127, 6, 0, 0, "MOV64mi32", 0|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1127 = MOV64mi32
- { 1128, 6, 0, 0, "MOV64mr", 0|(1<<TID::MayStore), 0|4|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1128 = MOV64mr
- { 1129, 6, 1, 0, "MOV64ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1129 = MOV64ms
- { 1130, 1, 0, 0, "MOV64o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1130 = MOV64o32a
- { 1131, 1, 0, 0, "MOV64o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1131 = MOV64o8a
- { 1132, 2, 1, 0, "MOV64ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<12)|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1132 = MOV64ri
- { 1133, 2, 1, 0, "MOV64ri32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|16|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1133 = MOV64ri32
- { 1134, 2, 1, 0, "MOV64ri64i32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1134 = MOV64ri64i32
- { 1135, 6, 1, 0, "MOV64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1135 = MOV64rm
- { 1136, 2, 1, 0, "MOV64rr", 0, 0|3|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1136 = MOV64rr
- { 1137, 2, 1, 0, "MOV64rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo148 }, // Inst #1137 = MOV64rs
- { 1138, 6, 1, 0, "MOV64sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1138 = MOV64sm
- { 1139, 2, 1, 0, "MOV64sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo149 }, // Inst #1139 = MOV64sr
- { 1140, 2, 1, 0, "MOV64toPQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1140 = MOV64toPQIrr
- { 1141, 6, 1, 0, "MOV64toSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1141 = MOV64toSDrm
- { 1142, 2, 1, 0, "MOV64toSDrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo81 }, // Inst #1142 = MOV64toSDrr
- { 1143, 1, 1, 0, "MOV8ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1143 = MOV8ao8
- { 1144, 6, 0, 0, "MOV8mi", 0|(1<<TID::MayStore), 0|24|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1144 = MOV8mi
- { 1145, 6, 0, 0, "MOV8mr", 0|(1<<TID::MayStore), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo19 }, // Inst #1145 = MOV8mr
- { 1146, 6, 0, 0, "MOV8mr_NOREX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo151 }, // Inst #1146 = MOV8mr_NOREX
- { 1147, 1, 0, 0, "MOV8o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1147 = MOV8o8a
- { 1148, 1, 1, 0, "MOV8r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #1148 = MOV8r0
- { 1149, 2, 1, 0, "MOV8ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<13)|(176<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1149 = MOV8ri
- { 1150, 6, 1, 0, "MOV8rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo68 }, // Inst #1150 = MOV8rm
- { 1151, 6, 1, 0, "MOV8rm_NOREX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo152 }, // Inst #1151 = MOV8rm_NOREX
- { 1152, 2, 1, 0, "MOV8rr", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo66 }, // Inst #1152 = MOV8rr
- { 1153, 2, 1, 0, "MOV8rr_NOREX", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo153 }, // Inst #1153 = MOV8rr_NOREX
- { 1154, 6, 0, 0, "MOVAPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1154 = MOVAPDmr
- { 1155, 6, 1, 0, "MOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1155 = MOVAPDrm
- { 1156, 2, 1, 0, "MOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1156 = MOVAPDrr
- { 1157, 6, 0, 0, "MOVAPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1157 = MOVAPSmr
- { 1158, 6, 1, 0, "MOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1158 = MOVAPSrm
- { 1159, 2, 1, 0, "MOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1159 = MOVAPSrr
- { 1160, 6, 1, 0, "MOVDDUPrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1160 = MOVDDUPrm
- { 1161, 2, 1, 0, "MOVDDUPrr", 0, 0|5|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1161 = MOVDDUPrr
- { 1162, 6, 1, 0, "MOVDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1162 = MOVDI2PDIrm
- { 1163, 2, 1, 0, "MOVDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1163 = MOVDI2PDIrr
- { 1164, 6, 1, 0, "MOVDI2SSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #1164 = MOVDI2SSrm
- { 1165, 2, 1, 0, "MOVDI2SSrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo84 }, // Inst #1165 = MOVDI2SSrr
- { 1166, 6, 0, 0, "MOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1166 = MOVDQAmr
- { 1167, 6, 1, 0, "MOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1167 = MOVDQArm
- { 1168, 2, 1, 0, "MOVDQArr", 0, 0|5|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1168 = MOVDQArr
- { 1169, 6, 0, 0, "MOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1169 = MOVDQUmr
- { 1170, 6, 0, 0, "MOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1170 = MOVDQUmr_Int
- { 1171, 6, 1, 0, "MOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1171 = MOVDQUrm
- { 1172, 6, 1, 0, "MOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1172 = MOVDQUrm_Int
- { 1173, 3, 1, 0, "MOVHLPSrr", 0, 0|5|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1173 = MOVHLPSrr
- { 1174, 6, 0, 0, "MOVHPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1174 = MOVHPDmr
- { 1175, 7, 1, 0, "MOVHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1175 = MOVHPDrm
- { 1176, 6, 0, 0, "MOVHPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1176 = MOVHPSmr
- { 1177, 7, 1, 0, "MOVHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1177 = MOVHPSrm
- { 1178, 3, 1, 0, "MOVLHPSrr", 0, 0|5|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1178 = MOVLHPSrr
- { 1179, 6, 0, 0, "MOVLPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1179 = MOVLPDmr
- { 1180, 7, 1, 0, "MOVLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1180 = MOVLPDrm
- { 1181, 3, 1, 0, "MOVLPDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1181 = MOVLPDrr
- { 1182, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1182 = MOVLPSmr
- { 1183, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1183 = MOVLPSrm
- { 1184, 3, 1, 0, "MOVLPSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1184 = MOVLPSrr
- { 1185, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1185 = MOVLQ128mr
- { 1186, 3, 1, 0, "MOVLSD2PDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo156 }, // Inst #1186 = MOVLSD2PDrr
- { 1187, 3, 1, 0, "MOVLSS2PSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo157 }, // Inst #1187 = MOVLSS2PSrr
- { 1188, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1188 = MOVMSKPDrr
- { 1189, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1189 = MOVMSKPSrr
- { 1190, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1190 = MOVNTDQArm
- { 1191, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1191 = MOVNTDQmr
- { 1192, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1192 = MOVNTImr
- { 1193, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1193 = MOVNTPDmr
- { 1194, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1194 = MOVNTPSmr
- { 1195, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(3<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo54 }, // Inst #1195 = MOVPC32r
- { 1196, 6, 0, 0, "MOVPD2SDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1196 = MOVPD2SDmr
- { 1197, 2, 1, 0, "MOVPD2SDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo158 }, // Inst #1197 = MOVPD2SDrr
- { 1198, 6, 0, 0, "MOVPDI2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1198 = MOVPDI2DImr
- { 1199, 2, 1, 0, "MOVPDI2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1199 = MOVPDI2DIrr
- { 1200, 6, 0, 0, "MOVPQI2QImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1200 = MOVPQI2QImr
- { 1201, 2, 1, 0, "MOVPQIto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #1201 = MOVPQIto64rr
- { 1202, 6, 0, 0, "MOVPS2SSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1202 = MOVPS2SSmr
- { 1203, 2, 1, 0, "MOVPS2SSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1203 = MOVPS2SSrr
- { 1204, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1204 = MOVQI2PQIrm
- { 1205, 6, 1, 0, "MOVSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1205 = MOVSD2PDrm
- { 1206, 2, 1, 0, "MOVSD2PDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo160 }, // Inst #1206 = MOVSD2PDrr
- { 1207, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1207 = MOVSDmr
- { 1208, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1208 = MOVSDrm
- { 1209, 2, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #1209 = MOVSDrr
- { 1210, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1210 = MOVSDto64mr
- { 1211, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #1211 = MOVSDto64rr
- { 1212, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1212 = MOVSHDUPrm
- { 1213, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1213 = MOVSHDUPrr
- { 1214, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1214 = MOVSLDUPrm
- { 1215, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1215 = MOVSLDUPrr
- { 1216, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1216 = MOVSS2DImr
- { 1217, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1217 = MOVSS2DIrr
- { 1218, 6, 1, 0, "MOVSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1218 = MOVSS2PSrm
- { 1219, 2, 1, 0, "MOVSS2PSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1219 = MOVSS2PSrr
- { 1220, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1220 = MOVSSmr
- { 1221, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #1221 = MOVSSrm
- { 1222, 2, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1222 = MOVSSrr
- { 1223, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1223 = MOVSX16rm8
- { 1224, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1224 = MOVSX16rr8
- { 1225, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1225 = MOVSX32rm16
- { 1226, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1226 = MOVSX32rm8
- { 1227, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1227 = MOVSX32rr16
- { 1228, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1228 = MOVSX32rr8
- { 1229, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1229 = MOVSX64rm16
- { 1230, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1230 = MOVSX64rm32
- { 1231, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1231 = MOVSX64rm8
- { 1232, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1232 = MOVSX64rr16
- { 1233, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #1233 = MOVSX64rr32
- { 1234, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1234 = MOVSX64rr8
- { 1235, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1235 = MOVUPDmr
- { 1236, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1236 = MOVUPDmr_Int
- { 1237, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1237 = MOVUPDrm
- { 1238, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1238 = MOVUPDrm_Int
- { 1239, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1239 = MOVUPDrr
- { 1240, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1240 = MOVUPSmr
- { 1241, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1241 = MOVUPSmr_Int
- { 1242, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1242 = MOVUPSrm
- { 1243, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1243 = MOVUPSrm_Int
- { 1244, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1244 = MOVUPSrr
- { 1245, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1245 = MOVZDI2PDIrm
- { 1246, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1246 = MOVZDI2PDIrr
- { 1247, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1247 = MOVZPQILo2PQIrm
- { 1248, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1248 = MOVZPQILo2PQIrr
- { 1249, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1249 = MOVZQI2PQIrm
- { 1250, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1250 = MOVZQI2PQIrr
- { 1251, 6, 1, 0, "MOVZSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1251 = MOVZSD2PDrm
- { 1252, 6, 1, 0, "MOVZSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1252 = MOVZSS2PSrm
- { 1253, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1253 = MOVZX16rm8
- { 1254, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1254 = MOVZX16rr8
- { 1255, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1255 = MOVZX32_NOREXrm8
- { 1256, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1256 = MOVZX32_NOREXrr8
- { 1257, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1257 = MOVZX32rm16
- { 1258, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1258 = MOVZX32rm8
- { 1259, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1259 = MOVZX32rr16
- { 1260, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1260 = MOVZX32rr8
- { 1261, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1261 = MOVZX64rm16
- { 1262, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1262 = MOVZX64rm32
- { 1263, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1263 = MOVZX64rm8
- { 1264, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1264 = MOVZX64rr16
- { 1265, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #1265 = MOVZX64rr32
- { 1266, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1266 = MOVZX64rr8
- { 1267, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1267 = MOV_Fp3232
- { 1268, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo171 }, // Inst #1268 = MOV_Fp3264
- { 1269, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo172 }, // Inst #1269 = MOV_Fp3280
- { 1270, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo173 }, // Inst #1270 = MOV_Fp6432
- { 1271, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1271 = MOV_Fp6464
- { 1272, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo174 }, // Inst #1272 = MOV_Fp6480
- { 1273, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo175 }, // Inst #1273 = MOV_Fp8032
- { 1274, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo176 }, // Inst #1274 = MOV_Fp8064
- { 1275, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1275 = MOV_Fp8080
- { 1276, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1276 = MPSADBWrmi
- { 1277, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1277 = MPSADBWrri
- { 1278, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo29 }, // Inst #1278 = MUL16m
- { 1279, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo92 }, // Inst #1279 = MUL16r
- { 1280, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo29 }, // Inst #1280 = MUL32m
- { 1281, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo56 }, // Inst #1281 = MUL32r
- { 1282, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo29 }, // Inst #1282 = MUL64m
- { 1283, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo57 }, // Inst #1283 = MUL64r
- { 1284, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo29 }, // Inst #1284 = MUL8m
- { 1285, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #1285 = MUL8r
- { 1286, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1286 = MULPDrm
- { 1287, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1287 = MULPDrr
- { 1288, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1288 = MULPSrm
- { 1289, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1289 = MULPSrr
- { 1290, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1290 = MULSDrm
- { 1291, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1291 = MULSDrm_Int
- { 1292, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1292 = MULSDrr
- { 1293, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1293 = MULSDrr_Int
- { 1294, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1294 = MULSSrm
- { 1295, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1295 = MULSSrm_Int
- { 1296, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1296 = MULSSrr
- { 1297, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1297 = MULSSrr_Int
- { 1298, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1298 = MUL_F32m
- { 1299, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1299 = MUL_F64m
- { 1300, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1300 = MUL_FI16m
- { 1301, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1301 = MUL_FI32m
- { 1302, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1302 = MUL_FPrST0
- { 1303, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1303 = MUL_FST0r
- { 1304, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo31 }, // Inst #1304 = MUL_Fp32
- { 1305, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1305 = MUL_Fp32m
- { 1306, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1306 = MUL_Fp64
- { 1307, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1307 = MUL_Fp64m
- { 1308, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1308 = MUL_Fp64m32
- { 1309, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1309 = MUL_Fp80
- { 1310, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1310 = MUL_Fp80m32
- { 1311, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1311 = MUL_Fp80m64
- { 1312, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1312 = MUL_FpI16m32
- { 1313, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1313 = MUL_FpI16m64
- { 1314, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1314 = MUL_FpI16m80
- { 1315, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1315 = MUL_FpI32m32
- { 1316, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1316 = MUL_FpI32m64
- { 1317, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1317 = MUL_FpI32m80
- { 1318, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1318 = MUL_FrST0
- { 1319, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1319 = MWAIT
- { 1320, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1320 = NEG16m
- { 1321, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1321 = NEG16r
- { 1322, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1322 = NEG32m
- { 1323, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1323 = NEG32r
- { 1324, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1324 = NEG64m
- { 1325, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1325 = NEG64r
- { 1326, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1326 = NEG8m
- { 1327, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1327 = NEG8r
- { 1328, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1328 = NOOP
- { 1329, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1329 = NOOPL
- { 1330, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1330 = NOT16m
- { 1331, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo90 }, // Inst #1331 = NOT16r
- { 1332, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1332 = NOT32m
- { 1333, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1333 = NOT32r
- { 1334, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1334 = NOT64m
- { 1335, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1335 = NOT64r
- { 1336, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1336 = NOT8m
- { 1337, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1337 = NOT8r
- { 1338, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1338 = OR16i16
- { 1339, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1339 = OR16mi
- { 1340, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1340 = OR16mi8
- { 1341, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1341 = OR16mr
- { 1342, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1342 = OR16ri
- { 1343, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1343 = OR16ri8
- { 1344, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1344 = OR16rm
- { 1345, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1345 = OR16rr
- { 1346, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1346 = OR32i32
- { 1347, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1347 = OR32mi
- { 1348, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1348 = OR32mi8
- { 1349, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1349 = OR32mr
- { 1350, 3, 1, 0, "OR32ri", 0, 0|17|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1350 = OR32ri
- { 1351, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1351 = OR32ri8
- { 1352, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1352 = OR32rm
- { 1353, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1353 = OR32rr
- { 1354, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1354 = OR64i32
- { 1355, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1355 = OR64mi32
- { 1356, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1356 = OR64mi8
- { 1357, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1357 = OR64mr
- { 1358, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1358 = OR64ri32
- { 1359, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1359 = OR64ri8
- { 1360, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1360 = OR64rm
- { 1361, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1361 = OR64rr
- { 1362, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1362 = OR8i8
- { 1363, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1363 = OR8mi
- { 1364, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #1364 = OR8mr
- { 1365, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1365 = OR8ri
- { 1366, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1366 = OR8rm
- { 1367, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1367 = OR8rr
- { 1368, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1368 = ORPDrm
- { 1369, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1369 = ORPDrr
- { 1370, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1370 = ORPSrm
- { 1371, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1371 = ORPSrr
- { 1372, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1372 = OUT16ir
- { 1373, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList35, NULL, NULL, 0 }, // Inst #1373 = OUT16rr
- { 1374, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1374 = OUT32ir
- { 1375, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList36, NULL, NULL, 0 }, // Inst #1375 = OUT32rr
- { 1376, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1376 = OUT8ir
- { 1377, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList37, NULL, NULL, 0 }, // Inst #1377 = OUT8rr
- { 1378, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1378 = PABSBrm128
- { 1379, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #1379 = PABSBrm64
- { 1380, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1380 = PABSBrr128
- { 1381, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #1381 = PABSBrr64
- { 1382, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1382 = PABSDrm128
- { 1383, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #1383 = PABSDrm64
- { 1384, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1384 = PABSDrr128
- { 1385, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #1385 = PABSDrr64
- { 1386, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1386 = PABSWrm128
- { 1387, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #1387 = PABSWrm64
- { 1388, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1388 = PABSWrr128
- { 1389, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #1389 = PABSWrr64
- { 1390, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1390 = PACKSSDWrm
- { 1391, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1391 = PACKSSDWrr
- { 1392, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1392 = PACKSSWBrm
- { 1393, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1393 = PACKSSWBrr
- { 1394, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1394 = PACKUSDWrm
- { 1395, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1395 = PACKUSDWrr
- { 1396, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1396 = PACKUSWBrm
- { 1397, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1397 = PACKUSWBrr
- { 1398, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1398 = PADDBrm
- { 1399, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1399 = PADDBrr
- { 1400, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1400 = PADDDrm
- { 1401, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1401 = PADDDrr
- { 1402, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1402 = PADDQrm
- { 1403, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1403 = PADDQrr
- { 1404, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1404 = PADDSBrm
- { 1405, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1405 = PADDSBrr
- { 1406, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1406 = PADDSWrm
- { 1407, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1407 = PADDSWrr
- { 1408, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1408 = PADDUSBrm
- { 1409, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1409 = PADDUSBrr
- { 1410, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1410 = PADDUSWrm
- { 1411, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1411 = PADDUSWrr
- { 1412, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1412 = PADDWrm
- { 1413, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1413 = PADDWrr
- { 1414, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1414 = PALIGNR128rm
- { 1415, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1415 = PALIGNR128rr
- { 1416, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1416 = PALIGNR64rm
- { 1417, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1417 = PALIGNR64rr
- { 1418, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1418 = PANDNrm
- { 1419, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1419 = PANDNrr
- { 1420, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1420 = PANDrm
- { 1421, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1421 = PANDrr
- { 1422, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1422 = PAVGBrm
- { 1423, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1423 = PAVGBrr
- { 1424, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1424 = PAVGWrm
- { 1425, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1425 = PAVGWrr
- { 1426, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo23 }, // Inst #1426 = PBLENDVBrm0
- { 1427, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1427 = PBLENDVBrr0
- { 1428, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1428 = PBLENDWrmi
- { 1429, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1429 = PBLENDWrri
- { 1430, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1430 = PCMPEQBrm
- { 1431, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1431 = PCMPEQBrr
- { 1432, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1432 = PCMPEQDrm
- { 1433, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1433 = PCMPEQDrr
- { 1434, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1434 = PCMPEQQrm
- { 1435, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1435 = PCMPEQQrr
- { 1436, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1436 = PCMPEQWrm
- { 1437, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1437 = PCMPEQWrr
- { 1438, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1438 = PCMPESTRIArm
- { 1439, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1439 = PCMPESTRIArr
- { 1440, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1440 = PCMPESTRICrm
- { 1441, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1441 = PCMPESTRICrr
- { 1442, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1442 = PCMPESTRIOrm
- { 1443, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1443 = PCMPESTRIOrr
- { 1444, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1444 = PCMPESTRISrm
- { 1445, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1445 = PCMPESTRISrr
- { 1446, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1446 = PCMPESTRIZrm
- { 1447, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1447 = PCMPESTRIZrr
- { 1448, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1448 = PCMPESTRIrm
- { 1449, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1449 = PCMPESTRIrr
- { 1450, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo180 }, // Inst #1450 = PCMPESTRM128MEM
- { 1451, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo65 }, // Inst #1451 = PCMPESTRM128REG
- { 1452, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo178 }, // Inst #1452 = PCMPESTRM128rm
- { 1453, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo179 }, // Inst #1453 = PCMPESTRM128rr
- { 1454, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1454 = PCMPGTBrm
- { 1455, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1455 = PCMPGTBrr
- { 1456, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1456 = PCMPGTDrm
- { 1457, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1457 = PCMPGTDrr
- { 1458, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1458 = PCMPGTQrm
- { 1459, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1459 = PCMPGTQrr
- { 1460, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1460 = PCMPGTWrm
- { 1461, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1461 = PCMPGTWrr
- { 1462, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1462 = PCMPISTRIArm
- { 1463, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1463 = PCMPISTRIArr
- { 1464, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1464 = PCMPISTRICrm
- { 1465, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1465 = PCMPISTRICrr
- { 1466, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1466 = PCMPISTRIOrm
- { 1467, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1467 = PCMPISTRIOrr
- { 1468, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1468 = PCMPISTRISrm
- { 1469, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1469 = PCMPISTRISrr
- { 1470, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1470 = PCMPISTRIZrm
- { 1471, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1471 = PCMPISTRIZrr
- { 1472, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1472 = PCMPISTRIrm
- { 1473, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1473 = PCMPISTRIrr
- { 1474, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo180 }, // Inst #1474 = PCMPISTRM128MEM
- { 1475, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo65 }, // Inst #1475 = PCMPISTRM128REG
- { 1476, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList39, Barriers1, OperandInfo178 }, // Inst #1476 = PCMPISTRM128rm
- { 1477, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList39, Barriers1, OperandInfo179 }, // Inst #1477 = PCMPISTRM128rr
- { 1478, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo94 }, // Inst #1478 = PEXTRBmr
- { 1479, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1479 = PEXTRBrr
- { 1480, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo94 }, // Inst #1480 = PEXTRDmr
- { 1481, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1481 = PEXTRDrr
- { 1482, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo94 }, // Inst #1482 = PEXTRQmr
- { 1483, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo181 }, // Inst #1483 = PEXTRQrr
- { 1484, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo94 }, // Inst #1484 = PEXTRWmr
- { 1485, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1485 = PEXTRWri
- { 1486, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1486 = PHADDDrm128
- { 1487, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1487 = PHADDDrm64
- { 1488, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1488 = PHADDDrr128
- { 1489, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1489 = PHADDDrr64
- { 1490, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1490 = PHADDSWrm128
- { 1491, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1491 = PHADDSWrm64
- { 1492, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1492 = PHADDSWrr128
- { 1493, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1493 = PHADDSWrr64
- { 1494, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1494 = PHADDWrm128
- { 1495, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1495 = PHADDWrm64
- { 1496, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1496 = PHADDWrr128
- { 1497, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1497 = PHADDWrr64
- { 1498, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1498 = PHMINPOSUWrm128
- { 1499, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1499 = PHMINPOSUWrr128
- { 1500, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1500 = PHSUBDrm128
- { 1501, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1501 = PHSUBDrm64
- { 1502, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1502 = PHSUBDrr128
- { 1503, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1503 = PHSUBDrr64
- { 1504, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1504 = PHSUBSWrm128
- { 1505, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1505 = PHSUBSWrm64
- { 1506, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1506 = PHSUBSWrr128
- { 1507, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1507 = PHSUBSWrr64
- { 1508, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1508 = PHSUBWrm128
- { 1509, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1509 = PHSUBWrm64
- { 1510, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1510 = PHSUBWrr128
- { 1511, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1511 = PHSUBWrr64
- { 1512, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1512 = PINSRBrm
- { 1513, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo182 }, // Inst #1513 = PINSRBrr
- { 1514, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1514 = PINSRDrm
- { 1515, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo182 }, // Inst #1515 = PINSRDrr
- { 1516, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1516 = PINSRQrm
- { 1517, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1517 = PINSRQrr
- { 1518, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1518 = PINSRWrmi
- { 1519, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo182 }, // Inst #1519 = PINSRWrri
- { 1520, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1520 = PMADDUBSWrm128
- { 1521, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1521 = PMADDUBSWrm64
- { 1522, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1522 = PMADDUBSWrr128
- { 1523, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1523 = PMADDUBSWrr64
- { 1524, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1524 = PMADDWDrm
- { 1525, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1525 = PMADDWDrr
- { 1526, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1526 = PMAXSBrm
- { 1527, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1527 = PMAXSBrr
- { 1528, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1528 = PMAXSDrm
- { 1529, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1529 = PMAXSDrr
- { 1530, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1530 = PMAXSWrm
- { 1531, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1531 = PMAXSWrr
- { 1532, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1532 = PMAXUBrm
- { 1533, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1533 = PMAXUBrr
- { 1534, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1534 = PMAXUDrm
- { 1535, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1535 = PMAXUDrr
- { 1536, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1536 = PMAXUWrm
- { 1537, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1537 = PMAXUWrr
- { 1538, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1538 = PMINSBrm
- { 1539, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1539 = PMINSBrr
- { 1540, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1540 = PMINSDrm
- { 1541, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1541 = PMINSDrr
- { 1542, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1542 = PMINSWrm
- { 1543, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1543 = PMINSWrr
- { 1544, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1544 = PMINUBrm
- { 1545, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1545 = PMINUBrr
- { 1546, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1546 = PMINUDrm
- { 1547, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1547 = PMINUDrr
- { 1548, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1548 = PMINUWrm
- { 1549, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1549 = PMINUWrr
- { 1550, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1550 = PMOVMSKBrr
- { 1551, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1551 = PMOVSXBDrm
- { 1552, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1552 = PMOVSXBDrr
- { 1553, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1553 = PMOVSXBQrm
- { 1554, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1554 = PMOVSXBQrr
- { 1555, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1555 = PMOVSXBWrm
- { 1556, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1556 = PMOVSXBWrr
- { 1557, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1557 = PMOVSXDQrm
- { 1558, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1558 = PMOVSXDQrr
- { 1559, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1559 = PMOVSXWDrm
- { 1560, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1560 = PMOVSXWDrr
- { 1561, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1561 = PMOVSXWQrm
- { 1562, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1562 = PMOVSXWQrr
- { 1563, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1563 = PMOVZXBDrm
- { 1564, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1564 = PMOVZXBDrr
- { 1565, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1565 = PMOVZXBQrm
- { 1566, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1566 = PMOVZXBQrr
- { 1567, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1567 = PMOVZXBWrm
- { 1568, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1568 = PMOVZXBWrr
- { 1569, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1569 = PMOVZXDQrm
- { 1570, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1570 = PMOVZXDQrr
- { 1571, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1571 = PMOVZXWDrm
- { 1572, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1572 = PMOVZXWDrr
- { 1573, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1573 = PMOVZXWQrm
- { 1574, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1574 = PMOVZXWQrr
- { 1575, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1575 = PMULDQrm
- { 1576, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1576 = PMULDQrr
- { 1577, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1577 = PMULHRSWrm128
- { 1578, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1578 = PMULHRSWrm64
- { 1579, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1579 = PMULHRSWrr128
- { 1580, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1580 = PMULHRSWrr64
- { 1581, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1581 = PMULHUWrm
- { 1582, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1582 = PMULHUWrr
- { 1583, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1583 = PMULHWrm
- { 1584, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1584 = PMULHWrr
- { 1585, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1585 = PMULLDrm
- { 1586, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1586 = PMULLDrm_int
- { 1587, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1587 = PMULLDrr
- { 1588, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1588 = PMULLDrr_int
- { 1589, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1589 = PMULLWrm
- { 1590, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1590 = PMULLWrr
- { 1591, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1591 = PMULUDQrm
- { 1592, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1592 = PMULUDQrr
- { 1593, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo92 }, // Inst #1593 = POP16r
- { 1594, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo29 }, // Inst #1594 = POP16rmm
- { 1595, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo92 }, // Inst #1595 = POP16rmr
- { 1596, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo56 }, // Inst #1596 = POP32r
- { 1597, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo29 }, // Inst #1597 = POP32rmm
- { 1598, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo56 }, // Inst #1598 = POP32rmr
- { 1599, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo57 }, // Inst #1599 = POP64r
- { 1600, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo29 }, // Inst #1600 = POP64rmm
- { 1601, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo57 }, // Inst #1601 = POP64rmr
- { 1602, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1602 = POPFD
- { 1603, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1603 = POPFQ
- { 1604, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1604 = PORrm
- { 1605, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1605 = PORrr
- { 1606, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1606 = PREFETCHNTA
- { 1607, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1607 = PREFETCHT0
- { 1608, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1608 = PREFETCHT1
- { 1609, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1609 = PREFETCHT2
- { 1610, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1610 = PSADBWrm
- { 1611, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1611 = PSADBWrr
- { 1612, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo23 }, // Inst #1612 = PSHUFBrm128
- { 1613, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo134 }, // Inst #1613 = PSHUFBrm64
- { 1614, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1614 = PSHUFBrr128
- { 1615, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo135 }, // Inst #1615 = PSHUFBrr64
- { 1616, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1616 = PSHUFDmi
- { 1617, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1617 = PSHUFDri
- { 1618, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1618 = PSHUFHWmi
- { 1619, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1619 = PSHUFHWri
- { 1620, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1620 = PSHUFLWmi
- { 1621, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1621 = PSHUFLWri
- { 1622, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1622 = PSIGNBrm128
- { 1623, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1623 = PSIGNBrm64
- { 1624, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1624 = PSIGNBrr128
- { 1625, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1625 = PSIGNBrr64
- { 1626, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1626 = PSIGNDrm128
- { 1627, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1627 = PSIGNDrm64
- { 1628, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1628 = PSIGNDrr128
- { 1629, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1629 = PSIGNDrr64
- { 1630, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1630 = PSIGNWrm128
- { 1631, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1631 = PSIGNWrm64
- { 1632, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1632 = PSIGNWrr128
- { 1633, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1633 = PSIGNWrr64
- { 1634, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1634 = PSLLDQri
- { 1635, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1635 = PSLLDri
- { 1636, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1636 = PSLLDrm
- { 1637, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1637 = PSLLDrr
- { 1638, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1638 = PSLLQri
- { 1639, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1639 = PSLLQrm
- { 1640, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1640 = PSLLQrr
- { 1641, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1641 = PSLLWri
- { 1642, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1642 = PSLLWrm
- { 1643, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1643 = PSLLWrr
- { 1644, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1644 = PSRADri
- { 1645, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1645 = PSRADrm
- { 1646, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1646 = PSRADrr
- { 1647, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1647 = PSRAWri
- { 1648, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1648 = PSRAWrm
- { 1649, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1649 = PSRAWrr
- { 1650, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1650 = PSRLDQri
- { 1651, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1651 = PSRLDri
- { 1652, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1652 = PSRLDrm
- { 1653, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1653 = PSRLDrr
- { 1654, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1654 = PSRLQri
- { 1655, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1655 = PSRLQrm
- { 1656, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1656 = PSRLQrr
- { 1657, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1657 = PSRLWri
- { 1658, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1658 = PSRLWrm
- { 1659, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1659 = PSRLWrr
- { 1660, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1660 = PSUBBrm
- { 1661, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1661 = PSUBBrr
- { 1662, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1662 = PSUBDrm
- { 1663, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1663 = PSUBDrr
- { 1664, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1664 = PSUBQrm
- { 1665, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1665 = PSUBQrr
- { 1666, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1666 = PSUBSBrm
- { 1667, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1667 = PSUBSBrr
- { 1668, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1668 = PSUBSWrm
- { 1669, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1669 = PSUBSWrr
- { 1670, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1670 = PSUBUSBrm
- { 1671, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1671 = PSUBUSBrr
- { 1672, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1672 = PSUBUSWrm
- { 1673, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1673 = PSUBUSWrr
- { 1674, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1674 = PSUBWrm
- { 1675, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1675 = PSUBWrr
- { 1676, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo73 }, // Inst #1676 = PTESTrm
- { 1677, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1677 = PTESTrr
- { 1678, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1678 = PUNPCKHBWrm
- { 1679, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1679 = PUNPCKHBWrr
- { 1680, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1680 = PUNPCKHDQrm
- { 1681, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1681 = PUNPCKHDQrr
- { 1682, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1682 = PUNPCKHQDQrm
- { 1683, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1683 = PUNPCKHQDQrr
- { 1684, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1684 = PUNPCKHWDrm
- { 1685, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1685 = PUNPCKHWDrr
- { 1686, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1686 = PUNPCKLBWrm
- { 1687, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1687 = PUNPCKLBWrr
- { 1688, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1688 = PUNPCKLDQrm
- { 1689, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1689 = PUNPCKLDQrr
- { 1690, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1690 = PUNPCKLQDQrm
- { 1691, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1691 = PUNPCKLQDQrr
- { 1692, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1692 = PUNPCKLWDrm
- { 1693, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1693 = PUNPCKLWDrr
- { 1694, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo92 }, // Inst #1694 = PUSH16r
- { 1695, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo29 }, // Inst #1695 = PUSH16rmm
- { 1696, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo92 }, // Inst #1696 = PUSH16rmr
- { 1697, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1697 = PUSH32i16
- { 1698, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1698 = PUSH32i32
- { 1699, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1699 = PUSH32i8
- { 1700, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo56 }, // Inst #1700 = PUSH32r
- { 1701, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo29 }, // Inst #1701 = PUSH32rmm
- { 1702, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo56 }, // Inst #1702 = PUSH32rmr
- { 1703, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1703 = PUSH64i16
- { 1704, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1704 = PUSH64i32
- { 1705, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1705 = PUSH64i8
- { 1706, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo57 }, // Inst #1706 = PUSH64r
- { 1707, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo29 }, // Inst #1707 = PUSH64rmm
- { 1708, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo57 }, // Inst #1708 = PUSH64rmr
- { 1709, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1709 = PUSHFD
- { 1710, 0, 0, 0, "PUSHFQ", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1710 = PUSHFQ
- { 1711, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1711 = PXORrm
- { 1712, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1712 = PXORrr
- { 1713, 10, 1, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1713 = RCL16m1
- { 1714, 10, 1, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1714 = RCL16mCL
- { 1715, 11, 1, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1715 = RCL16mi
- { 1716, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1716 = RCL16r1
- { 1717, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1717 = RCL16rCL
- { 1718, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1718 = RCL16ri
- { 1719, 10, 1, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1719 = RCL32m1
- { 1720, 10, 1, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1720 = RCL32mCL
- { 1721, 11, 1, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1721 = RCL32mi
- { 1722, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1722 = RCL32r1
- { 1723, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1723 = RCL32rCL
- { 1724, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1724 = RCL32ri
- { 1725, 10, 1, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1725 = RCL64m1
- { 1726, 10, 1, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1726 = RCL64mCL
- { 1727, 11, 1, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1727 = RCL64mi
- { 1728, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1728 = RCL64r1
- { 1729, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1729 = RCL64rCL
- { 1730, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1730 = RCL64ri
- { 1731, 10, 1, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1731 = RCL8m1
- { 1732, 10, 1, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1732 = RCL8mCL
- { 1733, 11, 1, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1733 = RCL8mi
- { 1734, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1734 = RCL8r1
- { 1735, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1735 = RCL8rCL
- { 1736, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1736 = RCL8ri
- { 1737, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1737 = RCPPSm
- { 1738, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1738 = RCPPSm_Int
- { 1739, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1739 = RCPPSr
- { 1740, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1740 = RCPPSr_Int
- { 1741, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #1741 = RCPSSm
- { 1742, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1742 = RCPSSm_Int
- { 1743, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1743 = RCPSSr
- { 1744, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1744 = RCPSSr_Int
- { 1745, 10, 1, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1745 = RCR16m1
- { 1746, 10, 1, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1746 = RCR16mCL
- { 1747, 11, 1, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1747 = RCR16mi
- { 1748, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1748 = RCR16r1
- { 1749, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1749 = RCR16rCL
- { 1750, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1750 = RCR16ri
- { 1751, 10, 1, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1751 = RCR32m1
- { 1752, 10, 1, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1752 = RCR32mCL
- { 1753, 11, 1, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1753 = RCR32mi
- { 1754, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1754 = RCR32r1
- { 1755, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1755 = RCR32rCL
- { 1756, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1756 = RCR32ri
- { 1757, 10, 1, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1757 = RCR64m1
- { 1758, 10, 1, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1758 = RCR64mCL
- { 1759, 11, 1, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1759 = RCR64mi
- { 1760, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1760 = RCR64r1
- { 1761, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1761 = RCR64rCL
- { 1762, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1762 = RCR64ri
- { 1763, 10, 1, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1763 = RCR8m1
- { 1764, 10, 1, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1764 = RCR8mCL
- { 1765, 11, 1, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1765 = RCR8mi
- { 1766, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1766 = RCR8r1
- { 1767, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1767 = RCR8rCL
- { 1768, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1768 = RCR8ri
- { 1769, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList16, NULL, 0 }, // Inst #1769 = RDTSC
- { 1770, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1770 = REP_MOVSB
- { 1771, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1771 = REP_MOVSD
- { 1772, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList42, ImplicitList42, NULL, 0 }, // Inst #1772 = REP_MOVSQ
- { 1773, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1773 = REP_MOVSW
- { 1774, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList43, ImplicitList44, NULL, 0 }, // Inst #1774 = REP_STOSB
- { 1775, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList45, ImplicitList44, NULL, 0 }, // Inst #1775 = REP_STOSD
- { 1776, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList46, ImplicitList47, NULL, 0 }, // Inst #1776 = REP_STOSQ
- { 1777, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList48, ImplicitList44, NULL, 0 }, // Inst #1777 = REP_STOSW
- { 1778, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1778 = RET
- { 1779, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(2<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1779 = RETI
- { 1780, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1780 = ROL16m1
- { 1781, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1781 = ROL16mCL
- { 1782, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1782 = ROL16mi
- { 1783, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1783 = ROL16r1
- { 1784, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1784 = ROL16rCL
- { 1785, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1785 = ROL16ri
- { 1786, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1786 = ROL32m1
- { 1787, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1787 = ROL32mCL
- { 1788, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1788 = ROL32mi
- { 1789, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1789 = ROL32r1
- { 1790, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1790 = ROL32rCL
- { 1791, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1791 = ROL32ri
- { 1792, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1792 = ROL64m1
- { 1793, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1793 = ROL64mCL
- { 1794, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1794 = ROL64mi
- { 1795, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1795 = ROL64r1
- { 1796, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1796 = ROL64rCL
- { 1797, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1797 = ROL64ri
- { 1798, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1798 = ROL8m1
- { 1799, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1799 = ROL8mCL
- { 1800, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1800 = ROL8mi
- { 1801, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1801 = ROL8r1
- { 1802, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1802 = ROL8rCL
- { 1803, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1803 = ROL8ri
- { 1804, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1804 = ROR16m1
- { 1805, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1805 = ROR16mCL
- { 1806, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1806 = ROR16mi
- { 1807, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1807 = ROR16r1
- { 1808, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1808 = ROR16rCL
- { 1809, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1809 = ROR16ri
- { 1810, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1810 = ROR32m1
- { 1811, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1811 = ROR32mCL
- { 1812, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1812 = ROR32mi
- { 1813, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1813 = ROR32r1
- { 1814, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1814 = ROR32rCL
- { 1815, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1815 = ROR32ri
- { 1816, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1816 = ROR64m1
- { 1817, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1817 = ROR64mCL
- { 1818, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1818 = ROR64mi
- { 1819, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1819 = ROR64r1
- { 1820, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1820 = ROR64rCL
- { 1821, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1821 = ROR64ri
- { 1822, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1822 = ROR8m1
- { 1823, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1823 = ROR8mCL
- { 1824, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1824 = ROR8mi
- { 1825, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1825 = ROR8r1
- { 1826, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1826 = ROR8rCL
- { 1827, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1827 = ROR8ri
- { 1828, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1828 = ROUNDPDm_Int
- { 1829, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1829 = ROUNDPDr_Int
- { 1830, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1830 = ROUNDPSm_Int
- { 1831, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1831 = ROUNDPSr_Int
- { 1832, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1832 = ROUNDSDm_Int
- { 1833, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1833 = ROUNDSDr_Int
- { 1834, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1834 = ROUNDSSm_Int
- { 1835, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1835 = ROUNDSSr_Int
- { 1836, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1836 = RSQRTPSm
- { 1837, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1837 = RSQRTPSm_Int
- { 1838, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1838 = RSQRTPSr
- { 1839, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1839 = RSQRTPSr_Int
- { 1840, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #1840 = RSQRTSSm
- { 1841, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1841 = RSQRTSSm_Int
- { 1842, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1842 = RSQRTSSr
- { 1843, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1843 = RSQRTSSr_Int
- { 1844, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList26, ImplicitList1, Barriers1, 0 }, // Inst #1844 = SAHF
- { 1845, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1845 = SAR16m1
- { 1846, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1846 = SAR16mCL
- { 1847, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1847 = SAR16mi
- { 1848, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1848 = SAR16r1
- { 1849, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1849 = SAR16rCL
- { 1850, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1850 = SAR16ri
- { 1851, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1851 = SAR32m1
- { 1852, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1852 = SAR32mCL
- { 1853, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1853 = SAR32mi
- { 1854, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1854 = SAR32r1
- { 1855, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1855 = SAR32rCL
- { 1856, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1856 = SAR32ri
- { 1857, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1857 = SAR64m1
- { 1858, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1858 = SAR64mCL
- { 1859, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1859 = SAR64mi
- { 1860, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1860 = SAR64r1
- { 1861, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1861 = SAR64rCL
- { 1862, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1862 = SAR64ri
- { 1863, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1863 = SAR8m1
- { 1864, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1864 = SAR8mCL
- { 1865, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1865 = SAR8mi
- { 1866, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1866 = SAR8r1
- { 1867, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1867 = SAR8rCL
- { 1868, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1868 = SAR8ri
- { 1869, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1869 = SBB16i16
- { 1870, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1870 = SBB16mi
- { 1871, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1871 = SBB16mi8
- { 1872, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1872 = SBB16mr
- { 1873, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1873 = SBB16ri
- { 1874, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1874 = SBB16ri8
- { 1875, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1875 = SBB16rm
- { 1876, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1876 = SBB16rr
- { 1877, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1877 = SBB32i32
- { 1878, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1878 = SBB32mi
- { 1879, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1879 = SBB32mi8
- { 1880, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1880 = SBB32mr
- { 1881, 3, 1, 0, "SBB32ri", 0, 0|19|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1881 = SBB32ri
- { 1882, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1882 = SBB32ri8
- { 1883, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1883 = SBB32rm
- { 1884, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1884 = SBB32rr
- { 1885, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1885 = SBB64i32
- { 1886, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1886 = SBB64mi32
- { 1887, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1887 = SBB64mi8
- { 1888, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1888 = SBB64mr
- { 1889, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1889 = SBB64ri32
- { 1890, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1890 = SBB64ri8
- { 1891, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1891 = SBB64rm
- { 1892, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1892 = SBB64rr
- { 1893, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1893 = SBB8i8
- { 1894, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1894 = SBB8mi
- { 1895, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #1895 = SBB8mr
- { 1896, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1896 = SBB8ri
- { 1897, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1897 = SBB8rm
- { 1898, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1898 = SBB8rr
- { 1899, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #1899 = SCAS16
- { 1900, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #1900 = SCAS32
- { 1901, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #1901 = SCAS64
- { 1902, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #1902 = SCAS8
- { 1903, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1903 = SETAEm
- { 1904, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1904 = SETAEr
- { 1905, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1905 = SETAm
- { 1906, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1906 = SETAr
- { 1907, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1907 = SETBEm
- { 1908, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1908 = SETBEr
- { 1909, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1909 = SETB_C16r
- { 1910, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #1910 = SETB_C32r
- { 1911, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #1911 = SETB_C64r
- { 1912, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #1912 = SETB_C8r
- { 1913, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1913 = SETBm
- { 1914, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1914 = SETBr
- { 1915, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1915 = SETEm
- { 1916, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1916 = SETEr
- { 1917, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1917 = SETGEm
- { 1918, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1918 = SETGEr
- { 1919, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1919 = SETGm
- { 1920, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1920 = SETGr
- { 1921, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1921 = SETLEm
- { 1922, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1922 = SETLEr
- { 1923, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1923 = SETLm
- { 1924, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1924 = SETLr
- { 1925, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1925 = SETNEm
- { 1926, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1926 = SETNEr
- { 1927, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1927 = SETNOm
- { 1928, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1928 = SETNOr
- { 1929, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1929 = SETNPm
- { 1930, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1930 = SETNPr
- { 1931, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1931 = SETNSm
- { 1932, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1932 = SETNSr
- { 1933, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1933 = SETOm
- { 1934, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1934 = SETOr
- { 1935, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1935 = SETPm
- { 1936, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1936 = SETPr
- { 1937, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1937 = SETSm
- { 1938, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1938 = SETSr
- { 1939, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #1939 = SFENCE
- { 1940, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1940 = SHL16m1
- { 1941, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1941 = SHL16mCL
- { 1942, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1942 = SHL16mi
- { 1943, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1943 = SHL16r1
- { 1944, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1944 = SHL16rCL
- { 1945, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1945 = SHL16ri
- { 1946, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1946 = SHL32m1
- { 1947, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1947 = SHL32mCL
- { 1948, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1948 = SHL32mi
- { 1949, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1949 = SHL32r1
- { 1950, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1950 = SHL32rCL
- { 1951, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1951 = SHL32ri
- { 1952, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1952 = SHL64m1
- { 1953, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1953 = SHL64mCL
- { 1954, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1954 = SHL64mi
- { 1955, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1955 = SHL64r1
- { 1956, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1956 = SHL64rCL
- { 1957, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1957 = SHL64ri
- { 1958, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1958 = SHL8m1
- { 1959, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1959 = SHL8mCL
- { 1960, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1960 = SHL8mi
- { 1961, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1961 = SHL8r1
- { 1962, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1962 = SHL8rCL
- { 1963, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1963 = SHL8ri
- { 1964, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1964 = SHLD16mrCL
- { 1965, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo187 }, // Inst #1965 = SHLD16mri8
- { 1966, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1966 = SHLD16rrCL
- { 1967, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo188 }, // Inst #1967 = SHLD16rri8
- { 1968, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1968 = SHLD32mrCL
- { 1969, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1969 = SHLD32mri8
- { 1970, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1970 = SHLD32rrCL
- { 1971, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #1971 = SHLD32rri8
- { 1972, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1972 = SHLD64mrCL
- { 1973, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #1973 = SHLD64mri8
- { 1974, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1974 = SHLD64rrCL
- { 1975, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #1975 = SHLD64rri8
- { 1976, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1976 = SHR16m1
- { 1977, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1977 = SHR16mCL
- { 1978, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1978 = SHR16mi
- { 1979, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1979 = SHR16r1
- { 1980, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1980 = SHR16rCL
- { 1981, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1981 = SHR16ri
- { 1982, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1982 = SHR32m1
- { 1983, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1983 = SHR32mCL
- { 1984, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1984 = SHR32mi
- { 1985, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1985 = SHR32r1
- { 1986, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1986 = SHR32rCL
- { 1987, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1987 = SHR32ri
- { 1988, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1988 = SHR64m1
- { 1989, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1989 = SHR64mCL
- { 1990, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1990 = SHR64mi
- { 1991, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1991 = SHR64r1
- { 1992, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1992 = SHR64rCL
- { 1993, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1993 = SHR64ri
- { 1994, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1994 = SHR8m1
- { 1995, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1995 = SHR8mCL
- { 1996, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1996 = SHR8mi
- { 1997, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1997 = SHR8r1
- { 1998, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1998 = SHR8rCL
- { 1999, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1999 = SHR8ri
- { 2000, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2000 = SHRD16mrCL
- { 2001, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo187 }, // Inst #2001 = SHRD16mri8
- { 2002, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2002 = SHRD16rrCL
- { 2003, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo188 }, // Inst #2003 = SHRD16rri8
- { 2004, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2004 = SHRD32mrCL
- { 2005, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #2005 = SHRD32mri8
- { 2006, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2006 = SHRD32rrCL
- { 2007, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #2007 = SHRD32rri8
- { 2008, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2008 = SHRD64mrCL
- { 2009, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #2009 = SHRD64mri8
- { 2010, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2010 = SHRD64rrCL
- { 2011, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #2011 = SHRD64rri8
- { 2012, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #2012 = SHUFPDrmi
- { 2013, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2013 = SHUFPDrri
- { 2014, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #2014 = SHUFPSrmi
- { 2015, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2015 = SHUFPSrri
- { 2016, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2016 = SIN_F
- { 2017, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2017 = SIN_Fp32
- { 2018, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2018 = SIN_Fp64
- { 2019, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2019 = SIN_Fp80
- { 2020, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2020 = SQRTPDm
- { 2021, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2021 = SQRTPDm_Int
- { 2022, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2022 = SQRTPDr
- { 2023, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2023 = SQRTPDr_Int
- { 2024, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2024 = SQRTPSm
- { 2025, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2025 = SQRTPSm_Int
- { 2026, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2026 = SQRTPSr
- { 2027, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2027 = SQRTPSr_Int
- { 2028, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2028 = SQRTSDm
- { 2029, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2029 = SQRTSDm_Int
- { 2030, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #2030 = SQRTSDr
- { 2031, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2031 = SQRTSDr_Int
- { 2032, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #2032 = SQRTSSm
- { 2033, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2033 = SQRTSSm_Int
- { 2034, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2034 = SQRTSSr
- { 2035, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2035 = SQRTSSr_Int
- { 2036, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2036 = SQRT_F
- { 2037, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2037 = SQRT_Fp32
- { 2038, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2038 = SQRT_Fp64
- { 2039, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2039 = SQRT_Fp80
- { 2040, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2040 = STMXCSR
- { 2041, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2041 = ST_F32m
- { 2042, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2042 = ST_F64m
- { 2043, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2043 = ST_FP32m
- { 2044, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2044 = ST_FP64m
- { 2045, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2045 = ST_FP80m
- { 2046, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2046 = ST_FPrr
- { 2047, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #2047 = ST_Fp32m
- { 2048, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2048 = ST_Fp64m
- { 2049, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2049 = ST_Fp64m32
- { 2050, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2050 = ST_Fp80m32
- { 2051, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2051 = ST_Fp80m64
- { 2052, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #2052 = ST_FpP32m
- { 2053, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2053 = ST_FpP64m
- { 2054, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2054 = ST_FpP64m32
- { 2055, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2055 = ST_FpP80m
- { 2056, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2056 = ST_FpP80m32
- { 2057, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2057 = ST_FpP80m64
- { 2058, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2058 = ST_Frr
- { 2059, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2059 = SUB16i16
- { 2060, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2060 = SUB16mi
- { 2061, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2061 = SUB16mi8
- { 2062, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2062 = SUB16mr
- { 2063, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2063 = SUB16ri
- { 2064, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2064 = SUB16ri8
- { 2065, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2065 = SUB16rm
- { 2066, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2066 = SUB16rr
- { 2067, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2067 = SUB32i32
- { 2068, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2068 = SUB32mi
- { 2069, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2069 = SUB32mi8
- { 2070, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2070 = SUB32mr
- { 2071, 3, 1, 0, "SUB32ri", 0, 0|21|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2071 = SUB32ri
- { 2072, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2072 = SUB32ri8
- { 2073, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2073 = SUB32rm
- { 2074, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2074 = SUB32rr
- { 2075, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2075 = SUB64i32
- { 2076, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2076 = SUB64mi32
- { 2077, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2077 = SUB64mi8
- { 2078, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2078 = SUB64mr
- { 2079, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2079 = SUB64ri32
- { 2080, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2080 = SUB64ri8
- { 2081, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2081 = SUB64rm
- { 2082, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2082 = SUB64rr
- { 2083, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2083 = SUB8i8
- { 2084, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2084 = SUB8mi
- { 2085, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #2085 = SUB8mr
- { 2086, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2086 = SUB8ri
- { 2087, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2087 = SUB8rm
- { 2088, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2088 = SUB8rr
- { 2089, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2089 = SUBPDrm
- { 2090, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2090 = SUBPDrr
- { 2091, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2091 = SUBPSrm
- { 2092, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2092 = SUBPSrr
- { 2093, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2093 = SUBR_F32m
- { 2094, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2094 = SUBR_F64m
- { 2095, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2095 = SUBR_FI16m
- { 2096, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2096 = SUBR_FI32m
- { 2097, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2097 = SUBR_FPrST0
- { 2098, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2098 = SUBR_FST0r
- { 2099, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2099 = SUBR_Fp32m
- { 2100, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2100 = SUBR_Fp64m
- { 2101, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2101 = SUBR_Fp64m32
- { 2102, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2102 = SUBR_Fp80m32
- { 2103, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2103 = SUBR_Fp80m64
- { 2104, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2104 = SUBR_FpI16m32
- { 2105, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2105 = SUBR_FpI16m64
- { 2106, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2106 = SUBR_FpI16m80
- { 2107, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2107 = SUBR_FpI32m32
- { 2108, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2108 = SUBR_FpI32m64
- { 2109, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2109 = SUBR_FpI32m80
- { 2110, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2110 = SUBR_FrST0
- { 2111, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2111 = SUBSDrm
- { 2112, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2112 = SUBSDrm_Int
- { 2113, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2113 = SUBSDrr
- { 2114, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2114 = SUBSDrr_Int
- { 2115, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2115 = SUBSSrm
- { 2116, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2116 = SUBSSrm_Int
- { 2117, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2117 = SUBSSrr
- { 2118, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2118 = SUBSSrr_Int
- { 2119, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2119 = SUB_F32m
- { 2120, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2120 = SUB_F64m
- { 2121, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2121 = SUB_FI16m
- { 2122, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2122 = SUB_FI32m
- { 2123, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2123 = SUB_FPrST0
- { 2124, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2124 = SUB_FST0r
- { 2125, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo31 }, // Inst #2125 = SUB_Fp32
- { 2126, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2126 = SUB_Fp32m
- { 2127, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2127 = SUB_Fp64
- { 2128, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2128 = SUB_Fp64m
- { 2129, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2129 = SUB_Fp64m32
- { 2130, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2130 = SUB_Fp80
- { 2131, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2131 = SUB_Fp80m32
- { 2132, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2132 = SUB_Fp80m64
- { 2133, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2133 = SUB_FpI16m32
- { 2134, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2134 = SUB_FpI16m64
- { 2135, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2135 = SUB_FpI16m80
- { 2136, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2136 = SUB_FpI32m32
- { 2137, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2137 = SUB_FpI32m64
- { 2138, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2138 = SUB_FpI32m80
- { 2139, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2139 = SUB_FrST0
- { 2140, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2140 = SYSCALL
- { 2141, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2141 = SYSENTER
- { 2142, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2142 = SYSEXIT
- { 2143, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2143 = SYSEXIT64
- { 2144, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2144 = SYSRET
- { 2145, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2145 = TAILJMPd
- { 2146, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2146 = TAILJMPm
- { 2147, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #2147 = TAILJMPr
- { 2148, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2148 = TAILJMPr64
- { 2149, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo37 }, // Inst #2149 = TCRETURNdi
- { 2150, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo37 }, // Inst #2150 = TCRETURNdi64
- { 2151, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo54 }, // Inst #2151 = TCRETURNri
- { 2152, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2152 = TCRETURNri64
- { 2153, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2153 = TEST16i16
- { 2154, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2154 = TEST16mi
- { 2155, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2155 = TEST16ri
- { 2156, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo45 }, // Inst #2156 = TEST16rm
- { 2157, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2157 = TEST16rr
- { 2158, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2158 = TEST32i32
- { 2159, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2159 = TEST32mi
- { 2160, 2, 0, 0, "TEST32ri", 0, 0|16|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2160 = TEST32ri
- { 2161, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2161 = TEST32rm
- { 2162, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2162 = TEST32rr
- { 2163, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2163 = TEST64i32
- { 2164, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2164 = TEST64mi32
- { 2165, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2165 = TEST64ri32
- { 2166, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2166 = TEST64rm
- { 2167, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2167 = TEST64rr
- { 2168, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2168 = TEST8i8
- { 2169, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2169 = TEST8mi
- { 2170, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2170 = TEST8ri
- { 2171, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2171 = TEST8rm
- { 2172, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #2172 = TEST8rr
- { 2173, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo194 }, // Inst #2173 = TLS_addr32
- { 2174, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo195 }, // Inst #2174 = TLS_addr64
- { 2175, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2175 = TRAP
- { 2176, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2176 = TST_F
- { 2177, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2177 = TST_Fp32
- { 2178, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2178 = TST_Fp64
- { 2179, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2179 = TST_Fp80
- { 2180, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2180 = UCOMISDrm
- { 2181, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo104 }, // Inst #2181 = UCOMISDrr
- { 2182, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #2182 = UCOMISSrm
- { 2183, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2183 = UCOMISSrr
- { 2184, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2184 = UCOM_FIPr
- { 2185, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2185 = UCOM_FIr
- { 2186, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList23, ImplicitList1, Barriers1, 0 }, // Inst #2186 = UCOM_FPPr
- { 2187, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2187 = UCOM_FPr
- { 2188, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2188 = UCOM_FpIr32
- { 2189, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2189 = UCOM_FpIr64
- { 2190, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2190 = UCOM_FpIr80
- { 2191, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2191 = UCOM_Fpr32
- { 2192, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2192 = UCOM_Fpr64
- { 2193, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2193 = UCOM_Fpr80
- { 2194, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2194 = UCOM_Fr
- { 2195, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2195 = UNPCKHPDrm
- { 2196, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2196 = UNPCKHPDrr
- { 2197, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2197 = UNPCKHPSrm
- { 2198, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2198 = UNPCKHPSrr
- { 2199, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2199 = UNPCKLPDrm
- { 2200, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2200 = UNPCKLPDrr
- { 2201, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2201 = UNPCKLPSrm
- { 2202, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2202 = UNPCKLPSrr
- { 2203, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo196 }, // Inst #2203 = VASTART_SAVE_XMM_REGS
- { 2204, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo197 }, // Inst #2204 = V_SET0
- { 2205, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo197 }, // Inst #2205 = V_SETALLONES
- { 2206, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2206 = WAIT
- { 2207, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo29 }, // Inst #2207 = WINCALL64m
- { 2208, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo5 }, // Inst #2208 = WINCALL64pcrel32
- { 2209, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo57 }, // Inst #2209 = WINCALL64r
- { 2210, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo39 }, // Inst #2210 = XCHG16rm
- { 2211, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo40 }, // Inst #2211 = XCHG32rm
- { 2212, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo41 }, // Inst #2212 = XCHG64rm
- { 2213, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo42 }, // Inst #2213 = XCHG8rm
- { 2214, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2214 = XCH_F
- { 2215, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2215 = XOR16i16
- { 2216, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2216 = XOR16mi
- { 2217, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2217 = XOR16mi8
- { 2218, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2218 = XOR16mr
- { 2219, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2219 = XOR16ri
- { 2220, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2220 = XOR16ri8
- { 2221, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2221 = XOR16rm
- { 2222, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2222 = XOR16rr
- { 2223, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2223 = XOR32i32
- { 2224, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2224 = XOR32mi
- { 2225, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2225 = XOR32mi8
- { 2226, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2226 = XOR32mr
- { 2227, 3, 1, 0, "XOR32ri", 0, 0|22|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2227 = XOR32ri
- { 2228, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2228 = XOR32ri8
- { 2229, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2229 = XOR32rm
- { 2230, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2230 = XOR32rr
- { 2231, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2231 = XOR64i32
- { 2232, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2232 = XOR64mi32
- { 2233, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2233 = XOR64mi8
- { 2234, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2234 = XOR64mr
- { 2235, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2235 = XOR64ri32
- { 2236, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2236 = XOR64ri8
- { 2237, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2237 = XOR64rm
- { 2238, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2238 = XOR64rr
- { 2239, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2239 = XOR8i8
- { 2240, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2240 = XOR8mi
- { 2241, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #2241 = XOR8mr
- { 2242, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2242 = XOR8ri
- { 2243, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2243 = XOR8rm
- { 2244, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2244 = XOR8rr
- { 2245, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2245 = XORPDrm
- { 2246, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2246 = XORPDrr
- { 2247, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2247 = XORPSrm
- { 2248, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2248 = XORPSrr
+ { 23, 3, 1, 0, "ADC16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #23 = ADC16rr_REV
+ { 24, 1, 0, 0, "ADC32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #24 = ADC32i32
+ { 25, 6, 0, 0, "ADC32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #25 = ADC32mi
+ { 26, 6, 0, 0, "ADC32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #26 = ADC32mi8
+ { 27, 6, 0, 0, "ADC32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #27 = ADC32mr
+ { 28, 3, 1, 0, "ADC32ri", 0, 0|18|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #28 = ADC32ri
+ { 29, 3, 1, 0, "ADC32ri8", 0, 0|18|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #29 = ADC32ri8
+ { 30, 7, 1, 0, "ADC32rm", 0|(1<<TID::MayLoad), 0|6|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #30 = ADC32rm
+ { 31, 3, 1, 0, "ADC32rr", 0|(1<<TID::Commutable), 0|3|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #31 = ADC32rr
+ { 32, 3, 1, 0, "ADC32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #32 = ADC32rr_REV
+ { 33, 1, 0, 0, "ADC64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #33 = ADC64i32
+ { 34, 6, 0, 0, "ADC64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #34 = ADC64mi32
+ { 35, 6, 0, 0, "ADC64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #35 = ADC64mi8
+ { 36, 6, 0, 0, "ADC64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #36 = ADC64mr
+ { 37, 3, 1, 0, "ADC64ri32", 0, 0|18|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #37 = ADC64ri32
+ { 38, 3, 1, 0, "ADC64ri8", 0, 0|18|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #38 = ADC64ri8
+ { 39, 7, 1, 0, "ADC64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #39 = ADC64rm
+ { 40, 3, 1, 0, "ADC64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #40 = ADC64rr
+ { 41, 3, 1, 0, "ADC64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #41 = ADC64rr_REV
+ { 42, 1, 0, 0, "ADC8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(20<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #42 = ADC8i8
+ { 43, 6, 0, 0, "ADC8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #43 = ADC8mi
+ { 44, 6, 0, 0, "ADC8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #44 = ADC8mr
+ { 45, 3, 1, 0, "ADC8ri", 0, 0|18|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #45 = ADC8ri
+ { 46, 7, 1, 0, "ADC8rm", 0|(1<<TID::MayLoad), 0|6|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #46 = ADC8rm
+ { 47, 3, 1, 0, "ADC8rr", 0|(1<<TID::Commutable), 0|3|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #47 = ADC8rr
+ { 48, 3, 1, 0, "ADC8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #48 = ADC8rr_REV
+ { 49, 1, 0, 0, "ADD16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #49 = ADD16i16
+ { 50, 6, 0, 0, "ADD16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #50 = ADD16mi
+ { 51, 6, 0, 0, "ADD16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #51 = ADD16mi8
+ { 52, 6, 0, 0, "ADD16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #52 = ADD16mr
+ { 53, 3, 1, 0, "ADD16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #53 = ADD16mrmrr
+ { 54, 3, 1, 0, "ADD16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #54 = ADD16ri
+ { 55, 3, 1, 0, "ADD16ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #55 = ADD16ri8
+ { 56, 7, 1, 0, "ADD16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #56 = ADD16rm
+ { 57, 3, 1, 0, "ADD16rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #57 = ADD16rr
+ { 58, 1, 0, 0, "ADD32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #58 = ADD32i32
+ { 59, 6, 0, 0, "ADD32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #59 = ADD32mi
+ { 60, 6, 0, 0, "ADD32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #60 = ADD32mi8
+ { 61, 6, 0, 0, "ADD32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #61 = ADD32mr
+ { 62, 3, 1, 0, "ADD32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #62 = ADD32mrmrr
+ { 63, 3, 1, 0, "ADD32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #63 = ADD32ri
+ { 64, 3, 1, 0, "ADD32ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #64 = ADD32ri8
+ { 65, 7, 1, 0, "ADD32rm", 0|(1<<TID::MayLoad), 0|6|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #65 = ADD32rm
+ { 66, 3, 1, 0, "ADD32rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #66 = ADD32rr
+ { 67, 1, 0, 0, "ADD64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #67 = ADD64i32
+ { 68, 6, 0, 0, "ADD64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #68 = ADD64mi32
+ { 69, 6, 0, 0, "ADD64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #69 = ADD64mi8
+ { 70, 6, 0, 0, "ADD64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #70 = ADD64mr
+ { 71, 3, 1, 0, "ADD64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #71 = ADD64mrmrr
+ { 72, 3, 1, 0, "ADD64ri32", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #72 = ADD64ri32
+ { 73, 3, 1, 0, "ADD64ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #73 = ADD64ri8
+ { 74, 7, 1, 0, "ADD64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #74 = ADD64rm
+ { 75, 3, 1, 0, "ADD64rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #75 = ADD64rr
+ { 76, 1, 0, 0, "ADD8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(4<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #76 = ADD8i8
+ { 77, 6, 0, 0, "ADD8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #77 = ADD8mi
+ { 78, 6, 0, 0, "ADD8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4, NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #78 = ADD8mr
+ { 79, 3, 1, 0, "ADD8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #79 = ADD8mrmrr
+ { 80, 3, 1, 0, "ADD8ri", 0, 0|16|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #80 = ADD8ri
+ { 81, 7, 1, 0, "ADD8rm", 0|(1<<TID::MayLoad), 0|6|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #81 = ADD8rm
+ { 82, 3, 1, 0, "ADD8rr", 0|(1<<TID::Commutable), 0|3, NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #82 = ADD8rr
+ { 83, 7, 1, 0, "ADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #83 = ADDPDrm
+ { 84, 3, 1, 0, "ADDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #84 = ADDPDrr
+ { 85, 7, 1, 0, "ADDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #85 = ADDPSrm
+ { 86, 3, 1, 0, "ADDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #86 = ADDPSrr
+ { 87, 7, 1, 0, "ADDSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #87 = ADDSDrm
+ { 88, 7, 1, 0, "ADDSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #88 = ADDSDrm_Int
+ { 89, 3, 1, 0, "ADDSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #89 = ADDSDrr
+ { 90, 3, 1, 0, "ADDSDrr_Int", 0, 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #90 = ADDSDrr_Int
+ { 91, 7, 1, 0, "ADDSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #91 = ADDSSrm
+ { 92, 7, 1, 0, "ADDSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #92 = ADDSSrm_Int
+ { 93, 3, 1, 0, "ADDSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #93 = ADDSSrr
+ { 94, 3, 1, 0, "ADDSSrr_Int", 0, 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #94 = ADDSSrr_Int
+ { 95, 7, 1, 0, "ADDSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #95 = ADDSUBPDrm
+ { 96, 3, 1, 0, "ADDSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #96 = ADDSUBPDrr
+ { 97, 7, 1, 0, "ADDSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #97 = ADDSUBPSrm
+ { 98, 3, 1, 0, "ADDSUBPSrr", 0, 0|5|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #98 = ADDSUBPSrr
+ { 99, 5, 0, 0, "ADD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #99 = ADD_F32m
+ { 100, 5, 0, 0, "ADD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #100 = ADD_F64m
+ { 101, 5, 0, 0, "ADD_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #101 = ADD_FI16m
+ { 102, 5, 0, 0, "ADD_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #102 = ADD_FI32m
+ { 103, 1, 0, 0, "ADD_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #103 = ADD_FPrST0
+ { 104, 1, 0, 0, "ADD_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #104 = ADD_FST0r
+ { 105, 3, 1, 0, "ADD_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #105 = ADD_Fp32
+ { 106, 7, 1, 0, "ADD_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #106 = ADD_Fp32m
+ { 107, 3, 1, 0, "ADD_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #107 = ADD_Fp64
+ { 108, 7, 1, 0, "ADD_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #108 = ADD_Fp64m
+ { 109, 7, 1, 0, "ADD_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #109 = ADD_Fp64m32
+ { 110, 3, 1, 0, "ADD_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #110 = ADD_Fp80
+ { 111, 7, 1, 0, "ADD_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #111 = ADD_Fp80m32
+ { 112, 7, 1, 0, "ADD_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #112 = ADD_Fp80m64
+ { 113, 7, 1, 0, "ADD_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #113 = ADD_FpI16m32
+ { 114, 7, 1, 0, "ADD_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #114 = ADD_FpI16m64
+ { 115, 7, 1, 0, "ADD_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #115 = ADD_FpI16m80
+ { 116, 7, 1, 0, "ADD_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #116 = ADD_FpI32m32
+ { 117, 7, 1, 0, "ADD_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #117 = ADD_FpI32m64
+ { 118, 7, 1, 0, "ADD_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #118 = ADD_FpI32m80
+ { 119, 1, 0, 0, "ADD_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #119 = ADD_FrST0
+ { 120, 1, 0, 0, "ADJCALLSTACKDOWN32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo5 }, // Inst #120 = ADJCALLSTACKDOWN32
+ { 121, 1, 0, 0, "ADJCALLSTACKDOWN64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo5 }, // Inst #121 = ADJCALLSTACKDOWN64
+ { 122, 2, 0, 0, "ADJCALLSTACKUP32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo38 }, // Inst #122 = ADJCALLSTACKUP32
+ { 123, 2, 0, 0, "ADJCALLSTACKUP64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo38 }, // Inst #123 = ADJCALLSTACKUP64
+ { 124, 1, 0, 0, "AND16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #124 = AND16i16
+ { 125, 6, 0, 0, "AND16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #125 = AND16mi
+ { 126, 6, 0, 0, "AND16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #126 = AND16mi8
+ { 127, 6, 0, 0, "AND16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #127 = AND16mr
+ { 128, 3, 1, 0, "AND16ri", 0, 0|20|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #128 = AND16ri
+ { 129, 3, 1, 0, "AND16ri8", 0, 0|20|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #129 = AND16ri8
+ { 130, 7, 1, 0, "AND16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #130 = AND16rm
+ { 131, 3, 1, 0, "AND16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #131 = AND16rr
+ { 132, 3, 1, 0, "AND16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #132 = AND16rr_REV
+ { 133, 1, 0, 0, "AND32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #133 = AND32i32
+ { 134, 6, 0, 0, "AND32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #134 = AND32mi
+ { 135, 6, 0, 0, "AND32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #135 = AND32mi8
+ { 136, 6, 0, 0, "AND32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #136 = AND32mr
+ { 137, 3, 1, 0, "AND32ri", 0, 0|20|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #137 = AND32ri
+ { 138, 3, 1, 0, "AND32ri8", 0, 0|20|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #138 = AND32ri8
+ { 139, 7, 1, 0, "AND32rm", 0|(1<<TID::MayLoad), 0|6|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #139 = AND32rm
+ { 140, 3, 1, 0, "AND32rr", 0|(1<<TID::Commutable), 0|3|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #140 = AND32rr
+ { 141, 3, 1, 0, "AND32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #141 = AND32rr_REV
+ { 142, 1, 0, 0, "AND64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #142 = AND64i32
+ { 143, 6, 0, 0, "AND64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #143 = AND64mi32
+ { 144, 6, 0, 0, "AND64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #144 = AND64mi8
+ { 145, 6, 0, 0, "AND64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #145 = AND64mr
+ { 146, 3, 1, 0, "AND64ri32", 0, 0|20|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #146 = AND64ri32
+ { 147, 3, 1, 0, "AND64ri8", 0, 0|20|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #147 = AND64ri8
+ { 148, 7, 1, 0, "AND64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #148 = AND64rm
+ { 149, 3, 1, 0, "AND64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #149 = AND64rr
+ { 150, 3, 1, 0, "AND64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #150 = AND64rr_REV
+ { 151, 1, 0, 0, "AND8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(36<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #151 = AND8i8
+ { 152, 6, 0, 0, "AND8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #152 = AND8mi
+ { 153, 6, 0, 0, "AND8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #153 = AND8mr
+ { 154, 3, 1, 0, "AND8ri", 0, 0|20|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #154 = AND8ri
+ { 155, 7, 1, 0, "AND8rm", 0|(1<<TID::MayLoad), 0|6|(34<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #155 = AND8rm
+ { 156, 3, 1, 0, "AND8rr", 0|(1<<TID::Commutable), 0|3|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #156 = AND8rr
+ { 157, 3, 1, 0, "AND8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(34<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #157 = AND8rr_REV
+ { 158, 7, 1, 0, "ANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #158 = ANDNPDrm
+ { 159, 3, 1, 0, "ANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #159 = ANDNPDrr
+ { 160, 7, 1, 0, "ANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #160 = ANDNPSrm
+ { 161, 3, 1, 0, "ANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #161 = ANDNPSrr
+ { 162, 7, 1, 0, "ANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #162 = ANDPDrm
+ { 163, 3, 1, 0, "ANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #163 = ANDPDrr
+ { 164, 7, 1, 0, "ANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #164 = ANDPSrm
+ { 165, 3, 1, 0, "ANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #165 = ANDPSrr
+ { 166, 9, 2, 0, "ATOMADD6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #166 = ATOMADD6432
+ { 167, 7, 1, 0, "ATOMAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #167 = ATOMAND16
+ { 168, 7, 1, 0, "ATOMAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #168 = ATOMAND32
+ { 169, 7, 1, 0, "ATOMAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #169 = ATOMAND64
+ { 170, 9, 2, 0, "ATOMAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #170 = ATOMAND6432
+ { 171, 7, 1, 0, "ATOMAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #171 = ATOMAND8
+ { 172, 7, 1, 0, "ATOMMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #172 = ATOMMAX16
+ { 173, 7, 1, 0, "ATOMMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #173 = ATOMMAX32
+ { 174, 7, 1, 0, "ATOMMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #174 = ATOMMAX64
+ { 175, 7, 1, 0, "ATOMMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #175 = ATOMMIN16
+ { 176, 7, 1, 0, "ATOMMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #176 = ATOMMIN32
+ { 177, 7, 1, 0, "ATOMMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #177 = ATOMMIN64
+ { 178, 7, 1, 0, "ATOMNAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #178 = ATOMNAND16
+ { 179, 7, 1, 0, "ATOMNAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #179 = ATOMNAND32
+ { 180, 7, 1, 0, "ATOMNAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #180 = ATOMNAND64
+ { 181, 9, 2, 0, "ATOMNAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #181 = ATOMNAND6432
+ { 182, 7, 1, 0, "ATOMNAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #182 = ATOMNAND8
+ { 183, 7, 1, 0, "ATOMOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #183 = ATOMOR16
+ { 184, 7, 1, 0, "ATOMOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #184 = ATOMOR32
+ { 185, 7, 1, 0, "ATOMOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #185 = ATOMOR64
+ { 186, 9, 2, 0, "ATOMOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #186 = ATOMOR6432
+ { 187, 7, 1, 0, "ATOMOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #187 = ATOMOR8
+ { 188, 9, 2, 0, "ATOMSUB6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #188 = ATOMSUB6432
+ { 189, 9, 2, 0, "ATOMSWAP6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #189 = ATOMSWAP6432
+ { 190, 7, 1, 0, "ATOMUMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #190 = ATOMUMAX16
+ { 191, 7, 1, 0, "ATOMUMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #191 = ATOMUMAX32
+ { 192, 7, 1, 0, "ATOMUMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #192 = ATOMUMAX64
+ { 193, 7, 1, 0, "ATOMUMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #193 = ATOMUMIN16
+ { 194, 7, 1, 0, "ATOMUMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #194 = ATOMUMIN32
+ { 195, 7, 1, 0, "ATOMUMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #195 = ATOMUMIN64
+ { 196, 7, 1, 0, "ATOMXOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #196 = ATOMXOR16
+ { 197, 7, 1, 0, "ATOMXOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #197 = ATOMXOR32
+ { 198, 7, 1, 0, "ATOMXOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #198 = ATOMXOR64
+ { 199, 9, 2, 0, "ATOMXOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #199 = ATOMXOR6432
+ { 200, 7, 1, 0, "ATOMXOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #200 = ATOMXOR8
+ { 201, 8, 1, 0, "BLENDPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #201 = BLENDPDrmi
+ { 202, 4, 1, 0, "BLENDPDrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #202 = BLENDPDrri
+ { 203, 8, 1, 0, "BLENDPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #203 = BLENDPSrmi
+ { 204, 4, 1, 0, "BLENDPSrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #204 = BLENDPSrri
+ { 205, 7, 1, 0, "BLENDVPDrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #205 = BLENDVPDrm0
+ { 206, 3, 1, 0, "BLENDVPDrr0", 0, 0|5|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #206 = BLENDVPDrr0
+ { 207, 7, 1, 0, "BLENDVPSrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #207 = BLENDVPSrm0
+ { 208, 3, 1, 0, "BLENDVPSrr0", 0, 0|5|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #208 = BLENDVPSrr0
+ { 209, 6, 1, 0, "BSF16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #209 = BSF16rm
+ { 210, 2, 1, 0, "BSF16rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #210 = BSF16rr
+ { 211, 6, 1, 0, "BSF32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #211 = BSF32rm
+ { 212, 2, 1, 0, "BSF32rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #212 = BSF32rr
+ { 213, 6, 1, 0, "BSF64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #213 = BSF64rm
+ { 214, 2, 1, 0, "BSF64rr", 0, 0|5|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #214 = BSF64rr
+ { 215, 6, 1, 0, "BSR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #215 = BSR16rm
+ { 216, 2, 1, 0, "BSR16rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #216 = BSR16rr
+ { 217, 6, 1, 0, "BSR32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #217 = BSR32rm
+ { 218, 2, 1, 0, "BSR32rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #218 = BSR32rr
+ { 219, 6, 1, 0, "BSR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #219 = BSR64rm
+ { 220, 2, 1, 0, "BSR64rr", 0, 0|5|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #220 = BSR64rr
+ { 221, 2, 1, 0, "BSWAP32r", 0, 0|2|(1<<8)|(200<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #221 = BSWAP32r
+ { 222, 2, 1, 0, "BSWAP64r", 0, 0|2|(1<<8)|(1<<12)|(200<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #222 = BSWAP64r
+ { 223, 6, 0, 0, "BT16mi8", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #223 = BT16mi8
+ { 224, 6, 0, 0, "BT16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #224 = BT16mr
+ { 225, 2, 0, 0, "BT16ri8", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #225 = BT16ri8
+ { 226, 2, 0, 0, "BT16rr", 0, 0|3|(1<<6)|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #226 = BT16rr
+ { 227, 6, 0, 0, "BT32mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #227 = BT32mi8
+ { 228, 6, 0, 0, "BT32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #228 = BT32mr
+ { 229, 2, 0, 0, "BT32ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #229 = BT32ri8
+ { 230, 2, 0, 0, "BT32rr", 0, 0|3|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #230 = BT32rr
+ { 231, 6, 0, 0, "BT64mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #231 = BT64mi8
+ { 232, 6, 0, 0, "BT64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #232 = BT64mr
+ { 233, 2, 0, 0, "BT64ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #233 = BT64ri8
+ { 234, 2, 0, 0, "BT64rr", 0, 0|3|(1<<8)|(1<<12)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #234 = BT64rr
+ { 235, 6, 0, 0, "BTC16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #235 = BTC16mi8
+ { 236, 6, 0, 0, "BTC16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #236 = BTC16mr
+ { 237, 2, 0, 0, "BTC16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #237 = BTC16ri8
+ { 238, 2, 0, 0, "BTC16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #238 = BTC16rr
+ { 239, 6, 0, 0, "BTC32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #239 = BTC32mi8
+ { 240, 6, 0, 0, "BTC32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #240 = BTC32mr
+ { 241, 2, 0, 0, "BTC32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #241 = BTC32ri8
+ { 242, 2, 0, 0, "BTC32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #242 = BTC32rr
+ { 243, 6, 0, 0, "BTC64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #243 = BTC64mi8
+ { 244, 6, 0, 0, "BTC64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #244 = BTC64mr
+ { 245, 2, 0, 0, "BTC64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #245 = BTC64ri8
+ { 246, 2, 0, 0, "BTC64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #246 = BTC64rr
+ { 247, 6, 0, 0, "BTR16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #247 = BTR16mi8
+ { 248, 6, 0, 0, "BTR16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #248 = BTR16mr
+ { 249, 2, 0, 0, "BTR16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #249 = BTR16ri8
+ { 250, 2, 0, 0, "BTR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #250 = BTR16rr
+ { 251, 6, 0, 0, "BTR32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #251 = BTR32mi8
+ { 252, 6, 0, 0, "BTR32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #252 = BTR32mr
+ { 253, 2, 0, 0, "BTR32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #253 = BTR32ri8
+ { 254, 2, 0, 0, "BTR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #254 = BTR32rr
+ { 255, 6, 0, 0, "BTR64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #255 = BTR64mi8
+ { 256, 6, 0, 0, "BTR64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #256 = BTR64mr
+ { 257, 2, 0, 0, "BTR64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #257 = BTR64ri8
+ { 258, 2, 0, 0, "BTR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #258 = BTR64rr
+ { 259, 6, 0, 0, "BTS16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #259 = BTS16mi8
+ { 260, 6, 0, 0, "BTS16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #260 = BTS16mr
+ { 261, 2, 0, 0, "BTS16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #261 = BTS16ri8
+ { 262, 2, 0, 0, "BTS16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #262 = BTS16rr
+ { 263, 6, 0, 0, "BTS32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #263 = BTS32mi8
+ { 264, 6, 0, 0, "BTS32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #264 = BTS32mr
+ { 265, 2, 0, 0, "BTS32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #265 = BTS32ri8
+ { 266, 2, 0, 0, "BTS32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #266 = BTS32rr
+ { 267, 6, 0, 0, "BTS64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #267 = BTS64mi8
+ { 268, 6, 0, 0, "BTS64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #268 = BTS64mr
+ { 269, 2, 0, 0, "BTS64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #269 = BTS64ri8
+ { 270, 2, 0, 0, "BTS64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #270 = BTS64rr
+ { 271, 5, 0, 0, "CALL32m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #271 = CALL32m
+ { 272, 1, 0, 0, "CALL32r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo57 }, // Inst #272 = CALL32r
+ { 273, 5, 0, 0, "CALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo30 }, // Inst #273 = CALL64m
+ { 274, 1, 0, 0, "CALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo5 }, // Inst #274 = CALL64pcrel32
+ { 275, 1, 0, 0, "CALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo58 }, // Inst #275 = CALL64r
+ { 276, 1, 0, 0, "CALLpcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo5 }, // Inst #276 = CALLpcrel32
+ { 277, 0, 0, 0, "CBW", 0, 0|1|(1<<6)|(152<<24), ImplicitList11, ImplicitList12, NULL, 0 }, // Inst #277 = CBW
+ { 278, 0, 0, 0, "CDQ", 0, 0|1|(153<<24), ImplicitList13, ImplicitList14, Barriers5, 0 }, // Inst #278 = CDQ
+ { 279, 0, 0, 0, "CDQE", 0, 0|1|(1<<12)|(152<<24), ImplicitList13, ImplicitList15, NULL, 0 }, // Inst #279 = CDQE
+ { 280, 0, 0, 0, "CHS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(224<<24), NULL, NULL, NULL, 0 }, // Inst #280 = CHS_F
+ { 281, 2, 1, 0, "CHS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #281 = CHS_Fp32
+ { 282, 2, 1, 0, "CHS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #282 = CHS_Fp64
+ { 283, 2, 1, 0, "CHS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #283 = CHS_Fp80
+ { 284, 0, 0, 0, "CLC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(248<<24), NULL, NULL, NULL, 0 }, // Inst #284 = CLC
+ { 285, 0, 0, 0, "CLD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(252<<24), NULL, NULL, NULL, 0 }, // Inst #285 = CLD
+ { 286, 5, 0, 0, "CLFLUSH", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #286 = CLFLUSH
+ { 287, 0, 0, 0, "CLI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(250<<24), NULL, NULL, NULL, 0 }, // Inst #287 = CLI
+ { 288, 0, 0, 0, "CLTS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(6<<24), NULL, NULL, NULL, 0 }, // Inst #288 = CLTS
+ { 289, 0, 0, 0, "CMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(245<<24), NULL, NULL, NULL, 0 }, // Inst #289 = CMC
+ { 290, 7, 1, 0, "CMOVA16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #290 = CMOVA16rm
+ { 291, 3, 1, 0, "CMOVA16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #291 = CMOVA16rr
+ { 292, 7, 1, 0, "CMOVA32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #292 = CMOVA32rm
+ { 293, 3, 1, 0, "CMOVA32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #293 = CMOVA32rr
+ { 294, 7, 1, 0, "CMOVA64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #294 = CMOVA64rm
+ { 295, 3, 1, 0, "CMOVA64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #295 = CMOVA64rr
+ { 296, 7, 1, 0, "CMOVAE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #296 = CMOVAE16rm
+ { 297, 3, 1, 0, "CMOVAE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #297 = CMOVAE16rr
+ { 298, 7, 1, 0, "CMOVAE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #298 = CMOVAE32rm
+ { 299, 3, 1, 0, "CMOVAE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #299 = CMOVAE32rr
+ { 300, 7, 1, 0, "CMOVAE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #300 = CMOVAE64rm
+ { 301, 3, 1, 0, "CMOVAE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #301 = CMOVAE64rr
+ { 302, 7, 1, 0, "CMOVB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #302 = CMOVB16rm
+ { 303, 3, 1, 0, "CMOVB16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #303 = CMOVB16rr
+ { 304, 7, 1, 0, "CMOVB32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #304 = CMOVB32rm
+ { 305, 3, 1, 0, "CMOVB32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #305 = CMOVB32rr
+ { 306, 7, 1, 0, "CMOVB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #306 = CMOVB64rm
+ { 307, 3, 1, 0, "CMOVB64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #307 = CMOVB64rr
+ { 308, 7, 1, 0, "CMOVBE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #308 = CMOVBE16rm
+ { 309, 3, 1, 0, "CMOVBE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #309 = CMOVBE16rr
+ { 310, 7, 1, 0, "CMOVBE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #310 = CMOVBE32rm
+ { 311, 3, 1, 0, "CMOVBE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #311 = CMOVBE32rr
+ { 312, 7, 1, 0, "CMOVBE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #312 = CMOVBE64rm
+ { 313, 3, 1, 0, "CMOVBE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #313 = CMOVBE64rr
+ { 314, 1, 1, 0, "CMOVBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #314 = CMOVBE_F
+ { 315, 3, 1, 0, "CMOVBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #315 = CMOVBE_Fp32
+ { 316, 3, 1, 0, "CMOVBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #316 = CMOVBE_Fp64
+ { 317, 3, 1, 0, "CMOVBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #317 = CMOVBE_Fp80
+ { 318, 1, 1, 0, "CMOVB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #318 = CMOVB_F
+ { 319, 3, 1, 0, "CMOVB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #319 = CMOVB_Fp32
+ { 320, 3, 1, 0, "CMOVB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #320 = CMOVB_Fp64
+ { 321, 3, 1, 0, "CMOVB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #321 = CMOVB_Fp80
+ { 322, 7, 1, 0, "CMOVE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #322 = CMOVE16rm
+ { 323, 3, 1, 0, "CMOVE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #323 = CMOVE16rr
+ { 324, 7, 1, 0, "CMOVE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #324 = CMOVE32rm
+ { 325, 3, 1, 0, "CMOVE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #325 = CMOVE32rr
+ { 326, 7, 1, 0, "CMOVE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #326 = CMOVE64rm
+ { 327, 3, 1, 0, "CMOVE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #327 = CMOVE64rr
+ { 328, 1, 1, 0, "CMOVE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #328 = CMOVE_F
+ { 329, 3, 1, 0, "CMOVE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #329 = CMOVE_Fp32
+ { 330, 3, 1, 0, "CMOVE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #330 = CMOVE_Fp64
+ { 331, 3, 1, 0, "CMOVE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #331 = CMOVE_Fp80
+ { 332, 7, 1, 0, "CMOVG16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #332 = CMOVG16rm
+ { 333, 3, 1, 0, "CMOVG16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #333 = CMOVG16rr
+ { 334, 7, 1, 0, "CMOVG32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #334 = CMOVG32rm
+ { 335, 3, 1, 0, "CMOVG32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #335 = CMOVG32rr
+ { 336, 7, 1, 0, "CMOVG64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #336 = CMOVG64rm
+ { 337, 3, 1, 0, "CMOVG64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #337 = CMOVG64rr
+ { 338, 7, 1, 0, "CMOVGE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #338 = CMOVGE16rm
+ { 339, 3, 1, 0, "CMOVGE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #339 = CMOVGE16rr
+ { 340, 7, 1, 0, "CMOVGE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #340 = CMOVGE32rm
+ { 341, 3, 1, 0, "CMOVGE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #341 = CMOVGE32rr
+ { 342, 7, 1, 0, "CMOVGE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #342 = CMOVGE64rm
+ { 343, 3, 1, 0, "CMOVGE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #343 = CMOVGE64rr
+ { 344, 7, 1, 0, "CMOVL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #344 = CMOVL16rm
+ { 345, 3, 1, 0, "CMOVL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #345 = CMOVL16rr
+ { 346, 7, 1, 0, "CMOVL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #346 = CMOVL32rm
+ { 347, 3, 1, 0, "CMOVL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #347 = CMOVL32rr
+ { 348, 7, 1, 0, "CMOVL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #348 = CMOVL64rm
+ { 349, 3, 1, 0, "CMOVL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #349 = CMOVL64rr
+ { 350, 7, 1, 0, "CMOVLE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #350 = CMOVLE16rm
+ { 351, 3, 1, 0, "CMOVLE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #351 = CMOVLE16rr
+ { 352, 7, 1, 0, "CMOVLE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #352 = CMOVLE32rm
+ { 353, 3, 1, 0, "CMOVLE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #353 = CMOVLE32rr
+ { 354, 7, 1, 0, "CMOVLE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #354 = CMOVLE64rm
+ { 355, 3, 1, 0, "CMOVLE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #355 = CMOVLE64rr
+ { 356, 1, 1, 0, "CMOVNBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #356 = CMOVNBE_F
+ { 357, 3, 1, 0, "CMOVNBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #357 = CMOVNBE_Fp32
+ { 358, 3, 1, 0, "CMOVNBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #358 = CMOVNBE_Fp64
+ { 359, 3, 1, 0, "CMOVNBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #359 = CMOVNBE_Fp80
+ { 360, 1, 1, 0, "CMOVNB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #360 = CMOVNB_F
+ { 361, 3, 1, 0, "CMOVNB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #361 = CMOVNB_Fp32
+ { 362, 3, 1, 0, "CMOVNB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #362 = CMOVNB_Fp64
+ { 363, 3, 1, 0, "CMOVNB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #363 = CMOVNB_Fp80
+ { 364, 7, 1, 0, "CMOVNE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #364 = CMOVNE16rm
+ { 365, 3, 1, 0, "CMOVNE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #365 = CMOVNE16rr
+ { 366, 7, 1, 0, "CMOVNE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #366 = CMOVNE32rm
+ { 367, 3, 1, 0, "CMOVNE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #367 = CMOVNE32rr
+ { 368, 7, 1, 0, "CMOVNE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #368 = CMOVNE64rm
+ { 369, 3, 1, 0, "CMOVNE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #369 = CMOVNE64rr
+ { 370, 1, 1, 0, "CMOVNE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #370 = CMOVNE_F
+ { 371, 3, 1, 0, "CMOVNE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #371 = CMOVNE_Fp32
+ { 372, 3, 1, 0, "CMOVNE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #372 = CMOVNE_Fp64
+ { 373, 3, 1, 0, "CMOVNE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #373 = CMOVNE_Fp80
+ { 374, 7, 1, 0, "CMOVNO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #374 = CMOVNO16rm
+ { 375, 3, 1, 0, "CMOVNO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #375 = CMOVNO16rr
+ { 376, 7, 1, 0, "CMOVNO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #376 = CMOVNO32rm
+ { 377, 3, 1, 0, "CMOVNO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #377 = CMOVNO32rr
+ { 378, 7, 1, 0, "CMOVNO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #378 = CMOVNO64rm
+ { 379, 3, 1, 0, "CMOVNO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #379 = CMOVNO64rr
+ { 380, 7, 1, 0, "CMOVNP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #380 = CMOVNP16rm
+ { 381, 3, 1, 0, "CMOVNP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #381 = CMOVNP16rr
+ { 382, 7, 1, 0, "CMOVNP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #382 = CMOVNP32rm
+ { 383, 3, 1, 0, "CMOVNP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #383 = CMOVNP32rr
+ { 384, 7, 1, 0, "CMOVNP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #384 = CMOVNP64rm
+ { 385, 3, 1, 0, "CMOVNP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #385 = CMOVNP64rr
+ { 386, 1, 1, 0, "CMOVNP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #386 = CMOVNP_F
+ { 387, 3, 1, 0, "CMOVNP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #387 = CMOVNP_Fp32
+ { 388, 3, 1, 0, "CMOVNP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #388 = CMOVNP_Fp64
+ { 389, 3, 1, 0, "CMOVNP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #389 = CMOVNP_Fp80
+ { 390, 7, 1, 0, "CMOVNS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #390 = CMOVNS16rm
+ { 391, 3, 1, 0, "CMOVNS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #391 = CMOVNS16rr
+ { 392, 7, 1, 0, "CMOVNS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #392 = CMOVNS32rm
+ { 393, 3, 1, 0, "CMOVNS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #393 = CMOVNS32rr
+ { 394, 7, 1, 0, "CMOVNS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #394 = CMOVNS64rm
+ { 395, 3, 1, 0, "CMOVNS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #395 = CMOVNS64rr
+ { 396, 7, 1, 0, "CMOVO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #396 = CMOVO16rm
+ { 397, 3, 1, 0, "CMOVO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #397 = CMOVO16rr
+ { 398, 7, 1, 0, "CMOVO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #398 = CMOVO32rm
+ { 399, 3, 1, 0, "CMOVO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #399 = CMOVO32rr
+ { 400, 7, 1, 0, "CMOVO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #400 = CMOVO64rm
+ { 401, 3, 1, 0, "CMOVO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #401 = CMOVO64rr
+ { 402, 7, 1, 0, "CMOVP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #402 = CMOVP16rm
+ { 403, 3, 1, 0, "CMOVP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #403 = CMOVP16rr
+ { 404, 7, 1, 0, "CMOVP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #404 = CMOVP32rm
+ { 405, 3, 1, 0, "CMOVP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #405 = CMOVP32rr
+ { 406, 7, 1, 0, "CMOVP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #406 = CMOVP64rm
+ { 407, 3, 1, 0, "CMOVP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #407 = CMOVP64rr
+ { 408, 1, 1, 0, "CMOVP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #408 = CMOVP_F
+ { 409, 3, 1, 0, "CMOVP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #409 = CMOVP_Fp32
+ { 410, 3, 1, 0, "CMOVP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #410 = CMOVP_Fp64
+ { 411, 3, 1, 0, "CMOVP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #411 = CMOVP_Fp80
+ { 412, 7, 1, 0, "CMOVS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #412 = CMOVS16rm
+ { 413, 3, 1, 0, "CMOVS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #413 = CMOVS16rr
+ { 414, 7, 1, 0, "CMOVS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #414 = CMOVS32rm
+ { 415, 3, 1, 0, "CMOVS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #415 = CMOVS32rr
+ { 416, 7, 1, 0, "CMOVS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #416 = CMOVS64rm
+ { 417, 3, 1, 0, "CMOVS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #417 = CMOVS64rr
+ { 418, 4, 1, 0, "CMOV_FR32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo62 }, // Inst #418 = CMOV_FR32
+ { 419, 4, 1, 0, "CMOV_FR64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo63 }, // Inst #419 = CMOV_FR64
+ { 420, 4, 1, 0, "CMOV_GR8", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, ImplicitList1, Barriers1, OperandInfo64 }, // Inst #420 = CMOV_GR8
+ { 421, 4, 1, 0, "CMOV_V1I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo65 }, // Inst #421 = CMOV_V1I64
+ { 422, 4, 1, 0, "CMOV_V2F64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #422 = CMOV_V2F64
+ { 423, 4, 1, 0, "CMOV_V2I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #423 = CMOV_V2I64
+ { 424, 4, 1, 0, "CMOV_V4F32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #424 = CMOV_V4F32
+ { 425, 1, 0, 0, "CMP16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #425 = CMP16i16
+ { 426, 6, 0, 0, "CMP16mi", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #426 = CMP16mi
+ { 427, 6, 0, 0, "CMP16mi8", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #427 = CMP16mi8
+ { 428, 6, 0, 0, "CMP16mr", 0|(1<<TID::MayLoad), 0|4|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #428 = CMP16mr
+ { 429, 2, 0, 0, "CMP16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #429 = CMP16mrmrr
+ { 430, 2, 0, 0, "CMP16ri", 0, 0|23|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #430 = CMP16ri
+ { 431, 2, 0, 0, "CMP16ri8", 0, 0|23|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #431 = CMP16ri8
+ { 432, 6, 0, 0, "CMP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #432 = CMP16rm
+ { 433, 2, 0, 0, "CMP16rr", 0, 0|3|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #433 = CMP16rr
+ { 434, 1, 0, 0, "CMP32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #434 = CMP32i32
+ { 435, 6, 0, 0, "CMP32mi", 0|(1<<TID::MayLoad), 0|31|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #435 = CMP32mi
+ { 436, 6, 0, 0, "CMP32mi8", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #436 = CMP32mi8
+ { 437, 6, 0, 0, "CMP32mr", 0|(1<<TID::MayLoad), 0|4|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #437 = CMP32mr
+ { 438, 2, 0, 0, "CMP32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #438 = CMP32mrmrr
+ { 439, 2, 0, 0, "CMP32ri", 0, 0|23|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #439 = CMP32ri
+ { 440, 2, 0, 0, "CMP32ri8", 0, 0|23|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #440 = CMP32ri8
+ { 441, 6, 0, 0, "CMP32rm", 0|(1<<TID::MayLoad), 0|6|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #441 = CMP32rm
+ { 442, 2, 0, 0, "CMP32rr", 0, 0|3|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #442 = CMP32rr
+ { 443, 1, 0, 0, "CMP64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #443 = CMP64i32
+ { 444, 6, 0, 0, "CMP64mi32", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #444 = CMP64mi32
+ { 445, 6, 0, 0, "CMP64mi8", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #445 = CMP64mi8
+ { 446, 6, 0, 0, "CMP64mr", 0|(1<<TID::MayLoad), 0|4|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #446 = CMP64mr
+ { 447, 2, 0, 0, "CMP64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #447 = CMP64mrmrr
+ { 448, 2, 0, 0, "CMP64ri32", 0, 0|23|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #448 = CMP64ri32
+ { 449, 2, 0, 0, "CMP64ri8", 0, 0|23|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #449 = CMP64ri8
+ { 450, 6, 0, 0, "CMP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #450 = CMP64rm
+ { 451, 2, 0, 0, "CMP64rr", 0, 0|3|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #451 = CMP64rr
+ { 452, 1, 0, 0, "CMP8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(60<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #452 = CMP8i8
+ { 453, 6, 0, 0, "CMP8mi", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #453 = CMP8mi
+ { 454, 6, 0, 0, "CMP8mr", 0|(1<<TID::MayLoad), 0|4|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #454 = CMP8mr
+ { 455, 2, 0, 0, "CMP8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #455 = CMP8mrmrr
+ { 456, 2, 0, 0, "CMP8ri", 0, 0|23|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #456 = CMP8ri
+ { 457, 6, 0, 0, "CMP8rm", 0|(1<<TID::MayLoad), 0|6|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #457 = CMP8rm
+ { 458, 2, 0, 0, "CMP8rr", 0, 0|3|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #458 = CMP8rr
+ { 459, 8, 1, 0, "CMPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #459 = CMPPDrmi
+ { 460, 4, 1, 0, "CMPPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #460 = CMPPDrri
+ { 461, 8, 1, 0, "CMPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #461 = CMPPSrmi
+ { 462, 4, 1, 0, "CMPPSrri", 0, 0|5|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #462 = CMPPSrri
+ { 463, 0, 0, 0, "CMPS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #463 = CMPS16
+ { 464, 0, 0, 0, "CMPS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(167<<24), NULL, NULL, NULL, 0 }, // Inst #464 = CMPS32
+ { 465, 0, 0, 0, "CMPS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #465 = CMPS64
+ { 466, 0, 0, 0, "CMPS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(166<<24), NULL, NULL, NULL, 0 }, // Inst #466 = CMPS8
+ { 467, 8, 1, 0, "CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo70 }, // Inst #467 = CMPSDrm
+ { 468, 4, 1, 0, "CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo71 }, // Inst #468 = CMPSDrr
+ { 469, 8, 1, 0, "CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo72 }, // Inst #469 = CMPSSrm
+ { 470, 4, 1, 0, "CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #470 = CMPSSrr
+ { 471, 5, 0, 0, "CMPXCHG16B", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<12)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #471 = CMPXCHG16B
+ { 472, 6, 0, 0, "CMPXCHG16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #472 = CMPXCHG16rm
+ { 473, 2, 1, 0, "CMPXCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #473 = CMPXCHG16rr
+ { 474, 6, 0, 0, "CMPXCHG32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #474 = CMPXCHG32rm
+ { 475, 2, 1, 0, "CMPXCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #475 = CMPXCHG32rr
+ { 476, 6, 0, 0, "CMPXCHG64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(177<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #476 = CMPXCHG64rm
+ { 477, 2, 1, 0, "CMPXCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(177<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #477 = CMPXCHG64rr
+ { 478, 5, 0, 0, "CMPXCHG8B", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #478 = CMPXCHG8B
+ { 479, 6, 0, 0, "CMPXCHG8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(176<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #479 = CMPXCHG8rm
+ { 480, 2, 1, 0, "CMPXCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(176<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #480 = CMPXCHG8rr
+ { 481, 6, 0, 0, "COMISDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #481 = COMISDrm
+ { 482, 2, 0, 0, "COMISDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #482 = COMISDrr
+ { 483, 6, 0, 0, "COMISSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #483 = COMISSrm
+ { 484, 2, 0, 0, "COMISSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #484 = COMISSrr
+ { 485, 1, 0, 0, "COMP_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #485 = COMP_FST0r
+ { 486, 1, 0, 0, "COM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #486 = COM_FIPr
+ { 487, 1, 0, 0, "COM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #487 = COM_FIr
+ { 488, 1, 0, 0, "COM_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #488 = COM_FST0r
+ { 489, 0, 0, 0, "COS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(255<<24), NULL, NULL, NULL, 0 }, // Inst #489 = COS_F
+ { 490, 2, 1, 0, "COS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #490 = COS_Fp32
+ { 491, 2, 1, 0, "COS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #491 = COS_Fp64
+ { 492, 2, 1, 0, "COS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #492 = COS_Fp80
+ { 493, 0, 0, 0, "CPUID", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(162<<24), NULL, NULL, NULL, 0 }, // Inst #493 = CPUID
+ { 494, 0, 0, 0, "CQO", 0, 0|1|(1<<12)|(153<<24), ImplicitList15, ImplicitList16, NULL, 0 }, // Inst #494 = CQO
+ { 495, 7, 1, 0, "CRC32m16", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #495 = CRC32m16
+ { 496, 7, 1, 0, "CRC32m32", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #496 = CRC32m32
+ { 497, 7, 1, 0, "CRC32m8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #497 = CRC32m8
+ { 498, 3, 1, 0, "CRC32r16", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo77 }, // Inst #498 = CRC32r16
+ { 499, 3, 1, 0, "CRC32r32", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #499 = CRC32r32
+ { 500, 3, 1, 0, "CRC32r8", 0, 0|5|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #500 = CRC32r8
+ { 501, 7, 1, 0, "CRC64m64", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #501 = CRC64m64
+ { 502, 3, 1, 0, "CRC64r64", 0, 0|5|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #502 = CRC64r64
+ { 503, 6, 1, 0, "CVTDQ2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #503 = CVTDQ2PDrm
+ { 504, 2, 1, 0, "CVTDQ2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #504 = CVTDQ2PDrr
+ { 505, 6, 1, 0, "CVTDQ2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #505 = CVTDQ2PSrm
+ { 506, 2, 1, 0, "CVTDQ2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #506 = CVTDQ2PSrr
+ { 507, 6, 1, 0, "CVTPD2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #507 = CVTPD2DQrm
+ { 508, 2, 1, 0, "CVTPD2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #508 = CVTPD2DQrr
+ { 509, 6, 1, 0, "CVTPD2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #509 = CVTPD2PSrm
+ { 510, 2, 1, 0, "CVTPD2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #510 = CVTPD2PSrr
+ { 511, 6, 1, 0, "CVTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #511 = CVTPS2DQrm
+ { 512, 2, 1, 0, "CVTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #512 = CVTPS2DQrr
+ { 513, 6, 1, 0, "CVTPS2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #513 = CVTPS2PDrm
+ { 514, 2, 1, 0, "CVTPS2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #514 = CVTPS2PDrr
+ { 515, 6, 1, 0, "CVTSD2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #515 = CVTSD2SI64rm
+ { 516, 2, 1, 0, "CVTSD2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #516 = CVTSD2SI64rr
+ { 517, 6, 1, 0, "CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #517 = CVTSD2SSrm
+ { 518, 2, 1, 0, "CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo81 }, // Inst #518 = CVTSD2SSrr
+ { 519, 6, 1, 0, "CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #519 = CVTSI2SD64rm
+ { 520, 2, 1, 0, "CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #520 = CVTSI2SD64rr
+ { 521, 6, 1, 0, "CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #521 = CVTSI2SDrm
+ { 522, 2, 1, 0, "CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo84 }, // Inst #522 = CVTSI2SDrr
+ { 523, 6, 1, 0, "CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #523 = CVTSI2SS64rm
+ { 524, 2, 1, 0, "CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo85 }, // Inst #524 = CVTSI2SS64rr
+ { 525, 6, 1, 0, "CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #525 = CVTSI2SSrm
+ { 526, 2, 1, 0, "CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #526 = CVTSI2SSrr
+ { 527, 6, 1, 0, "CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #527 = CVTSS2SDrm
+ { 528, 2, 1, 0, "CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo87 }, // Inst #528 = CVTSS2SDrr
+ { 529, 6, 1, 0, "CVTSS2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #529 = CVTSS2SI64rm
+ { 530, 2, 1, 0, "CVTSS2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #530 = CVTSS2SI64rr
+ { 531, 6, 1, 0, "CVTSS2SIrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #531 = CVTSS2SIrm
+ { 532, 2, 1, 0, "CVTSS2SIrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #532 = CVTSS2SIrr
+ { 533, 6, 1, 0, "CVTTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #533 = CVTTPS2DQrm
+ { 534, 2, 1, 0, "CVTTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #534 = CVTTPS2DQrr
+ { 535, 6, 1, 0, "CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #535 = CVTTSD2SI64rm
+ { 536, 2, 1, 0, "CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #536 = CVTTSD2SI64rr
+ { 537, 6, 1, 0, "CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #537 = CVTTSD2SIrm
+ { 538, 2, 1, 0, "CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo90 }, // Inst #538 = CVTTSD2SIrr
+ { 539, 6, 1, 0, "CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #539 = CVTTSS2SI64rm
+ { 540, 2, 1, 0, "CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #540 = CVTTSS2SI64rr
+ { 541, 6, 1, 0, "CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #541 = CVTTSS2SIrm
+ { 542, 2, 1, 0, "CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #542 = CVTTSS2SIrr
+ { 543, 0, 0, 0, "CWD", 0, 0|1|(1<<6)|(153<<24), ImplicitList12, ImplicitList17, NULL, 0 }, // Inst #543 = CWD
+ { 544, 0, 0, 0, "CWDE", 0, 0|1|(152<<24), ImplicitList12, ImplicitList13, NULL, 0 }, // Inst #544 = CWDE
+ { 545, 5, 0, 0, "DEC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #545 = DEC16m
+ { 546, 2, 1, 0, "DEC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #546 = DEC16r
+ { 547, 5, 0, 0, "DEC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #547 = DEC32m
+ { 548, 2, 1, 0, "DEC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #548 = DEC32r
+ { 549, 5, 0, 0, "DEC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #549 = DEC64_16m
+ { 550, 2, 1, 0, "DEC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #550 = DEC64_16r
+ { 551, 5, 0, 0, "DEC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #551 = DEC64_32m
+ { 552, 2, 1, 0, "DEC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #552 = DEC64_32r
+ { 553, 5, 0, 0, "DEC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #553 = DEC64m
+ { 554, 2, 1, 0, "DEC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #554 = DEC64r
+ { 555, 5, 0, 0, "DEC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #555 = DEC8m
+ { 556, 2, 1, 0, "DEC8r", 0, 0|17|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #556 = DEC8r
+ { 557, 5, 0, 0, "DIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo30 }, // Inst #557 = DIV16m
+ { 558, 1, 0, 0, "DIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo93 }, // Inst #558 = DIV16r
+ { 559, 5, 0, 0, "DIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo30 }, // Inst #559 = DIV32m
+ { 560, 1, 0, 0, "DIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo57 }, // Inst #560 = DIV32r
+ { 561, 5, 0, 0, "DIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo30 }, // Inst #561 = DIV64m
+ { 562, 1, 0, 0, "DIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo58 }, // Inst #562 = DIV64r
+ { 563, 5, 0, 0, "DIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #563 = DIV8m
+ { 564, 1, 0, 0, "DIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo94 }, // Inst #564 = DIV8r
+ { 565, 7, 1, 0, "DIVPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #565 = DIVPDrm
+ { 566, 3, 1, 0, "DIVPDrr", 0, 0|5|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #566 = DIVPDrr
+ { 567, 7, 1, 0, "DIVPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #567 = DIVPSrm
+ { 568, 3, 1, 0, "DIVPSrr", 0, 0|5|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #568 = DIVPSrr
+ { 569, 5, 0, 0, "DIVR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #569 = DIVR_F32m
+ { 570, 5, 0, 0, "DIVR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #570 = DIVR_F64m
+ { 571, 5, 0, 0, "DIVR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #571 = DIVR_FI16m
+ { 572, 5, 0, 0, "DIVR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #572 = DIVR_FI32m
+ { 573, 1, 0, 0, "DIVR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #573 = DIVR_FPrST0
+ { 574, 1, 0, 0, "DIVR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #574 = DIVR_FST0r
+ { 575, 7, 1, 0, "DIVR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #575 = DIVR_Fp32m
+ { 576, 7, 1, 0, "DIVR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #576 = DIVR_Fp64m
+ { 577, 7, 1, 0, "DIVR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #577 = DIVR_Fp64m32
+ { 578, 7, 1, 0, "DIVR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #578 = DIVR_Fp80m32
+ { 579, 7, 1, 0, "DIVR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #579 = DIVR_Fp80m64
+ { 580, 7, 1, 0, "DIVR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #580 = DIVR_FpI16m32
+ { 581, 7, 1, 0, "DIVR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #581 = DIVR_FpI16m64
+ { 582, 7, 1, 0, "DIVR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #582 = DIVR_FpI16m80
+ { 583, 7, 1, 0, "DIVR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #583 = DIVR_FpI32m32
+ { 584, 7, 1, 0, "DIVR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #584 = DIVR_FpI32m64
+ { 585, 7, 1, 0, "DIVR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #585 = DIVR_FpI32m80
+ { 586, 1, 0, 0, "DIVR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #586 = DIVR_FrST0
+ { 587, 7, 1, 0, "DIVSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #587 = DIVSDrm
+ { 588, 7, 1, 0, "DIVSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #588 = DIVSDrm_Int
+ { 589, 3, 1, 0, "DIVSDrr", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #589 = DIVSDrr
+ { 590, 3, 1, 0, "DIVSDrr_Int", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #590 = DIVSDrr_Int
+ { 591, 7, 1, 0, "DIVSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #591 = DIVSSrm
+ { 592, 7, 1, 0, "DIVSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #592 = DIVSSrm_Int
+ { 593, 3, 1, 0, "DIVSSrr", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #593 = DIVSSrr
+ { 594, 3, 1, 0, "DIVSSrr_Int", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #594 = DIVSSrr_Int
+ { 595, 5, 0, 0, "DIV_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #595 = DIV_F32m
+ { 596, 5, 0, 0, "DIV_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #596 = DIV_F64m
+ { 597, 5, 0, 0, "DIV_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #597 = DIV_FI16m
+ { 598, 5, 0, 0, "DIV_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #598 = DIV_FI32m
+ { 599, 1, 0, 0, "DIV_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #599 = DIV_FPrST0
+ { 600, 1, 0, 0, "DIV_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #600 = DIV_FST0r
+ { 601, 3, 1, 0, "DIV_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #601 = DIV_Fp32
+ { 602, 7, 1, 0, "DIV_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #602 = DIV_Fp32m
+ { 603, 3, 1, 0, "DIV_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #603 = DIV_Fp64
+ { 604, 7, 1, 0, "DIV_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #604 = DIV_Fp64m
+ { 605, 7, 1, 0, "DIV_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #605 = DIV_Fp64m32
+ { 606, 3, 1, 0, "DIV_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #606 = DIV_Fp80
+ { 607, 7, 1, 0, "DIV_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #607 = DIV_Fp80m32
+ { 608, 7, 1, 0, "DIV_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #608 = DIV_Fp80m64
+ { 609, 7, 1, 0, "DIV_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #609 = DIV_FpI16m32
+ { 610, 7, 1, 0, "DIV_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #610 = DIV_FpI16m64
+ { 611, 7, 1, 0, "DIV_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #611 = DIV_FpI16m80
+ { 612, 7, 1, 0, "DIV_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #612 = DIV_FpI32m32
+ { 613, 7, 1, 0, "DIV_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #613 = DIV_FpI32m64
+ { 614, 7, 1, 0, "DIV_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #614 = DIV_FpI32m80
+ { 615, 1, 0, 0, "DIV_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #615 = DIV_FrST0
+ { 616, 8, 1, 0, "DPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #616 = DPPDrmi
+ { 617, 4, 1, 0, "DPPDrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #617 = DPPDrri
+ { 618, 8, 1, 0, "DPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #618 = DPPSrmi
+ { 619, 4, 1, 0, "DPPSrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #619 = DPPSrri
+ { 620, 1, 0, 0, "EH_RETURN", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #620 = EH_RETURN
+ { 621, 1, 0, 0, "EH_RETURN64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #621 = EH_RETURN64
+ { 622, 2, 0, 0, "ENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(200<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #622 = ENTER
+ { 623, 7, 0, 0, "EXTRACTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #623 = EXTRACTPSmr
+ { 624, 3, 1, 0, "EXTRACTPSrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #624 = EXTRACTPSrr
+ { 625, 0, 0, 0, "F2XM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(240<<24), NULL, NULL, NULL, 0 }, // Inst #625 = F2XM1
+ { 626, 2, 0, 0, "FARCALL16i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #626 = FARCALL16i
+ { 627, 5, 0, 0, "FARCALL16m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #627 = FARCALL16m
+ { 628, 2, 0, 0, "FARCALL32i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #628 = FARCALL32i
+ { 629, 5, 0, 0, "FARCALL32m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #629 = FARCALL32m
+ { 630, 5, 0, 0, "FARCALL64", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo30 }, // Inst #630 = FARCALL64
+ { 631, 2, 0, 0, "FARJMP16i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #631 = FARJMP16i
+ { 632, 5, 0, 0, "FARJMP16m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #632 = FARJMP16m
+ { 633, 2, 0, 0, "FARJMP32i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #633 = FARJMP32i
+ { 634, 5, 0, 0, "FARJMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #634 = FARJMP32m
+ { 635, 5, 0, 0, "FARJMP64", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #635 = FARJMP64
+ { 636, 5, 0, 0, "FBLDm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #636 = FBLDm
+ { 637, 5, 1, 0, "FBSTPm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #637 = FBSTPm
+ { 638, 5, 0, 0, "FCOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #638 = FCOM32m
+ { 639, 5, 0, 0, "FCOM64m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #639 = FCOM64m
+ { 640, 5, 0, 0, "FCOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #640 = FCOMP32m
+ { 641, 5, 0, 0, "FCOMP64m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #641 = FCOMP64m
+ { 642, 0, 0, 0, "FCOMPP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(9<<8)|(217<<24), NULL, NULL, NULL, 0 }, // Inst #642 = FCOMPP
+ { 643, 0, 0, 0, "FDECSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(246<<24), NULL, NULL, NULL, 0 }, // Inst #643 = FDECSTP
+ { 644, 1, 0, 0, "FFREE", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #644 = FFREE
+ { 645, 5, 0, 0, "FICOM16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #645 = FICOM16m
+ { 646, 5, 0, 0, "FICOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #646 = FICOM32m
+ { 647, 5, 0, 0, "FICOMP16m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #647 = FICOMP16m
+ { 648, 5, 0, 0, "FICOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #648 = FICOMP32m
+ { 649, 0, 0, 0, "FINCSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(247<<24), NULL, NULL, NULL, 0 }, // Inst #649 = FINCSTP
+ { 650, 5, 1, 0, "FISTTP32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #650 = FISTTP32m
+ { 651, 5, 0, 0, "FLDCW16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #651 = FLDCW16m
+ { 652, 5, 0, 0, "FLDENVm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #652 = FLDENVm
+ { 653, 0, 0, 0, "FLDL2E", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(234<<24), NULL, NULL, NULL, 0 }, // Inst #653 = FLDL2E
+ { 654, 0, 0, 0, "FLDL2T", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(233<<24), NULL, NULL, NULL, 0 }, // Inst #654 = FLDL2T
+ { 655, 0, 0, 0, "FLDLG2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(236<<24), NULL, NULL, NULL, 0 }, // Inst #655 = FLDLG2
+ { 656, 0, 0, 0, "FLDLN2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(237<<24), NULL, NULL, NULL, 0 }, // Inst #656 = FLDLN2
+ { 657, 0, 0, 0, "FLDPI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(235<<24), NULL, NULL, NULL, 0 }, // Inst #657 = FLDPI
+ { 658, 0, 0, 0, "FNCLEX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(226<<24), NULL, NULL, NULL, 0 }, // Inst #658 = FNCLEX
+ { 659, 0, 0, 0, "FNINIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(227<<24), NULL, NULL, NULL, 0 }, // Inst #659 = FNINIT
+ { 660, 0, 0, 0, "FNOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(208<<24), NULL, NULL, NULL, 0 }, // Inst #660 = FNOP
+ { 661, 5, 0, 0, "FNSTCW16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #661 = FNSTCW16m
+ { 662, 0, 0, 0, "FNSTSW8r", 0|(1<<TID::UnmodeledSideEffects), 0|1|(10<<8)|(224<<24), NULL, ImplicitList12, NULL, 0 }, // Inst #662 = FNSTSW8r
+ { 663, 5, 1, 0, "FNSTSWm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #663 = FNSTSWm
+ { 664, 6, 0, 0, "FP32_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #664 = FP32_TO_INT16_IN_MEM
+ { 665, 6, 0, 0, "FP32_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #665 = FP32_TO_INT32_IN_MEM
+ { 666, 6, 0, 0, "FP32_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #666 = FP32_TO_INT64_IN_MEM
+ { 667, 6, 0, 0, "FP64_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #667 = FP64_TO_INT16_IN_MEM
+ { 668, 6, 0, 0, "FP64_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #668 = FP64_TO_INT32_IN_MEM
+ { 669, 6, 0, 0, "FP64_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #669 = FP64_TO_INT64_IN_MEM
+ { 670, 6, 0, 0, "FP80_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #670 = FP80_TO_INT16_IN_MEM
+ { 671, 6, 0, 0, "FP80_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #671 = FP80_TO_INT32_IN_MEM
+ { 672, 6, 0, 0, "FP80_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #672 = FP80_TO_INT64_IN_MEM
+ { 673, 0, 0, 0, "FPATAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(243<<24), NULL, NULL, NULL, 0 }, // Inst #673 = FPATAN
+ { 674, 0, 0, 0, "FPREM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(248<<24), NULL, NULL, NULL, 0 }, // Inst #674 = FPREM
+ { 675, 0, 0, 0, "FPREM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(245<<24), NULL, NULL, NULL, 0 }, // Inst #675 = FPREM1
+ { 676, 0, 0, 0, "FPTAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(242<<24), NULL, NULL, NULL, 0 }, // Inst #676 = FPTAN
+ { 677, 0, 0, 0, "FP_REG_KILL", 0|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0, NULL, ImplicitList22, Barriers7, 0 }, // Inst #677 = FP_REG_KILL
+ { 678, 0, 0, 0, "FRNDINT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(252<<24), NULL, NULL, NULL, 0 }, // Inst #678 = FRNDINT
+ { 679, 5, 1, 0, "FRSTORm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #679 = FRSTORm
+ { 680, 5, 1, 0, "FSAVEm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #680 = FSAVEm
+ { 681, 0, 0, 0, "FSCALE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(253<<24), NULL, NULL, NULL, 0 }, // Inst #681 = FSCALE
+ { 682, 0, 0, 0, "FSINCOS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(251<<24), NULL, NULL, NULL, 0 }, // Inst #682 = FSINCOS
+ { 683, 5, 1, 0, "FSTENVm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #683 = FSTENVm
+ { 684, 6, 1, 0, "FS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #684 = FS_MOV32rm
+ { 685, 0, 0, 0, "FXAM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(229<<24), NULL, NULL, NULL, 0 }, // Inst #685 = FXAM
+ { 686, 5, 0, 0, "FXRSTOR", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #686 = FXRSTOR
+ { 687, 5, 1, 0, "FXSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #687 = FXSAVE
+ { 688, 0, 0, 0, "FXTRACT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(244<<24), NULL, NULL, NULL, 0 }, // Inst #688 = FXTRACT
+ { 689, 0, 0, 0, "FYL2X", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(241<<24), NULL, NULL, NULL, 0 }, // Inst #689 = FYL2X
+ { 690, 0, 0, 0, "FYL2XP1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(249<<24), NULL, NULL, NULL, 0 }, // Inst #690 = FYL2XP1
+ { 691, 1, 1, 0, "FpGET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #691 = FpGET_ST0_32
+ { 692, 1, 1, 0, "FpGET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #692 = FpGET_ST0_64
+ { 693, 1, 1, 0, "FpGET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #693 = FpGET_ST0_80
+ { 694, 1, 1, 0, "FpGET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #694 = FpGET_ST1_32
+ { 695, 1, 1, 0, "FpGET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #695 = FpGET_ST1_64
+ { 696, 1, 1, 0, "FpGET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #696 = FpGET_ST1_80
+ { 697, 1, 0, 0, "FpSET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo100 }, // Inst #697 = FpSET_ST0_32
+ { 698, 1, 0, 0, "FpSET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo101 }, // Inst #698 = FpSET_ST0_64
+ { 699, 1, 0, 0, "FpSET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo102 }, // Inst #699 = FpSET_ST0_80
+ { 700, 1, 0, 0, "FpSET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo100 }, // Inst #700 = FpSET_ST1_32
+ { 701, 1, 0, 0, "FpSET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo101 }, // Inst #701 = FpSET_ST1_64
+ { 702, 1, 0, 0, "FpSET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo102 }, // Inst #702 = FpSET_ST1_80
+ { 703, 7, 1, 0, "FsANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #703 = FsANDNPDrm
+ { 704, 3, 1, 0, "FsANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #704 = FsANDNPDrr
+ { 705, 7, 1, 0, "FsANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #705 = FsANDNPSrm
+ { 706, 3, 1, 0, "FsANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #706 = FsANDNPSrr
+ { 707, 7, 1, 0, "FsANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #707 = FsANDPDrm
+ { 708, 3, 1, 0, "FsANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #708 = FsANDPDrr
+ { 709, 7, 1, 0, "FsANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #709 = FsANDPSrm
+ { 710, 3, 1, 0, "FsANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #710 = FsANDPSrr
+ { 711, 1, 1, 0, "FsFLD0SD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo103 }, // Inst #711 = FsFLD0SD
+ { 712, 1, 1, 0, "FsFLD0SS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #712 = FsFLD0SS
+ { 713, 6, 1, 0, "FsMOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #713 = FsMOVAPDrm
+ { 714, 2, 1, 0, "FsMOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #714 = FsMOVAPDrr
+ { 715, 6, 1, 0, "FsMOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #715 = FsMOVAPSrm
+ { 716, 2, 1, 0, "FsMOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #716 = FsMOVAPSrr
+ { 717, 7, 1, 0, "FsORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #717 = FsORPDrm
+ { 718, 3, 1, 0, "FsORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #718 = FsORPDrr
+ { 719, 7, 1, 0, "FsORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #719 = FsORPSrm
+ { 720, 3, 1, 0, "FsORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #720 = FsORPSrr
+ { 721, 7, 1, 0, "FsXORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #721 = FsXORPDrm
+ { 722, 3, 1, 0, "FsXORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #722 = FsXORPDrr
+ { 723, 7, 1, 0, "FsXORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #723 = FsXORPSrm
+ { 724, 3, 1, 0, "FsXORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #724 = FsXORPSrr
+ { 725, 6, 1, 0, "GS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #725 = GS_MOV32rm
+ { 726, 7, 1, 0, "HADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #726 = HADDPDrm
+ { 727, 3, 1, 0, "HADDPDrr", 0, 0|5|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #727 = HADDPDrr
+ { 728, 7, 1, 0, "HADDPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #728 = HADDPSrm
+ { 729, 3, 1, 0, "HADDPSrr", 0, 0|5|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #729 = HADDPSrr
+ { 730, 0, 0, 0, "HLT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(244<<24), NULL, NULL, NULL, 0 }, // Inst #730 = HLT
+ { 731, 7, 1, 0, "HSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #731 = HSUBPDrm
+ { 732, 3, 1, 0, "HSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #732 = HSUBPDrr
+ { 733, 7, 1, 0, "HSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #733 = HSUBPSrm
+ { 734, 3, 1, 0, "HSUBPSrr", 0, 0|5|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #734 = HSUBPSrr
+ { 735, 5, 0, 0, "IDIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo30 }, // Inst #735 = IDIV16m
+ { 736, 1, 0, 0, "IDIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo93 }, // Inst #736 = IDIV16r
+ { 737, 5, 0, 0, "IDIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo30 }, // Inst #737 = IDIV32m
+ { 738, 1, 0, 0, "IDIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo57 }, // Inst #738 = IDIV32r
+ { 739, 5, 0, 0, "IDIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo30 }, // Inst #739 = IDIV64m
+ { 740, 1, 0, 0, "IDIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo58 }, // Inst #740 = IDIV64r
+ { 741, 5, 0, 0, "IDIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #741 = IDIV8m
+ { 742, 1, 0, 0, "IDIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo94 }, // Inst #742 = IDIV8r
+ { 743, 5, 0, 0, "ILD_F16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #743 = ILD_F16m
+ { 744, 5, 0, 0, "ILD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #744 = ILD_F32m
+ { 745, 5, 0, 0, "ILD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #745 = ILD_F64m
+ { 746, 6, 1, 0, "ILD_Fp16m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #746 = ILD_Fp16m32
+ { 747, 6, 1, 0, "ILD_Fp16m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #747 = ILD_Fp16m64
+ { 748, 6, 1, 0, "ILD_Fp16m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #748 = ILD_Fp16m80
+ { 749, 6, 1, 0, "ILD_Fp32m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #749 = ILD_Fp32m32
+ { 750, 6, 1, 0, "ILD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #750 = ILD_Fp32m64
+ { 751, 6, 1, 0, "ILD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #751 = ILD_Fp32m80
+ { 752, 6, 1, 0, "ILD_Fp64m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #752 = ILD_Fp64m32
+ { 753, 6, 1, 0, "ILD_Fp64m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #753 = ILD_Fp64m64
+ { 754, 6, 1, 0, "ILD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #754 = ILD_Fp64m80
+ { 755, 5, 0, 0, "IMUL16m", 0|(1<<TID::MayLoad), 0|29|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo30 }, // Inst #755 = IMUL16m
+ { 756, 1, 0, 0, "IMUL16r", 0, 0|21|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo93 }, // Inst #756 = IMUL16r
+ { 757, 7, 1, 0, "IMUL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #757 = IMUL16rm
+ { 758, 7, 1, 0, "IMUL16rmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #758 = IMUL16rmi
+ { 759, 7, 1, 0, "IMUL16rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #759 = IMUL16rmi8
+ { 760, 3, 1, 0, "IMUL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #760 = IMUL16rr
+ { 761, 3, 1, 0, "IMUL16rri", 0, 0|5|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #761 = IMUL16rri
+ { 762, 3, 1, 0, "IMUL16rri8", 0, 0|5|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #762 = IMUL16rri8
+ { 763, 5, 0, 0, "IMUL32m", 0|(1<<TID::MayLoad), 0|29|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo30 }, // Inst #763 = IMUL32m
+ { 764, 1, 0, 0, "IMUL32r", 0, 0|21|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo57 }, // Inst #764 = IMUL32r
+ { 765, 7, 1, 0, "IMUL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #765 = IMUL32rm
+ { 766, 7, 1, 0, "IMUL32rmi", 0|(1<<TID::MayLoad), 0|6|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #766 = IMUL32rmi
+ { 767, 7, 1, 0, "IMUL32rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #767 = IMUL32rmi8
+ { 768, 3, 1, 0, "IMUL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #768 = IMUL32rr
+ { 769, 3, 1, 0, "IMUL32rri", 0, 0|5|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #769 = IMUL32rri
+ { 770, 3, 1, 0, "IMUL32rri8", 0, 0|5|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #770 = IMUL32rri8
+ { 771, 5, 0, 0, "IMUL64m", 0|(1<<TID::MayLoad), 0|29|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo30 }, // Inst #771 = IMUL64m
+ { 772, 1, 0, 0, "IMUL64r", 0, 0|21|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo58 }, // Inst #772 = IMUL64r
+ { 773, 7, 1, 0, "IMUL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #773 = IMUL64rm
+ { 774, 7, 1, 0, "IMUL64rmi32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #774 = IMUL64rmi32
+ { 775, 7, 1, 0, "IMUL64rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #775 = IMUL64rmi8
+ { 776, 3, 1, 0, "IMUL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #776 = IMUL64rr
+ { 777, 3, 1, 0, "IMUL64rri32", 0, 0|5|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #777 = IMUL64rri32
+ { 778, 3, 1, 0, "IMUL64rri8", 0, 0|5|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #778 = IMUL64rri8
+ { 779, 5, 0, 0, "IMUL8m", 0|(1<<TID::MayLoad), 0|29|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #779 = IMUL8m
+ { 780, 1, 0, 0, "IMUL8r", 0, 0|21|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo94 }, // Inst #780 = IMUL8r
+ { 781, 0, 0, 0, "IN16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(109<<24), NULL, NULL, NULL, 0 }, // Inst #781 = IN16
+ { 782, 1, 0, 0, "IN16ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(229<<24), NULL, ImplicitList12, NULL, OperandInfo5 }, // Inst #782 = IN16ri
+ { 783, 0, 0, 0, "IN16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(237<<24), ImplicitList25, ImplicitList12, NULL, 0 }, // Inst #783 = IN16rr
+ { 784, 0, 0, 0, "IN32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(109<<24), NULL, NULL, NULL, 0 }, // Inst #784 = IN32
+ { 785, 1, 0, 0, "IN32ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(229<<24), NULL, ImplicitList13, NULL, OperandInfo5 }, // Inst #785 = IN32ri
+ { 786, 0, 0, 0, "IN32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(237<<24), ImplicitList25, ImplicitList13, NULL, 0 }, // Inst #786 = IN32rr
+ { 787, 0, 0, 0, "IN8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(108<<24), NULL, NULL, NULL, 0 }, // Inst #787 = IN8
+ { 788, 1, 0, 0, "IN8ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(228<<24), NULL, ImplicitList11, NULL, OperandInfo5 }, // Inst #788 = IN8ri
+ { 789, 0, 0, 0, "IN8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(236<<24), ImplicitList25, ImplicitList11, NULL, 0 }, // Inst #789 = IN8rr
+ { 790, 5, 0, 0, "INC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #790 = INC16m
+ { 791, 2, 1, 0, "INC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #791 = INC16r
+ { 792, 5, 0, 0, "INC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #792 = INC32m
+ { 793, 2, 1, 0, "INC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #793 = INC32r
+ { 794, 5, 0, 0, "INC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #794 = INC64_16m
+ { 795, 2, 1, 0, "INC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #795 = INC64_16r
+ { 796, 5, 0, 0, "INC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #796 = INC64_32m
+ { 797, 2, 1, 0, "INC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #797 = INC64_32r
+ { 798, 5, 0, 0, "INC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #798 = INC64m
+ { 799, 2, 1, 0, "INC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #799 = INC64r
+ { 800, 5, 0, 0, "INC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #800 = INC8m
+ { 801, 2, 1, 0, "INC8r", 0, 0|16|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #801 = INC8r
+ { 802, 8, 1, 0, "INSERTPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #802 = INSERTPSrm
+ { 803, 4, 1, 0, "INSERTPSrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #803 = INSERTPSrr
+ { 804, 1, 0, 0, "INT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(205<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #804 = INT
+ { 805, 0, 0, 0, "INT3", 0|(1<<TID::UnmodeledSideEffects), 0|1|(204<<24), NULL, NULL, NULL, 0 }, // Inst #805 = INT3
+ { 806, 0, 0, 0, "INVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(8<<24), NULL, NULL, NULL, 0 }, // Inst #806 = INVD
+ { 807, 0, 0, 0, "INVEPT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(56<<24), NULL, NULL, NULL, 0 }, // Inst #807 = INVEPT
+ { 808, 0, 0, 0, "INVLPG", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #808 = INVLPG
+ { 809, 0, 0, 0, "INVVPID", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(56<<24), NULL, NULL, NULL, 0 }, // Inst #809 = INVVPID
+ { 810, 0, 0, 0, "IRET16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #810 = IRET16
+ { 811, 0, 0, 0, "IRET32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(207<<24), NULL, NULL, NULL, 0 }, // Inst #811 = IRET32
+ { 812, 0, 0, 0, "IRET64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #812 = IRET64
+ { 813, 5, 0, 0, "ISTT_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #813 = ISTT_FP16m
+ { 814, 5, 0, 0, "ISTT_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #814 = ISTT_FP32m
+ { 815, 5, 0, 0, "ISTT_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #815 = ISTT_FP64m
+ { 816, 6, 0, 0, "ISTT_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #816 = ISTT_Fp16m32
+ { 817, 6, 0, 0, "ISTT_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #817 = ISTT_Fp16m64
+ { 818, 6, 0, 0, "ISTT_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #818 = ISTT_Fp16m80
+ { 819, 6, 0, 0, "ISTT_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #819 = ISTT_Fp32m32
+ { 820, 6, 0, 0, "ISTT_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #820 = ISTT_Fp32m64
+ { 821, 6, 0, 0, "ISTT_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #821 = ISTT_Fp32m80
+ { 822, 6, 0, 0, "ISTT_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #822 = ISTT_Fp64m32
+ { 823, 6, 0, 0, "ISTT_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #823 = ISTT_Fp64m64
+ { 824, 6, 0, 0, "ISTT_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #824 = ISTT_Fp64m80
+ { 825, 5, 0, 0, "IST_F16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #825 = IST_F16m
+ { 826, 5, 0, 0, "IST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #826 = IST_F32m
+ { 827, 5, 0, 0, "IST_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #827 = IST_FP16m
+ { 828, 5, 0, 0, "IST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #828 = IST_FP32m
+ { 829, 5, 0, 0, "IST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #829 = IST_FP64m
+ { 830, 6, 0, 0, "IST_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #830 = IST_Fp16m32
+ { 831, 6, 0, 0, "IST_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #831 = IST_Fp16m64
+ { 832, 6, 0, 0, "IST_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #832 = IST_Fp16m80
+ { 833, 6, 0, 0, "IST_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #833 = IST_Fp32m32
+ { 834, 6, 0, 0, "IST_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #834 = IST_Fp32m64
+ { 835, 6, 0, 0, "IST_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #835 = IST_Fp32m80
+ { 836, 6, 0, 0, "IST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #836 = IST_Fp64m32
+ { 837, 6, 0, 0, "IST_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #837 = IST_Fp64m64
+ { 838, 6, 0, 0, "IST_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #838 = IST_Fp64m80
+ { 839, 8, 1, 0, "Int_CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #839 = Int_CMPSDrm
+ { 840, 4, 1, 0, "Int_CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #840 = Int_CMPSDrr
+ { 841, 8, 1, 0, "Int_CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #841 = Int_CMPSSrm
+ { 842, 4, 1, 0, "Int_CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #842 = Int_CMPSSrr
+ { 843, 6, 0, 0, "Int_COMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #843 = Int_COMISDrm
+ { 844, 2, 0, 0, "Int_COMISDrr", 0, 0|5|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #844 = Int_COMISDrr
+ { 845, 6, 0, 0, "Int_COMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #845 = Int_COMISSrm
+ { 846, 2, 0, 0, "Int_COMISSrr", 0, 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #846 = Int_COMISSrr
+ { 847, 6, 1, 0, "Int_CVTDQ2PDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #847 = Int_CVTDQ2PDrm
+ { 848, 2, 1, 0, "Int_CVTDQ2PDrr", 0, 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #848 = Int_CVTDQ2PDrr
+ { 849, 6, 1, 0, "Int_CVTDQ2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #849 = Int_CVTDQ2PSrm
+ { 850, 2, 1, 0, "Int_CVTDQ2PSrr", 0, 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #850 = Int_CVTDQ2PSrr
+ { 851, 6, 1, 0, "Int_CVTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #851 = Int_CVTPD2DQrm
+ { 852, 2, 1, 0, "Int_CVTPD2DQrr", 0, 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #852 = Int_CVTPD2DQrr
+ { 853, 6, 1, 0, "Int_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #853 = Int_CVTPD2PIrm
+ { 854, 2, 1, 0, "Int_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #854 = Int_CVTPD2PIrr
+ { 855, 6, 1, 0, "Int_CVTPD2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #855 = Int_CVTPD2PSrm
+ { 856, 2, 1, 0, "Int_CVTPD2PSrr", 0, 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #856 = Int_CVTPD2PSrr
+ { 857, 6, 1, 0, "Int_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #857 = Int_CVTPI2PDrm
+ { 858, 2, 1, 0, "Int_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #858 = Int_CVTPI2PDrr
+ { 859, 7, 1, 0, "Int_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #859 = Int_CVTPI2PSrm
+ { 860, 3, 1, 0, "Int_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #860 = Int_CVTPI2PSrr
+ { 861, 6, 1, 0, "Int_CVTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #861 = Int_CVTPS2DQrm
+ { 862, 2, 1, 0, "Int_CVTPS2DQrr", 0, 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #862 = Int_CVTPS2DQrr
+ { 863, 6, 1, 0, "Int_CVTPS2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #863 = Int_CVTPS2PDrm
+ { 864, 2, 1, 0, "Int_CVTPS2PDrr", 0, 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #864 = Int_CVTPS2PDrr
+ { 865, 6, 1, 0, "Int_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #865 = Int_CVTPS2PIrm
+ { 866, 2, 1, 0, "Int_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #866 = Int_CVTPS2PIrr
+ { 867, 6, 1, 0, "Int_CVTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #867 = Int_CVTSD2SI64rm
+ { 868, 2, 1, 0, "Int_CVTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #868 = Int_CVTSD2SI64rr
+ { 869, 6, 1, 0, "Int_CVTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #869 = Int_CVTSD2SIrm
+ { 870, 2, 1, 0, "Int_CVTSD2SIrr", 0, 0|5|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #870 = Int_CVTSD2SIrr
+ { 871, 7, 1, 0, "Int_CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #871 = Int_CVTSD2SSrm
+ { 872, 3, 1, 0, "Int_CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #872 = Int_CVTSD2SSrr
+ { 873, 7, 1, 0, "Int_CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #873 = Int_CVTSI2SD64rm
+ { 874, 3, 1, 0, "Int_CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #874 = Int_CVTSI2SD64rr
+ { 875, 7, 1, 0, "Int_CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #875 = Int_CVTSI2SDrm
+ { 876, 3, 1, 0, "Int_CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #876 = Int_CVTSI2SDrr
+ { 877, 7, 1, 0, "Int_CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #877 = Int_CVTSI2SS64rm
+ { 878, 3, 1, 0, "Int_CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #878 = Int_CVTSI2SS64rr
+ { 879, 7, 1, 0, "Int_CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #879 = Int_CVTSI2SSrm
+ { 880, 3, 1, 0, "Int_CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #880 = Int_CVTSI2SSrr
+ { 881, 7, 1, 0, "Int_CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #881 = Int_CVTSS2SDrm
+ { 882, 3, 1, 0, "Int_CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #882 = Int_CVTSS2SDrr
+ { 883, 6, 1, 0, "Int_CVTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #883 = Int_CVTSS2SI64rm
+ { 884, 2, 1, 0, "Int_CVTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #884 = Int_CVTSS2SI64rr
+ { 885, 6, 1, 0, "Int_CVTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #885 = Int_CVTSS2SIrm
+ { 886, 2, 1, 0, "Int_CVTSS2SIrr", 0, 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #886 = Int_CVTSS2SIrr
+ { 887, 6, 1, 0, "Int_CVTTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #887 = Int_CVTTPD2DQrm
+ { 888, 2, 1, 0, "Int_CVTTPD2DQrr", 0, 0|5|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #888 = Int_CVTTPD2DQrr
+ { 889, 6, 1, 0, "Int_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #889 = Int_CVTTPD2PIrm
+ { 890, 2, 1, 0, "Int_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #890 = Int_CVTTPD2PIrr
+ { 891, 6, 1, 0, "Int_CVTTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #891 = Int_CVTTPS2DQrm
+ { 892, 2, 1, 0, "Int_CVTTPS2DQrr", 0, 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #892 = Int_CVTTPS2DQrr
+ { 893, 6, 1, 0, "Int_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #893 = Int_CVTTPS2PIrm
+ { 894, 2, 1, 0, "Int_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #894 = Int_CVTTPS2PIrr
+ { 895, 6, 1, 0, "Int_CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #895 = Int_CVTTSD2SI64rm
+ { 896, 2, 1, 0, "Int_CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #896 = Int_CVTTSD2SI64rr
+ { 897, 6, 1, 0, "Int_CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #897 = Int_CVTTSD2SIrm
+ { 898, 2, 1, 0, "Int_CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #898 = Int_CVTTSD2SIrr
+ { 899, 6, 1, 0, "Int_CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #899 = Int_CVTTSS2SI64rm
+ { 900, 2, 1, 0, "Int_CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #900 = Int_CVTTSS2SI64rr
+ { 901, 6, 1, 0, "Int_CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #901 = Int_CVTTSS2SIrm
+ { 902, 2, 1, 0, "Int_CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #902 = Int_CVTTSS2SIrr
+ { 903, 6, 0, 0, "Int_UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #903 = Int_UCOMISDrm
+ { 904, 2, 0, 0, "Int_UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #904 = Int_UCOMISDrr
+ { 905, 6, 0, 0, "Int_UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #905 = Int_UCOMISSrm
+ { 906, 2, 0, 0, "Int_UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #906 = Int_UCOMISSrr
+ { 907, 1, 0, 0, "JA", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(135<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #907 = JA
+ { 908, 1, 0, 0, "JA8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(119<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #908 = JA8
+ { 909, 1, 0, 0, "JAE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(131<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #909 = JAE
+ { 910, 1, 0, 0, "JAE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(115<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #910 = JAE8
+ { 911, 1, 0, 0, "JB", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(130<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #911 = JB
+ { 912, 1, 0, 0, "JB8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(114<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #912 = JB8
+ { 913, 1, 0, 0, "JBE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(134<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #913 = JBE
+ { 914, 1, 0, 0, "JBE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(118<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #914 = JBE8
+ { 915, 1, 0, 0, "JCXZ8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(227<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #915 = JCXZ8
+ { 916, 1, 0, 0, "JE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(132<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #916 = JE
+ { 917, 1, 0, 0, "JE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(116<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #917 = JE8
+ { 918, 1, 0, 0, "JG", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(143<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #918 = JG
+ { 919, 1, 0, 0, "JG8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(127<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #919 = JG8
+ { 920, 1, 0, 0, "JGE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(141<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #920 = JGE
+ { 921, 1, 0, 0, "JGE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(125<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #921 = JGE8
+ { 922, 1, 0, 0, "JL", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(140<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #922 = JL
+ { 923, 1, 0, 0, "JL8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(124<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #923 = JL8
+ { 924, 1, 0, 0, "JLE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(142<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #924 = JLE
+ { 925, 1, 0, 0, "JLE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(126<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #925 = JLE8
+ { 926, 1, 0, 0, "JMP", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #926 = JMP
+ { 927, 5, 0, 0, "JMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #927 = JMP32m
+ { 928, 1, 0, 0, "JMP32r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #928 = JMP32r
+ { 929, 5, 0, 0, "JMP64m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #929 = JMP64m
+ { 930, 1, 0, 0, "JMP64pcrel32", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #930 = JMP64pcrel32
+ { 931, 1, 0, 0, "JMP64r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #931 = JMP64r
+ { 932, 1, 0, 0, "JMP8", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(235<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #932 = JMP8
+ { 933, 1, 0, 0, "JNE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(133<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #933 = JNE
+ { 934, 1, 0, 0, "JNE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(117<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #934 = JNE8
+ { 935, 1, 0, 0, "JNO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(129<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #935 = JNO
+ { 936, 1, 0, 0, "JNO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(113<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #936 = JNO8
+ { 937, 1, 0, 0, "JNP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(139<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #937 = JNP
+ { 938, 1, 0, 0, "JNP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(123<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #938 = JNP8
+ { 939, 1, 0, 0, "JNS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(137<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #939 = JNS
+ { 940, 1, 0, 0, "JNS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(121<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #940 = JNS8
+ { 941, 1, 0, 0, "JO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(128<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #941 = JO
+ { 942, 1, 0, 0, "JO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(112<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #942 = JO8
+ { 943, 1, 0, 0, "JP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(138<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #943 = JP
+ { 944, 1, 0, 0, "JP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(122<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #944 = JP8
+ { 945, 1, 0, 0, "JS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(136<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #945 = JS
+ { 946, 1, 0, 0, "JS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(120<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #946 = JS8
+ { 947, 0, 0, 0, "LAHF", 0, 0|1|(159<<24), ImplicitList1, ImplicitList26, NULL, 0 }, // Inst #947 = LAHF
+ { 948, 6, 1, 0, "LAR16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #948 = LAR16rm
+ { 949, 2, 1, 0, "LAR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #949 = LAR16rr
+ { 950, 6, 1, 0, "LAR32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #950 = LAR32rm
+ { 951, 2, 1, 0, "LAR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #951 = LAR32rr
+ { 952, 6, 1, 0, "LAR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #952 = LAR64rm
+ { 953, 2, 1, 0, "LAR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #953 = LAR64rr
+ { 954, 6, 0, 0, "LCMPXCHG16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<19)|(177<<24), ImplicitList12, ImplicitList27, Barriers1, OperandInfo7 }, // Inst #954 = LCMPXCHG16
+ { 955, 6, 0, 0, "LCMPXCHG32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(177<<24), ImplicitList13, ImplicitList28, Barriers1, OperandInfo11 }, // Inst #955 = LCMPXCHG32
+ { 956, 6, 0, 0, "LCMPXCHG64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<19)|(177<<24), ImplicitList15, ImplicitList29, Barriers1, OperandInfo15 }, // Inst #956 = LCMPXCHG64
+ { 957, 6, 0, 0, "LCMPXCHG8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(176<<24), ImplicitList11, ImplicitList30, Barriers1, OperandInfo20 }, // Inst #957 = LCMPXCHG8
+ { 958, 5, 0, 0, "LCMPXCHG8B", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(1<<19)|(199<<24), ImplicitList6, ImplicitList19, Barriers6, OperandInfo30 }, // Inst #958 = LCMPXCHG8B
+ { 959, 6, 1, 0, "LDDQUrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(240<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #959 = LDDQUrm
+ { 960, 5, 0, 0, "LDMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #960 = LDMXCSR
+ { 961, 6, 1, 0, "LDS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(197<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #961 = LDS16rm
+ { 962, 6, 1, 0, "LDS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(197<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #962 = LDS32rm
+ { 963, 0, 0, 0, "LD_F0", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(238<<24), NULL, NULL, NULL, 0 }, // Inst #963 = LD_F0
+ { 964, 0, 0, 0, "LD_F1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(232<<24), NULL, NULL, NULL, 0 }, // Inst #964 = LD_F1
+ { 965, 5, 0, 0, "LD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #965 = LD_F32m
+ { 966, 5, 0, 0, "LD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #966 = LD_F64m
+ { 967, 5, 0, 0, "LD_F80m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #967 = LD_F80m
+ { 968, 1, 1, 0, "LD_Fp032", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #968 = LD_Fp032
+ { 969, 1, 1, 0, "LD_Fp064", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #969 = LD_Fp064
+ { 970, 1, 1, 0, "LD_Fp080", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #970 = LD_Fp080
+ { 971, 1, 1, 0, "LD_Fp132", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #971 = LD_Fp132
+ { 972, 1, 1, 0, "LD_Fp164", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #972 = LD_Fp164
+ { 973, 1, 1, 0, "LD_Fp180", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #973 = LD_Fp180
+ { 974, 6, 1, 0, "LD_Fp32m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #974 = LD_Fp32m
+ { 975, 6, 1, 0, "LD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #975 = LD_Fp32m64
+ { 976, 6, 1, 0, "LD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #976 = LD_Fp32m80
+ { 977, 6, 1, 0, "LD_Fp64m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #977 = LD_Fp64m
+ { 978, 6, 1, 0, "LD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #978 = LD_Fp64m80
+ { 979, 6, 1, 0, "LD_Fp80m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #979 = LD_Fp80m
+ { 980, 1, 0, 0, "LD_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #980 = LD_Frr
+ { 981, 5, 1, 0, "LEA16r", 0, 0|6|(1<<6)|(141<<24), NULL, NULL, NULL, OperandInfo126 }, // Inst #981 = LEA16r
+ { 982, 5, 1, 0, "LEA32r", 0|(1<<TID::Rematerializable), 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #982 = LEA32r
+ { 983, 5, 1, 0, "LEA64_32r", 0, 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #983 = LEA64_32r
+ { 984, 5, 1, 0, "LEA64r", 0|(1<<TID::Rematerializable), 0|6|(1<<12)|(141<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #984 = LEA64r
+ { 985, 0, 0, 0, "LEAVE", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList31, ImplicitList31, NULL, 0 }, // Inst #985 = LEAVE
+ { 986, 0, 0, 0, "LEAVE64", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList32, ImplicitList32, NULL, 0 }, // Inst #986 = LEAVE64
+ { 987, 6, 1, 0, "LES16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(196<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #987 = LES16rm
+ { 988, 6, 1, 0, "LES32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(196<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #988 = LES32rm
+ { 989, 0, 0, 0, "LFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #989 = LFENCE
+ { 990, 6, 1, 0, "LFS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #990 = LFS16rm
+ { 991, 6, 1, 0, "LFS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #991 = LFS32rm
+ { 992, 6, 1, 0, "LFS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(180<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #992 = LFS64rm
+ { 993, 5, 0, 0, "LGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #993 = LGDTm
+ { 994, 6, 1, 0, "LGS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #994 = LGS16rm
+ { 995, 6, 1, 0, "LGS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #995 = LGS32rm
+ { 996, 6, 1, 0, "LGS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(181<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #996 = LGS64rm
+ { 997, 5, 0, 0, "LIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #997 = LIDTm
+ { 998, 5, 0, 0, "LLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #998 = LLDT16m
+ { 999, 1, 0, 0, "LLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #999 = LLDT16r
+ { 1000, 5, 0, 0, "LMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1000 = LMSW16m
+ { 1001, 1, 0, 0, "LMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #1001 = LMSW16r
+ { 1002, 6, 0, 0, "LOCK_ADD16mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1002 = LOCK_ADD16mi
+ { 1003, 6, 0, 0, "LOCK_ADD16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1003 = LOCK_ADD16mi8
+ { 1004, 6, 0, 0, "LOCK_ADD16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1004 = LOCK_ADD16mr
+ { 1005, 6, 0, 0, "LOCK_ADD32mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1005 = LOCK_ADD32mi
+ { 1006, 6, 0, 0, "LOCK_ADD32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1006 = LOCK_ADD32mi8
+ { 1007, 6, 0, 0, "LOCK_ADD32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1007 = LOCK_ADD32mr
+ { 1008, 6, 0, 0, "LOCK_ADD64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1008 = LOCK_ADD64mi32
+ { 1009, 6, 0, 0, "LOCK_ADD64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1009 = LOCK_ADD64mi8
+ { 1010, 6, 0, 0, "LOCK_ADD64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1010 = LOCK_ADD64mr
+ { 1011, 6, 0, 0, "LOCK_ADD8mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1011 = LOCK_ADD8mi
+ { 1012, 6, 0, 0, "LOCK_ADD8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1012 = LOCK_ADD8mr
+ { 1013, 5, 0, 0, "LOCK_DEC16m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1013 = LOCK_DEC16m
+ { 1014, 5, 0, 0, "LOCK_DEC32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1014 = LOCK_DEC32m
+ { 1015, 5, 0, 0, "LOCK_DEC64m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1015 = LOCK_DEC64m
+ { 1016, 5, 0, 0, "LOCK_DEC8m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1016 = LOCK_DEC8m
+ { 1017, 5, 0, 0, "LOCK_INC16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1017 = LOCK_INC16m
+ { 1018, 5, 0, 0, "LOCK_INC32m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1018 = LOCK_INC32m
+ { 1019, 5, 0, 0, "LOCK_INC64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1019 = LOCK_INC64m
+ { 1020, 5, 0, 0, "LOCK_INC8m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1020 = LOCK_INC8m
+ { 1021, 6, 0, 0, "LOCK_SUB16mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1021 = LOCK_SUB16mi
+ { 1022, 6, 0, 0, "LOCK_SUB16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1022 = LOCK_SUB16mi8
+ { 1023, 6, 0, 0, "LOCK_SUB16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1023 = LOCK_SUB16mr
+ { 1024, 6, 0, 0, "LOCK_SUB32mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1024 = LOCK_SUB32mi
+ { 1025, 6, 0, 0, "LOCK_SUB32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1025 = LOCK_SUB32mi8
+ { 1026, 6, 0, 0, "LOCK_SUB32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1026 = LOCK_SUB32mr
+ { 1027, 6, 0, 0, "LOCK_SUB64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1027 = LOCK_SUB64mi32
+ { 1028, 6, 0, 0, "LOCK_SUB64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1028 = LOCK_SUB64mi8
+ { 1029, 6, 0, 0, "LOCK_SUB64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1029 = LOCK_SUB64mr
+ { 1030, 6, 0, 0, "LOCK_SUB8mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1030 = LOCK_SUB8mi
+ { 1031, 6, 0, 0, "LOCK_SUB8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1031 = LOCK_SUB8mr
+ { 1032, 0, 0, 0, "LODSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(172<<24), NULL, NULL, NULL, 0 }, // Inst #1032 = LODSB
+ { 1033, 0, 0, 0, "LODSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1033 = LODSD
+ { 1034, 0, 0, 0, "LODSQ", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1034 = LODSQ
+ { 1035, 0, 0, 0, "LODSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1035 = LODSW
+ { 1036, 1, 1, 0, "LOOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(226<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1036 = LOOP
+ { 1037, 1, 1, 0, "LOOPE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(225<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1037 = LOOPE
+ { 1038, 1, 1, 0, "LOOPNE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(224<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1038 = LOOPNE
+ { 1039, 0, 0, 0, "LRET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(7<<16)|(203<<24), NULL, NULL, NULL, 0 }, // Inst #1039 = LRET
+ { 1040, 1, 0, 0, "LRETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(7<<16)|(202<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1040 = LRETI
+ { 1041, 6, 1, 0, "LSL16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1041 = LSL16rm
+ { 1042, 2, 1, 0, "LSL16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1042 = LSL16rr
+ { 1043, 6, 1, 0, "LSL32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1043 = LSL32rm
+ { 1044, 2, 1, 0, "LSL32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1044 = LSL32rr
+ { 1045, 6, 1, 0, "LSL64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1045 = LSL64rm
+ { 1046, 2, 1, 0, "LSL64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1046 = LSL64rr
+ { 1047, 6, 1, 0, "LSS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1047 = LSS16rm
+ { 1048, 6, 1, 0, "LSS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1048 = LSS32rm
+ { 1049, 6, 1, 0, "LSS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(178<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1049 = LSS64rm
+ { 1050, 5, 0, 0, "LTRm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #1050 = LTRm
+ { 1051, 1, 0, 0, "LTRr", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #1051 = LTRr
+ { 1052, 7, 1, 0, "LXADD16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1052 = LXADD16
+ { 1053, 7, 1, 0, "LXADD32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1053 = LXADD32
+ { 1054, 7, 1, 0, "LXADD64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<12)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1054 = LXADD64
+ { 1055, 7, 1, 0, "LXADD8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1055 = LXADD8
+ { 1056, 2, 0, 0, "MASKMOVDQU", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList33, NULL, NULL, OperandInfo75 }, // Inst #1056 = MASKMOVDQU
+ { 1057, 2, 0, 0, "MASKMOVDQU64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo75 }, // Inst #1057 = MASKMOVDQU64
+ { 1058, 7, 1, 0, "MAXPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1058 = MAXPDrm
+ { 1059, 7, 1, 0, "MAXPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1059 = MAXPDrm_Int
+ { 1060, 3, 1, 0, "MAXPDrr", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1060 = MAXPDrr
+ { 1061, 3, 1, 0, "MAXPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1061 = MAXPDrr_Int
+ { 1062, 7, 1, 0, "MAXPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1062 = MAXPSrm
+ { 1063, 7, 1, 0, "MAXPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1063 = MAXPSrm_Int
+ { 1064, 3, 1, 0, "MAXPSrr", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1064 = MAXPSrr
+ { 1065, 3, 1, 0, "MAXPSrr_Int", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1065 = MAXPSrr_Int
+ { 1066, 7, 1, 0, "MAXSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1066 = MAXSDrm
+ { 1067, 7, 1, 0, "MAXSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1067 = MAXSDrm_Int
+ { 1068, 3, 1, 0, "MAXSDrr", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1068 = MAXSDrr
+ { 1069, 3, 1, 0, "MAXSDrr_Int", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1069 = MAXSDrr_Int
+ { 1070, 7, 1, 0, "MAXSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1070 = MAXSSrm
+ { 1071, 7, 1, 0, "MAXSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1071 = MAXSSrm_Int
+ { 1072, 3, 1, 0, "MAXSSrr", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1072 = MAXSSrr
+ { 1073, 3, 1, 0, "MAXSSrr_Int", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1073 = MAXSSrr_Int
+ { 1074, 0, 0, 0, "MFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #1074 = MFENCE
+ { 1075, 7, 1, 0, "MINPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1075 = MINPDrm
+ { 1076, 7, 1, 0, "MINPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1076 = MINPDrm_Int
+ { 1077, 3, 1, 0, "MINPDrr", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1077 = MINPDrr
+ { 1078, 3, 1, 0, "MINPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1078 = MINPDrr_Int
+ { 1079, 7, 1, 0, "MINPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1079 = MINPSrm
+ { 1080, 7, 1, 0, "MINPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1080 = MINPSrm_Int
+ { 1081, 3, 1, 0, "MINPSrr", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1081 = MINPSrr
+ { 1082, 3, 1, 0, "MINPSrr_Int", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1082 = MINPSrr_Int
+ { 1083, 7, 1, 0, "MINSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1083 = MINSDrm
+ { 1084, 7, 1, 0, "MINSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1084 = MINSDrm_Int
+ { 1085, 3, 1, 0, "MINSDrr", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1085 = MINSDrr
+ { 1086, 3, 1, 0, "MINSDrr_Int", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1086 = MINSDrr_Int
+ { 1087, 7, 1, 0, "MINSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1087 = MINSSrm
+ { 1088, 7, 1, 0, "MINSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1088 = MINSSrm_Int
+ { 1089, 3, 1, 0, "MINSSrr", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1089 = MINSSrr
+ { 1090, 3, 1, 0, "MINSSrr_Int", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1090 = MINSSrr_Int
+ { 1091, 6, 1, 0, "MMX_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1091 = MMX_CVTPD2PIrm
+ { 1092, 2, 1, 0, "MMX_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1092 = MMX_CVTPD2PIrr
+ { 1093, 6, 1, 0, "MMX_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1093 = MMX_CVTPI2PDrm
+ { 1094, 2, 1, 0, "MMX_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1094 = MMX_CVTPI2PDrr
+ { 1095, 6, 1, 0, "MMX_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1095 = MMX_CVTPI2PSrm
+ { 1096, 2, 1, 0, "MMX_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1096 = MMX_CVTPI2PSrr
+ { 1097, 6, 1, 0, "MMX_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1097 = MMX_CVTPS2PIrm
+ { 1098, 2, 1, 0, "MMX_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1098 = MMX_CVTPS2PIrr
+ { 1099, 6, 1, 0, "MMX_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1099 = MMX_CVTTPD2PIrm
+ { 1100, 2, 1, 0, "MMX_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1100 = MMX_CVTTPD2PIrr
+ { 1101, 6, 1, 0, "MMX_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1101 = MMX_CVTTPS2PIrm
+ { 1102, 2, 1, 0, "MMX_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1102 = MMX_CVTTPS2PIrr
+ { 1103, 0, 0, 0, "MMX_EMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(119<<24), NULL, NULL, NULL, 0 }, // Inst #1103 = MMX_EMMS
+ { 1104, 0, 0, 0, "MMX_FEMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(14<<24), NULL, NULL, NULL, 0 }, // Inst #1104 = MMX_FEMMS
+ { 1105, 2, 0, 0, "MMX_MASKMOVQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList33, NULL, NULL, OperandInfo129 }, // Inst #1105 = MMX_MASKMOVQ
+ { 1106, 2, 0, 0, "MMX_MASKMOVQ64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo129 }, // Inst #1106 = MMX_MASKMOVQ64
+ { 1107, 2, 1, 0, "MMX_MOVD64from64rr", 0, 0|3|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #1107 = MMX_MOVD64from64rr
+ { 1108, 2, 0, 0, "MMX_MOVD64grr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1108 = MMX_MOVD64grr
+ { 1109, 6, 0, 0, "MMX_MOVD64mr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1109 = MMX_MOVD64mr
+ { 1110, 6, 1, 0, "MMX_MOVD64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1110 = MMX_MOVD64rm
+ { 1111, 2, 1, 0, "MMX_MOVD64rr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1111 = MMX_MOVD64rr
+ { 1112, 2, 1, 0, "MMX_MOVD64rrv164", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1112 = MMX_MOVD64rrv164
+ { 1113, 2, 1, 0, "MMX_MOVD64to64rr", 0, 0|5|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1113 = MMX_MOVD64to64rr
+ { 1114, 2, 1, 0, "MMX_MOVDQ2Qrr", 0, 0|5|(11<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1114 = MMX_MOVDQ2Qrr
+ { 1115, 6, 0, 0, "MMX_MOVNTQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1115 = MMX_MOVNTQmr
+ { 1116, 2, 1, 0, "MMX_MOVQ2DQrr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1116 = MMX_MOVQ2DQrr
+ { 1117, 2, 1, 0, "MMX_MOVQ2FR64rr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1117 = MMX_MOVQ2FR64rr
+ { 1118, 6, 0, 0, "MMX_MOVQ64gmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1118 = MMX_MOVQ64gmr
+ { 1119, 6, 0, 0, "MMX_MOVQ64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1119 = MMX_MOVQ64mr
+ { 1120, 6, 1, 0, "MMX_MOVQ64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1120 = MMX_MOVQ64rm
+ { 1121, 2, 1, 0, "MMX_MOVQ64rr", 0, 0|5|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1121 = MMX_MOVQ64rr
+ { 1122, 6, 1, 0, "MMX_MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1122 = MMX_MOVZDI2PDIrm
+ { 1123, 2, 1, 0, "MMX_MOVZDI2PDIrr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1123 = MMX_MOVZDI2PDIrr
+ { 1124, 7, 1, 0, "MMX_PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1124 = MMX_PACKSSDWrm
+ { 1125, 3, 1, 0, "MMX_PACKSSDWrr", 0, 0|5|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1125 = MMX_PACKSSDWrr
+ { 1126, 7, 1, 0, "MMX_PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1126 = MMX_PACKSSWBrm
+ { 1127, 3, 1, 0, "MMX_PACKSSWBrr", 0, 0|5|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1127 = MMX_PACKSSWBrr
+ { 1128, 7, 1, 0, "MMX_PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1128 = MMX_PACKUSWBrm
+ { 1129, 3, 1, 0, "MMX_PACKUSWBrr", 0, 0|5|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1129 = MMX_PACKUSWBrr
+ { 1130, 7, 1, 0, "MMX_PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1130 = MMX_PADDBrm
+ { 1131, 3, 1, 0, "MMX_PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1131 = MMX_PADDBrr
+ { 1132, 7, 1, 0, "MMX_PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1132 = MMX_PADDDrm
+ { 1133, 3, 1, 0, "MMX_PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1133 = MMX_PADDDrr
+ { 1134, 7, 1, 0, "MMX_PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1134 = MMX_PADDQrm
+ { 1135, 3, 1, 0, "MMX_PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1135 = MMX_PADDQrr
+ { 1136, 7, 1, 0, "MMX_PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1136 = MMX_PADDSBrm
+ { 1137, 3, 1, 0, "MMX_PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1137 = MMX_PADDSBrr
+ { 1138, 7, 1, 0, "MMX_PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1138 = MMX_PADDSWrm
+ { 1139, 3, 1, 0, "MMX_PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1139 = MMX_PADDSWrr
+ { 1140, 7, 1, 0, "MMX_PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1140 = MMX_PADDUSBrm
+ { 1141, 3, 1, 0, "MMX_PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1141 = MMX_PADDUSBrr
+ { 1142, 7, 1, 0, "MMX_PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1142 = MMX_PADDUSWrm
+ { 1143, 3, 1, 0, "MMX_PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1143 = MMX_PADDUSWrr
+ { 1144, 7, 1, 0, "MMX_PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1144 = MMX_PADDWrm
+ { 1145, 3, 1, 0, "MMX_PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1145 = MMX_PADDWrr
+ { 1146, 7, 1, 0, "MMX_PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1146 = MMX_PANDNrm
+ { 1147, 3, 1, 0, "MMX_PANDNrr", 0, 0|5|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1147 = MMX_PANDNrr
+ { 1148, 7, 1, 0, "MMX_PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1148 = MMX_PANDrm
+ { 1149, 3, 1, 0, "MMX_PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1149 = MMX_PANDrr
+ { 1150, 7, 1, 0, "MMX_PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1150 = MMX_PAVGBrm
+ { 1151, 3, 1, 0, "MMX_PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1151 = MMX_PAVGBrr
+ { 1152, 7, 1, 0, "MMX_PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1152 = MMX_PAVGWrm
+ { 1153, 3, 1, 0, "MMX_PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1153 = MMX_PAVGWrr
+ { 1154, 7, 1, 0, "MMX_PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1154 = MMX_PCMPEQBrm
+ { 1155, 3, 1, 0, "MMX_PCMPEQBrr", 0, 0|5|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1155 = MMX_PCMPEQBrr
+ { 1156, 7, 1, 0, "MMX_PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1156 = MMX_PCMPEQDrm
+ { 1157, 3, 1, 0, "MMX_PCMPEQDrr", 0, 0|5|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1157 = MMX_PCMPEQDrr
+ { 1158, 7, 1, 0, "MMX_PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1158 = MMX_PCMPEQWrm
+ { 1159, 3, 1, 0, "MMX_PCMPEQWrr", 0, 0|5|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1159 = MMX_PCMPEQWrr
+ { 1160, 7, 1, 0, "MMX_PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1160 = MMX_PCMPGTBrm
+ { 1161, 3, 1, 0, "MMX_PCMPGTBrr", 0, 0|5|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1161 = MMX_PCMPGTBrr
+ { 1162, 7, 1, 0, "MMX_PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1162 = MMX_PCMPGTDrm
+ { 1163, 3, 1, 0, "MMX_PCMPGTDrr", 0, 0|5|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1163 = MMX_PCMPGTDrr
+ { 1164, 7, 1, 0, "MMX_PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1164 = MMX_PCMPGTWrm
+ { 1165, 3, 1, 0, "MMX_PCMPGTWrr", 0, 0|5|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1165 = MMX_PCMPGTWrr
+ { 1166, 3, 1, 0, "MMX_PEXTRWri", 0, 0|5|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo138 }, // Inst #1166 = MMX_PEXTRWri
+ { 1167, 8, 1, 0, "MMX_PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1167 = MMX_PINSRWrmi
+ { 1168, 4, 1, 0, "MMX_PINSRWrri", 0, 0|5|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo140 }, // Inst #1168 = MMX_PINSRWrri
+ { 1169, 7, 1, 0, "MMX_PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1169 = MMX_PMADDWDrm
+ { 1170, 3, 1, 0, "MMX_PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1170 = MMX_PMADDWDrr
+ { 1171, 7, 1, 0, "MMX_PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1171 = MMX_PMAXSWrm
+ { 1172, 3, 1, 0, "MMX_PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1172 = MMX_PMAXSWrr
+ { 1173, 7, 1, 0, "MMX_PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1173 = MMX_PMAXUBrm
+ { 1174, 3, 1, 0, "MMX_PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1174 = MMX_PMAXUBrr
+ { 1175, 7, 1, 0, "MMX_PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1175 = MMX_PMINSWrm
+ { 1176, 3, 1, 0, "MMX_PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1176 = MMX_PMINSWrr
+ { 1177, 7, 1, 0, "MMX_PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1177 = MMX_PMINUBrm
+ { 1178, 3, 1, 0, "MMX_PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1178 = MMX_PMINUBrr
+ { 1179, 2, 1, 0, "MMX_PMOVMSKBrr", 0, 0|5|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1179 = MMX_PMOVMSKBrr
+ { 1180, 7, 1, 0, "MMX_PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1180 = MMX_PMULHUWrm
+ { 1181, 3, 1, 0, "MMX_PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1181 = MMX_PMULHUWrr
+ { 1182, 7, 1, 0, "MMX_PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1182 = MMX_PMULHWrm
+ { 1183, 3, 1, 0, "MMX_PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1183 = MMX_PMULHWrr
+ { 1184, 7, 1, 0, "MMX_PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1184 = MMX_PMULLWrm
+ { 1185, 3, 1, 0, "MMX_PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1185 = MMX_PMULLWrr
+ { 1186, 7, 1, 0, "MMX_PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1186 = MMX_PMULUDQrm
+ { 1187, 3, 1, 0, "MMX_PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1187 = MMX_PMULUDQrr
+ { 1188, 7, 1, 0, "MMX_PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1188 = MMX_PORrm
+ { 1189, 3, 1, 0, "MMX_PORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1189 = MMX_PORrr
+ { 1190, 7, 1, 0, "MMX_PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1190 = MMX_PSADBWrm
+ { 1191, 3, 1, 0, "MMX_PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1191 = MMX_PSADBWrr
+ { 1192, 7, 1, 0, "MMX_PSHUFWmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo141 }, // Inst #1192 = MMX_PSHUFWmi
+ { 1193, 3, 1, 0, "MMX_PSHUFWri", 0, 0|5|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1193 = MMX_PSHUFWri
+ { 1194, 3, 1, 0, "MMX_PSLLDri", 0, 0|22|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1194 = MMX_PSLLDri
+ { 1195, 7, 1, 0, "MMX_PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1195 = MMX_PSLLDrm
+ { 1196, 3, 1, 0, "MMX_PSLLDrr", 0, 0|5|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1196 = MMX_PSLLDrr
+ { 1197, 3, 1, 0, "MMX_PSLLQri", 0, 0|22|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1197 = MMX_PSLLQri
+ { 1198, 7, 1, 0, "MMX_PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1198 = MMX_PSLLQrm
+ { 1199, 3, 1, 0, "MMX_PSLLQrr", 0, 0|5|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1199 = MMX_PSLLQrr
+ { 1200, 3, 1, 0, "MMX_PSLLWri", 0, 0|22|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1200 = MMX_PSLLWri
+ { 1201, 7, 1, 0, "MMX_PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1201 = MMX_PSLLWrm
+ { 1202, 3, 1, 0, "MMX_PSLLWrr", 0, 0|5|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1202 = MMX_PSLLWrr
+ { 1203, 3, 1, 0, "MMX_PSRADri", 0, 0|20|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1203 = MMX_PSRADri
+ { 1204, 7, 1, 0, "MMX_PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1204 = MMX_PSRADrm
+ { 1205, 3, 1, 0, "MMX_PSRADrr", 0, 0|5|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1205 = MMX_PSRADrr
+ { 1206, 3, 1, 0, "MMX_PSRAWri", 0, 0|20|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1206 = MMX_PSRAWri
+ { 1207, 7, 1, 0, "MMX_PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1207 = MMX_PSRAWrm
+ { 1208, 3, 1, 0, "MMX_PSRAWrr", 0, 0|5|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1208 = MMX_PSRAWrr
+ { 1209, 3, 1, 0, "MMX_PSRLDri", 0, 0|18|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1209 = MMX_PSRLDri
+ { 1210, 7, 1, 0, "MMX_PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1210 = MMX_PSRLDrm
+ { 1211, 3, 1, 0, "MMX_PSRLDrr", 0, 0|5|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1211 = MMX_PSRLDrr
+ { 1212, 3, 1, 0, "MMX_PSRLQri", 0, 0|18|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1212 = MMX_PSRLQri
+ { 1213, 7, 1, 0, "MMX_PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1213 = MMX_PSRLQrm
+ { 1214, 3, 1, 0, "MMX_PSRLQrr", 0, 0|5|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1214 = MMX_PSRLQrr
+ { 1215, 3, 1, 0, "MMX_PSRLWri", 0, 0|18|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1215 = MMX_PSRLWri
+ { 1216, 7, 1, 0, "MMX_PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1216 = MMX_PSRLWrm
+ { 1217, 3, 1, 0, "MMX_PSRLWrr", 0, 0|5|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1217 = MMX_PSRLWrr
+ { 1218, 7, 1, 0, "MMX_PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1218 = MMX_PSUBBrm
+ { 1219, 3, 1, 0, "MMX_PSUBBrr", 0, 0|5|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1219 = MMX_PSUBBrr
+ { 1220, 7, 1, 0, "MMX_PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1220 = MMX_PSUBDrm
+ { 1221, 3, 1, 0, "MMX_PSUBDrr", 0, 0|5|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1221 = MMX_PSUBDrr
+ { 1222, 7, 1, 0, "MMX_PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1222 = MMX_PSUBQrm
+ { 1223, 3, 1, 0, "MMX_PSUBQrr", 0, 0|5|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1223 = MMX_PSUBQrr
+ { 1224, 7, 1, 0, "MMX_PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1224 = MMX_PSUBSBrm
+ { 1225, 3, 1, 0, "MMX_PSUBSBrr", 0, 0|5|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1225 = MMX_PSUBSBrr
+ { 1226, 7, 1, 0, "MMX_PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1226 = MMX_PSUBSWrm
+ { 1227, 3, 1, 0, "MMX_PSUBSWrr", 0, 0|5|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1227 = MMX_PSUBSWrr
+ { 1228, 7, 1, 0, "MMX_PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1228 = MMX_PSUBUSBrm
+ { 1229, 3, 1, 0, "MMX_PSUBUSBrr", 0, 0|5|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1229 = MMX_PSUBUSBrr
+ { 1230, 7, 1, 0, "MMX_PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1230 = MMX_PSUBUSWrm
+ { 1231, 3, 1, 0, "MMX_PSUBUSWrr", 0, 0|5|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1231 = MMX_PSUBUSWrr
+ { 1232, 7, 1, 0, "MMX_PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1232 = MMX_PSUBWrm
+ { 1233, 3, 1, 0, "MMX_PSUBWrr", 0, 0|5|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1233 = MMX_PSUBWrr
+ { 1234, 7, 1, 0, "MMX_PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1234 = MMX_PUNPCKHBWrm
+ { 1235, 3, 1, 0, "MMX_PUNPCKHBWrr", 0, 0|5|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1235 = MMX_PUNPCKHBWrr
+ { 1236, 7, 1, 0, "MMX_PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1236 = MMX_PUNPCKHDQrm
+ { 1237, 3, 1, 0, "MMX_PUNPCKHDQrr", 0, 0|5|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1237 = MMX_PUNPCKHDQrr
+ { 1238, 7, 1, 0, "MMX_PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1238 = MMX_PUNPCKHWDrm
+ { 1239, 3, 1, 0, "MMX_PUNPCKHWDrr", 0, 0|5|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1239 = MMX_PUNPCKHWDrr
+ { 1240, 7, 1, 0, "MMX_PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1240 = MMX_PUNPCKLBWrm
+ { 1241, 3, 1, 0, "MMX_PUNPCKLBWrr", 0, 0|5|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1241 = MMX_PUNPCKLBWrr
+ { 1242, 7, 1, 0, "MMX_PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1242 = MMX_PUNPCKLDQrm
+ { 1243, 3, 1, 0, "MMX_PUNPCKLDQrr", 0, 0|5|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1243 = MMX_PUNPCKLDQrr
+ { 1244, 7, 1, 0, "MMX_PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1244 = MMX_PUNPCKLWDrm
+ { 1245, 3, 1, 0, "MMX_PUNPCKLWDrr", 0, 0|5|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1245 = MMX_PUNPCKLWDrr
+ { 1246, 7, 1, 0, "MMX_PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1246 = MMX_PXORrm
+ { 1247, 3, 1, 0, "MMX_PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1247 = MMX_PXORrr
+ { 1248, 1, 1, 0, "MMX_V_SET0", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1248 = MMX_V_SET0
+ { 1249, 1, 1, 0, "MMX_V_SETALLONES", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1249 = MMX_V_SETALLONES
+ { 1250, 0, 0, 0, "MONITOR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1250 = MONITOR
+ { 1251, 1, 1, 0, "MOV16ao16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1251 = MOV16ao16
+ { 1252, 6, 0, 0, "MOV16mi", 0|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1252 = MOV16mi
+ { 1253, 6, 0, 0, "MOV16mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #1253 = MOV16mr
+ { 1254, 6, 1, 0, "MOV16ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1254 = MOV16ms
+ { 1255, 1, 0, 0, "MOV16o16a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1255 = MOV16o16a
+ { 1256, 2, 1, 0, "MOV16ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<6)|(2<<13)|(184<<24), NULL, NULL, NULL, OperandInfo54 }, // Inst #1256 = MOV16ri
+ { 1257, 6, 1, 0, "MOV16rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1257 = MOV16rm
+ { 1258, 2, 1, 0, "MOV16rr", 0, 0|3|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1258 = MOV16rr
+ { 1259, 2, 1, 0, "MOV16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1259 = MOV16rr_REV
+ { 1260, 2, 1, 0, "MOV16rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(140<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1260 = MOV16rs
+ { 1261, 6, 1, 0, "MOV16sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1261 = MOV16sm
+ { 1262, 2, 1, 0, "MOV16sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(142<<24), NULL, NULL, NULL, OperandInfo148 }, // Inst #1262 = MOV16sr
+ { 1263, 1, 1, 0, "MOV32ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1263 = MOV32ao32
+ { 1264, 2, 1, 0, "MOV32cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo149 }, // Inst #1264 = MOV32cr
+ { 1265, 2, 1, 0, "MOV32dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1265 = MOV32dr
+ { 1266, 6, 0, 0, "MOV32mi", 0|(1<<TID::MayStore), 0|24|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1266 = MOV32mi
+ { 1267, 6, 0, 0, "MOV32mr", 0|(1<<TID::MayStore), 0|4|(137<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1267 = MOV32mr
+ { 1268, 1, 0, 0, "MOV32o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1268 = MOV32o32a
+ { 1269, 1, 1, 0, "MOV32r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #1269 = MOV32r0
+ { 1270, 2, 1, 0, "MOV32rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo151 }, // Inst #1270 = MOV32rc
+ { 1271, 2, 1, 0, "MOV32rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo152 }, // Inst #1271 = MOV32rd
+ { 1272, 2, 1, 0, "MOV32ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1272 = MOV32ri
+ { 1273, 6, 1, 0, "MOV32rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1273 = MOV32rm
+ { 1274, 2, 1, 0, "MOV32rr", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1274 = MOV32rr
+ { 1275, 2, 1, 0, "MOV32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1275 = MOV32rr_REV
+ { 1276, 6, 1, 0, "MOV64FSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1276 = MOV64FSrm
+ { 1277, 6, 1, 0, "MOV64GSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1277 = MOV64GSrm
+ { 1278, 1, 1, 0, "MOV64ao64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1278 = MOV64ao64
+ { 1279, 1, 1, 0, "MOV64ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1279 = MOV64ao8
+ { 1280, 2, 1, 0, "MOV64cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo153 }, // Inst #1280 = MOV64cr
+ { 1281, 2, 1, 0, "MOV64dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1281 = MOV64dr
+ { 1282, 6, 0, 0, "MOV64mi32", 0|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1282 = MOV64mi32
+ { 1283, 6, 0, 0, "MOV64mr", 0|(1<<TID::MayStore), 0|4|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1283 = MOV64mr
+ { 1284, 6, 1, 0, "MOV64ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1284 = MOV64ms
+ { 1285, 1, 0, 0, "MOV64o64a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1285 = MOV64o64a
+ { 1286, 1, 0, 0, "MOV64o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1286 = MOV64o8a
+ { 1287, 2, 1, 0, "MOV64rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1287 = MOV64rc
+ { 1288, 2, 1, 0, "MOV64rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo156 }, // Inst #1288 = MOV64rd
+ { 1289, 2, 1, 0, "MOV64ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<12)|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1289 = MOV64ri
+ { 1290, 2, 1, 0, "MOV64ri32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|16|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1290 = MOV64ri32
+ { 1291, 2, 1, 0, "MOV64ri64i32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1291 = MOV64ri64i32
+ { 1292, 6, 1, 0, "MOV64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1292 = MOV64rm
+ { 1293, 2, 1, 0, "MOV64rr", 0, 0|3|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1293 = MOV64rr
+ { 1294, 2, 1, 0, "MOV64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1294 = MOV64rr_REV
+ { 1295, 2, 1, 0, "MOV64rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo157 }, // Inst #1295 = MOV64rs
+ { 1296, 6, 1, 0, "MOV64sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1296 = MOV64sm
+ { 1297, 2, 1, 0, "MOV64sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo158 }, // Inst #1297 = MOV64sr
+ { 1298, 2, 1, 0, "MOV64toPQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1298 = MOV64toPQIrr
+ { 1299, 6, 1, 0, "MOV64toSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1299 = MOV64toSDrm
+ { 1300, 2, 1, 0, "MOV64toSDrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #1300 = MOV64toSDrr
+ { 1301, 1, 1, 0, "MOV8ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1301 = MOV8ao8
+ { 1302, 6, 0, 0, "MOV8mi", 0|(1<<TID::MayStore), 0|24|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1302 = MOV8mi
+ { 1303, 6, 0, 0, "MOV8mr", 0|(1<<TID::MayStore), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #1303 = MOV8mr
+ { 1304, 6, 0, 0, "MOV8mr_NOREX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo160 }, // Inst #1304 = MOV8mr_NOREX
+ { 1305, 1, 0, 0, "MOV8o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1305 = MOV8o8a
+ { 1306, 1, 1, 0, "MOV8r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #1306 = MOV8r0
+ { 1307, 2, 1, 0, "MOV8ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<13)|(176<<24), NULL, NULL, NULL, OperandInfo68 }, // Inst #1307 = MOV8ri
+ { 1308, 6, 1, 0, "MOV8rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo69 }, // Inst #1308 = MOV8rm
+ { 1309, 6, 1, 0, "MOV8rm_NOREX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1309 = MOV8rm_NOREX
+ { 1310, 2, 1, 0, "MOV8rr", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1310 = MOV8rr
+ { 1311, 2, 1, 0, "MOV8rr_NOREX", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1311 = MOV8rr_NOREX
+ { 1312, 2, 1, 0, "MOV8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(138<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1312 = MOV8rr_REV
+ { 1313, 6, 0, 0, "MOVAPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1313 = MOVAPDmr
+ { 1314, 6, 1, 0, "MOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1314 = MOVAPDrm
+ { 1315, 2, 1, 0, "MOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1315 = MOVAPDrr
+ { 1316, 6, 0, 0, "MOVAPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1316 = MOVAPSmr
+ { 1317, 6, 1, 0, "MOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1317 = MOVAPSrm
+ { 1318, 2, 1, 0, "MOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1318 = MOVAPSrr
+ { 1319, 6, 1, 0, "MOVDDUPrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1319 = MOVDDUPrm
+ { 1320, 2, 1, 0, "MOVDDUPrr", 0, 0|5|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1320 = MOVDDUPrr
+ { 1321, 6, 1, 0, "MOVDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1321 = MOVDI2PDIrm
+ { 1322, 2, 1, 0, "MOVDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1322 = MOVDI2PDIrr
+ { 1323, 6, 1, 0, "MOVDI2SSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1323 = MOVDI2SSrm
+ { 1324, 2, 1, 0, "MOVDI2SSrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #1324 = MOVDI2SSrr
+ { 1325, 6, 0, 0, "MOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1325 = MOVDQAmr
+ { 1326, 6, 1, 0, "MOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1326 = MOVDQArm
+ { 1327, 2, 1, 0, "MOVDQArr", 0, 0|5|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1327 = MOVDQArr
+ { 1328, 6, 0, 0, "MOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1328 = MOVDQUmr
+ { 1329, 6, 0, 0, "MOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1329 = MOVDQUmr_Int
+ { 1330, 6, 1, 0, "MOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1330 = MOVDQUrm
+ { 1331, 6, 1, 0, "MOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1331 = MOVDQUrm_Int
+ { 1332, 3, 1, 0, "MOVHLPSrr", 0, 0|5|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1332 = MOVHLPSrr
+ { 1333, 6, 0, 0, "MOVHPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1333 = MOVHPDmr
+ { 1334, 7, 1, 0, "MOVHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1334 = MOVHPDrm
+ { 1335, 6, 0, 0, "MOVHPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1335 = MOVHPSmr
+ { 1336, 7, 1, 0, "MOVHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1336 = MOVHPSrm
+ { 1337, 3, 1, 0, "MOVLHPSrr", 0, 0|5|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1337 = MOVLHPSrr
+ { 1338, 6, 0, 0, "MOVLPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1338 = MOVLPDmr
+ { 1339, 7, 1, 0, "MOVLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1339 = MOVLPDrm
+ { 1340, 3, 1, 0, "MOVLPDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1340 = MOVLPDrr
+ { 1341, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1341 = MOVLPSmr
+ { 1342, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1342 = MOVLPSrm
+ { 1343, 3, 1, 0, "MOVLPSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1343 = MOVLPSrr
+ { 1344, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1344 = MOVLQ128mr
+ { 1345, 3, 1, 0, "MOVLSD2PDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1345 = MOVLSD2PDrr
+ { 1346, 3, 1, 0, "MOVLSS2PSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1346 = MOVLSS2PSrr
+ { 1347, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1347 = MOVMSKPDrr
+ { 1348, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1348 = MOVMSKPSrr
+ { 1349, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1349 = MOVNTDQArm
+ { 1350, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1350 = MOVNTDQmr
+ { 1351, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1351 = MOVNTImr
+ { 1352, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1352 = MOVNTPDmr
+ { 1353, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1353 = MOVNTPSmr
+ { 1354, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(3<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo55 }, // Inst #1354 = MOVPC32r
+ { 1355, 6, 0, 0, "MOVPD2SDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1355 = MOVPD2SDmr
+ { 1356, 2, 1, 0, "MOVPD2SDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1356 = MOVPD2SDrr
+ { 1357, 6, 0, 0, "MOVPDI2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1357 = MOVPDI2DImr
+ { 1358, 2, 1, 0, "MOVPDI2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1358 = MOVPDI2DIrr
+ { 1359, 6, 0, 0, "MOVPQI2QImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1359 = MOVPQI2QImr
+ { 1360, 2, 1, 0, "MOVPQIto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1360 = MOVPQIto64rr
+ { 1361, 6, 0, 0, "MOVPS2SSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1361 = MOVPS2SSmr
+ { 1362, 2, 1, 0, "MOVPS2SSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1362 = MOVPS2SSrr
+ { 1363, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1363 = MOVQI2PQIrm
+ { 1364, 2, 1, 0, "MOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1364 = MOVQxrxr
+ { 1365, 6, 1, 0, "MOVSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1365 = MOVSD2PDrm
+ { 1366, 2, 1, 0, "MOVSD2PDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1366 = MOVSD2PDrr
+ { 1367, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1367 = MOVSDmr
+ { 1368, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1368 = MOVSDrm
+ { 1369, 2, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1369 = MOVSDrr
+ { 1370, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1370 = MOVSDto64mr
+ { 1371, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #1371 = MOVSDto64rr
+ { 1372, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1372 = MOVSHDUPrm
+ { 1373, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1373 = MOVSHDUPrr
+ { 1374, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1374 = MOVSLDUPrm
+ { 1375, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1375 = MOVSLDUPrr
+ { 1376, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1376 = MOVSS2DImr
+ { 1377, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1377 = MOVSS2DIrr
+ { 1378, 6, 1, 0, "MOVSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1378 = MOVSS2PSrm
+ { 1379, 2, 1, 0, "MOVSS2PSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1379 = MOVSS2PSrr
+ { 1380, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1380 = MOVSSmr
+ { 1381, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1381 = MOVSSrm
+ { 1382, 2, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1382 = MOVSSrr
+ { 1383, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1383 = MOVSX16rm8
+ { 1384, 6, 1, 0, "MOVSX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1384 = MOVSX16rm8W
+ { 1385, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1385 = MOVSX16rr8
+ { 1386, 2, 1, 0, "MOVSX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1386 = MOVSX16rr8W
+ { 1387, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1387 = MOVSX32rm16
+ { 1388, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1388 = MOVSX32rm8
+ { 1389, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1389 = MOVSX32rr16
+ { 1390, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1390 = MOVSX32rr8
+ { 1391, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1391 = MOVSX64rm16
+ { 1392, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1392 = MOVSX64rm32
+ { 1393, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1393 = MOVSX64rm8
+ { 1394, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1394 = MOVSX64rr16
+ { 1395, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1395 = MOVSX64rr32
+ { 1396, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1396 = MOVSX64rr8
+ { 1397, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1397 = MOVUPDmr
+ { 1398, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1398 = MOVUPDmr_Int
+ { 1399, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1399 = MOVUPDrm
+ { 1400, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1400 = MOVUPDrm_Int
+ { 1401, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1401 = MOVUPDrr
+ { 1402, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1402 = MOVUPSmr
+ { 1403, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1403 = MOVUPSmr_Int
+ { 1404, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1404 = MOVUPSrm
+ { 1405, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1405 = MOVUPSrm_Int
+ { 1406, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1406 = MOVUPSrr
+ { 1407, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1407 = MOVZDI2PDIrm
+ { 1408, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1408 = MOVZDI2PDIrr
+ { 1409, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1409 = MOVZPQILo2PQIrm
+ { 1410, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1410 = MOVZPQILo2PQIrr
+ { 1411, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1411 = MOVZQI2PQIrm
+ { 1412, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1412 = MOVZQI2PQIrr
+ { 1413, 6, 1, 0, "MOVZSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1413 = MOVZSD2PDrm
+ { 1414, 6, 1, 0, "MOVZSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1414 = MOVZSS2PSrm
+ { 1415, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1415 = MOVZX16rm8
+ { 1416, 6, 1, 0, "MOVZX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1416 = MOVZX16rm8W
+ { 1417, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1417 = MOVZX16rr8
+ { 1418, 2, 1, 0, "MOVZX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1418 = MOVZX16rr8W
+ { 1419, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1419 = MOVZX32_NOREXrm8
+ { 1420, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1420 = MOVZX32_NOREXrr8
+ { 1421, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1421 = MOVZX32rm16
+ { 1422, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1422 = MOVZX32rm8
+ { 1423, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1423 = MOVZX32rr16
+ { 1424, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1424 = MOVZX32rr8
+ { 1425, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1425 = MOVZX64rm16
+ { 1426, 6, 1, 0, "MOVZX64rm16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1426 = MOVZX64rm16_Q
+ { 1427, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1427 = MOVZX64rm32
+ { 1428, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1428 = MOVZX64rm8
+ { 1429, 6, 1, 0, "MOVZX64rm8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1429 = MOVZX64rm8_Q
+ { 1430, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1430 = MOVZX64rr16
+ { 1431, 2, 1, 0, "MOVZX64rr16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1431 = MOVZX64rr16_Q
+ { 1432, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1432 = MOVZX64rr32
+ { 1433, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1433 = MOVZX64rr8
+ { 1434, 2, 1, 0, "MOVZX64rr8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1434 = MOVZX64rr8_Q
+ { 1435, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1435 = MOV_Fp3232
+ { 1436, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo180 }, // Inst #1436 = MOV_Fp3264
+ { 1437, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo181 }, // Inst #1437 = MOV_Fp3280
+ { 1438, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo182 }, // Inst #1438 = MOV_Fp6432
+ { 1439, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1439 = MOV_Fp6464
+ { 1440, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo183 }, // Inst #1440 = MOV_Fp6480
+ { 1441, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo184 }, // Inst #1441 = MOV_Fp8032
+ { 1442, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo185 }, // Inst #1442 = MOV_Fp8064
+ { 1443, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1443 = MOV_Fp8080
+ { 1444, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1444 = MPSADBWrmi
+ { 1445, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1445 = MPSADBWrri
+ { 1446, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo30 }, // Inst #1446 = MUL16m
+ { 1447, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo93 }, // Inst #1447 = MUL16r
+ { 1448, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo30 }, // Inst #1448 = MUL32m
+ { 1449, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo57 }, // Inst #1449 = MUL32r
+ { 1450, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo30 }, // Inst #1450 = MUL64m
+ { 1451, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo58 }, // Inst #1451 = MUL64r
+ { 1452, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #1452 = MUL8m
+ { 1453, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo94 }, // Inst #1453 = MUL8r
+ { 1454, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1454 = MULPDrm
+ { 1455, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1455 = MULPDrr
+ { 1456, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1456 = MULPSrm
+ { 1457, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1457 = MULPSrr
+ { 1458, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1458 = MULSDrm
+ { 1459, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1459 = MULSDrm_Int
+ { 1460, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1460 = MULSDrr
+ { 1461, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1461 = MULSDrr_Int
+ { 1462, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1462 = MULSSrm
+ { 1463, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1463 = MULSSrm_Int
+ { 1464, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1464 = MULSSrr
+ { 1465, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1465 = MULSSrr_Int
+ { 1466, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1466 = MUL_F32m
+ { 1467, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1467 = MUL_F64m
+ { 1468, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1468 = MUL_FI16m
+ { 1469, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1469 = MUL_FI32m
+ { 1470, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1470 = MUL_FPrST0
+ { 1471, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1471 = MUL_FST0r
+ { 1472, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1472 = MUL_Fp32
+ { 1473, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1473 = MUL_Fp32m
+ { 1474, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1474 = MUL_Fp64
+ { 1475, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1475 = MUL_Fp64m
+ { 1476, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1476 = MUL_Fp64m32
+ { 1477, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1477 = MUL_Fp80
+ { 1478, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1478 = MUL_Fp80m32
+ { 1479, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1479 = MUL_Fp80m64
+ { 1480, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1480 = MUL_FpI16m32
+ { 1481, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1481 = MUL_FpI16m64
+ { 1482, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1482 = MUL_FpI16m80
+ { 1483, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1483 = MUL_FpI32m32
+ { 1484, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1484 = MUL_FpI32m64
+ { 1485, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1485 = MUL_FpI32m80
+ { 1486, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1486 = MUL_FrST0
+ { 1487, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1487 = MWAIT
+ { 1488, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1488 = NEG16m
+ { 1489, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1489 = NEG16r
+ { 1490, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1490 = NEG32m
+ { 1491, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1491 = NEG32r
+ { 1492, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1492 = NEG64m
+ { 1493, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1493 = NEG64r
+ { 1494, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1494 = NEG8m
+ { 1495, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1495 = NEG8r
+ { 1496, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1496 = NOOP
+ { 1497, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1497 = NOOPL
+ { 1498, 5, 0, 0, "NOOPW", 0, 0|24|(1<<6)|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1498 = NOOPW
+ { 1499, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1499 = NOT16m
+ { 1500, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1500 = NOT16r
+ { 1501, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1501 = NOT32m
+ { 1502, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1502 = NOT32r
+ { 1503, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1503 = NOT64m
+ { 1504, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1504 = NOT64r
+ { 1505, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1505 = NOT8m
+ { 1506, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo92 }, // Inst #1506 = NOT8r
+ { 1507, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1507 = OR16i16
+ { 1508, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1508 = OR16mi
+ { 1509, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1509 = OR16mi8
+ { 1510, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1510 = OR16mr
+ { 1511, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1511 = OR16ri
+ { 1512, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1512 = OR16ri8
+ { 1513, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1513 = OR16rm
+ { 1514, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1514 = OR16rr
+ { 1515, 3, 1, 0, "OR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1515 = OR16rr_REV
+ { 1516, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1516 = OR32i32
+ { 1517, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1517 = OR32mi
+ { 1518, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1518 = OR32mi8
+ { 1519, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1519 = OR32mr
+ { 1520, 3, 1, 0, "OR32ri", 0, 0|17|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1520 = OR32ri
+ { 1521, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1521 = OR32ri8
+ { 1522, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1522 = OR32rm
+ { 1523, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1523 = OR32rr
+ { 1524, 3, 1, 0, "OR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1524 = OR32rr_REV
+ { 1525, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1525 = OR64i32
+ { 1526, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1526 = OR64mi32
+ { 1527, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1527 = OR64mi8
+ { 1528, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1528 = OR64mr
+ { 1529, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1529 = OR64ri32
+ { 1530, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1530 = OR64ri8
+ { 1531, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1531 = OR64rm
+ { 1532, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1532 = OR64rr
+ { 1533, 3, 1, 0, "OR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1533 = OR64rr_REV
+ { 1534, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1534 = OR8i8
+ { 1535, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1535 = OR8mi
+ { 1536, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1536 = OR8mr
+ { 1537, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1537 = OR8ri
+ { 1538, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1538 = OR8rm
+ { 1539, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1539 = OR8rr
+ { 1540, 3, 1, 0, "OR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1540 = OR8rr_REV
+ { 1541, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1541 = ORPDrm
+ { 1542, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1542 = ORPDrr
+ { 1543, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1543 = ORPSrm
+ { 1544, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1544 = ORPSrr
+ { 1545, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1545 = OUT16ir
+ { 1546, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList35, NULL, NULL, 0 }, // Inst #1546 = OUT16rr
+ { 1547, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1547 = OUT32ir
+ { 1548, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList36, NULL, NULL, 0 }, // Inst #1548 = OUT32rr
+ { 1549, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1549 = OUT8ir
+ { 1550, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList37, NULL, NULL, 0 }, // Inst #1550 = OUT8rr
+ { 1551, 0, 0, 0, "OUTSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(110<<24), NULL, NULL, NULL, 0 }, // Inst #1551 = OUTSB
+ { 1552, 0, 0, 0, "OUTSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1552 = OUTSD
+ { 1553, 0, 0, 0, "OUTSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1553 = OUTSW
+ { 1554, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1554 = PABSBrm128
+ { 1555, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1555 = PABSBrm64
+ { 1556, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1556 = PABSBrr128
+ { 1557, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1557 = PABSBrr64
+ { 1558, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1558 = PABSDrm128
+ { 1559, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1559 = PABSDrm64
+ { 1560, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1560 = PABSDrr128
+ { 1561, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1561 = PABSDrr64
+ { 1562, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1562 = PABSWrm128
+ { 1563, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1563 = PABSWrm64
+ { 1564, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1564 = PABSWrr128
+ { 1565, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1565 = PABSWrr64
+ { 1566, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1566 = PACKSSDWrm
+ { 1567, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1567 = PACKSSDWrr
+ { 1568, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1568 = PACKSSWBrm
+ { 1569, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1569 = PACKSSWBrr
+ { 1570, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1570 = PACKUSDWrm
+ { 1571, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1571 = PACKUSDWrr
+ { 1572, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1572 = PACKUSWBrm
+ { 1573, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1573 = PACKUSWBrr
+ { 1574, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1574 = PADDBrm
+ { 1575, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1575 = PADDBrr
+ { 1576, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1576 = PADDDrm
+ { 1577, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1577 = PADDDrr
+ { 1578, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1578 = PADDQrm
+ { 1579, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1579 = PADDQrr
+ { 1580, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1580 = PADDSBrm
+ { 1581, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1581 = PADDSBrr
+ { 1582, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1582 = PADDSWrm
+ { 1583, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1583 = PADDSWrr
+ { 1584, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1584 = PADDUSBrm
+ { 1585, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1585 = PADDUSBrr
+ { 1586, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1586 = PADDUSWrm
+ { 1587, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1587 = PADDUSWrr
+ { 1588, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1588 = PADDWrm
+ { 1589, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1589 = PADDWrr
+ { 1590, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1590 = PALIGNR128rm
+ { 1591, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1591 = PALIGNR128rr
+ { 1592, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1592 = PALIGNR64rm
+ { 1593, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo186 }, // Inst #1593 = PALIGNR64rr
+ { 1594, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1594 = PANDNrm
+ { 1595, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1595 = PANDNrr
+ { 1596, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1596 = PANDrm
+ { 1597, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1597 = PANDrr
+ { 1598, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1598 = PAVGBrm
+ { 1599, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1599 = PAVGBrr
+ { 1600, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1600 = PAVGWrm
+ { 1601, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1601 = PAVGWrr
+ { 1602, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1602 = PBLENDVBrm0
+ { 1603, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #1603 = PBLENDVBrr0
+ { 1604, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1604 = PBLENDWrmi
+ { 1605, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1605 = PBLENDWrri
+ { 1606, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1606 = PCMPEQBrm
+ { 1607, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1607 = PCMPEQBrr
+ { 1608, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1608 = PCMPEQDrm
+ { 1609, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1609 = PCMPEQDrr
+ { 1610, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1610 = PCMPEQQrm
+ { 1611, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1611 = PCMPEQQrr
+ { 1612, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1612 = PCMPEQWrm
+ { 1613, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1613 = PCMPEQWrr
+ { 1614, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1614 = PCMPESTRIArm
+ { 1615, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1615 = PCMPESTRIArr
+ { 1616, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1616 = PCMPESTRICrm
+ { 1617, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1617 = PCMPESTRICrr
+ { 1618, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1618 = PCMPESTRIOrm
+ { 1619, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1619 = PCMPESTRIOrr
+ { 1620, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1620 = PCMPESTRISrm
+ { 1621, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1621 = PCMPESTRISrr
+ { 1622, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1622 = PCMPESTRIZrm
+ { 1623, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1623 = PCMPESTRIZrr
+ { 1624, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1624 = PCMPESTRIrm
+ { 1625, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1625 = PCMPESTRIrr
+ { 1626, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1626 = PCMPESTRM128MEM
+ { 1627, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1627 = PCMPESTRM128REG
+ { 1628, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1628 = PCMPESTRM128rm
+ { 1629, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1629 = PCMPESTRM128rr
+ { 1630, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1630 = PCMPGTBrm
+ { 1631, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1631 = PCMPGTBrr
+ { 1632, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1632 = PCMPGTDrm
+ { 1633, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1633 = PCMPGTDrr
+ { 1634, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1634 = PCMPGTQrm
+ { 1635, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1635 = PCMPGTQrr
+ { 1636, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1636 = PCMPGTWrm
+ { 1637, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1637 = PCMPGTWrr
+ { 1638, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1638 = PCMPISTRIArm
+ { 1639, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1639 = PCMPISTRIArr
+ { 1640, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1640 = PCMPISTRICrm
+ { 1641, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1641 = PCMPISTRICrr
+ { 1642, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1642 = PCMPISTRIOrm
+ { 1643, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1643 = PCMPISTRIOrr
+ { 1644, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1644 = PCMPISTRISrm
+ { 1645, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1645 = PCMPISTRISrr
+ { 1646, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1646 = PCMPISTRIZrm
+ { 1647, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1647 = PCMPISTRIZrr
+ { 1648, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1648 = PCMPISTRIrm
+ { 1649, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1649 = PCMPISTRIrr
+ { 1650, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1650 = PCMPISTRM128MEM
+ { 1651, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1651 = PCMPISTRM128REG
+ { 1652, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1652 = PCMPISTRM128rm
+ { 1653, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1653 = PCMPISTRM128rr
+ { 1654, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1654 = PEXTRBmr
+ { 1655, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1655 = PEXTRBrr
+ { 1656, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1656 = PEXTRDmr
+ { 1657, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1657 = PEXTRDrr
+ { 1658, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1658 = PEXTRQmr
+ { 1659, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo190 }, // Inst #1659 = PEXTRQrr
+ { 1660, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1660 = PEXTRWmr
+ { 1661, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1661 = PEXTRWri
+ { 1662, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1662 = PHADDDrm128
+ { 1663, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1663 = PHADDDrm64
+ { 1664, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1664 = PHADDDrr128
+ { 1665, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1665 = PHADDDrr64
+ { 1666, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1666 = PHADDSWrm128
+ { 1667, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1667 = PHADDSWrm64
+ { 1668, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1668 = PHADDSWrr128
+ { 1669, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1669 = PHADDSWrr64
+ { 1670, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1670 = PHADDWrm128
+ { 1671, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1671 = PHADDWrm64
+ { 1672, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1672 = PHADDWrr128
+ { 1673, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1673 = PHADDWrr64
+ { 1674, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1674 = PHMINPOSUWrm128
+ { 1675, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1675 = PHMINPOSUWrr128
+ { 1676, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1676 = PHSUBDrm128
+ { 1677, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1677 = PHSUBDrm64
+ { 1678, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1678 = PHSUBDrr128
+ { 1679, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1679 = PHSUBDrr64
+ { 1680, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1680 = PHSUBSWrm128
+ { 1681, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1681 = PHSUBSWrm64
+ { 1682, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1682 = PHSUBSWrr128
+ { 1683, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1683 = PHSUBSWrr64
+ { 1684, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1684 = PHSUBWrm128
+ { 1685, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1685 = PHSUBWrm64
+ { 1686, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1686 = PHSUBWrr128
+ { 1687, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1687 = PHSUBWrr64
+ { 1688, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1688 = PINSRBrm
+ { 1689, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1689 = PINSRBrr
+ { 1690, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1690 = PINSRDrm
+ { 1691, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1691 = PINSRDrr
+ { 1692, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1692 = PINSRQrm
+ { 1693, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo192 }, // Inst #1693 = PINSRQrr
+ { 1694, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1694 = PINSRWrmi
+ { 1695, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1695 = PINSRWrri
+ { 1696, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1696 = PMADDUBSWrm128
+ { 1697, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1697 = PMADDUBSWrm64
+ { 1698, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1698 = PMADDUBSWrr128
+ { 1699, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1699 = PMADDUBSWrr64
+ { 1700, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1700 = PMADDWDrm
+ { 1701, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1701 = PMADDWDrr
+ { 1702, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1702 = PMAXSBrm
+ { 1703, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1703 = PMAXSBrr
+ { 1704, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1704 = PMAXSDrm
+ { 1705, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1705 = PMAXSDrr
+ { 1706, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1706 = PMAXSWrm
+ { 1707, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1707 = PMAXSWrr
+ { 1708, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1708 = PMAXUBrm
+ { 1709, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1709 = PMAXUBrr
+ { 1710, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1710 = PMAXUDrm
+ { 1711, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1711 = PMAXUDrr
+ { 1712, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1712 = PMAXUWrm
+ { 1713, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1713 = PMAXUWrr
+ { 1714, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1714 = PMINSBrm
+ { 1715, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1715 = PMINSBrr
+ { 1716, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1716 = PMINSDrm
+ { 1717, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1717 = PMINSDrr
+ { 1718, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1718 = PMINSWrm
+ { 1719, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1719 = PMINSWrr
+ { 1720, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1720 = PMINUBrm
+ { 1721, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1721 = PMINUBrr
+ { 1722, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1722 = PMINUDrm
+ { 1723, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1723 = PMINUDrr
+ { 1724, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1724 = PMINUWrm
+ { 1725, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1725 = PMINUWrr
+ { 1726, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1726 = PMOVMSKBrr
+ { 1727, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1727 = PMOVSXBDrm
+ { 1728, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1728 = PMOVSXBDrr
+ { 1729, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1729 = PMOVSXBQrm
+ { 1730, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1730 = PMOVSXBQrr
+ { 1731, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1731 = PMOVSXBWrm
+ { 1732, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1732 = PMOVSXBWrr
+ { 1733, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1733 = PMOVSXDQrm
+ { 1734, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1734 = PMOVSXDQrr
+ { 1735, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1735 = PMOVSXWDrm
+ { 1736, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1736 = PMOVSXWDrr
+ { 1737, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1737 = PMOVSXWQrm
+ { 1738, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1738 = PMOVSXWQrr
+ { 1739, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1739 = PMOVZXBDrm
+ { 1740, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1740 = PMOVZXBDrr
+ { 1741, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1741 = PMOVZXBQrm
+ { 1742, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1742 = PMOVZXBQrr
+ { 1743, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1743 = PMOVZXBWrm
+ { 1744, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1744 = PMOVZXBWrr
+ { 1745, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1745 = PMOVZXDQrm
+ { 1746, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1746 = PMOVZXDQrr
+ { 1747, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1747 = PMOVZXWDrm
+ { 1748, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1748 = PMOVZXWDrr
+ { 1749, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1749 = PMOVZXWQrm
+ { 1750, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1750 = PMOVZXWQrr
+ { 1751, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1751 = PMULDQrm
+ { 1752, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1752 = PMULDQrr
+ { 1753, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1753 = PMULHRSWrm128
+ { 1754, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1754 = PMULHRSWrm64
+ { 1755, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1755 = PMULHRSWrr128
+ { 1756, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1756 = PMULHRSWrr64
+ { 1757, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1757 = PMULHUWrm
+ { 1758, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1758 = PMULHUWrr
+ { 1759, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1759 = PMULHWrm
+ { 1760, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1760 = PMULHWrr
+ { 1761, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1761 = PMULLDrm
+ { 1762, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1762 = PMULLDrm_int
+ { 1763, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1763 = PMULLDrr
+ { 1764, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1764 = PMULLDrr_int
+ { 1765, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1765 = PMULLWrm
+ { 1766, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1766 = PMULLWrr
+ { 1767, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1767 = PMULUDQrm
+ { 1768, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1768 = PMULUDQrr
+ { 1769, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1769 = POP16r
+ { 1770, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1770 = POP16rmm
+ { 1771, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1771 = POP16rmr
+ { 1772, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1772 = POP32r
+ { 1773, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1773 = POP32rmm
+ { 1774, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1774 = POP32rmr
+ { 1775, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1775 = POP64r
+ { 1776, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1776 = POP64rmm
+ { 1777, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1777 = POP64rmr
+ { 1778, 6, 1, 0, "POPCNT16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1778 = POPCNT16rm
+ { 1779, 2, 1, 0, "POPCNT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1779 = POPCNT16rr
+ { 1780, 6, 1, 0, "POPCNT32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1780 = POPCNT32rm
+ { 1781, 2, 1, 0, "POPCNT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1781 = POPCNT32rr
+ { 1782, 6, 1, 0, "POPCNT64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1782 = POPCNT64rm
+ { 1783, 2, 1, 0, "POPCNT64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1783 = POPCNT64rr
+ { 1784, 0, 0, 0, "POPF", 0|(1<<TID::MayLoad), 0|1|(1<<6)|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1784 = POPF
+ { 1785, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1785 = POPFD
+ { 1786, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1786 = POPFQ
+ { 1787, 0, 0, 0, "POPFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1787 = POPFS16
+ { 1788, 0, 0, 0, "POPFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1788 = POPFS32
+ { 1789, 0, 0, 0, "POPFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1789 = POPFS64
+ { 1790, 0, 0, 0, "POPGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1790 = POPGS16
+ { 1791, 0, 0, 0, "POPGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1791 = POPGS32
+ { 1792, 0, 0, 0, "POPGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1792 = POPGS64
+ { 1793, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1793 = PORrm
+ { 1794, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1794 = PORrr
+ { 1795, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1795 = PREFETCHNTA
+ { 1796, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1796 = PREFETCHT0
+ { 1797, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1797 = PREFETCHT1
+ { 1798, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1798 = PREFETCHT2
+ { 1799, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1799 = PSADBWrm
+ { 1800, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1800 = PSADBWrr
+ { 1801, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1801 = PSHUFBrm128
+ { 1802, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo136 }, // Inst #1802 = PSHUFBrm64
+ { 1803, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo25 }, // Inst #1803 = PSHUFBrr128
+ { 1804, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo137 }, // Inst #1804 = PSHUFBrr64
+ { 1805, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1805 = PSHUFDmi
+ { 1806, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1806 = PSHUFDri
+ { 1807, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1807 = PSHUFHWmi
+ { 1808, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1808 = PSHUFHWri
+ { 1809, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1809 = PSHUFLWmi
+ { 1810, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1810 = PSHUFLWri
+ { 1811, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1811 = PSIGNBrm128
+ { 1812, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1812 = PSIGNBrm64
+ { 1813, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1813 = PSIGNBrr128
+ { 1814, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1814 = PSIGNBrr64
+ { 1815, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1815 = PSIGNDrm128
+ { 1816, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1816 = PSIGNDrm64
+ { 1817, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1817 = PSIGNDrr128
+ { 1818, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1818 = PSIGNDrr64
+ { 1819, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1819 = PSIGNWrm128
+ { 1820, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1820 = PSIGNWrm64
+ { 1821, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1821 = PSIGNWrr128
+ { 1822, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1822 = PSIGNWrr64
+ { 1823, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1823 = PSLLDQri
+ { 1824, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1824 = PSLLDri
+ { 1825, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1825 = PSLLDrm
+ { 1826, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1826 = PSLLDrr
+ { 1827, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1827 = PSLLQri
+ { 1828, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1828 = PSLLQrm
+ { 1829, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1829 = PSLLQrr
+ { 1830, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1830 = PSLLWri
+ { 1831, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1831 = PSLLWrm
+ { 1832, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1832 = PSLLWrr
+ { 1833, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1833 = PSRADri
+ { 1834, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1834 = PSRADrm
+ { 1835, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1835 = PSRADrr
+ { 1836, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1836 = PSRAWri
+ { 1837, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1837 = PSRAWrm
+ { 1838, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1838 = PSRAWrr
+ { 1839, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1839 = PSRLDQri
+ { 1840, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1840 = PSRLDri
+ { 1841, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1841 = PSRLDrm
+ { 1842, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1842 = PSRLDrr
+ { 1843, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1843 = PSRLQri
+ { 1844, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1844 = PSRLQrm
+ { 1845, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1845 = PSRLQrr
+ { 1846, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1846 = PSRLWri
+ { 1847, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1847 = PSRLWrm
+ { 1848, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1848 = PSRLWrr
+ { 1849, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1849 = PSUBBrm
+ { 1850, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1850 = PSUBBrr
+ { 1851, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1851 = PSUBDrm
+ { 1852, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1852 = PSUBDrr
+ { 1853, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1853 = PSUBQrm
+ { 1854, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1854 = PSUBQrr
+ { 1855, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1855 = PSUBSBrm
+ { 1856, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1856 = PSUBSBrr
+ { 1857, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1857 = PSUBSWrm
+ { 1858, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1858 = PSUBSWrr
+ { 1859, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1859 = PSUBUSBrm
+ { 1860, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1860 = PSUBUSBrr
+ { 1861, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1861 = PSUBUSWrm
+ { 1862, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1862 = PSUBUSWrr
+ { 1863, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1863 = PSUBWrm
+ { 1864, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1864 = PSUBWrr
+ { 1865, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1865 = PTESTrm
+ { 1866, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #1866 = PTESTrr
+ { 1867, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1867 = PUNPCKHBWrm
+ { 1868, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1868 = PUNPCKHBWrr
+ { 1869, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1869 = PUNPCKHDQrm
+ { 1870, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1870 = PUNPCKHDQrr
+ { 1871, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1871 = PUNPCKHQDQrm
+ { 1872, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1872 = PUNPCKHQDQrr
+ { 1873, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1873 = PUNPCKHWDrm
+ { 1874, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1874 = PUNPCKHWDrr
+ { 1875, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1875 = PUNPCKLBWrm
+ { 1876, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1876 = PUNPCKLBWrr
+ { 1877, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1877 = PUNPCKLDQrm
+ { 1878, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1878 = PUNPCKLDQrr
+ { 1879, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1879 = PUNPCKLQDQrm
+ { 1880, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1880 = PUNPCKLQDQrr
+ { 1881, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1881 = PUNPCKLWDrm
+ { 1882, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1882 = PUNPCKLWDrr
+ { 1883, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1883 = PUSH16r
+ { 1884, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1884 = PUSH16rmm
+ { 1885, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1885 = PUSH16rmr
+ { 1886, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1886 = PUSH32i16
+ { 1887, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1887 = PUSH32i32
+ { 1888, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1888 = PUSH32i8
+ { 1889, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1889 = PUSH32r
+ { 1890, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1890 = PUSH32rmm
+ { 1891, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1891 = PUSH32rmr
+ { 1892, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1892 = PUSH64i16
+ { 1893, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1893 = PUSH64i32
+ { 1894, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1894 = PUSH64i8
+ { 1895, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1895 = PUSH64r
+ { 1896, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1896 = PUSH64rmm
+ { 1897, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1897 = PUSH64rmr
+ { 1898, 0, 0, 0, "PUSHF", 0|(1<<TID::MayStore), 0|1|(1<<6)|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1898 = PUSHF
+ { 1899, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1899 = PUSHFD
+ { 1900, 0, 0, 0, "PUSHFQ64", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1900 = PUSHFQ64
+ { 1901, 0, 0, 0, "PUSHFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1901 = PUSHFS16
+ { 1902, 0, 0, 0, "PUSHFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1902 = PUSHFS32
+ { 1903, 0, 0, 0, "PUSHFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1903 = PUSHFS64
+ { 1904, 0, 0, 0, "PUSHGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1904 = PUSHGS16
+ { 1905, 0, 0, 0, "PUSHGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1905 = PUSHGS32
+ { 1906, 0, 0, 0, "PUSHGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1906 = PUSHGS64
+ { 1907, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1907 = PXORrm
+ { 1908, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1908 = PXORrr
+ { 1909, 10, 1, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1909 = RCL16m1
+ { 1910, 10, 1, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1910 = RCL16mCL
+ { 1911, 11, 1, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1911 = RCL16mi
+ { 1912, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1912 = RCL16r1
+ { 1913, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1913 = RCL16rCL
+ { 1914, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1914 = RCL16ri
+ { 1915, 10, 1, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1915 = RCL32m1
+ { 1916, 10, 1, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1916 = RCL32mCL
+ { 1917, 11, 1, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1917 = RCL32mi
+ { 1918, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1918 = RCL32r1
+ { 1919, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1919 = RCL32rCL
+ { 1920, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1920 = RCL32ri
+ { 1921, 10, 1, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1921 = RCL64m1
+ { 1922, 10, 1, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1922 = RCL64mCL
+ { 1923, 11, 1, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1923 = RCL64mi
+ { 1924, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1924 = RCL64r1
+ { 1925, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1925 = RCL64rCL
+ { 1926, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1926 = RCL64ri
+ { 1927, 10, 1, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1927 = RCL8m1
+ { 1928, 10, 1, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1928 = RCL8mCL
+ { 1929, 11, 1, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1929 = RCL8mi
+ { 1930, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1930 = RCL8r1
+ { 1931, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1931 = RCL8rCL
+ { 1932, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1932 = RCL8ri
+ { 1933, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1933 = RCPPSm
+ { 1934, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1934 = RCPPSm_Int
+ { 1935, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1935 = RCPPSr
+ { 1936, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1936 = RCPPSr_Int
+ { 1937, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1937 = RCPSSm
+ { 1938, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1938 = RCPSSm_Int
+ { 1939, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1939 = RCPSSr
+ { 1940, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1940 = RCPSSr_Int
+ { 1941, 10, 1, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1941 = RCR16m1
+ { 1942, 10, 1, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1942 = RCR16mCL
+ { 1943, 11, 1, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1943 = RCR16mi
+ { 1944, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1944 = RCR16r1
+ { 1945, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1945 = RCR16rCL
+ { 1946, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1946 = RCR16ri
+ { 1947, 10, 1, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1947 = RCR32m1
+ { 1948, 10, 1, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1948 = RCR32mCL
+ { 1949, 11, 1, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1949 = RCR32mi
+ { 1950, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1950 = RCR32r1
+ { 1951, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1951 = RCR32rCL
+ { 1952, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1952 = RCR32ri
+ { 1953, 10, 1, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1953 = RCR64m1
+ { 1954, 10, 1, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1954 = RCR64mCL
+ { 1955, 11, 1, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1955 = RCR64mi
+ { 1956, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1956 = RCR64r1
+ { 1957, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1957 = RCR64rCL
+ { 1958, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1958 = RCR64ri
+ { 1959, 10, 1, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1959 = RCR8m1
+ { 1960, 10, 1, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1960 = RCR8mCL
+ { 1961, 11, 1, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1961 = RCR8mi
+ { 1962, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1962 = RCR8r1
+ { 1963, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1963 = RCR8rCL
+ { 1964, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1964 = RCR8ri
+ { 1965, 0, 0, 0, "RDMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(50<<24), NULL, NULL, NULL, 0 }, // Inst #1965 = RDMSR
+ { 1966, 0, 0, 0, "RDPMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(51<<24), NULL, NULL, NULL, 0 }, // Inst #1966 = RDPMC
+ { 1967, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList16, NULL, 0 }, // Inst #1967 = RDTSC
+ { 1968, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1968 = REP_MOVSB
+ { 1969, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1969 = REP_MOVSD
+ { 1970, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList42, ImplicitList42, NULL, 0 }, // Inst #1970 = REP_MOVSQ
+ { 1971, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1971 = REP_MOVSW
+ { 1972, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList43, ImplicitList44, NULL, 0 }, // Inst #1972 = REP_STOSB
+ { 1973, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList45, ImplicitList44, NULL, 0 }, // Inst #1973 = REP_STOSD
+ { 1974, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList46, ImplicitList47, NULL, 0 }, // Inst #1974 = REP_STOSQ
+ { 1975, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList48, ImplicitList44, NULL, 0 }, // Inst #1975 = REP_STOSW
+ { 1976, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1976 = RET
+ { 1977, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(2<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1977 = RETI
+ { 1978, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1978 = ROL16m1
+ { 1979, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1979 = ROL16mCL
+ { 1980, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1980 = ROL16mi
+ { 1981, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1981 = ROL16r1
+ { 1982, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1982 = ROL16rCL
+ { 1983, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1983 = ROL16ri
+ { 1984, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1984 = ROL32m1
+ { 1985, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1985 = ROL32mCL
+ { 1986, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1986 = ROL32mi
+ { 1987, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1987 = ROL32r1
+ { 1988, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1988 = ROL32rCL
+ { 1989, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1989 = ROL32ri
+ { 1990, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1990 = ROL64m1
+ { 1991, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1991 = ROL64mCL
+ { 1992, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1992 = ROL64mi
+ { 1993, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1993 = ROL64r1
+ { 1994, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1994 = ROL64rCL
+ { 1995, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1995 = ROL64ri
+ { 1996, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1996 = ROL8m1
+ { 1997, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1997 = ROL8mCL
+ { 1998, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1998 = ROL8mi
+ { 1999, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1999 = ROL8r1
+ { 2000, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2000 = ROL8rCL
+ { 2001, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2001 = ROL8ri
+ { 2002, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2002 = ROR16m1
+ { 2003, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2003 = ROR16mCL
+ { 2004, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2004 = ROR16mi
+ { 2005, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2005 = ROR16r1
+ { 2006, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2006 = ROR16rCL
+ { 2007, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2007 = ROR16ri
+ { 2008, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2008 = ROR32m1
+ { 2009, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2009 = ROR32mCL
+ { 2010, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2010 = ROR32mi
+ { 2011, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2011 = ROR32r1
+ { 2012, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2012 = ROR32rCL
+ { 2013, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2013 = ROR32ri
+ { 2014, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2014 = ROR64m1
+ { 2015, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2015 = ROR64mCL
+ { 2016, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2016 = ROR64mi
+ { 2017, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2017 = ROR64r1
+ { 2018, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2018 = ROR64rCL
+ { 2019, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2019 = ROR64ri
+ { 2020, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2020 = ROR8m1
+ { 2021, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2021 = ROR8mCL
+ { 2022, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2022 = ROR8mi
+ { 2023, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2023 = ROR8r1
+ { 2024, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2024 = ROR8rCL
+ { 2025, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2025 = ROR8ri
+ { 2026, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2026 = ROUNDPDm_Int
+ { 2027, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2027 = ROUNDPDr_Int
+ { 2028, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2028 = ROUNDPSm_Int
+ { 2029, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2029 = ROUNDPSr_Int
+ { 2030, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2030 = ROUNDSDm_Int
+ { 2031, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2031 = ROUNDSDr_Int
+ { 2032, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2032 = ROUNDSSm_Int
+ { 2033, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2033 = ROUNDSSr_Int
+ { 2034, 0, 0, 0, "RSM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(170<<24), NULL, NULL, NULL, 0 }, // Inst #2034 = RSM
+ { 2035, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2035 = RSQRTPSm
+ { 2036, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2036 = RSQRTPSm_Int
+ { 2037, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2037 = RSQRTPSr
+ { 2038, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2038 = RSQRTPSr_Int
+ { 2039, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2039 = RSQRTSSm
+ { 2040, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2040 = RSQRTSSm_Int
+ { 2041, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2041 = RSQRTSSr
+ { 2042, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2042 = RSQRTSSr_Int
+ { 2043, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList26, ImplicitList1, Barriers1, 0 }, // Inst #2043 = SAHF
+ { 2044, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2044 = SAR16m1
+ { 2045, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2045 = SAR16mCL
+ { 2046, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2046 = SAR16mi
+ { 2047, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2047 = SAR16r1
+ { 2048, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2048 = SAR16rCL
+ { 2049, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2049 = SAR16ri
+ { 2050, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2050 = SAR32m1
+ { 2051, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2051 = SAR32mCL
+ { 2052, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2052 = SAR32mi
+ { 2053, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2053 = SAR32r1
+ { 2054, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2054 = SAR32rCL
+ { 2055, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2055 = SAR32ri
+ { 2056, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2056 = SAR64m1
+ { 2057, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2057 = SAR64mCL
+ { 2058, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2058 = SAR64mi
+ { 2059, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2059 = SAR64r1
+ { 2060, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2060 = SAR64rCL
+ { 2061, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2061 = SAR64ri
+ { 2062, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2062 = SAR8m1
+ { 2063, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2063 = SAR8mCL
+ { 2064, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2064 = SAR8mi
+ { 2065, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2065 = SAR8r1
+ { 2066, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2066 = SAR8rCL
+ { 2067, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2067 = SAR8ri
+ { 2068, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2068 = SBB16i16
+ { 2069, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2069 = SBB16mi
+ { 2070, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2070 = SBB16mi8
+ { 2071, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2071 = SBB16mr
+ { 2072, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2072 = SBB16ri
+ { 2073, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2073 = SBB16ri8
+ { 2074, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2074 = SBB16rm
+ { 2075, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2075 = SBB16rr
+ { 2076, 3, 1, 0, "SBB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2076 = SBB16rr_REV
+ { 2077, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2077 = SBB32i32
+ { 2078, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2078 = SBB32mi
+ { 2079, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2079 = SBB32mi8
+ { 2080, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2080 = SBB32mr
+ { 2081, 3, 1, 0, "SBB32ri", 0, 0|19|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2081 = SBB32ri
+ { 2082, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2082 = SBB32ri8
+ { 2083, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2083 = SBB32rm
+ { 2084, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2084 = SBB32rr
+ { 2085, 3, 1, 0, "SBB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2085 = SBB32rr_REV
+ { 2086, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2086 = SBB64i32
+ { 2087, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2087 = SBB64mi32
+ { 2088, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2088 = SBB64mi8
+ { 2089, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2089 = SBB64mr
+ { 2090, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2090 = SBB64ri32
+ { 2091, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2091 = SBB64ri8
+ { 2092, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2092 = SBB64rm
+ { 2093, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2093 = SBB64rr
+ { 2094, 3, 1, 0, "SBB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2094 = SBB64rr_REV
+ { 2095, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2095 = SBB8i8
+ { 2096, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2096 = SBB8mi
+ { 2097, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2097 = SBB8mr
+ { 2098, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2098 = SBB8ri
+ { 2099, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2099 = SBB8rm
+ { 2100, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2100 = SBB8rr
+ { 2101, 3, 1, 0, "SBB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2101 = SBB8rr_REV
+ { 2102, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2102 = SCAS16
+ { 2103, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2103 = SCAS32
+ { 2104, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2104 = SCAS64
+ { 2105, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2105 = SCAS8
+ { 2106, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2106 = SETAEm
+ { 2107, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2107 = SETAEr
+ { 2108, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2108 = SETAm
+ { 2109, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2109 = SETAr
+ { 2110, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2110 = SETBEm
+ { 2111, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2111 = SETBEr
+ { 2112, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #2112 = SETB_C16r
+ { 2113, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #2113 = SETB_C32r
+ { 2114, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #2114 = SETB_C64r
+ { 2115, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #2115 = SETB_C8r
+ { 2116, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2116 = SETBm
+ { 2117, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2117 = SETBr
+ { 2118, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2118 = SETEm
+ { 2119, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2119 = SETEr
+ { 2120, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2120 = SETGEm
+ { 2121, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2121 = SETGEr
+ { 2122, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2122 = SETGm
+ { 2123, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2123 = SETGr
+ { 2124, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2124 = SETLEm
+ { 2125, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2125 = SETLEr
+ { 2126, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2126 = SETLm
+ { 2127, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2127 = SETLr
+ { 2128, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2128 = SETNEm
+ { 2129, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2129 = SETNEr
+ { 2130, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2130 = SETNOm
+ { 2131, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2131 = SETNOr
+ { 2132, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2132 = SETNPm
+ { 2133, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2133 = SETNPr
+ { 2134, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2134 = SETNSm
+ { 2135, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2135 = SETNSr
+ { 2136, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2136 = SETOm
+ { 2137, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2137 = SETOr
+ { 2138, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2138 = SETPm
+ { 2139, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2139 = SETPr
+ { 2140, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2140 = SETSm
+ { 2141, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2141 = SETSr
+ { 2142, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2142 = SFENCE
+ { 2143, 5, 1, 0, "SGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2143 = SGDTm
+ { 2144, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2144 = SHL16m1
+ { 2145, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2145 = SHL16mCL
+ { 2146, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2146 = SHL16mi
+ { 2147, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2147 = SHL16r1
+ { 2148, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2148 = SHL16rCL
+ { 2149, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2149 = SHL16ri
+ { 2150, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2150 = SHL32m1
+ { 2151, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2151 = SHL32mCL
+ { 2152, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2152 = SHL32mi
+ { 2153, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2153 = SHL32r1
+ { 2154, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2154 = SHL32rCL
+ { 2155, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2155 = SHL32ri
+ { 2156, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2156 = SHL64m1
+ { 2157, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2157 = SHL64mCL
+ { 2158, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2158 = SHL64mi
+ { 2159, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2159 = SHL64r1
+ { 2160, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2160 = SHL64rCL
+ { 2161, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2161 = SHL64ri
+ { 2162, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2162 = SHL8m1
+ { 2163, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2163 = SHL8mCL
+ { 2164, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2164 = SHL8mi
+ { 2165, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2165 = SHL8r1
+ { 2166, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2166 = SHL8rCL
+ { 2167, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2167 = SHL8ri
+ { 2168, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2168 = SHLD16mrCL
+ { 2169, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2169 = SHLD16mri8
+ { 2170, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2170 = SHLD16rrCL
+ { 2171, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2171 = SHLD16rri8
+ { 2172, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2172 = SHLD32mrCL
+ { 2173, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2173 = SHLD32mri8
+ { 2174, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2174 = SHLD32rrCL
+ { 2175, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2175 = SHLD32rri8
+ { 2176, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2176 = SHLD64mrCL
+ { 2177, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo200 }, // Inst #2177 = SHLD64mri8
+ { 2178, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2178 = SHLD64rrCL
+ { 2179, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo201 }, // Inst #2179 = SHLD64rri8
+ { 2180, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2180 = SHR16m1
+ { 2181, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2181 = SHR16mCL
+ { 2182, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2182 = SHR16mi
+ { 2183, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2183 = SHR16r1
+ { 2184, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2184 = SHR16rCL
+ { 2185, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2185 = SHR16ri
+ { 2186, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2186 = SHR32m1
+ { 2187, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2187 = SHR32mCL
+ { 2188, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2188 = SHR32mi
+ { 2189, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2189 = SHR32r1
+ { 2190, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2190 = SHR32rCL
+ { 2191, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2191 = SHR32ri
+ { 2192, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2192 = SHR64m1
+ { 2193, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2193 = SHR64mCL
+ { 2194, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2194 = SHR64mi
+ { 2195, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2195 = SHR64r1
+ { 2196, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2196 = SHR64rCL
+ { 2197, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2197 = SHR64ri
+ { 2198, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2198 = SHR8m1
+ { 2199, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2199 = SHR8mCL
+ { 2200, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2200 = SHR8mi
+ { 2201, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2201 = SHR8r1
+ { 2202, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2202 = SHR8rCL
+ { 2203, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2203 = SHR8ri
+ { 2204, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2204 = SHRD16mrCL
+ { 2205, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2205 = SHRD16mri8
+ { 2206, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2206 = SHRD16rrCL
+ { 2207, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2207 = SHRD16rri8
+ { 2208, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2208 = SHRD32mrCL
+ { 2209, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2209 = SHRD32mri8
+ { 2210, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2210 = SHRD32rrCL
+ { 2211, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2211 = SHRD32rri8
+ { 2212, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2212 = SHRD64mrCL
+ { 2213, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo200 }, // Inst #2213 = SHRD64mri8
+ { 2214, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2214 = SHRD64rrCL
+ { 2215, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo201 }, // Inst #2215 = SHRD64rri8
+ { 2216, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2216 = SHUFPDrmi
+ { 2217, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2217 = SHUFPDrri
+ { 2218, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2218 = SHUFPSrmi
+ { 2219, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2219 = SHUFPSrri
+ { 2220, 5, 1, 0, "SIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2220 = SIDTm
+ { 2221, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2221 = SIN_F
+ { 2222, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2222 = SIN_Fp32
+ { 2223, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2223 = SIN_Fp64
+ { 2224, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2224 = SIN_Fp80
+ { 2225, 5, 1, 0, "SLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2225 = SLDT16m
+ { 2226, 1, 1, 0, "SLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2226 = SLDT16r
+ { 2227, 5, 1, 0, "SLDT64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo30 }, // Inst #2227 = SLDT64m
+ { 2228, 1, 1, 0, "SLDT64r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo58 }, // Inst #2228 = SLDT64r
+ { 2229, 5, 1, 0, "SMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2229 = SMSW16m
+ { 2230, 1, 1, 0, "SMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2230 = SMSW16r
+ { 2231, 1, 1, 0, "SMSW32r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2231 = SMSW32r
+ { 2232, 1, 1, 0, "SMSW64r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<12)|(1<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2232 = SMSW64r
+ { 2233, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2233 = SQRTPDm
+ { 2234, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2234 = SQRTPDm_Int
+ { 2235, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2235 = SQRTPDr
+ { 2236, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2236 = SQRTPDr_Int
+ { 2237, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2237 = SQRTPSm
+ { 2238, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2238 = SQRTPSm_Int
+ { 2239, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2239 = SQRTPSr
+ { 2240, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2240 = SQRTPSr_Int
+ { 2241, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #2241 = SQRTSDm
+ { 2242, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2242 = SQRTSDm_Int
+ { 2243, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2243 = SQRTSDr
+ { 2244, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2244 = SQRTSDr_Int
+ { 2245, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2245 = SQRTSSm
+ { 2246, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2246 = SQRTSSm_Int
+ { 2247, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2247 = SQRTSSr
+ { 2248, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2248 = SQRTSSr_Int
+ { 2249, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2249 = SQRT_F
+ { 2250, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2250 = SQRT_Fp32
+ { 2251, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2251 = SQRT_Fp64
+ { 2252, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2252 = SQRT_Fp80
+ { 2253, 0, 0, 0, "STC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(249<<24), NULL, NULL, NULL, 0 }, // Inst #2253 = STC
+ { 2254, 0, 0, 0, "STD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(253<<24), NULL, NULL, NULL, 0 }, // Inst #2254 = STD
+ { 2255, 0, 0, 0, "STI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(251<<24), NULL, NULL, NULL, 0 }, // Inst #2255 = STI
+ { 2256, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2256 = STMXCSR
+ { 2257, 5, 1, 0, "STRm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2257 = STRm
+ { 2258, 1, 1, 0, "STRr", 0|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2258 = STRr
+ { 2259, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2259 = ST_F32m
+ { 2260, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2260 = ST_F64m
+ { 2261, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2261 = ST_FP32m
+ { 2262, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2262 = ST_FP64m
+ { 2263, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2263 = ST_FP80m
+ { 2264, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2264 = ST_FPrr
+ { 2265, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2265 = ST_Fp32m
+ { 2266, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2266 = ST_Fp64m
+ { 2267, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2267 = ST_Fp64m32
+ { 2268, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2268 = ST_Fp80m32
+ { 2269, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2269 = ST_Fp80m64
+ { 2270, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2270 = ST_FpP32m
+ { 2271, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2271 = ST_FpP64m
+ { 2272, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2272 = ST_FpP64m32
+ { 2273, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2273 = ST_FpP80m
+ { 2274, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2274 = ST_FpP80m32
+ { 2275, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2275 = ST_FpP80m64
+ { 2276, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2276 = ST_Frr
+ { 2277, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2277 = SUB16i16
+ { 2278, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2278 = SUB16mi
+ { 2279, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2279 = SUB16mi8
+ { 2280, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2280 = SUB16mr
+ { 2281, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2281 = SUB16ri
+ { 2282, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2282 = SUB16ri8
+ { 2283, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2283 = SUB16rm
+ { 2284, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2284 = SUB16rr
+ { 2285, 3, 1, 0, "SUB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2285 = SUB16rr_REV
+ { 2286, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2286 = SUB32i32
+ { 2287, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2287 = SUB32mi
+ { 2288, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2288 = SUB32mi8
+ { 2289, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2289 = SUB32mr
+ { 2290, 3, 1, 0, "SUB32ri", 0, 0|21|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2290 = SUB32ri
+ { 2291, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2291 = SUB32ri8
+ { 2292, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2292 = SUB32rm
+ { 2293, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2293 = SUB32rr
+ { 2294, 3, 1, 0, "SUB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2294 = SUB32rr_REV
+ { 2295, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2295 = SUB64i32
+ { 2296, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2296 = SUB64mi32
+ { 2297, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2297 = SUB64mi8
+ { 2298, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2298 = SUB64mr
+ { 2299, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2299 = SUB64ri32
+ { 2300, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2300 = SUB64ri8
+ { 2301, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2301 = SUB64rm
+ { 2302, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2302 = SUB64rr
+ { 2303, 3, 1, 0, "SUB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2303 = SUB64rr_REV
+ { 2304, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2304 = SUB8i8
+ { 2305, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2305 = SUB8mi
+ { 2306, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2306 = SUB8mr
+ { 2307, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2307 = SUB8ri
+ { 2308, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2308 = SUB8rm
+ { 2309, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2309 = SUB8rr
+ { 2310, 3, 1, 0, "SUB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2310 = SUB8rr_REV
+ { 2311, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2311 = SUBPDrm
+ { 2312, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2312 = SUBPDrr
+ { 2313, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2313 = SUBPSrm
+ { 2314, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2314 = SUBPSrr
+ { 2315, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2315 = SUBR_F32m
+ { 2316, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2316 = SUBR_F64m
+ { 2317, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2317 = SUBR_FI16m
+ { 2318, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2318 = SUBR_FI32m
+ { 2319, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2319 = SUBR_FPrST0
+ { 2320, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2320 = SUBR_FST0r
+ { 2321, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2321 = SUBR_Fp32m
+ { 2322, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2322 = SUBR_Fp64m
+ { 2323, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2323 = SUBR_Fp64m32
+ { 2324, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2324 = SUBR_Fp80m32
+ { 2325, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2325 = SUBR_Fp80m64
+ { 2326, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2326 = SUBR_FpI16m32
+ { 2327, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2327 = SUBR_FpI16m64
+ { 2328, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2328 = SUBR_FpI16m80
+ { 2329, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2329 = SUBR_FpI32m32
+ { 2330, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2330 = SUBR_FpI32m64
+ { 2331, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2331 = SUBR_FpI32m80
+ { 2332, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2332 = SUBR_FrST0
+ { 2333, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2333 = SUBSDrm
+ { 2334, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2334 = SUBSDrm_Int
+ { 2335, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2335 = SUBSDrr
+ { 2336, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2336 = SUBSDrr_Int
+ { 2337, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2337 = SUBSSrm
+ { 2338, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2338 = SUBSSrm_Int
+ { 2339, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2339 = SUBSSrr
+ { 2340, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2340 = SUBSSrr_Int
+ { 2341, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2341 = SUB_F32m
+ { 2342, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2342 = SUB_F64m
+ { 2343, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2343 = SUB_FI16m
+ { 2344, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2344 = SUB_FI32m
+ { 2345, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2345 = SUB_FPrST0
+ { 2346, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2346 = SUB_FST0r
+ { 2347, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2347 = SUB_Fp32
+ { 2348, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2348 = SUB_Fp32m
+ { 2349, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2349 = SUB_Fp64
+ { 2350, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2350 = SUB_Fp64m
+ { 2351, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2351 = SUB_Fp64m32
+ { 2352, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2352 = SUB_Fp80
+ { 2353, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2353 = SUB_Fp80m32
+ { 2354, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2354 = SUB_Fp80m64
+ { 2355, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2355 = SUB_FpI16m32
+ { 2356, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2356 = SUB_FpI16m64
+ { 2357, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2357 = SUB_FpI16m80
+ { 2358, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2358 = SUB_FpI32m32
+ { 2359, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2359 = SUB_FpI32m64
+ { 2360, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2360 = SUB_FpI32m80
+ { 2361, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2361 = SUB_FrST0
+ { 2362, 0, 0, 0, "SWPGS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2362 = SWPGS
+ { 2363, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2363 = SYSCALL
+ { 2364, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2364 = SYSENTER
+ { 2365, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2365 = SYSEXIT
+ { 2366, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2366 = SYSEXIT64
+ { 2367, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2367 = SYSRET
+ { 2368, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2368 = TAILJMPd
+ { 2369, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2369 = TAILJMPm
+ { 2370, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2370 = TAILJMPr
+ { 2371, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2371 = TAILJMPr64
+ { 2372, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2372 = TCRETURNdi
+ { 2373, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2373 = TCRETURNdi64
+ { 2374, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2374 = TCRETURNri
+ { 2375, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo56 }, // Inst #2375 = TCRETURNri64
+ { 2376, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2376 = TEST16i16
+ { 2377, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2377 = TEST16mi
+ { 2378, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2378 = TEST16ri
+ { 2379, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2379 = TEST16rm
+ { 2380, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2380 = TEST16rr
+ { 2381, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2381 = TEST32i32
+ { 2382, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2382 = TEST32mi
+ { 2383, 2, 0, 0, "TEST32ri", 0, 0|16|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2383 = TEST32ri
+ { 2384, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2384 = TEST32rm
+ { 2385, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2385 = TEST32rr
+ { 2386, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2386 = TEST64i32
+ { 2387, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2387 = TEST64mi32
+ { 2388, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #2388 = TEST64ri32
+ { 2389, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2389 = TEST64rm
+ { 2390, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #2390 = TEST64rr
+ { 2391, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2391 = TEST8i8
+ { 2392, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2392 = TEST8mi
+ { 2393, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2393 = TEST8ri
+ { 2394, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #2394 = TEST8rm
+ { 2395, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2395 = TEST8rr
+ { 2396, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo203 }, // Inst #2396 = TLS_addr32
+ { 2397, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo204 }, // Inst #2397 = TLS_addr64
+ { 2398, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2398 = TRAP
+ { 2399, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2399 = TST_F
+ { 2400, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2400 = TST_Fp32
+ { 2401, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2401 = TST_Fp64
+ { 2402, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #2402 = TST_Fp80
+ { 2403, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo82 }, // Inst #2403 = UCOMISDrm
+ { 2404, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2404 = UCOMISDrr
+ { 2405, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2405 = UCOMISSrm
+ { 2406, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo106 }, // Inst #2406 = UCOMISSrr
+ { 2407, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2407 = UCOM_FIPr
+ { 2408, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2408 = UCOM_FIr
+ { 2409, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList23, ImplicitList1, Barriers1, 0 }, // Inst #2409 = UCOM_FPPr
+ { 2410, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2410 = UCOM_FPr
+ { 2411, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2411 = UCOM_FpIr32
+ { 2412, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2412 = UCOM_FpIr64
+ { 2413, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2413 = UCOM_FpIr80
+ { 2414, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2414 = UCOM_Fpr32
+ { 2415, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2415 = UCOM_Fpr64
+ { 2416, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2416 = UCOM_Fpr80
+ { 2417, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2417 = UCOM_Fr
+ { 2418, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2418 = UNPCKHPDrm
+ { 2419, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2419 = UNPCKHPDrr
+ { 2420, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2420 = UNPCKHPSrm
+ { 2421, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2421 = UNPCKHPSrr
+ { 2422, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2422 = UNPCKLPDrm
+ { 2423, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2423 = UNPCKLPDrr
+ { 2424, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2424 = UNPCKLPSrm
+ { 2425, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2425 = UNPCKLPSrr
+ { 2426, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo205 }, // Inst #2426 = VASTART_SAVE_XMM_REGS
+ { 2427, 5, 0, 0, "VERRm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2427 = VERRm
+ { 2428, 1, 0, 0, "VERRr", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2428 = VERRr
+ { 2429, 5, 0, 0, "VERWm", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2429 = VERWm
+ { 2430, 1, 0, 0, "VERWr", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2430 = VERWr
+ { 2431, 0, 0, 0, "VMCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2431 = VMCALL
+ { 2432, 5, 0, 0, "VMCLEARm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2432 = VMCLEARm
+ { 2433, 0, 0, 0, "VMLAUNCH", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2433 = VMLAUNCH
+ { 2434, 5, 0, 0, "VMPTRLDm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2434 = VMPTRLDm
+ { 2435, 5, 1, 0, "VMPTRSTm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2435 = VMPTRSTm
+ { 2436, 6, 1, 0, "VMREAD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2436 = VMREAD32rm
+ { 2437, 2, 1, 0, "VMREAD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2437 = VMREAD32rr
+ { 2438, 6, 1, 0, "VMREAD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2438 = VMREAD64rm
+ { 2439, 2, 1, 0, "VMREAD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2439 = VMREAD64rr
+ { 2440, 0, 0, 0, "VMRESUME", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2440 = VMRESUME
+ { 2441, 6, 1, 0, "VMWRITE32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #2441 = VMWRITE32rm
+ { 2442, 2, 1, 0, "VMWRITE32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2442 = VMWRITE32rr
+ { 2443, 6, 1, 0, "VMWRITE64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #2443 = VMWRITE64rm
+ { 2444, 2, 1, 0, "VMWRITE64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2444 = VMWRITE64rr
+ { 2445, 0, 0, 0, "VMXOFF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2445 = VMXOFF
+ { 2446, 5, 0, 0, "VMXON", 0|(1<<TID::UnmodeledSideEffects), 0|30|(11<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2446 = VMXON
+ { 2447, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo206 }, // Inst #2447 = V_SET0
+ { 2448, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo206 }, // Inst #2448 = V_SETALLONES
+ { 2449, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2449 = WAIT
+ { 2450, 0, 0, 0, "WBINVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(9<<24), NULL, NULL, NULL, 0 }, // Inst #2450 = WBINVD
+ { 2451, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo30 }, // Inst #2451 = WINCALL64m
+ { 2452, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo5 }, // Inst #2452 = WINCALL64pcrel32
+ { 2453, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo58 }, // Inst #2453 = WINCALL64r
+ { 2454, 0, 0, 0, "WRMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(48<<24), NULL, NULL, NULL, 0 }, // Inst #2454 = WRMSR
+ { 2455, 6, 0, 0, "XADD16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #2455 = XADD16rm
+ { 2456, 2, 1, 0, "XADD16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #2456 = XADD16rr
+ { 2457, 6, 0, 0, "XADD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2457 = XADD32rm
+ { 2458, 2, 1, 0, "XADD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2458 = XADD32rr
+ { 2459, 6, 0, 0, "XADD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2459 = XADD64rm
+ { 2460, 2, 1, 0, "XADD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2460 = XADD64rr
+ { 2461, 6, 0, 0, "XADD8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #2461 = XADD8rm
+ { 2462, 2, 1, 0, "XADD8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #2462 = XADD8rr
+ { 2463, 1, 0, 0, "XCHG16ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<6)|(144<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2463 = XCHG16ar
+ { 2464, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo9 }, // Inst #2464 = XCHG16rm
+ { 2465, 3, 1, 0, "XCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo10 }, // Inst #2465 = XCHG16rr
+ { 2466, 1, 0, 0, "XCHG32ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(144<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2466 = XCHG32ar
+ { 2467, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #2467 = XCHG32rm
+ { 2468, 3, 1, 0, "XCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(135<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #2468 = XCHG32rr
+ { 2469, 1, 0, 0, "XCHG64ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<12)|(144<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2469 = XCHG64ar
+ { 2470, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #2470 = XCHG64rm
+ { 2471, 3, 1, 0, "XCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #2471 = XCHG64rr
+ { 2472, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo22 }, // Inst #2472 = XCHG8rm
+ { 2473, 3, 1, 0, "XCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(134<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2473 = XCHG8rr
+ { 2474, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2474 = XCH_F
+ { 2475, 0, 0, 0, "XLAT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(215<<24), NULL, NULL, NULL, 0 }, // Inst #2475 = XLAT
+ { 2476, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2476 = XOR16i16
+ { 2477, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2477 = XOR16mi
+ { 2478, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2478 = XOR16mi8
+ { 2479, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2479 = XOR16mr
+ { 2480, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2480 = XOR16ri
+ { 2481, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2481 = XOR16ri8
+ { 2482, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2482 = XOR16rm
+ { 2483, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2483 = XOR16rr
+ { 2484, 3, 1, 0, "XOR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2484 = XOR16rr_REV
+ { 2485, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2485 = XOR32i32
+ { 2486, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2486 = XOR32mi
+ { 2487, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2487 = XOR32mi8
+ { 2488, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2488 = XOR32mr
+ { 2489, 3, 1, 0, "XOR32ri", 0, 0|22|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2489 = XOR32ri
+ { 2490, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2490 = XOR32ri8
+ { 2491, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2491 = XOR32rm
+ { 2492, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2492 = XOR32rr
+ { 2493, 3, 1, 0, "XOR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2493 = XOR32rr_REV
+ { 2494, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2494 = XOR64i32
+ { 2495, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2495 = XOR64mi32
+ { 2496, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2496 = XOR64mi8
+ { 2497, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2497 = XOR64mr
+ { 2498, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2498 = XOR64ri32
+ { 2499, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2499 = XOR64ri8
+ { 2500, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2500 = XOR64rm
+ { 2501, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2501 = XOR64rr
+ { 2502, 3, 1, 0, "XOR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2502 = XOR64rr_REV
+ { 2503, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2503 = XOR8i8
+ { 2504, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2504 = XOR8mi
+ { 2505, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2505 = XOR8mr
+ { 2506, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2506 = XOR8ri
+ { 2507, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2507 = XOR8rm
+ { 2508, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2508 = XOR8rr
+ { 2509, 3, 1, 0, "XOR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2509 = XOR8rr_REV
+ { 2510, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2510 = XORPDrm
+ { 2511, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2511 = XORPDrr
+ { 2512, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2512 = XORPSrm
+ { 2513, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2513 = XORPSrr
};
} // End llvm namespace
diff --git a/libclamav/c++/X86GenInstrNames.inc b/libclamav/c++/X86GenInstrNames.inc
index a65c3c4..e107252 100644
--- a/libclamav/c++/X86GenInstrNames.inc
+++ b/libclamav/c++/X86GenInstrNames.inc
@@ -33,2233 +33,2498 @@ namespace X86 {
ADC16ri8 = 20,
ADC16rm = 21,
ADC16rr = 22,
- ADC32i32 = 23,
- ADC32mi = 24,
- ADC32mi8 = 25,
- ADC32mr = 26,
- ADC32ri = 27,
- ADC32ri8 = 28,
- ADC32rm = 29,
- ADC32rr = 30,
- ADC64i32 = 31,
- ADC64mi32 = 32,
- ADC64mi8 = 33,
- ADC64mr = 34,
- ADC64ri32 = 35,
- ADC64ri8 = 36,
- ADC64rm = 37,
- ADC64rr = 38,
- ADC8i8 = 39,
- ADC8mi = 40,
- ADC8mr = 41,
- ADC8ri = 42,
- ADC8rm = 43,
- ADC8rr = 44,
- ADD16i16 = 45,
- ADD16mi = 46,
- ADD16mi8 = 47,
- ADD16mr = 48,
- ADD16mrmrr = 49,
- ADD16ri = 50,
- ADD16ri8 = 51,
- ADD16rm = 52,
- ADD16rr = 53,
- ADD32i32 = 54,
- ADD32mi = 55,
- ADD32mi8 = 56,
- ADD32mr = 57,
- ADD32mrmrr = 58,
- ADD32ri = 59,
- ADD32ri8 = 60,
- ADD32rm = 61,
- ADD32rr = 62,
- ADD64i32 = 63,
- ADD64mi32 = 64,
- ADD64mi8 = 65,
- ADD64mr = 66,
- ADD64mrmrr = 67,
- ADD64ri32 = 68,
- ADD64ri8 = 69,
- ADD64rm = 70,
- ADD64rr = 71,
- ADD8i8 = 72,
- ADD8mi = 73,
- ADD8mr = 74,
- ADD8mrmrr = 75,
- ADD8ri = 76,
- ADD8rm = 77,
- ADD8rr = 78,
- ADDPDrm = 79,
- ADDPDrr = 80,
- ADDPSrm = 81,
- ADDPSrr = 82,
- ADDSDrm = 83,
- ADDSDrm_Int = 84,
- ADDSDrr = 85,
- ADDSDrr_Int = 86,
- ADDSSrm = 87,
- ADDSSrm_Int = 88,
- ADDSSrr = 89,
- ADDSSrr_Int = 90,
- ADDSUBPDrm = 91,
- ADDSUBPDrr = 92,
- ADDSUBPSrm = 93,
- ADDSUBPSrr = 94,
- ADD_F32m = 95,
- ADD_F64m = 96,
- ADD_FI16m = 97,
- ADD_FI32m = 98,
- ADD_FPrST0 = 99,
- ADD_FST0r = 100,
- ADD_Fp32 = 101,
- ADD_Fp32m = 102,
- ADD_Fp64 = 103,
- ADD_Fp64m = 104,
- ADD_Fp64m32 = 105,
- ADD_Fp80 = 106,
- ADD_Fp80m32 = 107,
- ADD_Fp80m64 = 108,
- ADD_FpI16m32 = 109,
- ADD_FpI16m64 = 110,
- ADD_FpI16m80 = 111,
- ADD_FpI32m32 = 112,
- ADD_FpI32m64 = 113,
- ADD_FpI32m80 = 114,
- ADD_FrST0 = 115,
- ADJCALLSTACKDOWN32 = 116,
- ADJCALLSTACKDOWN64 = 117,
- ADJCALLSTACKUP32 = 118,
- ADJCALLSTACKUP64 = 119,
- AND16i16 = 120,
- AND16mi = 121,
- AND16mi8 = 122,
- AND16mr = 123,
- AND16ri = 124,
- AND16ri8 = 125,
- AND16rm = 126,
- AND16rr = 127,
- AND32i32 = 128,
- AND32mi = 129,
- AND32mi8 = 130,
- AND32mr = 131,
- AND32ri = 132,
- AND32ri8 = 133,
- AND32rm = 134,
- AND32rr = 135,
- AND64i32 = 136,
- AND64mi32 = 137,
- AND64mi8 = 138,
- AND64mr = 139,
- AND64ri32 = 140,
- AND64ri8 = 141,
- AND64rm = 142,
- AND64rr = 143,
- AND8i8 = 144,
- AND8mi = 145,
- AND8mr = 146,
- AND8ri = 147,
- AND8rm = 148,
- AND8rr = 149,
- ANDNPDrm = 150,
- ANDNPDrr = 151,
- ANDNPSrm = 152,
- ANDNPSrr = 153,
- ANDPDrm = 154,
- ANDPDrr = 155,
- ANDPSrm = 156,
- ANDPSrr = 157,
- ATOMADD6432 = 158,
- ATOMAND16 = 159,
- ATOMAND32 = 160,
- ATOMAND64 = 161,
- ATOMAND6432 = 162,
- ATOMAND8 = 163,
- ATOMMAX16 = 164,
- ATOMMAX32 = 165,
- ATOMMAX64 = 166,
- ATOMMIN16 = 167,
- ATOMMIN32 = 168,
- ATOMMIN64 = 169,
- ATOMNAND16 = 170,
- ATOMNAND32 = 171,
- ATOMNAND64 = 172,
- ATOMNAND6432 = 173,
- ATOMNAND8 = 174,
- ATOMOR16 = 175,
- ATOMOR32 = 176,
- ATOMOR64 = 177,
- ATOMOR6432 = 178,
- ATOMOR8 = 179,
- ATOMSUB6432 = 180,
- ATOMSWAP6432 = 181,
- ATOMUMAX16 = 182,
- ATOMUMAX32 = 183,
- ATOMUMAX64 = 184,
- ATOMUMIN16 = 185,
- ATOMUMIN32 = 186,
- ATOMUMIN64 = 187,
- ATOMXOR16 = 188,
- ATOMXOR32 = 189,
- ATOMXOR64 = 190,
- ATOMXOR6432 = 191,
- ATOMXOR8 = 192,
- BLENDPDrmi = 193,
- BLENDPDrri = 194,
- BLENDPSrmi = 195,
- BLENDPSrri = 196,
- BLENDVPDrm0 = 197,
- BLENDVPDrr0 = 198,
- BLENDVPSrm0 = 199,
- BLENDVPSrr0 = 200,
- BSF16rm = 201,
- BSF16rr = 202,
- BSF32rm = 203,
- BSF32rr = 204,
- BSF64rm = 205,
- BSF64rr = 206,
- BSR16rm = 207,
- BSR16rr = 208,
- BSR32rm = 209,
- BSR32rr = 210,
- BSR64rm = 211,
- BSR64rr = 212,
- BSWAP32r = 213,
- BSWAP64r = 214,
- BT16mi8 = 215,
- BT16ri8 = 216,
- BT16rr = 217,
- BT32mi8 = 218,
- BT32ri8 = 219,
- BT32rr = 220,
- BT64mi8 = 221,
- BT64ri8 = 222,
- BT64rr = 223,
- CALL32m = 224,
- CALL32r = 225,
- CALL64m = 226,
- CALL64pcrel32 = 227,
- CALL64r = 228,
- CALLpcrel32 = 229,
- CBW = 230,
- CDQ = 231,
- CDQE = 232,
- CHS_F = 233,
- CHS_Fp32 = 234,
- CHS_Fp64 = 235,
- CHS_Fp80 = 236,
- CLFLUSH = 237,
- CMOVA16rm = 238,
- CMOVA16rr = 239,
- CMOVA32rm = 240,
- CMOVA32rr = 241,
- CMOVA64rm = 242,
- CMOVA64rr = 243,
- CMOVAE16rm = 244,
- CMOVAE16rr = 245,
- CMOVAE32rm = 246,
- CMOVAE32rr = 247,
- CMOVAE64rm = 248,
- CMOVAE64rr = 249,
- CMOVB16rm = 250,
- CMOVB16rr = 251,
- CMOVB32rm = 252,
- CMOVB32rr = 253,
- CMOVB64rm = 254,
- CMOVB64rr = 255,
- CMOVBE16rm = 256,
- CMOVBE16rr = 257,
- CMOVBE32rm = 258,
- CMOVBE32rr = 259,
- CMOVBE64rm = 260,
- CMOVBE64rr = 261,
- CMOVBE_F = 262,
- CMOVBE_Fp32 = 263,
- CMOVBE_Fp64 = 264,
- CMOVBE_Fp80 = 265,
- CMOVB_F = 266,
- CMOVB_Fp32 = 267,
- CMOVB_Fp64 = 268,
- CMOVB_Fp80 = 269,
- CMOVE16rm = 270,
- CMOVE16rr = 271,
- CMOVE32rm = 272,
- CMOVE32rr = 273,
- CMOVE64rm = 274,
- CMOVE64rr = 275,
- CMOVE_F = 276,
- CMOVE_Fp32 = 277,
- CMOVE_Fp64 = 278,
- CMOVE_Fp80 = 279,
- CMOVG16rm = 280,
- CMOVG16rr = 281,
- CMOVG32rm = 282,
- CMOVG32rr = 283,
- CMOVG64rm = 284,
- CMOVG64rr = 285,
- CMOVGE16rm = 286,
- CMOVGE16rr = 287,
- CMOVGE32rm = 288,
- CMOVGE32rr = 289,
- CMOVGE64rm = 290,
- CMOVGE64rr = 291,
- CMOVL16rm = 292,
- CMOVL16rr = 293,
- CMOVL32rm = 294,
- CMOVL32rr = 295,
- CMOVL64rm = 296,
- CMOVL64rr = 297,
- CMOVLE16rm = 298,
- CMOVLE16rr = 299,
- CMOVLE32rm = 300,
- CMOVLE32rr = 301,
- CMOVLE64rm = 302,
- CMOVLE64rr = 303,
- CMOVNBE_F = 304,
- CMOVNBE_Fp32 = 305,
- CMOVNBE_Fp64 = 306,
- CMOVNBE_Fp80 = 307,
- CMOVNB_F = 308,
- CMOVNB_Fp32 = 309,
- CMOVNB_Fp64 = 310,
- CMOVNB_Fp80 = 311,
- CMOVNE16rm = 312,
- CMOVNE16rr = 313,
- CMOVNE32rm = 314,
- CMOVNE32rr = 315,
- CMOVNE64rm = 316,
- CMOVNE64rr = 317,
- CMOVNE_F = 318,
- CMOVNE_Fp32 = 319,
- CMOVNE_Fp64 = 320,
- CMOVNE_Fp80 = 321,
- CMOVNO16rm = 322,
- CMOVNO16rr = 323,
- CMOVNO32rm = 324,
- CMOVNO32rr = 325,
- CMOVNO64rm = 326,
- CMOVNO64rr = 327,
- CMOVNP16rm = 328,
- CMOVNP16rr = 329,
- CMOVNP32rm = 330,
- CMOVNP32rr = 331,
- CMOVNP64rm = 332,
- CMOVNP64rr = 333,
- CMOVNP_F = 334,
- CMOVNP_Fp32 = 335,
- CMOVNP_Fp64 = 336,
- CMOVNP_Fp80 = 337,
- CMOVNS16rm = 338,
- CMOVNS16rr = 339,
- CMOVNS32rm = 340,
- CMOVNS32rr = 341,
- CMOVNS64rm = 342,
- CMOVNS64rr = 343,
- CMOVO16rm = 344,
- CMOVO16rr = 345,
- CMOVO32rm = 346,
- CMOVO32rr = 347,
- CMOVO64rm = 348,
- CMOVO64rr = 349,
- CMOVP16rm = 350,
- CMOVP16rr = 351,
- CMOVP32rm = 352,
- CMOVP32rr = 353,
- CMOVP64rm = 354,
- CMOVP64rr = 355,
- CMOVP_F = 356,
- CMOVP_Fp32 = 357,
- CMOVP_Fp64 = 358,
- CMOVP_Fp80 = 359,
- CMOVS16rm = 360,
- CMOVS16rr = 361,
- CMOVS32rm = 362,
- CMOVS32rr = 363,
- CMOVS64rm = 364,
- CMOVS64rr = 365,
- CMOV_FR32 = 366,
- CMOV_FR64 = 367,
- CMOV_GR8 = 368,
- CMOV_V1I64 = 369,
- CMOV_V2F64 = 370,
- CMOV_V2I64 = 371,
- CMOV_V4F32 = 372,
- CMP16i16 = 373,
- CMP16mi = 374,
- CMP16mi8 = 375,
- CMP16mr = 376,
- CMP16mrmrr = 377,
- CMP16ri = 378,
- CMP16ri8 = 379,
- CMP16rm = 380,
- CMP16rr = 381,
- CMP32i32 = 382,
- CMP32mi = 383,
- CMP32mi8 = 384,
- CMP32mr = 385,
- CMP32mrmrr = 386,
- CMP32ri = 387,
- CMP32ri8 = 388,
- CMP32rm = 389,
- CMP32rr = 390,
- CMP64i32 = 391,
- CMP64mi32 = 392,
- CMP64mi8 = 393,
- CMP64mr = 394,
- CMP64mrmrr = 395,
- CMP64ri32 = 396,
- CMP64ri8 = 397,
- CMP64rm = 398,
- CMP64rr = 399,
- CMP8i8 = 400,
- CMP8mi = 401,
- CMP8mr = 402,
- CMP8mrmrr = 403,
- CMP8ri = 404,
- CMP8rm = 405,
- CMP8rr = 406,
- CMPPDrmi = 407,
- CMPPDrri = 408,
- CMPPSrmi = 409,
- CMPPSrri = 410,
- CMPS16 = 411,
- CMPS32 = 412,
- CMPS64 = 413,
- CMPS8 = 414,
- CMPSDrm = 415,
- CMPSDrr = 416,
- CMPSSrm = 417,
- CMPSSrr = 418,
- COMISDrm = 419,
- COMISDrr = 420,
- COS_F = 421,
- COS_Fp32 = 422,
- COS_Fp64 = 423,
- COS_Fp80 = 424,
- CQO = 425,
- CRC32m16 = 426,
- CRC32m32 = 427,
- CRC32m8 = 428,
- CRC32r16 = 429,
- CRC32r32 = 430,
- CRC32r8 = 431,
- CRC64m64 = 432,
- CRC64r64 = 433,
- CVTDQ2PDrm = 434,
- CVTDQ2PDrr = 435,
- CVTDQ2PSrm = 436,
- CVTDQ2PSrr = 437,
- CVTPD2DQrm = 438,
- CVTPD2DQrr = 439,
- CVTPS2DQrm = 440,
- CVTPS2DQrr = 441,
- CVTSD2SSrm = 442,
- CVTSD2SSrr = 443,
- CVTSI2SD64rm = 444,
- CVTSI2SD64rr = 445,
- CVTSI2SDrm = 446,
- CVTSI2SDrr = 447,
- CVTSI2SS64rm = 448,
- CVTSI2SS64rr = 449,
- CVTSI2SSrm = 450,
- CVTSI2SSrr = 451,
- CVTSS2SDrm = 452,
- CVTSS2SDrr = 453,
- CVTTSD2SI64rm = 454,
- CVTTSD2SI64rr = 455,
- CVTTSD2SIrm = 456,
- CVTTSD2SIrr = 457,
- CVTTSS2SI64rm = 458,
- CVTTSS2SI64rr = 459,
- CVTTSS2SIrm = 460,
- CVTTSS2SIrr = 461,
- CWD = 462,
- CWDE = 463,
- DEC16m = 464,
- DEC16r = 465,
- DEC32m = 466,
- DEC32r = 467,
- DEC64_16m = 468,
- DEC64_16r = 469,
- DEC64_32m = 470,
- DEC64_32r = 471,
- DEC64m = 472,
- DEC64r = 473,
- DEC8m = 474,
- DEC8r = 475,
- DIV16m = 476,
- DIV16r = 477,
- DIV32m = 478,
- DIV32r = 479,
- DIV64m = 480,
- DIV64r = 481,
- DIV8m = 482,
- DIV8r = 483,
- DIVPDrm = 484,
- DIVPDrr = 485,
- DIVPSrm = 486,
- DIVPSrr = 487,
- DIVR_F32m = 488,
- DIVR_F64m = 489,
- DIVR_FI16m = 490,
- DIVR_FI32m = 491,
- DIVR_FPrST0 = 492,
- DIVR_FST0r = 493,
- DIVR_Fp32m = 494,
- DIVR_Fp64m = 495,
- DIVR_Fp64m32 = 496,
- DIVR_Fp80m32 = 497,
- DIVR_Fp80m64 = 498,
- DIVR_FpI16m32 = 499,
- DIVR_FpI16m64 = 500,
- DIVR_FpI16m80 = 501,
- DIVR_FpI32m32 = 502,
- DIVR_FpI32m64 = 503,
- DIVR_FpI32m80 = 504,
- DIVR_FrST0 = 505,
- DIVSDrm = 506,
- DIVSDrm_Int = 507,
- DIVSDrr = 508,
- DIVSDrr_Int = 509,
- DIVSSrm = 510,
- DIVSSrm_Int = 511,
- DIVSSrr = 512,
- DIVSSrr_Int = 513,
- DIV_F32m = 514,
- DIV_F64m = 515,
- DIV_FI16m = 516,
- DIV_FI32m = 517,
- DIV_FPrST0 = 518,
- DIV_FST0r = 519,
- DIV_Fp32 = 520,
- DIV_Fp32m = 521,
- DIV_Fp64 = 522,
- DIV_Fp64m = 523,
- DIV_Fp64m32 = 524,
- DIV_Fp80 = 525,
- DIV_Fp80m32 = 526,
- DIV_Fp80m64 = 527,
- DIV_FpI16m32 = 528,
- DIV_FpI16m64 = 529,
- DIV_FpI16m80 = 530,
- DIV_FpI32m32 = 531,
- DIV_FpI32m64 = 532,
- DIV_FpI32m80 = 533,
- DIV_FrST0 = 534,
- DPPDrmi = 535,
- DPPDrri = 536,
- DPPSrmi = 537,
- DPPSrri = 538,
- EH_RETURN = 539,
- EH_RETURN64 = 540,
- ENTER = 541,
- EXTRACTPSmr = 542,
- EXTRACTPSrr = 543,
- FARCALL16i = 544,
- FARCALL16m = 545,
- FARCALL32i = 546,
- FARCALL32m = 547,
- FARCALL64 = 548,
- FARJMP16i = 549,
- FARJMP16m = 550,
- FARJMP32i = 551,
- FARJMP32m = 552,
- FARJMP64 = 553,
- FBLDm = 554,
- FBSTPm = 555,
- FCOM32m = 556,
- FCOM64m = 557,
- FCOMP32m = 558,
- FCOMP64m = 559,
- FICOM16m = 560,
- FICOM32m = 561,
- FICOMP16m = 562,
- FICOMP32m = 563,
- FISTTP32m = 564,
- FLDCW16m = 565,
- FLDENVm = 566,
- FNSTCW16m = 567,
- FNSTSW8r = 568,
- FP32_TO_INT16_IN_MEM = 569,
- FP32_TO_INT32_IN_MEM = 570,
- FP32_TO_INT64_IN_MEM = 571,
- FP64_TO_INT16_IN_MEM = 572,
- FP64_TO_INT32_IN_MEM = 573,
- FP64_TO_INT64_IN_MEM = 574,
- FP80_TO_INT16_IN_MEM = 575,
- FP80_TO_INT32_IN_MEM = 576,
- FP80_TO_INT64_IN_MEM = 577,
- FP_REG_KILL = 578,
- FRSTORm = 579,
- FSAVEm = 580,
- FSTENVm = 581,
- FSTSWm = 582,
- FS_MOV32rm = 583,
- FpGET_ST0_32 = 584,
- FpGET_ST0_64 = 585,
- FpGET_ST0_80 = 586,
- FpGET_ST1_32 = 587,
- FpGET_ST1_64 = 588,
- FpGET_ST1_80 = 589,
- FpSET_ST0_32 = 590,
- FpSET_ST0_64 = 591,
- FpSET_ST0_80 = 592,
- FpSET_ST1_32 = 593,
- FpSET_ST1_64 = 594,
- FpSET_ST1_80 = 595,
- FsANDNPDrm = 596,
- FsANDNPDrr = 597,
- FsANDNPSrm = 598,
- FsANDNPSrr = 599,
- FsANDPDrm = 600,
- FsANDPDrr = 601,
- FsANDPSrm = 602,
- FsANDPSrr = 603,
- FsFLD0SD = 604,
- FsFLD0SS = 605,
- FsMOVAPDrm = 606,
- FsMOVAPDrr = 607,
- FsMOVAPSrm = 608,
- FsMOVAPSrr = 609,
- FsORPDrm = 610,
- FsORPDrr = 611,
- FsORPSrm = 612,
- FsORPSrr = 613,
- FsXORPDrm = 614,
- FsXORPDrr = 615,
- FsXORPSrm = 616,
- FsXORPSrr = 617,
- GS_MOV32rm = 618,
- HADDPDrm = 619,
- HADDPDrr = 620,
- HADDPSrm = 621,
- HADDPSrr = 622,
- HSUBPDrm = 623,
- HSUBPDrr = 624,
- HSUBPSrm = 625,
- HSUBPSrr = 626,
- IDIV16m = 627,
- IDIV16r = 628,
- IDIV32m = 629,
- IDIV32r = 630,
- IDIV64m = 631,
- IDIV64r = 632,
- IDIV8m = 633,
- IDIV8r = 634,
- ILD_F16m = 635,
- ILD_F32m = 636,
- ILD_F64m = 637,
- ILD_Fp16m32 = 638,
- ILD_Fp16m64 = 639,
- ILD_Fp16m80 = 640,
- ILD_Fp32m32 = 641,
- ILD_Fp32m64 = 642,
- ILD_Fp32m80 = 643,
- ILD_Fp64m32 = 644,
- ILD_Fp64m64 = 645,
- ILD_Fp64m80 = 646,
- IMUL16m = 647,
- IMUL16r = 648,
- IMUL16rm = 649,
- IMUL16rmi = 650,
- IMUL16rmi8 = 651,
- IMUL16rr = 652,
- IMUL16rri = 653,
- IMUL16rri8 = 654,
- IMUL32m = 655,
- IMUL32r = 656,
- IMUL32rm = 657,
- IMUL32rmi = 658,
- IMUL32rmi8 = 659,
- IMUL32rr = 660,
- IMUL32rri = 661,
- IMUL32rri8 = 662,
- IMUL64m = 663,
- IMUL64r = 664,
- IMUL64rm = 665,
- IMUL64rmi32 = 666,
- IMUL64rmi8 = 667,
- IMUL64rr = 668,
- IMUL64rri32 = 669,
- IMUL64rri8 = 670,
- IMUL8m = 671,
- IMUL8r = 672,
- IN16ri = 673,
- IN16rr = 674,
- IN32ri = 675,
- IN32rr = 676,
- IN8ri = 677,
- IN8rr = 678,
- INC16m = 679,
- INC16r = 680,
- INC32m = 681,
- INC32r = 682,
- INC64_16m = 683,
- INC64_16r = 684,
- INC64_32m = 685,
- INC64_32r = 686,
- INC64m = 687,
- INC64r = 688,
- INC8m = 689,
- INC8r = 690,
- INSERTPSrm = 691,
- INSERTPSrr = 692,
- INT = 693,
- INT3 = 694,
- ISTT_FP16m = 695,
- ISTT_FP32m = 696,
- ISTT_FP64m = 697,
- ISTT_Fp16m32 = 698,
- ISTT_Fp16m64 = 699,
- ISTT_Fp16m80 = 700,
- ISTT_Fp32m32 = 701,
- ISTT_Fp32m64 = 702,
- ISTT_Fp32m80 = 703,
- ISTT_Fp64m32 = 704,
- ISTT_Fp64m64 = 705,
- ISTT_Fp64m80 = 706,
- IST_F16m = 707,
- IST_F32m = 708,
- IST_FP16m = 709,
- IST_FP32m = 710,
- IST_FP64m = 711,
- IST_Fp16m32 = 712,
- IST_Fp16m64 = 713,
- IST_Fp16m80 = 714,
- IST_Fp32m32 = 715,
- IST_Fp32m64 = 716,
- IST_Fp32m80 = 717,
- IST_Fp64m32 = 718,
- IST_Fp64m64 = 719,
- IST_Fp64m80 = 720,
- Int_CMPSDrm = 721,
- Int_CMPSDrr = 722,
- Int_CMPSSrm = 723,
- Int_CMPSSrr = 724,
- Int_COMISDrm = 725,
- Int_COMISDrr = 726,
- Int_COMISSrm = 727,
- Int_COMISSrr = 728,
- Int_CVTDQ2PDrm = 729,
- Int_CVTDQ2PDrr = 730,
- Int_CVTDQ2PSrm = 731,
- Int_CVTDQ2PSrr = 732,
- Int_CVTPD2DQrm = 733,
- Int_CVTPD2DQrr = 734,
- Int_CVTPD2PIrm = 735,
- Int_CVTPD2PIrr = 736,
- Int_CVTPD2PSrm = 737,
- Int_CVTPD2PSrr = 738,
- Int_CVTPI2PDrm = 739,
- Int_CVTPI2PDrr = 740,
- Int_CVTPI2PSrm = 741,
- Int_CVTPI2PSrr = 742,
- Int_CVTPS2DQrm = 743,
- Int_CVTPS2DQrr = 744,
- Int_CVTPS2PDrm = 745,
- Int_CVTPS2PDrr = 746,
- Int_CVTPS2PIrm = 747,
- Int_CVTPS2PIrr = 748,
- Int_CVTSD2SI64rm = 749,
- Int_CVTSD2SI64rr = 750,
- Int_CVTSD2SIrm = 751,
- Int_CVTSD2SIrr = 752,
- Int_CVTSD2SSrm = 753,
- Int_CVTSD2SSrr = 754,
- Int_CVTSI2SD64rm = 755,
- Int_CVTSI2SD64rr = 756,
- Int_CVTSI2SDrm = 757,
- Int_CVTSI2SDrr = 758,
- Int_CVTSI2SS64rm = 759,
- Int_CVTSI2SS64rr = 760,
- Int_CVTSI2SSrm = 761,
- Int_CVTSI2SSrr = 762,
- Int_CVTSS2SDrm = 763,
- Int_CVTSS2SDrr = 764,
- Int_CVTSS2SI64rm = 765,
- Int_CVTSS2SI64rr = 766,
- Int_CVTSS2SIrm = 767,
- Int_CVTSS2SIrr = 768,
- Int_CVTTPD2DQrm = 769,
- Int_CVTTPD2DQrr = 770,
- Int_CVTTPD2PIrm = 771,
- Int_CVTTPD2PIrr = 772,
- Int_CVTTPS2DQrm = 773,
- Int_CVTTPS2DQrr = 774,
- Int_CVTTPS2PIrm = 775,
- Int_CVTTPS2PIrr = 776,
- Int_CVTTSD2SI64rm = 777,
- Int_CVTTSD2SI64rr = 778,
- Int_CVTTSD2SIrm = 779,
- Int_CVTTSD2SIrr = 780,
- Int_CVTTSS2SI64rm = 781,
- Int_CVTTSS2SI64rr = 782,
- Int_CVTTSS2SIrm = 783,
- Int_CVTTSS2SIrr = 784,
- Int_UCOMISDrm = 785,
- Int_UCOMISDrr = 786,
- Int_UCOMISSrm = 787,
- Int_UCOMISSrr = 788,
- JA = 789,
- JA8 = 790,
- JAE = 791,
- JAE8 = 792,
- JB = 793,
- JB8 = 794,
- JBE = 795,
- JBE8 = 796,
- JCXZ8 = 797,
- JE = 798,
- JE8 = 799,
- JG = 800,
- JG8 = 801,
- JGE = 802,
- JGE8 = 803,
- JL = 804,
- JL8 = 805,
- JLE = 806,
- JLE8 = 807,
- JMP = 808,
- JMP32m = 809,
- JMP32r = 810,
- JMP64m = 811,
- JMP64r = 812,
- JMP8 = 813,
- JNE = 814,
- JNE8 = 815,
- JNO = 816,
- JNO8 = 817,
- JNP = 818,
- JNP8 = 819,
- JNS = 820,
- JNS8 = 821,
- JO = 822,
- JO8 = 823,
- JP = 824,
- JP8 = 825,
- JS = 826,
- JS8 = 827,
- LAHF = 828,
- LAR16rm = 829,
- LAR16rr = 830,
- LAR32rm = 831,
- LAR32rr = 832,
- LAR64rm = 833,
- LAR64rr = 834,
- LCMPXCHG16 = 835,
- LCMPXCHG32 = 836,
- LCMPXCHG64 = 837,
- LCMPXCHG8 = 838,
- LCMPXCHG8B = 839,
- LDDQUrm = 840,
- LDMXCSR = 841,
- LD_F0 = 842,
- LD_F1 = 843,
- LD_F32m = 844,
- LD_F64m = 845,
- LD_F80m = 846,
- LD_Fp032 = 847,
- LD_Fp064 = 848,
- LD_Fp080 = 849,
- LD_Fp132 = 850,
- LD_Fp164 = 851,
- LD_Fp180 = 852,
- LD_Fp32m = 853,
- LD_Fp32m64 = 854,
- LD_Fp32m80 = 855,
- LD_Fp64m = 856,
- LD_Fp64m80 = 857,
- LD_Fp80m = 858,
- LD_Frr = 859,
- LEA16r = 860,
- LEA32r = 861,
- LEA64_32r = 862,
- LEA64r = 863,
- LEAVE = 864,
- LEAVE64 = 865,
- LFENCE = 866,
- LOCK_ADD16mi = 867,
- LOCK_ADD16mi8 = 868,
- LOCK_ADD16mr = 869,
- LOCK_ADD32mi = 870,
- LOCK_ADD32mi8 = 871,
- LOCK_ADD32mr = 872,
- LOCK_ADD64mi32 = 873,
- LOCK_ADD64mi8 = 874,
- LOCK_ADD64mr = 875,
- LOCK_ADD8mi = 876,
- LOCK_ADD8mr = 877,
- LOCK_DEC16m = 878,
- LOCK_DEC32m = 879,
- LOCK_DEC64m = 880,
- LOCK_DEC8m = 881,
- LOCK_INC16m = 882,
- LOCK_INC32m = 883,
- LOCK_INC64m = 884,
- LOCK_INC8m = 885,
- LOCK_SUB16mi = 886,
- LOCK_SUB16mi8 = 887,
- LOCK_SUB16mr = 888,
- LOCK_SUB32mi = 889,
- LOCK_SUB32mi8 = 890,
- LOCK_SUB32mr = 891,
- LOCK_SUB64mi32 = 892,
- LOCK_SUB64mi8 = 893,
- LOCK_SUB64mr = 894,
- LOCK_SUB8mi = 895,
- LOCK_SUB8mr = 896,
- LODSB = 897,
- LODSD = 898,
- LODSQ = 899,
- LODSW = 900,
- LOOP = 901,
- LOOPE = 902,
- LOOPNE = 903,
- LRET = 904,
- LRETI = 905,
- LXADD16 = 906,
- LXADD32 = 907,
- LXADD64 = 908,
- LXADD8 = 909,
- MASKMOVDQU = 910,
- MASKMOVDQU64 = 911,
- MAXPDrm = 912,
- MAXPDrm_Int = 913,
- MAXPDrr = 914,
- MAXPDrr_Int = 915,
- MAXPSrm = 916,
- MAXPSrm_Int = 917,
- MAXPSrr = 918,
- MAXPSrr_Int = 919,
- MAXSDrm = 920,
- MAXSDrm_Int = 921,
- MAXSDrr = 922,
- MAXSDrr_Int = 923,
- MAXSSrm = 924,
- MAXSSrm_Int = 925,
- MAXSSrr = 926,
- MAXSSrr_Int = 927,
- MFENCE = 928,
- MINPDrm = 929,
- MINPDrm_Int = 930,
- MINPDrr = 931,
- MINPDrr_Int = 932,
- MINPSrm = 933,
- MINPSrm_Int = 934,
- MINPSrr = 935,
- MINPSrr_Int = 936,
- MINSDrm = 937,
- MINSDrm_Int = 938,
- MINSDrr = 939,
- MINSDrr_Int = 940,
- MINSSrm = 941,
- MINSSrm_Int = 942,
- MINSSrr = 943,
- MINSSrr_Int = 944,
- MMX_CVTPD2PIrm = 945,
- MMX_CVTPD2PIrr = 946,
- MMX_CVTPI2PDrm = 947,
- MMX_CVTPI2PDrr = 948,
- MMX_CVTPI2PSrm = 949,
- MMX_CVTPI2PSrr = 950,
- MMX_CVTPS2PIrm = 951,
- MMX_CVTPS2PIrr = 952,
- MMX_CVTTPD2PIrm = 953,
- MMX_CVTTPD2PIrr = 954,
- MMX_CVTTPS2PIrm = 955,
- MMX_CVTTPS2PIrr = 956,
- MMX_EMMS = 957,
- MMX_FEMMS = 958,
- MMX_MASKMOVQ = 959,
- MMX_MASKMOVQ64 = 960,
- MMX_MOVD64from64rr = 961,
- MMX_MOVD64mr = 962,
- MMX_MOVD64rm = 963,
- MMX_MOVD64rr = 964,
- MMX_MOVD64rrv164 = 965,
- MMX_MOVD64to64rr = 966,
- MMX_MOVDQ2Qrr = 967,
- MMX_MOVNTQmr = 968,
- MMX_MOVQ2DQrr = 969,
- MMX_MOVQ2FR64rr = 970,
- MMX_MOVQ64mr = 971,
- MMX_MOVQ64rm = 972,
- MMX_MOVQ64rr = 973,
- MMX_MOVZDI2PDIrm = 974,
- MMX_MOVZDI2PDIrr = 975,
- MMX_PACKSSDWrm = 976,
- MMX_PACKSSDWrr = 977,
- MMX_PACKSSWBrm = 978,
- MMX_PACKSSWBrr = 979,
- MMX_PACKUSWBrm = 980,
- MMX_PACKUSWBrr = 981,
- MMX_PADDBrm = 982,
- MMX_PADDBrr = 983,
- MMX_PADDDrm = 984,
- MMX_PADDDrr = 985,
- MMX_PADDQrm = 986,
- MMX_PADDQrr = 987,
- MMX_PADDSBrm = 988,
- MMX_PADDSBrr = 989,
- MMX_PADDSWrm = 990,
- MMX_PADDSWrr = 991,
- MMX_PADDUSBrm = 992,
- MMX_PADDUSBrr = 993,
- MMX_PADDUSWrm = 994,
- MMX_PADDUSWrr = 995,
- MMX_PADDWrm = 996,
- MMX_PADDWrr = 997,
- MMX_PANDNrm = 998,
- MMX_PANDNrr = 999,
- MMX_PANDrm = 1000,
- MMX_PANDrr = 1001,
- MMX_PAVGBrm = 1002,
- MMX_PAVGBrr = 1003,
- MMX_PAVGWrm = 1004,
- MMX_PAVGWrr = 1005,
- MMX_PCMPEQBrm = 1006,
- MMX_PCMPEQBrr = 1007,
- MMX_PCMPEQDrm = 1008,
- MMX_PCMPEQDrr = 1009,
- MMX_PCMPEQWrm = 1010,
- MMX_PCMPEQWrr = 1011,
- MMX_PCMPGTBrm = 1012,
- MMX_PCMPGTBrr = 1013,
- MMX_PCMPGTDrm = 1014,
- MMX_PCMPGTDrr = 1015,
- MMX_PCMPGTWrm = 1016,
- MMX_PCMPGTWrr = 1017,
- MMX_PEXTRWri = 1018,
- MMX_PINSRWrmi = 1019,
- MMX_PINSRWrri = 1020,
- MMX_PMADDWDrm = 1021,
- MMX_PMADDWDrr = 1022,
- MMX_PMAXSWrm = 1023,
- MMX_PMAXSWrr = 1024,
- MMX_PMAXUBrm = 1025,
- MMX_PMAXUBrr = 1026,
- MMX_PMINSWrm = 1027,
- MMX_PMINSWrr = 1028,
- MMX_PMINUBrm = 1029,
- MMX_PMINUBrr = 1030,
- MMX_PMOVMSKBrr = 1031,
- MMX_PMULHUWrm = 1032,
- MMX_PMULHUWrr = 1033,
- MMX_PMULHWrm = 1034,
- MMX_PMULHWrr = 1035,
- MMX_PMULLWrm = 1036,
- MMX_PMULLWrr = 1037,
- MMX_PMULUDQrm = 1038,
- MMX_PMULUDQrr = 1039,
- MMX_PORrm = 1040,
- MMX_PORrr = 1041,
- MMX_PSADBWrm = 1042,
- MMX_PSADBWrr = 1043,
- MMX_PSHUFWmi = 1044,
- MMX_PSHUFWri = 1045,
- MMX_PSLLDri = 1046,
- MMX_PSLLDrm = 1047,
- MMX_PSLLDrr = 1048,
- MMX_PSLLQri = 1049,
- MMX_PSLLQrm = 1050,
- MMX_PSLLQrr = 1051,
- MMX_PSLLWri = 1052,
- MMX_PSLLWrm = 1053,
- MMX_PSLLWrr = 1054,
- MMX_PSRADri = 1055,
- MMX_PSRADrm = 1056,
- MMX_PSRADrr = 1057,
- MMX_PSRAWri = 1058,
- MMX_PSRAWrm = 1059,
- MMX_PSRAWrr = 1060,
- MMX_PSRLDri = 1061,
- MMX_PSRLDrm = 1062,
- MMX_PSRLDrr = 1063,
- MMX_PSRLQri = 1064,
- MMX_PSRLQrm = 1065,
- MMX_PSRLQrr = 1066,
- MMX_PSRLWri = 1067,
- MMX_PSRLWrm = 1068,
- MMX_PSRLWrr = 1069,
- MMX_PSUBBrm = 1070,
- MMX_PSUBBrr = 1071,
- MMX_PSUBDrm = 1072,
- MMX_PSUBDrr = 1073,
- MMX_PSUBQrm = 1074,
- MMX_PSUBQrr = 1075,
- MMX_PSUBSBrm = 1076,
- MMX_PSUBSBrr = 1077,
- MMX_PSUBSWrm = 1078,
- MMX_PSUBSWrr = 1079,
- MMX_PSUBUSBrm = 1080,
- MMX_PSUBUSBrr = 1081,
- MMX_PSUBUSWrm = 1082,
- MMX_PSUBUSWrr = 1083,
- MMX_PSUBWrm = 1084,
- MMX_PSUBWrr = 1085,
- MMX_PUNPCKHBWrm = 1086,
- MMX_PUNPCKHBWrr = 1087,
- MMX_PUNPCKHDQrm = 1088,
- MMX_PUNPCKHDQrr = 1089,
- MMX_PUNPCKHWDrm = 1090,
- MMX_PUNPCKHWDrr = 1091,
- MMX_PUNPCKLBWrm = 1092,
- MMX_PUNPCKLBWrr = 1093,
- MMX_PUNPCKLDQrm = 1094,
- MMX_PUNPCKLDQrr = 1095,
- MMX_PUNPCKLWDrm = 1096,
- MMX_PUNPCKLWDrr = 1097,
- MMX_PXORrm = 1098,
- MMX_PXORrr = 1099,
- MMX_V_SET0 = 1100,
- MMX_V_SETALLONES = 1101,
- MONITOR = 1102,
- MOV16ao16 = 1103,
- MOV16mi = 1104,
- MOV16mr = 1105,
- MOV16ms = 1106,
- MOV16o16a = 1107,
- MOV16r0 = 1108,
- MOV16ri = 1109,
- MOV16rm = 1110,
- MOV16rr = 1111,
- MOV16rs = 1112,
- MOV16sm = 1113,
- MOV16sr = 1114,
- MOV32ao32 = 1115,
- MOV32mi = 1116,
- MOV32mr = 1117,
- MOV32o32a = 1118,
- MOV32r0 = 1119,
- MOV32ri = 1120,
- MOV32rm = 1121,
- MOV32rr = 1122,
- MOV64FSrm = 1123,
- MOV64GSrm = 1124,
- MOV64ao32 = 1125,
- MOV64ao8 = 1126,
- MOV64mi32 = 1127,
- MOV64mr = 1128,
- MOV64ms = 1129,
- MOV64o32a = 1130,
- MOV64o8a = 1131,
- MOV64ri = 1132,
- MOV64ri32 = 1133,
- MOV64ri64i32 = 1134,
- MOV64rm = 1135,
- MOV64rr = 1136,
- MOV64rs = 1137,
- MOV64sm = 1138,
- MOV64sr = 1139,
- MOV64toPQIrr = 1140,
- MOV64toSDrm = 1141,
- MOV64toSDrr = 1142,
- MOV8ao8 = 1143,
- MOV8mi = 1144,
- MOV8mr = 1145,
- MOV8mr_NOREX = 1146,
- MOV8o8a = 1147,
- MOV8r0 = 1148,
- MOV8ri = 1149,
- MOV8rm = 1150,
- MOV8rm_NOREX = 1151,
- MOV8rr = 1152,
- MOV8rr_NOREX = 1153,
- MOVAPDmr = 1154,
- MOVAPDrm = 1155,
- MOVAPDrr = 1156,
- MOVAPSmr = 1157,
- MOVAPSrm = 1158,
- MOVAPSrr = 1159,
- MOVDDUPrm = 1160,
- MOVDDUPrr = 1161,
- MOVDI2PDIrm = 1162,
- MOVDI2PDIrr = 1163,
- MOVDI2SSrm = 1164,
- MOVDI2SSrr = 1165,
- MOVDQAmr = 1166,
- MOVDQArm = 1167,
- MOVDQArr = 1168,
- MOVDQUmr = 1169,
- MOVDQUmr_Int = 1170,
- MOVDQUrm = 1171,
- MOVDQUrm_Int = 1172,
- MOVHLPSrr = 1173,
- MOVHPDmr = 1174,
- MOVHPDrm = 1175,
- MOVHPSmr = 1176,
- MOVHPSrm = 1177,
- MOVLHPSrr = 1178,
- MOVLPDmr = 1179,
- MOVLPDrm = 1180,
- MOVLPDrr = 1181,
- MOVLPSmr = 1182,
- MOVLPSrm = 1183,
- MOVLPSrr = 1184,
- MOVLQ128mr = 1185,
- MOVLSD2PDrr = 1186,
- MOVLSS2PSrr = 1187,
- MOVMSKPDrr = 1188,
- MOVMSKPSrr = 1189,
- MOVNTDQArm = 1190,
- MOVNTDQmr = 1191,
- MOVNTImr = 1192,
- MOVNTPDmr = 1193,
- MOVNTPSmr = 1194,
- MOVPC32r = 1195,
- MOVPD2SDmr = 1196,
- MOVPD2SDrr = 1197,
- MOVPDI2DImr = 1198,
- MOVPDI2DIrr = 1199,
- MOVPQI2QImr = 1200,
- MOVPQIto64rr = 1201,
- MOVPS2SSmr = 1202,
- MOVPS2SSrr = 1203,
- MOVQI2PQIrm = 1204,
- MOVSD2PDrm = 1205,
- MOVSD2PDrr = 1206,
- MOVSDmr = 1207,
- MOVSDrm = 1208,
- MOVSDrr = 1209,
- MOVSDto64mr = 1210,
- MOVSDto64rr = 1211,
- MOVSHDUPrm = 1212,
- MOVSHDUPrr = 1213,
- MOVSLDUPrm = 1214,
- MOVSLDUPrr = 1215,
- MOVSS2DImr = 1216,
- MOVSS2DIrr = 1217,
- MOVSS2PSrm = 1218,
- MOVSS2PSrr = 1219,
- MOVSSmr = 1220,
- MOVSSrm = 1221,
- MOVSSrr = 1222,
- MOVSX16rm8 = 1223,
- MOVSX16rr8 = 1224,
- MOVSX32rm16 = 1225,
- MOVSX32rm8 = 1226,
- MOVSX32rr16 = 1227,
- MOVSX32rr8 = 1228,
- MOVSX64rm16 = 1229,
- MOVSX64rm32 = 1230,
- MOVSX64rm8 = 1231,
- MOVSX64rr16 = 1232,
- MOVSX64rr32 = 1233,
- MOVSX64rr8 = 1234,
- MOVUPDmr = 1235,
- MOVUPDmr_Int = 1236,
- MOVUPDrm = 1237,
- MOVUPDrm_Int = 1238,
- MOVUPDrr = 1239,
- MOVUPSmr = 1240,
- MOVUPSmr_Int = 1241,
- MOVUPSrm = 1242,
- MOVUPSrm_Int = 1243,
- MOVUPSrr = 1244,
- MOVZDI2PDIrm = 1245,
- MOVZDI2PDIrr = 1246,
- MOVZPQILo2PQIrm = 1247,
- MOVZPQILo2PQIrr = 1248,
- MOVZQI2PQIrm = 1249,
- MOVZQI2PQIrr = 1250,
- MOVZSD2PDrm = 1251,
- MOVZSS2PSrm = 1252,
- MOVZX16rm8 = 1253,
- MOVZX16rr8 = 1254,
- MOVZX32_NOREXrm8 = 1255,
- MOVZX32_NOREXrr8 = 1256,
- MOVZX32rm16 = 1257,
- MOVZX32rm8 = 1258,
- MOVZX32rr16 = 1259,
- MOVZX32rr8 = 1260,
- MOVZX64rm16 = 1261,
- MOVZX64rm32 = 1262,
- MOVZX64rm8 = 1263,
- MOVZX64rr16 = 1264,
- MOVZX64rr32 = 1265,
- MOVZX64rr8 = 1266,
- MOV_Fp3232 = 1267,
- MOV_Fp3264 = 1268,
- MOV_Fp3280 = 1269,
- MOV_Fp6432 = 1270,
- MOV_Fp6464 = 1271,
- MOV_Fp6480 = 1272,
- MOV_Fp8032 = 1273,
- MOV_Fp8064 = 1274,
- MOV_Fp8080 = 1275,
- MPSADBWrmi = 1276,
- MPSADBWrri = 1277,
- MUL16m = 1278,
- MUL16r = 1279,
- MUL32m = 1280,
- MUL32r = 1281,
- MUL64m = 1282,
- MUL64r = 1283,
- MUL8m = 1284,
- MUL8r = 1285,
- MULPDrm = 1286,
- MULPDrr = 1287,
- MULPSrm = 1288,
- MULPSrr = 1289,
- MULSDrm = 1290,
- MULSDrm_Int = 1291,
- MULSDrr = 1292,
- MULSDrr_Int = 1293,
- MULSSrm = 1294,
- MULSSrm_Int = 1295,
- MULSSrr = 1296,
- MULSSrr_Int = 1297,
- MUL_F32m = 1298,
- MUL_F64m = 1299,
- MUL_FI16m = 1300,
- MUL_FI32m = 1301,
- MUL_FPrST0 = 1302,
- MUL_FST0r = 1303,
- MUL_Fp32 = 1304,
- MUL_Fp32m = 1305,
- MUL_Fp64 = 1306,
- MUL_Fp64m = 1307,
- MUL_Fp64m32 = 1308,
- MUL_Fp80 = 1309,
- MUL_Fp80m32 = 1310,
- MUL_Fp80m64 = 1311,
- MUL_FpI16m32 = 1312,
- MUL_FpI16m64 = 1313,
- MUL_FpI16m80 = 1314,
- MUL_FpI32m32 = 1315,
- MUL_FpI32m64 = 1316,
- MUL_FpI32m80 = 1317,
- MUL_FrST0 = 1318,
- MWAIT = 1319,
- NEG16m = 1320,
- NEG16r = 1321,
- NEG32m = 1322,
- NEG32r = 1323,
- NEG64m = 1324,
- NEG64r = 1325,
- NEG8m = 1326,
- NEG8r = 1327,
- NOOP = 1328,
- NOOPL = 1329,
- NOT16m = 1330,
- NOT16r = 1331,
- NOT32m = 1332,
- NOT32r = 1333,
- NOT64m = 1334,
- NOT64r = 1335,
- NOT8m = 1336,
- NOT8r = 1337,
- OR16i16 = 1338,
- OR16mi = 1339,
- OR16mi8 = 1340,
- OR16mr = 1341,
- OR16ri = 1342,
- OR16ri8 = 1343,
- OR16rm = 1344,
- OR16rr = 1345,
- OR32i32 = 1346,
- OR32mi = 1347,
- OR32mi8 = 1348,
- OR32mr = 1349,
- OR32ri = 1350,
- OR32ri8 = 1351,
- OR32rm = 1352,
- OR32rr = 1353,
- OR64i32 = 1354,
- OR64mi32 = 1355,
- OR64mi8 = 1356,
- OR64mr = 1357,
- OR64ri32 = 1358,
- OR64ri8 = 1359,
- OR64rm = 1360,
- OR64rr = 1361,
- OR8i8 = 1362,
- OR8mi = 1363,
- OR8mr = 1364,
- OR8ri = 1365,
- OR8rm = 1366,
- OR8rr = 1367,
- ORPDrm = 1368,
- ORPDrr = 1369,
- ORPSrm = 1370,
- ORPSrr = 1371,
- OUT16ir = 1372,
- OUT16rr = 1373,
- OUT32ir = 1374,
- OUT32rr = 1375,
- OUT8ir = 1376,
- OUT8rr = 1377,
- PABSBrm128 = 1378,
- PABSBrm64 = 1379,
- PABSBrr128 = 1380,
- PABSBrr64 = 1381,
- PABSDrm128 = 1382,
- PABSDrm64 = 1383,
- PABSDrr128 = 1384,
- PABSDrr64 = 1385,
- PABSWrm128 = 1386,
- PABSWrm64 = 1387,
- PABSWrr128 = 1388,
- PABSWrr64 = 1389,
- PACKSSDWrm = 1390,
- PACKSSDWrr = 1391,
- PACKSSWBrm = 1392,
- PACKSSWBrr = 1393,
- PACKUSDWrm = 1394,
- PACKUSDWrr = 1395,
- PACKUSWBrm = 1396,
- PACKUSWBrr = 1397,
- PADDBrm = 1398,
- PADDBrr = 1399,
- PADDDrm = 1400,
- PADDDrr = 1401,
- PADDQrm = 1402,
- PADDQrr = 1403,
- PADDSBrm = 1404,
- PADDSBrr = 1405,
- PADDSWrm = 1406,
- PADDSWrr = 1407,
- PADDUSBrm = 1408,
- PADDUSBrr = 1409,
- PADDUSWrm = 1410,
- PADDUSWrr = 1411,
- PADDWrm = 1412,
- PADDWrr = 1413,
- PALIGNR128rm = 1414,
- PALIGNR128rr = 1415,
- PALIGNR64rm = 1416,
- PALIGNR64rr = 1417,
- PANDNrm = 1418,
- PANDNrr = 1419,
- PANDrm = 1420,
- PANDrr = 1421,
- PAVGBrm = 1422,
- PAVGBrr = 1423,
- PAVGWrm = 1424,
- PAVGWrr = 1425,
- PBLENDVBrm0 = 1426,
- PBLENDVBrr0 = 1427,
- PBLENDWrmi = 1428,
- PBLENDWrri = 1429,
- PCMPEQBrm = 1430,
- PCMPEQBrr = 1431,
- PCMPEQDrm = 1432,
- PCMPEQDrr = 1433,
- PCMPEQQrm = 1434,
- PCMPEQQrr = 1435,
- PCMPEQWrm = 1436,
- PCMPEQWrr = 1437,
- PCMPESTRIArm = 1438,
- PCMPESTRIArr = 1439,
- PCMPESTRICrm = 1440,
- PCMPESTRICrr = 1441,
- PCMPESTRIOrm = 1442,
- PCMPESTRIOrr = 1443,
- PCMPESTRISrm = 1444,
- PCMPESTRISrr = 1445,
- PCMPESTRIZrm = 1446,
- PCMPESTRIZrr = 1447,
- PCMPESTRIrm = 1448,
- PCMPESTRIrr = 1449,
- PCMPESTRM128MEM = 1450,
- PCMPESTRM128REG = 1451,
- PCMPESTRM128rm = 1452,
- PCMPESTRM128rr = 1453,
- PCMPGTBrm = 1454,
- PCMPGTBrr = 1455,
- PCMPGTDrm = 1456,
- PCMPGTDrr = 1457,
- PCMPGTQrm = 1458,
- PCMPGTQrr = 1459,
- PCMPGTWrm = 1460,
- PCMPGTWrr = 1461,
- PCMPISTRIArm = 1462,
- PCMPISTRIArr = 1463,
- PCMPISTRICrm = 1464,
- PCMPISTRICrr = 1465,
- PCMPISTRIOrm = 1466,
- PCMPISTRIOrr = 1467,
- PCMPISTRISrm = 1468,
- PCMPISTRISrr = 1469,
- PCMPISTRIZrm = 1470,
- PCMPISTRIZrr = 1471,
- PCMPISTRIrm = 1472,
- PCMPISTRIrr = 1473,
- PCMPISTRM128MEM = 1474,
- PCMPISTRM128REG = 1475,
- PCMPISTRM128rm = 1476,
- PCMPISTRM128rr = 1477,
- PEXTRBmr = 1478,
- PEXTRBrr = 1479,
- PEXTRDmr = 1480,
- PEXTRDrr = 1481,
- PEXTRQmr = 1482,
- PEXTRQrr = 1483,
- PEXTRWmr = 1484,
- PEXTRWri = 1485,
- PHADDDrm128 = 1486,
- PHADDDrm64 = 1487,
- PHADDDrr128 = 1488,
- PHADDDrr64 = 1489,
- PHADDSWrm128 = 1490,
- PHADDSWrm64 = 1491,
- PHADDSWrr128 = 1492,
- PHADDSWrr64 = 1493,
- PHADDWrm128 = 1494,
- PHADDWrm64 = 1495,
- PHADDWrr128 = 1496,
- PHADDWrr64 = 1497,
- PHMINPOSUWrm128 = 1498,
- PHMINPOSUWrr128 = 1499,
- PHSUBDrm128 = 1500,
- PHSUBDrm64 = 1501,
- PHSUBDrr128 = 1502,
- PHSUBDrr64 = 1503,
- PHSUBSWrm128 = 1504,
- PHSUBSWrm64 = 1505,
- PHSUBSWrr128 = 1506,
- PHSUBSWrr64 = 1507,
- PHSUBWrm128 = 1508,
- PHSUBWrm64 = 1509,
- PHSUBWrr128 = 1510,
- PHSUBWrr64 = 1511,
- PINSRBrm = 1512,
- PINSRBrr = 1513,
- PINSRDrm = 1514,
- PINSRDrr = 1515,
- PINSRQrm = 1516,
- PINSRQrr = 1517,
- PINSRWrmi = 1518,
- PINSRWrri = 1519,
- PMADDUBSWrm128 = 1520,
- PMADDUBSWrm64 = 1521,
- PMADDUBSWrr128 = 1522,
- PMADDUBSWrr64 = 1523,
- PMADDWDrm = 1524,
- PMADDWDrr = 1525,
- PMAXSBrm = 1526,
- PMAXSBrr = 1527,
- PMAXSDrm = 1528,
- PMAXSDrr = 1529,
- PMAXSWrm = 1530,
- PMAXSWrr = 1531,
- PMAXUBrm = 1532,
- PMAXUBrr = 1533,
- PMAXUDrm = 1534,
- PMAXUDrr = 1535,
- PMAXUWrm = 1536,
- PMAXUWrr = 1537,
- PMINSBrm = 1538,
- PMINSBrr = 1539,
- PMINSDrm = 1540,
- PMINSDrr = 1541,
- PMINSWrm = 1542,
- PMINSWrr = 1543,
- PMINUBrm = 1544,
- PMINUBrr = 1545,
- PMINUDrm = 1546,
- PMINUDrr = 1547,
- PMINUWrm = 1548,
- PMINUWrr = 1549,
- PMOVMSKBrr = 1550,
- PMOVSXBDrm = 1551,
- PMOVSXBDrr = 1552,
- PMOVSXBQrm = 1553,
- PMOVSXBQrr = 1554,
- PMOVSXBWrm = 1555,
- PMOVSXBWrr = 1556,
- PMOVSXDQrm = 1557,
- PMOVSXDQrr = 1558,
- PMOVSXWDrm = 1559,
- PMOVSXWDrr = 1560,
- PMOVSXWQrm = 1561,
- PMOVSXWQrr = 1562,
- PMOVZXBDrm = 1563,
- PMOVZXBDrr = 1564,
- PMOVZXBQrm = 1565,
- PMOVZXBQrr = 1566,
- PMOVZXBWrm = 1567,
- PMOVZXBWrr = 1568,
- PMOVZXDQrm = 1569,
- PMOVZXDQrr = 1570,
- PMOVZXWDrm = 1571,
- PMOVZXWDrr = 1572,
- PMOVZXWQrm = 1573,
- PMOVZXWQrr = 1574,
- PMULDQrm = 1575,
- PMULDQrr = 1576,
- PMULHRSWrm128 = 1577,
- PMULHRSWrm64 = 1578,
- PMULHRSWrr128 = 1579,
- PMULHRSWrr64 = 1580,
- PMULHUWrm = 1581,
- PMULHUWrr = 1582,
- PMULHWrm = 1583,
- PMULHWrr = 1584,
- PMULLDrm = 1585,
- PMULLDrm_int = 1586,
- PMULLDrr = 1587,
- PMULLDrr_int = 1588,
- PMULLWrm = 1589,
- PMULLWrr = 1590,
- PMULUDQrm = 1591,
- PMULUDQrr = 1592,
- POP16r = 1593,
- POP16rmm = 1594,
- POP16rmr = 1595,
- POP32r = 1596,
- POP32rmm = 1597,
- POP32rmr = 1598,
- POP64r = 1599,
- POP64rmm = 1600,
- POP64rmr = 1601,
- POPFD = 1602,
- POPFQ = 1603,
- PORrm = 1604,
- PORrr = 1605,
- PREFETCHNTA = 1606,
- PREFETCHT0 = 1607,
- PREFETCHT1 = 1608,
- PREFETCHT2 = 1609,
- PSADBWrm = 1610,
- PSADBWrr = 1611,
- PSHUFBrm128 = 1612,
- PSHUFBrm64 = 1613,
- PSHUFBrr128 = 1614,
- PSHUFBrr64 = 1615,
- PSHUFDmi = 1616,
- PSHUFDri = 1617,
- PSHUFHWmi = 1618,
- PSHUFHWri = 1619,
- PSHUFLWmi = 1620,
- PSHUFLWri = 1621,
- PSIGNBrm128 = 1622,
- PSIGNBrm64 = 1623,
- PSIGNBrr128 = 1624,
- PSIGNBrr64 = 1625,
- PSIGNDrm128 = 1626,
- PSIGNDrm64 = 1627,
- PSIGNDrr128 = 1628,
- PSIGNDrr64 = 1629,
- PSIGNWrm128 = 1630,
- PSIGNWrm64 = 1631,
- PSIGNWrr128 = 1632,
- PSIGNWrr64 = 1633,
- PSLLDQri = 1634,
- PSLLDri = 1635,
- PSLLDrm = 1636,
- PSLLDrr = 1637,
- PSLLQri = 1638,
- PSLLQrm = 1639,
- PSLLQrr = 1640,
- PSLLWri = 1641,
- PSLLWrm = 1642,
- PSLLWrr = 1643,
- PSRADri = 1644,
- PSRADrm = 1645,
- PSRADrr = 1646,
- PSRAWri = 1647,
- PSRAWrm = 1648,
- PSRAWrr = 1649,
- PSRLDQri = 1650,
- PSRLDri = 1651,
- PSRLDrm = 1652,
- PSRLDrr = 1653,
- PSRLQri = 1654,
- PSRLQrm = 1655,
- PSRLQrr = 1656,
- PSRLWri = 1657,
- PSRLWrm = 1658,
- PSRLWrr = 1659,
- PSUBBrm = 1660,
- PSUBBrr = 1661,
- PSUBDrm = 1662,
- PSUBDrr = 1663,
- PSUBQrm = 1664,
- PSUBQrr = 1665,
- PSUBSBrm = 1666,
- PSUBSBrr = 1667,
- PSUBSWrm = 1668,
- PSUBSWrr = 1669,
- PSUBUSBrm = 1670,
- PSUBUSBrr = 1671,
- PSUBUSWrm = 1672,
- PSUBUSWrr = 1673,
- PSUBWrm = 1674,
- PSUBWrr = 1675,
- PTESTrm = 1676,
- PTESTrr = 1677,
- PUNPCKHBWrm = 1678,
- PUNPCKHBWrr = 1679,
- PUNPCKHDQrm = 1680,
- PUNPCKHDQrr = 1681,
- PUNPCKHQDQrm = 1682,
- PUNPCKHQDQrr = 1683,
- PUNPCKHWDrm = 1684,
- PUNPCKHWDrr = 1685,
- PUNPCKLBWrm = 1686,
- PUNPCKLBWrr = 1687,
- PUNPCKLDQrm = 1688,
- PUNPCKLDQrr = 1689,
- PUNPCKLQDQrm = 1690,
- PUNPCKLQDQrr = 1691,
- PUNPCKLWDrm = 1692,
- PUNPCKLWDrr = 1693,
- PUSH16r = 1694,
- PUSH16rmm = 1695,
- PUSH16rmr = 1696,
- PUSH32i16 = 1697,
- PUSH32i32 = 1698,
- PUSH32i8 = 1699,
- PUSH32r = 1700,
- PUSH32rmm = 1701,
- PUSH32rmr = 1702,
- PUSH64i16 = 1703,
- PUSH64i32 = 1704,
- PUSH64i8 = 1705,
- PUSH64r = 1706,
- PUSH64rmm = 1707,
- PUSH64rmr = 1708,
- PUSHFD = 1709,
- PUSHFQ = 1710,
- PXORrm = 1711,
- PXORrr = 1712,
- RCL16m1 = 1713,
- RCL16mCL = 1714,
- RCL16mi = 1715,
- RCL16r1 = 1716,
- RCL16rCL = 1717,
- RCL16ri = 1718,
- RCL32m1 = 1719,
- RCL32mCL = 1720,
- RCL32mi = 1721,
- RCL32r1 = 1722,
- RCL32rCL = 1723,
- RCL32ri = 1724,
- RCL64m1 = 1725,
- RCL64mCL = 1726,
- RCL64mi = 1727,
- RCL64r1 = 1728,
- RCL64rCL = 1729,
- RCL64ri = 1730,
- RCL8m1 = 1731,
- RCL8mCL = 1732,
- RCL8mi = 1733,
- RCL8r1 = 1734,
- RCL8rCL = 1735,
- RCL8ri = 1736,
- RCPPSm = 1737,
- RCPPSm_Int = 1738,
- RCPPSr = 1739,
- RCPPSr_Int = 1740,
- RCPSSm = 1741,
- RCPSSm_Int = 1742,
- RCPSSr = 1743,
- RCPSSr_Int = 1744,
- RCR16m1 = 1745,
- RCR16mCL = 1746,
- RCR16mi = 1747,
- RCR16r1 = 1748,
- RCR16rCL = 1749,
- RCR16ri = 1750,
- RCR32m1 = 1751,
- RCR32mCL = 1752,
- RCR32mi = 1753,
- RCR32r1 = 1754,
- RCR32rCL = 1755,
- RCR32ri = 1756,
- RCR64m1 = 1757,
- RCR64mCL = 1758,
- RCR64mi = 1759,
- RCR64r1 = 1760,
- RCR64rCL = 1761,
- RCR64ri = 1762,
- RCR8m1 = 1763,
- RCR8mCL = 1764,
- RCR8mi = 1765,
- RCR8r1 = 1766,
- RCR8rCL = 1767,
- RCR8ri = 1768,
- RDTSC = 1769,
- REP_MOVSB = 1770,
- REP_MOVSD = 1771,
- REP_MOVSQ = 1772,
- REP_MOVSW = 1773,
- REP_STOSB = 1774,
- REP_STOSD = 1775,
- REP_STOSQ = 1776,
- REP_STOSW = 1777,
- RET = 1778,
- RETI = 1779,
- ROL16m1 = 1780,
- ROL16mCL = 1781,
- ROL16mi = 1782,
- ROL16r1 = 1783,
- ROL16rCL = 1784,
- ROL16ri = 1785,
- ROL32m1 = 1786,
- ROL32mCL = 1787,
- ROL32mi = 1788,
- ROL32r1 = 1789,
- ROL32rCL = 1790,
- ROL32ri = 1791,
- ROL64m1 = 1792,
- ROL64mCL = 1793,
- ROL64mi = 1794,
- ROL64r1 = 1795,
- ROL64rCL = 1796,
- ROL64ri = 1797,
- ROL8m1 = 1798,
- ROL8mCL = 1799,
- ROL8mi = 1800,
- ROL8r1 = 1801,
- ROL8rCL = 1802,
- ROL8ri = 1803,
- ROR16m1 = 1804,
- ROR16mCL = 1805,
- ROR16mi = 1806,
- ROR16r1 = 1807,
- ROR16rCL = 1808,
- ROR16ri = 1809,
- ROR32m1 = 1810,
- ROR32mCL = 1811,
- ROR32mi = 1812,
- ROR32r1 = 1813,
- ROR32rCL = 1814,
- ROR32ri = 1815,
- ROR64m1 = 1816,
- ROR64mCL = 1817,
- ROR64mi = 1818,
- ROR64r1 = 1819,
- ROR64rCL = 1820,
- ROR64ri = 1821,
- ROR8m1 = 1822,
- ROR8mCL = 1823,
- ROR8mi = 1824,
- ROR8r1 = 1825,
- ROR8rCL = 1826,
- ROR8ri = 1827,
- ROUNDPDm_Int = 1828,
- ROUNDPDr_Int = 1829,
- ROUNDPSm_Int = 1830,
- ROUNDPSr_Int = 1831,
- ROUNDSDm_Int = 1832,
- ROUNDSDr_Int = 1833,
- ROUNDSSm_Int = 1834,
- ROUNDSSr_Int = 1835,
- RSQRTPSm = 1836,
- RSQRTPSm_Int = 1837,
- RSQRTPSr = 1838,
- RSQRTPSr_Int = 1839,
- RSQRTSSm = 1840,
- RSQRTSSm_Int = 1841,
- RSQRTSSr = 1842,
- RSQRTSSr_Int = 1843,
- SAHF = 1844,
- SAR16m1 = 1845,
- SAR16mCL = 1846,
- SAR16mi = 1847,
- SAR16r1 = 1848,
- SAR16rCL = 1849,
- SAR16ri = 1850,
- SAR32m1 = 1851,
- SAR32mCL = 1852,
- SAR32mi = 1853,
- SAR32r1 = 1854,
- SAR32rCL = 1855,
- SAR32ri = 1856,
- SAR64m1 = 1857,
- SAR64mCL = 1858,
- SAR64mi = 1859,
- SAR64r1 = 1860,
- SAR64rCL = 1861,
- SAR64ri = 1862,
- SAR8m1 = 1863,
- SAR8mCL = 1864,
- SAR8mi = 1865,
- SAR8r1 = 1866,
- SAR8rCL = 1867,
- SAR8ri = 1868,
- SBB16i16 = 1869,
- SBB16mi = 1870,
- SBB16mi8 = 1871,
- SBB16mr = 1872,
- SBB16ri = 1873,
- SBB16ri8 = 1874,
- SBB16rm = 1875,
- SBB16rr = 1876,
- SBB32i32 = 1877,
- SBB32mi = 1878,
- SBB32mi8 = 1879,
- SBB32mr = 1880,
- SBB32ri = 1881,
- SBB32ri8 = 1882,
- SBB32rm = 1883,
- SBB32rr = 1884,
- SBB64i32 = 1885,
- SBB64mi32 = 1886,
- SBB64mi8 = 1887,
- SBB64mr = 1888,
- SBB64ri32 = 1889,
- SBB64ri8 = 1890,
- SBB64rm = 1891,
- SBB64rr = 1892,
- SBB8i8 = 1893,
- SBB8mi = 1894,
- SBB8mr = 1895,
- SBB8ri = 1896,
- SBB8rm = 1897,
- SBB8rr = 1898,
- SCAS16 = 1899,
- SCAS32 = 1900,
- SCAS64 = 1901,
- SCAS8 = 1902,
- SETAEm = 1903,
- SETAEr = 1904,
- SETAm = 1905,
- SETAr = 1906,
- SETBEm = 1907,
- SETBEr = 1908,
- SETB_C16r = 1909,
- SETB_C32r = 1910,
- SETB_C64r = 1911,
- SETB_C8r = 1912,
- SETBm = 1913,
- SETBr = 1914,
- SETEm = 1915,
- SETEr = 1916,
- SETGEm = 1917,
- SETGEr = 1918,
- SETGm = 1919,
- SETGr = 1920,
- SETLEm = 1921,
- SETLEr = 1922,
- SETLm = 1923,
- SETLr = 1924,
- SETNEm = 1925,
- SETNEr = 1926,
- SETNOm = 1927,
- SETNOr = 1928,
- SETNPm = 1929,
- SETNPr = 1930,
- SETNSm = 1931,
- SETNSr = 1932,
- SETOm = 1933,
- SETOr = 1934,
- SETPm = 1935,
- SETPr = 1936,
- SETSm = 1937,
- SETSr = 1938,
- SFENCE = 1939,
- SHL16m1 = 1940,
- SHL16mCL = 1941,
- SHL16mi = 1942,
- SHL16r1 = 1943,
- SHL16rCL = 1944,
- SHL16ri = 1945,
- SHL32m1 = 1946,
- SHL32mCL = 1947,
- SHL32mi = 1948,
- SHL32r1 = 1949,
- SHL32rCL = 1950,
- SHL32ri = 1951,
- SHL64m1 = 1952,
- SHL64mCL = 1953,
- SHL64mi = 1954,
- SHL64r1 = 1955,
- SHL64rCL = 1956,
- SHL64ri = 1957,
- SHL8m1 = 1958,
- SHL8mCL = 1959,
- SHL8mi = 1960,
- SHL8r1 = 1961,
- SHL8rCL = 1962,
- SHL8ri = 1963,
- SHLD16mrCL = 1964,
- SHLD16mri8 = 1965,
- SHLD16rrCL = 1966,
- SHLD16rri8 = 1967,
- SHLD32mrCL = 1968,
- SHLD32mri8 = 1969,
- SHLD32rrCL = 1970,
- SHLD32rri8 = 1971,
- SHLD64mrCL = 1972,
- SHLD64mri8 = 1973,
- SHLD64rrCL = 1974,
- SHLD64rri8 = 1975,
- SHR16m1 = 1976,
- SHR16mCL = 1977,
- SHR16mi = 1978,
- SHR16r1 = 1979,
- SHR16rCL = 1980,
- SHR16ri = 1981,
- SHR32m1 = 1982,
- SHR32mCL = 1983,
- SHR32mi = 1984,
- SHR32r1 = 1985,
- SHR32rCL = 1986,
- SHR32ri = 1987,
- SHR64m1 = 1988,
- SHR64mCL = 1989,
- SHR64mi = 1990,
- SHR64r1 = 1991,
- SHR64rCL = 1992,
- SHR64ri = 1993,
- SHR8m1 = 1994,
- SHR8mCL = 1995,
- SHR8mi = 1996,
- SHR8r1 = 1997,
- SHR8rCL = 1998,
- SHR8ri = 1999,
- SHRD16mrCL = 2000,
- SHRD16mri8 = 2001,
- SHRD16rrCL = 2002,
- SHRD16rri8 = 2003,
- SHRD32mrCL = 2004,
- SHRD32mri8 = 2005,
- SHRD32rrCL = 2006,
- SHRD32rri8 = 2007,
- SHRD64mrCL = 2008,
- SHRD64mri8 = 2009,
- SHRD64rrCL = 2010,
- SHRD64rri8 = 2011,
- SHUFPDrmi = 2012,
- SHUFPDrri = 2013,
- SHUFPSrmi = 2014,
- SHUFPSrri = 2015,
- SIN_F = 2016,
- SIN_Fp32 = 2017,
- SIN_Fp64 = 2018,
- SIN_Fp80 = 2019,
- SQRTPDm = 2020,
- SQRTPDm_Int = 2021,
- SQRTPDr = 2022,
- SQRTPDr_Int = 2023,
- SQRTPSm = 2024,
- SQRTPSm_Int = 2025,
- SQRTPSr = 2026,
- SQRTPSr_Int = 2027,
- SQRTSDm = 2028,
- SQRTSDm_Int = 2029,
- SQRTSDr = 2030,
- SQRTSDr_Int = 2031,
- SQRTSSm = 2032,
- SQRTSSm_Int = 2033,
- SQRTSSr = 2034,
- SQRTSSr_Int = 2035,
- SQRT_F = 2036,
- SQRT_Fp32 = 2037,
- SQRT_Fp64 = 2038,
- SQRT_Fp80 = 2039,
- STMXCSR = 2040,
- ST_F32m = 2041,
- ST_F64m = 2042,
- ST_FP32m = 2043,
- ST_FP64m = 2044,
- ST_FP80m = 2045,
- ST_FPrr = 2046,
- ST_Fp32m = 2047,
- ST_Fp64m = 2048,
- ST_Fp64m32 = 2049,
- ST_Fp80m32 = 2050,
- ST_Fp80m64 = 2051,
- ST_FpP32m = 2052,
- ST_FpP64m = 2053,
- ST_FpP64m32 = 2054,
- ST_FpP80m = 2055,
- ST_FpP80m32 = 2056,
- ST_FpP80m64 = 2057,
- ST_Frr = 2058,
- SUB16i16 = 2059,
- SUB16mi = 2060,
- SUB16mi8 = 2061,
- SUB16mr = 2062,
- SUB16ri = 2063,
- SUB16ri8 = 2064,
- SUB16rm = 2065,
- SUB16rr = 2066,
- SUB32i32 = 2067,
- SUB32mi = 2068,
- SUB32mi8 = 2069,
- SUB32mr = 2070,
- SUB32ri = 2071,
- SUB32ri8 = 2072,
- SUB32rm = 2073,
- SUB32rr = 2074,
- SUB64i32 = 2075,
- SUB64mi32 = 2076,
- SUB64mi8 = 2077,
- SUB64mr = 2078,
- SUB64ri32 = 2079,
- SUB64ri8 = 2080,
- SUB64rm = 2081,
- SUB64rr = 2082,
- SUB8i8 = 2083,
- SUB8mi = 2084,
- SUB8mr = 2085,
- SUB8ri = 2086,
- SUB8rm = 2087,
- SUB8rr = 2088,
- SUBPDrm = 2089,
- SUBPDrr = 2090,
- SUBPSrm = 2091,
- SUBPSrr = 2092,
- SUBR_F32m = 2093,
- SUBR_F64m = 2094,
- SUBR_FI16m = 2095,
- SUBR_FI32m = 2096,
- SUBR_FPrST0 = 2097,
- SUBR_FST0r = 2098,
- SUBR_Fp32m = 2099,
- SUBR_Fp64m = 2100,
- SUBR_Fp64m32 = 2101,
- SUBR_Fp80m32 = 2102,
- SUBR_Fp80m64 = 2103,
- SUBR_FpI16m32 = 2104,
- SUBR_FpI16m64 = 2105,
- SUBR_FpI16m80 = 2106,
- SUBR_FpI32m32 = 2107,
- SUBR_FpI32m64 = 2108,
- SUBR_FpI32m80 = 2109,
- SUBR_FrST0 = 2110,
- SUBSDrm = 2111,
- SUBSDrm_Int = 2112,
- SUBSDrr = 2113,
- SUBSDrr_Int = 2114,
- SUBSSrm = 2115,
- SUBSSrm_Int = 2116,
- SUBSSrr = 2117,
- SUBSSrr_Int = 2118,
- SUB_F32m = 2119,
- SUB_F64m = 2120,
- SUB_FI16m = 2121,
- SUB_FI32m = 2122,
- SUB_FPrST0 = 2123,
- SUB_FST0r = 2124,
- SUB_Fp32 = 2125,
- SUB_Fp32m = 2126,
- SUB_Fp64 = 2127,
- SUB_Fp64m = 2128,
- SUB_Fp64m32 = 2129,
- SUB_Fp80 = 2130,
- SUB_Fp80m32 = 2131,
- SUB_Fp80m64 = 2132,
- SUB_FpI16m32 = 2133,
- SUB_FpI16m64 = 2134,
- SUB_FpI16m80 = 2135,
- SUB_FpI32m32 = 2136,
- SUB_FpI32m64 = 2137,
- SUB_FpI32m80 = 2138,
- SUB_FrST0 = 2139,
- SYSCALL = 2140,
- SYSENTER = 2141,
- SYSEXIT = 2142,
- SYSEXIT64 = 2143,
- SYSRET = 2144,
- TAILJMPd = 2145,
- TAILJMPm = 2146,
- TAILJMPr = 2147,
- TAILJMPr64 = 2148,
- TCRETURNdi = 2149,
- TCRETURNdi64 = 2150,
- TCRETURNri = 2151,
- TCRETURNri64 = 2152,
- TEST16i16 = 2153,
- TEST16mi = 2154,
- TEST16ri = 2155,
- TEST16rm = 2156,
- TEST16rr = 2157,
- TEST32i32 = 2158,
- TEST32mi = 2159,
- TEST32ri = 2160,
- TEST32rm = 2161,
- TEST32rr = 2162,
- TEST64i32 = 2163,
- TEST64mi32 = 2164,
- TEST64ri32 = 2165,
- TEST64rm = 2166,
- TEST64rr = 2167,
- TEST8i8 = 2168,
- TEST8mi = 2169,
- TEST8ri = 2170,
- TEST8rm = 2171,
- TEST8rr = 2172,
- TLS_addr32 = 2173,
- TLS_addr64 = 2174,
- TRAP = 2175,
- TST_F = 2176,
- TST_Fp32 = 2177,
- TST_Fp64 = 2178,
- TST_Fp80 = 2179,
- UCOMISDrm = 2180,
- UCOMISDrr = 2181,
- UCOMISSrm = 2182,
- UCOMISSrr = 2183,
- UCOM_FIPr = 2184,
- UCOM_FIr = 2185,
- UCOM_FPPr = 2186,
- UCOM_FPr = 2187,
- UCOM_FpIr32 = 2188,
- UCOM_FpIr64 = 2189,
- UCOM_FpIr80 = 2190,
- UCOM_Fpr32 = 2191,
- UCOM_Fpr64 = 2192,
- UCOM_Fpr80 = 2193,
- UCOM_Fr = 2194,
- UNPCKHPDrm = 2195,
- UNPCKHPDrr = 2196,
- UNPCKHPSrm = 2197,
- UNPCKHPSrr = 2198,
- UNPCKLPDrm = 2199,
- UNPCKLPDrr = 2200,
- UNPCKLPSrm = 2201,
- UNPCKLPSrr = 2202,
- VASTART_SAVE_XMM_REGS = 2203,
- V_SET0 = 2204,
- V_SETALLONES = 2205,
- WAIT = 2206,
- WINCALL64m = 2207,
- WINCALL64pcrel32 = 2208,
- WINCALL64r = 2209,
- XCHG16rm = 2210,
- XCHG32rm = 2211,
- XCHG64rm = 2212,
- XCHG8rm = 2213,
- XCH_F = 2214,
- XOR16i16 = 2215,
- XOR16mi = 2216,
- XOR16mi8 = 2217,
- XOR16mr = 2218,
- XOR16ri = 2219,
- XOR16ri8 = 2220,
- XOR16rm = 2221,
- XOR16rr = 2222,
- XOR32i32 = 2223,
- XOR32mi = 2224,
- XOR32mi8 = 2225,
- XOR32mr = 2226,
- XOR32ri = 2227,
- XOR32ri8 = 2228,
- XOR32rm = 2229,
- XOR32rr = 2230,
- XOR64i32 = 2231,
- XOR64mi32 = 2232,
- XOR64mi8 = 2233,
- XOR64mr = 2234,
- XOR64ri32 = 2235,
- XOR64ri8 = 2236,
- XOR64rm = 2237,
- XOR64rr = 2238,
- XOR8i8 = 2239,
- XOR8mi = 2240,
- XOR8mr = 2241,
- XOR8ri = 2242,
- XOR8rm = 2243,
- XOR8rr = 2244,
- XORPDrm = 2245,
- XORPDrr = 2246,
- XORPSrm = 2247,
- XORPSrr = 2248,
- INSTRUCTION_LIST_END = 2249
+ ADC16rr_REV = 23,
+ ADC32i32 = 24,
+ ADC32mi = 25,
+ ADC32mi8 = 26,
+ ADC32mr = 27,
+ ADC32ri = 28,
+ ADC32ri8 = 29,
+ ADC32rm = 30,
+ ADC32rr = 31,
+ ADC32rr_REV = 32,
+ ADC64i32 = 33,
+ ADC64mi32 = 34,
+ ADC64mi8 = 35,
+ ADC64mr = 36,
+ ADC64ri32 = 37,
+ ADC64ri8 = 38,
+ ADC64rm = 39,
+ ADC64rr = 40,
+ ADC64rr_REV = 41,
+ ADC8i8 = 42,
+ ADC8mi = 43,
+ ADC8mr = 44,
+ ADC8ri = 45,
+ ADC8rm = 46,
+ ADC8rr = 47,
+ ADC8rr_REV = 48,
+ ADD16i16 = 49,
+ ADD16mi = 50,
+ ADD16mi8 = 51,
+ ADD16mr = 52,
+ ADD16mrmrr = 53,
+ ADD16ri = 54,
+ ADD16ri8 = 55,
+ ADD16rm = 56,
+ ADD16rr = 57,
+ ADD32i32 = 58,
+ ADD32mi = 59,
+ ADD32mi8 = 60,
+ ADD32mr = 61,
+ ADD32mrmrr = 62,
+ ADD32ri = 63,
+ ADD32ri8 = 64,
+ ADD32rm = 65,
+ ADD32rr = 66,
+ ADD64i32 = 67,
+ ADD64mi32 = 68,
+ ADD64mi8 = 69,
+ ADD64mr = 70,
+ ADD64mrmrr = 71,
+ ADD64ri32 = 72,
+ ADD64ri8 = 73,
+ ADD64rm = 74,
+ ADD64rr = 75,
+ ADD8i8 = 76,
+ ADD8mi = 77,
+ ADD8mr = 78,
+ ADD8mrmrr = 79,
+ ADD8ri = 80,
+ ADD8rm = 81,
+ ADD8rr = 82,
+ ADDPDrm = 83,
+ ADDPDrr = 84,
+ ADDPSrm = 85,
+ ADDPSrr = 86,
+ ADDSDrm = 87,
+ ADDSDrm_Int = 88,
+ ADDSDrr = 89,
+ ADDSDrr_Int = 90,
+ ADDSSrm = 91,
+ ADDSSrm_Int = 92,
+ ADDSSrr = 93,
+ ADDSSrr_Int = 94,
+ ADDSUBPDrm = 95,
+ ADDSUBPDrr = 96,
+ ADDSUBPSrm = 97,
+ ADDSUBPSrr = 98,
+ ADD_F32m = 99,
+ ADD_F64m = 100,
+ ADD_FI16m = 101,
+ ADD_FI32m = 102,
+ ADD_FPrST0 = 103,
+ ADD_FST0r = 104,
+ ADD_Fp32 = 105,
+ ADD_Fp32m = 106,
+ ADD_Fp64 = 107,
+ ADD_Fp64m = 108,
+ ADD_Fp64m32 = 109,
+ ADD_Fp80 = 110,
+ ADD_Fp80m32 = 111,
+ ADD_Fp80m64 = 112,
+ ADD_FpI16m32 = 113,
+ ADD_FpI16m64 = 114,
+ ADD_FpI16m80 = 115,
+ ADD_FpI32m32 = 116,
+ ADD_FpI32m64 = 117,
+ ADD_FpI32m80 = 118,
+ ADD_FrST0 = 119,
+ ADJCALLSTACKDOWN32 = 120,
+ ADJCALLSTACKDOWN64 = 121,
+ ADJCALLSTACKUP32 = 122,
+ ADJCALLSTACKUP64 = 123,
+ AND16i16 = 124,
+ AND16mi = 125,
+ AND16mi8 = 126,
+ AND16mr = 127,
+ AND16ri = 128,
+ AND16ri8 = 129,
+ AND16rm = 130,
+ AND16rr = 131,
+ AND16rr_REV = 132,
+ AND32i32 = 133,
+ AND32mi = 134,
+ AND32mi8 = 135,
+ AND32mr = 136,
+ AND32ri = 137,
+ AND32ri8 = 138,
+ AND32rm = 139,
+ AND32rr = 140,
+ AND32rr_REV = 141,
+ AND64i32 = 142,
+ AND64mi32 = 143,
+ AND64mi8 = 144,
+ AND64mr = 145,
+ AND64ri32 = 146,
+ AND64ri8 = 147,
+ AND64rm = 148,
+ AND64rr = 149,
+ AND64rr_REV = 150,
+ AND8i8 = 151,
+ AND8mi = 152,
+ AND8mr = 153,
+ AND8ri = 154,
+ AND8rm = 155,
+ AND8rr = 156,
+ AND8rr_REV = 157,
+ ANDNPDrm = 158,
+ ANDNPDrr = 159,
+ ANDNPSrm = 160,
+ ANDNPSrr = 161,
+ ANDPDrm = 162,
+ ANDPDrr = 163,
+ ANDPSrm = 164,
+ ANDPSrr = 165,
+ ATOMADD6432 = 166,
+ ATOMAND16 = 167,
+ ATOMAND32 = 168,
+ ATOMAND64 = 169,
+ ATOMAND6432 = 170,
+ ATOMAND8 = 171,
+ ATOMMAX16 = 172,
+ ATOMMAX32 = 173,
+ ATOMMAX64 = 174,
+ ATOMMIN16 = 175,
+ ATOMMIN32 = 176,
+ ATOMMIN64 = 177,
+ ATOMNAND16 = 178,
+ ATOMNAND32 = 179,
+ ATOMNAND64 = 180,
+ ATOMNAND6432 = 181,
+ ATOMNAND8 = 182,
+ ATOMOR16 = 183,
+ ATOMOR32 = 184,
+ ATOMOR64 = 185,
+ ATOMOR6432 = 186,
+ ATOMOR8 = 187,
+ ATOMSUB6432 = 188,
+ ATOMSWAP6432 = 189,
+ ATOMUMAX16 = 190,
+ ATOMUMAX32 = 191,
+ ATOMUMAX64 = 192,
+ ATOMUMIN16 = 193,
+ ATOMUMIN32 = 194,
+ ATOMUMIN64 = 195,
+ ATOMXOR16 = 196,
+ ATOMXOR32 = 197,
+ ATOMXOR64 = 198,
+ ATOMXOR6432 = 199,
+ ATOMXOR8 = 200,
+ BLENDPDrmi = 201,
+ BLENDPDrri = 202,
+ BLENDPSrmi = 203,
+ BLENDPSrri = 204,
+ BLENDVPDrm0 = 205,
+ BLENDVPDrr0 = 206,
+ BLENDVPSrm0 = 207,
+ BLENDVPSrr0 = 208,
+ BSF16rm = 209,
+ BSF16rr = 210,
+ BSF32rm = 211,
+ BSF32rr = 212,
+ BSF64rm = 213,
+ BSF64rr = 214,
+ BSR16rm = 215,
+ BSR16rr = 216,
+ BSR32rm = 217,
+ BSR32rr = 218,
+ BSR64rm = 219,
+ BSR64rr = 220,
+ BSWAP32r = 221,
+ BSWAP64r = 222,
+ BT16mi8 = 223,
+ BT16mr = 224,
+ BT16ri8 = 225,
+ BT16rr = 226,
+ BT32mi8 = 227,
+ BT32mr = 228,
+ BT32ri8 = 229,
+ BT32rr = 230,
+ BT64mi8 = 231,
+ BT64mr = 232,
+ BT64ri8 = 233,
+ BT64rr = 234,
+ BTC16mi8 = 235,
+ BTC16mr = 236,
+ BTC16ri8 = 237,
+ BTC16rr = 238,
+ BTC32mi8 = 239,
+ BTC32mr = 240,
+ BTC32ri8 = 241,
+ BTC32rr = 242,
+ BTC64mi8 = 243,
+ BTC64mr = 244,
+ BTC64ri8 = 245,
+ BTC64rr = 246,
+ BTR16mi8 = 247,
+ BTR16mr = 248,
+ BTR16ri8 = 249,
+ BTR16rr = 250,
+ BTR32mi8 = 251,
+ BTR32mr = 252,
+ BTR32ri8 = 253,
+ BTR32rr = 254,
+ BTR64mi8 = 255,
+ BTR64mr = 256,
+ BTR64ri8 = 257,
+ BTR64rr = 258,
+ BTS16mi8 = 259,
+ BTS16mr = 260,
+ BTS16ri8 = 261,
+ BTS16rr = 262,
+ BTS32mi8 = 263,
+ BTS32mr = 264,
+ BTS32ri8 = 265,
+ BTS32rr = 266,
+ BTS64mi8 = 267,
+ BTS64mr = 268,
+ BTS64ri8 = 269,
+ BTS64rr = 270,
+ CALL32m = 271,
+ CALL32r = 272,
+ CALL64m = 273,
+ CALL64pcrel32 = 274,
+ CALL64r = 275,
+ CALLpcrel32 = 276,
+ CBW = 277,
+ CDQ = 278,
+ CDQE = 279,
+ CHS_F = 280,
+ CHS_Fp32 = 281,
+ CHS_Fp64 = 282,
+ CHS_Fp80 = 283,
+ CLC = 284,
+ CLD = 285,
+ CLFLUSH = 286,
+ CLI = 287,
+ CLTS = 288,
+ CMC = 289,
+ CMOVA16rm = 290,
+ CMOVA16rr = 291,
+ CMOVA32rm = 292,
+ CMOVA32rr = 293,
+ CMOVA64rm = 294,
+ CMOVA64rr = 295,
+ CMOVAE16rm = 296,
+ CMOVAE16rr = 297,
+ CMOVAE32rm = 298,
+ CMOVAE32rr = 299,
+ CMOVAE64rm = 300,
+ CMOVAE64rr = 301,
+ CMOVB16rm = 302,
+ CMOVB16rr = 303,
+ CMOVB32rm = 304,
+ CMOVB32rr = 305,
+ CMOVB64rm = 306,
+ CMOVB64rr = 307,
+ CMOVBE16rm = 308,
+ CMOVBE16rr = 309,
+ CMOVBE32rm = 310,
+ CMOVBE32rr = 311,
+ CMOVBE64rm = 312,
+ CMOVBE64rr = 313,
+ CMOVBE_F = 314,
+ CMOVBE_Fp32 = 315,
+ CMOVBE_Fp64 = 316,
+ CMOVBE_Fp80 = 317,
+ CMOVB_F = 318,
+ CMOVB_Fp32 = 319,
+ CMOVB_Fp64 = 320,
+ CMOVB_Fp80 = 321,
+ CMOVE16rm = 322,
+ CMOVE16rr = 323,
+ CMOVE32rm = 324,
+ CMOVE32rr = 325,
+ CMOVE64rm = 326,
+ CMOVE64rr = 327,
+ CMOVE_F = 328,
+ CMOVE_Fp32 = 329,
+ CMOVE_Fp64 = 330,
+ CMOVE_Fp80 = 331,
+ CMOVG16rm = 332,
+ CMOVG16rr = 333,
+ CMOVG32rm = 334,
+ CMOVG32rr = 335,
+ CMOVG64rm = 336,
+ CMOVG64rr = 337,
+ CMOVGE16rm = 338,
+ CMOVGE16rr = 339,
+ CMOVGE32rm = 340,
+ CMOVGE32rr = 341,
+ CMOVGE64rm = 342,
+ CMOVGE64rr = 343,
+ CMOVL16rm = 344,
+ CMOVL16rr = 345,
+ CMOVL32rm = 346,
+ CMOVL32rr = 347,
+ CMOVL64rm = 348,
+ CMOVL64rr = 349,
+ CMOVLE16rm = 350,
+ CMOVLE16rr = 351,
+ CMOVLE32rm = 352,
+ CMOVLE32rr = 353,
+ CMOVLE64rm = 354,
+ CMOVLE64rr = 355,
+ CMOVNBE_F = 356,
+ CMOVNBE_Fp32 = 357,
+ CMOVNBE_Fp64 = 358,
+ CMOVNBE_Fp80 = 359,
+ CMOVNB_F = 360,
+ CMOVNB_Fp32 = 361,
+ CMOVNB_Fp64 = 362,
+ CMOVNB_Fp80 = 363,
+ CMOVNE16rm = 364,
+ CMOVNE16rr = 365,
+ CMOVNE32rm = 366,
+ CMOVNE32rr = 367,
+ CMOVNE64rm = 368,
+ CMOVNE64rr = 369,
+ CMOVNE_F = 370,
+ CMOVNE_Fp32 = 371,
+ CMOVNE_Fp64 = 372,
+ CMOVNE_Fp80 = 373,
+ CMOVNO16rm = 374,
+ CMOVNO16rr = 375,
+ CMOVNO32rm = 376,
+ CMOVNO32rr = 377,
+ CMOVNO64rm = 378,
+ CMOVNO64rr = 379,
+ CMOVNP16rm = 380,
+ CMOVNP16rr = 381,
+ CMOVNP32rm = 382,
+ CMOVNP32rr = 383,
+ CMOVNP64rm = 384,
+ CMOVNP64rr = 385,
+ CMOVNP_F = 386,
+ CMOVNP_Fp32 = 387,
+ CMOVNP_Fp64 = 388,
+ CMOVNP_Fp80 = 389,
+ CMOVNS16rm = 390,
+ CMOVNS16rr = 391,
+ CMOVNS32rm = 392,
+ CMOVNS32rr = 393,
+ CMOVNS64rm = 394,
+ CMOVNS64rr = 395,
+ CMOVO16rm = 396,
+ CMOVO16rr = 397,
+ CMOVO32rm = 398,
+ CMOVO32rr = 399,
+ CMOVO64rm = 400,
+ CMOVO64rr = 401,
+ CMOVP16rm = 402,
+ CMOVP16rr = 403,
+ CMOVP32rm = 404,
+ CMOVP32rr = 405,
+ CMOVP64rm = 406,
+ CMOVP64rr = 407,
+ CMOVP_F = 408,
+ CMOVP_Fp32 = 409,
+ CMOVP_Fp64 = 410,
+ CMOVP_Fp80 = 411,
+ CMOVS16rm = 412,
+ CMOVS16rr = 413,
+ CMOVS32rm = 414,
+ CMOVS32rr = 415,
+ CMOVS64rm = 416,
+ CMOVS64rr = 417,
+ CMOV_FR32 = 418,
+ CMOV_FR64 = 419,
+ CMOV_GR8 = 420,
+ CMOV_V1I64 = 421,
+ CMOV_V2F64 = 422,
+ CMOV_V2I64 = 423,
+ CMOV_V4F32 = 424,
+ CMP16i16 = 425,
+ CMP16mi = 426,
+ CMP16mi8 = 427,
+ CMP16mr = 428,
+ CMP16mrmrr = 429,
+ CMP16ri = 430,
+ CMP16ri8 = 431,
+ CMP16rm = 432,
+ CMP16rr = 433,
+ CMP32i32 = 434,
+ CMP32mi = 435,
+ CMP32mi8 = 436,
+ CMP32mr = 437,
+ CMP32mrmrr = 438,
+ CMP32ri = 439,
+ CMP32ri8 = 440,
+ CMP32rm = 441,
+ CMP32rr = 442,
+ CMP64i32 = 443,
+ CMP64mi32 = 444,
+ CMP64mi8 = 445,
+ CMP64mr = 446,
+ CMP64mrmrr = 447,
+ CMP64ri32 = 448,
+ CMP64ri8 = 449,
+ CMP64rm = 450,
+ CMP64rr = 451,
+ CMP8i8 = 452,
+ CMP8mi = 453,
+ CMP8mr = 454,
+ CMP8mrmrr = 455,
+ CMP8ri = 456,
+ CMP8rm = 457,
+ CMP8rr = 458,
+ CMPPDrmi = 459,
+ CMPPDrri = 460,
+ CMPPSrmi = 461,
+ CMPPSrri = 462,
+ CMPS16 = 463,
+ CMPS32 = 464,
+ CMPS64 = 465,
+ CMPS8 = 466,
+ CMPSDrm = 467,
+ CMPSDrr = 468,
+ CMPSSrm = 469,
+ CMPSSrr = 470,
+ CMPXCHG16B = 471,
+ CMPXCHG16rm = 472,
+ CMPXCHG16rr = 473,
+ CMPXCHG32rm = 474,
+ CMPXCHG32rr = 475,
+ CMPXCHG64rm = 476,
+ CMPXCHG64rr = 477,
+ CMPXCHG8B = 478,
+ CMPXCHG8rm = 479,
+ CMPXCHG8rr = 480,
+ COMISDrm = 481,
+ COMISDrr = 482,
+ COMISSrm = 483,
+ COMISSrr = 484,
+ COMP_FST0r = 485,
+ COM_FIPr = 486,
+ COM_FIr = 487,
+ COM_FST0r = 488,
+ COS_F = 489,
+ COS_Fp32 = 490,
+ COS_Fp64 = 491,
+ COS_Fp80 = 492,
+ CPUID = 493,
+ CQO = 494,
+ CRC32m16 = 495,
+ CRC32m32 = 496,
+ CRC32m8 = 497,
+ CRC32r16 = 498,
+ CRC32r32 = 499,
+ CRC32r8 = 500,
+ CRC64m64 = 501,
+ CRC64r64 = 502,
+ CVTDQ2PDrm = 503,
+ CVTDQ2PDrr = 504,
+ CVTDQ2PSrm = 505,
+ CVTDQ2PSrr = 506,
+ CVTPD2DQrm = 507,
+ CVTPD2DQrr = 508,
+ CVTPD2PSrm = 509,
+ CVTPD2PSrr = 510,
+ CVTPS2DQrm = 511,
+ CVTPS2DQrr = 512,
+ CVTPS2PDrm = 513,
+ CVTPS2PDrr = 514,
+ CVTSD2SI64rm = 515,
+ CVTSD2SI64rr = 516,
+ CVTSD2SSrm = 517,
+ CVTSD2SSrr = 518,
+ CVTSI2SD64rm = 519,
+ CVTSI2SD64rr = 520,
+ CVTSI2SDrm = 521,
+ CVTSI2SDrr = 522,
+ CVTSI2SS64rm = 523,
+ CVTSI2SS64rr = 524,
+ CVTSI2SSrm = 525,
+ CVTSI2SSrr = 526,
+ CVTSS2SDrm = 527,
+ CVTSS2SDrr = 528,
+ CVTSS2SI64rm = 529,
+ CVTSS2SI64rr = 530,
+ CVTSS2SIrm = 531,
+ CVTSS2SIrr = 532,
+ CVTTPS2DQrm = 533,
+ CVTTPS2DQrr = 534,
+ CVTTSD2SI64rm = 535,
+ CVTTSD2SI64rr = 536,
+ CVTTSD2SIrm = 537,
+ CVTTSD2SIrr = 538,
+ CVTTSS2SI64rm = 539,
+ CVTTSS2SI64rr = 540,
+ CVTTSS2SIrm = 541,
+ CVTTSS2SIrr = 542,
+ CWD = 543,
+ CWDE = 544,
+ DEC16m = 545,
+ DEC16r = 546,
+ DEC32m = 547,
+ DEC32r = 548,
+ DEC64_16m = 549,
+ DEC64_16r = 550,
+ DEC64_32m = 551,
+ DEC64_32r = 552,
+ DEC64m = 553,
+ DEC64r = 554,
+ DEC8m = 555,
+ DEC8r = 556,
+ DIV16m = 557,
+ DIV16r = 558,
+ DIV32m = 559,
+ DIV32r = 560,
+ DIV64m = 561,
+ DIV64r = 562,
+ DIV8m = 563,
+ DIV8r = 564,
+ DIVPDrm = 565,
+ DIVPDrr = 566,
+ DIVPSrm = 567,
+ DIVPSrr = 568,
+ DIVR_F32m = 569,
+ DIVR_F64m = 570,
+ DIVR_FI16m = 571,
+ DIVR_FI32m = 572,
+ DIVR_FPrST0 = 573,
+ DIVR_FST0r = 574,
+ DIVR_Fp32m = 575,
+ DIVR_Fp64m = 576,
+ DIVR_Fp64m32 = 577,
+ DIVR_Fp80m32 = 578,
+ DIVR_Fp80m64 = 579,
+ DIVR_FpI16m32 = 580,
+ DIVR_FpI16m64 = 581,
+ DIVR_FpI16m80 = 582,
+ DIVR_FpI32m32 = 583,
+ DIVR_FpI32m64 = 584,
+ DIVR_FpI32m80 = 585,
+ DIVR_FrST0 = 586,
+ DIVSDrm = 587,
+ DIVSDrm_Int = 588,
+ DIVSDrr = 589,
+ DIVSDrr_Int = 590,
+ DIVSSrm = 591,
+ DIVSSrm_Int = 592,
+ DIVSSrr = 593,
+ DIVSSrr_Int = 594,
+ DIV_F32m = 595,
+ DIV_F64m = 596,
+ DIV_FI16m = 597,
+ DIV_FI32m = 598,
+ DIV_FPrST0 = 599,
+ DIV_FST0r = 600,
+ DIV_Fp32 = 601,
+ DIV_Fp32m = 602,
+ DIV_Fp64 = 603,
+ DIV_Fp64m = 604,
+ DIV_Fp64m32 = 605,
+ DIV_Fp80 = 606,
+ DIV_Fp80m32 = 607,
+ DIV_Fp80m64 = 608,
+ DIV_FpI16m32 = 609,
+ DIV_FpI16m64 = 610,
+ DIV_FpI16m80 = 611,
+ DIV_FpI32m32 = 612,
+ DIV_FpI32m64 = 613,
+ DIV_FpI32m80 = 614,
+ DIV_FrST0 = 615,
+ DPPDrmi = 616,
+ DPPDrri = 617,
+ DPPSrmi = 618,
+ DPPSrri = 619,
+ EH_RETURN = 620,
+ EH_RETURN64 = 621,
+ ENTER = 622,
+ EXTRACTPSmr = 623,
+ EXTRACTPSrr = 624,
+ F2XM1 = 625,
+ FARCALL16i = 626,
+ FARCALL16m = 627,
+ FARCALL32i = 628,
+ FARCALL32m = 629,
+ FARCALL64 = 630,
+ FARJMP16i = 631,
+ FARJMP16m = 632,
+ FARJMP32i = 633,
+ FARJMP32m = 634,
+ FARJMP64 = 635,
+ FBLDm = 636,
+ FBSTPm = 637,
+ FCOM32m = 638,
+ FCOM64m = 639,
+ FCOMP32m = 640,
+ FCOMP64m = 641,
+ FCOMPP = 642,
+ FDECSTP = 643,
+ FFREE = 644,
+ FICOM16m = 645,
+ FICOM32m = 646,
+ FICOMP16m = 647,
+ FICOMP32m = 648,
+ FINCSTP = 649,
+ FISTTP32m = 650,
+ FLDCW16m = 651,
+ FLDENVm = 652,
+ FLDL2E = 653,
+ FLDL2T = 654,
+ FLDLG2 = 655,
+ FLDLN2 = 656,
+ FLDPI = 657,
+ FNCLEX = 658,
+ FNINIT = 659,
+ FNOP = 660,
+ FNSTCW16m = 661,
+ FNSTSW8r = 662,
+ FNSTSWm = 663,
+ FP32_TO_INT16_IN_MEM = 664,
+ FP32_TO_INT32_IN_MEM = 665,
+ FP32_TO_INT64_IN_MEM = 666,
+ FP64_TO_INT16_IN_MEM = 667,
+ FP64_TO_INT32_IN_MEM = 668,
+ FP64_TO_INT64_IN_MEM = 669,
+ FP80_TO_INT16_IN_MEM = 670,
+ FP80_TO_INT32_IN_MEM = 671,
+ FP80_TO_INT64_IN_MEM = 672,
+ FPATAN = 673,
+ FPREM = 674,
+ FPREM1 = 675,
+ FPTAN = 676,
+ FP_REG_KILL = 677,
+ FRNDINT = 678,
+ FRSTORm = 679,
+ FSAVEm = 680,
+ FSCALE = 681,
+ FSINCOS = 682,
+ FSTENVm = 683,
+ FS_MOV32rm = 684,
+ FXAM = 685,
+ FXRSTOR = 686,
+ FXSAVE = 687,
+ FXTRACT = 688,
+ FYL2X = 689,
+ FYL2XP1 = 690,
+ FpGET_ST0_32 = 691,
+ FpGET_ST0_64 = 692,
+ FpGET_ST0_80 = 693,
+ FpGET_ST1_32 = 694,
+ FpGET_ST1_64 = 695,
+ FpGET_ST1_80 = 696,
+ FpSET_ST0_32 = 697,
+ FpSET_ST0_64 = 698,
+ FpSET_ST0_80 = 699,
+ FpSET_ST1_32 = 700,
+ FpSET_ST1_64 = 701,
+ FpSET_ST1_80 = 702,
+ FsANDNPDrm = 703,
+ FsANDNPDrr = 704,
+ FsANDNPSrm = 705,
+ FsANDNPSrr = 706,
+ FsANDPDrm = 707,
+ FsANDPDrr = 708,
+ FsANDPSrm = 709,
+ FsANDPSrr = 710,
+ FsFLD0SD = 711,
+ FsFLD0SS = 712,
+ FsMOVAPDrm = 713,
+ FsMOVAPDrr = 714,
+ FsMOVAPSrm = 715,
+ FsMOVAPSrr = 716,
+ FsORPDrm = 717,
+ FsORPDrr = 718,
+ FsORPSrm = 719,
+ FsORPSrr = 720,
+ FsXORPDrm = 721,
+ FsXORPDrr = 722,
+ FsXORPSrm = 723,
+ FsXORPSrr = 724,
+ GS_MOV32rm = 725,
+ HADDPDrm = 726,
+ HADDPDrr = 727,
+ HADDPSrm = 728,
+ HADDPSrr = 729,
+ HLT = 730,
+ HSUBPDrm = 731,
+ HSUBPDrr = 732,
+ HSUBPSrm = 733,
+ HSUBPSrr = 734,
+ IDIV16m = 735,
+ IDIV16r = 736,
+ IDIV32m = 737,
+ IDIV32r = 738,
+ IDIV64m = 739,
+ IDIV64r = 740,
+ IDIV8m = 741,
+ IDIV8r = 742,
+ ILD_F16m = 743,
+ ILD_F32m = 744,
+ ILD_F64m = 745,
+ ILD_Fp16m32 = 746,
+ ILD_Fp16m64 = 747,
+ ILD_Fp16m80 = 748,
+ ILD_Fp32m32 = 749,
+ ILD_Fp32m64 = 750,
+ ILD_Fp32m80 = 751,
+ ILD_Fp64m32 = 752,
+ ILD_Fp64m64 = 753,
+ ILD_Fp64m80 = 754,
+ IMUL16m = 755,
+ IMUL16r = 756,
+ IMUL16rm = 757,
+ IMUL16rmi = 758,
+ IMUL16rmi8 = 759,
+ IMUL16rr = 760,
+ IMUL16rri = 761,
+ IMUL16rri8 = 762,
+ IMUL32m = 763,
+ IMUL32r = 764,
+ IMUL32rm = 765,
+ IMUL32rmi = 766,
+ IMUL32rmi8 = 767,
+ IMUL32rr = 768,
+ IMUL32rri = 769,
+ IMUL32rri8 = 770,
+ IMUL64m = 771,
+ IMUL64r = 772,
+ IMUL64rm = 773,
+ IMUL64rmi32 = 774,
+ IMUL64rmi8 = 775,
+ IMUL64rr = 776,
+ IMUL64rri32 = 777,
+ IMUL64rri8 = 778,
+ IMUL8m = 779,
+ IMUL8r = 780,
+ IN16 = 781,
+ IN16ri = 782,
+ IN16rr = 783,
+ IN32 = 784,
+ IN32ri = 785,
+ IN32rr = 786,
+ IN8 = 787,
+ IN8ri = 788,
+ IN8rr = 789,
+ INC16m = 790,
+ INC16r = 791,
+ INC32m = 792,
+ INC32r = 793,
+ INC64_16m = 794,
+ INC64_16r = 795,
+ INC64_32m = 796,
+ INC64_32r = 797,
+ INC64m = 798,
+ INC64r = 799,
+ INC8m = 800,
+ INC8r = 801,
+ INSERTPSrm = 802,
+ INSERTPSrr = 803,
+ INT = 804,
+ INT3 = 805,
+ INVD = 806,
+ INVEPT = 807,
+ INVLPG = 808,
+ INVVPID = 809,
+ IRET16 = 810,
+ IRET32 = 811,
+ IRET64 = 812,
+ ISTT_FP16m = 813,
+ ISTT_FP32m = 814,
+ ISTT_FP64m = 815,
+ ISTT_Fp16m32 = 816,
+ ISTT_Fp16m64 = 817,
+ ISTT_Fp16m80 = 818,
+ ISTT_Fp32m32 = 819,
+ ISTT_Fp32m64 = 820,
+ ISTT_Fp32m80 = 821,
+ ISTT_Fp64m32 = 822,
+ ISTT_Fp64m64 = 823,
+ ISTT_Fp64m80 = 824,
+ IST_F16m = 825,
+ IST_F32m = 826,
+ IST_FP16m = 827,
+ IST_FP32m = 828,
+ IST_FP64m = 829,
+ IST_Fp16m32 = 830,
+ IST_Fp16m64 = 831,
+ IST_Fp16m80 = 832,
+ IST_Fp32m32 = 833,
+ IST_Fp32m64 = 834,
+ IST_Fp32m80 = 835,
+ IST_Fp64m32 = 836,
+ IST_Fp64m64 = 837,
+ IST_Fp64m80 = 838,
+ Int_CMPSDrm = 839,
+ Int_CMPSDrr = 840,
+ Int_CMPSSrm = 841,
+ Int_CMPSSrr = 842,
+ Int_COMISDrm = 843,
+ Int_COMISDrr = 844,
+ Int_COMISSrm = 845,
+ Int_COMISSrr = 846,
+ Int_CVTDQ2PDrm = 847,
+ Int_CVTDQ2PDrr = 848,
+ Int_CVTDQ2PSrm = 849,
+ Int_CVTDQ2PSrr = 850,
+ Int_CVTPD2DQrm = 851,
+ Int_CVTPD2DQrr = 852,
+ Int_CVTPD2PIrm = 853,
+ Int_CVTPD2PIrr = 854,
+ Int_CVTPD2PSrm = 855,
+ Int_CVTPD2PSrr = 856,
+ Int_CVTPI2PDrm = 857,
+ Int_CVTPI2PDrr = 858,
+ Int_CVTPI2PSrm = 859,
+ Int_CVTPI2PSrr = 860,
+ Int_CVTPS2DQrm = 861,
+ Int_CVTPS2DQrr = 862,
+ Int_CVTPS2PDrm = 863,
+ Int_CVTPS2PDrr = 864,
+ Int_CVTPS2PIrm = 865,
+ Int_CVTPS2PIrr = 866,
+ Int_CVTSD2SI64rm = 867,
+ Int_CVTSD2SI64rr = 868,
+ Int_CVTSD2SIrm = 869,
+ Int_CVTSD2SIrr = 870,
+ Int_CVTSD2SSrm = 871,
+ Int_CVTSD2SSrr = 872,
+ Int_CVTSI2SD64rm = 873,
+ Int_CVTSI2SD64rr = 874,
+ Int_CVTSI2SDrm = 875,
+ Int_CVTSI2SDrr = 876,
+ Int_CVTSI2SS64rm = 877,
+ Int_CVTSI2SS64rr = 878,
+ Int_CVTSI2SSrm = 879,
+ Int_CVTSI2SSrr = 880,
+ Int_CVTSS2SDrm = 881,
+ Int_CVTSS2SDrr = 882,
+ Int_CVTSS2SI64rm = 883,
+ Int_CVTSS2SI64rr = 884,
+ Int_CVTSS2SIrm = 885,
+ Int_CVTSS2SIrr = 886,
+ Int_CVTTPD2DQrm = 887,
+ Int_CVTTPD2DQrr = 888,
+ Int_CVTTPD2PIrm = 889,
+ Int_CVTTPD2PIrr = 890,
+ Int_CVTTPS2DQrm = 891,
+ Int_CVTTPS2DQrr = 892,
+ Int_CVTTPS2PIrm = 893,
+ Int_CVTTPS2PIrr = 894,
+ Int_CVTTSD2SI64rm = 895,
+ Int_CVTTSD2SI64rr = 896,
+ Int_CVTTSD2SIrm = 897,
+ Int_CVTTSD2SIrr = 898,
+ Int_CVTTSS2SI64rm = 899,
+ Int_CVTTSS2SI64rr = 900,
+ Int_CVTTSS2SIrm = 901,
+ Int_CVTTSS2SIrr = 902,
+ Int_UCOMISDrm = 903,
+ Int_UCOMISDrr = 904,
+ Int_UCOMISSrm = 905,
+ Int_UCOMISSrr = 906,
+ JA = 907,
+ JA8 = 908,
+ JAE = 909,
+ JAE8 = 910,
+ JB = 911,
+ JB8 = 912,
+ JBE = 913,
+ JBE8 = 914,
+ JCXZ8 = 915,
+ JE = 916,
+ JE8 = 917,
+ JG = 918,
+ JG8 = 919,
+ JGE = 920,
+ JGE8 = 921,
+ JL = 922,
+ JL8 = 923,
+ JLE = 924,
+ JLE8 = 925,
+ JMP = 926,
+ JMP32m = 927,
+ JMP32r = 928,
+ JMP64m = 929,
+ JMP64pcrel32 = 930,
+ JMP64r = 931,
+ JMP8 = 932,
+ JNE = 933,
+ JNE8 = 934,
+ JNO = 935,
+ JNO8 = 936,
+ JNP = 937,
+ JNP8 = 938,
+ JNS = 939,
+ JNS8 = 940,
+ JO = 941,
+ JO8 = 942,
+ JP = 943,
+ JP8 = 944,
+ JS = 945,
+ JS8 = 946,
+ LAHF = 947,
+ LAR16rm = 948,
+ LAR16rr = 949,
+ LAR32rm = 950,
+ LAR32rr = 951,
+ LAR64rm = 952,
+ LAR64rr = 953,
+ LCMPXCHG16 = 954,
+ LCMPXCHG32 = 955,
+ LCMPXCHG64 = 956,
+ LCMPXCHG8 = 957,
+ LCMPXCHG8B = 958,
+ LDDQUrm = 959,
+ LDMXCSR = 960,
+ LDS16rm = 961,
+ LDS32rm = 962,
+ LD_F0 = 963,
+ LD_F1 = 964,
+ LD_F32m = 965,
+ LD_F64m = 966,
+ LD_F80m = 967,
+ LD_Fp032 = 968,
+ LD_Fp064 = 969,
+ LD_Fp080 = 970,
+ LD_Fp132 = 971,
+ LD_Fp164 = 972,
+ LD_Fp180 = 973,
+ LD_Fp32m = 974,
+ LD_Fp32m64 = 975,
+ LD_Fp32m80 = 976,
+ LD_Fp64m = 977,
+ LD_Fp64m80 = 978,
+ LD_Fp80m = 979,
+ LD_Frr = 980,
+ LEA16r = 981,
+ LEA32r = 982,
+ LEA64_32r = 983,
+ LEA64r = 984,
+ LEAVE = 985,
+ LEAVE64 = 986,
+ LES16rm = 987,
+ LES32rm = 988,
+ LFENCE = 989,
+ LFS16rm = 990,
+ LFS32rm = 991,
+ LFS64rm = 992,
+ LGDTm = 993,
+ LGS16rm = 994,
+ LGS32rm = 995,
+ LGS64rm = 996,
+ LIDTm = 997,
+ LLDT16m = 998,
+ LLDT16r = 999,
+ LMSW16m = 1000,
+ LMSW16r = 1001,
+ LOCK_ADD16mi = 1002,
+ LOCK_ADD16mi8 = 1003,
+ LOCK_ADD16mr = 1004,
+ LOCK_ADD32mi = 1005,
+ LOCK_ADD32mi8 = 1006,
+ LOCK_ADD32mr = 1007,
+ LOCK_ADD64mi32 = 1008,
+ LOCK_ADD64mi8 = 1009,
+ LOCK_ADD64mr = 1010,
+ LOCK_ADD8mi = 1011,
+ LOCK_ADD8mr = 1012,
+ LOCK_DEC16m = 1013,
+ LOCK_DEC32m = 1014,
+ LOCK_DEC64m = 1015,
+ LOCK_DEC8m = 1016,
+ LOCK_INC16m = 1017,
+ LOCK_INC32m = 1018,
+ LOCK_INC64m = 1019,
+ LOCK_INC8m = 1020,
+ LOCK_SUB16mi = 1021,
+ LOCK_SUB16mi8 = 1022,
+ LOCK_SUB16mr = 1023,
+ LOCK_SUB32mi = 1024,
+ LOCK_SUB32mi8 = 1025,
+ LOCK_SUB32mr = 1026,
+ LOCK_SUB64mi32 = 1027,
+ LOCK_SUB64mi8 = 1028,
+ LOCK_SUB64mr = 1029,
+ LOCK_SUB8mi = 1030,
+ LOCK_SUB8mr = 1031,
+ LODSB = 1032,
+ LODSD = 1033,
+ LODSQ = 1034,
+ LODSW = 1035,
+ LOOP = 1036,
+ LOOPE = 1037,
+ LOOPNE = 1038,
+ LRET = 1039,
+ LRETI = 1040,
+ LSL16rm = 1041,
+ LSL16rr = 1042,
+ LSL32rm = 1043,
+ LSL32rr = 1044,
+ LSL64rm = 1045,
+ LSL64rr = 1046,
+ LSS16rm = 1047,
+ LSS32rm = 1048,
+ LSS64rm = 1049,
+ LTRm = 1050,
+ LTRr = 1051,
+ LXADD16 = 1052,
+ LXADD32 = 1053,
+ LXADD64 = 1054,
+ LXADD8 = 1055,
+ MASKMOVDQU = 1056,
+ MASKMOVDQU64 = 1057,
+ MAXPDrm = 1058,
+ MAXPDrm_Int = 1059,
+ MAXPDrr = 1060,
+ MAXPDrr_Int = 1061,
+ MAXPSrm = 1062,
+ MAXPSrm_Int = 1063,
+ MAXPSrr = 1064,
+ MAXPSrr_Int = 1065,
+ MAXSDrm = 1066,
+ MAXSDrm_Int = 1067,
+ MAXSDrr = 1068,
+ MAXSDrr_Int = 1069,
+ MAXSSrm = 1070,
+ MAXSSrm_Int = 1071,
+ MAXSSrr = 1072,
+ MAXSSrr_Int = 1073,
+ MFENCE = 1074,
+ MINPDrm = 1075,
+ MINPDrm_Int = 1076,
+ MINPDrr = 1077,
+ MINPDrr_Int = 1078,
+ MINPSrm = 1079,
+ MINPSrm_Int = 1080,
+ MINPSrr = 1081,
+ MINPSrr_Int = 1082,
+ MINSDrm = 1083,
+ MINSDrm_Int = 1084,
+ MINSDrr = 1085,
+ MINSDrr_Int = 1086,
+ MINSSrm = 1087,
+ MINSSrm_Int = 1088,
+ MINSSrr = 1089,
+ MINSSrr_Int = 1090,
+ MMX_CVTPD2PIrm = 1091,
+ MMX_CVTPD2PIrr = 1092,
+ MMX_CVTPI2PDrm = 1093,
+ MMX_CVTPI2PDrr = 1094,
+ MMX_CVTPI2PSrm = 1095,
+ MMX_CVTPI2PSrr = 1096,
+ MMX_CVTPS2PIrm = 1097,
+ MMX_CVTPS2PIrr = 1098,
+ MMX_CVTTPD2PIrm = 1099,
+ MMX_CVTTPD2PIrr = 1100,
+ MMX_CVTTPS2PIrm = 1101,
+ MMX_CVTTPS2PIrr = 1102,
+ MMX_EMMS = 1103,
+ MMX_FEMMS = 1104,
+ MMX_MASKMOVQ = 1105,
+ MMX_MASKMOVQ64 = 1106,
+ MMX_MOVD64from64rr = 1107,
+ MMX_MOVD64grr = 1108,
+ MMX_MOVD64mr = 1109,
+ MMX_MOVD64rm = 1110,
+ MMX_MOVD64rr = 1111,
+ MMX_MOVD64rrv164 = 1112,
+ MMX_MOVD64to64rr = 1113,
+ MMX_MOVDQ2Qrr = 1114,
+ MMX_MOVNTQmr = 1115,
+ MMX_MOVQ2DQrr = 1116,
+ MMX_MOVQ2FR64rr = 1117,
+ MMX_MOVQ64gmr = 1118,
+ MMX_MOVQ64mr = 1119,
+ MMX_MOVQ64rm = 1120,
+ MMX_MOVQ64rr = 1121,
+ MMX_MOVZDI2PDIrm = 1122,
+ MMX_MOVZDI2PDIrr = 1123,
+ MMX_PACKSSDWrm = 1124,
+ MMX_PACKSSDWrr = 1125,
+ MMX_PACKSSWBrm = 1126,
+ MMX_PACKSSWBrr = 1127,
+ MMX_PACKUSWBrm = 1128,
+ MMX_PACKUSWBrr = 1129,
+ MMX_PADDBrm = 1130,
+ MMX_PADDBrr = 1131,
+ MMX_PADDDrm = 1132,
+ MMX_PADDDrr = 1133,
+ MMX_PADDQrm = 1134,
+ MMX_PADDQrr = 1135,
+ MMX_PADDSBrm = 1136,
+ MMX_PADDSBrr = 1137,
+ MMX_PADDSWrm = 1138,
+ MMX_PADDSWrr = 1139,
+ MMX_PADDUSBrm = 1140,
+ MMX_PADDUSBrr = 1141,
+ MMX_PADDUSWrm = 1142,
+ MMX_PADDUSWrr = 1143,
+ MMX_PADDWrm = 1144,
+ MMX_PADDWrr = 1145,
+ MMX_PANDNrm = 1146,
+ MMX_PANDNrr = 1147,
+ MMX_PANDrm = 1148,
+ MMX_PANDrr = 1149,
+ MMX_PAVGBrm = 1150,
+ MMX_PAVGBrr = 1151,
+ MMX_PAVGWrm = 1152,
+ MMX_PAVGWrr = 1153,
+ MMX_PCMPEQBrm = 1154,
+ MMX_PCMPEQBrr = 1155,
+ MMX_PCMPEQDrm = 1156,
+ MMX_PCMPEQDrr = 1157,
+ MMX_PCMPEQWrm = 1158,
+ MMX_PCMPEQWrr = 1159,
+ MMX_PCMPGTBrm = 1160,
+ MMX_PCMPGTBrr = 1161,
+ MMX_PCMPGTDrm = 1162,
+ MMX_PCMPGTDrr = 1163,
+ MMX_PCMPGTWrm = 1164,
+ MMX_PCMPGTWrr = 1165,
+ MMX_PEXTRWri = 1166,
+ MMX_PINSRWrmi = 1167,
+ MMX_PINSRWrri = 1168,
+ MMX_PMADDWDrm = 1169,
+ MMX_PMADDWDrr = 1170,
+ MMX_PMAXSWrm = 1171,
+ MMX_PMAXSWrr = 1172,
+ MMX_PMAXUBrm = 1173,
+ MMX_PMAXUBrr = 1174,
+ MMX_PMINSWrm = 1175,
+ MMX_PMINSWrr = 1176,
+ MMX_PMINUBrm = 1177,
+ MMX_PMINUBrr = 1178,
+ MMX_PMOVMSKBrr = 1179,
+ MMX_PMULHUWrm = 1180,
+ MMX_PMULHUWrr = 1181,
+ MMX_PMULHWrm = 1182,
+ MMX_PMULHWrr = 1183,
+ MMX_PMULLWrm = 1184,
+ MMX_PMULLWrr = 1185,
+ MMX_PMULUDQrm = 1186,
+ MMX_PMULUDQrr = 1187,
+ MMX_PORrm = 1188,
+ MMX_PORrr = 1189,
+ MMX_PSADBWrm = 1190,
+ MMX_PSADBWrr = 1191,
+ MMX_PSHUFWmi = 1192,
+ MMX_PSHUFWri = 1193,
+ MMX_PSLLDri = 1194,
+ MMX_PSLLDrm = 1195,
+ MMX_PSLLDrr = 1196,
+ MMX_PSLLQri = 1197,
+ MMX_PSLLQrm = 1198,
+ MMX_PSLLQrr = 1199,
+ MMX_PSLLWri = 1200,
+ MMX_PSLLWrm = 1201,
+ MMX_PSLLWrr = 1202,
+ MMX_PSRADri = 1203,
+ MMX_PSRADrm = 1204,
+ MMX_PSRADrr = 1205,
+ MMX_PSRAWri = 1206,
+ MMX_PSRAWrm = 1207,
+ MMX_PSRAWrr = 1208,
+ MMX_PSRLDri = 1209,
+ MMX_PSRLDrm = 1210,
+ MMX_PSRLDrr = 1211,
+ MMX_PSRLQri = 1212,
+ MMX_PSRLQrm = 1213,
+ MMX_PSRLQrr = 1214,
+ MMX_PSRLWri = 1215,
+ MMX_PSRLWrm = 1216,
+ MMX_PSRLWrr = 1217,
+ MMX_PSUBBrm = 1218,
+ MMX_PSUBBrr = 1219,
+ MMX_PSUBDrm = 1220,
+ MMX_PSUBDrr = 1221,
+ MMX_PSUBQrm = 1222,
+ MMX_PSUBQrr = 1223,
+ MMX_PSUBSBrm = 1224,
+ MMX_PSUBSBrr = 1225,
+ MMX_PSUBSWrm = 1226,
+ MMX_PSUBSWrr = 1227,
+ MMX_PSUBUSBrm = 1228,
+ MMX_PSUBUSBrr = 1229,
+ MMX_PSUBUSWrm = 1230,
+ MMX_PSUBUSWrr = 1231,
+ MMX_PSUBWrm = 1232,
+ MMX_PSUBWrr = 1233,
+ MMX_PUNPCKHBWrm = 1234,
+ MMX_PUNPCKHBWrr = 1235,
+ MMX_PUNPCKHDQrm = 1236,
+ MMX_PUNPCKHDQrr = 1237,
+ MMX_PUNPCKHWDrm = 1238,
+ MMX_PUNPCKHWDrr = 1239,
+ MMX_PUNPCKLBWrm = 1240,
+ MMX_PUNPCKLBWrr = 1241,
+ MMX_PUNPCKLDQrm = 1242,
+ MMX_PUNPCKLDQrr = 1243,
+ MMX_PUNPCKLWDrm = 1244,
+ MMX_PUNPCKLWDrr = 1245,
+ MMX_PXORrm = 1246,
+ MMX_PXORrr = 1247,
+ MMX_V_SET0 = 1248,
+ MMX_V_SETALLONES = 1249,
+ MONITOR = 1250,
+ MOV16ao16 = 1251,
+ MOV16mi = 1252,
+ MOV16mr = 1253,
+ MOV16ms = 1254,
+ MOV16o16a = 1255,
+ MOV16ri = 1256,
+ MOV16rm = 1257,
+ MOV16rr = 1258,
+ MOV16rr_REV = 1259,
+ MOV16rs = 1260,
+ MOV16sm = 1261,
+ MOV16sr = 1262,
+ MOV32ao32 = 1263,
+ MOV32cr = 1264,
+ MOV32dr = 1265,
+ MOV32mi = 1266,
+ MOV32mr = 1267,
+ MOV32o32a = 1268,
+ MOV32r0 = 1269,
+ MOV32rc = 1270,
+ MOV32rd = 1271,
+ MOV32ri = 1272,
+ MOV32rm = 1273,
+ MOV32rr = 1274,
+ MOV32rr_REV = 1275,
+ MOV64FSrm = 1276,
+ MOV64GSrm = 1277,
+ MOV64ao64 = 1278,
+ MOV64ao8 = 1279,
+ MOV64cr = 1280,
+ MOV64dr = 1281,
+ MOV64mi32 = 1282,
+ MOV64mr = 1283,
+ MOV64ms = 1284,
+ MOV64o64a = 1285,
+ MOV64o8a = 1286,
+ MOV64rc = 1287,
+ MOV64rd = 1288,
+ MOV64ri = 1289,
+ MOV64ri32 = 1290,
+ MOV64ri64i32 = 1291,
+ MOV64rm = 1292,
+ MOV64rr = 1293,
+ MOV64rr_REV = 1294,
+ MOV64rs = 1295,
+ MOV64sm = 1296,
+ MOV64sr = 1297,
+ MOV64toPQIrr = 1298,
+ MOV64toSDrm = 1299,
+ MOV64toSDrr = 1300,
+ MOV8ao8 = 1301,
+ MOV8mi = 1302,
+ MOV8mr = 1303,
+ MOV8mr_NOREX = 1304,
+ MOV8o8a = 1305,
+ MOV8r0 = 1306,
+ MOV8ri = 1307,
+ MOV8rm = 1308,
+ MOV8rm_NOREX = 1309,
+ MOV8rr = 1310,
+ MOV8rr_NOREX = 1311,
+ MOV8rr_REV = 1312,
+ MOVAPDmr = 1313,
+ MOVAPDrm = 1314,
+ MOVAPDrr = 1315,
+ MOVAPSmr = 1316,
+ MOVAPSrm = 1317,
+ MOVAPSrr = 1318,
+ MOVDDUPrm = 1319,
+ MOVDDUPrr = 1320,
+ MOVDI2PDIrm = 1321,
+ MOVDI2PDIrr = 1322,
+ MOVDI2SSrm = 1323,
+ MOVDI2SSrr = 1324,
+ MOVDQAmr = 1325,
+ MOVDQArm = 1326,
+ MOVDQArr = 1327,
+ MOVDQUmr = 1328,
+ MOVDQUmr_Int = 1329,
+ MOVDQUrm = 1330,
+ MOVDQUrm_Int = 1331,
+ MOVHLPSrr = 1332,
+ MOVHPDmr = 1333,
+ MOVHPDrm = 1334,
+ MOVHPSmr = 1335,
+ MOVHPSrm = 1336,
+ MOVLHPSrr = 1337,
+ MOVLPDmr = 1338,
+ MOVLPDrm = 1339,
+ MOVLPDrr = 1340,
+ MOVLPSmr = 1341,
+ MOVLPSrm = 1342,
+ MOVLPSrr = 1343,
+ MOVLQ128mr = 1344,
+ MOVLSD2PDrr = 1345,
+ MOVLSS2PSrr = 1346,
+ MOVMSKPDrr = 1347,
+ MOVMSKPSrr = 1348,
+ MOVNTDQArm = 1349,
+ MOVNTDQmr = 1350,
+ MOVNTImr = 1351,
+ MOVNTPDmr = 1352,
+ MOVNTPSmr = 1353,
+ MOVPC32r = 1354,
+ MOVPD2SDmr = 1355,
+ MOVPD2SDrr = 1356,
+ MOVPDI2DImr = 1357,
+ MOVPDI2DIrr = 1358,
+ MOVPQI2QImr = 1359,
+ MOVPQIto64rr = 1360,
+ MOVPS2SSmr = 1361,
+ MOVPS2SSrr = 1362,
+ MOVQI2PQIrm = 1363,
+ MOVQxrxr = 1364,
+ MOVSD2PDrm = 1365,
+ MOVSD2PDrr = 1366,
+ MOVSDmr = 1367,
+ MOVSDrm = 1368,
+ MOVSDrr = 1369,
+ MOVSDto64mr = 1370,
+ MOVSDto64rr = 1371,
+ MOVSHDUPrm = 1372,
+ MOVSHDUPrr = 1373,
+ MOVSLDUPrm = 1374,
+ MOVSLDUPrr = 1375,
+ MOVSS2DImr = 1376,
+ MOVSS2DIrr = 1377,
+ MOVSS2PSrm = 1378,
+ MOVSS2PSrr = 1379,
+ MOVSSmr = 1380,
+ MOVSSrm = 1381,
+ MOVSSrr = 1382,
+ MOVSX16rm8 = 1383,
+ MOVSX16rm8W = 1384,
+ MOVSX16rr8 = 1385,
+ MOVSX16rr8W = 1386,
+ MOVSX32rm16 = 1387,
+ MOVSX32rm8 = 1388,
+ MOVSX32rr16 = 1389,
+ MOVSX32rr8 = 1390,
+ MOVSX64rm16 = 1391,
+ MOVSX64rm32 = 1392,
+ MOVSX64rm8 = 1393,
+ MOVSX64rr16 = 1394,
+ MOVSX64rr32 = 1395,
+ MOVSX64rr8 = 1396,
+ MOVUPDmr = 1397,
+ MOVUPDmr_Int = 1398,
+ MOVUPDrm = 1399,
+ MOVUPDrm_Int = 1400,
+ MOVUPDrr = 1401,
+ MOVUPSmr = 1402,
+ MOVUPSmr_Int = 1403,
+ MOVUPSrm = 1404,
+ MOVUPSrm_Int = 1405,
+ MOVUPSrr = 1406,
+ MOVZDI2PDIrm = 1407,
+ MOVZDI2PDIrr = 1408,
+ MOVZPQILo2PQIrm = 1409,
+ MOVZPQILo2PQIrr = 1410,
+ MOVZQI2PQIrm = 1411,
+ MOVZQI2PQIrr = 1412,
+ MOVZSD2PDrm = 1413,
+ MOVZSS2PSrm = 1414,
+ MOVZX16rm8 = 1415,
+ MOVZX16rm8W = 1416,
+ MOVZX16rr8 = 1417,
+ MOVZX16rr8W = 1418,
+ MOVZX32_NOREXrm8 = 1419,
+ MOVZX32_NOREXrr8 = 1420,
+ MOVZX32rm16 = 1421,
+ MOVZX32rm8 = 1422,
+ MOVZX32rr16 = 1423,
+ MOVZX32rr8 = 1424,
+ MOVZX64rm16 = 1425,
+ MOVZX64rm16_Q = 1426,
+ MOVZX64rm32 = 1427,
+ MOVZX64rm8 = 1428,
+ MOVZX64rm8_Q = 1429,
+ MOVZX64rr16 = 1430,
+ MOVZX64rr16_Q = 1431,
+ MOVZX64rr32 = 1432,
+ MOVZX64rr8 = 1433,
+ MOVZX64rr8_Q = 1434,
+ MOV_Fp3232 = 1435,
+ MOV_Fp3264 = 1436,
+ MOV_Fp3280 = 1437,
+ MOV_Fp6432 = 1438,
+ MOV_Fp6464 = 1439,
+ MOV_Fp6480 = 1440,
+ MOV_Fp8032 = 1441,
+ MOV_Fp8064 = 1442,
+ MOV_Fp8080 = 1443,
+ MPSADBWrmi = 1444,
+ MPSADBWrri = 1445,
+ MUL16m = 1446,
+ MUL16r = 1447,
+ MUL32m = 1448,
+ MUL32r = 1449,
+ MUL64m = 1450,
+ MUL64r = 1451,
+ MUL8m = 1452,
+ MUL8r = 1453,
+ MULPDrm = 1454,
+ MULPDrr = 1455,
+ MULPSrm = 1456,
+ MULPSrr = 1457,
+ MULSDrm = 1458,
+ MULSDrm_Int = 1459,
+ MULSDrr = 1460,
+ MULSDrr_Int = 1461,
+ MULSSrm = 1462,
+ MULSSrm_Int = 1463,
+ MULSSrr = 1464,
+ MULSSrr_Int = 1465,
+ MUL_F32m = 1466,
+ MUL_F64m = 1467,
+ MUL_FI16m = 1468,
+ MUL_FI32m = 1469,
+ MUL_FPrST0 = 1470,
+ MUL_FST0r = 1471,
+ MUL_Fp32 = 1472,
+ MUL_Fp32m = 1473,
+ MUL_Fp64 = 1474,
+ MUL_Fp64m = 1475,
+ MUL_Fp64m32 = 1476,
+ MUL_Fp80 = 1477,
+ MUL_Fp80m32 = 1478,
+ MUL_Fp80m64 = 1479,
+ MUL_FpI16m32 = 1480,
+ MUL_FpI16m64 = 1481,
+ MUL_FpI16m80 = 1482,
+ MUL_FpI32m32 = 1483,
+ MUL_FpI32m64 = 1484,
+ MUL_FpI32m80 = 1485,
+ MUL_FrST0 = 1486,
+ MWAIT = 1487,
+ NEG16m = 1488,
+ NEG16r = 1489,
+ NEG32m = 1490,
+ NEG32r = 1491,
+ NEG64m = 1492,
+ NEG64r = 1493,
+ NEG8m = 1494,
+ NEG8r = 1495,
+ NOOP = 1496,
+ NOOPL = 1497,
+ NOOPW = 1498,
+ NOT16m = 1499,
+ NOT16r = 1500,
+ NOT32m = 1501,
+ NOT32r = 1502,
+ NOT64m = 1503,
+ NOT64r = 1504,
+ NOT8m = 1505,
+ NOT8r = 1506,
+ OR16i16 = 1507,
+ OR16mi = 1508,
+ OR16mi8 = 1509,
+ OR16mr = 1510,
+ OR16ri = 1511,
+ OR16ri8 = 1512,
+ OR16rm = 1513,
+ OR16rr = 1514,
+ OR16rr_REV = 1515,
+ OR32i32 = 1516,
+ OR32mi = 1517,
+ OR32mi8 = 1518,
+ OR32mr = 1519,
+ OR32ri = 1520,
+ OR32ri8 = 1521,
+ OR32rm = 1522,
+ OR32rr = 1523,
+ OR32rr_REV = 1524,
+ OR64i32 = 1525,
+ OR64mi32 = 1526,
+ OR64mi8 = 1527,
+ OR64mr = 1528,
+ OR64ri32 = 1529,
+ OR64ri8 = 1530,
+ OR64rm = 1531,
+ OR64rr = 1532,
+ OR64rr_REV = 1533,
+ OR8i8 = 1534,
+ OR8mi = 1535,
+ OR8mr = 1536,
+ OR8ri = 1537,
+ OR8rm = 1538,
+ OR8rr = 1539,
+ OR8rr_REV = 1540,
+ ORPDrm = 1541,
+ ORPDrr = 1542,
+ ORPSrm = 1543,
+ ORPSrr = 1544,
+ OUT16ir = 1545,
+ OUT16rr = 1546,
+ OUT32ir = 1547,
+ OUT32rr = 1548,
+ OUT8ir = 1549,
+ OUT8rr = 1550,
+ OUTSB = 1551,
+ OUTSD = 1552,
+ OUTSW = 1553,
+ PABSBrm128 = 1554,
+ PABSBrm64 = 1555,
+ PABSBrr128 = 1556,
+ PABSBrr64 = 1557,
+ PABSDrm128 = 1558,
+ PABSDrm64 = 1559,
+ PABSDrr128 = 1560,
+ PABSDrr64 = 1561,
+ PABSWrm128 = 1562,
+ PABSWrm64 = 1563,
+ PABSWrr128 = 1564,
+ PABSWrr64 = 1565,
+ PACKSSDWrm = 1566,
+ PACKSSDWrr = 1567,
+ PACKSSWBrm = 1568,
+ PACKSSWBrr = 1569,
+ PACKUSDWrm = 1570,
+ PACKUSDWrr = 1571,
+ PACKUSWBrm = 1572,
+ PACKUSWBrr = 1573,
+ PADDBrm = 1574,
+ PADDBrr = 1575,
+ PADDDrm = 1576,
+ PADDDrr = 1577,
+ PADDQrm = 1578,
+ PADDQrr = 1579,
+ PADDSBrm = 1580,
+ PADDSBrr = 1581,
+ PADDSWrm = 1582,
+ PADDSWrr = 1583,
+ PADDUSBrm = 1584,
+ PADDUSBrr = 1585,
+ PADDUSWrm = 1586,
+ PADDUSWrr = 1587,
+ PADDWrm = 1588,
+ PADDWrr = 1589,
+ PALIGNR128rm = 1590,
+ PALIGNR128rr = 1591,
+ PALIGNR64rm = 1592,
+ PALIGNR64rr = 1593,
+ PANDNrm = 1594,
+ PANDNrr = 1595,
+ PANDrm = 1596,
+ PANDrr = 1597,
+ PAVGBrm = 1598,
+ PAVGBrr = 1599,
+ PAVGWrm = 1600,
+ PAVGWrr = 1601,
+ PBLENDVBrm0 = 1602,
+ PBLENDVBrr0 = 1603,
+ PBLENDWrmi = 1604,
+ PBLENDWrri = 1605,
+ PCMPEQBrm = 1606,
+ PCMPEQBrr = 1607,
+ PCMPEQDrm = 1608,
+ PCMPEQDrr = 1609,
+ PCMPEQQrm = 1610,
+ PCMPEQQrr = 1611,
+ PCMPEQWrm = 1612,
+ PCMPEQWrr = 1613,
+ PCMPESTRIArm = 1614,
+ PCMPESTRIArr = 1615,
+ PCMPESTRICrm = 1616,
+ PCMPESTRICrr = 1617,
+ PCMPESTRIOrm = 1618,
+ PCMPESTRIOrr = 1619,
+ PCMPESTRISrm = 1620,
+ PCMPESTRISrr = 1621,
+ PCMPESTRIZrm = 1622,
+ PCMPESTRIZrr = 1623,
+ PCMPESTRIrm = 1624,
+ PCMPESTRIrr = 1625,
+ PCMPESTRM128MEM = 1626,
+ PCMPESTRM128REG = 1627,
+ PCMPESTRM128rm = 1628,
+ PCMPESTRM128rr = 1629,
+ PCMPGTBrm = 1630,
+ PCMPGTBrr = 1631,
+ PCMPGTDrm = 1632,
+ PCMPGTDrr = 1633,
+ PCMPGTQrm = 1634,
+ PCMPGTQrr = 1635,
+ PCMPGTWrm = 1636,
+ PCMPGTWrr = 1637,
+ PCMPISTRIArm = 1638,
+ PCMPISTRIArr = 1639,
+ PCMPISTRICrm = 1640,
+ PCMPISTRICrr = 1641,
+ PCMPISTRIOrm = 1642,
+ PCMPISTRIOrr = 1643,
+ PCMPISTRISrm = 1644,
+ PCMPISTRISrr = 1645,
+ PCMPISTRIZrm = 1646,
+ PCMPISTRIZrr = 1647,
+ PCMPISTRIrm = 1648,
+ PCMPISTRIrr = 1649,
+ PCMPISTRM128MEM = 1650,
+ PCMPISTRM128REG = 1651,
+ PCMPISTRM128rm = 1652,
+ PCMPISTRM128rr = 1653,
+ PEXTRBmr = 1654,
+ PEXTRBrr = 1655,
+ PEXTRDmr = 1656,
+ PEXTRDrr = 1657,
+ PEXTRQmr = 1658,
+ PEXTRQrr = 1659,
+ PEXTRWmr = 1660,
+ PEXTRWri = 1661,
+ PHADDDrm128 = 1662,
+ PHADDDrm64 = 1663,
+ PHADDDrr128 = 1664,
+ PHADDDrr64 = 1665,
+ PHADDSWrm128 = 1666,
+ PHADDSWrm64 = 1667,
+ PHADDSWrr128 = 1668,
+ PHADDSWrr64 = 1669,
+ PHADDWrm128 = 1670,
+ PHADDWrm64 = 1671,
+ PHADDWrr128 = 1672,
+ PHADDWrr64 = 1673,
+ PHMINPOSUWrm128 = 1674,
+ PHMINPOSUWrr128 = 1675,
+ PHSUBDrm128 = 1676,
+ PHSUBDrm64 = 1677,
+ PHSUBDrr128 = 1678,
+ PHSUBDrr64 = 1679,
+ PHSUBSWrm128 = 1680,
+ PHSUBSWrm64 = 1681,
+ PHSUBSWrr128 = 1682,
+ PHSUBSWrr64 = 1683,
+ PHSUBWrm128 = 1684,
+ PHSUBWrm64 = 1685,
+ PHSUBWrr128 = 1686,
+ PHSUBWrr64 = 1687,
+ PINSRBrm = 1688,
+ PINSRBrr = 1689,
+ PINSRDrm = 1690,
+ PINSRDrr = 1691,
+ PINSRQrm = 1692,
+ PINSRQrr = 1693,
+ PINSRWrmi = 1694,
+ PINSRWrri = 1695,
+ PMADDUBSWrm128 = 1696,
+ PMADDUBSWrm64 = 1697,
+ PMADDUBSWrr128 = 1698,
+ PMADDUBSWrr64 = 1699,
+ PMADDWDrm = 1700,
+ PMADDWDrr = 1701,
+ PMAXSBrm = 1702,
+ PMAXSBrr = 1703,
+ PMAXSDrm = 1704,
+ PMAXSDrr = 1705,
+ PMAXSWrm = 1706,
+ PMAXSWrr = 1707,
+ PMAXUBrm = 1708,
+ PMAXUBrr = 1709,
+ PMAXUDrm = 1710,
+ PMAXUDrr = 1711,
+ PMAXUWrm = 1712,
+ PMAXUWrr = 1713,
+ PMINSBrm = 1714,
+ PMINSBrr = 1715,
+ PMINSDrm = 1716,
+ PMINSDrr = 1717,
+ PMINSWrm = 1718,
+ PMINSWrr = 1719,
+ PMINUBrm = 1720,
+ PMINUBrr = 1721,
+ PMINUDrm = 1722,
+ PMINUDrr = 1723,
+ PMINUWrm = 1724,
+ PMINUWrr = 1725,
+ PMOVMSKBrr = 1726,
+ PMOVSXBDrm = 1727,
+ PMOVSXBDrr = 1728,
+ PMOVSXBQrm = 1729,
+ PMOVSXBQrr = 1730,
+ PMOVSXBWrm = 1731,
+ PMOVSXBWrr = 1732,
+ PMOVSXDQrm = 1733,
+ PMOVSXDQrr = 1734,
+ PMOVSXWDrm = 1735,
+ PMOVSXWDrr = 1736,
+ PMOVSXWQrm = 1737,
+ PMOVSXWQrr = 1738,
+ PMOVZXBDrm = 1739,
+ PMOVZXBDrr = 1740,
+ PMOVZXBQrm = 1741,
+ PMOVZXBQrr = 1742,
+ PMOVZXBWrm = 1743,
+ PMOVZXBWrr = 1744,
+ PMOVZXDQrm = 1745,
+ PMOVZXDQrr = 1746,
+ PMOVZXWDrm = 1747,
+ PMOVZXWDrr = 1748,
+ PMOVZXWQrm = 1749,
+ PMOVZXWQrr = 1750,
+ PMULDQrm = 1751,
+ PMULDQrr = 1752,
+ PMULHRSWrm128 = 1753,
+ PMULHRSWrm64 = 1754,
+ PMULHRSWrr128 = 1755,
+ PMULHRSWrr64 = 1756,
+ PMULHUWrm = 1757,
+ PMULHUWrr = 1758,
+ PMULHWrm = 1759,
+ PMULHWrr = 1760,
+ PMULLDrm = 1761,
+ PMULLDrm_int = 1762,
+ PMULLDrr = 1763,
+ PMULLDrr_int = 1764,
+ PMULLWrm = 1765,
+ PMULLWrr = 1766,
+ PMULUDQrm = 1767,
+ PMULUDQrr = 1768,
+ POP16r = 1769,
+ POP16rmm = 1770,
+ POP16rmr = 1771,
+ POP32r = 1772,
+ POP32rmm = 1773,
+ POP32rmr = 1774,
+ POP64r = 1775,
+ POP64rmm = 1776,
+ POP64rmr = 1777,
+ POPCNT16rm = 1778,
+ POPCNT16rr = 1779,
+ POPCNT32rm = 1780,
+ POPCNT32rr = 1781,
+ POPCNT64rm = 1782,
+ POPCNT64rr = 1783,
+ POPF = 1784,
+ POPFD = 1785,
+ POPFQ = 1786,
+ POPFS16 = 1787,
+ POPFS32 = 1788,
+ POPFS64 = 1789,
+ POPGS16 = 1790,
+ POPGS32 = 1791,
+ POPGS64 = 1792,
+ PORrm = 1793,
+ PORrr = 1794,
+ PREFETCHNTA = 1795,
+ PREFETCHT0 = 1796,
+ PREFETCHT1 = 1797,
+ PREFETCHT2 = 1798,
+ PSADBWrm = 1799,
+ PSADBWrr = 1800,
+ PSHUFBrm128 = 1801,
+ PSHUFBrm64 = 1802,
+ PSHUFBrr128 = 1803,
+ PSHUFBrr64 = 1804,
+ PSHUFDmi = 1805,
+ PSHUFDri = 1806,
+ PSHUFHWmi = 1807,
+ PSHUFHWri = 1808,
+ PSHUFLWmi = 1809,
+ PSHUFLWri = 1810,
+ PSIGNBrm128 = 1811,
+ PSIGNBrm64 = 1812,
+ PSIGNBrr128 = 1813,
+ PSIGNBrr64 = 1814,
+ PSIGNDrm128 = 1815,
+ PSIGNDrm64 = 1816,
+ PSIGNDrr128 = 1817,
+ PSIGNDrr64 = 1818,
+ PSIGNWrm128 = 1819,
+ PSIGNWrm64 = 1820,
+ PSIGNWrr128 = 1821,
+ PSIGNWrr64 = 1822,
+ PSLLDQri = 1823,
+ PSLLDri = 1824,
+ PSLLDrm = 1825,
+ PSLLDrr = 1826,
+ PSLLQri = 1827,
+ PSLLQrm = 1828,
+ PSLLQrr = 1829,
+ PSLLWri = 1830,
+ PSLLWrm = 1831,
+ PSLLWrr = 1832,
+ PSRADri = 1833,
+ PSRADrm = 1834,
+ PSRADrr = 1835,
+ PSRAWri = 1836,
+ PSRAWrm = 1837,
+ PSRAWrr = 1838,
+ PSRLDQri = 1839,
+ PSRLDri = 1840,
+ PSRLDrm = 1841,
+ PSRLDrr = 1842,
+ PSRLQri = 1843,
+ PSRLQrm = 1844,
+ PSRLQrr = 1845,
+ PSRLWri = 1846,
+ PSRLWrm = 1847,
+ PSRLWrr = 1848,
+ PSUBBrm = 1849,
+ PSUBBrr = 1850,
+ PSUBDrm = 1851,
+ PSUBDrr = 1852,
+ PSUBQrm = 1853,
+ PSUBQrr = 1854,
+ PSUBSBrm = 1855,
+ PSUBSBrr = 1856,
+ PSUBSWrm = 1857,
+ PSUBSWrr = 1858,
+ PSUBUSBrm = 1859,
+ PSUBUSBrr = 1860,
+ PSUBUSWrm = 1861,
+ PSUBUSWrr = 1862,
+ PSUBWrm = 1863,
+ PSUBWrr = 1864,
+ PTESTrm = 1865,
+ PTESTrr = 1866,
+ PUNPCKHBWrm = 1867,
+ PUNPCKHBWrr = 1868,
+ PUNPCKHDQrm = 1869,
+ PUNPCKHDQrr = 1870,
+ PUNPCKHQDQrm = 1871,
+ PUNPCKHQDQrr = 1872,
+ PUNPCKHWDrm = 1873,
+ PUNPCKHWDrr = 1874,
+ PUNPCKLBWrm = 1875,
+ PUNPCKLBWrr = 1876,
+ PUNPCKLDQrm = 1877,
+ PUNPCKLDQrr = 1878,
+ PUNPCKLQDQrm = 1879,
+ PUNPCKLQDQrr = 1880,
+ PUNPCKLWDrm = 1881,
+ PUNPCKLWDrr = 1882,
+ PUSH16r = 1883,
+ PUSH16rmm = 1884,
+ PUSH16rmr = 1885,
+ PUSH32i16 = 1886,
+ PUSH32i32 = 1887,
+ PUSH32i8 = 1888,
+ PUSH32r = 1889,
+ PUSH32rmm = 1890,
+ PUSH32rmr = 1891,
+ PUSH64i16 = 1892,
+ PUSH64i32 = 1893,
+ PUSH64i8 = 1894,
+ PUSH64r = 1895,
+ PUSH64rmm = 1896,
+ PUSH64rmr = 1897,
+ PUSHF = 1898,
+ PUSHFD = 1899,
+ PUSHFQ64 = 1900,
+ PUSHFS16 = 1901,
+ PUSHFS32 = 1902,
+ PUSHFS64 = 1903,
+ PUSHGS16 = 1904,
+ PUSHGS32 = 1905,
+ PUSHGS64 = 1906,
+ PXORrm = 1907,
+ PXORrr = 1908,
+ RCL16m1 = 1909,
+ RCL16mCL = 1910,
+ RCL16mi = 1911,
+ RCL16r1 = 1912,
+ RCL16rCL = 1913,
+ RCL16ri = 1914,
+ RCL32m1 = 1915,
+ RCL32mCL = 1916,
+ RCL32mi = 1917,
+ RCL32r1 = 1918,
+ RCL32rCL = 1919,
+ RCL32ri = 1920,
+ RCL64m1 = 1921,
+ RCL64mCL = 1922,
+ RCL64mi = 1923,
+ RCL64r1 = 1924,
+ RCL64rCL = 1925,
+ RCL64ri = 1926,
+ RCL8m1 = 1927,
+ RCL8mCL = 1928,
+ RCL8mi = 1929,
+ RCL8r1 = 1930,
+ RCL8rCL = 1931,
+ RCL8ri = 1932,
+ RCPPSm = 1933,
+ RCPPSm_Int = 1934,
+ RCPPSr = 1935,
+ RCPPSr_Int = 1936,
+ RCPSSm = 1937,
+ RCPSSm_Int = 1938,
+ RCPSSr = 1939,
+ RCPSSr_Int = 1940,
+ RCR16m1 = 1941,
+ RCR16mCL = 1942,
+ RCR16mi = 1943,
+ RCR16r1 = 1944,
+ RCR16rCL = 1945,
+ RCR16ri = 1946,
+ RCR32m1 = 1947,
+ RCR32mCL = 1948,
+ RCR32mi = 1949,
+ RCR32r1 = 1950,
+ RCR32rCL = 1951,
+ RCR32ri = 1952,
+ RCR64m1 = 1953,
+ RCR64mCL = 1954,
+ RCR64mi = 1955,
+ RCR64r1 = 1956,
+ RCR64rCL = 1957,
+ RCR64ri = 1958,
+ RCR8m1 = 1959,
+ RCR8mCL = 1960,
+ RCR8mi = 1961,
+ RCR8r1 = 1962,
+ RCR8rCL = 1963,
+ RCR8ri = 1964,
+ RDMSR = 1965,
+ RDPMC = 1966,
+ RDTSC = 1967,
+ REP_MOVSB = 1968,
+ REP_MOVSD = 1969,
+ REP_MOVSQ = 1970,
+ REP_MOVSW = 1971,
+ REP_STOSB = 1972,
+ REP_STOSD = 1973,
+ REP_STOSQ = 1974,
+ REP_STOSW = 1975,
+ RET = 1976,
+ RETI = 1977,
+ ROL16m1 = 1978,
+ ROL16mCL = 1979,
+ ROL16mi = 1980,
+ ROL16r1 = 1981,
+ ROL16rCL = 1982,
+ ROL16ri = 1983,
+ ROL32m1 = 1984,
+ ROL32mCL = 1985,
+ ROL32mi = 1986,
+ ROL32r1 = 1987,
+ ROL32rCL = 1988,
+ ROL32ri = 1989,
+ ROL64m1 = 1990,
+ ROL64mCL = 1991,
+ ROL64mi = 1992,
+ ROL64r1 = 1993,
+ ROL64rCL = 1994,
+ ROL64ri = 1995,
+ ROL8m1 = 1996,
+ ROL8mCL = 1997,
+ ROL8mi = 1998,
+ ROL8r1 = 1999,
+ ROL8rCL = 2000,
+ ROL8ri = 2001,
+ ROR16m1 = 2002,
+ ROR16mCL = 2003,
+ ROR16mi = 2004,
+ ROR16r1 = 2005,
+ ROR16rCL = 2006,
+ ROR16ri = 2007,
+ ROR32m1 = 2008,
+ ROR32mCL = 2009,
+ ROR32mi = 2010,
+ ROR32r1 = 2011,
+ ROR32rCL = 2012,
+ ROR32ri = 2013,
+ ROR64m1 = 2014,
+ ROR64mCL = 2015,
+ ROR64mi = 2016,
+ ROR64r1 = 2017,
+ ROR64rCL = 2018,
+ ROR64ri = 2019,
+ ROR8m1 = 2020,
+ ROR8mCL = 2021,
+ ROR8mi = 2022,
+ ROR8r1 = 2023,
+ ROR8rCL = 2024,
+ ROR8ri = 2025,
+ ROUNDPDm_Int = 2026,
+ ROUNDPDr_Int = 2027,
+ ROUNDPSm_Int = 2028,
+ ROUNDPSr_Int = 2029,
+ ROUNDSDm_Int = 2030,
+ ROUNDSDr_Int = 2031,
+ ROUNDSSm_Int = 2032,
+ ROUNDSSr_Int = 2033,
+ RSM = 2034,
+ RSQRTPSm = 2035,
+ RSQRTPSm_Int = 2036,
+ RSQRTPSr = 2037,
+ RSQRTPSr_Int = 2038,
+ RSQRTSSm = 2039,
+ RSQRTSSm_Int = 2040,
+ RSQRTSSr = 2041,
+ RSQRTSSr_Int = 2042,
+ SAHF = 2043,
+ SAR16m1 = 2044,
+ SAR16mCL = 2045,
+ SAR16mi = 2046,
+ SAR16r1 = 2047,
+ SAR16rCL = 2048,
+ SAR16ri = 2049,
+ SAR32m1 = 2050,
+ SAR32mCL = 2051,
+ SAR32mi = 2052,
+ SAR32r1 = 2053,
+ SAR32rCL = 2054,
+ SAR32ri = 2055,
+ SAR64m1 = 2056,
+ SAR64mCL = 2057,
+ SAR64mi = 2058,
+ SAR64r1 = 2059,
+ SAR64rCL = 2060,
+ SAR64ri = 2061,
+ SAR8m1 = 2062,
+ SAR8mCL = 2063,
+ SAR8mi = 2064,
+ SAR8r1 = 2065,
+ SAR8rCL = 2066,
+ SAR8ri = 2067,
+ SBB16i16 = 2068,
+ SBB16mi = 2069,
+ SBB16mi8 = 2070,
+ SBB16mr = 2071,
+ SBB16ri = 2072,
+ SBB16ri8 = 2073,
+ SBB16rm = 2074,
+ SBB16rr = 2075,
+ SBB16rr_REV = 2076,
+ SBB32i32 = 2077,
+ SBB32mi = 2078,
+ SBB32mi8 = 2079,
+ SBB32mr = 2080,
+ SBB32ri = 2081,
+ SBB32ri8 = 2082,
+ SBB32rm = 2083,
+ SBB32rr = 2084,
+ SBB32rr_REV = 2085,
+ SBB64i32 = 2086,
+ SBB64mi32 = 2087,
+ SBB64mi8 = 2088,
+ SBB64mr = 2089,
+ SBB64ri32 = 2090,
+ SBB64ri8 = 2091,
+ SBB64rm = 2092,
+ SBB64rr = 2093,
+ SBB64rr_REV = 2094,
+ SBB8i8 = 2095,
+ SBB8mi = 2096,
+ SBB8mr = 2097,
+ SBB8ri = 2098,
+ SBB8rm = 2099,
+ SBB8rr = 2100,
+ SBB8rr_REV = 2101,
+ SCAS16 = 2102,
+ SCAS32 = 2103,
+ SCAS64 = 2104,
+ SCAS8 = 2105,
+ SETAEm = 2106,
+ SETAEr = 2107,
+ SETAm = 2108,
+ SETAr = 2109,
+ SETBEm = 2110,
+ SETBEr = 2111,
+ SETB_C16r = 2112,
+ SETB_C32r = 2113,
+ SETB_C64r = 2114,
+ SETB_C8r = 2115,
+ SETBm = 2116,
+ SETBr = 2117,
+ SETEm = 2118,
+ SETEr = 2119,
+ SETGEm = 2120,
+ SETGEr = 2121,
+ SETGm = 2122,
+ SETGr = 2123,
+ SETLEm = 2124,
+ SETLEr = 2125,
+ SETLm = 2126,
+ SETLr = 2127,
+ SETNEm = 2128,
+ SETNEr = 2129,
+ SETNOm = 2130,
+ SETNOr = 2131,
+ SETNPm = 2132,
+ SETNPr = 2133,
+ SETNSm = 2134,
+ SETNSr = 2135,
+ SETOm = 2136,
+ SETOr = 2137,
+ SETPm = 2138,
+ SETPr = 2139,
+ SETSm = 2140,
+ SETSr = 2141,
+ SFENCE = 2142,
+ SGDTm = 2143,
+ SHL16m1 = 2144,
+ SHL16mCL = 2145,
+ SHL16mi = 2146,
+ SHL16r1 = 2147,
+ SHL16rCL = 2148,
+ SHL16ri = 2149,
+ SHL32m1 = 2150,
+ SHL32mCL = 2151,
+ SHL32mi = 2152,
+ SHL32r1 = 2153,
+ SHL32rCL = 2154,
+ SHL32ri = 2155,
+ SHL64m1 = 2156,
+ SHL64mCL = 2157,
+ SHL64mi = 2158,
+ SHL64r1 = 2159,
+ SHL64rCL = 2160,
+ SHL64ri = 2161,
+ SHL8m1 = 2162,
+ SHL8mCL = 2163,
+ SHL8mi = 2164,
+ SHL8r1 = 2165,
+ SHL8rCL = 2166,
+ SHL8ri = 2167,
+ SHLD16mrCL = 2168,
+ SHLD16mri8 = 2169,
+ SHLD16rrCL = 2170,
+ SHLD16rri8 = 2171,
+ SHLD32mrCL = 2172,
+ SHLD32mri8 = 2173,
+ SHLD32rrCL = 2174,
+ SHLD32rri8 = 2175,
+ SHLD64mrCL = 2176,
+ SHLD64mri8 = 2177,
+ SHLD64rrCL = 2178,
+ SHLD64rri8 = 2179,
+ SHR16m1 = 2180,
+ SHR16mCL = 2181,
+ SHR16mi = 2182,
+ SHR16r1 = 2183,
+ SHR16rCL = 2184,
+ SHR16ri = 2185,
+ SHR32m1 = 2186,
+ SHR32mCL = 2187,
+ SHR32mi = 2188,
+ SHR32r1 = 2189,
+ SHR32rCL = 2190,
+ SHR32ri = 2191,
+ SHR64m1 = 2192,
+ SHR64mCL = 2193,
+ SHR64mi = 2194,
+ SHR64r1 = 2195,
+ SHR64rCL = 2196,
+ SHR64ri = 2197,
+ SHR8m1 = 2198,
+ SHR8mCL = 2199,
+ SHR8mi = 2200,
+ SHR8r1 = 2201,
+ SHR8rCL = 2202,
+ SHR8ri = 2203,
+ SHRD16mrCL = 2204,
+ SHRD16mri8 = 2205,
+ SHRD16rrCL = 2206,
+ SHRD16rri8 = 2207,
+ SHRD32mrCL = 2208,
+ SHRD32mri8 = 2209,
+ SHRD32rrCL = 2210,
+ SHRD32rri8 = 2211,
+ SHRD64mrCL = 2212,
+ SHRD64mri8 = 2213,
+ SHRD64rrCL = 2214,
+ SHRD64rri8 = 2215,
+ SHUFPDrmi = 2216,
+ SHUFPDrri = 2217,
+ SHUFPSrmi = 2218,
+ SHUFPSrri = 2219,
+ SIDTm = 2220,
+ SIN_F = 2221,
+ SIN_Fp32 = 2222,
+ SIN_Fp64 = 2223,
+ SIN_Fp80 = 2224,
+ SLDT16m = 2225,
+ SLDT16r = 2226,
+ SLDT64m = 2227,
+ SLDT64r = 2228,
+ SMSW16m = 2229,
+ SMSW16r = 2230,
+ SMSW32r = 2231,
+ SMSW64r = 2232,
+ SQRTPDm = 2233,
+ SQRTPDm_Int = 2234,
+ SQRTPDr = 2235,
+ SQRTPDr_Int = 2236,
+ SQRTPSm = 2237,
+ SQRTPSm_Int = 2238,
+ SQRTPSr = 2239,
+ SQRTPSr_Int = 2240,
+ SQRTSDm = 2241,
+ SQRTSDm_Int = 2242,
+ SQRTSDr = 2243,
+ SQRTSDr_Int = 2244,
+ SQRTSSm = 2245,
+ SQRTSSm_Int = 2246,
+ SQRTSSr = 2247,
+ SQRTSSr_Int = 2248,
+ SQRT_F = 2249,
+ SQRT_Fp32 = 2250,
+ SQRT_Fp64 = 2251,
+ SQRT_Fp80 = 2252,
+ STC = 2253,
+ STD = 2254,
+ STI = 2255,
+ STMXCSR = 2256,
+ STRm = 2257,
+ STRr = 2258,
+ ST_F32m = 2259,
+ ST_F64m = 2260,
+ ST_FP32m = 2261,
+ ST_FP64m = 2262,
+ ST_FP80m = 2263,
+ ST_FPrr = 2264,
+ ST_Fp32m = 2265,
+ ST_Fp64m = 2266,
+ ST_Fp64m32 = 2267,
+ ST_Fp80m32 = 2268,
+ ST_Fp80m64 = 2269,
+ ST_FpP32m = 2270,
+ ST_FpP64m = 2271,
+ ST_FpP64m32 = 2272,
+ ST_FpP80m = 2273,
+ ST_FpP80m32 = 2274,
+ ST_FpP80m64 = 2275,
+ ST_Frr = 2276,
+ SUB16i16 = 2277,
+ SUB16mi = 2278,
+ SUB16mi8 = 2279,
+ SUB16mr = 2280,
+ SUB16ri = 2281,
+ SUB16ri8 = 2282,
+ SUB16rm = 2283,
+ SUB16rr = 2284,
+ SUB16rr_REV = 2285,
+ SUB32i32 = 2286,
+ SUB32mi = 2287,
+ SUB32mi8 = 2288,
+ SUB32mr = 2289,
+ SUB32ri = 2290,
+ SUB32ri8 = 2291,
+ SUB32rm = 2292,
+ SUB32rr = 2293,
+ SUB32rr_REV = 2294,
+ SUB64i32 = 2295,
+ SUB64mi32 = 2296,
+ SUB64mi8 = 2297,
+ SUB64mr = 2298,
+ SUB64ri32 = 2299,
+ SUB64ri8 = 2300,
+ SUB64rm = 2301,
+ SUB64rr = 2302,
+ SUB64rr_REV = 2303,
+ SUB8i8 = 2304,
+ SUB8mi = 2305,
+ SUB8mr = 2306,
+ SUB8ri = 2307,
+ SUB8rm = 2308,
+ SUB8rr = 2309,
+ SUB8rr_REV = 2310,
+ SUBPDrm = 2311,
+ SUBPDrr = 2312,
+ SUBPSrm = 2313,
+ SUBPSrr = 2314,
+ SUBR_F32m = 2315,
+ SUBR_F64m = 2316,
+ SUBR_FI16m = 2317,
+ SUBR_FI32m = 2318,
+ SUBR_FPrST0 = 2319,
+ SUBR_FST0r = 2320,
+ SUBR_Fp32m = 2321,
+ SUBR_Fp64m = 2322,
+ SUBR_Fp64m32 = 2323,
+ SUBR_Fp80m32 = 2324,
+ SUBR_Fp80m64 = 2325,
+ SUBR_FpI16m32 = 2326,
+ SUBR_FpI16m64 = 2327,
+ SUBR_FpI16m80 = 2328,
+ SUBR_FpI32m32 = 2329,
+ SUBR_FpI32m64 = 2330,
+ SUBR_FpI32m80 = 2331,
+ SUBR_FrST0 = 2332,
+ SUBSDrm = 2333,
+ SUBSDrm_Int = 2334,
+ SUBSDrr = 2335,
+ SUBSDrr_Int = 2336,
+ SUBSSrm = 2337,
+ SUBSSrm_Int = 2338,
+ SUBSSrr = 2339,
+ SUBSSrr_Int = 2340,
+ SUB_F32m = 2341,
+ SUB_F64m = 2342,
+ SUB_FI16m = 2343,
+ SUB_FI32m = 2344,
+ SUB_FPrST0 = 2345,
+ SUB_FST0r = 2346,
+ SUB_Fp32 = 2347,
+ SUB_Fp32m = 2348,
+ SUB_Fp64 = 2349,
+ SUB_Fp64m = 2350,
+ SUB_Fp64m32 = 2351,
+ SUB_Fp80 = 2352,
+ SUB_Fp80m32 = 2353,
+ SUB_Fp80m64 = 2354,
+ SUB_FpI16m32 = 2355,
+ SUB_FpI16m64 = 2356,
+ SUB_FpI16m80 = 2357,
+ SUB_FpI32m32 = 2358,
+ SUB_FpI32m64 = 2359,
+ SUB_FpI32m80 = 2360,
+ SUB_FrST0 = 2361,
+ SWPGS = 2362,
+ SYSCALL = 2363,
+ SYSENTER = 2364,
+ SYSEXIT = 2365,
+ SYSEXIT64 = 2366,
+ SYSRET = 2367,
+ TAILJMPd = 2368,
+ TAILJMPm = 2369,
+ TAILJMPr = 2370,
+ TAILJMPr64 = 2371,
+ TCRETURNdi = 2372,
+ TCRETURNdi64 = 2373,
+ TCRETURNri = 2374,
+ TCRETURNri64 = 2375,
+ TEST16i16 = 2376,
+ TEST16mi = 2377,
+ TEST16ri = 2378,
+ TEST16rm = 2379,
+ TEST16rr = 2380,
+ TEST32i32 = 2381,
+ TEST32mi = 2382,
+ TEST32ri = 2383,
+ TEST32rm = 2384,
+ TEST32rr = 2385,
+ TEST64i32 = 2386,
+ TEST64mi32 = 2387,
+ TEST64ri32 = 2388,
+ TEST64rm = 2389,
+ TEST64rr = 2390,
+ TEST8i8 = 2391,
+ TEST8mi = 2392,
+ TEST8ri = 2393,
+ TEST8rm = 2394,
+ TEST8rr = 2395,
+ TLS_addr32 = 2396,
+ TLS_addr64 = 2397,
+ TRAP = 2398,
+ TST_F = 2399,
+ TST_Fp32 = 2400,
+ TST_Fp64 = 2401,
+ TST_Fp80 = 2402,
+ UCOMISDrm = 2403,
+ UCOMISDrr = 2404,
+ UCOMISSrm = 2405,
+ UCOMISSrr = 2406,
+ UCOM_FIPr = 2407,
+ UCOM_FIr = 2408,
+ UCOM_FPPr = 2409,
+ UCOM_FPr = 2410,
+ UCOM_FpIr32 = 2411,
+ UCOM_FpIr64 = 2412,
+ UCOM_FpIr80 = 2413,
+ UCOM_Fpr32 = 2414,
+ UCOM_Fpr64 = 2415,
+ UCOM_Fpr80 = 2416,
+ UCOM_Fr = 2417,
+ UNPCKHPDrm = 2418,
+ UNPCKHPDrr = 2419,
+ UNPCKHPSrm = 2420,
+ UNPCKHPSrr = 2421,
+ UNPCKLPDrm = 2422,
+ UNPCKLPDrr = 2423,
+ UNPCKLPSrm = 2424,
+ UNPCKLPSrr = 2425,
+ VASTART_SAVE_XMM_REGS = 2426,
+ VERRm = 2427,
+ VERRr = 2428,
+ VERWm = 2429,
+ VERWr = 2430,
+ VMCALL = 2431,
+ VMCLEARm = 2432,
+ VMLAUNCH = 2433,
+ VMPTRLDm = 2434,
+ VMPTRSTm = 2435,
+ VMREAD32rm = 2436,
+ VMREAD32rr = 2437,
+ VMREAD64rm = 2438,
+ VMREAD64rr = 2439,
+ VMRESUME = 2440,
+ VMWRITE32rm = 2441,
+ VMWRITE32rr = 2442,
+ VMWRITE64rm = 2443,
+ VMWRITE64rr = 2444,
+ VMXOFF = 2445,
+ VMXON = 2446,
+ V_SET0 = 2447,
+ V_SETALLONES = 2448,
+ WAIT = 2449,
+ WBINVD = 2450,
+ WINCALL64m = 2451,
+ WINCALL64pcrel32 = 2452,
+ WINCALL64r = 2453,
+ WRMSR = 2454,
+ XADD16rm = 2455,
+ XADD16rr = 2456,
+ XADD32rm = 2457,
+ XADD32rr = 2458,
+ XADD64rm = 2459,
+ XADD64rr = 2460,
+ XADD8rm = 2461,
+ XADD8rr = 2462,
+ XCHG16ar = 2463,
+ XCHG16rm = 2464,
+ XCHG16rr = 2465,
+ XCHG32ar = 2466,
+ XCHG32rm = 2467,
+ XCHG32rr = 2468,
+ XCHG64ar = 2469,
+ XCHG64rm = 2470,
+ XCHG64rr = 2471,
+ XCHG8rm = 2472,
+ XCHG8rr = 2473,
+ XCH_F = 2474,
+ XLAT = 2475,
+ XOR16i16 = 2476,
+ XOR16mi = 2477,
+ XOR16mi8 = 2478,
+ XOR16mr = 2479,
+ XOR16ri = 2480,
+ XOR16ri8 = 2481,
+ XOR16rm = 2482,
+ XOR16rr = 2483,
+ XOR16rr_REV = 2484,
+ XOR32i32 = 2485,
+ XOR32mi = 2486,
+ XOR32mi8 = 2487,
+ XOR32mr = 2488,
+ XOR32ri = 2489,
+ XOR32ri8 = 2490,
+ XOR32rm = 2491,
+ XOR32rr = 2492,
+ XOR32rr_REV = 2493,
+ XOR64i32 = 2494,
+ XOR64mi32 = 2495,
+ XOR64mi8 = 2496,
+ XOR64mr = 2497,
+ XOR64ri32 = 2498,
+ XOR64ri8 = 2499,
+ XOR64rm = 2500,
+ XOR64rr = 2501,
+ XOR64rr_REV = 2502,
+ XOR8i8 = 2503,
+ XOR8mi = 2504,
+ XOR8mr = 2505,
+ XOR8ri = 2506,
+ XOR8rm = 2507,
+ XOR8rr = 2508,
+ XOR8rr_REV = 2509,
+ XORPDrm = 2510,
+ XORPDrr = 2511,
+ XORPSrm = 2512,
+ XORPSrr = 2513,
+ INSTRUCTION_LIST_END = 2514
};
}
} // End llvm namespace
diff --git a/libclamav/c++/X86GenRegisterInfo.h.inc b/libclamav/c++/X86GenRegisterInfo.h.inc
index 9e5343e..8279ef8 100644
--- a/libclamav/c++/X86GenRegisterInfo.h.inc
+++ b/libclamav/c++/X86GenRegisterInfo.h.inc
@@ -24,33 +24,36 @@ struct X86GenRegisterInfo : public TargetRegisterInfo {
namespace X86 { // Register classes
enum {
CCRRegClassID = 1,
- FR32RegClassID = 2,
- FR64RegClassID = 3,
- GR16RegClassID = 4,
- GR16_ABCDRegClassID = 5,
- GR16_NOREXRegClassID = 6,
- GR32RegClassID = 7,
- GR32_ABCDRegClassID = 8,
- GR32_ADRegClassID = 9,
- GR32_NOREXRegClassID = 10,
- GR32_NOSPRegClassID = 11,
- GR64RegClassID = 12,
- GR64_ABCDRegClassID = 13,
- GR64_NOREXRegClassID = 14,
- GR64_NOREX_NOSPRegClassID = 15,
- GR64_NOSPRegClassID = 16,
- GR8RegClassID = 17,
- GR8_ABCD_HRegClassID = 18,
- GR8_ABCD_LRegClassID = 19,
- GR8_NOREXRegClassID = 20,
- RFP32RegClassID = 21,
- RFP64RegClassID = 22,
- RFP80RegClassID = 23,
- RSTRegClassID = 24,
- SEGMENT_REGRegClassID = 25,
- VR128RegClassID = 26,
- VR256RegClassID = 27,
- VR64RegClassID = 28
+ CONTROL_REG_32RegClassID = 2,
+ CONTROL_REG_64RegClassID = 3,
+ DEBUG_REGRegClassID = 4,
+ FR32RegClassID = 5,
+ FR64RegClassID = 6,
+ GR16RegClassID = 7,
+ GR16_ABCDRegClassID = 8,
+ GR16_NOREXRegClassID = 9,
+ GR32RegClassID = 10,
+ GR32_ABCDRegClassID = 11,
+ GR32_ADRegClassID = 12,
+ GR32_NOREXRegClassID = 13,
+ GR32_NOSPRegClassID = 14,
+ GR64RegClassID = 15,
+ GR64_ABCDRegClassID = 16,
+ GR64_NOREXRegClassID = 17,
+ GR64_NOREX_NOSPRegClassID = 18,
+ GR64_NOSPRegClassID = 19,
+ GR8RegClassID = 20,
+ GR8_ABCD_HRegClassID = 21,
+ GR8_ABCD_LRegClassID = 22,
+ GR8_NOREXRegClassID = 23,
+ RFP32RegClassID = 24,
+ RFP64RegClassID = 25,
+ RFP80RegClassID = 26,
+ RSTRegClassID = 27,
+ SEGMENT_REGRegClassID = 28,
+ VR128RegClassID = 29,
+ VR256RegClassID = 30,
+ VR64RegClassID = 31
};
struct CCRClass : public TargetRegisterClass {
@@ -58,6 +61,21 @@ namespace X86 { // Register classes
};
extern CCRClass CCRRegClass;
static TargetRegisterClass * const CCRRegisterClass = &CCRRegClass;
+ struct CONTROL_REG_32Class : public TargetRegisterClass {
+ CONTROL_REG_32Class();
+ };
+ extern CONTROL_REG_32Class CONTROL_REG_32RegClass;
+ static TargetRegisterClass * const CONTROL_REG_32RegisterClass = &CONTROL_REG_32RegClass;
+ struct CONTROL_REG_64Class : public TargetRegisterClass {
+ CONTROL_REG_64Class();
+ };
+ extern CONTROL_REG_64Class CONTROL_REG_64RegClass;
+ static TargetRegisterClass * const CONTROL_REG_64RegisterClass = &CONTROL_REG_64RegClass;
+ struct DEBUG_REGClass : public TargetRegisterClass {
+ DEBUG_REGClass();
+ };
+ extern DEBUG_REGClass DEBUG_REGRegClass;
+ static TargetRegisterClass * const DEBUG_REGRegisterClass = &DEBUG_REGRegClass;
struct FR32Class : public TargetRegisterClass {
FR32Class();
diff --git a/libclamav/c++/X86GenRegisterInfo.inc b/libclamav/c++/X86GenRegisterInfo.inc
index 6f4b235..1dd0521 100644
--- a/libclamav/c++/X86GenRegisterInfo.inc
+++ b/libclamav/c++/X86GenRegisterInfo.inc
@@ -14,6 +14,21 @@ namespace { // Register classes...
X86::EFLAGS,
};
+ // CONTROL_REG_32 Register Class...
+ static const unsigned CONTROL_REG_32[] = {
+ X86::ECR0, X86::ECR1, X86::ECR2, X86::ECR3, X86::ECR4, X86::ECR5, X86::ECR6, X86::ECR7,
+ };
+
+ // CONTROL_REG_64 Register Class...
+ static const unsigned CONTROL_REG_64[] = {
+ X86::RCR0, X86::RCR1, X86::RCR2, X86::RCR3, X86::RCR4, X86::RCR5, X86::RCR6, X86::RCR7, X86::RCR8,
+ };
+
+ // DEBUG_REG Register Class...
+ static const unsigned DEBUG_REG[] = {
+ X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7,
+ };
+
// FR32 Register Class...
static const unsigned FR32[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
@@ -154,6 +169,21 @@ namespace { // Register classes...
MVT::i32, MVT::Other
};
+ // CONTROL_REG_32VTs Register Class Value Types...
+ static const EVT CONTROL_REG_32VTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // CONTROL_REG_64VTs Register Class Value Types...
+ static const EVT CONTROL_REG_64VTs[] = {
+ MVT::i64, MVT::Other
+ };
+
+ // DEBUG_REGVTs Register Class Value Types...
+ static const EVT DEBUG_REGVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
// FR32VTs Register Class Value Types...
static const EVT FR32VTs[] = {
MVT::f32, MVT::Other
@@ -293,6 +323,9 @@ namespace { // Register classes...
namespace X86 { // Register class instances
CCRClass CCRRegClass;
+ CONTROL_REG_32Class CONTROL_REG_32RegClass;
+ CONTROL_REG_64Class CONTROL_REG_64RegClass;
+ DEBUG_REGClass DEBUG_REGRegClass;
FR32Class FR32RegClass;
FR64Class FR64RegClass;
GR16Class GR16RegClass;
@@ -326,6 +359,21 @@ namespace X86 { // Register class instances
NULL
};
+ // CONTROL_REG_32 Sub-register Classes...
+ static const TargetRegisterClass* const CONTROL_REG_32SubRegClasses[] = {
+ NULL
+ };
+
+ // CONTROL_REG_64 Sub-register Classes...
+ static const TargetRegisterClass* const CONTROL_REG_64SubRegClasses[] = {
+ NULL
+ };
+
+ // DEBUG_REG Sub-register Classes...
+ static const TargetRegisterClass* const DEBUG_REGSubRegClasses[] = {
+ NULL
+ };
+
// FR32 Sub-register Classes...
static const TargetRegisterClass* const FR32SubRegClasses[] = {
NULL
@@ -466,6 +514,21 @@ namespace X86 { // Register class instances
NULL
};
+ // CONTROL_REG_32 Super-register Classes...
+ static const TargetRegisterClass* const CONTROL_REG_32SuperRegClasses[] = {
+ NULL
+ };
+
+ // CONTROL_REG_64 Super-register Classes...
+ static const TargetRegisterClass* const CONTROL_REG_64SuperRegClasses[] = {
+ NULL
+ };
+
+ // DEBUG_REG Super-register Classes...
+ static const TargetRegisterClass* const DEBUG_REGSuperRegClasses[] = {
+ NULL
+ };
+
// FR32 Super-register Classes...
static const TargetRegisterClass* const FR32SuperRegClasses[] = {
NULL
@@ -606,6 +669,21 @@ namespace X86 { // Register class instances
NULL
};
+ // CONTROL_REG_32 Register Class sub-classes...
+ static const TargetRegisterClass* const CONTROL_REG_32Subclasses[] = {
+ NULL
+ };
+
+ // CONTROL_REG_64 Register Class sub-classes...
+ static const TargetRegisterClass* const CONTROL_REG_64Subclasses[] = {
+ NULL
+ };
+
+ // DEBUG_REG Register Class sub-classes...
+ static const TargetRegisterClass* const DEBUG_REGSubclasses[] = {
+ NULL
+ };
+
// FR32 Register Class sub-classes...
static const TargetRegisterClass* const FR32Subclasses[] = {
&X86::FR64RegClass, &X86::VR128RegClass, NULL
@@ -746,6 +824,21 @@ namespace X86 { // Register class instances
NULL
};
+ // CONTROL_REG_32 Register Class super-classes...
+ static const TargetRegisterClass* const CONTROL_REG_32Superclasses[] = {
+ NULL
+ };
+
+ // CONTROL_REG_64 Register Class super-classes...
+ static const TargetRegisterClass* const CONTROL_REG_64Superclasses[] = {
+ NULL
+ };
+
+ // DEBUG_REG Register Class super-classes...
+ static const TargetRegisterClass* const DEBUG_REGSuperclasses[] = {
+ NULL
+ };
+
// FR32 Register Class super-classes...
static const TargetRegisterClass* const FR32Superclasses[] = {
NULL
@@ -884,6 +977,12 @@ namespace X86 { // Register class instances
CCRClass::CCRClass() : TargetRegisterClass(CCRRegClassID, "CCR", CCRVTs, CCRSubclasses, CCRSuperclasses, CCRSubRegClasses, CCRSuperRegClasses, 4, 4, -1, CCR, CCR + 1) {}
+CONTROL_REG_32Class::CONTROL_REG_32Class() : TargetRegisterClass(CONTROL_REG_32RegClassID, "CONTROL_REG_32", CONTROL_REG_32VTs, CONTROL_REG_32Subclasses, CONTROL_REG_32Superclasses, CONTROL_REG_32SubRegClasses, CONTROL_REG_32SuperRegClasses, 4, 4, 1, CONTROL_REG_32, CONTROL_REG_32 + 8) {}
+
+CONTROL_REG_64Class::CONTROL_REG_64Class() : TargetRegisterClass(CONTROL_REG_64RegClassID, "CONTROL_REG_64", CONTROL_REG_64VTs, CONTROL_REG_64Subclasses, CONTROL_REG_64Superclasses, CONTROL_REG_64SubRegClasses, CONTROL_REG_64SuperRegClasses, 8, 8, 1, CONTROL_REG_64, CONTROL_REG_64 + 9) {}
+
+DEBUG_REGClass::DEBUG_REGClass() : TargetRegisterClass(DEBUG_REGRegClassID, "DEBUG_REG", DEBUG_REGVTs, DEBUG_REGSubclasses, DEBUG_REGSuperclasses, DEBUG_REGSubRegClasses, DEBUG_REGSuperRegClasses, 4, 4, 1, DEBUG_REG, DEBUG_REG + 8) {}
+
FR32Class::iterator
FR32Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
@@ -1103,7 +1202,8 @@ GR64_ABCDClass::GR64_ABCDClass() : TargetRegisterClass(GR64_ABCDRegClassID, "GR
GR64_NOREXClass::GR64_NOREXClass() : TargetRegisterClass(GR64_NOREXRegClassID, "GR64_NOREX", GR64_NOREXVTs, GR64_NOREXSubclasses, GR64_NOREXSuperclasses, GR64_NOREXSubRegClasses, GR64_NOREXSuperRegClasses, 8, 8, 1, GR64_NOREX, GR64_NOREX + 9) {}
GR64_NOREX_NOSPClass::iterator
- GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
+ GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const
+ {
const TargetMachine &TM = MF.getTarget();
const TargetRegisterInfo *RI = TM.getRegisterInfo();
// Does the function dedicate RBP to being a frame ptr?
@@ -1239,6 +1339,9 @@ VR64Class::VR64Class() : TargetRegisterClass(VR64RegClassID, "VR64", VR64VTs, V
namespace {
const TargetRegisterClass* const RegisterClasses[] = {
&X86::CCRRegClass,
+ &X86::CONTROL_REG_32RegClass,
+ &X86::CONTROL_REG_64RegClass,
+ &X86::DEBUG_REGRegClass,
&X86::FR32RegClass,
&X86::FR64RegClass,
&X86::GR16RegClass,
@@ -1269,37 +1372,38 @@ namespace {
};
- // Number of hash collisions: 20
+ // Number of hash collisions: 14
const unsigned SubregHashTable[] = { X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R11, X86::R11D,
- X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R14, X86::R14B,
X86::NoRegister, X86::NoRegister,
+ X86::R14D, X86::R14B,
+ X86::R14W, X86::R14B,
+ X86::EDX, X86::DH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RCX, X86::CX,
X86::NoRegister, X86::NoRegister,
+ X86::RDI, X86::EDI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R9, X86::R9W,
X86::NoRegister, X86::NoRegister,
- X86::RIP, X86::EIP,
+ X86::R9D, X86::R9W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EIP, X86::IP,
X86::NoRegister, X86::NoRegister,
- X86::EDI, X86::DI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1309,46 +1413,52 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R11, X86::R11W,
X86::AX, X86::AH,
- X86::R11D, X86::R11W,
X86::NoRegister, X86::NoRegister,
+ X86::R14, X86::R14D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EDI, X86::DI,
+ X86::RCX, X86::CX,
X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::EDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DI, X86::DIL,
X86::NoRegister, X86::NoRegister,
- X86::RDX, X86::DH,
X86::NoRegister, X86::NoRegister,
- X86::EAX, X86::AH,
- X86::DI, X86::DIL,
X86::NoRegister, X86::NoRegister,
+ X86::R11, X86::R11B,
X86::NoRegister, X86::NoRegister,
+ X86::R11D, X86::R11B,
+ X86::EAX, X86::AH,
X86::NoRegister, X86::NoRegister,
- X86::R15, X86::R15B,
+ X86::R11W, X86::R11B,
X86::NoRegister, X86::NoRegister,
- X86::R15D, X86::R15B,
- X86::R15W, X86::R15B,
X86::NoRegister, X86::NoRegister,
- X86::EDI, X86::DIL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::EAX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::AX, X86::AL,
X86::NoRegister, X86::NoRegister,
+ X86::R14, X86::R14W,
X86::NoRegister, X86::NoRegister,
+ X86::R14D, X86::R14W,
+ X86::EDI, X86::DIL,
X86::NoRegister, X86::NoRegister,
- X86::AX, X86::AL,
X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1360,73 +1470,76 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDI, X86::DI,
X86::NoRegister, X86::NoRegister,
+ X86::R11, X86::R11D,
X86::NoRegister, X86::NoRegister,
+ X86::RIP, X86::IP,
X86::EAX, X86::AL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::DX, X86::DL,
- X86::RSI, X86::ESI,
- X86::R15, X86::R15D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RBP, X86::EBP,
X86::NoRegister, X86::NoRegister,
- X86::EDX, X86::DL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RDI, X86::DI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::DL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R12, X86::R12B,
X86::NoRegister, X86::NoRegister,
- X86::R12D, X86::R12B,
- X86::R12W, X86::R12B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RAX, X86::AH,
X86::NoRegister, X86::NoRegister,
+ X86::RIP, X86::EIP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDI, X86::DIL,
X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::AH,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11, X86::R11W,
X86::NoRegister, X86::NoRegister,
+ X86::R11D, X86::R11W,
X86::EAX, X86::AX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R15, X86::R15W,
X86::NoRegister, X86::NoRegister,
- X86::R15D, X86::R15W,
X86::NoRegister, X86::NoRegister,
- X86::RSP, X86::ESP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::EBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RDI, X86::DIL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::BH,
+ X86::R15, X86::R15B,
X86::NoRegister, X86::NoRegister,
+ X86::R15D, X86::R15B,
+ X86::R15W, X86::R15B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R12, X86::R12D,
X86::NoRegister, X86::NoRegister,
- X86::BX, X86::BH,
+ X86::ESI, X86::SI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1435,8 +1548,6 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDX, X86::DL,
- X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::EBX, X86::BH,
@@ -1448,24 +1559,26 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EDX, X86::DX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::BL,
+ X86::R15, X86::R15D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R12, X86::R12W,
X86::NoRegister, X86::NoRegister,
- X86::BX, X86::BL,
X86::NoRegister, X86::NoRegister,
- X86::R12D, X86::R12W,
+ X86::ESI, X86::SIL,
+ X86::RSI, X86::ESI,
+ X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::RAX, X86::AX,
X86::NoRegister, X86::NoRegister,
@@ -1473,93 +1586,95 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R12, X86::R12B,
+ X86::EBX, X86::BL,
+ X86::R12D, X86::R12B,
+ X86::R12W, X86::R12B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EBX, X86::BL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R8, X86::R8B,
X86::NoRegister, X86::NoRegister,
- X86::R8D, X86::R8B,
- X86::R8W, X86::R8B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R15, X86::R15W,
X86::NoRegister, X86::NoRegister,
+ X86::R15D, X86::R15W,
+ X86::RSI, X86::SI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::ESP, X86::SP,
+ X86::RSP, X86::ESP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RBX, X86::BH,
X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::BH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::BP,
X86::NoRegister, X86::NoRegister,
+ X86::R12, X86::R12D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDX, X86::DX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EBP, X86::BP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ESI, X86::SI,
- X86::R8, X86::R8D,
X86::NoRegister, X86::NoRegister,
+ X86::BP, X86::BPL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RSI, X86::SIL,
X86::NoRegister, X86::NoRegister,
+ X86::SI, X86::SIL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::ESP, X86::SPL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::BP, X86::BPL,
X86::NoRegister, X86::NoRegister,
X86::RBX, X86::BL,
X86::NoRegister, X86::NoRegister,
- X86::R13, X86::R13B,
X86::NoRegister, X86::NoRegister,
- X86::R13D, X86::R13B,
- X86::R13W, X86::R13B,
- X86::RAX, X86::EAX,
X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::BPL,
X86::NoRegister, X86::NoRegister,
+ X86::R12, X86::R12W,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12D, X86::R12W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EBP, X86::BPL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ESI, X86::SIL,
- X86::R8, X86::R8W,
X86::NoRegister, X86::NoRegister,
- X86::R8D, X86::R8W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1567,38 +1682,35 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R8, X86::R8B,
X86::NoRegister, X86::NoRegister,
+ X86::R8D, X86::R8B,
+ X86::R8W, X86::R8B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RSP, X86::SP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::RBP, X86::BP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R13, X86::R13D,
X86::NoRegister, X86::NoRegister,
- X86::RSI, X86::SI,
- X86::RBP, X86::EBP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::BX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EBX, X86::BX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ESP, X86::SP,
- X86::R10, X86::R10B,
X86::NoRegister, X86::NoRegister,
- X86::R10D, X86::R10B,
- X86::R10W, X86::R10B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1606,39 +1718,35 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::CH,
+ X86::R8, X86::R8D,
X86::NoRegister, X86::NoRegister,
+ X86::RSP, X86::SPL,
+ X86::SP, X86::SPL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RBP, X86::BPL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R13, X86::R13W,
X86::NoRegister, X86::NoRegister,
- X86::CX, X86::CH,
+ X86::RBP, X86::BPL,
X86::NoRegister, X86::NoRegister,
- X86::R13D, X86::R13W,
X86::NoRegister, X86::NoRegister,
- X86::RBX, X86::EBX,
X86::NoRegister, X86::NoRegister,
- X86::RSI, X86::SIL,
X86::NoRegister, X86::NoRegister,
- X86::SI, X86::SIL,
X86::NoRegister, X86::NoRegister,
- X86::ECX, X86::CH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R13, X86::R13B,
X86::NoRegister, X86::NoRegister,
+ X86::R13D, X86::R13B,
+ X86::R13W, X86::R13B,
X86::NoRegister, X86::NoRegister,
- X86::ESP, X86::SPL,
- X86::R10, X86::R10D,
X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CH,
X86::NoRegister, X86::NoRegister,
- X86::R9, X86::R9B,
X86::NoRegister, X86::NoRegister,
- X86::R9D, X86::R9B,
- X86::R9W, X86::R9B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1647,35 +1755,33 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::CL,
+ X86::R8, X86::R8W,
X86::NoRegister, X86::NoRegister,
- X86::RBX, X86::BX,
+ X86::R8D, X86::R8W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::CX, X86::CL,
- X86::RSP, X86::SP,
X86::NoRegister, X86::NoRegister,
- X86::RCX, X86::ECX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::BX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ECX, X86::CL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R13, X86::R13D,
X86::NoRegister, X86::NoRegister,
- X86::R10, X86::R10W,
X86::NoRegister, X86::NoRegister,
- X86::R10D, X86::R10W,
- X86::R9, X86::R9D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1686,20 +1792,16 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RCX, X86::CH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R10, X86::R10B,
X86::NoRegister, X86::NoRegister,
- X86::RSP, X86::SPL,
- X86::R14, X86::R14B,
+ X86::R10D, X86::R10B,
+ X86::R10W, X86::R10B,
X86::NoRegister, X86::NoRegister,
- X86::R14D, X86::R14B,
- X86::R14W, X86::R14B,
- X86::RDI, X86::EDI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::SP, X86::SPL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1709,13 +1811,13 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R9, X86::R9W,
X86::NoRegister, X86::NoRegister,
- X86::R9D, X86::R9W,
+ X86::R13, X86::R13W,
X86::NoRegister, X86::NoRegister,
+ X86::R13D, X86::R13W,
X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::CH,
X86::NoRegister, X86::NoRegister,
- X86::EIP, X86::IP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1723,20 +1825,20 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RCX, X86::CL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R14, X86::R14D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDX, X86::EDX,
+ X86::R10, X86::R10D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R9, X86::R9B,
X86::NoRegister, X86::NoRegister,
+ X86::R9D, X86::R9B,
+ X86::R9W, X86::R9B,
X86::NoRegister, X86::NoRegister,
- X86::ECX, X86::CX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1747,14 +1849,13 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R11, X86::R11B,
X86::NoRegister, X86::NoRegister,
- X86::R11D, X86::R11B,
- X86::R11W, X86::R11B,
X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::CL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1762,22 +1863,24 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::DX,
X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::ECX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R14, X86::R14W,
+ X86::R10, X86::R10W,
X86::NoRegister, X86::NoRegister,
- X86::R14D, X86::R14W,
+ X86::R10D, X86::R10W,
+ X86::R9, X86::R9D,
X86::NoRegister, X86::NoRegister,
- X86::DX, X86::DH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EDX, X86::DH,
X86::NoRegister, X86::NoRegister,
- X86::RIP, X86::IP,
+ X86::NoRegister, X86::NoRegister,
+ X86::DX, X86::DH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1785,80 +1888,88 @@ X86::NoRegister, X86::NoRegister };
const unsigned SubregHashTableSize = 512;
- // Number of hash collisions: 15
- const unsigned SuperregHashTable[] = { X86::NoRegister, X86::NoRegister,
+ // Number of hash collisions: 18
+ const unsigned SuperregHashTable[] = { X86::DX, X86::RDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R11B, X86::R11D,
X86::NoRegister, X86::NoRegister,
- X86::R11W, X86::R11D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::CH, X86::RCX,
- X86::CL, X86::RCX,
X86::NoRegister, X86::NoRegister,
- X86::CX, X86::RCX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::BP, X86::RBP,
+ X86::BPL, X86::RBP,
X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::RDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::BP, X86::EBP,
+ X86::BPL, X86::EBP,
X86::NoRegister, X86::NoRegister,
X86::DIL, X86::DI,
X86::NoRegister, X86::NoRegister,
- X86::ECX, X86::RCX,
- X86::NoRegister, X86::NoRegister,
- X86::R15B, X86::R15,
- X86::R15D, X86::R15,
- X86::R15W, X86::R15,
- X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R9B, X86::R9W,
+ X86::R11B, X86::R11,
+ X86::R11D, X86::R11,
+ X86::R11W, X86::R11,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::RBP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R11B, X86::R11W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R14D, X86::R14,
+ X86::R14B, X86::R14D,
X86::NoRegister, X86::NoRegister,
+ X86::R14W, X86::R14D,
+ X86::BH, X86::RBX,
+ X86::BL, X86::RBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::RBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DI, X86::RDI,
- X86::DIL, X86::RDI,
+ X86::BH, X86::EBX,
+ X86::BL, X86::EBX,
+ X86::EIP, X86::RIP,
X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::EBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EDI, X86::RDI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::IP, X86::RIP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::RBX,
X86::NoRegister, X86::NoRegister,
+ X86::IP, X86::EIP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R14B, X86::R14W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1867,29 +1978,21 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R12B, X86::R12,
- X86::R12D, X86::R12,
- X86::R12W, X86::R12,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DH, X86::RDX,
X86::NoRegister, X86::NoRegister,
+ X86::ESI, X86::RSI,
X86::NoRegister, X86::NoRegister,
- X86::DL, X86::RDX,
X86::NoRegister, X86::NoRegister,
- X86::DX, X86::RDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R11B, X86::R11D,
X86::NoRegister, X86::NoRegister,
- X86::EDX, X86::RDX,
+ X86::R11W, X86::R11D,
X86::NoRegister, X86::NoRegister,
- X86::R15B, X86::R15D,
X86::NoRegister, X86::NoRegister,
- X86::R15W, X86::R15D,
- X86::SIL, X86::ESI,
- X86::SI, X86::ESI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1907,27 +2010,28 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R15B, X86::R15,
+ X86::R15D, X86::R15,
+ X86::R15W, X86::R15,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::ESP, X86::RSP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R11B, X86::R11W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EIP, X86::RIP,
X86::NoRegister, X86::NoRegister,
- X86::R15B, X86::R15W,
X86::NoRegister, X86::NoRegister,
- X86::SP, X86::ESP,
- X86::SPL, X86::ESP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1935,40 +2039,38 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::IP, X86::RIP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R12B, X86::R12D,
X86::NoRegister, X86::NoRegister,
- X86::R12W, X86::R12D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::SI, X86::RSI,
+ X86::SIL, X86::RSI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DH, X86::DX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DL, X86::DX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ESI, X86::RSI,
X86::NoRegister, X86::NoRegister,
- X86::R8B, X86::R8,
- X86::R8D, X86::R8,
- X86::R8W, X86::R8,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R12B, X86::R12,
+ X86::R12D, X86::R12,
+ X86::R12W, X86::R12,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1978,28 +2080,29 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::AH, X86::EAX,
- X86::AL, X86::EAX,
- X86::AX, X86::EAX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R12B, X86::R12W,
X86::NoRegister, X86::NoRegister,
+ X86::R15B, X86::R15D,
X86::NoRegister, X86::NoRegister,
+ X86::R15W, X86::R15D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::SP, X86::RSP,
+ X86::SPL, X86::RSP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::SI, X86::ESI,
+ X86::SIL, X86::ESI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ESP, X86::RSP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2018,17 +2121,12 @@ X86::NoRegister, X86::NoRegister };
X86::BPL, X86::BP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R15B, X86::R15W,
X86::NoRegister, X86::NoRegister,
- X86::R13B, X86::R13,
- X86::BP, X86::EBP,
- X86::BPL, X86::EBP,
- X86::R13D, X86::R13,
- X86::R13W, X86::R13,
- X86::SI, X86::RSI,
- X86::SIL, X86::RSI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::SIL, X86::SI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2036,13 +2134,15 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::SP, X86::ESP,
+ X86::SPL, X86::ESP,
X86::NoRegister, X86::NoRegister,
- X86::R8B, X86::R8D,
X86::NoRegister, X86::NoRegister,
- X86::R8W, X86::R8D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R12B, X86::R12D,
X86::NoRegister, X86::NoRegister,
+ X86::R12W, X86::R12D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2055,18 +2155,16 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::BH, X86::EBX,
- X86::BL, X86::EBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::BX, X86::EBX,
X86::NoRegister, X86::NoRegister,
- X86::SP, X86::RSP,
- X86::SPL, X86::RSP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R8B, X86::R8,
+ X86::R8D, X86::R8,
+ X86::R8W, X86::R8,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2074,34 +2172,25 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R8B, X86::R8W,
- X86::R10B, X86::R10,
- X86::R10D, X86::R10,
- X86::R10W, X86::R10,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R12B, X86::R12W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::BH, X86::BX,
- X86::BL, X86::BX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R13B, X86::R13D,
X86::NoRegister, X86::NoRegister,
- X86::R13W, X86::R13D,
X86::NoRegister, X86::NoRegister,
- X86::CH, X86::ECX,
- X86::CL, X86::ECX,
- X86::SIL, X86::SI,
- X86::CX, X86::ECX,
X86::NoRegister, X86::NoRegister,
+ X86::BH, X86::BX,
+ X86::BL, X86::BX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2113,11 +2202,9 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::SPL, X86::SP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R9B, X86::R9,
- X86::R9D, X86::R9,
- X86::R9W, X86::R9,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2130,8 +2217,10 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R13B, X86::R13W,
X86::NoRegister, X86::NoRegister,
+ X86::R13B, X86::R13,
+ X86::R13D, X86::R13,
+ X86::R13W, X86::R13,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2139,8 +2228,6 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DI, X86::EDI,
- X86::DIL, X86::EDI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2149,9 +2236,9 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R10B, X86::R10D,
+ X86::R8B, X86::R8D,
X86::NoRegister, X86::NoRegister,
- X86::R10W, X86::R10D,
+ X86::R8W, X86::R8D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2171,48 +2258,43 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R14B, X86::R14,
- X86::R14D, X86::R14,
- X86::R14W, X86::R14,
X86::NoRegister, X86::NoRegister,
- X86::DH, X86::EDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DL, X86::EDX,
- X86::SPL, X86::SP,
- X86::DX, X86::EDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R10B, X86::R10W,
- X86::AH, X86::RAX,
- X86::AL, X86::RAX,
- X86::AX, X86::RAX,
X86::NoRegister, X86::NoRegister,
- X86::R9B, X86::R9D,
X86::NoRegister, X86::NoRegister,
- X86::R9W, X86::R9D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R8B, X86::R8W,
+ X86::R10B, X86::R10,
+ X86::R10D, X86::R10,
+ X86::R10W, X86::R10,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::CH, X86::ECX,
+ X86::CL, X86::ECX,
X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::ECX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EAX, X86::RAX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R13B, X86::R13D,
X86::NoRegister, X86::NoRegister,
+ X86::R13W, X86::R13D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2226,30 +2308,28 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R9B, X86::R9W,
- X86::R11B, X86::R11,
- X86::R11D, X86::R11,
- X86::BP, X86::RBP,
- X86::BPL, X86::RBP,
- X86::R11W, X86::R11,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::CH, X86::RCX,
+ X86::CL, X86::RCX,
X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::RCX,
+ X86::R9B, X86::R9,
+ X86::R9D, X86::R9,
+ X86::R9W, X86::R9,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::CH, X86::CX,
- X86::CL, X86::CX,
X86::NoRegister, X86::NoRegister,
+ X86::DI, X86::EDI,
+ X86::DIL, X86::EDI,
X86::NoRegister, X86::NoRegister,
- X86::EBP, X86::RBP,
X86::NoRegister, X86::NoRegister,
- X86::R14B, X86::R14D,
X86::NoRegister, X86::NoRegister,
- X86::R14W, X86::R14D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R13B, X86::R13W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2259,80 +2339,102 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::RCX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::CH, X86::CX,
+ X86::CL, X86::CX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::BH, X86::RBX,
- X86::BL, X86::RBX,
X86::NoRegister, X86::NoRegister,
+ X86::R10B, X86::R10D,
X86::NoRegister, X86::NoRegister,
- X86::BX, X86::RBX,
+ X86::R10W, X86::R10D,
X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::DX,
+ X86::DIL, X86::RDI,
+ X86::DI, X86::RDI,
+ X86::DL, X86::DX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::EDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DL, X86::EDX,
X86::NoRegister, X86::NoRegister,
- X86::IP, X86::EIP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EBX, X86::RBX,
- X86::R14B, X86::R14W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::AH, X86::RAX,
+ X86::AL, X86::RAX,
+ X86::AX, X86::RAX,
+ X86::DX, X86::EDX,
+ X86::R14W, X86::R14,
X86::NoRegister, X86::NoRegister,
+ X86::R14B, X86::R14,
+ X86::AH, X86::EAX,
+ X86::AL, X86::EAX,
+ X86::AX, X86::EAX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EDI, X86::RDI,
X86::NoRegister, X86::NoRegister,
+ X86::R10B, X86::R10W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::RDX,
X86::NoRegister, X86::NoRegister,
+ X86::R9B, X86::R9D,
+ X86::DL, X86::RDX,
+ X86::R9W, X86::R9D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::RAX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister };
const unsigned SuperregHashTableSize = 512;
- // Number of hash collisions: 32
- const unsigned AliasesHashTable[] = { X86::NoRegister, X86::NoRegister,
+ // Number of hash collisions: 23
+ const unsigned AliasesHashTable[] = { X86::DX, X86::RDX,
X86::NoRegister, X86::NoRegister,
- X86::R11, X86::R11D,
- X86::R11B, X86::R11D,
X86::NoRegister, X86::NoRegister,
- X86::R11W, X86::R11D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::CH, X86::RCX,
- X86::CL, X86::RCX,
+ X86::R14, X86::R14B,
X86::NoRegister, X86::NoRegister,
- X86::CX, X86::RCX,
+ X86::R14D, X86::R14B,
+ X86::R14W, X86::R14B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::RDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::BP, X86::EBP,
+ X86::BPL, X86::EBP,
X86::NoRegister, X86::NoRegister,
- X86::ECX, X86::RCX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RIP, X86::EIP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EIP, X86::IP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2341,70 +2443,70 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R11, X86::R11W,
- X86::AX, X86::AH,
- X86::R11D, X86::R11W,
- X86::R11B, X86::R11W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::AX, X86::AH,
X86::NoRegister, X86::NoRegister,
+ X86::R14, X86::R14D,
+ X86::R14B, X86::R14D,
X86::NoRegister, X86::NoRegister,
+ X86::R14W, X86::R14D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DX,
X86::NoRegister, X86::NoRegister,
- X86::DI, X86::RDI,
- X86::DIL, X86::RDI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::BH, X86::EBX,
+ X86::BL, X86::EBX,
+ X86::EIP, X86::RIP,
X86::NoRegister, X86::NoRegister,
- X86::EAX, X86::AH,
+ X86::BX, X86::EBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EDI, X86::RDI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::AH,
X86::NoRegister, X86::NoRegister,
+ X86::IP, X86::RIP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::EAX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::AX, X86::AL,
X86::NoRegister, X86::NoRegister,
+ X86::R14, X86::R14W,
+ X86::R14B, X86::R14W,
+ X86::R14D, X86::R14W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::AX, X86::AL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R12B, X86::R12,
- X86::R12D, X86::R12,
- X86::R12W, X86::R12,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DH, X86::RDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DL, X86::RDX,
X86::NoRegister, X86::NoRegister,
- X86::DX, X86::RDX,
+ X86::ESI, X86::RSI,
X86::NoRegister, X86::NoRegister,
- X86::EAX, X86::AL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EDX, X86::RDX,
X86::NoRegister, X86::NoRegister,
- X86::RSI, X86::ESI,
+ X86::RIP, X86::IP,
X86::NoRegister, X86::NoRegister,
- X86::SI, X86::ESI,
- X86::SIL, X86::ESI,
+ X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::AL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2412,6 +2514,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RBP, X86::EBP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::AH, X86::AX,
@@ -2419,31 +2522,28 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R12, X86::R12B,
X86::NoRegister, X86::NoRegister,
- X86::R12D, X86::R12B,
- X86::R12W, X86::R12B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RAX, X86::AH,
X86::NoRegister, X86::NoRegister,
+ X86::R15B, X86::R15,
+ X86::R15D, X86::R15,
+ X86::R15W, X86::R15,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EAX, X86::AX,
X86::NoRegister, X86::NoRegister,
+ X86::ESP, X86::RSP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::AH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EIP, X86::RIP,
- X86::RSP, X86::ESP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::SP, X86::ESP,
- X86::SPL, X86::ESP,
+ X86::EAX, X86::AX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2451,37 +2551,38 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::IP, X86::RIP,
- X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::EBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R12, X86::R12D,
- X86::R12B, X86::R12D,
- X86::BX, X86::BH,
- X86::R12W, X86::R12D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RAX, X86::AL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::BH,
+ X86::R15, X86::R15B,
X86::NoRegister, X86::NoRegister,
+ X86::R15D, X86::R15B,
+ X86::R15W, X86::R15B,
X86::NoRegister, X86::NoRegister,
+ X86::SI, X86::RSI,
+ X86::SIL, X86::RSI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EBX, X86::BH,
+ X86::ESI, X86::SI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::AL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ESI, X86::RSI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::BH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2493,30 +2594,32 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R12, X86::R12W,
- X86::R12B, X86::R12W,
- X86::BX, X86::BL,
X86::NoRegister, X86::NoRegister,
- X86::R12D, X86::R12W,
X86::NoRegister, X86::NoRegister,
- X86::RAX, X86::AX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::BL,
+ X86::R15, X86::R15D,
+ X86::R15B, X86::R15D,
X86::NoRegister, X86::NoRegister,
+ X86::R15W, X86::R15D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::SP, X86::RSP,
+ X86::SPL, X86::RSP,
+ X86::ESI, X86::SIL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EBX, X86::BL,
X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::AX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ESP, X86::RSP,
X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::BL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2532,27 +2635,27 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::BPL, X86::BP,
- X86::RBX, X86::BH,
X86::NoRegister, X86::NoRegister,
+ X86::R15, X86::R15W,
+ X86::R15B, X86::R15W,
+ X86::R15D, X86::R15W,
+ X86::RSI, X86::SI,
X86::NoRegister, X86::NoRegister,
- X86::R13B, X86::R13,
- X86::R13D, X86::R13,
- X86::R13W, X86::R13,
- X86::SI, X86::RSI,
- X86::SIL, X86::RSI,
X86::NoRegister, X86::NoRegister,
+ X86::SIL, X86::SI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EBP, X86::BP,
+ X86::ESP, X86::SP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::BH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ESI, X86::SI,
X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::BP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2569,27 +2672,27 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::BP, X86::BPL,
X86::NoRegister, X86::NoRegister,
- X86::RBX, X86::BL,
X86::NoRegister, X86::NoRegister,
- X86::R13, X86::R13B,
X86::NoRegister, X86::NoRegister,
- X86::R13D, X86::R13B,
- X86::R13W, X86::R13B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::SP, X86::RSP,
- X86::SPL, X86::RSP,
+ X86::RSI, X86::SIL,
X86::NoRegister, X86::NoRegister,
+ X86::R8B, X86::R8,
+ X86::R8D, X86::R8,
+ X86::R8W, X86::R8,
X86::NoRegister, X86::NoRegister,
- X86::EBP, X86::BPL,
X86::NoRegister, X86::NoRegister,
+ X86::ESP, X86::SPL,
+ X86::SI, X86::SIL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::BL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ESI, X86::SIL,
X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::BPL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2605,30 +2708,29 @@ X86::NoRegister, X86::NoRegister };
X86::BH, X86::BX,
X86::BL, X86::BX,
X86::NoRegister, X86::NoRegister,
- X86::RBP, X86::BP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R13, X86::R13D,
- X86::R13B, X86::R13D,
- X86::RSI, X86::SI,
- X86::R13W, X86::R13D,
X86::NoRegister, X86::NoRegister,
- X86::SIL, X86::SI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R8, X86::R8B,
X86::NoRegister, X86::NoRegister,
+ X86::R8D, X86::R8B,
+ X86::R8W, X86::R8B,
+ X86::SPL, X86::SP,
X86::NoRegister, X86::NoRegister,
- X86::EBX, X86::BX,
+ X86::RSP, X86::SP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RBP, X86::BP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ESP, X86::SP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::BX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2642,28 +2744,26 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RBP, X86::BPL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R13, X86::R13W,
- X86::R13B, X86::R13W,
- X86::CX, X86::CH,
X86::NoRegister, X86::NoRegister,
- X86::R13D, X86::R13W,
X86::NoRegister, X86::NoRegister,
- X86::SI, X86::SIL,
X86::NoRegister, X86::NoRegister,
- X86::RSI, X86::SIL,
X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::CH,
+ X86::R8, X86::R8D,
+ X86::R8B, X86::R8D,
+ X86::RSP, X86::SPL,
+ X86::R8W, X86::R8D,
X86::NoRegister, X86::NoRegister,
+ X86::SP, X86::SPL,
X86::NoRegister, X86::NoRegister,
- X86::ECX, X86::CH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RBP, X86::BPL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::ESP, X86::SPL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2676,29 +2776,33 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RBX, X86::BX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::CX, X86::CL,
- X86::RSP, X86::SP,
X86::NoRegister, X86::NoRegister,
- X86::R14B, X86::R14,
- X86::R14D, X86::R14,
- X86::R14W, X86::R14,
X86::NoRegister, X86::NoRegister,
- X86::SPL, X86::SP,
X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::CL,
+ X86::R8, X86::R8W,
+ X86::R8B, X86::R8W,
+ X86::R10B, X86::R10,
+ X86::R10D, X86::R10,
+ X86::R10W, X86::R10,
X86::NoRegister, X86::NoRegister,
- X86::ECX, X86::CL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::CH, X86::ECX,
+ X86::CL, X86::ECX,
X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::ECX,
X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::BX,
+ X86::R8D, X86::R8W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2709,6 +2813,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2718,27 +2823,30 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RCX, X86::CH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RSP, X86::SPL,
- X86::R14, X86::R14B,
+ X86::R10, X86::R10B,
X86::NoRegister, X86::NoRegister,
- X86::R14D, X86::R14B,
- X86::R14W, X86::R14B,
- X86::SP, X86::SPL,
+ X86::R10D, X86::R10B,
+ X86::R10W, X86::R10B,
+ X86::R9B, X86::R9,
+ X86::R9D, X86::R9,
+ X86::R9W, X86::R9,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DI, X86::EDI,
+ X86::DIL, X86::EDI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::CH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2747,48 +2855,66 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EIP, X86::IP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::CH, X86::CX,
+ X86::CL, X86::CX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R10, X86::R10D,
+ X86::R10B, X86::R10D,
X86::NoRegister, X86::NoRegister,
- X86::CH, X86::CX,
- X86::CL, X86::CX,
- X86::RCX, X86::CL,
+ X86::R10W, X86::R10D,
X86::NoRegister, X86::NoRegister,
+ X86::R9, X86::R9B,
+ X86::R9W, X86::R9B,
+ X86::R9D, X86::R9B,
X86::NoRegister, X86::NoRegister,
- X86::R14, X86::R14D,
- X86::R14B, X86::R14D,
X86::NoRegister, X86::NoRegister,
- X86::R14W, X86::R14D,
X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::EDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DL, X86::EDX,
X86::NoRegister, X86::NoRegister,
- X86::ECX, X86::CX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::CL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::AH, X86::RAX,
+ X86::AL, X86::RAX,
+ X86::AX, X86::RAX,
+ X86::DX, X86::EDX,
+ X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CX,
X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::ECX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R10, X86::R10W,
+ X86::R10B, X86::R10W,
+ X86::R10D, X86::R10W,
+ X86::R9, X86::R9D,
+ X86::R9B, X86::R9D,
X86::NoRegister, X86::NoRegister,
+ X86::R9W, X86::R9D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DX, X86::DH,
X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::RAX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2797,69 +2923,83 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R14, X86::R14W,
- X86::R14B, X86::R14W,
- X86::R14D, X86::R14W,
X86::NoRegister, X86::NoRegister,
- X86::DX, X86::DH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::DH,
X86::NoRegister, X86::NoRegister,
+ X86::BP, X86::RBP,
+ X86::BPL, X86::RBP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EDX, X86::DH,
X86::NoRegister, X86::NoRegister,
- X86::RIP, X86::IP,
+ X86::RDI, X86::EDI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DIL, X86::DI,
X86::NoRegister, X86::NoRegister,
+ X86::R9, X86::R9W,
+ X86::R9B, X86::R9W,
+ X86::R11B, X86::R11,
+ X86::R11D, X86::R11,
+ X86::R11W, X86::R11,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R9D, X86::R9W,
X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::RBP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::CX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RCX, X86::CX,
+ X86::EDI, X86::DI,
+ X86::BH, X86::RBX,
+ X86::BL, X86::RBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::RBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DIL, X86::DI,
+ X86::RDX, X86::EDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DI, X86::DIL,
X86::NoRegister, X86::NoRegister,
- X86::R15B, X86::R15,
- X86::R15D, X86::R15,
- X86::R15W, X86::R15,
X86::NoRegister, X86::NoRegister,
- X86::EDI, X86::DI,
X86::NoRegister, X86::NoRegister,
+ X86::R11, X86::R11B,
X86::NoRegister, X86::NoRegister,
+ X86::R11D, X86::R11B,
+ X86::R11W, X86::R11B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::RBX,
X86::NoRegister, X86::NoRegister,
+ X86::IP, X86::EIP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EDI, X86::DIL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2868,24 +3008,22 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDX, X86::DH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DI, X86::DIL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R15, X86::R15B,
X86::NoRegister, X86::NoRegister,
- X86::R15D, X86::R15B,
- X86::R15W, X86::R15B,
X86::NoRegister, X86::NoRegister,
- X86::EDI, X86::DIL,
+ X86::R11, X86::R11D,
+ X86::R11B, X86::R11D,
X86::NoRegister, X86::NoRegister,
+ X86::R11W, X86::R11D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DX, X86::DL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2894,31 +3032,31 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RDI, X86::DI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::DL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDI, X86::DI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RIP, X86::EIP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DX, X86::DL,
- X86::R15B, X86::R15D,
- X86::R15, X86::R15D,
- X86::R15W, X86::R15D,
+ X86::R11, X86::R11W,
+ X86::R11B, X86::R11W,
+ X86::R11D, X86::R11W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EDX, X86::DL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2931,6 +3069,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RDI, X86::DIL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2941,7 +3080,6 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDI, X86::DIL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2949,9 +3087,6 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R15, X86::R15W,
- X86::R15B, X86::R15W,
- X86::R15D, X86::R15W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2959,6 +3094,9 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R12B, X86::R12,
+ X86::R12D, X86::R12,
+ X86::R12W, X86::R12,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2969,6 +3107,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2979,23 +3118,22 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDX, X86::DL,
X86::NoRegister, X86::NoRegister,
- X86::DH, X86::DX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DL, X86::DX,
+ X86::RSI, X86::ESI,
X86::NoRegister, X86::NoRegister,
+ X86::SI, X86::ESI,
+ X86::SIL, X86::ESI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R8B, X86::R8,
- X86::EDX, X86::DX,
- X86::R8W, X86::R8,
- X86::R8D, X86::R8,
+ X86::R12, X86::R12B,
X86::NoRegister, X86::NoRegister,
+ X86::R12D, X86::R12B,
+ X86::R12W, X86::R12B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3006,9 +3144,6 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::AH, X86::EAX,
- X86::AL, X86::EAX,
- X86::AX, X86::EAX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3024,15 +3159,18 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::RSP, X86::ESP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::SP, X86::ESP,
+ X86::SPL, X86::ESP,
X86::NoRegister, X86::NoRegister,
- X86::R8, X86::R8B,
X86::NoRegister, X86::NoRegister,
- X86::R8D, X86::R8B,
- X86::R8W, X86::R8B,
X86::NoRegister, X86::NoRegister,
+ X86::R12, X86::R12D,
+ X86::R12B, X86::R12D,
X86::NoRegister, X86::NoRegister,
+ X86::R12W, X86::R12D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3048,12 +3186,9 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::BP, X86::EBP,
- X86::BPL, X86::EBP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDX, X86::DX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3064,14 +3199,14 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R8, X86::R8D,
- X86::R8B, X86::R8D,
X86::NoRegister, X86::NoRegister,
- X86::R8W, X86::R8D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R12, X86::R12W,
+ X86::R12B, X86::R12W,
+ X86::R12D, X86::R12W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3083,11 +3218,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::BH, X86::EBX,
- X86::BL, X86::EBX,
- X86::RAX, X86::EAX,
X86::NoRegister, X86::NoRegister,
- X86::BX, X86::EBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3101,15 +3232,9 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R8, X86::R8W,
- X86::R8B, X86::R8W,
- X86::R10B, X86::R10,
- X86::R10D, X86::R10,
- X86::R10W, X86::R10,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R8D, X86::R8W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3121,14 +3246,13 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R13B, X86::R13,
+ X86::R13D, X86::R13,
+ X86::R13W, X86::R13,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RBP, X86::EBP,
X86::NoRegister, X86::NoRegister,
- X86::CH, X86::ECX,
- X86::CL, X86::ECX,
X86::NoRegister, X86::NoRegister,
- X86::CX, X86::ECX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3139,13 +3263,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R10, X86::R10B,
X86::NoRegister, X86::NoRegister,
- X86::R10D, X86::R10B,
- X86::R10W, X86::R10B,
- X86::R9B, X86::R9,
- X86::R9D, X86::R9,
- X86::R9W, X86::R9,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3161,14 +3279,14 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RBX, X86::EBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R13, X86::R13B,
X86::NoRegister, X86::NoRegister,
+ X86::R13D, X86::R13B,
+ X86::R13W, X86::R13B,
X86::NoRegister, X86::NoRegister,
- X86::DI, X86::EDI,
- X86::DIL, X86::EDI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3176,14 +3294,8 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R10, X86::R10D,
- X86::R10B, X86::R10D,
X86::NoRegister, X86::NoRegister,
- X86::R10W, X86::R10D,
X86::NoRegister, X86::NoRegister,
- X86::R9, X86::R9B,
- X86::R9W, X86::R9B,
- X86::R9D, X86::R9B,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3199,33 +3311,23 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RCX, X86::ECX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DH, X86::EDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::DL, X86::EDX,
X86::NoRegister, X86::NoRegister,
- X86::DX, X86::EDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::R13, X86::R13D,
+ X86::R13B, X86::R13D,
X86::NoRegister, X86::NoRegister,
+ X86::R13W, X86::R13D,
X86::NoRegister, X86::NoRegister,
- X86::R10, X86::R10W,
- X86::R10B, X86::R10W,
- X86::AH, X86::RAX,
- X86::AL, X86::RAX,
- X86::AX, X86::RAX,
- X86::R9, X86::R9D,
- X86::R9B, X86::R9D,
X86::NoRegister, X86::NoRegister,
- X86::R10D, X86::R10W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R9W, X86::R9D,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3233,12 +3335,13 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EAX, X86::RAX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDI, X86::EDI,
+ X86::CH, X86::RCX,
+ X86::CL, X86::RCX,
X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::RCX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3253,15 +3356,10 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R9, X86::R9W,
- X86::R9B, X86::R9W,
- X86::R11B, X86::R11,
- X86::R11D, X86::R11,
- X86::BP, X86::RBP,
- X86::BPL, X86::RBP,
- X86::R11W, X86::R11,
+ X86::R13, X86::R13W,
+ X86::R13B, X86::R13W,
+ X86::R13D, X86::R13W,
X86::NoRegister, X86::NoRegister,
- X86::R9D, X86::R9W,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3269,13 +3367,12 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::RCX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::EBP, X86::RBP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::RDX, X86::EDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3283,6 +3380,10 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::DX,
+ X86::DIL, X86::RDI,
+ X86::DI, X86::RDI,
+ X86::DL, X86::DX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3291,32 +3392,34 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::R11, X86::R11B,
- X86::BH, X86::RBX,
- X86::BL, X86::RBX,
- X86::R11W, X86::R11B,
- X86::R11D, X86::R11B,
- X86::BX, X86::RBX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::IP, X86::EIP,
+ X86::R14B, X86::R14,
+ X86::R14D, X86::R14,
+ X86::R14W, X86::R14,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::AH, X86::EAX,
+ X86::AL, X86::EAX,
+ X86::AX, X86::EAX,
X86::NoRegister, X86::NoRegister,
- X86::EBX, X86::RBX,
+ X86::EDX, X86::DX,
X86::NoRegister, X86::NoRegister,
+ X86::EDI, X86::RDI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::RDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::DL, X86::RDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3347,11 +3450,27 @@ X86::NoRegister, X86::NoRegister };
const unsigned DI_AliasSet[] = { X86::DIL, X86::EDI, X86::RDI, 0 };
const unsigned DIL_AliasSet[] = { X86::DI, X86::EDI, X86::RDI, 0 };
const unsigned DL_AliasSet[] = { X86::DX, X86::EDX, X86::RDX, 0 };
+ const unsigned DR0_AliasSet[] = { 0 };
+ const unsigned DR1_AliasSet[] = { 0 };
+ const unsigned DR2_AliasSet[] = { 0 };
+ const unsigned DR3_AliasSet[] = { 0 };
+ const unsigned DR4_AliasSet[] = { 0 };
+ const unsigned DR5_AliasSet[] = { 0 };
+ const unsigned DR6_AliasSet[] = { 0 };
+ const unsigned DR7_AliasSet[] = { 0 };
const unsigned DS_AliasSet[] = { 0 };
const unsigned DX_AliasSet[] = { X86::DL, X86::DH, X86::EDX, X86::RDX, 0 };
const unsigned EAX_AliasSet[] = { X86::AL, X86::AH, X86::AX, X86::RAX, 0 };
const unsigned EBP_AliasSet[] = { X86::BPL, X86::BP, X86::RBP, 0 };
const unsigned EBX_AliasSet[] = { X86::BL, X86::BH, X86::BX, X86::RBX, 0 };
+ const unsigned ECR0_AliasSet[] = { 0 };
+ const unsigned ECR1_AliasSet[] = { 0 };
+ const unsigned ECR2_AliasSet[] = { 0 };
+ const unsigned ECR3_AliasSet[] = { 0 };
+ const unsigned ECR4_AliasSet[] = { 0 };
+ const unsigned ECR5_AliasSet[] = { 0 };
+ const unsigned ECR6_AliasSet[] = { 0 };
+ const unsigned ECR7_AliasSet[] = { 0 };
const unsigned ECX_AliasSet[] = { X86::CL, X86::CH, X86::CX, X86::RCX, 0 };
const unsigned EDI_AliasSet[] = { X86::DIL, X86::DI, X86::RDI, 0 };
const unsigned EDX_AliasSet[] = { X86::DL, X86::DH, X86::DX, X86::RDX, 0 };
@@ -3413,6 +3532,15 @@ X86::NoRegister, X86::NoRegister };
const unsigned RAX_AliasSet[] = { X86::AL, X86::AH, X86::AX, X86::EAX, 0 };
const unsigned RBP_AliasSet[] = { X86::BPL, X86::BP, X86::EBP, 0 };
const unsigned RBX_AliasSet[] = { X86::BL, X86::BH, X86::BX, X86::EBX, 0 };
+ const unsigned RCR0_AliasSet[] = { 0 };
+ const unsigned RCR1_AliasSet[] = { 0 };
+ const unsigned RCR2_AliasSet[] = { 0 };
+ const unsigned RCR3_AliasSet[] = { 0 };
+ const unsigned RCR4_AliasSet[] = { 0 };
+ const unsigned RCR5_AliasSet[] = { 0 };
+ const unsigned RCR6_AliasSet[] = { 0 };
+ const unsigned RCR7_AliasSet[] = { 0 };
+ const unsigned RCR8_AliasSet[] = { 0 };
const unsigned RCX_AliasSet[] = { X86::CL, X86::CH, X86::CX, X86::ECX, 0 };
const unsigned RDI_AliasSet[] = { X86::DIL, X86::DI, X86::EDI, 0 };
const unsigned RDX_AliasSet[] = { X86::DL, X86::DH, X86::DX, X86::EDX, 0 };
@@ -3484,11 +3612,27 @@ X86::NoRegister, X86::NoRegister };
const unsigned DI_SubRegsSet[] = { X86::DIL, 0 };
const unsigned DIL_SubRegsSet[] = { 0 };
const unsigned DL_SubRegsSet[] = { 0 };
+ const unsigned DR0_SubRegsSet[] = { 0 };
+ const unsigned DR1_SubRegsSet[] = { 0 };
+ const unsigned DR2_SubRegsSet[] = { 0 };
+ const unsigned DR3_SubRegsSet[] = { 0 };
+ const unsigned DR4_SubRegsSet[] = { 0 };
+ const unsigned DR5_SubRegsSet[] = { 0 };
+ const unsigned DR6_SubRegsSet[] = { 0 };
+ const unsigned DR7_SubRegsSet[] = { 0 };
const unsigned DS_SubRegsSet[] = { 0 };
const unsigned DX_SubRegsSet[] = { X86::DL, X86::DH, 0 };
const unsigned EAX_SubRegsSet[] = { X86::AX, X86::AL, X86::AH, 0 };
const unsigned EBP_SubRegsSet[] = { X86::BP, X86::BPL, 0 };
const unsigned EBX_SubRegsSet[] = { X86::BX, X86::BL, X86::BH, 0 };
+ const unsigned ECR0_SubRegsSet[] = { 0 };
+ const unsigned ECR1_SubRegsSet[] = { 0 };
+ const unsigned ECR2_SubRegsSet[] = { 0 };
+ const unsigned ECR3_SubRegsSet[] = { 0 };
+ const unsigned ECR4_SubRegsSet[] = { 0 };
+ const unsigned ECR5_SubRegsSet[] = { 0 };
+ const unsigned ECR6_SubRegsSet[] = { 0 };
+ const unsigned ECR7_SubRegsSet[] = { 0 };
const unsigned ECX_SubRegsSet[] = { X86::CX, X86::CL, X86::CH, 0 };
const unsigned EDI_SubRegsSet[] = { X86::DI, X86::DIL, 0 };
const unsigned EDX_SubRegsSet[] = { X86::DX, X86::DL, X86::DH, 0 };
@@ -3550,6 +3694,15 @@ X86::NoRegister, X86::NoRegister };
const unsigned RAX_SubRegsSet[] = { X86::EAX, X86::AX, X86::AL, X86::AH, 0 };
const unsigned RBP_SubRegsSet[] = { X86::EBP, X86::BP, X86::BPL, 0 };
const unsigned RBX_SubRegsSet[] = { X86::EBX, X86::BX, X86::BL, X86::BH, 0 };
+ const unsigned RCR0_SubRegsSet[] = { 0 };
+ const unsigned RCR1_SubRegsSet[] = { 0 };
+ const unsigned RCR2_SubRegsSet[] = { 0 };
+ const unsigned RCR3_SubRegsSet[] = { 0 };
+ const unsigned RCR4_SubRegsSet[] = { 0 };
+ const unsigned RCR5_SubRegsSet[] = { 0 };
+ const unsigned RCR6_SubRegsSet[] = { 0 };
+ const unsigned RCR7_SubRegsSet[] = { 0 };
+ const unsigned RCR8_SubRegsSet[] = { 0 };
const unsigned RCX_SubRegsSet[] = { X86::ECX, X86::CX, X86::CL, X86::CH, 0 };
const unsigned RDI_SubRegsSet[] = { X86::EDI, X86::DI, X86::DIL, 0 };
const unsigned RDX_SubRegsSet[] = { X86::EDX, X86::DX, X86::DL, X86::DH, 0 };
@@ -3621,11 +3774,27 @@ X86::NoRegister, X86::NoRegister };
const unsigned DI_SuperRegsSet[] = { X86::RDI, X86::EDI, 0 };
const unsigned DIL_SuperRegsSet[] = { X86::RDI, X86::EDI, X86::DI, 0 };
const unsigned DL_SuperRegsSet[] = { X86::RDX, X86::EDX, X86::DX, 0 };
+ const unsigned DR0_SuperRegsSet[] = { 0 };
+ const unsigned DR1_SuperRegsSet[] = { 0 };
+ const unsigned DR2_SuperRegsSet[] = { 0 };
+ const unsigned DR3_SuperRegsSet[] = { 0 };
+ const unsigned DR4_SuperRegsSet[] = { 0 };
+ const unsigned DR5_SuperRegsSet[] = { 0 };
+ const unsigned DR6_SuperRegsSet[] = { 0 };
+ const unsigned DR7_SuperRegsSet[] = { 0 };
const unsigned DS_SuperRegsSet[] = { 0 };
const unsigned DX_SuperRegsSet[] = { X86::RDX, X86::EDX, 0 };
const unsigned EAX_SuperRegsSet[] = { X86::RAX, 0 };
const unsigned EBP_SuperRegsSet[] = { X86::RBP, 0 };
const unsigned EBX_SuperRegsSet[] = { X86::RBX, 0 };
+ const unsigned ECR0_SuperRegsSet[] = { 0 };
+ const unsigned ECR1_SuperRegsSet[] = { 0 };
+ const unsigned ECR2_SuperRegsSet[] = { 0 };
+ const unsigned ECR3_SuperRegsSet[] = { 0 };
+ const unsigned ECR4_SuperRegsSet[] = { 0 };
+ const unsigned ECR5_SuperRegsSet[] = { 0 };
+ const unsigned ECR6_SuperRegsSet[] = { 0 };
+ const unsigned ECR7_SuperRegsSet[] = { 0 };
const unsigned ECX_SuperRegsSet[] = { X86::RCX, 0 };
const unsigned EDI_SuperRegsSet[] = { X86::RDI, 0 };
const unsigned EDX_SuperRegsSet[] = { X86::RDX, 0 };
@@ -3687,6 +3856,15 @@ X86::NoRegister, X86::NoRegister };
const unsigned RAX_SuperRegsSet[] = { 0 };
const unsigned RBP_SuperRegsSet[] = { 0 };
const unsigned RBX_SuperRegsSet[] = { 0 };
+ const unsigned RCR0_SuperRegsSet[] = { 0 };
+ const unsigned RCR1_SuperRegsSet[] = { 0 };
+ const unsigned RCR2_SuperRegsSet[] = { 0 };
+ const unsigned RCR3_SuperRegsSet[] = { 0 };
+ const unsigned RCR4_SuperRegsSet[] = { 0 };
+ const unsigned RCR5_SuperRegsSet[] = { 0 };
+ const unsigned RCR6_SuperRegsSet[] = { 0 };
+ const unsigned RCR7_SuperRegsSet[] = { 0 };
+ const unsigned RCR8_SuperRegsSet[] = { 0 };
const unsigned RCX_SuperRegsSet[] = { 0 };
const unsigned RDI_SuperRegsSet[] = { 0 };
const unsigned RDX_SuperRegsSet[] = { 0 };
@@ -3757,11 +3935,27 @@ X86::NoRegister, X86::NoRegister };
{ "DI", DI_AliasSet, DI_SubRegsSet, DI_SuperRegsSet },
{ "DIL", DIL_AliasSet, DIL_SubRegsSet, DIL_SuperRegsSet },
{ "DL", DL_AliasSet, DL_SubRegsSet, DL_SuperRegsSet },
+ { "DR0", DR0_AliasSet, DR0_SubRegsSet, DR0_SuperRegsSet },
+ { "DR1", DR1_AliasSet, DR1_SubRegsSet, DR1_SuperRegsSet },
+ { "DR2", DR2_AliasSet, DR2_SubRegsSet, DR2_SuperRegsSet },
+ { "DR3", DR3_AliasSet, DR3_SubRegsSet, DR3_SuperRegsSet },
+ { "DR4", DR4_AliasSet, DR4_SubRegsSet, DR4_SuperRegsSet },
+ { "DR5", DR5_AliasSet, DR5_SubRegsSet, DR5_SuperRegsSet },
+ { "DR6", DR6_AliasSet, DR6_SubRegsSet, DR6_SuperRegsSet },
+ { "DR7", DR7_AliasSet, DR7_SubRegsSet, DR7_SuperRegsSet },
{ "DS", DS_AliasSet, DS_SubRegsSet, DS_SuperRegsSet },
{ "DX", DX_AliasSet, DX_SubRegsSet, DX_SuperRegsSet },
{ "EAX", EAX_AliasSet, EAX_SubRegsSet, EAX_SuperRegsSet },
{ "EBP", EBP_AliasSet, EBP_SubRegsSet, EBP_SuperRegsSet },
{ "EBX", EBX_AliasSet, EBX_SubRegsSet, EBX_SuperRegsSet },
+ { "ECR0", ECR0_AliasSet, ECR0_SubRegsSet, ECR0_SuperRegsSet },
+ { "ECR1", ECR1_AliasSet, ECR1_SubRegsSet, ECR1_SuperRegsSet },
+ { "ECR2", ECR2_AliasSet, ECR2_SubRegsSet, ECR2_SuperRegsSet },
+ { "ECR3", ECR3_AliasSet, ECR3_SubRegsSet, ECR3_SuperRegsSet },
+ { "ECR4", ECR4_AliasSet, ECR4_SubRegsSet, ECR4_SuperRegsSet },
+ { "ECR5", ECR5_AliasSet, ECR5_SubRegsSet, ECR5_SuperRegsSet },
+ { "ECR6", ECR6_AliasSet, ECR6_SubRegsSet, ECR6_SuperRegsSet },
+ { "ECR7", ECR7_AliasSet, ECR7_SubRegsSet, ECR7_SuperRegsSet },
{ "ECX", ECX_AliasSet, ECX_SubRegsSet, ECX_SuperRegsSet },
{ "EDI", EDI_AliasSet, EDI_SubRegsSet, EDI_SuperRegsSet },
{ "EDX", EDX_AliasSet, EDX_SubRegsSet, EDX_SuperRegsSet },
@@ -3823,6 +4017,15 @@ X86::NoRegister, X86::NoRegister };
{ "RAX", RAX_AliasSet, RAX_SubRegsSet, RAX_SuperRegsSet },
{ "RBP", RBP_AliasSet, RBP_SubRegsSet, RBP_SuperRegsSet },
{ "RBX", RBX_AliasSet, RBX_SubRegsSet, RBX_SuperRegsSet },
+ { "RCR0", RCR0_AliasSet, RCR0_SubRegsSet, RCR0_SuperRegsSet },
+ { "RCR1", RCR1_AliasSet, RCR1_SubRegsSet, RCR1_SuperRegsSet },
+ { "RCR2", RCR2_AliasSet, RCR2_SubRegsSet, RCR2_SuperRegsSet },
+ { "RCR3", RCR3_AliasSet, RCR3_SubRegsSet, RCR3_SuperRegsSet },
+ { "RCR4", RCR4_AliasSet, RCR4_SubRegsSet, RCR4_SuperRegsSet },
+ { "RCR5", RCR5_AliasSet, RCR5_SubRegsSet, RCR5_SuperRegsSet },
+ { "RCR6", RCR6_AliasSet, RCR6_SubRegsSet, RCR6_SuperRegsSet },
+ { "RCR7", RCR7_AliasSet, RCR7_SubRegsSet, RCR7_SuperRegsSet },
+ { "RCR8", RCR8_AliasSet, RCR8_SubRegsSet, RCR8_SuperRegsSet },
{ "RCX", RCX_AliasSet, RCX_SubRegsSet, RCX_SuperRegsSet },
{ "RDI", RDI_AliasSet, RDI_SubRegsSet, RDI_SuperRegsSet },
{ "RDX", RDX_AliasSet, RDX_SubRegsSet, RDX_SuperRegsSet },
@@ -4590,7 +4793,7 @@ unsigned X86GenRegisterInfo::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) c
}
X86GenRegisterInfo::X86GenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)
- : TargetRegisterInfo(RegisterDescriptors, 134, RegisterClasses, RegisterClasses+28,
+ : TargetRegisterInfo(RegisterDescriptors, 159, RegisterClasses, RegisterClasses+31,
CallFrameSetupOpcode, CallFrameDestroyOpcode,
SubregHashTable, SubregHashTableSize,
SuperregHashTable, SuperregHashTableSize,
@@ -4639,6 +4842,22 @@ int X86GenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) co
return 5;
case X86::DL:
return 1;
+ case X86::DR0:
+ return -1;
+ case X86::DR1:
+ return -1;
+ case X86::DR2:
+ return -1;
+ case X86::DR3:
+ return -1;
+ case X86::DR4:
+ return -1;
+ case X86::DR5:
+ return -1;
+ case X86::DR6:
+ return -1;
+ case X86::DR7:
+ return -1;
case X86::DS:
return -1;
case X86::DX:
@@ -4649,6 +4868,22 @@ int X86GenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) co
return 6;
case X86::EBX:
return 3;
+ case X86::ECR0:
+ return -1;
+ case X86::ECR1:
+ return -1;
+ case X86::ECR2:
+ return -1;
+ case X86::ECR3:
+ return -1;
+ case X86::ECR4:
+ return -1;
+ case X86::ECR5:
+ return -1;
+ case X86::ECR6:
+ return -1;
+ case X86::ECR7:
+ return -1;
case X86::ECX:
return 2;
case X86::EDI:
@@ -4771,6 +5006,24 @@ int X86GenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) co
return 6;
case X86::RBX:
return 3;
+ case X86::RCR0:
+ return -1;
+ case X86::RCR1:
+ return -1;
+ case X86::RCR2:
+ return -1;
+ case X86::RCR3:
+ return -1;
+ case X86::RCR4:
+ return -1;
+ case X86::RCR5:
+ return -1;
+ case X86::RCR6:
+ return -1;
+ case X86::RCR7:
+ return -1;
+ case X86::RCR8:
+ return -1;
case X86::RCX:
return 2;
case X86::RDI:
@@ -4911,6 +5164,22 @@ int X86GenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) co
return 7;
case X86::DL:
return 2;
+ case X86::DR0:
+ return -1;
+ case X86::DR1:
+ return -1;
+ case X86::DR2:
+ return -1;
+ case X86::DR3:
+ return -1;
+ case X86::DR4:
+ return -1;
+ case X86::DR5:
+ return -1;
+ case X86::DR6:
+ return -1;
+ case X86::DR7:
+ return -1;
case X86::DS:
return -1;
case X86::DX:
@@ -4921,6 +5190,22 @@ int X86GenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) co
return 4;
case X86::EBX:
return 3;
+ case X86::ECR0:
+ return -1;
+ case X86::ECR1:
+ return -1;
+ case X86::ECR2:
+ return -1;
+ case X86::ECR3:
+ return -1;
+ case X86::ECR4:
+ return -1;
+ case X86::ECR5:
+ return -1;
+ case X86::ECR6:
+ return -1;
+ case X86::ECR7:
+ return -1;
case X86::ECX:
return 1;
case X86::EDI:
@@ -5078,6 +5363,24 @@ int X86GenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) co
case X86::RBX:
assert(0 && "Invalid register for this mode");
return -1;
+ case X86::RCR0:
+ return -1;
+ case X86::RCR1:
+ return -1;
+ case X86::RCR2:
+ return -1;
+ case X86::RCR3:
+ return -1;
+ case X86::RCR4:
+ return -1;
+ case X86::RCR5:
+ return -1;
+ case X86::RCR6:
+ return -1;
+ case X86::RCR7:
+ return -1;
+ case X86::RCR8:
+ return -1;
case X86::RCX:
assert(0 && "Invalid register for this mode");
return -1;
@@ -5240,6 +5543,22 @@ int X86GenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) co
return 7;
case X86::DL:
return 2;
+ case X86::DR0:
+ return -1;
+ case X86::DR1:
+ return -1;
+ case X86::DR2:
+ return -1;
+ case X86::DR3:
+ return -1;
+ case X86::DR4:
+ return -1;
+ case X86::DR5:
+ return -1;
+ case X86::DR6:
+ return -1;
+ case X86::DR7:
+ return -1;
case X86::DS:
return -1;
case X86::DX:
@@ -5250,6 +5569,22 @@ int X86GenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) co
return 5;
case X86::EBX:
return 3;
+ case X86::ECR0:
+ return -1;
+ case X86::ECR1:
+ return -1;
+ case X86::ECR2:
+ return -1;
+ case X86::ECR3:
+ return -1;
+ case X86::ECR4:
+ return -1;
+ case X86::ECR5:
+ return -1;
+ case X86::ECR6:
+ return -1;
+ case X86::ECR7:
+ return -1;
case X86::ECX:
return 1;
case X86::EDI:
@@ -5407,6 +5742,24 @@ int X86GenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) co
case X86::RBX:
assert(0 && "Invalid register for this mode");
return -1;
+ case X86::RCR0:
+ return -1;
+ case X86::RCR1:
+ return -1;
+ case X86::RCR2:
+ return -1;
+ case X86::RCR3:
+ return -1;
+ case X86::RCR4:
+ return -1;
+ case X86::RCR5:
+ return -1;
+ case X86::RCR6:
+ return -1;
+ case X86::RCR7:
+ return -1;
+ case X86::RCR8:
+ return -1;
case X86::RCX:
assert(0 && "Invalid register for this mode");
return -1;
diff --git a/libclamav/c++/X86GenRegisterNames.inc b/libclamav/c++/X86GenRegisterNames.inc
index 49dbe75..6edb8ec 100644
--- a/libclamav/c++/X86GenRegisterNames.inc
+++ b/libclamav/c++/X86GenRegisterNames.inc
@@ -27,124 +27,149 @@ namespace X86 {
DI, // 14
DIL, // 15
DL, // 16
- DS, // 17
- DX, // 18
- EAX, // 19
- EBP, // 20
- EBX, // 21
- ECX, // 22
- EDI, // 23
- EDX, // 24
- EFLAGS, // 25
- EIP, // 26
- ES, // 27
- ESI, // 28
- ESP, // 29
- FP0, // 30
- FP1, // 31
- FP2, // 32
- FP3, // 33
- FP4, // 34
- FP5, // 35
- FP6, // 36
- FS, // 37
- GS, // 38
- IP, // 39
- MM0, // 40
- MM1, // 41
- MM2, // 42
- MM3, // 43
- MM4, // 44
- MM5, // 45
- MM6, // 46
- MM7, // 47
- R10, // 48
- R10B, // 49
- R10D, // 50
- R10W, // 51
- R11, // 52
- R11B, // 53
- R11D, // 54
- R11W, // 55
- R12, // 56
- R12B, // 57
- R12D, // 58
- R12W, // 59
- R13, // 60
- R13B, // 61
- R13D, // 62
- R13W, // 63
- R14, // 64
- R14B, // 65
- R14D, // 66
- R14W, // 67
- R15, // 68
- R15B, // 69
- R15D, // 70
- R15W, // 71
- R8, // 72
- R8B, // 73
- R8D, // 74
- R8W, // 75
- R9, // 76
- R9B, // 77
- R9D, // 78
- R9W, // 79
- RAX, // 80
- RBP, // 81
- RBX, // 82
- RCX, // 83
- RDI, // 84
- RDX, // 85
- RIP, // 86
- RSI, // 87
- RSP, // 88
- SI, // 89
- SIL, // 90
- SP, // 91
- SPL, // 92
- SS, // 93
- ST0, // 94
- ST1, // 95
- ST2, // 96
- ST3, // 97
- ST4, // 98
- ST5, // 99
- ST6, // 100
- ST7, // 101
- XMM0, // 102
- XMM1, // 103
- XMM10, // 104
- XMM11, // 105
- XMM12, // 106
- XMM13, // 107
- XMM14, // 108
- XMM15, // 109
- XMM2, // 110
- XMM3, // 111
- XMM4, // 112
- XMM5, // 113
- XMM6, // 114
- XMM7, // 115
- XMM8, // 116
- XMM9, // 117
- YMM0, // 118
- YMM1, // 119
- YMM10, // 120
- YMM11, // 121
- YMM12, // 122
- YMM13, // 123
- YMM14, // 124
- YMM15, // 125
- YMM2, // 126
- YMM3, // 127
- YMM4, // 128
- YMM5, // 129
- YMM6, // 130
- YMM7, // 131
- YMM8, // 132
- YMM9, // 133
- NUM_TARGET_REGS // 134
+ DR0, // 17
+ DR1, // 18
+ DR2, // 19
+ DR3, // 20
+ DR4, // 21
+ DR5, // 22
+ DR6, // 23
+ DR7, // 24
+ DS, // 25
+ DX, // 26
+ EAX, // 27
+ EBP, // 28
+ EBX, // 29
+ ECR0, // 30
+ ECR1, // 31
+ ECR2, // 32
+ ECR3, // 33
+ ECR4, // 34
+ ECR5, // 35
+ ECR6, // 36
+ ECR7, // 37
+ ECX, // 38
+ EDI, // 39
+ EDX, // 40
+ EFLAGS, // 41
+ EIP, // 42
+ ES, // 43
+ ESI, // 44
+ ESP, // 45
+ FP0, // 46
+ FP1, // 47
+ FP2, // 48
+ FP3, // 49
+ FP4, // 50
+ FP5, // 51
+ FP6, // 52
+ FS, // 53
+ GS, // 54
+ IP, // 55
+ MM0, // 56
+ MM1, // 57
+ MM2, // 58
+ MM3, // 59
+ MM4, // 60
+ MM5, // 61
+ MM6, // 62
+ MM7, // 63
+ R10, // 64
+ R10B, // 65
+ R10D, // 66
+ R10W, // 67
+ R11, // 68
+ R11B, // 69
+ R11D, // 70
+ R11W, // 71
+ R12, // 72
+ R12B, // 73
+ R12D, // 74
+ R12W, // 75
+ R13, // 76
+ R13B, // 77
+ R13D, // 78
+ R13W, // 79
+ R14, // 80
+ R14B, // 81
+ R14D, // 82
+ R14W, // 83
+ R15, // 84
+ R15B, // 85
+ R15D, // 86
+ R15W, // 87
+ R8, // 88
+ R8B, // 89
+ R8D, // 90
+ R8W, // 91
+ R9, // 92
+ R9B, // 93
+ R9D, // 94
+ R9W, // 95
+ RAX, // 96
+ RBP, // 97
+ RBX, // 98
+ RCR0, // 99
+ RCR1, // 100
+ RCR2, // 101
+ RCR3, // 102
+ RCR4, // 103
+ RCR5, // 104
+ RCR6, // 105
+ RCR7, // 106
+ RCR8, // 107
+ RCX, // 108
+ RDI, // 109
+ RDX, // 110
+ RIP, // 111
+ RSI, // 112
+ RSP, // 113
+ SI, // 114
+ SIL, // 115
+ SP, // 116
+ SPL, // 117
+ SS, // 118
+ ST0, // 119
+ ST1, // 120
+ ST2, // 121
+ ST3, // 122
+ ST4, // 123
+ ST5, // 124
+ ST6, // 125
+ ST7, // 126
+ XMM0, // 127
+ XMM1, // 128
+ XMM10, // 129
+ XMM11, // 130
+ XMM12, // 131
+ XMM13, // 132
+ XMM14, // 133
+ XMM15, // 134
+ XMM2, // 135
+ XMM3, // 136
+ XMM4, // 137
+ XMM5, // 138
+ XMM6, // 139
+ XMM7, // 140
+ XMM8, // 141
+ XMM9, // 142
+ YMM0, // 143
+ YMM1, // 144
+ YMM10, // 145
+ YMM11, // 146
+ YMM12, // 147
+ YMM13, // 148
+ YMM14, // 149
+ YMM15, // 150
+ YMM2, // 151
+ YMM3, // 152
+ YMM4, // 153
+ YMM5, // 154
+ YMM6, // 155
+ YMM7, // 156
+ YMM8, // 157
+ YMM9, // 158
+ NUM_TARGET_REGS // 159
};
}
} // End llvm namespace
diff --git a/libclamav/c++/llvm/include/llvm/Intrinsics.gen b/libclamav/c++/llvm/include/llvm/Intrinsics.gen
index 96cbbfa..cd1c589 100644
--- a/libclamav/c++/llvm/include/llvm/Intrinsics.gen
+++ b/libclamav/c++/llvm/include/llvm/Intrinsics.gen
@@ -3213,7 +3213,7 @@
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::iAny, MVT::iAny, MVT::i32, MVT::i32);
break;
case Intrinsic::objectsize: // llvm.objectsize
- VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTR, MVT::i32);
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTR, MVT::i1);
break;
case Intrinsic::sadd_with_overflow: // llvm.sadd.with.overflow
VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0);
@@ -4516,7 +4516,7 @@
case Intrinsic::objectsize: // llvm.objectsize
ResultTy = Tys[0];
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
- ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 1));
break;
case Intrinsic::sadd_with_overflow: // llvm.sadd.with.overflow
ResultTy = StructType::get(Context, Tys[0], IntegerType::get(Context, 1), NULL);
--
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